1 //===-- SelectionDAGISel.cpp - Implement the SelectionDAGISel class -------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements the SelectionDAGISel class.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "isel"
15 #include "llvm/CodeGen/SelectionDAGISel.h"
16 #include "llvm/CallingConv.h"
17 #include "llvm/Constants.h"
18 #include "llvm/DerivedTypes.h"
19 #include "llvm/Function.h"
20 #include "llvm/Instructions.h"
21 #include "llvm/Intrinsics.h"
22 #include "llvm/CodeGen/MachineFunction.h"
23 #include "llvm/CodeGen/MachineFrameInfo.h"
24 #include "llvm/CodeGen/MachineInstrBuilder.h"
25 #include "llvm/CodeGen/SelectionDAG.h"
26 #include "llvm/CodeGen/SSARegMap.h"
27 #include "llvm/Target/MRegisterInfo.h"
28 #include "llvm/Target/TargetData.h"
29 #include "llvm/Target/TargetFrameInfo.h"
30 #include "llvm/Target/TargetInstrInfo.h"
31 #include "llvm/Target/TargetLowering.h"
32 #include "llvm/Target/TargetMachine.h"
33 #include "llvm/Transforms/Utils/BasicBlockUtils.h"
34 #include "llvm/Support/CommandLine.h"
35 #include "llvm/Support/MathExtras.h"
36 #include "llvm/Support/Debug.h"
43 ViewDAGs("view-isel-dags", cl::Hidden,
44 cl::desc("Pop up a window to show isel dags as they are selected"));
46 static const bool ViewDAGs = 0;
51 //===--------------------------------------------------------------------===//
52 /// FunctionLoweringInfo - This contains information that is global to a
53 /// function that is used when lowering a region of the function.
54 class FunctionLoweringInfo {
61 FunctionLoweringInfo(TargetLowering &TLI, Function &Fn,MachineFunction &MF);
63 /// MBBMap - A mapping from LLVM basic blocks to their machine code entry.
64 std::map<const BasicBlock*, MachineBasicBlock *> MBBMap;
66 /// ValueMap - Since we emit code for the function a basic block at a time,
67 /// we must remember which virtual registers hold the values for
68 /// cross-basic-block values.
69 std::map<const Value*, unsigned> ValueMap;
71 /// StaticAllocaMap - Keep track of frame indices for fixed sized allocas in
72 /// the entry block. This allows the allocas to be efficiently referenced
73 /// anywhere in the function.
74 std::map<const AllocaInst*, int> StaticAllocaMap;
76 unsigned MakeReg(MVT::ValueType VT) {
77 return RegMap->createVirtualRegister(TLI.getRegClassFor(VT));
80 unsigned CreateRegForValue(const Value *V) {
81 MVT::ValueType VT = TLI.getValueType(V->getType());
82 // The common case is that we will only create one register for this
83 // value. If we have that case, create and return the virtual register.
84 unsigned NV = TLI.getNumElements(VT);
86 // If we are promoting this value, pick the next largest supported type.
87 return MakeReg(TLI.getTypeToTransformTo(VT));
90 // If this value is represented with multiple target registers, make sure
91 // to create enough consequtive registers of the right (smaller) type.
92 unsigned NT = VT-1; // Find the type to use.
93 while (TLI.getNumElements((MVT::ValueType)NT) != 1)
96 unsigned R = MakeReg((MVT::ValueType)NT);
97 for (unsigned i = 1; i != NV; ++i)
98 MakeReg((MVT::ValueType)NT);
102 unsigned InitializeRegForValue(const Value *V) {
103 unsigned &R = ValueMap[V];
104 assert(R == 0 && "Already initialized this value register!");
105 return R = CreateRegForValue(V);
110 /// isUsedOutsideOfDefiningBlock - Return true if this instruction is used by
111 /// PHI nodes or outside of the basic block that defines it.
112 static bool isUsedOutsideOfDefiningBlock(Instruction *I) {
113 if (isa<PHINode>(I)) return true;
114 BasicBlock *BB = I->getParent();
115 for (Value::use_iterator UI = I->use_begin(), E = I->use_end(); UI != E; ++UI)
116 if (cast<Instruction>(*UI)->getParent() != BB || isa<PHINode>(*UI))
121 /// isOnlyUsedInEntryBlock - If the specified argument is only used in the
122 /// entry block, return true.
123 static bool isOnlyUsedInEntryBlock(Argument *A) {
124 BasicBlock *Entry = A->getParent()->begin();
125 for (Value::use_iterator UI = A->use_begin(), E = A->use_end(); UI != E; ++UI)
126 if (cast<Instruction>(*UI)->getParent() != Entry)
127 return false; // Use not in entry block.
131 FunctionLoweringInfo::FunctionLoweringInfo(TargetLowering &tli,
132 Function &fn, MachineFunction &mf)
133 : TLI(tli), Fn(fn), MF(mf), RegMap(MF.getSSARegMap()) {
135 // Create a vreg for each argument register that is not dead and is used
136 // outside of the entry block for the function.
137 for (Function::arg_iterator AI = Fn.arg_begin(), E = Fn.arg_end();
139 if (!isOnlyUsedInEntryBlock(AI))
140 InitializeRegForValue(AI);
142 // Initialize the mapping of values to registers. This is only set up for
143 // instruction values that are used outside of the block that defines
145 Function::iterator BB = Fn.begin(), EB = Fn.end();
146 for (BasicBlock::iterator I = BB->begin(), E = BB->end(); I != E; ++I)
147 if (AllocaInst *AI = dyn_cast<AllocaInst>(I))
148 if (ConstantUInt *CUI = dyn_cast<ConstantUInt>(AI->getArraySize())) {
149 const Type *Ty = AI->getAllocatedType();
150 uint64_t TySize = TLI.getTargetData().getTypeSize(Ty);
152 std::max((unsigned)TLI.getTargetData().getTypeAlignment(Ty),
155 // If the alignment of the value is smaller than the size of the value,
156 // and if the size of the value is particularly small (<= 8 bytes),
157 // round up to the size of the value for potentially better performance.
159 // FIXME: This could be made better with a preferred alignment hook in
160 // TargetData. It serves primarily to 8-byte align doubles for X86.
161 if (Align < TySize && TySize <= 8) Align = TySize;
162 TySize *= CUI->getValue(); // Get total allocated size.
163 if (TySize == 0) TySize = 1; // Don't create zero-sized stack objects.
164 StaticAllocaMap[AI] =
165 MF.getFrameInfo()->CreateStackObject((unsigned)TySize, Align);
168 for (; BB != EB; ++BB)
169 for (BasicBlock::iterator I = BB->begin(), E = BB->end(); I != E; ++I)
170 if (!I->use_empty() && isUsedOutsideOfDefiningBlock(I))
171 if (!isa<AllocaInst>(I) ||
172 !StaticAllocaMap.count(cast<AllocaInst>(I)))
173 InitializeRegForValue(I);
175 // Create an initial MachineBasicBlock for each LLVM BasicBlock in F. This
176 // also creates the initial PHI MachineInstrs, though none of the input
177 // operands are populated.
178 for (BB = Fn.begin(), EB = Fn.end(); BB != EB; ++BB) {
179 MachineBasicBlock *MBB = new MachineBasicBlock(BB);
181 MF.getBasicBlockList().push_back(MBB);
183 // Create Machine PHI nodes for LLVM PHI nodes, lowering them as
186 for (BasicBlock::iterator I = BB->begin();
187 (PN = dyn_cast<PHINode>(I)); ++I)
188 if (!PN->use_empty()) {
189 unsigned NumElements =
190 TLI.getNumElements(TLI.getValueType(PN->getType()));
191 unsigned PHIReg = ValueMap[PN];
192 assert(PHIReg &&"PHI node does not have an assigned virtual register!");
193 for (unsigned i = 0; i != NumElements; ++i)
194 BuildMI(MBB, TargetInstrInfo::PHI, PN->getNumOperands(), PHIReg+i);
201 //===----------------------------------------------------------------------===//
202 /// SelectionDAGLowering - This is the common target-independent lowering
203 /// implementation that is parameterized by a TargetLowering object.
204 /// Also, targets can overload any lowering method.
207 class SelectionDAGLowering {
208 MachineBasicBlock *CurMBB;
210 std::map<const Value*, SDOperand> NodeMap;
212 /// PendingLoads - Loads are not emitted to the program immediately. We bunch
213 /// them up and then emit token factor nodes when possible. This allows us to
214 /// get simple disambiguation between loads without worrying about alias
216 std::vector<SDOperand> PendingLoads;
219 // TLI - This is information that describes the available target features we
220 // need for lowering. This indicates when operations are unavailable,
221 // implemented with a libcall, etc.
224 const TargetData &TD;
226 /// FuncInfo - Information about the function as a whole.
228 FunctionLoweringInfo &FuncInfo;
230 SelectionDAGLowering(SelectionDAG &dag, TargetLowering &tli,
231 FunctionLoweringInfo &funcinfo)
232 : TLI(tli), DAG(dag), TD(DAG.getTarget().getTargetData()),
236 /// getRoot - Return the current virtual root of the Selection DAG.
238 SDOperand getRoot() {
239 if (PendingLoads.empty())
240 return DAG.getRoot();
242 if (PendingLoads.size() == 1) {
243 SDOperand Root = PendingLoads[0];
245 PendingLoads.clear();
249 // Otherwise, we have to make a token factor node.
250 SDOperand Root = DAG.getNode(ISD::TokenFactor, MVT::Other, PendingLoads);
251 PendingLoads.clear();
256 void visit(Instruction &I) { visit(I.getOpcode(), I); }
258 void visit(unsigned Opcode, User &I) {
260 default: assert(0 && "Unknown instruction type encountered!");
262 // Build the switch statement using the Instruction.def file.
263 #define HANDLE_INST(NUM, OPCODE, CLASS) \
264 case Instruction::OPCODE:return visit##OPCODE((CLASS&)I);
265 #include "llvm/Instruction.def"
269 void setCurrentBasicBlock(MachineBasicBlock *MBB) { CurMBB = MBB; }
272 SDOperand getIntPtrConstant(uint64_t Val) {
273 return DAG.getConstant(Val, TLI.getPointerTy());
276 SDOperand getValue(const Value *V) {
277 SDOperand &N = NodeMap[V];
280 MVT::ValueType VT = TLI.getValueType(V->getType());
281 if (Constant *C = const_cast<Constant*>(dyn_cast<Constant>(V)))
282 if (ConstantExpr *CE = dyn_cast<ConstantExpr>(C)) {
283 visit(CE->getOpcode(), *CE);
284 assert(N.Val && "visit didn't populate the ValueMap!");
286 } else if (GlobalValue *GV = dyn_cast<GlobalValue>(C)) {
287 return N = DAG.getGlobalAddress(GV, VT);
288 } else if (isa<ConstantPointerNull>(C)) {
289 return N = DAG.getConstant(0, TLI.getPointerTy());
290 } else if (isa<UndefValue>(C)) {
291 return N = DAG.getNode(ISD::UNDEF, VT);
292 } else if (ConstantFP *CFP = dyn_cast<ConstantFP>(C)) {
293 return N = DAG.getConstantFP(CFP->getValue(), VT);
295 // Canonicalize all constant ints to be unsigned.
296 return N = DAG.getConstant(cast<ConstantIntegral>(C)->getRawValue(),VT);
299 if (const AllocaInst *AI = dyn_cast<AllocaInst>(V)) {
300 std::map<const AllocaInst*, int>::iterator SI =
301 FuncInfo.StaticAllocaMap.find(AI);
302 if (SI != FuncInfo.StaticAllocaMap.end())
303 return DAG.getFrameIndex(SI->second, TLI.getPointerTy());
306 std::map<const Value*, unsigned>::const_iterator VMI =
307 FuncInfo.ValueMap.find(V);
308 assert(VMI != FuncInfo.ValueMap.end() && "Value not in map!");
310 unsigned InReg = VMI->second;
312 // If this type is not legal, make it so now.
313 MVT::ValueType DestVT = TLI.getTypeToTransformTo(VT);
315 N = DAG.getCopyFromReg(DAG.getEntryNode(), InReg, DestVT);
317 // Source must be expanded. This input value is actually coming from the
318 // register pair VMI->second and VMI->second+1.
319 N = DAG.getNode(ISD::BUILD_PAIR, VT, N,
320 DAG.getCopyFromReg(DAG.getEntryNode(), InReg+1, DestVT));
322 if (DestVT > VT) { // Promotion case
323 if (MVT::isFloatingPoint(VT))
324 N = DAG.getNode(ISD::FP_ROUND, VT, N);
326 N = DAG.getNode(ISD::TRUNCATE, VT, N);
333 const SDOperand &setValue(const Value *V, SDOperand NewN) {
334 SDOperand &N = NodeMap[V];
335 assert(N.Val == 0 && "Already set a value for this node!");
339 // Terminator instructions.
340 void visitRet(ReturnInst &I);
341 void visitBr(BranchInst &I);
342 void visitUnreachable(UnreachableInst &I) { /* noop */ }
344 // These all get lowered before this pass.
345 void visitSwitch(SwitchInst &I) { assert(0 && "TODO"); }
346 void visitInvoke(InvokeInst &I) { assert(0 && "TODO"); }
347 void visitUnwind(UnwindInst &I) { assert(0 && "TODO"); }
350 void visitBinary(User &I, unsigned Opcode, bool isShift = false);
351 void visitAdd(User &I) {
352 visitBinary(I, I.getType()->isFloatingPoint() ? ISD::FADD : ISD::ADD);
354 void visitSub(User &I);
355 void visitMul(User &I) {
356 visitBinary(I, I.getType()->isFloatingPoint() ? ISD::FMUL : ISD::MUL);
358 void visitDiv(User &I) {
360 const Type *Ty = I.getType();
361 if (Ty->isFloatingPoint())
363 else if (Ty->isUnsigned())
369 void visitRem(User &I) {
371 const Type *Ty = I.getType();
372 if (Ty->isFloatingPoint())
374 else if (Ty->isUnsigned())
380 void visitAnd(User &I) { visitBinary(I, ISD::AND); }
381 void visitOr (User &I) { visitBinary(I, ISD::OR); }
382 void visitXor(User &I) { visitBinary(I, ISD::XOR); }
383 void visitShl(User &I) { visitBinary(I, ISD::SHL, true); }
384 void visitShr(User &I) {
385 visitBinary(I, I.getType()->isUnsigned() ? ISD::SRL : ISD::SRA, true);
388 void visitSetCC(User &I, ISD::CondCode SignedOpc, ISD::CondCode UnsignedOpc);
389 void visitSetEQ(User &I) { visitSetCC(I, ISD::SETEQ, ISD::SETEQ); }
390 void visitSetNE(User &I) { visitSetCC(I, ISD::SETNE, ISD::SETNE); }
391 void visitSetLE(User &I) { visitSetCC(I, ISD::SETLE, ISD::SETULE); }
392 void visitSetGE(User &I) { visitSetCC(I, ISD::SETGE, ISD::SETUGE); }
393 void visitSetLT(User &I) { visitSetCC(I, ISD::SETLT, ISD::SETULT); }
394 void visitSetGT(User &I) { visitSetCC(I, ISD::SETGT, ISD::SETUGT); }
396 void visitGetElementPtr(User &I);
397 void visitCast(User &I);
398 void visitSelect(User &I);
401 void visitMalloc(MallocInst &I);
402 void visitFree(FreeInst &I);
403 void visitAlloca(AllocaInst &I);
404 void visitLoad(LoadInst &I);
405 void visitStore(StoreInst &I);
406 void visitPHI(PHINode &I) { } // PHI nodes are handled specially.
407 void visitCall(CallInst &I);
409 void visitVAStart(CallInst &I);
410 void visitVAArg(VAArgInst &I);
411 void visitVAEnd(CallInst &I);
412 void visitVACopy(CallInst &I);
413 void visitFrameReturnAddress(CallInst &I, bool isFrameAddress);
415 void visitMemIntrinsic(CallInst &I, unsigned Op);
417 void visitUserOp1(Instruction &I) {
418 assert(0 && "UserOp1 should not exist at instruction selection time!");
421 void visitUserOp2(Instruction &I) {
422 assert(0 && "UserOp2 should not exist at instruction selection time!");
426 } // end namespace llvm
428 void SelectionDAGLowering::visitRet(ReturnInst &I) {
429 if (I.getNumOperands() == 0) {
430 DAG.setRoot(DAG.getNode(ISD::RET, MVT::Other, getRoot()));
434 SDOperand Op1 = getValue(I.getOperand(0));
435 MVT::ValueType TmpVT;
437 switch (Op1.getValueType()) {
438 default: assert(0 && "Unknown value type!");
443 // If this is a machine where 32-bits is legal or expanded, promote to
444 // 32-bits, otherwise, promote to 64-bits.
445 if (TLI.getTypeAction(MVT::i32) == TargetLowering::Promote)
446 TmpVT = TLI.getTypeToTransformTo(MVT::i32);
450 // Extend integer types to result type.
451 if (I.getOperand(0)->getType()->isSigned())
452 Op1 = DAG.getNode(ISD::SIGN_EXTEND, TmpVT, Op1);
454 Op1 = DAG.getNode(ISD::ZERO_EXTEND, TmpVT, Op1);
459 break; // No extension needed!
461 // Allow targets to lower this further to meet ABI requirements
462 DAG.setRoot(TLI.LowerReturnTo(getRoot(), Op1, DAG));
465 void SelectionDAGLowering::visitBr(BranchInst &I) {
466 // Update machine-CFG edges.
467 MachineBasicBlock *Succ0MBB = FuncInfo.MBBMap[I.getSuccessor(0)];
469 // Figure out which block is immediately after the current one.
470 MachineBasicBlock *NextBlock = 0;
471 MachineFunction::iterator BBI = CurMBB;
472 if (++BBI != CurMBB->getParent()->end())
475 if (I.isUnconditional()) {
476 // If this is not a fall-through branch, emit the branch.
477 if (Succ0MBB != NextBlock)
478 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, getRoot(),
479 DAG.getBasicBlock(Succ0MBB)));
481 MachineBasicBlock *Succ1MBB = FuncInfo.MBBMap[I.getSuccessor(1)];
483 SDOperand Cond = getValue(I.getCondition());
484 if (Succ1MBB == NextBlock) {
485 // If the condition is false, fall through. This means we should branch
486 // if the condition is true to Succ #0.
487 DAG.setRoot(DAG.getNode(ISD::BRCOND, MVT::Other, getRoot(),
488 Cond, DAG.getBasicBlock(Succ0MBB)));
489 } else if (Succ0MBB == NextBlock) {
490 // If the condition is true, fall through. This means we should branch if
491 // the condition is false to Succ #1. Invert the condition first.
492 SDOperand True = DAG.getConstant(1, Cond.getValueType());
493 Cond = DAG.getNode(ISD::XOR, Cond.getValueType(), Cond, True);
494 DAG.setRoot(DAG.getNode(ISD::BRCOND, MVT::Other, getRoot(),
495 Cond, DAG.getBasicBlock(Succ1MBB)));
497 std::vector<SDOperand> Ops;
498 Ops.push_back(getRoot());
500 Ops.push_back(DAG.getBasicBlock(Succ0MBB));
501 Ops.push_back(DAG.getBasicBlock(Succ1MBB));
502 DAG.setRoot(DAG.getNode(ISD::BRCONDTWOWAY, MVT::Other, Ops));
507 void SelectionDAGLowering::visitSub(User &I) {
509 if (I.getType()->isFloatingPoint()) {
510 if (ConstantFP *CFP = dyn_cast<ConstantFP>(I.getOperand(0)))
511 if (CFP->isExactlyValue(-0.0)) {
512 SDOperand Op2 = getValue(I.getOperand(1));
513 setValue(&I, DAG.getNode(ISD::FNEG, Op2.getValueType(), Op2));
516 visitBinary(I, ISD::FSUB);
518 visitBinary(I, ISD::SUB);
522 void SelectionDAGLowering::visitBinary(User &I, unsigned Opcode, bool isShift) {
523 SDOperand Op1 = getValue(I.getOperand(0));
524 SDOperand Op2 = getValue(I.getOperand(1));
527 Op2 = DAG.getNode(ISD::ANY_EXTEND, TLI.getShiftAmountTy(), Op2);
529 setValue(&I, DAG.getNode(Opcode, Op1.getValueType(), Op1, Op2));
532 void SelectionDAGLowering::visitSetCC(User &I,ISD::CondCode SignedOpcode,
533 ISD::CondCode UnsignedOpcode) {
534 SDOperand Op1 = getValue(I.getOperand(0));
535 SDOperand Op2 = getValue(I.getOperand(1));
536 ISD::CondCode Opcode = SignedOpcode;
537 if (I.getOperand(0)->getType()->isUnsigned())
538 Opcode = UnsignedOpcode;
539 setValue(&I, DAG.getSetCC(MVT::i1, Op1, Op2, Opcode));
542 void SelectionDAGLowering::visitSelect(User &I) {
543 SDOperand Cond = getValue(I.getOperand(0));
544 SDOperand TrueVal = getValue(I.getOperand(1));
545 SDOperand FalseVal = getValue(I.getOperand(2));
546 setValue(&I, DAG.getNode(ISD::SELECT, TrueVal.getValueType(), Cond,
550 void SelectionDAGLowering::visitCast(User &I) {
551 SDOperand N = getValue(I.getOperand(0));
552 MVT::ValueType SrcTy = TLI.getValueType(I.getOperand(0)->getType());
553 MVT::ValueType DestTy = TLI.getValueType(I.getType());
555 if (N.getValueType() == DestTy) {
556 setValue(&I, N); // noop cast.
557 } else if (DestTy == MVT::i1) {
558 // Cast to bool is a comparison against zero, not truncation to zero.
559 SDOperand Zero = isInteger(SrcTy) ? DAG.getConstant(0, N.getValueType()) :
560 DAG.getConstantFP(0.0, N.getValueType());
561 setValue(&I, DAG.getSetCC(MVT::i1, N, Zero, ISD::SETNE));
562 } else if (isInteger(SrcTy)) {
563 if (isInteger(DestTy)) { // Int -> Int cast
564 if (DestTy < SrcTy) // Truncating cast?
565 setValue(&I, DAG.getNode(ISD::TRUNCATE, DestTy, N));
566 else if (I.getOperand(0)->getType()->isSigned())
567 setValue(&I, DAG.getNode(ISD::SIGN_EXTEND, DestTy, N));
569 setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, DestTy, N));
570 } else { // Int -> FP cast
571 if (I.getOperand(0)->getType()->isSigned())
572 setValue(&I, DAG.getNode(ISD::SINT_TO_FP, DestTy, N));
574 setValue(&I, DAG.getNode(ISD::UINT_TO_FP, DestTy, N));
577 assert(isFloatingPoint(SrcTy) && "Unknown value type!");
578 if (isFloatingPoint(DestTy)) { // FP -> FP cast
579 if (DestTy < SrcTy) // Rounding cast?
580 setValue(&I, DAG.getNode(ISD::FP_ROUND, DestTy, N));
582 setValue(&I, DAG.getNode(ISD::FP_EXTEND, DestTy, N));
583 } else { // FP -> Int cast.
584 if (I.getType()->isSigned())
585 setValue(&I, DAG.getNode(ISD::FP_TO_SINT, DestTy, N));
587 setValue(&I, DAG.getNode(ISD::FP_TO_UINT, DestTy, N));
592 void SelectionDAGLowering::visitGetElementPtr(User &I) {
593 SDOperand N = getValue(I.getOperand(0));
594 const Type *Ty = I.getOperand(0)->getType();
595 const Type *UIntPtrTy = TD.getIntPtrType();
597 for (GetElementPtrInst::op_iterator OI = I.op_begin()+1, E = I.op_end();
600 if (const StructType *StTy = dyn_cast<StructType> (Ty)) {
601 unsigned Field = cast<ConstantUInt>(Idx)->getValue();
604 uint64_t Offset = TD.getStructLayout(StTy)->MemberOffsets[Field];
605 N = DAG.getNode(ISD::ADD, N.getValueType(), N,
606 getIntPtrConstant(Offset));
608 Ty = StTy->getElementType(Field);
610 Ty = cast<SequentialType>(Ty)->getElementType();
612 // If this is a constant subscript, handle it quickly.
613 if (ConstantInt *CI = dyn_cast<ConstantInt>(Idx)) {
614 if (CI->getRawValue() == 0) continue;
617 if (ConstantSInt *CSI = dyn_cast<ConstantSInt>(CI))
618 Offs = (int64_t)TD.getTypeSize(Ty)*CSI->getValue();
620 Offs = TD.getTypeSize(Ty)*cast<ConstantUInt>(CI)->getValue();
621 N = DAG.getNode(ISD::ADD, N.getValueType(), N, getIntPtrConstant(Offs));
625 // N = N + Idx * ElementSize;
626 uint64_t ElementSize = TD.getTypeSize(Ty);
627 SDOperand IdxN = getValue(Idx);
629 // If the index is smaller or larger than intptr_t, truncate or extend
631 if (IdxN.getValueType() < N.getValueType()) {
632 if (Idx->getType()->isSigned())
633 IdxN = DAG.getNode(ISD::SIGN_EXTEND, N.getValueType(), IdxN);
635 IdxN = DAG.getNode(ISD::ZERO_EXTEND, N.getValueType(), IdxN);
636 } else if (IdxN.getValueType() > N.getValueType())
637 IdxN = DAG.getNode(ISD::TRUNCATE, N.getValueType(), IdxN);
639 // If this is a multiply by a power of two, turn it into a shl
640 // immediately. This is a very common case.
641 if (isPowerOf2_64(ElementSize)) {
642 unsigned Amt = Log2_64(ElementSize);
643 IdxN = DAG.getNode(ISD::SHL, N.getValueType(), IdxN,
644 getIntPtrConstant(Amt));
645 N = DAG.getNode(ISD::ADD, N.getValueType(), N, IdxN);
649 SDOperand Scale = getIntPtrConstant(ElementSize);
650 IdxN = DAG.getNode(ISD::MUL, N.getValueType(), IdxN, Scale);
651 N = DAG.getNode(ISD::ADD, N.getValueType(), N, IdxN);
657 void SelectionDAGLowering::visitAlloca(AllocaInst &I) {
658 // If this is a fixed sized alloca in the entry block of the function,
659 // allocate it statically on the stack.
660 if (FuncInfo.StaticAllocaMap.count(&I))
661 return; // getValue will auto-populate this.
663 const Type *Ty = I.getAllocatedType();
664 uint64_t TySize = TLI.getTargetData().getTypeSize(Ty);
665 unsigned Align = std::max((unsigned)TLI.getTargetData().getTypeAlignment(Ty),
668 SDOperand AllocSize = getValue(I.getArraySize());
669 MVT::ValueType IntPtr = TLI.getPointerTy();
670 if (IntPtr < AllocSize.getValueType())
671 AllocSize = DAG.getNode(ISD::TRUNCATE, IntPtr, AllocSize);
672 else if (IntPtr > AllocSize.getValueType())
673 AllocSize = DAG.getNode(ISD::ZERO_EXTEND, IntPtr, AllocSize);
675 AllocSize = DAG.getNode(ISD::MUL, IntPtr, AllocSize,
676 getIntPtrConstant(TySize));
678 // Handle alignment. If the requested alignment is less than or equal to the
679 // stack alignment, ignore it and round the size of the allocation up to the
680 // stack alignment size. If the size is greater than the stack alignment, we
681 // note this in the DYNAMIC_STACKALLOC node.
682 unsigned StackAlign =
683 TLI.getTargetMachine().getFrameInfo()->getStackAlignment();
684 if (Align <= StackAlign) {
686 // Add SA-1 to the size.
687 AllocSize = DAG.getNode(ISD::ADD, AllocSize.getValueType(), AllocSize,
688 getIntPtrConstant(StackAlign-1));
689 // Mask out the low bits for alignment purposes.
690 AllocSize = DAG.getNode(ISD::AND, AllocSize.getValueType(), AllocSize,
691 getIntPtrConstant(~(uint64_t)(StackAlign-1)));
694 std::vector<MVT::ValueType> VTs;
695 VTs.push_back(AllocSize.getValueType());
696 VTs.push_back(MVT::Other);
697 std::vector<SDOperand> Ops;
698 Ops.push_back(getRoot());
699 Ops.push_back(AllocSize);
700 Ops.push_back(getIntPtrConstant(Align));
701 SDOperand DSA = DAG.getNode(ISD::DYNAMIC_STACKALLOC, VTs, Ops);
702 DAG.setRoot(setValue(&I, DSA).getValue(1));
704 // Inform the Frame Information that we have just allocated a variable-sized
706 CurMBB->getParent()->getFrameInfo()->CreateVariableSizedObject();
710 void SelectionDAGLowering::visitLoad(LoadInst &I) {
711 SDOperand Ptr = getValue(I.getOperand(0));
717 // Do not serialize non-volatile loads against each other.
718 Root = DAG.getRoot();
721 SDOperand L = DAG.getLoad(TLI.getValueType(I.getType()), Root, Ptr,
722 DAG.getSrcValue(I.getOperand(0)));
726 DAG.setRoot(L.getValue(1));
728 PendingLoads.push_back(L.getValue(1));
732 void SelectionDAGLowering::visitStore(StoreInst &I) {
733 Value *SrcV = I.getOperand(0);
734 SDOperand Src = getValue(SrcV);
735 SDOperand Ptr = getValue(I.getOperand(1));
736 DAG.setRoot(DAG.getNode(ISD::STORE, MVT::Other, getRoot(), Src, Ptr,
737 DAG.getSrcValue(I.getOperand(1))));
740 void SelectionDAGLowering::visitCall(CallInst &I) {
741 const char *RenameFn = 0;
743 if (Function *F = I.getCalledFunction())
745 switch (F->getIntrinsicID()) {
746 case 0: // Not an LLVM intrinsic.
747 if (F->getName() == "fabs" || F->getName() == "fabsf") {
748 if (I.getNumOperands() == 2 && // Basic sanity checks.
749 I.getOperand(1)->getType()->isFloatingPoint() &&
750 I.getType() == I.getOperand(1)->getType()) {
751 Tmp = getValue(I.getOperand(1));
752 setValue(&I, DAG.getNode(ISD::FABS, Tmp.getValueType(), Tmp));
756 else if (F->getName() == "sin" || F->getName() == "sinf") {
757 if (I.getNumOperands() == 2 && // Basic sanity checks.
758 I.getOperand(1)->getType()->isFloatingPoint() &&
759 I.getType() == I.getOperand(1)->getType()) {
760 Tmp = getValue(I.getOperand(1));
761 setValue(&I, DAG.getNode(ISD::FSIN, Tmp.getValueType(), Tmp));
765 else if (F->getName() == "cos" || F->getName() == "cosf") {
766 if (I.getNumOperands() == 2 && // Basic sanity checks.
767 I.getOperand(1)->getType()->isFloatingPoint() &&
768 I.getType() == I.getOperand(1)->getType()) {
769 Tmp = getValue(I.getOperand(1));
770 setValue(&I, DAG.getNode(ISD::FCOS, Tmp.getValueType(), Tmp));
775 case Intrinsic::vastart: visitVAStart(I); return;
776 case Intrinsic::vaend: visitVAEnd(I); return;
777 case Intrinsic::vacopy: visitVACopy(I); return;
778 case Intrinsic::returnaddress: visitFrameReturnAddress(I, false); return;
779 case Intrinsic::frameaddress: visitFrameReturnAddress(I, true); return;
781 case Intrinsic::setjmp:
782 RenameFn = "_setjmp"+!TLI.usesUnderscoreSetJmpLongJmp();
784 case Intrinsic::longjmp:
785 RenameFn = "_longjmp"+!TLI.usesUnderscoreSetJmpLongJmp();
787 case Intrinsic::memcpy: visitMemIntrinsic(I, ISD::MEMCPY); return;
788 case Intrinsic::memset: visitMemIntrinsic(I, ISD::MEMSET); return;
789 case Intrinsic::memmove: visitMemIntrinsic(I, ISD::MEMMOVE); return;
791 case Intrinsic::readport:
792 case Intrinsic::readio: {
793 std::vector<MVT::ValueType> VTs;
794 VTs.push_back(TLI.getValueType(I.getType()));
795 VTs.push_back(MVT::Other);
796 std::vector<SDOperand> Ops;
797 Ops.push_back(getRoot());
798 Ops.push_back(getValue(I.getOperand(1)));
799 Tmp = DAG.getNode(F->getIntrinsicID() == Intrinsic::readport ?
800 ISD::READPORT : ISD::READIO, VTs, Ops);
803 DAG.setRoot(Tmp.getValue(1));
806 case Intrinsic::writeport:
807 case Intrinsic::writeio:
808 DAG.setRoot(DAG.getNode(F->getIntrinsicID() == Intrinsic::writeport ?
809 ISD::WRITEPORT : ISD::WRITEIO, MVT::Other,
810 getRoot(), getValue(I.getOperand(1)),
811 getValue(I.getOperand(2))));
813 case Intrinsic::dbg_stoppoint:
814 case Intrinsic::dbg_region_start:
815 case Intrinsic::dbg_region_end:
816 case Intrinsic::dbg_func_start:
817 case Intrinsic::dbg_declare:
818 if (I.getType() != Type::VoidTy)
819 setValue(&I, DAG.getNode(ISD::UNDEF, TLI.getValueType(I.getType())));
822 case Intrinsic::isunordered:
823 setValue(&I, DAG.getSetCC(MVT::i1,getValue(I.getOperand(1)),
824 getValue(I.getOperand(2)), ISD::SETUO));
827 case Intrinsic::sqrt:
828 setValue(&I, DAG.getNode(ISD::FSQRT,
829 getValue(I.getOperand(1)).getValueType(),
830 getValue(I.getOperand(1))));
833 case Intrinsic::pcmarker:
834 Tmp = getValue(I.getOperand(1));
835 DAG.setRoot(DAG.getNode(ISD::PCMARKER, MVT::Other, getRoot(), Tmp));
837 case Intrinsic::cttz:
838 setValue(&I, DAG.getNode(ISD::CTTZ,
839 getValue(I.getOperand(1)).getValueType(),
840 getValue(I.getOperand(1))));
842 case Intrinsic::ctlz:
843 setValue(&I, DAG.getNode(ISD::CTLZ,
844 getValue(I.getOperand(1)).getValueType(),
845 getValue(I.getOperand(1))));
847 case Intrinsic::ctpop:
848 setValue(&I, DAG.getNode(ISD::CTPOP,
849 getValue(I.getOperand(1)).getValueType(),
850 getValue(I.getOperand(1))));
854 assert(0 && "This intrinsic is not implemented yet!");
860 Callee = getValue(I.getOperand(0));
862 Callee = DAG.getExternalSymbol(RenameFn, TLI.getPointerTy());
863 std::vector<std::pair<SDOperand, const Type*> > Args;
865 for (unsigned i = 1, e = I.getNumOperands(); i != e; ++i) {
866 Value *Arg = I.getOperand(i);
867 SDOperand ArgNode = getValue(Arg);
868 Args.push_back(std::make_pair(ArgNode, Arg->getType()));
871 const PointerType *PT = cast<PointerType>(I.getCalledValue()->getType());
872 const FunctionType *FTy = cast<FunctionType>(PT->getElementType());
874 std::pair<SDOperand,SDOperand> Result =
875 TLI.LowerCallTo(getRoot(), I.getType(), FTy->isVarArg(), I.getCallingConv(),
876 I.isTailCall(), Callee, Args, DAG);
877 if (I.getType() != Type::VoidTy)
878 setValue(&I, Result.first);
879 DAG.setRoot(Result.second);
882 void SelectionDAGLowering::visitMalloc(MallocInst &I) {
883 SDOperand Src = getValue(I.getOperand(0));
885 MVT::ValueType IntPtr = TLI.getPointerTy();
887 if (IntPtr < Src.getValueType())
888 Src = DAG.getNode(ISD::TRUNCATE, IntPtr, Src);
889 else if (IntPtr > Src.getValueType())
890 Src = DAG.getNode(ISD::ZERO_EXTEND, IntPtr, Src);
892 // Scale the source by the type size.
893 uint64_t ElementSize = TD.getTypeSize(I.getType()->getElementType());
894 Src = DAG.getNode(ISD::MUL, Src.getValueType(),
895 Src, getIntPtrConstant(ElementSize));
897 std::vector<std::pair<SDOperand, const Type*> > Args;
898 Args.push_back(std::make_pair(Src, TLI.getTargetData().getIntPtrType()));
900 std::pair<SDOperand,SDOperand> Result =
901 TLI.LowerCallTo(getRoot(), I.getType(), false, CallingConv::C, true,
902 DAG.getExternalSymbol("malloc", IntPtr),
904 setValue(&I, Result.first); // Pointers always fit in registers
905 DAG.setRoot(Result.second);
908 void SelectionDAGLowering::visitFree(FreeInst &I) {
909 std::vector<std::pair<SDOperand, const Type*> > Args;
910 Args.push_back(std::make_pair(getValue(I.getOperand(0)),
911 TLI.getTargetData().getIntPtrType()));
912 MVT::ValueType IntPtr = TLI.getPointerTy();
913 std::pair<SDOperand,SDOperand> Result =
914 TLI.LowerCallTo(getRoot(), Type::VoidTy, false, CallingConv::C, true,
915 DAG.getExternalSymbol("free", IntPtr), Args, DAG);
916 DAG.setRoot(Result.second);
919 // InsertAtEndOfBasicBlock - This method should be implemented by targets that
920 // mark instructions with the 'usesCustomDAGSchedInserter' flag. These
921 // instructions are special in various ways, which require special support to
922 // insert. The specified MachineInstr is created but not inserted into any
923 // basic blocks, and the scheduler passes ownership of it to this method.
924 MachineBasicBlock *TargetLowering::InsertAtEndOfBasicBlock(MachineInstr *MI,
925 MachineBasicBlock *MBB) {
926 std::cerr << "If a target marks an instruction with "
927 "'usesCustomDAGSchedInserter', it must implement "
928 "TargetLowering::InsertAtEndOfBasicBlock!\n";
933 SDOperand TargetLowering::LowerReturnTo(SDOperand Chain, SDOperand Op,
935 return DAG.getNode(ISD::RET, MVT::Other, Chain, Op);
938 SDOperand TargetLowering::LowerVAStart(SDOperand Chain,
939 SDOperand VAListP, Value *VAListV,
941 // We have no sane default behavior, just emit a useful error message and bail
943 std::cerr << "Variable arguments handling not implemented on this target!\n";
948 SDOperand TargetLowering::LowerVAEnd(SDOperand Chain, SDOperand LP, Value *LV,
950 // Default to a noop.
954 SDOperand TargetLowering::LowerVACopy(SDOperand Chain,
955 SDOperand SrcP, Value *SrcV,
956 SDOperand DestP, Value *DestV,
958 // Default to copying the input list.
959 SDOperand Val = DAG.getLoad(getPointerTy(), Chain,
960 SrcP, DAG.getSrcValue(SrcV));
961 SDOperand Result = DAG.getNode(ISD::STORE, MVT::Other, Val.getValue(1),
962 Val, DestP, DAG.getSrcValue(DestV));
966 std::pair<SDOperand,SDOperand>
967 TargetLowering::LowerVAArg(SDOperand Chain, SDOperand VAListP, Value *VAListV,
968 const Type *ArgTy, SelectionDAG &DAG) {
969 // We have no sane default behavior, just emit a useful error message and bail
971 std::cerr << "Variable arguments handling not implemented on this target!\n";
973 return std::make_pair(SDOperand(), SDOperand());
977 void SelectionDAGLowering::visitVAStart(CallInst &I) {
978 DAG.setRoot(TLI.LowerVAStart(getRoot(), getValue(I.getOperand(1)),
979 I.getOperand(1), DAG));
982 void SelectionDAGLowering::visitVAArg(VAArgInst &I) {
983 std::pair<SDOperand,SDOperand> Result =
984 TLI.LowerVAArg(getRoot(), getValue(I.getOperand(0)), I.getOperand(0),
986 setValue(&I, Result.first);
987 DAG.setRoot(Result.second);
990 void SelectionDAGLowering::visitVAEnd(CallInst &I) {
991 DAG.setRoot(TLI.LowerVAEnd(getRoot(), getValue(I.getOperand(1)),
992 I.getOperand(1), DAG));
995 void SelectionDAGLowering::visitVACopy(CallInst &I) {
997 TLI.LowerVACopy(getRoot(), getValue(I.getOperand(2)), I.getOperand(2),
998 getValue(I.getOperand(1)), I.getOperand(1), DAG);
1003 // It is always conservatively correct for llvm.returnaddress and
1004 // llvm.frameaddress to return 0.
1005 std::pair<SDOperand, SDOperand>
1006 TargetLowering::LowerFrameReturnAddress(bool isFrameAddr, SDOperand Chain,
1007 unsigned Depth, SelectionDAG &DAG) {
1008 return std::make_pair(DAG.getConstant(0, getPointerTy()), Chain);
1011 SDOperand TargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
1012 assert(0 && "LowerOperation not implemented for this target!");
1017 void SelectionDAGLowering::visitFrameReturnAddress(CallInst &I, bool isFrame) {
1018 unsigned Depth = (unsigned)cast<ConstantUInt>(I.getOperand(1))->getValue();
1019 std::pair<SDOperand,SDOperand> Result =
1020 TLI.LowerFrameReturnAddress(isFrame, getRoot(), Depth, DAG);
1021 setValue(&I, Result.first);
1022 DAG.setRoot(Result.second);
1025 void SelectionDAGLowering::visitMemIntrinsic(CallInst &I, unsigned Op) {
1026 std::vector<SDOperand> Ops;
1027 Ops.push_back(getRoot());
1028 Ops.push_back(getValue(I.getOperand(1)));
1029 Ops.push_back(getValue(I.getOperand(2)));
1030 Ops.push_back(getValue(I.getOperand(3)));
1031 Ops.push_back(getValue(I.getOperand(4)));
1032 DAG.setRoot(DAG.getNode(Op, MVT::Other, Ops));
1035 //===----------------------------------------------------------------------===//
1036 // SelectionDAGISel code
1037 //===----------------------------------------------------------------------===//
1039 unsigned SelectionDAGISel::MakeReg(MVT::ValueType VT) {
1040 return RegMap->createVirtualRegister(TLI.getRegClassFor(VT));
1043 void SelectionDAGISel::getAnalysisUsage(AnalysisUsage &AU) const {
1044 // FIXME: we only modify the CFG to split critical edges. This
1045 // updates dom and loop info.
1049 bool SelectionDAGISel::runOnFunction(Function &Fn) {
1050 MachineFunction &MF = MachineFunction::construct(&Fn, TLI.getTargetMachine());
1051 RegMap = MF.getSSARegMap();
1052 DEBUG(std::cerr << "\n\n\n=== " << Fn.getName() << "\n");
1054 // First pass, split all critical edges for PHI nodes with incoming values
1055 // that are constants, this way the load of the constant into a vreg will not
1056 // be placed into MBBs that are used some other way.
1057 for (Function::iterator BB = Fn.begin(), E = Fn.end(); BB != E; ++BB) {
1059 for (BasicBlock::iterator BBI = BB->begin();
1060 (PN = dyn_cast<PHINode>(BBI)); ++BBI)
1061 for (unsigned i = 0, e = PN->getNumIncomingValues(); i != e; ++i)
1062 if (isa<Constant>(PN->getIncomingValue(i)))
1063 SplitCriticalEdge(PN->getIncomingBlock(i), BB);
1066 FunctionLoweringInfo FuncInfo(TLI, Fn, MF);
1068 for (Function::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I)
1069 SelectBasicBlock(I, MF, FuncInfo);
1075 SDOperand SelectionDAGISel::
1076 CopyValueToVirtualRegister(SelectionDAGLowering &SDL, Value *V, unsigned Reg) {
1077 SDOperand Op = SDL.getValue(V);
1078 assert((Op.getOpcode() != ISD::CopyFromReg ||
1079 cast<RegisterSDNode>(Op.getOperand(1))->getReg() != Reg) &&
1080 "Copy from a reg to the same reg!");
1082 // If this type is not legal, we must make sure to not create an invalid
1084 MVT::ValueType SrcVT = Op.getValueType();
1085 MVT::ValueType DestVT = TLI.getTypeToTransformTo(SrcVT);
1086 SelectionDAG &DAG = SDL.DAG;
1087 if (SrcVT == DestVT) {
1088 return DAG.getCopyToReg(SDL.getRoot(), Reg, Op);
1089 } else if (SrcVT < DestVT) {
1090 // The src value is promoted to the register.
1091 if (MVT::isFloatingPoint(SrcVT))
1092 Op = DAG.getNode(ISD::FP_EXTEND, DestVT, Op);
1094 Op = DAG.getNode(ISD::ANY_EXTEND, DestVT, Op);
1095 return DAG.getCopyToReg(SDL.getRoot(), Reg, Op);
1097 // The src value is expanded into multiple registers.
1098 SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, DestVT,
1099 Op, DAG.getConstant(0, MVT::i32));
1100 SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, DestVT,
1101 Op, DAG.getConstant(1, MVT::i32));
1102 Op = DAG.getCopyToReg(SDL.getRoot(), Reg, Lo);
1103 return DAG.getCopyToReg(Op, Reg+1, Hi);
1107 void SelectionDAGISel::
1108 LowerArguments(BasicBlock *BB, SelectionDAGLowering &SDL,
1109 std::vector<SDOperand> &UnorderedChains) {
1110 // If this is the entry block, emit arguments.
1111 Function &F = *BB->getParent();
1112 FunctionLoweringInfo &FuncInfo = SDL.FuncInfo;
1113 SDOperand OldRoot = SDL.DAG.getRoot();
1114 std::vector<SDOperand> Args = TLI.LowerArguments(F, SDL.DAG);
1117 for (Function::arg_iterator AI = F.arg_begin(), E = F.arg_end();
1119 if (!AI->use_empty()) {
1120 SDL.setValue(AI, Args[a]);
1122 // If this argument is live outside of the entry block, insert a copy from
1123 // whereever we got it to the vreg that other BB's will reference it as.
1124 if (FuncInfo.ValueMap.count(AI)) {
1126 CopyValueToVirtualRegister(SDL, AI, FuncInfo.ValueMap[AI]);
1127 UnorderedChains.push_back(Copy);
1131 // Next, if the function has live ins that need to be copied into vregs,
1132 // emit the copies now, into the top of the block.
1133 MachineFunction &MF = SDL.DAG.getMachineFunction();
1134 if (MF.livein_begin() != MF.livein_end()) {
1135 SSARegMap *RegMap = MF.getSSARegMap();
1136 const MRegisterInfo &MRI = *MF.getTarget().getRegisterInfo();
1137 for (MachineFunction::livein_iterator LI = MF.livein_begin(),
1138 E = MF.livein_end(); LI != E; ++LI)
1140 MRI.copyRegToReg(*MF.begin(), MF.begin()->end(), LI->second,
1141 LI->first, RegMap->getRegClass(LI->second));
1144 // Finally, if the target has anything special to do, allow it to do so.
1145 EmitFunctionEntryCode(F, SDL.DAG.getMachineFunction());
1149 void SelectionDAGISel::BuildSelectionDAG(SelectionDAG &DAG, BasicBlock *LLVMBB,
1150 std::vector<std::pair<MachineInstr*, unsigned> > &PHINodesToUpdate,
1151 FunctionLoweringInfo &FuncInfo) {
1152 SelectionDAGLowering SDL(DAG, TLI, FuncInfo);
1154 std::vector<SDOperand> UnorderedChains;
1156 // Lower any arguments needed in this block if this is the entry block.
1157 if (LLVMBB == &LLVMBB->getParent()->front())
1158 LowerArguments(LLVMBB, SDL, UnorderedChains);
1160 BB = FuncInfo.MBBMap[LLVMBB];
1161 SDL.setCurrentBasicBlock(BB);
1163 // Lower all of the non-terminator instructions.
1164 for (BasicBlock::iterator I = LLVMBB->begin(), E = --LLVMBB->end();
1168 // Ensure that all instructions which are used outside of their defining
1169 // blocks are available as virtual registers.
1170 for (BasicBlock::iterator I = LLVMBB->begin(), E = LLVMBB->end(); I != E;++I)
1171 if (!I->use_empty() && !isa<PHINode>(I)) {
1172 std::map<const Value*, unsigned>::iterator VMI =FuncInfo.ValueMap.find(I);
1173 if (VMI != FuncInfo.ValueMap.end())
1174 UnorderedChains.push_back(
1175 CopyValueToVirtualRegister(SDL, I, VMI->second));
1178 // Handle PHI nodes in successor blocks. Emit code into the SelectionDAG to
1179 // ensure constants are generated when needed. Remember the virtual registers
1180 // that need to be added to the Machine PHI nodes as input. We cannot just
1181 // directly add them, because expansion might result in multiple MBB's for one
1182 // BB. As such, the start of the BB might correspond to a different MBB than
1186 // Emit constants only once even if used by multiple PHI nodes.
1187 std::map<Constant*, unsigned> ConstantsOut;
1189 // Check successor nodes PHI nodes that expect a constant to be available from
1191 TerminatorInst *TI = LLVMBB->getTerminator();
1192 for (unsigned succ = 0, e = TI->getNumSuccessors(); succ != e; ++succ) {
1193 BasicBlock *SuccBB = TI->getSuccessor(succ);
1194 MachineBasicBlock::iterator MBBI = FuncInfo.MBBMap[SuccBB]->begin();
1197 // At this point we know that there is a 1-1 correspondence between LLVM PHI
1198 // nodes and Machine PHI nodes, but the incoming operands have not been
1200 for (BasicBlock::iterator I = SuccBB->begin();
1201 (PN = dyn_cast<PHINode>(I)); ++I)
1202 if (!PN->use_empty()) {
1204 Value *PHIOp = PN->getIncomingValueForBlock(LLVMBB);
1205 if (Constant *C = dyn_cast<Constant>(PHIOp)) {
1206 unsigned &RegOut = ConstantsOut[C];
1208 RegOut = FuncInfo.CreateRegForValue(C);
1209 UnorderedChains.push_back(
1210 CopyValueToVirtualRegister(SDL, C, RegOut));
1214 Reg = FuncInfo.ValueMap[PHIOp];
1216 assert(isa<AllocaInst>(PHIOp) &&
1217 FuncInfo.StaticAllocaMap.count(cast<AllocaInst>(PHIOp)) &&
1218 "Didn't codegen value into a register!??");
1219 Reg = FuncInfo.CreateRegForValue(PHIOp);
1220 UnorderedChains.push_back(
1221 CopyValueToVirtualRegister(SDL, PHIOp, Reg));
1225 // Remember that this register needs to added to the machine PHI node as
1226 // the input for this MBB.
1227 unsigned NumElements =
1228 TLI.getNumElements(TLI.getValueType(PN->getType()));
1229 for (unsigned i = 0, e = NumElements; i != e; ++i)
1230 PHINodesToUpdate.push_back(std::make_pair(MBBI++, Reg+i));
1233 ConstantsOut.clear();
1235 // Turn all of the unordered chains into one factored node.
1236 if (!UnorderedChains.empty()) {
1237 UnorderedChains.push_back(SDL.getRoot());
1238 DAG.setRoot(DAG.getNode(ISD::TokenFactor, MVT::Other, UnorderedChains));
1241 // Lower the terminator after the copies are emitted.
1242 SDL.visit(*LLVMBB->getTerminator());
1244 // Make sure the root of the DAG is up-to-date.
1245 DAG.setRoot(SDL.getRoot());
1248 void SelectionDAGISel::SelectBasicBlock(BasicBlock *LLVMBB, MachineFunction &MF,
1249 FunctionLoweringInfo &FuncInfo) {
1250 SelectionDAG DAG(TLI, MF);
1252 std::vector<std::pair<MachineInstr*, unsigned> > PHINodesToUpdate;
1254 // First step, lower LLVM code to some DAG. This DAG may use operations and
1255 // types that are not supported by the target.
1256 BuildSelectionDAG(DAG, LLVMBB, PHINodesToUpdate, FuncInfo);
1258 // Run the DAG combiner in pre-legalize mode.
1261 DEBUG(std::cerr << "Lowered selection DAG:\n");
1264 // Second step, hack on the DAG until it only uses operations and types that
1265 // the target supports.
1268 DEBUG(std::cerr << "Legalized selection DAG:\n");
1271 // Run the DAG combiner in post-legalize mode.
1274 if (ViewDAGs) DAG.viewGraph();
1276 // Third, instruction select all of the operations to machine code, adding the
1277 // code to the MachineBasicBlock.
1278 InstructionSelectBasicBlock(DAG);
1280 DEBUG(std::cerr << "Selected machine code:\n");
1283 // Next, now that we know what the last MBB the LLVM BB expanded is, update
1284 // PHI nodes in successors.
1285 for (unsigned i = 0, e = PHINodesToUpdate.size(); i != e; ++i) {
1286 MachineInstr *PHI = PHINodesToUpdate[i].first;
1287 assert(PHI->getOpcode() == TargetInstrInfo::PHI &&
1288 "This is not a machine PHI node that we are updating!");
1289 PHI->addRegOperand(PHINodesToUpdate[i].second);
1290 PHI->addMachineBasicBlockOperand(BB);
1293 // Finally, add the CFG edges from the last selected MBB to the successor
1295 TerminatorInst *TI = LLVMBB->getTerminator();
1296 for (unsigned i = 0, e = TI->getNumSuccessors(); i != e; ++i) {
1297 MachineBasicBlock *Succ0MBB = FuncInfo.MBBMap[TI->getSuccessor(i)];
1298 BB->addSuccessor(Succ0MBB);