1 //===-- SelectionDAGISel.cpp - Implement the SelectionDAGISel class -------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements the SelectionDAGISel class.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "isel"
15 #include "llvm/Analysis/AliasAnalysis.h"
16 #include "llvm/CodeGen/SelectionDAGISel.h"
17 #include "llvm/CodeGen/ScheduleDAG.h"
18 #include "llvm/CallingConv.h"
19 #include "llvm/Constants.h"
20 #include "llvm/DerivedTypes.h"
21 #include "llvm/Function.h"
22 #include "llvm/GlobalVariable.h"
23 #include "llvm/InlineAsm.h"
24 #include "llvm/Instructions.h"
25 #include "llvm/Intrinsics.h"
26 #include "llvm/IntrinsicInst.h"
27 #include "llvm/CodeGen/IntrinsicLowering.h"
28 #include "llvm/CodeGen/MachineDebugInfo.h"
29 #include "llvm/CodeGen/MachineFunction.h"
30 #include "llvm/CodeGen/MachineFrameInfo.h"
31 #include "llvm/CodeGen/MachineJumpTableInfo.h"
32 #include "llvm/CodeGen/MachineInstrBuilder.h"
33 #include "llvm/CodeGen/SchedulerRegistry.h"
34 #include "llvm/CodeGen/SelectionDAG.h"
35 #include "llvm/CodeGen/SSARegMap.h"
36 #include "llvm/Target/MRegisterInfo.h"
37 #include "llvm/Target/TargetData.h"
38 #include "llvm/Target/TargetFrameInfo.h"
39 #include "llvm/Target/TargetInstrInfo.h"
40 #include "llvm/Target/TargetLowering.h"
41 #include "llvm/Target/TargetMachine.h"
42 #include "llvm/Target/TargetOptions.h"
43 #include "llvm/Transforms/Utils/BasicBlockUtils.h"
44 #include "llvm/Support/MathExtras.h"
45 #include "llvm/Support/Debug.h"
46 #include "llvm/Support/Compiler.h"
53 ViewISelDAGs("view-isel-dags", cl::Hidden,
54 cl::desc("Pop up a window to show isel dags as they are selected"));
56 ViewSchedDAGs("view-sched-dags", cl::Hidden,
57 cl::desc("Pop up a window to show sched dags as they are processed"));
59 static const bool ViewISelDAGs = 0, ViewSchedDAGs = 0;
63 //===---------------------------------------------------------------------===//
65 /// RegisterScheduler class - Track the registration of instruction schedulers.
67 //===---------------------------------------------------------------------===//
68 MachinePassRegistry RegisterScheduler::Registry;
70 //===---------------------------------------------------------------------===//
72 /// ISHeuristic command line option for instruction schedulers.
74 //===---------------------------------------------------------------------===//
76 cl::opt<RegisterScheduler::FunctionPassCtor, false,
77 RegisterPassParser<RegisterScheduler> >
79 cl::init(&createDefaultScheduler),
80 cl::desc("Instruction schedulers available:"));
82 static RegisterScheduler
83 defaultListDAGScheduler("default", " Best scheduler for the target",
84 createDefaultScheduler);
88 /// RegsForValue - This struct represents the physical registers that a
89 /// particular value is assigned and the type information about the value.
90 /// This is needed because values can be promoted into larger registers and
91 /// expanded into multiple smaller registers than the value.
92 struct VISIBILITY_HIDDEN RegsForValue {
93 /// Regs - This list hold the register (for legal and promoted values)
94 /// or register set (for expanded values) that the value should be assigned
96 std::vector<unsigned> Regs;
98 /// RegVT - The value type of each register.
100 MVT::ValueType RegVT;
102 /// ValueVT - The value type of the LLVM value, which may be promoted from
103 /// RegVT or made from merging the two expanded parts.
104 MVT::ValueType ValueVT;
106 RegsForValue() : RegVT(MVT::Other), ValueVT(MVT::Other) {}
108 RegsForValue(unsigned Reg, MVT::ValueType regvt, MVT::ValueType valuevt)
109 : RegVT(regvt), ValueVT(valuevt) {
112 RegsForValue(const std::vector<unsigned> ®s,
113 MVT::ValueType regvt, MVT::ValueType valuevt)
114 : Regs(regs), RegVT(regvt), ValueVT(valuevt) {
117 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from
118 /// this value and returns the result as a ValueVT value. This uses
119 /// Chain/Flag as the input and updates them for the output Chain/Flag.
120 SDOperand getCopyFromRegs(SelectionDAG &DAG,
121 SDOperand &Chain, SDOperand &Flag) const;
123 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
124 /// specified value into the registers specified by this object. This uses
125 /// Chain/Flag as the input and updates them for the output Chain/Flag.
126 void getCopyToRegs(SDOperand Val, SelectionDAG &DAG,
127 SDOperand &Chain, SDOperand &Flag,
128 MVT::ValueType PtrVT) const;
130 /// AddInlineAsmOperands - Add this value to the specified inlineasm node
131 /// operand list. This adds the code marker and includes the number of
132 /// values added into it.
133 void AddInlineAsmOperands(unsigned Code, SelectionDAG &DAG,
134 std::vector<SDOperand> &Ops) const;
139 //===--------------------------------------------------------------------===//
140 /// createDefaultScheduler - This creates an instruction scheduler appropriate
142 ScheduleDAG* createDefaultScheduler(SelectionDAGISel *IS,
144 MachineBasicBlock *BB) {
145 TargetLowering &TLI = IS->getTargetLowering();
147 if (TLI.getSchedulingPreference() == TargetLowering::SchedulingForLatency) {
148 return createTDListDAGScheduler(IS, DAG, BB);
150 assert(TLI.getSchedulingPreference() ==
151 TargetLowering::SchedulingForRegPressure && "Unknown sched type!");
152 return createBURRListDAGScheduler(IS, DAG, BB);
157 //===--------------------------------------------------------------------===//
158 /// FunctionLoweringInfo - This contains information that is global to a
159 /// function that is used when lowering a region of the function.
160 class FunctionLoweringInfo {
167 FunctionLoweringInfo(TargetLowering &TLI, Function &Fn,MachineFunction &MF);
169 /// MBBMap - A mapping from LLVM basic blocks to their machine code entry.
170 std::map<const BasicBlock*, MachineBasicBlock *> MBBMap;
172 /// ValueMap - Since we emit code for the function a basic block at a time,
173 /// we must remember which virtual registers hold the values for
174 /// cross-basic-block values.
175 std::map<const Value*, unsigned> ValueMap;
177 /// StaticAllocaMap - Keep track of frame indices for fixed sized allocas in
178 /// the entry block. This allows the allocas to be efficiently referenced
179 /// anywhere in the function.
180 std::map<const AllocaInst*, int> StaticAllocaMap;
182 unsigned MakeReg(MVT::ValueType VT) {
183 return RegMap->createVirtualRegister(TLI.getRegClassFor(VT));
186 /// isExportedInst - Return true if the specified value is an instruction
187 /// exported from its block.
188 bool isExportedInst(const Value *V) {
189 return ValueMap.count(V);
192 unsigned CreateRegForValue(const Value *V);
194 unsigned InitializeRegForValue(const Value *V) {
195 unsigned &R = ValueMap[V];
196 assert(R == 0 && "Already initialized this value register!");
197 return R = CreateRegForValue(V);
202 /// isUsedOutsideOfDefiningBlock - Return true if this instruction is used by
203 /// PHI nodes or outside of the basic block that defines it, or used by a
204 /// switch instruction, which may expand to multiple basic blocks.
205 static bool isUsedOutsideOfDefiningBlock(Instruction *I) {
206 if (isa<PHINode>(I)) return true;
207 BasicBlock *BB = I->getParent();
208 for (Value::use_iterator UI = I->use_begin(), E = I->use_end(); UI != E; ++UI)
209 if (cast<Instruction>(*UI)->getParent() != BB || isa<PHINode>(*UI) ||
210 // FIXME: Remove switchinst special case.
211 isa<SwitchInst>(*UI))
216 /// isOnlyUsedInEntryBlock - If the specified argument is only used in the
217 /// entry block, return true. This includes arguments used by switches, since
218 /// the switch may expand into multiple basic blocks.
219 static bool isOnlyUsedInEntryBlock(Argument *A) {
220 BasicBlock *Entry = A->getParent()->begin();
221 for (Value::use_iterator UI = A->use_begin(), E = A->use_end(); UI != E; ++UI)
222 if (cast<Instruction>(*UI)->getParent() != Entry || isa<SwitchInst>(*UI))
223 return false; // Use not in entry block.
227 FunctionLoweringInfo::FunctionLoweringInfo(TargetLowering &tli,
228 Function &fn, MachineFunction &mf)
229 : TLI(tli), Fn(fn), MF(mf), RegMap(MF.getSSARegMap()) {
231 // Create a vreg for each argument register that is not dead and is used
232 // outside of the entry block for the function.
233 for (Function::arg_iterator AI = Fn.arg_begin(), E = Fn.arg_end();
235 if (!isOnlyUsedInEntryBlock(AI))
236 InitializeRegForValue(AI);
238 // Initialize the mapping of values to registers. This is only set up for
239 // instruction values that are used outside of the block that defines
241 Function::iterator BB = Fn.begin(), EB = Fn.end();
242 for (BasicBlock::iterator I = BB->begin(), E = BB->end(); I != E; ++I)
243 if (AllocaInst *AI = dyn_cast<AllocaInst>(I))
244 if (ConstantInt *CUI = dyn_cast<ConstantInt>(AI->getArraySize())) {
245 const Type *Ty = AI->getAllocatedType();
246 uint64_t TySize = TLI.getTargetData()->getTypeSize(Ty);
248 std::max((unsigned)TLI.getTargetData()->getTypeAlignment(Ty),
251 // If the alignment of the value is smaller than the size of the
252 // value, and if the size of the value is particularly small
253 // (<= 8 bytes), round up to the size of the value for potentially
254 // better performance.
256 // FIXME: This could be made better with a preferred alignment hook in
257 // TargetData. It serves primarily to 8-byte align doubles for X86.
258 if (Align < TySize && TySize <= 8) Align = TySize;
259 TySize *= CUI->getZExtValue(); // Get total allocated size.
260 if (TySize == 0) TySize = 1; // Don't create zero-sized stack objects.
261 StaticAllocaMap[AI] =
262 MF.getFrameInfo()->CreateStackObject((unsigned)TySize, Align);
265 for (; BB != EB; ++BB)
266 for (BasicBlock::iterator I = BB->begin(), E = BB->end(); I != E; ++I)
267 if (!I->use_empty() && isUsedOutsideOfDefiningBlock(I))
268 if (!isa<AllocaInst>(I) ||
269 !StaticAllocaMap.count(cast<AllocaInst>(I)))
270 InitializeRegForValue(I);
272 // Create an initial MachineBasicBlock for each LLVM BasicBlock in F. This
273 // also creates the initial PHI MachineInstrs, though none of the input
274 // operands are populated.
275 for (BB = Fn.begin(), EB = Fn.end(); BB != EB; ++BB) {
276 MachineBasicBlock *MBB = new MachineBasicBlock(BB);
278 MF.getBasicBlockList().push_back(MBB);
280 // Create Machine PHI nodes for LLVM PHI nodes, lowering them as
283 for (BasicBlock::iterator I = BB->begin();(PN = dyn_cast<PHINode>(I)); ++I){
284 if (PN->use_empty()) continue;
286 MVT::ValueType VT = TLI.getValueType(PN->getType());
287 unsigned NumElements;
288 if (VT != MVT::Vector)
289 NumElements = TLI.getNumElements(VT);
291 MVT::ValueType VT1,VT2;
293 TLI.getPackedTypeBreakdown(cast<PackedType>(PN->getType()),
296 unsigned PHIReg = ValueMap[PN];
297 assert(PHIReg && "PHI node does not have an assigned virtual register!");
298 for (unsigned i = 0; i != NumElements; ++i)
299 BuildMI(MBB, TargetInstrInfo::PHI, PN->getNumOperands(), PHIReg+i);
304 /// CreateRegForValue - Allocate the appropriate number of virtual registers of
305 /// the correctly promoted or expanded types. Assign these registers
306 /// consecutive vreg numbers and return the first assigned number.
307 unsigned FunctionLoweringInfo::CreateRegForValue(const Value *V) {
308 MVT::ValueType VT = TLI.getValueType(V->getType());
310 // The number of multiples of registers that we need, to, e.g., split up
311 // a <2 x int64> -> 4 x i32 registers.
312 unsigned NumVectorRegs = 1;
314 // If this is a packed type, figure out what type it will decompose into
315 // and how many of the elements it will use.
316 if (VT == MVT::Vector) {
317 const PackedType *PTy = cast<PackedType>(V->getType());
318 unsigned NumElts = PTy->getNumElements();
319 MVT::ValueType EltTy = TLI.getValueType(PTy->getElementType());
321 // Divide the input until we get to a supported size. This will always
322 // end with a scalar if the target doesn't support vectors.
323 while (NumElts > 1 && !TLI.isTypeLegal(getVectorType(EltTy, NumElts))) {
330 VT = getVectorType(EltTy, NumElts);
333 // The common case is that we will only create one register for this
334 // value. If we have that case, create and return the virtual register.
335 unsigned NV = TLI.getNumElements(VT);
337 // If we are promoting this value, pick the next largest supported type.
338 MVT::ValueType PromotedType = TLI.getTypeToTransformTo(VT);
339 unsigned Reg = MakeReg(PromotedType);
340 // If this is a vector of supported or promoted types (e.g. 4 x i16),
341 // create all of the registers.
342 for (unsigned i = 1; i != NumVectorRegs; ++i)
343 MakeReg(PromotedType);
347 // If this value is represented with multiple target registers, make sure
348 // to create enough consecutive registers of the right (smaller) type.
349 unsigned NT = VT-1; // Find the type to use.
350 while (TLI.getNumElements((MVT::ValueType)NT) != 1)
353 unsigned R = MakeReg((MVT::ValueType)NT);
354 for (unsigned i = 1; i != NV*NumVectorRegs; ++i)
355 MakeReg((MVT::ValueType)NT);
359 //===----------------------------------------------------------------------===//
360 /// SelectionDAGLowering - This is the common target-independent lowering
361 /// implementation that is parameterized by a TargetLowering object.
362 /// Also, targets can overload any lowering method.
365 class SelectionDAGLowering {
366 MachineBasicBlock *CurMBB;
368 std::map<const Value*, SDOperand> NodeMap;
370 /// PendingLoads - Loads are not emitted to the program immediately. We bunch
371 /// them up and then emit token factor nodes when possible. This allows us to
372 /// get simple disambiguation between loads without worrying about alias
374 std::vector<SDOperand> PendingLoads;
376 /// Case - A pair of values to record the Value for a switch case, and the
377 /// case's target basic block.
378 typedef std::pair<Constant*, MachineBasicBlock*> Case;
379 typedef std::vector<Case>::iterator CaseItr;
380 typedef std::pair<CaseItr, CaseItr> CaseRange;
382 /// CaseRec - A struct with ctor used in lowering switches to a binary tree
383 /// of conditional branches.
385 CaseRec(MachineBasicBlock *bb, Constant *lt, Constant *ge, CaseRange r) :
386 CaseBB(bb), LT(lt), GE(ge), Range(r) {}
388 /// CaseBB - The MBB in which to emit the compare and branch
389 MachineBasicBlock *CaseBB;
390 /// LT, GE - If nonzero, we know the current case value must be less-than or
391 /// greater-than-or-equal-to these Constants.
394 /// Range - A pair of iterators representing the range of case values to be
395 /// processed at this point in the binary search tree.
399 /// The comparison function for sorting Case values.
401 bool operator () (const Case& C1, const Case& C2) {
402 if (const ConstantInt* I1 = dyn_cast<const ConstantInt>(C1.first))
403 if (I1->getType()->isUnsigned())
404 return I1->getZExtValue() <
405 cast<const ConstantInt>(C2.first)->getZExtValue();
407 return cast<const ConstantInt>(C1.first)->getSExtValue() <
408 cast<const ConstantInt>(C2.first)->getSExtValue();
413 // TLI - This is information that describes the available target features we
414 // need for lowering. This indicates when operations are unavailable,
415 // implemented with a libcall, etc.
418 const TargetData *TD;
420 /// SwitchCases - Vector of CaseBlock structures used to communicate
421 /// SwitchInst code generation information.
422 std::vector<SelectionDAGISel::CaseBlock> SwitchCases;
423 SelectionDAGISel::JumpTable JT;
425 /// FuncInfo - Information about the function as a whole.
427 FunctionLoweringInfo &FuncInfo;
429 SelectionDAGLowering(SelectionDAG &dag, TargetLowering &tli,
430 FunctionLoweringInfo &funcinfo)
431 : TLI(tli), DAG(dag), TD(DAG.getTarget().getTargetData()),
432 JT(0,0,0,0), FuncInfo(funcinfo) {
435 /// getRoot - Return the current virtual root of the Selection DAG.
437 SDOperand getRoot() {
438 if (PendingLoads.empty())
439 return DAG.getRoot();
441 if (PendingLoads.size() == 1) {
442 SDOperand Root = PendingLoads[0];
444 PendingLoads.clear();
448 // Otherwise, we have to make a token factor node.
449 SDOperand Root = DAG.getNode(ISD::TokenFactor, MVT::Other,
450 &PendingLoads[0], PendingLoads.size());
451 PendingLoads.clear();
456 SDOperand CopyValueToVirtualRegister(Value *V, unsigned Reg);
458 void visit(Instruction &I) { visit(I.getOpcode(), I); }
460 void visit(unsigned Opcode, User &I) {
462 default: assert(0 && "Unknown instruction type encountered!");
464 // Build the switch statement using the Instruction.def file.
465 #define HANDLE_INST(NUM, OPCODE, CLASS) \
466 case Instruction::OPCODE:return visit##OPCODE((CLASS&)I);
467 #include "llvm/Instruction.def"
471 void setCurrentBasicBlock(MachineBasicBlock *MBB) { CurMBB = MBB; }
473 SDOperand getLoadFrom(const Type *Ty, SDOperand Ptr,
474 const Value *SV, SDOperand Root,
477 SDOperand getIntPtrConstant(uint64_t Val) {
478 return DAG.getConstant(Val, TLI.getPointerTy());
481 SDOperand getValue(const Value *V);
483 const SDOperand &setValue(const Value *V, SDOperand NewN) {
484 SDOperand &N = NodeMap[V];
485 assert(N.Val == 0 && "Already set a value for this node!");
489 RegsForValue GetRegistersForValue(const std::string &ConstrCode,
491 bool OutReg, bool InReg,
492 std::set<unsigned> &OutputRegs,
493 std::set<unsigned> &InputRegs);
495 void FindMergedConditions(Value *Cond, MachineBasicBlock *TBB,
496 MachineBasicBlock *FBB, MachineBasicBlock *CurBB,
498 bool isExportableFromCurrentBlock(Value *V, const BasicBlock *FromBB);
499 void ExportFromCurrentBlock(Value *V);
501 // Terminator instructions.
502 void visitRet(ReturnInst &I);
503 void visitBr(BranchInst &I);
504 void visitSwitch(SwitchInst &I);
505 void visitUnreachable(UnreachableInst &I) { /* noop */ }
507 // Helper for visitSwitch
508 void visitSwitchCase(SelectionDAGISel::CaseBlock &CB);
509 void visitJumpTable(SelectionDAGISel::JumpTable &JT);
511 // These all get lowered before this pass.
512 void visitInvoke(InvokeInst &I) { assert(0 && "TODO"); }
513 void visitUnwind(UnwindInst &I) { assert(0 && "TODO"); }
515 void visitIntBinary(User &I, unsigned IntOp, unsigned VecOp);
516 void visitFPBinary(User &I, unsigned FPOp, unsigned VecOp);
517 void visitShift(User &I, unsigned Opcode);
518 void visitAdd(User &I) {
519 if (I.getType()->isFloatingPoint())
520 visitFPBinary(I, ISD::FADD, ISD::VADD);
522 visitIntBinary(I, ISD::ADD, ISD::VADD);
524 void visitSub(User &I);
525 void visitMul(User &I) {
526 if (I.getType()->isFloatingPoint())
527 visitFPBinary(I, ISD::FMUL, ISD::VMUL);
529 visitIntBinary(I, ISD::MUL, ISD::VMUL);
531 void visitUDiv(User &I) { visitIntBinary(I, ISD::UDIV, ISD::VUDIV); }
532 void visitSDiv(User &I) { visitIntBinary(I, ISD::SDIV, ISD::VSDIV); }
533 void visitFDiv(User &I) { visitFPBinary(I, ISD::FDIV, ISD::VSDIV); }
534 void visitRem(User &I) {
535 const Type *Ty = I.getType();
536 if (Ty->isFloatingPoint())
537 visitFPBinary(I, ISD::FREM, 0);
539 visitIntBinary(I, Ty->isSigned() ? ISD::SREM : ISD::UREM, 0);
541 void visitAnd(User &I) { visitIntBinary(I, ISD::AND, ISD::VAND); }
542 void visitOr (User &I) { visitIntBinary(I, ISD::OR, ISD::VOR); }
543 void visitXor(User &I) { visitIntBinary(I, ISD::XOR, ISD::VXOR); }
544 void visitShl(User &I) { visitShift(I, ISD::SHL); }
545 void visitShr(User &I) {
546 visitShift(I, I.getType()->isUnsigned() ? ISD::SRL : ISD::SRA);
549 void visitSetCC(User &I, ISD::CondCode SignedOpc, ISD::CondCode UnsignedOpc,
550 ISD::CondCode FPOpc);
551 void visitSetEQ(User &I) { visitSetCC(I, ISD::SETEQ, ISD::SETEQ,
553 void visitSetNE(User &I) { visitSetCC(I, ISD::SETNE, ISD::SETNE,
555 void visitSetLE(User &I) { visitSetCC(I, ISD::SETLE, ISD::SETULE,
557 void visitSetGE(User &I) { visitSetCC(I, ISD::SETGE, ISD::SETUGE,
559 void visitSetLT(User &I) { visitSetCC(I, ISD::SETLT, ISD::SETULT,
561 void visitSetGT(User &I) { visitSetCC(I, ISD::SETGT, ISD::SETUGT,
564 void visitExtractElement(User &I);
565 void visitInsertElement(User &I);
566 void visitShuffleVector(User &I);
568 void visitGetElementPtr(User &I);
569 void visitCast(User &I);
570 void visitSelect(User &I);
572 void visitMalloc(MallocInst &I);
573 void visitFree(FreeInst &I);
574 void visitAlloca(AllocaInst &I);
575 void visitLoad(LoadInst &I);
576 void visitStore(StoreInst &I);
577 void visitPHI(PHINode &I) { } // PHI nodes are handled specially.
578 void visitCall(CallInst &I);
579 void visitInlineAsm(CallInst &I);
580 const char *visitIntrinsicCall(CallInst &I, unsigned Intrinsic);
581 void visitTargetIntrinsic(CallInst &I, unsigned Intrinsic);
583 void visitVAStart(CallInst &I);
584 void visitVAArg(VAArgInst &I);
585 void visitVAEnd(CallInst &I);
586 void visitVACopy(CallInst &I);
587 void visitFrameReturnAddress(CallInst &I, bool isFrameAddress);
589 void visitMemIntrinsic(CallInst &I, unsigned Op);
591 void visitUserOp1(Instruction &I) {
592 assert(0 && "UserOp1 should not exist at instruction selection time!");
595 void visitUserOp2(Instruction &I) {
596 assert(0 && "UserOp2 should not exist at instruction selection time!");
600 } // end namespace llvm
602 SDOperand SelectionDAGLowering::getValue(const Value *V) {
603 SDOperand &N = NodeMap[V];
606 const Type *VTy = V->getType();
607 MVT::ValueType VT = TLI.getValueType(VTy);
608 if (Constant *C = const_cast<Constant*>(dyn_cast<Constant>(V))) {
609 if (ConstantExpr *CE = dyn_cast<ConstantExpr>(C)) {
610 visit(CE->getOpcode(), *CE);
611 assert(N.Val && "visit didn't populate the ValueMap!");
613 } else if (GlobalValue *GV = dyn_cast<GlobalValue>(C)) {
614 return N = DAG.getGlobalAddress(GV, VT);
615 } else if (isa<ConstantPointerNull>(C)) {
616 return N = DAG.getConstant(0, TLI.getPointerTy());
617 } else if (isa<UndefValue>(C)) {
618 if (!isa<PackedType>(VTy))
619 return N = DAG.getNode(ISD::UNDEF, VT);
621 // Create a VBUILD_VECTOR of undef nodes.
622 const PackedType *PTy = cast<PackedType>(VTy);
623 unsigned NumElements = PTy->getNumElements();
624 MVT::ValueType PVT = TLI.getValueType(PTy->getElementType());
626 SmallVector<SDOperand, 8> Ops;
627 Ops.assign(NumElements, DAG.getNode(ISD::UNDEF, PVT));
629 // Create a VConstant node with generic Vector type.
630 Ops.push_back(DAG.getConstant(NumElements, MVT::i32));
631 Ops.push_back(DAG.getValueType(PVT));
632 return N = DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector,
633 &Ops[0], Ops.size());
634 } else if (ConstantFP *CFP = dyn_cast<ConstantFP>(C)) {
635 return N = DAG.getConstantFP(CFP->getValue(), VT);
636 } else if (const PackedType *PTy = dyn_cast<PackedType>(VTy)) {
637 unsigned NumElements = PTy->getNumElements();
638 MVT::ValueType PVT = TLI.getValueType(PTy->getElementType());
640 // Now that we know the number and type of the elements, push a
641 // Constant or ConstantFP node onto the ops list for each element of
642 // the packed constant.
643 SmallVector<SDOperand, 8> Ops;
644 if (ConstantPacked *CP = dyn_cast<ConstantPacked>(C)) {
645 for (unsigned i = 0; i != NumElements; ++i)
646 Ops.push_back(getValue(CP->getOperand(i)));
648 assert(isa<ConstantAggregateZero>(C) && "Unknown packed constant!");
650 if (MVT::isFloatingPoint(PVT))
651 Op = DAG.getConstantFP(0, PVT);
653 Op = DAG.getConstant(0, PVT);
654 Ops.assign(NumElements, Op);
657 // Create a VBUILD_VECTOR node with generic Vector type.
658 Ops.push_back(DAG.getConstant(NumElements, MVT::i32));
659 Ops.push_back(DAG.getValueType(PVT));
660 return N = DAG.getNode(ISD::VBUILD_VECTOR,MVT::Vector,&Ops[0],Ops.size());
662 // Canonicalize all constant ints to be unsigned.
663 return N = DAG.getConstant(cast<ConstantIntegral>(C)->getZExtValue(),VT);
667 if (const AllocaInst *AI = dyn_cast<AllocaInst>(V)) {
668 std::map<const AllocaInst*, int>::iterator SI =
669 FuncInfo.StaticAllocaMap.find(AI);
670 if (SI != FuncInfo.StaticAllocaMap.end())
671 return DAG.getFrameIndex(SI->second, TLI.getPointerTy());
674 std::map<const Value*, unsigned>::const_iterator VMI =
675 FuncInfo.ValueMap.find(V);
676 assert(VMI != FuncInfo.ValueMap.end() && "Value not in map!");
678 unsigned InReg = VMI->second;
680 // If this type is not legal, make it so now.
681 if (VT != MVT::Vector) {
682 MVT::ValueType DestVT = TLI.getTypeToTransformTo(VT);
684 N = DAG.getCopyFromReg(DAG.getEntryNode(), InReg, DestVT);
686 // Source must be expanded. This input value is actually coming from the
687 // register pair VMI->second and VMI->second+1.
688 N = DAG.getNode(ISD::BUILD_PAIR, VT, N,
689 DAG.getCopyFromReg(DAG.getEntryNode(), InReg+1, DestVT));
690 } else if (DestVT > VT) { // Promotion case
691 if (MVT::isFloatingPoint(VT))
692 N = DAG.getNode(ISD::FP_ROUND, VT, N);
694 N = DAG.getNode(ISD::TRUNCATE, VT, N);
697 // Otherwise, if this is a vector, make it available as a generic vector
699 MVT::ValueType PTyElementVT, PTyLegalElementVT;
700 const PackedType *PTy = cast<PackedType>(VTy);
701 unsigned NE = TLI.getPackedTypeBreakdown(PTy, PTyElementVT,
704 // Build a VBUILD_VECTOR with the input registers.
705 SmallVector<SDOperand, 8> Ops;
706 if (PTyElementVT == PTyLegalElementVT) {
707 // If the value types are legal, just VBUILD the CopyFromReg nodes.
708 for (unsigned i = 0; i != NE; ++i)
709 Ops.push_back(DAG.getCopyFromReg(DAG.getEntryNode(), InReg++,
711 } else if (PTyElementVT < PTyLegalElementVT) {
712 // If the register was promoted, use TRUNCATE of FP_ROUND as appropriate.
713 for (unsigned i = 0; i != NE; ++i) {
714 SDOperand Op = DAG.getCopyFromReg(DAG.getEntryNode(), InReg++,
716 if (MVT::isFloatingPoint(PTyElementVT))
717 Op = DAG.getNode(ISD::FP_ROUND, PTyElementVT, Op);
719 Op = DAG.getNode(ISD::TRUNCATE, PTyElementVT, Op);
723 // If the register was expanded, use BUILD_PAIR.
724 assert((NE & 1) == 0 && "Must expand into a multiple of 2 elements!");
725 for (unsigned i = 0; i != NE/2; ++i) {
726 SDOperand Op0 = DAG.getCopyFromReg(DAG.getEntryNode(), InReg++,
728 SDOperand Op1 = DAG.getCopyFromReg(DAG.getEntryNode(), InReg++,
730 Ops.push_back(DAG.getNode(ISD::BUILD_PAIR, VT, Op0, Op1));
734 Ops.push_back(DAG.getConstant(NE, MVT::i32));
735 Ops.push_back(DAG.getValueType(PTyLegalElementVT));
736 N = DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, &Ops[0], Ops.size());
738 // Finally, use a VBIT_CONVERT to make this available as the appropriate
740 N = DAG.getNode(ISD::VBIT_CONVERT, MVT::Vector, N,
741 DAG.getConstant(PTy->getNumElements(),
743 DAG.getValueType(TLI.getValueType(PTy->getElementType())));
750 void SelectionDAGLowering::visitRet(ReturnInst &I) {
751 if (I.getNumOperands() == 0) {
752 DAG.setRoot(DAG.getNode(ISD::RET, MVT::Other, getRoot()));
755 SmallVector<SDOperand, 8> NewValues;
756 NewValues.push_back(getRoot());
757 for (unsigned i = 0, e = I.getNumOperands(); i != e; ++i) {
758 SDOperand RetOp = getValue(I.getOperand(i));
759 bool isSigned = I.getOperand(i)->getType()->isSigned();
761 // If this is an integer return value, we need to promote it ourselves to
762 // the full width of a register, since LegalizeOp will use ANY_EXTEND rather
764 // FIXME: C calling convention requires the return type to be promoted to
765 // at least 32-bit. But this is not necessary for non-C calling conventions.
766 if (MVT::isInteger(RetOp.getValueType()) &&
767 RetOp.getValueType() < MVT::i64) {
768 MVT::ValueType TmpVT;
769 if (TLI.getTypeAction(MVT::i32) == TargetLowering::Promote)
770 TmpVT = TLI.getTypeToTransformTo(MVT::i32);
775 RetOp = DAG.getNode(ISD::SIGN_EXTEND, TmpVT, RetOp);
777 RetOp = DAG.getNode(ISD::ZERO_EXTEND, TmpVT, RetOp);
779 NewValues.push_back(RetOp);
780 NewValues.push_back(DAG.getConstant(isSigned, MVT::i32));
782 DAG.setRoot(DAG.getNode(ISD::RET, MVT::Other,
783 &NewValues[0], NewValues.size()));
786 /// ExportFromCurrentBlock - If this condition isn't known to be exported from
787 /// the current basic block, add it to ValueMap now so that we'll get a
789 void SelectionDAGLowering::ExportFromCurrentBlock(Value *V) {
790 // No need to export constants.
791 if (!isa<Instruction>(V) && !isa<Argument>(V)) return;
794 if (FuncInfo.isExportedInst(V)) return;
796 unsigned Reg = FuncInfo.InitializeRegForValue(V);
797 PendingLoads.push_back(CopyValueToVirtualRegister(V, Reg));
800 bool SelectionDAGLowering::isExportableFromCurrentBlock(Value *V,
801 const BasicBlock *FromBB) {
802 // The operands of the setcc have to be in this block. We don't know
803 // how to export them from some other block.
804 if (Instruction *VI = dyn_cast<Instruction>(V)) {
805 // Can export from current BB.
806 if (VI->getParent() == FromBB)
809 // Is already exported, noop.
810 return FuncInfo.isExportedInst(V);
813 // If this is an argument, we can export it if the BB is the entry block or
814 // if it is already exported.
815 if (isa<Argument>(V)) {
816 if (FromBB == &FromBB->getParent()->getEntryBlock())
819 // Otherwise, can only export this if it is already exported.
820 return FuncInfo.isExportedInst(V);
823 // Otherwise, constants can always be exported.
827 static bool InBlock(const Value *V, const BasicBlock *BB) {
828 if (const Instruction *I = dyn_cast<Instruction>(V))
829 return I->getParent() == BB;
833 /// FindMergedConditions - If Cond is an expression like
834 void SelectionDAGLowering::FindMergedConditions(Value *Cond,
835 MachineBasicBlock *TBB,
836 MachineBasicBlock *FBB,
837 MachineBasicBlock *CurBB,
839 // If this node is not part of the or/and tree, emit it as a branch.
840 BinaryOperator *BOp = dyn_cast<BinaryOperator>(Cond);
842 if (!BOp || (unsigned)BOp->getOpcode() != Opc || !BOp->hasOneUse() ||
843 BOp->getParent() != CurBB->getBasicBlock() ||
844 !InBlock(BOp->getOperand(0), CurBB->getBasicBlock()) ||
845 !InBlock(BOp->getOperand(1), CurBB->getBasicBlock())) {
846 const BasicBlock *BB = CurBB->getBasicBlock();
848 if (IntrinsicInst *II = dyn_cast<IntrinsicInst>(Cond))
849 if ((II->getIntrinsicID() == Intrinsic::isunordered_f32 ||
850 II->getIntrinsicID() == Intrinsic::isunordered_f64) &&
851 // The operands of the setcc have to be in this block. We don't know
852 // how to export them from some other block. If this is the first
853 // block of the sequence, no exporting is needed.
855 (isExportableFromCurrentBlock(II->getOperand(1), BB) &&
856 isExportableFromCurrentBlock(II->getOperand(2), BB)))) {
857 SelectionDAGISel::CaseBlock CB(ISD::SETUO, II->getOperand(1),
858 II->getOperand(2), TBB, FBB, CurBB);
859 SwitchCases.push_back(CB);
864 // If the leaf of the tree is a setcond inst, merge the condition into the
866 if (BOp && isa<SetCondInst>(BOp) &&
867 // The operands of the setcc have to be in this block. We don't know
868 // how to export them from some other block. If this is the first block
869 // of the sequence, no exporting is needed.
871 (isExportableFromCurrentBlock(BOp->getOperand(0), BB) &&
872 isExportableFromCurrentBlock(BOp->getOperand(1), BB)))) {
873 ISD::CondCode SignCond, UnsCond, FPCond, Condition;
874 switch (BOp->getOpcode()) {
875 default: assert(0 && "Unknown setcc opcode!");
876 case Instruction::SetEQ:
877 SignCond = ISD::SETEQ;
878 UnsCond = ISD::SETEQ;
879 FPCond = ISD::SETOEQ;
881 case Instruction::SetNE:
882 SignCond = ISD::SETNE;
883 UnsCond = ISD::SETNE;
884 FPCond = ISD::SETUNE;
886 case Instruction::SetLE:
887 SignCond = ISD::SETLE;
888 UnsCond = ISD::SETULE;
889 FPCond = ISD::SETOLE;
891 case Instruction::SetGE:
892 SignCond = ISD::SETGE;
893 UnsCond = ISD::SETUGE;
894 FPCond = ISD::SETOGE;
896 case Instruction::SetLT:
897 SignCond = ISD::SETLT;
898 UnsCond = ISD::SETULT;
899 FPCond = ISD::SETOLT;
901 case Instruction::SetGT:
902 SignCond = ISD::SETGT;
903 UnsCond = ISD::SETUGT;
904 FPCond = ISD::SETOGT;
908 const Type *OpType = BOp->getOperand(0)->getType();
909 if (const PackedType *PTy = dyn_cast<PackedType>(OpType))
910 OpType = PTy->getElementType();
912 if (!FiniteOnlyFPMath() && OpType->isFloatingPoint())
914 else if (OpType->isUnsigned())
917 Condition = SignCond;
919 SelectionDAGISel::CaseBlock CB(Condition, BOp->getOperand(0),
920 BOp->getOperand(1), TBB, FBB, CurBB);
921 SwitchCases.push_back(CB);
925 // Create a CaseBlock record representing this branch.
926 SelectionDAGISel::CaseBlock CB(ISD::SETEQ, Cond, ConstantBool::getTrue(),
928 SwitchCases.push_back(CB);
933 // Create TmpBB after CurBB.
934 MachineFunction::iterator BBI = CurBB;
935 MachineBasicBlock *TmpBB = new MachineBasicBlock(CurBB->getBasicBlock());
936 CurBB->getParent()->getBasicBlockList().insert(++BBI, TmpBB);
938 if (Opc == Instruction::Or) {
947 // Emit the LHS condition.
948 FindMergedConditions(BOp->getOperand(0), TBB, TmpBB, CurBB, Opc);
950 // Emit the RHS condition into TmpBB.
951 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, Opc);
953 assert(Opc == Instruction::And && "Unknown merge op!");
961 // This requires creation of TmpBB after CurBB.
963 // Emit the LHS condition.
964 FindMergedConditions(BOp->getOperand(0), TmpBB, FBB, CurBB, Opc);
966 // Emit the RHS condition into TmpBB.
967 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, Opc);
971 /// If the set of cases should be emitted as a series of branches, return true.
972 /// If we should emit this as a bunch of and/or'd together conditions, return
975 ShouldEmitAsBranches(const std::vector<SelectionDAGISel::CaseBlock> &Cases) {
976 if (Cases.size() != 2) return true;
978 // If this is two comparisons of the same values or'd or and'd together, they
979 // will get folded into a single comparison, so don't emit two blocks.
980 if ((Cases[0].CmpLHS == Cases[1].CmpLHS &&
981 Cases[0].CmpRHS == Cases[1].CmpRHS) ||
982 (Cases[0].CmpRHS == Cases[1].CmpLHS &&
983 Cases[0].CmpLHS == Cases[1].CmpRHS)) {
990 void SelectionDAGLowering::visitBr(BranchInst &I) {
991 // Update machine-CFG edges.
992 MachineBasicBlock *Succ0MBB = FuncInfo.MBBMap[I.getSuccessor(0)];
994 // Figure out which block is immediately after the current one.
995 MachineBasicBlock *NextBlock = 0;
996 MachineFunction::iterator BBI = CurMBB;
997 if (++BBI != CurMBB->getParent()->end())
1000 if (I.isUnconditional()) {
1001 // If this is not a fall-through branch, emit the branch.
1002 if (Succ0MBB != NextBlock)
1003 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, getRoot(),
1004 DAG.getBasicBlock(Succ0MBB)));
1006 // Update machine-CFG edges.
1007 CurMBB->addSuccessor(Succ0MBB);
1012 // If this condition is one of the special cases we handle, do special stuff
1014 Value *CondVal = I.getCondition();
1015 MachineBasicBlock *Succ1MBB = FuncInfo.MBBMap[I.getSuccessor(1)];
1017 // If this is a series of conditions that are or'd or and'd together, emit
1018 // this as a sequence of branches instead of setcc's with and/or operations.
1019 // For example, instead of something like:
1032 if (BinaryOperator *BOp = dyn_cast<BinaryOperator>(CondVal)) {
1033 if (BOp->hasOneUse() &&
1034 (BOp->getOpcode() == Instruction::And ||
1035 BOp->getOpcode() == Instruction::Or)) {
1036 FindMergedConditions(BOp, Succ0MBB, Succ1MBB, CurMBB, BOp->getOpcode());
1037 // If the compares in later blocks need to use values not currently
1038 // exported from this block, export them now. This block should always
1039 // be the first entry.
1040 assert(SwitchCases[0].ThisBB == CurMBB && "Unexpected lowering!");
1042 // Allow some cases to be rejected.
1043 if (ShouldEmitAsBranches(SwitchCases)) {
1044 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i) {
1045 ExportFromCurrentBlock(SwitchCases[i].CmpLHS);
1046 ExportFromCurrentBlock(SwitchCases[i].CmpRHS);
1049 // Emit the branch for this block.
1050 visitSwitchCase(SwitchCases[0]);
1051 SwitchCases.erase(SwitchCases.begin());
1055 // Okay, we decided not to do this, remove any inserted MBB's and clear
1057 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i)
1058 CurMBB->getParent()->getBasicBlockList().erase(SwitchCases[i].ThisBB);
1060 SwitchCases.clear();
1064 // Create a CaseBlock record representing this branch.
1065 SelectionDAGISel::CaseBlock CB(ISD::SETEQ, CondVal, ConstantBool::getTrue(),
1066 Succ0MBB, Succ1MBB, CurMBB);
1067 // Use visitSwitchCase to actually insert the fast branch sequence for this
1069 visitSwitchCase(CB);
1072 /// visitSwitchCase - Emits the necessary code to represent a single node in
1073 /// the binary search tree resulting from lowering a switch instruction.
1074 void SelectionDAGLowering::visitSwitchCase(SelectionDAGISel::CaseBlock &CB) {
1076 SDOperand CondLHS = getValue(CB.CmpLHS);
1078 // Build the setcc now, fold "(X == true)" to X and "(X == false)" to !X to
1079 // handle common cases produced by branch lowering.
1080 if (CB.CmpRHS == ConstantBool::getTrue() && CB.CC == ISD::SETEQ)
1082 else if (CB.CmpRHS == ConstantBool::getFalse() && CB.CC == ISD::SETEQ) {
1083 SDOperand True = DAG.getConstant(1, CondLHS.getValueType());
1084 Cond = DAG.getNode(ISD::XOR, CondLHS.getValueType(), CondLHS, True);
1086 Cond = DAG.getSetCC(MVT::i1, CondLHS, getValue(CB.CmpRHS), CB.CC);
1088 // Set NextBlock to be the MBB immediately after the current one, if any.
1089 // This is used to avoid emitting unnecessary branches to the next block.
1090 MachineBasicBlock *NextBlock = 0;
1091 MachineFunction::iterator BBI = CurMBB;
1092 if (++BBI != CurMBB->getParent()->end())
1095 // If the lhs block is the next block, invert the condition so that we can
1096 // fall through to the lhs instead of the rhs block.
1097 if (CB.TrueBB == NextBlock) {
1098 std::swap(CB.TrueBB, CB.FalseBB);
1099 SDOperand True = DAG.getConstant(1, Cond.getValueType());
1100 Cond = DAG.getNode(ISD::XOR, Cond.getValueType(), Cond, True);
1102 SDOperand BrCond = DAG.getNode(ISD::BRCOND, MVT::Other, getRoot(), Cond,
1103 DAG.getBasicBlock(CB.TrueBB));
1104 if (CB.FalseBB == NextBlock)
1105 DAG.setRoot(BrCond);
1107 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, BrCond,
1108 DAG.getBasicBlock(CB.FalseBB)));
1109 // Update successor info
1110 CurMBB->addSuccessor(CB.TrueBB);
1111 CurMBB->addSuccessor(CB.FalseBB);
1114 void SelectionDAGLowering::visitJumpTable(SelectionDAGISel::JumpTable &JT) {
1115 // Emit the code for the jump table
1116 MVT::ValueType PTy = TLI.getPointerTy();
1117 SDOperand Index = DAG.getCopyFromReg(getRoot(), JT.Reg, PTy);
1118 SDOperand Table = DAG.getJumpTable(JT.JTI, PTy);
1119 DAG.setRoot(DAG.getNode(ISD::BR_JT, MVT::Other, Index.getValue(1),
1124 void SelectionDAGLowering::visitSwitch(SwitchInst &I) {
1125 // Figure out which block is immediately after the current one.
1126 MachineBasicBlock *NextBlock = 0;
1127 MachineFunction::iterator BBI = CurMBB;
1129 if (++BBI != CurMBB->getParent()->end())
1132 MachineBasicBlock *Default = FuncInfo.MBBMap[I.getDefaultDest()];
1134 // If there is only the default destination, branch to it if it is not the
1135 // next basic block. Otherwise, just fall through.
1136 if (I.getNumOperands() == 2) {
1137 // Update machine-CFG edges.
1139 // If this is not a fall-through branch, emit the branch.
1140 if (Default != NextBlock)
1141 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, getRoot(),
1142 DAG.getBasicBlock(Default)));
1144 CurMBB->addSuccessor(Default);
1148 // If there are any non-default case statements, create a vector of Cases
1149 // representing each one, and sort the vector so that we can efficiently
1150 // create a binary search tree from them.
1151 std::vector<Case> Cases;
1153 for (unsigned i = 1; i < I.getNumSuccessors(); ++i) {
1154 MachineBasicBlock *SMBB = FuncInfo.MBBMap[I.getSuccessor(i)];
1155 Cases.push_back(Case(I.getSuccessorValue(i), SMBB));
1158 std::sort(Cases.begin(), Cases.end(), CaseCmp());
1160 // Get the Value to be switched on and default basic blocks, which will be
1161 // inserted into CaseBlock records, representing basic blocks in the binary
1163 Value *SV = I.getOperand(0);
1165 // Get the MachineFunction which holds the current MBB. This is used during
1166 // emission of jump tables, and when inserting any additional MBBs necessary
1167 // to represent the switch.
1168 MachineFunction *CurMF = CurMBB->getParent();
1169 const BasicBlock *LLVMBB = CurMBB->getBasicBlock();
1171 // If the switch has few cases (two or less) emit a series of specific
1173 if (Cases.size() < 3) {
1174 // TODO: If any two of the cases has the same destination, and if one value
1175 // is the same as the other, but has one bit unset that the other has set,
1176 // use bit manipulation to do two compares at once. For example:
1177 // "if (X == 6 || X == 4)" -> "if ((X|2) == 6)"
1179 // Rearrange the case blocks so that the last one falls through if possible.
1180 if (NextBlock && Default != NextBlock && Cases.back().second != NextBlock) {
1181 // The last case block won't fall through into 'NextBlock' if we emit the
1182 // branches in this order. See if rearranging a case value would help.
1183 for (unsigned i = 0, e = Cases.size()-1; i != e; ++i) {
1184 if (Cases[i].second == NextBlock) {
1185 std::swap(Cases[i], Cases.back());
1191 // Create a CaseBlock record representing a conditional branch to
1192 // the Case's target mbb if the value being switched on SV is equal
1194 MachineBasicBlock *CurBlock = CurMBB;
1195 for (unsigned i = 0, e = Cases.size(); i != e; ++i) {
1196 MachineBasicBlock *FallThrough;
1198 FallThrough = new MachineBasicBlock(CurMBB->getBasicBlock());
1199 CurMF->getBasicBlockList().insert(BBI, FallThrough);
1201 // If the last case doesn't match, go to the default block.
1202 FallThrough = Default;
1205 SelectionDAGISel::CaseBlock CB(ISD::SETEQ, SV, Cases[i].first,
1206 Cases[i].second, FallThrough, CurBlock);
1208 // If emitting the first comparison, just call visitSwitchCase to emit the
1209 // code into the current block. Otherwise, push the CaseBlock onto the
1210 // vector to be later processed by SDISel, and insert the node's MBB
1211 // before the next MBB.
1212 if (CurBlock == CurMBB)
1213 visitSwitchCase(CB);
1215 SwitchCases.push_back(CB);
1217 CurBlock = FallThrough;
1222 // If the switch has more than 5 blocks, and at least 31.25% dense, and the
1223 // target supports indirect branches, then emit a jump table rather than
1224 // lowering the switch to a binary tree of conditional branches.
1225 if ((TLI.isOperationLegal(ISD::BR_JT, MVT::Other) ||
1226 TLI.isOperationLegal(ISD::BRIND, MVT::Other)) &&
1228 uint64_t First =cast<ConstantIntegral>(Cases.front().first)->getZExtValue();
1229 uint64_t Last = cast<ConstantIntegral>(Cases.back().first)->getZExtValue();
1230 double Density = (double)Cases.size() / (double)((Last - First) + 1ULL);
1232 if (Density >= 0.3125) {
1233 // Create a new basic block to hold the code for loading the address
1234 // of the jump table, and jumping to it. Update successor information;
1235 // we will either branch to the default case for the switch, or the jump
1237 MachineBasicBlock *JumpTableBB = new MachineBasicBlock(LLVMBB);
1238 CurMF->getBasicBlockList().insert(BBI, JumpTableBB);
1239 CurMBB->addSuccessor(Default);
1240 CurMBB->addSuccessor(JumpTableBB);
1242 // Subtract the lowest switch case value from the value being switched on
1243 // and conditional branch to default mbb if the result is greater than the
1244 // difference between smallest and largest cases.
1245 SDOperand SwitchOp = getValue(SV);
1246 MVT::ValueType VT = SwitchOp.getValueType();
1247 SDOperand SUB = DAG.getNode(ISD::SUB, VT, SwitchOp,
1248 DAG.getConstant(First, VT));
1250 // The SDNode we just created, which holds the value being switched on
1251 // minus the the smallest case value, needs to be copied to a virtual
1252 // register so it can be used as an index into the jump table in a
1253 // subsequent basic block. This value may be smaller or larger than the
1254 // target's pointer type, and therefore require extension or truncating.
1255 if (VT > TLI.getPointerTy())
1256 SwitchOp = DAG.getNode(ISD::TRUNCATE, TLI.getPointerTy(), SUB);
1258 SwitchOp = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(), SUB);
1260 unsigned JumpTableReg = FuncInfo.MakeReg(TLI.getPointerTy());
1261 SDOperand CopyTo = DAG.getCopyToReg(getRoot(), JumpTableReg, SwitchOp);
1263 // Emit the range check for the jump table, and branch to the default
1264 // block for the switch statement if the value being switched on exceeds
1265 // the largest case in the switch.
1266 SDOperand CMP = DAG.getSetCC(TLI.getSetCCResultTy(), SUB,
1267 DAG.getConstant(Last-First,VT), ISD::SETUGT);
1268 DAG.setRoot(DAG.getNode(ISD::BRCOND, MVT::Other, CopyTo, CMP,
1269 DAG.getBasicBlock(Default)));
1271 // Build a vector of destination BBs, corresponding to each target
1272 // of the jump table. If the value of the jump table slot corresponds to
1273 // a case statement, push the case's BB onto the vector, otherwise, push
1275 std::vector<MachineBasicBlock*> DestBBs;
1276 uint64_t TEI = First;
1277 for (CaseItr ii = Cases.begin(), ee = Cases.end(); ii != ee; ++TEI)
1278 if (cast<ConstantIntegral>(ii->first)->getZExtValue() == TEI) {
1279 DestBBs.push_back(ii->second);
1282 DestBBs.push_back(Default);
1285 // Update successor info. Add one edge to each unique successor.
1286 // Vector bool would be better, but vector<bool> is really slow.
1287 std::vector<unsigned char> SuccsHandled;
1288 SuccsHandled.resize(CurMBB->getParent()->getNumBlockIDs());
1290 for (std::vector<MachineBasicBlock*>::iterator I = DestBBs.begin(),
1291 E = DestBBs.end(); I != E; ++I) {
1292 if (!SuccsHandled[(*I)->getNumber()]) {
1293 SuccsHandled[(*I)->getNumber()] = true;
1294 JumpTableBB->addSuccessor(*I);
1298 // Create a jump table index for this jump table, or return an existing
1300 unsigned JTI = CurMF->getJumpTableInfo()->getJumpTableIndex(DestBBs);
1302 // Set the jump table information so that we can codegen it as a second
1303 // MachineBasicBlock
1304 JT.Reg = JumpTableReg;
1306 JT.MBB = JumpTableBB;
1307 JT.Default = Default;
1312 // Push the initial CaseRec onto the worklist
1313 std::vector<CaseRec> CaseVec;
1314 CaseVec.push_back(CaseRec(CurMBB,0,0,CaseRange(Cases.begin(),Cases.end())));
1316 while (!CaseVec.empty()) {
1317 // Grab a record representing a case range to process off the worklist
1318 CaseRec CR = CaseVec.back();
1321 // Size is the number of Cases represented by this range. If Size is 1,
1322 // then we are processing a leaf of the binary search tree. Otherwise,
1323 // we need to pick a pivot, and push left and right ranges onto the
1325 unsigned Size = CR.Range.second - CR.Range.first;
1328 // Create a CaseBlock record representing a conditional branch to
1329 // the Case's target mbb if the value being switched on SV is equal
1330 // to C. Otherwise, branch to default.
1331 Constant *C = CR.Range.first->first;
1332 MachineBasicBlock *Target = CR.Range.first->second;
1333 SelectionDAGISel::CaseBlock CB(ISD::SETEQ, SV, C, Target, Default,
1336 // If the MBB representing the leaf node is the current MBB, then just
1337 // call visitSwitchCase to emit the code into the current block.
1338 // Otherwise, push the CaseBlock onto the vector to be later processed
1339 // by SDISel, and insert the node's MBB before the next MBB.
1340 if (CR.CaseBB == CurMBB)
1341 visitSwitchCase(CB);
1343 SwitchCases.push_back(CB);
1345 // split case range at pivot
1346 CaseItr Pivot = CR.Range.first + (Size / 2);
1347 CaseRange LHSR(CR.Range.first, Pivot);
1348 CaseRange RHSR(Pivot, CR.Range.second);
1349 Constant *C = Pivot->first;
1350 MachineBasicBlock *FalseBB = 0, *TrueBB = 0;
1352 // We know that we branch to the LHS if the Value being switched on is
1353 // less than the Pivot value, C. We use this to optimize our binary
1354 // tree a bit, by recognizing that if SV is greater than or equal to the
1355 // LHS's Case Value, and that Case Value is exactly one less than the
1356 // Pivot's Value, then we can branch directly to the LHS's Target,
1357 // rather than creating a leaf node for it.
1358 if ((LHSR.second - LHSR.first) == 1 &&
1359 LHSR.first->first == CR.GE &&
1360 cast<ConstantIntegral>(C)->getZExtValue() ==
1361 (cast<ConstantIntegral>(CR.GE)->getZExtValue() + 1ULL)) {
1362 TrueBB = LHSR.first->second;
1364 TrueBB = new MachineBasicBlock(LLVMBB);
1365 CurMF->getBasicBlockList().insert(BBI, TrueBB);
1366 CaseVec.push_back(CaseRec(TrueBB, C, CR.GE, LHSR));
1369 // Similar to the optimization above, if the Value being switched on is
1370 // known to be less than the Constant CR.LT, and the current Case Value
1371 // is CR.LT - 1, then we can branch directly to the target block for
1372 // the current Case Value, rather than emitting a RHS leaf node for it.
1373 if ((RHSR.second - RHSR.first) == 1 && CR.LT &&
1374 cast<ConstantIntegral>(RHSR.first->first)->getZExtValue() ==
1375 (cast<ConstantIntegral>(CR.LT)->getZExtValue() - 1ULL)) {
1376 FalseBB = RHSR.first->second;
1378 FalseBB = new MachineBasicBlock(LLVMBB);
1379 CurMF->getBasicBlockList().insert(BBI, FalseBB);
1380 CaseVec.push_back(CaseRec(FalseBB,CR.LT,C,RHSR));
1383 // Create a CaseBlock record representing a conditional branch to
1384 // the LHS node if the value being switched on SV is less than C.
1385 // Otherwise, branch to LHS.
1386 ISD::CondCode CC = C->getType()->isSigned() ? ISD::SETLT : ISD::SETULT;
1387 SelectionDAGISel::CaseBlock CB(CC, SV, C, TrueBB, FalseBB, CR.CaseBB);
1389 if (CR.CaseBB == CurMBB)
1390 visitSwitchCase(CB);
1392 SwitchCases.push_back(CB);
1397 void SelectionDAGLowering::visitSub(User &I) {
1398 // -0.0 - X --> fneg
1399 if (I.getType()->isFloatingPoint()) {
1400 if (ConstantFP *CFP = dyn_cast<ConstantFP>(I.getOperand(0)))
1401 if (CFP->isExactlyValue(-0.0)) {
1402 SDOperand Op2 = getValue(I.getOperand(1));
1403 setValue(&I, DAG.getNode(ISD::FNEG, Op2.getValueType(), Op2));
1406 visitFPBinary(I, ISD::FSUB, ISD::VSUB);
1408 visitIntBinary(I, ISD::SUB, ISD::VSUB);
1412 SelectionDAGLowering::visitIntBinary(User &I, unsigned IntOp, unsigned VecOp) {
1413 const Type *Ty = I.getType();
1414 SDOperand Op1 = getValue(I.getOperand(0));
1415 SDOperand Op2 = getValue(I.getOperand(1));
1417 if (const PackedType *PTy = dyn_cast<PackedType>(Ty)) {
1418 SDOperand Num = DAG.getConstant(PTy->getNumElements(), MVT::i32);
1419 SDOperand Typ = DAG.getValueType(TLI.getValueType(PTy->getElementType()));
1420 setValue(&I, DAG.getNode(VecOp, MVT::Vector, Op1, Op2, Num, Typ));
1422 setValue(&I, DAG.getNode(IntOp, Op1.getValueType(), Op1, Op2));
1427 SelectionDAGLowering::visitFPBinary(User &I, unsigned FPOp, unsigned VecOp) {
1428 const Type *Ty = I.getType();
1429 SDOperand Op1 = getValue(I.getOperand(0));
1430 SDOperand Op2 = getValue(I.getOperand(1));
1432 if (const PackedType *PTy = dyn_cast<PackedType>(Ty)) {
1433 SDOperand Num = DAG.getConstant(PTy->getNumElements(), MVT::i32);
1434 SDOperand Typ = DAG.getValueType(TLI.getValueType(PTy->getElementType()));
1435 setValue(&I, DAG.getNode(VecOp, MVT::Vector, Op1, Op2, Num, Typ));
1437 setValue(&I, DAG.getNode(FPOp, Op1.getValueType(), Op1, Op2));
1441 void SelectionDAGLowering::visitShift(User &I, unsigned Opcode) {
1442 SDOperand Op1 = getValue(I.getOperand(0));
1443 SDOperand Op2 = getValue(I.getOperand(1));
1445 Op2 = DAG.getNode(ISD::ANY_EXTEND, TLI.getShiftAmountTy(), Op2);
1447 setValue(&I, DAG.getNode(Opcode, Op1.getValueType(), Op1, Op2));
1450 void SelectionDAGLowering::visitSetCC(User &I,ISD::CondCode SignedOpcode,
1451 ISD::CondCode UnsignedOpcode,
1452 ISD::CondCode FPOpcode) {
1453 SDOperand Op1 = getValue(I.getOperand(0));
1454 SDOperand Op2 = getValue(I.getOperand(1));
1455 ISD::CondCode Opcode = SignedOpcode;
1456 if (!FiniteOnlyFPMath() && I.getOperand(0)->getType()->isFloatingPoint())
1458 else if (I.getOperand(0)->getType()->isUnsigned())
1459 Opcode = UnsignedOpcode;
1460 setValue(&I, DAG.getSetCC(MVT::i1, Op1, Op2, Opcode));
1463 void SelectionDAGLowering::visitSelect(User &I) {
1464 SDOperand Cond = getValue(I.getOperand(0));
1465 SDOperand TrueVal = getValue(I.getOperand(1));
1466 SDOperand FalseVal = getValue(I.getOperand(2));
1467 if (!isa<PackedType>(I.getType())) {
1468 setValue(&I, DAG.getNode(ISD::SELECT, TrueVal.getValueType(), Cond,
1469 TrueVal, FalseVal));
1471 setValue(&I, DAG.getNode(ISD::VSELECT, MVT::Vector, Cond, TrueVal, FalseVal,
1472 *(TrueVal.Val->op_end()-2),
1473 *(TrueVal.Val->op_end()-1)));
1477 void SelectionDAGLowering::visitCast(User &I) {
1478 SDOperand N = getValue(I.getOperand(0));
1479 MVT::ValueType SrcVT = N.getValueType();
1480 MVT::ValueType DestVT = TLI.getValueType(I.getType());
1482 if (DestVT == MVT::Vector) {
1483 // This is a cast to a vector from something else. This is always a bit
1484 // convert. Get information about the input vector.
1485 const PackedType *DestTy = cast<PackedType>(I.getType());
1486 MVT::ValueType EltVT = TLI.getValueType(DestTy->getElementType());
1487 setValue(&I, DAG.getNode(ISD::VBIT_CONVERT, DestVT, N,
1488 DAG.getConstant(DestTy->getNumElements(),MVT::i32),
1489 DAG.getValueType(EltVT)));
1490 } else if (SrcVT == DestVT) {
1491 setValue(&I, N); // noop cast.
1492 } else if (DestVT == MVT::i1) {
1493 // Cast to bool is a comparison against zero, not truncation to zero.
1494 SDOperand Zero = isInteger(SrcVT) ? DAG.getConstant(0, N.getValueType()) :
1495 DAG.getConstantFP(0.0, N.getValueType());
1496 setValue(&I, DAG.getSetCC(MVT::i1, N, Zero, ISD::SETNE));
1497 } else if (isInteger(SrcVT)) {
1498 if (isInteger(DestVT)) { // Int -> Int cast
1499 if (DestVT < SrcVT) // Truncating cast?
1500 setValue(&I, DAG.getNode(ISD::TRUNCATE, DestVT, N));
1501 else if (I.getOperand(0)->getType()->isSigned())
1502 setValue(&I, DAG.getNode(ISD::SIGN_EXTEND, DestVT, N));
1504 setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, DestVT, N));
1505 } else if (isFloatingPoint(DestVT)) { // Int -> FP cast
1506 if (I.getOperand(0)->getType()->isSigned())
1507 setValue(&I, DAG.getNode(ISD::SINT_TO_FP, DestVT, N));
1509 setValue(&I, DAG.getNode(ISD::UINT_TO_FP, DestVT, N));
1511 assert(0 && "Unknown cast!");
1513 } else if (isFloatingPoint(SrcVT)) {
1514 if (isFloatingPoint(DestVT)) { // FP -> FP cast
1515 if (DestVT < SrcVT) // Rounding cast?
1516 setValue(&I, DAG.getNode(ISD::FP_ROUND, DestVT, N));
1518 setValue(&I, DAG.getNode(ISD::FP_EXTEND, DestVT, N));
1519 } else if (isInteger(DestVT)) { // FP -> Int cast.
1520 if (I.getType()->isSigned())
1521 setValue(&I, DAG.getNode(ISD::FP_TO_SINT, DestVT, N));
1523 setValue(&I, DAG.getNode(ISD::FP_TO_UINT, DestVT, N));
1525 assert(0 && "Unknown cast!");
1528 assert(SrcVT == MVT::Vector && "Unknown cast!");
1529 assert(DestVT != MVT::Vector && "Casts to vector already handled!");
1530 // This is a cast from a vector to something else. This is always a bit
1531 // convert. Get information about the input vector.
1532 setValue(&I, DAG.getNode(ISD::VBIT_CONVERT, DestVT, N));
1536 void SelectionDAGLowering::visitInsertElement(User &I) {
1537 SDOperand InVec = getValue(I.getOperand(0));
1538 SDOperand InVal = getValue(I.getOperand(1));
1539 SDOperand InIdx = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(),
1540 getValue(I.getOperand(2)));
1542 SDOperand Num = *(InVec.Val->op_end()-2);
1543 SDOperand Typ = *(InVec.Val->op_end()-1);
1544 setValue(&I, DAG.getNode(ISD::VINSERT_VECTOR_ELT, MVT::Vector,
1545 InVec, InVal, InIdx, Num, Typ));
1548 void SelectionDAGLowering::visitExtractElement(User &I) {
1549 SDOperand InVec = getValue(I.getOperand(0));
1550 SDOperand InIdx = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(),
1551 getValue(I.getOperand(1)));
1552 SDOperand Typ = *(InVec.Val->op_end()-1);
1553 setValue(&I, DAG.getNode(ISD::VEXTRACT_VECTOR_ELT,
1554 TLI.getValueType(I.getType()), InVec, InIdx));
1557 void SelectionDAGLowering::visitShuffleVector(User &I) {
1558 SDOperand V1 = getValue(I.getOperand(0));
1559 SDOperand V2 = getValue(I.getOperand(1));
1560 SDOperand Mask = getValue(I.getOperand(2));
1562 SDOperand Num = *(V1.Val->op_end()-2);
1563 SDOperand Typ = *(V2.Val->op_end()-1);
1564 setValue(&I, DAG.getNode(ISD::VVECTOR_SHUFFLE, MVT::Vector,
1565 V1, V2, Mask, Num, Typ));
1569 void SelectionDAGLowering::visitGetElementPtr(User &I) {
1570 SDOperand N = getValue(I.getOperand(0));
1571 const Type *Ty = I.getOperand(0)->getType();
1573 for (GetElementPtrInst::op_iterator OI = I.op_begin()+1, E = I.op_end();
1576 if (const StructType *StTy = dyn_cast<StructType>(Ty)) {
1577 unsigned Field = cast<ConstantInt>(Idx)->getZExtValue();
1580 uint64_t Offset = TD->getStructLayout(StTy)->MemberOffsets[Field];
1581 N = DAG.getNode(ISD::ADD, N.getValueType(), N,
1582 getIntPtrConstant(Offset));
1584 Ty = StTy->getElementType(Field);
1586 Ty = cast<SequentialType>(Ty)->getElementType();
1588 // If this is a constant subscript, handle it quickly.
1589 if (ConstantInt *CI = dyn_cast<ConstantInt>(Idx)) {
1590 if (CI->getZExtValue() == 0) continue;
1592 if (CI->getType()->isSigned())
1594 TD->getTypeSize(Ty)*cast<ConstantInt>(CI)->getSExtValue();
1597 TD->getTypeSize(Ty)*cast<ConstantInt>(CI)->getZExtValue();
1598 N = DAG.getNode(ISD::ADD, N.getValueType(), N, getIntPtrConstant(Offs));
1602 // N = N + Idx * ElementSize;
1603 uint64_t ElementSize = TD->getTypeSize(Ty);
1604 SDOperand IdxN = getValue(Idx);
1606 // If the index is smaller or larger than intptr_t, truncate or extend
1608 if (IdxN.getValueType() < N.getValueType()) {
1609 if (Idx->getType()->isSigned())
1610 IdxN = DAG.getNode(ISD::SIGN_EXTEND, N.getValueType(), IdxN);
1612 IdxN = DAG.getNode(ISD::ZERO_EXTEND, N.getValueType(), IdxN);
1613 } else if (IdxN.getValueType() > N.getValueType())
1614 IdxN = DAG.getNode(ISD::TRUNCATE, N.getValueType(), IdxN);
1616 // If this is a multiply by a power of two, turn it into a shl
1617 // immediately. This is a very common case.
1618 if (isPowerOf2_64(ElementSize)) {
1619 unsigned Amt = Log2_64(ElementSize);
1620 IdxN = DAG.getNode(ISD::SHL, N.getValueType(), IdxN,
1621 DAG.getConstant(Amt, TLI.getShiftAmountTy()));
1622 N = DAG.getNode(ISD::ADD, N.getValueType(), N, IdxN);
1626 SDOperand Scale = getIntPtrConstant(ElementSize);
1627 IdxN = DAG.getNode(ISD::MUL, N.getValueType(), IdxN, Scale);
1628 N = DAG.getNode(ISD::ADD, N.getValueType(), N, IdxN);
1634 void SelectionDAGLowering::visitAlloca(AllocaInst &I) {
1635 // If this is a fixed sized alloca in the entry block of the function,
1636 // allocate it statically on the stack.
1637 if (FuncInfo.StaticAllocaMap.count(&I))
1638 return; // getValue will auto-populate this.
1640 const Type *Ty = I.getAllocatedType();
1641 uint64_t TySize = TLI.getTargetData()->getTypeSize(Ty);
1642 unsigned Align = std::max((unsigned)TLI.getTargetData()->getTypeAlignment(Ty),
1645 SDOperand AllocSize = getValue(I.getArraySize());
1646 MVT::ValueType IntPtr = TLI.getPointerTy();
1647 if (IntPtr < AllocSize.getValueType())
1648 AllocSize = DAG.getNode(ISD::TRUNCATE, IntPtr, AllocSize);
1649 else if (IntPtr > AllocSize.getValueType())
1650 AllocSize = DAG.getNode(ISD::ZERO_EXTEND, IntPtr, AllocSize);
1652 AllocSize = DAG.getNode(ISD::MUL, IntPtr, AllocSize,
1653 getIntPtrConstant(TySize));
1655 // Handle alignment. If the requested alignment is less than or equal to the
1656 // stack alignment, ignore it and round the size of the allocation up to the
1657 // stack alignment size. If the size is greater than the stack alignment, we
1658 // note this in the DYNAMIC_STACKALLOC node.
1659 unsigned StackAlign =
1660 TLI.getTargetMachine().getFrameInfo()->getStackAlignment();
1661 if (Align <= StackAlign) {
1663 // Add SA-1 to the size.
1664 AllocSize = DAG.getNode(ISD::ADD, AllocSize.getValueType(), AllocSize,
1665 getIntPtrConstant(StackAlign-1));
1666 // Mask out the low bits for alignment purposes.
1667 AllocSize = DAG.getNode(ISD::AND, AllocSize.getValueType(), AllocSize,
1668 getIntPtrConstant(~(uint64_t)(StackAlign-1)));
1671 SDOperand Ops[] = { getRoot(), AllocSize, getIntPtrConstant(Align) };
1672 const MVT::ValueType *VTs = DAG.getNodeValueTypes(AllocSize.getValueType(),
1674 SDOperand DSA = DAG.getNode(ISD::DYNAMIC_STACKALLOC, VTs, 2, Ops, 3);
1675 DAG.setRoot(setValue(&I, DSA).getValue(1));
1677 // Inform the Frame Information that we have just allocated a variable-sized
1679 CurMBB->getParent()->getFrameInfo()->CreateVariableSizedObject();
1682 void SelectionDAGLowering::visitLoad(LoadInst &I) {
1683 SDOperand Ptr = getValue(I.getOperand(0));
1689 // Do not serialize non-volatile loads against each other.
1690 Root = DAG.getRoot();
1693 setValue(&I, getLoadFrom(I.getType(), Ptr, I.getOperand(0),
1694 Root, I.isVolatile()));
1697 SDOperand SelectionDAGLowering::getLoadFrom(const Type *Ty, SDOperand Ptr,
1698 const Value *SV, SDOperand Root,
1701 if (const PackedType *PTy = dyn_cast<PackedType>(Ty)) {
1702 MVT::ValueType PVT = TLI.getValueType(PTy->getElementType());
1703 L = DAG.getVecLoad(PTy->getNumElements(), PVT, Root, Ptr,
1704 DAG.getSrcValue(SV));
1706 L = DAG.getLoad(TLI.getValueType(Ty), Root, Ptr, SV, isVolatile);
1710 DAG.setRoot(L.getValue(1));
1712 PendingLoads.push_back(L.getValue(1));
1718 void SelectionDAGLowering::visitStore(StoreInst &I) {
1719 Value *SrcV = I.getOperand(0);
1720 SDOperand Src = getValue(SrcV);
1721 SDOperand Ptr = getValue(I.getOperand(1));
1722 DAG.setRoot(DAG.getStore(getRoot(), Src, Ptr, I.getOperand(1),
1726 /// IntrinsicCannotAccessMemory - Return true if the specified intrinsic cannot
1727 /// access memory and has no other side effects at all.
1728 static bool IntrinsicCannotAccessMemory(unsigned IntrinsicID) {
1729 #define GET_NO_MEMORY_INTRINSICS
1730 #include "llvm/Intrinsics.gen"
1731 #undef GET_NO_MEMORY_INTRINSICS
1735 // IntrinsicOnlyReadsMemory - Return true if the specified intrinsic doesn't
1736 // have any side-effects or if it only reads memory.
1737 static bool IntrinsicOnlyReadsMemory(unsigned IntrinsicID) {
1738 #define GET_SIDE_EFFECT_INFO
1739 #include "llvm/Intrinsics.gen"
1740 #undef GET_SIDE_EFFECT_INFO
1744 /// visitTargetIntrinsic - Lower a call of a target intrinsic to an INTRINSIC
1746 void SelectionDAGLowering::visitTargetIntrinsic(CallInst &I,
1747 unsigned Intrinsic) {
1748 bool HasChain = !IntrinsicCannotAccessMemory(Intrinsic);
1749 bool OnlyLoad = HasChain && IntrinsicOnlyReadsMemory(Intrinsic);
1751 // Build the operand list.
1752 SmallVector<SDOperand, 8> Ops;
1753 if (HasChain) { // If this intrinsic has side-effects, chainify it.
1755 // We don't need to serialize loads against other loads.
1756 Ops.push_back(DAG.getRoot());
1758 Ops.push_back(getRoot());
1762 // Add the intrinsic ID as an integer operand.
1763 Ops.push_back(DAG.getConstant(Intrinsic, TLI.getPointerTy()));
1765 // Add all operands of the call to the operand list.
1766 for (unsigned i = 1, e = I.getNumOperands(); i != e; ++i) {
1767 SDOperand Op = getValue(I.getOperand(i));
1769 // If this is a vector type, force it to the right packed type.
1770 if (Op.getValueType() == MVT::Vector) {
1771 const PackedType *OpTy = cast<PackedType>(I.getOperand(i)->getType());
1772 MVT::ValueType EltVT = TLI.getValueType(OpTy->getElementType());
1774 MVT::ValueType VVT = MVT::getVectorType(EltVT, OpTy->getNumElements());
1775 assert(VVT != MVT::Other && "Intrinsic uses a non-legal type?");
1776 Op = DAG.getNode(ISD::VBIT_CONVERT, VVT, Op);
1779 assert(TLI.isTypeLegal(Op.getValueType()) &&
1780 "Intrinsic uses a non-legal type?");
1784 std::vector<MVT::ValueType> VTs;
1785 if (I.getType() != Type::VoidTy) {
1786 MVT::ValueType VT = TLI.getValueType(I.getType());
1787 if (VT == MVT::Vector) {
1788 const PackedType *DestTy = cast<PackedType>(I.getType());
1789 MVT::ValueType EltVT = TLI.getValueType(DestTy->getElementType());
1791 VT = MVT::getVectorType(EltVT, DestTy->getNumElements());
1792 assert(VT != MVT::Other && "Intrinsic uses a non-legal type?");
1795 assert(TLI.isTypeLegal(VT) && "Intrinsic uses a non-legal type?");
1799 VTs.push_back(MVT::Other);
1801 const MVT::ValueType *VTList = DAG.getNodeValueTypes(VTs);
1806 Result = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, VTList, VTs.size(),
1807 &Ops[0], Ops.size());
1808 else if (I.getType() != Type::VoidTy)
1809 Result = DAG.getNode(ISD::INTRINSIC_W_CHAIN, VTList, VTs.size(),
1810 &Ops[0], Ops.size());
1812 Result = DAG.getNode(ISD::INTRINSIC_VOID, VTList, VTs.size(),
1813 &Ops[0], Ops.size());
1816 SDOperand Chain = Result.getValue(Result.Val->getNumValues()-1);
1818 PendingLoads.push_back(Chain);
1822 if (I.getType() != Type::VoidTy) {
1823 if (const PackedType *PTy = dyn_cast<PackedType>(I.getType())) {
1824 MVT::ValueType EVT = TLI.getValueType(PTy->getElementType());
1825 Result = DAG.getNode(ISD::VBIT_CONVERT, MVT::Vector, Result,
1826 DAG.getConstant(PTy->getNumElements(), MVT::i32),
1827 DAG.getValueType(EVT));
1829 setValue(&I, Result);
1833 /// visitIntrinsicCall - Lower the call to the specified intrinsic function. If
1834 /// we want to emit this as a call to a named external function, return the name
1835 /// otherwise lower it and return null.
1837 SelectionDAGLowering::visitIntrinsicCall(CallInst &I, unsigned Intrinsic) {
1838 switch (Intrinsic) {
1840 // By default, turn this into a target intrinsic node.
1841 visitTargetIntrinsic(I, Intrinsic);
1843 case Intrinsic::vastart: visitVAStart(I); return 0;
1844 case Intrinsic::vaend: visitVAEnd(I); return 0;
1845 case Intrinsic::vacopy: visitVACopy(I); return 0;
1846 case Intrinsic::returnaddress: visitFrameReturnAddress(I, false); return 0;
1847 case Intrinsic::frameaddress: visitFrameReturnAddress(I, true); return 0;
1848 case Intrinsic::setjmp:
1849 return "_setjmp"+!TLI.usesUnderscoreSetJmpLongJmp();
1851 case Intrinsic::longjmp:
1852 return "_longjmp"+!TLI.usesUnderscoreSetJmpLongJmp();
1854 case Intrinsic::memcpy_i32:
1855 case Intrinsic::memcpy_i64:
1856 visitMemIntrinsic(I, ISD::MEMCPY);
1858 case Intrinsic::memset_i32:
1859 case Intrinsic::memset_i64:
1860 visitMemIntrinsic(I, ISD::MEMSET);
1862 case Intrinsic::memmove_i32:
1863 case Intrinsic::memmove_i64:
1864 visitMemIntrinsic(I, ISD::MEMMOVE);
1867 case Intrinsic::dbg_stoppoint: {
1868 MachineDebugInfo *DebugInfo = DAG.getMachineDebugInfo();
1869 DbgStopPointInst &SPI = cast<DbgStopPointInst>(I);
1870 if (DebugInfo && SPI.getContext() && DebugInfo->Verify(SPI.getContext())) {
1874 Ops[1] = getValue(SPI.getLineValue());
1875 Ops[2] = getValue(SPI.getColumnValue());
1877 DebugInfoDesc *DD = DebugInfo->getDescFor(SPI.getContext());
1878 assert(DD && "Not a debug information descriptor");
1879 CompileUnitDesc *CompileUnit = cast<CompileUnitDesc>(DD);
1881 Ops[3] = DAG.getString(CompileUnit->getFileName());
1882 Ops[4] = DAG.getString(CompileUnit->getDirectory());
1884 DAG.setRoot(DAG.getNode(ISD::LOCATION, MVT::Other, Ops, 5));
1889 case Intrinsic::dbg_region_start: {
1890 MachineDebugInfo *DebugInfo = DAG.getMachineDebugInfo();
1891 DbgRegionStartInst &RSI = cast<DbgRegionStartInst>(I);
1892 if (DebugInfo && RSI.getContext() && DebugInfo->Verify(RSI.getContext())) {
1893 unsigned LabelID = DebugInfo->RecordRegionStart(RSI.getContext());
1894 DAG.setRoot(DAG.getNode(ISD::DEBUG_LABEL, MVT::Other, getRoot(),
1895 DAG.getConstant(LabelID, MVT::i32)));
1900 case Intrinsic::dbg_region_end: {
1901 MachineDebugInfo *DebugInfo = DAG.getMachineDebugInfo();
1902 DbgRegionEndInst &REI = cast<DbgRegionEndInst>(I);
1903 if (DebugInfo && REI.getContext() && DebugInfo->Verify(REI.getContext())) {
1904 unsigned LabelID = DebugInfo->RecordRegionEnd(REI.getContext());
1905 DAG.setRoot(DAG.getNode(ISD::DEBUG_LABEL, MVT::Other,
1906 getRoot(), DAG.getConstant(LabelID, MVT::i32)));
1911 case Intrinsic::dbg_func_start: {
1912 MachineDebugInfo *DebugInfo = DAG.getMachineDebugInfo();
1913 DbgFuncStartInst &FSI = cast<DbgFuncStartInst>(I);
1914 if (DebugInfo && FSI.getSubprogram() &&
1915 DebugInfo->Verify(FSI.getSubprogram())) {
1916 unsigned LabelID = DebugInfo->RecordRegionStart(FSI.getSubprogram());
1917 DAG.setRoot(DAG.getNode(ISD::DEBUG_LABEL, MVT::Other,
1918 getRoot(), DAG.getConstant(LabelID, MVT::i32)));
1923 case Intrinsic::dbg_declare: {
1924 MachineDebugInfo *DebugInfo = DAG.getMachineDebugInfo();
1925 DbgDeclareInst &DI = cast<DbgDeclareInst>(I);
1926 if (DebugInfo && DI.getVariable() && DebugInfo->Verify(DI.getVariable())) {
1927 SDOperand AddressOp = getValue(DI.getAddress());
1928 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(AddressOp))
1929 DebugInfo->RecordVariable(DI.getVariable(), FI->getIndex());
1935 case Intrinsic::isunordered_f32:
1936 case Intrinsic::isunordered_f64:
1937 setValue(&I, DAG.getSetCC(MVT::i1,getValue(I.getOperand(1)),
1938 getValue(I.getOperand(2)), ISD::SETUO));
1941 case Intrinsic::sqrt_f32:
1942 case Intrinsic::sqrt_f64:
1943 setValue(&I, DAG.getNode(ISD::FSQRT,
1944 getValue(I.getOperand(1)).getValueType(),
1945 getValue(I.getOperand(1))));
1947 case Intrinsic::powi_f32:
1948 case Intrinsic::powi_f64:
1949 setValue(&I, DAG.getNode(ISD::FPOWI,
1950 getValue(I.getOperand(1)).getValueType(),
1951 getValue(I.getOperand(1)),
1952 getValue(I.getOperand(2))));
1954 case Intrinsic::pcmarker: {
1955 SDOperand Tmp = getValue(I.getOperand(1));
1956 DAG.setRoot(DAG.getNode(ISD::PCMARKER, MVT::Other, getRoot(), Tmp));
1959 case Intrinsic::readcyclecounter: {
1960 SDOperand Op = getRoot();
1961 SDOperand Tmp = DAG.getNode(ISD::READCYCLECOUNTER,
1962 DAG.getNodeValueTypes(MVT::i64, MVT::Other), 2,
1965 DAG.setRoot(Tmp.getValue(1));
1968 case Intrinsic::bswap_i16:
1969 case Intrinsic::bswap_i32:
1970 case Intrinsic::bswap_i64:
1971 setValue(&I, DAG.getNode(ISD::BSWAP,
1972 getValue(I.getOperand(1)).getValueType(),
1973 getValue(I.getOperand(1))));
1975 case Intrinsic::cttz_i8:
1976 case Intrinsic::cttz_i16:
1977 case Intrinsic::cttz_i32:
1978 case Intrinsic::cttz_i64:
1979 setValue(&I, DAG.getNode(ISD::CTTZ,
1980 getValue(I.getOperand(1)).getValueType(),
1981 getValue(I.getOperand(1))));
1983 case Intrinsic::ctlz_i8:
1984 case Intrinsic::ctlz_i16:
1985 case Intrinsic::ctlz_i32:
1986 case Intrinsic::ctlz_i64:
1987 setValue(&I, DAG.getNode(ISD::CTLZ,
1988 getValue(I.getOperand(1)).getValueType(),
1989 getValue(I.getOperand(1))));
1991 case Intrinsic::ctpop_i8:
1992 case Intrinsic::ctpop_i16:
1993 case Intrinsic::ctpop_i32:
1994 case Intrinsic::ctpop_i64:
1995 setValue(&I, DAG.getNode(ISD::CTPOP,
1996 getValue(I.getOperand(1)).getValueType(),
1997 getValue(I.getOperand(1))));
1999 case Intrinsic::stacksave: {
2000 SDOperand Op = getRoot();
2001 SDOperand Tmp = DAG.getNode(ISD::STACKSAVE,
2002 DAG.getNodeValueTypes(TLI.getPointerTy(), MVT::Other), 2, &Op, 1);
2004 DAG.setRoot(Tmp.getValue(1));
2007 case Intrinsic::stackrestore: {
2008 SDOperand Tmp = getValue(I.getOperand(1));
2009 DAG.setRoot(DAG.getNode(ISD::STACKRESTORE, MVT::Other, getRoot(), Tmp));
2012 case Intrinsic::prefetch:
2013 // FIXME: Currently discarding prefetches.
2019 void SelectionDAGLowering::visitCall(CallInst &I) {
2020 const char *RenameFn = 0;
2021 if (Function *F = I.getCalledFunction()) {
2022 if (F->isExternal())
2023 if (unsigned IID = F->getIntrinsicID()) {
2024 RenameFn = visitIntrinsicCall(I, IID);
2027 } else { // Not an LLVM intrinsic.
2028 const std::string &Name = F->getName();
2029 if (Name[0] == 'c' && (Name == "copysign" || Name == "copysignf")) {
2030 if (I.getNumOperands() == 3 && // Basic sanity checks.
2031 I.getOperand(1)->getType()->isFloatingPoint() &&
2032 I.getType() == I.getOperand(1)->getType() &&
2033 I.getType() == I.getOperand(2)->getType()) {
2034 SDOperand LHS = getValue(I.getOperand(1));
2035 SDOperand RHS = getValue(I.getOperand(2));
2036 setValue(&I, DAG.getNode(ISD::FCOPYSIGN, LHS.getValueType(),
2040 } else if (Name[0] == 'f' && (Name == "fabs" || Name == "fabsf")) {
2041 if (I.getNumOperands() == 2 && // Basic sanity checks.
2042 I.getOperand(1)->getType()->isFloatingPoint() &&
2043 I.getType() == I.getOperand(1)->getType()) {
2044 SDOperand Tmp = getValue(I.getOperand(1));
2045 setValue(&I, DAG.getNode(ISD::FABS, Tmp.getValueType(), Tmp));
2048 } else if (Name[0] == 's' && (Name == "sin" || Name == "sinf")) {
2049 if (I.getNumOperands() == 2 && // Basic sanity checks.
2050 I.getOperand(1)->getType()->isFloatingPoint() &&
2051 I.getType() == I.getOperand(1)->getType()) {
2052 SDOperand Tmp = getValue(I.getOperand(1));
2053 setValue(&I, DAG.getNode(ISD::FSIN, Tmp.getValueType(), Tmp));
2056 } else if (Name[0] == 'c' && (Name == "cos" || Name == "cosf")) {
2057 if (I.getNumOperands() == 2 && // Basic sanity checks.
2058 I.getOperand(1)->getType()->isFloatingPoint() &&
2059 I.getType() == I.getOperand(1)->getType()) {
2060 SDOperand Tmp = getValue(I.getOperand(1));
2061 setValue(&I, DAG.getNode(ISD::FCOS, Tmp.getValueType(), Tmp));
2066 } else if (isa<InlineAsm>(I.getOperand(0))) {
2073 Callee = getValue(I.getOperand(0));
2075 Callee = DAG.getExternalSymbol(RenameFn, TLI.getPointerTy());
2076 std::vector<std::pair<SDOperand, const Type*> > Args;
2077 Args.reserve(I.getNumOperands());
2078 for (unsigned i = 1, e = I.getNumOperands(); i != e; ++i) {
2079 Value *Arg = I.getOperand(i);
2080 SDOperand ArgNode = getValue(Arg);
2081 Args.push_back(std::make_pair(ArgNode, Arg->getType()));
2084 const PointerType *PT = cast<PointerType>(I.getCalledValue()->getType());
2085 const FunctionType *FTy = cast<FunctionType>(PT->getElementType());
2087 std::pair<SDOperand,SDOperand> Result =
2088 TLI.LowerCallTo(getRoot(), I.getType(), FTy->isVarArg(), I.getCallingConv(),
2089 I.isTailCall(), Callee, Args, DAG);
2090 if (I.getType() != Type::VoidTy)
2091 setValue(&I, Result.first);
2092 DAG.setRoot(Result.second);
2095 SDOperand RegsForValue::getCopyFromRegs(SelectionDAG &DAG,
2096 SDOperand &Chain, SDOperand &Flag)const{
2097 SDOperand Val = DAG.getCopyFromReg(Chain, Regs[0], RegVT, Flag);
2098 Chain = Val.getValue(1);
2099 Flag = Val.getValue(2);
2101 // If the result was expanded, copy from the top part.
2102 if (Regs.size() > 1) {
2103 assert(Regs.size() == 2 &&
2104 "Cannot expand to more than 2 elts yet!");
2105 SDOperand Hi = DAG.getCopyFromReg(Chain, Regs[1], RegVT, Flag);
2106 Chain = Hi.getValue(1);
2107 Flag = Hi.getValue(2);
2108 if (DAG.getTargetLoweringInfo().isLittleEndian())
2109 return DAG.getNode(ISD::BUILD_PAIR, ValueVT, Val, Hi);
2111 return DAG.getNode(ISD::BUILD_PAIR, ValueVT, Hi, Val);
2114 // Otherwise, if the return value was promoted or extended, truncate it to the
2115 // appropriate type.
2116 if (RegVT == ValueVT)
2119 if (MVT::isInteger(RegVT)) {
2120 if (ValueVT < RegVT)
2121 return DAG.getNode(ISD::TRUNCATE, ValueVT, Val);
2123 return DAG.getNode(ISD::ANY_EXTEND, ValueVT, Val);
2125 return DAG.getNode(ISD::FP_ROUND, ValueVT, Val);
2129 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
2130 /// specified value into the registers specified by this object. This uses
2131 /// Chain/Flag as the input and updates them for the output Chain/Flag.
2132 void RegsForValue::getCopyToRegs(SDOperand Val, SelectionDAG &DAG,
2133 SDOperand &Chain, SDOperand &Flag,
2134 MVT::ValueType PtrVT) const {
2135 if (Regs.size() == 1) {
2136 // If there is a single register and the types differ, this must be
2138 if (RegVT != ValueVT) {
2139 if (MVT::isInteger(RegVT)) {
2140 if (RegVT < ValueVT)
2141 Val = DAG.getNode(ISD::TRUNCATE, RegVT, Val);
2143 Val = DAG.getNode(ISD::ANY_EXTEND, RegVT, Val);
2145 Val = DAG.getNode(ISD::FP_EXTEND, RegVT, Val);
2147 Chain = DAG.getCopyToReg(Chain, Regs[0], Val, Flag);
2148 Flag = Chain.getValue(1);
2150 std::vector<unsigned> R(Regs);
2151 if (!DAG.getTargetLoweringInfo().isLittleEndian())
2152 std::reverse(R.begin(), R.end());
2154 for (unsigned i = 0, e = R.size(); i != e; ++i) {
2155 SDOperand Part = DAG.getNode(ISD::EXTRACT_ELEMENT, RegVT, Val,
2156 DAG.getConstant(i, PtrVT));
2157 Chain = DAG.getCopyToReg(Chain, R[i], Part, Flag);
2158 Flag = Chain.getValue(1);
2163 /// AddInlineAsmOperands - Add this value to the specified inlineasm node
2164 /// operand list. This adds the code marker and includes the number of
2165 /// values added into it.
2166 void RegsForValue::AddInlineAsmOperands(unsigned Code, SelectionDAG &DAG,
2167 std::vector<SDOperand> &Ops) const {
2168 Ops.push_back(DAG.getConstant(Code | (Regs.size() << 3), MVT::i32));
2169 for (unsigned i = 0, e = Regs.size(); i != e; ++i)
2170 Ops.push_back(DAG.getRegister(Regs[i], RegVT));
2173 /// isAllocatableRegister - If the specified register is safe to allocate,
2174 /// i.e. it isn't a stack pointer or some other special register, return the
2175 /// register class for the register. Otherwise, return null.
2176 static const TargetRegisterClass *
2177 isAllocatableRegister(unsigned Reg, MachineFunction &MF,
2178 const TargetLowering &TLI, const MRegisterInfo *MRI) {
2179 MVT::ValueType FoundVT = MVT::Other;
2180 const TargetRegisterClass *FoundRC = 0;
2181 for (MRegisterInfo::regclass_iterator RCI = MRI->regclass_begin(),
2182 E = MRI->regclass_end(); RCI != E; ++RCI) {
2183 MVT::ValueType ThisVT = MVT::Other;
2185 const TargetRegisterClass *RC = *RCI;
2186 // If none of the the value types for this register class are valid, we
2187 // can't use it. For example, 64-bit reg classes on 32-bit targets.
2188 for (TargetRegisterClass::vt_iterator I = RC->vt_begin(), E = RC->vt_end();
2190 if (TLI.isTypeLegal(*I)) {
2191 // If we have already found this register in a different register class,
2192 // choose the one with the largest VT specified. For example, on
2193 // PowerPC, we favor f64 register classes over f32.
2194 if (FoundVT == MVT::Other ||
2195 MVT::getSizeInBits(FoundVT) < MVT::getSizeInBits(*I)) {
2202 if (ThisVT == MVT::Other) continue;
2204 // NOTE: This isn't ideal. In particular, this might allocate the
2205 // frame pointer in functions that need it (due to them not being taken
2206 // out of allocation, because a variable sized allocation hasn't been seen
2207 // yet). This is a slight code pessimization, but should still work.
2208 for (TargetRegisterClass::iterator I = RC->allocation_order_begin(MF),
2209 E = RC->allocation_order_end(MF); I != E; ++I)
2211 // We found a matching register class. Keep looking at others in case
2212 // we find one with larger registers that this physreg is also in.
2221 RegsForValue SelectionDAGLowering::
2222 GetRegistersForValue(const std::string &ConstrCode,
2223 MVT::ValueType VT, bool isOutReg, bool isInReg,
2224 std::set<unsigned> &OutputRegs,
2225 std::set<unsigned> &InputRegs) {
2226 std::pair<unsigned, const TargetRegisterClass*> PhysReg =
2227 TLI.getRegForInlineAsmConstraint(ConstrCode, VT);
2228 std::vector<unsigned> Regs;
2230 unsigned NumRegs = VT != MVT::Other ? TLI.getNumElements(VT) : 1;
2231 MVT::ValueType RegVT;
2232 MVT::ValueType ValueVT = VT;
2234 // If this is a constraint for a specific physical register, like {r17},
2236 if (PhysReg.first) {
2237 if (VT == MVT::Other)
2238 ValueVT = *PhysReg.second->vt_begin();
2240 // Get the actual register value type. This is important, because the user
2241 // may have asked for (e.g.) the AX register in i32 type. We need to
2242 // remember that AX is actually i16 to get the right extension.
2243 RegVT = *PhysReg.second->vt_begin();
2245 // This is a explicit reference to a physical register.
2246 Regs.push_back(PhysReg.first);
2248 // If this is an expanded reference, add the rest of the regs to Regs.
2250 TargetRegisterClass::iterator I = PhysReg.second->begin();
2251 TargetRegisterClass::iterator E = PhysReg.second->end();
2252 for (; *I != PhysReg.first; ++I)
2253 assert(I != E && "Didn't find reg!");
2255 // Already added the first reg.
2257 for (; NumRegs; --NumRegs, ++I) {
2258 assert(I != E && "Ran out of registers to allocate!");
2262 return RegsForValue(Regs, RegVT, ValueVT);
2265 // Otherwise, if this was a reference to an LLVM register class, create vregs
2266 // for this reference.
2267 std::vector<unsigned> RegClassRegs;
2268 if (PhysReg.second) {
2269 // If this is an early clobber or tied register, our regalloc doesn't know
2270 // how to maintain the constraint. If it isn't, go ahead and create vreg
2271 // and let the regalloc do the right thing.
2272 if (!isOutReg || !isInReg) {
2273 if (VT == MVT::Other)
2274 ValueVT = *PhysReg.second->vt_begin();
2275 RegVT = *PhysReg.second->vt_begin();
2277 // Create the appropriate number of virtual registers.
2278 SSARegMap *RegMap = DAG.getMachineFunction().getSSARegMap();
2279 for (; NumRegs; --NumRegs)
2280 Regs.push_back(RegMap->createVirtualRegister(PhysReg.second));
2282 return RegsForValue(Regs, RegVT, ValueVT);
2285 // Otherwise, we can't allocate it. Let the code below figure out how to
2286 // maintain these constraints.
2287 RegClassRegs.assign(PhysReg.second->begin(), PhysReg.second->end());
2290 // This is a reference to a register class that doesn't directly correspond
2291 // to an LLVM register class. Allocate NumRegs consecutive, available,
2292 // registers from the class.
2293 RegClassRegs = TLI.getRegClassForInlineAsmConstraint(ConstrCode, VT);
2296 const MRegisterInfo *MRI = DAG.getTarget().getRegisterInfo();
2297 MachineFunction &MF = *CurMBB->getParent();
2298 unsigned NumAllocated = 0;
2299 for (unsigned i = 0, e = RegClassRegs.size(); i != e; ++i) {
2300 unsigned Reg = RegClassRegs[i];
2301 // See if this register is available.
2302 if ((isOutReg && OutputRegs.count(Reg)) || // Already used.
2303 (isInReg && InputRegs.count(Reg))) { // Already used.
2304 // Make sure we find consecutive registers.
2309 // Check to see if this register is allocatable (i.e. don't give out the
2311 const TargetRegisterClass *RC = isAllocatableRegister(Reg, MF, TLI, MRI);
2313 // Make sure we find consecutive registers.
2318 // Okay, this register is good, we can use it.
2321 // If we allocated enough consecutive
2322 if (NumAllocated == NumRegs) {
2323 unsigned RegStart = (i-NumAllocated)+1;
2324 unsigned RegEnd = i+1;
2325 // Mark all of the allocated registers used.
2326 for (unsigned i = RegStart; i != RegEnd; ++i) {
2327 unsigned Reg = RegClassRegs[i];
2328 Regs.push_back(Reg);
2329 if (isOutReg) OutputRegs.insert(Reg); // Mark reg used.
2330 if (isInReg) InputRegs.insert(Reg); // Mark reg used.
2333 return RegsForValue(Regs, *RC->vt_begin(), VT);
2337 // Otherwise, we couldn't allocate enough registers for this.
2338 return RegsForValue();
2342 /// visitInlineAsm - Handle a call to an InlineAsm object.
2344 void SelectionDAGLowering::visitInlineAsm(CallInst &I) {
2345 InlineAsm *IA = cast<InlineAsm>(I.getOperand(0));
2347 SDOperand AsmStr = DAG.getTargetExternalSymbol(IA->getAsmString().c_str(),
2350 // Note, we treat inline asms both with and without side-effects as the same.
2351 // If an inline asm doesn't have side effects and doesn't access memory, we
2352 // could not choose to not chain it.
2353 bool hasSideEffects = IA->hasSideEffects();
2355 std::vector<InlineAsm::ConstraintInfo> Constraints = IA->ParseConstraints();
2356 std::vector<MVT::ValueType> ConstraintVTs;
2358 /// AsmNodeOperands - A list of pairs. The first element is a register, the
2359 /// second is a bitfield where bit #0 is set if it is a use and bit #1 is set
2360 /// if it is a def of that register.
2361 std::vector<SDOperand> AsmNodeOperands;
2362 AsmNodeOperands.push_back(SDOperand()); // reserve space for input chain
2363 AsmNodeOperands.push_back(AsmStr);
2365 SDOperand Chain = getRoot();
2368 // We fully assign registers here at isel time. This is not optimal, but
2369 // should work. For register classes that correspond to LLVM classes, we
2370 // could let the LLVM RA do its thing, but we currently don't. Do a prepass
2371 // over the constraints, collecting fixed registers that we know we can't use.
2372 std::set<unsigned> OutputRegs, InputRegs;
2374 for (unsigned i = 0, e = Constraints.size(); i != e; ++i) {
2375 assert(Constraints[i].Codes.size() == 1 && "Only handles one code so far!");
2376 std::string &ConstraintCode = Constraints[i].Codes[0];
2378 MVT::ValueType OpVT;
2380 // Compute the value type for each operand and add it to ConstraintVTs.
2381 switch (Constraints[i].Type) {
2382 case InlineAsm::isOutput:
2383 if (!Constraints[i].isIndirectOutput) {
2384 assert(I.getType() != Type::VoidTy && "Bad inline asm!");
2385 OpVT = TLI.getValueType(I.getType());
2387 const Type *OpTy = I.getOperand(OpNum)->getType();
2388 OpVT = TLI.getValueType(cast<PointerType>(OpTy)->getElementType());
2389 OpNum++; // Consumes a call operand.
2392 case InlineAsm::isInput:
2393 OpVT = TLI.getValueType(I.getOperand(OpNum)->getType());
2394 OpNum++; // Consumes a call operand.
2396 case InlineAsm::isClobber:
2401 ConstraintVTs.push_back(OpVT);
2403 if (TLI.getRegForInlineAsmConstraint(ConstraintCode, OpVT).first == 0)
2404 continue; // Not assigned a fixed reg.
2406 // Build a list of regs that this operand uses. This always has a single
2407 // element for promoted/expanded operands.
2408 RegsForValue Regs = GetRegistersForValue(ConstraintCode, OpVT,
2410 OutputRegs, InputRegs);
2412 switch (Constraints[i].Type) {
2413 case InlineAsm::isOutput:
2414 // We can't assign any other output to this register.
2415 OutputRegs.insert(Regs.Regs.begin(), Regs.Regs.end());
2416 // If this is an early-clobber output, it cannot be assigned to the same
2417 // value as the input reg.
2418 if (Constraints[i].isEarlyClobber || Constraints[i].hasMatchingInput)
2419 InputRegs.insert(Regs.Regs.begin(), Regs.Regs.end());
2421 case InlineAsm::isInput:
2422 // We can't assign any other input to this register.
2423 InputRegs.insert(Regs.Regs.begin(), Regs.Regs.end());
2425 case InlineAsm::isClobber:
2426 // Clobbered regs cannot be used as inputs or outputs.
2427 InputRegs.insert(Regs.Regs.begin(), Regs.Regs.end());
2428 OutputRegs.insert(Regs.Regs.begin(), Regs.Regs.end());
2433 // Loop over all of the inputs, copying the operand values into the
2434 // appropriate registers and processing the output regs.
2435 RegsForValue RetValRegs;
2436 std::vector<std::pair<RegsForValue, Value*> > IndirectStoresToEmit;
2439 for (unsigned i = 0, e = Constraints.size(); i != e; ++i) {
2440 assert(Constraints[i].Codes.size() == 1 && "Only handles one code so far!");
2441 std::string &ConstraintCode = Constraints[i].Codes[0];
2443 switch (Constraints[i].Type) {
2444 case InlineAsm::isOutput: {
2445 TargetLowering::ConstraintType CTy = TargetLowering::C_RegisterClass;
2446 if (ConstraintCode.size() == 1) // not a physreg name.
2447 CTy = TLI.getConstraintType(ConstraintCode[0]);
2449 if (CTy == TargetLowering::C_Memory) {
2451 SDOperand InOperandVal = getValue(I.getOperand(OpNum));
2453 // Check that the operand (the address to store to) isn't a float.
2454 if (!MVT::isInteger(InOperandVal.getValueType()))
2455 assert(0 && "MATCH FAIL!");
2457 if (!Constraints[i].isIndirectOutput)
2458 assert(0 && "MATCH FAIL!");
2460 OpNum++; // Consumes a call operand.
2462 // Extend/truncate to the right pointer type if needed.
2463 MVT::ValueType PtrType = TLI.getPointerTy();
2464 if (InOperandVal.getValueType() < PtrType)
2465 InOperandVal = DAG.getNode(ISD::ZERO_EXTEND, PtrType, InOperandVal);
2466 else if (InOperandVal.getValueType() > PtrType)
2467 InOperandVal = DAG.getNode(ISD::TRUNCATE, PtrType, InOperandVal);
2469 // Add information to the INLINEASM node to know about this output.
2470 unsigned ResOpType = 4/*MEM*/ | (1 << 3);
2471 AsmNodeOperands.push_back(DAG.getConstant(ResOpType, MVT::i32));
2472 AsmNodeOperands.push_back(InOperandVal);
2476 // Otherwise, this is a register output.
2477 assert(CTy == TargetLowering::C_RegisterClass && "Unknown op type!");
2479 // If this is an early-clobber output, or if there is an input
2480 // constraint that matches this, we need to reserve the input register
2481 // so no other inputs allocate to it.
2482 bool UsesInputRegister = false;
2483 if (Constraints[i].isEarlyClobber || Constraints[i].hasMatchingInput)
2484 UsesInputRegister = true;
2486 // Copy the output from the appropriate register. Find a register that
2489 GetRegistersForValue(ConstraintCode, ConstraintVTs[i],
2490 true, UsesInputRegister,
2491 OutputRegs, InputRegs);
2492 if (Regs.Regs.empty()) {
2493 std::cerr << "Couldn't allocate output reg for contraint '"
2494 << ConstraintCode << "'!\n";
2498 if (!Constraints[i].isIndirectOutput) {
2499 assert(RetValRegs.Regs.empty() &&
2500 "Cannot have multiple output constraints yet!");
2501 assert(I.getType() != Type::VoidTy && "Bad inline asm!");
2504 IndirectStoresToEmit.push_back(std::make_pair(Regs,
2505 I.getOperand(OpNum)));
2506 OpNum++; // Consumes a call operand.
2509 // Add information to the INLINEASM node to know that this register is
2511 Regs.AddInlineAsmOperands(2 /*REGDEF*/, DAG, AsmNodeOperands);
2514 case InlineAsm::isInput: {
2515 SDOperand InOperandVal = getValue(I.getOperand(OpNum));
2516 OpNum++; // Consumes a call operand.
2518 if (isdigit(ConstraintCode[0])) { // Matching constraint?
2519 // If this is required to match an output register we have already set,
2520 // just use its register.
2521 unsigned OperandNo = atoi(ConstraintCode.c_str());
2523 // Scan until we find the definition we already emitted of this operand.
2524 // When we find it, create a RegsForValue operand.
2525 unsigned CurOp = 2; // The first operand.
2526 for (; OperandNo; --OperandNo) {
2527 // Advance to the next operand.
2529 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getValue();
2530 assert(((NumOps & 7) == 2 /*REGDEF*/ ||
2531 (NumOps & 7) == 4 /*MEM*/) &&
2532 "Skipped past definitions?");
2533 CurOp += (NumOps>>3)+1;
2537 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getValue();
2538 assert((NumOps & 7) == 2 /*REGDEF*/ &&
2539 "Skipped past definitions?");
2541 // Add NumOps>>3 registers to MatchedRegs.
2542 RegsForValue MatchedRegs;
2543 MatchedRegs.ValueVT = InOperandVal.getValueType();
2544 MatchedRegs.RegVT = AsmNodeOperands[CurOp+1].getValueType();
2545 for (unsigned i = 0, e = NumOps>>3; i != e; ++i) {
2546 unsigned Reg=cast<RegisterSDNode>(AsmNodeOperands[++CurOp])->getReg();
2547 MatchedRegs.Regs.push_back(Reg);
2550 // Use the produced MatchedRegs object to
2551 MatchedRegs.getCopyToRegs(InOperandVal, DAG, Chain, Flag,
2552 TLI.getPointerTy());
2553 MatchedRegs.AddInlineAsmOperands(1 /*REGUSE*/, DAG, AsmNodeOperands);
2557 TargetLowering::ConstraintType CTy = TargetLowering::C_RegisterClass;
2558 if (ConstraintCode.size() == 1) // not a physreg name.
2559 CTy = TLI.getConstraintType(ConstraintCode[0]);
2561 if (CTy == TargetLowering::C_Other) {
2562 InOperandVal = TLI.isOperandValidForConstraint(InOperandVal,
2563 ConstraintCode[0], DAG);
2564 if (!InOperandVal.Val) {
2565 std::cerr << "Invalid operand for inline asm constraint '"
2566 << ConstraintCode << "'!\n";
2570 // Add information to the INLINEASM node to know about this input.
2571 unsigned ResOpType = 3 /*IMM*/ | (1 << 3);
2572 AsmNodeOperands.push_back(DAG.getConstant(ResOpType, MVT::i32));
2573 AsmNodeOperands.push_back(InOperandVal);
2575 } else if (CTy == TargetLowering::C_Memory) {
2578 // Check that the operand isn't a float.
2579 if (!MVT::isInteger(InOperandVal.getValueType()))
2580 assert(0 && "MATCH FAIL!");
2582 // Extend/truncate to the right pointer type if needed.
2583 MVT::ValueType PtrType = TLI.getPointerTy();
2584 if (InOperandVal.getValueType() < PtrType)
2585 InOperandVal = DAG.getNode(ISD::ZERO_EXTEND, PtrType, InOperandVal);
2586 else if (InOperandVal.getValueType() > PtrType)
2587 InOperandVal = DAG.getNode(ISD::TRUNCATE, PtrType, InOperandVal);
2589 // Add information to the INLINEASM node to know about this input.
2590 unsigned ResOpType = 4/*MEM*/ | (1 << 3);
2591 AsmNodeOperands.push_back(DAG.getConstant(ResOpType, MVT::i32));
2592 AsmNodeOperands.push_back(InOperandVal);
2596 assert(CTy == TargetLowering::C_RegisterClass && "Unknown op type!");
2598 // Copy the input into the appropriate registers.
2599 RegsForValue InRegs =
2600 GetRegistersForValue(ConstraintCode, ConstraintVTs[i],
2601 false, true, OutputRegs, InputRegs);
2602 // FIXME: should be match fail.
2603 assert(!InRegs.Regs.empty() && "Couldn't allocate input reg!");
2605 InRegs.getCopyToRegs(InOperandVal, DAG, Chain, Flag, TLI.getPointerTy());
2607 InRegs.AddInlineAsmOperands(1/*REGUSE*/, DAG, AsmNodeOperands);
2610 case InlineAsm::isClobber: {
2611 RegsForValue ClobberedRegs =
2612 GetRegistersForValue(ConstraintCode, MVT::Other, false, false,
2613 OutputRegs, InputRegs);
2614 // Add the clobbered value to the operand list, so that the register
2615 // allocator is aware that the physreg got clobbered.
2616 if (!ClobberedRegs.Regs.empty())
2617 ClobberedRegs.AddInlineAsmOperands(2/*REGDEF*/, DAG, AsmNodeOperands);
2623 // Finish up input operands.
2624 AsmNodeOperands[0] = Chain;
2625 if (Flag.Val) AsmNodeOperands.push_back(Flag);
2627 Chain = DAG.getNode(ISD::INLINEASM,
2628 DAG.getNodeValueTypes(MVT::Other, MVT::Flag), 2,
2629 &AsmNodeOperands[0], AsmNodeOperands.size());
2630 Flag = Chain.getValue(1);
2632 // If this asm returns a register value, copy the result from that register
2633 // and set it as the value of the call.
2634 if (!RetValRegs.Regs.empty())
2635 setValue(&I, RetValRegs.getCopyFromRegs(DAG, Chain, Flag));
2637 std::vector<std::pair<SDOperand, Value*> > StoresToEmit;
2639 // Process indirect outputs, first output all of the flagged copies out of
2641 for (unsigned i = 0, e = IndirectStoresToEmit.size(); i != e; ++i) {
2642 RegsForValue &OutRegs = IndirectStoresToEmit[i].first;
2643 Value *Ptr = IndirectStoresToEmit[i].second;
2644 SDOperand OutVal = OutRegs.getCopyFromRegs(DAG, Chain, Flag);
2645 StoresToEmit.push_back(std::make_pair(OutVal, Ptr));
2648 // Emit the non-flagged stores from the physregs.
2649 SmallVector<SDOperand, 8> OutChains;
2650 for (unsigned i = 0, e = StoresToEmit.size(); i != e; ++i)
2651 OutChains.push_back(DAG.getStore(Chain, StoresToEmit[i].first,
2652 getValue(StoresToEmit[i].second),
2653 StoresToEmit[i].second, 0));
2654 if (!OutChains.empty())
2655 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other,
2656 &OutChains[0], OutChains.size());
2661 void SelectionDAGLowering::visitMalloc(MallocInst &I) {
2662 SDOperand Src = getValue(I.getOperand(0));
2664 MVT::ValueType IntPtr = TLI.getPointerTy();
2666 if (IntPtr < Src.getValueType())
2667 Src = DAG.getNode(ISD::TRUNCATE, IntPtr, Src);
2668 else if (IntPtr > Src.getValueType())
2669 Src = DAG.getNode(ISD::ZERO_EXTEND, IntPtr, Src);
2671 // Scale the source by the type size.
2672 uint64_t ElementSize = TD->getTypeSize(I.getType()->getElementType());
2673 Src = DAG.getNode(ISD::MUL, Src.getValueType(),
2674 Src, getIntPtrConstant(ElementSize));
2676 std::vector<std::pair<SDOperand, const Type*> > Args;
2677 Args.push_back(std::make_pair(Src, TLI.getTargetData()->getIntPtrType()));
2679 std::pair<SDOperand,SDOperand> Result =
2680 TLI.LowerCallTo(getRoot(), I.getType(), false, CallingConv::C, true,
2681 DAG.getExternalSymbol("malloc", IntPtr),
2683 setValue(&I, Result.first); // Pointers always fit in registers
2684 DAG.setRoot(Result.second);
2687 void SelectionDAGLowering::visitFree(FreeInst &I) {
2688 std::vector<std::pair<SDOperand, const Type*> > Args;
2689 Args.push_back(std::make_pair(getValue(I.getOperand(0)),
2690 TLI.getTargetData()->getIntPtrType()));
2691 MVT::ValueType IntPtr = TLI.getPointerTy();
2692 std::pair<SDOperand,SDOperand> Result =
2693 TLI.LowerCallTo(getRoot(), Type::VoidTy, false, CallingConv::C, true,
2694 DAG.getExternalSymbol("free", IntPtr), Args, DAG);
2695 DAG.setRoot(Result.second);
2698 // InsertAtEndOfBasicBlock - This method should be implemented by targets that
2699 // mark instructions with the 'usesCustomDAGSchedInserter' flag. These
2700 // instructions are special in various ways, which require special support to
2701 // insert. The specified MachineInstr is created but not inserted into any
2702 // basic blocks, and the scheduler passes ownership of it to this method.
2703 MachineBasicBlock *TargetLowering::InsertAtEndOfBasicBlock(MachineInstr *MI,
2704 MachineBasicBlock *MBB) {
2705 std::cerr << "If a target marks an instruction with "
2706 "'usesCustomDAGSchedInserter', it must implement "
2707 "TargetLowering::InsertAtEndOfBasicBlock!\n";
2712 void SelectionDAGLowering::visitVAStart(CallInst &I) {
2713 DAG.setRoot(DAG.getNode(ISD::VASTART, MVT::Other, getRoot(),
2714 getValue(I.getOperand(1)),
2715 DAG.getSrcValue(I.getOperand(1))));
2718 void SelectionDAGLowering::visitVAArg(VAArgInst &I) {
2719 SDOperand V = DAG.getVAArg(TLI.getValueType(I.getType()), getRoot(),
2720 getValue(I.getOperand(0)),
2721 DAG.getSrcValue(I.getOperand(0)));
2723 DAG.setRoot(V.getValue(1));
2726 void SelectionDAGLowering::visitVAEnd(CallInst &I) {
2727 DAG.setRoot(DAG.getNode(ISD::VAEND, MVT::Other, getRoot(),
2728 getValue(I.getOperand(1)),
2729 DAG.getSrcValue(I.getOperand(1))));
2732 void SelectionDAGLowering::visitVACopy(CallInst &I) {
2733 DAG.setRoot(DAG.getNode(ISD::VACOPY, MVT::Other, getRoot(),
2734 getValue(I.getOperand(1)),
2735 getValue(I.getOperand(2)),
2736 DAG.getSrcValue(I.getOperand(1)),
2737 DAG.getSrcValue(I.getOperand(2))));
2740 /// TargetLowering::LowerArguments - This is the default LowerArguments
2741 /// implementation, which just inserts a FORMAL_ARGUMENTS node. FIXME: When all
2742 /// targets are migrated to using FORMAL_ARGUMENTS, this hook should be
2743 /// integrated into SDISel.
2744 std::vector<SDOperand>
2745 TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
2746 // Add CC# and isVararg as operands to the FORMAL_ARGUMENTS node.
2747 std::vector<SDOperand> Ops;
2748 Ops.push_back(DAG.getRoot());
2749 Ops.push_back(DAG.getConstant(F.getCallingConv(), getPointerTy()));
2750 Ops.push_back(DAG.getConstant(F.isVarArg(), getPointerTy()));
2752 // Add one result value for each formal argument.
2753 std::vector<MVT::ValueType> RetVals;
2754 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; ++I) {
2755 MVT::ValueType VT = getValueType(I->getType());
2757 switch (getTypeAction(VT)) {
2758 default: assert(0 && "Unknown type action!");
2760 RetVals.push_back(VT);
2763 RetVals.push_back(getTypeToTransformTo(VT));
2766 if (VT != MVT::Vector) {
2767 // If this is a large integer, it needs to be broken up into small
2768 // integers. Figure out what the destination type is and how many small
2769 // integers it turns into.
2770 MVT::ValueType NVT = getTypeToTransformTo(VT);
2771 unsigned NumVals = MVT::getSizeInBits(VT)/MVT::getSizeInBits(NVT);
2772 for (unsigned i = 0; i != NumVals; ++i)
2773 RetVals.push_back(NVT);
2775 // Otherwise, this is a vector type. We only support legal vectors
2777 unsigned NumElems = cast<PackedType>(I->getType())->getNumElements();
2778 const Type *EltTy = cast<PackedType>(I->getType())->getElementType();
2780 // Figure out if there is a Packed type corresponding to this Vector
2781 // type. If so, convert to the packed type.
2782 MVT::ValueType TVT = MVT::getVectorType(getValueType(EltTy), NumElems);
2783 if (TVT != MVT::Other && isTypeLegal(TVT)) {
2784 RetVals.push_back(TVT);
2786 assert(0 && "Don't support illegal by-val vector arguments yet!");
2793 RetVals.push_back(MVT::Other);
2796 SDNode *Result = DAG.getNode(ISD::FORMAL_ARGUMENTS,
2797 DAG.getNodeValueTypes(RetVals), RetVals.size(),
2798 &Ops[0], Ops.size()).Val;
2800 DAG.setRoot(SDOperand(Result, Result->getNumValues()-1));
2802 // Set up the return result vector.
2805 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; ++I) {
2806 MVT::ValueType VT = getValueType(I->getType());
2808 switch (getTypeAction(VT)) {
2809 default: assert(0 && "Unknown type action!");
2811 Ops.push_back(SDOperand(Result, i++));
2814 SDOperand Op(Result, i++);
2815 if (MVT::isInteger(VT)) {
2816 unsigned AssertOp = I->getType()->isSigned() ? ISD::AssertSext
2818 Op = DAG.getNode(AssertOp, Op.getValueType(), Op, DAG.getValueType(VT));
2819 Op = DAG.getNode(ISD::TRUNCATE, VT, Op);
2821 assert(MVT::isFloatingPoint(VT) && "Not int or FP?");
2822 Op = DAG.getNode(ISD::FP_ROUND, VT, Op);
2828 if (VT != MVT::Vector) {
2829 // If this is a large integer, it needs to be reassembled from small
2830 // integers. Figure out what the source elt type is and how many small
2832 MVT::ValueType NVT = getTypeToTransformTo(VT);
2833 unsigned NumVals = MVT::getSizeInBits(VT)/MVT::getSizeInBits(NVT);
2835 SDOperand Lo = SDOperand(Result, i++);
2836 SDOperand Hi = SDOperand(Result, i++);
2838 if (!isLittleEndian())
2841 Ops.push_back(DAG.getNode(ISD::BUILD_PAIR, VT, Lo, Hi));
2843 // Value scalarized into many values. Unimp for now.
2844 assert(0 && "Cannot expand i64 -> i16 yet!");
2847 // Otherwise, this is a vector type. We only support legal vectors
2849 const PackedType *PTy = cast<PackedType>(I->getType());
2850 unsigned NumElems = PTy->getNumElements();
2851 const Type *EltTy = PTy->getElementType();
2853 // Figure out if there is a Packed type corresponding to this Vector
2854 // type. If so, convert to the packed type.
2855 MVT::ValueType TVT = MVT::getVectorType(getValueType(EltTy), NumElems);
2856 if (TVT != MVT::Other && isTypeLegal(TVT)) {
2857 SDOperand N = SDOperand(Result, i++);
2858 // Handle copies from generic vectors to registers.
2859 N = DAG.getNode(ISD::VBIT_CONVERT, MVT::Vector, N,
2860 DAG.getConstant(NumElems, MVT::i32),
2861 DAG.getValueType(getValueType(EltTy)));
2864 assert(0 && "Don't support illegal by-val vector arguments yet!");
2875 /// TargetLowering::LowerCallTo - This is the default LowerCallTo
2876 /// implementation, which just inserts an ISD::CALL node, which is later custom
2877 /// lowered by the target to something concrete. FIXME: When all targets are
2878 /// migrated to using ISD::CALL, this hook should be integrated into SDISel.
2879 std::pair<SDOperand, SDOperand>
2880 TargetLowering::LowerCallTo(SDOperand Chain, const Type *RetTy, bool isVarArg,
2881 unsigned CallingConv, bool isTailCall,
2883 ArgListTy &Args, SelectionDAG &DAG) {
2884 SmallVector<SDOperand, 32> Ops;
2885 Ops.push_back(Chain); // Op#0 - Chain
2886 Ops.push_back(DAG.getConstant(CallingConv, getPointerTy())); // Op#1 - CC
2887 Ops.push_back(DAG.getConstant(isVarArg, getPointerTy())); // Op#2 - VarArg
2888 Ops.push_back(DAG.getConstant(isTailCall, getPointerTy())); // Op#3 - Tail
2889 Ops.push_back(Callee);
2891 // Handle all of the outgoing arguments.
2892 for (unsigned i = 0, e = Args.size(); i != e; ++i) {
2893 MVT::ValueType VT = getValueType(Args[i].second);
2894 SDOperand Op = Args[i].first;
2895 bool isSigned = Args[i].second->isSigned();
2896 switch (getTypeAction(VT)) {
2897 default: assert(0 && "Unknown type action!");
2900 Ops.push_back(DAG.getConstant(isSigned, MVT::i32));
2903 if (MVT::isInteger(VT)) {
2904 unsigned ExtOp = isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
2905 Op = DAG.getNode(ExtOp, getTypeToTransformTo(VT), Op);
2907 assert(MVT::isFloatingPoint(VT) && "Not int or FP?");
2908 Op = DAG.getNode(ISD::FP_EXTEND, getTypeToTransformTo(VT), Op);
2911 Ops.push_back(DAG.getConstant(isSigned, MVT::i32));
2914 if (VT != MVT::Vector) {
2915 // If this is a large integer, it needs to be broken down into small
2916 // integers. Figure out what the source elt type is and how many small
2918 MVT::ValueType NVT = getTypeToTransformTo(VT);
2919 unsigned NumVals = MVT::getSizeInBits(VT)/MVT::getSizeInBits(NVT);
2921 SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, NVT, Op,
2922 DAG.getConstant(0, getPointerTy()));
2923 SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, NVT, Op,
2924 DAG.getConstant(1, getPointerTy()));
2925 if (!isLittleEndian())
2929 Ops.push_back(DAG.getConstant(isSigned, MVT::i32));
2931 Ops.push_back(DAG.getConstant(isSigned, MVT::i32));
2933 // Value scalarized into many values. Unimp for now.
2934 assert(0 && "Cannot expand i64 -> i16 yet!");
2937 // Otherwise, this is a vector type. We only support legal vectors
2939 const PackedType *PTy = cast<PackedType>(Args[i].second);
2940 unsigned NumElems = PTy->getNumElements();
2941 const Type *EltTy = PTy->getElementType();
2943 // Figure out if there is a Packed type corresponding to this Vector
2944 // type. If so, convert to the packed type.
2945 MVT::ValueType TVT = MVT::getVectorType(getValueType(EltTy), NumElems);
2946 if (TVT != MVT::Other && isTypeLegal(TVT)) {
2947 // Insert a VBIT_CONVERT of the MVT::Vector type to the packed type.
2948 Op = DAG.getNode(ISD::VBIT_CONVERT, TVT, Op);
2950 Ops.push_back(DAG.getConstant(isSigned, MVT::i32));
2952 assert(0 && "Don't support illegal by-val vector call args yet!");
2960 // Figure out the result value types.
2961 SmallVector<MVT::ValueType, 4> RetTys;
2963 if (RetTy != Type::VoidTy) {
2964 MVT::ValueType VT = getValueType(RetTy);
2965 switch (getTypeAction(VT)) {
2966 default: assert(0 && "Unknown type action!");
2968 RetTys.push_back(VT);
2971 RetTys.push_back(getTypeToTransformTo(VT));
2974 if (VT != MVT::Vector) {
2975 // If this is a large integer, it needs to be reassembled from small
2976 // integers. Figure out what the source elt type is and how many small
2978 MVT::ValueType NVT = getTypeToTransformTo(VT);
2979 unsigned NumVals = MVT::getSizeInBits(VT)/MVT::getSizeInBits(NVT);
2980 for (unsigned i = 0; i != NumVals; ++i)
2981 RetTys.push_back(NVT);
2983 // Otherwise, this is a vector type. We only support legal vectors
2985 const PackedType *PTy = cast<PackedType>(RetTy);
2986 unsigned NumElems = PTy->getNumElements();
2987 const Type *EltTy = PTy->getElementType();
2989 // Figure out if there is a Packed type corresponding to this Vector
2990 // type. If so, convert to the packed type.
2991 MVT::ValueType TVT = MVT::getVectorType(getValueType(EltTy), NumElems);
2992 if (TVT != MVT::Other && isTypeLegal(TVT)) {
2993 RetTys.push_back(TVT);
2995 assert(0 && "Don't support illegal by-val vector call results yet!");
3002 RetTys.push_back(MVT::Other); // Always has a chain.
3004 // Finally, create the CALL node.
3005 SDOperand Res = DAG.getNode(ISD::CALL,
3006 DAG.getVTList(&RetTys[0], RetTys.size()),
3007 &Ops[0], Ops.size());
3009 // This returns a pair of operands. The first element is the
3010 // return value for the function (if RetTy is not VoidTy). The second
3011 // element is the outgoing token chain.
3013 if (RetTys.size() != 1) {
3014 MVT::ValueType VT = getValueType(RetTy);
3015 if (RetTys.size() == 2) {
3018 // If this value was promoted, truncate it down.
3019 if (ResVal.getValueType() != VT) {
3020 if (VT == MVT::Vector) {
3021 // Insert a VBITCONVERT to convert from the packed result type to the
3022 // MVT::Vector type.
3023 unsigned NumElems = cast<PackedType>(RetTy)->getNumElements();
3024 const Type *EltTy = cast<PackedType>(RetTy)->getElementType();
3026 // Figure out if there is a Packed type corresponding to this Vector
3027 // type. If so, convert to the packed type.
3028 MVT::ValueType TVT = MVT::getVectorType(getValueType(EltTy), NumElems);
3029 if (TVT != MVT::Other && isTypeLegal(TVT)) {
3030 // Insert a VBIT_CONVERT of the FORMAL_ARGUMENTS to a
3031 // "N x PTyElementVT" MVT::Vector type.
3032 ResVal = DAG.getNode(ISD::VBIT_CONVERT, MVT::Vector, ResVal,
3033 DAG.getConstant(NumElems, MVT::i32),
3034 DAG.getValueType(getValueType(EltTy)));
3038 } else if (MVT::isInteger(VT)) {
3039 unsigned AssertOp = RetTy->isSigned() ?
3040 ISD::AssertSext : ISD::AssertZext;
3041 ResVal = DAG.getNode(AssertOp, ResVal.getValueType(), ResVal,
3042 DAG.getValueType(VT));
3043 ResVal = DAG.getNode(ISD::TRUNCATE, VT, ResVal);
3045 assert(MVT::isFloatingPoint(VT));
3046 ResVal = DAG.getNode(ISD::FP_ROUND, VT, ResVal);
3049 } else if (RetTys.size() == 3) {
3050 ResVal = DAG.getNode(ISD::BUILD_PAIR, VT,
3051 Res.getValue(0), Res.getValue(1));
3054 assert(0 && "Case not handled yet!");
3058 return std::make_pair(ResVal, Res.getValue(Res.Val->getNumValues()-1));
3063 // It is always conservatively correct for llvm.returnaddress and
3064 // llvm.frameaddress to return 0.
3066 // FIXME: Change this to insert a FRAMEADDR/RETURNADDR node, and have that be
3067 // expanded to 0 if the target wants.
3068 std::pair<SDOperand, SDOperand>
3069 TargetLowering::LowerFrameReturnAddress(bool isFrameAddr, SDOperand Chain,
3070 unsigned Depth, SelectionDAG &DAG) {
3071 return std::make_pair(DAG.getConstant(0, getPointerTy()), Chain);
3074 SDOperand TargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
3075 assert(0 && "LowerOperation not implemented for this target!");
3080 SDOperand TargetLowering::CustomPromoteOperation(SDOperand Op,
3081 SelectionDAG &DAG) {
3082 assert(0 && "CustomPromoteOperation not implemented for this target!");
3087 void SelectionDAGLowering::visitFrameReturnAddress(CallInst &I, bool isFrame) {
3088 unsigned Depth = (unsigned)cast<ConstantInt>(I.getOperand(1))->getZExtValue();
3089 std::pair<SDOperand,SDOperand> Result =
3090 TLI.LowerFrameReturnAddress(isFrame, getRoot(), Depth, DAG);
3091 setValue(&I, Result.first);
3092 DAG.setRoot(Result.second);
3095 /// getMemsetValue - Vectorized representation of the memset value
3097 static SDOperand getMemsetValue(SDOperand Value, MVT::ValueType VT,
3098 SelectionDAG &DAG) {
3099 MVT::ValueType CurVT = VT;
3100 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Value)) {
3101 uint64_t Val = C->getValue() & 255;
3103 while (CurVT != MVT::i8) {
3104 Val = (Val << Shift) | Val;
3106 CurVT = (MVT::ValueType)((unsigned)CurVT - 1);
3108 return DAG.getConstant(Val, VT);
3110 Value = DAG.getNode(ISD::ZERO_EXTEND, VT, Value);
3112 while (CurVT != MVT::i8) {
3114 DAG.getNode(ISD::OR, VT,
3115 DAG.getNode(ISD::SHL, VT, Value,
3116 DAG.getConstant(Shift, MVT::i8)), Value);
3118 CurVT = (MVT::ValueType)((unsigned)CurVT - 1);
3125 /// getMemsetStringVal - Similar to getMemsetValue. Except this is only
3126 /// used when a memcpy is turned into a memset when the source is a constant
3128 static SDOperand getMemsetStringVal(MVT::ValueType VT,
3129 SelectionDAG &DAG, TargetLowering &TLI,
3130 std::string &Str, unsigned Offset) {
3131 MVT::ValueType CurVT = VT;
3133 unsigned MSB = getSizeInBits(VT) / 8;
3134 if (TLI.isLittleEndian())
3135 Offset = Offset + MSB - 1;
3136 for (unsigned i = 0; i != MSB; ++i) {
3137 Val = (Val << 8) | Str[Offset];
3138 Offset += TLI.isLittleEndian() ? -1 : 1;
3140 return DAG.getConstant(Val, VT);
3143 /// getMemBasePlusOffset - Returns base and offset node for the
3144 static SDOperand getMemBasePlusOffset(SDOperand Base, unsigned Offset,
3145 SelectionDAG &DAG, TargetLowering &TLI) {
3146 MVT::ValueType VT = Base.getValueType();
3147 return DAG.getNode(ISD::ADD, VT, Base, DAG.getConstant(Offset, VT));
3150 /// MeetsMaxMemopRequirement - Determines if the number of memory ops required
3151 /// to replace the memset / memcpy is below the threshold. It also returns the
3152 /// types of the sequence of memory ops to perform memset / memcpy.
3153 static bool MeetsMaxMemopRequirement(std::vector<MVT::ValueType> &MemOps,
3154 unsigned Limit, uint64_t Size,
3155 unsigned Align, TargetLowering &TLI) {
3158 if (TLI.allowsUnalignedMemoryAccesses()) {
3161 switch (Align & 7) {
3177 MVT::ValueType LVT = MVT::i64;
3178 while (!TLI.isTypeLegal(LVT))
3179 LVT = (MVT::ValueType)((unsigned)LVT - 1);
3180 assert(MVT::isInteger(LVT));
3185 unsigned NumMemOps = 0;
3187 unsigned VTSize = getSizeInBits(VT) / 8;
3188 while (VTSize > Size) {
3189 VT = (MVT::ValueType)((unsigned)VT - 1);
3192 assert(MVT::isInteger(VT));
3194 if (++NumMemOps > Limit)
3196 MemOps.push_back(VT);
3203 void SelectionDAGLowering::visitMemIntrinsic(CallInst &I, unsigned Op) {
3204 SDOperand Op1 = getValue(I.getOperand(1));
3205 SDOperand Op2 = getValue(I.getOperand(2));
3206 SDOperand Op3 = getValue(I.getOperand(3));
3207 SDOperand Op4 = getValue(I.getOperand(4));
3208 unsigned Align = (unsigned)cast<ConstantSDNode>(Op4)->getValue();
3209 if (Align == 0) Align = 1;
3211 if (ConstantSDNode *Size = dyn_cast<ConstantSDNode>(Op3)) {
3212 std::vector<MVT::ValueType> MemOps;
3214 // Expand memset / memcpy to a series of load / store ops
3215 // if the size operand falls below a certain threshold.
3216 SmallVector<SDOperand, 8> OutChains;
3218 default: break; // Do nothing for now.
3220 if (MeetsMaxMemopRequirement(MemOps, TLI.getMaxStoresPerMemset(),
3221 Size->getValue(), Align, TLI)) {
3222 unsigned NumMemOps = MemOps.size();
3223 unsigned Offset = 0;
3224 for (unsigned i = 0; i < NumMemOps; i++) {
3225 MVT::ValueType VT = MemOps[i];
3226 unsigned VTSize = getSizeInBits(VT) / 8;
3227 SDOperand Value = getMemsetValue(Op2, VT, DAG);
3228 SDOperand Store = DAG.getStore(getRoot(), Value,
3229 getMemBasePlusOffset(Op1, Offset, DAG, TLI),
3230 I.getOperand(1), Offset);
3231 OutChains.push_back(Store);
3238 if (MeetsMaxMemopRequirement(MemOps, TLI.getMaxStoresPerMemcpy(),
3239 Size->getValue(), Align, TLI)) {
3240 unsigned NumMemOps = MemOps.size();
3241 unsigned SrcOff = 0, DstOff = 0, SrcDelta = 0;
3242 GlobalAddressSDNode *G = NULL;
3244 bool CopyFromStr = false;
3246 if (Op2.getOpcode() == ISD::GlobalAddress)
3247 G = cast<GlobalAddressSDNode>(Op2);
3248 else if (Op2.getOpcode() == ISD::ADD &&
3249 Op2.getOperand(0).getOpcode() == ISD::GlobalAddress &&
3250 Op2.getOperand(1).getOpcode() == ISD::Constant) {
3251 G = cast<GlobalAddressSDNode>(Op2.getOperand(0));
3252 SrcDelta = cast<ConstantSDNode>(Op2.getOperand(1))->getValue();
3255 GlobalVariable *GV = dyn_cast<GlobalVariable>(G->getGlobal());
3257 Str = GV->getStringValue(false);
3265 for (unsigned i = 0; i < NumMemOps; i++) {
3266 MVT::ValueType VT = MemOps[i];
3267 unsigned VTSize = getSizeInBits(VT) / 8;
3268 SDOperand Value, Chain, Store;
3271 Value = getMemsetStringVal(VT, DAG, TLI, Str, SrcOff);
3274 DAG.getStore(Chain, Value,
3275 getMemBasePlusOffset(Op1, DstOff, DAG, TLI),
3276 I.getOperand(1), DstOff);
3278 Value = DAG.getLoad(VT, getRoot(),
3279 getMemBasePlusOffset(Op2, SrcOff, DAG, TLI),
3280 I.getOperand(2), SrcOff);
3281 Chain = Value.getValue(1);
3283 DAG.getStore(Chain, Value,
3284 getMemBasePlusOffset(Op1, DstOff, DAG, TLI),
3285 I.getOperand(1), DstOff);
3287 OutChains.push_back(Store);
3296 if (!OutChains.empty()) {
3297 DAG.setRoot(DAG.getNode(ISD::TokenFactor, MVT::Other,
3298 &OutChains[0], OutChains.size()));
3303 DAG.setRoot(DAG.getNode(Op, MVT::Other, getRoot(), Op1, Op2, Op3, Op4));
3306 //===----------------------------------------------------------------------===//
3307 // SelectionDAGISel code
3308 //===----------------------------------------------------------------------===//
3310 unsigned SelectionDAGISel::MakeReg(MVT::ValueType VT) {
3311 return RegMap->createVirtualRegister(TLI.getRegClassFor(VT));
3314 void SelectionDAGISel::getAnalysisUsage(AnalysisUsage &AU) const {
3315 // FIXME: we only modify the CFG to split critical edges. This
3316 // updates dom and loop info.
3317 AU.addRequired<AliasAnalysis>();
3321 /// OptimizeNoopCopyExpression - We have determined that the specified cast
3322 /// instruction is a noop copy (e.g. it's casting from one pointer type to
3323 /// another, int->uint, or int->sbyte on PPC.
3325 /// Return true if any changes are made.
3326 static bool OptimizeNoopCopyExpression(CastInst *CI) {
3327 BasicBlock *DefBB = CI->getParent();
3329 /// InsertedCasts - Only insert a cast in each block once.
3330 std::map<BasicBlock*, CastInst*> InsertedCasts;
3332 bool MadeChange = false;
3333 for (Value::use_iterator UI = CI->use_begin(), E = CI->use_end();
3335 Use &TheUse = UI.getUse();
3336 Instruction *User = cast<Instruction>(*UI);
3338 // Figure out which BB this cast is used in. For PHI's this is the
3339 // appropriate predecessor block.
3340 BasicBlock *UserBB = User->getParent();
3341 if (PHINode *PN = dyn_cast<PHINode>(User)) {
3342 unsigned OpVal = UI.getOperandNo()/2;
3343 UserBB = PN->getIncomingBlock(OpVal);
3346 // Preincrement use iterator so we don't invalidate it.
3349 // If this user is in the same block as the cast, don't change the cast.
3350 if (UserBB == DefBB) continue;
3352 // If we have already inserted a cast into this block, use it.
3353 CastInst *&InsertedCast = InsertedCasts[UserBB];
3355 if (!InsertedCast) {
3356 BasicBlock::iterator InsertPt = UserBB->begin();
3357 while (isa<PHINode>(InsertPt)) ++InsertPt;
3360 new CastInst(CI->getOperand(0), CI->getType(), "", InsertPt);
3364 // Replace a use of the cast with a use of the new casat.
3365 TheUse = InsertedCast;
3368 // If we removed all uses, nuke the cast.
3369 if (CI->use_empty())
3370 CI->eraseFromParent();
3375 /// InsertGEPComputeCode - Insert code into BB to compute Ptr+PtrOffset,
3376 /// casting to the type of GEPI.
3377 static Instruction *InsertGEPComputeCode(Instruction *&V, BasicBlock *BB,
3378 Instruction *GEPI, Value *Ptr,
3380 if (V) return V; // Already computed.
3382 BasicBlock::iterator InsertPt;
3383 if (BB == GEPI->getParent()) {
3384 // If insert into the GEP's block, insert right after the GEP.
3388 // Otherwise, insert at the top of BB, after any PHI nodes
3389 InsertPt = BB->begin();
3390 while (isa<PHINode>(InsertPt)) ++InsertPt;
3393 // If Ptr is itself a cast, but in some other BB, emit a copy of the cast into
3394 // BB so that there is only one value live across basic blocks (the cast
3396 if (CastInst *CI = dyn_cast<CastInst>(Ptr))
3397 if (CI->getParent() != BB && isa<PointerType>(CI->getOperand(0)->getType()))
3398 Ptr = new CastInst(CI->getOperand(0), CI->getType(), "", InsertPt);
3400 // Add the offset, cast it to the right type.
3401 Ptr = BinaryOperator::createAdd(Ptr, PtrOffset, "", InsertPt);
3402 return V = new CastInst(Ptr, GEPI->getType(), "", InsertPt);
3405 /// ReplaceUsesOfGEPInst - Replace all uses of RepPtr with inserted code to
3406 /// compute its value. The RepPtr value can be computed with Ptr+PtrOffset. One
3407 /// trivial way of doing this would be to evaluate Ptr+PtrOffset in RepPtr's
3408 /// block, then ReplaceAllUsesWith'ing everything. However, we would prefer to
3409 /// sink PtrOffset into user blocks where doing so will likely allow us to fold
3410 /// the constant add into a load or store instruction. Additionally, if a user
3411 /// is a pointer-pointer cast, we look through it to find its users.
3412 static void ReplaceUsesOfGEPInst(Instruction *RepPtr, Value *Ptr,
3413 Constant *PtrOffset, BasicBlock *DefBB,
3414 GetElementPtrInst *GEPI,
3415 std::map<BasicBlock*,Instruction*> &InsertedExprs) {
3416 while (!RepPtr->use_empty()) {
3417 Instruction *User = cast<Instruction>(RepPtr->use_back());
3419 // If the user is a Pointer-Pointer cast, recurse.
3420 if (isa<CastInst>(User) && isa<PointerType>(User->getType())) {
3421 ReplaceUsesOfGEPInst(User, Ptr, PtrOffset, DefBB, GEPI, InsertedExprs);
3423 // Drop the use of RepPtr. The cast is dead. Don't delete it now, else we
3424 // could invalidate an iterator.
3425 User->setOperand(0, UndefValue::get(RepPtr->getType()));
3429 // If this is a load of the pointer, or a store through the pointer, emit
3430 // the increment into the load/store block.
3431 Instruction *NewVal;
3432 if (isa<LoadInst>(User) ||
3433 (isa<StoreInst>(User) && User->getOperand(0) != RepPtr)) {
3434 NewVal = InsertGEPComputeCode(InsertedExprs[User->getParent()],
3435 User->getParent(), GEPI,
3438 // If this use is not foldable into the addressing mode, use a version
3439 // emitted in the GEP block.
3440 NewVal = InsertGEPComputeCode(InsertedExprs[DefBB], DefBB, GEPI,
3444 if (GEPI->getType() != RepPtr->getType()) {
3445 BasicBlock::iterator IP = NewVal;
3447 NewVal = new CastInst(NewVal, RepPtr->getType(), "", IP);
3449 User->replaceUsesOfWith(RepPtr, NewVal);
3454 /// OptimizeGEPExpression - Since we are doing basic-block-at-a-time instruction
3455 /// selection, we want to be a bit careful about some things. In particular, if
3456 /// we have a GEP instruction that is used in a different block than it is
3457 /// defined, the addressing expression of the GEP cannot be folded into loads or
3458 /// stores that use it. In this case, decompose the GEP and move constant
3459 /// indices into blocks that use it.
3460 static bool OptimizeGEPExpression(GetElementPtrInst *GEPI,
3461 const TargetData *TD) {
3462 // If this GEP is only used inside the block it is defined in, there is no
3463 // need to rewrite it.
3464 bool isUsedOutsideDefBB = false;
3465 BasicBlock *DefBB = GEPI->getParent();
3466 for (Value::use_iterator UI = GEPI->use_begin(), E = GEPI->use_end();
3468 if (cast<Instruction>(*UI)->getParent() != DefBB) {
3469 isUsedOutsideDefBB = true;
3473 if (!isUsedOutsideDefBB) return false;
3475 // If this GEP has no non-zero constant indices, there is nothing we can do,
3477 bool hasConstantIndex = false;
3478 bool hasVariableIndex = false;
3479 for (GetElementPtrInst::op_iterator OI = GEPI->op_begin()+1,
3480 E = GEPI->op_end(); OI != E; ++OI) {
3481 if (ConstantInt *CI = dyn_cast<ConstantInt>(*OI)) {
3482 if (CI->getZExtValue()) {
3483 hasConstantIndex = true;
3487 hasVariableIndex = true;
3491 // If this is a "GEP X, 0, 0, 0", turn this into a cast.
3492 if (!hasConstantIndex && !hasVariableIndex) {
3493 Value *NC = new CastInst(GEPI->getOperand(0), GEPI->getType(),
3494 GEPI->getName(), GEPI);
3495 GEPI->replaceAllUsesWith(NC);
3496 GEPI->eraseFromParent();
3500 // If this is a GEP &Alloca, 0, 0, forward subst the frame index into uses.
3501 if (!hasConstantIndex && !isa<AllocaInst>(GEPI->getOperand(0)))
3504 // Otherwise, decompose the GEP instruction into multiplies and adds. Sum the
3505 // constant offset (which we now know is non-zero) and deal with it later.
3506 uint64_t ConstantOffset = 0;
3507 const Type *UIntPtrTy = TD->getIntPtrType();
3508 Value *Ptr = new CastInst(GEPI->getOperand(0), UIntPtrTy, "", GEPI);
3509 const Type *Ty = GEPI->getOperand(0)->getType();
3511 for (GetElementPtrInst::op_iterator OI = GEPI->op_begin()+1,
3512 E = GEPI->op_end(); OI != E; ++OI) {
3514 if (const StructType *StTy = dyn_cast<StructType>(Ty)) {
3515 unsigned Field = cast<ConstantInt>(Idx)->getZExtValue();
3517 ConstantOffset += TD->getStructLayout(StTy)->MemberOffsets[Field];
3518 Ty = StTy->getElementType(Field);
3520 Ty = cast<SequentialType>(Ty)->getElementType();
3522 // Handle constant subscripts.
3523 if (ConstantInt *CI = dyn_cast<ConstantInt>(Idx)) {
3524 if (CI->getZExtValue() == 0) continue;
3525 if (CI->getType()->isSigned())
3526 ConstantOffset += (int64_t)TD->getTypeSize(Ty)*CI->getSExtValue();
3528 ConstantOffset += TD->getTypeSize(Ty)*CI->getZExtValue();
3532 // Ptr = Ptr + Idx * ElementSize;
3534 // Cast Idx to UIntPtrTy if needed.
3535 Idx = new CastInst(Idx, UIntPtrTy, "", GEPI);
3537 uint64_t ElementSize = TD->getTypeSize(Ty);
3538 // Mask off bits that should not be set.
3539 ElementSize &= ~0ULL >> (64-UIntPtrTy->getPrimitiveSizeInBits());
3540 Constant *SizeCst = ConstantInt::get(UIntPtrTy, ElementSize);
3542 // Multiply by the element size and add to the base.
3543 Idx = BinaryOperator::createMul(Idx, SizeCst, "", GEPI);
3544 Ptr = BinaryOperator::createAdd(Ptr, Idx, "", GEPI);
3548 // Make sure that the offset fits in uintptr_t.
3549 ConstantOffset &= ~0ULL >> (64-UIntPtrTy->getPrimitiveSizeInBits());
3550 Constant *PtrOffset = ConstantInt::get(UIntPtrTy, ConstantOffset);
3552 // Okay, we have now emitted all of the variable index parts to the BB that
3553 // the GEP is defined in. Loop over all of the using instructions, inserting
3554 // an "add Ptr, ConstantOffset" into each block that uses it and update the
3555 // instruction to use the newly computed value, making GEPI dead. When the
3556 // user is a load or store instruction address, we emit the add into the user
3557 // block, otherwise we use a canonical version right next to the gep (these
3558 // won't be foldable as addresses, so we might as well share the computation).
3560 std::map<BasicBlock*,Instruction*> InsertedExprs;
3561 ReplaceUsesOfGEPInst(GEPI, Ptr, PtrOffset, DefBB, GEPI, InsertedExprs);
3563 // Finally, the GEP is dead, remove it.
3564 GEPI->eraseFromParent();
3570 /// SplitEdgeNicely - Split the critical edge from TI to it's specified
3571 /// successor if it will improve codegen. We only do this if the successor has
3572 /// phi nodes (otherwise critical edges are ok). If there is already another
3573 /// predecessor of the succ that is empty (and thus has no phi nodes), use it
3574 /// instead of introducing a new block.
3575 static void SplitEdgeNicely(TerminatorInst *TI, unsigned SuccNum, Pass *P) {
3576 BasicBlock *TIBB = TI->getParent();
3577 BasicBlock *Dest = TI->getSuccessor(SuccNum);
3578 assert(isa<PHINode>(Dest->begin()) &&
3579 "This should only be called if Dest has a PHI!");
3581 /// TIPHIValues - This array is lazily computed to determine the values of
3582 /// PHIs in Dest that TI would provide.
3583 std::vector<Value*> TIPHIValues;
3585 // Check to see if Dest has any blocks that can be used as a split edge for
3587 for (pred_iterator PI = pred_begin(Dest), E = pred_end(Dest); PI != E; ++PI) {
3588 BasicBlock *Pred = *PI;
3589 // To be usable, the pred has to end with an uncond branch to the dest.
3590 BranchInst *PredBr = dyn_cast<BranchInst>(Pred->getTerminator());
3591 if (!PredBr || !PredBr->isUnconditional() ||
3592 // Must be empty other than the branch.
3593 &Pred->front() != PredBr)
3596 // Finally, since we know that Dest has phi nodes in it, we have to make
3597 // sure that jumping to Pred will have the same affect as going to Dest in
3598 // terms of PHI values.
3601 bool FoundMatch = true;
3602 for (BasicBlock::iterator I = Dest->begin();
3603 (PN = dyn_cast<PHINode>(I)); ++I, ++PHINo) {
3604 if (PHINo == TIPHIValues.size())
3605 TIPHIValues.push_back(PN->getIncomingValueForBlock(TIBB));
3607 // If the PHI entry doesn't work, we can't use this pred.
3608 if (TIPHIValues[PHINo] != PN->getIncomingValueForBlock(Pred)) {
3614 // If we found a workable predecessor, change TI to branch to Succ.
3616 Dest->removePredecessor(TIBB);
3617 TI->setSuccessor(SuccNum, Pred);
3622 SplitCriticalEdge(TI, SuccNum, P, true);
3626 bool SelectionDAGISel::runOnFunction(Function &Fn) {
3627 MachineFunction &MF = MachineFunction::construct(&Fn, TLI.getTargetMachine());
3628 RegMap = MF.getSSARegMap();
3629 DEBUG(std::cerr << "\n\n\n=== " << Fn.getName() << "\n");
3631 // First, split all critical edges.
3633 // In this pass we also look for GEP and cast instructions that are used
3634 // across basic blocks and rewrite them to improve basic-block-at-a-time
3637 bool MadeChange = true;
3638 while (MadeChange) {
3640 for (Function::iterator BB = Fn.begin(), E = Fn.end(); BB != E; ++BB) {
3641 // Split all critical edges where the dest block has a PHI.
3642 TerminatorInst *BBTI = BB->getTerminator();
3643 if (BBTI->getNumSuccessors() > 1) {
3644 for (unsigned i = 0, e = BBTI->getNumSuccessors(); i != e; ++i)
3645 if (isa<PHINode>(BBTI->getSuccessor(i)->begin()) &&
3646 isCriticalEdge(BBTI, i, true))
3647 SplitEdgeNicely(BBTI, i, this);
3651 for (BasicBlock::iterator BBI = BB->begin(), E = BB->end(); BBI != E; ) {
3652 Instruction *I = BBI++;
3653 if (GetElementPtrInst *GEPI = dyn_cast<GetElementPtrInst>(I)) {
3654 MadeChange |= OptimizeGEPExpression(GEPI, TLI.getTargetData());
3655 } else if (CastInst *CI = dyn_cast<CastInst>(I)) {
3656 // If the source of the cast is a constant, then this should have
3657 // already been constant folded. The only reason NOT to constant fold
3658 // it is if something (e.g. LSR) was careful to place the constant
3659 // evaluation in a block other than then one that uses it (e.g. to hoist
3660 // the address of globals out of a loop). If this is the case, we don't
3661 // want to forward-subst the cast.
3662 if (isa<Constant>(CI->getOperand(0)))
3665 // If this is a noop copy, sink it into user blocks to reduce the number
3666 // of virtual registers that must be created and coallesced.
3667 MVT::ValueType SrcVT = TLI.getValueType(CI->getOperand(0)->getType());
3668 MVT::ValueType DstVT = TLI.getValueType(CI->getType());
3670 // This is an fp<->int conversion?
3671 if (MVT::isInteger(SrcVT) != MVT::isInteger(DstVT))
3674 // If this is an extension, it will be a zero or sign extension, which
3676 if (SrcVT < DstVT) continue;
3678 // If these values will be promoted, find out what they will be promoted
3679 // to. This helps us consider truncates on PPC as noop copies when they
3681 if (TLI.getTypeAction(SrcVT) == TargetLowering::Promote)
3682 SrcVT = TLI.getTypeToTransformTo(SrcVT);
3683 if (TLI.getTypeAction(DstVT) == TargetLowering::Promote)
3684 DstVT = TLI.getTypeToTransformTo(DstVT);
3686 // If, after promotion, these are the same types, this is a noop copy.
3688 MadeChange |= OptimizeNoopCopyExpression(CI);
3694 FunctionLoweringInfo FuncInfo(TLI, Fn, MF);
3696 for (Function::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I)
3697 SelectBasicBlock(I, MF, FuncInfo);
3702 SDOperand SelectionDAGLowering::CopyValueToVirtualRegister(Value *V,
3704 SDOperand Op = getValue(V);
3705 assert((Op.getOpcode() != ISD::CopyFromReg ||
3706 cast<RegisterSDNode>(Op.getOperand(1))->getReg() != Reg) &&
3707 "Copy from a reg to the same reg!");
3709 // If this type is not legal, we must make sure to not create an invalid
3711 MVT::ValueType SrcVT = Op.getValueType();
3712 MVT::ValueType DestVT = TLI.getTypeToTransformTo(SrcVT);
3713 if (SrcVT == DestVT) {
3714 return DAG.getCopyToReg(getRoot(), Reg, Op);
3715 } else if (SrcVT == MVT::Vector) {
3716 // Handle copies from generic vectors to registers.
3717 MVT::ValueType PTyElementVT, PTyLegalElementVT;
3718 unsigned NE = TLI.getPackedTypeBreakdown(cast<PackedType>(V->getType()),
3719 PTyElementVT, PTyLegalElementVT);
3721 // Insert a VBIT_CONVERT of the input vector to a "N x PTyElementVT"
3722 // MVT::Vector type.
3723 Op = DAG.getNode(ISD::VBIT_CONVERT, MVT::Vector, Op,
3724 DAG.getConstant(NE, MVT::i32),
3725 DAG.getValueType(PTyElementVT));
3727 // Loop over all of the elements of the resultant vector,
3728 // VEXTRACT_VECTOR_ELT'ing them, converting them to PTyLegalElementVT, then
3729 // copying them into output registers.
3730 SmallVector<SDOperand, 8> OutChains;
3731 SDOperand Root = getRoot();
3732 for (unsigned i = 0; i != NE; ++i) {
3733 SDOperand Elt = DAG.getNode(ISD::VEXTRACT_VECTOR_ELT, PTyElementVT,
3734 Op, DAG.getConstant(i, TLI.getPointerTy()));
3735 if (PTyElementVT == PTyLegalElementVT) {
3736 // Elements are legal.
3737 OutChains.push_back(DAG.getCopyToReg(Root, Reg++, Elt));
3738 } else if (PTyLegalElementVT > PTyElementVT) {
3739 // Elements are promoted.
3740 if (MVT::isFloatingPoint(PTyLegalElementVT))
3741 Elt = DAG.getNode(ISD::FP_EXTEND, PTyLegalElementVT, Elt);
3743 Elt = DAG.getNode(ISD::ANY_EXTEND, PTyLegalElementVT, Elt);
3744 OutChains.push_back(DAG.getCopyToReg(Root, Reg++, Elt));
3746 // Elements are expanded.
3747 // The src value is expanded into multiple registers.
3748 SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, PTyLegalElementVT,
3749 Elt, DAG.getConstant(0, TLI.getPointerTy()));
3750 SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, PTyLegalElementVT,
3751 Elt, DAG.getConstant(1, TLI.getPointerTy()));
3752 OutChains.push_back(DAG.getCopyToReg(Root, Reg++, Lo));
3753 OutChains.push_back(DAG.getCopyToReg(Root, Reg++, Hi));
3756 return DAG.getNode(ISD::TokenFactor, MVT::Other,
3757 &OutChains[0], OutChains.size());
3758 } else if (SrcVT < DestVT) {
3759 // The src value is promoted to the register.
3760 if (MVT::isFloatingPoint(SrcVT))
3761 Op = DAG.getNode(ISD::FP_EXTEND, DestVT, Op);
3763 Op = DAG.getNode(ISD::ANY_EXTEND, DestVT, Op);
3764 return DAG.getCopyToReg(getRoot(), Reg, Op);
3766 // The src value is expanded into multiple registers.
3767 SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, DestVT,
3768 Op, DAG.getConstant(0, TLI.getPointerTy()));
3769 SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, DestVT,
3770 Op, DAG.getConstant(1, TLI.getPointerTy()));
3771 Op = DAG.getCopyToReg(getRoot(), Reg, Lo);
3772 return DAG.getCopyToReg(Op, Reg+1, Hi);
3776 void SelectionDAGISel::
3777 LowerArguments(BasicBlock *BB, SelectionDAGLowering &SDL,
3778 std::vector<SDOperand> &UnorderedChains) {
3779 // If this is the entry block, emit arguments.
3780 Function &F = *BB->getParent();
3781 FunctionLoweringInfo &FuncInfo = SDL.FuncInfo;
3782 SDOperand OldRoot = SDL.DAG.getRoot();
3783 std::vector<SDOperand> Args = TLI.LowerArguments(F, SDL.DAG);
3786 for (Function::arg_iterator AI = F.arg_begin(), E = F.arg_end();
3788 if (!AI->use_empty()) {
3789 SDL.setValue(AI, Args[a]);
3791 // If this argument is live outside of the entry block, insert a copy from
3792 // whereever we got it to the vreg that other BB's will reference it as.
3793 if (FuncInfo.ValueMap.count(AI)) {
3795 SDL.CopyValueToVirtualRegister(AI, FuncInfo.ValueMap[AI]);
3796 UnorderedChains.push_back(Copy);
3800 // Finally, if the target has anything special to do, allow it to do so.
3801 // FIXME: this should insert code into the DAG!
3802 EmitFunctionEntryCode(F, SDL.DAG.getMachineFunction());
3805 void SelectionDAGISel::BuildSelectionDAG(SelectionDAG &DAG, BasicBlock *LLVMBB,
3806 std::vector<std::pair<MachineInstr*, unsigned> > &PHINodesToUpdate,
3807 FunctionLoweringInfo &FuncInfo) {
3808 SelectionDAGLowering SDL(DAG, TLI, FuncInfo);
3810 std::vector<SDOperand> UnorderedChains;
3812 // Lower any arguments needed in this block if this is the entry block.
3813 if (LLVMBB == &LLVMBB->getParent()->front())
3814 LowerArguments(LLVMBB, SDL, UnorderedChains);
3816 BB = FuncInfo.MBBMap[LLVMBB];
3817 SDL.setCurrentBasicBlock(BB);
3819 // Lower all of the non-terminator instructions.
3820 for (BasicBlock::iterator I = LLVMBB->begin(), E = --LLVMBB->end();
3824 // Ensure that all instructions which are used outside of their defining
3825 // blocks are available as virtual registers.
3826 for (BasicBlock::iterator I = LLVMBB->begin(), E = LLVMBB->end(); I != E;++I)
3827 if (!I->use_empty() && !isa<PHINode>(I)) {
3828 std::map<const Value*, unsigned>::iterator VMI =FuncInfo.ValueMap.find(I);
3829 if (VMI != FuncInfo.ValueMap.end())
3830 UnorderedChains.push_back(
3831 SDL.CopyValueToVirtualRegister(I, VMI->second));
3834 // Handle PHI nodes in successor blocks. Emit code into the SelectionDAG to
3835 // ensure constants are generated when needed. Remember the virtual registers
3836 // that need to be added to the Machine PHI nodes as input. We cannot just
3837 // directly add them, because expansion might result in multiple MBB's for one
3838 // BB. As such, the start of the BB might correspond to a different MBB than
3841 TerminatorInst *TI = LLVMBB->getTerminator();
3843 // Emit constants only once even if used by multiple PHI nodes.
3844 std::map<Constant*, unsigned> ConstantsOut;
3846 // Vector bool would be better, but vector<bool> is really slow.
3847 std::vector<unsigned char> SuccsHandled;
3848 if (TI->getNumSuccessors())
3849 SuccsHandled.resize(BB->getParent()->getNumBlockIDs());
3851 // Check successor nodes PHI nodes that expect a constant to be available from
3853 for (unsigned succ = 0, e = TI->getNumSuccessors(); succ != e; ++succ) {
3854 BasicBlock *SuccBB = TI->getSuccessor(succ);
3855 if (!isa<PHINode>(SuccBB->begin())) continue;
3856 MachineBasicBlock *SuccMBB = FuncInfo.MBBMap[SuccBB];
3858 // If this terminator has multiple identical successors (common for
3859 // switches), only handle each succ once.
3860 unsigned SuccMBBNo = SuccMBB->getNumber();
3861 if (SuccsHandled[SuccMBBNo]) continue;
3862 SuccsHandled[SuccMBBNo] = true;
3864 MachineBasicBlock::iterator MBBI = SuccMBB->begin();
3867 // At this point we know that there is a 1-1 correspondence between LLVM PHI
3868 // nodes and Machine PHI nodes, but the incoming operands have not been
3870 for (BasicBlock::iterator I = SuccBB->begin();
3871 (PN = dyn_cast<PHINode>(I)); ++I) {
3872 // Ignore dead phi's.
3873 if (PN->use_empty()) continue;
3876 Value *PHIOp = PN->getIncomingValueForBlock(LLVMBB);
3877 if (Constant *C = dyn_cast<Constant>(PHIOp)) {
3878 unsigned &RegOut = ConstantsOut[C];
3880 RegOut = FuncInfo.CreateRegForValue(C);
3881 UnorderedChains.push_back(
3882 SDL.CopyValueToVirtualRegister(C, RegOut));
3886 Reg = FuncInfo.ValueMap[PHIOp];
3888 assert(isa<AllocaInst>(PHIOp) &&
3889 FuncInfo.StaticAllocaMap.count(cast<AllocaInst>(PHIOp)) &&
3890 "Didn't codegen value into a register!??");
3891 Reg = FuncInfo.CreateRegForValue(PHIOp);
3892 UnorderedChains.push_back(
3893 SDL.CopyValueToVirtualRegister(PHIOp, Reg));
3897 // Remember that this register needs to added to the machine PHI node as
3898 // the input for this MBB.
3899 MVT::ValueType VT = TLI.getValueType(PN->getType());
3900 unsigned NumElements;
3901 if (VT != MVT::Vector)
3902 NumElements = TLI.getNumElements(VT);
3904 MVT::ValueType VT1,VT2;
3906 TLI.getPackedTypeBreakdown(cast<PackedType>(PN->getType()),
3909 for (unsigned i = 0, e = NumElements; i != e; ++i)
3910 PHINodesToUpdate.push_back(std::make_pair(MBBI++, Reg+i));
3913 ConstantsOut.clear();
3915 // Turn all of the unordered chains into one factored node.
3916 if (!UnorderedChains.empty()) {
3917 SDOperand Root = SDL.getRoot();
3918 if (Root.getOpcode() != ISD::EntryToken) {
3919 unsigned i = 0, e = UnorderedChains.size();
3920 for (; i != e; ++i) {
3921 assert(UnorderedChains[i].Val->getNumOperands() > 1);
3922 if (UnorderedChains[i].Val->getOperand(0) == Root)
3923 break; // Don't add the root if we already indirectly depend on it.
3927 UnorderedChains.push_back(Root);
3929 DAG.setRoot(DAG.getNode(ISD::TokenFactor, MVT::Other,
3930 &UnorderedChains[0], UnorderedChains.size()));
3933 // Lower the terminator after the copies are emitted.
3934 SDL.visit(*LLVMBB->getTerminator());
3936 // Copy over any CaseBlock records that may now exist due to SwitchInst
3937 // lowering, as well as any jump table information.
3938 SwitchCases.clear();
3939 SwitchCases = SDL.SwitchCases;
3942 // Make sure the root of the DAG is up-to-date.
3943 DAG.setRoot(SDL.getRoot());
3946 void SelectionDAGISel::CodeGenAndEmitDAG(SelectionDAG &DAG) {
3947 // Get alias analysis for load/store combining.
3948 AliasAnalysis &AA = getAnalysis<AliasAnalysis>();
3950 // Run the DAG combiner in pre-legalize mode.
3951 DAG.Combine(false, AA);
3953 DEBUG(std::cerr << "Lowered selection DAG:\n");
3956 // Second step, hack on the DAG until it only uses operations and types that
3957 // the target supports.
3960 DEBUG(std::cerr << "Legalized selection DAG:\n");
3963 // Run the DAG combiner in post-legalize mode.
3964 DAG.Combine(true, AA);
3966 if (ViewISelDAGs) DAG.viewGraph();
3968 // Third, instruction select all of the operations to machine code, adding the
3969 // code to the MachineBasicBlock.
3970 InstructionSelectBasicBlock(DAG);
3972 DEBUG(std::cerr << "Selected machine code:\n");
3976 void SelectionDAGISel::SelectBasicBlock(BasicBlock *LLVMBB, MachineFunction &MF,
3977 FunctionLoweringInfo &FuncInfo) {
3978 std::vector<std::pair<MachineInstr*, unsigned> > PHINodesToUpdate;
3980 SelectionDAG DAG(TLI, MF, getAnalysisToUpdate<MachineDebugInfo>());
3983 // First step, lower LLVM code to some DAG. This DAG may use operations and
3984 // types that are not supported by the target.
3985 BuildSelectionDAG(DAG, LLVMBB, PHINodesToUpdate, FuncInfo);
3987 // Second step, emit the lowered DAG as machine code.
3988 CodeGenAndEmitDAG(DAG);
3991 // Next, now that we know what the last MBB the LLVM BB expanded is, update
3992 // PHI nodes in successors.
3993 if (SwitchCases.empty() && JT.Reg == 0) {
3994 for (unsigned i = 0, e = PHINodesToUpdate.size(); i != e; ++i) {
3995 MachineInstr *PHI = PHINodesToUpdate[i].first;
3996 assert(PHI->getOpcode() == TargetInstrInfo::PHI &&
3997 "This is not a machine PHI node that we are updating!");
3998 PHI->addRegOperand(PHINodesToUpdate[i].second, false);
3999 PHI->addMachineBasicBlockOperand(BB);
4004 // If the JumpTable record is filled in, then we need to emit a jump table.
4005 // Updating the PHI nodes is tricky in this case, since we need to determine
4006 // whether the PHI is a successor of the range check MBB or the jump table MBB
4008 assert(SwitchCases.empty() && "Cannot have jump table and lowered switch");
4009 SelectionDAG SDAG(TLI, MF, getAnalysisToUpdate<MachineDebugInfo>());
4011 SelectionDAGLowering SDL(SDAG, TLI, FuncInfo);
4012 MachineBasicBlock *RangeBB = BB;
4013 // Set the current basic block to the mbb we wish to insert the code into
4015 SDL.setCurrentBasicBlock(BB);
4017 SDL.visitJumpTable(JT);
4018 SDAG.setRoot(SDL.getRoot());
4019 CodeGenAndEmitDAG(SDAG);
4021 for (unsigned pi = 0, pe = PHINodesToUpdate.size(); pi != pe; ++pi) {
4022 MachineInstr *PHI = PHINodesToUpdate[pi].first;
4023 MachineBasicBlock *PHIBB = PHI->getParent();
4024 assert(PHI->getOpcode() == TargetInstrInfo::PHI &&
4025 "This is not a machine PHI node that we are updating!");
4026 if (PHIBB == JT.Default) {
4027 PHI->addRegOperand(PHINodesToUpdate[pi].second, false);
4028 PHI->addMachineBasicBlockOperand(RangeBB);
4030 if (BB->succ_end() != std::find(BB->succ_begin(),BB->succ_end(), PHIBB)) {
4031 PHI->addRegOperand(PHINodesToUpdate[pi].second, false);
4032 PHI->addMachineBasicBlockOperand(BB);
4038 // If the switch block involved a branch to one of the actual successors, we
4039 // need to update PHI nodes in that block.
4040 for (unsigned i = 0, e = PHINodesToUpdate.size(); i != e; ++i) {
4041 MachineInstr *PHI = PHINodesToUpdate[i].first;
4042 assert(PHI->getOpcode() == TargetInstrInfo::PHI &&
4043 "This is not a machine PHI node that we are updating!");
4044 if (BB->isSuccessor(PHI->getParent())) {
4045 PHI->addRegOperand(PHINodesToUpdate[i].second, false);
4046 PHI->addMachineBasicBlockOperand(BB);
4050 // If we generated any switch lowering information, build and codegen any
4051 // additional DAGs necessary.
4052 for (unsigned i = 0, e = SwitchCases.size(); i != e; ++i) {
4053 SelectionDAG SDAG(TLI, MF, getAnalysisToUpdate<MachineDebugInfo>());
4055 SelectionDAGLowering SDL(SDAG, TLI, FuncInfo);
4057 // Set the current basic block to the mbb we wish to insert the code into
4058 BB = SwitchCases[i].ThisBB;
4059 SDL.setCurrentBasicBlock(BB);
4062 SDL.visitSwitchCase(SwitchCases[i]);
4063 SDAG.setRoot(SDL.getRoot());
4064 CodeGenAndEmitDAG(SDAG);
4066 // Handle any PHI nodes in successors of this chunk, as if we were coming
4067 // from the original BB before switch expansion. Note that PHI nodes can
4068 // occur multiple times in PHINodesToUpdate. We have to be very careful to
4069 // handle them the right number of times.
4070 while ((BB = SwitchCases[i].TrueBB)) { // Handle LHS and RHS.
4071 for (MachineBasicBlock::iterator Phi = BB->begin();
4072 Phi != BB->end() && Phi->getOpcode() == TargetInstrInfo::PHI; ++Phi){
4073 // This value for this PHI node is recorded in PHINodesToUpdate, get it.
4074 for (unsigned pn = 0; ; ++pn) {
4075 assert(pn != PHINodesToUpdate.size() && "Didn't find PHI entry!");
4076 if (PHINodesToUpdate[pn].first == Phi) {
4077 Phi->addRegOperand(PHINodesToUpdate[pn].second, false);
4078 Phi->addMachineBasicBlockOperand(SwitchCases[i].ThisBB);
4084 // Don't process RHS if same block as LHS.
4085 if (BB == SwitchCases[i].FalseBB)
4086 SwitchCases[i].FalseBB = 0;
4088 // If we haven't handled the RHS, do so now. Otherwise, we're done.
4089 SwitchCases[i].TrueBB = SwitchCases[i].FalseBB;
4090 SwitchCases[i].FalseBB = 0;
4092 assert(SwitchCases[i].TrueBB == 0 && SwitchCases[i].FalseBB == 0);
4097 //===----------------------------------------------------------------------===//
4098 /// ScheduleAndEmitDAG - Pick a safe ordering and emit instructions for each
4099 /// target node in the graph.
4100 void SelectionDAGISel::ScheduleAndEmitDAG(SelectionDAG &DAG) {
4101 if (ViewSchedDAGs) DAG.viewGraph();
4103 RegisterScheduler::FunctionPassCtor Ctor = RegisterScheduler::getDefault();
4107 RegisterScheduler::setDefault(Ctor);
4110 ScheduleDAG *SL = Ctor(this, &DAG, BB);
4116 HazardRecognizer *SelectionDAGISel::CreateTargetHazardRecognizer() {
4117 return new HazardRecognizer();
4120 //===----------------------------------------------------------------------===//
4121 // Helper functions used by the generated instruction selector.
4122 //===----------------------------------------------------------------------===//
4123 // Calls to these methods are generated by tblgen.
4125 /// CheckAndMask - The isel is trying to match something like (and X, 255). If
4126 /// the dag combiner simplified the 255, we still want to match. RHS is the
4127 /// actual value in the DAG on the RHS of an AND, and DesiredMaskS is the value
4128 /// specified in the .td file (e.g. 255).
4129 bool SelectionDAGISel::CheckAndMask(SDOperand LHS, ConstantSDNode *RHS,
4130 int64_t DesiredMaskS) {
4131 uint64_t ActualMask = RHS->getValue();
4132 uint64_t DesiredMask =DesiredMaskS & MVT::getIntVTBitMask(LHS.getValueType());
4134 // If the actual mask exactly matches, success!
4135 if (ActualMask == DesiredMask)
4138 // If the actual AND mask is allowing unallowed bits, this doesn't match.
4139 if (ActualMask & ~DesiredMask)
4142 // Otherwise, the DAG Combiner may have proven that the value coming in is
4143 // either already zero or is not demanded. Check for known zero input bits.
4144 uint64_t NeededMask = DesiredMask & ~ActualMask;
4145 if (getTargetLowering().MaskedValueIsZero(LHS, NeededMask))
4148 // TODO: check to see if missing bits are just not demanded.
4150 // Otherwise, this pattern doesn't match.
4154 /// CheckOrMask - The isel is trying to match something like (or X, 255). If
4155 /// the dag combiner simplified the 255, we still want to match. RHS is the
4156 /// actual value in the DAG on the RHS of an OR, and DesiredMaskS is the value
4157 /// specified in the .td file (e.g. 255).
4158 bool SelectionDAGISel::CheckOrMask(SDOperand LHS, ConstantSDNode *RHS,
4159 int64_t DesiredMaskS) {
4160 uint64_t ActualMask = RHS->getValue();
4161 uint64_t DesiredMask =DesiredMaskS & MVT::getIntVTBitMask(LHS.getValueType());
4163 // If the actual mask exactly matches, success!
4164 if (ActualMask == DesiredMask)
4167 // If the actual AND mask is allowing unallowed bits, this doesn't match.
4168 if (ActualMask & ~DesiredMask)
4171 // Otherwise, the DAG Combiner may have proven that the value coming in is
4172 // either already zero or is not demanded. Check for known zero input bits.
4173 uint64_t NeededMask = DesiredMask & ~ActualMask;
4175 uint64_t KnownZero, KnownOne;
4176 getTargetLowering().ComputeMaskedBits(LHS, NeededMask, KnownZero, KnownOne);
4178 // If all the missing bits in the or are already known to be set, match!
4179 if ((NeededMask & KnownOne) == NeededMask)
4182 // TODO: check to see if missing bits are just not demanded.
4184 // Otherwise, this pattern doesn't match.
4189 /// SelectInlineAsmMemoryOperands - Calls to this are automatically generated
4190 /// by tblgen. Others should not call it.
4191 void SelectionDAGISel::
4192 SelectInlineAsmMemoryOperands(std::vector<SDOperand> &Ops, SelectionDAG &DAG) {
4193 std::vector<SDOperand> InOps;
4194 std::swap(InOps, Ops);
4196 Ops.push_back(InOps[0]); // input chain.
4197 Ops.push_back(InOps[1]); // input asm string.
4199 unsigned i = 2, e = InOps.size();
4200 if (InOps[e-1].getValueType() == MVT::Flag)
4201 --e; // Don't process a flag operand if it is here.
4204 unsigned Flags = cast<ConstantSDNode>(InOps[i])->getValue();
4205 if ((Flags & 7) != 4 /*MEM*/) {
4206 // Just skip over this operand, copying the operands verbatim.
4207 Ops.insert(Ops.end(), InOps.begin()+i, InOps.begin()+i+(Flags >> 3) + 1);
4208 i += (Flags >> 3) + 1;
4210 assert((Flags >> 3) == 1 && "Memory operand with multiple values?");
4211 // Otherwise, this is a memory operand. Ask the target to select it.
4212 std::vector<SDOperand> SelOps;
4213 if (SelectInlineAsmMemoryOperand(InOps[i+1], 'm', SelOps, DAG)) {
4214 std::cerr << "Could not match memory address. Inline asm failure!\n";
4218 // Add this to the output node.
4219 Ops.push_back(DAG.getConstant(4/*MEM*/ | (SelOps.size() << 3), MVT::i32));
4220 Ops.insert(Ops.end(), SelOps.begin(), SelOps.end());
4225 // Add the flag input back if present.
4226 if (e != InOps.size())
4227 Ops.push_back(InOps.back());