1 //===-- SelectionDAGISel.cpp - Implement the SelectionDAGISel class -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements the SelectionDAGISel class.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "isel"
15 #include "llvm/ADT/BitVector.h"
16 #include "llvm/Analysis/AliasAnalysis.h"
17 #include "llvm/CodeGen/SelectionDAGISel.h"
18 #include "llvm/CodeGen/ScheduleDAG.h"
19 #include "llvm/Constants.h"
20 #include "llvm/CallingConv.h"
21 #include "llvm/DerivedTypes.h"
22 #include "llvm/Function.h"
23 #include "llvm/GlobalVariable.h"
24 #include "llvm/InlineAsm.h"
25 #include "llvm/Instructions.h"
26 #include "llvm/Intrinsics.h"
27 #include "llvm/IntrinsicInst.h"
28 #include "llvm/ParameterAttributes.h"
29 #include "llvm/CodeGen/Collector.h"
30 #include "llvm/CodeGen/MachineFunction.h"
31 #include "llvm/CodeGen/MachineFrameInfo.h"
32 #include "llvm/CodeGen/MachineInstrBuilder.h"
33 #include "llvm/CodeGen/MachineJumpTableInfo.h"
34 #include "llvm/CodeGen/MachineModuleInfo.h"
35 #include "llvm/CodeGen/MachineRegisterInfo.h"
36 #include "llvm/CodeGen/SchedulerRegistry.h"
37 #include "llvm/CodeGen/SelectionDAG.h"
38 #include "llvm/Target/TargetRegisterInfo.h"
39 #include "llvm/Target/TargetData.h"
40 #include "llvm/Target/TargetFrameInfo.h"
41 #include "llvm/Target/TargetInstrInfo.h"
42 #include "llvm/Target/TargetLowering.h"
43 #include "llvm/Target/TargetMachine.h"
44 #include "llvm/Target/TargetOptions.h"
45 #include "llvm/Support/MathExtras.h"
46 #include "llvm/Support/Debug.h"
47 #include "llvm/Support/Compiler.h"
53 ViewISelDAGs("view-isel-dags", cl::Hidden,
54 cl::desc("Pop up a window to show isel dags as they are selected"));
56 ViewSchedDAGs("view-sched-dags", cl::Hidden,
57 cl::desc("Pop up a window to show sched dags as they are processed"));
59 ViewSUnitDAGs("view-sunit-dags", cl::Hidden,
60 cl::desc("Pop up a window to show SUnit dags after they are processed"));
62 static const bool ViewISelDAGs = 0, ViewSchedDAGs = 0, ViewSUnitDAGs = 0;
65 //===---------------------------------------------------------------------===//
67 /// RegisterScheduler class - Track the registration of instruction schedulers.
69 //===---------------------------------------------------------------------===//
70 MachinePassRegistry RegisterScheduler::Registry;
72 //===---------------------------------------------------------------------===//
74 /// ISHeuristic command line option for instruction schedulers.
76 //===---------------------------------------------------------------------===//
78 cl::opt<RegisterScheduler::FunctionPassCtor, false,
79 RegisterPassParser<RegisterScheduler> >
80 ISHeuristic("pre-RA-sched",
81 cl::init(&createDefaultScheduler),
82 cl::desc("Instruction schedulers available (before register"
85 static RegisterScheduler
86 defaultListDAGScheduler("default", " Best scheduler for the target",
87 createDefaultScheduler);
90 namespace { struct AsmOperandInfo; }
93 /// RegsForValue - This struct represents the physical registers that a
94 /// particular value is assigned and the type information about the value.
95 /// This is needed because values can be promoted into larger registers and
96 /// expanded into multiple smaller registers than the value.
97 struct VISIBILITY_HIDDEN RegsForValue {
98 /// Regs - This list holds the register (for legal and promoted values)
99 /// or register set (for expanded values) that the value should be assigned
101 std::vector<unsigned> Regs;
103 /// RegVT - The value type of each register.
105 MVT::ValueType RegVT;
107 /// ValueVT - The value type of the LLVM value, which may be promoted from
108 /// RegVT or made from merging the two expanded parts.
109 MVT::ValueType ValueVT;
111 RegsForValue() : RegVT(MVT::Other), ValueVT(MVT::Other) {}
113 RegsForValue(unsigned Reg, MVT::ValueType regvt, MVT::ValueType valuevt)
114 : RegVT(regvt), ValueVT(valuevt) {
117 RegsForValue(const std::vector<unsigned> ®s,
118 MVT::ValueType regvt, MVT::ValueType valuevt)
119 : Regs(regs), RegVT(regvt), ValueVT(valuevt) {
122 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from
123 /// this value and returns the result as a ValueVT value. This uses
124 /// Chain/Flag as the input and updates them for the output Chain/Flag.
125 /// If the Flag pointer is NULL, no flag is used.
126 SDOperand getCopyFromRegs(SelectionDAG &DAG,
127 SDOperand &Chain, SDOperand *Flag) const;
129 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
130 /// specified value into the registers specified by this object. This uses
131 /// Chain/Flag as the input and updates them for the output Chain/Flag.
132 /// If the Flag pointer is NULL, no flag is used.
133 void getCopyToRegs(SDOperand Val, SelectionDAG &DAG,
134 SDOperand &Chain, SDOperand *Flag) const;
136 /// AddInlineAsmOperands - Add this value to the specified inlineasm node
137 /// operand list. This adds the code marker and includes the number of
138 /// values added into it.
139 void AddInlineAsmOperands(unsigned Code, SelectionDAG &DAG,
140 std::vector<SDOperand> &Ops) const;
145 //===--------------------------------------------------------------------===//
146 /// createDefaultScheduler - This creates an instruction scheduler appropriate
148 ScheduleDAG* createDefaultScheduler(SelectionDAGISel *IS,
150 MachineBasicBlock *BB) {
151 TargetLowering &TLI = IS->getTargetLowering();
153 if (TLI.getSchedulingPreference() == TargetLowering::SchedulingForLatency) {
154 return createTDListDAGScheduler(IS, DAG, BB);
156 assert(TLI.getSchedulingPreference() ==
157 TargetLowering::SchedulingForRegPressure && "Unknown sched type!");
158 return createBURRListDAGScheduler(IS, DAG, BB);
163 //===--------------------------------------------------------------------===//
164 /// FunctionLoweringInfo - This contains information that is global to a
165 /// function that is used when lowering a region of the function.
166 class FunctionLoweringInfo {
171 MachineRegisterInfo &RegInfo;
173 FunctionLoweringInfo(TargetLowering &TLI, Function &Fn,MachineFunction &MF);
175 /// MBBMap - A mapping from LLVM basic blocks to their machine code entry.
176 std::map<const BasicBlock*, MachineBasicBlock *> MBBMap;
178 /// ValueMap - Since we emit code for the function a basic block at a time,
179 /// we must remember which virtual registers hold the values for
180 /// cross-basic-block values.
181 DenseMap<const Value*, unsigned> ValueMap;
183 /// StaticAllocaMap - Keep track of frame indices for fixed sized allocas in
184 /// the entry block. This allows the allocas to be efficiently referenced
185 /// anywhere in the function.
186 std::map<const AllocaInst*, int> StaticAllocaMap;
189 SmallSet<Instruction*, 8> CatchInfoLost;
190 SmallSet<Instruction*, 8> CatchInfoFound;
193 unsigned MakeReg(MVT::ValueType VT) {
194 return RegInfo.createVirtualRegister(TLI.getRegClassFor(VT));
197 /// isExportedInst - Return true if the specified value is an instruction
198 /// exported from its block.
199 bool isExportedInst(const Value *V) {
200 return ValueMap.count(V);
203 unsigned CreateRegForValue(const Value *V);
205 unsigned InitializeRegForValue(const Value *V) {
206 unsigned &R = ValueMap[V];
207 assert(R == 0 && "Already initialized this value register!");
208 return R = CreateRegForValue(V);
213 /// isSelector - Return true if this instruction is a call to the
214 /// eh.selector intrinsic.
215 static bool isSelector(Instruction *I) {
216 if (IntrinsicInst *II = dyn_cast<IntrinsicInst>(I))
217 return (II->getIntrinsicID() == Intrinsic::eh_selector_i32 ||
218 II->getIntrinsicID() == Intrinsic::eh_selector_i64);
222 /// isUsedOutsideOfDefiningBlock - Return true if this instruction is used by
223 /// PHI nodes or outside of the basic block that defines it, or used by a
224 /// switch instruction, which may expand to multiple basic blocks.
225 static bool isUsedOutsideOfDefiningBlock(Instruction *I) {
226 if (isa<PHINode>(I)) return true;
227 BasicBlock *BB = I->getParent();
228 for (Value::use_iterator UI = I->use_begin(), E = I->use_end(); UI != E; ++UI)
229 if (cast<Instruction>(*UI)->getParent() != BB || isa<PHINode>(*UI) ||
230 // FIXME: Remove switchinst special case.
231 isa<SwitchInst>(*UI))
236 /// isOnlyUsedInEntryBlock - If the specified argument is only used in the
237 /// entry block, return true. This includes arguments used by switches, since
238 /// the switch may expand into multiple basic blocks.
239 static bool isOnlyUsedInEntryBlock(Argument *A) {
240 BasicBlock *Entry = A->getParent()->begin();
241 for (Value::use_iterator UI = A->use_begin(), E = A->use_end(); UI != E; ++UI)
242 if (cast<Instruction>(*UI)->getParent() != Entry || isa<SwitchInst>(*UI))
243 return false; // Use not in entry block.
247 FunctionLoweringInfo::FunctionLoweringInfo(TargetLowering &tli,
248 Function &fn, MachineFunction &mf)
249 : TLI(tli), Fn(fn), MF(mf), RegInfo(MF.getRegInfo()) {
251 // Create a vreg for each argument register that is not dead and is used
252 // outside of the entry block for the function.
253 for (Function::arg_iterator AI = Fn.arg_begin(), E = Fn.arg_end();
255 if (!isOnlyUsedInEntryBlock(AI))
256 InitializeRegForValue(AI);
258 // Initialize the mapping of values to registers. This is only set up for
259 // instruction values that are used outside of the block that defines
261 Function::iterator BB = Fn.begin(), EB = Fn.end();
262 for (BasicBlock::iterator I = BB->begin(), E = BB->end(); I != E; ++I)
263 if (AllocaInst *AI = dyn_cast<AllocaInst>(I))
264 if (ConstantInt *CUI = dyn_cast<ConstantInt>(AI->getArraySize())) {
265 const Type *Ty = AI->getAllocatedType();
266 uint64_t TySize = TLI.getTargetData()->getABITypeSize(Ty);
268 std::max((unsigned)TLI.getTargetData()->getPrefTypeAlignment(Ty),
271 TySize *= CUI->getZExtValue(); // Get total allocated size.
272 if (TySize == 0) TySize = 1; // Don't create zero-sized stack objects.
273 StaticAllocaMap[AI] =
274 MF.getFrameInfo()->CreateStackObject(TySize, Align);
277 for (; BB != EB; ++BB)
278 for (BasicBlock::iterator I = BB->begin(), E = BB->end(); I != E; ++I)
279 if (!I->use_empty() && isUsedOutsideOfDefiningBlock(I))
280 if (!isa<AllocaInst>(I) ||
281 !StaticAllocaMap.count(cast<AllocaInst>(I)))
282 InitializeRegForValue(I);
284 // Create an initial MachineBasicBlock for each LLVM BasicBlock in F. This
285 // also creates the initial PHI MachineInstrs, though none of the input
286 // operands are populated.
287 for (BB = Fn.begin(), EB = Fn.end(); BB != EB; ++BB) {
288 MachineBasicBlock *MBB = new MachineBasicBlock(BB);
290 MF.getBasicBlockList().push_back(MBB);
292 // Create Machine PHI nodes for LLVM PHI nodes, lowering them as
295 for (BasicBlock::iterator I = BB->begin();(PN = dyn_cast<PHINode>(I)); ++I){
296 if (PN->use_empty()) continue;
298 MVT::ValueType VT = TLI.getValueType(PN->getType());
299 unsigned NumRegisters = TLI.getNumRegisters(VT);
300 unsigned PHIReg = ValueMap[PN];
301 assert(PHIReg && "PHI node does not have an assigned virtual register!");
302 const TargetInstrInfo *TII = TLI.getTargetMachine().getInstrInfo();
303 for (unsigned i = 0; i != NumRegisters; ++i)
304 BuildMI(MBB, TII->get(TargetInstrInfo::PHI), PHIReg+i);
309 /// CreateRegForValue - Allocate the appropriate number of virtual registers of
310 /// the correctly promoted or expanded types. Assign these registers
311 /// consecutive vreg numbers and return the first assigned number.
312 unsigned FunctionLoweringInfo::CreateRegForValue(const Value *V) {
313 MVT::ValueType VT = TLI.getValueType(V->getType());
315 unsigned NumRegisters = TLI.getNumRegisters(VT);
316 MVT::ValueType RegisterVT = TLI.getRegisterType(VT);
318 unsigned R = MakeReg(RegisterVT);
319 for (unsigned i = 1; i != NumRegisters; ++i)
325 //===----------------------------------------------------------------------===//
326 /// SelectionDAGLowering - This is the common target-independent lowering
327 /// implementation that is parameterized by a TargetLowering object.
328 /// Also, targets can overload any lowering method.
331 class SelectionDAGLowering {
332 MachineBasicBlock *CurMBB;
334 DenseMap<const Value*, SDOperand> NodeMap;
336 /// PendingLoads - Loads are not emitted to the program immediately. We bunch
337 /// them up and then emit token factor nodes when possible. This allows us to
338 /// get simple disambiguation between loads without worrying about alias
340 std::vector<SDOperand> PendingLoads;
342 /// Case - A struct to record the Value for a switch case, and the
343 /// case's target basic block.
347 MachineBasicBlock* BB;
349 Case() : Low(0), High(0), BB(0) { }
350 Case(Constant* low, Constant* high, MachineBasicBlock* bb) :
351 Low(low), High(high), BB(bb) { }
352 uint64_t size() const {
353 uint64_t rHigh = cast<ConstantInt>(High)->getSExtValue();
354 uint64_t rLow = cast<ConstantInt>(Low)->getSExtValue();
355 return (rHigh - rLow + 1ULL);
361 MachineBasicBlock* BB;
364 CaseBits(uint64_t mask, MachineBasicBlock* bb, unsigned bits):
365 Mask(mask), BB(bb), Bits(bits) { }
368 typedef std::vector<Case> CaseVector;
369 typedef std::vector<CaseBits> CaseBitsVector;
370 typedef CaseVector::iterator CaseItr;
371 typedef std::pair<CaseItr, CaseItr> CaseRange;
373 /// CaseRec - A struct with ctor used in lowering switches to a binary tree
374 /// of conditional branches.
376 CaseRec(MachineBasicBlock *bb, Constant *lt, Constant *ge, CaseRange r) :
377 CaseBB(bb), LT(lt), GE(ge), Range(r) {}
379 /// CaseBB - The MBB in which to emit the compare and branch
380 MachineBasicBlock *CaseBB;
381 /// LT, GE - If nonzero, we know the current case value must be less-than or
382 /// greater-than-or-equal-to these Constants.
385 /// Range - A pair of iterators representing the range of case values to be
386 /// processed at this point in the binary search tree.
390 typedef std::vector<CaseRec> CaseRecVector;
392 /// The comparison function for sorting the switch case values in the vector.
393 /// WARNING: Case ranges should be disjoint!
395 bool operator () (const Case& C1, const Case& C2) {
396 assert(isa<ConstantInt>(C1.Low) && isa<ConstantInt>(C2.High));
397 const ConstantInt* CI1 = cast<const ConstantInt>(C1.Low);
398 const ConstantInt* CI2 = cast<const ConstantInt>(C2.High);
399 return CI1->getValue().slt(CI2->getValue());
404 bool operator () (const CaseBits& C1, const CaseBits& C2) {
405 return C1.Bits > C2.Bits;
409 unsigned Clusterify(CaseVector& Cases, const SwitchInst &SI);
412 // TLI - This is information that describes the available target features we
413 // need for lowering. This indicates when operations are unavailable,
414 // implemented with a libcall, etc.
417 const TargetData *TD;
420 /// SwitchCases - Vector of CaseBlock structures used to communicate
421 /// SwitchInst code generation information.
422 std::vector<SelectionDAGISel::CaseBlock> SwitchCases;
423 /// JTCases - Vector of JumpTable structures used to communicate
424 /// SwitchInst code generation information.
425 std::vector<SelectionDAGISel::JumpTableBlock> JTCases;
426 std::vector<SelectionDAGISel::BitTestBlock> BitTestCases;
428 /// FuncInfo - Information about the function as a whole.
430 FunctionLoweringInfo &FuncInfo;
432 /// GCI - Garbage collection metadata for the function.
433 CollectorMetadata *GCI;
435 SelectionDAGLowering(SelectionDAG &dag, TargetLowering &tli,
437 FunctionLoweringInfo &funcinfo,
438 CollectorMetadata *gci)
439 : TLI(tli), DAG(dag), TD(DAG.getTarget().getTargetData()), AA(aa),
440 FuncInfo(funcinfo), GCI(gci) {
443 /// getRoot - Return the current virtual root of the Selection DAG.
445 SDOperand getRoot() {
446 if (PendingLoads.empty())
447 return DAG.getRoot();
449 if (PendingLoads.size() == 1) {
450 SDOperand Root = PendingLoads[0];
452 PendingLoads.clear();
456 // Otherwise, we have to make a token factor node.
457 SDOperand Root = DAG.getNode(ISD::TokenFactor, MVT::Other,
458 &PendingLoads[0], PendingLoads.size());
459 PendingLoads.clear();
464 SDOperand CopyValueToVirtualRegister(Value *V, unsigned Reg);
466 void visit(Instruction &I) { visit(I.getOpcode(), I); }
468 void visit(unsigned Opcode, User &I) {
469 // Note: this doesn't use InstVisitor, because it has to work with
470 // ConstantExpr's in addition to instructions.
472 default: assert(0 && "Unknown instruction type encountered!");
474 // Build the switch statement using the Instruction.def file.
475 #define HANDLE_INST(NUM, OPCODE, CLASS) \
476 case Instruction::OPCODE:return visit##OPCODE((CLASS&)I);
477 #include "llvm/Instruction.def"
481 void setCurrentBasicBlock(MachineBasicBlock *MBB) { CurMBB = MBB; }
483 SDOperand getLoadFrom(const Type *Ty, SDOperand Ptr,
484 const Value *SV, SDOperand Root,
485 bool isVolatile, unsigned Alignment);
487 SDOperand getValue(const Value *V);
489 void setValue(const Value *V, SDOperand NewN) {
490 SDOperand &N = NodeMap[V];
491 assert(N.Val == 0 && "Already set a value for this node!");
495 void GetRegistersForValue(AsmOperandInfo &OpInfo, bool HasEarlyClobber,
496 std::set<unsigned> &OutputRegs,
497 std::set<unsigned> &InputRegs);
499 void FindMergedConditions(Value *Cond, MachineBasicBlock *TBB,
500 MachineBasicBlock *FBB, MachineBasicBlock *CurBB,
502 bool isExportableFromCurrentBlock(Value *V, const BasicBlock *FromBB);
503 void ExportFromCurrentBlock(Value *V);
504 void LowerCallTo(CallSite CS, SDOperand Callee, bool IsTailCall,
505 MachineBasicBlock *LandingPad = NULL);
507 // Terminator instructions.
508 void visitRet(ReturnInst &I);
509 void visitBr(BranchInst &I);
510 void visitSwitch(SwitchInst &I);
511 void visitUnreachable(UnreachableInst &I) { /* noop */ }
513 // Helpers for visitSwitch
514 bool handleSmallSwitchRange(CaseRec& CR,
515 CaseRecVector& WorkList,
517 MachineBasicBlock* Default);
518 bool handleJTSwitchCase(CaseRec& CR,
519 CaseRecVector& WorkList,
521 MachineBasicBlock* Default);
522 bool handleBTSplitSwitchCase(CaseRec& CR,
523 CaseRecVector& WorkList,
525 MachineBasicBlock* Default);
526 bool handleBitTestsSwitchCase(CaseRec& CR,
527 CaseRecVector& WorkList,
529 MachineBasicBlock* Default);
530 void visitSwitchCase(SelectionDAGISel::CaseBlock &CB);
531 void visitBitTestHeader(SelectionDAGISel::BitTestBlock &B);
532 void visitBitTestCase(MachineBasicBlock* NextMBB,
534 SelectionDAGISel::BitTestCase &B);
535 void visitJumpTable(SelectionDAGISel::JumpTable &JT);
536 void visitJumpTableHeader(SelectionDAGISel::JumpTable &JT,
537 SelectionDAGISel::JumpTableHeader &JTH);
539 // These all get lowered before this pass.
540 void visitInvoke(InvokeInst &I);
541 void visitUnwind(UnwindInst &I);
543 void visitBinary(User &I, unsigned OpCode);
544 void visitShift(User &I, unsigned Opcode);
545 void visitAdd(User &I) {
546 if (I.getType()->isFPOrFPVector())
547 visitBinary(I, ISD::FADD);
549 visitBinary(I, ISD::ADD);
551 void visitSub(User &I);
552 void visitMul(User &I) {
553 if (I.getType()->isFPOrFPVector())
554 visitBinary(I, ISD::FMUL);
556 visitBinary(I, ISD::MUL);
558 void visitURem(User &I) { visitBinary(I, ISD::UREM); }
559 void visitSRem(User &I) { visitBinary(I, ISD::SREM); }
560 void visitFRem(User &I) { visitBinary(I, ISD::FREM); }
561 void visitUDiv(User &I) { visitBinary(I, ISD::UDIV); }
562 void visitSDiv(User &I) { visitBinary(I, ISD::SDIV); }
563 void visitFDiv(User &I) { visitBinary(I, ISD::FDIV); }
564 void visitAnd (User &I) { visitBinary(I, ISD::AND); }
565 void visitOr (User &I) { visitBinary(I, ISD::OR); }
566 void visitXor (User &I) { visitBinary(I, ISD::XOR); }
567 void visitShl (User &I) { visitShift(I, ISD::SHL); }
568 void visitLShr(User &I) { visitShift(I, ISD::SRL); }
569 void visitAShr(User &I) { visitShift(I, ISD::SRA); }
570 void visitICmp(User &I);
571 void visitFCmp(User &I);
572 // Visit the conversion instructions
573 void visitTrunc(User &I);
574 void visitZExt(User &I);
575 void visitSExt(User &I);
576 void visitFPTrunc(User &I);
577 void visitFPExt(User &I);
578 void visitFPToUI(User &I);
579 void visitFPToSI(User &I);
580 void visitUIToFP(User &I);
581 void visitSIToFP(User &I);
582 void visitPtrToInt(User &I);
583 void visitIntToPtr(User &I);
584 void visitBitCast(User &I);
586 void visitExtractElement(User &I);
587 void visitInsertElement(User &I);
588 void visitShuffleVector(User &I);
590 void visitGetElementPtr(User &I);
591 void visitSelect(User &I);
593 void visitMalloc(MallocInst &I);
594 void visitFree(FreeInst &I);
595 void visitAlloca(AllocaInst &I);
596 void visitLoad(LoadInst &I);
597 void visitStore(StoreInst &I);
598 void visitPHI(PHINode &I) { } // PHI nodes are handled specially.
599 void visitCall(CallInst &I);
600 void visitInlineAsm(CallSite CS);
601 const char *visitIntrinsicCall(CallInst &I, unsigned Intrinsic);
602 void visitTargetIntrinsic(CallInst &I, unsigned Intrinsic);
604 void visitVAStart(CallInst &I);
605 void visitVAArg(VAArgInst &I);
606 void visitVAEnd(CallInst &I);
607 void visitVACopy(CallInst &I);
609 void visitMemIntrinsic(CallInst &I, unsigned Op);
611 void visitUserOp1(Instruction &I) {
612 assert(0 && "UserOp1 should not exist at instruction selection time!");
615 void visitUserOp2(Instruction &I) {
616 assert(0 && "UserOp2 should not exist at instruction selection time!");
620 } // end namespace llvm
623 /// getCopyFromParts - Create a value that contains the specified legal parts
624 /// combined into the value they represent. If the parts combine to a type
625 /// larger then ValueVT then AssertOp can be used to specify whether the extra
626 /// bits are known to be zero (ISD::AssertZext) or sign extended from ValueVT
627 /// (ISD::AssertSext). Likewise TruncExact is used for floating point types to
628 /// indicate that the extra bits can be discarded without losing precision.
629 static SDOperand getCopyFromParts(SelectionDAG &DAG,
630 const SDOperand *Parts,
632 MVT::ValueType PartVT,
633 MVT::ValueType ValueVT,
634 ISD::NodeType AssertOp = ISD::DELETED_NODE,
635 bool TruncExact = false) {
636 assert(NumParts > 0 && "No parts to assemble!");
637 TargetLowering &TLI = DAG.getTargetLoweringInfo();
638 SDOperand Val = Parts[0];
641 // Assemble the value from multiple parts.
642 if (!MVT::isVector(ValueVT)) {
643 unsigned PartBits = MVT::getSizeInBits(PartVT);
644 unsigned ValueBits = MVT::getSizeInBits(ValueVT);
646 // Assemble the power of 2 part.
647 unsigned RoundParts = NumParts & (NumParts - 1) ?
648 1 << Log2_32(NumParts) : NumParts;
649 unsigned RoundBits = PartBits * RoundParts;
650 MVT::ValueType RoundVT = RoundBits == ValueBits ?
651 ValueVT : MVT::getIntegerType(RoundBits);
654 if (RoundParts > 2) {
655 MVT::ValueType HalfVT = MVT::getIntegerType(RoundBits/2);
656 Lo = getCopyFromParts(DAG, Parts, RoundParts/2, PartVT, HalfVT);
657 Hi = getCopyFromParts(DAG, Parts+RoundParts/2, RoundParts/2,
663 if (TLI.isBigEndian())
665 Val = DAG.getNode(ISD::BUILD_PAIR, RoundVT, Lo, Hi);
667 if (RoundParts < NumParts) {
668 // Assemble the trailing non-power-of-2 part.
669 unsigned OddParts = NumParts - RoundParts;
670 MVT::ValueType OddVT = MVT::getIntegerType(OddParts * PartBits);
671 Hi = getCopyFromParts(DAG, Parts+RoundParts, OddParts, PartVT, OddVT);
673 // Combine the round and odd parts.
675 if (TLI.isBigEndian())
677 MVT::ValueType TotalVT = MVT::getIntegerType(NumParts * PartBits);
678 Hi = DAG.getNode(ISD::ANY_EXTEND, TotalVT, Hi);
679 Hi = DAG.getNode(ISD::SHL, TotalVT, Hi,
680 DAG.getConstant(MVT::getSizeInBits(Lo.getValueType()),
681 TLI.getShiftAmountTy()));
682 Lo = DAG.getNode(ISD::ZERO_EXTEND, TotalVT, Lo);
683 Val = DAG.getNode(ISD::OR, TotalVT, Lo, Hi);
686 // Handle a multi-element vector.
687 MVT::ValueType IntermediateVT, RegisterVT;
688 unsigned NumIntermediates;
690 TLI.getVectorTypeBreakdown(ValueVT, IntermediateVT, NumIntermediates,
693 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!");
694 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!");
695 assert(RegisterVT == Parts[0].getValueType() &&
696 "Part type doesn't match part!");
698 // Assemble the parts into intermediate operands.
699 SmallVector<SDOperand, 8> Ops(NumIntermediates);
700 if (NumIntermediates == NumParts) {
701 // If the register was not expanded, truncate or copy the value,
703 for (unsigned i = 0; i != NumParts; ++i)
704 Ops[i] = getCopyFromParts(DAG, &Parts[i], 1,
705 PartVT, IntermediateVT);
706 } else if (NumParts > 0) {
707 // If the intermediate type was expanded, build the intermediate operands
709 assert(NumParts % NumIntermediates == 0 &&
710 "Must expand into a divisible number of parts!");
711 unsigned Factor = NumParts / NumIntermediates;
712 for (unsigned i = 0; i != NumIntermediates; ++i)
713 Ops[i] = getCopyFromParts(DAG, &Parts[i * Factor], Factor,
714 PartVT, IntermediateVT);
717 // Build a vector with BUILD_VECTOR or CONCAT_VECTORS from the intermediate
719 Val = DAG.getNode(MVT::isVector(IntermediateVT) ?
720 ISD::CONCAT_VECTORS : ISD::BUILD_VECTOR,
721 ValueVT, &Ops[0], NumIntermediates);
725 // There is now one part, held in Val. Correct it to match ValueVT.
726 PartVT = Val.getValueType();
728 if (PartVT == ValueVT)
731 if (MVT::isVector(PartVT)) {
732 assert(MVT::isVector(ValueVT) && "Unknown vector conversion!");
733 return DAG.getNode(ISD::BIT_CONVERT, ValueVT, Val);
736 if (MVT::isVector(ValueVT)) {
737 assert(MVT::getVectorElementType(ValueVT) == PartVT &&
738 MVT::getVectorNumElements(ValueVT) == 1 &&
739 "Only trivial scalar-to-vector conversions should get here!");
740 return DAG.getNode(ISD::BUILD_VECTOR, ValueVT, Val);
743 if (MVT::isInteger(PartVT) &&
744 MVT::isInteger(ValueVT)) {
745 if (MVT::getSizeInBits(ValueVT) < MVT::getSizeInBits(PartVT)) {
746 // For a truncate, see if we have any information to
747 // indicate whether the truncated bits will always be
748 // zero or sign-extension.
749 if (AssertOp != ISD::DELETED_NODE)
750 Val = DAG.getNode(AssertOp, PartVT, Val,
751 DAG.getValueType(ValueVT));
752 return DAG.getNode(ISD::TRUNCATE, ValueVT, Val);
754 return DAG.getNode(ISD::ANY_EXTEND, ValueVT, Val);
758 if (MVT::isFloatingPoint(PartVT) && MVT::isFloatingPoint(ValueVT))
759 return DAG.getNode(ISD::FP_ROUND, ValueVT, Val,
760 DAG.getIntPtrConstant(TruncExact));
762 if (MVT::getSizeInBits(PartVT) == MVT::getSizeInBits(ValueVT))
763 return DAG.getNode(ISD::BIT_CONVERT, ValueVT, Val);
765 assert(0 && "Unknown mismatch!");
768 /// getCopyToParts - Create a series of nodes that contain the specified value
769 /// split into legal parts. If the parts contain more bits than Val, then, for
770 /// integers, ExtendKind can be used to specify how to generate the extra bits.
771 static void getCopyToParts(SelectionDAG &DAG,
775 MVT::ValueType PartVT,
776 ISD::NodeType ExtendKind = ISD::ANY_EXTEND) {
777 TargetLowering &TLI = DAG.getTargetLoweringInfo();
778 MVT::ValueType PtrVT = TLI.getPointerTy();
779 MVT::ValueType ValueVT = Val.getValueType();
780 unsigned PartBits = MVT::getSizeInBits(PartVT);
781 assert(TLI.isTypeLegal(PartVT) && "Copying to an illegal type!");
786 if (!MVT::isVector(ValueVT)) {
787 if (PartVT == ValueVT) {
788 assert(NumParts == 1 && "No-op copy with multiple parts!");
793 if (NumParts * PartBits > MVT::getSizeInBits(ValueVT)) {
794 // If the parts cover more bits than the value has, promote the value.
795 if (MVT::isFloatingPoint(PartVT) && MVT::isFloatingPoint(ValueVT)) {
796 assert(NumParts == 1 && "Do not know what to promote to!");
797 Val = DAG.getNode(ISD::FP_EXTEND, PartVT, Val);
798 } else if (MVT::isInteger(PartVT) && MVT::isInteger(ValueVT)) {
799 ValueVT = MVT::getIntegerType(NumParts * PartBits);
800 Val = DAG.getNode(ExtendKind, ValueVT, Val);
802 assert(0 && "Unknown mismatch!");
804 } else if (PartBits == MVT::getSizeInBits(ValueVT)) {
805 // Different types of the same size.
806 assert(NumParts == 1 && PartVT != ValueVT);
807 Val = DAG.getNode(ISD::BIT_CONVERT, PartVT, Val);
808 } else if (NumParts * PartBits < MVT::getSizeInBits(ValueVT)) {
809 // If the parts cover less bits than value has, truncate the value.
810 if (MVT::isInteger(PartVT) && MVT::isInteger(ValueVT)) {
811 ValueVT = MVT::getIntegerType(NumParts * PartBits);
812 Val = DAG.getNode(ISD::TRUNCATE, ValueVT, Val);
814 assert(0 && "Unknown mismatch!");
818 // The value may have changed - recompute ValueVT.
819 ValueVT = Val.getValueType();
820 assert(NumParts * PartBits == MVT::getSizeInBits(ValueVT) &&
821 "Failed to tile the value with PartVT!");
824 assert(PartVT == ValueVT && "Type conversion failed!");
829 // Expand the value into multiple parts.
830 if (NumParts & (NumParts - 1)) {
831 // The number of parts is not a power of 2. Split off and copy the tail.
832 assert(MVT::isInteger(PartVT) && MVT::isInteger(ValueVT) &&
833 "Do not know what to expand to!");
834 unsigned RoundParts = 1 << Log2_32(NumParts);
835 unsigned RoundBits = RoundParts * PartBits;
836 unsigned OddParts = NumParts - RoundParts;
837 SDOperand OddVal = DAG.getNode(ISD::SRL, ValueVT, Val,
838 DAG.getConstant(RoundBits,
839 TLI.getShiftAmountTy()));
840 getCopyToParts(DAG, OddVal, Parts + RoundParts, OddParts, PartVT);
841 if (TLI.isBigEndian())
842 // The odd parts were reversed by getCopyToParts - unreverse them.
843 std::reverse(Parts + RoundParts, Parts + NumParts);
844 NumParts = RoundParts;
845 ValueVT = MVT::getIntegerType(NumParts * PartBits);
846 Val = DAG.getNode(ISD::TRUNCATE, ValueVT, Val);
849 // The number of parts is a power of 2. Repeatedly bisect the value using
852 for (unsigned StepSize = NumParts; StepSize > 1; StepSize /= 2) {
853 for (unsigned i = 0; i < NumParts; i += StepSize) {
854 unsigned ThisBits = StepSize * PartBits / 2;
855 MVT::ValueType ThisVT =
856 ThisBits == PartBits ? PartVT : MVT::getIntegerType (ThisBits);
858 Parts[i+StepSize/2] =
859 DAG.getNode(ISD::EXTRACT_ELEMENT, ThisVT, Parts[i],
860 DAG.getConstant(1, PtrVT));
862 DAG.getNode(ISD::EXTRACT_ELEMENT, ThisVT, Parts[i],
863 DAG.getConstant(0, PtrVT));
867 if (TLI.isBigEndian())
868 std::reverse(Parts, Parts + NumParts);
875 if (PartVT != ValueVT) {
876 if (MVT::isVector(PartVT)) {
877 Val = DAG.getNode(ISD::BIT_CONVERT, PartVT, Val);
879 assert(MVT::getVectorElementType(ValueVT) == PartVT &&
880 MVT::getVectorNumElements(ValueVT) == 1 &&
881 "Only trivial vector-to-scalar conversions should get here!");
882 Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, PartVT, Val,
883 DAG.getConstant(0, PtrVT));
891 // Handle a multi-element vector.
892 MVT::ValueType IntermediateVT, RegisterVT;
893 unsigned NumIntermediates;
895 DAG.getTargetLoweringInfo()
896 .getVectorTypeBreakdown(ValueVT, IntermediateVT, NumIntermediates,
898 unsigned NumElements = MVT::getVectorNumElements(ValueVT);
900 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!");
901 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!");
903 // Split the vector into intermediate operands.
904 SmallVector<SDOperand, 8> Ops(NumIntermediates);
905 for (unsigned i = 0; i != NumIntermediates; ++i)
906 if (MVT::isVector(IntermediateVT))
907 Ops[i] = DAG.getNode(ISD::EXTRACT_SUBVECTOR,
909 DAG.getConstant(i * (NumElements / NumIntermediates),
912 Ops[i] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT,
914 DAG.getConstant(i, PtrVT));
916 // Split the intermediate operands into legal parts.
917 if (NumParts == NumIntermediates) {
918 // If the register was not expanded, promote or copy the value,
920 for (unsigned i = 0; i != NumParts; ++i)
921 getCopyToParts(DAG, Ops[i], &Parts[i], 1, PartVT);
922 } else if (NumParts > 0) {
923 // If the intermediate type was expanded, split each the value into
925 assert(NumParts % NumIntermediates == 0 &&
926 "Must expand into a divisible number of parts!");
927 unsigned Factor = NumParts / NumIntermediates;
928 for (unsigned i = 0; i != NumIntermediates; ++i)
929 getCopyToParts(DAG, Ops[i], &Parts[i * Factor], Factor, PartVT);
934 SDOperand SelectionDAGLowering::getValue(const Value *V) {
935 SDOperand &N = NodeMap[V];
938 const Type *VTy = V->getType();
939 MVT::ValueType VT = TLI.getValueType(VTy);
940 if (Constant *C = const_cast<Constant*>(dyn_cast<Constant>(V))) {
941 if (ConstantExpr *CE = dyn_cast<ConstantExpr>(C)) {
942 visit(CE->getOpcode(), *CE);
943 SDOperand N1 = NodeMap[V];
944 assert(N1.Val && "visit didn't populate the ValueMap!");
946 } else if (GlobalValue *GV = dyn_cast<GlobalValue>(C)) {
947 return N = DAG.getGlobalAddress(GV, VT);
948 } else if (isa<ConstantPointerNull>(C)) {
949 return N = DAG.getConstant(0, TLI.getPointerTy());
950 } else if (isa<UndefValue>(C)) {
951 if (!isa<VectorType>(VTy))
952 return N = DAG.getNode(ISD::UNDEF, VT);
954 // Create a BUILD_VECTOR of undef nodes.
955 const VectorType *PTy = cast<VectorType>(VTy);
956 unsigned NumElements = PTy->getNumElements();
957 MVT::ValueType PVT = TLI.getValueType(PTy->getElementType());
959 SmallVector<SDOperand, 8> Ops;
960 Ops.assign(NumElements, DAG.getNode(ISD::UNDEF, PVT));
962 // Create a VConstant node with generic Vector type.
963 MVT::ValueType VT = MVT::getVectorType(PVT, NumElements);
964 return N = DAG.getNode(ISD::BUILD_VECTOR, VT,
965 &Ops[0], Ops.size());
966 } else if (ConstantFP *CFP = dyn_cast<ConstantFP>(C)) {
967 return N = DAG.getConstantFP(CFP->getValueAPF(), VT);
968 } else if (const VectorType *PTy = dyn_cast<VectorType>(VTy)) {
969 unsigned NumElements = PTy->getNumElements();
970 MVT::ValueType PVT = TLI.getValueType(PTy->getElementType());
972 // Now that we know the number and type of the elements, push a
973 // Constant or ConstantFP node onto the ops list for each element of
974 // the vector constant.
975 SmallVector<SDOperand, 8> Ops;
976 if (ConstantVector *CP = dyn_cast<ConstantVector>(C)) {
977 for (unsigned i = 0; i != NumElements; ++i)
978 Ops.push_back(getValue(CP->getOperand(i)));
980 assert(isa<ConstantAggregateZero>(C) && "Unknown vector constant!");
982 if (MVT::isFloatingPoint(PVT))
983 Op = DAG.getConstantFP(0, PVT);
985 Op = DAG.getConstant(0, PVT);
986 Ops.assign(NumElements, Op);
989 // Create a BUILD_VECTOR node.
990 MVT::ValueType VT = MVT::getVectorType(PVT, NumElements);
991 return NodeMap[V] = DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0],
994 // Canonicalize all constant ints to be unsigned.
995 return N = DAG.getConstant(cast<ConstantInt>(C)->getZExtValue(),VT);
999 if (const AllocaInst *AI = dyn_cast<AllocaInst>(V)) {
1000 std::map<const AllocaInst*, int>::iterator SI =
1001 FuncInfo.StaticAllocaMap.find(AI);
1002 if (SI != FuncInfo.StaticAllocaMap.end())
1003 return DAG.getFrameIndex(SI->second, TLI.getPointerTy());
1006 unsigned InReg = FuncInfo.ValueMap[V];
1007 assert(InReg && "Value not in map!");
1009 MVT::ValueType RegisterVT = TLI.getRegisterType(VT);
1010 unsigned NumRegs = TLI.getNumRegisters(VT);
1012 std::vector<unsigned> Regs(NumRegs);
1013 for (unsigned i = 0; i != NumRegs; ++i)
1014 Regs[i] = InReg + i;
1016 RegsForValue RFV(Regs, RegisterVT, VT);
1017 SDOperand Chain = DAG.getEntryNode();
1019 return RFV.getCopyFromRegs(DAG, Chain, NULL);
1023 void SelectionDAGLowering::visitRet(ReturnInst &I) {
1024 if (I.getNumOperands() == 0) {
1025 DAG.setRoot(DAG.getNode(ISD::RET, MVT::Other, getRoot()));
1028 SmallVector<SDOperand, 8> NewValues;
1029 NewValues.push_back(getRoot());
1030 for (unsigned i = 0, e = I.getNumOperands(); i != e; ++i) {
1031 SDOperand RetOp = getValue(I.getOperand(i));
1032 MVT::ValueType VT = RetOp.getValueType();
1034 // FIXME: C calling convention requires the return type to be promoted to
1035 // at least 32-bit. But this is not necessary for non-C calling conventions.
1036 if (MVT::isInteger(VT)) {
1037 MVT::ValueType MinVT = TLI.getRegisterType(MVT::i32);
1038 if (MVT::getSizeInBits(VT) < MVT::getSizeInBits(MinVT))
1042 unsigned NumParts = TLI.getNumRegisters(VT);
1043 MVT::ValueType PartVT = TLI.getRegisterType(VT);
1044 SmallVector<SDOperand, 4> Parts(NumParts);
1045 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
1047 const Function *F = I.getParent()->getParent();
1048 if (F->paramHasAttr(0, ParamAttr::SExt))
1049 ExtendKind = ISD::SIGN_EXTEND;
1050 else if (F->paramHasAttr(0, ParamAttr::ZExt))
1051 ExtendKind = ISD::ZERO_EXTEND;
1053 getCopyToParts(DAG, RetOp, &Parts[0], NumParts, PartVT, ExtendKind);
1055 for (unsigned i = 0; i < NumParts; ++i) {
1056 NewValues.push_back(Parts[i]);
1057 NewValues.push_back(DAG.getConstant(false, MVT::i32));
1060 DAG.setRoot(DAG.getNode(ISD::RET, MVT::Other,
1061 &NewValues[0], NewValues.size()));
1064 /// ExportFromCurrentBlock - If this condition isn't known to be exported from
1065 /// the current basic block, add it to ValueMap now so that we'll get a
1067 void SelectionDAGLowering::ExportFromCurrentBlock(Value *V) {
1068 // No need to export constants.
1069 if (!isa<Instruction>(V) && !isa<Argument>(V)) return;
1071 // Already exported?
1072 if (FuncInfo.isExportedInst(V)) return;
1074 unsigned Reg = FuncInfo.InitializeRegForValue(V);
1075 PendingLoads.push_back(CopyValueToVirtualRegister(V, Reg));
1078 bool SelectionDAGLowering::isExportableFromCurrentBlock(Value *V,
1079 const BasicBlock *FromBB) {
1080 // The operands of the setcc have to be in this block. We don't know
1081 // how to export them from some other block.
1082 if (Instruction *VI = dyn_cast<Instruction>(V)) {
1083 // Can export from current BB.
1084 if (VI->getParent() == FromBB)
1087 // Is already exported, noop.
1088 return FuncInfo.isExportedInst(V);
1091 // If this is an argument, we can export it if the BB is the entry block or
1092 // if it is already exported.
1093 if (isa<Argument>(V)) {
1094 if (FromBB == &FromBB->getParent()->getEntryBlock())
1097 // Otherwise, can only export this if it is already exported.
1098 return FuncInfo.isExportedInst(V);
1101 // Otherwise, constants can always be exported.
1105 static bool InBlock(const Value *V, const BasicBlock *BB) {
1106 if (const Instruction *I = dyn_cast<Instruction>(V))
1107 return I->getParent() == BB;
1111 /// FindMergedConditions - If Cond is an expression like
1112 void SelectionDAGLowering::FindMergedConditions(Value *Cond,
1113 MachineBasicBlock *TBB,
1114 MachineBasicBlock *FBB,
1115 MachineBasicBlock *CurBB,
1117 // If this node is not part of the or/and tree, emit it as a branch.
1118 Instruction *BOp = dyn_cast<Instruction>(Cond);
1120 if (!BOp || !(isa<BinaryOperator>(BOp) || isa<CmpInst>(BOp)) ||
1121 (unsigned)BOp->getOpcode() != Opc || !BOp->hasOneUse() ||
1122 BOp->getParent() != CurBB->getBasicBlock() ||
1123 !InBlock(BOp->getOperand(0), CurBB->getBasicBlock()) ||
1124 !InBlock(BOp->getOperand(1), CurBB->getBasicBlock())) {
1125 const BasicBlock *BB = CurBB->getBasicBlock();
1127 // If the leaf of the tree is a comparison, merge the condition into
1129 if ((isa<ICmpInst>(Cond) || isa<FCmpInst>(Cond)) &&
1130 // The operands of the cmp have to be in this block. We don't know
1131 // how to export them from some other block. If this is the first block
1132 // of the sequence, no exporting is needed.
1134 (isExportableFromCurrentBlock(BOp->getOperand(0), BB) &&
1135 isExportableFromCurrentBlock(BOp->getOperand(1), BB)))) {
1136 BOp = cast<Instruction>(Cond);
1137 ISD::CondCode Condition;
1138 if (ICmpInst *IC = dyn_cast<ICmpInst>(Cond)) {
1139 switch (IC->getPredicate()) {
1140 default: assert(0 && "Unknown icmp predicate opcode!");
1141 case ICmpInst::ICMP_EQ: Condition = ISD::SETEQ; break;
1142 case ICmpInst::ICMP_NE: Condition = ISD::SETNE; break;
1143 case ICmpInst::ICMP_SLE: Condition = ISD::SETLE; break;
1144 case ICmpInst::ICMP_ULE: Condition = ISD::SETULE; break;
1145 case ICmpInst::ICMP_SGE: Condition = ISD::SETGE; break;
1146 case ICmpInst::ICMP_UGE: Condition = ISD::SETUGE; break;
1147 case ICmpInst::ICMP_SLT: Condition = ISD::SETLT; break;
1148 case ICmpInst::ICMP_ULT: Condition = ISD::SETULT; break;
1149 case ICmpInst::ICMP_SGT: Condition = ISD::SETGT; break;
1150 case ICmpInst::ICMP_UGT: Condition = ISD::SETUGT; break;
1152 } else if (FCmpInst *FC = dyn_cast<FCmpInst>(Cond)) {
1153 ISD::CondCode FPC, FOC;
1154 switch (FC->getPredicate()) {
1155 default: assert(0 && "Unknown fcmp predicate opcode!");
1156 case FCmpInst::FCMP_FALSE: FOC = FPC = ISD::SETFALSE; break;
1157 case FCmpInst::FCMP_OEQ: FOC = ISD::SETEQ; FPC = ISD::SETOEQ; break;
1158 case FCmpInst::FCMP_OGT: FOC = ISD::SETGT; FPC = ISD::SETOGT; break;
1159 case FCmpInst::FCMP_OGE: FOC = ISD::SETGE; FPC = ISD::SETOGE; break;
1160 case FCmpInst::FCMP_OLT: FOC = ISD::SETLT; FPC = ISD::SETOLT; break;
1161 case FCmpInst::FCMP_OLE: FOC = ISD::SETLE; FPC = ISD::SETOLE; break;
1162 case FCmpInst::FCMP_ONE: FOC = ISD::SETNE; FPC = ISD::SETONE; break;
1163 case FCmpInst::FCMP_ORD: FOC = ISD::SETEQ; FPC = ISD::SETO; break;
1164 case FCmpInst::FCMP_UNO: FOC = ISD::SETNE; FPC = ISD::SETUO; break;
1165 case FCmpInst::FCMP_UEQ: FOC = ISD::SETEQ; FPC = ISD::SETUEQ; break;
1166 case FCmpInst::FCMP_UGT: FOC = ISD::SETGT; FPC = ISD::SETUGT; break;
1167 case FCmpInst::FCMP_UGE: FOC = ISD::SETGE; FPC = ISD::SETUGE; break;
1168 case FCmpInst::FCMP_ULT: FOC = ISD::SETLT; FPC = ISD::SETULT; break;
1169 case FCmpInst::FCMP_ULE: FOC = ISD::SETLE; FPC = ISD::SETULE; break;
1170 case FCmpInst::FCMP_UNE: FOC = ISD::SETNE; FPC = ISD::SETUNE; break;
1171 case FCmpInst::FCMP_TRUE: FOC = FPC = ISD::SETTRUE; break;
1173 if (FiniteOnlyFPMath())
1178 Condition = ISD::SETEQ; // silence warning.
1179 assert(0 && "Unknown compare instruction");
1182 SelectionDAGISel::CaseBlock CB(Condition, BOp->getOperand(0),
1183 BOp->getOperand(1), NULL, TBB, FBB, CurBB);
1184 SwitchCases.push_back(CB);
1188 // Create a CaseBlock record representing this branch.
1189 SelectionDAGISel::CaseBlock CB(ISD::SETEQ, Cond, ConstantInt::getTrue(),
1190 NULL, TBB, FBB, CurBB);
1191 SwitchCases.push_back(CB);
1196 // Create TmpBB after CurBB.
1197 MachineFunction::iterator BBI = CurBB;
1198 MachineBasicBlock *TmpBB = new MachineBasicBlock(CurBB->getBasicBlock());
1199 CurBB->getParent()->getBasicBlockList().insert(++BBI, TmpBB);
1201 if (Opc == Instruction::Or) {
1202 // Codegen X | Y as:
1210 // Emit the LHS condition.
1211 FindMergedConditions(BOp->getOperand(0), TBB, TmpBB, CurBB, Opc);
1213 // Emit the RHS condition into TmpBB.
1214 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, Opc);
1216 assert(Opc == Instruction::And && "Unknown merge op!");
1217 // Codegen X & Y as:
1224 // This requires creation of TmpBB after CurBB.
1226 // Emit the LHS condition.
1227 FindMergedConditions(BOp->getOperand(0), TmpBB, FBB, CurBB, Opc);
1229 // Emit the RHS condition into TmpBB.
1230 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, Opc);
1234 /// If the set of cases should be emitted as a series of branches, return true.
1235 /// If we should emit this as a bunch of and/or'd together conditions, return
1238 ShouldEmitAsBranches(const std::vector<SelectionDAGISel::CaseBlock> &Cases) {
1239 if (Cases.size() != 2) return true;
1241 // If this is two comparisons of the same values or'd or and'd together, they
1242 // will get folded into a single comparison, so don't emit two blocks.
1243 if ((Cases[0].CmpLHS == Cases[1].CmpLHS &&
1244 Cases[0].CmpRHS == Cases[1].CmpRHS) ||
1245 (Cases[0].CmpRHS == Cases[1].CmpLHS &&
1246 Cases[0].CmpLHS == Cases[1].CmpRHS)) {
1253 void SelectionDAGLowering::visitBr(BranchInst &I) {
1254 // Update machine-CFG edges.
1255 MachineBasicBlock *Succ0MBB = FuncInfo.MBBMap[I.getSuccessor(0)];
1257 // Figure out which block is immediately after the current one.
1258 MachineBasicBlock *NextBlock = 0;
1259 MachineFunction::iterator BBI = CurMBB;
1260 if (++BBI != CurMBB->getParent()->end())
1263 if (I.isUnconditional()) {
1264 // If this is not a fall-through branch, emit the branch.
1265 if (Succ0MBB != NextBlock)
1266 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, getRoot(),
1267 DAG.getBasicBlock(Succ0MBB)));
1269 // Update machine-CFG edges.
1270 CurMBB->addSuccessor(Succ0MBB);
1274 // If this condition is one of the special cases we handle, do special stuff
1276 Value *CondVal = I.getCondition();
1277 MachineBasicBlock *Succ1MBB = FuncInfo.MBBMap[I.getSuccessor(1)];
1279 // If this is a series of conditions that are or'd or and'd together, emit
1280 // this as a sequence of branches instead of setcc's with and/or operations.
1281 // For example, instead of something like:
1294 if (BinaryOperator *BOp = dyn_cast<BinaryOperator>(CondVal)) {
1295 if (BOp->hasOneUse() &&
1296 (BOp->getOpcode() == Instruction::And ||
1297 BOp->getOpcode() == Instruction::Or)) {
1298 FindMergedConditions(BOp, Succ0MBB, Succ1MBB, CurMBB, BOp->getOpcode());
1299 // If the compares in later blocks need to use values not currently
1300 // exported from this block, export them now. This block should always
1301 // be the first entry.
1302 assert(SwitchCases[0].ThisBB == CurMBB && "Unexpected lowering!");
1304 // Allow some cases to be rejected.
1305 if (ShouldEmitAsBranches(SwitchCases)) {
1306 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i) {
1307 ExportFromCurrentBlock(SwitchCases[i].CmpLHS);
1308 ExportFromCurrentBlock(SwitchCases[i].CmpRHS);
1311 // Emit the branch for this block.
1312 visitSwitchCase(SwitchCases[0]);
1313 SwitchCases.erase(SwitchCases.begin());
1317 // Okay, we decided not to do this, remove any inserted MBB's and clear
1319 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i)
1320 CurMBB->getParent()->getBasicBlockList().erase(SwitchCases[i].ThisBB);
1322 SwitchCases.clear();
1326 // Create a CaseBlock record representing this branch.
1327 SelectionDAGISel::CaseBlock CB(ISD::SETEQ, CondVal, ConstantInt::getTrue(),
1328 NULL, Succ0MBB, Succ1MBB, CurMBB);
1329 // Use visitSwitchCase to actually insert the fast branch sequence for this
1331 visitSwitchCase(CB);
1334 /// visitSwitchCase - Emits the necessary code to represent a single node in
1335 /// the binary search tree resulting from lowering a switch instruction.
1336 void SelectionDAGLowering::visitSwitchCase(SelectionDAGISel::CaseBlock &CB) {
1338 SDOperand CondLHS = getValue(CB.CmpLHS);
1340 // Build the setcc now.
1341 if (CB.CmpMHS == NULL) {
1342 // Fold "(X == true)" to X and "(X == false)" to !X to
1343 // handle common cases produced by branch lowering.
1344 if (CB.CmpRHS == ConstantInt::getTrue() && CB.CC == ISD::SETEQ)
1346 else if (CB.CmpRHS == ConstantInt::getFalse() && CB.CC == ISD::SETEQ) {
1347 SDOperand True = DAG.getConstant(1, CondLHS.getValueType());
1348 Cond = DAG.getNode(ISD::XOR, CondLHS.getValueType(), CondLHS, True);
1350 Cond = DAG.getSetCC(MVT::i1, CondLHS, getValue(CB.CmpRHS), CB.CC);
1352 assert(CB.CC == ISD::SETLE && "Can handle only LE ranges now");
1354 uint64_t Low = cast<ConstantInt>(CB.CmpLHS)->getSExtValue();
1355 uint64_t High = cast<ConstantInt>(CB.CmpRHS)->getSExtValue();
1357 SDOperand CmpOp = getValue(CB.CmpMHS);
1358 MVT::ValueType VT = CmpOp.getValueType();
1360 if (cast<ConstantInt>(CB.CmpLHS)->isMinValue(true)) {
1361 Cond = DAG.getSetCC(MVT::i1, CmpOp, DAG.getConstant(High, VT), ISD::SETLE);
1363 SDOperand SUB = DAG.getNode(ISD::SUB, VT, CmpOp, DAG.getConstant(Low, VT));
1364 Cond = DAG.getSetCC(MVT::i1, SUB,
1365 DAG.getConstant(High-Low, VT), ISD::SETULE);
1370 // Set NextBlock to be the MBB immediately after the current one, if any.
1371 // This is used to avoid emitting unnecessary branches to the next block.
1372 MachineBasicBlock *NextBlock = 0;
1373 MachineFunction::iterator BBI = CurMBB;
1374 if (++BBI != CurMBB->getParent()->end())
1377 // If the lhs block is the next block, invert the condition so that we can
1378 // fall through to the lhs instead of the rhs block.
1379 if (CB.TrueBB == NextBlock) {
1380 std::swap(CB.TrueBB, CB.FalseBB);
1381 SDOperand True = DAG.getConstant(1, Cond.getValueType());
1382 Cond = DAG.getNode(ISD::XOR, Cond.getValueType(), Cond, True);
1384 SDOperand BrCond = DAG.getNode(ISD::BRCOND, MVT::Other, getRoot(), Cond,
1385 DAG.getBasicBlock(CB.TrueBB));
1386 if (CB.FalseBB == NextBlock)
1387 DAG.setRoot(BrCond);
1389 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, BrCond,
1390 DAG.getBasicBlock(CB.FalseBB)));
1391 // Update successor info
1392 CurMBB->addSuccessor(CB.TrueBB);
1393 CurMBB->addSuccessor(CB.FalseBB);
1396 /// visitJumpTable - Emit JumpTable node in the current MBB
1397 void SelectionDAGLowering::visitJumpTable(SelectionDAGISel::JumpTable &JT) {
1398 // Emit the code for the jump table
1399 assert(JT.Reg != -1U && "Should lower JT Header first!");
1400 MVT::ValueType PTy = TLI.getPointerTy();
1401 SDOperand Index = DAG.getCopyFromReg(getRoot(), JT.Reg, PTy);
1402 SDOperand Table = DAG.getJumpTable(JT.JTI, PTy);
1403 DAG.setRoot(DAG.getNode(ISD::BR_JT, MVT::Other, Index.getValue(1),
1408 /// visitJumpTableHeader - This function emits necessary code to produce index
1409 /// in the JumpTable from switch case.
1410 void SelectionDAGLowering::visitJumpTableHeader(SelectionDAGISel::JumpTable &JT,
1411 SelectionDAGISel::JumpTableHeader &JTH) {
1412 // Subtract the lowest switch case value from the value being switched on
1413 // and conditional branch to default mbb if the result is greater than the
1414 // difference between smallest and largest cases.
1415 SDOperand SwitchOp = getValue(JTH.SValue);
1416 MVT::ValueType VT = SwitchOp.getValueType();
1417 SDOperand SUB = DAG.getNode(ISD::SUB, VT, SwitchOp,
1418 DAG.getConstant(JTH.First, VT));
1420 // The SDNode we just created, which holds the value being switched on
1421 // minus the the smallest case value, needs to be copied to a virtual
1422 // register so it can be used as an index into the jump table in a
1423 // subsequent basic block. This value may be smaller or larger than the
1424 // target's pointer type, and therefore require extension or truncating.
1425 if (MVT::getSizeInBits(VT) > MVT::getSizeInBits(TLI.getPointerTy()))
1426 SwitchOp = DAG.getNode(ISD::TRUNCATE, TLI.getPointerTy(), SUB);
1428 SwitchOp = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(), SUB);
1430 unsigned JumpTableReg = FuncInfo.MakeReg(TLI.getPointerTy());
1431 SDOperand CopyTo = DAG.getCopyToReg(getRoot(), JumpTableReg, SwitchOp);
1432 JT.Reg = JumpTableReg;
1434 // Emit the range check for the jump table, and branch to the default
1435 // block for the switch statement if the value being switched on exceeds
1436 // the largest case in the switch.
1437 SDOperand CMP = DAG.getSetCC(TLI.getSetCCResultTy(), SUB,
1438 DAG.getConstant(JTH.Last-JTH.First,VT),
1441 // Set NextBlock to be the MBB immediately after the current one, if any.
1442 // This is used to avoid emitting unnecessary branches to the next block.
1443 MachineBasicBlock *NextBlock = 0;
1444 MachineFunction::iterator BBI = CurMBB;
1445 if (++BBI != CurMBB->getParent()->end())
1448 SDOperand BrCond = DAG.getNode(ISD::BRCOND, MVT::Other, CopyTo, CMP,
1449 DAG.getBasicBlock(JT.Default));
1451 if (JT.MBB == NextBlock)
1452 DAG.setRoot(BrCond);
1454 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, BrCond,
1455 DAG.getBasicBlock(JT.MBB)));
1460 /// visitBitTestHeader - This function emits necessary code to produce value
1461 /// suitable for "bit tests"
1462 void SelectionDAGLowering::visitBitTestHeader(SelectionDAGISel::BitTestBlock &B) {
1463 // Subtract the minimum value
1464 SDOperand SwitchOp = getValue(B.SValue);
1465 MVT::ValueType VT = SwitchOp.getValueType();
1466 SDOperand SUB = DAG.getNode(ISD::SUB, VT, SwitchOp,
1467 DAG.getConstant(B.First, VT));
1470 SDOperand RangeCmp = DAG.getSetCC(TLI.getSetCCResultTy(), SUB,
1471 DAG.getConstant(B.Range, VT),
1475 if (MVT::getSizeInBits(VT) > MVT::getSizeInBits(TLI.getShiftAmountTy()))
1476 ShiftOp = DAG.getNode(ISD::TRUNCATE, TLI.getShiftAmountTy(), SUB);
1478 ShiftOp = DAG.getNode(ISD::ZERO_EXTEND, TLI.getShiftAmountTy(), SUB);
1480 // Make desired shift
1481 SDOperand SwitchVal = DAG.getNode(ISD::SHL, TLI.getPointerTy(),
1482 DAG.getConstant(1, TLI.getPointerTy()),
1485 unsigned SwitchReg = FuncInfo.MakeReg(TLI.getPointerTy());
1486 SDOperand CopyTo = DAG.getCopyToReg(getRoot(), SwitchReg, SwitchVal);
1489 SDOperand BrRange = DAG.getNode(ISD::BRCOND, MVT::Other, CopyTo, RangeCmp,
1490 DAG.getBasicBlock(B.Default));
1492 // Set NextBlock to be the MBB immediately after the current one, if any.
1493 // This is used to avoid emitting unnecessary branches to the next block.
1494 MachineBasicBlock *NextBlock = 0;
1495 MachineFunction::iterator BBI = CurMBB;
1496 if (++BBI != CurMBB->getParent()->end())
1499 MachineBasicBlock* MBB = B.Cases[0].ThisBB;
1500 if (MBB == NextBlock)
1501 DAG.setRoot(BrRange);
1503 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, CopyTo,
1504 DAG.getBasicBlock(MBB)));
1506 CurMBB->addSuccessor(B.Default);
1507 CurMBB->addSuccessor(MBB);
1512 /// visitBitTestCase - this function produces one "bit test"
1513 void SelectionDAGLowering::visitBitTestCase(MachineBasicBlock* NextMBB,
1515 SelectionDAGISel::BitTestCase &B) {
1516 // Emit bit tests and jumps
1517 SDOperand SwitchVal = DAG.getCopyFromReg(getRoot(), Reg, TLI.getPointerTy());
1519 SDOperand AndOp = DAG.getNode(ISD::AND, TLI.getPointerTy(),
1521 DAG.getConstant(B.Mask,
1522 TLI.getPointerTy()));
1523 SDOperand AndCmp = DAG.getSetCC(TLI.getSetCCResultTy(), AndOp,
1524 DAG.getConstant(0, TLI.getPointerTy()),
1526 SDOperand BrAnd = DAG.getNode(ISD::BRCOND, MVT::Other, getRoot(),
1527 AndCmp, DAG.getBasicBlock(B.TargetBB));
1529 // Set NextBlock to be the MBB immediately after the current one, if any.
1530 // This is used to avoid emitting unnecessary branches to the next block.
1531 MachineBasicBlock *NextBlock = 0;
1532 MachineFunction::iterator BBI = CurMBB;
1533 if (++BBI != CurMBB->getParent()->end())
1536 if (NextMBB == NextBlock)
1539 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, BrAnd,
1540 DAG.getBasicBlock(NextMBB)));
1542 CurMBB->addSuccessor(B.TargetBB);
1543 CurMBB->addSuccessor(NextMBB);
1548 void SelectionDAGLowering::visitInvoke(InvokeInst &I) {
1549 // Retrieve successors.
1550 MachineBasicBlock *Return = FuncInfo.MBBMap[I.getSuccessor(0)];
1551 MachineBasicBlock *LandingPad = FuncInfo.MBBMap[I.getSuccessor(1)];
1553 if (isa<InlineAsm>(I.getCalledValue()))
1556 LowerCallTo(&I, getValue(I.getOperand(0)), false, LandingPad);
1558 // If the value of the invoke is used outside of its defining block, make it
1559 // available as a virtual register.
1560 if (!I.use_empty()) {
1561 DenseMap<const Value*, unsigned>::iterator VMI = FuncInfo.ValueMap.find(&I);
1562 if (VMI != FuncInfo.ValueMap.end())
1563 DAG.setRoot(CopyValueToVirtualRegister(&I, VMI->second));
1566 // Drop into normal successor.
1567 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, getRoot(),
1568 DAG.getBasicBlock(Return)));
1570 // Update successor info
1571 CurMBB->addSuccessor(Return);
1572 CurMBB->addSuccessor(LandingPad);
1575 void SelectionDAGLowering::visitUnwind(UnwindInst &I) {
1578 /// handleSmallSwitchCaseRange - Emit a series of specific tests (suitable for
1579 /// small case ranges).
1580 bool SelectionDAGLowering::handleSmallSwitchRange(CaseRec& CR,
1581 CaseRecVector& WorkList,
1583 MachineBasicBlock* Default) {
1584 Case& BackCase = *(CR.Range.second-1);
1586 // Size is the number of Cases represented by this range.
1587 unsigned Size = CR.Range.second - CR.Range.first;
1591 // Get the MachineFunction which holds the current MBB. This is used when
1592 // inserting any additional MBBs necessary to represent the switch.
1593 MachineFunction *CurMF = CurMBB->getParent();
1595 // Figure out which block is immediately after the current one.
1596 MachineBasicBlock *NextBlock = 0;
1597 MachineFunction::iterator BBI = CR.CaseBB;
1599 if (++BBI != CurMBB->getParent()->end())
1602 // TODO: If any two of the cases has the same destination, and if one value
1603 // is the same as the other, but has one bit unset that the other has set,
1604 // use bit manipulation to do two compares at once. For example:
1605 // "if (X == 6 || X == 4)" -> "if ((X|2) == 6)"
1607 // Rearrange the case blocks so that the last one falls through if possible.
1608 if (NextBlock && Default != NextBlock && BackCase.BB != NextBlock) {
1609 // The last case block won't fall through into 'NextBlock' if we emit the
1610 // branches in this order. See if rearranging a case value would help.
1611 for (CaseItr I = CR.Range.first, E = CR.Range.second-1; I != E; ++I) {
1612 if (I->BB == NextBlock) {
1613 std::swap(*I, BackCase);
1619 // Create a CaseBlock record representing a conditional branch to
1620 // the Case's target mbb if the value being switched on SV is equal
1622 MachineBasicBlock *CurBlock = CR.CaseBB;
1623 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++I) {
1624 MachineBasicBlock *FallThrough;
1626 FallThrough = new MachineBasicBlock(CurBlock->getBasicBlock());
1627 CurMF->getBasicBlockList().insert(BBI, FallThrough);
1629 // If the last case doesn't match, go to the default block.
1630 FallThrough = Default;
1633 Value *RHS, *LHS, *MHS;
1635 if (I->High == I->Low) {
1636 // This is just small small case range :) containing exactly 1 case
1638 LHS = SV; RHS = I->High; MHS = NULL;
1641 LHS = I->Low; MHS = SV; RHS = I->High;
1643 SelectionDAGISel::CaseBlock CB(CC, LHS, RHS, MHS,
1644 I->BB, FallThrough, CurBlock);
1646 // If emitting the first comparison, just call visitSwitchCase to emit the
1647 // code into the current block. Otherwise, push the CaseBlock onto the
1648 // vector to be later processed by SDISel, and insert the node's MBB
1649 // before the next MBB.
1650 if (CurBlock == CurMBB)
1651 visitSwitchCase(CB);
1653 SwitchCases.push_back(CB);
1655 CurBlock = FallThrough;
1661 static inline bool areJTsAllowed(const TargetLowering &TLI) {
1662 return (TLI.isOperationLegal(ISD::BR_JT, MVT::Other) ||
1663 TLI.isOperationLegal(ISD::BRIND, MVT::Other));
1666 /// handleJTSwitchCase - Emit jumptable for current switch case range
1667 bool SelectionDAGLowering::handleJTSwitchCase(CaseRec& CR,
1668 CaseRecVector& WorkList,
1670 MachineBasicBlock* Default) {
1671 Case& FrontCase = *CR.Range.first;
1672 Case& BackCase = *(CR.Range.second-1);
1674 int64_t First = cast<ConstantInt>(FrontCase.Low)->getSExtValue();
1675 int64_t Last = cast<ConstantInt>(BackCase.High)->getSExtValue();
1678 for (CaseItr I = CR.Range.first, E = CR.Range.second;
1682 if (!areJTsAllowed(TLI) || TSize <= 3)
1685 double Density = (double)TSize / (double)((Last - First) + 1ULL);
1689 DOUT << "Lowering jump table\n"
1690 << "First entry: " << First << ". Last entry: " << Last << "\n"
1691 << "Size: " << TSize << ". Density: " << Density << "\n\n";
1693 // Get the MachineFunction which holds the current MBB. This is used when
1694 // inserting any additional MBBs necessary to represent the switch.
1695 MachineFunction *CurMF = CurMBB->getParent();
1697 // Figure out which block is immediately after the current one.
1698 MachineBasicBlock *NextBlock = 0;
1699 MachineFunction::iterator BBI = CR.CaseBB;
1701 if (++BBI != CurMBB->getParent()->end())
1704 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
1706 // Create a new basic block to hold the code for loading the address
1707 // of the jump table, and jumping to it. Update successor information;
1708 // we will either branch to the default case for the switch, or the jump
1710 MachineBasicBlock *JumpTableBB = new MachineBasicBlock(LLVMBB);
1711 CurMF->getBasicBlockList().insert(BBI, JumpTableBB);
1712 CR.CaseBB->addSuccessor(Default);
1713 CR.CaseBB->addSuccessor(JumpTableBB);
1715 // Build a vector of destination BBs, corresponding to each target
1716 // of the jump table. If the value of the jump table slot corresponds to
1717 // a case statement, push the case's BB onto the vector, otherwise, push
1719 std::vector<MachineBasicBlock*> DestBBs;
1720 int64_t TEI = First;
1721 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++TEI) {
1722 int64_t Low = cast<ConstantInt>(I->Low)->getSExtValue();
1723 int64_t High = cast<ConstantInt>(I->High)->getSExtValue();
1725 if ((Low <= TEI) && (TEI <= High)) {
1726 DestBBs.push_back(I->BB);
1730 DestBBs.push_back(Default);
1734 // Update successor info. Add one edge to each unique successor.
1735 BitVector SuccsHandled(CR.CaseBB->getParent()->getNumBlockIDs());
1736 for (std::vector<MachineBasicBlock*>::iterator I = DestBBs.begin(),
1737 E = DestBBs.end(); I != E; ++I) {
1738 if (!SuccsHandled[(*I)->getNumber()]) {
1739 SuccsHandled[(*I)->getNumber()] = true;
1740 JumpTableBB->addSuccessor(*I);
1744 // Create a jump table index for this jump table, or return an existing
1746 unsigned JTI = CurMF->getJumpTableInfo()->getJumpTableIndex(DestBBs);
1748 // Set the jump table information so that we can codegen it as a second
1749 // MachineBasicBlock
1750 SelectionDAGISel::JumpTable JT(-1U, JTI, JumpTableBB, Default);
1751 SelectionDAGISel::JumpTableHeader JTH(First, Last, SV, CR.CaseBB,
1752 (CR.CaseBB == CurMBB));
1753 if (CR.CaseBB == CurMBB)
1754 visitJumpTableHeader(JT, JTH);
1756 JTCases.push_back(SelectionDAGISel::JumpTableBlock(JTH, JT));
1761 /// handleBTSplitSwitchCase - emit comparison and split binary search tree into
1763 bool SelectionDAGLowering::handleBTSplitSwitchCase(CaseRec& CR,
1764 CaseRecVector& WorkList,
1766 MachineBasicBlock* Default) {
1767 // Get the MachineFunction which holds the current MBB. This is used when
1768 // inserting any additional MBBs necessary to represent the switch.
1769 MachineFunction *CurMF = CurMBB->getParent();
1771 // Figure out which block is immediately after the current one.
1772 MachineBasicBlock *NextBlock = 0;
1773 MachineFunction::iterator BBI = CR.CaseBB;
1775 if (++BBI != CurMBB->getParent()->end())
1778 Case& FrontCase = *CR.Range.first;
1779 Case& BackCase = *(CR.Range.second-1);
1780 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
1782 // Size is the number of Cases represented by this range.
1783 unsigned Size = CR.Range.second - CR.Range.first;
1785 int64_t First = cast<ConstantInt>(FrontCase.Low)->getSExtValue();
1786 int64_t Last = cast<ConstantInt>(BackCase.High)->getSExtValue();
1788 CaseItr Pivot = CR.Range.first + Size/2;
1790 // Select optimal pivot, maximizing sum density of LHS and RHS. This will
1791 // (heuristically) allow us to emit JumpTable's later.
1793 for (CaseItr I = CR.Range.first, E = CR.Range.second;
1797 uint64_t LSize = FrontCase.size();
1798 uint64_t RSize = TSize-LSize;
1799 DOUT << "Selecting best pivot: \n"
1800 << "First: " << First << ", Last: " << Last <<"\n"
1801 << "LSize: " << LSize << ", RSize: " << RSize << "\n";
1802 for (CaseItr I = CR.Range.first, J=I+1, E = CR.Range.second;
1804 int64_t LEnd = cast<ConstantInt>(I->High)->getSExtValue();
1805 int64_t RBegin = cast<ConstantInt>(J->Low)->getSExtValue();
1806 assert((RBegin-LEnd>=1) && "Invalid case distance");
1807 double LDensity = (double)LSize / (double)((LEnd - First) + 1ULL);
1808 double RDensity = (double)RSize / (double)((Last - RBegin) + 1ULL);
1809 double Metric = Log2_64(RBegin-LEnd)*(LDensity+RDensity);
1810 // Should always split in some non-trivial place
1812 << "LEnd: " << LEnd << ", RBegin: " << RBegin << "\n"
1813 << "LDensity: " << LDensity << ", RDensity: " << RDensity << "\n"
1814 << "Metric: " << Metric << "\n";
1815 if (FMetric < Metric) {
1818 DOUT << "Current metric set to: " << FMetric << "\n";
1824 if (areJTsAllowed(TLI)) {
1825 // If our case is dense we *really* should handle it earlier!
1826 assert((FMetric > 0) && "Should handle dense range earlier!");
1828 Pivot = CR.Range.first + Size/2;
1831 CaseRange LHSR(CR.Range.first, Pivot);
1832 CaseRange RHSR(Pivot, CR.Range.second);
1833 Constant *C = Pivot->Low;
1834 MachineBasicBlock *FalseBB = 0, *TrueBB = 0;
1836 // We know that we branch to the LHS if the Value being switched on is
1837 // less than the Pivot value, C. We use this to optimize our binary
1838 // tree a bit, by recognizing that if SV is greater than or equal to the
1839 // LHS's Case Value, and that Case Value is exactly one less than the
1840 // Pivot's Value, then we can branch directly to the LHS's Target,
1841 // rather than creating a leaf node for it.
1842 if ((LHSR.second - LHSR.first) == 1 &&
1843 LHSR.first->High == CR.GE &&
1844 cast<ConstantInt>(C)->getSExtValue() ==
1845 (cast<ConstantInt>(CR.GE)->getSExtValue() + 1LL)) {
1846 TrueBB = LHSR.first->BB;
1848 TrueBB = new MachineBasicBlock(LLVMBB);
1849 CurMF->getBasicBlockList().insert(BBI, TrueBB);
1850 WorkList.push_back(CaseRec(TrueBB, C, CR.GE, LHSR));
1853 // Similar to the optimization above, if the Value being switched on is
1854 // known to be less than the Constant CR.LT, and the current Case Value
1855 // is CR.LT - 1, then we can branch directly to the target block for
1856 // the current Case Value, rather than emitting a RHS leaf node for it.
1857 if ((RHSR.second - RHSR.first) == 1 && CR.LT &&
1858 cast<ConstantInt>(RHSR.first->Low)->getSExtValue() ==
1859 (cast<ConstantInt>(CR.LT)->getSExtValue() - 1LL)) {
1860 FalseBB = RHSR.first->BB;
1862 FalseBB = new MachineBasicBlock(LLVMBB);
1863 CurMF->getBasicBlockList().insert(BBI, FalseBB);
1864 WorkList.push_back(CaseRec(FalseBB,CR.LT,C,RHSR));
1867 // Create a CaseBlock record representing a conditional branch to
1868 // the LHS node if the value being switched on SV is less than C.
1869 // Otherwise, branch to LHS.
1870 SelectionDAGISel::CaseBlock CB(ISD::SETLT, SV, C, NULL,
1871 TrueBB, FalseBB, CR.CaseBB);
1873 if (CR.CaseBB == CurMBB)
1874 visitSwitchCase(CB);
1876 SwitchCases.push_back(CB);
1881 /// handleBitTestsSwitchCase - if current case range has few destination and
1882 /// range span less, than machine word bitwidth, encode case range into series
1883 /// of masks and emit bit tests with these masks.
1884 bool SelectionDAGLowering::handleBitTestsSwitchCase(CaseRec& CR,
1885 CaseRecVector& WorkList,
1887 MachineBasicBlock* Default){
1888 unsigned IntPtrBits = MVT::getSizeInBits(TLI.getPointerTy());
1890 Case& FrontCase = *CR.Range.first;
1891 Case& BackCase = *(CR.Range.second-1);
1893 // Get the MachineFunction which holds the current MBB. This is used when
1894 // inserting any additional MBBs necessary to represent the switch.
1895 MachineFunction *CurMF = CurMBB->getParent();
1897 unsigned numCmps = 0;
1898 for (CaseItr I = CR.Range.first, E = CR.Range.second;
1900 // Single case counts one, case range - two.
1901 if (I->Low == I->High)
1907 // Count unique destinations
1908 SmallSet<MachineBasicBlock*, 4> Dests;
1909 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) {
1910 Dests.insert(I->BB);
1911 if (Dests.size() > 3)
1912 // Don't bother the code below, if there are too much unique destinations
1915 DOUT << "Total number of unique destinations: " << Dests.size() << "\n"
1916 << "Total number of comparisons: " << numCmps << "\n";
1918 // Compute span of values.
1919 Constant* minValue = FrontCase.Low;
1920 Constant* maxValue = BackCase.High;
1921 uint64_t range = cast<ConstantInt>(maxValue)->getSExtValue() -
1922 cast<ConstantInt>(minValue)->getSExtValue();
1923 DOUT << "Compare range: " << range << "\n"
1924 << "Low bound: " << cast<ConstantInt>(minValue)->getSExtValue() << "\n"
1925 << "High bound: " << cast<ConstantInt>(maxValue)->getSExtValue() << "\n";
1927 if (range>=IntPtrBits ||
1928 (!(Dests.size() == 1 && numCmps >= 3) &&
1929 !(Dests.size() == 2 && numCmps >= 5) &&
1930 !(Dests.size() >= 3 && numCmps >= 6)))
1933 DOUT << "Emitting bit tests\n";
1934 int64_t lowBound = 0;
1936 // Optimize the case where all the case values fit in a
1937 // word without having to subtract minValue. In this case,
1938 // we can optimize away the subtraction.
1939 if (cast<ConstantInt>(minValue)->getSExtValue() >= 0 &&
1940 cast<ConstantInt>(maxValue)->getSExtValue() < IntPtrBits) {
1941 range = cast<ConstantInt>(maxValue)->getSExtValue();
1943 lowBound = cast<ConstantInt>(minValue)->getSExtValue();
1946 CaseBitsVector CasesBits;
1947 unsigned i, count = 0;
1949 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) {
1950 MachineBasicBlock* Dest = I->BB;
1951 for (i = 0; i < count; ++i)
1952 if (Dest == CasesBits[i].BB)
1956 assert((count < 3) && "Too much destinations to test!");
1957 CasesBits.push_back(CaseBits(0, Dest, 0));
1961 uint64_t lo = cast<ConstantInt>(I->Low)->getSExtValue() - lowBound;
1962 uint64_t hi = cast<ConstantInt>(I->High)->getSExtValue() - lowBound;
1964 for (uint64_t j = lo; j <= hi; j++) {
1965 CasesBits[i].Mask |= 1ULL << j;
1966 CasesBits[i].Bits++;
1970 std::sort(CasesBits.begin(), CasesBits.end(), CaseBitsCmp());
1972 SelectionDAGISel::BitTestInfo BTC;
1974 // Figure out which block is immediately after the current one.
1975 MachineFunction::iterator BBI = CR.CaseBB;
1978 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
1981 for (unsigned i = 0, e = CasesBits.size(); i!=e; ++i) {
1982 DOUT << "Mask: " << CasesBits[i].Mask << ", Bits: " << CasesBits[i].Bits
1983 << ", BB: " << CasesBits[i].BB << "\n";
1985 MachineBasicBlock *CaseBB = new MachineBasicBlock(LLVMBB);
1986 CurMF->getBasicBlockList().insert(BBI, CaseBB);
1987 BTC.push_back(SelectionDAGISel::BitTestCase(CasesBits[i].Mask,
1992 SelectionDAGISel::BitTestBlock BTB(lowBound, range, SV,
1993 -1U, (CR.CaseBB == CurMBB),
1994 CR.CaseBB, Default, BTC);
1996 if (CR.CaseBB == CurMBB)
1997 visitBitTestHeader(BTB);
1999 BitTestCases.push_back(BTB);
2005 // Clusterify - Transform simple list of Cases into list of CaseRange's
2006 unsigned SelectionDAGLowering::Clusterify(CaseVector& Cases,
2007 const SwitchInst& SI) {
2008 unsigned numCmps = 0;
2010 // Start with "simple" cases
2011 for (unsigned i = 1; i < SI.getNumSuccessors(); ++i) {
2012 MachineBasicBlock *SMBB = FuncInfo.MBBMap[SI.getSuccessor(i)];
2013 Cases.push_back(Case(SI.getSuccessorValue(i),
2014 SI.getSuccessorValue(i),
2017 std::sort(Cases.begin(), Cases.end(), CaseCmp());
2019 // Merge case into clusters
2020 if (Cases.size()>=2)
2021 // Must recompute end() each iteration because it may be
2022 // invalidated by erase if we hold on to it
2023 for (CaseItr I=Cases.begin(), J=++(Cases.begin()); J!=Cases.end(); ) {
2024 int64_t nextValue = cast<ConstantInt>(J->Low)->getSExtValue();
2025 int64_t currentValue = cast<ConstantInt>(I->High)->getSExtValue();
2026 MachineBasicBlock* nextBB = J->BB;
2027 MachineBasicBlock* currentBB = I->BB;
2029 // If the two neighboring cases go to the same destination, merge them
2030 // into a single case.
2031 if ((nextValue-currentValue==1) && (currentBB == nextBB)) {
2039 for (CaseItr I=Cases.begin(), E=Cases.end(); I!=E; ++I, ++numCmps) {
2040 if (I->Low != I->High)
2041 // A range counts double, since it requires two compares.
2048 void SelectionDAGLowering::visitSwitch(SwitchInst &SI) {
2049 // Figure out which block is immediately after the current one.
2050 MachineBasicBlock *NextBlock = 0;
2051 MachineFunction::iterator BBI = CurMBB;
2053 MachineBasicBlock *Default = FuncInfo.MBBMap[SI.getDefaultDest()];
2055 // If there is only the default destination, branch to it if it is not the
2056 // next basic block. Otherwise, just fall through.
2057 if (SI.getNumOperands() == 2) {
2058 // Update machine-CFG edges.
2060 // If this is not a fall-through branch, emit the branch.
2061 if (Default != NextBlock)
2062 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, getRoot(),
2063 DAG.getBasicBlock(Default)));
2065 CurMBB->addSuccessor(Default);
2069 // If there are any non-default case statements, create a vector of Cases
2070 // representing each one, and sort the vector so that we can efficiently
2071 // create a binary search tree from them.
2073 unsigned numCmps = Clusterify(Cases, SI);
2074 DOUT << "Clusterify finished. Total clusters: " << Cases.size()
2075 << ". Total compares: " << numCmps << "\n";
2077 // Get the Value to be switched on and default basic blocks, which will be
2078 // inserted into CaseBlock records, representing basic blocks in the binary
2080 Value *SV = SI.getOperand(0);
2082 // Push the initial CaseRec onto the worklist
2083 CaseRecVector WorkList;
2084 WorkList.push_back(CaseRec(CurMBB,0,0,CaseRange(Cases.begin(),Cases.end())));
2086 while (!WorkList.empty()) {
2087 // Grab a record representing a case range to process off the worklist
2088 CaseRec CR = WorkList.back();
2089 WorkList.pop_back();
2091 if (handleBitTestsSwitchCase(CR, WorkList, SV, Default))
2094 // If the range has few cases (two or less) emit a series of specific
2096 if (handleSmallSwitchRange(CR, WorkList, SV, Default))
2099 // If the switch has more than 5 blocks, and at least 40% dense, and the
2100 // target supports indirect branches, then emit a jump table rather than
2101 // lowering the switch to a binary tree of conditional branches.
2102 if (handleJTSwitchCase(CR, WorkList, SV, Default))
2105 // Emit binary tree. We need to pick a pivot, and push left and right ranges
2106 // onto the worklist. Leafs are handled via handleSmallSwitchRange() call.
2107 handleBTSplitSwitchCase(CR, WorkList, SV, Default);
2112 void SelectionDAGLowering::visitSub(User &I) {
2113 // -0.0 - X --> fneg
2114 const Type *Ty = I.getType();
2115 if (isa<VectorType>(Ty)) {
2116 if (ConstantVector *CV = dyn_cast<ConstantVector>(I.getOperand(0))) {
2117 const VectorType *DestTy = cast<VectorType>(I.getType());
2118 const Type *ElTy = DestTy->getElementType();
2119 if (ElTy->isFloatingPoint()) {
2120 unsigned VL = DestTy->getNumElements();
2121 std::vector<Constant*> NZ(VL, ConstantFP::getNegativeZero(ElTy));
2122 Constant *CNZ = ConstantVector::get(&NZ[0], NZ.size());
2124 SDOperand Op2 = getValue(I.getOperand(1));
2125 setValue(&I, DAG.getNode(ISD::FNEG, Op2.getValueType(), Op2));
2131 if (Ty->isFloatingPoint()) {
2132 if (ConstantFP *CFP = dyn_cast<ConstantFP>(I.getOperand(0)))
2133 if (CFP->isExactlyValue(ConstantFP::getNegativeZero(Ty)->getValueAPF())) {
2134 SDOperand Op2 = getValue(I.getOperand(1));
2135 setValue(&I, DAG.getNode(ISD::FNEG, Op2.getValueType(), Op2));
2140 visitBinary(I, Ty->isFPOrFPVector() ? ISD::FSUB : ISD::SUB);
2143 void SelectionDAGLowering::visitBinary(User &I, unsigned OpCode) {
2144 SDOperand Op1 = getValue(I.getOperand(0));
2145 SDOperand Op2 = getValue(I.getOperand(1));
2147 setValue(&I, DAG.getNode(OpCode, Op1.getValueType(), Op1, Op2));
2150 void SelectionDAGLowering::visitShift(User &I, unsigned Opcode) {
2151 SDOperand Op1 = getValue(I.getOperand(0));
2152 SDOperand Op2 = getValue(I.getOperand(1));
2154 if (MVT::getSizeInBits(TLI.getShiftAmountTy()) <
2155 MVT::getSizeInBits(Op2.getValueType()))
2156 Op2 = DAG.getNode(ISD::TRUNCATE, TLI.getShiftAmountTy(), Op2);
2157 else if (TLI.getShiftAmountTy() > Op2.getValueType())
2158 Op2 = DAG.getNode(ISD::ANY_EXTEND, TLI.getShiftAmountTy(), Op2);
2160 setValue(&I, DAG.getNode(Opcode, Op1.getValueType(), Op1, Op2));
2163 void SelectionDAGLowering::visitICmp(User &I) {
2164 ICmpInst::Predicate predicate = ICmpInst::BAD_ICMP_PREDICATE;
2165 if (ICmpInst *IC = dyn_cast<ICmpInst>(&I))
2166 predicate = IC->getPredicate();
2167 else if (ConstantExpr *IC = dyn_cast<ConstantExpr>(&I))
2168 predicate = ICmpInst::Predicate(IC->getPredicate());
2169 SDOperand Op1 = getValue(I.getOperand(0));
2170 SDOperand Op2 = getValue(I.getOperand(1));
2171 ISD::CondCode Opcode;
2172 switch (predicate) {
2173 case ICmpInst::ICMP_EQ : Opcode = ISD::SETEQ; break;
2174 case ICmpInst::ICMP_NE : Opcode = ISD::SETNE; break;
2175 case ICmpInst::ICMP_UGT : Opcode = ISD::SETUGT; break;
2176 case ICmpInst::ICMP_UGE : Opcode = ISD::SETUGE; break;
2177 case ICmpInst::ICMP_ULT : Opcode = ISD::SETULT; break;
2178 case ICmpInst::ICMP_ULE : Opcode = ISD::SETULE; break;
2179 case ICmpInst::ICMP_SGT : Opcode = ISD::SETGT; break;
2180 case ICmpInst::ICMP_SGE : Opcode = ISD::SETGE; break;
2181 case ICmpInst::ICMP_SLT : Opcode = ISD::SETLT; break;
2182 case ICmpInst::ICMP_SLE : Opcode = ISD::SETLE; break;
2184 assert(!"Invalid ICmp predicate value");
2185 Opcode = ISD::SETEQ;
2188 setValue(&I, DAG.getSetCC(MVT::i1, Op1, Op2, Opcode));
2191 void SelectionDAGLowering::visitFCmp(User &I) {
2192 FCmpInst::Predicate predicate = FCmpInst::BAD_FCMP_PREDICATE;
2193 if (FCmpInst *FC = dyn_cast<FCmpInst>(&I))
2194 predicate = FC->getPredicate();
2195 else if (ConstantExpr *FC = dyn_cast<ConstantExpr>(&I))
2196 predicate = FCmpInst::Predicate(FC->getPredicate());
2197 SDOperand Op1 = getValue(I.getOperand(0));
2198 SDOperand Op2 = getValue(I.getOperand(1));
2199 ISD::CondCode Condition, FOC, FPC;
2200 switch (predicate) {
2201 case FCmpInst::FCMP_FALSE: FOC = FPC = ISD::SETFALSE; break;
2202 case FCmpInst::FCMP_OEQ: FOC = ISD::SETEQ; FPC = ISD::SETOEQ; break;
2203 case FCmpInst::FCMP_OGT: FOC = ISD::SETGT; FPC = ISD::SETOGT; break;
2204 case FCmpInst::FCMP_OGE: FOC = ISD::SETGE; FPC = ISD::SETOGE; break;
2205 case FCmpInst::FCMP_OLT: FOC = ISD::SETLT; FPC = ISD::SETOLT; break;
2206 case FCmpInst::FCMP_OLE: FOC = ISD::SETLE; FPC = ISD::SETOLE; break;
2207 case FCmpInst::FCMP_ONE: FOC = ISD::SETNE; FPC = ISD::SETONE; break;
2208 case FCmpInst::FCMP_ORD: FOC = ISD::SETEQ; FPC = ISD::SETO; break;
2209 case FCmpInst::FCMP_UNO: FOC = ISD::SETNE; FPC = ISD::SETUO; break;
2210 case FCmpInst::FCMP_UEQ: FOC = ISD::SETEQ; FPC = ISD::SETUEQ; break;
2211 case FCmpInst::FCMP_UGT: FOC = ISD::SETGT; FPC = ISD::SETUGT; break;
2212 case FCmpInst::FCMP_UGE: FOC = ISD::SETGE; FPC = ISD::SETUGE; break;
2213 case FCmpInst::FCMP_ULT: FOC = ISD::SETLT; FPC = ISD::SETULT; break;
2214 case FCmpInst::FCMP_ULE: FOC = ISD::SETLE; FPC = ISD::SETULE; break;
2215 case FCmpInst::FCMP_UNE: FOC = ISD::SETNE; FPC = ISD::SETUNE; break;
2216 case FCmpInst::FCMP_TRUE: FOC = FPC = ISD::SETTRUE; break;
2218 assert(!"Invalid FCmp predicate value");
2219 FOC = FPC = ISD::SETFALSE;
2222 if (FiniteOnlyFPMath())
2226 setValue(&I, DAG.getSetCC(MVT::i1, Op1, Op2, Condition));
2229 void SelectionDAGLowering::visitSelect(User &I) {
2230 SDOperand Cond = getValue(I.getOperand(0));
2231 SDOperand TrueVal = getValue(I.getOperand(1));
2232 SDOperand FalseVal = getValue(I.getOperand(2));
2233 setValue(&I, DAG.getNode(ISD::SELECT, TrueVal.getValueType(), Cond,
2234 TrueVal, FalseVal));
2238 void SelectionDAGLowering::visitTrunc(User &I) {
2239 // TruncInst cannot be a no-op cast because sizeof(src) > sizeof(dest).
2240 SDOperand N = getValue(I.getOperand(0));
2241 MVT::ValueType DestVT = TLI.getValueType(I.getType());
2242 setValue(&I, DAG.getNode(ISD::TRUNCATE, DestVT, N));
2245 void SelectionDAGLowering::visitZExt(User &I) {
2246 // ZExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
2247 // ZExt also can't be a cast to bool for same reason. So, nothing much to do
2248 SDOperand N = getValue(I.getOperand(0));
2249 MVT::ValueType DestVT = TLI.getValueType(I.getType());
2250 setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, DestVT, N));
2253 void SelectionDAGLowering::visitSExt(User &I) {
2254 // SExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
2255 // SExt also can't be a cast to bool for same reason. So, nothing much to do
2256 SDOperand N = getValue(I.getOperand(0));
2257 MVT::ValueType DestVT = TLI.getValueType(I.getType());
2258 setValue(&I, DAG.getNode(ISD::SIGN_EXTEND, DestVT, N));
2261 void SelectionDAGLowering::visitFPTrunc(User &I) {
2262 // FPTrunc is never a no-op cast, no need to check
2263 SDOperand N = getValue(I.getOperand(0));
2264 MVT::ValueType DestVT = TLI.getValueType(I.getType());
2265 setValue(&I, DAG.getNode(ISD::FP_ROUND, DestVT, N, DAG.getIntPtrConstant(0)));
2268 void SelectionDAGLowering::visitFPExt(User &I){
2269 // FPTrunc is never a no-op cast, no need to check
2270 SDOperand N = getValue(I.getOperand(0));
2271 MVT::ValueType DestVT = TLI.getValueType(I.getType());
2272 setValue(&I, DAG.getNode(ISD::FP_EXTEND, DestVT, N));
2275 void SelectionDAGLowering::visitFPToUI(User &I) {
2276 // FPToUI is never a no-op cast, no need to check
2277 SDOperand N = getValue(I.getOperand(0));
2278 MVT::ValueType DestVT = TLI.getValueType(I.getType());
2279 setValue(&I, DAG.getNode(ISD::FP_TO_UINT, DestVT, N));
2282 void SelectionDAGLowering::visitFPToSI(User &I) {
2283 // FPToSI is never a no-op cast, no need to check
2284 SDOperand N = getValue(I.getOperand(0));
2285 MVT::ValueType DestVT = TLI.getValueType(I.getType());
2286 setValue(&I, DAG.getNode(ISD::FP_TO_SINT, DestVT, N));
2289 void SelectionDAGLowering::visitUIToFP(User &I) {
2290 // UIToFP is never a no-op cast, no need to check
2291 SDOperand N = getValue(I.getOperand(0));
2292 MVT::ValueType DestVT = TLI.getValueType(I.getType());
2293 setValue(&I, DAG.getNode(ISD::UINT_TO_FP, DestVT, N));
2296 void SelectionDAGLowering::visitSIToFP(User &I){
2297 // UIToFP is never a no-op cast, no need to check
2298 SDOperand N = getValue(I.getOperand(0));
2299 MVT::ValueType DestVT = TLI.getValueType(I.getType());
2300 setValue(&I, DAG.getNode(ISD::SINT_TO_FP, DestVT, N));
2303 void SelectionDAGLowering::visitPtrToInt(User &I) {
2304 // What to do depends on the size of the integer and the size of the pointer.
2305 // We can either truncate, zero extend, or no-op, accordingly.
2306 SDOperand N = getValue(I.getOperand(0));
2307 MVT::ValueType SrcVT = N.getValueType();
2308 MVT::ValueType DestVT = TLI.getValueType(I.getType());
2310 if (MVT::getSizeInBits(DestVT) < MVT::getSizeInBits(SrcVT))
2311 Result = DAG.getNode(ISD::TRUNCATE, DestVT, N);
2313 // Note: ZERO_EXTEND can handle cases where the sizes are equal too
2314 Result = DAG.getNode(ISD::ZERO_EXTEND, DestVT, N);
2315 setValue(&I, Result);
2318 void SelectionDAGLowering::visitIntToPtr(User &I) {
2319 // What to do depends on the size of the integer and the size of the pointer.
2320 // We can either truncate, zero extend, or no-op, accordingly.
2321 SDOperand N = getValue(I.getOperand(0));
2322 MVT::ValueType SrcVT = N.getValueType();
2323 MVT::ValueType DestVT = TLI.getValueType(I.getType());
2324 if (MVT::getSizeInBits(DestVT) < MVT::getSizeInBits(SrcVT))
2325 setValue(&I, DAG.getNode(ISD::TRUNCATE, DestVT, N));
2327 // Note: ZERO_EXTEND can handle cases where the sizes are equal too
2328 setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, DestVT, N));
2331 void SelectionDAGLowering::visitBitCast(User &I) {
2332 SDOperand N = getValue(I.getOperand(0));
2333 MVT::ValueType DestVT = TLI.getValueType(I.getType());
2335 // BitCast assures us that source and destination are the same size so this
2336 // is either a BIT_CONVERT or a no-op.
2337 if (DestVT != N.getValueType())
2338 setValue(&I, DAG.getNode(ISD::BIT_CONVERT, DestVT, N)); // convert types
2340 setValue(&I, N); // noop cast.
2343 void SelectionDAGLowering::visitInsertElement(User &I) {
2344 SDOperand InVec = getValue(I.getOperand(0));
2345 SDOperand InVal = getValue(I.getOperand(1));
2346 SDOperand InIdx = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(),
2347 getValue(I.getOperand(2)));
2349 setValue(&I, DAG.getNode(ISD::INSERT_VECTOR_ELT,
2350 TLI.getValueType(I.getType()),
2351 InVec, InVal, InIdx));
2354 void SelectionDAGLowering::visitExtractElement(User &I) {
2355 SDOperand InVec = getValue(I.getOperand(0));
2356 SDOperand InIdx = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(),
2357 getValue(I.getOperand(1)));
2358 setValue(&I, DAG.getNode(ISD::EXTRACT_VECTOR_ELT,
2359 TLI.getValueType(I.getType()), InVec, InIdx));
2362 void SelectionDAGLowering::visitShuffleVector(User &I) {
2363 SDOperand V1 = getValue(I.getOperand(0));
2364 SDOperand V2 = getValue(I.getOperand(1));
2365 SDOperand Mask = getValue(I.getOperand(2));
2367 setValue(&I, DAG.getNode(ISD::VECTOR_SHUFFLE,
2368 TLI.getValueType(I.getType()),
2373 void SelectionDAGLowering::visitGetElementPtr(User &I) {
2374 SDOperand N = getValue(I.getOperand(0));
2375 const Type *Ty = I.getOperand(0)->getType();
2377 for (GetElementPtrInst::op_iterator OI = I.op_begin()+1, E = I.op_end();
2380 if (const StructType *StTy = dyn_cast<StructType>(Ty)) {
2381 unsigned Field = cast<ConstantInt>(Idx)->getZExtValue();
2384 uint64_t Offset = TD->getStructLayout(StTy)->getElementOffset(Field);
2385 N = DAG.getNode(ISD::ADD, N.getValueType(), N,
2386 DAG.getIntPtrConstant(Offset));
2388 Ty = StTy->getElementType(Field);
2390 Ty = cast<SequentialType>(Ty)->getElementType();
2392 // If this is a constant subscript, handle it quickly.
2393 if (ConstantInt *CI = dyn_cast<ConstantInt>(Idx)) {
2394 if (CI->getZExtValue() == 0) continue;
2396 TD->getABITypeSize(Ty)*cast<ConstantInt>(CI)->getSExtValue();
2397 N = DAG.getNode(ISD::ADD, N.getValueType(), N,
2398 DAG.getIntPtrConstant(Offs));
2402 // N = N + Idx * ElementSize;
2403 uint64_t ElementSize = TD->getABITypeSize(Ty);
2404 SDOperand IdxN = getValue(Idx);
2406 // If the index is smaller or larger than intptr_t, truncate or extend
2408 if (IdxN.getValueType() < N.getValueType()) {
2409 IdxN = DAG.getNode(ISD::SIGN_EXTEND, N.getValueType(), IdxN);
2410 } else if (IdxN.getValueType() > N.getValueType())
2411 IdxN = DAG.getNode(ISD::TRUNCATE, N.getValueType(), IdxN);
2413 // If this is a multiply by a power of two, turn it into a shl
2414 // immediately. This is a very common case.
2415 if (isPowerOf2_64(ElementSize)) {
2416 unsigned Amt = Log2_64(ElementSize);
2417 IdxN = DAG.getNode(ISD::SHL, N.getValueType(), IdxN,
2418 DAG.getConstant(Amt, TLI.getShiftAmountTy()));
2419 N = DAG.getNode(ISD::ADD, N.getValueType(), N, IdxN);
2423 SDOperand Scale = DAG.getIntPtrConstant(ElementSize);
2424 IdxN = DAG.getNode(ISD::MUL, N.getValueType(), IdxN, Scale);
2425 N = DAG.getNode(ISD::ADD, N.getValueType(), N, IdxN);
2431 void SelectionDAGLowering::visitAlloca(AllocaInst &I) {
2432 // If this is a fixed sized alloca in the entry block of the function,
2433 // allocate it statically on the stack.
2434 if (FuncInfo.StaticAllocaMap.count(&I))
2435 return; // getValue will auto-populate this.
2437 const Type *Ty = I.getAllocatedType();
2438 uint64_t TySize = TLI.getTargetData()->getABITypeSize(Ty);
2440 std::max((unsigned)TLI.getTargetData()->getPrefTypeAlignment(Ty),
2443 SDOperand AllocSize = getValue(I.getArraySize());
2444 MVT::ValueType IntPtr = TLI.getPointerTy();
2445 if (IntPtr < AllocSize.getValueType())
2446 AllocSize = DAG.getNode(ISD::TRUNCATE, IntPtr, AllocSize);
2447 else if (IntPtr > AllocSize.getValueType())
2448 AllocSize = DAG.getNode(ISD::ZERO_EXTEND, IntPtr, AllocSize);
2450 AllocSize = DAG.getNode(ISD::MUL, IntPtr, AllocSize,
2451 DAG.getIntPtrConstant(TySize));
2453 // Handle alignment. If the requested alignment is less than or equal to
2454 // the stack alignment, ignore it. If the size is greater than or equal to
2455 // the stack alignment, we note this in the DYNAMIC_STACKALLOC node.
2456 unsigned StackAlign =
2457 TLI.getTargetMachine().getFrameInfo()->getStackAlignment();
2458 if (Align <= StackAlign)
2461 // Round the size of the allocation up to the stack alignment size
2462 // by add SA-1 to the size.
2463 AllocSize = DAG.getNode(ISD::ADD, AllocSize.getValueType(), AllocSize,
2464 DAG.getIntPtrConstant(StackAlign-1));
2465 // Mask out the low bits for alignment purposes.
2466 AllocSize = DAG.getNode(ISD::AND, AllocSize.getValueType(), AllocSize,
2467 DAG.getIntPtrConstant(~(uint64_t)(StackAlign-1)));
2469 SDOperand Ops[] = { getRoot(), AllocSize, DAG.getIntPtrConstant(Align) };
2470 const MVT::ValueType *VTs = DAG.getNodeValueTypes(AllocSize.getValueType(),
2472 SDOperand DSA = DAG.getNode(ISD::DYNAMIC_STACKALLOC, VTs, 2, Ops, 3);
2474 DAG.setRoot(DSA.getValue(1));
2476 // Inform the Frame Information that we have just allocated a variable-sized
2478 CurMBB->getParent()->getFrameInfo()->CreateVariableSizedObject();
2481 void SelectionDAGLowering::visitLoad(LoadInst &I) {
2482 SDOperand Ptr = getValue(I.getOperand(0));
2488 // Do not serialize non-volatile loads against each other.
2489 Root = DAG.getRoot();
2492 setValue(&I, getLoadFrom(I.getType(), Ptr, I.getOperand(0),
2493 Root, I.isVolatile(), I.getAlignment()));
2496 SDOperand SelectionDAGLowering::getLoadFrom(const Type *Ty, SDOperand Ptr,
2497 const Value *SV, SDOperand Root,
2499 unsigned Alignment) {
2501 DAG.getLoad(TLI.getValueType(Ty), Root, Ptr, SV, 0,
2502 isVolatile, Alignment);
2505 DAG.setRoot(L.getValue(1));
2507 PendingLoads.push_back(L.getValue(1));
2513 void SelectionDAGLowering::visitStore(StoreInst &I) {
2514 Value *SrcV = I.getOperand(0);
2515 SDOperand Src = getValue(SrcV);
2516 SDOperand Ptr = getValue(I.getOperand(1));
2517 DAG.setRoot(DAG.getStore(getRoot(), Src, Ptr, I.getOperand(1), 0,
2518 I.isVolatile(), I.getAlignment()));
2521 /// visitTargetIntrinsic - Lower a call of a target intrinsic to an INTRINSIC
2523 void SelectionDAGLowering::visitTargetIntrinsic(CallInst &I,
2524 unsigned Intrinsic) {
2525 bool HasChain = !I.doesNotAccessMemory();
2526 bool OnlyLoad = HasChain && I.onlyReadsMemory();
2528 // Build the operand list.
2529 SmallVector<SDOperand, 8> Ops;
2530 if (HasChain) { // If this intrinsic has side-effects, chainify it.
2532 // We don't need to serialize loads against other loads.
2533 Ops.push_back(DAG.getRoot());
2535 Ops.push_back(getRoot());
2539 // Add the intrinsic ID as an integer operand.
2540 Ops.push_back(DAG.getConstant(Intrinsic, TLI.getPointerTy()));
2542 // Add all operands of the call to the operand list.
2543 for (unsigned i = 1, e = I.getNumOperands(); i != e; ++i) {
2544 SDOperand Op = getValue(I.getOperand(i));
2545 assert(TLI.isTypeLegal(Op.getValueType()) &&
2546 "Intrinsic uses a non-legal type?");
2550 std::vector<MVT::ValueType> VTs;
2551 if (I.getType() != Type::VoidTy) {
2552 MVT::ValueType VT = TLI.getValueType(I.getType());
2553 if (MVT::isVector(VT)) {
2554 const VectorType *DestTy = cast<VectorType>(I.getType());
2555 MVT::ValueType EltVT = TLI.getValueType(DestTy->getElementType());
2557 VT = MVT::getVectorType(EltVT, DestTy->getNumElements());
2558 assert(VT != MVT::Other && "Intrinsic uses a non-legal type?");
2561 assert(TLI.isTypeLegal(VT) && "Intrinsic uses a non-legal type?");
2565 VTs.push_back(MVT::Other);
2567 const MVT::ValueType *VTList = DAG.getNodeValueTypes(VTs);
2572 Result = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, VTList, VTs.size(),
2573 &Ops[0], Ops.size());
2574 else if (I.getType() != Type::VoidTy)
2575 Result = DAG.getNode(ISD::INTRINSIC_W_CHAIN, VTList, VTs.size(),
2576 &Ops[0], Ops.size());
2578 Result = DAG.getNode(ISD::INTRINSIC_VOID, VTList, VTs.size(),
2579 &Ops[0], Ops.size());
2582 SDOperand Chain = Result.getValue(Result.Val->getNumValues()-1);
2584 PendingLoads.push_back(Chain);
2588 if (I.getType() != Type::VoidTy) {
2589 if (const VectorType *PTy = dyn_cast<VectorType>(I.getType())) {
2590 MVT::ValueType VT = TLI.getValueType(PTy);
2591 Result = DAG.getNode(ISD::BIT_CONVERT, VT, Result);
2593 setValue(&I, Result);
2597 /// ExtractTypeInfo - Returns the type info, possibly bitcast, encoded in V.
2598 static GlobalVariable *ExtractTypeInfo (Value *V) {
2599 V = IntrinsicInst::StripPointerCasts(V);
2600 GlobalVariable *GV = dyn_cast<GlobalVariable>(V);
2601 assert (GV || isa<ConstantPointerNull>(V) &&
2602 "TypeInfo must be a global variable or NULL");
2606 /// addCatchInfo - Extract the personality and type infos from an eh.selector
2607 /// call, and add them to the specified machine basic block.
2608 static void addCatchInfo(CallInst &I, MachineModuleInfo *MMI,
2609 MachineBasicBlock *MBB) {
2610 // Inform the MachineModuleInfo of the personality for this landing pad.
2611 ConstantExpr *CE = cast<ConstantExpr>(I.getOperand(2));
2612 assert(CE->getOpcode() == Instruction::BitCast &&
2613 isa<Function>(CE->getOperand(0)) &&
2614 "Personality should be a function");
2615 MMI->addPersonality(MBB, cast<Function>(CE->getOperand(0)));
2617 // Gather all the type infos for this landing pad and pass them along to
2618 // MachineModuleInfo.
2619 std::vector<GlobalVariable *> TyInfo;
2620 unsigned N = I.getNumOperands();
2622 for (unsigned i = N - 1; i > 2; --i) {
2623 if (ConstantInt *CI = dyn_cast<ConstantInt>(I.getOperand(i))) {
2624 unsigned FilterLength = CI->getZExtValue();
2625 unsigned FirstCatch = i + FilterLength + !FilterLength;
2626 assert (FirstCatch <= N && "Invalid filter length");
2628 if (FirstCatch < N) {
2629 TyInfo.reserve(N - FirstCatch);
2630 for (unsigned j = FirstCatch; j < N; ++j)
2631 TyInfo.push_back(ExtractTypeInfo(I.getOperand(j)));
2632 MMI->addCatchTypeInfo(MBB, TyInfo);
2636 if (!FilterLength) {
2638 MMI->addCleanup(MBB);
2641 TyInfo.reserve(FilterLength - 1);
2642 for (unsigned j = i + 1; j < FirstCatch; ++j)
2643 TyInfo.push_back(ExtractTypeInfo(I.getOperand(j)));
2644 MMI->addFilterTypeInfo(MBB, TyInfo);
2653 TyInfo.reserve(N - 3);
2654 for (unsigned j = 3; j < N; ++j)
2655 TyInfo.push_back(ExtractTypeInfo(I.getOperand(j)));
2656 MMI->addCatchTypeInfo(MBB, TyInfo);
2660 /// visitIntrinsicCall - Lower the call to the specified intrinsic function. If
2661 /// we want to emit this as a call to a named external function, return the name
2662 /// otherwise lower it and return null.
2664 SelectionDAGLowering::visitIntrinsicCall(CallInst &I, unsigned Intrinsic) {
2665 switch (Intrinsic) {
2667 // By default, turn this into a target intrinsic node.
2668 visitTargetIntrinsic(I, Intrinsic);
2670 case Intrinsic::vastart: visitVAStart(I); return 0;
2671 case Intrinsic::vaend: visitVAEnd(I); return 0;
2672 case Intrinsic::vacopy: visitVACopy(I); return 0;
2673 case Intrinsic::returnaddress:
2674 setValue(&I, DAG.getNode(ISD::RETURNADDR, TLI.getPointerTy(),
2675 getValue(I.getOperand(1))));
2677 case Intrinsic::frameaddress:
2678 setValue(&I, DAG.getNode(ISD::FRAMEADDR, TLI.getPointerTy(),
2679 getValue(I.getOperand(1))));
2681 case Intrinsic::setjmp:
2682 return "_setjmp"+!TLI.usesUnderscoreSetJmp();
2684 case Intrinsic::longjmp:
2685 return "_longjmp"+!TLI.usesUnderscoreLongJmp();
2687 case Intrinsic::memcpy_i32:
2688 case Intrinsic::memcpy_i64:
2689 visitMemIntrinsic(I, ISD::MEMCPY);
2691 case Intrinsic::memset_i32:
2692 case Intrinsic::memset_i64:
2693 visitMemIntrinsic(I, ISD::MEMSET);
2695 case Intrinsic::memmove_i32:
2696 case Intrinsic::memmove_i64:
2697 visitMemIntrinsic(I, ISD::MEMMOVE);
2700 case Intrinsic::dbg_stoppoint: {
2701 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
2702 DbgStopPointInst &SPI = cast<DbgStopPointInst>(I);
2703 if (MMI && SPI.getContext() && MMI->Verify(SPI.getContext())) {
2707 Ops[1] = getValue(SPI.getLineValue());
2708 Ops[2] = getValue(SPI.getColumnValue());
2710 DebugInfoDesc *DD = MMI->getDescFor(SPI.getContext());
2711 assert(DD && "Not a debug information descriptor");
2712 CompileUnitDesc *CompileUnit = cast<CompileUnitDesc>(DD);
2714 Ops[3] = DAG.getString(CompileUnit->getFileName());
2715 Ops[4] = DAG.getString(CompileUnit->getDirectory());
2717 DAG.setRoot(DAG.getNode(ISD::LOCATION, MVT::Other, Ops, 5));
2722 case Intrinsic::dbg_region_start: {
2723 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
2724 DbgRegionStartInst &RSI = cast<DbgRegionStartInst>(I);
2725 if (MMI && RSI.getContext() && MMI->Verify(RSI.getContext())) {
2726 unsigned LabelID = MMI->RecordRegionStart(RSI.getContext());
2727 DAG.setRoot(DAG.getNode(ISD::LABEL, MVT::Other, getRoot(),
2728 DAG.getConstant(LabelID, MVT::i32),
2729 DAG.getConstant(0, MVT::i32)));
2734 case Intrinsic::dbg_region_end: {
2735 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
2736 DbgRegionEndInst &REI = cast<DbgRegionEndInst>(I);
2737 if (MMI && REI.getContext() && MMI->Verify(REI.getContext())) {
2738 unsigned LabelID = MMI->RecordRegionEnd(REI.getContext());
2739 DAG.setRoot(DAG.getNode(ISD::LABEL, MVT::Other, getRoot(),
2740 DAG.getConstant(LabelID, MVT::i32),
2741 DAG.getConstant(0, MVT::i32)));
2746 case Intrinsic::dbg_func_start: {
2747 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
2749 DbgFuncStartInst &FSI = cast<DbgFuncStartInst>(I);
2750 Value *SP = FSI.getSubprogram();
2751 if (SP && MMI->Verify(SP)) {
2752 // llvm.dbg.func.start implicitly defines a dbg_stoppoint which is
2753 // what (most?) gdb expects.
2754 DebugInfoDesc *DD = MMI->getDescFor(SP);
2755 assert(DD && "Not a debug information descriptor");
2756 SubprogramDesc *Subprogram = cast<SubprogramDesc>(DD);
2757 const CompileUnitDesc *CompileUnit = Subprogram->getFile();
2758 unsigned SrcFile = MMI->RecordSource(CompileUnit->getDirectory(),
2759 CompileUnit->getFileName());
2760 // Record the source line but does create a label. It will be emitted
2761 // at asm emission time.
2762 MMI->RecordSourceLine(Subprogram->getLine(), 0, SrcFile);
2767 case Intrinsic::dbg_declare: {
2768 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
2769 DbgDeclareInst &DI = cast<DbgDeclareInst>(I);
2770 Value *Variable = DI.getVariable();
2771 if (MMI && Variable && MMI->Verify(Variable))
2772 DAG.setRoot(DAG.getNode(ISD::DECLARE, MVT::Other, getRoot(),
2773 getValue(DI.getAddress()), getValue(Variable)));
2777 case Intrinsic::eh_exception: {
2778 if (ExceptionHandling) {
2779 if (!CurMBB->isLandingPad()) {
2780 // FIXME: Mark exception register as live in. Hack for PR1508.
2781 unsigned Reg = TLI.getExceptionAddressRegister();
2782 if (Reg) CurMBB->addLiveIn(Reg);
2784 // Insert the EXCEPTIONADDR instruction.
2785 SDVTList VTs = DAG.getVTList(TLI.getPointerTy(), MVT::Other);
2787 Ops[0] = DAG.getRoot();
2788 SDOperand Op = DAG.getNode(ISD::EXCEPTIONADDR, VTs, Ops, 1);
2790 DAG.setRoot(Op.getValue(1));
2792 setValue(&I, DAG.getConstant(0, TLI.getPointerTy()));
2797 case Intrinsic::eh_selector_i32:
2798 case Intrinsic::eh_selector_i64: {
2799 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
2800 MVT::ValueType VT = (Intrinsic == Intrinsic::eh_selector_i32 ?
2801 MVT::i32 : MVT::i64);
2803 if (ExceptionHandling && MMI) {
2804 if (CurMBB->isLandingPad())
2805 addCatchInfo(I, MMI, CurMBB);
2808 FuncInfo.CatchInfoLost.insert(&I);
2810 // FIXME: Mark exception selector register as live in. Hack for PR1508.
2811 unsigned Reg = TLI.getExceptionSelectorRegister();
2812 if (Reg) CurMBB->addLiveIn(Reg);
2815 // Insert the EHSELECTION instruction.
2816 SDVTList VTs = DAG.getVTList(VT, MVT::Other);
2818 Ops[0] = getValue(I.getOperand(1));
2820 SDOperand Op = DAG.getNode(ISD::EHSELECTION, VTs, Ops, 2);
2822 DAG.setRoot(Op.getValue(1));
2824 setValue(&I, DAG.getConstant(0, VT));
2830 case Intrinsic::eh_typeid_for_i32:
2831 case Intrinsic::eh_typeid_for_i64: {
2832 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
2833 MVT::ValueType VT = (Intrinsic == Intrinsic::eh_typeid_for_i32 ?
2834 MVT::i32 : MVT::i64);
2837 // Find the type id for the given typeinfo.
2838 GlobalVariable *GV = ExtractTypeInfo(I.getOperand(1));
2840 unsigned TypeID = MMI->getTypeIDFor(GV);
2841 setValue(&I, DAG.getConstant(TypeID, VT));
2843 // Return something different to eh_selector.
2844 setValue(&I, DAG.getConstant(1, VT));
2850 case Intrinsic::eh_return: {
2851 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
2853 if (MMI && ExceptionHandling) {
2854 MMI->setCallsEHReturn(true);
2855 DAG.setRoot(DAG.getNode(ISD::EH_RETURN,
2858 getValue(I.getOperand(1)),
2859 getValue(I.getOperand(2))));
2861 setValue(&I, DAG.getConstant(0, TLI.getPointerTy()));
2867 case Intrinsic::eh_unwind_init: {
2868 if (MachineModuleInfo *MMI = DAG.getMachineModuleInfo()) {
2869 MMI->setCallsUnwindInit(true);
2875 case Intrinsic::eh_dwarf_cfa: {
2876 if (ExceptionHandling) {
2877 MVT::ValueType VT = getValue(I.getOperand(1)).getValueType();
2879 if (MVT::getSizeInBits(VT) > MVT::getSizeInBits(TLI.getPointerTy()))
2880 CfaArg = DAG.getNode(ISD::TRUNCATE,
2881 TLI.getPointerTy(), getValue(I.getOperand(1)));
2883 CfaArg = DAG.getNode(ISD::SIGN_EXTEND,
2884 TLI.getPointerTy(), getValue(I.getOperand(1)));
2886 SDOperand Offset = DAG.getNode(ISD::ADD,
2888 DAG.getNode(ISD::FRAME_TO_ARGS_OFFSET,
2889 TLI.getPointerTy()),
2891 setValue(&I, DAG.getNode(ISD::ADD,
2893 DAG.getNode(ISD::FRAMEADDR,
2896 TLI.getPointerTy())),
2899 setValue(&I, DAG.getConstant(0, TLI.getPointerTy()));
2905 case Intrinsic::sqrt:
2906 setValue(&I, DAG.getNode(ISD::FSQRT,
2907 getValue(I.getOperand(1)).getValueType(),
2908 getValue(I.getOperand(1))));
2910 case Intrinsic::powi:
2911 setValue(&I, DAG.getNode(ISD::FPOWI,
2912 getValue(I.getOperand(1)).getValueType(),
2913 getValue(I.getOperand(1)),
2914 getValue(I.getOperand(2))));
2916 case Intrinsic::sin:
2917 setValue(&I, DAG.getNode(ISD::FSIN,
2918 getValue(I.getOperand(1)).getValueType(),
2919 getValue(I.getOperand(1))));
2921 case Intrinsic::cos:
2922 setValue(&I, DAG.getNode(ISD::FCOS,
2923 getValue(I.getOperand(1)).getValueType(),
2924 getValue(I.getOperand(1))));
2926 case Intrinsic::pow:
2927 setValue(&I, DAG.getNode(ISD::FPOW,
2928 getValue(I.getOperand(1)).getValueType(),
2929 getValue(I.getOperand(1)),
2930 getValue(I.getOperand(2))));
2932 case Intrinsic::pcmarker: {
2933 SDOperand Tmp = getValue(I.getOperand(1));
2934 DAG.setRoot(DAG.getNode(ISD::PCMARKER, MVT::Other, getRoot(), Tmp));
2937 case Intrinsic::readcyclecounter: {
2938 SDOperand Op = getRoot();
2939 SDOperand Tmp = DAG.getNode(ISD::READCYCLECOUNTER,
2940 DAG.getNodeValueTypes(MVT::i64, MVT::Other), 2,
2943 DAG.setRoot(Tmp.getValue(1));
2946 case Intrinsic::part_select: {
2947 // Currently not implemented: just abort
2948 assert(0 && "part_select intrinsic not implemented");
2951 case Intrinsic::part_set: {
2952 // Currently not implemented: just abort
2953 assert(0 && "part_set intrinsic not implemented");
2956 case Intrinsic::bswap:
2957 setValue(&I, DAG.getNode(ISD::BSWAP,
2958 getValue(I.getOperand(1)).getValueType(),
2959 getValue(I.getOperand(1))));
2961 case Intrinsic::cttz: {
2962 SDOperand Arg = getValue(I.getOperand(1));
2963 MVT::ValueType Ty = Arg.getValueType();
2964 SDOperand result = DAG.getNode(ISD::CTTZ, Ty, Arg);
2965 setValue(&I, result);
2968 case Intrinsic::ctlz: {
2969 SDOperand Arg = getValue(I.getOperand(1));
2970 MVT::ValueType Ty = Arg.getValueType();
2971 SDOperand result = DAG.getNode(ISD::CTLZ, Ty, Arg);
2972 setValue(&I, result);
2975 case Intrinsic::ctpop: {
2976 SDOperand Arg = getValue(I.getOperand(1));
2977 MVT::ValueType Ty = Arg.getValueType();
2978 SDOperand result = DAG.getNode(ISD::CTPOP, Ty, Arg);
2979 setValue(&I, result);
2982 case Intrinsic::stacksave: {
2983 SDOperand Op = getRoot();
2984 SDOperand Tmp = DAG.getNode(ISD::STACKSAVE,
2985 DAG.getNodeValueTypes(TLI.getPointerTy(), MVT::Other), 2, &Op, 1);
2987 DAG.setRoot(Tmp.getValue(1));
2990 case Intrinsic::stackrestore: {
2991 SDOperand Tmp = getValue(I.getOperand(1));
2992 DAG.setRoot(DAG.getNode(ISD::STACKRESTORE, MVT::Other, getRoot(), Tmp));
2995 case Intrinsic::prefetch:
2996 // FIXME: Currently discarding prefetches.
2999 case Intrinsic::var_annotation:
3000 // Discard annotate attributes
3003 case Intrinsic::init_trampoline: {
3005 cast<Function>(IntrinsicInst::StripPointerCasts(I.getOperand(2)));
3009 Ops[1] = getValue(I.getOperand(1));
3010 Ops[2] = getValue(I.getOperand(2));
3011 Ops[3] = getValue(I.getOperand(3));
3012 Ops[4] = DAG.getSrcValue(I.getOperand(1));
3013 Ops[5] = DAG.getSrcValue(F);
3015 SDOperand Tmp = DAG.getNode(ISD::TRAMPOLINE,
3016 DAG.getNodeValueTypes(TLI.getPointerTy(),
3021 DAG.setRoot(Tmp.getValue(1));
3025 case Intrinsic::gcroot:
3027 Value *Alloca = I.getOperand(1);
3028 Constant *TypeMap = cast<Constant>(I.getOperand(2));
3030 FrameIndexSDNode *FI = cast<FrameIndexSDNode>(getValue(Alloca).Val);
3031 GCI->addStackRoot(FI->getIndex(), TypeMap);
3035 case Intrinsic::gcread:
3036 case Intrinsic::gcwrite:
3037 assert(0 && "Collector failed to lower gcread/gcwrite intrinsics!");
3040 case Intrinsic::flt_rounds: {
3041 setValue(&I, DAG.getNode(ISD::FLT_ROUNDS_, MVT::i32));
3045 case Intrinsic::trap: {
3046 DAG.setRoot(DAG.getNode(ISD::TRAP, MVT::Other, getRoot()));
3049 case Intrinsic::memory_barrier: {
3052 for (int x = 1; x < 6; ++x)
3053 Ops[x] = getValue(I.getOperand(x));
3055 DAG.setRoot(DAG.getNode(ISD::MEMBARRIER, MVT::Other, &Ops[0], 6));
3062 void SelectionDAGLowering::LowerCallTo(CallSite CS, SDOperand Callee,
3064 MachineBasicBlock *LandingPad) {
3065 const PointerType *PT = cast<PointerType>(CS.getCalledValue()->getType());
3066 const FunctionType *FTy = cast<FunctionType>(PT->getElementType());
3067 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
3068 unsigned BeginLabel = 0, EndLabel = 0;
3070 TargetLowering::ArgListTy Args;
3071 TargetLowering::ArgListEntry Entry;
3072 Args.reserve(CS.arg_size());
3073 for (CallSite::arg_iterator i = CS.arg_begin(), e = CS.arg_end();
3075 SDOperand ArgNode = getValue(*i);
3076 Entry.Node = ArgNode; Entry.Ty = (*i)->getType();
3078 unsigned attrInd = i - CS.arg_begin() + 1;
3079 Entry.isSExt = CS.paramHasAttr(attrInd, ParamAttr::SExt);
3080 Entry.isZExt = CS.paramHasAttr(attrInd, ParamAttr::ZExt);
3081 Entry.isInReg = CS.paramHasAttr(attrInd, ParamAttr::InReg);
3082 Entry.isSRet = CS.paramHasAttr(attrInd, ParamAttr::StructRet);
3083 Entry.isNest = CS.paramHasAttr(attrInd, ParamAttr::Nest);
3084 Entry.isByVal = CS.paramHasAttr(attrInd, ParamAttr::ByVal);
3085 Args.push_back(Entry);
3088 bool MarkTryRange = LandingPad ||
3089 // C++ requires special handling of 'nounwind' calls.
3090 (CS.doesNotThrow());
3092 if (MarkTryRange && ExceptionHandling && MMI) {
3093 // Insert a label before the invoke call to mark the try range. This can be
3094 // used to detect deletion of the invoke via the MachineModuleInfo.
3095 BeginLabel = MMI->NextLabelID();
3096 DAG.setRoot(DAG.getNode(ISD::LABEL, MVT::Other, getRoot(),
3097 DAG.getConstant(BeginLabel, MVT::i32),
3098 DAG.getConstant(1, MVT::i32)));
3101 std::pair<SDOperand,SDOperand> Result =
3102 TLI.LowerCallTo(getRoot(), CS.getType(),
3103 CS.paramHasAttr(0, ParamAttr::SExt),
3104 CS.paramHasAttr(0, ParamAttr::ZExt),
3105 FTy->isVarArg(), CS.getCallingConv(), IsTailCall,
3107 if (CS.getType() != Type::VoidTy)
3108 setValue(CS.getInstruction(), Result.first);
3109 DAG.setRoot(Result.second);
3111 if (MarkTryRange && ExceptionHandling && MMI) {
3112 // Insert a label at the end of the invoke call to mark the try range. This
3113 // can be used to detect deletion of the invoke via the MachineModuleInfo.
3114 EndLabel = MMI->NextLabelID();
3115 DAG.setRoot(DAG.getNode(ISD::LABEL, MVT::Other, getRoot(),
3116 DAG.getConstant(EndLabel, MVT::i32),
3117 DAG.getConstant(1, MVT::i32)));
3119 // Inform MachineModuleInfo of range.
3120 MMI->addInvoke(LandingPad, BeginLabel, EndLabel);
3125 void SelectionDAGLowering::visitCall(CallInst &I) {
3126 const char *RenameFn = 0;
3127 if (Function *F = I.getCalledFunction()) {
3128 if (F->isDeclaration()) {
3129 if (unsigned IID = F->getIntrinsicID()) {
3130 RenameFn = visitIntrinsicCall(I, IID);
3136 // Check for well-known libc/libm calls. If the function is internal, it
3137 // can't be a library call.
3138 unsigned NameLen = F->getNameLen();
3139 if (!F->hasInternalLinkage() && NameLen) {
3140 const char *NameStr = F->getNameStart();
3141 if (NameStr[0] == 'c' &&
3142 ((NameLen == 8 && !strcmp(NameStr, "copysign")) ||
3143 (NameLen == 9 && !strcmp(NameStr, "copysignf")))) {
3144 if (I.getNumOperands() == 3 && // Basic sanity checks.
3145 I.getOperand(1)->getType()->isFloatingPoint() &&
3146 I.getType() == I.getOperand(1)->getType() &&
3147 I.getType() == I.getOperand(2)->getType()) {
3148 SDOperand LHS = getValue(I.getOperand(1));
3149 SDOperand RHS = getValue(I.getOperand(2));
3150 setValue(&I, DAG.getNode(ISD::FCOPYSIGN, LHS.getValueType(),
3154 } else if (NameStr[0] == 'f' &&
3155 ((NameLen == 4 && !strcmp(NameStr, "fabs")) ||
3156 (NameLen == 5 && !strcmp(NameStr, "fabsf")) ||
3157 (NameLen == 5 && !strcmp(NameStr, "fabsl")))) {
3158 if (I.getNumOperands() == 2 && // Basic sanity checks.
3159 I.getOperand(1)->getType()->isFloatingPoint() &&
3160 I.getType() == I.getOperand(1)->getType()) {
3161 SDOperand Tmp = getValue(I.getOperand(1));
3162 setValue(&I, DAG.getNode(ISD::FABS, Tmp.getValueType(), Tmp));
3165 } else if (NameStr[0] == 's' &&
3166 ((NameLen == 3 && !strcmp(NameStr, "sin")) ||
3167 (NameLen == 4 && !strcmp(NameStr, "sinf")) ||
3168 (NameLen == 4 && !strcmp(NameStr, "sinl")))) {
3169 if (I.getNumOperands() == 2 && // Basic sanity checks.
3170 I.getOperand(1)->getType()->isFloatingPoint() &&
3171 I.getType() == I.getOperand(1)->getType()) {
3172 SDOperand Tmp = getValue(I.getOperand(1));
3173 setValue(&I, DAG.getNode(ISD::FSIN, Tmp.getValueType(), Tmp));
3176 } else if (NameStr[0] == 'c' &&
3177 ((NameLen == 3 && !strcmp(NameStr, "cos")) ||
3178 (NameLen == 4 && !strcmp(NameStr, "cosf")) ||
3179 (NameLen == 4 && !strcmp(NameStr, "cosl")))) {
3180 if (I.getNumOperands() == 2 && // Basic sanity checks.
3181 I.getOperand(1)->getType()->isFloatingPoint() &&
3182 I.getType() == I.getOperand(1)->getType()) {
3183 SDOperand Tmp = getValue(I.getOperand(1));
3184 setValue(&I, DAG.getNode(ISD::FCOS, Tmp.getValueType(), Tmp));
3189 } else if (isa<InlineAsm>(I.getOperand(0))) {
3196 Callee = getValue(I.getOperand(0));
3198 Callee = DAG.getExternalSymbol(RenameFn, TLI.getPointerTy());
3200 LowerCallTo(&I, Callee, I.isTailCall());
3204 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from
3205 /// this value and returns the result as a ValueVT value. This uses
3206 /// Chain/Flag as the input and updates them for the output Chain/Flag.
3207 /// If the Flag pointer is NULL, no flag is used.
3208 SDOperand RegsForValue::getCopyFromRegs(SelectionDAG &DAG,
3209 SDOperand &Chain, SDOperand *Flag)const{
3210 // Copy the legal parts from the registers.
3211 unsigned NumParts = Regs.size();
3212 SmallVector<SDOperand, 8> Parts(NumParts);
3213 for (unsigned i = 0; i != NumParts; ++i) {
3214 SDOperand Part = Flag ?
3215 DAG.getCopyFromReg(Chain, Regs[i], RegVT, *Flag) :
3216 DAG.getCopyFromReg(Chain, Regs[i], RegVT);
3217 Chain = Part.getValue(1);
3219 *Flag = Part.getValue(2);
3223 // Assemble the legal parts into the final value.
3224 return getCopyFromParts(DAG, &Parts[0], NumParts, RegVT, ValueVT);
3227 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
3228 /// specified value into the registers specified by this object. This uses
3229 /// Chain/Flag as the input and updates them for the output Chain/Flag.
3230 /// If the Flag pointer is NULL, no flag is used.
3231 void RegsForValue::getCopyToRegs(SDOperand Val, SelectionDAG &DAG,
3232 SDOperand &Chain, SDOperand *Flag) const {
3233 // Get the list of the values's legal parts.
3234 unsigned NumParts = Regs.size();
3235 SmallVector<SDOperand, 8> Parts(NumParts);
3236 getCopyToParts(DAG, Val, &Parts[0], NumParts, RegVT);
3238 // Copy the parts into the registers.
3239 for (unsigned i = 0; i != NumParts; ++i) {
3240 SDOperand Part = Flag ?
3241 DAG.getCopyToReg(Chain, Regs[i], Parts[i], *Flag) :
3242 DAG.getCopyToReg(Chain, Regs[i], Parts[i]);
3243 Chain = Part.getValue(0);
3245 *Flag = Part.getValue(1);
3249 /// AddInlineAsmOperands - Add this value to the specified inlineasm node
3250 /// operand list. This adds the code marker and includes the number of
3251 /// values added into it.
3252 void RegsForValue::AddInlineAsmOperands(unsigned Code, SelectionDAG &DAG,
3253 std::vector<SDOperand> &Ops) const {
3254 MVT::ValueType IntPtrTy = DAG.getTargetLoweringInfo().getPointerTy();
3255 Ops.push_back(DAG.getTargetConstant(Code | (Regs.size() << 3), IntPtrTy));
3256 for (unsigned i = 0, e = Regs.size(); i != e; ++i)
3257 Ops.push_back(DAG.getRegister(Regs[i], RegVT));
3260 /// isAllocatableRegister - If the specified register is safe to allocate,
3261 /// i.e. it isn't a stack pointer or some other special register, return the
3262 /// register class for the register. Otherwise, return null.
3263 static const TargetRegisterClass *
3264 isAllocatableRegister(unsigned Reg, MachineFunction &MF,
3265 const TargetLowering &TLI,
3266 const TargetRegisterInfo *TRI) {
3267 MVT::ValueType FoundVT = MVT::Other;
3268 const TargetRegisterClass *FoundRC = 0;
3269 for (TargetRegisterInfo::regclass_iterator RCI = TRI->regclass_begin(),
3270 E = TRI->regclass_end(); RCI != E; ++RCI) {
3271 MVT::ValueType ThisVT = MVT::Other;
3273 const TargetRegisterClass *RC = *RCI;
3274 // If none of the the value types for this register class are valid, we
3275 // can't use it. For example, 64-bit reg classes on 32-bit targets.
3276 for (TargetRegisterClass::vt_iterator I = RC->vt_begin(), E = RC->vt_end();
3278 if (TLI.isTypeLegal(*I)) {
3279 // If we have already found this register in a different register class,
3280 // choose the one with the largest VT specified. For example, on
3281 // PowerPC, we favor f64 register classes over f32.
3282 if (FoundVT == MVT::Other ||
3283 MVT::getSizeInBits(FoundVT) < MVT::getSizeInBits(*I)) {
3290 if (ThisVT == MVT::Other) continue;
3292 // NOTE: This isn't ideal. In particular, this might allocate the
3293 // frame pointer in functions that need it (due to them not being taken
3294 // out of allocation, because a variable sized allocation hasn't been seen
3295 // yet). This is a slight code pessimization, but should still work.
3296 for (TargetRegisterClass::iterator I = RC->allocation_order_begin(MF),
3297 E = RC->allocation_order_end(MF); I != E; ++I)
3299 // We found a matching register class. Keep looking at others in case
3300 // we find one with larger registers that this physreg is also in.
3311 /// AsmOperandInfo - This contains information for each constraint that we are
3313 struct AsmOperandInfo : public InlineAsm::ConstraintInfo {
3314 /// ConstraintCode - This contains the actual string for the code, like "m".
3315 std::string ConstraintCode;
3317 /// ConstraintType - Information about the constraint code, e.g. Register,
3318 /// RegisterClass, Memory, Other, Unknown.
3319 TargetLowering::ConstraintType ConstraintType;
3321 /// CallOperand/CallOperandval - If this is the result output operand or a
3322 /// clobber, this is null, otherwise it is the incoming operand to the
3323 /// CallInst. This gets modified as the asm is processed.
3324 SDOperand CallOperand;
3325 Value *CallOperandVal;
3327 /// ConstraintVT - The ValueType for the operand value.
3328 MVT::ValueType ConstraintVT;
3330 /// AssignedRegs - If this is a register or register class operand, this
3331 /// contains the set of register corresponding to the operand.
3332 RegsForValue AssignedRegs;
3334 AsmOperandInfo(const InlineAsm::ConstraintInfo &info)
3335 : InlineAsm::ConstraintInfo(info),
3336 ConstraintType(TargetLowering::C_Unknown),
3337 CallOperand(0,0), CallOperandVal(0), ConstraintVT(MVT::Other) {
3340 void ComputeConstraintToUse(const TargetLowering &TLI);
3342 /// MarkAllocatedRegs - Once AssignedRegs is set, mark the assigned registers
3343 /// busy in OutputRegs/InputRegs.
3344 void MarkAllocatedRegs(bool isOutReg, bool isInReg,
3345 std::set<unsigned> &OutputRegs,
3346 std::set<unsigned> &InputRegs) const {
3348 OutputRegs.insert(AssignedRegs.Regs.begin(), AssignedRegs.Regs.end());
3350 InputRegs.insert(AssignedRegs.Regs.begin(), AssignedRegs.Regs.end());
3353 } // end anon namespace.
3355 /// getConstraintGenerality - Return an integer indicating how general CT is.
3356 static unsigned getConstraintGenerality(TargetLowering::ConstraintType CT) {
3358 default: assert(0 && "Unknown constraint type!");
3359 case TargetLowering::C_Other:
3360 case TargetLowering::C_Unknown:
3362 case TargetLowering::C_Register:
3364 case TargetLowering::C_RegisterClass:
3366 case TargetLowering::C_Memory:
3371 void AsmOperandInfo::ComputeConstraintToUse(const TargetLowering &TLI) {
3372 assert(!Codes.empty() && "Must have at least one constraint");
3374 std::string *Current = &Codes[0];
3375 TargetLowering::ConstraintType CurType = TLI.getConstraintType(*Current);
3376 if (Codes.size() == 1) { // Single-letter constraints ('r') are very common.
3377 ConstraintCode = *Current;
3378 ConstraintType = CurType;
3380 unsigned CurGenerality = getConstraintGenerality(CurType);
3382 // If we have multiple constraints, try to pick the most general one ahead
3383 // of time. This isn't a wonderful solution, but handles common cases.
3384 for (unsigned j = 1, e = Codes.size(); j != e; ++j) {
3385 TargetLowering::ConstraintType ThisType = TLI.getConstraintType(Codes[j]);
3386 unsigned ThisGenerality = getConstraintGenerality(ThisType);
3387 if (ThisGenerality > CurGenerality) {
3388 // This constraint letter is more general than the previous one,
3391 Current = &Codes[j];
3392 CurGenerality = ThisGenerality;
3396 ConstraintCode = *Current;
3397 ConstraintType = CurType;
3400 if (ConstraintCode == "X") {
3401 if (isa<BasicBlock>(CallOperandVal) || isa<ConstantInt>(CallOperandVal))
3403 // This matches anything. Labels and constants we handle elsewhere
3404 // ('X' is the only thing that matches labels). Otherwise, try to
3405 // resolve it to something we know about by looking at the actual
3408 TLI.lowerXConstraint(ConstraintVT, s);
3411 ConstraintType = TLI.getConstraintType(ConstraintCode);
3417 void SelectionDAGLowering::
3418 GetRegistersForValue(AsmOperandInfo &OpInfo, bool HasEarlyClobber,
3419 std::set<unsigned> &OutputRegs,
3420 std::set<unsigned> &InputRegs) {
3421 // Compute whether this value requires an input register, an output register,
3423 bool isOutReg = false;
3424 bool isInReg = false;
3425 switch (OpInfo.Type) {
3426 case InlineAsm::isOutput:
3429 // If this is an early-clobber output, or if there is an input
3430 // constraint that matches this, we need to reserve the input register
3431 // so no other inputs allocate to it.
3432 isInReg = OpInfo.isEarlyClobber || OpInfo.hasMatchingInput;
3434 case InlineAsm::isInput:
3438 case InlineAsm::isClobber:
3445 MachineFunction &MF = DAG.getMachineFunction();
3446 std::vector<unsigned> Regs;
3448 // If this is a constraint for a single physreg, or a constraint for a
3449 // register class, find it.
3450 std::pair<unsigned, const TargetRegisterClass*> PhysReg =
3451 TLI.getRegForInlineAsmConstraint(OpInfo.ConstraintCode,
3452 OpInfo.ConstraintVT);
3454 unsigned NumRegs = 1;
3455 if (OpInfo.ConstraintVT != MVT::Other)
3456 NumRegs = TLI.getNumRegisters(OpInfo.ConstraintVT);
3457 MVT::ValueType RegVT;
3458 MVT::ValueType ValueVT = OpInfo.ConstraintVT;
3461 // If this is a constraint for a specific physical register, like {r17},
3463 if (PhysReg.first) {
3464 if (OpInfo.ConstraintVT == MVT::Other)
3465 ValueVT = *PhysReg.second->vt_begin();
3467 // Get the actual register value type. This is important, because the user
3468 // may have asked for (e.g.) the AX register in i32 type. We need to
3469 // remember that AX is actually i16 to get the right extension.
3470 RegVT = *PhysReg.second->vt_begin();
3472 // This is a explicit reference to a physical register.
3473 Regs.push_back(PhysReg.first);
3475 // If this is an expanded reference, add the rest of the regs to Regs.
3477 TargetRegisterClass::iterator I = PhysReg.second->begin();
3478 TargetRegisterClass::iterator E = PhysReg.second->end();
3479 for (; *I != PhysReg.first; ++I)
3480 assert(I != E && "Didn't find reg!");
3482 // Already added the first reg.
3484 for (; NumRegs; --NumRegs, ++I) {
3485 assert(I != E && "Ran out of registers to allocate!");
3489 OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT);
3490 OpInfo.MarkAllocatedRegs(isOutReg, isInReg, OutputRegs, InputRegs);
3494 // Otherwise, if this was a reference to an LLVM register class, create vregs
3495 // for this reference.
3496 std::vector<unsigned> RegClassRegs;
3497 const TargetRegisterClass *RC = PhysReg.second;
3499 // If this is an early clobber or tied register, our regalloc doesn't know
3500 // how to maintain the constraint. If it isn't, go ahead and create vreg
3501 // and let the regalloc do the right thing.
3502 if (!OpInfo.hasMatchingInput && !OpInfo.isEarlyClobber &&
3503 // If there is some other early clobber and this is an input register,
3504 // then we are forced to pre-allocate the input reg so it doesn't
3505 // conflict with the earlyclobber.
3506 !(OpInfo.Type == InlineAsm::isInput && HasEarlyClobber)) {
3507 RegVT = *PhysReg.second->vt_begin();
3509 if (OpInfo.ConstraintVT == MVT::Other)
3512 // Create the appropriate number of virtual registers.
3513 MachineRegisterInfo &RegInfo = MF.getRegInfo();
3514 for (; NumRegs; --NumRegs)
3515 Regs.push_back(RegInfo.createVirtualRegister(PhysReg.second));
3517 OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT);
3518 OpInfo.MarkAllocatedRegs(isOutReg, isInReg, OutputRegs, InputRegs);
3522 // Otherwise, we can't allocate it. Let the code below figure out how to
3523 // maintain these constraints.
3524 RegClassRegs.assign(PhysReg.second->begin(), PhysReg.second->end());
3527 // This is a reference to a register class that doesn't directly correspond
3528 // to an LLVM register class. Allocate NumRegs consecutive, available,
3529 // registers from the class.
3530 RegClassRegs = TLI.getRegClassForInlineAsmConstraint(OpInfo.ConstraintCode,
3531 OpInfo.ConstraintVT);
3534 const TargetRegisterInfo *TRI = DAG.getTarget().getRegisterInfo();
3535 unsigned NumAllocated = 0;
3536 for (unsigned i = 0, e = RegClassRegs.size(); i != e; ++i) {
3537 unsigned Reg = RegClassRegs[i];
3538 // See if this register is available.
3539 if ((isOutReg && OutputRegs.count(Reg)) || // Already used.
3540 (isInReg && InputRegs.count(Reg))) { // Already used.
3541 // Make sure we find consecutive registers.
3546 // Check to see if this register is allocatable (i.e. don't give out the
3549 RC = isAllocatableRegister(Reg, MF, TLI, TRI);
3550 if (!RC) { // Couldn't allocate this register.
3551 // Reset NumAllocated to make sure we return consecutive registers.
3557 // Okay, this register is good, we can use it.
3560 // If we allocated enough consecutive registers, succeed.
3561 if (NumAllocated == NumRegs) {
3562 unsigned RegStart = (i-NumAllocated)+1;
3563 unsigned RegEnd = i+1;
3564 // Mark all of the allocated registers used.
3565 for (unsigned i = RegStart; i != RegEnd; ++i)
3566 Regs.push_back(RegClassRegs[i]);
3568 OpInfo.AssignedRegs = RegsForValue(Regs, *RC->vt_begin(),
3569 OpInfo.ConstraintVT);
3570 OpInfo.MarkAllocatedRegs(isOutReg, isInReg, OutputRegs, InputRegs);
3575 // Otherwise, we couldn't allocate enough registers for this.
3580 /// visitInlineAsm - Handle a call to an InlineAsm object.
3582 void SelectionDAGLowering::visitInlineAsm(CallSite CS) {
3583 InlineAsm *IA = cast<InlineAsm>(CS.getCalledValue());
3585 /// ConstraintOperands - Information about all of the constraints.
3586 std::vector<AsmOperandInfo> ConstraintOperands;
3588 SDOperand Chain = getRoot();
3591 std::set<unsigned> OutputRegs, InputRegs;
3593 // Do a prepass over the constraints, canonicalizing them, and building up the
3594 // ConstraintOperands list.
3595 std::vector<InlineAsm::ConstraintInfo>
3596 ConstraintInfos = IA->ParseConstraints();
3598 // SawEarlyClobber - Keep track of whether we saw an earlyclobber output
3599 // constraint. If so, we can't let the register allocator allocate any input
3600 // registers, because it will not know to avoid the earlyclobbered output reg.
3601 bool SawEarlyClobber = false;
3603 unsigned ArgNo = 0; // ArgNo - The argument of the CallInst.
3604 for (unsigned i = 0, e = ConstraintInfos.size(); i != e; ++i) {
3605 ConstraintOperands.push_back(AsmOperandInfo(ConstraintInfos[i]));
3606 AsmOperandInfo &OpInfo = ConstraintOperands.back();
3608 MVT::ValueType OpVT = MVT::Other;
3610 // Compute the value type for each operand.
3611 switch (OpInfo.Type) {
3612 case InlineAsm::isOutput:
3613 if (!OpInfo.isIndirect) {
3614 // The return value of the call is this value. As such, there is no
3615 // corresponding argument.
3616 assert(CS.getType() != Type::VoidTy && "Bad inline asm!");
3617 OpVT = TLI.getValueType(CS.getType());
3619 OpInfo.CallOperandVal = CS.getArgument(ArgNo++);
3622 case InlineAsm::isInput:
3623 OpInfo.CallOperandVal = CS.getArgument(ArgNo++);
3625 case InlineAsm::isClobber:
3630 // If this is an input or an indirect output, process the call argument.
3631 // BasicBlocks are labels, currently appearing only in asm's.
3632 if (OpInfo.CallOperandVal) {
3633 if (isa<BasicBlock>(OpInfo.CallOperandVal))
3634 OpInfo.CallOperand =
3635 DAG.getBasicBlock(FuncInfo.MBBMap[cast<BasicBlock>(
3636 OpInfo.CallOperandVal)]);
3638 OpInfo.CallOperand = getValue(OpInfo.CallOperandVal);
3639 const Type *OpTy = OpInfo.CallOperandVal->getType();
3640 // If this is an indirect operand, the operand is a pointer to the
3642 if (OpInfo.isIndirect)
3643 OpTy = cast<PointerType>(OpTy)->getElementType();
3645 // If OpTy is not a first-class value, it may be a struct/union that we
3646 // can tile with integers.
3647 if (!OpTy->isFirstClassType() && OpTy->isSized()) {
3648 unsigned BitSize = TD->getTypeSizeInBits(OpTy);
3656 OpTy = IntegerType::get(BitSize);
3661 OpVT = TLI.getValueType(OpTy, true);
3665 OpInfo.ConstraintVT = OpVT;
3667 // Compute the constraint code and ConstraintType to use.
3668 OpInfo.ComputeConstraintToUse(TLI);
3670 // Keep track of whether we see an earlyclobber.
3671 SawEarlyClobber |= OpInfo.isEarlyClobber;
3673 // If this is a memory input, and if the operand is not indirect, do what we
3674 // need to to provide an address for the memory input.
3675 if (OpInfo.ConstraintType == TargetLowering::C_Memory &&
3676 !OpInfo.isIndirect) {
3677 assert(OpInfo.Type == InlineAsm::isInput &&
3678 "Can only indirectify direct input operands!");
3680 // Memory operands really want the address of the value. If we don't have
3681 // an indirect input, put it in the constpool if we can, otherwise spill
3682 // it to a stack slot.
3684 // If the operand is a float, integer, or vector constant, spill to a
3685 // constant pool entry to get its address.
3686 Value *OpVal = OpInfo.CallOperandVal;
3687 if (isa<ConstantFP>(OpVal) || isa<ConstantInt>(OpVal) ||
3688 isa<ConstantVector>(OpVal)) {
3689 OpInfo.CallOperand = DAG.getConstantPool(cast<Constant>(OpVal),
3690 TLI.getPointerTy());
3692 // Otherwise, create a stack slot and emit a store to it before the
3694 const Type *Ty = OpVal->getType();
3695 uint64_t TySize = TLI.getTargetData()->getABITypeSize(Ty);
3696 unsigned Align = TLI.getTargetData()->getPrefTypeAlignment(Ty);
3697 MachineFunction &MF = DAG.getMachineFunction();
3698 int SSFI = MF.getFrameInfo()->CreateStackObject(TySize, Align);
3699 SDOperand StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy());
3700 Chain = DAG.getStore(Chain, OpInfo.CallOperand, StackSlot, NULL, 0);
3701 OpInfo.CallOperand = StackSlot;
3704 // There is no longer a Value* corresponding to this operand.
3705 OpInfo.CallOperandVal = 0;
3706 // It is now an indirect operand.
3707 OpInfo.isIndirect = true;
3710 // If this constraint is for a specific register, allocate it before
3712 if (OpInfo.ConstraintType == TargetLowering::C_Register)
3713 GetRegistersForValue(OpInfo, SawEarlyClobber, OutputRegs, InputRegs);
3715 ConstraintInfos.clear();
3718 // Second pass - Loop over all of the operands, assigning virtual or physregs
3719 // to registerclass operands.
3720 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
3721 AsmOperandInfo &OpInfo = ConstraintOperands[i];
3723 // C_Register operands have already been allocated, Other/Memory don't need
3725 if (OpInfo.ConstraintType == TargetLowering::C_RegisterClass)
3726 GetRegistersForValue(OpInfo, SawEarlyClobber, OutputRegs, InputRegs);
3729 // AsmNodeOperands - The operands for the ISD::INLINEASM node.
3730 std::vector<SDOperand> AsmNodeOperands;
3731 AsmNodeOperands.push_back(SDOperand()); // reserve space for input chain
3732 AsmNodeOperands.push_back(
3733 DAG.getTargetExternalSymbol(IA->getAsmString().c_str(), MVT::Other));
3736 // Loop over all of the inputs, copying the operand values into the
3737 // appropriate registers and processing the output regs.
3738 RegsForValue RetValRegs;
3740 // IndirectStoresToEmit - The set of stores to emit after the inline asm node.
3741 std::vector<std::pair<RegsForValue, Value*> > IndirectStoresToEmit;
3743 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
3744 AsmOperandInfo &OpInfo = ConstraintOperands[i];
3746 switch (OpInfo.Type) {
3747 case InlineAsm::isOutput: {
3748 if (OpInfo.ConstraintType != TargetLowering::C_RegisterClass &&
3749 OpInfo.ConstraintType != TargetLowering::C_Register) {
3750 // Memory output, or 'other' output (e.g. 'X' constraint).
3751 assert(OpInfo.isIndirect && "Memory output must be indirect operand");
3753 // Add information to the INLINEASM node to know about this output.
3754 unsigned ResOpType = 4/*MEM*/ | (1 << 3);
3755 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
3756 TLI.getPointerTy()));
3757 AsmNodeOperands.push_back(OpInfo.CallOperand);
3761 // Otherwise, this is a register or register class output.
3763 // Copy the output from the appropriate register. Find a register that
3765 if (OpInfo.AssignedRegs.Regs.empty()) {
3766 cerr << "Couldn't allocate output reg for contraint '"
3767 << OpInfo.ConstraintCode << "'!\n";
3771 if (!OpInfo.isIndirect) {
3772 // This is the result value of the call.
3773 assert(RetValRegs.Regs.empty() &&
3774 "Cannot have multiple output constraints yet!");
3775 assert(CS.getType() != Type::VoidTy && "Bad inline asm!");
3776 RetValRegs = OpInfo.AssignedRegs;
3778 IndirectStoresToEmit.push_back(std::make_pair(OpInfo.AssignedRegs,
3779 OpInfo.CallOperandVal));
3782 // Add information to the INLINEASM node to know that this register is
3784 OpInfo.AssignedRegs.AddInlineAsmOperands(2 /*REGDEF*/, DAG,
3788 case InlineAsm::isInput: {
3789 SDOperand InOperandVal = OpInfo.CallOperand;
3791 if (isdigit(OpInfo.ConstraintCode[0])) { // Matching constraint?
3792 // If this is required to match an output register we have already set,
3793 // just use its register.
3794 unsigned OperandNo = atoi(OpInfo.ConstraintCode.c_str());
3796 // Scan until we find the definition we already emitted of this operand.
3797 // When we find it, create a RegsForValue operand.
3798 unsigned CurOp = 2; // The first operand.
3799 for (; OperandNo; --OperandNo) {
3800 // Advance to the next operand.
3802 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getValue();
3803 assert(((NumOps & 7) == 2 /*REGDEF*/ ||
3804 (NumOps & 7) == 4 /*MEM*/) &&
3805 "Skipped past definitions?");
3806 CurOp += (NumOps>>3)+1;
3810 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getValue();
3811 if ((NumOps & 7) == 2 /*REGDEF*/) {
3812 // Add NumOps>>3 registers to MatchedRegs.
3813 RegsForValue MatchedRegs;
3814 MatchedRegs.ValueVT = InOperandVal.getValueType();
3815 MatchedRegs.RegVT = AsmNodeOperands[CurOp+1].getValueType();
3816 for (unsigned i = 0, e = NumOps>>3; i != e; ++i) {
3818 cast<RegisterSDNode>(AsmNodeOperands[++CurOp])->getReg();
3819 MatchedRegs.Regs.push_back(Reg);
3822 // Use the produced MatchedRegs object to
3823 MatchedRegs.getCopyToRegs(InOperandVal, DAG, Chain, &Flag);
3824 MatchedRegs.AddInlineAsmOperands(1 /*REGUSE*/, DAG, AsmNodeOperands);
3827 assert((NumOps & 7) == 4/*MEM*/ && "Unknown matching constraint!");
3828 assert(0 && "matching constraints for memory operands unimp");
3832 if (OpInfo.ConstraintType == TargetLowering::C_Other) {
3833 assert(!OpInfo.isIndirect &&
3834 "Don't know how to handle indirect other inputs yet!");
3836 std::vector<SDOperand> Ops;
3837 TLI.LowerAsmOperandForConstraint(InOperandVal, OpInfo.ConstraintCode[0],
3840 cerr << "Invalid operand for inline asm constraint '"
3841 << OpInfo.ConstraintCode << "'!\n";
3845 // Add information to the INLINEASM node to know about this input.
3846 unsigned ResOpType = 3 /*IMM*/ | (Ops.size() << 3);
3847 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
3848 TLI.getPointerTy()));
3849 AsmNodeOperands.insert(AsmNodeOperands.end(), Ops.begin(), Ops.end());
3851 } else if (OpInfo.ConstraintType == TargetLowering::C_Memory) {
3852 assert(OpInfo.isIndirect && "Operand must be indirect to be a mem!");
3853 assert(InOperandVal.getValueType() == TLI.getPointerTy() &&
3854 "Memory operands expect pointer values");
3856 // Add information to the INLINEASM node to know about this input.
3857 unsigned ResOpType = 4/*MEM*/ | (1 << 3);
3858 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
3859 TLI.getPointerTy()));
3860 AsmNodeOperands.push_back(InOperandVal);
3864 assert((OpInfo.ConstraintType == TargetLowering::C_RegisterClass ||
3865 OpInfo.ConstraintType == TargetLowering::C_Register) &&
3866 "Unknown constraint type!");
3867 assert(!OpInfo.isIndirect &&
3868 "Don't know how to handle indirect register inputs yet!");
3870 // Copy the input into the appropriate registers.
3871 assert(!OpInfo.AssignedRegs.Regs.empty() &&
3872 "Couldn't allocate input reg!");
3874 OpInfo.AssignedRegs.getCopyToRegs(InOperandVal, DAG, Chain, &Flag);
3876 OpInfo.AssignedRegs.AddInlineAsmOperands(1/*REGUSE*/, DAG,
3880 case InlineAsm::isClobber: {
3881 // Add the clobbered value to the operand list, so that the register
3882 // allocator is aware that the physreg got clobbered.
3883 if (!OpInfo.AssignedRegs.Regs.empty())
3884 OpInfo.AssignedRegs.AddInlineAsmOperands(2/*REGDEF*/, DAG,
3891 // Finish up input operands.
3892 AsmNodeOperands[0] = Chain;
3893 if (Flag.Val) AsmNodeOperands.push_back(Flag);
3895 Chain = DAG.getNode(ISD::INLINEASM,
3896 DAG.getNodeValueTypes(MVT::Other, MVT::Flag), 2,
3897 &AsmNodeOperands[0], AsmNodeOperands.size());
3898 Flag = Chain.getValue(1);
3900 // If this asm returns a register value, copy the result from that register
3901 // and set it as the value of the call.
3902 if (!RetValRegs.Regs.empty()) {
3903 SDOperand Val = RetValRegs.getCopyFromRegs(DAG, Chain, &Flag);
3905 // If the result of the inline asm is a vector, it may have the wrong
3906 // width/num elts. Make sure to convert it to the right type with
3908 if (MVT::isVector(Val.getValueType())) {
3909 const VectorType *VTy = cast<VectorType>(CS.getType());
3910 MVT::ValueType DesiredVT = TLI.getValueType(VTy);
3912 Val = DAG.getNode(ISD::BIT_CONVERT, DesiredVT, Val);
3915 setValue(CS.getInstruction(), Val);
3918 std::vector<std::pair<SDOperand, Value*> > StoresToEmit;
3920 // Process indirect outputs, first output all of the flagged copies out of
3922 for (unsigned i = 0, e = IndirectStoresToEmit.size(); i != e; ++i) {
3923 RegsForValue &OutRegs = IndirectStoresToEmit[i].first;
3924 Value *Ptr = IndirectStoresToEmit[i].second;
3925 SDOperand OutVal = OutRegs.getCopyFromRegs(DAG, Chain, &Flag);
3926 StoresToEmit.push_back(std::make_pair(OutVal, Ptr));
3929 // Emit the non-flagged stores from the physregs.
3930 SmallVector<SDOperand, 8> OutChains;
3931 for (unsigned i = 0, e = StoresToEmit.size(); i != e; ++i)
3932 OutChains.push_back(DAG.getStore(Chain, StoresToEmit[i].first,
3933 getValue(StoresToEmit[i].second),
3934 StoresToEmit[i].second, 0));
3935 if (!OutChains.empty())
3936 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other,
3937 &OutChains[0], OutChains.size());
3942 void SelectionDAGLowering::visitMalloc(MallocInst &I) {
3943 SDOperand Src = getValue(I.getOperand(0));
3945 MVT::ValueType IntPtr = TLI.getPointerTy();
3947 if (IntPtr < Src.getValueType())
3948 Src = DAG.getNode(ISD::TRUNCATE, IntPtr, Src);
3949 else if (IntPtr > Src.getValueType())
3950 Src = DAG.getNode(ISD::ZERO_EXTEND, IntPtr, Src);
3952 // Scale the source by the type size.
3953 uint64_t ElementSize = TD->getABITypeSize(I.getType()->getElementType());
3954 Src = DAG.getNode(ISD::MUL, Src.getValueType(),
3955 Src, DAG.getIntPtrConstant(ElementSize));
3957 TargetLowering::ArgListTy Args;
3958 TargetLowering::ArgListEntry Entry;
3960 Entry.Ty = TLI.getTargetData()->getIntPtrType();
3961 Args.push_back(Entry);
3963 std::pair<SDOperand,SDOperand> Result =
3964 TLI.LowerCallTo(getRoot(), I.getType(), false, false, false, CallingConv::C,
3965 true, DAG.getExternalSymbol("malloc", IntPtr), Args, DAG);
3966 setValue(&I, Result.first); // Pointers always fit in registers
3967 DAG.setRoot(Result.second);
3970 void SelectionDAGLowering::visitFree(FreeInst &I) {
3971 TargetLowering::ArgListTy Args;
3972 TargetLowering::ArgListEntry Entry;
3973 Entry.Node = getValue(I.getOperand(0));
3974 Entry.Ty = TLI.getTargetData()->getIntPtrType();
3975 Args.push_back(Entry);
3976 MVT::ValueType IntPtr = TLI.getPointerTy();
3977 std::pair<SDOperand,SDOperand> Result =
3978 TLI.LowerCallTo(getRoot(), Type::VoidTy, false, false, false,
3979 CallingConv::C, true,
3980 DAG.getExternalSymbol("free", IntPtr), Args, DAG);
3981 DAG.setRoot(Result.second);
3984 // EmitInstrWithCustomInserter - This method should be implemented by targets
3985 // that mark instructions with the 'usesCustomDAGSchedInserter' flag. These
3986 // instructions are special in various ways, which require special support to
3987 // insert. The specified MachineInstr is created but not inserted into any
3988 // basic blocks, and the scheduler passes ownership of it to this method.
3989 MachineBasicBlock *TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
3990 MachineBasicBlock *MBB) {
3991 cerr << "If a target marks an instruction with "
3992 << "'usesCustomDAGSchedInserter', it must implement "
3993 << "TargetLowering::EmitInstrWithCustomInserter!\n";
3998 void SelectionDAGLowering::visitVAStart(CallInst &I) {
3999 DAG.setRoot(DAG.getNode(ISD::VASTART, MVT::Other, getRoot(),
4000 getValue(I.getOperand(1)),
4001 DAG.getSrcValue(I.getOperand(1))));
4004 void SelectionDAGLowering::visitVAArg(VAArgInst &I) {
4005 SDOperand V = DAG.getVAArg(TLI.getValueType(I.getType()), getRoot(),
4006 getValue(I.getOperand(0)),
4007 DAG.getSrcValue(I.getOperand(0)));
4009 DAG.setRoot(V.getValue(1));
4012 void SelectionDAGLowering::visitVAEnd(CallInst &I) {
4013 DAG.setRoot(DAG.getNode(ISD::VAEND, MVT::Other, getRoot(),
4014 getValue(I.getOperand(1)),
4015 DAG.getSrcValue(I.getOperand(1))));
4018 void SelectionDAGLowering::visitVACopy(CallInst &I) {
4019 DAG.setRoot(DAG.getNode(ISD::VACOPY, MVT::Other, getRoot(),
4020 getValue(I.getOperand(1)),
4021 getValue(I.getOperand(2)),
4022 DAG.getSrcValue(I.getOperand(1)),
4023 DAG.getSrcValue(I.getOperand(2))));
4026 /// TargetLowering::LowerArguments - This is the default LowerArguments
4027 /// implementation, which just inserts a FORMAL_ARGUMENTS node. FIXME: When all
4028 /// targets are migrated to using FORMAL_ARGUMENTS, this hook should be
4029 /// integrated into SDISel.
4030 std::vector<SDOperand>
4031 TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
4032 // Add CC# and isVararg as operands to the FORMAL_ARGUMENTS node.
4033 std::vector<SDOperand> Ops;
4034 Ops.push_back(DAG.getRoot());
4035 Ops.push_back(DAG.getConstant(F.getCallingConv(), getPointerTy()));
4036 Ops.push_back(DAG.getConstant(F.isVarArg(), getPointerTy()));
4038 // Add one result value for each formal argument.
4039 std::vector<MVT::ValueType> RetVals;
4041 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end();
4043 MVT::ValueType VT = getValueType(I->getType());
4044 unsigned Flags = ISD::ParamFlags::NoFlagSet;
4045 unsigned OriginalAlignment =
4046 getTargetData()->getABITypeAlignment(I->getType());
4048 // FIXME: Distinguish between a formal with no [sz]ext attribute from one
4049 // that is zero extended!
4050 if (F.paramHasAttr(j, ParamAttr::ZExt))
4051 Flags &= ~(ISD::ParamFlags::SExt);
4052 if (F.paramHasAttr(j, ParamAttr::SExt))
4053 Flags |= ISD::ParamFlags::SExt;
4054 if (F.paramHasAttr(j, ParamAttr::InReg))
4055 Flags |= ISD::ParamFlags::InReg;
4056 if (F.paramHasAttr(j, ParamAttr::StructRet))
4057 Flags |= ISD::ParamFlags::StructReturn;
4058 if (F.paramHasAttr(j, ParamAttr::ByVal)) {
4059 Flags |= ISD::ParamFlags::ByVal;
4060 const PointerType *Ty = cast<PointerType>(I->getType());
4061 const Type *ElementTy = Ty->getElementType();
4062 unsigned FrameAlign = Log2_32(getByValTypeAlignment(ElementTy));
4063 unsigned FrameSize = getTargetData()->getABITypeSize(ElementTy);
4064 Flags |= (FrameAlign << ISD::ParamFlags::ByValAlignOffs);
4065 Flags |= (FrameSize << ISD::ParamFlags::ByValSizeOffs);
4067 if (F.paramHasAttr(j, ParamAttr::Nest))
4068 Flags |= ISD::ParamFlags::Nest;
4069 Flags |= (OriginalAlignment << ISD::ParamFlags::OrigAlignmentOffs);
4071 MVT::ValueType RegisterVT = getRegisterType(VT);
4072 unsigned NumRegs = getNumRegisters(VT);
4073 for (unsigned i = 0; i != NumRegs; ++i) {
4074 RetVals.push_back(RegisterVT);
4075 // if it isn't first piece, alignment must be 1
4077 Flags = (Flags & (~ISD::ParamFlags::OrigAlignment)) |
4078 (1 << ISD::ParamFlags::OrigAlignmentOffs);
4079 Ops.push_back(DAG.getConstant(Flags, MVT::i32));
4083 RetVals.push_back(MVT::Other);
4086 SDNode *Result = DAG.getNode(ISD::FORMAL_ARGUMENTS,
4087 DAG.getVTList(&RetVals[0], RetVals.size()),
4088 &Ops[0], Ops.size()).Val;
4090 // Prelower FORMAL_ARGUMENTS. This isn't required for functionality, but
4091 // allows exposing the loads that may be part of the argument access to the
4092 // first DAGCombiner pass.
4093 SDOperand TmpRes = LowerOperation(SDOperand(Result, 0), DAG);
4095 // The number of results should match up, except that the lowered one may have
4096 // an extra flag result.
4097 assert((Result->getNumValues() == TmpRes.Val->getNumValues() ||
4098 (Result->getNumValues()+1 == TmpRes.Val->getNumValues() &&
4099 TmpRes.getValue(Result->getNumValues()).getValueType() == MVT::Flag))
4100 && "Lowering produced unexpected number of results!");
4101 Result = TmpRes.Val;
4103 unsigned NumArgRegs = Result->getNumValues() - 1;
4104 DAG.setRoot(SDOperand(Result, NumArgRegs));
4106 // Set up the return result vector.
4110 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E;
4112 MVT::ValueType VT = getValueType(I->getType());
4113 MVT::ValueType PartVT = getRegisterType(VT);
4115 unsigned NumParts = getNumRegisters(VT);
4116 SmallVector<SDOperand, 4> Parts(NumParts);
4117 for (unsigned j = 0; j != NumParts; ++j)
4118 Parts[j] = SDOperand(Result, i++);
4120 ISD::NodeType AssertOp = ISD::DELETED_NODE;
4121 if (F.paramHasAttr(Idx, ParamAttr::SExt))
4122 AssertOp = ISD::AssertSext;
4123 else if (F.paramHasAttr(Idx, ParamAttr::ZExt))
4124 AssertOp = ISD::AssertZext;
4126 Ops.push_back(getCopyFromParts(DAG, &Parts[0], NumParts, PartVT, VT,
4129 assert(i == NumArgRegs && "Argument register count mismatch!");
4134 /// TargetLowering::LowerCallTo - This is the default LowerCallTo
4135 /// implementation, which just inserts an ISD::CALL node, which is later custom
4136 /// lowered by the target to something concrete. FIXME: When all targets are
4137 /// migrated to using ISD::CALL, this hook should be integrated into SDISel.
4138 std::pair<SDOperand, SDOperand>
4139 TargetLowering::LowerCallTo(SDOperand Chain, const Type *RetTy,
4140 bool RetSExt, bool RetZExt, bool isVarArg,
4141 unsigned CallingConv, bool isTailCall,
4143 ArgListTy &Args, SelectionDAG &DAG) {
4144 SmallVector<SDOperand, 32> Ops;
4145 Ops.push_back(Chain); // Op#0 - Chain
4146 Ops.push_back(DAG.getConstant(CallingConv, getPointerTy())); // Op#1 - CC
4147 Ops.push_back(DAG.getConstant(isVarArg, getPointerTy())); // Op#2 - VarArg
4148 Ops.push_back(DAG.getConstant(isTailCall, getPointerTy())); // Op#3 - Tail
4149 Ops.push_back(Callee);
4151 // Handle all of the outgoing arguments.
4152 for (unsigned i = 0, e = Args.size(); i != e; ++i) {
4153 MVT::ValueType VT = getValueType(Args[i].Ty);
4154 SDOperand Op = Args[i].Node;
4155 unsigned Flags = ISD::ParamFlags::NoFlagSet;
4156 unsigned OriginalAlignment =
4157 getTargetData()->getABITypeAlignment(Args[i].Ty);
4160 Flags |= ISD::ParamFlags::SExt;
4162 Flags |= ISD::ParamFlags::ZExt;
4163 if (Args[i].isInReg)
4164 Flags |= ISD::ParamFlags::InReg;
4166 Flags |= ISD::ParamFlags::StructReturn;
4167 if (Args[i].isByVal) {
4168 Flags |= ISD::ParamFlags::ByVal;
4169 const PointerType *Ty = cast<PointerType>(Args[i].Ty);
4170 const Type *ElementTy = Ty->getElementType();
4171 unsigned FrameAlign = Log2_32(getByValTypeAlignment(ElementTy));
4172 unsigned FrameSize = getTargetData()->getABITypeSize(ElementTy);
4173 Flags |= (FrameAlign << ISD::ParamFlags::ByValAlignOffs);
4174 Flags |= (FrameSize << ISD::ParamFlags::ByValSizeOffs);
4177 Flags |= ISD::ParamFlags::Nest;
4178 Flags |= OriginalAlignment << ISD::ParamFlags::OrigAlignmentOffs;
4180 MVT::ValueType PartVT = getRegisterType(VT);
4181 unsigned NumParts = getNumRegisters(VT);
4182 SmallVector<SDOperand, 4> Parts(NumParts);
4183 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
4186 ExtendKind = ISD::SIGN_EXTEND;
4187 else if (Args[i].isZExt)
4188 ExtendKind = ISD::ZERO_EXTEND;
4190 getCopyToParts(DAG, Op, &Parts[0], NumParts, PartVT, ExtendKind);
4192 for (unsigned i = 0; i != NumParts; ++i) {
4193 // if it isn't first piece, alignment must be 1
4194 unsigned MyFlags = Flags;
4196 MyFlags = (MyFlags & (~ISD::ParamFlags::OrigAlignment)) |
4197 (1 << ISD::ParamFlags::OrigAlignmentOffs);
4199 Ops.push_back(Parts[i]);
4200 Ops.push_back(DAG.getConstant(MyFlags, MVT::i32));
4204 // Figure out the result value types.
4205 MVT::ValueType VT = getValueType(RetTy);
4206 MVT::ValueType RegisterVT = getRegisterType(VT);
4207 unsigned NumRegs = getNumRegisters(VT);
4208 SmallVector<MVT::ValueType, 4> RetTys(NumRegs);
4209 for (unsigned i = 0; i != NumRegs; ++i)
4210 RetTys[i] = RegisterVT;
4212 RetTys.push_back(MVT::Other); // Always has a chain.
4214 // Create the CALL node.
4215 SDOperand Res = DAG.getNode(ISD::CALL,
4216 DAG.getVTList(&RetTys[0], NumRegs + 1),
4217 &Ops[0], Ops.size());
4218 Chain = Res.getValue(NumRegs);
4220 // Gather up the call result into a single value.
4221 if (RetTy != Type::VoidTy) {
4222 ISD::NodeType AssertOp = ISD::DELETED_NODE;
4225 AssertOp = ISD::AssertSext;
4227 AssertOp = ISD::AssertZext;
4229 SmallVector<SDOperand, 4> Results(NumRegs);
4230 for (unsigned i = 0; i != NumRegs; ++i)
4231 Results[i] = Res.getValue(i);
4232 Res = getCopyFromParts(DAG, &Results[0], NumRegs, RegisterVT, VT,
4236 return std::make_pair(Res, Chain);
4239 SDOperand TargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
4240 assert(0 && "LowerOperation not implemented for this target!");
4245 SDOperand TargetLowering::CustomPromoteOperation(SDOperand Op,
4246 SelectionDAG &DAG) {
4247 assert(0 && "CustomPromoteOperation not implemented for this target!");
4252 /// getMemsetValue - Vectorized representation of the memset value
4254 static SDOperand getMemsetValue(SDOperand Value, MVT::ValueType VT,
4255 SelectionDAG &DAG) {
4256 MVT::ValueType CurVT = VT;
4257 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Value)) {
4258 uint64_t Val = C->getValue() & 255;
4260 while (CurVT != MVT::i8) {
4261 Val = (Val << Shift) | Val;
4263 CurVT = (MVT::ValueType)((unsigned)CurVT - 1);
4265 return DAG.getConstant(Val, VT);
4267 Value = DAG.getNode(ISD::ZERO_EXTEND, VT, Value);
4269 while (CurVT != MVT::i8) {
4271 DAG.getNode(ISD::OR, VT,
4272 DAG.getNode(ISD::SHL, VT, Value,
4273 DAG.getConstant(Shift, MVT::i8)), Value);
4275 CurVT = (MVT::ValueType)((unsigned)CurVT - 1);
4282 /// getMemsetStringVal - Similar to getMemsetValue. Except this is only
4283 /// used when a memcpy is turned into a memset when the source is a constant
4285 static SDOperand getMemsetStringVal(MVT::ValueType VT,
4286 SelectionDAG &DAG, TargetLowering &TLI,
4287 std::string &Str, unsigned Offset) {
4289 unsigned MSB = MVT::getSizeInBits(VT) / 8;
4290 if (TLI.isLittleEndian())
4291 Offset = Offset + MSB - 1;
4292 for (unsigned i = 0; i != MSB; ++i) {
4293 Val = (Val << 8) | (unsigned char)Str[Offset];
4294 Offset += TLI.isLittleEndian() ? -1 : 1;
4296 return DAG.getConstant(Val, VT);
4299 /// getMemBasePlusOffset - Returns base and offset node for the
4300 static SDOperand getMemBasePlusOffset(SDOperand Base, unsigned Offset,
4301 SelectionDAG &DAG, TargetLowering &TLI) {
4302 MVT::ValueType VT = Base.getValueType();
4303 return DAG.getNode(ISD::ADD, VT, Base, DAG.getConstant(Offset, VT));
4306 /// MeetsMaxMemopRequirement - Determines if the number of memory ops required
4307 /// to replace the memset / memcpy is below the threshold. It also returns the
4308 /// types of the sequence of memory ops to perform memset / memcpy.
4309 static bool MeetsMaxMemopRequirement(std::vector<MVT::ValueType> &MemOps,
4310 unsigned Limit, uint64_t Size,
4311 unsigned Align, TargetLowering &TLI) {
4314 if (TLI.allowsUnalignedMemoryAccesses()) {
4317 switch (Align & 7) {
4333 MVT::ValueType LVT = MVT::i64;
4334 while (!TLI.isTypeLegal(LVT))
4335 LVT = (MVT::ValueType)((unsigned)LVT - 1);
4336 assert(MVT::isInteger(LVT));
4341 unsigned NumMemOps = 0;
4343 unsigned VTSize = MVT::getSizeInBits(VT) / 8;
4344 while (VTSize > Size) {
4345 VT = (MVT::ValueType)((unsigned)VT - 1);
4348 assert(MVT::isInteger(VT));
4350 if (++NumMemOps > Limit)
4352 MemOps.push_back(VT);
4359 void SelectionDAGLowering::visitMemIntrinsic(CallInst &I, unsigned Op) {
4360 SDOperand Op1 = getValue(I.getOperand(1));
4361 SDOperand Op2 = getValue(I.getOperand(2));
4362 SDOperand Op3 = getValue(I.getOperand(3));
4363 SDOperand Op4 = getValue(I.getOperand(4));
4364 unsigned Align = (unsigned)cast<ConstantSDNode>(Op4)->getValue();
4365 if (Align == 0) Align = 1;
4367 // If the source and destination are known to not be aliases, we can
4368 // lower memmove as memcpy.
4369 if (Op == ISD::MEMMOVE) {
4370 uint64_t Size = -1ULL;
4371 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op3))
4372 Size = C->getValue();
4373 if (AA.alias(I.getOperand(1), Size, I.getOperand(2), Size) ==
4374 AliasAnalysis::NoAlias)
4378 if (ConstantSDNode *Size = dyn_cast<ConstantSDNode>(Op3)) {
4379 std::vector<MVT::ValueType> MemOps;
4381 // Expand memset / memcpy to a series of load / store ops
4382 // if the size operand falls below a certain threshold.
4383 SmallVector<SDOperand, 8> OutChains;
4385 default: break; // Do nothing for now.
4387 if (MeetsMaxMemopRequirement(MemOps, TLI.getMaxStoresPerMemset(),
4388 Size->getValue(), Align, TLI)) {
4389 unsigned NumMemOps = MemOps.size();
4390 unsigned Offset = 0;
4391 for (unsigned i = 0; i < NumMemOps; i++) {
4392 MVT::ValueType VT = MemOps[i];
4393 unsigned VTSize = MVT::getSizeInBits(VT) / 8;
4394 SDOperand Value = getMemsetValue(Op2, VT, DAG);
4395 SDOperand Store = DAG.getStore(getRoot(), Value,
4396 getMemBasePlusOffset(Op1, Offset, DAG, TLI),
4397 I.getOperand(1), Offset);
4398 OutChains.push_back(Store);
4405 if (MeetsMaxMemopRequirement(MemOps, TLI.getMaxStoresPerMemcpy(),
4406 Size->getValue(), Align, TLI)) {
4407 unsigned NumMemOps = MemOps.size();
4408 unsigned SrcOff = 0, DstOff = 0, SrcDelta = 0;
4409 GlobalAddressSDNode *G = NULL;
4411 bool CopyFromStr = false;
4413 if (Op2.getOpcode() == ISD::GlobalAddress)
4414 G = cast<GlobalAddressSDNode>(Op2);
4415 else if (Op2.getOpcode() == ISD::ADD &&
4416 Op2.getOperand(0).getOpcode() == ISD::GlobalAddress &&
4417 Op2.getOperand(1).getOpcode() == ISD::Constant) {
4418 G = cast<GlobalAddressSDNode>(Op2.getOperand(0));
4419 SrcDelta = cast<ConstantSDNode>(Op2.getOperand(1))->getValue();
4422 GlobalVariable *GV = dyn_cast<GlobalVariable>(G->getGlobal());
4423 if (GV && GV->isConstant()) {
4424 Str = GV->getStringValue(false);
4432 for (unsigned i = 0; i < NumMemOps; i++) {
4433 MVT::ValueType VT = MemOps[i];
4434 unsigned VTSize = MVT::getSizeInBits(VT) / 8;
4435 SDOperand Value, Chain, Store;
4438 Value = getMemsetStringVal(VT, DAG, TLI, Str, SrcOff);
4441 DAG.getStore(Chain, Value,
4442 getMemBasePlusOffset(Op1, DstOff, DAG, TLI),
4443 I.getOperand(1), DstOff);
4445 Value = DAG.getLoad(VT, getRoot(),
4446 getMemBasePlusOffset(Op2, SrcOff, DAG, TLI),
4447 I.getOperand(2), SrcOff, false, Align);
4448 Chain = Value.getValue(1);
4450 DAG.getStore(Chain, Value,
4451 getMemBasePlusOffset(Op1, DstOff, DAG, TLI),
4452 I.getOperand(1), DstOff, false, Align);
4454 OutChains.push_back(Store);
4463 if (!OutChains.empty()) {
4464 DAG.setRoot(DAG.getNode(ISD::TokenFactor, MVT::Other,
4465 &OutChains[0], OutChains.size()));
4470 SDOperand AlwaysInline = DAG.getConstant(0, MVT::i1);
4474 assert(0 && "Unknown Op");
4476 Node = DAG.getMemcpy(getRoot(), Op1, Op2, Op3, Op4, AlwaysInline);
4479 Node = DAG.getMemmove(getRoot(), Op1, Op2, Op3, Op4, AlwaysInline);
4482 Node = DAG.getMemset(getRoot(), Op1, Op2, Op3, Op4, AlwaysInline);
4488 //===----------------------------------------------------------------------===//
4489 // SelectionDAGISel code
4490 //===----------------------------------------------------------------------===//
4492 unsigned SelectionDAGISel::MakeReg(MVT::ValueType VT) {
4493 return RegInfo->createVirtualRegister(TLI.getRegClassFor(VT));
4496 void SelectionDAGISel::getAnalysisUsage(AnalysisUsage &AU) const {
4497 AU.addRequired<AliasAnalysis>();
4498 AU.addRequired<CollectorModuleMetadata>();
4499 AU.setPreservesAll();
4504 bool SelectionDAGISel::runOnFunction(Function &Fn) {
4505 // Get alias analysis for load/store combining.
4506 AA = &getAnalysis<AliasAnalysis>();
4508 MachineFunction &MF = MachineFunction::construct(&Fn, TLI.getTargetMachine());
4509 if (MF.getFunction()->hasCollector())
4510 GCI = &getAnalysis<CollectorModuleMetadata>().get(*MF.getFunction());
4513 RegInfo = &MF.getRegInfo();
4514 DOUT << "\n\n\n=== " << Fn.getName() << "\n";
4516 FunctionLoweringInfo FuncInfo(TLI, Fn, MF);
4518 if (ExceptionHandling)
4519 for (Function::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I)
4520 if (InvokeInst *Invoke = dyn_cast<InvokeInst>(I->getTerminator()))
4521 // Mark landing pad.
4522 FuncInfo.MBBMap[Invoke->getSuccessor(1)]->setIsLandingPad();
4524 for (Function::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I)
4525 SelectBasicBlock(I, MF, FuncInfo);
4527 // Add function live-ins to entry block live-in set.
4528 BasicBlock *EntryBB = &Fn.getEntryBlock();
4529 BB = FuncInfo.MBBMap[EntryBB];
4530 if (!RegInfo->livein_empty())
4531 for (MachineRegisterInfo::livein_iterator I = RegInfo->livein_begin(),
4532 E = RegInfo->livein_end(); I != E; ++I)
4533 BB->addLiveIn(I->first);
4536 assert(FuncInfo.CatchInfoFound.size() == FuncInfo.CatchInfoLost.size() &&
4537 "Not all catch info was assigned to a landing pad!");
4543 SDOperand SelectionDAGLowering::CopyValueToVirtualRegister(Value *V,
4545 SDOperand Op = getValue(V);
4546 assert((Op.getOpcode() != ISD::CopyFromReg ||
4547 cast<RegisterSDNode>(Op.getOperand(1))->getReg() != Reg) &&
4548 "Copy from a reg to the same reg!");
4550 MVT::ValueType SrcVT = Op.getValueType();
4551 MVT::ValueType RegisterVT = TLI.getRegisterType(SrcVT);
4552 unsigned NumRegs = TLI.getNumRegisters(SrcVT);
4553 SmallVector<SDOperand, 8> Regs(NumRegs);
4554 SmallVector<SDOperand, 8> Chains(NumRegs);
4556 // Copy the value by legal parts into sequential virtual registers.
4557 getCopyToParts(DAG, Op, &Regs[0], NumRegs, RegisterVT);
4558 for (unsigned i = 0; i != NumRegs; ++i)
4559 Chains[i] = DAG.getCopyToReg(getRoot(), Reg + i, Regs[i]);
4560 return DAG.getNode(ISD::TokenFactor, MVT::Other, &Chains[0], NumRegs);
4563 void SelectionDAGISel::
4564 LowerArguments(BasicBlock *LLVMBB, SelectionDAGLowering &SDL,
4565 std::vector<SDOperand> &UnorderedChains) {
4566 // If this is the entry block, emit arguments.
4567 Function &F = *LLVMBB->getParent();
4568 FunctionLoweringInfo &FuncInfo = SDL.FuncInfo;
4569 SDOperand OldRoot = SDL.DAG.getRoot();
4570 std::vector<SDOperand> Args = TLI.LowerArguments(F, SDL.DAG);
4573 for (Function::arg_iterator AI = F.arg_begin(), E = F.arg_end();
4575 if (!AI->use_empty()) {
4576 SDL.setValue(AI, Args[a]);
4578 // If this argument is live outside of the entry block, insert a copy from
4579 // whereever we got it to the vreg that other BB's will reference it as.
4580 DenseMap<const Value*, unsigned>::iterator VMI=FuncInfo.ValueMap.find(AI);
4581 if (VMI != FuncInfo.ValueMap.end()) {
4582 SDOperand Copy = SDL.CopyValueToVirtualRegister(AI, VMI->second);
4583 UnorderedChains.push_back(Copy);
4587 // Finally, if the target has anything special to do, allow it to do so.
4588 // FIXME: this should insert code into the DAG!
4589 EmitFunctionEntryCode(F, SDL.DAG.getMachineFunction());
4592 static void copyCatchInfo(BasicBlock *SrcBB, BasicBlock *DestBB,
4593 MachineModuleInfo *MMI, FunctionLoweringInfo &FLI) {
4594 for (BasicBlock::iterator I = SrcBB->begin(), E = --SrcBB->end(); I != E; ++I)
4595 if (isSelector(I)) {
4596 // Apply the catch info to DestBB.
4597 addCatchInfo(cast<CallInst>(*I), MMI, FLI.MBBMap[DestBB]);
4599 if (!FLI.MBBMap[SrcBB]->isLandingPad())
4600 FLI.CatchInfoFound.insert(I);
4605 /// CheckDAGForTailCallsAndFixThem - This Function looks for CALL nodes in the
4606 /// DAG and fixes their tailcall attribute operand.
4607 static void CheckDAGForTailCallsAndFixThem(SelectionDAG &DAG,
4608 TargetLowering& TLI) {
4609 SDNode * Ret = NULL;
4610 SDOperand Terminator = DAG.getRoot();
4613 if (Terminator.getOpcode() == ISD::RET) {
4614 Ret = Terminator.Val;
4617 // Fix tail call attribute of CALL nodes.
4618 for (SelectionDAG::allnodes_iterator BE = DAG.allnodes_begin(),
4619 BI = prior(DAG.allnodes_end()); BI != BE; --BI) {
4620 if (BI->getOpcode() == ISD::CALL) {
4621 SDOperand OpRet(Ret, 0);
4622 SDOperand OpCall(static_cast<SDNode*>(BI), 0);
4623 bool isMarkedTailCall =
4624 cast<ConstantSDNode>(OpCall.getOperand(3))->getValue() != 0;
4625 // If CALL node has tail call attribute set to true and the call is not
4626 // eligible (no RET or the target rejects) the attribute is fixed to
4627 // false. The TargetLowering::IsEligibleForTailCallOptimization function
4628 // must correctly identify tail call optimizable calls.
4629 if (isMarkedTailCall &&
4631 !TLI.IsEligibleForTailCallOptimization(OpCall, OpRet, DAG))) {
4632 SmallVector<SDOperand, 32> Ops;
4634 for(SDNode::op_iterator I =OpCall.Val->op_begin(),
4635 E=OpCall.Val->op_end(); I!=E; I++, idx++) {
4639 Ops.push_back(DAG.getConstant(false, TLI.getPointerTy()));
4641 DAG.UpdateNodeOperands(OpCall, Ops.begin(), Ops.size());
4647 void SelectionDAGISel::BuildSelectionDAG(SelectionDAG &DAG, BasicBlock *LLVMBB,
4648 std::vector<std::pair<MachineInstr*, unsigned> > &PHINodesToUpdate,
4649 FunctionLoweringInfo &FuncInfo) {
4650 SelectionDAGLowering SDL(DAG, TLI, *AA, FuncInfo, GCI);
4652 std::vector<SDOperand> UnorderedChains;
4654 // Lower any arguments needed in this block if this is the entry block.
4655 if (LLVMBB == &LLVMBB->getParent()->getEntryBlock())
4656 LowerArguments(LLVMBB, SDL, UnorderedChains);
4658 BB = FuncInfo.MBBMap[LLVMBB];
4659 SDL.setCurrentBasicBlock(BB);
4661 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
4663 if (ExceptionHandling && MMI && BB->isLandingPad()) {
4664 // Add a label to mark the beginning of the landing pad. Deletion of the
4665 // landing pad can thus be detected via the MachineModuleInfo.
4666 unsigned LabelID = MMI->addLandingPad(BB);
4667 DAG.setRoot(DAG.getNode(ISD::LABEL, MVT::Other, DAG.getEntryNode(),
4668 DAG.getConstant(LabelID, MVT::i32),
4669 DAG.getConstant(1, MVT::i32)));
4671 // Mark exception register as live in.
4672 unsigned Reg = TLI.getExceptionAddressRegister();
4673 if (Reg) BB->addLiveIn(Reg);
4675 // Mark exception selector register as live in.
4676 Reg = TLI.getExceptionSelectorRegister();
4677 if (Reg) BB->addLiveIn(Reg);
4679 // FIXME: Hack around an exception handling flaw (PR1508): the personality
4680 // function and list of typeids logically belong to the invoke (or, if you
4681 // like, the basic block containing the invoke), and need to be associated
4682 // with it in the dwarf exception handling tables. Currently however the
4683 // information is provided by an intrinsic (eh.selector) that can be moved
4684 // to unexpected places by the optimizers: if the unwind edge is critical,
4685 // then breaking it can result in the intrinsics being in the successor of
4686 // the landing pad, not the landing pad itself. This results in exceptions
4687 // not being caught because no typeids are associated with the invoke.
4688 // This may not be the only way things can go wrong, but it is the only way
4689 // we try to work around for the moment.
4690 BranchInst *Br = dyn_cast<BranchInst>(LLVMBB->getTerminator());
4692 if (Br && Br->isUnconditional()) { // Critical edge?
4693 BasicBlock::iterator I, E;
4694 for (I = LLVMBB->begin(), E = --LLVMBB->end(); I != E; ++I)
4699 // No catch info found - try to extract some from the successor.
4700 copyCatchInfo(Br->getSuccessor(0), LLVMBB, MMI, FuncInfo);
4704 // Lower all of the non-terminator instructions.
4705 for (BasicBlock::iterator I = LLVMBB->begin(), E = --LLVMBB->end();
4709 // Ensure that all instructions which are used outside of their defining
4710 // blocks are available as virtual registers. Invoke is handled elsewhere.
4711 for (BasicBlock::iterator I = LLVMBB->begin(), E = LLVMBB->end(); I != E;++I)
4712 if (!I->use_empty() && !isa<PHINode>(I) && !isa<InvokeInst>(I)) {
4713 DenseMap<const Value*, unsigned>::iterator VMI =FuncInfo.ValueMap.find(I);
4714 if (VMI != FuncInfo.ValueMap.end())
4715 UnorderedChains.push_back(
4716 SDL.CopyValueToVirtualRegister(I, VMI->second));
4719 // Handle PHI nodes in successor blocks. Emit code into the SelectionDAG to
4720 // ensure constants are generated when needed. Remember the virtual registers
4721 // that need to be added to the Machine PHI nodes as input. We cannot just
4722 // directly add them, because expansion might result in multiple MBB's for one
4723 // BB. As such, the start of the BB might correspond to a different MBB than
4726 TerminatorInst *TI = LLVMBB->getTerminator();
4728 // Emit constants only once even if used by multiple PHI nodes.
4729 std::map<Constant*, unsigned> ConstantsOut;
4731 // Vector bool would be better, but vector<bool> is really slow.
4732 std::vector<unsigned char> SuccsHandled;
4733 if (TI->getNumSuccessors())
4734 SuccsHandled.resize(BB->getParent()->getNumBlockIDs());
4736 // Check successor nodes' PHI nodes that expect a constant to be available
4738 for (unsigned succ = 0, e = TI->getNumSuccessors(); succ != e; ++succ) {
4739 BasicBlock *SuccBB = TI->getSuccessor(succ);
4740 if (!isa<PHINode>(SuccBB->begin())) continue;
4741 MachineBasicBlock *SuccMBB = FuncInfo.MBBMap[SuccBB];
4743 // If this terminator has multiple identical successors (common for
4744 // switches), only handle each succ once.
4745 unsigned SuccMBBNo = SuccMBB->getNumber();
4746 if (SuccsHandled[SuccMBBNo]) continue;
4747 SuccsHandled[SuccMBBNo] = true;
4749 MachineBasicBlock::iterator MBBI = SuccMBB->begin();
4752 // At this point we know that there is a 1-1 correspondence between LLVM PHI
4753 // nodes and Machine PHI nodes, but the incoming operands have not been
4755 for (BasicBlock::iterator I = SuccBB->begin();
4756 (PN = dyn_cast<PHINode>(I)); ++I) {
4757 // Ignore dead phi's.
4758 if (PN->use_empty()) continue;
4761 Value *PHIOp = PN->getIncomingValueForBlock(LLVMBB);
4763 if (Constant *C = dyn_cast<Constant>(PHIOp)) {
4764 unsigned &RegOut = ConstantsOut[C];
4766 RegOut = FuncInfo.CreateRegForValue(C);
4767 UnorderedChains.push_back(
4768 SDL.CopyValueToVirtualRegister(C, RegOut));
4772 Reg = FuncInfo.ValueMap[PHIOp];
4774 assert(isa<AllocaInst>(PHIOp) &&
4775 FuncInfo.StaticAllocaMap.count(cast<AllocaInst>(PHIOp)) &&
4776 "Didn't codegen value into a register!??");
4777 Reg = FuncInfo.CreateRegForValue(PHIOp);
4778 UnorderedChains.push_back(
4779 SDL.CopyValueToVirtualRegister(PHIOp, Reg));
4783 // Remember that this register needs to added to the machine PHI node as
4784 // the input for this MBB.
4785 MVT::ValueType VT = TLI.getValueType(PN->getType());
4786 unsigned NumRegisters = TLI.getNumRegisters(VT);
4787 for (unsigned i = 0, e = NumRegisters; i != e; ++i)
4788 PHINodesToUpdate.push_back(std::make_pair(MBBI++, Reg+i));
4791 ConstantsOut.clear();
4793 // Turn all of the unordered chains into one factored node.
4794 if (!UnorderedChains.empty()) {
4795 SDOperand Root = SDL.getRoot();
4796 if (Root.getOpcode() != ISD::EntryToken) {
4797 unsigned i = 0, e = UnorderedChains.size();
4798 for (; i != e; ++i) {
4799 assert(UnorderedChains[i].Val->getNumOperands() > 1);
4800 if (UnorderedChains[i].Val->getOperand(0) == Root)
4801 break; // Don't add the root if we already indirectly depend on it.
4805 UnorderedChains.push_back(Root);
4807 DAG.setRoot(DAG.getNode(ISD::TokenFactor, MVT::Other,
4808 &UnorderedChains[0], UnorderedChains.size()));
4811 // Lower the terminator after the copies are emitted.
4812 SDL.visit(*LLVMBB->getTerminator());
4814 // Copy over any CaseBlock records that may now exist due to SwitchInst
4815 // lowering, as well as any jump table information.
4816 SwitchCases.clear();
4817 SwitchCases = SDL.SwitchCases;
4819 JTCases = SDL.JTCases;
4820 BitTestCases.clear();
4821 BitTestCases = SDL.BitTestCases;
4823 // Make sure the root of the DAG is up-to-date.
4824 DAG.setRoot(SDL.getRoot());
4826 // Check whether calls in this block are real tail calls. Fix up CALL nodes
4827 // with correct tailcall attribute so that the target can rely on the tailcall
4828 // attribute indicating whether the call is really eligible for tail call
4830 CheckDAGForTailCallsAndFixThem(DAG, TLI);
4833 void SelectionDAGISel::CodeGenAndEmitDAG(SelectionDAG &DAG) {
4834 DOUT << "Lowered selection DAG:\n";
4837 // Run the DAG combiner in pre-legalize mode.
4838 DAG.Combine(false, *AA);
4840 DOUT << "Optimized lowered selection DAG:\n";
4843 // Second step, hack on the DAG until it only uses operations and types that
4844 // the target supports.
4845 #if 0 // Enable this some day.
4846 DAG.LegalizeTypes();
4847 // Someday even later, enable a dag combine pass here.
4851 DOUT << "Legalized selection DAG:\n";
4854 // Run the DAG combiner in post-legalize mode.
4855 DAG.Combine(true, *AA);
4857 DOUT << "Optimized legalized selection DAG:\n";
4860 if (ViewISelDAGs) DAG.viewGraph();
4862 // Third, instruction select all of the operations to machine code, adding the
4863 // code to the MachineBasicBlock.
4864 InstructionSelectBasicBlock(DAG);
4866 DOUT << "Selected machine code:\n";
4870 void SelectionDAGISel::SelectBasicBlock(BasicBlock *LLVMBB, MachineFunction &MF,
4871 FunctionLoweringInfo &FuncInfo) {
4872 std::vector<std::pair<MachineInstr*, unsigned> > PHINodesToUpdate;
4874 SelectionDAG DAG(TLI, MF, getAnalysisToUpdate<MachineModuleInfo>());
4877 // First step, lower LLVM code to some DAG. This DAG may use operations and
4878 // types that are not supported by the target.
4879 BuildSelectionDAG(DAG, LLVMBB, PHINodesToUpdate, FuncInfo);
4881 // Second step, emit the lowered DAG as machine code.
4882 CodeGenAndEmitDAG(DAG);
4885 DOUT << "Total amount of phi nodes to update: "
4886 << PHINodesToUpdate.size() << "\n";
4887 DEBUG(for (unsigned i = 0, e = PHINodesToUpdate.size(); i != e; ++i)
4888 DOUT << "Node " << i << " : (" << PHINodesToUpdate[i].first
4889 << ", " << PHINodesToUpdate[i].second << ")\n";);
4891 // Next, now that we know what the last MBB the LLVM BB expanded is, update
4892 // PHI nodes in successors.
4893 if (SwitchCases.empty() && JTCases.empty() && BitTestCases.empty()) {
4894 for (unsigned i = 0, e = PHINodesToUpdate.size(); i != e; ++i) {
4895 MachineInstr *PHI = PHINodesToUpdate[i].first;
4896 assert(PHI->getOpcode() == TargetInstrInfo::PHI &&
4897 "This is not a machine PHI node that we are updating!");
4898 PHI->addOperand(MachineOperand::CreateReg(PHINodesToUpdate[i].second,
4900 PHI->addOperand(MachineOperand::CreateMBB(BB));
4905 for (unsigned i = 0, e = BitTestCases.size(); i != e; ++i) {
4906 // Lower header first, if it wasn't already lowered
4907 if (!BitTestCases[i].Emitted) {
4908 SelectionDAG HSDAG(TLI, MF, getAnalysisToUpdate<MachineModuleInfo>());
4910 SelectionDAGLowering HSDL(HSDAG, TLI, *AA, FuncInfo, GCI);
4911 // Set the current basic block to the mbb we wish to insert the code into
4912 BB = BitTestCases[i].Parent;
4913 HSDL.setCurrentBasicBlock(BB);
4915 HSDL.visitBitTestHeader(BitTestCases[i]);
4916 HSDAG.setRoot(HSDL.getRoot());
4917 CodeGenAndEmitDAG(HSDAG);
4920 for (unsigned j = 0, ej = BitTestCases[i].Cases.size(); j != ej; ++j) {
4921 SelectionDAG BSDAG(TLI, MF, getAnalysisToUpdate<MachineModuleInfo>());
4923 SelectionDAGLowering BSDL(BSDAG, TLI, *AA, FuncInfo, GCI);
4924 // Set the current basic block to the mbb we wish to insert the code into
4925 BB = BitTestCases[i].Cases[j].ThisBB;
4926 BSDL.setCurrentBasicBlock(BB);
4929 BSDL.visitBitTestCase(BitTestCases[i].Cases[j+1].ThisBB,
4930 BitTestCases[i].Reg,
4931 BitTestCases[i].Cases[j]);
4933 BSDL.visitBitTestCase(BitTestCases[i].Default,
4934 BitTestCases[i].Reg,
4935 BitTestCases[i].Cases[j]);
4938 BSDAG.setRoot(BSDL.getRoot());
4939 CodeGenAndEmitDAG(BSDAG);
4943 for (unsigned pi = 0, pe = PHINodesToUpdate.size(); pi != pe; ++pi) {
4944 MachineInstr *PHI = PHINodesToUpdate[pi].first;
4945 MachineBasicBlock *PHIBB = PHI->getParent();
4946 assert(PHI->getOpcode() == TargetInstrInfo::PHI &&
4947 "This is not a machine PHI node that we are updating!");
4948 // This is "default" BB. We have two jumps to it. From "header" BB and
4949 // from last "case" BB.
4950 if (PHIBB == BitTestCases[i].Default) {
4951 PHI->addOperand(MachineOperand::CreateReg(PHINodesToUpdate[pi].second,
4953 PHI->addOperand(MachineOperand::CreateMBB(BitTestCases[i].Parent));
4954 PHI->addOperand(MachineOperand::CreateReg(PHINodesToUpdate[pi].second,
4956 PHI->addOperand(MachineOperand::CreateMBB(BitTestCases[i].Cases.
4959 // One of "cases" BB.
4960 for (unsigned j = 0, ej = BitTestCases[i].Cases.size(); j != ej; ++j) {
4961 MachineBasicBlock* cBB = BitTestCases[i].Cases[j].ThisBB;
4962 if (cBB->succ_end() !=
4963 std::find(cBB->succ_begin(),cBB->succ_end(), PHIBB)) {
4964 PHI->addOperand(MachineOperand::CreateReg(PHINodesToUpdate[pi].second,
4966 PHI->addOperand(MachineOperand::CreateMBB(cBB));
4972 // If the JumpTable record is filled in, then we need to emit a jump table.
4973 // Updating the PHI nodes is tricky in this case, since we need to determine
4974 // whether the PHI is a successor of the range check MBB or the jump table MBB
4975 for (unsigned i = 0, e = JTCases.size(); i != e; ++i) {
4976 // Lower header first, if it wasn't already lowered
4977 if (!JTCases[i].first.Emitted) {
4978 SelectionDAG HSDAG(TLI, MF, getAnalysisToUpdate<MachineModuleInfo>());
4980 SelectionDAGLowering HSDL(HSDAG, TLI, *AA, FuncInfo, GCI);
4981 // Set the current basic block to the mbb we wish to insert the code into
4982 BB = JTCases[i].first.HeaderBB;
4983 HSDL.setCurrentBasicBlock(BB);
4985 HSDL.visitJumpTableHeader(JTCases[i].second, JTCases[i].first);
4986 HSDAG.setRoot(HSDL.getRoot());
4987 CodeGenAndEmitDAG(HSDAG);
4990 SelectionDAG JSDAG(TLI, MF, getAnalysisToUpdate<MachineModuleInfo>());
4992 SelectionDAGLowering JSDL(JSDAG, TLI, *AA, FuncInfo, GCI);
4993 // Set the current basic block to the mbb we wish to insert the code into
4994 BB = JTCases[i].second.MBB;
4995 JSDL.setCurrentBasicBlock(BB);
4997 JSDL.visitJumpTable(JTCases[i].second);
4998 JSDAG.setRoot(JSDL.getRoot());
4999 CodeGenAndEmitDAG(JSDAG);
5002 for (unsigned pi = 0, pe = PHINodesToUpdate.size(); pi != pe; ++pi) {
5003 MachineInstr *PHI = PHINodesToUpdate[pi].first;
5004 MachineBasicBlock *PHIBB = PHI->getParent();
5005 assert(PHI->getOpcode() == TargetInstrInfo::PHI &&
5006 "This is not a machine PHI node that we are updating!");
5007 // "default" BB. We can go there only from header BB.
5008 if (PHIBB == JTCases[i].second.Default) {
5009 PHI->addOperand(MachineOperand::CreateReg(PHINodesToUpdate[pi].second,
5011 PHI->addOperand(MachineOperand::CreateMBB(JTCases[i].first.HeaderBB));
5013 // JT BB. Just iterate over successors here
5014 if (BB->succ_end() != std::find(BB->succ_begin(),BB->succ_end(), PHIBB)) {
5015 PHI->addOperand(MachineOperand::CreateReg(PHINodesToUpdate[pi].second,
5017 PHI->addOperand(MachineOperand::CreateMBB(BB));
5022 // If the switch block involved a branch to one of the actual successors, we
5023 // need to update PHI nodes in that block.
5024 for (unsigned i = 0, e = PHINodesToUpdate.size(); i != e; ++i) {
5025 MachineInstr *PHI = PHINodesToUpdate[i].first;
5026 assert(PHI->getOpcode() == TargetInstrInfo::PHI &&
5027 "This is not a machine PHI node that we are updating!");
5028 if (BB->isSuccessor(PHI->getParent())) {
5029 PHI->addOperand(MachineOperand::CreateReg(PHINodesToUpdate[i].second,
5031 PHI->addOperand(MachineOperand::CreateMBB(BB));
5035 // If we generated any switch lowering information, build and codegen any
5036 // additional DAGs necessary.
5037 for (unsigned i = 0, e = SwitchCases.size(); i != e; ++i) {
5038 SelectionDAG SDAG(TLI, MF, getAnalysisToUpdate<MachineModuleInfo>());
5040 SelectionDAGLowering SDL(SDAG, TLI, *AA, FuncInfo, GCI);
5042 // Set the current basic block to the mbb we wish to insert the code into
5043 BB = SwitchCases[i].ThisBB;
5044 SDL.setCurrentBasicBlock(BB);
5047 SDL.visitSwitchCase(SwitchCases[i]);
5048 SDAG.setRoot(SDL.getRoot());
5049 CodeGenAndEmitDAG(SDAG);
5051 // Handle any PHI nodes in successors of this chunk, as if we were coming
5052 // from the original BB before switch expansion. Note that PHI nodes can
5053 // occur multiple times in PHINodesToUpdate. We have to be very careful to
5054 // handle them the right number of times.
5055 while ((BB = SwitchCases[i].TrueBB)) { // Handle LHS and RHS.
5056 for (MachineBasicBlock::iterator Phi = BB->begin();
5057 Phi != BB->end() && Phi->getOpcode() == TargetInstrInfo::PHI; ++Phi){
5058 // This value for this PHI node is recorded in PHINodesToUpdate, get it.
5059 for (unsigned pn = 0; ; ++pn) {
5060 assert(pn != PHINodesToUpdate.size() && "Didn't find PHI entry!");
5061 if (PHINodesToUpdate[pn].first == Phi) {
5062 Phi->addOperand(MachineOperand::CreateReg(PHINodesToUpdate[pn].
5064 Phi->addOperand(MachineOperand::CreateMBB(SwitchCases[i].ThisBB));
5070 // Don't process RHS if same block as LHS.
5071 if (BB == SwitchCases[i].FalseBB)
5072 SwitchCases[i].FalseBB = 0;
5074 // If we haven't handled the RHS, do so now. Otherwise, we're done.
5075 SwitchCases[i].TrueBB = SwitchCases[i].FalseBB;
5076 SwitchCases[i].FalseBB = 0;
5078 assert(SwitchCases[i].TrueBB == 0 && SwitchCases[i].FalseBB == 0);
5083 //===----------------------------------------------------------------------===//
5084 /// ScheduleAndEmitDAG - Pick a safe ordering and emit instructions for each
5085 /// target node in the graph.
5086 void SelectionDAGISel::ScheduleAndEmitDAG(SelectionDAG &DAG) {
5087 if (ViewSchedDAGs) DAG.viewGraph();
5089 RegisterScheduler::FunctionPassCtor Ctor = RegisterScheduler::getDefault();
5093 RegisterScheduler::setDefault(Ctor);
5096 ScheduleDAG *SL = Ctor(this, &DAG, BB);
5099 if (ViewSUnitDAGs) SL->viewGraph();
5105 HazardRecognizer *SelectionDAGISel::CreateTargetHazardRecognizer() {
5106 return new HazardRecognizer();
5109 //===----------------------------------------------------------------------===//
5110 // Helper functions used by the generated instruction selector.
5111 //===----------------------------------------------------------------------===//
5112 // Calls to these methods are generated by tblgen.
5114 /// CheckAndMask - The isel is trying to match something like (and X, 255). If
5115 /// the dag combiner simplified the 255, we still want to match. RHS is the
5116 /// actual value in the DAG on the RHS of an AND, and DesiredMaskS is the value
5117 /// specified in the .td file (e.g. 255).
5118 bool SelectionDAGISel::CheckAndMask(SDOperand LHS, ConstantSDNode *RHS,
5119 int64_t DesiredMaskS) const {
5120 uint64_t ActualMask = RHS->getValue();
5121 uint64_t DesiredMask =DesiredMaskS & MVT::getIntVTBitMask(LHS.getValueType());
5123 // If the actual mask exactly matches, success!
5124 if (ActualMask == DesiredMask)
5127 // If the actual AND mask is allowing unallowed bits, this doesn't match.
5128 if (ActualMask & ~DesiredMask)
5131 // Otherwise, the DAG Combiner may have proven that the value coming in is
5132 // either already zero or is not demanded. Check for known zero input bits.
5133 uint64_t NeededMask = DesiredMask & ~ActualMask;
5134 if (CurDAG->MaskedValueIsZero(LHS, NeededMask))
5137 // TODO: check to see if missing bits are just not demanded.
5139 // Otherwise, this pattern doesn't match.
5143 /// CheckOrMask - The isel is trying to match something like (or X, 255). If
5144 /// the dag combiner simplified the 255, we still want to match. RHS is the
5145 /// actual value in the DAG on the RHS of an OR, and DesiredMaskS is the value
5146 /// specified in the .td file (e.g. 255).
5147 bool SelectionDAGISel::CheckOrMask(SDOperand LHS, ConstantSDNode *RHS,
5148 int64_t DesiredMaskS) const {
5149 uint64_t ActualMask = RHS->getValue();
5150 uint64_t DesiredMask =DesiredMaskS & MVT::getIntVTBitMask(LHS.getValueType());
5152 // If the actual mask exactly matches, success!
5153 if (ActualMask == DesiredMask)
5156 // If the actual AND mask is allowing unallowed bits, this doesn't match.
5157 if (ActualMask & ~DesiredMask)
5160 // Otherwise, the DAG Combiner may have proven that the value coming in is
5161 // either already zero or is not demanded. Check for known zero input bits.
5162 uint64_t NeededMask = DesiredMask & ~ActualMask;
5164 uint64_t KnownZero, KnownOne;
5165 CurDAG->ComputeMaskedBits(LHS, NeededMask, KnownZero, KnownOne);
5167 // If all the missing bits in the or are already known to be set, match!
5168 if ((NeededMask & KnownOne) == NeededMask)
5171 // TODO: check to see if missing bits are just not demanded.
5173 // Otherwise, this pattern doesn't match.
5178 /// SelectInlineAsmMemoryOperands - Calls to this are automatically generated
5179 /// by tblgen. Others should not call it.
5180 void SelectionDAGISel::
5181 SelectInlineAsmMemoryOperands(std::vector<SDOperand> &Ops, SelectionDAG &DAG) {
5182 std::vector<SDOperand> InOps;
5183 std::swap(InOps, Ops);
5185 Ops.push_back(InOps[0]); // input chain.
5186 Ops.push_back(InOps[1]); // input asm string.
5188 unsigned i = 2, e = InOps.size();
5189 if (InOps[e-1].getValueType() == MVT::Flag)
5190 --e; // Don't process a flag operand if it is here.
5193 unsigned Flags = cast<ConstantSDNode>(InOps[i])->getValue();
5194 if ((Flags & 7) != 4 /*MEM*/) {
5195 // Just skip over this operand, copying the operands verbatim.
5196 Ops.insert(Ops.end(), InOps.begin()+i, InOps.begin()+i+(Flags >> 3) + 1);
5197 i += (Flags >> 3) + 1;
5199 assert((Flags >> 3) == 1 && "Memory operand with multiple values?");
5200 // Otherwise, this is a memory operand. Ask the target to select it.
5201 std::vector<SDOperand> SelOps;
5202 if (SelectInlineAsmMemoryOperand(InOps[i+1], 'm', SelOps, DAG)) {
5203 cerr << "Could not match memory address. Inline asm failure!\n";
5207 // Add this to the output node.
5208 MVT::ValueType IntPtrTy = DAG.getTargetLoweringInfo().getPointerTy();
5209 Ops.push_back(DAG.getTargetConstant(4/*MEM*/ | (SelOps.size() << 3),
5211 Ops.insert(Ops.end(), SelOps.begin(), SelOps.end());
5216 // Add the flag input back if present.
5217 if (e != InOps.size())
5218 Ops.push_back(InOps.back());
5221 char SelectionDAGISel::ID = 0;