1 //===-- SelectionDAGISel.cpp - Implement the SelectionDAGISel class -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements the SelectionDAGISel class.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/CodeGen/SelectionDAGISel.h"
15 #include "ScheduleDAGSDNodes.h"
16 #include "SelectionDAGBuilder.h"
17 #include "llvm/ADT/PostOrderIterator.h"
18 #include "llvm/ADT/Statistic.h"
19 #include "llvm/Analysis/AliasAnalysis.h"
20 #include "llvm/Analysis/BranchProbabilityInfo.h"
21 #include "llvm/Analysis/CFG.h"
22 #include "llvm/CodeGen/FastISel.h"
23 #include "llvm/CodeGen/FunctionLoweringInfo.h"
24 #include "llvm/CodeGen/GCMetadata.h"
25 #include "llvm/CodeGen/GCStrategy.h"
26 #include "llvm/CodeGen/MachineFrameInfo.h"
27 #include "llvm/CodeGen/MachineFunction.h"
28 #include "llvm/CodeGen/MachineInstrBuilder.h"
29 #include "llvm/CodeGen/MachineModuleInfo.h"
30 #include "llvm/CodeGen/MachineRegisterInfo.h"
31 #include "llvm/CodeGen/ScheduleHazardRecognizer.h"
32 #include "llvm/CodeGen/SchedulerRegistry.h"
33 #include "llvm/CodeGen/SelectionDAG.h"
34 #include "llvm/IR/Constants.h"
35 #include "llvm/IR/DebugInfo.h"
36 #include "llvm/IR/Function.h"
37 #include "llvm/IR/InlineAsm.h"
38 #include "llvm/IR/Instructions.h"
39 #include "llvm/IR/IntrinsicInst.h"
40 #include "llvm/IR/Intrinsics.h"
41 #include "llvm/IR/LLVMContext.h"
42 #include "llvm/IR/Module.h"
43 #include "llvm/Support/Compiler.h"
44 #include "llvm/Support/Debug.h"
45 #include "llvm/Support/ErrorHandling.h"
46 #include "llvm/Support/Timer.h"
47 #include "llvm/Support/raw_ostream.h"
48 #include "llvm/Target/TargetInstrInfo.h"
49 #include "llvm/Target/TargetIntrinsicInfo.h"
50 #include "llvm/Target/TargetLibraryInfo.h"
51 #include "llvm/Target/TargetLowering.h"
52 #include "llvm/Target/TargetMachine.h"
53 #include "llvm/Target/TargetOptions.h"
54 #include "llvm/Target/TargetRegisterInfo.h"
55 #include "llvm/Target/TargetSubtargetInfo.h"
56 #include "llvm/Transforms/Utils/BasicBlockUtils.h"
60 #define DEBUG_TYPE "isel"
62 STATISTIC(NumFastIselFailures, "Number of instructions fast isel failed on");
63 STATISTIC(NumFastIselSuccess, "Number of instructions fast isel selected");
64 STATISTIC(NumFastIselBlocks, "Number of blocks selected entirely by fast isel");
65 STATISTIC(NumDAGBlocks, "Number of blocks selected using DAG");
66 STATISTIC(NumDAGIselRetries,"Number of times dag isel has to try another path");
67 STATISTIC(NumEntryBlocks, "Number of entry blocks encountered");
68 STATISTIC(NumFastIselFailLowerArguments,
69 "Number of entry blocks where fast isel failed to lower arguments");
73 EnableFastISelVerbose2("fast-isel-verbose2", cl::Hidden,
74 cl::desc("Enable extra verbose messages in the \"fast\" "
75 "instruction selector"));
78 STATISTIC(NumFastIselFailRet,"Fast isel fails on Ret");
79 STATISTIC(NumFastIselFailBr,"Fast isel fails on Br");
80 STATISTIC(NumFastIselFailSwitch,"Fast isel fails on Switch");
81 STATISTIC(NumFastIselFailIndirectBr,"Fast isel fails on IndirectBr");
82 STATISTIC(NumFastIselFailInvoke,"Fast isel fails on Invoke");
83 STATISTIC(NumFastIselFailResume,"Fast isel fails on Resume");
84 STATISTIC(NumFastIselFailUnreachable,"Fast isel fails on Unreachable");
86 // Standard binary operators...
87 STATISTIC(NumFastIselFailAdd,"Fast isel fails on Add");
88 STATISTIC(NumFastIselFailFAdd,"Fast isel fails on FAdd");
89 STATISTIC(NumFastIselFailSub,"Fast isel fails on Sub");
90 STATISTIC(NumFastIselFailFSub,"Fast isel fails on FSub");
91 STATISTIC(NumFastIselFailMul,"Fast isel fails on Mul");
92 STATISTIC(NumFastIselFailFMul,"Fast isel fails on FMul");
93 STATISTIC(NumFastIselFailUDiv,"Fast isel fails on UDiv");
94 STATISTIC(NumFastIselFailSDiv,"Fast isel fails on SDiv");
95 STATISTIC(NumFastIselFailFDiv,"Fast isel fails on FDiv");
96 STATISTIC(NumFastIselFailURem,"Fast isel fails on URem");
97 STATISTIC(NumFastIselFailSRem,"Fast isel fails on SRem");
98 STATISTIC(NumFastIselFailFRem,"Fast isel fails on FRem");
100 // Logical operators...
101 STATISTIC(NumFastIselFailAnd,"Fast isel fails on And");
102 STATISTIC(NumFastIselFailOr,"Fast isel fails on Or");
103 STATISTIC(NumFastIselFailXor,"Fast isel fails on Xor");
105 // Memory instructions...
106 STATISTIC(NumFastIselFailAlloca,"Fast isel fails on Alloca");
107 STATISTIC(NumFastIselFailLoad,"Fast isel fails on Load");
108 STATISTIC(NumFastIselFailStore,"Fast isel fails on Store");
109 STATISTIC(NumFastIselFailAtomicCmpXchg,"Fast isel fails on AtomicCmpXchg");
110 STATISTIC(NumFastIselFailAtomicRMW,"Fast isel fails on AtomicRWM");
111 STATISTIC(NumFastIselFailFence,"Fast isel fails on Frence");
112 STATISTIC(NumFastIselFailGetElementPtr,"Fast isel fails on GetElementPtr");
114 // Convert instructions...
115 STATISTIC(NumFastIselFailTrunc,"Fast isel fails on Trunc");
116 STATISTIC(NumFastIselFailZExt,"Fast isel fails on ZExt");
117 STATISTIC(NumFastIselFailSExt,"Fast isel fails on SExt");
118 STATISTIC(NumFastIselFailFPTrunc,"Fast isel fails on FPTrunc");
119 STATISTIC(NumFastIselFailFPExt,"Fast isel fails on FPExt");
120 STATISTIC(NumFastIselFailFPToUI,"Fast isel fails on FPToUI");
121 STATISTIC(NumFastIselFailFPToSI,"Fast isel fails on FPToSI");
122 STATISTIC(NumFastIselFailUIToFP,"Fast isel fails on UIToFP");
123 STATISTIC(NumFastIselFailSIToFP,"Fast isel fails on SIToFP");
124 STATISTIC(NumFastIselFailIntToPtr,"Fast isel fails on IntToPtr");
125 STATISTIC(NumFastIselFailPtrToInt,"Fast isel fails on PtrToInt");
126 STATISTIC(NumFastIselFailBitCast,"Fast isel fails on BitCast");
128 // Other instructions...
129 STATISTIC(NumFastIselFailICmp,"Fast isel fails on ICmp");
130 STATISTIC(NumFastIselFailFCmp,"Fast isel fails on FCmp");
131 STATISTIC(NumFastIselFailPHI,"Fast isel fails on PHI");
132 STATISTIC(NumFastIselFailSelect,"Fast isel fails on Select");
133 STATISTIC(NumFastIselFailCall,"Fast isel fails on Call");
134 STATISTIC(NumFastIselFailShl,"Fast isel fails on Shl");
135 STATISTIC(NumFastIselFailLShr,"Fast isel fails on LShr");
136 STATISTIC(NumFastIselFailAShr,"Fast isel fails on AShr");
137 STATISTIC(NumFastIselFailVAArg,"Fast isel fails on VAArg");
138 STATISTIC(NumFastIselFailExtractElement,"Fast isel fails on ExtractElement");
139 STATISTIC(NumFastIselFailInsertElement,"Fast isel fails on InsertElement");
140 STATISTIC(NumFastIselFailShuffleVector,"Fast isel fails on ShuffleVector");
141 STATISTIC(NumFastIselFailExtractValue,"Fast isel fails on ExtractValue");
142 STATISTIC(NumFastIselFailInsertValue,"Fast isel fails on InsertValue");
143 STATISTIC(NumFastIselFailLandingPad,"Fast isel fails on LandingPad");
147 EnableFastISelVerbose("fast-isel-verbose", cl::Hidden,
148 cl::desc("Enable verbose messages in the \"fast\" "
149 "instruction selector"));
151 EnableFastISelAbort("fast-isel-abort", cl::Hidden,
152 cl::desc("Enable abort calls when \"fast\" instruction selection "
153 "fails to lower an instruction"));
155 EnableFastISelAbortArgs("fast-isel-abort-args", cl::Hidden,
156 cl::desc("Enable abort calls when \"fast\" instruction selection "
157 "fails to lower a formal argument"));
161 cl::desc("use Machine Branch Probability Info"),
162 cl::init(true), cl::Hidden);
166 ViewDAGCombine1("view-dag-combine1-dags", cl::Hidden,
167 cl::desc("Pop up a window to show dags before the first "
168 "dag combine pass"));
170 ViewLegalizeTypesDAGs("view-legalize-types-dags", cl::Hidden,
171 cl::desc("Pop up a window to show dags before legalize types"));
173 ViewLegalizeDAGs("view-legalize-dags", cl::Hidden,
174 cl::desc("Pop up a window to show dags before legalize"));
176 ViewDAGCombine2("view-dag-combine2-dags", cl::Hidden,
177 cl::desc("Pop up a window to show dags before the second "
178 "dag combine pass"));
180 ViewDAGCombineLT("view-dag-combine-lt-dags", cl::Hidden,
181 cl::desc("Pop up a window to show dags before the post legalize types"
182 " dag combine pass"));
184 ViewISelDAGs("view-isel-dags", cl::Hidden,
185 cl::desc("Pop up a window to show isel dags as they are selected"));
187 ViewSchedDAGs("view-sched-dags", cl::Hidden,
188 cl::desc("Pop up a window to show sched dags as they are processed"));
190 ViewSUnitDAGs("view-sunit-dags", cl::Hidden,
191 cl::desc("Pop up a window to show SUnit dags after they are processed"));
193 static const bool ViewDAGCombine1 = false,
194 ViewLegalizeTypesDAGs = false, ViewLegalizeDAGs = false,
195 ViewDAGCombine2 = false,
196 ViewDAGCombineLT = false,
197 ViewISelDAGs = false, ViewSchedDAGs = false,
198 ViewSUnitDAGs = false;
201 //===---------------------------------------------------------------------===//
203 /// RegisterScheduler class - Track the registration of instruction schedulers.
205 //===---------------------------------------------------------------------===//
206 MachinePassRegistry RegisterScheduler::Registry;
208 //===---------------------------------------------------------------------===//
210 /// ISHeuristic command line option for instruction schedulers.
212 //===---------------------------------------------------------------------===//
213 static cl::opt<RegisterScheduler::FunctionPassCtor, false,
214 RegisterPassParser<RegisterScheduler> >
215 ISHeuristic("pre-RA-sched",
216 cl::init(&createDefaultScheduler), cl::Hidden,
217 cl::desc("Instruction schedulers available (before register"
220 static RegisterScheduler
221 defaultListDAGScheduler("default", "Best scheduler for the target",
222 createDefaultScheduler);
225 //===--------------------------------------------------------------------===//
226 /// \brief This class is used by SelectionDAGISel to temporarily override
227 /// the optimization level on a per-function basis.
228 class OptLevelChanger {
229 SelectionDAGISel &IS;
230 CodeGenOpt::Level SavedOptLevel;
234 OptLevelChanger(SelectionDAGISel &ISel,
235 CodeGenOpt::Level NewOptLevel) : IS(ISel) {
236 SavedOptLevel = IS.OptLevel;
237 if (NewOptLevel == SavedOptLevel)
239 IS.OptLevel = NewOptLevel;
240 IS.TM.setOptLevel(NewOptLevel);
241 SavedFastISel = IS.TM.Options.EnableFastISel;
242 if (NewOptLevel == CodeGenOpt::None)
243 IS.TM.setFastISel(true);
244 DEBUG(dbgs() << "\nChanging optimization level for Function "
245 << IS.MF->getFunction()->getName() << "\n");
246 DEBUG(dbgs() << "\tBefore: -O" << SavedOptLevel
247 << " ; After: -O" << NewOptLevel << "\n");
251 if (IS.OptLevel == SavedOptLevel)
253 DEBUG(dbgs() << "\nRestoring optimization level for Function "
254 << IS.MF->getFunction()->getName() << "\n");
255 DEBUG(dbgs() << "\tBefore: -O" << IS.OptLevel
256 << " ; After: -O" << SavedOptLevel << "\n");
257 IS.OptLevel = SavedOptLevel;
258 IS.TM.setOptLevel(SavedOptLevel);
259 IS.TM.setFastISel(SavedFastISel);
263 //===--------------------------------------------------------------------===//
264 /// createDefaultScheduler - This creates an instruction scheduler appropriate
266 ScheduleDAGSDNodes* createDefaultScheduler(SelectionDAGISel *IS,
267 CodeGenOpt::Level OptLevel) {
268 const TargetLowering *TLI = IS->getTargetLowering();
269 const TargetSubtargetInfo &ST = IS->TM.getSubtarget<TargetSubtargetInfo>();
271 if (OptLevel == CodeGenOpt::None || ST.useMachineScheduler() ||
272 TLI->getSchedulingPreference() == Sched::Source)
273 return createSourceListDAGScheduler(IS, OptLevel);
274 if (TLI->getSchedulingPreference() == Sched::RegPressure)
275 return createBURRListDAGScheduler(IS, OptLevel);
276 if (TLI->getSchedulingPreference() == Sched::Hybrid)
277 return createHybridListDAGScheduler(IS, OptLevel);
278 if (TLI->getSchedulingPreference() == Sched::VLIW)
279 return createVLIWDAGScheduler(IS, OptLevel);
280 assert(TLI->getSchedulingPreference() == Sched::ILP &&
281 "Unknown sched type!");
282 return createILPListDAGScheduler(IS, OptLevel);
286 // EmitInstrWithCustomInserter - This method should be implemented by targets
287 // that mark instructions with the 'usesCustomInserter' flag. These
288 // instructions are special in various ways, which require special support to
289 // insert. The specified MachineInstr is created but not inserted into any
290 // basic blocks, and this method is called to expand it into a sequence of
291 // instructions, potentially also creating new basic blocks and control flow.
292 // When new basic blocks are inserted and the edges from MBB to its successors
293 // are modified, the method should insert pairs of <OldSucc, NewSucc> into the
296 TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
297 MachineBasicBlock *MBB) const {
299 dbgs() << "If a target marks an instruction with "
300 "'usesCustomInserter', it must implement "
301 "TargetLowering::EmitInstrWithCustomInserter!";
303 llvm_unreachable(nullptr);
306 void TargetLowering::AdjustInstrPostInstrSelection(MachineInstr *MI,
307 SDNode *Node) const {
308 assert(!MI->hasPostISelHook() &&
309 "If a target marks an instruction with 'hasPostISelHook', "
310 "it must implement TargetLowering::AdjustInstrPostInstrSelection!");
313 //===----------------------------------------------------------------------===//
314 // SelectionDAGISel code
315 //===----------------------------------------------------------------------===//
317 SelectionDAGISel::SelectionDAGISel(TargetMachine &tm,
318 CodeGenOpt::Level OL) :
319 MachineFunctionPass(ID), TM(tm),
320 FuncInfo(new FunctionLoweringInfo(TM)),
321 CurDAG(new SelectionDAG(tm, OL)),
322 SDB(new SelectionDAGBuilder(*CurDAG, *FuncInfo, OL)),
326 initializeGCModuleInfoPass(*PassRegistry::getPassRegistry());
327 initializeAliasAnalysisAnalysisGroup(*PassRegistry::getPassRegistry());
328 initializeBranchProbabilityInfoPass(*PassRegistry::getPassRegistry());
329 initializeTargetLibraryInfoPass(*PassRegistry::getPassRegistry());
332 SelectionDAGISel::~SelectionDAGISel() {
338 void SelectionDAGISel::getAnalysisUsage(AnalysisUsage &AU) const {
339 AU.addRequired<AliasAnalysis>();
340 AU.addPreserved<AliasAnalysis>();
341 AU.addRequired<GCModuleInfo>();
342 AU.addPreserved<GCModuleInfo>();
343 AU.addRequired<TargetLibraryInfo>();
344 if (UseMBPI && OptLevel != CodeGenOpt::None)
345 AU.addRequired<BranchProbabilityInfo>();
346 MachineFunctionPass::getAnalysisUsage(AU);
349 /// SplitCriticalSideEffectEdges - Look for critical edges with a PHI value that
350 /// may trap on it. In this case we have to split the edge so that the path
351 /// through the predecessor block that doesn't go to the phi block doesn't
352 /// execute the possibly trapping instruction.
354 /// This is required for correctness, so it must be done at -O0.
356 static void SplitCriticalSideEffectEdges(Function &Fn, Pass *SDISel) {
357 // Loop for blocks with phi nodes.
358 for (Function::iterator BB = Fn.begin(), E = Fn.end(); BB != E; ++BB) {
359 PHINode *PN = dyn_cast<PHINode>(BB->begin());
363 // For each block with a PHI node, check to see if any of the input values
364 // are potentially trapping constant expressions. Constant expressions are
365 // the only potentially trapping value that can occur as the argument to a
367 for (BasicBlock::iterator I = BB->begin(); (PN = dyn_cast<PHINode>(I)); ++I)
368 for (unsigned i = 0, e = PN->getNumIncomingValues(); i != e; ++i) {
369 ConstantExpr *CE = dyn_cast<ConstantExpr>(PN->getIncomingValue(i));
370 if (!CE || !CE->canTrap()) continue;
372 // The only case we have to worry about is when the edge is critical.
373 // Since this block has a PHI Node, we assume it has multiple input
374 // edges: check to see if the pred has multiple successors.
375 BasicBlock *Pred = PN->getIncomingBlock(i);
376 if (Pred->getTerminator()->getNumSuccessors() == 1)
379 // Okay, we have to split this edge.
380 SplitCriticalEdge(Pred->getTerminator(),
381 GetSuccessorNumber(Pred, BB), SDISel, true);
387 bool SelectionDAGISel::runOnMachineFunction(MachineFunction &mf) {
388 // Do some sanity-checking on the command-line options.
389 assert((!EnableFastISelVerbose || TM.Options.EnableFastISel) &&
390 "-fast-isel-verbose requires -fast-isel");
391 assert((!EnableFastISelAbort || TM.Options.EnableFastISel) &&
392 "-fast-isel-abort requires -fast-isel");
394 const Function &Fn = *mf.getFunction();
395 const TargetInstrInfo &TII = *TM.getInstrInfo();
396 const TargetRegisterInfo &TRI = *TM.getRegisterInfo();
397 const TargetLowering *TLI = TM.getTargetLowering();
400 RegInfo = &MF->getRegInfo();
401 AA = &getAnalysis<AliasAnalysis>();
402 LibInfo = &getAnalysis<TargetLibraryInfo>();
403 GFI = Fn.hasGC() ? &getAnalysis<GCModuleInfo>().getFunctionInfo(Fn) : nullptr;
405 TargetSubtargetInfo &ST =
406 const_cast<TargetSubtargetInfo&>(TM.getSubtarget<TargetSubtargetInfo>());
407 ST.resetSubtargetFeatures(MF);
408 TM.resetTargetOptions(MF);
410 // Reset OptLevel to None for optnone functions.
411 CodeGenOpt::Level NewOptLevel = OptLevel;
412 if (Fn.hasFnAttribute(Attribute::OptimizeNone))
413 NewOptLevel = CodeGenOpt::None;
414 OptLevelChanger OLC(*this, NewOptLevel);
416 DEBUG(dbgs() << "\n\n\n=== " << Fn.getName() << "\n");
418 SplitCriticalSideEffectEdges(const_cast<Function&>(Fn), this);
420 CurDAG->init(*MF, TLI);
421 FuncInfo->set(Fn, *MF, CurDAG);
423 if (UseMBPI && OptLevel != CodeGenOpt::None)
424 FuncInfo->BPI = &getAnalysis<BranchProbabilityInfo>();
426 FuncInfo->BPI = nullptr;
428 SDB->init(GFI, *AA, LibInfo);
430 MF->setHasInlineAsm(false);
432 SelectAllBasicBlocks(Fn);
434 // If the first basic block in the function has live ins that need to be
435 // copied into vregs, emit the copies into the top of the block before
436 // emitting the code for the block.
437 MachineBasicBlock *EntryMBB = MF->begin();
438 RegInfo->EmitLiveInCopies(EntryMBB, TRI, TII);
440 DenseMap<unsigned, unsigned> LiveInMap;
441 if (!FuncInfo->ArgDbgValues.empty())
442 for (MachineRegisterInfo::livein_iterator LI = RegInfo->livein_begin(),
443 E = RegInfo->livein_end(); LI != E; ++LI)
445 LiveInMap.insert(std::make_pair(LI->first, LI->second));
447 // Insert DBG_VALUE instructions for function arguments to the entry block.
448 for (unsigned i = 0, e = FuncInfo->ArgDbgValues.size(); i != e; ++i) {
449 MachineInstr *MI = FuncInfo->ArgDbgValues[e-i-1];
450 bool hasFI = MI->getOperand(0).isFI();
452 hasFI ? TRI.getFrameRegister(*MF) : MI->getOperand(0).getReg();
453 if (TargetRegisterInfo::isPhysicalRegister(Reg))
454 EntryMBB->insert(EntryMBB->begin(), MI);
456 MachineInstr *Def = RegInfo->getVRegDef(Reg);
458 MachineBasicBlock::iterator InsertPos = Def;
459 // FIXME: VR def may not be in entry block.
460 Def->getParent()->insert(std::next(InsertPos), MI);
462 DEBUG(dbgs() << "Dropping debug info for dead vreg"
463 << TargetRegisterInfo::virtReg2Index(Reg) << "\n");
466 // If Reg is live-in then update debug info to track its copy in a vreg.
467 DenseMap<unsigned, unsigned>::iterator LDI = LiveInMap.find(Reg);
468 if (LDI != LiveInMap.end()) {
469 assert(!hasFI && "There's no handling of frame pointer updating here yet "
471 MachineInstr *Def = RegInfo->getVRegDef(LDI->second);
472 MachineBasicBlock::iterator InsertPos = Def;
473 const MDNode *Variable =
474 MI->getOperand(MI->getNumOperands()-1).getMetadata();
475 bool IsIndirect = MI->isIndirectDebugValue();
476 unsigned Offset = IsIndirect ? MI->getOperand(1).getImm() : 0;
477 // Def is never a terminator here, so it is ok to increment InsertPos.
478 BuildMI(*EntryMBB, ++InsertPos, MI->getDebugLoc(),
479 TII.get(TargetOpcode::DBG_VALUE),
481 LDI->second, Offset, Variable);
483 // If this vreg is directly copied into an exported register then
484 // that COPY instructions also need DBG_VALUE, if it is the only
485 // user of LDI->second.
486 MachineInstr *CopyUseMI = nullptr;
487 for (MachineRegisterInfo::use_instr_iterator
488 UI = RegInfo->use_instr_begin(LDI->second),
489 E = RegInfo->use_instr_end(); UI != E; ) {
490 MachineInstr *UseMI = &*(UI++);
491 if (UseMI->isDebugValue()) continue;
492 if (UseMI->isCopy() && !CopyUseMI && UseMI->getParent() == EntryMBB) {
493 CopyUseMI = UseMI; continue;
495 // Otherwise this is another use or second copy use.
496 CopyUseMI = nullptr; break;
499 MachineInstr *NewMI =
500 BuildMI(*MF, CopyUseMI->getDebugLoc(),
501 TII.get(TargetOpcode::DBG_VALUE),
503 CopyUseMI->getOperand(0).getReg(),
505 MachineBasicBlock::iterator Pos = CopyUseMI;
506 EntryMBB->insertAfter(Pos, NewMI);
511 // Determine if there are any calls in this machine function.
512 MachineFrameInfo *MFI = MF->getFrameInfo();
513 for (MachineFunction::const_iterator I = MF->begin(), E = MF->end(); I != E;
516 if (MFI->hasCalls() && MF->hasInlineAsm())
519 const MachineBasicBlock *MBB = I;
520 for (MachineBasicBlock::const_iterator II = MBB->begin(), IE = MBB->end();
522 const MCInstrDesc &MCID = TM.getInstrInfo()->get(II->getOpcode());
523 if ((MCID.isCall() && !MCID.isReturn()) ||
524 II->isStackAligningInlineAsm()) {
525 MFI->setHasCalls(true);
527 if (II->isInlineAsm()) {
528 MF->setHasInlineAsm(true);
533 // Determine if there is a call to setjmp in the machine function.
534 MF->setExposesReturnsTwice(Fn.callsFunctionThatReturnsTwice());
536 // Replace forward-declared registers with the registers containing
537 // the desired value.
538 MachineRegisterInfo &MRI = MF->getRegInfo();
539 for (DenseMap<unsigned, unsigned>::iterator
540 I = FuncInfo->RegFixups.begin(), E = FuncInfo->RegFixups.end();
542 unsigned From = I->first;
543 unsigned To = I->second;
544 // If To is also scheduled to be replaced, find what its ultimate
547 DenseMap<unsigned, unsigned>::iterator J = FuncInfo->RegFixups.find(To);
551 // Make sure the new register has a sufficiently constrained register class.
552 if (TargetRegisterInfo::isVirtualRegister(From) &&
553 TargetRegisterInfo::isVirtualRegister(To))
554 MRI.constrainRegClass(To, MRI.getRegClass(From));
556 MRI.replaceRegWith(From, To);
559 // Freeze the set of reserved registers now that MachineFrameInfo has been
560 // set up. All the information required by getReservedRegs() should be
562 MRI.freezeReservedRegs(*MF);
564 // Release function-specific state. SDB and CurDAG are already cleared
568 DEBUG(dbgs() << "*** MachineFunction at end of ISel ***\n");
569 DEBUG(MF->print(dbgs()));
574 void SelectionDAGISel::SelectBasicBlock(BasicBlock::const_iterator Begin,
575 BasicBlock::const_iterator End,
577 // Lower all of the non-terminator instructions. If a call is emitted
578 // as a tail call, cease emitting nodes for this block. Terminators
579 // are handled below.
580 for (BasicBlock::const_iterator I = Begin; I != End && !SDB->HasTailCall; ++I)
583 // Make sure the root of the DAG is up-to-date.
584 CurDAG->setRoot(SDB->getControlRoot());
585 HadTailCall = SDB->HasTailCall;
588 // Final step, emit the lowered DAG as machine code.
592 void SelectionDAGISel::ComputeLiveOutVRegInfo() {
593 SmallPtrSet<SDNode*, 128> VisitedNodes;
594 SmallVector<SDNode*, 128> Worklist;
596 Worklist.push_back(CurDAG->getRoot().getNode());
602 SDNode *N = Worklist.pop_back_val();
604 // If we've already seen this node, ignore it.
605 if (!VisitedNodes.insert(N))
608 // Otherwise, add all chain operands to the worklist.
609 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
610 if (N->getOperand(i).getValueType() == MVT::Other)
611 Worklist.push_back(N->getOperand(i).getNode());
613 // If this is a CopyToReg with a vreg dest, process it.
614 if (N->getOpcode() != ISD::CopyToReg)
617 unsigned DestReg = cast<RegisterSDNode>(N->getOperand(1))->getReg();
618 if (!TargetRegisterInfo::isVirtualRegister(DestReg))
621 // Ignore non-scalar or non-integer values.
622 SDValue Src = N->getOperand(2);
623 EVT SrcVT = Src.getValueType();
624 if (!SrcVT.isInteger() || SrcVT.isVector())
627 unsigned NumSignBits = CurDAG->ComputeNumSignBits(Src);
628 CurDAG->ComputeMaskedBits(Src, KnownZero, KnownOne);
629 FuncInfo->AddLiveOutRegInfo(DestReg, NumSignBits, KnownZero, KnownOne);
630 } while (!Worklist.empty());
633 void SelectionDAGISel::CodeGenAndEmitDAG() {
634 std::string GroupName;
635 if (TimePassesIsEnabled)
636 GroupName = "Instruction Selection and Scheduling";
637 std::string BlockName;
638 int BlockNumber = -1;
641 if (ViewDAGCombine1 || ViewLegalizeTypesDAGs || ViewLegalizeDAGs ||
642 ViewDAGCombine2 || ViewDAGCombineLT || ViewISelDAGs || ViewSchedDAGs ||
646 BlockNumber = FuncInfo->MBB->getNumber();
647 BlockName = MF->getName().str() + ":" +
648 FuncInfo->MBB->getBasicBlock()->getName().str();
650 DEBUG(dbgs() << "Initial selection DAG: BB#" << BlockNumber
651 << " '" << BlockName << "'\n"; CurDAG->dump());
653 if (ViewDAGCombine1) CurDAG->viewGraph("dag-combine1 input for " + BlockName);
655 // Run the DAG combiner in pre-legalize mode.
657 NamedRegionTimer T("DAG Combining 1", GroupName, TimePassesIsEnabled);
658 CurDAG->Combine(BeforeLegalizeTypes, *AA, OptLevel);
661 DEBUG(dbgs() << "Optimized lowered selection DAG: BB#" << BlockNumber
662 << " '" << BlockName << "'\n"; CurDAG->dump());
664 // Second step, hack on the DAG until it only uses operations and types that
665 // the target supports.
666 if (ViewLegalizeTypesDAGs) CurDAG->viewGraph("legalize-types input for " +
671 NamedRegionTimer T("Type Legalization", GroupName, TimePassesIsEnabled);
672 Changed = CurDAG->LegalizeTypes();
675 DEBUG(dbgs() << "Type-legalized selection DAG: BB#" << BlockNumber
676 << " '" << BlockName << "'\n"; CurDAG->dump());
678 CurDAG->NewNodesMustHaveLegalTypes = true;
681 if (ViewDAGCombineLT)
682 CurDAG->viewGraph("dag-combine-lt input for " + BlockName);
684 // Run the DAG combiner in post-type-legalize mode.
686 NamedRegionTimer T("DAG Combining after legalize types", GroupName,
687 TimePassesIsEnabled);
688 CurDAG->Combine(AfterLegalizeTypes, *AA, OptLevel);
691 DEBUG(dbgs() << "Optimized type-legalized selection DAG: BB#" << BlockNumber
692 << " '" << BlockName << "'\n"; CurDAG->dump());
697 NamedRegionTimer T("Vector Legalization", GroupName, TimePassesIsEnabled);
698 Changed = CurDAG->LegalizeVectors();
703 NamedRegionTimer T("Type Legalization 2", GroupName, TimePassesIsEnabled);
704 CurDAG->LegalizeTypes();
707 if (ViewDAGCombineLT)
708 CurDAG->viewGraph("dag-combine-lv input for " + BlockName);
710 // Run the DAG combiner in post-type-legalize mode.
712 NamedRegionTimer T("DAG Combining after legalize vectors", GroupName,
713 TimePassesIsEnabled);
714 CurDAG->Combine(AfterLegalizeVectorOps, *AA, OptLevel);
717 DEBUG(dbgs() << "Optimized vector-legalized selection DAG: BB#"
718 << BlockNumber << " '" << BlockName << "'\n"; CurDAG->dump());
721 if (ViewLegalizeDAGs) CurDAG->viewGraph("legalize input for " + BlockName);
724 NamedRegionTimer T("DAG Legalization", GroupName, TimePassesIsEnabled);
728 DEBUG(dbgs() << "Legalized selection DAG: BB#" << BlockNumber
729 << " '" << BlockName << "'\n"; CurDAG->dump());
731 if (ViewDAGCombine2) CurDAG->viewGraph("dag-combine2 input for " + BlockName);
733 // Run the DAG combiner in post-legalize mode.
735 NamedRegionTimer T("DAG Combining 2", GroupName, TimePassesIsEnabled);
736 CurDAG->Combine(AfterLegalizeDAG, *AA, OptLevel);
739 DEBUG(dbgs() << "Optimized legalized selection DAG: BB#" << BlockNumber
740 << " '" << BlockName << "'\n"; CurDAG->dump());
742 if (OptLevel != CodeGenOpt::None)
743 ComputeLiveOutVRegInfo();
745 if (ViewISelDAGs) CurDAG->viewGraph("isel input for " + BlockName);
747 // Third, instruction select all of the operations to machine code, adding the
748 // code to the MachineBasicBlock.
750 NamedRegionTimer T("Instruction Selection", GroupName, TimePassesIsEnabled);
751 DoInstructionSelection();
754 DEBUG(dbgs() << "Selected selection DAG: BB#" << BlockNumber
755 << " '" << BlockName << "'\n"; CurDAG->dump());
757 if (ViewSchedDAGs) CurDAG->viewGraph("scheduler input for " + BlockName);
759 // Schedule machine code.
760 ScheduleDAGSDNodes *Scheduler = CreateScheduler();
762 NamedRegionTimer T("Instruction Scheduling", GroupName,
763 TimePassesIsEnabled);
764 Scheduler->Run(CurDAG, FuncInfo->MBB);
767 if (ViewSUnitDAGs) Scheduler->viewGraph();
769 // Emit machine code to BB. This can change 'BB' to the last block being
771 MachineBasicBlock *FirstMBB = FuncInfo->MBB, *LastMBB;
773 NamedRegionTimer T("Instruction Creation", GroupName, TimePassesIsEnabled);
775 // FuncInfo->InsertPt is passed by reference and set to the end of the
776 // scheduled instructions.
777 LastMBB = FuncInfo->MBB = Scheduler->EmitSchedule(FuncInfo->InsertPt);
780 // If the block was split, make sure we update any references that are used to
781 // update PHI nodes later on.
782 if (FirstMBB != LastMBB)
783 SDB->UpdateSplitBlock(FirstMBB, LastMBB);
785 // Free the scheduler state.
787 NamedRegionTimer T("Instruction Scheduling Cleanup", GroupName,
788 TimePassesIsEnabled);
792 // Free the SelectionDAG state, now that we're finished with it.
797 /// ISelUpdater - helper class to handle updates of the instruction selection
799 class ISelUpdater : public SelectionDAG::DAGUpdateListener {
800 SelectionDAG::allnodes_iterator &ISelPosition;
802 ISelUpdater(SelectionDAG &DAG, SelectionDAG::allnodes_iterator &isp)
803 : SelectionDAG::DAGUpdateListener(DAG), ISelPosition(isp) {}
805 /// NodeDeleted - Handle nodes deleted from the graph. If the node being
806 /// deleted is the current ISelPosition node, update ISelPosition.
808 void NodeDeleted(SDNode *N, SDNode *E) override {
809 if (ISelPosition == SelectionDAG::allnodes_iterator(N))
813 } // end anonymous namespace
815 void SelectionDAGISel::DoInstructionSelection() {
816 DEBUG(dbgs() << "===== Instruction selection begins: BB#"
817 << FuncInfo->MBB->getNumber()
818 << " '" << FuncInfo->MBB->getName() << "'\n");
822 // Select target instructions for the DAG.
824 // Number all nodes with a topological order and set DAGSize.
825 DAGSize = CurDAG->AssignTopologicalOrder();
827 // Create a dummy node (which is not added to allnodes), that adds
828 // a reference to the root node, preventing it from being deleted,
829 // and tracking any changes of the root.
830 HandleSDNode Dummy(CurDAG->getRoot());
831 SelectionDAG::allnodes_iterator ISelPosition (CurDAG->getRoot().getNode());
834 // Make sure that ISelPosition gets properly updated when nodes are deleted
835 // in calls made from this function.
836 ISelUpdater ISU(*CurDAG, ISelPosition);
838 // The AllNodes list is now topological-sorted. Visit the
839 // nodes by starting at the end of the list (the root of the
840 // graph) and preceding back toward the beginning (the entry
842 while (ISelPosition != CurDAG->allnodes_begin()) {
843 SDNode *Node = --ISelPosition;
844 // Skip dead nodes. DAGCombiner is expected to eliminate all dead nodes,
845 // but there are currently some corner cases that it misses. Also, this
846 // makes it theoretically possible to disable the DAGCombiner.
847 if (Node->use_empty())
850 SDNode *ResNode = Select(Node);
852 // FIXME: This is pretty gross. 'Select' should be changed to not return
853 // anything at all and this code should be nuked with a tactical strike.
855 // If node should not be replaced, continue with the next one.
856 if (ResNode == Node || Node->getOpcode() == ISD::DELETED_NODE)
860 ReplaceUses(Node, ResNode);
863 // If after the replacement this node is not used any more,
864 // remove this dead node.
865 if (Node->use_empty()) // Don't delete EntryToken, etc.
866 CurDAG->RemoveDeadNode(Node);
869 CurDAG->setRoot(Dummy.getValue());
872 DEBUG(dbgs() << "===== Instruction selection ends:\n");
874 PostprocessISelDAG();
877 /// PrepareEHLandingPad - Emit an EH_LABEL, set up live-in registers, and
878 /// do other setup for EH landing-pad blocks.
879 void SelectionDAGISel::PrepareEHLandingPad() {
880 MachineBasicBlock *MBB = FuncInfo->MBB;
882 // Add a label to mark the beginning of the landing pad. Deletion of the
883 // landing pad can thus be detected via the MachineModuleInfo.
884 MCSymbol *Label = MF->getMMI().addLandingPad(MBB);
886 // Assign the call site to the landing pad's begin label.
887 MF->getMMI().setCallSiteLandingPad(Label, SDB->LPadToCallSiteMap[MBB]);
889 const MCInstrDesc &II = TM.getInstrInfo()->get(TargetOpcode::EH_LABEL);
890 BuildMI(*MBB, FuncInfo->InsertPt, SDB->getCurDebugLoc(), II)
893 // Mark exception register as live in.
894 const TargetLowering *TLI = getTargetLowering();
895 const TargetRegisterClass *PtrRC = TLI->getRegClassFor(TLI->getPointerTy());
896 if (unsigned Reg = TLI->getExceptionPointerRegister())
897 FuncInfo->ExceptionPointerVirtReg = MBB->addLiveIn(Reg, PtrRC);
899 // Mark exception selector register as live in.
900 if (unsigned Reg = TLI->getExceptionSelectorRegister())
901 FuncInfo->ExceptionSelectorVirtReg = MBB->addLiveIn(Reg, PtrRC);
904 /// isFoldedOrDeadInstruction - Return true if the specified instruction is
905 /// side-effect free and is either dead or folded into a generated instruction.
906 /// Return false if it needs to be emitted.
907 static bool isFoldedOrDeadInstruction(const Instruction *I,
908 FunctionLoweringInfo *FuncInfo) {
909 return !I->mayWriteToMemory() && // Side-effecting instructions aren't folded.
910 !isa<TerminatorInst>(I) && // Terminators aren't folded.
911 !isa<DbgInfoIntrinsic>(I) && // Debug instructions aren't folded.
912 !isa<LandingPadInst>(I) && // Landingpad instructions aren't folded.
913 !FuncInfo->isExportedInst(I); // Exported instrs must be computed.
917 // Collect per Instruction statistics for fast-isel misses. Only those
918 // instructions that cause the bail are accounted for. It does not account for
919 // instructions higher in the block. Thus, summing the per instructions stats
920 // will not add up to what is reported by NumFastIselFailures.
921 static void collectFailStats(const Instruction *I) {
922 switch (I->getOpcode()) {
923 default: assert (0 && "<Invalid operator> ");
926 case Instruction::Ret: NumFastIselFailRet++; return;
927 case Instruction::Br: NumFastIselFailBr++; return;
928 case Instruction::Switch: NumFastIselFailSwitch++; return;
929 case Instruction::IndirectBr: NumFastIselFailIndirectBr++; return;
930 case Instruction::Invoke: NumFastIselFailInvoke++; return;
931 case Instruction::Resume: NumFastIselFailResume++; return;
932 case Instruction::Unreachable: NumFastIselFailUnreachable++; return;
934 // Standard binary operators...
935 case Instruction::Add: NumFastIselFailAdd++; return;
936 case Instruction::FAdd: NumFastIselFailFAdd++; return;
937 case Instruction::Sub: NumFastIselFailSub++; return;
938 case Instruction::FSub: NumFastIselFailFSub++; return;
939 case Instruction::Mul: NumFastIselFailMul++; return;
940 case Instruction::FMul: NumFastIselFailFMul++; return;
941 case Instruction::UDiv: NumFastIselFailUDiv++; return;
942 case Instruction::SDiv: NumFastIselFailSDiv++; return;
943 case Instruction::FDiv: NumFastIselFailFDiv++; return;
944 case Instruction::URem: NumFastIselFailURem++; return;
945 case Instruction::SRem: NumFastIselFailSRem++; return;
946 case Instruction::FRem: NumFastIselFailFRem++; return;
948 // Logical operators...
949 case Instruction::And: NumFastIselFailAnd++; return;
950 case Instruction::Or: NumFastIselFailOr++; return;
951 case Instruction::Xor: NumFastIselFailXor++; return;
953 // Memory instructions...
954 case Instruction::Alloca: NumFastIselFailAlloca++; return;
955 case Instruction::Load: NumFastIselFailLoad++; return;
956 case Instruction::Store: NumFastIselFailStore++; return;
957 case Instruction::AtomicCmpXchg: NumFastIselFailAtomicCmpXchg++; return;
958 case Instruction::AtomicRMW: NumFastIselFailAtomicRMW++; return;
959 case Instruction::Fence: NumFastIselFailFence++; return;
960 case Instruction::GetElementPtr: NumFastIselFailGetElementPtr++; return;
962 // Convert instructions...
963 case Instruction::Trunc: NumFastIselFailTrunc++; return;
964 case Instruction::ZExt: NumFastIselFailZExt++; return;
965 case Instruction::SExt: NumFastIselFailSExt++; return;
966 case Instruction::FPTrunc: NumFastIselFailFPTrunc++; return;
967 case Instruction::FPExt: NumFastIselFailFPExt++; return;
968 case Instruction::FPToUI: NumFastIselFailFPToUI++; return;
969 case Instruction::FPToSI: NumFastIselFailFPToSI++; return;
970 case Instruction::UIToFP: NumFastIselFailUIToFP++; return;
971 case Instruction::SIToFP: NumFastIselFailSIToFP++; return;
972 case Instruction::IntToPtr: NumFastIselFailIntToPtr++; return;
973 case Instruction::PtrToInt: NumFastIselFailPtrToInt++; return;
974 case Instruction::BitCast: NumFastIselFailBitCast++; return;
976 // Other instructions...
977 case Instruction::ICmp: NumFastIselFailICmp++; return;
978 case Instruction::FCmp: NumFastIselFailFCmp++; return;
979 case Instruction::PHI: NumFastIselFailPHI++; return;
980 case Instruction::Select: NumFastIselFailSelect++; return;
981 case Instruction::Call: NumFastIselFailCall++; return;
982 case Instruction::Shl: NumFastIselFailShl++; return;
983 case Instruction::LShr: NumFastIselFailLShr++; return;
984 case Instruction::AShr: NumFastIselFailAShr++; return;
985 case Instruction::VAArg: NumFastIselFailVAArg++; return;
986 case Instruction::ExtractElement: NumFastIselFailExtractElement++; return;
987 case Instruction::InsertElement: NumFastIselFailInsertElement++; return;
988 case Instruction::ShuffleVector: NumFastIselFailShuffleVector++; return;
989 case Instruction::ExtractValue: NumFastIselFailExtractValue++; return;
990 case Instruction::InsertValue: NumFastIselFailInsertValue++; return;
991 case Instruction::LandingPad: NumFastIselFailLandingPad++; return;
996 void SelectionDAGISel::SelectAllBasicBlocks(const Function &Fn) {
997 // Initialize the Fast-ISel state, if needed.
998 FastISel *FastIS = nullptr;
999 if (TM.Options.EnableFastISel)
1000 FastIS = getTargetLowering()->createFastISel(*FuncInfo, LibInfo);
1002 // Iterate over all basic blocks in the function.
1003 ReversePostOrderTraversal<const Function*> RPOT(&Fn);
1004 for (ReversePostOrderTraversal<const Function*>::rpo_iterator
1005 I = RPOT.begin(), E = RPOT.end(); I != E; ++I) {
1006 const BasicBlock *LLVMBB = *I;
1008 if (OptLevel != CodeGenOpt::None) {
1009 bool AllPredsVisited = true;
1010 for (const_pred_iterator PI = pred_begin(LLVMBB), PE = pred_end(LLVMBB);
1012 if (!FuncInfo->VisitedBBs.count(*PI)) {
1013 AllPredsVisited = false;
1018 if (AllPredsVisited) {
1019 for (BasicBlock::const_iterator I = LLVMBB->begin();
1020 const PHINode *PN = dyn_cast<PHINode>(I); ++I)
1021 FuncInfo->ComputePHILiveOutRegInfo(PN);
1023 for (BasicBlock::const_iterator I = LLVMBB->begin();
1024 const PHINode *PN = dyn_cast<PHINode>(I); ++I)
1025 FuncInfo->InvalidatePHILiveOutRegInfo(PN);
1028 FuncInfo->VisitedBBs.insert(LLVMBB);
1031 BasicBlock::const_iterator const Begin = LLVMBB->getFirstNonPHI();
1032 BasicBlock::const_iterator const End = LLVMBB->end();
1033 BasicBlock::const_iterator BI = End;
1035 FuncInfo->MBB = FuncInfo->MBBMap[LLVMBB];
1036 FuncInfo->InsertPt = FuncInfo->MBB->getFirstNonPHI();
1038 // Setup an EH landing-pad block.
1039 FuncInfo->ExceptionPointerVirtReg = 0;
1040 FuncInfo->ExceptionSelectorVirtReg = 0;
1041 if (FuncInfo->MBB->isLandingPad())
1042 PrepareEHLandingPad();
1044 // Before doing SelectionDAG ISel, see if FastISel has been requested.
1046 FastIS->startNewBlock();
1048 // Emit code for any incoming arguments. This must happen before
1049 // beginning FastISel on the entry block.
1050 if (LLVMBB == &Fn.getEntryBlock()) {
1053 // Lower any arguments needed in this block if this is the entry block.
1054 if (!FastIS->LowerArguments()) {
1055 // Fast isel failed to lower these arguments
1056 ++NumFastIselFailLowerArguments;
1057 if (EnableFastISelAbortArgs)
1058 llvm_unreachable("FastISel didn't lower all arguments");
1060 // Use SelectionDAG argument lowering
1062 CurDAG->setRoot(SDB->getControlRoot());
1064 CodeGenAndEmitDAG();
1067 // If we inserted any instructions at the beginning, make a note of
1068 // where they are, so we can be sure to emit subsequent instructions
1070 if (FuncInfo->InsertPt != FuncInfo->MBB->begin())
1071 FastIS->setLastLocalValue(std::prev(FuncInfo->InsertPt));
1073 FastIS->setLastLocalValue(nullptr);
1076 unsigned NumFastIselRemaining = std::distance(Begin, End);
1077 // Do FastISel on as many instructions as possible.
1078 for (; BI != Begin; --BI) {
1079 const Instruction *Inst = std::prev(BI);
1081 // If we no longer require this instruction, skip it.
1082 if (isFoldedOrDeadInstruction(Inst, FuncInfo)) {
1083 --NumFastIselRemaining;
1087 // Bottom-up: reset the insert pos at the top, after any local-value
1089 FastIS->recomputeInsertPt();
1091 // Try to select the instruction with FastISel.
1092 if (FastIS->SelectInstruction(Inst)) {
1093 --NumFastIselRemaining;
1094 ++NumFastIselSuccess;
1095 // If fast isel succeeded, skip over all the folded instructions, and
1096 // then see if there is a load right before the selected instructions.
1097 // Try to fold the load if so.
1098 const Instruction *BeforeInst = Inst;
1099 while (BeforeInst != Begin) {
1100 BeforeInst = std::prev(BasicBlock::const_iterator(BeforeInst));
1101 if (!isFoldedOrDeadInstruction(BeforeInst, FuncInfo))
1104 if (BeforeInst != Inst && isa<LoadInst>(BeforeInst) &&
1105 BeforeInst->hasOneUse() &&
1106 FastIS->tryToFoldLoad(cast<LoadInst>(BeforeInst), Inst)) {
1107 // If we succeeded, don't re-select the load.
1108 BI = std::next(BasicBlock::const_iterator(BeforeInst));
1109 --NumFastIselRemaining;
1110 ++NumFastIselSuccess;
1116 if (EnableFastISelVerbose2)
1117 collectFailStats(Inst);
1120 // Then handle certain instructions as single-LLVM-Instruction blocks.
1121 if (isa<CallInst>(Inst)) {
1123 if (EnableFastISelVerbose || EnableFastISelAbort) {
1124 dbgs() << "FastISel missed call: ";
1128 if (!Inst->getType()->isVoidTy() && !Inst->use_empty()) {
1129 unsigned &R = FuncInfo->ValueMap[Inst];
1131 R = FuncInfo->CreateRegs(Inst->getType());
1134 bool HadTailCall = false;
1135 MachineBasicBlock::iterator SavedInsertPt = FuncInfo->InsertPt;
1136 SelectBasicBlock(Inst, BI, HadTailCall);
1138 // If the call was emitted as a tail call, we're done with the block.
1139 // We also need to delete any previously emitted instructions.
1141 FastIS->removeDeadCode(SavedInsertPt, FuncInfo->MBB->end());
1146 // Recompute NumFastIselRemaining as Selection DAG instruction
1147 // selection may have handled the call, input args, etc.
1148 unsigned RemainingNow = std::distance(Begin, BI);
1149 NumFastIselFailures += NumFastIselRemaining - RemainingNow;
1150 NumFastIselRemaining = RemainingNow;
1154 if (isa<TerminatorInst>(Inst) && !isa<BranchInst>(Inst)) {
1155 // Don't abort, and use a different message for terminator misses.
1156 NumFastIselFailures += NumFastIselRemaining;
1157 if (EnableFastISelVerbose || EnableFastISelAbort) {
1158 dbgs() << "FastISel missed terminator: ";
1162 NumFastIselFailures += NumFastIselRemaining;
1163 if (EnableFastISelVerbose || EnableFastISelAbort) {
1164 dbgs() << "FastISel miss: ";
1167 if (EnableFastISelAbort)
1168 // The "fast" selector couldn't handle something and bailed.
1169 // For the purpose of debugging, just abort.
1170 llvm_unreachable("FastISel didn't select the entire block");
1175 FastIS->recomputeInsertPt();
1177 // Lower any arguments needed in this block if this is the entry block.
1178 if (LLVMBB == &Fn.getEntryBlock()) {
1187 ++NumFastIselBlocks;
1190 // Run SelectionDAG instruction selection on the remainder of the block
1191 // not handled by FastISel. If FastISel is not run, this is the entire
1194 SelectBasicBlock(Begin, BI, HadTailCall);
1198 FuncInfo->PHINodesToUpdate.clear();
1202 SDB->clearDanglingDebugInfo();
1203 SDB->SPDescriptor.resetPerFunctionState();
1206 /// Given that the input MI is before a partial terminator sequence TSeq, return
1207 /// true if M + TSeq also a partial terminator sequence.
1209 /// A Terminator sequence is a sequence of MachineInstrs which at this point in
1210 /// lowering copy vregs into physical registers, which are then passed into
1211 /// terminator instructors so we can satisfy ABI constraints. A partial
1212 /// terminator sequence is an improper subset of a terminator sequence (i.e. it
1213 /// may be the whole terminator sequence).
1214 static bool MIIsInTerminatorSequence(const MachineInstr *MI) {
1215 // If we do not have a copy or an implicit def, we return true if and only if
1216 // MI is a debug value.
1217 if (!MI->isCopy() && !MI->isImplicitDef())
1218 // Sometimes DBG_VALUE MI sneak in between the copies from the vregs to the
1219 // physical registers if there is debug info associated with the terminator
1220 // of our mbb. We want to include said debug info in our terminator
1221 // sequence, so we return true in that case.
1222 return MI->isDebugValue();
1224 // We have left the terminator sequence if we are not doing one of the
1227 // 1. Copying a vreg into a physical register.
1228 // 2. Copying a vreg into a vreg.
1229 // 3. Defining a register via an implicit def.
1231 // OPI should always be a register definition...
1232 MachineInstr::const_mop_iterator OPI = MI->operands_begin();
1233 if (!OPI->isReg() || !OPI->isDef())
1236 // Defining any register via an implicit def is always ok.
1237 if (MI->isImplicitDef())
1240 // Grab the copy source...
1241 MachineInstr::const_mop_iterator OPI2 = OPI;
1243 assert(OPI2 != MI->operands_end()
1244 && "Should have a copy implying we should have 2 arguments.");
1246 // Make sure that the copy dest is not a vreg when the copy source is a
1247 // physical register.
1248 if (!OPI2->isReg() ||
1249 (!TargetRegisterInfo::isPhysicalRegister(OPI->getReg()) &&
1250 TargetRegisterInfo::isPhysicalRegister(OPI2->getReg())))
1256 /// Find the split point at which to splice the end of BB into its success stack
1257 /// protector check machine basic block.
1259 /// On many platforms, due to ABI constraints, terminators, even before register
1260 /// allocation, use physical registers. This creates an issue for us since
1261 /// physical registers at this point can not travel across basic
1262 /// blocks. Luckily, selectiondag always moves physical registers into vregs
1263 /// when they enter functions and moves them through a sequence of copies back
1264 /// into the physical registers right before the terminator creating a
1265 /// ``Terminator Sequence''. This function is searching for the beginning of the
1266 /// terminator sequence so that we can ensure that we splice off not just the
1267 /// terminator, but additionally the copies that move the vregs into the
1268 /// physical registers.
1269 static MachineBasicBlock::iterator
1270 FindSplitPointForStackProtector(MachineBasicBlock *BB, DebugLoc DL) {
1271 MachineBasicBlock::iterator SplitPoint = BB->getFirstTerminator();
1273 if (SplitPoint == BB->begin())
1276 MachineBasicBlock::iterator Start = BB->begin();
1277 MachineBasicBlock::iterator Previous = SplitPoint;
1280 while (MIIsInTerminatorSequence(Previous)) {
1281 SplitPoint = Previous;
1282 if (Previous == Start)
1291 SelectionDAGISel::FinishBasicBlock() {
1293 DEBUG(dbgs() << "Total amount of phi nodes to update: "
1294 << FuncInfo->PHINodesToUpdate.size() << "\n";
1295 for (unsigned i = 0, e = FuncInfo->PHINodesToUpdate.size(); i != e; ++i)
1296 dbgs() << "Node " << i << " : ("
1297 << FuncInfo->PHINodesToUpdate[i].first
1298 << ", " << FuncInfo->PHINodesToUpdate[i].second << ")\n");
1300 const bool MustUpdatePHINodes = SDB->SwitchCases.empty() &&
1301 SDB->JTCases.empty() &&
1302 SDB->BitTestCases.empty();
1304 // Next, now that we know what the last MBB the LLVM BB expanded is, update
1305 // PHI nodes in successors.
1306 if (MustUpdatePHINodes) {
1307 for (unsigned i = 0, e = FuncInfo->PHINodesToUpdate.size(); i != e; ++i) {
1308 MachineInstrBuilder PHI(*MF, FuncInfo->PHINodesToUpdate[i].first);
1309 assert(PHI->isPHI() &&
1310 "This is not a machine PHI node that we are updating!");
1311 if (!FuncInfo->MBB->isSuccessor(PHI->getParent()))
1313 PHI.addReg(FuncInfo->PHINodesToUpdate[i].second).addMBB(FuncInfo->MBB);
1317 // Handle stack protector.
1318 if (SDB->SPDescriptor.shouldEmitStackProtector()) {
1319 MachineBasicBlock *ParentMBB = SDB->SPDescriptor.getParentMBB();
1320 MachineBasicBlock *SuccessMBB = SDB->SPDescriptor.getSuccessMBB();
1322 // Find the split point to split the parent mbb. At the same time copy all
1323 // physical registers used in the tail of parent mbb into virtual registers
1324 // before the split point and back into physical registers after the split
1325 // point. This prevents us needing to deal with Live-ins and many other
1326 // register allocation issues caused by us splitting the parent mbb. The
1327 // register allocator will clean up said virtual copies later on.
1328 MachineBasicBlock::iterator SplitPoint =
1329 FindSplitPointForStackProtector(ParentMBB, SDB->getCurDebugLoc());
1331 // Splice the terminator of ParentMBB into SuccessMBB.
1332 SuccessMBB->splice(SuccessMBB->end(), ParentMBB,
1336 // Add compare/jump on neq/jump to the parent BB.
1337 FuncInfo->MBB = ParentMBB;
1338 FuncInfo->InsertPt = ParentMBB->end();
1339 SDB->visitSPDescriptorParent(SDB->SPDescriptor, ParentMBB);
1340 CurDAG->setRoot(SDB->getRoot());
1342 CodeGenAndEmitDAG();
1344 // CodeGen Failure MBB if we have not codegened it yet.
1345 MachineBasicBlock *FailureMBB = SDB->SPDescriptor.getFailureMBB();
1346 if (!FailureMBB->size()) {
1347 FuncInfo->MBB = FailureMBB;
1348 FuncInfo->InsertPt = FailureMBB->end();
1349 SDB->visitSPDescriptorFailure(SDB->SPDescriptor);
1350 CurDAG->setRoot(SDB->getRoot());
1352 CodeGenAndEmitDAG();
1355 // Clear the Per-BB State.
1356 SDB->SPDescriptor.resetPerBBState();
1359 // If we updated PHI Nodes, return early.
1360 if (MustUpdatePHINodes)
1363 for (unsigned i = 0, e = SDB->BitTestCases.size(); i != e; ++i) {
1364 // Lower header first, if it wasn't already lowered
1365 if (!SDB->BitTestCases[i].Emitted) {
1366 // Set the current basic block to the mbb we wish to insert the code into
1367 FuncInfo->MBB = SDB->BitTestCases[i].Parent;
1368 FuncInfo->InsertPt = FuncInfo->MBB->end();
1370 SDB->visitBitTestHeader(SDB->BitTestCases[i], FuncInfo->MBB);
1371 CurDAG->setRoot(SDB->getRoot());
1373 CodeGenAndEmitDAG();
1376 uint32_t UnhandledWeight = 0;
1377 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size(); j != ej; ++j)
1378 UnhandledWeight += SDB->BitTestCases[i].Cases[j].ExtraWeight;
1380 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size(); j != ej; ++j) {
1381 UnhandledWeight -= SDB->BitTestCases[i].Cases[j].ExtraWeight;
1382 // Set the current basic block to the mbb we wish to insert the code into
1383 FuncInfo->MBB = SDB->BitTestCases[i].Cases[j].ThisBB;
1384 FuncInfo->InsertPt = FuncInfo->MBB->end();
1387 SDB->visitBitTestCase(SDB->BitTestCases[i],
1388 SDB->BitTestCases[i].Cases[j+1].ThisBB,
1390 SDB->BitTestCases[i].Reg,
1391 SDB->BitTestCases[i].Cases[j],
1394 SDB->visitBitTestCase(SDB->BitTestCases[i],
1395 SDB->BitTestCases[i].Default,
1397 SDB->BitTestCases[i].Reg,
1398 SDB->BitTestCases[i].Cases[j],
1402 CurDAG->setRoot(SDB->getRoot());
1404 CodeGenAndEmitDAG();
1408 for (unsigned pi = 0, pe = FuncInfo->PHINodesToUpdate.size();
1410 MachineInstrBuilder PHI(*MF, FuncInfo->PHINodesToUpdate[pi].first);
1411 MachineBasicBlock *PHIBB = PHI->getParent();
1412 assert(PHI->isPHI() &&
1413 "This is not a machine PHI node that we are updating!");
1414 // This is "default" BB. We have two jumps to it. From "header" BB and
1415 // from last "case" BB.
1416 if (PHIBB == SDB->BitTestCases[i].Default)
1417 PHI.addReg(FuncInfo->PHINodesToUpdate[pi].second)
1418 .addMBB(SDB->BitTestCases[i].Parent)
1419 .addReg(FuncInfo->PHINodesToUpdate[pi].second)
1420 .addMBB(SDB->BitTestCases[i].Cases.back().ThisBB);
1421 // One of "cases" BB.
1422 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size();
1424 MachineBasicBlock* cBB = SDB->BitTestCases[i].Cases[j].ThisBB;
1425 if (cBB->isSuccessor(PHIBB))
1426 PHI.addReg(FuncInfo->PHINodesToUpdate[pi].second).addMBB(cBB);
1430 SDB->BitTestCases.clear();
1432 // If the JumpTable record is filled in, then we need to emit a jump table.
1433 // Updating the PHI nodes is tricky in this case, since we need to determine
1434 // whether the PHI is a successor of the range check MBB or the jump table MBB
1435 for (unsigned i = 0, e = SDB->JTCases.size(); i != e; ++i) {
1436 // Lower header first, if it wasn't already lowered
1437 if (!SDB->JTCases[i].first.Emitted) {
1438 // Set the current basic block to the mbb we wish to insert the code into
1439 FuncInfo->MBB = SDB->JTCases[i].first.HeaderBB;
1440 FuncInfo->InsertPt = FuncInfo->MBB->end();
1442 SDB->visitJumpTableHeader(SDB->JTCases[i].second, SDB->JTCases[i].first,
1444 CurDAG->setRoot(SDB->getRoot());
1446 CodeGenAndEmitDAG();
1449 // Set the current basic block to the mbb we wish to insert the code into
1450 FuncInfo->MBB = SDB->JTCases[i].second.MBB;
1451 FuncInfo->InsertPt = FuncInfo->MBB->end();
1453 SDB->visitJumpTable(SDB->JTCases[i].second);
1454 CurDAG->setRoot(SDB->getRoot());
1456 CodeGenAndEmitDAG();
1459 for (unsigned pi = 0, pe = FuncInfo->PHINodesToUpdate.size();
1461 MachineInstrBuilder PHI(*MF, FuncInfo->PHINodesToUpdate[pi].first);
1462 MachineBasicBlock *PHIBB = PHI->getParent();
1463 assert(PHI->isPHI() &&
1464 "This is not a machine PHI node that we are updating!");
1465 // "default" BB. We can go there only from header BB.
1466 if (PHIBB == SDB->JTCases[i].second.Default)
1467 PHI.addReg(FuncInfo->PHINodesToUpdate[pi].second)
1468 .addMBB(SDB->JTCases[i].first.HeaderBB);
1469 // JT BB. Just iterate over successors here
1470 if (FuncInfo->MBB->isSuccessor(PHIBB))
1471 PHI.addReg(FuncInfo->PHINodesToUpdate[pi].second).addMBB(FuncInfo->MBB);
1474 SDB->JTCases.clear();
1476 // If the switch block involved a branch to one of the actual successors, we
1477 // need to update PHI nodes in that block.
1478 for (unsigned i = 0, e = FuncInfo->PHINodesToUpdate.size(); i != e; ++i) {
1479 MachineInstrBuilder PHI(*MF, FuncInfo->PHINodesToUpdate[i].first);
1480 assert(PHI->isPHI() &&
1481 "This is not a machine PHI node that we are updating!");
1482 if (FuncInfo->MBB->isSuccessor(PHI->getParent()))
1483 PHI.addReg(FuncInfo->PHINodesToUpdate[i].second).addMBB(FuncInfo->MBB);
1486 // If we generated any switch lowering information, build and codegen any
1487 // additional DAGs necessary.
1488 for (unsigned i = 0, e = SDB->SwitchCases.size(); i != e; ++i) {
1489 // Set the current basic block to the mbb we wish to insert the code into
1490 FuncInfo->MBB = SDB->SwitchCases[i].ThisBB;
1491 FuncInfo->InsertPt = FuncInfo->MBB->end();
1493 // Determine the unique successors.
1494 SmallVector<MachineBasicBlock *, 2> Succs;
1495 Succs.push_back(SDB->SwitchCases[i].TrueBB);
1496 if (SDB->SwitchCases[i].TrueBB != SDB->SwitchCases[i].FalseBB)
1497 Succs.push_back(SDB->SwitchCases[i].FalseBB);
1499 // Emit the code. Note that this could result in FuncInfo->MBB being split.
1500 SDB->visitSwitchCase(SDB->SwitchCases[i], FuncInfo->MBB);
1501 CurDAG->setRoot(SDB->getRoot());
1503 CodeGenAndEmitDAG();
1505 // Remember the last block, now that any splitting is done, for use in
1506 // populating PHI nodes in successors.
1507 MachineBasicBlock *ThisBB = FuncInfo->MBB;
1509 // Handle any PHI nodes in successors of this chunk, as if we were coming
1510 // from the original BB before switch expansion. Note that PHI nodes can
1511 // occur multiple times in PHINodesToUpdate. We have to be very careful to
1512 // handle them the right number of times.
1513 for (unsigned i = 0, e = Succs.size(); i != e; ++i) {
1514 FuncInfo->MBB = Succs[i];
1515 FuncInfo->InsertPt = FuncInfo->MBB->end();
1516 // FuncInfo->MBB may have been removed from the CFG if a branch was
1518 if (ThisBB->isSuccessor(FuncInfo->MBB)) {
1519 for (MachineBasicBlock::iterator
1520 MBBI = FuncInfo->MBB->begin(), MBBE = FuncInfo->MBB->end();
1521 MBBI != MBBE && MBBI->isPHI(); ++MBBI) {
1522 MachineInstrBuilder PHI(*MF, MBBI);
1523 // This value for this PHI node is recorded in PHINodesToUpdate.
1524 for (unsigned pn = 0; ; ++pn) {
1525 assert(pn != FuncInfo->PHINodesToUpdate.size() &&
1526 "Didn't find PHI entry!");
1527 if (FuncInfo->PHINodesToUpdate[pn].first == PHI) {
1528 PHI.addReg(FuncInfo->PHINodesToUpdate[pn].second).addMBB(ThisBB);
1536 SDB->SwitchCases.clear();
1540 /// Create the scheduler. If a specific scheduler was specified
1541 /// via the SchedulerRegistry, use it, otherwise select the
1542 /// one preferred by the target.
1544 ScheduleDAGSDNodes *SelectionDAGISel::CreateScheduler() {
1545 RegisterScheduler::FunctionPassCtor Ctor = RegisterScheduler::getDefault();
1549 RegisterScheduler::setDefault(Ctor);
1552 return Ctor(this, OptLevel);
1555 //===----------------------------------------------------------------------===//
1556 // Helper functions used by the generated instruction selector.
1557 //===----------------------------------------------------------------------===//
1558 // Calls to these methods are generated by tblgen.
1560 /// CheckAndMask - The isel is trying to match something like (and X, 255). If
1561 /// the dag combiner simplified the 255, we still want to match. RHS is the
1562 /// actual value in the DAG on the RHS of an AND, and DesiredMaskS is the value
1563 /// specified in the .td file (e.g. 255).
1564 bool SelectionDAGISel::CheckAndMask(SDValue LHS, ConstantSDNode *RHS,
1565 int64_t DesiredMaskS) const {
1566 const APInt &ActualMask = RHS->getAPIntValue();
1567 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS);
1569 // If the actual mask exactly matches, success!
1570 if (ActualMask == DesiredMask)
1573 // If the actual AND mask is allowing unallowed bits, this doesn't match.
1574 if (ActualMask.intersects(~DesiredMask))
1577 // Otherwise, the DAG Combiner may have proven that the value coming in is
1578 // either already zero or is not demanded. Check for known zero input bits.
1579 APInt NeededMask = DesiredMask & ~ActualMask;
1580 if (CurDAG->MaskedValueIsZero(LHS, NeededMask))
1583 // TODO: check to see if missing bits are just not demanded.
1585 // Otherwise, this pattern doesn't match.
1589 /// CheckOrMask - The isel is trying to match something like (or X, 255). If
1590 /// the dag combiner simplified the 255, we still want to match. RHS is the
1591 /// actual value in the DAG on the RHS of an OR, and DesiredMaskS is the value
1592 /// specified in the .td file (e.g. 255).
1593 bool SelectionDAGISel::CheckOrMask(SDValue LHS, ConstantSDNode *RHS,
1594 int64_t DesiredMaskS) const {
1595 const APInt &ActualMask = RHS->getAPIntValue();
1596 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS);
1598 // If the actual mask exactly matches, success!
1599 if (ActualMask == DesiredMask)
1602 // If the actual AND mask is allowing unallowed bits, this doesn't match.
1603 if (ActualMask.intersects(~DesiredMask))
1606 // Otherwise, the DAG Combiner may have proven that the value coming in is
1607 // either already zero or is not demanded. Check for known zero input bits.
1608 APInt NeededMask = DesiredMask & ~ActualMask;
1610 APInt KnownZero, KnownOne;
1611 CurDAG->ComputeMaskedBits(LHS, KnownZero, KnownOne);
1613 // If all the missing bits in the or are already known to be set, match!
1614 if ((NeededMask & KnownOne) == NeededMask)
1617 // TODO: check to see if missing bits are just not demanded.
1619 // Otherwise, this pattern doesn't match.
1624 /// SelectInlineAsmMemoryOperands - Calls to this are automatically generated
1625 /// by tblgen. Others should not call it.
1626 void SelectionDAGISel::
1627 SelectInlineAsmMemoryOperands(std::vector<SDValue> &Ops) {
1628 std::vector<SDValue> InOps;
1629 std::swap(InOps, Ops);
1631 Ops.push_back(InOps[InlineAsm::Op_InputChain]); // 0
1632 Ops.push_back(InOps[InlineAsm::Op_AsmString]); // 1
1633 Ops.push_back(InOps[InlineAsm::Op_MDNode]); // 2, !srcloc
1634 Ops.push_back(InOps[InlineAsm::Op_ExtraInfo]); // 3 (SideEffect, AlignStack)
1636 unsigned i = InlineAsm::Op_FirstOperand, e = InOps.size();
1637 if (InOps[e-1].getValueType() == MVT::Glue)
1638 --e; // Don't process a glue operand if it is here.
1641 unsigned Flags = cast<ConstantSDNode>(InOps[i])->getZExtValue();
1642 if (!InlineAsm::isMemKind(Flags)) {
1643 // Just skip over this operand, copying the operands verbatim.
1644 Ops.insert(Ops.end(), InOps.begin()+i,
1645 InOps.begin()+i+InlineAsm::getNumOperandRegisters(Flags) + 1);
1646 i += InlineAsm::getNumOperandRegisters(Flags) + 1;
1648 assert(InlineAsm::getNumOperandRegisters(Flags) == 1 &&
1649 "Memory operand with multiple values?");
1650 // Otherwise, this is a memory operand. Ask the target to select it.
1651 std::vector<SDValue> SelOps;
1652 if (SelectInlineAsmMemoryOperand(InOps[i+1], 'm', SelOps))
1653 report_fatal_error("Could not match memory address. Inline asm"
1656 // Add this to the output node.
1658 InlineAsm::getFlagWord(InlineAsm::Kind_Mem, SelOps.size());
1659 Ops.push_back(CurDAG->getTargetConstant(NewFlags, MVT::i32));
1660 Ops.insert(Ops.end(), SelOps.begin(), SelOps.end());
1665 // Add the glue input back if present.
1666 if (e != InOps.size())
1667 Ops.push_back(InOps.back());
1670 /// findGlueUse - Return use of MVT::Glue value produced by the specified
1673 static SDNode *findGlueUse(SDNode *N) {
1674 unsigned FlagResNo = N->getNumValues()-1;
1675 for (SDNode::use_iterator I = N->use_begin(), E = N->use_end(); I != E; ++I) {
1676 SDUse &Use = I.getUse();
1677 if (Use.getResNo() == FlagResNo)
1678 return Use.getUser();
1683 /// findNonImmUse - Return true if "Use" is a non-immediate use of "Def".
1684 /// This function recursively traverses up the operand chain, ignoring
1686 static bool findNonImmUse(SDNode *Use, SDNode* Def, SDNode *ImmedUse,
1687 SDNode *Root, SmallPtrSet<SDNode*, 16> &Visited,
1688 bool IgnoreChains) {
1689 // The NodeID's are given uniques ID's where a node ID is guaranteed to be
1690 // greater than all of its (recursive) operands. If we scan to a point where
1691 // 'use' is smaller than the node we're scanning for, then we know we will
1694 // The Use may be -1 (unassigned) if it is a newly allocated node. This can
1695 // happen because we scan down to newly selected nodes in the case of glue
1697 if ((Use->getNodeId() < Def->getNodeId() && Use->getNodeId() != -1))
1700 // Don't revisit nodes if we already scanned it and didn't fail, we know we
1701 // won't fail if we scan it again.
1702 if (!Visited.insert(Use))
1705 for (unsigned i = 0, e = Use->getNumOperands(); i != e; ++i) {
1706 // Ignore chain uses, they are validated by HandleMergeInputChains.
1707 if (Use->getOperand(i).getValueType() == MVT::Other && IgnoreChains)
1710 SDNode *N = Use->getOperand(i).getNode();
1712 if (Use == ImmedUse || Use == Root)
1713 continue; // We are not looking for immediate use.
1718 // Traverse up the operand chain.
1719 if (findNonImmUse(N, Def, ImmedUse, Root, Visited, IgnoreChains))
1725 /// IsProfitableToFold - Returns true if it's profitable to fold the specific
1726 /// operand node N of U during instruction selection that starts at Root.
1727 bool SelectionDAGISel::IsProfitableToFold(SDValue N, SDNode *U,
1728 SDNode *Root) const {
1729 if (OptLevel == CodeGenOpt::None) return false;
1730 return N.hasOneUse();
1733 /// IsLegalToFold - Returns true if the specific operand node N of
1734 /// U can be folded during instruction selection that starts at Root.
1735 bool SelectionDAGISel::IsLegalToFold(SDValue N, SDNode *U, SDNode *Root,
1736 CodeGenOpt::Level OptLevel,
1737 bool IgnoreChains) {
1738 if (OptLevel == CodeGenOpt::None) return false;
1740 // If Root use can somehow reach N through a path that that doesn't contain
1741 // U then folding N would create a cycle. e.g. In the following
1742 // diagram, Root can reach N through X. If N is folded into into Root, then
1743 // X is both a predecessor and a successor of U.
1754 // * indicates nodes to be folded together.
1756 // If Root produces glue, then it gets (even more) interesting. Since it
1757 // will be "glued" together with its glue use in the scheduler, we need to
1758 // check if it might reach N.
1777 // If GU (glue use) indirectly reaches N (the load), and Root folds N
1778 // (call it Fold), then X is a predecessor of GU and a successor of
1779 // Fold. But since Fold and GU are glued together, this will create
1780 // a cycle in the scheduling graph.
1782 // If the node has glue, walk down the graph to the "lowest" node in the
1784 EVT VT = Root->getValueType(Root->getNumValues()-1);
1785 while (VT == MVT::Glue) {
1786 SDNode *GU = findGlueUse(Root);
1790 VT = Root->getValueType(Root->getNumValues()-1);
1792 // If our query node has a glue result with a use, we've walked up it. If
1793 // the user (which has already been selected) has a chain or indirectly uses
1794 // the chain, our WalkChainUsers predicate will not consider it. Because of
1795 // this, we cannot ignore chains in this predicate.
1796 IgnoreChains = false;
1800 SmallPtrSet<SDNode*, 16> Visited;
1801 return !findNonImmUse(Root, N.getNode(), U, Root, Visited, IgnoreChains);
1804 SDNode *SelectionDAGISel::Select_INLINEASM(SDNode *N) {
1805 std::vector<SDValue> Ops(N->op_begin(), N->op_end());
1806 SelectInlineAsmMemoryOperands(Ops);
1808 EVT VTs[] = { MVT::Other, MVT::Glue };
1809 SDValue New = CurDAG->getNode(ISD::INLINEASM, SDLoc(N),
1810 VTs, &Ops[0], Ops.size());
1812 return New.getNode();
1815 SDNode *SelectionDAGISel::Select_UNDEF(SDNode *N) {
1816 return CurDAG->SelectNodeTo(N, TargetOpcode::IMPLICIT_DEF,N->getValueType(0));
1819 /// GetVBR - decode a vbr encoding whose top bit is set.
1820 LLVM_ATTRIBUTE_ALWAYS_INLINE static uint64_t
1821 GetVBR(uint64_t Val, const unsigned char *MatcherTable, unsigned &Idx) {
1822 assert(Val >= 128 && "Not a VBR");
1823 Val &= 127; // Remove first vbr bit.
1828 NextBits = MatcherTable[Idx++];
1829 Val |= (NextBits&127) << Shift;
1831 } while (NextBits & 128);
1837 /// UpdateChainsAndGlue - When a match is complete, this method updates uses of
1838 /// interior glue and chain results to use the new glue and chain results.
1839 void SelectionDAGISel::
1840 UpdateChainsAndGlue(SDNode *NodeToMatch, SDValue InputChain,
1841 const SmallVectorImpl<SDNode*> &ChainNodesMatched,
1843 const SmallVectorImpl<SDNode*> &GlueResultNodesMatched,
1844 bool isMorphNodeTo) {
1845 SmallVector<SDNode*, 4> NowDeadNodes;
1847 // Now that all the normal results are replaced, we replace the chain and
1848 // glue results if present.
1849 if (!ChainNodesMatched.empty()) {
1850 assert(InputChain.getNode() &&
1851 "Matched input chains but didn't produce a chain");
1852 // Loop over all of the nodes we matched that produced a chain result.
1853 // Replace all the chain results with the final chain we ended up with.
1854 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) {
1855 SDNode *ChainNode = ChainNodesMatched[i];
1857 // If this node was already deleted, don't look at it.
1858 if (ChainNode->getOpcode() == ISD::DELETED_NODE)
1861 // Don't replace the results of the root node if we're doing a
1863 if (ChainNode == NodeToMatch && isMorphNodeTo)
1866 SDValue ChainVal = SDValue(ChainNode, ChainNode->getNumValues()-1);
1867 if (ChainVal.getValueType() == MVT::Glue)
1868 ChainVal = ChainVal.getValue(ChainVal->getNumValues()-2);
1869 assert(ChainVal.getValueType() == MVT::Other && "Not a chain?");
1870 CurDAG->ReplaceAllUsesOfValueWith(ChainVal, InputChain);
1872 // If the node became dead and we haven't already seen it, delete it.
1873 if (ChainNode->use_empty() &&
1874 !std::count(NowDeadNodes.begin(), NowDeadNodes.end(), ChainNode))
1875 NowDeadNodes.push_back(ChainNode);
1879 // If the result produces glue, update any glue results in the matched
1880 // pattern with the glue result.
1881 if (InputGlue.getNode()) {
1882 // Handle any interior nodes explicitly marked.
1883 for (unsigned i = 0, e = GlueResultNodesMatched.size(); i != e; ++i) {
1884 SDNode *FRN = GlueResultNodesMatched[i];
1886 // If this node was already deleted, don't look at it.
1887 if (FRN->getOpcode() == ISD::DELETED_NODE)
1890 assert(FRN->getValueType(FRN->getNumValues()-1) == MVT::Glue &&
1891 "Doesn't have a glue result");
1892 CurDAG->ReplaceAllUsesOfValueWith(SDValue(FRN, FRN->getNumValues()-1),
1895 // If the node became dead and we haven't already seen it, delete it.
1896 if (FRN->use_empty() &&
1897 !std::count(NowDeadNodes.begin(), NowDeadNodes.end(), FRN))
1898 NowDeadNodes.push_back(FRN);
1902 if (!NowDeadNodes.empty())
1903 CurDAG->RemoveDeadNodes(NowDeadNodes);
1905 DEBUG(dbgs() << "ISEL: Match complete!\n");
1911 CR_LeadsToInteriorNode
1914 /// WalkChainUsers - Walk down the users of the specified chained node that is
1915 /// part of the pattern we're matching, looking at all of the users we find.
1916 /// This determines whether something is an interior node, whether we have a
1917 /// non-pattern node in between two pattern nodes (which prevent folding because
1918 /// it would induce a cycle) and whether we have a TokenFactor node sandwiched
1919 /// between pattern nodes (in which case the TF becomes part of the pattern).
1921 /// The walk we do here is guaranteed to be small because we quickly get down to
1922 /// already selected nodes "below" us.
1924 WalkChainUsers(const SDNode *ChainedNode,
1925 SmallVectorImpl<SDNode*> &ChainedNodesInPattern,
1926 SmallVectorImpl<SDNode*> &InteriorChainedNodes) {
1927 ChainResult Result = CR_Simple;
1929 for (SDNode::use_iterator UI = ChainedNode->use_begin(),
1930 E = ChainedNode->use_end(); UI != E; ++UI) {
1931 // Make sure the use is of the chain, not some other value we produce.
1932 if (UI.getUse().getValueType() != MVT::Other) continue;
1936 if (User->getOpcode() == ISD::HANDLENODE) // Root of the graph.
1939 // If we see an already-selected machine node, then we've gone beyond the
1940 // pattern that we're selecting down into the already selected chunk of the
1942 unsigned UserOpcode = User->getOpcode();
1943 if (User->isMachineOpcode() ||
1944 UserOpcode == ISD::CopyToReg ||
1945 UserOpcode == ISD::CopyFromReg ||
1946 UserOpcode == ISD::INLINEASM ||
1947 UserOpcode == ISD::EH_LABEL ||
1948 UserOpcode == ISD::LIFETIME_START ||
1949 UserOpcode == ISD::LIFETIME_END) {
1950 // If their node ID got reset to -1 then they've already been selected.
1951 // Treat them like a MachineOpcode.
1952 if (User->getNodeId() == -1)
1956 // If we have a TokenFactor, we handle it specially.
1957 if (User->getOpcode() != ISD::TokenFactor) {
1958 // If the node isn't a token factor and isn't part of our pattern, then it
1959 // must be a random chained node in between two nodes we're selecting.
1960 // This happens when we have something like:
1965 // Because we structurally match the load/store as a read/modify/write,
1966 // but the call is chained between them. We cannot fold in this case
1967 // because it would induce a cycle in the graph.
1968 if (!std::count(ChainedNodesInPattern.begin(),
1969 ChainedNodesInPattern.end(), User))
1970 return CR_InducesCycle;
1972 // Otherwise we found a node that is part of our pattern. For example in:
1976 // This would happen when we're scanning down from the load and see the
1977 // store as a user. Record that there is a use of ChainedNode that is
1978 // part of the pattern and keep scanning uses.
1979 Result = CR_LeadsToInteriorNode;
1980 InteriorChainedNodes.push_back(User);
1984 // If we found a TokenFactor, there are two cases to consider: first if the
1985 // TokenFactor is just hanging "below" the pattern we're matching (i.e. no
1986 // uses of the TF are in our pattern) we just want to ignore it. Second,
1987 // the TokenFactor can be sandwiched in between two chained nodes, like so:
1993 // | \ DAG's like cheese
1996 // [TokenFactor] [Op]
2003 // In this case, the TokenFactor becomes part of our match and we rewrite it
2004 // as a new TokenFactor.
2006 // To distinguish these two cases, do a recursive walk down the uses.
2007 switch (WalkChainUsers(User, ChainedNodesInPattern, InteriorChainedNodes)) {
2009 // If the uses of the TokenFactor are just already-selected nodes, ignore
2010 // it, it is "below" our pattern.
2012 case CR_InducesCycle:
2013 // If the uses of the TokenFactor lead to nodes that are not part of our
2014 // pattern that are not selected, folding would turn this into a cycle,
2016 return CR_InducesCycle;
2017 case CR_LeadsToInteriorNode:
2018 break; // Otherwise, keep processing.
2021 // Okay, we know we're in the interesting interior case. The TokenFactor
2022 // is now going to be considered part of the pattern so that we rewrite its
2023 // uses (it may have uses that are not part of the pattern) with the
2024 // ultimate chain result of the generated code. We will also add its chain
2025 // inputs as inputs to the ultimate TokenFactor we create.
2026 Result = CR_LeadsToInteriorNode;
2027 ChainedNodesInPattern.push_back(User);
2028 InteriorChainedNodes.push_back(User);
2035 /// HandleMergeInputChains - This implements the OPC_EmitMergeInputChains
2036 /// operation for when the pattern matched at least one node with a chains. The
2037 /// input vector contains a list of all of the chained nodes that we match. We
2038 /// must determine if this is a valid thing to cover (i.e. matching it won't
2039 /// induce cycles in the DAG) and if so, creating a TokenFactor node. that will
2040 /// be used as the input node chain for the generated nodes.
2042 HandleMergeInputChains(SmallVectorImpl<SDNode*> &ChainNodesMatched,
2043 SelectionDAG *CurDAG) {
2044 // Walk all of the chained nodes we've matched, recursively scanning down the
2045 // users of the chain result. This adds any TokenFactor nodes that are caught
2046 // in between chained nodes to the chained and interior nodes list.
2047 SmallVector<SDNode*, 3> InteriorChainedNodes;
2048 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) {
2049 if (WalkChainUsers(ChainNodesMatched[i], ChainNodesMatched,
2050 InteriorChainedNodes) == CR_InducesCycle)
2051 return SDValue(); // Would induce a cycle.
2054 // Okay, we have walked all the matched nodes and collected TokenFactor nodes
2055 // that we are interested in. Form our input TokenFactor node.
2056 SmallVector<SDValue, 3> InputChains;
2057 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) {
2058 // Add the input chain of this node to the InputChains list (which will be
2059 // the operands of the generated TokenFactor) if it's not an interior node.
2060 SDNode *N = ChainNodesMatched[i];
2061 if (N->getOpcode() != ISD::TokenFactor) {
2062 if (std::count(InteriorChainedNodes.begin(),InteriorChainedNodes.end(),N))
2065 // Otherwise, add the input chain.
2066 SDValue InChain = ChainNodesMatched[i]->getOperand(0);
2067 assert(InChain.getValueType() == MVT::Other && "Not a chain");
2068 InputChains.push_back(InChain);
2072 // If we have a token factor, we want to add all inputs of the token factor
2073 // that are not part of the pattern we're matching.
2074 for (unsigned op = 0, e = N->getNumOperands(); op != e; ++op) {
2075 if (!std::count(ChainNodesMatched.begin(), ChainNodesMatched.end(),
2076 N->getOperand(op).getNode()))
2077 InputChains.push_back(N->getOperand(op));
2081 if (InputChains.size() == 1)
2082 return InputChains[0];
2083 return CurDAG->getNode(ISD::TokenFactor, SDLoc(ChainNodesMatched[0]),
2084 MVT::Other, &InputChains[0], InputChains.size());
2087 /// MorphNode - Handle morphing a node in place for the selector.
2088 SDNode *SelectionDAGISel::
2089 MorphNode(SDNode *Node, unsigned TargetOpc, SDVTList VTList,
2090 const SDValue *Ops, unsigned NumOps, unsigned EmitNodeInfo) {
2091 // It is possible we're using MorphNodeTo to replace a node with no
2092 // normal results with one that has a normal result (or we could be
2093 // adding a chain) and the input could have glue and chains as well.
2094 // In this case we need to shift the operands down.
2095 // FIXME: This is a horrible hack and broken in obscure cases, no worse
2096 // than the old isel though.
2097 int OldGlueResultNo = -1, OldChainResultNo = -1;
2099 unsigned NTMNumResults = Node->getNumValues();
2100 if (Node->getValueType(NTMNumResults-1) == MVT::Glue) {
2101 OldGlueResultNo = NTMNumResults-1;
2102 if (NTMNumResults != 1 &&
2103 Node->getValueType(NTMNumResults-2) == MVT::Other)
2104 OldChainResultNo = NTMNumResults-2;
2105 } else if (Node->getValueType(NTMNumResults-1) == MVT::Other)
2106 OldChainResultNo = NTMNumResults-1;
2108 // Call the underlying SelectionDAG routine to do the transmogrification. Note
2109 // that this deletes operands of the old node that become dead.
2110 SDNode *Res = CurDAG->MorphNodeTo(Node, ~TargetOpc, VTList, Ops, NumOps);
2112 // MorphNodeTo can operate in two ways: if an existing node with the
2113 // specified operands exists, it can just return it. Otherwise, it
2114 // updates the node in place to have the requested operands.
2116 // If we updated the node in place, reset the node ID. To the isel,
2117 // this should be just like a newly allocated machine node.
2121 unsigned ResNumResults = Res->getNumValues();
2122 // Move the glue if needed.
2123 if ((EmitNodeInfo & OPFL_GlueOutput) && OldGlueResultNo != -1 &&
2124 (unsigned)OldGlueResultNo != ResNumResults-1)
2125 CurDAG->ReplaceAllUsesOfValueWith(SDValue(Node, OldGlueResultNo),
2126 SDValue(Res, ResNumResults-1));
2128 if ((EmitNodeInfo & OPFL_GlueOutput) != 0)
2131 // Move the chain reference if needed.
2132 if ((EmitNodeInfo & OPFL_Chain) && OldChainResultNo != -1 &&
2133 (unsigned)OldChainResultNo != ResNumResults-1)
2134 CurDAG->ReplaceAllUsesOfValueWith(SDValue(Node, OldChainResultNo),
2135 SDValue(Res, ResNumResults-1));
2137 // Otherwise, no replacement happened because the node already exists. Replace
2138 // Uses of the old node with the new one.
2140 CurDAG->ReplaceAllUsesWith(Node, Res);
2145 /// CheckSame - Implements OP_CheckSame.
2146 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2147 CheckSame(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2149 const SmallVectorImpl<std::pair<SDValue, SDNode*> > &RecordedNodes) {
2150 // Accept if it is exactly the same as a previously recorded node.
2151 unsigned RecNo = MatcherTable[MatcherIndex++];
2152 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2153 return N == RecordedNodes[RecNo].first;
2156 /// CheckChildSame - Implements OP_CheckChildXSame.
2157 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2158 CheckChildSame(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2160 const SmallVectorImpl<std::pair<SDValue, SDNode*> > &RecordedNodes,
2162 if (ChildNo >= N.getNumOperands())
2163 return false; // Match fails if out of range child #.
2164 return ::CheckSame(MatcherTable, MatcherIndex, N.getOperand(ChildNo),
2168 /// CheckPatternPredicate - Implements OP_CheckPatternPredicate.
2169 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2170 CheckPatternPredicate(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2171 const SelectionDAGISel &SDISel) {
2172 return SDISel.CheckPatternPredicate(MatcherTable[MatcherIndex++]);
2175 /// CheckNodePredicate - Implements OP_CheckNodePredicate.
2176 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2177 CheckNodePredicate(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2178 const SelectionDAGISel &SDISel, SDNode *N) {
2179 return SDISel.CheckNodePredicate(N, MatcherTable[MatcherIndex++]);
2182 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2183 CheckOpcode(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2185 uint16_t Opc = MatcherTable[MatcherIndex++];
2186 Opc |= (unsigned short)MatcherTable[MatcherIndex++] << 8;
2187 return N->getOpcode() == Opc;
2190 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2191 CheckType(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2192 SDValue N, const TargetLowering *TLI) {
2193 MVT::SimpleValueType VT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2194 if (N.getValueType() == VT) return true;
2196 // Handle the case when VT is iPTR.
2197 return VT == MVT::iPTR && N.getValueType() == TLI->getPointerTy();
2200 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2201 CheckChildType(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2202 SDValue N, const TargetLowering *TLI, unsigned ChildNo) {
2203 if (ChildNo >= N.getNumOperands())
2204 return false; // Match fails if out of range child #.
2205 return ::CheckType(MatcherTable, MatcherIndex, N.getOperand(ChildNo), TLI);
2208 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2209 CheckCondCode(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2211 return cast<CondCodeSDNode>(N)->get() ==
2212 (ISD::CondCode)MatcherTable[MatcherIndex++];
2215 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2216 CheckValueType(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2217 SDValue N, const TargetLowering *TLI) {
2218 MVT::SimpleValueType VT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2219 if (cast<VTSDNode>(N)->getVT() == VT)
2222 // Handle the case when VT is iPTR.
2223 return VT == MVT::iPTR && cast<VTSDNode>(N)->getVT() == TLI->getPointerTy();
2226 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2227 CheckInteger(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2229 int64_t Val = MatcherTable[MatcherIndex++];
2231 Val = GetVBR(Val, MatcherTable, MatcherIndex);
2233 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N);
2234 return C && C->getSExtValue() == Val;
2237 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2238 CheckChildInteger(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2239 SDValue N, unsigned ChildNo) {
2240 if (ChildNo >= N.getNumOperands())
2241 return false; // Match fails if out of range child #.
2242 return ::CheckInteger(MatcherTable, MatcherIndex, N.getOperand(ChildNo));
2245 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2246 CheckAndImm(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2247 SDValue N, const SelectionDAGISel &SDISel) {
2248 int64_t Val = MatcherTable[MatcherIndex++];
2250 Val = GetVBR(Val, MatcherTable, MatcherIndex);
2252 if (N->getOpcode() != ISD::AND) return false;
2254 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
2255 return C && SDISel.CheckAndMask(N.getOperand(0), C, Val);
2258 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2259 CheckOrImm(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2260 SDValue N, const SelectionDAGISel &SDISel) {
2261 int64_t Val = MatcherTable[MatcherIndex++];
2263 Val = GetVBR(Val, MatcherTable, MatcherIndex);
2265 if (N->getOpcode() != ISD::OR) return false;
2267 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
2268 return C && SDISel.CheckOrMask(N.getOperand(0), C, Val);
2271 /// IsPredicateKnownToFail - If we know how and can do so without pushing a
2272 /// scope, evaluate the current node. If the current predicate is known to
2273 /// fail, set Result=true and return anything. If the current predicate is
2274 /// known to pass, set Result=false and return the MatcherIndex to continue
2275 /// with. If the current predicate is unknown, set Result=false and return the
2276 /// MatcherIndex to continue with.
2277 static unsigned IsPredicateKnownToFail(const unsigned char *Table,
2278 unsigned Index, SDValue N,
2280 const SelectionDAGISel &SDISel,
2281 SmallVectorImpl<std::pair<SDValue, SDNode*> > &RecordedNodes) {
2282 switch (Table[Index++]) {
2285 return Index-1; // Could not evaluate this predicate.
2286 case SelectionDAGISel::OPC_CheckSame:
2287 Result = !::CheckSame(Table, Index, N, RecordedNodes);
2289 case SelectionDAGISel::OPC_CheckChild0Same:
2290 case SelectionDAGISel::OPC_CheckChild1Same:
2291 case SelectionDAGISel::OPC_CheckChild2Same:
2292 case SelectionDAGISel::OPC_CheckChild3Same:
2293 Result = !::CheckChildSame(Table, Index, N, RecordedNodes,
2294 Table[Index-1] - SelectionDAGISel::OPC_CheckChild0Same);
2296 case SelectionDAGISel::OPC_CheckPatternPredicate:
2297 Result = !::CheckPatternPredicate(Table, Index, SDISel);
2299 case SelectionDAGISel::OPC_CheckPredicate:
2300 Result = !::CheckNodePredicate(Table, Index, SDISel, N.getNode());
2302 case SelectionDAGISel::OPC_CheckOpcode:
2303 Result = !::CheckOpcode(Table, Index, N.getNode());
2305 case SelectionDAGISel::OPC_CheckType:
2306 Result = !::CheckType(Table, Index, N, SDISel.getTargetLowering());
2308 case SelectionDAGISel::OPC_CheckChild0Type:
2309 case SelectionDAGISel::OPC_CheckChild1Type:
2310 case SelectionDAGISel::OPC_CheckChild2Type:
2311 case SelectionDAGISel::OPC_CheckChild3Type:
2312 case SelectionDAGISel::OPC_CheckChild4Type:
2313 case SelectionDAGISel::OPC_CheckChild5Type:
2314 case SelectionDAGISel::OPC_CheckChild6Type:
2315 case SelectionDAGISel::OPC_CheckChild7Type:
2316 Result = !::CheckChildType(Table, Index, N, SDISel.getTargetLowering(),
2317 Table[Index-1] - SelectionDAGISel::OPC_CheckChild0Type);
2319 case SelectionDAGISel::OPC_CheckCondCode:
2320 Result = !::CheckCondCode(Table, Index, N);
2322 case SelectionDAGISel::OPC_CheckValueType:
2323 Result = !::CheckValueType(Table, Index, N, SDISel.getTargetLowering());
2325 case SelectionDAGISel::OPC_CheckInteger:
2326 Result = !::CheckInteger(Table, Index, N);
2328 case SelectionDAGISel::OPC_CheckChild0Integer:
2329 case SelectionDAGISel::OPC_CheckChild1Integer:
2330 case SelectionDAGISel::OPC_CheckChild2Integer:
2331 case SelectionDAGISel::OPC_CheckChild3Integer:
2332 case SelectionDAGISel::OPC_CheckChild4Integer:
2333 Result = !::CheckChildInteger(Table, Index, N,
2334 Table[Index-1] - SelectionDAGISel::OPC_CheckChild0Integer);
2336 case SelectionDAGISel::OPC_CheckAndImm:
2337 Result = !::CheckAndImm(Table, Index, N, SDISel);
2339 case SelectionDAGISel::OPC_CheckOrImm:
2340 Result = !::CheckOrImm(Table, Index, N, SDISel);
2348 /// FailIndex - If this match fails, this is the index to continue with.
2351 /// NodeStack - The node stack when the scope was formed.
2352 SmallVector<SDValue, 4> NodeStack;
2354 /// NumRecordedNodes - The number of recorded nodes when the scope was formed.
2355 unsigned NumRecordedNodes;
2357 /// NumMatchedMemRefs - The number of matched memref entries.
2358 unsigned NumMatchedMemRefs;
2360 /// InputChain/InputGlue - The current chain/glue
2361 SDValue InputChain, InputGlue;
2363 /// HasChainNodesMatched - True if the ChainNodesMatched list is non-empty.
2364 bool HasChainNodesMatched, HasGlueResultNodesMatched;
2369 SDNode *SelectionDAGISel::
2370 SelectCodeCommon(SDNode *NodeToMatch, const unsigned char *MatcherTable,
2371 unsigned TableSize) {
2372 // FIXME: Should these even be selected? Handle these cases in the caller?
2373 switch (NodeToMatch->getOpcode()) {
2376 case ISD::EntryToken: // These nodes remain the same.
2377 case ISD::BasicBlock:
2379 case ISD::RegisterMask:
2380 //case ISD::VALUETYPE:
2381 //case ISD::CONDCODE:
2382 case ISD::HANDLENODE:
2383 case ISD::MDNODE_SDNODE:
2384 case ISD::TargetConstant:
2385 case ISD::TargetConstantFP:
2386 case ISD::TargetConstantPool:
2387 case ISD::TargetFrameIndex:
2388 case ISD::TargetExternalSymbol:
2389 case ISD::TargetBlockAddress:
2390 case ISD::TargetJumpTable:
2391 case ISD::TargetGlobalTLSAddress:
2392 case ISD::TargetGlobalAddress:
2393 case ISD::TokenFactor:
2394 case ISD::CopyFromReg:
2395 case ISD::CopyToReg:
2397 case ISD::LIFETIME_START:
2398 case ISD::LIFETIME_END:
2399 NodeToMatch->setNodeId(-1); // Mark selected.
2401 case ISD::AssertSext:
2402 case ISD::AssertZext:
2403 CurDAG->ReplaceAllUsesOfValueWith(SDValue(NodeToMatch, 0),
2404 NodeToMatch->getOperand(0));
2406 case ISD::INLINEASM: return Select_INLINEASM(NodeToMatch);
2407 case ISD::UNDEF: return Select_UNDEF(NodeToMatch);
2410 assert(!NodeToMatch->isMachineOpcode() && "Node already selected!");
2412 // Set up the node stack with NodeToMatch as the only node on the stack.
2413 SmallVector<SDValue, 8> NodeStack;
2414 SDValue N = SDValue(NodeToMatch, 0);
2415 NodeStack.push_back(N);
2417 // MatchScopes - Scopes used when matching, if a match failure happens, this
2418 // indicates where to continue checking.
2419 SmallVector<MatchScope, 8> MatchScopes;
2421 // RecordedNodes - This is the set of nodes that have been recorded by the
2422 // state machine. The second value is the parent of the node, or null if the
2423 // root is recorded.
2424 SmallVector<std::pair<SDValue, SDNode*>, 8> RecordedNodes;
2426 // MatchedMemRefs - This is the set of MemRef's we've seen in the input
2428 SmallVector<MachineMemOperand*, 2> MatchedMemRefs;
2430 // These are the current input chain and glue for use when generating nodes.
2431 // Various Emit operations change these. For example, emitting a copytoreg
2432 // uses and updates these.
2433 SDValue InputChain, InputGlue;
2435 // ChainNodesMatched - If a pattern matches nodes that have input/output
2436 // chains, the OPC_EmitMergeInputChains operation is emitted which indicates
2437 // which ones they are. The result is captured into this list so that we can
2438 // update the chain results when the pattern is complete.
2439 SmallVector<SDNode*, 3> ChainNodesMatched;
2440 SmallVector<SDNode*, 3> GlueResultNodesMatched;
2442 DEBUG(dbgs() << "ISEL: Starting pattern match on root node: ";
2443 NodeToMatch->dump(CurDAG);
2446 // Determine where to start the interpreter. Normally we start at opcode #0,
2447 // but if the state machine starts with an OPC_SwitchOpcode, then we
2448 // accelerate the first lookup (which is guaranteed to be hot) with the
2449 // OpcodeOffset table.
2450 unsigned MatcherIndex = 0;
2452 if (!OpcodeOffset.empty()) {
2453 // Already computed the OpcodeOffset table, just index into it.
2454 if (N.getOpcode() < OpcodeOffset.size())
2455 MatcherIndex = OpcodeOffset[N.getOpcode()];
2456 DEBUG(dbgs() << " Initial Opcode index to " << MatcherIndex << "\n");
2458 } else if (MatcherTable[0] == OPC_SwitchOpcode) {
2459 // Otherwise, the table isn't computed, but the state machine does start
2460 // with an OPC_SwitchOpcode instruction. Populate the table now, since this
2461 // is the first time we're selecting an instruction.
2464 // Get the size of this case.
2465 unsigned CaseSize = MatcherTable[Idx++];
2467 CaseSize = GetVBR(CaseSize, MatcherTable, Idx);
2468 if (CaseSize == 0) break;
2470 // Get the opcode, add the index to the table.
2471 uint16_t Opc = MatcherTable[Idx++];
2472 Opc |= (unsigned short)MatcherTable[Idx++] << 8;
2473 if (Opc >= OpcodeOffset.size())
2474 OpcodeOffset.resize((Opc+1)*2);
2475 OpcodeOffset[Opc] = Idx;
2479 // Okay, do the lookup for the first opcode.
2480 if (N.getOpcode() < OpcodeOffset.size())
2481 MatcherIndex = OpcodeOffset[N.getOpcode()];
2485 assert(MatcherIndex < TableSize && "Invalid index");
2487 unsigned CurrentOpcodeIndex = MatcherIndex;
2489 BuiltinOpcodes Opcode = (BuiltinOpcodes)MatcherTable[MatcherIndex++];
2492 // Okay, the semantics of this operation are that we should push a scope
2493 // then evaluate the first child. However, pushing a scope only to have
2494 // the first check fail (which then pops it) is inefficient. If we can
2495 // determine immediately that the first check (or first several) will
2496 // immediately fail, don't even bother pushing a scope for them.
2500 unsigned NumToSkip = MatcherTable[MatcherIndex++];
2501 if (NumToSkip & 128)
2502 NumToSkip = GetVBR(NumToSkip, MatcherTable, MatcherIndex);
2503 // Found the end of the scope with no match.
2504 if (NumToSkip == 0) {
2509 FailIndex = MatcherIndex+NumToSkip;
2511 unsigned MatcherIndexOfPredicate = MatcherIndex;
2512 (void)MatcherIndexOfPredicate; // silence warning.
2514 // If we can't evaluate this predicate without pushing a scope (e.g. if
2515 // it is a 'MoveParent') or if the predicate succeeds on this node, we
2516 // push the scope and evaluate the full predicate chain.
2518 MatcherIndex = IsPredicateKnownToFail(MatcherTable, MatcherIndex, N,
2519 Result, *this, RecordedNodes);
2523 DEBUG(dbgs() << " Skipped scope entry (due to false predicate) at "
2524 << "index " << MatcherIndexOfPredicate
2525 << ", continuing at " << FailIndex << "\n");
2526 ++NumDAGIselRetries;
2528 // Otherwise, we know that this case of the Scope is guaranteed to fail,
2529 // move to the next case.
2530 MatcherIndex = FailIndex;
2533 // If the whole scope failed to match, bail.
2534 if (FailIndex == 0) break;
2536 // Push a MatchScope which indicates where to go if the first child fails
2538 MatchScope NewEntry;
2539 NewEntry.FailIndex = FailIndex;
2540 NewEntry.NodeStack.append(NodeStack.begin(), NodeStack.end());
2541 NewEntry.NumRecordedNodes = RecordedNodes.size();
2542 NewEntry.NumMatchedMemRefs = MatchedMemRefs.size();
2543 NewEntry.InputChain = InputChain;
2544 NewEntry.InputGlue = InputGlue;
2545 NewEntry.HasChainNodesMatched = !ChainNodesMatched.empty();
2546 NewEntry.HasGlueResultNodesMatched = !GlueResultNodesMatched.empty();
2547 MatchScopes.push_back(NewEntry);
2550 case OPC_RecordNode: {
2551 // Remember this node, it may end up being an operand in the pattern.
2552 SDNode *Parent = nullptr;
2553 if (NodeStack.size() > 1)
2554 Parent = NodeStack[NodeStack.size()-2].getNode();
2555 RecordedNodes.push_back(std::make_pair(N, Parent));
2559 case OPC_RecordChild0: case OPC_RecordChild1:
2560 case OPC_RecordChild2: case OPC_RecordChild3:
2561 case OPC_RecordChild4: case OPC_RecordChild5:
2562 case OPC_RecordChild6: case OPC_RecordChild7: {
2563 unsigned ChildNo = Opcode-OPC_RecordChild0;
2564 if (ChildNo >= N.getNumOperands())
2565 break; // Match fails if out of range child #.
2567 RecordedNodes.push_back(std::make_pair(N->getOperand(ChildNo),
2571 case OPC_RecordMemRef:
2572 MatchedMemRefs.push_back(cast<MemSDNode>(N)->getMemOperand());
2575 case OPC_CaptureGlueInput:
2576 // If the current node has an input glue, capture it in InputGlue.
2577 if (N->getNumOperands() != 0 &&
2578 N->getOperand(N->getNumOperands()-1).getValueType() == MVT::Glue)
2579 InputGlue = N->getOperand(N->getNumOperands()-1);
2582 case OPC_MoveChild: {
2583 unsigned ChildNo = MatcherTable[MatcherIndex++];
2584 if (ChildNo >= N.getNumOperands())
2585 break; // Match fails if out of range child #.
2586 N = N.getOperand(ChildNo);
2587 NodeStack.push_back(N);
2591 case OPC_MoveParent:
2592 // Pop the current node off the NodeStack.
2593 NodeStack.pop_back();
2594 assert(!NodeStack.empty() && "Node stack imbalance!");
2595 N = NodeStack.back();
2599 if (!::CheckSame(MatcherTable, MatcherIndex, N, RecordedNodes)) break;
2602 case OPC_CheckChild0Same: case OPC_CheckChild1Same:
2603 case OPC_CheckChild2Same: case OPC_CheckChild3Same:
2604 if (!::CheckChildSame(MatcherTable, MatcherIndex, N, RecordedNodes,
2605 Opcode-OPC_CheckChild0Same))
2609 case OPC_CheckPatternPredicate:
2610 if (!::CheckPatternPredicate(MatcherTable, MatcherIndex, *this)) break;
2612 case OPC_CheckPredicate:
2613 if (!::CheckNodePredicate(MatcherTable, MatcherIndex, *this,
2617 case OPC_CheckComplexPat: {
2618 unsigned CPNum = MatcherTable[MatcherIndex++];
2619 unsigned RecNo = MatcherTable[MatcherIndex++];
2620 assert(RecNo < RecordedNodes.size() && "Invalid CheckComplexPat");
2621 if (!CheckComplexPattern(NodeToMatch, RecordedNodes[RecNo].second,
2622 RecordedNodes[RecNo].first, CPNum,
2627 case OPC_CheckOpcode:
2628 if (!::CheckOpcode(MatcherTable, MatcherIndex, N.getNode())) break;
2632 if (!::CheckType(MatcherTable, MatcherIndex, N, getTargetLowering()))
2636 case OPC_SwitchOpcode: {
2637 unsigned CurNodeOpcode = N.getOpcode();
2638 unsigned SwitchStart = MatcherIndex-1; (void)SwitchStart;
2641 // Get the size of this case.
2642 CaseSize = MatcherTable[MatcherIndex++];
2644 CaseSize = GetVBR(CaseSize, MatcherTable, MatcherIndex);
2645 if (CaseSize == 0) break;
2647 uint16_t Opc = MatcherTable[MatcherIndex++];
2648 Opc |= (unsigned short)MatcherTable[MatcherIndex++] << 8;
2650 // If the opcode matches, then we will execute this case.
2651 if (CurNodeOpcode == Opc)
2654 // Otherwise, skip over this case.
2655 MatcherIndex += CaseSize;
2658 // If no cases matched, bail out.
2659 if (CaseSize == 0) break;
2661 // Otherwise, execute the case we found.
2662 DEBUG(dbgs() << " OpcodeSwitch from " << SwitchStart
2663 << " to " << MatcherIndex << "\n");
2667 case OPC_SwitchType: {
2668 MVT CurNodeVT = N.getSimpleValueType();
2669 unsigned SwitchStart = MatcherIndex-1; (void)SwitchStart;
2672 // Get the size of this case.
2673 CaseSize = MatcherTable[MatcherIndex++];
2675 CaseSize = GetVBR(CaseSize, MatcherTable, MatcherIndex);
2676 if (CaseSize == 0) break;
2678 MVT CaseVT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2679 if (CaseVT == MVT::iPTR)
2680 CaseVT = getTargetLowering()->getPointerTy();
2682 // If the VT matches, then we will execute this case.
2683 if (CurNodeVT == CaseVT)
2686 // Otherwise, skip over this case.
2687 MatcherIndex += CaseSize;
2690 // If no cases matched, bail out.
2691 if (CaseSize == 0) break;
2693 // Otherwise, execute the case we found.
2694 DEBUG(dbgs() << " TypeSwitch[" << EVT(CurNodeVT).getEVTString()
2695 << "] from " << SwitchStart << " to " << MatcherIndex<<'\n');
2698 case OPC_CheckChild0Type: case OPC_CheckChild1Type:
2699 case OPC_CheckChild2Type: case OPC_CheckChild3Type:
2700 case OPC_CheckChild4Type: case OPC_CheckChild5Type:
2701 case OPC_CheckChild6Type: case OPC_CheckChild7Type:
2702 if (!::CheckChildType(MatcherTable, MatcherIndex, N, getTargetLowering(),
2703 Opcode-OPC_CheckChild0Type))
2706 case OPC_CheckCondCode:
2707 if (!::CheckCondCode(MatcherTable, MatcherIndex, N)) break;
2709 case OPC_CheckValueType:
2710 if (!::CheckValueType(MatcherTable, MatcherIndex, N, getTargetLowering()))
2713 case OPC_CheckInteger:
2714 if (!::CheckInteger(MatcherTable, MatcherIndex, N)) break;
2716 case OPC_CheckChild0Integer: case OPC_CheckChild1Integer:
2717 case OPC_CheckChild2Integer: case OPC_CheckChild3Integer:
2718 case OPC_CheckChild4Integer:
2719 if (!::CheckChildInteger(MatcherTable, MatcherIndex, N,
2720 Opcode-OPC_CheckChild0Integer)) break;
2722 case OPC_CheckAndImm:
2723 if (!::CheckAndImm(MatcherTable, MatcherIndex, N, *this)) break;
2725 case OPC_CheckOrImm:
2726 if (!::CheckOrImm(MatcherTable, MatcherIndex, N, *this)) break;
2729 case OPC_CheckFoldableChainNode: {
2730 assert(NodeStack.size() != 1 && "No parent node");
2731 // Verify that all intermediate nodes between the root and this one have
2733 bool HasMultipleUses = false;
2734 for (unsigned i = 1, e = NodeStack.size()-1; i != e; ++i)
2735 if (!NodeStack[i].hasOneUse()) {
2736 HasMultipleUses = true;
2739 if (HasMultipleUses) break;
2741 // Check to see that the target thinks this is profitable to fold and that
2742 // we can fold it without inducing cycles in the graph.
2743 if (!IsProfitableToFold(N, NodeStack[NodeStack.size()-2].getNode(),
2745 !IsLegalToFold(N, NodeStack[NodeStack.size()-2].getNode(),
2746 NodeToMatch, OptLevel,
2747 true/*We validate our own chains*/))
2752 case OPC_EmitInteger: {
2753 MVT::SimpleValueType VT =
2754 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2755 int64_t Val = MatcherTable[MatcherIndex++];
2757 Val = GetVBR(Val, MatcherTable, MatcherIndex);
2758 RecordedNodes.push_back(std::pair<SDValue, SDNode*>(
2759 CurDAG->getTargetConstant(Val, VT), nullptr));
2762 case OPC_EmitRegister: {
2763 MVT::SimpleValueType VT =
2764 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2765 unsigned RegNo = MatcherTable[MatcherIndex++];
2766 RecordedNodes.push_back(std::pair<SDValue, SDNode*>(
2767 CurDAG->getRegister(RegNo, VT), nullptr));
2770 case OPC_EmitRegister2: {
2771 // For targets w/ more than 256 register names, the register enum
2772 // values are stored in two bytes in the matcher table (just like
2774 MVT::SimpleValueType VT =
2775 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2776 unsigned RegNo = MatcherTable[MatcherIndex++];
2777 RegNo |= MatcherTable[MatcherIndex++] << 8;
2778 RecordedNodes.push_back(std::pair<SDValue, SDNode*>(
2779 CurDAG->getRegister(RegNo, VT), nullptr));
2783 case OPC_EmitConvertToTarget: {
2784 // Convert from IMM/FPIMM to target version.
2785 unsigned RecNo = MatcherTable[MatcherIndex++];
2786 assert(RecNo < RecordedNodes.size() && "Invalid EmitConvertToTarget");
2787 SDValue Imm = RecordedNodes[RecNo].first;
2789 if (Imm->getOpcode() == ISD::Constant) {
2790 const ConstantInt *Val=cast<ConstantSDNode>(Imm)->getConstantIntValue();
2791 Imm = CurDAG->getConstant(*Val, Imm.getValueType(), true);
2792 } else if (Imm->getOpcode() == ISD::ConstantFP) {
2793 const ConstantFP *Val=cast<ConstantFPSDNode>(Imm)->getConstantFPValue();
2794 Imm = CurDAG->getConstantFP(*Val, Imm.getValueType(), true);
2797 RecordedNodes.push_back(std::make_pair(Imm, RecordedNodes[RecNo].second));
2801 case OPC_EmitMergeInputChains1_0: // OPC_EmitMergeInputChains, 1, 0
2802 case OPC_EmitMergeInputChains1_1: { // OPC_EmitMergeInputChains, 1, 1
2803 // These are space-optimized forms of OPC_EmitMergeInputChains.
2804 assert(!InputChain.getNode() &&
2805 "EmitMergeInputChains should be the first chain producing node");
2806 assert(ChainNodesMatched.empty() &&
2807 "Should only have one EmitMergeInputChains per match");
2809 // Read all of the chained nodes.
2810 unsigned RecNo = Opcode == OPC_EmitMergeInputChains1_1;
2811 assert(RecNo < RecordedNodes.size() && "Invalid EmitMergeInputChains");
2812 ChainNodesMatched.push_back(RecordedNodes[RecNo].first.getNode());
2814 // FIXME: What if other value results of the node have uses not matched
2816 if (ChainNodesMatched.back() != NodeToMatch &&
2817 !RecordedNodes[RecNo].first.hasOneUse()) {
2818 ChainNodesMatched.clear();
2822 // Merge the input chains if they are not intra-pattern references.
2823 InputChain = HandleMergeInputChains(ChainNodesMatched, CurDAG);
2825 if (!InputChain.getNode())
2826 break; // Failed to merge.
2830 case OPC_EmitMergeInputChains: {
2831 assert(!InputChain.getNode() &&
2832 "EmitMergeInputChains should be the first chain producing node");
2833 // This node gets a list of nodes we matched in the input that have
2834 // chains. We want to token factor all of the input chains to these nodes
2835 // together. However, if any of the input chains is actually one of the
2836 // nodes matched in this pattern, then we have an intra-match reference.
2837 // Ignore these because the newly token factored chain should not refer to
2839 unsigned NumChains = MatcherTable[MatcherIndex++];
2840 assert(NumChains != 0 && "Can't TF zero chains");
2842 assert(ChainNodesMatched.empty() &&
2843 "Should only have one EmitMergeInputChains per match");
2845 // Read all of the chained nodes.
2846 for (unsigned i = 0; i != NumChains; ++i) {
2847 unsigned RecNo = MatcherTable[MatcherIndex++];
2848 assert(RecNo < RecordedNodes.size() && "Invalid EmitMergeInputChains");
2849 ChainNodesMatched.push_back(RecordedNodes[RecNo].first.getNode());
2851 // FIXME: What if other value results of the node have uses not matched
2853 if (ChainNodesMatched.back() != NodeToMatch &&
2854 !RecordedNodes[RecNo].first.hasOneUse()) {
2855 ChainNodesMatched.clear();
2860 // If the inner loop broke out, the match fails.
2861 if (ChainNodesMatched.empty())
2864 // Merge the input chains if they are not intra-pattern references.
2865 InputChain = HandleMergeInputChains(ChainNodesMatched, CurDAG);
2867 if (!InputChain.getNode())
2868 break; // Failed to merge.
2873 case OPC_EmitCopyToReg: {
2874 unsigned RecNo = MatcherTable[MatcherIndex++];
2875 assert(RecNo < RecordedNodes.size() && "Invalid EmitCopyToReg");
2876 unsigned DestPhysReg = MatcherTable[MatcherIndex++];
2878 if (!InputChain.getNode())
2879 InputChain = CurDAG->getEntryNode();
2881 InputChain = CurDAG->getCopyToReg(InputChain, SDLoc(NodeToMatch),
2882 DestPhysReg, RecordedNodes[RecNo].first,
2885 InputGlue = InputChain.getValue(1);
2889 case OPC_EmitNodeXForm: {
2890 unsigned XFormNo = MatcherTable[MatcherIndex++];
2891 unsigned RecNo = MatcherTable[MatcherIndex++];
2892 assert(RecNo < RecordedNodes.size() && "Invalid EmitNodeXForm");
2893 SDValue Res = RunSDNodeXForm(RecordedNodes[RecNo].first, XFormNo);
2894 RecordedNodes.push_back(std::pair<SDValue,SDNode*>(Res, nullptr));
2899 case OPC_MorphNodeTo: {
2900 uint16_t TargetOpc = MatcherTable[MatcherIndex++];
2901 TargetOpc |= (unsigned short)MatcherTable[MatcherIndex++] << 8;
2902 unsigned EmitNodeInfo = MatcherTable[MatcherIndex++];
2903 // Get the result VT list.
2904 unsigned NumVTs = MatcherTable[MatcherIndex++];
2905 SmallVector<EVT, 4> VTs;
2906 for (unsigned i = 0; i != NumVTs; ++i) {
2907 MVT::SimpleValueType VT =
2908 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2909 if (VT == MVT::iPTR) VT = getTargetLowering()->getPointerTy().SimpleTy;
2913 if (EmitNodeInfo & OPFL_Chain)
2914 VTs.push_back(MVT::Other);
2915 if (EmitNodeInfo & OPFL_GlueOutput)
2916 VTs.push_back(MVT::Glue);
2918 // This is hot code, so optimize the two most common cases of 1 and 2
2921 if (VTs.size() == 1)
2922 VTList = CurDAG->getVTList(VTs[0]);
2923 else if (VTs.size() == 2)
2924 VTList = CurDAG->getVTList(VTs[0], VTs[1]);
2926 VTList = CurDAG->getVTList(VTs);
2928 // Get the operand list.
2929 unsigned NumOps = MatcherTable[MatcherIndex++];
2930 SmallVector<SDValue, 8> Ops;
2931 for (unsigned i = 0; i != NumOps; ++i) {
2932 unsigned RecNo = MatcherTable[MatcherIndex++];
2934 RecNo = GetVBR(RecNo, MatcherTable, MatcherIndex);
2936 assert(RecNo < RecordedNodes.size() && "Invalid EmitNode");
2937 Ops.push_back(RecordedNodes[RecNo].first);
2940 // If there are variadic operands to add, handle them now.
2941 if (EmitNodeInfo & OPFL_VariadicInfo) {
2942 // Determine the start index to copy from.
2943 unsigned FirstOpToCopy = getNumFixedFromVariadicInfo(EmitNodeInfo);
2944 FirstOpToCopy += (EmitNodeInfo & OPFL_Chain) ? 1 : 0;
2945 assert(NodeToMatch->getNumOperands() >= FirstOpToCopy &&
2946 "Invalid variadic node");
2947 // Copy all of the variadic operands, not including a potential glue
2949 for (unsigned i = FirstOpToCopy, e = NodeToMatch->getNumOperands();
2951 SDValue V = NodeToMatch->getOperand(i);
2952 if (V.getValueType() == MVT::Glue) break;
2957 // If this has chain/glue inputs, add them.
2958 if (EmitNodeInfo & OPFL_Chain)
2959 Ops.push_back(InputChain);
2960 if ((EmitNodeInfo & OPFL_GlueInput) && InputGlue.getNode() != nullptr)
2961 Ops.push_back(InputGlue);
2964 SDNode *Res = nullptr;
2965 if (Opcode != OPC_MorphNodeTo) {
2966 // If this is a normal EmitNode command, just create the new node and
2967 // add the results to the RecordedNodes list.
2968 Res = CurDAG->getMachineNode(TargetOpc, SDLoc(NodeToMatch),
2971 // Add all the non-glue/non-chain results to the RecordedNodes list.
2972 for (unsigned i = 0, e = VTs.size(); i != e; ++i) {
2973 if (VTs[i] == MVT::Other || VTs[i] == MVT::Glue) break;
2974 RecordedNodes.push_back(std::pair<SDValue,SDNode*>(SDValue(Res, i),
2978 } else if (NodeToMatch->getOpcode() != ISD::DELETED_NODE) {
2979 Res = MorphNode(NodeToMatch, TargetOpc, VTList, Ops.data(), Ops.size(),
2982 // NodeToMatch was eliminated by CSE when the target changed the DAG.
2983 // We will visit the equivalent node later.
2984 DEBUG(dbgs() << "Node was eliminated by CSE\n");
2988 // If the node had chain/glue results, update our notion of the current
2990 if (EmitNodeInfo & OPFL_GlueOutput) {
2991 InputGlue = SDValue(Res, VTs.size()-1);
2992 if (EmitNodeInfo & OPFL_Chain)
2993 InputChain = SDValue(Res, VTs.size()-2);
2994 } else if (EmitNodeInfo & OPFL_Chain)
2995 InputChain = SDValue(Res, VTs.size()-1);
2997 // If the OPFL_MemRefs glue is set on this node, slap all of the
2998 // accumulated memrefs onto it.
3000 // FIXME: This is vastly incorrect for patterns with multiple outputs
3001 // instructions that access memory and for ComplexPatterns that match
3003 if (EmitNodeInfo & OPFL_MemRefs) {
3004 // Only attach load or store memory operands if the generated
3005 // instruction may load or store.
3006 const MCInstrDesc &MCID = TM.getInstrInfo()->get(TargetOpc);
3007 bool mayLoad = MCID.mayLoad();
3008 bool mayStore = MCID.mayStore();
3010 unsigned NumMemRefs = 0;
3011 for (SmallVectorImpl<MachineMemOperand *>::const_iterator I =
3012 MatchedMemRefs.begin(), E = MatchedMemRefs.end(); I != E; ++I) {
3013 if ((*I)->isLoad()) {
3016 } else if ((*I)->isStore()) {
3024 MachineSDNode::mmo_iterator MemRefs =
3025 MF->allocateMemRefsArray(NumMemRefs);
3027 MachineSDNode::mmo_iterator MemRefsPos = MemRefs;
3028 for (SmallVectorImpl<MachineMemOperand *>::const_iterator I =
3029 MatchedMemRefs.begin(), E = MatchedMemRefs.end(); I != E; ++I) {
3030 if ((*I)->isLoad()) {
3033 } else if ((*I)->isStore()) {
3041 cast<MachineSDNode>(Res)
3042 ->setMemRefs(MemRefs, MemRefs + NumMemRefs);
3046 << (Opcode == OPC_MorphNodeTo ? "Morphed" : "Created")
3047 << " node: "; Res->dump(CurDAG); dbgs() << "\n");
3049 // If this was a MorphNodeTo then we're completely done!
3050 if (Opcode == OPC_MorphNodeTo) {
3051 // Update chain and glue uses.
3052 UpdateChainsAndGlue(NodeToMatch, InputChain, ChainNodesMatched,
3053 InputGlue, GlueResultNodesMatched, true);
3060 case OPC_MarkGlueResults: {
3061 unsigned NumNodes = MatcherTable[MatcherIndex++];
3063 // Read and remember all the glue-result nodes.
3064 for (unsigned i = 0; i != NumNodes; ++i) {
3065 unsigned RecNo = MatcherTable[MatcherIndex++];
3067 RecNo = GetVBR(RecNo, MatcherTable, MatcherIndex);
3069 assert(RecNo < RecordedNodes.size() && "Invalid MarkGlueResults");
3070 GlueResultNodesMatched.push_back(RecordedNodes[RecNo].first.getNode());
3075 case OPC_CompleteMatch: {
3076 // The match has been completed, and any new nodes (if any) have been
3077 // created. Patch up references to the matched dag to use the newly
3079 unsigned NumResults = MatcherTable[MatcherIndex++];
3081 for (unsigned i = 0; i != NumResults; ++i) {
3082 unsigned ResSlot = MatcherTable[MatcherIndex++];
3084 ResSlot = GetVBR(ResSlot, MatcherTable, MatcherIndex);
3086 assert(ResSlot < RecordedNodes.size() && "Invalid CompleteMatch");
3087 SDValue Res = RecordedNodes[ResSlot].first;
3089 assert(i < NodeToMatch->getNumValues() &&
3090 NodeToMatch->getValueType(i) != MVT::Other &&
3091 NodeToMatch->getValueType(i) != MVT::Glue &&
3092 "Invalid number of results to complete!");
3093 assert((NodeToMatch->getValueType(i) == Res.getValueType() ||
3094 NodeToMatch->getValueType(i) == MVT::iPTR ||
3095 Res.getValueType() == MVT::iPTR ||
3096 NodeToMatch->getValueType(i).getSizeInBits() ==
3097 Res.getValueType().getSizeInBits()) &&
3098 "invalid replacement");
3099 CurDAG->ReplaceAllUsesOfValueWith(SDValue(NodeToMatch, i), Res);
3102 // If the root node defines glue, add it to the glue nodes to update list.
3103 if (NodeToMatch->getValueType(NodeToMatch->getNumValues()-1) == MVT::Glue)
3104 GlueResultNodesMatched.push_back(NodeToMatch);
3106 // Update chain and glue uses.
3107 UpdateChainsAndGlue(NodeToMatch, InputChain, ChainNodesMatched,
3108 InputGlue, GlueResultNodesMatched, false);
3110 assert(NodeToMatch->use_empty() &&
3111 "Didn't replace all uses of the node?");
3113 // FIXME: We just return here, which interacts correctly with SelectRoot
3114 // above. We should fix this to not return an SDNode* anymore.
3119 // If the code reached this point, then the match failed. See if there is
3120 // another child to try in the current 'Scope', otherwise pop it until we
3121 // find a case to check.
3122 DEBUG(dbgs() << " Match failed at index " << CurrentOpcodeIndex << "\n");
3123 ++NumDAGIselRetries;
3125 if (MatchScopes.empty()) {
3126 CannotYetSelect(NodeToMatch);
3130 // Restore the interpreter state back to the point where the scope was
3132 MatchScope &LastScope = MatchScopes.back();
3133 RecordedNodes.resize(LastScope.NumRecordedNodes);
3135 NodeStack.append(LastScope.NodeStack.begin(), LastScope.NodeStack.end());
3136 N = NodeStack.back();
3138 if (LastScope.NumMatchedMemRefs != MatchedMemRefs.size())
3139 MatchedMemRefs.resize(LastScope.NumMatchedMemRefs);
3140 MatcherIndex = LastScope.FailIndex;
3142 DEBUG(dbgs() << " Continuing at " << MatcherIndex << "\n");
3144 InputChain = LastScope.InputChain;
3145 InputGlue = LastScope.InputGlue;
3146 if (!LastScope.HasChainNodesMatched)
3147 ChainNodesMatched.clear();
3148 if (!LastScope.HasGlueResultNodesMatched)
3149 GlueResultNodesMatched.clear();
3151 // Check to see what the offset is at the new MatcherIndex. If it is zero
3152 // we have reached the end of this scope, otherwise we have another child
3153 // in the current scope to try.
3154 unsigned NumToSkip = MatcherTable[MatcherIndex++];
3155 if (NumToSkip & 128)
3156 NumToSkip = GetVBR(NumToSkip, MatcherTable, MatcherIndex);
3158 // If we have another child in this scope to match, update FailIndex and
3160 if (NumToSkip != 0) {
3161 LastScope.FailIndex = MatcherIndex+NumToSkip;
3165 // End of this scope, pop it and try the next child in the containing
3167 MatchScopes.pop_back();
3174 void SelectionDAGISel::CannotYetSelect(SDNode *N) {
3176 raw_string_ostream Msg(msg);
3177 Msg << "Cannot select: ";
3179 if (N->getOpcode() != ISD::INTRINSIC_W_CHAIN &&
3180 N->getOpcode() != ISD::INTRINSIC_WO_CHAIN &&
3181 N->getOpcode() != ISD::INTRINSIC_VOID) {
3182 N->printrFull(Msg, CurDAG);
3183 Msg << "\nIn function: " << MF->getName();
3185 bool HasInputChain = N->getOperand(0).getValueType() == MVT::Other;
3187 cast<ConstantSDNode>(N->getOperand(HasInputChain))->getZExtValue();
3188 if (iid < Intrinsic::num_intrinsics)
3189 Msg << "intrinsic %" << Intrinsic::getName((Intrinsic::ID)iid);
3190 else if (const TargetIntrinsicInfo *TII = TM.getIntrinsicInfo())
3191 Msg << "target intrinsic %" << TII->getName(iid);
3193 Msg << "unknown intrinsic #" << iid;
3195 report_fatal_error(Msg.str());
3198 char SelectionDAGISel::ID = 0;