1 //===-- SelectionDAGISel.cpp - Implement the SelectionDAGISel class -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements the SelectionDAGISel class.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "isel"
15 #include "llvm/ADT/BitVector.h"
16 #include "llvm/Analysis/AliasAnalysis.h"
17 #include "llvm/CodeGen/SelectionDAGISel.h"
18 #include "llvm/CodeGen/ScheduleDAG.h"
19 #include "llvm/Constants.h"
20 #include "llvm/CallingConv.h"
21 #include "llvm/DerivedTypes.h"
22 #include "llvm/Function.h"
23 #include "llvm/GlobalVariable.h"
24 #include "llvm/InlineAsm.h"
25 #include "llvm/Instructions.h"
26 #include "llvm/Intrinsics.h"
27 #include "llvm/IntrinsicInst.h"
28 #include "llvm/ParameterAttributes.h"
29 #include "llvm/CodeGen/Collector.h"
30 #include "llvm/CodeGen/MachineFunction.h"
31 #include "llvm/CodeGen/MachineFrameInfo.h"
32 #include "llvm/CodeGen/MachineInstrBuilder.h"
33 #include "llvm/CodeGen/MachineJumpTableInfo.h"
34 #include "llvm/CodeGen/MachineModuleInfo.h"
35 #include "llvm/CodeGen/MachineRegisterInfo.h"
36 #include "llvm/CodeGen/SchedulerRegistry.h"
37 #include "llvm/CodeGen/SelectionDAG.h"
38 #include "llvm/Target/TargetRegisterInfo.h"
39 #include "llvm/Target/TargetData.h"
40 #include "llvm/Target/TargetFrameInfo.h"
41 #include "llvm/Target/TargetInstrInfo.h"
42 #include "llvm/Target/TargetLowering.h"
43 #include "llvm/Target/TargetMachine.h"
44 #include "llvm/Target/TargetOptions.h"
45 #include "llvm/Support/MathExtras.h"
46 #include "llvm/Support/Debug.h"
47 #include "llvm/Support/Compiler.h"
53 ViewISelDAGs("view-isel-dags", cl::Hidden,
54 cl::desc("Pop up a window to show isel dags as they are selected"));
56 ViewSchedDAGs("view-sched-dags", cl::Hidden,
57 cl::desc("Pop up a window to show sched dags as they are processed"));
59 ViewSUnitDAGs("view-sunit-dags", cl::Hidden,
60 cl::desc("Pop up a window to show SUnit dags after they are processed"));
62 static const bool ViewISelDAGs = 0, ViewSchedDAGs = 0, ViewSUnitDAGs = 0;
65 //===---------------------------------------------------------------------===//
67 /// RegisterScheduler class - Track the registration of instruction schedulers.
69 //===---------------------------------------------------------------------===//
70 MachinePassRegistry RegisterScheduler::Registry;
72 //===---------------------------------------------------------------------===//
74 /// ISHeuristic command line option for instruction schedulers.
76 //===---------------------------------------------------------------------===//
78 cl::opt<RegisterScheduler::FunctionPassCtor, false,
79 RegisterPassParser<RegisterScheduler> >
80 ISHeuristic("pre-RA-sched",
81 cl::init(&createDefaultScheduler),
82 cl::desc("Instruction schedulers available (before register"
85 static RegisterScheduler
86 defaultListDAGScheduler("default", " Best scheduler for the target",
87 createDefaultScheduler);
90 namespace { struct AsmOperandInfo; }
93 /// RegsForValue - This struct represents the physical registers that a
94 /// particular value is assigned and the type information about the value.
95 /// This is needed because values can be promoted into larger registers and
96 /// expanded into multiple smaller registers than the value.
97 struct VISIBILITY_HIDDEN RegsForValue {
98 /// Regs - This list holds the register (for legal and promoted values)
99 /// or register set (for expanded values) that the value should be assigned
101 std::vector<unsigned> Regs;
103 /// RegVT - The value type of each register.
105 MVT::ValueType RegVT;
107 /// ValueVT - The value type of the LLVM value, which may be promoted from
108 /// RegVT or made from merging the two expanded parts.
109 MVT::ValueType ValueVT;
111 RegsForValue() : RegVT(MVT::Other), ValueVT(MVT::Other) {}
113 RegsForValue(unsigned Reg, MVT::ValueType regvt, MVT::ValueType valuevt)
114 : RegVT(regvt), ValueVT(valuevt) {
117 RegsForValue(const std::vector<unsigned> ®s,
118 MVT::ValueType regvt, MVT::ValueType valuevt)
119 : Regs(regs), RegVT(regvt), ValueVT(valuevt) {
122 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from
123 /// this value and returns the result as a ValueVT value. This uses
124 /// Chain/Flag as the input and updates them for the output Chain/Flag.
125 /// If the Flag pointer is NULL, no flag is used.
126 SDOperand getCopyFromRegs(SelectionDAG &DAG,
127 SDOperand &Chain, SDOperand *Flag) const;
129 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
130 /// specified value into the registers specified by this object. This uses
131 /// Chain/Flag as the input and updates them for the output Chain/Flag.
132 /// If the Flag pointer is NULL, no flag is used.
133 void getCopyToRegs(SDOperand Val, SelectionDAG &DAG,
134 SDOperand &Chain, SDOperand *Flag) const;
136 /// AddInlineAsmOperands - Add this value to the specified inlineasm node
137 /// operand list. This adds the code marker and includes the number of
138 /// values added into it.
139 void AddInlineAsmOperands(unsigned Code, SelectionDAG &DAG,
140 std::vector<SDOperand> &Ops) const;
145 //===--------------------------------------------------------------------===//
146 /// createDefaultScheduler - This creates an instruction scheduler appropriate
148 ScheduleDAG* createDefaultScheduler(SelectionDAGISel *IS,
150 MachineBasicBlock *BB) {
151 TargetLowering &TLI = IS->getTargetLowering();
153 if (TLI.getSchedulingPreference() == TargetLowering::SchedulingForLatency) {
154 return createTDListDAGScheduler(IS, DAG, BB);
156 assert(TLI.getSchedulingPreference() ==
157 TargetLowering::SchedulingForRegPressure && "Unknown sched type!");
158 return createBURRListDAGScheduler(IS, DAG, BB);
163 //===--------------------------------------------------------------------===//
164 /// FunctionLoweringInfo - This contains information that is global to a
165 /// function that is used when lowering a region of the function.
166 class FunctionLoweringInfo {
171 MachineRegisterInfo &RegInfo;
173 FunctionLoweringInfo(TargetLowering &TLI, Function &Fn,MachineFunction &MF);
175 /// MBBMap - A mapping from LLVM basic blocks to their machine code entry.
176 std::map<const BasicBlock*, MachineBasicBlock *> MBBMap;
178 /// ValueMap - Since we emit code for the function a basic block at a time,
179 /// we must remember which virtual registers hold the values for
180 /// cross-basic-block values.
181 DenseMap<const Value*, unsigned> ValueMap;
183 /// StaticAllocaMap - Keep track of frame indices for fixed sized allocas in
184 /// the entry block. This allows the allocas to be efficiently referenced
185 /// anywhere in the function.
186 std::map<const AllocaInst*, int> StaticAllocaMap;
189 SmallSet<Instruction*, 8> CatchInfoLost;
190 SmallSet<Instruction*, 8> CatchInfoFound;
193 unsigned MakeReg(MVT::ValueType VT) {
194 return RegInfo.createVirtualRegister(TLI.getRegClassFor(VT));
197 /// isExportedInst - Return true if the specified value is an instruction
198 /// exported from its block.
199 bool isExportedInst(const Value *V) {
200 return ValueMap.count(V);
203 unsigned CreateRegForValue(const Value *V);
205 unsigned InitializeRegForValue(const Value *V) {
206 unsigned &R = ValueMap[V];
207 assert(R == 0 && "Already initialized this value register!");
208 return R = CreateRegForValue(V);
213 /// isSelector - Return true if this instruction is a call to the
214 /// eh.selector intrinsic.
215 static bool isSelector(Instruction *I) {
216 if (IntrinsicInst *II = dyn_cast<IntrinsicInst>(I))
217 return (II->getIntrinsicID() == Intrinsic::eh_selector_i32 ||
218 II->getIntrinsicID() == Intrinsic::eh_selector_i64);
222 /// isUsedOutsideOfDefiningBlock - Return true if this instruction is used by
223 /// PHI nodes or outside of the basic block that defines it, or used by a
224 /// switch or atomic instruction, which may expand to multiple basic blocks.
225 static bool isUsedOutsideOfDefiningBlock(Instruction *I) {
226 if (isa<PHINode>(I)) return true;
227 BasicBlock *BB = I->getParent();
228 for (Value::use_iterator UI = I->use_begin(), E = I->use_end(); UI != E; ++UI)
229 if (cast<Instruction>(*UI)->getParent() != BB || isa<PHINode>(*UI) ||
230 // FIXME: Remove switchinst special case.
231 isa<SwitchInst>(*UI))
236 /// isOnlyUsedInEntryBlock - If the specified argument is only used in the
237 /// entry block, return true. This includes arguments used by switches, since
238 /// the switch may expand into multiple basic blocks.
239 static bool isOnlyUsedInEntryBlock(Argument *A) {
240 BasicBlock *Entry = A->getParent()->begin();
241 for (Value::use_iterator UI = A->use_begin(), E = A->use_end(); UI != E; ++UI)
242 if (cast<Instruction>(*UI)->getParent() != Entry || isa<SwitchInst>(*UI))
243 return false; // Use not in entry block.
247 FunctionLoweringInfo::FunctionLoweringInfo(TargetLowering &tli,
248 Function &fn, MachineFunction &mf)
249 : TLI(tli), Fn(fn), MF(mf), RegInfo(MF.getRegInfo()) {
251 // Create a vreg for each argument register that is not dead and is used
252 // outside of the entry block for the function.
253 for (Function::arg_iterator AI = Fn.arg_begin(), E = Fn.arg_end();
255 if (!isOnlyUsedInEntryBlock(AI))
256 InitializeRegForValue(AI);
258 // Initialize the mapping of values to registers. This is only set up for
259 // instruction values that are used outside of the block that defines
261 Function::iterator BB = Fn.begin(), EB = Fn.end();
262 for (BasicBlock::iterator I = BB->begin(), E = BB->end(); I != E; ++I)
263 if (AllocaInst *AI = dyn_cast<AllocaInst>(I))
264 if (ConstantInt *CUI = dyn_cast<ConstantInt>(AI->getArraySize())) {
265 const Type *Ty = AI->getAllocatedType();
266 uint64_t TySize = TLI.getTargetData()->getABITypeSize(Ty);
268 std::max((unsigned)TLI.getTargetData()->getPrefTypeAlignment(Ty),
271 TySize *= CUI->getZExtValue(); // Get total allocated size.
272 if (TySize == 0) TySize = 1; // Don't create zero-sized stack objects.
273 StaticAllocaMap[AI] =
274 MF.getFrameInfo()->CreateStackObject(TySize, Align);
277 for (; BB != EB; ++BB)
278 for (BasicBlock::iterator I = BB->begin(), E = BB->end(); I != E; ++I)
279 if (!I->use_empty() && isUsedOutsideOfDefiningBlock(I))
280 if (!isa<AllocaInst>(I) ||
281 !StaticAllocaMap.count(cast<AllocaInst>(I)))
282 InitializeRegForValue(I);
284 // Create an initial MachineBasicBlock for each LLVM BasicBlock in F. This
285 // also creates the initial PHI MachineInstrs, though none of the input
286 // operands are populated.
287 for (BB = Fn.begin(), EB = Fn.end(); BB != EB; ++BB) {
288 MachineBasicBlock *MBB = new MachineBasicBlock(BB);
290 MF.getBasicBlockList().push_back(MBB);
292 // Create Machine PHI nodes for LLVM PHI nodes, lowering them as
295 for (BasicBlock::iterator I = BB->begin();(PN = dyn_cast<PHINode>(I)); ++I){
296 if (PN->use_empty()) continue;
298 MVT::ValueType VT = TLI.getValueType(PN->getType());
299 unsigned NumRegisters = TLI.getNumRegisters(VT);
300 unsigned PHIReg = ValueMap[PN];
301 assert(PHIReg && "PHI node does not have an assigned virtual register!");
302 const TargetInstrInfo *TII = TLI.getTargetMachine().getInstrInfo();
303 for (unsigned i = 0; i != NumRegisters; ++i)
304 BuildMI(MBB, TII->get(TargetInstrInfo::PHI), PHIReg+i);
309 /// CreateRegForValue - Allocate the appropriate number of virtual registers of
310 /// the correctly promoted or expanded types. Assign these registers
311 /// consecutive vreg numbers and return the first assigned number.
312 unsigned FunctionLoweringInfo::CreateRegForValue(const Value *V) {
313 MVT::ValueType VT = TLI.getValueType(V->getType());
315 unsigned NumRegisters = TLI.getNumRegisters(VT);
316 MVT::ValueType RegisterVT = TLI.getRegisterType(VT);
318 unsigned R = MakeReg(RegisterVT);
319 for (unsigned i = 1; i != NumRegisters; ++i)
325 //===----------------------------------------------------------------------===//
326 /// SelectionDAGLowering - This is the common target-independent lowering
327 /// implementation that is parameterized by a TargetLowering object.
328 /// Also, targets can overload any lowering method.
331 class SelectionDAGLowering {
332 MachineBasicBlock *CurMBB;
334 DenseMap<const Value*, SDOperand> NodeMap;
336 /// PendingLoads - Loads are not emitted to the program immediately. We bunch
337 /// them up and then emit token factor nodes when possible. This allows us to
338 /// get simple disambiguation between loads without worrying about alias
340 std::vector<SDOperand> PendingLoads;
342 /// Case - A struct to record the Value for a switch case, and the
343 /// case's target basic block.
347 MachineBasicBlock* BB;
349 Case() : Low(0), High(0), BB(0) { }
350 Case(Constant* low, Constant* high, MachineBasicBlock* bb) :
351 Low(low), High(high), BB(bb) { }
352 uint64_t size() const {
353 uint64_t rHigh = cast<ConstantInt>(High)->getSExtValue();
354 uint64_t rLow = cast<ConstantInt>(Low)->getSExtValue();
355 return (rHigh - rLow + 1ULL);
361 MachineBasicBlock* BB;
364 CaseBits(uint64_t mask, MachineBasicBlock* bb, unsigned bits):
365 Mask(mask), BB(bb), Bits(bits) { }
368 typedef std::vector<Case> CaseVector;
369 typedef std::vector<CaseBits> CaseBitsVector;
370 typedef CaseVector::iterator CaseItr;
371 typedef std::pair<CaseItr, CaseItr> CaseRange;
373 /// CaseRec - A struct with ctor used in lowering switches to a binary tree
374 /// of conditional branches.
376 CaseRec(MachineBasicBlock *bb, Constant *lt, Constant *ge, CaseRange r) :
377 CaseBB(bb), LT(lt), GE(ge), Range(r) {}
379 /// CaseBB - The MBB in which to emit the compare and branch
380 MachineBasicBlock *CaseBB;
381 /// LT, GE - If nonzero, we know the current case value must be less-than or
382 /// greater-than-or-equal-to these Constants.
385 /// Range - A pair of iterators representing the range of case values to be
386 /// processed at this point in the binary search tree.
390 typedef std::vector<CaseRec> CaseRecVector;
392 /// The comparison function for sorting the switch case values in the vector.
393 /// WARNING: Case ranges should be disjoint!
395 bool operator () (const Case& C1, const Case& C2) {
396 assert(isa<ConstantInt>(C1.Low) && isa<ConstantInt>(C2.High));
397 const ConstantInt* CI1 = cast<const ConstantInt>(C1.Low);
398 const ConstantInt* CI2 = cast<const ConstantInt>(C2.High);
399 return CI1->getValue().slt(CI2->getValue());
404 bool operator () (const CaseBits& C1, const CaseBits& C2) {
405 return C1.Bits > C2.Bits;
409 unsigned Clusterify(CaseVector& Cases, const SwitchInst &SI);
412 // TLI - This is information that describes the available target features we
413 // need for lowering. This indicates when operations are unavailable,
414 // implemented with a libcall, etc.
417 const TargetData *TD;
420 /// SwitchCases - Vector of CaseBlock structures used to communicate
421 /// SwitchInst code generation information.
422 std::vector<SelectionDAGISel::CaseBlock> SwitchCases;
423 /// JTCases - Vector of JumpTable structures used to communicate
424 /// SwitchInst code generation information.
425 std::vector<SelectionDAGISel::JumpTableBlock> JTCases;
426 std::vector<SelectionDAGISel::BitTestBlock> BitTestCases;
428 /// FuncInfo - Information about the function as a whole.
430 FunctionLoweringInfo &FuncInfo;
432 /// GCI - Garbage collection metadata for the function.
433 CollectorMetadata *GCI;
435 SelectionDAGLowering(SelectionDAG &dag, TargetLowering &tli,
437 FunctionLoweringInfo &funcinfo,
438 CollectorMetadata *gci)
439 : TLI(tli), DAG(dag), TD(DAG.getTarget().getTargetData()), AA(aa),
440 FuncInfo(funcinfo), GCI(gci) {
443 /// getRoot - Return the current virtual root of the Selection DAG.
445 SDOperand getRoot() {
446 if (PendingLoads.empty())
447 return DAG.getRoot();
449 if (PendingLoads.size() == 1) {
450 SDOperand Root = PendingLoads[0];
452 PendingLoads.clear();
456 // Otherwise, we have to make a token factor node.
457 SDOperand Root = DAG.getNode(ISD::TokenFactor, MVT::Other,
458 &PendingLoads[0], PendingLoads.size());
459 PendingLoads.clear();
464 SDOperand CopyValueToVirtualRegister(Value *V, unsigned Reg);
466 void visit(Instruction &I) { visit(I.getOpcode(), I); }
468 void visit(unsigned Opcode, User &I) {
469 // Note: this doesn't use InstVisitor, because it has to work with
470 // ConstantExpr's in addition to instructions.
472 default: assert(0 && "Unknown instruction type encountered!");
474 // Build the switch statement using the Instruction.def file.
475 #define HANDLE_INST(NUM, OPCODE, CLASS) \
476 case Instruction::OPCODE:return visit##OPCODE((CLASS&)I);
477 #include "llvm/Instruction.def"
481 void setCurrentBasicBlock(MachineBasicBlock *MBB) { CurMBB = MBB; }
483 SDOperand getLoadFrom(const Type *Ty, SDOperand Ptr,
484 const Value *SV, SDOperand Root,
485 bool isVolatile, unsigned Alignment);
487 SDOperand getValue(const Value *V);
489 void setValue(const Value *V, SDOperand NewN) {
490 SDOperand &N = NodeMap[V];
491 assert(N.Val == 0 && "Already set a value for this node!");
495 void GetRegistersForValue(AsmOperandInfo &OpInfo, bool HasEarlyClobber,
496 std::set<unsigned> &OutputRegs,
497 std::set<unsigned> &InputRegs);
499 void FindMergedConditions(Value *Cond, MachineBasicBlock *TBB,
500 MachineBasicBlock *FBB, MachineBasicBlock *CurBB,
502 bool isExportableFromCurrentBlock(Value *V, const BasicBlock *FromBB);
503 void ExportFromCurrentBlock(Value *V);
504 void LowerCallTo(CallSite CS, SDOperand Callee, bool IsTailCall,
505 MachineBasicBlock *LandingPad = NULL);
507 // Terminator instructions.
508 void visitRet(ReturnInst &I);
509 void visitBr(BranchInst &I);
510 void visitSwitch(SwitchInst &I);
511 void visitUnreachable(UnreachableInst &I) { /* noop */ }
513 // Helpers for visitSwitch
514 bool handleSmallSwitchRange(CaseRec& CR,
515 CaseRecVector& WorkList,
517 MachineBasicBlock* Default);
518 bool handleJTSwitchCase(CaseRec& CR,
519 CaseRecVector& WorkList,
521 MachineBasicBlock* Default);
522 bool handleBTSplitSwitchCase(CaseRec& CR,
523 CaseRecVector& WorkList,
525 MachineBasicBlock* Default);
526 bool handleBitTestsSwitchCase(CaseRec& CR,
527 CaseRecVector& WorkList,
529 MachineBasicBlock* Default);
530 void visitSwitchCase(SelectionDAGISel::CaseBlock &CB);
531 void visitBitTestHeader(SelectionDAGISel::BitTestBlock &B);
532 void visitBitTestCase(MachineBasicBlock* NextMBB,
534 SelectionDAGISel::BitTestCase &B);
535 void visitJumpTable(SelectionDAGISel::JumpTable &JT);
536 void visitJumpTableHeader(SelectionDAGISel::JumpTable &JT,
537 SelectionDAGISel::JumpTableHeader &JTH);
539 // These all get lowered before this pass.
540 void visitInvoke(InvokeInst &I);
541 void visitUnwind(UnwindInst &I);
543 void visitBinary(User &I, unsigned OpCode);
544 void visitShift(User &I, unsigned Opcode);
545 void visitAdd(User &I) {
546 if (I.getType()->isFPOrFPVector())
547 visitBinary(I, ISD::FADD);
549 visitBinary(I, ISD::ADD);
551 void visitSub(User &I);
552 void visitMul(User &I) {
553 if (I.getType()->isFPOrFPVector())
554 visitBinary(I, ISD::FMUL);
556 visitBinary(I, ISD::MUL);
558 void visitURem(User &I) { visitBinary(I, ISD::UREM); }
559 void visitSRem(User &I) { visitBinary(I, ISD::SREM); }
560 void visitFRem(User &I) { visitBinary(I, ISD::FREM); }
561 void visitUDiv(User &I) { visitBinary(I, ISD::UDIV); }
562 void visitSDiv(User &I) { visitBinary(I, ISD::SDIV); }
563 void visitFDiv(User &I) { visitBinary(I, ISD::FDIV); }
564 void visitAnd (User &I) { visitBinary(I, ISD::AND); }
565 void visitOr (User &I) { visitBinary(I, ISD::OR); }
566 void visitXor (User &I) { visitBinary(I, ISD::XOR); }
567 void visitShl (User &I) { visitShift(I, ISD::SHL); }
568 void visitLShr(User &I) { visitShift(I, ISD::SRL); }
569 void visitAShr(User &I) { visitShift(I, ISD::SRA); }
570 void visitICmp(User &I);
571 void visitFCmp(User &I);
572 // Visit the conversion instructions
573 void visitTrunc(User &I);
574 void visitZExt(User &I);
575 void visitSExt(User &I);
576 void visitFPTrunc(User &I);
577 void visitFPExt(User &I);
578 void visitFPToUI(User &I);
579 void visitFPToSI(User &I);
580 void visitUIToFP(User &I);
581 void visitSIToFP(User &I);
582 void visitPtrToInt(User &I);
583 void visitIntToPtr(User &I);
584 void visitBitCast(User &I);
586 void visitExtractElement(User &I);
587 void visitInsertElement(User &I);
588 void visitShuffleVector(User &I);
590 void visitGetElementPtr(User &I);
591 void visitSelect(User &I);
593 void visitMalloc(MallocInst &I);
594 void visitFree(FreeInst &I);
595 void visitAlloca(AllocaInst &I);
596 void visitLoad(LoadInst &I);
597 void visitStore(StoreInst &I);
598 void visitPHI(PHINode &I) { } // PHI nodes are handled specially.
599 void visitCall(CallInst &I);
600 void visitInlineAsm(CallSite CS);
601 const char *visitIntrinsicCall(CallInst &I, unsigned Intrinsic);
602 void visitTargetIntrinsic(CallInst &I, unsigned Intrinsic);
604 void visitVAStart(CallInst &I);
605 void visitVAArg(VAArgInst &I);
606 void visitVAEnd(CallInst &I);
607 void visitVACopy(CallInst &I);
609 void visitMemIntrinsic(CallInst &I, unsigned Op);
611 void visitGetResult(GetResultInst &I) {
612 assert (0 && "getresult unimplemented");
615 void visitUserOp1(Instruction &I) {
616 assert(0 && "UserOp1 should not exist at instruction selection time!");
619 void visitUserOp2(Instruction &I) {
620 assert(0 && "UserOp2 should not exist at instruction selection time!");
624 } // end namespace llvm
627 /// getCopyFromParts - Create a value that contains the specified legal parts
628 /// combined into the value they represent. If the parts combine to a type
629 /// larger then ValueVT then AssertOp can be used to specify whether the extra
630 /// bits are known to be zero (ISD::AssertZext) or sign extended from ValueVT
631 /// (ISD::AssertSext). Likewise TruncExact is used for floating point types to
632 /// indicate that the extra bits can be discarded without losing precision.
633 static SDOperand getCopyFromParts(SelectionDAG &DAG,
634 const SDOperand *Parts,
636 MVT::ValueType PartVT,
637 MVT::ValueType ValueVT,
638 ISD::NodeType AssertOp = ISD::DELETED_NODE,
639 bool TruncExact = false) {
640 assert(NumParts > 0 && "No parts to assemble!");
641 TargetLowering &TLI = DAG.getTargetLoweringInfo();
642 SDOperand Val = Parts[0];
645 // Assemble the value from multiple parts.
646 if (!MVT::isVector(ValueVT)) {
647 unsigned PartBits = MVT::getSizeInBits(PartVT);
648 unsigned ValueBits = MVT::getSizeInBits(ValueVT);
650 // Assemble the power of 2 part.
651 unsigned RoundParts = NumParts & (NumParts - 1) ?
652 1 << Log2_32(NumParts) : NumParts;
653 unsigned RoundBits = PartBits * RoundParts;
654 MVT::ValueType RoundVT = RoundBits == ValueBits ?
655 ValueVT : MVT::getIntegerType(RoundBits);
658 if (RoundParts > 2) {
659 MVT::ValueType HalfVT = MVT::getIntegerType(RoundBits/2);
660 Lo = getCopyFromParts(DAG, Parts, RoundParts/2, PartVT, HalfVT);
661 Hi = getCopyFromParts(DAG, Parts+RoundParts/2, RoundParts/2,
667 if (TLI.isBigEndian())
669 Val = DAG.getNode(ISD::BUILD_PAIR, RoundVT, Lo, Hi);
671 if (RoundParts < NumParts) {
672 // Assemble the trailing non-power-of-2 part.
673 unsigned OddParts = NumParts - RoundParts;
674 MVT::ValueType OddVT = MVT::getIntegerType(OddParts * PartBits);
675 Hi = getCopyFromParts(DAG, Parts+RoundParts, OddParts, PartVT, OddVT);
677 // Combine the round and odd parts.
679 if (TLI.isBigEndian())
681 MVT::ValueType TotalVT = MVT::getIntegerType(NumParts * PartBits);
682 Hi = DAG.getNode(ISD::ANY_EXTEND, TotalVT, Hi);
683 Hi = DAG.getNode(ISD::SHL, TotalVT, Hi,
684 DAG.getConstant(MVT::getSizeInBits(Lo.getValueType()),
685 TLI.getShiftAmountTy()));
686 Lo = DAG.getNode(ISD::ZERO_EXTEND, TotalVT, Lo);
687 Val = DAG.getNode(ISD::OR, TotalVT, Lo, Hi);
690 // Handle a multi-element vector.
691 MVT::ValueType IntermediateVT, RegisterVT;
692 unsigned NumIntermediates;
694 TLI.getVectorTypeBreakdown(ValueVT, IntermediateVT, NumIntermediates,
697 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!");
698 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!");
699 assert(RegisterVT == Parts[0].getValueType() &&
700 "Part type doesn't match part!");
702 // Assemble the parts into intermediate operands.
703 SmallVector<SDOperand, 8> Ops(NumIntermediates);
704 if (NumIntermediates == NumParts) {
705 // If the register was not expanded, truncate or copy the value,
707 for (unsigned i = 0; i != NumParts; ++i)
708 Ops[i] = getCopyFromParts(DAG, &Parts[i], 1,
709 PartVT, IntermediateVT);
710 } else if (NumParts > 0) {
711 // If the intermediate type was expanded, build the intermediate operands
713 assert(NumParts % NumIntermediates == 0 &&
714 "Must expand into a divisible number of parts!");
715 unsigned Factor = NumParts / NumIntermediates;
716 for (unsigned i = 0; i != NumIntermediates; ++i)
717 Ops[i] = getCopyFromParts(DAG, &Parts[i * Factor], Factor,
718 PartVT, IntermediateVT);
721 // Build a vector with BUILD_VECTOR or CONCAT_VECTORS from the intermediate
723 Val = DAG.getNode(MVT::isVector(IntermediateVT) ?
724 ISD::CONCAT_VECTORS : ISD::BUILD_VECTOR,
725 ValueVT, &Ops[0], NumIntermediates);
729 // There is now one part, held in Val. Correct it to match ValueVT.
730 PartVT = Val.getValueType();
732 if (PartVT == ValueVT)
735 if (MVT::isVector(PartVT)) {
736 assert(MVT::isVector(ValueVT) && "Unknown vector conversion!");
737 return DAG.getNode(ISD::BIT_CONVERT, ValueVT, Val);
740 if (MVT::isVector(ValueVT)) {
741 assert(MVT::getVectorElementType(ValueVT) == PartVT &&
742 MVT::getVectorNumElements(ValueVT) == 1 &&
743 "Only trivial scalar-to-vector conversions should get here!");
744 return DAG.getNode(ISD::BUILD_VECTOR, ValueVT, Val);
747 if (MVT::isInteger(PartVT) &&
748 MVT::isInteger(ValueVT)) {
749 if (MVT::getSizeInBits(ValueVT) < MVT::getSizeInBits(PartVT)) {
750 // For a truncate, see if we have any information to
751 // indicate whether the truncated bits will always be
752 // zero or sign-extension.
753 if (AssertOp != ISD::DELETED_NODE)
754 Val = DAG.getNode(AssertOp, PartVT, Val,
755 DAG.getValueType(ValueVT));
756 return DAG.getNode(ISD::TRUNCATE, ValueVT, Val);
758 return DAG.getNode(ISD::ANY_EXTEND, ValueVT, Val);
762 if (MVT::isFloatingPoint(PartVT) && MVT::isFloatingPoint(ValueVT))
763 return DAG.getNode(ISD::FP_ROUND, ValueVT, Val,
764 DAG.getIntPtrConstant(TruncExact));
766 if (MVT::getSizeInBits(PartVT) == MVT::getSizeInBits(ValueVT))
767 return DAG.getNode(ISD::BIT_CONVERT, ValueVT, Val);
769 assert(0 && "Unknown mismatch!");
772 /// getCopyToParts - Create a series of nodes that contain the specified value
773 /// split into legal parts. If the parts contain more bits than Val, then, for
774 /// integers, ExtendKind can be used to specify how to generate the extra bits.
775 static void getCopyToParts(SelectionDAG &DAG,
779 MVT::ValueType PartVT,
780 ISD::NodeType ExtendKind = ISD::ANY_EXTEND) {
781 TargetLowering &TLI = DAG.getTargetLoweringInfo();
782 MVT::ValueType PtrVT = TLI.getPointerTy();
783 MVT::ValueType ValueVT = Val.getValueType();
784 unsigned PartBits = MVT::getSizeInBits(PartVT);
785 assert(TLI.isTypeLegal(PartVT) && "Copying to an illegal type!");
790 if (!MVT::isVector(ValueVT)) {
791 if (PartVT == ValueVT) {
792 assert(NumParts == 1 && "No-op copy with multiple parts!");
797 if (NumParts * PartBits > MVT::getSizeInBits(ValueVT)) {
798 // If the parts cover more bits than the value has, promote the value.
799 if (MVT::isFloatingPoint(PartVT) && MVT::isFloatingPoint(ValueVT)) {
800 assert(NumParts == 1 && "Do not know what to promote to!");
801 Val = DAG.getNode(ISD::FP_EXTEND, PartVT, Val);
802 } else if (MVT::isInteger(PartVT) && MVT::isInteger(ValueVT)) {
803 ValueVT = MVT::getIntegerType(NumParts * PartBits);
804 Val = DAG.getNode(ExtendKind, ValueVT, Val);
806 assert(0 && "Unknown mismatch!");
808 } else if (PartBits == MVT::getSizeInBits(ValueVT)) {
809 // Different types of the same size.
810 assert(NumParts == 1 && PartVT != ValueVT);
811 Val = DAG.getNode(ISD::BIT_CONVERT, PartVT, Val);
812 } else if (NumParts * PartBits < MVT::getSizeInBits(ValueVT)) {
813 // If the parts cover less bits than value has, truncate the value.
814 if (MVT::isInteger(PartVT) && MVT::isInteger(ValueVT)) {
815 ValueVT = MVT::getIntegerType(NumParts * PartBits);
816 Val = DAG.getNode(ISD::TRUNCATE, ValueVT, Val);
818 assert(0 && "Unknown mismatch!");
822 // The value may have changed - recompute ValueVT.
823 ValueVT = Val.getValueType();
824 assert(NumParts * PartBits == MVT::getSizeInBits(ValueVT) &&
825 "Failed to tile the value with PartVT!");
828 assert(PartVT == ValueVT && "Type conversion failed!");
833 // Expand the value into multiple parts.
834 if (NumParts & (NumParts - 1)) {
835 // The number of parts is not a power of 2. Split off and copy the tail.
836 assert(MVT::isInteger(PartVT) && MVT::isInteger(ValueVT) &&
837 "Do not know what to expand to!");
838 unsigned RoundParts = 1 << Log2_32(NumParts);
839 unsigned RoundBits = RoundParts * PartBits;
840 unsigned OddParts = NumParts - RoundParts;
841 SDOperand OddVal = DAG.getNode(ISD::SRL, ValueVT, Val,
842 DAG.getConstant(RoundBits,
843 TLI.getShiftAmountTy()));
844 getCopyToParts(DAG, OddVal, Parts + RoundParts, OddParts, PartVT);
845 if (TLI.isBigEndian())
846 // The odd parts were reversed by getCopyToParts - unreverse them.
847 std::reverse(Parts + RoundParts, Parts + NumParts);
848 NumParts = RoundParts;
849 ValueVT = MVT::getIntegerType(NumParts * PartBits);
850 Val = DAG.getNode(ISD::TRUNCATE, ValueVT, Val);
853 // The number of parts is a power of 2. Repeatedly bisect the value using
856 for (unsigned StepSize = NumParts; StepSize > 1; StepSize /= 2) {
857 for (unsigned i = 0; i < NumParts; i += StepSize) {
858 unsigned ThisBits = StepSize * PartBits / 2;
859 MVT::ValueType ThisVT =
860 ThisBits == PartBits ? PartVT : MVT::getIntegerType (ThisBits);
862 Parts[i+StepSize/2] =
863 DAG.getNode(ISD::EXTRACT_ELEMENT, ThisVT, Parts[i],
864 DAG.getConstant(1, PtrVT));
866 DAG.getNode(ISD::EXTRACT_ELEMENT, ThisVT, Parts[i],
867 DAG.getConstant(0, PtrVT));
871 if (TLI.isBigEndian())
872 std::reverse(Parts, Parts + NumParts);
879 if (PartVT != ValueVT) {
880 if (MVT::isVector(PartVT)) {
881 Val = DAG.getNode(ISD::BIT_CONVERT, PartVT, Val);
883 assert(MVT::getVectorElementType(ValueVT) == PartVT &&
884 MVT::getVectorNumElements(ValueVT) == 1 &&
885 "Only trivial vector-to-scalar conversions should get here!");
886 Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, PartVT, Val,
887 DAG.getConstant(0, PtrVT));
895 // Handle a multi-element vector.
896 MVT::ValueType IntermediateVT, RegisterVT;
897 unsigned NumIntermediates;
899 DAG.getTargetLoweringInfo()
900 .getVectorTypeBreakdown(ValueVT, IntermediateVT, NumIntermediates,
902 unsigned NumElements = MVT::getVectorNumElements(ValueVT);
904 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!");
905 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!");
907 // Split the vector into intermediate operands.
908 SmallVector<SDOperand, 8> Ops(NumIntermediates);
909 for (unsigned i = 0; i != NumIntermediates; ++i)
910 if (MVT::isVector(IntermediateVT))
911 Ops[i] = DAG.getNode(ISD::EXTRACT_SUBVECTOR,
913 DAG.getConstant(i * (NumElements / NumIntermediates),
916 Ops[i] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT,
918 DAG.getConstant(i, PtrVT));
920 // Split the intermediate operands into legal parts.
921 if (NumParts == NumIntermediates) {
922 // If the register was not expanded, promote or copy the value,
924 for (unsigned i = 0; i != NumParts; ++i)
925 getCopyToParts(DAG, Ops[i], &Parts[i], 1, PartVT);
926 } else if (NumParts > 0) {
927 // If the intermediate type was expanded, split each the value into
929 assert(NumParts % NumIntermediates == 0 &&
930 "Must expand into a divisible number of parts!");
931 unsigned Factor = NumParts / NumIntermediates;
932 for (unsigned i = 0; i != NumIntermediates; ++i)
933 getCopyToParts(DAG, Ops[i], &Parts[i * Factor], Factor, PartVT);
938 SDOperand SelectionDAGLowering::getValue(const Value *V) {
939 SDOperand &N = NodeMap[V];
942 const Type *VTy = V->getType();
943 MVT::ValueType VT = TLI.getValueType(VTy);
944 if (Constant *C = const_cast<Constant*>(dyn_cast<Constant>(V))) {
945 if (ConstantExpr *CE = dyn_cast<ConstantExpr>(C)) {
946 visit(CE->getOpcode(), *CE);
947 SDOperand N1 = NodeMap[V];
948 assert(N1.Val && "visit didn't populate the ValueMap!");
950 } else if (GlobalValue *GV = dyn_cast<GlobalValue>(C)) {
951 return N = DAG.getGlobalAddress(GV, VT);
952 } else if (isa<ConstantPointerNull>(C)) {
953 return N = DAG.getConstant(0, TLI.getPointerTy());
954 } else if (isa<UndefValue>(C)) {
955 if (!isa<VectorType>(VTy))
956 return N = DAG.getNode(ISD::UNDEF, VT);
958 // Create a BUILD_VECTOR of undef nodes.
959 const VectorType *PTy = cast<VectorType>(VTy);
960 unsigned NumElements = PTy->getNumElements();
961 MVT::ValueType PVT = TLI.getValueType(PTy->getElementType());
963 SmallVector<SDOperand, 8> Ops;
964 Ops.assign(NumElements, DAG.getNode(ISD::UNDEF, PVT));
966 // Create a VConstant node with generic Vector type.
967 MVT::ValueType VT = MVT::getVectorType(PVT, NumElements);
968 return N = DAG.getNode(ISD::BUILD_VECTOR, VT,
969 &Ops[0], Ops.size());
970 } else if (ConstantFP *CFP = dyn_cast<ConstantFP>(C)) {
971 return N = DAG.getConstantFP(CFP->getValueAPF(), VT);
972 } else if (const VectorType *PTy = dyn_cast<VectorType>(VTy)) {
973 unsigned NumElements = PTy->getNumElements();
974 MVT::ValueType PVT = TLI.getValueType(PTy->getElementType());
976 // Now that we know the number and type of the elements, push a
977 // Constant or ConstantFP node onto the ops list for each element of
978 // the vector constant.
979 SmallVector<SDOperand, 8> Ops;
980 if (ConstantVector *CP = dyn_cast<ConstantVector>(C)) {
981 for (unsigned i = 0; i != NumElements; ++i)
982 Ops.push_back(getValue(CP->getOperand(i)));
984 assert(isa<ConstantAggregateZero>(C) && "Unknown vector constant!");
986 if (MVT::isFloatingPoint(PVT))
987 Op = DAG.getConstantFP(0, PVT);
989 Op = DAG.getConstant(0, PVT);
990 Ops.assign(NumElements, Op);
993 // Create a BUILD_VECTOR node.
994 MVT::ValueType VT = MVT::getVectorType(PVT, NumElements);
995 return NodeMap[V] = DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0],
998 // Canonicalize all constant ints to be unsigned.
999 return N = DAG.getConstant(cast<ConstantInt>(C)->getZExtValue(),VT);
1003 if (const AllocaInst *AI = dyn_cast<AllocaInst>(V)) {
1004 std::map<const AllocaInst*, int>::iterator SI =
1005 FuncInfo.StaticAllocaMap.find(AI);
1006 if (SI != FuncInfo.StaticAllocaMap.end())
1007 return DAG.getFrameIndex(SI->second, TLI.getPointerTy());
1010 unsigned InReg = FuncInfo.ValueMap[V];
1011 assert(InReg && "Value not in map!");
1013 MVT::ValueType RegisterVT = TLI.getRegisterType(VT);
1014 unsigned NumRegs = TLI.getNumRegisters(VT);
1016 std::vector<unsigned> Regs(NumRegs);
1017 for (unsigned i = 0; i != NumRegs; ++i)
1018 Regs[i] = InReg + i;
1020 RegsForValue RFV(Regs, RegisterVT, VT);
1021 SDOperand Chain = DAG.getEntryNode();
1023 return RFV.getCopyFromRegs(DAG, Chain, NULL);
1027 void SelectionDAGLowering::visitRet(ReturnInst &I) {
1028 if (I.getNumOperands() == 0) {
1029 DAG.setRoot(DAG.getNode(ISD::RET, MVT::Other, getRoot()));
1032 SmallVector<SDOperand, 8> NewValues;
1033 NewValues.push_back(getRoot());
1034 for (unsigned i = 0, e = I.getNumOperands(); i != e; ++i) {
1035 SDOperand RetOp = getValue(I.getOperand(i));
1036 MVT::ValueType VT = RetOp.getValueType();
1038 // FIXME: C calling convention requires the return type to be promoted to
1039 // at least 32-bit. But this is not necessary for non-C calling conventions.
1040 if (MVT::isInteger(VT)) {
1041 MVT::ValueType MinVT = TLI.getRegisterType(MVT::i32);
1042 if (MVT::getSizeInBits(VT) < MVT::getSizeInBits(MinVT))
1046 unsigned NumParts = TLI.getNumRegisters(VT);
1047 MVT::ValueType PartVT = TLI.getRegisterType(VT);
1048 SmallVector<SDOperand, 4> Parts(NumParts);
1049 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
1051 const Function *F = I.getParent()->getParent();
1052 if (F->paramHasAttr(0, ParamAttr::SExt))
1053 ExtendKind = ISD::SIGN_EXTEND;
1054 else if (F->paramHasAttr(0, ParamAttr::ZExt))
1055 ExtendKind = ISD::ZERO_EXTEND;
1057 getCopyToParts(DAG, RetOp, &Parts[0], NumParts, PartVT, ExtendKind);
1059 for (unsigned i = 0; i < NumParts; ++i) {
1060 NewValues.push_back(Parts[i]);
1061 NewValues.push_back(DAG.getConstant(false, MVT::i32));
1064 DAG.setRoot(DAG.getNode(ISD::RET, MVT::Other,
1065 &NewValues[0], NewValues.size()));
1068 /// ExportFromCurrentBlock - If this condition isn't known to be exported from
1069 /// the current basic block, add it to ValueMap now so that we'll get a
1071 void SelectionDAGLowering::ExportFromCurrentBlock(Value *V) {
1072 // No need to export constants.
1073 if (!isa<Instruction>(V) && !isa<Argument>(V)) return;
1075 // Already exported?
1076 if (FuncInfo.isExportedInst(V)) return;
1078 unsigned Reg = FuncInfo.InitializeRegForValue(V);
1079 PendingLoads.push_back(CopyValueToVirtualRegister(V, Reg));
1082 bool SelectionDAGLowering::isExportableFromCurrentBlock(Value *V,
1083 const BasicBlock *FromBB) {
1084 // The operands of the setcc have to be in this block. We don't know
1085 // how to export them from some other block.
1086 if (Instruction *VI = dyn_cast<Instruction>(V)) {
1087 // Can export from current BB.
1088 if (VI->getParent() == FromBB)
1091 // Is already exported, noop.
1092 return FuncInfo.isExportedInst(V);
1095 // If this is an argument, we can export it if the BB is the entry block or
1096 // if it is already exported.
1097 if (isa<Argument>(V)) {
1098 if (FromBB == &FromBB->getParent()->getEntryBlock())
1101 // Otherwise, can only export this if it is already exported.
1102 return FuncInfo.isExportedInst(V);
1105 // Otherwise, constants can always be exported.
1109 static bool InBlock(const Value *V, const BasicBlock *BB) {
1110 if (const Instruction *I = dyn_cast<Instruction>(V))
1111 return I->getParent() == BB;
1115 /// FindMergedConditions - If Cond is an expression like
1116 void SelectionDAGLowering::FindMergedConditions(Value *Cond,
1117 MachineBasicBlock *TBB,
1118 MachineBasicBlock *FBB,
1119 MachineBasicBlock *CurBB,
1121 // If this node is not part of the or/and tree, emit it as a branch.
1122 Instruction *BOp = dyn_cast<Instruction>(Cond);
1124 if (!BOp || !(isa<BinaryOperator>(BOp) || isa<CmpInst>(BOp)) ||
1125 (unsigned)BOp->getOpcode() != Opc || !BOp->hasOneUse() ||
1126 BOp->getParent() != CurBB->getBasicBlock() ||
1127 !InBlock(BOp->getOperand(0), CurBB->getBasicBlock()) ||
1128 !InBlock(BOp->getOperand(1), CurBB->getBasicBlock())) {
1129 const BasicBlock *BB = CurBB->getBasicBlock();
1131 // If the leaf of the tree is a comparison, merge the condition into
1133 if ((isa<ICmpInst>(Cond) || isa<FCmpInst>(Cond)) &&
1134 // The operands of the cmp have to be in this block. We don't know
1135 // how to export them from some other block. If this is the first block
1136 // of the sequence, no exporting is needed.
1138 (isExportableFromCurrentBlock(BOp->getOperand(0), BB) &&
1139 isExportableFromCurrentBlock(BOp->getOperand(1), BB)))) {
1140 BOp = cast<Instruction>(Cond);
1141 ISD::CondCode Condition;
1142 if (ICmpInst *IC = dyn_cast<ICmpInst>(Cond)) {
1143 switch (IC->getPredicate()) {
1144 default: assert(0 && "Unknown icmp predicate opcode!");
1145 case ICmpInst::ICMP_EQ: Condition = ISD::SETEQ; break;
1146 case ICmpInst::ICMP_NE: Condition = ISD::SETNE; break;
1147 case ICmpInst::ICMP_SLE: Condition = ISD::SETLE; break;
1148 case ICmpInst::ICMP_ULE: Condition = ISD::SETULE; break;
1149 case ICmpInst::ICMP_SGE: Condition = ISD::SETGE; break;
1150 case ICmpInst::ICMP_UGE: Condition = ISD::SETUGE; break;
1151 case ICmpInst::ICMP_SLT: Condition = ISD::SETLT; break;
1152 case ICmpInst::ICMP_ULT: Condition = ISD::SETULT; break;
1153 case ICmpInst::ICMP_SGT: Condition = ISD::SETGT; break;
1154 case ICmpInst::ICMP_UGT: Condition = ISD::SETUGT; break;
1156 } else if (FCmpInst *FC = dyn_cast<FCmpInst>(Cond)) {
1157 ISD::CondCode FPC, FOC;
1158 switch (FC->getPredicate()) {
1159 default: assert(0 && "Unknown fcmp predicate opcode!");
1160 case FCmpInst::FCMP_FALSE: FOC = FPC = ISD::SETFALSE; break;
1161 case FCmpInst::FCMP_OEQ: FOC = ISD::SETEQ; FPC = ISD::SETOEQ; break;
1162 case FCmpInst::FCMP_OGT: FOC = ISD::SETGT; FPC = ISD::SETOGT; break;
1163 case FCmpInst::FCMP_OGE: FOC = ISD::SETGE; FPC = ISD::SETOGE; break;
1164 case FCmpInst::FCMP_OLT: FOC = ISD::SETLT; FPC = ISD::SETOLT; break;
1165 case FCmpInst::FCMP_OLE: FOC = ISD::SETLE; FPC = ISD::SETOLE; break;
1166 case FCmpInst::FCMP_ONE: FOC = ISD::SETNE; FPC = ISD::SETONE; break;
1167 case FCmpInst::FCMP_ORD: FOC = ISD::SETEQ; FPC = ISD::SETO; break;
1168 case FCmpInst::FCMP_UNO: FOC = ISD::SETNE; FPC = ISD::SETUO; break;
1169 case FCmpInst::FCMP_UEQ: FOC = ISD::SETEQ; FPC = ISD::SETUEQ; break;
1170 case FCmpInst::FCMP_UGT: FOC = ISD::SETGT; FPC = ISD::SETUGT; break;
1171 case FCmpInst::FCMP_UGE: FOC = ISD::SETGE; FPC = ISD::SETUGE; break;
1172 case FCmpInst::FCMP_ULT: FOC = ISD::SETLT; FPC = ISD::SETULT; break;
1173 case FCmpInst::FCMP_ULE: FOC = ISD::SETLE; FPC = ISD::SETULE; break;
1174 case FCmpInst::FCMP_UNE: FOC = ISD::SETNE; FPC = ISD::SETUNE; break;
1175 case FCmpInst::FCMP_TRUE: FOC = FPC = ISD::SETTRUE; break;
1177 if (FiniteOnlyFPMath())
1182 Condition = ISD::SETEQ; // silence warning.
1183 assert(0 && "Unknown compare instruction");
1186 SelectionDAGISel::CaseBlock CB(Condition, BOp->getOperand(0),
1187 BOp->getOperand(1), NULL, TBB, FBB, CurBB);
1188 SwitchCases.push_back(CB);
1192 // Create a CaseBlock record representing this branch.
1193 SelectionDAGISel::CaseBlock CB(ISD::SETEQ, Cond, ConstantInt::getTrue(),
1194 NULL, TBB, FBB, CurBB);
1195 SwitchCases.push_back(CB);
1200 // Create TmpBB after CurBB.
1201 MachineFunction::iterator BBI = CurBB;
1202 MachineBasicBlock *TmpBB = new MachineBasicBlock(CurBB->getBasicBlock());
1203 CurBB->getParent()->getBasicBlockList().insert(++BBI, TmpBB);
1205 if (Opc == Instruction::Or) {
1206 // Codegen X | Y as:
1214 // Emit the LHS condition.
1215 FindMergedConditions(BOp->getOperand(0), TBB, TmpBB, CurBB, Opc);
1217 // Emit the RHS condition into TmpBB.
1218 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, Opc);
1220 assert(Opc == Instruction::And && "Unknown merge op!");
1221 // Codegen X & Y as:
1228 // This requires creation of TmpBB after CurBB.
1230 // Emit the LHS condition.
1231 FindMergedConditions(BOp->getOperand(0), TmpBB, FBB, CurBB, Opc);
1233 // Emit the RHS condition into TmpBB.
1234 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, Opc);
1238 /// If the set of cases should be emitted as a series of branches, return true.
1239 /// If we should emit this as a bunch of and/or'd together conditions, return
1242 ShouldEmitAsBranches(const std::vector<SelectionDAGISel::CaseBlock> &Cases) {
1243 if (Cases.size() != 2) return true;
1245 // If this is two comparisons of the same values or'd or and'd together, they
1246 // will get folded into a single comparison, so don't emit two blocks.
1247 if ((Cases[0].CmpLHS == Cases[1].CmpLHS &&
1248 Cases[0].CmpRHS == Cases[1].CmpRHS) ||
1249 (Cases[0].CmpRHS == Cases[1].CmpLHS &&
1250 Cases[0].CmpLHS == Cases[1].CmpRHS)) {
1257 void SelectionDAGLowering::visitBr(BranchInst &I) {
1258 // Update machine-CFG edges.
1259 MachineBasicBlock *Succ0MBB = FuncInfo.MBBMap[I.getSuccessor(0)];
1261 // Figure out which block is immediately after the current one.
1262 MachineBasicBlock *NextBlock = 0;
1263 MachineFunction::iterator BBI = CurMBB;
1264 if (++BBI != CurMBB->getParent()->end())
1267 if (I.isUnconditional()) {
1268 // If this is not a fall-through branch, emit the branch.
1269 if (Succ0MBB != NextBlock)
1270 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, getRoot(),
1271 DAG.getBasicBlock(Succ0MBB)));
1273 // Update machine-CFG edges.
1274 CurMBB->addSuccessor(Succ0MBB);
1278 // If this condition is one of the special cases we handle, do special stuff
1280 Value *CondVal = I.getCondition();
1281 MachineBasicBlock *Succ1MBB = FuncInfo.MBBMap[I.getSuccessor(1)];
1283 // If this is a series of conditions that are or'd or and'd together, emit
1284 // this as a sequence of branches instead of setcc's with and/or operations.
1285 // For example, instead of something like:
1298 if (BinaryOperator *BOp = dyn_cast<BinaryOperator>(CondVal)) {
1299 if (BOp->hasOneUse() &&
1300 (BOp->getOpcode() == Instruction::And ||
1301 BOp->getOpcode() == Instruction::Or)) {
1302 FindMergedConditions(BOp, Succ0MBB, Succ1MBB, CurMBB, BOp->getOpcode());
1303 // If the compares in later blocks need to use values not currently
1304 // exported from this block, export them now. This block should always
1305 // be the first entry.
1306 assert(SwitchCases[0].ThisBB == CurMBB && "Unexpected lowering!");
1308 // Allow some cases to be rejected.
1309 if (ShouldEmitAsBranches(SwitchCases)) {
1310 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i) {
1311 ExportFromCurrentBlock(SwitchCases[i].CmpLHS);
1312 ExportFromCurrentBlock(SwitchCases[i].CmpRHS);
1315 // Emit the branch for this block.
1316 visitSwitchCase(SwitchCases[0]);
1317 SwitchCases.erase(SwitchCases.begin());
1321 // Okay, we decided not to do this, remove any inserted MBB's and clear
1323 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i)
1324 CurMBB->getParent()->getBasicBlockList().erase(SwitchCases[i].ThisBB);
1326 SwitchCases.clear();
1330 // Create a CaseBlock record representing this branch.
1331 SelectionDAGISel::CaseBlock CB(ISD::SETEQ, CondVal, ConstantInt::getTrue(),
1332 NULL, Succ0MBB, Succ1MBB, CurMBB);
1333 // Use visitSwitchCase to actually insert the fast branch sequence for this
1335 visitSwitchCase(CB);
1338 /// visitSwitchCase - Emits the necessary code to represent a single node in
1339 /// the binary search tree resulting from lowering a switch instruction.
1340 void SelectionDAGLowering::visitSwitchCase(SelectionDAGISel::CaseBlock &CB) {
1342 SDOperand CondLHS = getValue(CB.CmpLHS);
1344 // Build the setcc now.
1345 if (CB.CmpMHS == NULL) {
1346 // Fold "(X == true)" to X and "(X == false)" to !X to
1347 // handle common cases produced by branch lowering.
1348 if (CB.CmpRHS == ConstantInt::getTrue() && CB.CC == ISD::SETEQ)
1350 else if (CB.CmpRHS == ConstantInt::getFalse() && CB.CC == ISD::SETEQ) {
1351 SDOperand True = DAG.getConstant(1, CondLHS.getValueType());
1352 Cond = DAG.getNode(ISD::XOR, CondLHS.getValueType(), CondLHS, True);
1354 Cond = DAG.getSetCC(MVT::i1, CondLHS, getValue(CB.CmpRHS), CB.CC);
1356 assert(CB.CC == ISD::SETLE && "Can handle only LE ranges now");
1358 uint64_t Low = cast<ConstantInt>(CB.CmpLHS)->getSExtValue();
1359 uint64_t High = cast<ConstantInt>(CB.CmpRHS)->getSExtValue();
1361 SDOperand CmpOp = getValue(CB.CmpMHS);
1362 MVT::ValueType VT = CmpOp.getValueType();
1364 if (cast<ConstantInt>(CB.CmpLHS)->isMinValue(true)) {
1365 Cond = DAG.getSetCC(MVT::i1, CmpOp, DAG.getConstant(High, VT), ISD::SETLE);
1367 SDOperand SUB = DAG.getNode(ISD::SUB, VT, CmpOp, DAG.getConstant(Low, VT));
1368 Cond = DAG.getSetCC(MVT::i1, SUB,
1369 DAG.getConstant(High-Low, VT), ISD::SETULE);
1374 // Set NextBlock to be the MBB immediately after the current one, if any.
1375 // This is used to avoid emitting unnecessary branches to the next block.
1376 MachineBasicBlock *NextBlock = 0;
1377 MachineFunction::iterator BBI = CurMBB;
1378 if (++BBI != CurMBB->getParent()->end())
1381 // If the lhs block is the next block, invert the condition so that we can
1382 // fall through to the lhs instead of the rhs block.
1383 if (CB.TrueBB == NextBlock) {
1384 std::swap(CB.TrueBB, CB.FalseBB);
1385 SDOperand True = DAG.getConstant(1, Cond.getValueType());
1386 Cond = DAG.getNode(ISD::XOR, Cond.getValueType(), Cond, True);
1388 SDOperand BrCond = DAG.getNode(ISD::BRCOND, MVT::Other, getRoot(), Cond,
1389 DAG.getBasicBlock(CB.TrueBB));
1390 if (CB.FalseBB == NextBlock)
1391 DAG.setRoot(BrCond);
1393 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, BrCond,
1394 DAG.getBasicBlock(CB.FalseBB)));
1395 // Update successor info
1396 CurMBB->addSuccessor(CB.TrueBB);
1397 CurMBB->addSuccessor(CB.FalseBB);
1400 /// visitJumpTable - Emit JumpTable node in the current MBB
1401 void SelectionDAGLowering::visitJumpTable(SelectionDAGISel::JumpTable &JT) {
1402 // Emit the code for the jump table
1403 assert(JT.Reg != -1U && "Should lower JT Header first!");
1404 MVT::ValueType PTy = TLI.getPointerTy();
1405 SDOperand Index = DAG.getCopyFromReg(getRoot(), JT.Reg, PTy);
1406 SDOperand Table = DAG.getJumpTable(JT.JTI, PTy);
1407 DAG.setRoot(DAG.getNode(ISD::BR_JT, MVT::Other, Index.getValue(1),
1412 /// visitJumpTableHeader - This function emits necessary code to produce index
1413 /// in the JumpTable from switch case.
1414 void SelectionDAGLowering::visitJumpTableHeader(SelectionDAGISel::JumpTable &JT,
1415 SelectionDAGISel::JumpTableHeader &JTH) {
1416 // Subtract the lowest switch case value from the value being switched on
1417 // and conditional branch to default mbb if the result is greater than the
1418 // difference between smallest and largest cases.
1419 SDOperand SwitchOp = getValue(JTH.SValue);
1420 MVT::ValueType VT = SwitchOp.getValueType();
1421 SDOperand SUB = DAG.getNode(ISD::SUB, VT, SwitchOp,
1422 DAG.getConstant(JTH.First, VT));
1424 // The SDNode we just created, which holds the value being switched on
1425 // minus the the smallest case value, needs to be copied to a virtual
1426 // register so it can be used as an index into the jump table in a
1427 // subsequent basic block. This value may be smaller or larger than the
1428 // target's pointer type, and therefore require extension or truncating.
1429 if (MVT::getSizeInBits(VT) > MVT::getSizeInBits(TLI.getPointerTy()))
1430 SwitchOp = DAG.getNode(ISD::TRUNCATE, TLI.getPointerTy(), SUB);
1432 SwitchOp = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(), SUB);
1434 unsigned JumpTableReg = FuncInfo.MakeReg(TLI.getPointerTy());
1435 SDOperand CopyTo = DAG.getCopyToReg(getRoot(), JumpTableReg, SwitchOp);
1436 JT.Reg = JumpTableReg;
1438 // Emit the range check for the jump table, and branch to the default
1439 // block for the switch statement if the value being switched on exceeds
1440 // the largest case in the switch.
1441 SDOperand CMP = DAG.getSetCC(TLI.getSetCCResultTy(), SUB,
1442 DAG.getConstant(JTH.Last-JTH.First,VT),
1445 // Set NextBlock to be the MBB immediately after the current one, if any.
1446 // This is used to avoid emitting unnecessary branches to the next block.
1447 MachineBasicBlock *NextBlock = 0;
1448 MachineFunction::iterator BBI = CurMBB;
1449 if (++BBI != CurMBB->getParent()->end())
1452 SDOperand BrCond = DAG.getNode(ISD::BRCOND, MVT::Other, CopyTo, CMP,
1453 DAG.getBasicBlock(JT.Default));
1455 if (JT.MBB == NextBlock)
1456 DAG.setRoot(BrCond);
1458 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, BrCond,
1459 DAG.getBasicBlock(JT.MBB)));
1464 /// visitBitTestHeader - This function emits necessary code to produce value
1465 /// suitable for "bit tests"
1466 void SelectionDAGLowering::visitBitTestHeader(SelectionDAGISel::BitTestBlock &B) {
1467 // Subtract the minimum value
1468 SDOperand SwitchOp = getValue(B.SValue);
1469 MVT::ValueType VT = SwitchOp.getValueType();
1470 SDOperand SUB = DAG.getNode(ISD::SUB, VT, SwitchOp,
1471 DAG.getConstant(B.First, VT));
1474 SDOperand RangeCmp = DAG.getSetCC(TLI.getSetCCResultTy(), SUB,
1475 DAG.getConstant(B.Range, VT),
1479 if (MVT::getSizeInBits(VT) > MVT::getSizeInBits(TLI.getShiftAmountTy()))
1480 ShiftOp = DAG.getNode(ISD::TRUNCATE, TLI.getShiftAmountTy(), SUB);
1482 ShiftOp = DAG.getNode(ISD::ZERO_EXTEND, TLI.getShiftAmountTy(), SUB);
1484 // Make desired shift
1485 SDOperand SwitchVal = DAG.getNode(ISD::SHL, TLI.getPointerTy(),
1486 DAG.getConstant(1, TLI.getPointerTy()),
1489 unsigned SwitchReg = FuncInfo.MakeReg(TLI.getPointerTy());
1490 SDOperand CopyTo = DAG.getCopyToReg(getRoot(), SwitchReg, SwitchVal);
1493 SDOperand BrRange = DAG.getNode(ISD::BRCOND, MVT::Other, CopyTo, RangeCmp,
1494 DAG.getBasicBlock(B.Default));
1496 // Set NextBlock to be the MBB immediately after the current one, if any.
1497 // This is used to avoid emitting unnecessary branches to the next block.
1498 MachineBasicBlock *NextBlock = 0;
1499 MachineFunction::iterator BBI = CurMBB;
1500 if (++BBI != CurMBB->getParent()->end())
1503 MachineBasicBlock* MBB = B.Cases[0].ThisBB;
1504 if (MBB == NextBlock)
1505 DAG.setRoot(BrRange);
1507 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, CopyTo,
1508 DAG.getBasicBlock(MBB)));
1510 CurMBB->addSuccessor(B.Default);
1511 CurMBB->addSuccessor(MBB);
1516 /// visitBitTestCase - this function produces one "bit test"
1517 void SelectionDAGLowering::visitBitTestCase(MachineBasicBlock* NextMBB,
1519 SelectionDAGISel::BitTestCase &B) {
1520 // Emit bit tests and jumps
1521 SDOperand SwitchVal = DAG.getCopyFromReg(getRoot(), Reg, TLI.getPointerTy());
1523 SDOperand AndOp = DAG.getNode(ISD::AND, TLI.getPointerTy(),
1525 DAG.getConstant(B.Mask,
1526 TLI.getPointerTy()));
1527 SDOperand AndCmp = DAG.getSetCC(TLI.getSetCCResultTy(), AndOp,
1528 DAG.getConstant(0, TLI.getPointerTy()),
1530 SDOperand BrAnd = DAG.getNode(ISD::BRCOND, MVT::Other, getRoot(),
1531 AndCmp, DAG.getBasicBlock(B.TargetBB));
1533 // Set NextBlock to be the MBB immediately after the current one, if any.
1534 // This is used to avoid emitting unnecessary branches to the next block.
1535 MachineBasicBlock *NextBlock = 0;
1536 MachineFunction::iterator BBI = CurMBB;
1537 if (++BBI != CurMBB->getParent()->end())
1540 if (NextMBB == NextBlock)
1543 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, BrAnd,
1544 DAG.getBasicBlock(NextMBB)));
1546 CurMBB->addSuccessor(B.TargetBB);
1547 CurMBB->addSuccessor(NextMBB);
1552 void SelectionDAGLowering::visitInvoke(InvokeInst &I) {
1553 // Retrieve successors.
1554 MachineBasicBlock *Return = FuncInfo.MBBMap[I.getSuccessor(0)];
1555 MachineBasicBlock *LandingPad = FuncInfo.MBBMap[I.getSuccessor(1)];
1557 if (isa<InlineAsm>(I.getCalledValue()))
1560 LowerCallTo(&I, getValue(I.getOperand(0)), false, LandingPad);
1562 // If the value of the invoke is used outside of its defining block, make it
1563 // available as a virtual register.
1564 if (!I.use_empty()) {
1565 DenseMap<const Value*, unsigned>::iterator VMI = FuncInfo.ValueMap.find(&I);
1566 if (VMI != FuncInfo.ValueMap.end())
1567 DAG.setRoot(CopyValueToVirtualRegister(&I, VMI->second));
1570 // Drop into normal successor.
1571 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, getRoot(),
1572 DAG.getBasicBlock(Return)));
1574 // Update successor info
1575 CurMBB->addSuccessor(Return);
1576 CurMBB->addSuccessor(LandingPad);
1579 void SelectionDAGLowering::visitUnwind(UnwindInst &I) {
1582 /// handleSmallSwitchCaseRange - Emit a series of specific tests (suitable for
1583 /// small case ranges).
1584 bool SelectionDAGLowering::handleSmallSwitchRange(CaseRec& CR,
1585 CaseRecVector& WorkList,
1587 MachineBasicBlock* Default) {
1588 Case& BackCase = *(CR.Range.second-1);
1590 // Size is the number of Cases represented by this range.
1591 unsigned Size = CR.Range.second - CR.Range.first;
1595 // Get the MachineFunction which holds the current MBB. This is used when
1596 // inserting any additional MBBs necessary to represent the switch.
1597 MachineFunction *CurMF = CurMBB->getParent();
1599 // Figure out which block is immediately after the current one.
1600 MachineBasicBlock *NextBlock = 0;
1601 MachineFunction::iterator BBI = CR.CaseBB;
1603 if (++BBI != CurMBB->getParent()->end())
1606 // TODO: If any two of the cases has the same destination, and if one value
1607 // is the same as the other, but has one bit unset that the other has set,
1608 // use bit manipulation to do two compares at once. For example:
1609 // "if (X == 6 || X == 4)" -> "if ((X|2) == 6)"
1611 // Rearrange the case blocks so that the last one falls through if possible.
1612 if (NextBlock && Default != NextBlock && BackCase.BB != NextBlock) {
1613 // The last case block won't fall through into 'NextBlock' if we emit the
1614 // branches in this order. See if rearranging a case value would help.
1615 for (CaseItr I = CR.Range.first, E = CR.Range.second-1; I != E; ++I) {
1616 if (I->BB == NextBlock) {
1617 std::swap(*I, BackCase);
1623 // Create a CaseBlock record representing a conditional branch to
1624 // the Case's target mbb if the value being switched on SV is equal
1626 MachineBasicBlock *CurBlock = CR.CaseBB;
1627 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++I) {
1628 MachineBasicBlock *FallThrough;
1630 FallThrough = new MachineBasicBlock(CurBlock->getBasicBlock());
1631 CurMF->getBasicBlockList().insert(BBI, FallThrough);
1633 // If the last case doesn't match, go to the default block.
1634 FallThrough = Default;
1637 Value *RHS, *LHS, *MHS;
1639 if (I->High == I->Low) {
1640 // This is just small small case range :) containing exactly 1 case
1642 LHS = SV; RHS = I->High; MHS = NULL;
1645 LHS = I->Low; MHS = SV; RHS = I->High;
1647 SelectionDAGISel::CaseBlock CB(CC, LHS, RHS, MHS,
1648 I->BB, FallThrough, CurBlock);
1650 // If emitting the first comparison, just call visitSwitchCase to emit the
1651 // code into the current block. Otherwise, push the CaseBlock onto the
1652 // vector to be later processed by SDISel, and insert the node's MBB
1653 // before the next MBB.
1654 if (CurBlock == CurMBB)
1655 visitSwitchCase(CB);
1657 SwitchCases.push_back(CB);
1659 CurBlock = FallThrough;
1665 static inline bool areJTsAllowed(const TargetLowering &TLI) {
1666 return (TLI.isOperationLegal(ISD::BR_JT, MVT::Other) ||
1667 TLI.isOperationLegal(ISD::BRIND, MVT::Other));
1670 /// handleJTSwitchCase - Emit jumptable for current switch case range
1671 bool SelectionDAGLowering::handleJTSwitchCase(CaseRec& CR,
1672 CaseRecVector& WorkList,
1674 MachineBasicBlock* Default) {
1675 Case& FrontCase = *CR.Range.first;
1676 Case& BackCase = *(CR.Range.second-1);
1678 int64_t First = cast<ConstantInt>(FrontCase.Low)->getSExtValue();
1679 int64_t Last = cast<ConstantInt>(BackCase.High)->getSExtValue();
1682 for (CaseItr I = CR.Range.first, E = CR.Range.second;
1686 if (!areJTsAllowed(TLI) || TSize <= 3)
1689 double Density = (double)TSize / (double)((Last - First) + 1ULL);
1693 DOUT << "Lowering jump table\n"
1694 << "First entry: " << First << ". Last entry: " << Last << "\n"
1695 << "Size: " << TSize << ". Density: " << Density << "\n\n";
1697 // Get the MachineFunction which holds the current MBB. This is used when
1698 // inserting any additional MBBs necessary to represent the switch.
1699 MachineFunction *CurMF = CurMBB->getParent();
1701 // Figure out which block is immediately after the current one.
1702 MachineBasicBlock *NextBlock = 0;
1703 MachineFunction::iterator BBI = CR.CaseBB;
1705 if (++BBI != CurMBB->getParent()->end())
1708 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
1710 // Create a new basic block to hold the code for loading the address
1711 // of the jump table, and jumping to it. Update successor information;
1712 // we will either branch to the default case for the switch, or the jump
1714 MachineBasicBlock *JumpTableBB = new MachineBasicBlock(LLVMBB);
1715 CurMF->getBasicBlockList().insert(BBI, JumpTableBB);
1716 CR.CaseBB->addSuccessor(Default);
1717 CR.CaseBB->addSuccessor(JumpTableBB);
1719 // Build a vector of destination BBs, corresponding to each target
1720 // of the jump table. If the value of the jump table slot corresponds to
1721 // a case statement, push the case's BB onto the vector, otherwise, push
1723 std::vector<MachineBasicBlock*> DestBBs;
1724 int64_t TEI = First;
1725 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++TEI) {
1726 int64_t Low = cast<ConstantInt>(I->Low)->getSExtValue();
1727 int64_t High = cast<ConstantInt>(I->High)->getSExtValue();
1729 if ((Low <= TEI) && (TEI <= High)) {
1730 DestBBs.push_back(I->BB);
1734 DestBBs.push_back(Default);
1738 // Update successor info. Add one edge to each unique successor.
1739 BitVector SuccsHandled(CR.CaseBB->getParent()->getNumBlockIDs());
1740 for (std::vector<MachineBasicBlock*>::iterator I = DestBBs.begin(),
1741 E = DestBBs.end(); I != E; ++I) {
1742 if (!SuccsHandled[(*I)->getNumber()]) {
1743 SuccsHandled[(*I)->getNumber()] = true;
1744 JumpTableBB->addSuccessor(*I);
1748 // Create a jump table index for this jump table, or return an existing
1750 unsigned JTI = CurMF->getJumpTableInfo()->getJumpTableIndex(DestBBs);
1752 // Set the jump table information so that we can codegen it as a second
1753 // MachineBasicBlock
1754 SelectionDAGISel::JumpTable JT(-1U, JTI, JumpTableBB, Default);
1755 SelectionDAGISel::JumpTableHeader JTH(First, Last, SV, CR.CaseBB,
1756 (CR.CaseBB == CurMBB));
1757 if (CR.CaseBB == CurMBB)
1758 visitJumpTableHeader(JT, JTH);
1760 JTCases.push_back(SelectionDAGISel::JumpTableBlock(JTH, JT));
1765 /// handleBTSplitSwitchCase - emit comparison and split binary search tree into
1767 bool SelectionDAGLowering::handleBTSplitSwitchCase(CaseRec& CR,
1768 CaseRecVector& WorkList,
1770 MachineBasicBlock* Default) {
1771 // Get the MachineFunction which holds the current MBB. This is used when
1772 // inserting any additional MBBs necessary to represent the switch.
1773 MachineFunction *CurMF = CurMBB->getParent();
1775 // Figure out which block is immediately after the current one.
1776 MachineBasicBlock *NextBlock = 0;
1777 MachineFunction::iterator BBI = CR.CaseBB;
1779 if (++BBI != CurMBB->getParent()->end())
1782 Case& FrontCase = *CR.Range.first;
1783 Case& BackCase = *(CR.Range.second-1);
1784 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
1786 // Size is the number of Cases represented by this range.
1787 unsigned Size = CR.Range.second - CR.Range.first;
1789 int64_t First = cast<ConstantInt>(FrontCase.Low)->getSExtValue();
1790 int64_t Last = cast<ConstantInt>(BackCase.High)->getSExtValue();
1792 CaseItr Pivot = CR.Range.first + Size/2;
1794 // Select optimal pivot, maximizing sum density of LHS and RHS. This will
1795 // (heuristically) allow us to emit JumpTable's later.
1797 for (CaseItr I = CR.Range.first, E = CR.Range.second;
1801 uint64_t LSize = FrontCase.size();
1802 uint64_t RSize = TSize-LSize;
1803 DOUT << "Selecting best pivot: \n"
1804 << "First: " << First << ", Last: " << Last <<"\n"
1805 << "LSize: " << LSize << ", RSize: " << RSize << "\n";
1806 for (CaseItr I = CR.Range.first, J=I+1, E = CR.Range.second;
1808 int64_t LEnd = cast<ConstantInt>(I->High)->getSExtValue();
1809 int64_t RBegin = cast<ConstantInt>(J->Low)->getSExtValue();
1810 assert((RBegin-LEnd>=1) && "Invalid case distance");
1811 double LDensity = (double)LSize / (double)((LEnd - First) + 1ULL);
1812 double RDensity = (double)RSize / (double)((Last - RBegin) + 1ULL);
1813 double Metric = Log2_64(RBegin-LEnd)*(LDensity+RDensity);
1814 // Should always split in some non-trivial place
1816 << "LEnd: " << LEnd << ", RBegin: " << RBegin << "\n"
1817 << "LDensity: " << LDensity << ", RDensity: " << RDensity << "\n"
1818 << "Metric: " << Metric << "\n";
1819 if (FMetric < Metric) {
1822 DOUT << "Current metric set to: " << FMetric << "\n";
1828 if (areJTsAllowed(TLI)) {
1829 // If our case is dense we *really* should handle it earlier!
1830 assert((FMetric > 0) && "Should handle dense range earlier!");
1832 Pivot = CR.Range.first + Size/2;
1835 CaseRange LHSR(CR.Range.first, Pivot);
1836 CaseRange RHSR(Pivot, CR.Range.second);
1837 Constant *C = Pivot->Low;
1838 MachineBasicBlock *FalseBB = 0, *TrueBB = 0;
1840 // We know that we branch to the LHS if the Value being switched on is
1841 // less than the Pivot value, C. We use this to optimize our binary
1842 // tree a bit, by recognizing that if SV is greater than or equal to the
1843 // LHS's Case Value, and that Case Value is exactly one less than the
1844 // Pivot's Value, then we can branch directly to the LHS's Target,
1845 // rather than creating a leaf node for it.
1846 if ((LHSR.second - LHSR.first) == 1 &&
1847 LHSR.first->High == CR.GE &&
1848 cast<ConstantInt>(C)->getSExtValue() ==
1849 (cast<ConstantInt>(CR.GE)->getSExtValue() + 1LL)) {
1850 TrueBB = LHSR.first->BB;
1852 TrueBB = new MachineBasicBlock(LLVMBB);
1853 CurMF->getBasicBlockList().insert(BBI, TrueBB);
1854 WorkList.push_back(CaseRec(TrueBB, C, CR.GE, LHSR));
1857 // Similar to the optimization above, if the Value being switched on is
1858 // known to be less than the Constant CR.LT, and the current Case Value
1859 // is CR.LT - 1, then we can branch directly to the target block for
1860 // the current Case Value, rather than emitting a RHS leaf node for it.
1861 if ((RHSR.second - RHSR.first) == 1 && CR.LT &&
1862 cast<ConstantInt>(RHSR.first->Low)->getSExtValue() ==
1863 (cast<ConstantInt>(CR.LT)->getSExtValue() - 1LL)) {
1864 FalseBB = RHSR.first->BB;
1866 FalseBB = new MachineBasicBlock(LLVMBB);
1867 CurMF->getBasicBlockList().insert(BBI, FalseBB);
1868 WorkList.push_back(CaseRec(FalseBB,CR.LT,C,RHSR));
1871 // Create a CaseBlock record representing a conditional branch to
1872 // the LHS node if the value being switched on SV is less than C.
1873 // Otherwise, branch to LHS.
1874 SelectionDAGISel::CaseBlock CB(ISD::SETLT, SV, C, NULL,
1875 TrueBB, FalseBB, CR.CaseBB);
1877 if (CR.CaseBB == CurMBB)
1878 visitSwitchCase(CB);
1880 SwitchCases.push_back(CB);
1885 /// handleBitTestsSwitchCase - if current case range has few destination and
1886 /// range span less, than machine word bitwidth, encode case range into series
1887 /// of masks and emit bit tests with these masks.
1888 bool SelectionDAGLowering::handleBitTestsSwitchCase(CaseRec& CR,
1889 CaseRecVector& WorkList,
1891 MachineBasicBlock* Default){
1892 unsigned IntPtrBits = MVT::getSizeInBits(TLI.getPointerTy());
1894 Case& FrontCase = *CR.Range.first;
1895 Case& BackCase = *(CR.Range.second-1);
1897 // Get the MachineFunction which holds the current MBB. This is used when
1898 // inserting any additional MBBs necessary to represent the switch.
1899 MachineFunction *CurMF = CurMBB->getParent();
1901 unsigned numCmps = 0;
1902 for (CaseItr I = CR.Range.first, E = CR.Range.second;
1904 // Single case counts one, case range - two.
1905 if (I->Low == I->High)
1911 // Count unique destinations
1912 SmallSet<MachineBasicBlock*, 4> Dests;
1913 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) {
1914 Dests.insert(I->BB);
1915 if (Dests.size() > 3)
1916 // Don't bother the code below, if there are too much unique destinations
1919 DOUT << "Total number of unique destinations: " << Dests.size() << "\n"
1920 << "Total number of comparisons: " << numCmps << "\n";
1922 // Compute span of values.
1923 Constant* minValue = FrontCase.Low;
1924 Constant* maxValue = BackCase.High;
1925 uint64_t range = cast<ConstantInt>(maxValue)->getSExtValue() -
1926 cast<ConstantInt>(minValue)->getSExtValue();
1927 DOUT << "Compare range: " << range << "\n"
1928 << "Low bound: " << cast<ConstantInt>(minValue)->getSExtValue() << "\n"
1929 << "High bound: " << cast<ConstantInt>(maxValue)->getSExtValue() << "\n";
1931 if (range>=IntPtrBits ||
1932 (!(Dests.size() == 1 && numCmps >= 3) &&
1933 !(Dests.size() == 2 && numCmps >= 5) &&
1934 !(Dests.size() >= 3 && numCmps >= 6)))
1937 DOUT << "Emitting bit tests\n";
1938 int64_t lowBound = 0;
1940 // Optimize the case where all the case values fit in a
1941 // word without having to subtract minValue. In this case,
1942 // we can optimize away the subtraction.
1943 if (cast<ConstantInt>(minValue)->getSExtValue() >= 0 &&
1944 cast<ConstantInt>(maxValue)->getSExtValue() < IntPtrBits) {
1945 range = cast<ConstantInt>(maxValue)->getSExtValue();
1947 lowBound = cast<ConstantInt>(minValue)->getSExtValue();
1950 CaseBitsVector CasesBits;
1951 unsigned i, count = 0;
1953 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) {
1954 MachineBasicBlock* Dest = I->BB;
1955 for (i = 0; i < count; ++i)
1956 if (Dest == CasesBits[i].BB)
1960 assert((count < 3) && "Too much destinations to test!");
1961 CasesBits.push_back(CaseBits(0, Dest, 0));
1965 uint64_t lo = cast<ConstantInt>(I->Low)->getSExtValue() - lowBound;
1966 uint64_t hi = cast<ConstantInt>(I->High)->getSExtValue() - lowBound;
1968 for (uint64_t j = lo; j <= hi; j++) {
1969 CasesBits[i].Mask |= 1ULL << j;
1970 CasesBits[i].Bits++;
1974 std::sort(CasesBits.begin(), CasesBits.end(), CaseBitsCmp());
1976 SelectionDAGISel::BitTestInfo BTC;
1978 // Figure out which block is immediately after the current one.
1979 MachineFunction::iterator BBI = CR.CaseBB;
1982 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
1985 for (unsigned i = 0, e = CasesBits.size(); i!=e; ++i) {
1986 DOUT << "Mask: " << CasesBits[i].Mask << ", Bits: " << CasesBits[i].Bits
1987 << ", BB: " << CasesBits[i].BB << "\n";
1989 MachineBasicBlock *CaseBB = new MachineBasicBlock(LLVMBB);
1990 CurMF->getBasicBlockList().insert(BBI, CaseBB);
1991 BTC.push_back(SelectionDAGISel::BitTestCase(CasesBits[i].Mask,
1996 SelectionDAGISel::BitTestBlock BTB(lowBound, range, SV,
1997 -1U, (CR.CaseBB == CurMBB),
1998 CR.CaseBB, Default, BTC);
2000 if (CR.CaseBB == CurMBB)
2001 visitBitTestHeader(BTB);
2003 BitTestCases.push_back(BTB);
2009 // Clusterify - Transform simple list of Cases into list of CaseRange's
2010 unsigned SelectionDAGLowering::Clusterify(CaseVector& Cases,
2011 const SwitchInst& SI) {
2012 unsigned numCmps = 0;
2014 // Start with "simple" cases
2015 for (unsigned i = 1; i < SI.getNumSuccessors(); ++i) {
2016 MachineBasicBlock *SMBB = FuncInfo.MBBMap[SI.getSuccessor(i)];
2017 Cases.push_back(Case(SI.getSuccessorValue(i),
2018 SI.getSuccessorValue(i),
2021 std::sort(Cases.begin(), Cases.end(), CaseCmp());
2023 // Merge case into clusters
2024 if (Cases.size()>=2)
2025 // Must recompute end() each iteration because it may be
2026 // invalidated by erase if we hold on to it
2027 for (CaseItr I=Cases.begin(), J=++(Cases.begin()); J!=Cases.end(); ) {
2028 int64_t nextValue = cast<ConstantInt>(J->Low)->getSExtValue();
2029 int64_t currentValue = cast<ConstantInt>(I->High)->getSExtValue();
2030 MachineBasicBlock* nextBB = J->BB;
2031 MachineBasicBlock* currentBB = I->BB;
2033 // If the two neighboring cases go to the same destination, merge them
2034 // into a single case.
2035 if ((nextValue-currentValue==1) && (currentBB == nextBB)) {
2043 for (CaseItr I=Cases.begin(), E=Cases.end(); I!=E; ++I, ++numCmps) {
2044 if (I->Low != I->High)
2045 // A range counts double, since it requires two compares.
2052 void SelectionDAGLowering::visitSwitch(SwitchInst &SI) {
2053 // Figure out which block is immediately after the current one.
2054 MachineBasicBlock *NextBlock = 0;
2055 MachineFunction::iterator BBI = CurMBB;
2057 MachineBasicBlock *Default = FuncInfo.MBBMap[SI.getDefaultDest()];
2059 // If there is only the default destination, branch to it if it is not the
2060 // next basic block. Otherwise, just fall through.
2061 if (SI.getNumOperands() == 2) {
2062 // Update machine-CFG edges.
2064 // If this is not a fall-through branch, emit the branch.
2065 if (Default != NextBlock)
2066 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, getRoot(),
2067 DAG.getBasicBlock(Default)));
2069 CurMBB->addSuccessor(Default);
2073 // If there are any non-default case statements, create a vector of Cases
2074 // representing each one, and sort the vector so that we can efficiently
2075 // create a binary search tree from them.
2077 unsigned numCmps = Clusterify(Cases, SI);
2078 DOUT << "Clusterify finished. Total clusters: " << Cases.size()
2079 << ". Total compares: " << numCmps << "\n";
2081 // Get the Value to be switched on and default basic blocks, which will be
2082 // inserted into CaseBlock records, representing basic blocks in the binary
2084 Value *SV = SI.getOperand(0);
2086 // Push the initial CaseRec onto the worklist
2087 CaseRecVector WorkList;
2088 WorkList.push_back(CaseRec(CurMBB,0,0,CaseRange(Cases.begin(),Cases.end())));
2090 while (!WorkList.empty()) {
2091 // Grab a record representing a case range to process off the worklist
2092 CaseRec CR = WorkList.back();
2093 WorkList.pop_back();
2095 if (handleBitTestsSwitchCase(CR, WorkList, SV, Default))
2098 // If the range has few cases (two or less) emit a series of specific
2100 if (handleSmallSwitchRange(CR, WorkList, SV, Default))
2103 // If the switch has more than 5 blocks, and at least 40% dense, and the
2104 // target supports indirect branches, then emit a jump table rather than
2105 // lowering the switch to a binary tree of conditional branches.
2106 if (handleJTSwitchCase(CR, WorkList, SV, Default))
2109 // Emit binary tree. We need to pick a pivot, and push left and right ranges
2110 // onto the worklist. Leafs are handled via handleSmallSwitchRange() call.
2111 handleBTSplitSwitchCase(CR, WorkList, SV, Default);
2116 void SelectionDAGLowering::visitSub(User &I) {
2117 // -0.0 - X --> fneg
2118 const Type *Ty = I.getType();
2119 if (isa<VectorType>(Ty)) {
2120 if (ConstantVector *CV = dyn_cast<ConstantVector>(I.getOperand(0))) {
2121 const VectorType *DestTy = cast<VectorType>(I.getType());
2122 const Type *ElTy = DestTy->getElementType();
2123 if (ElTy->isFloatingPoint()) {
2124 unsigned VL = DestTy->getNumElements();
2125 std::vector<Constant*> NZ(VL, ConstantFP::getNegativeZero(ElTy));
2126 Constant *CNZ = ConstantVector::get(&NZ[0], NZ.size());
2128 SDOperand Op2 = getValue(I.getOperand(1));
2129 setValue(&I, DAG.getNode(ISD::FNEG, Op2.getValueType(), Op2));
2135 if (Ty->isFloatingPoint()) {
2136 if (ConstantFP *CFP = dyn_cast<ConstantFP>(I.getOperand(0)))
2137 if (CFP->isExactlyValue(ConstantFP::getNegativeZero(Ty)->getValueAPF())) {
2138 SDOperand Op2 = getValue(I.getOperand(1));
2139 setValue(&I, DAG.getNode(ISD::FNEG, Op2.getValueType(), Op2));
2144 visitBinary(I, Ty->isFPOrFPVector() ? ISD::FSUB : ISD::SUB);
2147 void SelectionDAGLowering::visitBinary(User &I, unsigned OpCode) {
2148 SDOperand Op1 = getValue(I.getOperand(0));
2149 SDOperand Op2 = getValue(I.getOperand(1));
2151 setValue(&I, DAG.getNode(OpCode, Op1.getValueType(), Op1, Op2));
2154 void SelectionDAGLowering::visitShift(User &I, unsigned Opcode) {
2155 SDOperand Op1 = getValue(I.getOperand(0));
2156 SDOperand Op2 = getValue(I.getOperand(1));
2158 if (MVT::getSizeInBits(TLI.getShiftAmountTy()) <
2159 MVT::getSizeInBits(Op2.getValueType()))
2160 Op2 = DAG.getNode(ISD::TRUNCATE, TLI.getShiftAmountTy(), Op2);
2161 else if (TLI.getShiftAmountTy() > Op2.getValueType())
2162 Op2 = DAG.getNode(ISD::ANY_EXTEND, TLI.getShiftAmountTy(), Op2);
2164 setValue(&I, DAG.getNode(Opcode, Op1.getValueType(), Op1, Op2));
2167 void SelectionDAGLowering::visitICmp(User &I) {
2168 ICmpInst::Predicate predicate = ICmpInst::BAD_ICMP_PREDICATE;
2169 if (ICmpInst *IC = dyn_cast<ICmpInst>(&I))
2170 predicate = IC->getPredicate();
2171 else if (ConstantExpr *IC = dyn_cast<ConstantExpr>(&I))
2172 predicate = ICmpInst::Predicate(IC->getPredicate());
2173 SDOperand Op1 = getValue(I.getOperand(0));
2174 SDOperand Op2 = getValue(I.getOperand(1));
2175 ISD::CondCode Opcode;
2176 switch (predicate) {
2177 case ICmpInst::ICMP_EQ : Opcode = ISD::SETEQ; break;
2178 case ICmpInst::ICMP_NE : Opcode = ISD::SETNE; break;
2179 case ICmpInst::ICMP_UGT : Opcode = ISD::SETUGT; break;
2180 case ICmpInst::ICMP_UGE : Opcode = ISD::SETUGE; break;
2181 case ICmpInst::ICMP_ULT : Opcode = ISD::SETULT; break;
2182 case ICmpInst::ICMP_ULE : Opcode = ISD::SETULE; break;
2183 case ICmpInst::ICMP_SGT : Opcode = ISD::SETGT; break;
2184 case ICmpInst::ICMP_SGE : Opcode = ISD::SETGE; break;
2185 case ICmpInst::ICMP_SLT : Opcode = ISD::SETLT; break;
2186 case ICmpInst::ICMP_SLE : Opcode = ISD::SETLE; break;
2188 assert(!"Invalid ICmp predicate value");
2189 Opcode = ISD::SETEQ;
2192 setValue(&I, DAG.getSetCC(MVT::i1, Op1, Op2, Opcode));
2195 void SelectionDAGLowering::visitFCmp(User &I) {
2196 FCmpInst::Predicate predicate = FCmpInst::BAD_FCMP_PREDICATE;
2197 if (FCmpInst *FC = dyn_cast<FCmpInst>(&I))
2198 predicate = FC->getPredicate();
2199 else if (ConstantExpr *FC = dyn_cast<ConstantExpr>(&I))
2200 predicate = FCmpInst::Predicate(FC->getPredicate());
2201 SDOperand Op1 = getValue(I.getOperand(0));
2202 SDOperand Op2 = getValue(I.getOperand(1));
2203 ISD::CondCode Condition, FOC, FPC;
2204 switch (predicate) {
2205 case FCmpInst::FCMP_FALSE: FOC = FPC = ISD::SETFALSE; break;
2206 case FCmpInst::FCMP_OEQ: FOC = ISD::SETEQ; FPC = ISD::SETOEQ; break;
2207 case FCmpInst::FCMP_OGT: FOC = ISD::SETGT; FPC = ISD::SETOGT; break;
2208 case FCmpInst::FCMP_OGE: FOC = ISD::SETGE; FPC = ISD::SETOGE; break;
2209 case FCmpInst::FCMP_OLT: FOC = ISD::SETLT; FPC = ISD::SETOLT; break;
2210 case FCmpInst::FCMP_OLE: FOC = ISD::SETLE; FPC = ISD::SETOLE; break;
2211 case FCmpInst::FCMP_ONE: FOC = ISD::SETNE; FPC = ISD::SETONE; break;
2212 case FCmpInst::FCMP_ORD: FOC = ISD::SETEQ; FPC = ISD::SETO; break;
2213 case FCmpInst::FCMP_UNO: FOC = ISD::SETNE; FPC = ISD::SETUO; break;
2214 case FCmpInst::FCMP_UEQ: FOC = ISD::SETEQ; FPC = ISD::SETUEQ; break;
2215 case FCmpInst::FCMP_UGT: FOC = ISD::SETGT; FPC = ISD::SETUGT; break;
2216 case FCmpInst::FCMP_UGE: FOC = ISD::SETGE; FPC = ISD::SETUGE; break;
2217 case FCmpInst::FCMP_ULT: FOC = ISD::SETLT; FPC = ISD::SETULT; break;
2218 case FCmpInst::FCMP_ULE: FOC = ISD::SETLE; FPC = ISD::SETULE; break;
2219 case FCmpInst::FCMP_UNE: FOC = ISD::SETNE; FPC = ISD::SETUNE; break;
2220 case FCmpInst::FCMP_TRUE: FOC = FPC = ISD::SETTRUE; break;
2222 assert(!"Invalid FCmp predicate value");
2223 FOC = FPC = ISD::SETFALSE;
2226 if (FiniteOnlyFPMath())
2230 setValue(&I, DAG.getSetCC(MVT::i1, Op1, Op2, Condition));
2233 void SelectionDAGLowering::visitSelect(User &I) {
2234 SDOperand Cond = getValue(I.getOperand(0));
2235 SDOperand TrueVal = getValue(I.getOperand(1));
2236 SDOperand FalseVal = getValue(I.getOperand(2));
2237 setValue(&I, DAG.getNode(ISD::SELECT, TrueVal.getValueType(), Cond,
2238 TrueVal, FalseVal));
2242 void SelectionDAGLowering::visitTrunc(User &I) {
2243 // TruncInst cannot be a no-op cast because sizeof(src) > sizeof(dest).
2244 SDOperand N = getValue(I.getOperand(0));
2245 MVT::ValueType DestVT = TLI.getValueType(I.getType());
2246 setValue(&I, DAG.getNode(ISD::TRUNCATE, DestVT, N));
2249 void SelectionDAGLowering::visitZExt(User &I) {
2250 // ZExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
2251 // ZExt also can't be a cast to bool for same reason. So, nothing much to do
2252 SDOperand N = getValue(I.getOperand(0));
2253 MVT::ValueType DestVT = TLI.getValueType(I.getType());
2254 setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, DestVT, N));
2257 void SelectionDAGLowering::visitSExt(User &I) {
2258 // SExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
2259 // SExt also can't be a cast to bool for same reason. So, nothing much to do
2260 SDOperand N = getValue(I.getOperand(0));
2261 MVT::ValueType DestVT = TLI.getValueType(I.getType());
2262 setValue(&I, DAG.getNode(ISD::SIGN_EXTEND, DestVT, N));
2265 void SelectionDAGLowering::visitFPTrunc(User &I) {
2266 // FPTrunc is never a no-op cast, no need to check
2267 SDOperand N = getValue(I.getOperand(0));
2268 MVT::ValueType DestVT = TLI.getValueType(I.getType());
2269 setValue(&I, DAG.getNode(ISD::FP_ROUND, DestVT, N, DAG.getIntPtrConstant(0)));
2272 void SelectionDAGLowering::visitFPExt(User &I){
2273 // FPTrunc is never a no-op cast, no need to check
2274 SDOperand N = getValue(I.getOperand(0));
2275 MVT::ValueType DestVT = TLI.getValueType(I.getType());
2276 setValue(&I, DAG.getNode(ISD::FP_EXTEND, DestVT, N));
2279 void SelectionDAGLowering::visitFPToUI(User &I) {
2280 // FPToUI is never a no-op cast, no need to check
2281 SDOperand N = getValue(I.getOperand(0));
2282 MVT::ValueType DestVT = TLI.getValueType(I.getType());
2283 setValue(&I, DAG.getNode(ISD::FP_TO_UINT, DestVT, N));
2286 void SelectionDAGLowering::visitFPToSI(User &I) {
2287 // FPToSI is never a no-op cast, no need to check
2288 SDOperand N = getValue(I.getOperand(0));
2289 MVT::ValueType DestVT = TLI.getValueType(I.getType());
2290 setValue(&I, DAG.getNode(ISD::FP_TO_SINT, DestVT, N));
2293 void SelectionDAGLowering::visitUIToFP(User &I) {
2294 // UIToFP is never a no-op cast, no need to check
2295 SDOperand N = getValue(I.getOperand(0));
2296 MVT::ValueType DestVT = TLI.getValueType(I.getType());
2297 setValue(&I, DAG.getNode(ISD::UINT_TO_FP, DestVT, N));
2300 void SelectionDAGLowering::visitSIToFP(User &I){
2301 // UIToFP is never a no-op cast, no need to check
2302 SDOperand N = getValue(I.getOperand(0));
2303 MVT::ValueType DestVT = TLI.getValueType(I.getType());
2304 setValue(&I, DAG.getNode(ISD::SINT_TO_FP, DestVT, N));
2307 void SelectionDAGLowering::visitPtrToInt(User &I) {
2308 // What to do depends on the size of the integer and the size of the pointer.
2309 // We can either truncate, zero extend, or no-op, accordingly.
2310 SDOperand N = getValue(I.getOperand(0));
2311 MVT::ValueType SrcVT = N.getValueType();
2312 MVT::ValueType DestVT = TLI.getValueType(I.getType());
2314 if (MVT::getSizeInBits(DestVT) < MVT::getSizeInBits(SrcVT))
2315 Result = DAG.getNode(ISD::TRUNCATE, DestVT, N);
2317 // Note: ZERO_EXTEND can handle cases where the sizes are equal too
2318 Result = DAG.getNode(ISD::ZERO_EXTEND, DestVT, N);
2319 setValue(&I, Result);
2322 void SelectionDAGLowering::visitIntToPtr(User &I) {
2323 // What to do depends on the size of the integer and the size of the pointer.
2324 // We can either truncate, zero extend, or no-op, accordingly.
2325 SDOperand N = getValue(I.getOperand(0));
2326 MVT::ValueType SrcVT = N.getValueType();
2327 MVT::ValueType DestVT = TLI.getValueType(I.getType());
2328 if (MVT::getSizeInBits(DestVT) < MVT::getSizeInBits(SrcVT))
2329 setValue(&I, DAG.getNode(ISD::TRUNCATE, DestVT, N));
2331 // Note: ZERO_EXTEND can handle cases where the sizes are equal too
2332 setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, DestVT, N));
2335 void SelectionDAGLowering::visitBitCast(User &I) {
2336 SDOperand N = getValue(I.getOperand(0));
2337 MVT::ValueType DestVT = TLI.getValueType(I.getType());
2339 // BitCast assures us that source and destination are the same size so this
2340 // is either a BIT_CONVERT or a no-op.
2341 if (DestVT != N.getValueType())
2342 setValue(&I, DAG.getNode(ISD::BIT_CONVERT, DestVT, N)); // convert types
2344 setValue(&I, N); // noop cast.
2347 void SelectionDAGLowering::visitInsertElement(User &I) {
2348 SDOperand InVec = getValue(I.getOperand(0));
2349 SDOperand InVal = getValue(I.getOperand(1));
2350 SDOperand InIdx = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(),
2351 getValue(I.getOperand(2)));
2353 setValue(&I, DAG.getNode(ISD::INSERT_VECTOR_ELT,
2354 TLI.getValueType(I.getType()),
2355 InVec, InVal, InIdx));
2358 void SelectionDAGLowering::visitExtractElement(User &I) {
2359 SDOperand InVec = getValue(I.getOperand(0));
2360 SDOperand InIdx = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(),
2361 getValue(I.getOperand(1)));
2362 setValue(&I, DAG.getNode(ISD::EXTRACT_VECTOR_ELT,
2363 TLI.getValueType(I.getType()), InVec, InIdx));
2366 void SelectionDAGLowering::visitShuffleVector(User &I) {
2367 SDOperand V1 = getValue(I.getOperand(0));
2368 SDOperand V2 = getValue(I.getOperand(1));
2369 SDOperand Mask = getValue(I.getOperand(2));
2371 setValue(&I, DAG.getNode(ISD::VECTOR_SHUFFLE,
2372 TLI.getValueType(I.getType()),
2377 void SelectionDAGLowering::visitGetElementPtr(User &I) {
2378 SDOperand N = getValue(I.getOperand(0));
2379 const Type *Ty = I.getOperand(0)->getType();
2381 for (GetElementPtrInst::op_iterator OI = I.op_begin()+1, E = I.op_end();
2384 if (const StructType *StTy = dyn_cast<StructType>(Ty)) {
2385 unsigned Field = cast<ConstantInt>(Idx)->getZExtValue();
2388 uint64_t Offset = TD->getStructLayout(StTy)->getElementOffset(Field);
2389 N = DAG.getNode(ISD::ADD, N.getValueType(), N,
2390 DAG.getIntPtrConstant(Offset));
2392 Ty = StTy->getElementType(Field);
2394 Ty = cast<SequentialType>(Ty)->getElementType();
2396 // If this is a constant subscript, handle it quickly.
2397 if (ConstantInt *CI = dyn_cast<ConstantInt>(Idx)) {
2398 if (CI->getZExtValue() == 0) continue;
2400 TD->getABITypeSize(Ty)*cast<ConstantInt>(CI)->getSExtValue();
2401 N = DAG.getNode(ISD::ADD, N.getValueType(), N,
2402 DAG.getIntPtrConstant(Offs));
2406 // N = N + Idx * ElementSize;
2407 uint64_t ElementSize = TD->getABITypeSize(Ty);
2408 SDOperand IdxN = getValue(Idx);
2410 // If the index is smaller or larger than intptr_t, truncate or extend
2412 if (IdxN.getValueType() < N.getValueType()) {
2413 IdxN = DAG.getNode(ISD::SIGN_EXTEND, N.getValueType(), IdxN);
2414 } else if (IdxN.getValueType() > N.getValueType())
2415 IdxN = DAG.getNode(ISD::TRUNCATE, N.getValueType(), IdxN);
2417 // If this is a multiply by a power of two, turn it into a shl
2418 // immediately. This is a very common case.
2419 if (isPowerOf2_64(ElementSize)) {
2420 unsigned Amt = Log2_64(ElementSize);
2421 IdxN = DAG.getNode(ISD::SHL, N.getValueType(), IdxN,
2422 DAG.getConstant(Amt, TLI.getShiftAmountTy()));
2423 N = DAG.getNode(ISD::ADD, N.getValueType(), N, IdxN);
2427 SDOperand Scale = DAG.getIntPtrConstant(ElementSize);
2428 IdxN = DAG.getNode(ISD::MUL, N.getValueType(), IdxN, Scale);
2429 N = DAG.getNode(ISD::ADD, N.getValueType(), N, IdxN);
2435 void SelectionDAGLowering::visitAlloca(AllocaInst &I) {
2436 // If this is a fixed sized alloca in the entry block of the function,
2437 // allocate it statically on the stack.
2438 if (FuncInfo.StaticAllocaMap.count(&I))
2439 return; // getValue will auto-populate this.
2441 const Type *Ty = I.getAllocatedType();
2442 uint64_t TySize = TLI.getTargetData()->getABITypeSize(Ty);
2444 std::max((unsigned)TLI.getTargetData()->getPrefTypeAlignment(Ty),
2447 SDOperand AllocSize = getValue(I.getArraySize());
2448 MVT::ValueType IntPtr = TLI.getPointerTy();
2449 if (IntPtr < AllocSize.getValueType())
2450 AllocSize = DAG.getNode(ISD::TRUNCATE, IntPtr, AllocSize);
2451 else if (IntPtr > AllocSize.getValueType())
2452 AllocSize = DAG.getNode(ISD::ZERO_EXTEND, IntPtr, AllocSize);
2454 AllocSize = DAG.getNode(ISD::MUL, IntPtr, AllocSize,
2455 DAG.getIntPtrConstant(TySize));
2457 // Handle alignment. If the requested alignment is less than or equal to
2458 // the stack alignment, ignore it. If the size is greater than or equal to
2459 // the stack alignment, we note this in the DYNAMIC_STACKALLOC node.
2460 unsigned StackAlign =
2461 TLI.getTargetMachine().getFrameInfo()->getStackAlignment();
2462 if (Align <= StackAlign)
2465 // Round the size of the allocation up to the stack alignment size
2466 // by add SA-1 to the size.
2467 AllocSize = DAG.getNode(ISD::ADD, AllocSize.getValueType(), AllocSize,
2468 DAG.getIntPtrConstant(StackAlign-1));
2469 // Mask out the low bits for alignment purposes.
2470 AllocSize = DAG.getNode(ISD::AND, AllocSize.getValueType(), AllocSize,
2471 DAG.getIntPtrConstant(~(uint64_t)(StackAlign-1)));
2473 SDOperand Ops[] = { getRoot(), AllocSize, DAG.getIntPtrConstant(Align) };
2474 const MVT::ValueType *VTs = DAG.getNodeValueTypes(AllocSize.getValueType(),
2476 SDOperand DSA = DAG.getNode(ISD::DYNAMIC_STACKALLOC, VTs, 2, Ops, 3);
2478 DAG.setRoot(DSA.getValue(1));
2480 // Inform the Frame Information that we have just allocated a variable-sized
2482 CurMBB->getParent()->getFrameInfo()->CreateVariableSizedObject();
2485 void SelectionDAGLowering::visitLoad(LoadInst &I) {
2486 SDOperand Ptr = getValue(I.getOperand(0));
2492 // Do not serialize non-volatile loads against each other.
2493 Root = DAG.getRoot();
2496 setValue(&I, getLoadFrom(I.getType(), Ptr, I.getOperand(0),
2497 Root, I.isVolatile(), I.getAlignment()));
2500 SDOperand SelectionDAGLowering::getLoadFrom(const Type *Ty, SDOperand Ptr,
2501 const Value *SV, SDOperand Root,
2503 unsigned Alignment) {
2505 DAG.getLoad(TLI.getValueType(Ty), Root, Ptr, SV, 0,
2506 isVolatile, Alignment);
2509 DAG.setRoot(L.getValue(1));
2511 PendingLoads.push_back(L.getValue(1));
2517 void SelectionDAGLowering::visitStore(StoreInst &I) {
2518 Value *SrcV = I.getOperand(0);
2519 SDOperand Src = getValue(SrcV);
2520 SDOperand Ptr = getValue(I.getOperand(1));
2521 DAG.setRoot(DAG.getStore(getRoot(), Src, Ptr, I.getOperand(1), 0,
2522 I.isVolatile(), I.getAlignment()));
2525 /// visitTargetIntrinsic - Lower a call of a target intrinsic to an INTRINSIC
2527 void SelectionDAGLowering::visitTargetIntrinsic(CallInst &I,
2528 unsigned Intrinsic) {
2529 bool HasChain = !I.doesNotAccessMemory();
2530 bool OnlyLoad = HasChain && I.onlyReadsMemory();
2532 // Build the operand list.
2533 SmallVector<SDOperand, 8> Ops;
2534 if (HasChain) { // If this intrinsic has side-effects, chainify it.
2536 // We don't need to serialize loads against other loads.
2537 Ops.push_back(DAG.getRoot());
2539 Ops.push_back(getRoot());
2543 // Add the intrinsic ID as an integer operand.
2544 Ops.push_back(DAG.getConstant(Intrinsic, TLI.getPointerTy()));
2546 // Add all operands of the call to the operand list.
2547 for (unsigned i = 1, e = I.getNumOperands(); i != e; ++i) {
2548 SDOperand Op = getValue(I.getOperand(i));
2549 assert(TLI.isTypeLegal(Op.getValueType()) &&
2550 "Intrinsic uses a non-legal type?");
2554 std::vector<MVT::ValueType> VTs;
2555 if (I.getType() != Type::VoidTy) {
2556 MVT::ValueType VT = TLI.getValueType(I.getType());
2557 if (MVT::isVector(VT)) {
2558 const VectorType *DestTy = cast<VectorType>(I.getType());
2559 MVT::ValueType EltVT = TLI.getValueType(DestTy->getElementType());
2561 VT = MVT::getVectorType(EltVT, DestTy->getNumElements());
2562 assert(VT != MVT::Other && "Intrinsic uses a non-legal type?");
2565 assert(TLI.isTypeLegal(VT) && "Intrinsic uses a non-legal type?");
2569 VTs.push_back(MVT::Other);
2571 const MVT::ValueType *VTList = DAG.getNodeValueTypes(VTs);
2576 Result = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, VTList, VTs.size(),
2577 &Ops[0], Ops.size());
2578 else if (I.getType() != Type::VoidTy)
2579 Result = DAG.getNode(ISD::INTRINSIC_W_CHAIN, VTList, VTs.size(),
2580 &Ops[0], Ops.size());
2582 Result = DAG.getNode(ISD::INTRINSIC_VOID, VTList, VTs.size(),
2583 &Ops[0], Ops.size());
2586 SDOperand Chain = Result.getValue(Result.Val->getNumValues()-1);
2588 PendingLoads.push_back(Chain);
2592 if (I.getType() != Type::VoidTy) {
2593 if (const VectorType *PTy = dyn_cast<VectorType>(I.getType())) {
2594 MVT::ValueType VT = TLI.getValueType(PTy);
2595 Result = DAG.getNode(ISD::BIT_CONVERT, VT, Result);
2597 setValue(&I, Result);
2601 /// ExtractTypeInfo - Returns the type info, possibly bitcast, encoded in V.
2602 static GlobalVariable *ExtractTypeInfo (Value *V) {
2603 V = IntrinsicInst::StripPointerCasts(V);
2604 GlobalVariable *GV = dyn_cast<GlobalVariable>(V);
2605 assert ((GV || isa<ConstantPointerNull>(V)) &&
2606 "TypeInfo must be a global variable or NULL");
2610 /// addCatchInfo - Extract the personality and type infos from an eh.selector
2611 /// call, and add them to the specified machine basic block.
2612 static void addCatchInfo(CallInst &I, MachineModuleInfo *MMI,
2613 MachineBasicBlock *MBB) {
2614 // Inform the MachineModuleInfo of the personality for this landing pad.
2615 ConstantExpr *CE = cast<ConstantExpr>(I.getOperand(2));
2616 assert(CE->getOpcode() == Instruction::BitCast &&
2617 isa<Function>(CE->getOperand(0)) &&
2618 "Personality should be a function");
2619 MMI->addPersonality(MBB, cast<Function>(CE->getOperand(0)));
2621 // Gather all the type infos for this landing pad and pass them along to
2622 // MachineModuleInfo.
2623 std::vector<GlobalVariable *> TyInfo;
2624 unsigned N = I.getNumOperands();
2626 for (unsigned i = N - 1; i > 2; --i) {
2627 if (ConstantInt *CI = dyn_cast<ConstantInt>(I.getOperand(i))) {
2628 unsigned FilterLength = CI->getZExtValue();
2629 unsigned FirstCatch = i + FilterLength + !FilterLength;
2630 assert (FirstCatch <= N && "Invalid filter length");
2632 if (FirstCatch < N) {
2633 TyInfo.reserve(N - FirstCatch);
2634 for (unsigned j = FirstCatch; j < N; ++j)
2635 TyInfo.push_back(ExtractTypeInfo(I.getOperand(j)));
2636 MMI->addCatchTypeInfo(MBB, TyInfo);
2640 if (!FilterLength) {
2642 MMI->addCleanup(MBB);
2645 TyInfo.reserve(FilterLength - 1);
2646 for (unsigned j = i + 1; j < FirstCatch; ++j)
2647 TyInfo.push_back(ExtractTypeInfo(I.getOperand(j)));
2648 MMI->addFilterTypeInfo(MBB, TyInfo);
2657 TyInfo.reserve(N - 3);
2658 for (unsigned j = 3; j < N; ++j)
2659 TyInfo.push_back(ExtractTypeInfo(I.getOperand(j)));
2660 MMI->addCatchTypeInfo(MBB, TyInfo);
2664 /// visitIntrinsicCall - Lower the call to the specified intrinsic function. If
2665 /// we want to emit this as a call to a named external function, return the name
2666 /// otherwise lower it and return null.
2668 SelectionDAGLowering::visitIntrinsicCall(CallInst &I, unsigned Intrinsic) {
2669 switch (Intrinsic) {
2671 // By default, turn this into a target intrinsic node.
2672 visitTargetIntrinsic(I, Intrinsic);
2674 case Intrinsic::vastart: visitVAStart(I); return 0;
2675 case Intrinsic::vaend: visitVAEnd(I); return 0;
2676 case Intrinsic::vacopy: visitVACopy(I); return 0;
2677 case Intrinsic::returnaddress:
2678 setValue(&I, DAG.getNode(ISD::RETURNADDR, TLI.getPointerTy(),
2679 getValue(I.getOperand(1))));
2681 case Intrinsic::frameaddress:
2682 setValue(&I, DAG.getNode(ISD::FRAMEADDR, TLI.getPointerTy(),
2683 getValue(I.getOperand(1))));
2685 case Intrinsic::setjmp:
2686 return "_setjmp"+!TLI.usesUnderscoreSetJmp();
2688 case Intrinsic::longjmp:
2689 return "_longjmp"+!TLI.usesUnderscoreLongJmp();
2691 case Intrinsic::memcpy_i32:
2692 case Intrinsic::memcpy_i64:
2693 visitMemIntrinsic(I, ISD::MEMCPY);
2695 case Intrinsic::memset_i32:
2696 case Intrinsic::memset_i64:
2697 visitMemIntrinsic(I, ISD::MEMSET);
2699 case Intrinsic::memmove_i32:
2700 case Intrinsic::memmove_i64:
2701 visitMemIntrinsic(I, ISD::MEMMOVE);
2704 case Intrinsic::dbg_stoppoint: {
2705 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
2706 DbgStopPointInst &SPI = cast<DbgStopPointInst>(I);
2707 if (MMI && SPI.getContext() && MMI->Verify(SPI.getContext())) {
2711 Ops[1] = getValue(SPI.getLineValue());
2712 Ops[2] = getValue(SPI.getColumnValue());
2714 DebugInfoDesc *DD = MMI->getDescFor(SPI.getContext());
2715 assert(DD && "Not a debug information descriptor");
2716 CompileUnitDesc *CompileUnit = cast<CompileUnitDesc>(DD);
2718 Ops[3] = DAG.getString(CompileUnit->getFileName());
2719 Ops[4] = DAG.getString(CompileUnit->getDirectory());
2721 DAG.setRoot(DAG.getNode(ISD::LOCATION, MVT::Other, Ops, 5));
2726 case Intrinsic::dbg_region_start: {
2727 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
2728 DbgRegionStartInst &RSI = cast<DbgRegionStartInst>(I);
2729 if (MMI && RSI.getContext() && MMI->Verify(RSI.getContext())) {
2730 unsigned LabelID = MMI->RecordRegionStart(RSI.getContext());
2731 DAG.setRoot(DAG.getNode(ISD::LABEL, MVT::Other, getRoot(),
2732 DAG.getConstant(LabelID, MVT::i32),
2733 DAG.getConstant(0, MVT::i32)));
2738 case Intrinsic::dbg_region_end: {
2739 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
2740 DbgRegionEndInst &REI = cast<DbgRegionEndInst>(I);
2741 if (MMI && REI.getContext() && MMI->Verify(REI.getContext())) {
2742 unsigned LabelID = MMI->RecordRegionEnd(REI.getContext());
2743 DAG.setRoot(DAG.getNode(ISD::LABEL, MVT::Other, getRoot(),
2744 DAG.getConstant(LabelID, MVT::i32),
2745 DAG.getConstant(0, MVT::i32)));
2750 case Intrinsic::dbg_func_start: {
2751 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
2753 DbgFuncStartInst &FSI = cast<DbgFuncStartInst>(I);
2754 Value *SP = FSI.getSubprogram();
2755 if (SP && MMI->Verify(SP)) {
2756 // llvm.dbg.func.start implicitly defines a dbg_stoppoint which is
2757 // what (most?) gdb expects.
2758 DebugInfoDesc *DD = MMI->getDescFor(SP);
2759 assert(DD && "Not a debug information descriptor");
2760 SubprogramDesc *Subprogram = cast<SubprogramDesc>(DD);
2761 const CompileUnitDesc *CompileUnit = Subprogram->getFile();
2762 unsigned SrcFile = MMI->RecordSource(CompileUnit->getDirectory(),
2763 CompileUnit->getFileName());
2764 // Record the source line but does create a label. It will be emitted
2765 // at asm emission time.
2766 MMI->RecordSourceLine(Subprogram->getLine(), 0, SrcFile);
2771 case Intrinsic::dbg_declare: {
2772 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
2773 DbgDeclareInst &DI = cast<DbgDeclareInst>(I);
2774 Value *Variable = DI.getVariable();
2775 if (MMI && Variable && MMI->Verify(Variable))
2776 DAG.setRoot(DAG.getNode(ISD::DECLARE, MVT::Other, getRoot(),
2777 getValue(DI.getAddress()), getValue(Variable)));
2781 case Intrinsic::eh_exception: {
2782 if (ExceptionHandling) {
2783 if (!CurMBB->isLandingPad()) {
2784 // FIXME: Mark exception register as live in. Hack for PR1508.
2785 unsigned Reg = TLI.getExceptionAddressRegister();
2786 if (Reg) CurMBB->addLiveIn(Reg);
2788 // Insert the EXCEPTIONADDR instruction.
2789 SDVTList VTs = DAG.getVTList(TLI.getPointerTy(), MVT::Other);
2791 Ops[0] = DAG.getRoot();
2792 SDOperand Op = DAG.getNode(ISD::EXCEPTIONADDR, VTs, Ops, 1);
2794 DAG.setRoot(Op.getValue(1));
2796 setValue(&I, DAG.getConstant(0, TLI.getPointerTy()));
2801 case Intrinsic::eh_selector_i32:
2802 case Intrinsic::eh_selector_i64: {
2803 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
2804 MVT::ValueType VT = (Intrinsic == Intrinsic::eh_selector_i32 ?
2805 MVT::i32 : MVT::i64);
2807 if (ExceptionHandling && MMI) {
2808 if (CurMBB->isLandingPad())
2809 addCatchInfo(I, MMI, CurMBB);
2812 FuncInfo.CatchInfoLost.insert(&I);
2814 // FIXME: Mark exception selector register as live in. Hack for PR1508.
2815 unsigned Reg = TLI.getExceptionSelectorRegister();
2816 if (Reg) CurMBB->addLiveIn(Reg);
2819 // Insert the EHSELECTION instruction.
2820 SDVTList VTs = DAG.getVTList(VT, MVT::Other);
2822 Ops[0] = getValue(I.getOperand(1));
2824 SDOperand Op = DAG.getNode(ISD::EHSELECTION, VTs, Ops, 2);
2826 DAG.setRoot(Op.getValue(1));
2828 setValue(&I, DAG.getConstant(0, VT));
2834 case Intrinsic::eh_typeid_for_i32:
2835 case Intrinsic::eh_typeid_for_i64: {
2836 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
2837 MVT::ValueType VT = (Intrinsic == Intrinsic::eh_typeid_for_i32 ?
2838 MVT::i32 : MVT::i64);
2841 // Find the type id for the given typeinfo.
2842 GlobalVariable *GV = ExtractTypeInfo(I.getOperand(1));
2844 unsigned TypeID = MMI->getTypeIDFor(GV);
2845 setValue(&I, DAG.getConstant(TypeID, VT));
2847 // Return something different to eh_selector.
2848 setValue(&I, DAG.getConstant(1, VT));
2854 case Intrinsic::eh_return: {
2855 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
2857 if (MMI && ExceptionHandling) {
2858 MMI->setCallsEHReturn(true);
2859 DAG.setRoot(DAG.getNode(ISD::EH_RETURN,
2862 getValue(I.getOperand(1)),
2863 getValue(I.getOperand(2))));
2865 setValue(&I, DAG.getConstant(0, TLI.getPointerTy()));
2871 case Intrinsic::eh_unwind_init: {
2872 if (MachineModuleInfo *MMI = DAG.getMachineModuleInfo()) {
2873 MMI->setCallsUnwindInit(true);
2879 case Intrinsic::eh_dwarf_cfa: {
2880 if (ExceptionHandling) {
2881 MVT::ValueType VT = getValue(I.getOperand(1)).getValueType();
2883 if (MVT::getSizeInBits(VT) > MVT::getSizeInBits(TLI.getPointerTy()))
2884 CfaArg = DAG.getNode(ISD::TRUNCATE,
2885 TLI.getPointerTy(), getValue(I.getOperand(1)));
2887 CfaArg = DAG.getNode(ISD::SIGN_EXTEND,
2888 TLI.getPointerTy(), getValue(I.getOperand(1)));
2890 SDOperand Offset = DAG.getNode(ISD::ADD,
2892 DAG.getNode(ISD::FRAME_TO_ARGS_OFFSET,
2893 TLI.getPointerTy()),
2895 setValue(&I, DAG.getNode(ISD::ADD,
2897 DAG.getNode(ISD::FRAMEADDR,
2900 TLI.getPointerTy())),
2903 setValue(&I, DAG.getConstant(0, TLI.getPointerTy()));
2909 case Intrinsic::sqrt:
2910 setValue(&I, DAG.getNode(ISD::FSQRT,
2911 getValue(I.getOperand(1)).getValueType(),
2912 getValue(I.getOperand(1))));
2914 case Intrinsic::powi:
2915 setValue(&I, DAG.getNode(ISD::FPOWI,
2916 getValue(I.getOperand(1)).getValueType(),
2917 getValue(I.getOperand(1)),
2918 getValue(I.getOperand(2))));
2920 case Intrinsic::sin:
2921 setValue(&I, DAG.getNode(ISD::FSIN,
2922 getValue(I.getOperand(1)).getValueType(),
2923 getValue(I.getOperand(1))));
2925 case Intrinsic::cos:
2926 setValue(&I, DAG.getNode(ISD::FCOS,
2927 getValue(I.getOperand(1)).getValueType(),
2928 getValue(I.getOperand(1))));
2930 case Intrinsic::pow:
2931 setValue(&I, DAG.getNode(ISD::FPOW,
2932 getValue(I.getOperand(1)).getValueType(),
2933 getValue(I.getOperand(1)),
2934 getValue(I.getOperand(2))));
2936 case Intrinsic::pcmarker: {
2937 SDOperand Tmp = getValue(I.getOperand(1));
2938 DAG.setRoot(DAG.getNode(ISD::PCMARKER, MVT::Other, getRoot(), Tmp));
2941 case Intrinsic::readcyclecounter: {
2942 SDOperand Op = getRoot();
2943 SDOperand Tmp = DAG.getNode(ISD::READCYCLECOUNTER,
2944 DAG.getNodeValueTypes(MVT::i64, MVT::Other), 2,
2947 DAG.setRoot(Tmp.getValue(1));
2950 case Intrinsic::part_select: {
2951 // Currently not implemented: just abort
2952 assert(0 && "part_select intrinsic not implemented");
2955 case Intrinsic::part_set: {
2956 // Currently not implemented: just abort
2957 assert(0 && "part_set intrinsic not implemented");
2960 case Intrinsic::bswap:
2961 setValue(&I, DAG.getNode(ISD::BSWAP,
2962 getValue(I.getOperand(1)).getValueType(),
2963 getValue(I.getOperand(1))));
2965 case Intrinsic::cttz: {
2966 SDOperand Arg = getValue(I.getOperand(1));
2967 MVT::ValueType Ty = Arg.getValueType();
2968 SDOperand result = DAG.getNode(ISD::CTTZ, Ty, Arg);
2969 setValue(&I, result);
2972 case Intrinsic::ctlz: {
2973 SDOperand Arg = getValue(I.getOperand(1));
2974 MVT::ValueType Ty = Arg.getValueType();
2975 SDOperand result = DAG.getNode(ISD::CTLZ, Ty, Arg);
2976 setValue(&I, result);
2979 case Intrinsic::ctpop: {
2980 SDOperand Arg = getValue(I.getOperand(1));
2981 MVT::ValueType Ty = Arg.getValueType();
2982 SDOperand result = DAG.getNode(ISD::CTPOP, Ty, Arg);
2983 setValue(&I, result);
2986 case Intrinsic::stacksave: {
2987 SDOperand Op = getRoot();
2988 SDOperand Tmp = DAG.getNode(ISD::STACKSAVE,
2989 DAG.getNodeValueTypes(TLI.getPointerTy(), MVT::Other), 2, &Op, 1);
2991 DAG.setRoot(Tmp.getValue(1));
2994 case Intrinsic::stackrestore: {
2995 SDOperand Tmp = getValue(I.getOperand(1));
2996 DAG.setRoot(DAG.getNode(ISD::STACKRESTORE, MVT::Other, getRoot(), Tmp));
2999 case Intrinsic::prefetch:
3000 // FIXME: Currently discarding prefetches.
3003 case Intrinsic::var_annotation:
3004 // Discard annotate attributes
3007 case Intrinsic::init_trampoline: {
3009 cast<Function>(IntrinsicInst::StripPointerCasts(I.getOperand(2)));
3013 Ops[1] = getValue(I.getOperand(1));
3014 Ops[2] = getValue(I.getOperand(2));
3015 Ops[3] = getValue(I.getOperand(3));
3016 Ops[4] = DAG.getSrcValue(I.getOperand(1));
3017 Ops[5] = DAG.getSrcValue(F);
3019 SDOperand Tmp = DAG.getNode(ISD::TRAMPOLINE,
3020 DAG.getNodeValueTypes(TLI.getPointerTy(),
3025 DAG.setRoot(Tmp.getValue(1));
3029 case Intrinsic::gcroot:
3031 Value *Alloca = I.getOperand(1);
3032 Constant *TypeMap = cast<Constant>(I.getOperand(2));
3034 FrameIndexSDNode *FI = cast<FrameIndexSDNode>(getValue(Alloca).Val);
3035 GCI->addStackRoot(FI->getIndex(), TypeMap);
3039 case Intrinsic::gcread:
3040 case Intrinsic::gcwrite:
3041 assert(0 && "Collector failed to lower gcread/gcwrite intrinsics!");
3044 case Intrinsic::flt_rounds: {
3045 setValue(&I, DAG.getNode(ISD::FLT_ROUNDS_, MVT::i32));
3049 case Intrinsic::trap: {
3050 DAG.setRoot(DAG.getNode(ISD::TRAP, MVT::Other, getRoot()));
3053 case Intrinsic::memory_barrier: {
3056 for (int x = 1; x < 6; ++x)
3057 Ops[x] = getValue(I.getOperand(x));
3059 DAG.setRoot(DAG.getNode(ISD::MEMBARRIER, MVT::Other, &Ops[0], 6));
3062 case Intrinsic::atomic_lcs: {
3063 SDOperand Root = getRoot();
3064 SDOperand O3 = getValue(I.getOperand(3));
3065 SDOperand L = DAG.getAtomic(ISD::ATOMIC_LCS, Root,
3066 getValue(I.getOperand(1)),
3067 getValue(I.getOperand(2)),
3068 O3, O3.getValueType());
3070 DAG.setRoot(L.getValue(1));
3073 case Intrinsic::atomic_las: {
3074 SDOperand Root = getRoot();
3075 SDOperand O2 = getValue(I.getOperand(2));
3076 SDOperand L = DAG.getAtomic(ISD::ATOMIC_LAS, Root,
3077 getValue(I.getOperand(1)),
3078 O2, O2.getValueType());
3080 DAG.setRoot(L.getValue(1));
3083 case Intrinsic::atomic_swap: {
3084 SDOperand Root = getRoot();
3085 SDOperand O2 = getValue(I.getOperand(2));
3086 SDOperand L = DAG.getAtomic(ISD::ATOMIC_SWAP, Root,
3087 getValue(I.getOperand(1)),
3088 O2, O2.getValueType());
3090 DAG.setRoot(L.getValue(1));
3098 void SelectionDAGLowering::LowerCallTo(CallSite CS, SDOperand Callee,
3100 MachineBasicBlock *LandingPad) {
3101 const PointerType *PT = cast<PointerType>(CS.getCalledValue()->getType());
3102 const FunctionType *FTy = cast<FunctionType>(PT->getElementType());
3103 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
3104 unsigned BeginLabel = 0, EndLabel = 0;
3106 TargetLowering::ArgListTy Args;
3107 TargetLowering::ArgListEntry Entry;
3108 Args.reserve(CS.arg_size());
3109 for (CallSite::arg_iterator i = CS.arg_begin(), e = CS.arg_end();
3111 SDOperand ArgNode = getValue(*i);
3112 Entry.Node = ArgNode; Entry.Ty = (*i)->getType();
3114 unsigned attrInd = i - CS.arg_begin() + 1;
3115 Entry.isSExt = CS.paramHasAttr(attrInd, ParamAttr::SExt);
3116 Entry.isZExt = CS.paramHasAttr(attrInd, ParamAttr::ZExt);
3117 Entry.isInReg = CS.paramHasAttr(attrInd, ParamAttr::InReg);
3118 Entry.isSRet = CS.paramHasAttr(attrInd, ParamAttr::StructRet);
3119 Entry.isNest = CS.paramHasAttr(attrInd, ParamAttr::Nest);
3120 Entry.isByVal = CS.paramHasAttr(attrInd, ParamAttr::ByVal);
3121 Entry.Alignment = CS.getParamAlignment(attrInd);
3122 Args.push_back(Entry);
3125 bool MarkTryRange = LandingPad ||
3126 // C++ requires special handling of 'nounwind' calls.
3127 (CS.doesNotThrow());
3129 if (MarkTryRange && ExceptionHandling && MMI) {
3130 // Insert a label before the invoke call to mark the try range. This can be
3131 // used to detect deletion of the invoke via the MachineModuleInfo.
3132 BeginLabel = MMI->NextLabelID();
3133 DAG.setRoot(DAG.getNode(ISD::LABEL, MVT::Other, getRoot(),
3134 DAG.getConstant(BeginLabel, MVT::i32),
3135 DAG.getConstant(1, MVT::i32)));
3138 std::pair<SDOperand,SDOperand> Result =
3139 TLI.LowerCallTo(getRoot(), CS.getType(),
3140 CS.paramHasAttr(0, ParamAttr::SExt),
3141 CS.paramHasAttr(0, ParamAttr::ZExt),
3142 FTy->isVarArg(), CS.getCallingConv(), IsTailCall,
3144 if (CS.getType() != Type::VoidTy)
3145 setValue(CS.getInstruction(), Result.first);
3146 DAG.setRoot(Result.second);
3148 if (MarkTryRange && ExceptionHandling && MMI) {
3149 // Insert a label at the end of the invoke call to mark the try range. This
3150 // can be used to detect deletion of the invoke via the MachineModuleInfo.
3151 EndLabel = MMI->NextLabelID();
3152 DAG.setRoot(DAG.getNode(ISD::LABEL, MVT::Other, getRoot(),
3153 DAG.getConstant(EndLabel, MVT::i32),
3154 DAG.getConstant(1, MVT::i32)));
3156 // Inform MachineModuleInfo of range.
3157 MMI->addInvoke(LandingPad, BeginLabel, EndLabel);
3162 void SelectionDAGLowering::visitCall(CallInst &I) {
3163 const char *RenameFn = 0;
3164 if (Function *F = I.getCalledFunction()) {
3165 if (F->isDeclaration()) {
3166 if (unsigned IID = F->getIntrinsicID()) {
3167 RenameFn = visitIntrinsicCall(I, IID);
3173 // Check for well-known libc/libm calls. If the function is internal, it
3174 // can't be a library call.
3175 unsigned NameLen = F->getNameLen();
3176 if (!F->hasInternalLinkage() && NameLen) {
3177 const char *NameStr = F->getNameStart();
3178 if (NameStr[0] == 'c' &&
3179 ((NameLen == 8 && !strcmp(NameStr, "copysign")) ||
3180 (NameLen == 9 && !strcmp(NameStr, "copysignf")))) {
3181 if (I.getNumOperands() == 3 && // Basic sanity checks.
3182 I.getOperand(1)->getType()->isFloatingPoint() &&
3183 I.getType() == I.getOperand(1)->getType() &&
3184 I.getType() == I.getOperand(2)->getType()) {
3185 SDOperand LHS = getValue(I.getOperand(1));
3186 SDOperand RHS = getValue(I.getOperand(2));
3187 setValue(&I, DAG.getNode(ISD::FCOPYSIGN, LHS.getValueType(),
3191 } else if (NameStr[0] == 'f' &&
3192 ((NameLen == 4 && !strcmp(NameStr, "fabs")) ||
3193 (NameLen == 5 && !strcmp(NameStr, "fabsf")) ||
3194 (NameLen == 5 && !strcmp(NameStr, "fabsl")))) {
3195 if (I.getNumOperands() == 2 && // Basic sanity checks.
3196 I.getOperand(1)->getType()->isFloatingPoint() &&
3197 I.getType() == I.getOperand(1)->getType()) {
3198 SDOperand Tmp = getValue(I.getOperand(1));
3199 setValue(&I, DAG.getNode(ISD::FABS, Tmp.getValueType(), Tmp));
3202 } else if (NameStr[0] == 's' &&
3203 ((NameLen == 3 && !strcmp(NameStr, "sin")) ||
3204 (NameLen == 4 && !strcmp(NameStr, "sinf")) ||
3205 (NameLen == 4 && !strcmp(NameStr, "sinl")))) {
3206 if (I.getNumOperands() == 2 && // Basic sanity checks.
3207 I.getOperand(1)->getType()->isFloatingPoint() &&
3208 I.getType() == I.getOperand(1)->getType()) {
3209 SDOperand Tmp = getValue(I.getOperand(1));
3210 setValue(&I, DAG.getNode(ISD::FSIN, Tmp.getValueType(), Tmp));
3213 } else if (NameStr[0] == 'c' &&
3214 ((NameLen == 3 && !strcmp(NameStr, "cos")) ||
3215 (NameLen == 4 && !strcmp(NameStr, "cosf")) ||
3216 (NameLen == 4 && !strcmp(NameStr, "cosl")))) {
3217 if (I.getNumOperands() == 2 && // Basic sanity checks.
3218 I.getOperand(1)->getType()->isFloatingPoint() &&
3219 I.getType() == I.getOperand(1)->getType()) {
3220 SDOperand Tmp = getValue(I.getOperand(1));
3221 setValue(&I, DAG.getNode(ISD::FCOS, Tmp.getValueType(), Tmp));
3226 } else if (isa<InlineAsm>(I.getOperand(0))) {
3233 Callee = getValue(I.getOperand(0));
3235 Callee = DAG.getExternalSymbol(RenameFn, TLI.getPointerTy());
3237 LowerCallTo(&I, Callee, I.isTailCall());
3241 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from
3242 /// this value and returns the result as a ValueVT value. This uses
3243 /// Chain/Flag as the input and updates them for the output Chain/Flag.
3244 /// If the Flag pointer is NULL, no flag is used.
3245 SDOperand RegsForValue::getCopyFromRegs(SelectionDAG &DAG,
3246 SDOperand &Chain, SDOperand *Flag)const{
3247 // Copy the legal parts from the registers.
3248 unsigned NumParts = Regs.size();
3249 SmallVector<SDOperand, 8> Parts(NumParts);
3250 for (unsigned i = 0; i != NumParts; ++i) {
3251 SDOperand Part = Flag ?
3252 DAG.getCopyFromReg(Chain, Regs[i], RegVT, *Flag) :
3253 DAG.getCopyFromReg(Chain, Regs[i], RegVT);
3254 Chain = Part.getValue(1);
3256 *Flag = Part.getValue(2);
3260 // Assemble the legal parts into the final value.
3261 return getCopyFromParts(DAG, &Parts[0], NumParts, RegVT, ValueVT);
3264 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
3265 /// specified value into the registers specified by this object. This uses
3266 /// Chain/Flag as the input and updates them for the output Chain/Flag.
3267 /// If the Flag pointer is NULL, no flag is used.
3268 void RegsForValue::getCopyToRegs(SDOperand Val, SelectionDAG &DAG,
3269 SDOperand &Chain, SDOperand *Flag) const {
3270 // Get the list of the values's legal parts.
3271 unsigned NumParts = Regs.size();
3272 SmallVector<SDOperand, 8> Parts(NumParts);
3273 getCopyToParts(DAG, Val, &Parts[0], NumParts, RegVT);
3275 // Copy the parts into the registers.
3276 for (unsigned i = 0; i != NumParts; ++i) {
3277 SDOperand Part = Flag ?
3278 DAG.getCopyToReg(Chain, Regs[i], Parts[i], *Flag) :
3279 DAG.getCopyToReg(Chain, Regs[i], Parts[i]);
3280 Chain = Part.getValue(0);
3282 *Flag = Part.getValue(1);
3286 /// AddInlineAsmOperands - Add this value to the specified inlineasm node
3287 /// operand list. This adds the code marker and includes the number of
3288 /// values added into it.
3289 void RegsForValue::AddInlineAsmOperands(unsigned Code, SelectionDAG &DAG,
3290 std::vector<SDOperand> &Ops) const {
3291 MVT::ValueType IntPtrTy = DAG.getTargetLoweringInfo().getPointerTy();
3292 Ops.push_back(DAG.getTargetConstant(Code | (Regs.size() << 3), IntPtrTy));
3293 for (unsigned i = 0, e = Regs.size(); i != e; ++i)
3294 Ops.push_back(DAG.getRegister(Regs[i], RegVT));
3297 /// isAllocatableRegister - If the specified register is safe to allocate,
3298 /// i.e. it isn't a stack pointer or some other special register, return the
3299 /// register class for the register. Otherwise, return null.
3300 static const TargetRegisterClass *
3301 isAllocatableRegister(unsigned Reg, MachineFunction &MF,
3302 const TargetLowering &TLI,
3303 const TargetRegisterInfo *TRI) {
3304 MVT::ValueType FoundVT = MVT::Other;
3305 const TargetRegisterClass *FoundRC = 0;
3306 for (TargetRegisterInfo::regclass_iterator RCI = TRI->regclass_begin(),
3307 E = TRI->regclass_end(); RCI != E; ++RCI) {
3308 MVT::ValueType ThisVT = MVT::Other;
3310 const TargetRegisterClass *RC = *RCI;
3311 // If none of the the value types for this register class are valid, we
3312 // can't use it. For example, 64-bit reg classes on 32-bit targets.
3313 for (TargetRegisterClass::vt_iterator I = RC->vt_begin(), E = RC->vt_end();
3315 if (TLI.isTypeLegal(*I)) {
3316 // If we have already found this register in a different register class,
3317 // choose the one with the largest VT specified. For example, on
3318 // PowerPC, we favor f64 register classes over f32.
3319 if (FoundVT == MVT::Other ||
3320 MVT::getSizeInBits(FoundVT) < MVT::getSizeInBits(*I)) {
3327 if (ThisVT == MVT::Other) continue;
3329 // NOTE: This isn't ideal. In particular, this might allocate the
3330 // frame pointer in functions that need it (due to them not being taken
3331 // out of allocation, because a variable sized allocation hasn't been seen
3332 // yet). This is a slight code pessimization, but should still work.
3333 for (TargetRegisterClass::iterator I = RC->allocation_order_begin(MF),
3334 E = RC->allocation_order_end(MF); I != E; ++I)
3336 // We found a matching register class. Keep looking at others in case
3337 // we find one with larger registers that this physreg is also in.
3348 /// AsmOperandInfo - This contains information for each constraint that we are
3350 struct AsmOperandInfo : public InlineAsm::ConstraintInfo {
3351 /// ConstraintCode - This contains the actual string for the code, like "m".
3352 std::string ConstraintCode;
3354 /// ConstraintType - Information about the constraint code, e.g. Register,
3355 /// RegisterClass, Memory, Other, Unknown.
3356 TargetLowering::ConstraintType ConstraintType;
3358 /// CallOperand/CallOperandval - If this is the result output operand or a
3359 /// clobber, this is null, otherwise it is the incoming operand to the
3360 /// CallInst. This gets modified as the asm is processed.
3361 SDOperand CallOperand;
3362 Value *CallOperandVal;
3364 /// ConstraintVT - The ValueType for the operand value.
3365 MVT::ValueType ConstraintVT;
3367 /// AssignedRegs - If this is a register or register class operand, this
3368 /// contains the set of register corresponding to the operand.
3369 RegsForValue AssignedRegs;
3371 AsmOperandInfo(const InlineAsm::ConstraintInfo &info)
3372 : InlineAsm::ConstraintInfo(info),
3373 ConstraintType(TargetLowering::C_Unknown),
3374 CallOperand(0,0), CallOperandVal(0), ConstraintVT(MVT::Other) {
3377 void ComputeConstraintToUse(const TargetLowering &TLI);
3379 /// MarkAllocatedRegs - Once AssignedRegs is set, mark the assigned registers
3380 /// busy in OutputRegs/InputRegs.
3381 void MarkAllocatedRegs(bool isOutReg, bool isInReg,
3382 std::set<unsigned> &OutputRegs,
3383 std::set<unsigned> &InputRegs,
3384 const TargetRegisterInfo &TRI) const {
3386 for (unsigned i = 0, e = AssignedRegs.Regs.size(); i != e; ++i)
3387 MarkRegAndAliases(AssignedRegs.Regs[i], OutputRegs, TRI);
3390 for (unsigned i = 0, e = AssignedRegs.Regs.size(); i != e; ++i)
3391 MarkRegAndAliases(AssignedRegs.Regs[i], InputRegs, TRI);
3396 /// MarkRegAndAliases - Mark the specified register and all aliases in the
3398 static void MarkRegAndAliases(unsigned Reg, std::set<unsigned> &Regs,
3399 const TargetRegisterInfo &TRI) {
3400 assert(TargetRegisterInfo::isPhysicalRegister(Reg) && "Isn't a physreg");
3402 if (const unsigned *Aliases = TRI.getAliasSet(Reg))
3403 for (; *Aliases; ++Aliases)
3404 Regs.insert(*Aliases);
3407 } // end anon namespace.
3409 /// getConstraintGenerality - Return an integer indicating how general CT is.
3410 static unsigned getConstraintGenerality(TargetLowering::ConstraintType CT) {
3412 default: assert(0 && "Unknown constraint type!");
3413 case TargetLowering::C_Other:
3414 case TargetLowering::C_Unknown:
3416 case TargetLowering::C_Register:
3418 case TargetLowering::C_RegisterClass:
3420 case TargetLowering::C_Memory:
3425 void AsmOperandInfo::ComputeConstraintToUse(const TargetLowering &TLI) {
3426 assert(!Codes.empty() && "Must have at least one constraint");
3428 std::string *Current = &Codes[0];
3429 TargetLowering::ConstraintType CurType = TLI.getConstraintType(*Current);
3430 if (Codes.size() == 1) { // Single-letter constraints ('r') are very common.
3431 ConstraintCode = *Current;
3432 ConstraintType = CurType;
3434 unsigned CurGenerality = getConstraintGenerality(CurType);
3436 // If we have multiple constraints, try to pick the most general one ahead
3437 // of time. This isn't a wonderful solution, but handles common cases.
3438 for (unsigned j = 1, e = Codes.size(); j != e; ++j) {
3439 TargetLowering::ConstraintType ThisType = TLI.getConstraintType(Codes[j]);
3440 unsigned ThisGenerality = getConstraintGenerality(ThisType);
3441 if (ThisGenerality > CurGenerality) {
3442 // This constraint letter is more general than the previous one,
3445 Current = &Codes[j];
3446 CurGenerality = ThisGenerality;
3450 ConstraintCode = *Current;
3451 ConstraintType = CurType;
3454 if (ConstraintCode == "X") {
3455 if (isa<BasicBlock>(CallOperandVal) || isa<ConstantInt>(CallOperandVal))
3457 // This matches anything. Labels and constants we handle elsewhere
3458 // ('X' is the only thing that matches labels). Otherwise, try to
3459 // resolve it to something we know about by looking at the actual
3462 TLI.lowerXConstraint(ConstraintVT, s);
3465 ConstraintType = TLI.getConstraintType(ConstraintCode);
3471 /// GetRegistersForValue - Assign registers (virtual or physical) for the
3472 /// specified operand. We prefer to assign virtual registers, to allow the
3473 /// register allocator handle the assignment process. However, if the asm uses
3474 /// features that we can't model on machineinstrs, we have SDISel do the
3475 /// allocation. This produces generally horrible, but correct, code.
3477 /// OpInfo describes the operand.
3478 /// HasEarlyClobber is true if there are any early clobber constraints (=&r)
3479 /// or any explicitly clobbered registers.
3480 /// Input and OutputRegs are the set of already allocated physical registers.
3482 void SelectionDAGLowering::
3483 GetRegistersForValue(AsmOperandInfo &OpInfo, bool HasEarlyClobber,
3484 std::set<unsigned> &OutputRegs,
3485 std::set<unsigned> &InputRegs) {
3486 // Compute whether this value requires an input register, an output register,
3488 bool isOutReg = false;
3489 bool isInReg = false;
3490 switch (OpInfo.Type) {
3491 case InlineAsm::isOutput:
3494 // If this is an early-clobber output, or if there is an input
3495 // constraint that matches this, we need to reserve the input register
3496 // so no other inputs allocate to it.
3497 isInReg = OpInfo.isEarlyClobber || OpInfo.hasMatchingInput;
3499 case InlineAsm::isInput:
3503 case InlineAsm::isClobber:
3510 MachineFunction &MF = DAG.getMachineFunction();
3511 std::vector<unsigned> Regs;
3513 // If this is a constraint for a single physreg, or a constraint for a
3514 // register class, find it.
3515 std::pair<unsigned, const TargetRegisterClass*> PhysReg =
3516 TLI.getRegForInlineAsmConstraint(OpInfo.ConstraintCode,
3517 OpInfo.ConstraintVT);
3519 unsigned NumRegs = 1;
3520 if (OpInfo.ConstraintVT != MVT::Other)
3521 NumRegs = TLI.getNumRegisters(OpInfo.ConstraintVT);
3522 MVT::ValueType RegVT;
3523 MVT::ValueType ValueVT = OpInfo.ConstraintVT;
3526 // If this is a constraint for a specific physical register, like {r17},
3528 if (PhysReg.first) {
3529 if (OpInfo.ConstraintVT == MVT::Other)
3530 ValueVT = *PhysReg.second->vt_begin();
3532 // Get the actual register value type. This is important, because the user
3533 // may have asked for (e.g.) the AX register in i32 type. We need to
3534 // remember that AX is actually i16 to get the right extension.
3535 RegVT = *PhysReg.second->vt_begin();
3537 // This is a explicit reference to a physical register.
3538 Regs.push_back(PhysReg.first);
3540 // If this is an expanded reference, add the rest of the regs to Regs.
3542 TargetRegisterClass::iterator I = PhysReg.second->begin();
3543 TargetRegisterClass::iterator E = PhysReg.second->end();
3544 for (; *I != PhysReg.first; ++I)
3545 assert(I != E && "Didn't find reg!");
3547 // Already added the first reg.
3549 for (; NumRegs; --NumRegs, ++I) {
3550 assert(I != E && "Ran out of registers to allocate!");
3554 OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT);
3555 const TargetRegisterInfo *TRI = DAG.getTarget().getRegisterInfo();
3556 OpInfo.MarkAllocatedRegs(isOutReg, isInReg, OutputRegs, InputRegs, *TRI);
3560 // Otherwise, if this was a reference to an LLVM register class, create vregs
3561 // for this reference.
3562 std::vector<unsigned> RegClassRegs;
3563 const TargetRegisterClass *RC = PhysReg.second;
3565 // If this is an early clobber or tied register, our regalloc doesn't know
3566 // how to maintain the constraint. If it isn't, go ahead and create vreg
3567 // and let the regalloc do the right thing.
3568 if (!OpInfo.hasMatchingInput && !OpInfo.isEarlyClobber &&
3569 // If there is some other early clobber and this is an input register,
3570 // then we are forced to pre-allocate the input reg so it doesn't
3571 // conflict with the earlyclobber.
3572 !(OpInfo.Type == InlineAsm::isInput && HasEarlyClobber)) {
3573 RegVT = *PhysReg.second->vt_begin();
3575 if (OpInfo.ConstraintVT == MVT::Other)
3578 // Create the appropriate number of virtual registers.
3579 MachineRegisterInfo &RegInfo = MF.getRegInfo();
3580 for (; NumRegs; --NumRegs)
3581 Regs.push_back(RegInfo.createVirtualRegister(PhysReg.second));
3583 OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT);
3587 // Otherwise, we can't allocate it. Let the code below figure out how to
3588 // maintain these constraints.
3589 RegClassRegs.assign(PhysReg.second->begin(), PhysReg.second->end());
3592 // This is a reference to a register class that doesn't directly correspond
3593 // to an LLVM register class. Allocate NumRegs consecutive, available,
3594 // registers from the class.
3595 RegClassRegs = TLI.getRegClassForInlineAsmConstraint(OpInfo.ConstraintCode,
3596 OpInfo.ConstraintVT);
3599 const TargetRegisterInfo *TRI = DAG.getTarget().getRegisterInfo();
3600 unsigned NumAllocated = 0;
3601 for (unsigned i = 0, e = RegClassRegs.size(); i != e; ++i) {
3602 unsigned Reg = RegClassRegs[i];
3603 // See if this register is available.
3604 if ((isOutReg && OutputRegs.count(Reg)) || // Already used.
3605 (isInReg && InputRegs.count(Reg))) { // Already used.
3606 // Make sure we find consecutive registers.
3611 // Check to see if this register is allocatable (i.e. don't give out the
3614 RC = isAllocatableRegister(Reg, MF, TLI, TRI);
3615 if (!RC) { // Couldn't allocate this register.
3616 // Reset NumAllocated to make sure we return consecutive registers.
3622 // Okay, this register is good, we can use it.
3625 // If we allocated enough consecutive registers, succeed.
3626 if (NumAllocated == NumRegs) {
3627 unsigned RegStart = (i-NumAllocated)+1;
3628 unsigned RegEnd = i+1;
3629 // Mark all of the allocated registers used.
3630 for (unsigned i = RegStart; i != RegEnd; ++i)
3631 Regs.push_back(RegClassRegs[i]);
3633 OpInfo.AssignedRegs = RegsForValue(Regs, *RC->vt_begin(),
3634 OpInfo.ConstraintVT);
3635 OpInfo.MarkAllocatedRegs(isOutReg, isInReg, OutputRegs, InputRegs, *TRI);
3640 // Otherwise, we couldn't allocate enough registers for this.
3645 /// visitInlineAsm - Handle a call to an InlineAsm object.
3647 void SelectionDAGLowering::visitInlineAsm(CallSite CS) {
3648 InlineAsm *IA = cast<InlineAsm>(CS.getCalledValue());
3650 /// ConstraintOperands - Information about all of the constraints.
3651 std::vector<AsmOperandInfo> ConstraintOperands;
3653 SDOperand Chain = getRoot();
3656 std::set<unsigned> OutputRegs, InputRegs;
3658 // Do a prepass over the constraints, canonicalizing them, and building up the
3659 // ConstraintOperands list.
3660 std::vector<InlineAsm::ConstraintInfo>
3661 ConstraintInfos = IA->ParseConstraints();
3663 // SawEarlyClobber - Keep track of whether we saw an earlyclobber output
3664 // constraint. If so, we can't let the register allocator allocate any input
3665 // registers, because it will not know to avoid the earlyclobbered output reg.
3666 bool SawEarlyClobber = false;
3668 unsigned ArgNo = 0; // ArgNo - The argument of the CallInst.
3669 for (unsigned i = 0, e = ConstraintInfos.size(); i != e; ++i) {
3670 ConstraintOperands.push_back(AsmOperandInfo(ConstraintInfos[i]));
3671 AsmOperandInfo &OpInfo = ConstraintOperands.back();
3673 MVT::ValueType OpVT = MVT::Other;
3675 // Compute the value type for each operand.
3676 switch (OpInfo.Type) {
3677 case InlineAsm::isOutput:
3678 if (!OpInfo.isIndirect) {
3679 // The return value of the call is this value. As such, there is no
3680 // corresponding argument.
3681 assert(CS.getType() != Type::VoidTy && "Bad inline asm!");
3682 OpVT = TLI.getValueType(CS.getType());
3684 OpInfo.CallOperandVal = CS.getArgument(ArgNo++);
3687 case InlineAsm::isInput:
3688 OpInfo.CallOperandVal = CS.getArgument(ArgNo++);
3690 case InlineAsm::isClobber:
3695 // If this is an input or an indirect output, process the call argument.
3696 // BasicBlocks are labels, currently appearing only in asm's.
3697 if (OpInfo.CallOperandVal) {
3698 if (isa<BasicBlock>(OpInfo.CallOperandVal))
3699 OpInfo.CallOperand =
3700 DAG.getBasicBlock(FuncInfo.MBBMap[cast<BasicBlock>(
3701 OpInfo.CallOperandVal)]);
3703 OpInfo.CallOperand = getValue(OpInfo.CallOperandVal);
3704 const Type *OpTy = OpInfo.CallOperandVal->getType();
3705 // If this is an indirect operand, the operand is a pointer to the
3707 if (OpInfo.isIndirect)
3708 OpTy = cast<PointerType>(OpTy)->getElementType();
3710 // If OpTy is not a first-class value, it may be a struct/union that we
3711 // can tile with integers.
3712 if (!OpTy->isFirstClassType() && OpTy->isSized()) {
3713 unsigned BitSize = TD->getTypeSizeInBits(OpTy);
3721 OpTy = IntegerType::get(BitSize);
3726 OpVT = TLI.getValueType(OpTy, true);
3730 OpInfo.ConstraintVT = OpVT;
3732 // Compute the constraint code and ConstraintType to use.
3733 OpInfo.ComputeConstraintToUse(TLI);
3735 // Keep track of whether we see an earlyclobber.
3736 SawEarlyClobber |= OpInfo.isEarlyClobber;
3738 // If we see a clobber of a register, it is an early clobber.
3739 if (!SawEarlyClobber &&
3740 OpInfo.Type == InlineAsm::isClobber &&
3741 OpInfo.ConstraintType == TargetLowering::C_Register) {
3742 // Note that we want to ignore things that we don't trick here, like
3743 // dirflag, fpsr, flags, etc.
3744 std::pair<unsigned, const TargetRegisterClass*> PhysReg =
3745 TLI.getRegForInlineAsmConstraint(OpInfo.ConstraintCode,
3746 OpInfo.ConstraintVT);
3747 if (PhysReg.first || PhysReg.second) {
3748 // This is a register we know of.
3749 SawEarlyClobber = true;
3753 // If this is a memory input, and if the operand is not indirect, do what we
3754 // need to to provide an address for the memory input.
3755 if (OpInfo.ConstraintType == TargetLowering::C_Memory &&
3756 !OpInfo.isIndirect) {
3757 assert(OpInfo.Type == InlineAsm::isInput &&
3758 "Can only indirectify direct input operands!");
3760 // Memory operands really want the address of the value. If we don't have
3761 // an indirect input, put it in the constpool if we can, otherwise spill
3762 // it to a stack slot.
3764 // If the operand is a float, integer, or vector constant, spill to a
3765 // constant pool entry to get its address.
3766 Value *OpVal = OpInfo.CallOperandVal;
3767 if (isa<ConstantFP>(OpVal) || isa<ConstantInt>(OpVal) ||
3768 isa<ConstantVector>(OpVal)) {
3769 OpInfo.CallOperand = DAG.getConstantPool(cast<Constant>(OpVal),
3770 TLI.getPointerTy());
3772 // Otherwise, create a stack slot and emit a store to it before the
3774 const Type *Ty = OpVal->getType();
3775 uint64_t TySize = TLI.getTargetData()->getABITypeSize(Ty);
3776 unsigned Align = TLI.getTargetData()->getPrefTypeAlignment(Ty);
3777 MachineFunction &MF = DAG.getMachineFunction();
3778 int SSFI = MF.getFrameInfo()->CreateStackObject(TySize, Align);
3779 SDOperand StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy());
3780 Chain = DAG.getStore(Chain, OpInfo.CallOperand, StackSlot, NULL, 0);
3781 OpInfo.CallOperand = StackSlot;
3784 // There is no longer a Value* corresponding to this operand.
3785 OpInfo.CallOperandVal = 0;
3786 // It is now an indirect operand.
3787 OpInfo.isIndirect = true;
3790 // If this constraint is for a specific register, allocate it before
3792 if (OpInfo.ConstraintType == TargetLowering::C_Register)
3793 GetRegistersForValue(OpInfo, SawEarlyClobber, OutputRegs, InputRegs);
3795 ConstraintInfos.clear();
3798 // Second pass - Loop over all of the operands, assigning virtual or physregs
3799 // to registerclass operands.
3800 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
3801 AsmOperandInfo &OpInfo = ConstraintOperands[i];
3803 // C_Register operands have already been allocated, Other/Memory don't need
3805 if (OpInfo.ConstraintType == TargetLowering::C_RegisterClass)
3806 GetRegistersForValue(OpInfo, SawEarlyClobber, OutputRegs, InputRegs);
3809 // AsmNodeOperands - The operands for the ISD::INLINEASM node.
3810 std::vector<SDOperand> AsmNodeOperands;
3811 AsmNodeOperands.push_back(SDOperand()); // reserve space for input chain
3812 AsmNodeOperands.push_back(
3813 DAG.getTargetExternalSymbol(IA->getAsmString().c_str(), MVT::Other));
3816 // Loop over all of the inputs, copying the operand values into the
3817 // appropriate registers and processing the output regs.
3818 RegsForValue RetValRegs;
3820 // IndirectStoresToEmit - The set of stores to emit after the inline asm node.
3821 std::vector<std::pair<RegsForValue, Value*> > IndirectStoresToEmit;
3823 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
3824 AsmOperandInfo &OpInfo = ConstraintOperands[i];
3826 switch (OpInfo.Type) {
3827 case InlineAsm::isOutput: {
3828 if (OpInfo.ConstraintType != TargetLowering::C_RegisterClass &&
3829 OpInfo.ConstraintType != TargetLowering::C_Register) {
3830 // Memory output, or 'other' output (e.g. 'X' constraint).
3831 assert(OpInfo.isIndirect && "Memory output must be indirect operand");
3833 // Add information to the INLINEASM node to know about this output.
3834 unsigned ResOpType = 4/*MEM*/ | (1 << 3);
3835 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
3836 TLI.getPointerTy()));
3837 AsmNodeOperands.push_back(OpInfo.CallOperand);
3841 // Otherwise, this is a register or register class output.
3843 // Copy the output from the appropriate register. Find a register that
3845 if (OpInfo.AssignedRegs.Regs.empty()) {
3846 cerr << "Couldn't allocate output reg for contraint '"
3847 << OpInfo.ConstraintCode << "'!\n";
3851 if (!OpInfo.isIndirect) {
3852 // This is the result value of the call.
3853 assert(RetValRegs.Regs.empty() &&
3854 "Cannot have multiple output constraints yet!");
3855 assert(CS.getType() != Type::VoidTy && "Bad inline asm!");
3856 RetValRegs = OpInfo.AssignedRegs;
3858 IndirectStoresToEmit.push_back(std::make_pair(OpInfo.AssignedRegs,
3859 OpInfo.CallOperandVal));
3862 // Add information to the INLINEASM node to know that this register is
3864 OpInfo.AssignedRegs.AddInlineAsmOperands(2 /*REGDEF*/, DAG,
3868 case InlineAsm::isInput: {
3869 SDOperand InOperandVal = OpInfo.CallOperand;
3871 if (isdigit(OpInfo.ConstraintCode[0])) { // Matching constraint?
3872 // If this is required to match an output register we have already set,
3873 // just use its register.
3874 unsigned OperandNo = atoi(OpInfo.ConstraintCode.c_str());
3876 // Scan until we find the definition we already emitted of this operand.
3877 // When we find it, create a RegsForValue operand.
3878 unsigned CurOp = 2; // The first operand.
3879 for (; OperandNo; --OperandNo) {
3880 // Advance to the next operand.
3882 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getValue();
3883 assert(((NumOps & 7) == 2 /*REGDEF*/ ||
3884 (NumOps & 7) == 4 /*MEM*/) &&
3885 "Skipped past definitions?");
3886 CurOp += (NumOps>>3)+1;
3890 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getValue();
3891 if ((NumOps & 7) == 2 /*REGDEF*/) {
3892 // Add NumOps>>3 registers to MatchedRegs.
3893 RegsForValue MatchedRegs;
3894 MatchedRegs.ValueVT = InOperandVal.getValueType();
3895 MatchedRegs.RegVT = AsmNodeOperands[CurOp+1].getValueType();
3896 for (unsigned i = 0, e = NumOps>>3; i != e; ++i) {
3898 cast<RegisterSDNode>(AsmNodeOperands[++CurOp])->getReg();
3899 MatchedRegs.Regs.push_back(Reg);
3902 // Use the produced MatchedRegs object to
3903 MatchedRegs.getCopyToRegs(InOperandVal, DAG, Chain, &Flag);
3904 MatchedRegs.AddInlineAsmOperands(1 /*REGUSE*/, DAG, AsmNodeOperands);
3907 assert((NumOps & 7) == 4/*MEM*/ && "Unknown matching constraint!");
3908 assert((NumOps >> 3) == 1 && "Unexpected number of operands");
3909 // Add information to the INLINEASM node to know about this input.
3910 unsigned ResOpType = 4/*MEM*/ | (1 << 3);
3911 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
3912 TLI.getPointerTy()));
3913 AsmNodeOperands.push_back(AsmNodeOperands[CurOp+1]);
3918 if (OpInfo.ConstraintType == TargetLowering::C_Other) {
3919 assert(!OpInfo.isIndirect &&
3920 "Don't know how to handle indirect other inputs yet!");
3922 std::vector<SDOperand> Ops;
3923 TLI.LowerAsmOperandForConstraint(InOperandVal, OpInfo.ConstraintCode[0],
3926 cerr << "Invalid operand for inline asm constraint '"
3927 << OpInfo.ConstraintCode << "'!\n";
3931 // Add information to the INLINEASM node to know about this input.
3932 unsigned ResOpType = 3 /*IMM*/ | (Ops.size() << 3);
3933 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
3934 TLI.getPointerTy()));
3935 AsmNodeOperands.insert(AsmNodeOperands.end(), Ops.begin(), Ops.end());
3937 } else if (OpInfo.ConstraintType == TargetLowering::C_Memory) {
3938 assert(OpInfo.isIndirect && "Operand must be indirect to be a mem!");
3939 assert(InOperandVal.getValueType() == TLI.getPointerTy() &&
3940 "Memory operands expect pointer values");
3942 // Add information to the INLINEASM node to know about this input.
3943 unsigned ResOpType = 4/*MEM*/ | (1 << 3);
3944 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
3945 TLI.getPointerTy()));
3946 AsmNodeOperands.push_back(InOperandVal);
3950 assert((OpInfo.ConstraintType == TargetLowering::C_RegisterClass ||
3951 OpInfo.ConstraintType == TargetLowering::C_Register) &&
3952 "Unknown constraint type!");
3953 assert(!OpInfo.isIndirect &&
3954 "Don't know how to handle indirect register inputs yet!");
3956 // Copy the input into the appropriate registers.
3957 assert(!OpInfo.AssignedRegs.Regs.empty() &&
3958 "Couldn't allocate input reg!");
3960 OpInfo.AssignedRegs.getCopyToRegs(InOperandVal, DAG, Chain, &Flag);
3962 OpInfo.AssignedRegs.AddInlineAsmOperands(1/*REGUSE*/, DAG,
3966 case InlineAsm::isClobber: {
3967 // Add the clobbered value to the operand list, so that the register
3968 // allocator is aware that the physreg got clobbered.
3969 if (!OpInfo.AssignedRegs.Regs.empty())
3970 OpInfo.AssignedRegs.AddInlineAsmOperands(2/*REGDEF*/, DAG,
3977 // Finish up input operands.
3978 AsmNodeOperands[0] = Chain;
3979 if (Flag.Val) AsmNodeOperands.push_back(Flag);
3981 Chain = DAG.getNode(ISD::INLINEASM,
3982 DAG.getNodeValueTypes(MVT::Other, MVT::Flag), 2,
3983 &AsmNodeOperands[0], AsmNodeOperands.size());
3984 Flag = Chain.getValue(1);
3986 // If this asm returns a register value, copy the result from that register
3987 // and set it as the value of the call.
3988 if (!RetValRegs.Regs.empty()) {
3989 SDOperand Val = RetValRegs.getCopyFromRegs(DAG, Chain, &Flag);
3991 // If the result of the inline asm is a vector, it may have the wrong
3992 // width/num elts. Make sure to convert it to the right type with
3994 if (MVT::isVector(Val.getValueType())) {
3995 const VectorType *VTy = cast<VectorType>(CS.getType());
3996 MVT::ValueType DesiredVT = TLI.getValueType(VTy);
3998 Val = DAG.getNode(ISD::BIT_CONVERT, DesiredVT, Val);
4001 setValue(CS.getInstruction(), Val);
4004 std::vector<std::pair<SDOperand, Value*> > StoresToEmit;
4006 // Process indirect outputs, first output all of the flagged copies out of
4008 for (unsigned i = 0, e = IndirectStoresToEmit.size(); i != e; ++i) {
4009 RegsForValue &OutRegs = IndirectStoresToEmit[i].first;
4010 Value *Ptr = IndirectStoresToEmit[i].second;
4011 SDOperand OutVal = OutRegs.getCopyFromRegs(DAG, Chain, &Flag);
4012 StoresToEmit.push_back(std::make_pair(OutVal, Ptr));
4015 // Emit the non-flagged stores from the physregs.
4016 SmallVector<SDOperand, 8> OutChains;
4017 for (unsigned i = 0, e = StoresToEmit.size(); i != e; ++i)
4018 OutChains.push_back(DAG.getStore(Chain, StoresToEmit[i].first,
4019 getValue(StoresToEmit[i].second),
4020 StoresToEmit[i].second, 0));
4021 if (!OutChains.empty())
4022 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other,
4023 &OutChains[0], OutChains.size());
4028 void SelectionDAGLowering::visitMalloc(MallocInst &I) {
4029 SDOperand Src = getValue(I.getOperand(0));
4031 MVT::ValueType IntPtr = TLI.getPointerTy();
4033 if (IntPtr < Src.getValueType())
4034 Src = DAG.getNode(ISD::TRUNCATE, IntPtr, Src);
4035 else if (IntPtr > Src.getValueType())
4036 Src = DAG.getNode(ISD::ZERO_EXTEND, IntPtr, Src);
4038 // Scale the source by the type size.
4039 uint64_t ElementSize = TD->getABITypeSize(I.getType()->getElementType());
4040 Src = DAG.getNode(ISD::MUL, Src.getValueType(),
4041 Src, DAG.getIntPtrConstant(ElementSize));
4043 TargetLowering::ArgListTy Args;
4044 TargetLowering::ArgListEntry Entry;
4046 Entry.Ty = TLI.getTargetData()->getIntPtrType();
4047 Args.push_back(Entry);
4049 std::pair<SDOperand,SDOperand> Result =
4050 TLI.LowerCallTo(getRoot(), I.getType(), false, false, false, CallingConv::C,
4051 true, DAG.getExternalSymbol("malloc", IntPtr), Args, DAG);
4052 setValue(&I, Result.first); // Pointers always fit in registers
4053 DAG.setRoot(Result.second);
4056 void SelectionDAGLowering::visitFree(FreeInst &I) {
4057 TargetLowering::ArgListTy Args;
4058 TargetLowering::ArgListEntry Entry;
4059 Entry.Node = getValue(I.getOperand(0));
4060 Entry.Ty = TLI.getTargetData()->getIntPtrType();
4061 Args.push_back(Entry);
4062 MVT::ValueType IntPtr = TLI.getPointerTy();
4063 std::pair<SDOperand,SDOperand> Result =
4064 TLI.LowerCallTo(getRoot(), Type::VoidTy, false, false, false,
4065 CallingConv::C, true,
4066 DAG.getExternalSymbol("free", IntPtr), Args, DAG);
4067 DAG.setRoot(Result.second);
4070 // EmitInstrWithCustomInserter - This method should be implemented by targets
4071 // that mark instructions with the 'usesCustomDAGSchedInserter' flag. These
4072 // instructions are special in various ways, which require special support to
4073 // insert. The specified MachineInstr is created but not inserted into any
4074 // basic blocks, and the scheduler passes ownership of it to this method.
4075 MachineBasicBlock *TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
4076 MachineBasicBlock *MBB) {
4077 cerr << "If a target marks an instruction with "
4078 << "'usesCustomDAGSchedInserter', it must implement "
4079 << "TargetLowering::EmitInstrWithCustomInserter!\n";
4084 void SelectionDAGLowering::visitVAStart(CallInst &I) {
4085 DAG.setRoot(DAG.getNode(ISD::VASTART, MVT::Other, getRoot(),
4086 getValue(I.getOperand(1)),
4087 DAG.getSrcValue(I.getOperand(1))));
4090 void SelectionDAGLowering::visitVAArg(VAArgInst &I) {
4091 SDOperand V = DAG.getVAArg(TLI.getValueType(I.getType()), getRoot(),
4092 getValue(I.getOperand(0)),
4093 DAG.getSrcValue(I.getOperand(0)));
4095 DAG.setRoot(V.getValue(1));
4098 void SelectionDAGLowering::visitVAEnd(CallInst &I) {
4099 DAG.setRoot(DAG.getNode(ISD::VAEND, MVT::Other, getRoot(),
4100 getValue(I.getOperand(1)),
4101 DAG.getSrcValue(I.getOperand(1))));
4104 void SelectionDAGLowering::visitVACopy(CallInst &I) {
4105 DAG.setRoot(DAG.getNode(ISD::VACOPY, MVT::Other, getRoot(),
4106 getValue(I.getOperand(1)),
4107 getValue(I.getOperand(2)),
4108 DAG.getSrcValue(I.getOperand(1)),
4109 DAG.getSrcValue(I.getOperand(2))));
4112 /// TargetLowering::LowerArguments - This is the default LowerArguments
4113 /// implementation, which just inserts a FORMAL_ARGUMENTS node. FIXME: When all
4114 /// targets are migrated to using FORMAL_ARGUMENTS, this hook should be
4115 /// integrated into SDISel.
4116 std::vector<SDOperand>
4117 TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
4118 // Add CC# and isVararg as operands to the FORMAL_ARGUMENTS node.
4119 std::vector<SDOperand> Ops;
4120 Ops.push_back(DAG.getRoot());
4121 Ops.push_back(DAG.getConstant(F.getCallingConv(), getPointerTy()));
4122 Ops.push_back(DAG.getConstant(F.isVarArg(), getPointerTy()));
4124 // Add one result value for each formal argument.
4125 std::vector<MVT::ValueType> RetVals;
4127 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end();
4129 MVT::ValueType VT = getValueType(I->getType());
4130 unsigned Flags = ISD::ParamFlags::NoFlagSet;
4131 unsigned OriginalAlignment =
4132 getTargetData()->getABITypeAlignment(I->getType());
4134 // FIXME: Distinguish between a formal with no [sz]ext attribute from one
4135 // that is zero extended!
4136 if (F.paramHasAttr(j, ParamAttr::ZExt))
4137 Flags &= ~(ISD::ParamFlags::SExt);
4138 if (F.paramHasAttr(j, ParamAttr::SExt))
4139 Flags |= ISD::ParamFlags::SExt;
4140 if (F.paramHasAttr(j, ParamAttr::InReg))
4141 Flags |= ISD::ParamFlags::InReg;
4142 if (F.paramHasAttr(j, ParamAttr::StructRet))
4143 Flags |= ISD::ParamFlags::StructReturn;
4144 if (F.paramHasAttr(j, ParamAttr::ByVal)) {
4145 Flags |= ISD::ParamFlags::ByVal;
4146 const PointerType *Ty = cast<PointerType>(I->getType());
4147 const Type *ElementTy = Ty->getElementType();
4148 unsigned FrameAlign = Log2_32(getByValTypeAlignment(ElementTy));
4149 unsigned FrameSize = getTargetData()->getABITypeSize(ElementTy);
4150 // For ByVal, alignment should be passed from FE. BE will guess if
4151 // this info is not there but there are cases it cannot get right.
4152 if (F.getParamAlignment(j))
4153 FrameAlign = Log2_32(F.getParamAlignment(j));
4154 Flags |= (FrameAlign << ISD::ParamFlags::ByValAlignOffs);
4155 Flags |= (FrameSize << ISD::ParamFlags::ByValSizeOffs);
4157 if (F.paramHasAttr(j, ParamAttr::Nest))
4158 Flags |= ISD::ParamFlags::Nest;
4159 Flags |= (OriginalAlignment << ISD::ParamFlags::OrigAlignmentOffs);
4161 MVT::ValueType RegisterVT = getRegisterType(VT);
4162 unsigned NumRegs = getNumRegisters(VT);
4163 for (unsigned i = 0; i != NumRegs; ++i) {
4164 RetVals.push_back(RegisterVT);
4165 // if it isn't first piece, alignment must be 1
4167 Flags = (Flags & (~ISD::ParamFlags::OrigAlignment)) |
4168 (1 << ISD::ParamFlags::OrigAlignmentOffs);
4169 Ops.push_back(DAG.getConstant(Flags, MVT::i32));
4173 RetVals.push_back(MVT::Other);
4176 SDNode *Result = DAG.getNode(ISD::FORMAL_ARGUMENTS,
4177 DAG.getVTList(&RetVals[0], RetVals.size()),
4178 &Ops[0], Ops.size()).Val;
4180 // Prelower FORMAL_ARGUMENTS. This isn't required for functionality, but
4181 // allows exposing the loads that may be part of the argument access to the
4182 // first DAGCombiner pass.
4183 SDOperand TmpRes = LowerOperation(SDOperand(Result, 0), DAG);
4185 // The number of results should match up, except that the lowered one may have
4186 // an extra flag result.
4187 assert((Result->getNumValues() == TmpRes.Val->getNumValues() ||
4188 (Result->getNumValues()+1 == TmpRes.Val->getNumValues() &&
4189 TmpRes.getValue(Result->getNumValues()).getValueType() == MVT::Flag))
4190 && "Lowering produced unexpected number of results!");
4191 Result = TmpRes.Val;
4193 unsigned NumArgRegs = Result->getNumValues() - 1;
4194 DAG.setRoot(SDOperand(Result, NumArgRegs));
4196 // Set up the return result vector.
4200 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E;
4202 MVT::ValueType VT = getValueType(I->getType());
4203 MVT::ValueType PartVT = getRegisterType(VT);
4205 unsigned NumParts = getNumRegisters(VT);
4206 SmallVector<SDOperand, 4> Parts(NumParts);
4207 for (unsigned j = 0; j != NumParts; ++j)
4208 Parts[j] = SDOperand(Result, i++);
4210 ISD::NodeType AssertOp = ISD::DELETED_NODE;
4211 if (F.paramHasAttr(Idx, ParamAttr::SExt))
4212 AssertOp = ISD::AssertSext;
4213 else if (F.paramHasAttr(Idx, ParamAttr::ZExt))
4214 AssertOp = ISD::AssertZext;
4216 Ops.push_back(getCopyFromParts(DAG, &Parts[0], NumParts, PartVT, VT,
4219 assert(i == NumArgRegs && "Argument register count mismatch!");
4224 /// TargetLowering::LowerCallTo - This is the default LowerCallTo
4225 /// implementation, which just inserts an ISD::CALL node, which is later custom
4226 /// lowered by the target to something concrete. FIXME: When all targets are
4227 /// migrated to using ISD::CALL, this hook should be integrated into SDISel.
4228 std::pair<SDOperand, SDOperand>
4229 TargetLowering::LowerCallTo(SDOperand Chain, const Type *RetTy,
4230 bool RetSExt, bool RetZExt, bool isVarArg,
4231 unsigned CallingConv, bool isTailCall,
4233 ArgListTy &Args, SelectionDAG &DAG) {
4234 SmallVector<SDOperand, 32> Ops;
4235 Ops.push_back(Chain); // Op#0 - Chain
4236 Ops.push_back(DAG.getConstant(CallingConv, getPointerTy())); // Op#1 - CC
4237 Ops.push_back(DAG.getConstant(isVarArg, getPointerTy())); // Op#2 - VarArg
4238 Ops.push_back(DAG.getConstant(isTailCall, getPointerTy())); // Op#3 - Tail
4239 Ops.push_back(Callee);
4241 // Handle all of the outgoing arguments.
4242 for (unsigned i = 0, e = Args.size(); i != e; ++i) {
4243 MVT::ValueType VT = getValueType(Args[i].Ty);
4244 SDOperand Op = Args[i].Node;
4245 unsigned Flags = ISD::ParamFlags::NoFlagSet;
4246 unsigned OriginalAlignment =
4247 getTargetData()->getABITypeAlignment(Args[i].Ty);
4250 Flags |= ISD::ParamFlags::SExt;
4252 Flags |= ISD::ParamFlags::ZExt;
4253 if (Args[i].isInReg)
4254 Flags |= ISD::ParamFlags::InReg;
4256 Flags |= ISD::ParamFlags::StructReturn;
4257 if (Args[i].isByVal) {
4258 Flags |= ISD::ParamFlags::ByVal;
4259 const PointerType *Ty = cast<PointerType>(Args[i].Ty);
4260 const Type *ElementTy = Ty->getElementType();
4261 unsigned FrameAlign = Log2_32(getByValTypeAlignment(ElementTy));
4262 unsigned FrameSize = getTargetData()->getABITypeSize(ElementTy);
4263 // For ByVal, alignment should come from FE. BE will guess if this
4264 // info is not there but there are cases it cannot get right.
4265 if (Args[i].Alignment)
4266 FrameAlign = Log2_32(Args[i].Alignment);
4267 Flags |= (FrameAlign << ISD::ParamFlags::ByValAlignOffs);
4268 Flags |= (FrameSize << ISD::ParamFlags::ByValSizeOffs);
4271 Flags |= ISD::ParamFlags::Nest;
4272 Flags |= OriginalAlignment << ISD::ParamFlags::OrigAlignmentOffs;
4274 MVT::ValueType PartVT = getRegisterType(VT);
4275 unsigned NumParts = getNumRegisters(VT);
4276 SmallVector<SDOperand, 4> Parts(NumParts);
4277 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
4280 ExtendKind = ISD::SIGN_EXTEND;
4281 else if (Args[i].isZExt)
4282 ExtendKind = ISD::ZERO_EXTEND;
4284 getCopyToParts(DAG, Op, &Parts[0], NumParts, PartVT, ExtendKind);
4286 for (unsigned i = 0; i != NumParts; ++i) {
4287 // if it isn't first piece, alignment must be 1
4288 unsigned MyFlags = Flags;
4290 MyFlags = (MyFlags & (~ISD::ParamFlags::OrigAlignment)) |
4291 (1 << ISD::ParamFlags::OrigAlignmentOffs);
4293 Ops.push_back(Parts[i]);
4294 Ops.push_back(DAG.getConstant(MyFlags, MVT::i32));
4298 // Figure out the result value types.
4299 MVT::ValueType VT = getValueType(RetTy);
4300 MVT::ValueType RegisterVT = getRegisterType(VT);
4301 unsigned NumRegs = getNumRegisters(VT);
4302 SmallVector<MVT::ValueType, 4> RetTys(NumRegs);
4303 for (unsigned i = 0; i != NumRegs; ++i)
4304 RetTys[i] = RegisterVT;
4306 RetTys.push_back(MVT::Other); // Always has a chain.
4308 // Create the CALL node.
4309 SDOperand Res = DAG.getNode(ISD::CALL,
4310 DAG.getVTList(&RetTys[0], NumRegs + 1),
4311 &Ops[0], Ops.size());
4312 Chain = Res.getValue(NumRegs);
4314 // Gather up the call result into a single value.
4315 if (RetTy != Type::VoidTy) {
4316 ISD::NodeType AssertOp = ISD::DELETED_NODE;
4319 AssertOp = ISD::AssertSext;
4321 AssertOp = ISD::AssertZext;
4323 SmallVector<SDOperand, 4> Results(NumRegs);
4324 for (unsigned i = 0; i != NumRegs; ++i)
4325 Results[i] = Res.getValue(i);
4326 Res = getCopyFromParts(DAG, &Results[0], NumRegs, RegisterVT, VT,
4330 return std::make_pair(Res, Chain);
4333 SDOperand TargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
4334 assert(0 && "LowerOperation not implemented for this target!");
4339 SDOperand TargetLowering::CustomPromoteOperation(SDOperand Op,
4340 SelectionDAG &DAG) {
4341 assert(0 && "CustomPromoteOperation not implemented for this target!");
4346 /// getMemsetValue - Vectorized representation of the memset value
4348 static SDOperand getMemsetValue(SDOperand Value, MVT::ValueType VT,
4349 SelectionDAG &DAG) {
4350 MVT::ValueType CurVT = VT;
4351 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Value)) {
4352 uint64_t Val = C->getValue() & 255;
4354 while (CurVT != MVT::i8) {
4355 Val = (Val << Shift) | Val;
4357 CurVT = (MVT::ValueType)((unsigned)CurVT - 1);
4359 return DAG.getConstant(Val, VT);
4361 Value = DAG.getNode(ISD::ZERO_EXTEND, VT, Value);
4363 while (CurVT != MVT::i8) {
4365 DAG.getNode(ISD::OR, VT,
4366 DAG.getNode(ISD::SHL, VT, Value,
4367 DAG.getConstant(Shift, MVT::i8)), Value);
4369 CurVT = (MVT::ValueType)((unsigned)CurVT - 1);
4376 /// getMemsetStringVal - Similar to getMemsetValue. Except this is only
4377 /// used when a memcpy is turned into a memset when the source is a constant
4379 static SDOperand getMemsetStringVal(MVT::ValueType VT,
4380 SelectionDAG &DAG, TargetLowering &TLI,
4381 std::string &Str, unsigned Offset) {
4383 unsigned MSB = MVT::getSizeInBits(VT) / 8;
4384 if (TLI.isLittleEndian())
4385 Offset = Offset + MSB - 1;
4386 for (unsigned i = 0; i != MSB; ++i) {
4387 Val = (Val << 8) | (unsigned char)Str[Offset];
4388 Offset += TLI.isLittleEndian() ? -1 : 1;
4390 return DAG.getConstant(Val, VT);
4393 /// getMemBasePlusOffset - Returns base and offset node for the
4394 static SDOperand getMemBasePlusOffset(SDOperand Base, unsigned Offset,
4395 SelectionDAG &DAG, TargetLowering &TLI) {
4396 MVT::ValueType VT = Base.getValueType();
4397 return DAG.getNode(ISD::ADD, VT, Base, DAG.getConstant(Offset, VT));
4400 /// MeetsMaxMemopRequirement - Determines if the number of memory ops required
4401 /// to replace the memset / memcpy is below the threshold. It also returns the
4402 /// types of the sequence of memory ops to perform memset / memcpy.
4403 static bool MeetsMaxMemopRequirement(std::vector<MVT::ValueType> &MemOps,
4404 unsigned Limit, uint64_t Size,
4405 unsigned Align, TargetLowering &TLI) {
4408 if (TLI.allowsUnalignedMemoryAccesses()) {
4411 switch (Align & 7) {
4427 MVT::ValueType LVT = MVT::i64;
4428 while (!TLI.isTypeLegal(LVT))
4429 LVT = (MVT::ValueType)((unsigned)LVT - 1);
4430 assert(MVT::isInteger(LVT));
4435 unsigned NumMemOps = 0;
4437 unsigned VTSize = MVT::getSizeInBits(VT) / 8;
4438 while (VTSize > Size) {
4439 VT = (MVT::ValueType)((unsigned)VT - 1);
4442 assert(MVT::isInteger(VT));
4444 if (++NumMemOps > Limit)
4446 MemOps.push_back(VT);
4453 void SelectionDAGLowering::visitMemIntrinsic(CallInst &I, unsigned Op) {
4454 SDOperand Op1 = getValue(I.getOperand(1));
4455 SDOperand Op2 = getValue(I.getOperand(2));
4456 SDOperand Op3 = getValue(I.getOperand(3));
4457 SDOperand Op4 = getValue(I.getOperand(4));
4458 unsigned Align = (unsigned)cast<ConstantSDNode>(Op4)->getValue();
4459 if (Align == 0) Align = 1;
4461 // If the source and destination are known to not be aliases, we can
4462 // lower memmove as memcpy.
4463 if (Op == ISD::MEMMOVE) {
4464 uint64_t Size = -1ULL;
4465 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op3))
4466 Size = C->getValue();
4467 if (AA.alias(I.getOperand(1), Size, I.getOperand(2), Size) ==
4468 AliasAnalysis::NoAlias)
4472 if (ConstantSDNode *Size = dyn_cast<ConstantSDNode>(Op3)) {
4473 std::vector<MVT::ValueType> MemOps;
4475 // Expand memset / memcpy to a series of load / store ops
4476 // if the size operand falls below a certain threshold.
4477 SmallVector<SDOperand, 8> OutChains;
4479 default: break; // Do nothing for now.
4481 if (MeetsMaxMemopRequirement(MemOps, TLI.getMaxStoresPerMemset(),
4482 Size->getValue(), Align, TLI)) {
4483 unsigned NumMemOps = MemOps.size();
4484 unsigned Offset = 0;
4485 for (unsigned i = 0; i < NumMemOps; i++) {
4486 MVT::ValueType VT = MemOps[i];
4487 unsigned VTSize = MVT::getSizeInBits(VT) / 8;
4488 SDOperand Value = getMemsetValue(Op2, VT, DAG);
4489 SDOperand Store = DAG.getStore(getRoot(), Value,
4490 getMemBasePlusOffset(Op1, Offset, DAG, TLI),
4491 I.getOperand(1), Offset);
4492 OutChains.push_back(Store);
4499 if (MeetsMaxMemopRequirement(MemOps, TLI.getMaxStoresPerMemcpy(),
4500 Size->getValue(), Align, TLI)) {
4501 unsigned NumMemOps = MemOps.size();
4502 unsigned SrcOff = 0, DstOff = 0, SrcDelta = 0;
4503 GlobalAddressSDNode *G = NULL;
4505 bool CopyFromStr = false;
4507 if (Op2.getOpcode() == ISD::GlobalAddress)
4508 G = cast<GlobalAddressSDNode>(Op2);
4509 else if (Op2.getOpcode() == ISD::ADD &&
4510 Op2.getOperand(0).getOpcode() == ISD::GlobalAddress &&
4511 Op2.getOperand(1).getOpcode() == ISD::Constant) {
4512 G = cast<GlobalAddressSDNode>(Op2.getOperand(0));
4513 SrcDelta = cast<ConstantSDNode>(Op2.getOperand(1))->getValue();
4516 GlobalVariable *GV = dyn_cast<GlobalVariable>(G->getGlobal());
4517 if (GV && GV->isConstant()) {
4518 Str = GV->getStringValue(false);
4526 for (unsigned i = 0; i < NumMemOps; i++) {
4527 MVT::ValueType VT = MemOps[i];
4528 unsigned VTSize = MVT::getSizeInBits(VT) / 8;
4529 SDOperand Value, Chain, Store;
4532 Value = getMemsetStringVal(VT, DAG, TLI, Str, SrcOff);
4535 DAG.getStore(Chain, Value,
4536 getMemBasePlusOffset(Op1, DstOff, DAG, TLI),
4537 I.getOperand(1), DstOff);
4539 Value = DAG.getLoad(VT, getRoot(),
4540 getMemBasePlusOffset(Op2, SrcOff, DAG, TLI),
4541 I.getOperand(2), SrcOff, false, Align);
4542 Chain = Value.getValue(1);
4544 DAG.getStore(Chain, Value,
4545 getMemBasePlusOffset(Op1, DstOff, DAG, TLI),
4546 I.getOperand(1), DstOff, false, Align);
4548 OutChains.push_back(Store);
4557 if (!OutChains.empty()) {
4558 DAG.setRoot(DAG.getNode(ISD::TokenFactor, MVT::Other,
4559 &OutChains[0], OutChains.size()));
4564 SDOperand AlwaysInline = DAG.getConstant(0, MVT::i1);
4568 assert(0 && "Unknown Op");
4570 Node = DAG.getMemcpy(getRoot(), Op1, Op2, Op3, Op4, AlwaysInline);
4573 Node = DAG.getMemmove(getRoot(), Op1, Op2, Op3, Op4, AlwaysInline);
4576 Node = DAG.getMemset(getRoot(), Op1, Op2, Op3, Op4, AlwaysInline);
4582 //===----------------------------------------------------------------------===//
4583 // SelectionDAGISel code
4584 //===----------------------------------------------------------------------===//
4586 unsigned SelectionDAGISel::MakeReg(MVT::ValueType VT) {
4587 return RegInfo->createVirtualRegister(TLI.getRegClassFor(VT));
4590 void SelectionDAGISel::getAnalysisUsage(AnalysisUsage &AU) const {
4591 AU.addRequired<AliasAnalysis>();
4592 AU.addRequired<CollectorModuleMetadata>();
4593 AU.setPreservesAll();
4598 bool SelectionDAGISel::runOnFunction(Function &Fn) {
4599 // Get alias analysis for load/store combining.
4600 AA = &getAnalysis<AliasAnalysis>();
4602 MachineFunction &MF = MachineFunction::construct(&Fn, TLI.getTargetMachine());
4603 if (MF.getFunction()->hasCollector())
4604 GCI = &getAnalysis<CollectorModuleMetadata>().get(*MF.getFunction());
4607 RegInfo = &MF.getRegInfo();
4608 DOUT << "\n\n\n=== " << Fn.getName() << "\n";
4610 FunctionLoweringInfo FuncInfo(TLI, Fn, MF);
4612 if (ExceptionHandling)
4613 for (Function::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I)
4614 if (InvokeInst *Invoke = dyn_cast<InvokeInst>(I->getTerminator()))
4615 // Mark landing pad.
4616 FuncInfo.MBBMap[Invoke->getSuccessor(1)]->setIsLandingPad();
4618 for (Function::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I)
4619 SelectBasicBlock(I, MF, FuncInfo);
4621 // Add function live-ins to entry block live-in set.
4622 BasicBlock *EntryBB = &Fn.getEntryBlock();
4623 BB = FuncInfo.MBBMap[EntryBB];
4624 if (!RegInfo->livein_empty())
4625 for (MachineRegisterInfo::livein_iterator I = RegInfo->livein_begin(),
4626 E = RegInfo->livein_end(); I != E; ++I)
4627 BB->addLiveIn(I->first);
4630 assert(FuncInfo.CatchInfoFound.size() == FuncInfo.CatchInfoLost.size() &&
4631 "Not all catch info was assigned to a landing pad!");
4637 SDOperand SelectionDAGLowering::CopyValueToVirtualRegister(Value *V,
4639 SDOperand Op = getValue(V);
4640 assert((Op.getOpcode() != ISD::CopyFromReg ||
4641 cast<RegisterSDNode>(Op.getOperand(1))->getReg() != Reg) &&
4642 "Copy from a reg to the same reg!");
4644 MVT::ValueType SrcVT = Op.getValueType();
4645 MVT::ValueType RegisterVT = TLI.getRegisterType(SrcVT);
4646 unsigned NumRegs = TLI.getNumRegisters(SrcVT);
4647 SmallVector<SDOperand, 8> Regs(NumRegs);
4648 SmallVector<SDOperand, 8> Chains(NumRegs);
4650 // Copy the value by legal parts into sequential virtual registers.
4651 getCopyToParts(DAG, Op, &Regs[0], NumRegs, RegisterVT);
4652 for (unsigned i = 0; i != NumRegs; ++i)
4653 Chains[i] = DAG.getCopyToReg(getRoot(), Reg + i, Regs[i]);
4654 return DAG.getNode(ISD::TokenFactor, MVT::Other, &Chains[0], NumRegs);
4657 void SelectionDAGISel::
4658 LowerArguments(BasicBlock *LLVMBB, SelectionDAGLowering &SDL,
4659 std::vector<SDOperand> &UnorderedChains) {
4660 // If this is the entry block, emit arguments.
4661 Function &F = *LLVMBB->getParent();
4662 FunctionLoweringInfo &FuncInfo = SDL.FuncInfo;
4663 SDOperand OldRoot = SDL.DAG.getRoot();
4664 std::vector<SDOperand> Args = TLI.LowerArguments(F, SDL.DAG);
4667 for (Function::arg_iterator AI = F.arg_begin(), E = F.arg_end();
4669 if (!AI->use_empty()) {
4670 SDL.setValue(AI, Args[a]);
4672 // If this argument is live outside of the entry block, insert a copy from
4673 // whereever we got it to the vreg that other BB's will reference it as.
4674 DenseMap<const Value*, unsigned>::iterator VMI=FuncInfo.ValueMap.find(AI);
4675 if (VMI != FuncInfo.ValueMap.end()) {
4676 SDOperand Copy = SDL.CopyValueToVirtualRegister(AI, VMI->second);
4677 UnorderedChains.push_back(Copy);
4681 // Finally, if the target has anything special to do, allow it to do so.
4682 // FIXME: this should insert code into the DAG!
4683 EmitFunctionEntryCode(F, SDL.DAG.getMachineFunction());
4686 static void copyCatchInfo(BasicBlock *SrcBB, BasicBlock *DestBB,
4687 MachineModuleInfo *MMI, FunctionLoweringInfo &FLI) {
4688 for (BasicBlock::iterator I = SrcBB->begin(), E = --SrcBB->end(); I != E; ++I)
4689 if (isSelector(I)) {
4690 // Apply the catch info to DestBB.
4691 addCatchInfo(cast<CallInst>(*I), MMI, FLI.MBBMap[DestBB]);
4693 if (!FLI.MBBMap[SrcBB]->isLandingPad())
4694 FLI.CatchInfoFound.insert(I);
4699 /// CheckDAGForTailCallsAndFixThem - This Function looks for CALL nodes in the
4700 /// DAG and fixes their tailcall attribute operand.
4701 static void CheckDAGForTailCallsAndFixThem(SelectionDAG &DAG,
4702 TargetLowering& TLI) {
4703 SDNode * Ret = NULL;
4704 SDOperand Terminator = DAG.getRoot();
4707 if (Terminator.getOpcode() == ISD::RET) {
4708 Ret = Terminator.Val;
4711 // Fix tail call attribute of CALL nodes.
4712 for (SelectionDAG::allnodes_iterator BE = DAG.allnodes_begin(),
4713 BI = prior(DAG.allnodes_end()); BI != BE; --BI) {
4714 if (BI->getOpcode() == ISD::CALL) {
4715 SDOperand OpRet(Ret, 0);
4716 SDOperand OpCall(static_cast<SDNode*>(BI), 0);
4717 bool isMarkedTailCall =
4718 cast<ConstantSDNode>(OpCall.getOperand(3))->getValue() != 0;
4719 // If CALL node has tail call attribute set to true and the call is not
4720 // eligible (no RET or the target rejects) the attribute is fixed to
4721 // false. The TargetLowering::IsEligibleForTailCallOptimization function
4722 // must correctly identify tail call optimizable calls.
4723 if (isMarkedTailCall &&
4725 !TLI.IsEligibleForTailCallOptimization(OpCall, OpRet, DAG))) {
4726 SmallVector<SDOperand, 32> Ops;
4728 for(SDNode::op_iterator I =OpCall.Val->op_begin(),
4729 E=OpCall.Val->op_end(); I!=E; I++, idx++) {
4733 Ops.push_back(DAG.getConstant(false, TLI.getPointerTy()));
4735 DAG.UpdateNodeOperands(OpCall, Ops.begin(), Ops.size());
4741 void SelectionDAGISel::BuildSelectionDAG(SelectionDAG &DAG, BasicBlock *LLVMBB,
4742 std::vector<std::pair<MachineInstr*, unsigned> > &PHINodesToUpdate,
4743 FunctionLoweringInfo &FuncInfo) {
4744 SelectionDAGLowering SDL(DAG, TLI, *AA, FuncInfo, GCI);
4746 std::vector<SDOperand> UnorderedChains;
4748 // Lower any arguments needed in this block if this is the entry block.
4749 if (LLVMBB == &LLVMBB->getParent()->getEntryBlock())
4750 LowerArguments(LLVMBB, SDL, UnorderedChains);
4752 BB = FuncInfo.MBBMap[LLVMBB];
4753 SDL.setCurrentBasicBlock(BB);
4755 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
4757 if (ExceptionHandling && MMI && BB->isLandingPad()) {
4758 // Add a label to mark the beginning of the landing pad. Deletion of the
4759 // landing pad can thus be detected via the MachineModuleInfo.
4760 unsigned LabelID = MMI->addLandingPad(BB);
4761 DAG.setRoot(DAG.getNode(ISD::LABEL, MVT::Other, DAG.getEntryNode(),
4762 DAG.getConstant(LabelID, MVT::i32),
4763 DAG.getConstant(1, MVT::i32)));
4765 // Mark exception register as live in.
4766 unsigned Reg = TLI.getExceptionAddressRegister();
4767 if (Reg) BB->addLiveIn(Reg);
4769 // Mark exception selector register as live in.
4770 Reg = TLI.getExceptionSelectorRegister();
4771 if (Reg) BB->addLiveIn(Reg);
4773 // FIXME: Hack around an exception handling flaw (PR1508): the personality
4774 // function and list of typeids logically belong to the invoke (or, if you
4775 // like, the basic block containing the invoke), and need to be associated
4776 // with it in the dwarf exception handling tables. Currently however the
4777 // information is provided by an intrinsic (eh.selector) that can be moved
4778 // to unexpected places by the optimizers: if the unwind edge is critical,
4779 // then breaking it can result in the intrinsics being in the successor of
4780 // the landing pad, not the landing pad itself. This results in exceptions
4781 // not being caught because no typeids are associated with the invoke.
4782 // This may not be the only way things can go wrong, but it is the only way
4783 // we try to work around for the moment.
4784 BranchInst *Br = dyn_cast<BranchInst>(LLVMBB->getTerminator());
4786 if (Br && Br->isUnconditional()) { // Critical edge?
4787 BasicBlock::iterator I, E;
4788 for (I = LLVMBB->begin(), E = --LLVMBB->end(); I != E; ++I)
4793 // No catch info found - try to extract some from the successor.
4794 copyCatchInfo(Br->getSuccessor(0), LLVMBB, MMI, FuncInfo);
4798 // Lower all of the non-terminator instructions.
4799 for (BasicBlock::iterator I = LLVMBB->begin(), E = --LLVMBB->end();
4803 // Ensure that all instructions which are used outside of their defining
4804 // blocks are available as virtual registers. Invoke is handled elsewhere.
4805 for (BasicBlock::iterator I = LLVMBB->begin(), E = LLVMBB->end(); I != E;++I)
4806 if (!I->use_empty() && !isa<PHINode>(I) && !isa<InvokeInst>(I)) {
4807 DenseMap<const Value*, unsigned>::iterator VMI =FuncInfo.ValueMap.find(I);
4808 if (VMI != FuncInfo.ValueMap.end())
4809 UnorderedChains.push_back(
4810 SDL.CopyValueToVirtualRegister(I, VMI->second));
4813 // Handle PHI nodes in successor blocks. Emit code into the SelectionDAG to
4814 // ensure constants are generated when needed. Remember the virtual registers
4815 // that need to be added to the Machine PHI nodes as input. We cannot just
4816 // directly add them, because expansion might result in multiple MBB's for one
4817 // BB. As such, the start of the BB might correspond to a different MBB than
4820 TerminatorInst *TI = LLVMBB->getTerminator();
4822 // Emit constants only once even if used by multiple PHI nodes.
4823 std::map<Constant*, unsigned> ConstantsOut;
4825 // Vector bool would be better, but vector<bool> is really slow.
4826 std::vector<unsigned char> SuccsHandled;
4827 if (TI->getNumSuccessors())
4828 SuccsHandled.resize(BB->getParent()->getNumBlockIDs());
4830 // Check successor nodes' PHI nodes that expect a constant to be available
4832 for (unsigned succ = 0, e = TI->getNumSuccessors(); succ != e; ++succ) {
4833 BasicBlock *SuccBB = TI->getSuccessor(succ);
4834 if (!isa<PHINode>(SuccBB->begin())) continue;
4835 MachineBasicBlock *SuccMBB = FuncInfo.MBBMap[SuccBB];
4837 // If this terminator has multiple identical successors (common for
4838 // switches), only handle each succ once.
4839 unsigned SuccMBBNo = SuccMBB->getNumber();
4840 if (SuccsHandled[SuccMBBNo]) continue;
4841 SuccsHandled[SuccMBBNo] = true;
4843 MachineBasicBlock::iterator MBBI = SuccMBB->begin();
4846 // At this point we know that there is a 1-1 correspondence between LLVM PHI
4847 // nodes and Machine PHI nodes, but the incoming operands have not been
4849 for (BasicBlock::iterator I = SuccBB->begin();
4850 (PN = dyn_cast<PHINode>(I)); ++I) {
4851 // Ignore dead phi's.
4852 if (PN->use_empty()) continue;
4855 Value *PHIOp = PN->getIncomingValueForBlock(LLVMBB);
4857 if (Constant *C = dyn_cast<Constant>(PHIOp)) {
4858 unsigned &RegOut = ConstantsOut[C];
4860 RegOut = FuncInfo.CreateRegForValue(C);
4861 UnorderedChains.push_back(
4862 SDL.CopyValueToVirtualRegister(C, RegOut));
4866 Reg = FuncInfo.ValueMap[PHIOp];
4868 assert(isa<AllocaInst>(PHIOp) &&
4869 FuncInfo.StaticAllocaMap.count(cast<AllocaInst>(PHIOp)) &&
4870 "Didn't codegen value into a register!??");
4871 Reg = FuncInfo.CreateRegForValue(PHIOp);
4872 UnorderedChains.push_back(
4873 SDL.CopyValueToVirtualRegister(PHIOp, Reg));
4877 // Remember that this register needs to added to the machine PHI node as
4878 // the input for this MBB.
4879 MVT::ValueType VT = TLI.getValueType(PN->getType());
4880 unsigned NumRegisters = TLI.getNumRegisters(VT);
4881 for (unsigned i = 0, e = NumRegisters; i != e; ++i)
4882 PHINodesToUpdate.push_back(std::make_pair(MBBI++, Reg+i));
4885 ConstantsOut.clear();
4887 // Turn all of the unordered chains into one factored node.
4888 if (!UnorderedChains.empty()) {
4889 SDOperand Root = SDL.getRoot();
4890 if (Root.getOpcode() != ISD::EntryToken) {
4891 unsigned i = 0, e = UnorderedChains.size();
4892 for (; i != e; ++i) {
4893 assert(UnorderedChains[i].Val->getNumOperands() > 1);
4894 if (UnorderedChains[i].Val->getOperand(0) == Root)
4895 break; // Don't add the root if we already indirectly depend on it.
4899 UnorderedChains.push_back(Root);
4901 DAG.setRoot(DAG.getNode(ISD::TokenFactor, MVT::Other,
4902 &UnorderedChains[0], UnorderedChains.size()));
4905 // Lower the terminator after the copies are emitted.
4906 SDL.visit(*LLVMBB->getTerminator());
4908 // Copy over any CaseBlock records that may now exist due to SwitchInst
4909 // lowering, as well as any jump table information.
4910 SwitchCases.clear();
4911 SwitchCases = SDL.SwitchCases;
4913 JTCases = SDL.JTCases;
4914 BitTestCases.clear();
4915 BitTestCases = SDL.BitTestCases;
4917 // Make sure the root of the DAG is up-to-date.
4918 DAG.setRoot(SDL.getRoot());
4920 // Check whether calls in this block are real tail calls. Fix up CALL nodes
4921 // with correct tailcall attribute so that the target can rely on the tailcall
4922 // attribute indicating whether the call is really eligible for tail call
4924 CheckDAGForTailCallsAndFixThem(DAG, TLI);
4927 void SelectionDAGISel::CodeGenAndEmitDAG(SelectionDAG &DAG) {
4928 DOUT << "Lowered selection DAG:\n";
4931 // Run the DAG combiner in pre-legalize mode.
4932 DAG.Combine(false, *AA);
4934 DOUT << "Optimized lowered selection DAG:\n";
4937 // Second step, hack on the DAG until it only uses operations and types that
4938 // the target supports.
4939 #if 0 // Enable this some day.
4940 DAG.LegalizeTypes();
4941 // Someday even later, enable a dag combine pass here.
4945 DOUT << "Legalized selection DAG:\n";
4948 // Run the DAG combiner in post-legalize mode.
4949 DAG.Combine(true, *AA);
4951 DOUT << "Optimized legalized selection DAG:\n";
4954 if (ViewISelDAGs) DAG.viewGraph();
4956 // Third, instruction select all of the operations to machine code, adding the
4957 // code to the MachineBasicBlock.
4958 InstructionSelectBasicBlock(DAG);
4960 DOUT << "Selected machine code:\n";
4964 void SelectionDAGISel::SelectBasicBlock(BasicBlock *LLVMBB, MachineFunction &MF,
4965 FunctionLoweringInfo &FuncInfo) {
4966 std::vector<std::pair<MachineInstr*, unsigned> > PHINodesToUpdate;
4968 SelectionDAG DAG(TLI, MF, getAnalysisToUpdate<MachineModuleInfo>());
4971 // First step, lower LLVM code to some DAG. This DAG may use operations and
4972 // types that are not supported by the target.
4973 BuildSelectionDAG(DAG, LLVMBB, PHINodesToUpdate, FuncInfo);
4975 // Second step, emit the lowered DAG as machine code.
4976 CodeGenAndEmitDAG(DAG);
4979 DOUT << "Total amount of phi nodes to update: "
4980 << PHINodesToUpdate.size() << "\n";
4981 DEBUG(for (unsigned i = 0, e = PHINodesToUpdate.size(); i != e; ++i)
4982 DOUT << "Node " << i << " : (" << PHINodesToUpdate[i].first
4983 << ", " << PHINodesToUpdate[i].second << ")\n";);
4985 // Next, now that we know what the last MBB the LLVM BB expanded is, update
4986 // PHI nodes in successors.
4987 if (SwitchCases.empty() && JTCases.empty() && BitTestCases.empty()) {
4988 for (unsigned i = 0, e = PHINodesToUpdate.size(); i != e; ++i) {
4989 MachineInstr *PHI = PHINodesToUpdate[i].first;
4990 assert(PHI->getOpcode() == TargetInstrInfo::PHI &&
4991 "This is not a machine PHI node that we are updating!");
4992 PHI->addOperand(MachineOperand::CreateReg(PHINodesToUpdate[i].second,
4994 PHI->addOperand(MachineOperand::CreateMBB(BB));
4999 for (unsigned i = 0, e = BitTestCases.size(); i != e; ++i) {
5000 // Lower header first, if it wasn't already lowered
5001 if (!BitTestCases[i].Emitted) {
5002 SelectionDAG HSDAG(TLI, MF, getAnalysisToUpdate<MachineModuleInfo>());
5004 SelectionDAGLowering HSDL(HSDAG, TLI, *AA, FuncInfo, GCI);
5005 // Set the current basic block to the mbb we wish to insert the code into
5006 BB = BitTestCases[i].Parent;
5007 HSDL.setCurrentBasicBlock(BB);
5009 HSDL.visitBitTestHeader(BitTestCases[i]);
5010 HSDAG.setRoot(HSDL.getRoot());
5011 CodeGenAndEmitDAG(HSDAG);
5014 for (unsigned j = 0, ej = BitTestCases[i].Cases.size(); j != ej; ++j) {
5015 SelectionDAG BSDAG(TLI, MF, getAnalysisToUpdate<MachineModuleInfo>());
5017 SelectionDAGLowering BSDL(BSDAG, TLI, *AA, FuncInfo, GCI);
5018 // Set the current basic block to the mbb we wish to insert the code into
5019 BB = BitTestCases[i].Cases[j].ThisBB;
5020 BSDL.setCurrentBasicBlock(BB);
5023 BSDL.visitBitTestCase(BitTestCases[i].Cases[j+1].ThisBB,
5024 BitTestCases[i].Reg,
5025 BitTestCases[i].Cases[j]);
5027 BSDL.visitBitTestCase(BitTestCases[i].Default,
5028 BitTestCases[i].Reg,
5029 BitTestCases[i].Cases[j]);
5032 BSDAG.setRoot(BSDL.getRoot());
5033 CodeGenAndEmitDAG(BSDAG);
5037 for (unsigned pi = 0, pe = PHINodesToUpdate.size(); pi != pe; ++pi) {
5038 MachineInstr *PHI = PHINodesToUpdate[pi].first;
5039 MachineBasicBlock *PHIBB = PHI->getParent();
5040 assert(PHI->getOpcode() == TargetInstrInfo::PHI &&
5041 "This is not a machine PHI node that we are updating!");
5042 // This is "default" BB. We have two jumps to it. From "header" BB and
5043 // from last "case" BB.
5044 if (PHIBB == BitTestCases[i].Default) {
5045 PHI->addOperand(MachineOperand::CreateReg(PHINodesToUpdate[pi].second,
5047 PHI->addOperand(MachineOperand::CreateMBB(BitTestCases[i].Parent));
5048 PHI->addOperand(MachineOperand::CreateReg(PHINodesToUpdate[pi].second,
5050 PHI->addOperand(MachineOperand::CreateMBB(BitTestCases[i].Cases.
5053 // One of "cases" BB.
5054 for (unsigned j = 0, ej = BitTestCases[i].Cases.size(); j != ej; ++j) {
5055 MachineBasicBlock* cBB = BitTestCases[i].Cases[j].ThisBB;
5056 if (cBB->succ_end() !=
5057 std::find(cBB->succ_begin(),cBB->succ_end(), PHIBB)) {
5058 PHI->addOperand(MachineOperand::CreateReg(PHINodesToUpdate[pi].second,
5060 PHI->addOperand(MachineOperand::CreateMBB(cBB));
5066 // If the JumpTable record is filled in, then we need to emit a jump table.
5067 // Updating the PHI nodes is tricky in this case, since we need to determine
5068 // whether the PHI is a successor of the range check MBB or the jump table MBB
5069 for (unsigned i = 0, e = JTCases.size(); i != e; ++i) {
5070 // Lower header first, if it wasn't already lowered
5071 if (!JTCases[i].first.Emitted) {
5072 SelectionDAG HSDAG(TLI, MF, getAnalysisToUpdate<MachineModuleInfo>());
5074 SelectionDAGLowering HSDL(HSDAG, TLI, *AA, FuncInfo, GCI);
5075 // Set the current basic block to the mbb we wish to insert the code into
5076 BB = JTCases[i].first.HeaderBB;
5077 HSDL.setCurrentBasicBlock(BB);
5079 HSDL.visitJumpTableHeader(JTCases[i].second, JTCases[i].first);
5080 HSDAG.setRoot(HSDL.getRoot());
5081 CodeGenAndEmitDAG(HSDAG);
5084 SelectionDAG JSDAG(TLI, MF, getAnalysisToUpdate<MachineModuleInfo>());
5086 SelectionDAGLowering JSDL(JSDAG, TLI, *AA, FuncInfo, GCI);
5087 // Set the current basic block to the mbb we wish to insert the code into
5088 BB = JTCases[i].second.MBB;
5089 JSDL.setCurrentBasicBlock(BB);
5091 JSDL.visitJumpTable(JTCases[i].second);
5092 JSDAG.setRoot(JSDL.getRoot());
5093 CodeGenAndEmitDAG(JSDAG);
5096 for (unsigned pi = 0, pe = PHINodesToUpdate.size(); pi != pe; ++pi) {
5097 MachineInstr *PHI = PHINodesToUpdate[pi].first;
5098 MachineBasicBlock *PHIBB = PHI->getParent();
5099 assert(PHI->getOpcode() == TargetInstrInfo::PHI &&
5100 "This is not a machine PHI node that we are updating!");
5101 // "default" BB. We can go there only from header BB.
5102 if (PHIBB == JTCases[i].second.Default) {
5103 PHI->addOperand(MachineOperand::CreateReg(PHINodesToUpdate[pi].second,
5105 PHI->addOperand(MachineOperand::CreateMBB(JTCases[i].first.HeaderBB));
5107 // JT BB. Just iterate over successors here
5108 if (BB->succ_end() != std::find(BB->succ_begin(),BB->succ_end(), PHIBB)) {
5109 PHI->addOperand(MachineOperand::CreateReg(PHINodesToUpdate[pi].second,
5111 PHI->addOperand(MachineOperand::CreateMBB(BB));
5116 // If the switch block involved a branch to one of the actual successors, we
5117 // need to update PHI nodes in that block.
5118 for (unsigned i = 0, e = PHINodesToUpdate.size(); i != e; ++i) {
5119 MachineInstr *PHI = PHINodesToUpdate[i].first;
5120 assert(PHI->getOpcode() == TargetInstrInfo::PHI &&
5121 "This is not a machine PHI node that we are updating!");
5122 if (BB->isSuccessor(PHI->getParent())) {
5123 PHI->addOperand(MachineOperand::CreateReg(PHINodesToUpdate[i].second,
5125 PHI->addOperand(MachineOperand::CreateMBB(BB));
5129 // If we generated any switch lowering information, build and codegen any
5130 // additional DAGs necessary.
5131 for (unsigned i = 0, e = SwitchCases.size(); i != e; ++i) {
5132 SelectionDAG SDAG(TLI, MF, getAnalysisToUpdate<MachineModuleInfo>());
5134 SelectionDAGLowering SDL(SDAG, TLI, *AA, FuncInfo, GCI);
5136 // Set the current basic block to the mbb we wish to insert the code into
5137 BB = SwitchCases[i].ThisBB;
5138 SDL.setCurrentBasicBlock(BB);
5141 SDL.visitSwitchCase(SwitchCases[i]);
5142 SDAG.setRoot(SDL.getRoot());
5143 CodeGenAndEmitDAG(SDAG);
5145 // Handle any PHI nodes in successors of this chunk, as if we were coming
5146 // from the original BB before switch expansion. Note that PHI nodes can
5147 // occur multiple times in PHINodesToUpdate. We have to be very careful to
5148 // handle them the right number of times.
5149 while ((BB = SwitchCases[i].TrueBB)) { // Handle LHS and RHS.
5150 for (MachineBasicBlock::iterator Phi = BB->begin();
5151 Phi != BB->end() && Phi->getOpcode() == TargetInstrInfo::PHI; ++Phi){
5152 // This value for this PHI node is recorded in PHINodesToUpdate, get it.
5153 for (unsigned pn = 0; ; ++pn) {
5154 assert(pn != PHINodesToUpdate.size() && "Didn't find PHI entry!");
5155 if (PHINodesToUpdate[pn].first == Phi) {
5156 Phi->addOperand(MachineOperand::CreateReg(PHINodesToUpdate[pn].
5158 Phi->addOperand(MachineOperand::CreateMBB(SwitchCases[i].ThisBB));
5164 // Don't process RHS if same block as LHS.
5165 if (BB == SwitchCases[i].FalseBB)
5166 SwitchCases[i].FalseBB = 0;
5168 // If we haven't handled the RHS, do so now. Otherwise, we're done.
5169 SwitchCases[i].TrueBB = SwitchCases[i].FalseBB;
5170 SwitchCases[i].FalseBB = 0;
5172 assert(SwitchCases[i].TrueBB == 0 && SwitchCases[i].FalseBB == 0);
5177 //===----------------------------------------------------------------------===//
5178 /// ScheduleAndEmitDAG - Pick a safe ordering and emit instructions for each
5179 /// target node in the graph.
5180 void SelectionDAGISel::ScheduleAndEmitDAG(SelectionDAG &DAG) {
5181 if (ViewSchedDAGs) DAG.viewGraph();
5183 RegisterScheduler::FunctionPassCtor Ctor = RegisterScheduler::getDefault();
5187 RegisterScheduler::setDefault(Ctor);
5190 ScheduleDAG *SL = Ctor(this, &DAG, BB);
5193 if (ViewSUnitDAGs) SL->viewGraph();
5199 HazardRecognizer *SelectionDAGISel::CreateTargetHazardRecognizer() {
5200 return new HazardRecognizer();
5203 //===----------------------------------------------------------------------===//
5204 // Helper functions used by the generated instruction selector.
5205 //===----------------------------------------------------------------------===//
5206 // Calls to these methods are generated by tblgen.
5208 /// CheckAndMask - The isel is trying to match something like (and X, 255). If
5209 /// the dag combiner simplified the 255, we still want to match. RHS is the
5210 /// actual value in the DAG on the RHS of an AND, and DesiredMaskS is the value
5211 /// specified in the .td file (e.g. 255).
5212 bool SelectionDAGISel::CheckAndMask(SDOperand LHS, ConstantSDNode *RHS,
5213 int64_t DesiredMaskS) const {
5214 uint64_t ActualMask = RHS->getValue();
5215 uint64_t DesiredMask =DesiredMaskS & MVT::getIntVTBitMask(LHS.getValueType());
5217 // If the actual mask exactly matches, success!
5218 if (ActualMask == DesiredMask)
5221 // If the actual AND mask is allowing unallowed bits, this doesn't match.
5222 if (ActualMask & ~DesiredMask)
5225 // Otherwise, the DAG Combiner may have proven that the value coming in is
5226 // either already zero or is not demanded. Check for known zero input bits.
5227 uint64_t NeededMask = DesiredMask & ~ActualMask;
5228 if (CurDAG->MaskedValueIsZero(LHS, NeededMask))
5231 // TODO: check to see if missing bits are just not demanded.
5233 // Otherwise, this pattern doesn't match.
5237 /// CheckOrMask - The isel is trying to match something like (or X, 255). If
5238 /// the dag combiner simplified the 255, we still want to match. RHS is the
5239 /// actual value in the DAG on the RHS of an OR, and DesiredMaskS is the value
5240 /// specified in the .td file (e.g. 255).
5241 bool SelectionDAGISel::CheckOrMask(SDOperand LHS, ConstantSDNode *RHS,
5242 int64_t DesiredMaskS) const {
5243 uint64_t ActualMask = RHS->getValue();
5244 uint64_t DesiredMask =DesiredMaskS & MVT::getIntVTBitMask(LHS.getValueType());
5246 // If the actual mask exactly matches, success!
5247 if (ActualMask == DesiredMask)
5250 // If the actual AND mask is allowing unallowed bits, this doesn't match.
5251 if (ActualMask & ~DesiredMask)
5254 // Otherwise, the DAG Combiner may have proven that the value coming in is
5255 // either already zero or is not demanded. Check for known zero input bits.
5256 uint64_t NeededMask = DesiredMask & ~ActualMask;
5258 uint64_t KnownZero, KnownOne;
5259 CurDAG->ComputeMaskedBits(LHS, NeededMask, KnownZero, KnownOne);
5261 // If all the missing bits in the or are already known to be set, match!
5262 if ((NeededMask & KnownOne) == NeededMask)
5265 // TODO: check to see if missing bits are just not demanded.
5267 // Otherwise, this pattern doesn't match.
5272 /// SelectInlineAsmMemoryOperands - Calls to this are automatically generated
5273 /// by tblgen. Others should not call it.
5274 void SelectionDAGISel::
5275 SelectInlineAsmMemoryOperands(std::vector<SDOperand> &Ops, SelectionDAG &DAG) {
5276 std::vector<SDOperand> InOps;
5277 std::swap(InOps, Ops);
5279 Ops.push_back(InOps[0]); // input chain.
5280 Ops.push_back(InOps[1]); // input asm string.
5282 unsigned i = 2, e = InOps.size();
5283 if (InOps[e-1].getValueType() == MVT::Flag)
5284 --e; // Don't process a flag operand if it is here.
5287 unsigned Flags = cast<ConstantSDNode>(InOps[i])->getValue();
5288 if ((Flags & 7) != 4 /*MEM*/) {
5289 // Just skip over this operand, copying the operands verbatim.
5290 Ops.insert(Ops.end(), InOps.begin()+i, InOps.begin()+i+(Flags >> 3) + 1);
5291 i += (Flags >> 3) + 1;
5293 assert((Flags >> 3) == 1 && "Memory operand with multiple values?");
5294 // Otherwise, this is a memory operand. Ask the target to select it.
5295 std::vector<SDOperand> SelOps;
5296 if (SelectInlineAsmMemoryOperand(InOps[i+1], 'm', SelOps, DAG)) {
5297 cerr << "Could not match memory address. Inline asm failure!\n";
5301 // Add this to the output node.
5302 MVT::ValueType IntPtrTy = DAG.getTargetLoweringInfo().getPointerTy();
5303 Ops.push_back(DAG.getTargetConstant(4/*MEM*/ | (SelOps.size() << 3),
5305 Ops.insert(Ops.end(), SelOps.begin(), SelOps.end());
5310 // Add the flag input back if present.
5311 if (e != InOps.size())
5312 Ops.push_back(InOps.back());
5315 char SelectionDAGISel::ID = 0;