1 //===-- SelectionDAGISel.cpp - Implement the SelectionDAGISel class -------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements the SelectionDAGISel class.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "isel"
15 #include "llvm/ADT/BitVector.h"
16 #include "llvm/Analysis/AliasAnalysis.h"
17 #include "llvm/CodeGen/SelectionDAGISel.h"
18 #include "llvm/CodeGen/ScheduleDAG.h"
19 #include "llvm/Constants.h"
20 #include "llvm/CallingConv.h"
21 #include "llvm/DerivedTypes.h"
22 #include "llvm/Function.h"
23 #include "llvm/GlobalVariable.h"
24 #include "llvm/InlineAsm.h"
25 #include "llvm/Instructions.h"
26 #include "llvm/Intrinsics.h"
27 #include "llvm/IntrinsicInst.h"
28 #include "llvm/ParameterAttributes.h"
29 #include "llvm/CodeGen/MachineModuleInfo.h"
30 #include "llvm/CodeGen/MachineFunction.h"
31 #include "llvm/CodeGen/MachineFrameInfo.h"
32 #include "llvm/CodeGen/MachineJumpTableInfo.h"
33 #include "llvm/CodeGen/MachineInstrBuilder.h"
34 #include "llvm/CodeGen/SchedulerRegistry.h"
35 #include "llvm/CodeGen/SelectionDAG.h"
36 #include "llvm/CodeGen/SSARegMap.h"
37 #include "llvm/Target/MRegisterInfo.h"
38 #include "llvm/Target/TargetData.h"
39 #include "llvm/Target/TargetFrameInfo.h"
40 #include "llvm/Target/TargetInstrInfo.h"
41 #include "llvm/Target/TargetLowering.h"
42 #include "llvm/Target/TargetMachine.h"
43 #include "llvm/Target/TargetOptions.h"
44 #include "llvm/Support/MathExtras.h"
45 #include "llvm/Support/Debug.h"
46 #include "llvm/Support/Compiler.h"
52 ViewISelDAGs("view-isel-dags", cl::Hidden,
53 cl::desc("Pop up a window to show isel dags as they are selected"));
55 ViewSchedDAGs("view-sched-dags", cl::Hidden,
56 cl::desc("Pop up a window to show sched dags as they are processed"));
58 ViewSUnitDAGs("view-sunit-dags", cl::Hidden,
59 cl::desc("Pop up a window to show SUnit dags after they are processed"));
61 static const bool ViewISelDAGs = 0, ViewSchedDAGs = 0, ViewSUnitDAGs = 0;
64 //===---------------------------------------------------------------------===//
66 /// RegisterScheduler class - Track the registration of instruction schedulers.
68 //===---------------------------------------------------------------------===//
69 MachinePassRegistry RegisterScheduler::Registry;
71 //===---------------------------------------------------------------------===//
73 /// ISHeuristic command line option for instruction schedulers.
75 //===---------------------------------------------------------------------===//
77 cl::opt<RegisterScheduler::FunctionPassCtor, false,
78 RegisterPassParser<RegisterScheduler> >
79 ISHeuristic("pre-RA-sched",
80 cl::init(&createDefaultScheduler),
81 cl::desc("Instruction schedulers available (before register allocation):"));
83 static RegisterScheduler
84 defaultListDAGScheduler("default", " Best scheduler for the target",
85 createDefaultScheduler);
88 namespace { struct AsmOperandInfo; }
91 /// RegsForValue - This struct represents the physical registers that a
92 /// particular value is assigned and the type information about the value.
93 /// This is needed because values can be promoted into larger registers and
94 /// expanded into multiple smaller registers than the value.
95 struct VISIBILITY_HIDDEN RegsForValue {
96 /// Regs - This list holds the register (for legal and promoted values)
97 /// or register set (for expanded values) that the value should be assigned
99 std::vector<unsigned> Regs;
101 /// RegVT - The value type of each register.
103 MVT::ValueType RegVT;
105 /// ValueVT - The value type of the LLVM value, which may be promoted from
106 /// RegVT or made from merging the two expanded parts.
107 MVT::ValueType ValueVT;
109 RegsForValue() : RegVT(MVT::Other), ValueVT(MVT::Other) {}
111 RegsForValue(unsigned Reg, MVT::ValueType regvt, MVT::ValueType valuevt)
112 : RegVT(regvt), ValueVT(valuevt) {
115 RegsForValue(const std::vector<unsigned> ®s,
116 MVT::ValueType regvt, MVT::ValueType valuevt)
117 : Regs(regs), RegVT(regvt), ValueVT(valuevt) {
120 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from
121 /// this value and returns the result as a ValueVT value. This uses
122 /// Chain/Flag as the input and updates them for the output Chain/Flag.
123 /// If the Flag pointer is NULL, no flag is used.
124 SDOperand getCopyFromRegs(SelectionDAG &DAG,
125 SDOperand &Chain, SDOperand *Flag) const;
127 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
128 /// specified value into the registers specified by this object. This uses
129 /// Chain/Flag as the input and updates them for the output Chain/Flag.
130 /// If the Flag pointer is NULL, no flag is used.
131 void getCopyToRegs(SDOperand Val, SelectionDAG &DAG,
132 SDOperand &Chain, SDOperand *Flag) const;
134 /// AddInlineAsmOperands - Add this value to the specified inlineasm node
135 /// operand list. This adds the code marker and includes the number of
136 /// values added into it.
137 void AddInlineAsmOperands(unsigned Code, SelectionDAG &DAG,
138 std::vector<SDOperand> &Ops) const;
143 //===--------------------------------------------------------------------===//
144 /// createDefaultScheduler - This creates an instruction scheduler appropriate
146 ScheduleDAG* createDefaultScheduler(SelectionDAGISel *IS,
148 MachineBasicBlock *BB) {
149 TargetLowering &TLI = IS->getTargetLowering();
151 if (TLI.getSchedulingPreference() == TargetLowering::SchedulingForLatency) {
152 return createTDListDAGScheduler(IS, DAG, BB);
154 assert(TLI.getSchedulingPreference() ==
155 TargetLowering::SchedulingForRegPressure && "Unknown sched type!");
156 return createBURRListDAGScheduler(IS, DAG, BB);
161 //===--------------------------------------------------------------------===//
162 /// FunctionLoweringInfo - This contains information that is global to a
163 /// function that is used when lowering a region of the function.
164 class FunctionLoweringInfo {
171 FunctionLoweringInfo(TargetLowering &TLI, Function &Fn,MachineFunction &MF);
173 /// MBBMap - A mapping from LLVM basic blocks to their machine code entry.
174 std::map<const BasicBlock*, MachineBasicBlock *> MBBMap;
176 /// ValueMap - Since we emit code for the function a basic block at a time,
177 /// we must remember which virtual registers hold the values for
178 /// cross-basic-block values.
179 DenseMap<const Value*, unsigned> ValueMap;
181 /// StaticAllocaMap - Keep track of frame indices for fixed sized allocas in
182 /// the entry block. This allows the allocas to be efficiently referenced
183 /// anywhere in the function.
184 std::map<const AllocaInst*, int> StaticAllocaMap;
187 SmallSet<Instruction*, 8> CatchInfoLost;
188 SmallSet<Instruction*, 8> CatchInfoFound;
191 unsigned MakeReg(MVT::ValueType VT) {
192 return RegMap->createVirtualRegister(TLI.getRegClassFor(VT));
195 /// isExportedInst - Return true if the specified value is an instruction
196 /// exported from its block.
197 bool isExportedInst(const Value *V) {
198 return ValueMap.count(V);
201 unsigned CreateRegForValue(const Value *V);
203 unsigned InitializeRegForValue(const Value *V) {
204 unsigned &R = ValueMap[V];
205 assert(R == 0 && "Already initialized this value register!");
206 return R = CreateRegForValue(V);
211 /// isSelector - Return true if this instruction is a call to the
212 /// eh.selector intrinsic.
213 static bool isSelector(Instruction *I) {
214 if (IntrinsicInst *II = dyn_cast<IntrinsicInst>(I))
215 return II->getIntrinsicID() == Intrinsic::eh_selector;
219 /// isUsedOutsideOfDefiningBlock - Return true if this instruction is used by
220 /// PHI nodes or outside of the basic block that defines it, or used by a
221 /// switch instruction, which may expand to multiple basic blocks.
222 static bool isUsedOutsideOfDefiningBlock(Instruction *I) {
223 if (isa<PHINode>(I)) return true;
224 BasicBlock *BB = I->getParent();
225 for (Value::use_iterator UI = I->use_begin(), E = I->use_end(); UI != E; ++UI)
226 if (cast<Instruction>(*UI)->getParent() != BB || isa<PHINode>(*UI) ||
227 // FIXME: Remove switchinst special case.
228 isa<SwitchInst>(*UI))
233 /// isOnlyUsedInEntryBlock - If the specified argument is only used in the
234 /// entry block, return true. This includes arguments used by switches, since
235 /// the switch may expand into multiple basic blocks.
236 static bool isOnlyUsedInEntryBlock(Argument *A) {
237 BasicBlock *Entry = A->getParent()->begin();
238 for (Value::use_iterator UI = A->use_begin(), E = A->use_end(); UI != E; ++UI)
239 if (cast<Instruction>(*UI)->getParent() != Entry || isa<SwitchInst>(*UI))
240 return false; // Use not in entry block.
244 FunctionLoweringInfo::FunctionLoweringInfo(TargetLowering &tli,
245 Function &fn, MachineFunction &mf)
246 : TLI(tli), Fn(fn), MF(mf), RegMap(MF.getSSARegMap()) {
248 // Create a vreg for each argument register that is not dead and is used
249 // outside of the entry block for the function.
250 for (Function::arg_iterator AI = Fn.arg_begin(), E = Fn.arg_end();
252 if (!isOnlyUsedInEntryBlock(AI))
253 InitializeRegForValue(AI);
255 // Initialize the mapping of values to registers. This is only set up for
256 // instruction values that are used outside of the block that defines
258 Function::iterator BB = Fn.begin(), EB = Fn.end();
259 for (BasicBlock::iterator I = BB->begin(), E = BB->end(); I != E; ++I)
260 if (AllocaInst *AI = dyn_cast<AllocaInst>(I))
261 if (ConstantInt *CUI = dyn_cast<ConstantInt>(AI->getArraySize())) {
262 const Type *Ty = AI->getAllocatedType();
263 uint64_t TySize = TLI.getTargetData()->getTypeSize(Ty);
265 std::max((unsigned)TLI.getTargetData()->getPrefTypeAlignment(Ty),
268 TySize *= CUI->getZExtValue(); // Get total allocated size.
269 if (TySize == 0) TySize = 1; // Don't create zero-sized stack objects.
270 StaticAllocaMap[AI] =
271 MF.getFrameInfo()->CreateStackObject(TySize, Align);
274 for (; BB != EB; ++BB)
275 for (BasicBlock::iterator I = BB->begin(), E = BB->end(); I != E; ++I)
276 if (!I->use_empty() && isUsedOutsideOfDefiningBlock(I))
277 if (!isa<AllocaInst>(I) ||
278 !StaticAllocaMap.count(cast<AllocaInst>(I)))
279 InitializeRegForValue(I);
281 // Create an initial MachineBasicBlock for each LLVM BasicBlock in F. This
282 // also creates the initial PHI MachineInstrs, though none of the input
283 // operands are populated.
284 for (BB = Fn.begin(), EB = Fn.end(); BB != EB; ++BB) {
285 MachineBasicBlock *MBB = new MachineBasicBlock(BB);
287 MF.getBasicBlockList().push_back(MBB);
289 // Create Machine PHI nodes for LLVM PHI nodes, lowering them as
292 for (BasicBlock::iterator I = BB->begin();(PN = dyn_cast<PHINode>(I)); ++I){
293 if (PN->use_empty()) continue;
295 MVT::ValueType VT = TLI.getValueType(PN->getType());
296 unsigned NumRegisters = TLI.getNumRegisters(VT);
297 unsigned PHIReg = ValueMap[PN];
298 assert(PHIReg && "PHI node does not have an assigned virtual register!");
299 const TargetInstrInfo *TII = TLI.getTargetMachine().getInstrInfo();
300 for (unsigned i = 0; i != NumRegisters; ++i)
301 BuildMI(MBB, TII->get(TargetInstrInfo::PHI), PHIReg+i);
306 /// CreateRegForValue - Allocate the appropriate number of virtual registers of
307 /// the correctly promoted or expanded types. Assign these registers
308 /// consecutive vreg numbers and return the first assigned number.
309 unsigned FunctionLoweringInfo::CreateRegForValue(const Value *V) {
310 MVT::ValueType VT = TLI.getValueType(V->getType());
312 unsigned NumRegisters = TLI.getNumRegisters(VT);
313 MVT::ValueType RegisterVT = TLI.getRegisterType(VT);
315 unsigned R = MakeReg(RegisterVT);
316 for (unsigned i = 1; i != NumRegisters; ++i)
322 //===----------------------------------------------------------------------===//
323 /// SelectionDAGLowering - This is the common target-independent lowering
324 /// implementation that is parameterized by a TargetLowering object.
325 /// Also, targets can overload any lowering method.
328 class SelectionDAGLowering {
329 MachineBasicBlock *CurMBB;
331 DenseMap<const Value*, SDOperand> NodeMap;
333 /// PendingLoads - Loads are not emitted to the program immediately. We bunch
334 /// them up and then emit token factor nodes when possible. This allows us to
335 /// get simple disambiguation between loads without worrying about alias
337 std::vector<SDOperand> PendingLoads;
339 /// Case - A struct to record the Value for a switch case, and the
340 /// case's target basic block.
344 MachineBasicBlock* BB;
346 Case() : Low(0), High(0), BB(0) { }
347 Case(Constant* low, Constant* high, MachineBasicBlock* bb) :
348 Low(low), High(high), BB(bb) { }
349 uint64_t size() const {
350 uint64_t rHigh = cast<ConstantInt>(High)->getSExtValue();
351 uint64_t rLow = cast<ConstantInt>(Low)->getSExtValue();
352 return (rHigh - rLow + 1ULL);
358 MachineBasicBlock* BB;
361 CaseBits(uint64_t mask, MachineBasicBlock* bb, unsigned bits):
362 Mask(mask), BB(bb), Bits(bits) { }
365 typedef std::vector<Case> CaseVector;
366 typedef std::vector<CaseBits> CaseBitsVector;
367 typedef CaseVector::iterator CaseItr;
368 typedef std::pair<CaseItr, CaseItr> CaseRange;
370 /// CaseRec - A struct with ctor used in lowering switches to a binary tree
371 /// of conditional branches.
373 CaseRec(MachineBasicBlock *bb, Constant *lt, Constant *ge, CaseRange r) :
374 CaseBB(bb), LT(lt), GE(ge), Range(r) {}
376 /// CaseBB - The MBB in which to emit the compare and branch
377 MachineBasicBlock *CaseBB;
378 /// LT, GE - If nonzero, we know the current case value must be less-than or
379 /// greater-than-or-equal-to these Constants.
382 /// Range - A pair of iterators representing the range of case values to be
383 /// processed at this point in the binary search tree.
387 typedef std::vector<CaseRec> CaseRecVector;
389 /// The comparison function for sorting the switch case values in the vector.
390 /// WARNING: Case ranges should be disjoint!
392 bool operator () (const Case& C1, const Case& C2) {
393 assert(isa<ConstantInt>(C1.Low) && isa<ConstantInt>(C2.High));
394 const ConstantInt* CI1 = cast<const ConstantInt>(C1.Low);
395 const ConstantInt* CI2 = cast<const ConstantInt>(C2.High);
396 return CI1->getValue().slt(CI2->getValue());
401 bool operator () (const CaseBits& C1, const CaseBits& C2) {
402 return C1.Bits > C2.Bits;
406 unsigned Clusterify(CaseVector& Cases, const SwitchInst &SI);
409 // TLI - This is information that describes the available target features we
410 // need for lowering. This indicates when operations are unavailable,
411 // implemented with a libcall, etc.
414 const TargetData *TD;
417 /// SwitchCases - Vector of CaseBlock structures used to communicate
418 /// SwitchInst code generation information.
419 std::vector<SelectionDAGISel::CaseBlock> SwitchCases;
420 /// JTCases - Vector of JumpTable structures used to communicate
421 /// SwitchInst code generation information.
422 std::vector<SelectionDAGISel::JumpTableBlock> JTCases;
423 std::vector<SelectionDAGISel::BitTestBlock> BitTestCases;
425 /// FuncInfo - Information about the function as a whole.
427 FunctionLoweringInfo &FuncInfo;
429 SelectionDAGLowering(SelectionDAG &dag, TargetLowering &tli,
431 FunctionLoweringInfo &funcinfo)
432 : TLI(tli), DAG(dag), TD(DAG.getTarget().getTargetData()), AA(aa),
436 /// getRoot - Return the current virtual root of the Selection DAG.
438 SDOperand getRoot() {
439 if (PendingLoads.empty())
440 return DAG.getRoot();
442 if (PendingLoads.size() == 1) {
443 SDOperand Root = PendingLoads[0];
445 PendingLoads.clear();
449 // Otherwise, we have to make a token factor node.
450 SDOperand Root = DAG.getNode(ISD::TokenFactor, MVT::Other,
451 &PendingLoads[0], PendingLoads.size());
452 PendingLoads.clear();
457 SDOperand CopyValueToVirtualRegister(Value *V, unsigned Reg);
459 void visit(Instruction &I) { visit(I.getOpcode(), I); }
461 void visit(unsigned Opcode, User &I) {
462 // Note: this doesn't use InstVisitor, because it has to work with
463 // ConstantExpr's in addition to instructions.
465 default: assert(0 && "Unknown instruction type encountered!");
467 // Build the switch statement using the Instruction.def file.
468 #define HANDLE_INST(NUM, OPCODE, CLASS) \
469 case Instruction::OPCODE:return visit##OPCODE((CLASS&)I);
470 #include "llvm/Instruction.def"
474 void setCurrentBasicBlock(MachineBasicBlock *MBB) { CurMBB = MBB; }
476 SDOperand getLoadFrom(const Type *Ty, SDOperand Ptr,
477 const Value *SV, SDOperand Root,
478 bool isVolatile, unsigned Alignment);
480 SDOperand getIntPtrConstant(uint64_t Val) {
481 return DAG.getConstant(Val, TLI.getPointerTy());
484 SDOperand getValue(const Value *V);
486 void setValue(const Value *V, SDOperand NewN) {
487 SDOperand &N = NodeMap[V];
488 assert(N.Val == 0 && "Already set a value for this node!");
492 void GetRegistersForValue(AsmOperandInfo &OpInfo, bool HasEarlyClobber,
493 std::set<unsigned> &OutputRegs,
494 std::set<unsigned> &InputRegs);
496 void FindMergedConditions(Value *Cond, MachineBasicBlock *TBB,
497 MachineBasicBlock *FBB, MachineBasicBlock *CurBB,
499 bool isExportableFromCurrentBlock(Value *V, const BasicBlock *FromBB);
500 void ExportFromCurrentBlock(Value *V);
501 void LowerCallTo(Instruction &I,
502 const Type *CalledValueTy, unsigned CallingConv,
503 bool IsTailCall, SDOperand Callee, unsigned OpIdx,
504 MachineBasicBlock *LandingPad = NULL);
506 // Terminator instructions.
507 void visitRet(ReturnInst &I);
508 void visitBr(BranchInst &I);
509 void visitSwitch(SwitchInst &I);
510 void visitUnreachable(UnreachableInst &I) { /* noop */ }
512 // Helpers for visitSwitch
513 bool handleSmallSwitchRange(CaseRec& CR,
514 CaseRecVector& WorkList,
516 MachineBasicBlock* Default);
517 bool handleJTSwitchCase(CaseRec& CR,
518 CaseRecVector& WorkList,
520 MachineBasicBlock* Default);
521 bool handleBTSplitSwitchCase(CaseRec& CR,
522 CaseRecVector& WorkList,
524 MachineBasicBlock* Default);
525 bool handleBitTestsSwitchCase(CaseRec& CR,
526 CaseRecVector& WorkList,
528 MachineBasicBlock* Default);
529 void visitSwitchCase(SelectionDAGISel::CaseBlock &CB);
530 void visitBitTestHeader(SelectionDAGISel::BitTestBlock &B);
531 void visitBitTestCase(MachineBasicBlock* NextMBB,
533 SelectionDAGISel::BitTestCase &B);
534 void visitJumpTable(SelectionDAGISel::JumpTable &JT);
535 void visitJumpTableHeader(SelectionDAGISel::JumpTable &JT,
536 SelectionDAGISel::JumpTableHeader &JTH);
538 // These all get lowered before this pass.
539 void visitInvoke(InvokeInst &I);
540 void visitUnwind(UnwindInst &I);
542 void visitBinary(User &I, unsigned OpCode);
543 void visitShift(User &I, unsigned Opcode);
544 void visitAdd(User &I) {
545 if (I.getType()->isFPOrFPVector())
546 visitBinary(I, ISD::FADD);
548 visitBinary(I, ISD::ADD);
550 void visitSub(User &I);
551 void visitMul(User &I) {
552 if (I.getType()->isFPOrFPVector())
553 visitBinary(I, ISD::FMUL);
555 visitBinary(I, ISD::MUL);
557 void visitURem(User &I) { visitBinary(I, ISD::UREM); }
558 void visitSRem(User &I) { visitBinary(I, ISD::SREM); }
559 void visitFRem(User &I) { visitBinary(I, ISD::FREM); }
560 void visitUDiv(User &I) { visitBinary(I, ISD::UDIV); }
561 void visitSDiv(User &I) { visitBinary(I, ISD::SDIV); }
562 void visitFDiv(User &I) { visitBinary(I, ISD::FDIV); }
563 void visitAnd (User &I) { visitBinary(I, ISD::AND); }
564 void visitOr (User &I) { visitBinary(I, ISD::OR); }
565 void visitXor (User &I) { visitBinary(I, ISD::XOR); }
566 void visitShl (User &I) { visitShift(I, ISD::SHL); }
567 void visitLShr(User &I) { visitShift(I, ISD::SRL); }
568 void visitAShr(User &I) { visitShift(I, ISD::SRA); }
569 void visitICmp(User &I);
570 void visitFCmp(User &I);
571 // Visit the conversion instructions
572 void visitTrunc(User &I);
573 void visitZExt(User &I);
574 void visitSExt(User &I);
575 void visitFPTrunc(User &I);
576 void visitFPExt(User &I);
577 void visitFPToUI(User &I);
578 void visitFPToSI(User &I);
579 void visitUIToFP(User &I);
580 void visitSIToFP(User &I);
581 void visitPtrToInt(User &I);
582 void visitIntToPtr(User &I);
583 void visitBitCast(User &I);
585 void visitExtractElement(User &I);
586 void visitInsertElement(User &I);
587 void visitShuffleVector(User &I);
589 void visitGetElementPtr(User &I);
590 void visitSelect(User &I);
592 void visitMalloc(MallocInst &I);
593 void visitFree(FreeInst &I);
594 void visitAlloca(AllocaInst &I);
595 void visitLoad(LoadInst &I);
596 void visitStore(StoreInst &I);
597 void visitPHI(PHINode &I) { } // PHI nodes are handled specially.
598 void visitCall(CallInst &I);
599 void visitInlineAsm(CallInst &I);
600 const char *visitIntrinsicCall(CallInst &I, unsigned Intrinsic);
601 void visitTargetIntrinsic(CallInst &I, unsigned Intrinsic);
603 void visitVAStart(CallInst &I);
604 void visitVAArg(VAArgInst &I);
605 void visitVAEnd(CallInst &I);
606 void visitVACopy(CallInst &I);
608 void visitMemIntrinsic(CallInst &I, unsigned Op);
610 void visitUserOp1(Instruction &I) {
611 assert(0 && "UserOp1 should not exist at instruction selection time!");
614 void visitUserOp2(Instruction &I) {
615 assert(0 && "UserOp2 should not exist at instruction selection time!");
619 } // end namespace llvm
622 /// getCopyFromParts - Create a value that contains the
623 /// specified legal parts combined into the value they represent.
624 static SDOperand getCopyFromParts(SelectionDAG &DAG,
625 const SDOperand *Parts,
627 MVT::ValueType PartVT,
628 MVT::ValueType ValueVT,
629 ISD::NodeType AssertOp = ISD::DELETED_NODE) {
630 if (!MVT::isVector(ValueVT) || NumParts == 1) {
631 SDOperand Val = Parts[0];
633 // If the value was expanded, copy from the top part.
635 assert(NumParts == 2 &&
636 "Cannot expand to more than 2 elts yet!");
637 SDOperand Hi = Parts[1];
638 if (!DAG.getTargetLoweringInfo().isLittleEndian())
640 return DAG.getNode(ISD::BUILD_PAIR, ValueVT, Val, Hi);
643 // Otherwise, if the value was promoted or extended, truncate it to the
645 if (PartVT == ValueVT)
648 if (MVT::isVector(PartVT)) {
649 assert(MVT::isVector(ValueVT) && "Unknown vector conversion!");
650 return DAG.getNode(ISD::BIT_CONVERT, PartVT, Val);
653 if (MVT::isInteger(PartVT) &&
654 MVT::isInteger(ValueVT)) {
655 if (ValueVT < PartVT) {
656 // For a truncate, see if we have any information to
657 // indicate whether the truncated bits will always be
658 // zero or sign-extension.
659 if (AssertOp != ISD::DELETED_NODE)
660 Val = DAG.getNode(AssertOp, PartVT, Val,
661 DAG.getValueType(ValueVT));
662 return DAG.getNode(ISD::TRUNCATE, ValueVT, Val);
664 return DAG.getNode(ISD::ANY_EXTEND, ValueVT, Val);
668 if (MVT::isFloatingPoint(PartVT) &&
669 MVT::isFloatingPoint(ValueVT))
670 return DAG.getNode(ISD::FP_ROUND, ValueVT, Val);
672 if (MVT::getSizeInBits(PartVT) ==
673 MVT::getSizeInBits(ValueVT))
674 return DAG.getNode(ISD::BIT_CONVERT, ValueVT, Val);
676 assert(0 && "Unknown mismatch!");
679 // Handle a multi-element vector.
680 MVT::ValueType IntermediateVT, RegisterVT;
681 unsigned NumIntermediates;
683 DAG.getTargetLoweringInfo()
684 .getVectorTypeBreakdown(ValueVT, IntermediateVT, NumIntermediates,
687 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!");
688 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!");
689 assert(RegisterVT == Parts[0].getValueType() &&
690 "Part type doesn't match part!");
692 // Assemble the parts into intermediate operands.
693 SmallVector<SDOperand, 8> Ops(NumIntermediates);
694 if (NumIntermediates == NumParts) {
695 // If the register was not expanded, truncate or copy the value,
697 for (unsigned i = 0; i != NumParts; ++i)
698 Ops[i] = getCopyFromParts(DAG, &Parts[i], 1,
699 PartVT, IntermediateVT);
700 } else if (NumParts > 0) {
701 // If the intermediate type was expanded, build the intermediate operands
703 assert(NumParts % NumIntermediates == 0 &&
704 "Must expand into a divisible number of parts!");
705 unsigned Factor = NumParts / NumIntermediates;
706 for (unsigned i = 0; i != NumIntermediates; ++i)
707 Ops[i] = getCopyFromParts(DAG, &Parts[i * Factor], Factor,
708 PartVT, IntermediateVT);
711 // Build a vector with BUILD_VECTOR or CONCAT_VECTORS from the intermediate
713 return DAG.getNode(MVT::isVector(IntermediateVT) ?
714 ISD::CONCAT_VECTORS :
716 ValueVT, &Ops[0], NumIntermediates);
719 /// getCopyToParts - Create a series of nodes that contain the
720 /// specified value split into legal parts.
721 static void getCopyToParts(SelectionDAG &DAG,
725 MVT::ValueType PartVT) {
726 TargetLowering &TLI = DAG.getTargetLoweringInfo();
727 MVT::ValueType PtrVT = TLI.getPointerTy();
728 MVT::ValueType ValueVT = Val.getValueType();
730 if (!MVT::isVector(ValueVT) || NumParts == 1) {
731 // If the value was expanded, copy from the parts.
733 for (unsigned i = 0; i != NumParts; ++i)
734 Parts[i] = DAG.getNode(ISD::EXTRACT_ELEMENT, PartVT, Val,
735 DAG.getConstant(i, PtrVT));
736 if (!DAG.getTargetLoweringInfo().isLittleEndian())
737 std::reverse(Parts, Parts + NumParts);
741 // If there is a single part and the types differ, this must be
743 if (PartVT != ValueVT) {
744 if (MVT::isVector(PartVT)) {
745 assert(MVT::isVector(ValueVT) &&
746 "Not a vector-vector cast?");
747 Val = DAG.getNode(ISD::BIT_CONVERT, PartVT, Val);
748 } else if (MVT::isInteger(PartVT) && MVT::isInteger(ValueVT)) {
749 if (PartVT < ValueVT)
750 Val = DAG.getNode(ISD::TRUNCATE, PartVT, Val);
752 Val = DAG.getNode(ISD::ANY_EXTEND, PartVT, Val);
753 } else if (MVT::isFloatingPoint(PartVT) &&
754 MVT::isFloatingPoint(ValueVT)) {
755 Val = DAG.getNode(ISD::FP_EXTEND, PartVT, Val);
756 } else if (MVT::getSizeInBits(PartVT) ==
757 MVT::getSizeInBits(ValueVT)) {
758 Val = DAG.getNode(ISD::BIT_CONVERT, PartVT, Val);
760 assert(0 && "Unknown mismatch!");
767 // Handle a multi-element vector.
768 MVT::ValueType IntermediateVT, RegisterVT;
769 unsigned NumIntermediates;
771 DAG.getTargetLoweringInfo()
772 .getVectorTypeBreakdown(ValueVT, IntermediateVT, NumIntermediates,
774 unsigned NumElements = MVT::getVectorNumElements(ValueVT);
776 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!");
777 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!");
779 // Split the vector into intermediate operands.
780 SmallVector<SDOperand, 8> Ops(NumIntermediates);
781 for (unsigned i = 0; i != NumIntermediates; ++i)
782 if (MVT::isVector(IntermediateVT))
783 Ops[i] = DAG.getNode(ISD::EXTRACT_SUBVECTOR,
785 DAG.getConstant(i * (NumElements / NumIntermediates),
788 Ops[i] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT,
790 DAG.getConstant(i, PtrVT));
792 // Split the intermediate operands into legal parts.
793 if (NumParts == NumIntermediates) {
794 // If the register was not expanded, promote or copy the value,
796 for (unsigned i = 0; i != NumParts; ++i)
797 getCopyToParts(DAG, Ops[i], &Parts[i], 1, PartVT);
798 } else if (NumParts > 0) {
799 // If the intermediate type was expanded, split each the value into
801 assert(NumParts % NumIntermediates == 0 &&
802 "Must expand into a divisible number of parts!");
803 unsigned Factor = NumParts / NumIntermediates;
804 for (unsigned i = 0; i != NumIntermediates; ++i)
805 getCopyToParts(DAG, Ops[i], &Parts[i * Factor], Factor, PartVT);
810 SDOperand SelectionDAGLowering::getValue(const Value *V) {
811 SDOperand &N = NodeMap[V];
814 const Type *VTy = V->getType();
815 MVT::ValueType VT = TLI.getValueType(VTy);
816 if (Constant *C = const_cast<Constant*>(dyn_cast<Constant>(V))) {
817 if (ConstantExpr *CE = dyn_cast<ConstantExpr>(C)) {
818 visit(CE->getOpcode(), *CE);
819 SDOperand N1 = NodeMap[V];
820 assert(N1.Val && "visit didn't populate the ValueMap!");
822 } else if (GlobalValue *GV = dyn_cast<GlobalValue>(C)) {
823 return N = DAG.getGlobalAddress(GV, VT);
824 } else if (isa<ConstantPointerNull>(C)) {
825 return N = DAG.getConstant(0, TLI.getPointerTy());
826 } else if (isa<UndefValue>(C)) {
827 if (!isa<VectorType>(VTy))
828 return N = DAG.getNode(ISD::UNDEF, VT);
830 // Create a BUILD_VECTOR of undef nodes.
831 const VectorType *PTy = cast<VectorType>(VTy);
832 unsigned NumElements = PTy->getNumElements();
833 MVT::ValueType PVT = TLI.getValueType(PTy->getElementType());
835 SmallVector<SDOperand, 8> Ops;
836 Ops.assign(NumElements, DAG.getNode(ISD::UNDEF, PVT));
838 // Create a VConstant node with generic Vector type.
839 MVT::ValueType VT = MVT::getVectorType(PVT, NumElements);
840 return N = DAG.getNode(ISD::BUILD_VECTOR, VT,
841 &Ops[0], Ops.size());
842 } else if (ConstantFP *CFP = dyn_cast<ConstantFP>(C)) {
843 return N = DAG.getConstantFP(CFP->getValue(), VT);
844 } else if (const VectorType *PTy = dyn_cast<VectorType>(VTy)) {
845 unsigned NumElements = PTy->getNumElements();
846 MVT::ValueType PVT = TLI.getValueType(PTy->getElementType());
848 // Now that we know the number and type of the elements, push a
849 // Constant or ConstantFP node onto the ops list for each element of
850 // the vector constant.
851 SmallVector<SDOperand, 8> Ops;
852 if (ConstantVector *CP = dyn_cast<ConstantVector>(C)) {
853 for (unsigned i = 0; i != NumElements; ++i)
854 Ops.push_back(getValue(CP->getOperand(i)));
856 assert(isa<ConstantAggregateZero>(C) && "Unknown vector constant!");
858 if (MVT::isFloatingPoint(PVT))
859 Op = DAG.getConstantFP(0, PVT);
861 Op = DAG.getConstant(0, PVT);
862 Ops.assign(NumElements, Op);
865 // Create a BUILD_VECTOR node.
866 MVT::ValueType VT = MVT::getVectorType(PVT, NumElements);
867 return NodeMap[V] = DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0],
870 // Canonicalize all constant ints to be unsigned.
871 return N = DAG.getConstant(cast<ConstantInt>(C)->getZExtValue(),VT);
875 if (const AllocaInst *AI = dyn_cast<AllocaInst>(V)) {
876 std::map<const AllocaInst*, int>::iterator SI =
877 FuncInfo.StaticAllocaMap.find(AI);
878 if (SI != FuncInfo.StaticAllocaMap.end())
879 return DAG.getFrameIndex(SI->second, TLI.getPointerTy());
882 unsigned InReg = FuncInfo.ValueMap[V];
883 assert(InReg && "Value not in map!");
885 MVT::ValueType RegisterVT = TLI.getRegisterType(VT);
886 unsigned NumRegs = TLI.getNumRegisters(VT);
888 std::vector<unsigned> Regs(NumRegs);
889 for (unsigned i = 0; i != NumRegs; ++i)
892 RegsForValue RFV(Regs, RegisterVT, VT);
893 SDOperand Chain = DAG.getEntryNode();
895 return RFV.getCopyFromRegs(DAG, Chain, NULL);
899 void SelectionDAGLowering::visitRet(ReturnInst &I) {
900 if (I.getNumOperands() == 0) {
901 DAG.setRoot(DAG.getNode(ISD::RET, MVT::Other, getRoot()));
904 SmallVector<SDOperand, 8> NewValues;
905 NewValues.push_back(getRoot());
906 for (unsigned i = 0, e = I.getNumOperands(); i != e; ++i) {
907 SDOperand RetOp = getValue(I.getOperand(i));
909 // If this is an integer return value, we need to promote it ourselves to
910 // the full width of a register, since getCopyToParts and Legalize will use
911 // ANY_EXTEND rather than sign/zero.
912 // FIXME: C calling convention requires the return type to be promoted to
913 // at least 32-bit. But this is not necessary for non-C calling conventions.
914 if (MVT::isInteger(RetOp.getValueType()) &&
915 RetOp.getValueType() < MVT::i64) {
916 MVT::ValueType TmpVT;
917 if (TLI.getTypeAction(MVT::i32) == TargetLowering::Promote)
918 TmpVT = TLI.getTypeToTransformTo(MVT::i32);
921 const FunctionType *FTy = I.getParent()->getParent()->getFunctionType();
922 const ParamAttrsList *Attrs = FTy->getParamAttrs();
923 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
924 if (Attrs && Attrs->paramHasAttr(0, ParamAttr::SExt))
925 ExtendKind = ISD::SIGN_EXTEND;
926 if (Attrs && Attrs->paramHasAttr(0, ParamAttr::ZExt))
927 ExtendKind = ISD::ZERO_EXTEND;
928 RetOp = DAG.getNode(ExtendKind, TmpVT, RetOp);
929 NewValues.push_back(RetOp);
930 NewValues.push_back(DAG.getConstant(false, MVT::i32));
932 MVT::ValueType VT = RetOp.getValueType();
933 unsigned NumParts = TLI.getNumRegisters(VT);
934 MVT::ValueType PartVT = TLI.getRegisterType(VT);
935 SmallVector<SDOperand, 4> Parts(NumParts);
936 getCopyToParts(DAG, RetOp, &Parts[0], NumParts, PartVT);
937 for (unsigned i = 0; i < NumParts; ++i) {
938 NewValues.push_back(Parts[i]);
939 NewValues.push_back(DAG.getConstant(false, MVT::i32));
943 DAG.setRoot(DAG.getNode(ISD::RET, MVT::Other,
944 &NewValues[0], NewValues.size()));
947 /// ExportFromCurrentBlock - If this condition isn't known to be exported from
948 /// the current basic block, add it to ValueMap now so that we'll get a
950 void SelectionDAGLowering::ExportFromCurrentBlock(Value *V) {
951 // No need to export constants.
952 if (!isa<Instruction>(V) && !isa<Argument>(V)) return;
955 if (FuncInfo.isExportedInst(V)) return;
957 unsigned Reg = FuncInfo.InitializeRegForValue(V);
958 PendingLoads.push_back(CopyValueToVirtualRegister(V, Reg));
961 bool SelectionDAGLowering::isExportableFromCurrentBlock(Value *V,
962 const BasicBlock *FromBB) {
963 // The operands of the setcc have to be in this block. We don't know
964 // how to export them from some other block.
965 if (Instruction *VI = dyn_cast<Instruction>(V)) {
966 // Can export from current BB.
967 if (VI->getParent() == FromBB)
970 // Is already exported, noop.
971 return FuncInfo.isExportedInst(V);
974 // If this is an argument, we can export it if the BB is the entry block or
975 // if it is already exported.
976 if (isa<Argument>(V)) {
977 if (FromBB == &FromBB->getParent()->getEntryBlock())
980 // Otherwise, can only export this if it is already exported.
981 return FuncInfo.isExportedInst(V);
984 // Otherwise, constants can always be exported.
988 static bool InBlock(const Value *V, const BasicBlock *BB) {
989 if (const Instruction *I = dyn_cast<Instruction>(V))
990 return I->getParent() == BB;
994 /// FindMergedConditions - If Cond is an expression like
995 void SelectionDAGLowering::FindMergedConditions(Value *Cond,
996 MachineBasicBlock *TBB,
997 MachineBasicBlock *FBB,
998 MachineBasicBlock *CurBB,
1000 // If this node is not part of the or/and tree, emit it as a branch.
1001 Instruction *BOp = dyn_cast<Instruction>(Cond);
1003 if (!BOp || !(isa<BinaryOperator>(BOp) || isa<CmpInst>(BOp)) ||
1004 (unsigned)BOp->getOpcode() != Opc || !BOp->hasOneUse() ||
1005 BOp->getParent() != CurBB->getBasicBlock() ||
1006 !InBlock(BOp->getOperand(0), CurBB->getBasicBlock()) ||
1007 !InBlock(BOp->getOperand(1), CurBB->getBasicBlock())) {
1008 const BasicBlock *BB = CurBB->getBasicBlock();
1010 // If the leaf of the tree is a comparison, merge the condition into
1012 if ((isa<ICmpInst>(Cond) || isa<FCmpInst>(Cond)) &&
1013 // The operands of the cmp have to be in this block. We don't know
1014 // how to export them from some other block. If this is the first block
1015 // of the sequence, no exporting is needed.
1017 (isExportableFromCurrentBlock(BOp->getOperand(0), BB) &&
1018 isExportableFromCurrentBlock(BOp->getOperand(1), BB)))) {
1019 BOp = cast<Instruction>(Cond);
1020 ISD::CondCode Condition;
1021 if (ICmpInst *IC = dyn_cast<ICmpInst>(Cond)) {
1022 switch (IC->getPredicate()) {
1023 default: assert(0 && "Unknown icmp predicate opcode!");
1024 case ICmpInst::ICMP_EQ: Condition = ISD::SETEQ; break;
1025 case ICmpInst::ICMP_NE: Condition = ISD::SETNE; break;
1026 case ICmpInst::ICMP_SLE: Condition = ISD::SETLE; break;
1027 case ICmpInst::ICMP_ULE: Condition = ISD::SETULE; break;
1028 case ICmpInst::ICMP_SGE: Condition = ISD::SETGE; break;
1029 case ICmpInst::ICMP_UGE: Condition = ISD::SETUGE; break;
1030 case ICmpInst::ICMP_SLT: Condition = ISD::SETLT; break;
1031 case ICmpInst::ICMP_ULT: Condition = ISD::SETULT; break;
1032 case ICmpInst::ICMP_SGT: Condition = ISD::SETGT; break;
1033 case ICmpInst::ICMP_UGT: Condition = ISD::SETUGT; break;
1035 } else if (FCmpInst *FC = dyn_cast<FCmpInst>(Cond)) {
1036 ISD::CondCode FPC, FOC;
1037 switch (FC->getPredicate()) {
1038 default: assert(0 && "Unknown fcmp predicate opcode!");
1039 case FCmpInst::FCMP_FALSE: FOC = FPC = ISD::SETFALSE; break;
1040 case FCmpInst::FCMP_OEQ: FOC = ISD::SETEQ; FPC = ISD::SETOEQ; break;
1041 case FCmpInst::FCMP_OGT: FOC = ISD::SETGT; FPC = ISD::SETOGT; break;
1042 case FCmpInst::FCMP_OGE: FOC = ISD::SETGE; FPC = ISD::SETOGE; break;
1043 case FCmpInst::FCMP_OLT: FOC = ISD::SETLT; FPC = ISD::SETOLT; break;
1044 case FCmpInst::FCMP_OLE: FOC = ISD::SETLE; FPC = ISD::SETOLE; break;
1045 case FCmpInst::FCMP_ONE: FOC = ISD::SETNE; FPC = ISD::SETONE; break;
1046 case FCmpInst::FCMP_ORD: FOC = ISD::SETEQ; FPC = ISD::SETO; break;
1047 case FCmpInst::FCMP_UNO: FOC = ISD::SETNE; FPC = ISD::SETUO; break;
1048 case FCmpInst::FCMP_UEQ: FOC = ISD::SETEQ; FPC = ISD::SETUEQ; break;
1049 case FCmpInst::FCMP_UGT: FOC = ISD::SETGT; FPC = ISD::SETUGT; break;
1050 case FCmpInst::FCMP_UGE: FOC = ISD::SETGE; FPC = ISD::SETUGE; break;
1051 case FCmpInst::FCMP_ULT: FOC = ISD::SETLT; FPC = ISD::SETULT; break;
1052 case FCmpInst::FCMP_ULE: FOC = ISD::SETLE; FPC = ISD::SETULE; break;
1053 case FCmpInst::FCMP_UNE: FOC = ISD::SETNE; FPC = ISD::SETUNE; break;
1054 case FCmpInst::FCMP_TRUE: FOC = FPC = ISD::SETTRUE; break;
1056 if (FiniteOnlyFPMath())
1061 Condition = ISD::SETEQ; // silence warning.
1062 assert(0 && "Unknown compare instruction");
1065 SelectionDAGISel::CaseBlock CB(Condition, BOp->getOperand(0),
1066 BOp->getOperand(1), NULL, TBB, FBB, CurBB);
1067 SwitchCases.push_back(CB);
1071 // Create a CaseBlock record representing this branch.
1072 SelectionDAGISel::CaseBlock CB(ISD::SETEQ, Cond, ConstantInt::getTrue(),
1073 NULL, TBB, FBB, CurBB);
1074 SwitchCases.push_back(CB);
1079 // Create TmpBB after CurBB.
1080 MachineFunction::iterator BBI = CurBB;
1081 MachineBasicBlock *TmpBB = new MachineBasicBlock(CurBB->getBasicBlock());
1082 CurBB->getParent()->getBasicBlockList().insert(++BBI, TmpBB);
1084 if (Opc == Instruction::Or) {
1085 // Codegen X | Y as:
1093 // Emit the LHS condition.
1094 FindMergedConditions(BOp->getOperand(0), TBB, TmpBB, CurBB, Opc);
1096 // Emit the RHS condition into TmpBB.
1097 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, Opc);
1099 assert(Opc == Instruction::And && "Unknown merge op!");
1100 // Codegen X & Y as:
1107 // This requires creation of TmpBB after CurBB.
1109 // Emit the LHS condition.
1110 FindMergedConditions(BOp->getOperand(0), TmpBB, FBB, CurBB, Opc);
1112 // Emit the RHS condition into TmpBB.
1113 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, Opc);
1117 /// If the set of cases should be emitted as a series of branches, return true.
1118 /// If we should emit this as a bunch of and/or'd together conditions, return
1121 ShouldEmitAsBranches(const std::vector<SelectionDAGISel::CaseBlock> &Cases) {
1122 if (Cases.size() != 2) return true;
1124 // If this is two comparisons of the same values or'd or and'd together, they
1125 // will get folded into a single comparison, so don't emit two blocks.
1126 if ((Cases[0].CmpLHS == Cases[1].CmpLHS &&
1127 Cases[0].CmpRHS == Cases[1].CmpRHS) ||
1128 (Cases[0].CmpRHS == Cases[1].CmpLHS &&
1129 Cases[0].CmpLHS == Cases[1].CmpRHS)) {
1136 void SelectionDAGLowering::visitBr(BranchInst &I) {
1137 // Update machine-CFG edges.
1138 MachineBasicBlock *Succ0MBB = FuncInfo.MBBMap[I.getSuccessor(0)];
1140 // Figure out which block is immediately after the current one.
1141 MachineBasicBlock *NextBlock = 0;
1142 MachineFunction::iterator BBI = CurMBB;
1143 if (++BBI != CurMBB->getParent()->end())
1146 if (I.isUnconditional()) {
1147 // If this is not a fall-through branch, emit the branch.
1148 if (Succ0MBB != NextBlock)
1149 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, getRoot(),
1150 DAG.getBasicBlock(Succ0MBB)));
1152 // Update machine-CFG edges.
1153 CurMBB->addSuccessor(Succ0MBB);
1158 // If this condition is one of the special cases we handle, do special stuff
1160 Value *CondVal = I.getCondition();
1161 MachineBasicBlock *Succ1MBB = FuncInfo.MBBMap[I.getSuccessor(1)];
1163 // If this is a series of conditions that are or'd or and'd together, emit
1164 // this as a sequence of branches instead of setcc's with and/or operations.
1165 // For example, instead of something like:
1178 if (BinaryOperator *BOp = dyn_cast<BinaryOperator>(CondVal)) {
1179 if (BOp->hasOneUse() &&
1180 (BOp->getOpcode() == Instruction::And ||
1181 BOp->getOpcode() == Instruction::Or)) {
1182 FindMergedConditions(BOp, Succ0MBB, Succ1MBB, CurMBB, BOp->getOpcode());
1183 // If the compares in later blocks need to use values not currently
1184 // exported from this block, export them now. This block should always
1185 // be the first entry.
1186 assert(SwitchCases[0].ThisBB == CurMBB && "Unexpected lowering!");
1188 // Allow some cases to be rejected.
1189 if (ShouldEmitAsBranches(SwitchCases)) {
1190 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i) {
1191 ExportFromCurrentBlock(SwitchCases[i].CmpLHS);
1192 ExportFromCurrentBlock(SwitchCases[i].CmpRHS);
1195 // Emit the branch for this block.
1196 visitSwitchCase(SwitchCases[0]);
1197 SwitchCases.erase(SwitchCases.begin());
1201 // Okay, we decided not to do this, remove any inserted MBB's and clear
1203 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i)
1204 CurMBB->getParent()->getBasicBlockList().erase(SwitchCases[i].ThisBB);
1206 SwitchCases.clear();
1210 // Create a CaseBlock record representing this branch.
1211 SelectionDAGISel::CaseBlock CB(ISD::SETEQ, CondVal, ConstantInt::getTrue(),
1212 NULL, Succ0MBB, Succ1MBB, CurMBB);
1213 // Use visitSwitchCase to actually insert the fast branch sequence for this
1215 visitSwitchCase(CB);
1218 /// visitSwitchCase - Emits the necessary code to represent a single node in
1219 /// the binary search tree resulting from lowering a switch instruction.
1220 void SelectionDAGLowering::visitSwitchCase(SelectionDAGISel::CaseBlock &CB) {
1222 SDOperand CondLHS = getValue(CB.CmpLHS);
1224 // Build the setcc now.
1225 if (CB.CmpMHS == NULL) {
1226 // Fold "(X == true)" to X and "(X == false)" to !X to
1227 // handle common cases produced by branch lowering.
1228 if (CB.CmpRHS == ConstantInt::getTrue() && CB.CC == ISD::SETEQ)
1230 else if (CB.CmpRHS == ConstantInt::getFalse() && CB.CC == ISD::SETEQ) {
1231 SDOperand True = DAG.getConstant(1, CondLHS.getValueType());
1232 Cond = DAG.getNode(ISD::XOR, CondLHS.getValueType(), CondLHS, True);
1234 Cond = DAG.getSetCC(MVT::i1, CondLHS, getValue(CB.CmpRHS), CB.CC);
1236 assert(CB.CC == ISD::SETLE && "Can handle only LE ranges now");
1238 uint64_t Low = cast<ConstantInt>(CB.CmpLHS)->getSExtValue();
1239 uint64_t High = cast<ConstantInt>(CB.CmpRHS)->getSExtValue();
1241 SDOperand CmpOp = getValue(CB.CmpMHS);
1242 MVT::ValueType VT = CmpOp.getValueType();
1244 if (cast<ConstantInt>(CB.CmpLHS)->isMinValue(true)) {
1245 Cond = DAG.getSetCC(MVT::i1, CmpOp, DAG.getConstant(High, VT), ISD::SETLE);
1247 SDOperand SUB = DAG.getNode(ISD::SUB, VT, CmpOp, DAG.getConstant(Low, VT));
1248 Cond = DAG.getSetCC(MVT::i1, SUB,
1249 DAG.getConstant(High-Low, VT), ISD::SETULE);
1254 // Set NextBlock to be the MBB immediately after the current one, if any.
1255 // This is used to avoid emitting unnecessary branches to the next block.
1256 MachineBasicBlock *NextBlock = 0;
1257 MachineFunction::iterator BBI = CurMBB;
1258 if (++BBI != CurMBB->getParent()->end())
1261 // If the lhs block is the next block, invert the condition so that we can
1262 // fall through to the lhs instead of the rhs block.
1263 if (CB.TrueBB == NextBlock) {
1264 std::swap(CB.TrueBB, CB.FalseBB);
1265 SDOperand True = DAG.getConstant(1, Cond.getValueType());
1266 Cond = DAG.getNode(ISD::XOR, Cond.getValueType(), Cond, True);
1268 SDOperand BrCond = DAG.getNode(ISD::BRCOND, MVT::Other, getRoot(), Cond,
1269 DAG.getBasicBlock(CB.TrueBB));
1270 if (CB.FalseBB == NextBlock)
1271 DAG.setRoot(BrCond);
1273 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, BrCond,
1274 DAG.getBasicBlock(CB.FalseBB)));
1275 // Update successor info
1276 CurMBB->addSuccessor(CB.TrueBB);
1277 CurMBB->addSuccessor(CB.FalseBB);
1280 /// visitJumpTable - Emit JumpTable node in the current MBB
1281 void SelectionDAGLowering::visitJumpTable(SelectionDAGISel::JumpTable &JT) {
1282 // Emit the code for the jump table
1283 assert(JT.Reg != -1U && "Should lower JT Header first!");
1284 MVT::ValueType PTy = TLI.getPointerTy();
1285 SDOperand Index = DAG.getCopyFromReg(getRoot(), JT.Reg, PTy);
1286 SDOperand Table = DAG.getJumpTable(JT.JTI, PTy);
1287 DAG.setRoot(DAG.getNode(ISD::BR_JT, MVT::Other, Index.getValue(1),
1292 /// visitJumpTableHeader - This function emits necessary code to produce index
1293 /// in the JumpTable from switch case.
1294 void SelectionDAGLowering::visitJumpTableHeader(SelectionDAGISel::JumpTable &JT,
1295 SelectionDAGISel::JumpTableHeader &JTH) {
1296 // Subtract the lowest switch case value from the value being switched on
1297 // and conditional branch to default mbb if the result is greater than the
1298 // difference between smallest and largest cases.
1299 SDOperand SwitchOp = getValue(JTH.SValue);
1300 MVT::ValueType VT = SwitchOp.getValueType();
1301 SDOperand SUB = DAG.getNode(ISD::SUB, VT, SwitchOp,
1302 DAG.getConstant(JTH.First, VT));
1304 // The SDNode we just created, which holds the value being switched on
1305 // minus the the smallest case value, needs to be copied to a virtual
1306 // register so it can be used as an index into the jump table in a
1307 // subsequent basic block. This value may be smaller or larger than the
1308 // target's pointer type, and therefore require extension or truncating.
1309 if (MVT::getSizeInBits(VT) > MVT::getSizeInBits(TLI.getPointerTy()))
1310 SwitchOp = DAG.getNode(ISD::TRUNCATE, TLI.getPointerTy(), SUB);
1312 SwitchOp = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(), SUB);
1314 unsigned JumpTableReg = FuncInfo.MakeReg(TLI.getPointerTy());
1315 SDOperand CopyTo = DAG.getCopyToReg(getRoot(), JumpTableReg, SwitchOp);
1316 JT.Reg = JumpTableReg;
1318 // Emit the range check for the jump table, and branch to the default
1319 // block for the switch statement if the value being switched on exceeds
1320 // the largest case in the switch.
1321 SDOperand CMP = DAG.getSetCC(TLI.getSetCCResultTy(), SUB,
1322 DAG.getConstant(JTH.Last-JTH.First,VT),
1325 // Set NextBlock to be the MBB immediately after the current one, if any.
1326 // This is used to avoid emitting unnecessary branches to the next block.
1327 MachineBasicBlock *NextBlock = 0;
1328 MachineFunction::iterator BBI = CurMBB;
1329 if (++BBI != CurMBB->getParent()->end())
1332 SDOperand BrCond = DAG.getNode(ISD::BRCOND, MVT::Other, CopyTo, CMP,
1333 DAG.getBasicBlock(JT.Default));
1335 if (JT.MBB == NextBlock)
1336 DAG.setRoot(BrCond);
1338 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, BrCond,
1339 DAG.getBasicBlock(JT.MBB)));
1344 /// visitBitTestHeader - This function emits necessary code to produce value
1345 /// suitable for "bit tests"
1346 void SelectionDAGLowering::visitBitTestHeader(SelectionDAGISel::BitTestBlock &B) {
1347 // Subtract the minimum value
1348 SDOperand SwitchOp = getValue(B.SValue);
1349 MVT::ValueType VT = SwitchOp.getValueType();
1350 SDOperand SUB = DAG.getNode(ISD::SUB, VT, SwitchOp,
1351 DAG.getConstant(B.First, VT));
1354 SDOperand RangeCmp = DAG.getSetCC(TLI.getSetCCResultTy(), SUB,
1355 DAG.getConstant(B.Range, VT),
1359 if (MVT::getSizeInBits(VT) > MVT::getSizeInBits(TLI.getShiftAmountTy()))
1360 ShiftOp = DAG.getNode(ISD::TRUNCATE, TLI.getShiftAmountTy(), SUB);
1362 ShiftOp = DAG.getNode(ISD::ZERO_EXTEND, TLI.getShiftAmountTy(), SUB);
1364 // Make desired shift
1365 SDOperand SwitchVal = DAG.getNode(ISD::SHL, TLI.getPointerTy(),
1366 DAG.getConstant(1, TLI.getPointerTy()),
1369 unsigned SwitchReg = FuncInfo.MakeReg(TLI.getPointerTy());
1370 SDOperand CopyTo = DAG.getCopyToReg(getRoot(), SwitchReg, SwitchVal);
1373 SDOperand BrRange = DAG.getNode(ISD::BRCOND, MVT::Other, CopyTo, RangeCmp,
1374 DAG.getBasicBlock(B.Default));
1376 // Set NextBlock to be the MBB immediately after the current one, if any.
1377 // This is used to avoid emitting unnecessary branches to the next block.
1378 MachineBasicBlock *NextBlock = 0;
1379 MachineFunction::iterator BBI = CurMBB;
1380 if (++BBI != CurMBB->getParent()->end())
1383 MachineBasicBlock* MBB = B.Cases[0].ThisBB;
1384 if (MBB == NextBlock)
1385 DAG.setRoot(BrRange);
1387 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, CopyTo,
1388 DAG.getBasicBlock(MBB)));
1390 CurMBB->addSuccessor(B.Default);
1391 CurMBB->addSuccessor(MBB);
1396 /// visitBitTestCase - this function produces one "bit test"
1397 void SelectionDAGLowering::visitBitTestCase(MachineBasicBlock* NextMBB,
1399 SelectionDAGISel::BitTestCase &B) {
1400 // Emit bit tests and jumps
1401 SDOperand SwitchVal = DAG.getCopyFromReg(getRoot(), Reg, TLI.getPointerTy());
1403 SDOperand AndOp = DAG.getNode(ISD::AND, TLI.getPointerTy(),
1405 DAG.getConstant(B.Mask,
1406 TLI.getPointerTy()));
1407 SDOperand AndCmp = DAG.getSetCC(TLI.getSetCCResultTy(), AndOp,
1408 DAG.getConstant(0, TLI.getPointerTy()),
1410 SDOperand BrAnd = DAG.getNode(ISD::BRCOND, MVT::Other, getRoot(),
1411 AndCmp, DAG.getBasicBlock(B.TargetBB));
1413 // Set NextBlock to be the MBB immediately after the current one, if any.
1414 // This is used to avoid emitting unnecessary branches to the next block.
1415 MachineBasicBlock *NextBlock = 0;
1416 MachineFunction::iterator BBI = CurMBB;
1417 if (++BBI != CurMBB->getParent()->end())
1420 if (NextMBB == NextBlock)
1423 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, BrAnd,
1424 DAG.getBasicBlock(NextMBB)));
1426 CurMBB->addSuccessor(B.TargetBB);
1427 CurMBB->addSuccessor(NextMBB);
1432 void SelectionDAGLowering::visitInvoke(InvokeInst &I) {
1433 // Retrieve successors.
1434 MachineBasicBlock *Return = FuncInfo.MBBMap[I.getSuccessor(0)];
1435 MachineBasicBlock *LandingPad = FuncInfo.MBBMap[I.getSuccessor(1)];
1437 LowerCallTo(I, I.getCalledValue()->getType(),
1440 getValue(I.getOperand(0)),
1443 // If the value of the invoke is used outside of its defining block, make it
1444 // available as a virtual register.
1445 if (!I.use_empty()) {
1446 DenseMap<const Value*, unsigned>::iterator VMI = FuncInfo.ValueMap.find(&I);
1447 if (VMI != FuncInfo.ValueMap.end())
1448 DAG.setRoot(CopyValueToVirtualRegister(&I, VMI->second));
1451 // Drop into normal successor.
1452 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, getRoot(),
1453 DAG.getBasicBlock(Return)));
1455 // Update successor info
1456 CurMBB->addSuccessor(Return);
1457 CurMBB->addSuccessor(LandingPad);
1460 void SelectionDAGLowering::visitUnwind(UnwindInst &I) {
1463 /// handleSmallSwitchCaseRange - Emit a series of specific tests (suitable for
1464 /// small case ranges).
1465 bool SelectionDAGLowering::handleSmallSwitchRange(CaseRec& CR,
1466 CaseRecVector& WorkList,
1468 MachineBasicBlock* Default) {
1469 Case& BackCase = *(CR.Range.second-1);
1471 // Size is the number of Cases represented by this range.
1472 unsigned Size = CR.Range.second - CR.Range.first;
1476 // Get the MachineFunction which holds the current MBB. This is used when
1477 // inserting any additional MBBs necessary to represent the switch.
1478 MachineFunction *CurMF = CurMBB->getParent();
1480 // Figure out which block is immediately after the current one.
1481 MachineBasicBlock *NextBlock = 0;
1482 MachineFunction::iterator BBI = CR.CaseBB;
1484 if (++BBI != CurMBB->getParent()->end())
1487 // TODO: If any two of the cases has the same destination, and if one value
1488 // is the same as the other, but has one bit unset that the other has set,
1489 // use bit manipulation to do two compares at once. For example:
1490 // "if (X == 6 || X == 4)" -> "if ((X|2) == 6)"
1492 // Rearrange the case blocks so that the last one falls through if possible.
1493 if (NextBlock && Default != NextBlock && BackCase.BB != NextBlock) {
1494 // The last case block won't fall through into 'NextBlock' if we emit the
1495 // branches in this order. See if rearranging a case value would help.
1496 for (CaseItr I = CR.Range.first, E = CR.Range.second-1; I != E; ++I) {
1497 if (I->BB == NextBlock) {
1498 std::swap(*I, BackCase);
1504 // Create a CaseBlock record representing a conditional branch to
1505 // the Case's target mbb if the value being switched on SV is equal
1507 MachineBasicBlock *CurBlock = CR.CaseBB;
1508 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++I) {
1509 MachineBasicBlock *FallThrough;
1511 FallThrough = new MachineBasicBlock(CurBlock->getBasicBlock());
1512 CurMF->getBasicBlockList().insert(BBI, FallThrough);
1514 // If the last case doesn't match, go to the default block.
1515 FallThrough = Default;
1518 Value *RHS, *LHS, *MHS;
1520 if (I->High == I->Low) {
1521 // This is just small small case range :) containing exactly 1 case
1523 LHS = SV; RHS = I->High; MHS = NULL;
1526 LHS = I->Low; MHS = SV; RHS = I->High;
1528 SelectionDAGISel::CaseBlock CB(CC, LHS, RHS, MHS,
1529 I->BB, FallThrough, CurBlock);
1531 // If emitting the first comparison, just call visitSwitchCase to emit the
1532 // code into the current block. Otherwise, push the CaseBlock onto the
1533 // vector to be later processed by SDISel, and insert the node's MBB
1534 // before the next MBB.
1535 if (CurBlock == CurMBB)
1536 visitSwitchCase(CB);
1538 SwitchCases.push_back(CB);
1540 CurBlock = FallThrough;
1546 static inline bool areJTsAllowed(const TargetLowering &TLI) {
1547 return (TLI.isOperationLegal(ISD::BR_JT, MVT::Other) ||
1548 TLI.isOperationLegal(ISD::BRIND, MVT::Other));
1551 /// handleJTSwitchCase - Emit jumptable for current switch case range
1552 bool SelectionDAGLowering::handleJTSwitchCase(CaseRec& CR,
1553 CaseRecVector& WorkList,
1555 MachineBasicBlock* Default) {
1556 Case& FrontCase = *CR.Range.first;
1557 Case& BackCase = *(CR.Range.second-1);
1559 int64_t First = cast<ConstantInt>(FrontCase.Low)->getSExtValue();
1560 int64_t Last = cast<ConstantInt>(BackCase.High)->getSExtValue();
1563 for (CaseItr I = CR.Range.first, E = CR.Range.second;
1567 if (!areJTsAllowed(TLI) || TSize <= 3)
1570 double Density = (double)TSize / (double)((Last - First) + 1ULL);
1574 DOUT << "Lowering jump table\n"
1575 << "First entry: " << First << ". Last entry: " << Last << "\n"
1576 << "Size: " << TSize << ". Density: " << Density << "\n\n";
1578 // Get the MachineFunction which holds the current MBB. This is used when
1579 // inserting any additional MBBs necessary to represent the switch.
1580 MachineFunction *CurMF = CurMBB->getParent();
1582 // Figure out which block is immediately after the current one.
1583 MachineBasicBlock *NextBlock = 0;
1584 MachineFunction::iterator BBI = CR.CaseBB;
1586 if (++BBI != CurMBB->getParent()->end())
1589 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
1591 // Create a new basic block to hold the code for loading the address
1592 // of the jump table, and jumping to it. Update successor information;
1593 // we will either branch to the default case for the switch, or the jump
1595 MachineBasicBlock *JumpTableBB = new MachineBasicBlock(LLVMBB);
1596 CurMF->getBasicBlockList().insert(BBI, JumpTableBB);
1597 CR.CaseBB->addSuccessor(Default);
1598 CR.CaseBB->addSuccessor(JumpTableBB);
1600 // Build a vector of destination BBs, corresponding to each target
1601 // of the jump table. If the value of the jump table slot corresponds to
1602 // a case statement, push the case's BB onto the vector, otherwise, push
1604 std::vector<MachineBasicBlock*> DestBBs;
1605 int64_t TEI = First;
1606 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++TEI) {
1607 int64_t Low = cast<ConstantInt>(I->Low)->getSExtValue();
1608 int64_t High = cast<ConstantInt>(I->High)->getSExtValue();
1610 if ((Low <= TEI) && (TEI <= High)) {
1611 DestBBs.push_back(I->BB);
1615 DestBBs.push_back(Default);
1619 // Update successor info. Add one edge to each unique successor.
1620 BitVector SuccsHandled(CR.CaseBB->getParent()->getNumBlockIDs());
1621 for (std::vector<MachineBasicBlock*>::iterator I = DestBBs.begin(),
1622 E = DestBBs.end(); I != E; ++I) {
1623 if (!SuccsHandled[(*I)->getNumber()]) {
1624 SuccsHandled[(*I)->getNumber()] = true;
1625 JumpTableBB->addSuccessor(*I);
1629 // Create a jump table index for this jump table, or return an existing
1631 unsigned JTI = CurMF->getJumpTableInfo()->getJumpTableIndex(DestBBs);
1633 // Set the jump table information so that we can codegen it as a second
1634 // MachineBasicBlock
1635 SelectionDAGISel::JumpTable JT(-1U, JTI, JumpTableBB, Default);
1636 SelectionDAGISel::JumpTableHeader JTH(First, Last, SV, CR.CaseBB,
1637 (CR.CaseBB == CurMBB));
1638 if (CR.CaseBB == CurMBB)
1639 visitJumpTableHeader(JT, JTH);
1641 JTCases.push_back(SelectionDAGISel::JumpTableBlock(JTH, JT));
1646 /// handleBTSplitSwitchCase - emit comparison and split binary search tree into
1648 bool SelectionDAGLowering::handleBTSplitSwitchCase(CaseRec& CR,
1649 CaseRecVector& WorkList,
1651 MachineBasicBlock* Default) {
1652 // Get the MachineFunction which holds the current MBB. This is used when
1653 // inserting any additional MBBs necessary to represent the switch.
1654 MachineFunction *CurMF = CurMBB->getParent();
1656 // Figure out which block is immediately after the current one.
1657 MachineBasicBlock *NextBlock = 0;
1658 MachineFunction::iterator BBI = CR.CaseBB;
1660 if (++BBI != CurMBB->getParent()->end())
1663 Case& FrontCase = *CR.Range.first;
1664 Case& BackCase = *(CR.Range.second-1);
1665 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
1667 // Size is the number of Cases represented by this range.
1668 unsigned Size = CR.Range.second - CR.Range.first;
1670 int64_t First = cast<ConstantInt>(FrontCase.Low)->getSExtValue();
1671 int64_t Last = cast<ConstantInt>(BackCase.High)->getSExtValue();
1673 CaseItr Pivot = CR.Range.first + Size/2;
1675 // Select optimal pivot, maximizing sum density of LHS and RHS. This will
1676 // (heuristically) allow us to emit JumpTable's later.
1678 for (CaseItr I = CR.Range.first, E = CR.Range.second;
1682 uint64_t LSize = FrontCase.size();
1683 uint64_t RSize = TSize-LSize;
1684 DOUT << "Selecting best pivot: \n"
1685 << "First: " << First << ", Last: " << Last <<"\n"
1686 << "LSize: " << LSize << ", RSize: " << RSize << "\n";
1687 for (CaseItr I = CR.Range.first, J=I+1, E = CR.Range.second;
1689 int64_t LEnd = cast<ConstantInt>(I->High)->getSExtValue();
1690 int64_t RBegin = cast<ConstantInt>(J->Low)->getSExtValue();
1691 assert((RBegin-LEnd>=1) && "Invalid case distance");
1692 double LDensity = (double)LSize / (double)((LEnd - First) + 1ULL);
1693 double RDensity = (double)RSize / (double)((Last - RBegin) + 1ULL);
1694 double Metric = Log2_64(RBegin-LEnd)*(LDensity+RDensity);
1695 // Should always split in some non-trivial place
1697 << "LEnd: " << LEnd << ", RBegin: " << RBegin << "\n"
1698 << "LDensity: " << LDensity << ", RDensity: " << RDensity << "\n"
1699 << "Metric: " << Metric << "\n";
1700 if (FMetric < Metric) {
1703 DOUT << "Current metric set to: " << FMetric << "\n";
1709 if (areJTsAllowed(TLI)) {
1710 // If our case is dense we *really* should handle it earlier!
1711 assert((FMetric > 0) && "Should handle dense range earlier!");
1713 Pivot = CR.Range.first + Size/2;
1716 CaseRange LHSR(CR.Range.first, Pivot);
1717 CaseRange RHSR(Pivot, CR.Range.second);
1718 Constant *C = Pivot->Low;
1719 MachineBasicBlock *FalseBB = 0, *TrueBB = 0;
1721 // We know that we branch to the LHS if the Value being switched on is
1722 // less than the Pivot value, C. We use this to optimize our binary
1723 // tree a bit, by recognizing that if SV is greater than or equal to the
1724 // LHS's Case Value, and that Case Value is exactly one less than the
1725 // Pivot's Value, then we can branch directly to the LHS's Target,
1726 // rather than creating a leaf node for it.
1727 if ((LHSR.second - LHSR.first) == 1 &&
1728 LHSR.first->High == CR.GE &&
1729 cast<ConstantInt>(C)->getSExtValue() ==
1730 (cast<ConstantInt>(CR.GE)->getSExtValue() + 1LL)) {
1731 TrueBB = LHSR.first->BB;
1733 TrueBB = new MachineBasicBlock(LLVMBB);
1734 CurMF->getBasicBlockList().insert(BBI, TrueBB);
1735 WorkList.push_back(CaseRec(TrueBB, C, CR.GE, LHSR));
1738 // Similar to the optimization above, if the Value being switched on is
1739 // known to be less than the Constant CR.LT, and the current Case Value
1740 // is CR.LT - 1, then we can branch directly to the target block for
1741 // the current Case Value, rather than emitting a RHS leaf node for it.
1742 if ((RHSR.second - RHSR.first) == 1 && CR.LT &&
1743 cast<ConstantInt>(RHSR.first->Low)->getSExtValue() ==
1744 (cast<ConstantInt>(CR.LT)->getSExtValue() - 1LL)) {
1745 FalseBB = RHSR.first->BB;
1747 FalseBB = new MachineBasicBlock(LLVMBB);
1748 CurMF->getBasicBlockList().insert(BBI, FalseBB);
1749 WorkList.push_back(CaseRec(FalseBB,CR.LT,C,RHSR));
1752 // Create a CaseBlock record representing a conditional branch to
1753 // the LHS node if the value being switched on SV is less than C.
1754 // Otherwise, branch to LHS.
1755 SelectionDAGISel::CaseBlock CB(ISD::SETLT, SV, C, NULL,
1756 TrueBB, FalseBB, CR.CaseBB);
1758 if (CR.CaseBB == CurMBB)
1759 visitSwitchCase(CB);
1761 SwitchCases.push_back(CB);
1766 /// handleBitTestsSwitchCase - if current case range has few destination and
1767 /// range span less, than machine word bitwidth, encode case range into series
1768 /// of masks and emit bit tests with these masks.
1769 bool SelectionDAGLowering::handleBitTestsSwitchCase(CaseRec& CR,
1770 CaseRecVector& WorkList,
1772 MachineBasicBlock* Default){
1773 unsigned IntPtrBits = MVT::getSizeInBits(TLI.getPointerTy());
1775 Case& FrontCase = *CR.Range.first;
1776 Case& BackCase = *(CR.Range.second-1);
1778 // Get the MachineFunction which holds the current MBB. This is used when
1779 // inserting any additional MBBs necessary to represent the switch.
1780 MachineFunction *CurMF = CurMBB->getParent();
1782 unsigned numCmps = 0;
1783 for (CaseItr I = CR.Range.first, E = CR.Range.second;
1785 // Single case counts one, case range - two.
1786 if (I->Low == I->High)
1792 // Count unique destinations
1793 SmallSet<MachineBasicBlock*, 4> Dests;
1794 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) {
1795 Dests.insert(I->BB);
1796 if (Dests.size() > 3)
1797 // Don't bother the code below, if there are too much unique destinations
1800 DOUT << "Total number of unique destinations: " << Dests.size() << "\n"
1801 << "Total number of comparisons: " << numCmps << "\n";
1803 // Compute span of values.
1804 Constant* minValue = FrontCase.Low;
1805 Constant* maxValue = BackCase.High;
1806 uint64_t range = cast<ConstantInt>(maxValue)->getSExtValue() -
1807 cast<ConstantInt>(minValue)->getSExtValue();
1808 DOUT << "Compare range: " << range << "\n"
1809 << "Low bound: " << cast<ConstantInt>(minValue)->getSExtValue() << "\n"
1810 << "High bound: " << cast<ConstantInt>(maxValue)->getSExtValue() << "\n";
1812 if (range>=IntPtrBits ||
1813 (!(Dests.size() == 1 && numCmps >= 3) &&
1814 !(Dests.size() == 2 && numCmps >= 5) &&
1815 !(Dests.size() >= 3 && numCmps >= 6)))
1818 DOUT << "Emitting bit tests\n";
1819 int64_t lowBound = 0;
1821 // Optimize the case where all the case values fit in a
1822 // word without having to subtract minValue. In this case,
1823 // we can optimize away the subtraction.
1824 if (cast<ConstantInt>(minValue)->getSExtValue() >= 0 &&
1825 cast<ConstantInt>(maxValue)->getSExtValue() < IntPtrBits) {
1826 range = cast<ConstantInt>(maxValue)->getSExtValue();
1828 lowBound = cast<ConstantInt>(minValue)->getSExtValue();
1831 CaseBitsVector CasesBits;
1832 unsigned i, count = 0;
1834 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) {
1835 MachineBasicBlock* Dest = I->BB;
1836 for (i = 0; i < count; ++i)
1837 if (Dest == CasesBits[i].BB)
1841 assert((count < 3) && "Too much destinations to test!");
1842 CasesBits.push_back(CaseBits(0, Dest, 0));
1846 uint64_t lo = cast<ConstantInt>(I->Low)->getSExtValue() - lowBound;
1847 uint64_t hi = cast<ConstantInt>(I->High)->getSExtValue() - lowBound;
1849 for (uint64_t j = lo; j <= hi; j++) {
1850 CasesBits[i].Mask |= 1ULL << j;
1851 CasesBits[i].Bits++;
1855 std::sort(CasesBits.begin(), CasesBits.end(), CaseBitsCmp());
1857 SelectionDAGISel::BitTestInfo BTC;
1859 // Figure out which block is immediately after the current one.
1860 MachineFunction::iterator BBI = CR.CaseBB;
1863 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
1866 for (unsigned i = 0, e = CasesBits.size(); i!=e; ++i) {
1867 DOUT << "Mask: " << CasesBits[i].Mask << ", Bits: " << CasesBits[i].Bits
1868 << ", BB: " << CasesBits[i].BB << "\n";
1870 MachineBasicBlock *CaseBB = new MachineBasicBlock(LLVMBB);
1871 CurMF->getBasicBlockList().insert(BBI, CaseBB);
1872 BTC.push_back(SelectionDAGISel::BitTestCase(CasesBits[i].Mask,
1877 SelectionDAGISel::BitTestBlock BTB(lowBound, range, SV,
1878 -1U, (CR.CaseBB == CurMBB),
1879 CR.CaseBB, Default, BTC);
1881 if (CR.CaseBB == CurMBB)
1882 visitBitTestHeader(BTB);
1884 BitTestCases.push_back(BTB);
1890 // Clusterify - Transform simple list of Cases into list of CaseRange's
1891 unsigned SelectionDAGLowering::Clusterify(CaseVector& Cases,
1892 const SwitchInst& SI) {
1893 unsigned numCmps = 0;
1895 // Start with "simple" cases
1896 for (unsigned i = 1; i < SI.getNumSuccessors(); ++i) {
1897 MachineBasicBlock *SMBB = FuncInfo.MBBMap[SI.getSuccessor(i)];
1898 Cases.push_back(Case(SI.getSuccessorValue(i),
1899 SI.getSuccessorValue(i),
1902 sort(Cases.begin(), Cases.end(), CaseCmp());
1904 // Merge case into clusters
1905 if (Cases.size()>=2)
1906 // Must recompute end() each iteration because it may be
1907 // invalidated by erase if we hold on to it
1908 for (CaseItr I=Cases.begin(), J=++(Cases.begin()); J!=Cases.end(); ) {
1909 int64_t nextValue = cast<ConstantInt>(J->Low)->getSExtValue();
1910 int64_t currentValue = cast<ConstantInt>(I->High)->getSExtValue();
1911 MachineBasicBlock* nextBB = J->BB;
1912 MachineBasicBlock* currentBB = I->BB;
1914 // If the two neighboring cases go to the same destination, merge them
1915 // into a single case.
1916 if ((nextValue-currentValue==1) && (currentBB == nextBB)) {
1924 for (CaseItr I=Cases.begin(), E=Cases.end(); I!=E; ++I, ++numCmps) {
1925 if (I->Low != I->High)
1926 // A range counts double, since it requires two compares.
1933 void SelectionDAGLowering::visitSwitch(SwitchInst &SI) {
1934 // Figure out which block is immediately after the current one.
1935 MachineBasicBlock *NextBlock = 0;
1936 MachineFunction::iterator BBI = CurMBB;
1938 MachineBasicBlock *Default = FuncInfo.MBBMap[SI.getDefaultDest()];
1940 // If there is only the default destination, branch to it if it is not the
1941 // next basic block. Otherwise, just fall through.
1942 if (SI.getNumOperands() == 2) {
1943 // Update machine-CFG edges.
1945 // If this is not a fall-through branch, emit the branch.
1946 if (Default != NextBlock)
1947 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, getRoot(),
1948 DAG.getBasicBlock(Default)));
1950 CurMBB->addSuccessor(Default);
1954 // If there are any non-default case statements, create a vector of Cases
1955 // representing each one, and sort the vector so that we can efficiently
1956 // create a binary search tree from them.
1958 unsigned numCmps = Clusterify(Cases, SI);
1959 DOUT << "Clusterify finished. Total clusters: " << Cases.size()
1960 << ". Total compares: " << numCmps << "\n";
1962 // Get the Value to be switched on and default basic blocks, which will be
1963 // inserted into CaseBlock records, representing basic blocks in the binary
1965 Value *SV = SI.getOperand(0);
1967 // Push the initial CaseRec onto the worklist
1968 CaseRecVector WorkList;
1969 WorkList.push_back(CaseRec(CurMBB,0,0,CaseRange(Cases.begin(),Cases.end())));
1971 while (!WorkList.empty()) {
1972 // Grab a record representing a case range to process off the worklist
1973 CaseRec CR = WorkList.back();
1974 WorkList.pop_back();
1976 if (handleBitTestsSwitchCase(CR, WorkList, SV, Default))
1979 // If the range has few cases (two or less) emit a series of specific
1981 if (handleSmallSwitchRange(CR, WorkList, SV, Default))
1984 // If the switch has more than 5 blocks, and at least 40% dense, and the
1985 // target supports indirect branches, then emit a jump table rather than
1986 // lowering the switch to a binary tree of conditional branches.
1987 if (handleJTSwitchCase(CR, WorkList, SV, Default))
1990 // Emit binary tree. We need to pick a pivot, and push left and right ranges
1991 // onto the worklist. Leafs are handled via handleSmallSwitchRange() call.
1992 handleBTSplitSwitchCase(CR, WorkList, SV, Default);
1997 void SelectionDAGLowering::visitSub(User &I) {
1998 // -0.0 - X --> fneg
1999 const Type *Ty = I.getType();
2000 if (isa<VectorType>(Ty)) {
2001 if (ConstantVector *CV = dyn_cast<ConstantVector>(I.getOperand(0))) {
2002 const VectorType *DestTy = cast<VectorType>(I.getType());
2003 const Type *ElTy = DestTy->getElementType();
2004 if (ElTy->isFloatingPoint()) {
2005 unsigned VL = DestTy->getNumElements();
2006 std::vector<Constant*> NZ(VL, ConstantFP::get(ElTy, -0.0));
2007 Constant *CNZ = ConstantVector::get(&NZ[0], NZ.size());
2009 SDOperand Op2 = getValue(I.getOperand(1));
2010 setValue(&I, DAG.getNode(ISD::FNEG, Op2.getValueType(), Op2));
2016 if (Ty->isFloatingPoint()) {
2017 if (ConstantFP *CFP = dyn_cast<ConstantFP>(I.getOperand(0)))
2018 if (CFP->isExactlyValue(-0.0)) {
2019 SDOperand Op2 = getValue(I.getOperand(1));
2020 setValue(&I, DAG.getNode(ISD::FNEG, Op2.getValueType(), Op2));
2025 visitBinary(I, Ty->isFPOrFPVector() ? ISD::FSUB : ISD::SUB);
2028 void SelectionDAGLowering::visitBinary(User &I, unsigned OpCode) {
2029 SDOperand Op1 = getValue(I.getOperand(0));
2030 SDOperand Op2 = getValue(I.getOperand(1));
2032 setValue(&I, DAG.getNode(OpCode, Op1.getValueType(), Op1, Op2));
2035 void SelectionDAGLowering::visitShift(User &I, unsigned Opcode) {
2036 SDOperand Op1 = getValue(I.getOperand(0));
2037 SDOperand Op2 = getValue(I.getOperand(1));
2039 if (MVT::getSizeInBits(TLI.getShiftAmountTy()) <
2040 MVT::getSizeInBits(Op2.getValueType()))
2041 Op2 = DAG.getNode(ISD::TRUNCATE, TLI.getShiftAmountTy(), Op2);
2042 else if (TLI.getShiftAmountTy() > Op2.getValueType())
2043 Op2 = DAG.getNode(ISD::ANY_EXTEND, TLI.getShiftAmountTy(), Op2);
2045 setValue(&I, DAG.getNode(Opcode, Op1.getValueType(), Op1, Op2));
2048 void SelectionDAGLowering::visitICmp(User &I) {
2049 ICmpInst::Predicate predicate = ICmpInst::BAD_ICMP_PREDICATE;
2050 if (ICmpInst *IC = dyn_cast<ICmpInst>(&I))
2051 predicate = IC->getPredicate();
2052 else if (ConstantExpr *IC = dyn_cast<ConstantExpr>(&I))
2053 predicate = ICmpInst::Predicate(IC->getPredicate());
2054 SDOperand Op1 = getValue(I.getOperand(0));
2055 SDOperand Op2 = getValue(I.getOperand(1));
2056 ISD::CondCode Opcode;
2057 switch (predicate) {
2058 case ICmpInst::ICMP_EQ : Opcode = ISD::SETEQ; break;
2059 case ICmpInst::ICMP_NE : Opcode = ISD::SETNE; break;
2060 case ICmpInst::ICMP_UGT : Opcode = ISD::SETUGT; break;
2061 case ICmpInst::ICMP_UGE : Opcode = ISD::SETUGE; break;
2062 case ICmpInst::ICMP_ULT : Opcode = ISD::SETULT; break;
2063 case ICmpInst::ICMP_ULE : Opcode = ISD::SETULE; break;
2064 case ICmpInst::ICMP_SGT : Opcode = ISD::SETGT; break;
2065 case ICmpInst::ICMP_SGE : Opcode = ISD::SETGE; break;
2066 case ICmpInst::ICMP_SLT : Opcode = ISD::SETLT; break;
2067 case ICmpInst::ICMP_SLE : Opcode = ISD::SETLE; break;
2069 assert(!"Invalid ICmp predicate value");
2070 Opcode = ISD::SETEQ;
2073 setValue(&I, DAG.getSetCC(MVT::i1, Op1, Op2, Opcode));
2076 void SelectionDAGLowering::visitFCmp(User &I) {
2077 FCmpInst::Predicate predicate = FCmpInst::BAD_FCMP_PREDICATE;
2078 if (FCmpInst *FC = dyn_cast<FCmpInst>(&I))
2079 predicate = FC->getPredicate();
2080 else if (ConstantExpr *FC = dyn_cast<ConstantExpr>(&I))
2081 predicate = FCmpInst::Predicate(FC->getPredicate());
2082 SDOperand Op1 = getValue(I.getOperand(0));
2083 SDOperand Op2 = getValue(I.getOperand(1));
2084 ISD::CondCode Condition, FOC, FPC;
2085 switch (predicate) {
2086 case FCmpInst::FCMP_FALSE: FOC = FPC = ISD::SETFALSE; break;
2087 case FCmpInst::FCMP_OEQ: FOC = ISD::SETEQ; FPC = ISD::SETOEQ; break;
2088 case FCmpInst::FCMP_OGT: FOC = ISD::SETGT; FPC = ISD::SETOGT; break;
2089 case FCmpInst::FCMP_OGE: FOC = ISD::SETGE; FPC = ISD::SETOGE; break;
2090 case FCmpInst::FCMP_OLT: FOC = ISD::SETLT; FPC = ISD::SETOLT; break;
2091 case FCmpInst::FCMP_OLE: FOC = ISD::SETLE; FPC = ISD::SETOLE; break;
2092 case FCmpInst::FCMP_ONE: FOC = ISD::SETNE; FPC = ISD::SETONE; break;
2093 case FCmpInst::FCMP_ORD: FOC = ISD::SETEQ; FPC = ISD::SETO; break;
2094 case FCmpInst::FCMP_UNO: FOC = ISD::SETNE; FPC = ISD::SETUO; break;
2095 case FCmpInst::FCMP_UEQ: FOC = ISD::SETEQ; FPC = ISD::SETUEQ; break;
2096 case FCmpInst::FCMP_UGT: FOC = ISD::SETGT; FPC = ISD::SETUGT; break;
2097 case FCmpInst::FCMP_UGE: FOC = ISD::SETGE; FPC = ISD::SETUGE; break;
2098 case FCmpInst::FCMP_ULT: FOC = ISD::SETLT; FPC = ISD::SETULT; break;
2099 case FCmpInst::FCMP_ULE: FOC = ISD::SETLE; FPC = ISD::SETULE; break;
2100 case FCmpInst::FCMP_UNE: FOC = ISD::SETNE; FPC = ISD::SETUNE; break;
2101 case FCmpInst::FCMP_TRUE: FOC = FPC = ISD::SETTRUE; break;
2103 assert(!"Invalid FCmp predicate value");
2104 FOC = FPC = ISD::SETFALSE;
2107 if (FiniteOnlyFPMath())
2111 setValue(&I, DAG.getSetCC(MVT::i1, Op1, Op2, Condition));
2114 void SelectionDAGLowering::visitSelect(User &I) {
2115 SDOperand Cond = getValue(I.getOperand(0));
2116 SDOperand TrueVal = getValue(I.getOperand(1));
2117 SDOperand FalseVal = getValue(I.getOperand(2));
2118 setValue(&I, DAG.getNode(ISD::SELECT, TrueVal.getValueType(), Cond,
2119 TrueVal, FalseVal));
2123 void SelectionDAGLowering::visitTrunc(User &I) {
2124 // TruncInst cannot be a no-op cast because sizeof(src) > sizeof(dest).
2125 SDOperand N = getValue(I.getOperand(0));
2126 MVT::ValueType DestVT = TLI.getValueType(I.getType());
2127 setValue(&I, DAG.getNode(ISD::TRUNCATE, DestVT, N));
2130 void SelectionDAGLowering::visitZExt(User &I) {
2131 // ZExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
2132 // ZExt also can't be a cast to bool for same reason. So, nothing much to do
2133 SDOperand N = getValue(I.getOperand(0));
2134 MVT::ValueType DestVT = TLI.getValueType(I.getType());
2135 setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, DestVT, N));
2138 void SelectionDAGLowering::visitSExt(User &I) {
2139 // SExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
2140 // SExt also can't be a cast to bool for same reason. So, nothing much to do
2141 SDOperand N = getValue(I.getOperand(0));
2142 MVT::ValueType DestVT = TLI.getValueType(I.getType());
2143 setValue(&I, DAG.getNode(ISD::SIGN_EXTEND, DestVT, N));
2146 void SelectionDAGLowering::visitFPTrunc(User &I) {
2147 // FPTrunc is never a no-op cast, no need to check
2148 SDOperand N = getValue(I.getOperand(0));
2149 MVT::ValueType DestVT = TLI.getValueType(I.getType());
2150 setValue(&I, DAG.getNode(ISD::FP_ROUND, DestVT, N));
2153 void SelectionDAGLowering::visitFPExt(User &I){
2154 // FPTrunc is never a no-op cast, no need to check
2155 SDOperand N = getValue(I.getOperand(0));
2156 MVT::ValueType DestVT = TLI.getValueType(I.getType());
2157 setValue(&I, DAG.getNode(ISD::FP_EXTEND, DestVT, N));
2160 void SelectionDAGLowering::visitFPToUI(User &I) {
2161 // FPToUI is never a no-op cast, no need to check
2162 SDOperand N = getValue(I.getOperand(0));
2163 MVT::ValueType DestVT = TLI.getValueType(I.getType());
2164 setValue(&I, DAG.getNode(ISD::FP_TO_UINT, DestVT, N));
2167 void SelectionDAGLowering::visitFPToSI(User &I) {
2168 // FPToSI is never a no-op cast, no need to check
2169 SDOperand N = getValue(I.getOperand(0));
2170 MVT::ValueType DestVT = TLI.getValueType(I.getType());
2171 setValue(&I, DAG.getNode(ISD::FP_TO_SINT, DestVT, N));
2174 void SelectionDAGLowering::visitUIToFP(User &I) {
2175 // UIToFP is never a no-op cast, no need to check
2176 SDOperand N = getValue(I.getOperand(0));
2177 MVT::ValueType DestVT = TLI.getValueType(I.getType());
2178 setValue(&I, DAG.getNode(ISD::UINT_TO_FP, DestVT, N));
2181 void SelectionDAGLowering::visitSIToFP(User &I){
2182 // UIToFP is never a no-op cast, no need to check
2183 SDOperand N = getValue(I.getOperand(0));
2184 MVT::ValueType DestVT = TLI.getValueType(I.getType());
2185 setValue(&I, DAG.getNode(ISD::SINT_TO_FP, DestVT, N));
2188 void SelectionDAGLowering::visitPtrToInt(User &I) {
2189 // What to do depends on the size of the integer and the size of the pointer.
2190 // We can either truncate, zero extend, or no-op, accordingly.
2191 SDOperand N = getValue(I.getOperand(0));
2192 MVT::ValueType SrcVT = N.getValueType();
2193 MVT::ValueType DestVT = TLI.getValueType(I.getType());
2195 if (MVT::getSizeInBits(DestVT) < MVT::getSizeInBits(SrcVT))
2196 Result = DAG.getNode(ISD::TRUNCATE, DestVT, N);
2198 // Note: ZERO_EXTEND can handle cases where the sizes are equal too
2199 Result = DAG.getNode(ISD::ZERO_EXTEND, DestVT, N);
2200 setValue(&I, Result);
2203 void SelectionDAGLowering::visitIntToPtr(User &I) {
2204 // What to do depends on the size of the integer and the size of the pointer.
2205 // We can either truncate, zero extend, or no-op, accordingly.
2206 SDOperand N = getValue(I.getOperand(0));
2207 MVT::ValueType SrcVT = N.getValueType();
2208 MVT::ValueType DestVT = TLI.getValueType(I.getType());
2209 if (MVT::getSizeInBits(DestVT) < MVT::getSizeInBits(SrcVT))
2210 setValue(&I, DAG.getNode(ISD::TRUNCATE, DestVT, N));
2212 // Note: ZERO_EXTEND can handle cases where the sizes are equal too
2213 setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, DestVT, N));
2216 void SelectionDAGLowering::visitBitCast(User &I) {
2217 SDOperand N = getValue(I.getOperand(0));
2218 MVT::ValueType DestVT = TLI.getValueType(I.getType());
2220 // BitCast assures us that source and destination are the same size so this
2221 // is either a BIT_CONVERT or a no-op.
2222 if (DestVT != N.getValueType())
2223 setValue(&I, DAG.getNode(ISD::BIT_CONVERT, DestVT, N)); // convert types
2225 setValue(&I, N); // noop cast.
2228 void SelectionDAGLowering::visitInsertElement(User &I) {
2229 SDOperand InVec = getValue(I.getOperand(0));
2230 SDOperand InVal = getValue(I.getOperand(1));
2231 SDOperand InIdx = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(),
2232 getValue(I.getOperand(2)));
2234 setValue(&I, DAG.getNode(ISD::INSERT_VECTOR_ELT,
2235 TLI.getValueType(I.getType()),
2236 InVec, InVal, InIdx));
2239 void SelectionDAGLowering::visitExtractElement(User &I) {
2240 SDOperand InVec = getValue(I.getOperand(0));
2241 SDOperand InIdx = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(),
2242 getValue(I.getOperand(1)));
2243 setValue(&I, DAG.getNode(ISD::EXTRACT_VECTOR_ELT,
2244 TLI.getValueType(I.getType()), InVec, InIdx));
2247 void SelectionDAGLowering::visitShuffleVector(User &I) {
2248 SDOperand V1 = getValue(I.getOperand(0));
2249 SDOperand V2 = getValue(I.getOperand(1));
2250 SDOperand Mask = getValue(I.getOperand(2));
2252 setValue(&I, DAG.getNode(ISD::VECTOR_SHUFFLE,
2253 TLI.getValueType(I.getType()),
2258 void SelectionDAGLowering::visitGetElementPtr(User &I) {
2259 SDOperand N = getValue(I.getOperand(0));
2260 const Type *Ty = I.getOperand(0)->getType();
2262 for (GetElementPtrInst::op_iterator OI = I.op_begin()+1, E = I.op_end();
2265 if (const StructType *StTy = dyn_cast<StructType>(Ty)) {
2266 unsigned Field = cast<ConstantInt>(Idx)->getZExtValue();
2269 uint64_t Offset = TD->getStructLayout(StTy)->getElementOffset(Field);
2270 N = DAG.getNode(ISD::ADD, N.getValueType(), N,
2271 getIntPtrConstant(Offset));
2273 Ty = StTy->getElementType(Field);
2275 Ty = cast<SequentialType>(Ty)->getElementType();
2277 // If this is a constant subscript, handle it quickly.
2278 if (ConstantInt *CI = dyn_cast<ConstantInt>(Idx)) {
2279 if (CI->getZExtValue() == 0) continue;
2281 TD->getTypeSize(Ty)*cast<ConstantInt>(CI)->getSExtValue();
2282 N = DAG.getNode(ISD::ADD, N.getValueType(), N, getIntPtrConstant(Offs));
2286 // N = N + Idx * ElementSize;
2287 uint64_t ElementSize = TD->getTypeSize(Ty);
2288 SDOperand IdxN = getValue(Idx);
2290 // If the index is smaller or larger than intptr_t, truncate or extend
2292 if (IdxN.getValueType() < N.getValueType()) {
2293 IdxN = DAG.getNode(ISD::SIGN_EXTEND, N.getValueType(), IdxN);
2294 } else if (IdxN.getValueType() > N.getValueType())
2295 IdxN = DAG.getNode(ISD::TRUNCATE, N.getValueType(), IdxN);
2297 // If this is a multiply by a power of two, turn it into a shl
2298 // immediately. This is a very common case.
2299 if (isPowerOf2_64(ElementSize)) {
2300 unsigned Amt = Log2_64(ElementSize);
2301 IdxN = DAG.getNode(ISD::SHL, N.getValueType(), IdxN,
2302 DAG.getConstant(Amt, TLI.getShiftAmountTy()));
2303 N = DAG.getNode(ISD::ADD, N.getValueType(), N, IdxN);
2307 SDOperand Scale = getIntPtrConstant(ElementSize);
2308 IdxN = DAG.getNode(ISD::MUL, N.getValueType(), IdxN, Scale);
2309 N = DAG.getNode(ISD::ADD, N.getValueType(), N, IdxN);
2315 void SelectionDAGLowering::visitAlloca(AllocaInst &I) {
2316 // If this is a fixed sized alloca in the entry block of the function,
2317 // allocate it statically on the stack.
2318 if (FuncInfo.StaticAllocaMap.count(&I))
2319 return; // getValue will auto-populate this.
2321 const Type *Ty = I.getAllocatedType();
2322 uint64_t TySize = TLI.getTargetData()->getTypeSize(Ty);
2324 std::max((unsigned)TLI.getTargetData()->getPrefTypeAlignment(Ty),
2327 SDOperand AllocSize = getValue(I.getArraySize());
2328 MVT::ValueType IntPtr = TLI.getPointerTy();
2329 if (IntPtr < AllocSize.getValueType())
2330 AllocSize = DAG.getNode(ISD::TRUNCATE, IntPtr, AllocSize);
2331 else if (IntPtr > AllocSize.getValueType())
2332 AllocSize = DAG.getNode(ISD::ZERO_EXTEND, IntPtr, AllocSize);
2334 AllocSize = DAG.getNode(ISD::MUL, IntPtr, AllocSize,
2335 getIntPtrConstant(TySize));
2337 // Handle alignment. If the requested alignment is less than or equal to
2338 // the stack alignment, ignore it. If the size is greater than or equal to
2339 // the stack alignment, we note this in the DYNAMIC_STACKALLOC node.
2340 unsigned StackAlign =
2341 TLI.getTargetMachine().getFrameInfo()->getStackAlignment();
2342 if (Align <= StackAlign)
2345 // Round the size of the allocation up to the stack alignment size
2346 // by add SA-1 to the size.
2347 AllocSize = DAG.getNode(ISD::ADD, AllocSize.getValueType(), AllocSize,
2348 getIntPtrConstant(StackAlign-1));
2349 // Mask out the low bits for alignment purposes.
2350 AllocSize = DAG.getNode(ISD::AND, AllocSize.getValueType(), AllocSize,
2351 getIntPtrConstant(~(uint64_t)(StackAlign-1)));
2353 SDOperand Ops[] = { getRoot(), AllocSize, getIntPtrConstant(Align) };
2354 const MVT::ValueType *VTs = DAG.getNodeValueTypes(AllocSize.getValueType(),
2356 SDOperand DSA = DAG.getNode(ISD::DYNAMIC_STACKALLOC, VTs, 2, Ops, 3);
2358 DAG.setRoot(DSA.getValue(1));
2360 // Inform the Frame Information that we have just allocated a variable-sized
2362 CurMBB->getParent()->getFrameInfo()->CreateVariableSizedObject();
2365 void SelectionDAGLowering::visitLoad(LoadInst &I) {
2366 SDOperand Ptr = getValue(I.getOperand(0));
2372 // Do not serialize non-volatile loads against each other.
2373 Root = DAG.getRoot();
2376 setValue(&I, getLoadFrom(I.getType(), Ptr, I.getOperand(0),
2377 Root, I.isVolatile(), I.getAlignment()));
2380 SDOperand SelectionDAGLowering::getLoadFrom(const Type *Ty, SDOperand Ptr,
2381 const Value *SV, SDOperand Root,
2383 unsigned Alignment) {
2385 DAG.getLoad(TLI.getValueType(Ty), Root, Ptr, SV, 0,
2386 isVolatile, Alignment);
2389 DAG.setRoot(L.getValue(1));
2391 PendingLoads.push_back(L.getValue(1));
2397 void SelectionDAGLowering::visitStore(StoreInst &I) {
2398 Value *SrcV = I.getOperand(0);
2399 SDOperand Src = getValue(SrcV);
2400 SDOperand Ptr = getValue(I.getOperand(1));
2401 DAG.setRoot(DAG.getStore(getRoot(), Src, Ptr, I.getOperand(1), 0,
2402 I.isVolatile(), I.getAlignment()));
2405 /// IntrinsicCannotAccessMemory - Return true if the specified intrinsic cannot
2406 /// access memory and has no other side effects at all.
2407 static bool IntrinsicCannotAccessMemory(unsigned IntrinsicID) {
2408 #define GET_NO_MEMORY_INTRINSICS
2409 #include "llvm/Intrinsics.gen"
2410 #undef GET_NO_MEMORY_INTRINSICS
2414 // IntrinsicOnlyReadsMemory - Return true if the specified intrinsic doesn't
2415 // have any side-effects or if it only reads memory.
2416 static bool IntrinsicOnlyReadsMemory(unsigned IntrinsicID) {
2417 #define GET_SIDE_EFFECT_INFO
2418 #include "llvm/Intrinsics.gen"
2419 #undef GET_SIDE_EFFECT_INFO
2423 /// visitTargetIntrinsic - Lower a call of a target intrinsic to an INTRINSIC
2425 void SelectionDAGLowering::visitTargetIntrinsic(CallInst &I,
2426 unsigned Intrinsic) {
2427 bool HasChain = !IntrinsicCannotAccessMemory(Intrinsic);
2428 bool OnlyLoad = HasChain && IntrinsicOnlyReadsMemory(Intrinsic);
2430 // Build the operand list.
2431 SmallVector<SDOperand, 8> Ops;
2432 if (HasChain) { // If this intrinsic has side-effects, chainify it.
2434 // We don't need to serialize loads against other loads.
2435 Ops.push_back(DAG.getRoot());
2437 Ops.push_back(getRoot());
2441 // Add the intrinsic ID as an integer operand.
2442 Ops.push_back(DAG.getConstant(Intrinsic, TLI.getPointerTy()));
2444 // Add all operands of the call to the operand list.
2445 for (unsigned i = 1, e = I.getNumOperands(); i != e; ++i) {
2446 SDOperand Op = getValue(I.getOperand(i));
2447 assert(TLI.isTypeLegal(Op.getValueType()) &&
2448 "Intrinsic uses a non-legal type?");
2452 std::vector<MVT::ValueType> VTs;
2453 if (I.getType() != Type::VoidTy) {
2454 MVT::ValueType VT = TLI.getValueType(I.getType());
2455 if (MVT::isVector(VT)) {
2456 const VectorType *DestTy = cast<VectorType>(I.getType());
2457 MVT::ValueType EltVT = TLI.getValueType(DestTy->getElementType());
2459 VT = MVT::getVectorType(EltVT, DestTy->getNumElements());
2460 assert(VT != MVT::Other && "Intrinsic uses a non-legal type?");
2463 assert(TLI.isTypeLegal(VT) && "Intrinsic uses a non-legal type?");
2467 VTs.push_back(MVT::Other);
2469 const MVT::ValueType *VTList = DAG.getNodeValueTypes(VTs);
2474 Result = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, VTList, VTs.size(),
2475 &Ops[0], Ops.size());
2476 else if (I.getType() != Type::VoidTy)
2477 Result = DAG.getNode(ISD::INTRINSIC_W_CHAIN, VTList, VTs.size(),
2478 &Ops[0], Ops.size());
2480 Result = DAG.getNode(ISD::INTRINSIC_VOID, VTList, VTs.size(),
2481 &Ops[0], Ops.size());
2484 SDOperand Chain = Result.getValue(Result.Val->getNumValues()-1);
2486 PendingLoads.push_back(Chain);
2490 if (I.getType() != Type::VoidTy) {
2491 if (const VectorType *PTy = dyn_cast<VectorType>(I.getType())) {
2492 MVT::ValueType VT = TLI.getValueType(PTy);
2493 Result = DAG.getNode(ISD::BIT_CONVERT, VT, Result);
2495 setValue(&I, Result);
2499 /// ExtractTypeInfo - Returns the type info, possibly bitcast, encoded in V.
2500 static GlobalVariable *ExtractTypeInfo (Value *V) {
2501 V = IntrinsicInst::StripPointerCasts(V);
2502 GlobalVariable *GV = dyn_cast<GlobalVariable>(V);
2503 assert (GV || isa<ConstantPointerNull>(V) &&
2504 "TypeInfo must be a global variable or NULL");
2508 /// addCatchInfo - Extract the personality and type infos from an eh.selector
2509 /// call, and add them to the specified machine basic block.
2510 static void addCatchInfo(CallInst &I, MachineModuleInfo *MMI,
2511 MachineBasicBlock *MBB) {
2512 // Inform the MachineModuleInfo of the personality for this landing pad.
2513 ConstantExpr *CE = cast<ConstantExpr>(I.getOperand(2));
2514 assert(CE->getOpcode() == Instruction::BitCast &&
2515 isa<Function>(CE->getOperand(0)) &&
2516 "Personality should be a function");
2517 MMI->addPersonality(MBB, cast<Function>(CE->getOperand(0)));
2519 // Gather all the type infos for this landing pad and pass them along to
2520 // MachineModuleInfo.
2521 std::vector<GlobalVariable *> TyInfo;
2522 unsigned N = I.getNumOperands();
2524 for (unsigned i = N - 1; i > 2; --i) {
2525 if (ConstantInt *CI = dyn_cast<ConstantInt>(I.getOperand(i))) {
2526 unsigned FilterLength = CI->getZExtValue();
2527 unsigned FirstCatch = i + FilterLength + !FilterLength;
2528 assert (FirstCatch <= N && "Invalid filter length");
2530 if (FirstCatch < N) {
2531 TyInfo.reserve(N - FirstCatch);
2532 for (unsigned j = FirstCatch; j < N; ++j)
2533 TyInfo.push_back(ExtractTypeInfo(I.getOperand(j)));
2534 MMI->addCatchTypeInfo(MBB, TyInfo);
2538 if (!FilterLength) {
2540 MMI->addCleanup(MBB);
2543 TyInfo.reserve(FilterLength - 1);
2544 for (unsigned j = i + 1; j < FirstCatch; ++j)
2545 TyInfo.push_back(ExtractTypeInfo(I.getOperand(j)));
2546 MMI->addFilterTypeInfo(MBB, TyInfo);
2555 TyInfo.reserve(N - 3);
2556 for (unsigned j = 3; j < N; ++j)
2557 TyInfo.push_back(ExtractTypeInfo(I.getOperand(j)));
2558 MMI->addCatchTypeInfo(MBB, TyInfo);
2562 /// visitIntrinsicCall - Lower the call to the specified intrinsic function. If
2563 /// we want to emit this as a call to a named external function, return the name
2564 /// otherwise lower it and return null.
2566 SelectionDAGLowering::visitIntrinsicCall(CallInst &I, unsigned Intrinsic) {
2567 switch (Intrinsic) {
2569 // By default, turn this into a target intrinsic node.
2570 visitTargetIntrinsic(I, Intrinsic);
2572 case Intrinsic::vastart: visitVAStart(I); return 0;
2573 case Intrinsic::vaend: visitVAEnd(I); return 0;
2574 case Intrinsic::vacopy: visitVACopy(I); return 0;
2575 case Intrinsic::returnaddress:
2576 setValue(&I, DAG.getNode(ISD::RETURNADDR, TLI.getPointerTy(),
2577 getValue(I.getOperand(1))));
2579 case Intrinsic::frameaddress:
2580 setValue(&I, DAG.getNode(ISD::FRAMEADDR, TLI.getPointerTy(),
2581 getValue(I.getOperand(1))));
2583 case Intrinsic::setjmp:
2584 return "_setjmp"+!TLI.usesUnderscoreSetJmp();
2586 case Intrinsic::longjmp:
2587 return "_longjmp"+!TLI.usesUnderscoreLongJmp();
2589 case Intrinsic::memcpy_i32:
2590 case Intrinsic::memcpy_i64:
2591 visitMemIntrinsic(I, ISD::MEMCPY);
2593 case Intrinsic::memset_i32:
2594 case Intrinsic::memset_i64:
2595 visitMemIntrinsic(I, ISD::MEMSET);
2597 case Intrinsic::memmove_i32:
2598 case Intrinsic::memmove_i64:
2599 visitMemIntrinsic(I, ISD::MEMMOVE);
2602 case Intrinsic::dbg_stoppoint: {
2603 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
2604 DbgStopPointInst &SPI = cast<DbgStopPointInst>(I);
2605 if (MMI && SPI.getContext() && MMI->Verify(SPI.getContext())) {
2609 Ops[1] = getValue(SPI.getLineValue());
2610 Ops[2] = getValue(SPI.getColumnValue());
2612 DebugInfoDesc *DD = MMI->getDescFor(SPI.getContext());
2613 assert(DD && "Not a debug information descriptor");
2614 CompileUnitDesc *CompileUnit = cast<CompileUnitDesc>(DD);
2616 Ops[3] = DAG.getString(CompileUnit->getFileName());
2617 Ops[4] = DAG.getString(CompileUnit->getDirectory());
2619 DAG.setRoot(DAG.getNode(ISD::LOCATION, MVT::Other, Ops, 5));
2624 case Intrinsic::dbg_region_start: {
2625 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
2626 DbgRegionStartInst &RSI = cast<DbgRegionStartInst>(I);
2627 if (MMI && RSI.getContext() && MMI->Verify(RSI.getContext())) {
2628 unsigned LabelID = MMI->RecordRegionStart(RSI.getContext());
2629 DAG.setRoot(DAG.getNode(ISD::LABEL, MVT::Other, getRoot(),
2630 DAG.getConstant(LabelID, MVT::i32)));
2635 case Intrinsic::dbg_region_end: {
2636 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
2637 DbgRegionEndInst &REI = cast<DbgRegionEndInst>(I);
2638 if (MMI && REI.getContext() && MMI->Verify(REI.getContext())) {
2639 unsigned LabelID = MMI->RecordRegionEnd(REI.getContext());
2640 DAG.setRoot(DAG.getNode(ISD::LABEL, MVT::Other,
2641 getRoot(), DAG.getConstant(LabelID, MVT::i32)));
2646 case Intrinsic::dbg_func_start: {
2647 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
2648 DbgFuncStartInst &FSI = cast<DbgFuncStartInst>(I);
2649 if (MMI && FSI.getSubprogram() &&
2650 MMI->Verify(FSI.getSubprogram())) {
2651 unsigned LabelID = MMI->RecordRegionStart(FSI.getSubprogram());
2652 DAG.setRoot(DAG.getNode(ISD::LABEL, MVT::Other,
2653 getRoot(), DAG.getConstant(LabelID, MVT::i32)));
2658 case Intrinsic::dbg_declare: {
2659 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
2660 DbgDeclareInst &DI = cast<DbgDeclareInst>(I);
2661 if (MMI && DI.getVariable() && MMI->Verify(DI.getVariable())) {
2662 SDOperand AddressOp = getValue(DI.getAddress());
2663 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(AddressOp))
2664 MMI->RecordVariable(DI.getVariable(), FI->getIndex());
2670 case Intrinsic::eh_exception: {
2671 if (ExceptionHandling) {
2672 if (!CurMBB->isLandingPad()) {
2673 // FIXME: Mark exception register as live in. Hack for PR1508.
2674 unsigned Reg = TLI.getExceptionAddressRegister();
2675 if (Reg) CurMBB->addLiveIn(Reg);
2677 // Insert the EXCEPTIONADDR instruction.
2678 SDVTList VTs = DAG.getVTList(TLI.getPointerTy(), MVT::Other);
2680 Ops[0] = DAG.getRoot();
2681 SDOperand Op = DAG.getNode(ISD::EXCEPTIONADDR, VTs, Ops, 1);
2683 DAG.setRoot(Op.getValue(1));
2685 setValue(&I, DAG.getConstant(0, TLI.getPointerTy()));
2690 case Intrinsic::eh_selector:{
2691 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
2693 if (ExceptionHandling && MMI) {
2694 if (CurMBB->isLandingPad())
2695 addCatchInfo(I, MMI, CurMBB);
2698 FuncInfo.CatchInfoLost.insert(&I);
2700 // FIXME: Mark exception selector register as live in. Hack for PR1508.
2701 unsigned Reg = TLI.getExceptionSelectorRegister();
2702 if (Reg) CurMBB->addLiveIn(Reg);
2705 // Insert the EHSELECTION instruction.
2706 SDVTList VTs = DAG.getVTList(TLI.getPointerTy(), MVT::Other);
2708 Ops[0] = getValue(I.getOperand(1));
2710 SDOperand Op = DAG.getNode(ISD::EHSELECTION, VTs, Ops, 2);
2712 DAG.setRoot(Op.getValue(1));
2714 setValue(&I, DAG.getConstant(0, TLI.getPointerTy()));
2720 case Intrinsic::eh_typeid_for: {
2721 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
2724 // Find the type id for the given typeinfo.
2725 GlobalVariable *GV = ExtractTypeInfo(I.getOperand(1));
2727 unsigned TypeID = MMI->getTypeIDFor(GV);
2728 setValue(&I, DAG.getConstant(TypeID, MVT::i32));
2730 // Return something different to eh_selector.
2731 setValue(&I, DAG.getConstant(1, MVT::i32));
2737 case Intrinsic::eh_return: {
2738 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
2740 if (MMI && ExceptionHandling) {
2741 MMI->setCallsEHReturn(true);
2742 DAG.setRoot(DAG.getNode(ISD::EH_RETURN,
2745 getValue(I.getOperand(1)),
2746 getValue(I.getOperand(2))));
2748 setValue(&I, DAG.getConstant(0, TLI.getPointerTy()));
2754 case Intrinsic::eh_unwind_init: {
2755 if (MachineModuleInfo *MMI = DAG.getMachineModuleInfo()) {
2756 MMI->setCallsUnwindInit(true);
2762 case Intrinsic::eh_dwarf_cfa: {
2763 if (ExceptionHandling) {
2764 MVT::ValueType VT = getValue(I.getOperand(1)).getValueType();
2766 if (MVT::getSizeInBits(VT) > MVT::getSizeInBits(TLI.getPointerTy()))
2767 CfaArg = DAG.getNode(ISD::TRUNCATE,
2768 TLI.getPointerTy(), getValue(I.getOperand(1)));
2770 CfaArg = DAG.getNode(ISD::SIGN_EXTEND,
2771 TLI.getPointerTy(), getValue(I.getOperand(1)));
2773 SDOperand Offset = DAG.getNode(ISD::ADD,
2775 DAG.getNode(ISD::FRAME_TO_ARGS_OFFSET,
2776 TLI.getPointerTy()),
2778 setValue(&I, DAG.getNode(ISD::ADD,
2780 DAG.getNode(ISD::FRAMEADDR,
2783 TLI.getPointerTy())),
2786 setValue(&I, DAG.getConstant(0, TLI.getPointerTy()));
2792 case Intrinsic::sqrt_f32:
2793 case Intrinsic::sqrt_f64:
2794 setValue(&I, DAG.getNode(ISD::FSQRT,
2795 getValue(I.getOperand(1)).getValueType(),
2796 getValue(I.getOperand(1))));
2798 case Intrinsic::powi_f32:
2799 case Intrinsic::powi_f64:
2800 setValue(&I, DAG.getNode(ISD::FPOWI,
2801 getValue(I.getOperand(1)).getValueType(),
2802 getValue(I.getOperand(1)),
2803 getValue(I.getOperand(2))));
2805 case Intrinsic::pcmarker: {
2806 SDOperand Tmp = getValue(I.getOperand(1));
2807 DAG.setRoot(DAG.getNode(ISD::PCMARKER, MVT::Other, getRoot(), Tmp));
2810 case Intrinsic::readcyclecounter: {
2811 SDOperand Op = getRoot();
2812 SDOperand Tmp = DAG.getNode(ISD::READCYCLECOUNTER,
2813 DAG.getNodeValueTypes(MVT::i64, MVT::Other), 2,
2816 DAG.setRoot(Tmp.getValue(1));
2819 case Intrinsic::part_select: {
2820 // Currently not implemented: just abort
2821 assert(0 && "part_select intrinsic not implemented");
2824 case Intrinsic::part_set: {
2825 // Currently not implemented: just abort
2826 assert(0 && "part_set intrinsic not implemented");
2829 case Intrinsic::bswap:
2830 setValue(&I, DAG.getNode(ISD::BSWAP,
2831 getValue(I.getOperand(1)).getValueType(),
2832 getValue(I.getOperand(1))));
2834 case Intrinsic::cttz: {
2835 SDOperand Arg = getValue(I.getOperand(1));
2836 MVT::ValueType Ty = Arg.getValueType();
2837 SDOperand result = DAG.getNode(ISD::CTTZ, Ty, Arg);
2838 setValue(&I, result);
2841 case Intrinsic::ctlz: {
2842 SDOperand Arg = getValue(I.getOperand(1));
2843 MVT::ValueType Ty = Arg.getValueType();
2844 SDOperand result = DAG.getNode(ISD::CTLZ, Ty, Arg);
2845 setValue(&I, result);
2848 case Intrinsic::ctpop: {
2849 SDOperand Arg = getValue(I.getOperand(1));
2850 MVT::ValueType Ty = Arg.getValueType();
2851 SDOperand result = DAG.getNode(ISD::CTPOP, Ty, Arg);
2852 setValue(&I, result);
2855 case Intrinsic::stacksave: {
2856 SDOperand Op = getRoot();
2857 SDOperand Tmp = DAG.getNode(ISD::STACKSAVE,
2858 DAG.getNodeValueTypes(TLI.getPointerTy(), MVT::Other), 2, &Op, 1);
2860 DAG.setRoot(Tmp.getValue(1));
2863 case Intrinsic::stackrestore: {
2864 SDOperand Tmp = getValue(I.getOperand(1));
2865 DAG.setRoot(DAG.getNode(ISD::STACKRESTORE, MVT::Other, getRoot(), Tmp));
2868 case Intrinsic::prefetch:
2869 // FIXME: Currently discarding prefetches.
2872 case Intrinsic::var_annotation:
2873 // Discard annotate attributes
2876 case Intrinsic::adjust_trampoline: {
2877 SDOperand Arg = getValue(I.getOperand(1));
2878 setValue(&I, DAG.getNode(ISD::ADJUST_TRAMP, TLI.getPointerTy(), Arg));
2882 case Intrinsic::init_trampoline: {
2884 cast<Function>(IntrinsicInst::StripPointerCasts(I.getOperand(2)));
2888 Ops[1] = getValue(I.getOperand(1));
2889 Ops[2] = getValue(I.getOperand(2));
2890 Ops[3] = getValue(I.getOperand(3));
2891 Ops[4] = DAG.getSrcValue(I.getOperand(1));
2892 Ops[5] = DAG.getSrcValue(F);
2894 DAG.setRoot(DAG.getNode(ISD::TRAMPOLINE, MVT::Other, Ops, 6));
2901 void SelectionDAGLowering::LowerCallTo(Instruction &I,
2902 const Type *CalledValueTy,
2903 unsigned CallingConv,
2905 SDOperand Callee, unsigned OpIdx,
2906 MachineBasicBlock *LandingPad) {
2907 const PointerType *PT = cast<PointerType>(CalledValueTy);
2908 const FunctionType *FTy = cast<FunctionType>(PT->getElementType());
2909 const ParamAttrsList *Attrs = FTy->getParamAttrs();
2910 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
2911 unsigned BeginLabel = 0, EndLabel = 0;
2913 TargetLowering::ArgListTy Args;
2914 TargetLowering::ArgListEntry Entry;
2915 Args.reserve(I.getNumOperands());
2916 for (unsigned i = OpIdx, e = I.getNumOperands(); i != e; ++i) {
2917 Value *Arg = I.getOperand(i);
2918 SDOperand ArgNode = getValue(Arg);
2919 Entry.Node = ArgNode; Entry.Ty = Arg->getType();
2921 unsigned attrInd = i - OpIdx + 1;
2922 Entry.isSExt = Attrs && Attrs->paramHasAttr(attrInd, ParamAttr::SExt);
2923 Entry.isZExt = Attrs && Attrs->paramHasAttr(attrInd, ParamAttr::ZExt);
2924 Entry.isInReg = Attrs && Attrs->paramHasAttr(attrInd, ParamAttr::InReg);
2925 Entry.isSRet = Attrs && Attrs->paramHasAttr(attrInd, ParamAttr::StructRet);
2926 Entry.isNest = Attrs && Attrs->paramHasAttr(attrInd, ParamAttr::Nest);
2927 Entry.isByVal = Attrs && Attrs->paramHasAttr(attrInd, ParamAttr::ByVal);
2928 Args.push_back(Entry);
2931 if (ExceptionHandling && MMI) {
2932 // Insert a label before the invoke call to mark the try range. This can be
2933 // used to detect deletion of the invoke via the MachineModuleInfo.
2934 BeginLabel = MMI->NextLabelID();
2935 DAG.setRoot(DAG.getNode(ISD::LABEL, MVT::Other, getRoot(),
2936 DAG.getConstant(BeginLabel, MVT::i32)));
2939 std::pair<SDOperand,SDOperand> Result =
2940 TLI.LowerCallTo(getRoot(), I.getType(),
2941 Attrs && Attrs->paramHasAttr(0, ParamAttr::SExt),
2942 FTy->isVarArg(), CallingConv, IsTailCall,
2944 if (I.getType() != Type::VoidTy)
2945 setValue(&I, Result.first);
2946 DAG.setRoot(Result.second);
2948 if (ExceptionHandling && MMI) {
2949 // Insert a label at the end of the invoke call to mark the try range. This
2950 // can be used to detect deletion of the invoke via the MachineModuleInfo.
2951 EndLabel = MMI->NextLabelID();
2952 DAG.setRoot(DAG.getNode(ISD::LABEL, MVT::Other, getRoot(),
2953 DAG.getConstant(EndLabel, MVT::i32)));
2955 // Inform MachineModuleInfo of range.
2956 MMI->addInvoke(LandingPad, BeginLabel, EndLabel);
2961 void SelectionDAGLowering::visitCall(CallInst &I) {
2962 const char *RenameFn = 0;
2963 if (Function *F = I.getCalledFunction()) {
2964 if (F->isDeclaration())
2965 if (unsigned IID = F->getIntrinsicID()) {
2966 RenameFn = visitIntrinsicCall(I, IID);
2969 } else { // Not an LLVM intrinsic.
2970 const std::string &Name = F->getName();
2971 if (Name[0] == 'c' && (Name == "copysign" || Name == "copysignf")) {
2972 if (I.getNumOperands() == 3 && // Basic sanity checks.
2973 I.getOperand(1)->getType()->isFloatingPoint() &&
2974 I.getType() == I.getOperand(1)->getType() &&
2975 I.getType() == I.getOperand(2)->getType()) {
2976 SDOperand LHS = getValue(I.getOperand(1));
2977 SDOperand RHS = getValue(I.getOperand(2));
2978 setValue(&I, DAG.getNode(ISD::FCOPYSIGN, LHS.getValueType(),
2982 } else if (Name[0] == 'f' && (Name == "fabs" || Name == "fabsf")) {
2983 if (I.getNumOperands() == 2 && // Basic sanity checks.
2984 I.getOperand(1)->getType()->isFloatingPoint() &&
2985 I.getType() == I.getOperand(1)->getType()) {
2986 SDOperand Tmp = getValue(I.getOperand(1));
2987 setValue(&I, DAG.getNode(ISD::FABS, Tmp.getValueType(), Tmp));
2990 } else if (Name[0] == 's' && (Name == "sin" || Name == "sinf")) {
2991 if (I.getNumOperands() == 2 && // Basic sanity checks.
2992 I.getOperand(1)->getType()->isFloatingPoint() &&
2993 I.getType() == I.getOperand(1)->getType()) {
2994 SDOperand Tmp = getValue(I.getOperand(1));
2995 setValue(&I, DAG.getNode(ISD::FSIN, Tmp.getValueType(), Tmp));
2998 } else if (Name[0] == 'c' && (Name == "cos" || Name == "cosf")) {
2999 if (I.getNumOperands() == 2 && // Basic sanity checks.
3000 I.getOperand(1)->getType()->isFloatingPoint() &&
3001 I.getType() == I.getOperand(1)->getType()) {
3002 SDOperand Tmp = getValue(I.getOperand(1));
3003 setValue(&I, DAG.getNode(ISD::FCOS, Tmp.getValueType(), Tmp));
3008 } else if (isa<InlineAsm>(I.getOperand(0))) {
3015 Callee = getValue(I.getOperand(0));
3017 Callee = DAG.getExternalSymbol(RenameFn, TLI.getPointerTy());
3019 LowerCallTo(I, I.getCalledValue()->getType(),
3027 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from
3028 /// this value and returns the result as a ValueVT value. This uses
3029 /// Chain/Flag as the input and updates them for the output Chain/Flag.
3030 /// If the Flag pointer is NULL, no flag is used.
3031 SDOperand RegsForValue::getCopyFromRegs(SelectionDAG &DAG,
3032 SDOperand &Chain, SDOperand *Flag)const{
3033 // Copy the legal parts from the registers.
3034 unsigned NumParts = Regs.size();
3035 SmallVector<SDOperand, 8> Parts(NumParts);
3036 for (unsigned i = 0; i != NumParts; ++i) {
3037 SDOperand Part = Flag ?
3038 DAG.getCopyFromReg(Chain, Regs[i], RegVT, *Flag) :
3039 DAG.getCopyFromReg(Chain, Regs[i], RegVT);
3040 Chain = Part.getValue(1);
3042 *Flag = Part.getValue(2);
3046 // Assemble the legal parts into the final value.
3047 return getCopyFromParts(DAG, &Parts[0], NumParts, RegVT, ValueVT);
3050 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
3051 /// specified value into the registers specified by this object. This uses
3052 /// Chain/Flag as the input and updates them for the output Chain/Flag.
3053 /// If the Flag pointer is NULL, no flag is used.
3054 void RegsForValue::getCopyToRegs(SDOperand Val, SelectionDAG &DAG,
3055 SDOperand &Chain, SDOperand *Flag) const {
3056 // Get the list of the values's legal parts.
3057 unsigned NumParts = Regs.size();
3058 SmallVector<SDOperand, 8> Parts(NumParts);
3059 getCopyToParts(DAG, Val, &Parts[0], NumParts, RegVT);
3061 // Copy the parts into the registers.
3062 for (unsigned i = 0; i != NumParts; ++i) {
3063 SDOperand Part = Flag ?
3064 DAG.getCopyToReg(Chain, Regs[i], Parts[i], *Flag) :
3065 DAG.getCopyToReg(Chain, Regs[i], Parts[i]);
3066 Chain = Part.getValue(0);
3068 *Flag = Part.getValue(1);
3072 /// AddInlineAsmOperands - Add this value to the specified inlineasm node
3073 /// operand list. This adds the code marker and includes the number of
3074 /// values added into it.
3075 void RegsForValue::AddInlineAsmOperands(unsigned Code, SelectionDAG &DAG,
3076 std::vector<SDOperand> &Ops) const {
3077 MVT::ValueType IntPtrTy = DAG.getTargetLoweringInfo().getPointerTy();
3078 Ops.push_back(DAG.getTargetConstant(Code | (Regs.size() << 3), IntPtrTy));
3079 for (unsigned i = 0, e = Regs.size(); i != e; ++i)
3080 Ops.push_back(DAG.getRegister(Regs[i], RegVT));
3083 /// isAllocatableRegister - If the specified register is safe to allocate,
3084 /// i.e. it isn't a stack pointer or some other special register, return the
3085 /// register class for the register. Otherwise, return null.
3086 static const TargetRegisterClass *
3087 isAllocatableRegister(unsigned Reg, MachineFunction &MF,
3088 const TargetLowering &TLI, const MRegisterInfo *MRI) {
3089 MVT::ValueType FoundVT = MVT::Other;
3090 const TargetRegisterClass *FoundRC = 0;
3091 for (MRegisterInfo::regclass_iterator RCI = MRI->regclass_begin(),
3092 E = MRI->regclass_end(); RCI != E; ++RCI) {
3093 MVT::ValueType ThisVT = MVT::Other;
3095 const TargetRegisterClass *RC = *RCI;
3096 // If none of the the value types for this register class are valid, we
3097 // can't use it. For example, 64-bit reg classes on 32-bit targets.
3098 for (TargetRegisterClass::vt_iterator I = RC->vt_begin(), E = RC->vt_end();
3100 if (TLI.isTypeLegal(*I)) {
3101 // If we have already found this register in a different register class,
3102 // choose the one with the largest VT specified. For example, on
3103 // PowerPC, we favor f64 register classes over f32.
3104 if (FoundVT == MVT::Other ||
3105 MVT::getSizeInBits(FoundVT) < MVT::getSizeInBits(*I)) {
3112 if (ThisVT == MVT::Other) continue;
3114 // NOTE: This isn't ideal. In particular, this might allocate the
3115 // frame pointer in functions that need it (due to them not being taken
3116 // out of allocation, because a variable sized allocation hasn't been seen
3117 // yet). This is a slight code pessimization, but should still work.
3118 for (TargetRegisterClass::iterator I = RC->allocation_order_begin(MF),
3119 E = RC->allocation_order_end(MF); I != E; ++I)
3121 // We found a matching register class. Keep looking at others in case
3122 // we find one with larger registers that this physreg is also in.
3133 /// AsmOperandInfo - This contains information for each constraint that we are
3135 struct AsmOperandInfo : public InlineAsm::ConstraintInfo {
3136 /// ConstraintCode - This contains the actual string for the code, like "m".
3137 std::string ConstraintCode;
3139 /// ConstraintType - Information about the constraint code, e.g. Register,
3140 /// RegisterClass, Memory, Other, Unknown.
3141 TargetLowering::ConstraintType ConstraintType;
3143 /// CallOperand/CallOperandval - If this is the result output operand or a
3144 /// clobber, this is null, otherwise it is the incoming operand to the
3145 /// CallInst. This gets modified as the asm is processed.
3146 SDOperand CallOperand;
3147 Value *CallOperandVal;
3149 /// ConstraintVT - The ValueType for the operand value.
3150 MVT::ValueType ConstraintVT;
3152 /// AssignedRegs - If this is a register or register class operand, this
3153 /// contains the set of register corresponding to the operand.
3154 RegsForValue AssignedRegs;
3156 AsmOperandInfo(const InlineAsm::ConstraintInfo &info)
3157 : InlineAsm::ConstraintInfo(info),
3158 ConstraintType(TargetLowering::C_Unknown),
3159 CallOperand(0,0), CallOperandVal(0), ConstraintVT(MVT::Other) {
3162 void ComputeConstraintToUse(const TargetLowering &TLI);
3164 /// MarkAllocatedRegs - Once AssignedRegs is set, mark the assigned registers
3165 /// busy in OutputRegs/InputRegs.
3166 void MarkAllocatedRegs(bool isOutReg, bool isInReg,
3167 std::set<unsigned> &OutputRegs,
3168 std::set<unsigned> &InputRegs) const {
3170 OutputRegs.insert(AssignedRegs.Regs.begin(), AssignedRegs.Regs.end());
3172 InputRegs.insert(AssignedRegs.Regs.begin(), AssignedRegs.Regs.end());
3175 } // end anon namespace.
3177 /// getConstraintGenerality - Return an integer indicating how general CT is.
3178 static unsigned getConstraintGenerality(TargetLowering::ConstraintType CT) {
3180 default: assert(0 && "Unknown constraint type!");
3181 case TargetLowering::C_Other:
3182 case TargetLowering::C_Unknown:
3184 case TargetLowering::C_Register:
3186 case TargetLowering::C_RegisterClass:
3188 case TargetLowering::C_Memory:
3193 void AsmOperandInfo::ComputeConstraintToUse(const TargetLowering &TLI) {
3194 assert(!Codes.empty() && "Must have at least one constraint");
3196 std::string *Current = &Codes[0];
3197 TargetLowering::ConstraintType CurType = TLI.getConstraintType(*Current);
3198 if (Codes.size() == 1) { // Single-letter constraints ('r') are very common.
3199 ConstraintCode = *Current;
3200 ConstraintType = CurType;
3204 unsigned CurGenerality = getConstraintGenerality(CurType);
3206 // If we have multiple constraints, try to pick the most general one ahead
3207 // of time. This isn't a wonderful solution, but handles common cases.
3208 for (unsigned j = 1, e = Codes.size(); j != e; ++j) {
3209 TargetLowering::ConstraintType ThisType = TLI.getConstraintType(Codes[j]);
3210 unsigned ThisGenerality = getConstraintGenerality(ThisType);
3211 if (ThisGenerality > CurGenerality) {
3212 // This constraint letter is more general than the previous one,
3215 Current = &Codes[j];
3216 CurGenerality = ThisGenerality;
3220 ConstraintCode = *Current;
3221 ConstraintType = CurType;
3225 void SelectionDAGLowering::
3226 GetRegistersForValue(AsmOperandInfo &OpInfo, bool HasEarlyClobber,
3227 std::set<unsigned> &OutputRegs,
3228 std::set<unsigned> &InputRegs) {
3229 // Compute whether this value requires an input register, an output register,
3231 bool isOutReg = false;
3232 bool isInReg = false;
3233 switch (OpInfo.Type) {
3234 case InlineAsm::isOutput:
3237 // If this is an early-clobber output, or if there is an input
3238 // constraint that matches this, we need to reserve the input register
3239 // so no other inputs allocate to it.
3240 isInReg = OpInfo.isEarlyClobber || OpInfo.hasMatchingInput;
3242 case InlineAsm::isInput:
3246 case InlineAsm::isClobber:
3253 MachineFunction &MF = DAG.getMachineFunction();
3254 std::vector<unsigned> Regs;
3256 // If this is a constraint for a single physreg, or a constraint for a
3257 // register class, find it.
3258 std::pair<unsigned, const TargetRegisterClass*> PhysReg =
3259 TLI.getRegForInlineAsmConstraint(OpInfo.ConstraintCode,
3260 OpInfo.ConstraintVT);
3262 unsigned NumRegs = 1;
3263 if (OpInfo.ConstraintVT != MVT::Other)
3264 NumRegs = TLI.getNumRegisters(OpInfo.ConstraintVT);
3265 MVT::ValueType RegVT;
3266 MVT::ValueType ValueVT = OpInfo.ConstraintVT;
3269 // If this is a constraint for a specific physical register, like {r17},
3271 if (PhysReg.first) {
3272 if (OpInfo.ConstraintVT == MVT::Other)
3273 ValueVT = *PhysReg.second->vt_begin();
3275 // Get the actual register value type. This is important, because the user
3276 // may have asked for (e.g.) the AX register in i32 type. We need to
3277 // remember that AX is actually i16 to get the right extension.
3278 RegVT = *PhysReg.second->vt_begin();
3280 // This is a explicit reference to a physical register.
3281 Regs.push_back(PhysReg.first);
3283 // If this is an expanded reference, add the rest of the regs to Regs.
3285 TargetRegisterClass::iterator I = PhysReg.second->begin();
3286 TargetRegisterClass::iterator E = PhysReg.second->end();
3287 for (; *I != PhysReg.first; ++I)
3288 assert(I != E && "Didn't find reg!");
3290 // Already added the first reg.
3292 for (; NumRegs; --NumRegs, ++I) {
3293 assert(I != E && "Ran out of registers to allocate!");
3297 OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT);
3298 OpInfo.MarkAllocatedRegs(isOutReg, isInReg, OutputRegs, InputRegs);
3302 // Otherwise, if this was a reference to an LLVM register class, create vregs
3303 // for this reference.
3304 std::vector<unsigned> RegClassRegs;
3305 const TargetRegisterClass *RC = PhysReg.second;
3307 // If this is an early clobber or tied register, our regalloc doesn't know
3308 // how to maintain the constraint. If it isn't, go ahead and create vreg
3309 // and let the regalloc do the right thing.
3310 if (!OpInfo.hasMatchingInput && !OpInfo.isEarlyClobber &&
3311 // If there is some other early clobber and this is an input register,
3312 // then we are forced to pre-allocate the input reg so it doesn't
3313 // conflict with the earlyclobber.
3314 !(OpInfo.Type == InlineAsm::isInput && HasEarlyClobber)) {
3315 RegVT = *PhysReg.second->vt_begin();
3317 if (OpInfo.ConstraintVT == MVT::Other)
3320 // Create the appropriate number of virtual registers.
3321 SSARegMap *RegMap = MF.getSSARegMap();
3322 for (; NumRegs; --NumRegs)
3323 Regs.push_back(RegMap->createVirtualRegister(PhysReg.second));
3325 OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT);
3326 OpInfo.MarkAllocatedRegs(isOutReg, isInReg, OutputRegs, InputRegs);
3330 // Otherwise, we can't allocate it. Let the code below figure out how to
3331 // maintain these constraints.
3332 RegClassRegs.assign(PhysReg.second->begin(), PhysReg.second->end());
3335 // This is a reference to a register class that doesn't directly correspond
3336 // to an LLVM register class. Allocate NumRegs consecutive, available,
3337 // registers from the class.
3338 RegClassRegs = TLI.getRegClassForInlineAsmConstraint(OpInfo.ConstraintCode,
3339 OpInfo.ConstraintVT);
3342 const MRegisterInfo *MRI = DAG.getTarget().getRegisterInfo();
3343 unsigned NumAllocated = 0;
3344 for (unsigned i = 0, e = RegClassRegs.size(); i != e; ++i) {
3345 unsigned Reg = RegClassRegs[i];
3346 // See if this register is available.
3347 if ((isOutReg && OutputRegs.count(Reg)) || // Already used.
3348 (isInReg && InputRegs.count(Reg))) { // Already used.
3349 // Make sure we find consecutive registers.
3354 // Check to see if this register is allocatable (i.e. don't give out the
3357 RC = isAllocatableRegister(Reg, MF, TLI, MRI);
3358 if (!RC) { // Couldn't allocate this register.
3359 // Reset NumAllocated to make sure we return consecutive registers.
3365 // Okay, this register is good, we can use it.
3368 // If we allocated enough consecutive registers, succeed.
3369 if (NumAllocated == NumRegs) {
3370 unsigned RegStart = (i-NumAllocated)+1;
3371 unsigned RegEnd = i+1;
3372 // Mark all of the allocated registers used.
3373 for (unsigned i = RegStart; i != RegEnd; ++i)
3374 Regs.push_back(RegClassRegs[i]);
3376 OpInfo.AssignedRegs = RegsForValue(Regs, *RC->vt_begin(),
3377 OpInfo.ConstraintVT);
3378 OpInfo.MarkAllocatedRegs(isOutReg, isInReg, OutputRegs, InputRegs);
3383 // Otherwise, we couldn't allocate enough registers for this.
3388 /// visitInlineAsm - Handle a call to an InlineAsm object.
3390 void SelectionDAGLowering::visitInlineAsm(CallInst &I) {
3391 InlineAsm *IA = cast<InlineAsm>(I.getOperand(0));
3393 /// ConstraintOperands - Information about all of the constraints.
3394 std::vector<AsmOperandInfo> ConstraintOperands;
3396 SDOperand Chain = getRoot();
3399 std::set<unsigned> OutputRegs, InputRegs;
3401 // Do a prepass over the constraints, canonicalizing them, and building up the
3402 // ConstraintOperands list.
3403 std::vector<InlineAsm::ConstraintInfo>
3404 ConstraintInfos = IA->ParseConstraints();
3406 // SawEarlyClobber - Keep track of whether we saw an earlyclobber output
3407 // constraint. If so, we can't let the register allocator allocate any input
3408 // registers, because it will not know to avoid the earlyclobbered output reg.
3409 bool SawEarlyClobber = false;
3411 unsigned OpNo = 1; // OpNo - The operand of the CallInst.
3412 for (unsigned i = 0, e = ConstraintInfos.size(); i != e; ++i) {
3413 ConstraintOperands.push_back(AsmOperandInfo(ConstraintInfos[i]));
3414 AsmOperandInfo &OpInfo = ConstraintOperands.back();
3416 MVT::ValueType OpVT = MVT::Other;
3418 // Compute the value type for each operand.
3419 switch (OpInfo.Type) {
3420 case InlineAsm::isOutput:
3421 if (!OpInfo.isIndirect) {
3422 // The return value of the call is this value. As such, there is no
3423 // corresponding argument.
3424 assert(I.getType() != Type::VoidTy && "Bad inline asm!");
3425 OpVT = TLI.getValueType(I.getType());
3427 OpInfo.CallOperandVal = I.getOperand(OpNo++);
3430 case InlineAsm::isInput:
3431 OpInfo.CallOperandVal = I.getOperand(OpNo++);
3433 case InlineAsm::isClobber:
3438 // If this is an input or an indirect output, process the call argument.
3439 if (OpInfo.CallOperandVal) {
3440 OpInfo.CallOperand = getValue(OpInfo.CallOperandVal);
3441 const Type *OpTy = OpInfo.CallOperandVal->getType();
3442 // If this is an indirect operand, the operand is a pointer to the
3444 if (OpInfo.isIndirect)
3445 OpTy = cast<PointerType>(OpTy)->getElementType();
3447 // If OpTy is not a first-class value, it may be a struct/union that we
3448 // can tile with integers.
3449 if (!OpTy->isFirstClassType() && OpTy->isSized()) {
3450 unsigned BitSize = TD->getTypeSizeInBits(OpTy);
3458 OpTy = IntegerType::get(BitSize);
3463 OpVT = TLI.getValueType(OpTy, true);
3466 OpInfo.ConstraintVT = OpVT;
3468 // Compute the constraint code and ConstraintType to use.
3469 OpInfo.ComputeConstraintToUse(TLI);
3471 // Keep track of whether we see an earlyclobber.
3472 SawEarlyClobber |= OpInfo.isEarlyClobber;
3474 // If this is a memory input, and if the operand is not indirect, do what we
3475 // need to to provide an address for the memory input.
3476 if (OpInfo.ConstraintType == TargetLowering::C_Memory &&
3477 !OpInfo.isIndirect) {
3478 assert(OpInfo.Type == InlineAsm::isInput &&
3479 "Can only indirectify direct input operands!");
3481 // Memory operands really want the address of the value. If we don't have
3482 // an indirect input, put it in the constpool if we can, otherwise spill
3483 // it to a stack slot.
3485 // If the operand is a float, integer, or vector constant, spill to a
3486 // constant pool entry to get its address.
3487 Value *OpVal = OpInfo.CallOperandVal;
3488 if (isa<ConstantFP>(OpVal) || isa<ConstantInt>(OpVal) ||
3489 isa<ConstantVector>(OpVal)) {
3490 OpInfo.CallOperand = DAG.getConstantPool(cast<Constant>(OpVal),
3491 TLI.getPointerTy());
3493 // Otherwise, create a stack slot and emit a store to it before the
3495 const Type *Ty = OpVal->getType();
3496 uint64_t TySize = TLI.getTargetData()->getTypeSize(Ty);
3497 unsigned Align = TLI.getTargetData()->getPrefTypeAlignment(Ty);
3498 MachineFunction &MF = DAG.getMachineFunction();
3499 int SSFI = MF.getFrameInfo()->CreateStackObject(TySize, Align);
3500 SDOperand StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy());
3501 Chain = DAG.getStore(Chain, OpInfo.CallOperand, StackSlot, NULL, 0);
3502 OpInfo.CallOperand = StackSlot;
3505 // There is no longer a Value* corresponding to this operand.
3506 OpInfo.CallOperandVal = 0;
3507 // It is now an indirect operand.
3508 OpInfo.isIndirect = true;
3511 // If this constraint is for a specific register, allocate it before
3513 if (OpInfo.ConstraintType == TargetLowering::C_Register)
3514 GetRegistersForValue(OpInfo, SawEarlyClobber, OutputRegs, InputRegs);
3516 ConstraintInfos.clear();
3519 // Second pass - Loop over all of the operands, assigning virtual or physregs
3520 // to registerclass operands.
3521 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
3522 AsmOperandInfo &OpInfo = ConstraintOperands[i];
3524 // C_Register operands have already been allocated, Other/Memory don't need
3526 if (OpInfo.ConstraintType == TargetLowering::C_RegisterClass)
3527 GetRegistersForValue(OpInfo, SawEarlyClobber, OutputRegs, InputRegs);
3530 // AsmNodeOperands - The operands for the ISD::INLINEASM node.
3531 std::vector<SDOperand> AsmNodeOperands;
3532 AsmNodeOperands.push_back(SDOperand()); // reserve space for input chain
3533 AsmNodeOperands.push_back(
3534 DAG.getTargetExternalSymbol(IA->getAsmString().c_str(), MVT::Other));
3537 // Loop over all of the inputs, copying the operand values into the
3538 // appropriate registers and processing the output regs.
3539 RegsForValue RetValRegs;
3541 // IndirectStoresToEmit - The set of stores to emit after the inline asm node.
3542 std::vector<std::pair<RegsForValue, Value*> > IndirectStoresToEmit;
3544 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
3545 AsmOperandInfo &OpInfo = ConstraintOperands[i];
3547 switch (OpInfo.Type) {
3548 case InlineAsm::isOutput: {
3549 if (OpInfo.ConstraintType != TargetLowering::C_RegisterClass &&
3550 OpInfo.ConstraintType != TargetLowering::C_Register) {
3551 // Memory output, or 'other' output (e.g. 'X' constraint).
3552 assert(OpInfo.isIndirect && "Memory output must be indirect operand");
3554 // Add information to the INLINEASM node to know about this output.
3555 unsigned ResOpType = 4/*MEM*/ | (1 << 3);
3556 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
3557 TLI.getPointerTy()));
3558 AsmNodeOperands.push_back(OpInfo.CallOperand);
3562 // Otherwise, this is a register or register class output.
3564 // Copy the output from the appropriate register. Find a register that
3566 if (OpInfo.AssignedRegs.Regs.empty()) {
3567 cerr << "Couldn't allocate output reg for contraint '"
3568 << OpInfo.ConstraintCode << "'!\n";
3572 if (!OpInfo.isIndirect) {
3573 // This is the result value of the call.
3574 assert(RetValRegs.Regs.empty() &&
3575 "Cannot have multiple output constraints yet!");
3576 assert(I.getType() != Type::VoidTy && "Bad inline asm!");
3577 RetValRegs = OpInfo.AssignedRegs;
3579 IndirectStoresToEmit.push_back(std::make_pair(OpInfo.AssignedRegs,
3580 OpInfo.CallOperandVal));
3583 // Add information to the INLINEASM node to know that this register is
3585 OpInfo.AssignedRegs.AddInlineAsmOperands(2 /*REGDEF*/, DAG,
3589 case InlineAsm::isInput: {
3590 SDOperand InOperandVal = OpInfo.CallOperand;
3592 if (isdigit(OpInfo.ConstraintCode[0])) { // Matching constraint?
3593 // If this is required to match an output register we have already set,
3594 // just use its register.
3595 unsigned OperandNo = atoi(OpInfo.ConstraintCode.c_str());
3597 // Scan until we find the definition we already emitted of this operand.
3598 // When we find it, create a RegsForValue operand.
3599 unsigned CurOp = 2; // The first operand.
3600 for (; OperandNo; --OperandNo) {
3601 // Advance to the next operand.
3603 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getValue();
3604 assert(((NumOps & 7) == 2 /*REGDEF*/ ||
3605 (NumOps & 7) == 4 /*MEM*/) &&
3606 "Skipped past definitions?");
3607 CurOp += (NumOps>>3)+1;
3611 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getValue();
3612 if ((NumOps & 7) == 2 /*REGDEF*/) {
3613 // Add NumOps>>3 registers to MatchedRegs.
3614 RegsForValue MatchedRegs;
3615 MatchedRegs.ValueVT = InOperandVal.getValueType();
3616 MatchedRegs.RegVT = AsmNodeOperands[CurOp+1].getValueType();
3617 for (unsigned i = 0, e = NumOps>>3; i != e; ++i) {
3619 cast<RegisterSDNode>(AsmNodeOperands[++CurOp])->getReg();
3620 MatchedRegs.Regs.push_back(Reg);
3623 // Use the produced MatchedRegs object to
3624 MatchedRegs.getCopyToRegs(InOperandVal, DAG, Chain, &Flag);
3625 MatchedRegs.AddInlineAsmOperands(1 /*REGUSE*/, DAG, AsmNodeOperands);
3628 assert((NumOps & 7) == 4/*MEM*/ && "Unknown matching constraint!");
3629 assert(0 && "matching constraints for memory operands unimp");
3633 if (OpInfo.ConstraintType == TargetLowering::C_Other) {
3634 assert(!OpInfo.isIndirect &&
3635 "Don't know how to handle indirect other inputs yet!");
3637 std::vector<SDOperand> Ops;
3638 TLI.LowerAsmOperandForConstraint(InOperandVal, OpInfo.ConstraintCode[0],
3641 cerr << "Invalid operand for inline asm constraint '"
3642 << OpInfo.ConstraintCode << "'!\n";
3646 // Add information to the INLINEASM node to know about this input.
3647 unsigned ResOpType = 3 /*IMM*/ | (Ops.size() << 3);
3648 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
3649 TLI.getPointerTy()));
3650 AsmNodeOperands.insert(AsmNodeOperands.end(), Ops.begin(), Ops.end());
3652 } else if (OpInfo.ConstraintType == TargetLowering::C_Memory) {
3653 assert(OpInfo.isIndirect && "Operand must be indirect to be a mem!");
3654 assert(InOperandVal.getValueType() == TLI.getPointerTy() &&
3655 "Memory operands expect pointer values");
3657 // Add information to the INLINEASM node to know about this input.
3658 unsigned ResOpType = 4/*MEM*/ | (1 << 3);
3659 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
3660 TLI.getPointerTy()));
3661 AsmNodeOperands.push_back(InOperandVal);
3665 assert((OpInfo.ConstraintType == TargetLowering::C_RegisterClass ||
3666 OpInfo.ConstraintType == TargetLowering::C_Register) &&
3667 "Unknown constraint type!");
3668 assert(!OpInfo.isIndirect &&
3669 "Don't know how to handle indirect register inputs yet!");
3671 // Copy the input into the appropriate registers.
3672 assert(!OpInfo.AssignedRegs.Regs.empty() &&
3673 "Couldn't allocate input reg!");
3675 OpInfo.AssignedRegs.getCopyToRegs(InOperandVal, DAG, Chain, &Flag);
3677 OpInfo.AssignedRegs.AddInlineAsmOperands(1/*REGUSE*/, DAG,
3681 case InlineAsm::isClobber: {
3682 // Add the clobbered value to the operand list, so that the register
3683 // allocator is aware that the physreg got clobbered.
3684 if (!OpInfo.AssignedRegs.Regs.empty())
3685 OpInfo.AssignedRegs.AddInlineAsmOperands(2/*REGDEF*/, DAG,
3692 // Finish up input operands.
3693 AsmNodeOperands[0] = Chain;
3694 if (Flag.Val) AsmNodeOperands.push_back(Flag);
3696 Chain = DAG.getNode(ISD::INLINEASM,
3697 DAG.getNodeValueTypes(MVT::Other, MVT::Flag), 2,
3698 &AsmNodeOperands[0], AsmNodeOperands.size());
3699 Flag = Chain.getValue(1);
3701 // If this asm returns a register value, copy the result from that register
3702 // and set it as the value of the call.
3703 if (!RetValRegs.Regs.empty()) {
3704 SDOperand Val = RetValRegs.getCopyFromRegs(DAG, Chain, &Flag);
3706 // If the result of the inline asm is a vector, it may have the wrong
3707 // width/num elts. Make sure to convert it to the right type with
3709 if (MVT::isVector(Val.getValueType())) {
3710 const VectorType *VTy = cast<VectorType>(I.getType());
3711 MVT::ValueType DesiredVT = TLI.getValueType(VTy);
3713 Val = DAG.getNode(ISD::BIT_CONVERT, DesiredVT, Val);
3719 std::vector<std::pair<SDOperand, Value*> > StoresToEmit;
3721 // Process indirect outputs, first output all of the flagged copies out of
3723 for (unsigned i = 0, e = IndirectStoresToEmit.size(); i != e; ++i) {
3724 RegsForValue &OutRegs = IndirectStoresToEmit[i].first;
3725 Value *Ptr = IndirectStoresToEmit[i].second;
3726 SDOperand OutVal = OutRegs.getCopyFromRegs(DAG, Chain, &Flag);
3727 StoresToEmit.push_back(std::make_pair(OutVal, Ptr));
3730 // Emit the non-flagged stores from the physregs.
3731 SmallVector<SDOperand, 8> OutChains;
3732 for (unsigned i = 0, e = StoresToEmit.size(); i != e; ++i)
3733 OutChains.push_back(DAG.getStore(Chain, StoresToEmit[i].first,
3734 getValue(StoresToEmit[i].second),
3735 StoresToEmit[i].second, 0));
3736 if (!OutChains.empty())
3737 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other,
3738 &OutChains[0], OutChains.size());
3743 void SelectionDAGLowering::visitMalloc(MallocInst &I) {
3744 SDOperand Src = getValue(I.getOperand(0));
3746 MVT::ValueType IntPtr = TLI.getPointerTy();
3748 if (IntPtr < Src.getValueType())
3749 Src = DAG.getNode(ISD::TRUNCATE, IntPtr, Src);
3750 else if (IntPtr > Src.getValueType())
3751 Src = DAG.getNode(ISD::ZERO_EXTEND, IntPtr, Src);
3753 // Scale the source by the type size.
3754 uint64_t ElementSize = TD->getTypeSize(I.getType()->getElementType());
3755 Src = DAG.getNode(ISD::MUL, Src.getValueType(),
3756 Src, getIntPtrConstant(ElementSize));
3758 TargetLowering::ArgListTy Args;
3759 TargetLowering::ArgListEntry Entry;
3761 Entry.Ty = TLI.getTargetData()->getIntPtrType();
3762 Args.push_back(Entry);
3764 std::pair<SDOperand,SDOperand> Result =
3765 TLI.LowerCallTo(getRoot(), I.getType(), false, false, CallingConv::C, true,
3766 DAG.getExternalSymbol("malloc", IntPtr),
3768 setValue(&I, Result.first); // Pointers always fit in registers
3769 DAG.setRoot(Result.second);
3772 void SelectionDAGLowering::visitFree(FreeInst &I) {
3773 TargetLowering::ArgListTy Args;
3774 TargetLowering::ArgListEntry Entry;
3775 Entry.Node = getValue(I.getOperand(0));
3776 Entry.Ty = TLI.getTargetData()->getIntPtrType();
3777 Args.push_back(Entry);
3778 MVT::ValueType IntPtr = TLI.getPointerTy();
3779 std::pair<SDOperand,SDOperand> Result =
3780 TLI.LowerCallTo(getRoot(), Type::VoidTy, false, false, CallingConv::C, true,
3781 DAG.getExternalSymbol("free", IntPtr), Args, DAG);
3782 DAG.setRoot(Result.second);
3785 // InsertAtEndOfBasicBlock - This method should be implemented by targets that
3786 // mark instructions with the 'usesCustomDAGSchedInserter' flag. These
3787 // instructions are special in various ways, which require special support to
3788 // insert. The specified MachineInstr is created but not inserted into any
3789 // basic blocks, and the scheduler passes ownership of it to this method.
3790 MachineBasicBlock *TargetLowering::InsertAtEndOfBasicBlock(MachineInstr *MI,
3791 MachineBasicBlock *MBB) {
3792 cerr << "If a target marks an instruction with "
3793 << "'usesCustomDAGSchedInserter', it must implement "
3794 << "TargetLowering::InsertAtEndOfBasicBlock!\n";
3799 void SelectionDAGLowering::visitVAStart(CallInst &I) {
3800 DAG.setRoot(DAG.getNode(ISD::VASTART, MVT::Other, getRoot(),
3801 getValue(I.getOperand(1)),
3802 DAG.getSrcValue(I.getOperand(1))));
3805 void SelectionDAGLowering::visitVAArg(VAArgInst &I) {
3806 SDOperand V = DAG.getVAArg(TLI.getValueType(I.getType()), getRoot(),
3807 getValue(I.getOperand(0)),
3808 DAG.getSrcValue(I.getOperand(0)));
3810 DAG.setRoot(V.getValue(1));
3813 void SelectionDAGLowering::visitVAEnd(CallInst &I) {
3814 DAG.setRoot(DAG.getNode(ISD::VAEND, MVT::Other, getRoot(),
3815 getValue(I.getOperand(1)),
3816 DAG.getSrcValue(I.getOperand(1))));
3819 void SelectionDAGLowering::visitVACopy(CallInst &I) {
3820 DAG.setRoot(DAG.getNode(ISD::VACOPY, MVT::Other, getRoot(),
3821 getValue(I.getOperand(1)),
3822 getValue(I.getOperand(2)),
3823 DAG.getSrcValue(I.getOperand(1)),
3824 DAG.getSrcValue(I.getOperand(2))));
3827 /// TargetLowering::LowerArguments - This is the default LowerArguments
3828 /// implementation, which just inserts a FORMAL_ARGUMENTS node. FIXME: When all
3829 /// targets are migrated to using FORMAL_ARGUMENTS, this hook should be
3830 /// integrated into SDISel.
3831 std::vector<SDOperand>
3832 TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
3833 const FunctionType *FTy = F.getFunctionType();
3834 const ParamAttrsList *Attrs = FTy->getParamAttrs();
3835 // Add CC# and isVararg as operands to the FORMAL_ARGUMENTS node.
3836 std::vector<SDOperand> Ops;
3837 Ops.push_back(DAG.getRoot());
3838 Ops.push_back(DAG.getConstant(F.getCallingConv(), getPointerTy()));
3839 Ops.push_back(DAG.getConstant(F.isVarArg(), getPointerTy()));
3841 // Add one result value for each formal argument.
3842 std::vector<MVT::ValueType> RetVals;
3844 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end();
3846 MVT::ValueType VT = getValueType(I->getType());
3847 unsigned Flags = ISD::ParamFlags::NoFlagSet;
3848 unsigned OriginalAlignment =
3849 getTargetData()->getABITypeAlignment(I->getType());
3851 // FIXME: Distinguish between a formal with no [sz]ext attribute from one
3852 // that is zero extended!
3853 if (Attrs && Attrs->paramHasAttr(j, ParamAttr::ZExt))
3854 Flags &= ~(ISD::ParamFlags::SExt);
3855 if (Attrs && Attrs->paramHasAttr(j, ParamAttr::SExt))
3856 Flags |= ISD::ParamFlags::SExt;
3857 if (Attrs && Attrs->paramHasAttr(j, ParamAttr::InReg))
3858 Flags |= ISD::ParamFlags::InReg;
3859 if (Attrs && Attrs->paramHasAttr(j, ParamAttr::StructRet))
3860 Flags |= ISD::ParamFlags::StructReturn;
3861 if (Attrs && Attrs->paramHasAttr(j, ParamAttr::ByVal)) {
3862 Flags |= ISD::ParamFlags::ByVal;
3863 const PointerType *Ty = cast<PointerType>(I->getType());
3864 const StructType *STy = cast<StructType>(Ty->getElementType());
3865 unsigned StructAlign = Log2_32(getTargetData()->getABITypeAlignment(STy));
3866 unsigned StructSize = getTargetData()->getTypeSize(STy);
3867 Flags |= (StructAlign << ISD::ParamFlags::ByValAlignOffs);
3868 Flags |= (StructSize << ISD::ParamFlags::ByValSizeOffs);
3870 if (Attrs && Attrs->paramHasAttr(j, ParamAttr::Nest))
3871 Flags |= ISD::ParamFlags::Nest;
3872 Flags |= (OriginalAlignment << ISD::ParamFlags::OrigAlignmentOffs);
3874 switch (getTypeAction(VT)) {
3875 default: assert(0 && "Unknown type action!");
3877 RetVals.push_back(VT);
3878 Ops.push_back(DAG.getConstant(Flags, MVT::i32));
3881 RetVals.push_back(getTypeToTransformTo(VT));
3882 Ops.push_back(DAG.getConstant(Flags, MVT::i32));
3885 // If this is an illegal type, it needs to be broken up to fit into
3887 MVT::ValueType RegisterVT = getRegisterType(VT);
3888 unsigned NumRegs = getNumRegisters(VT);
3889 for (unsigned i = 0; i != NumRegs; ++i) {
3890 RetVals.push_back(RegisterVT);
3891 // if it isn't first piece, alignment must be 1
3893 Flags = (Flags & (~ISD::ParamFlags::OrigAlignment)) |
3894 (1 << ISD::ParamFlags::OrigAlignmentOffs);
3895 Ops.push_back(DAG.getConstant(Flags, MVT::i32));
3902 RetVals.push_back(MVT::Other);
3905 SDNode *Result = DAG.getNode(ISD::FORMAL_ARGUMENTS,
3906 DAG.getNodeValueTypes(RetVals), RetVals.size(),
3907 &Ops[0], Ops.size()).Val;
3908 unsigned NumArgRegs = Result->getNumValues() - 1;
3909 DAG.setRoot(SDOperand(Result, NumArgRegs));
3911 // Set up the return result vector.
3915 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E;
3917 MVT::ValueType VT = getValueType(I->getType());
3919 switch (getTypeAction(VT)) {
3920 default: assert(0 && "Unknown type action!");
3922 Ops.push_back(SDOperand(Result, i++));
3925 SDOperand Op(Result, i++);
3926 if (MVT::isInteger(VT)) {
3927 if (Attrs && Attrs->paramHasAttr(Idx, ParamAttr::SExt))
3928 Op = DAG.getNode(ISD::AssertSext, Op.getValueType(), Op,
3929 DAG.getValueType(VT));
3930 else if (Attrs && Attrs->paramHasAttr(Idx, ParamAttr::ZExt))
3931 Op = DAG.getNode(ISD::AssertZext, Op.getValueType(), Op,
3932 DAG.getValueType(VT));
3933 Op = DAG.getNode(ISD::TRUNCATE, VT, Op);
3935 assert(MVT::isFloatingPoint(VT) && "Not int or FP?");
3936 Op = DAG.getNode(ISD::FP_ROUND, VT, Op);
3942 MVT::ValueType PartVT = getRegisterType(VT);
3943 unsigned NumParts = getNumRegisters(VT);
3944 SmallVector<SDOperand, 4> Parts(NumParts);
3945 for (unsigned j = 0; j != NumParts; ++j)
3946 Parts[j] = SDOperand(Result, i++);
3947 Ops.push_back(getCopyFromParts(DAG, &Parts[0], NumParts, PartVT, VT));
3952 assert(i == NumArgRegs && "Argument register count mismatch!");
3957 /// TargetLowering::LowerCallTo - This is the default LowerCallTo
3958 /// implementation, which just inserts an ISD::CALL node, which is later custom
3959 /// lowered by the target to something concrete. FIXME: When all targets are
3960 /// migrated to using ISD::CALL, this hook should be integrated into SDISel.
3961 std::pair<SDOperand, SDOperand>
3962 TargetLowering::LowerCallTo(SDOperand Chain, const Type *RetTy,
3963 bool RetTyIsSigned, bool isVarArg,
3964 unsigned CallingConv, bool isTailCall,
3966 ArgListTy &Args, SelectionDAG &DAG) {
3967 SmallVector<SDOperand, 32> Ops;
3968 Ops.push_back(Chain); // Op#0 - Chain
3969 Ops.push_back(DAG.getConstant(CallingConv, getPointerTy())); // Op#1 - CC
3970 Ops.push_back(DAG.getConstant(isVarArg, getPointerTy())); // Op#2 - VarArg
3971 Ops.push_back(DAG.getConstant(isTailCall, getPointerTy())); // Op#3 - Tail
3972 Ops.push_back(Callee);
3974 // Handle all of the outgoing arguments.
3975 for (unsigned i = 0, e = Args.size(); i != e; ++i) {
3976 MVT::ValueType VT = getValueType(Args[i].Ty);
3977 SDOperand Op = Args[i].Node;
3978 unsigned Flags = ISD::ParamFlags::NoFlagSet;
3979 unsigned OriginalAlignment =
3980 getTargetData()->getABITypeAlignment(Args[i].Ty);
3983 Flags |= ISD::ParamFlags::SExt;
3985 Flags |= ISD::ParamFlags::ZExt;
3986 if (Args[i].isInReg)
3987 Flags |= ISD::ParamFlags::InReg;
3989 Flags |= ISD::ParamFlags::StructReturn;
3990 if (Args[i].isByVal) {
3991 Flags |= ISD::ParamFlags::ByVal;
3992 const PointerType *Ty = cast<PointerType>(Args[i].Ty);
3993 const StructType *STy = cast<StructType>(Ty->getElementType());
3994 unsigned StructAlign = Log2_32(getTargetData()->getABITypeAlignment(STy));
3995 unsigned StructSize = getTargetData()->getTypeSize(STy);
3996 Flags |= (StructAlign << ISD::ParamFlags::ByValAlignOffs);
3997 Flags |= (StructSize << ISD::ParamFlags::ByValSizeOffs);
4000 Flags |= ISD::ParamFlags::Nest;
4001 Flags |= OriginalAlignment << ISD::ParamFlags::OrigAlignmentOffs;
4003 switch (getTypeAction(VT)) {
4004 default: assert(0 && "Unknown type action!");
4007 Ops.push_back(DAG.getConstant(Flags, MVT::i32));
4010 if (MVT::isInteger(VT)) {
4013 ExtOp = ISD::SIGN_EXTEND;
4014 else if (Args[i].isZExt)
4015 ExtOp = ISD::ZERO_EXTEND;
4017 ExtOp = ISD::ANY_EXTEND;
4018 Op = DAG.getNode(ExtOp, getTypeToTransformTo(VT), Op);
4020 assert(MVT::isFloatingPoint(VT) && "Not int or FP?");
4021 Op = DAG.getNode(ISD::FP_EXTEND, getTypeToTransformTo(VT), Op);
4024 Ops.push_back(DAG.getConstant(Flags, MVT::i32));
4027 MVT::ValueType PartVT = getRegisterType(VT);
4028 unsigned NumParts = getNumRegisters(VT);
4029 SmallVector<SDOperand, 4> Parts(NumParts);
4030 getCopyToParts(DAG, Op, &Parts[0], NumParts, PartVT);
4031 for (unsigned i = 0; i != NumParts; ++i) {
4032 // if it isn't first piece, alignment must be 1
4033 unsigned MyFlags = Flags;
4035 MyFlags = (MyFlags & (~ISD::ParamFlags::OrigAlignment)) |
4036 (1 << ISD::ParamFlags::OrigAlignmentOffs);
4038 Ops.push_back(Parts[i]);
4039 Ops.push_back(DAG.getConstant(MyFlags, MVT::i32));
4046 // Figure out the result value types.
4047 MVT::ValueType VT = getValueType(RetTy);
4048 MVT::ValueType RegisterVT = getRegisterType(VT);
4049 unsigned NumRegs = getNumRegisters(VT);
4050 SmallVector<MVT::ValueType, 4> RetTys(NumRegs);
4051 for (unsigned i = 0; i != NumRegs; ++i)
4052 RetTys[i] = RegisterVT;
4054 RetTys.push_back(MVT::Other); // Always has a chain.
4056 // Create the CALL node.
4057 SDOperand Res = DAG.getNode(ISD::CALL,
4058 DAG.getVTList(&RetTys[0], NumRegs + 1),
4059 &Ops[0], Ops.size());
4060 Chain = Res.getValue(NumRegs);
4062 // Gather up the call result into a single value.
4063 if (RetTy != Type::VoidTy) {
4064 ISD::NodeType AssertOp = ISD::AssertSext;
4066 AssertOp = ISD::AssertZext;
4067 SmallVector<SDOperand, 4> Results(NumRegs);
4068 for (unsigned i = 0; i != NumRegs; ++i)
4069 Results[i] = Res.getValue(i);
4070 Res = getCopyFromParts(DAG, &Results[0], NumRegs, RegisterVT, VT, AssertOp);
4073 return std::make_pair(Res, Chain);
4076 SDOperand TargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
4077 assert(0 && "LowerOperation not implemented for this target!");
4082 SDOperand TargetLowering::CustomPromoteOperation(SDOperand Op,
4083 SelectionDAG &DAG) {
4084 assert(0 && "CustomPromoteOperation not implemented for this target!");
4089 /// getMemsetValue - Vectorized representation of the memset value
4091 static SDOperand getMemsetValue(SDOperand Value, MVT::ValueType VT,
4092 SelectionDAG &DAG) {
4093 MVT::ValueType CurVT = VT;
4094 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Value)) {
4095 uint64_t Val = C->getValue() & 255;
4097 while (CurVT != MVT::i8) {
4098 Val = (Val << Shift) | Val;
4100 CurVT = (MVT::ValueType)((unsigned)CurVT - 1);
4102 return DAG.getConstant(Val, VT);
4104 Value = DAG.getNode(ISD::ZERO_EXTEND, VT, Value);
4106 while (CurVT != MVT::i8) {
4108 DAG.getNode(ISD::OR, VT,
4109 DAG.getNode(ISD::SHL, VT, Value,
4110 DAG.getConstant(Shift, MVT::i8)), Value);
4112 CurVT = (MVT::ValueType)((unsigned)CurVT - 1);
4119 /// getMemsetStringVal - Similar to getMemsetValue. Except this is only
4120 /// used when a memcpy is turned into a memset when the source is a constant
4122 static SDOperand getMemsetStringVal(MVT::ValueType VT,
4123 SelectionDAG &DAG, TargetLowering &TLI,
4124 std::string &Str, unsigned Offset) {
4126 unsigned MSB = MVT::getSizeInBits(VT) / 8;
4127 if (TLI.isLittleEndian())
4128 Offset = Offset + MSB - 1;
4129 for (unsigned i = 0; i != MSB; ++i) {
4130 Val = (Val << 8) | (unsigned char)Str[Offset];
4131 Offset += TLI.isLittleEndian() ? -1 : 1;
4133 return DAG.getConstant(Val, VT);
4136 /// getMemBasePlusOffset - Returns base and offset node for the
4137 static SDOperand getMemBasePlusOffset(SDOperand Base, unsigned Offset,
4138 SelectionDAG &DAG, TargetLowering &TLI) {
4139 MVT::ValueType VT = Base.getValueType();
4140 return DAG.getNode(ISD::ADD, VT, Base, DAG.getConstant(Offset, VT));
4143 /// MeetsMaxMemopRequirement - Determines if the number of memory ops required
4144 /// to replace the memset / memcpy is below the threshold. It also returns the
4145 /// types of the sequence of memory ops to perform memset / memcpy.
4146 static bool MeetsMaxMemopRequirement(std::vector<MVT::ValueType> &MemOps,
4147 unsigned Limit, uint64_t Size,
4148 unsigned Align, TargetLowering &TLI) {
4151 if (TLI.allowsUnalignedMemoryAccesses()) {
4154 switch (Align & 7) {
4170 MVT::ValueType LVT = MVT::i64;
4171 while (!TLI.isTypeLegal(LVT))
4172 LVT = (MVT::ValueType)((unsigned)LVT - 1);
4173 assert(MVT::isInteger(LVT));
4178 unsigned NumMemOps = 0;
4180 unsigned VTSize = MVT::getSizeInBits(VT) / 8;
4181 while (VTSize > Size) {
4182 VT = (MVT::ValueType)((unsigned)VT - 1);
4185 assert(MVT::isInteger(VT));
4187 if (++NumMemOps > Limit)
4189 MemOps.push_back(VT);
4196 void SelectionDAGLowering::visitMemIntrinsic(CallInst &I, unsigned Op) {
4197 SDOperand Op1 = getValue(I.getOperand(1));
4198 SDOperand Op2 = getValue(I.getOperand(2));
4199 SDOperand Op3 = getValue(I.getOperand(3));
4200 SDOperand Op4 = getValue(I.getOperand(4));
4201 unsigned Align = (unsigned)cast<ConstantSDNode>(Op4)->getValue();
4202 if (Align == 0) Align = 1;
4204 // If the source and destination are known to not be aliases, we can
4205 // lower memmove as memcpy.
4206 if (Op == ISD::MEMMOVE) {
4208 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op3))
4209 Size = C->getValue();
4210 if (AA.alias(I.getOperand(1), Size, I.getOperand(2), Size) ==
4211 AliasAnalysis::NoAlias)
4215 if (ConstantSDNode *Size = dyn_cast<ConstantSDNode>(Op3)) {
4216 std::vector<MVT::ValueType> MemOps;
4218 // Expand memset / memcpy to a series of load / store ops
4219 // if the size operand falls below a certain threshold.
4220 SmallVector<SDOperand, 8> OutChains;
4222 default: break; // Do nothing for now.
4224 if (MeetsMaxMemopRequirement(MemOps, TLI.getMaxStoresPerMemset(),
4225 Size->getValue(), Align, TLI)) {
4226 unsigned NumMemOps = MemOps.size();
4227 unsigned Offset = 0;
4228 for (unsigned i = 0; i < NumMemOps; i++) {
4229 MVT::ValueType VT = MemOps[i];
4230 unsigned VTSize = MVT::getSizeInBits(VT) / 8;
4231 SDOperand Value = getMemsetValue(Op2, VT, DAG);
4232 SDOperand Store = DAG.getStore(getRoot(), Value,
4233 getMemBasePlusOffset(Op1, Offset, DAG, TLI),
4234 I.getOperand(1), Offset);
4235 OutChains.push_back(Store);
4242 if (MeetsMaxMemopRequirement(MemOps, TLI.getMaxStoresPerMemcpy(),
4243 Size->getValue(), Align, TLI)) {
4244 unsigned NumMemOps = MemOps.size();
4245 unsigned SrcOff = 0, DstOff = 0, SrcDelta = 0;
4246 GlobalAddressSDNode *G = NULL;
4248 bool CopyFromStr = false;
4250 if (Op2.getOpcode() == ISD::GlobalAddress)
4251 G = cast<GlobalAddressSDNode>(Op2);
4252 else if (Op2.getOpcode() == ISD::ADD &&
4253 Op2.getOperand(0).getOpcode() == ISD::GlobalAddress &&
4254 Op2.getOperand(1).getOpcode() == ISD::Constant) {
4255 G = cast<GlobalAddressSDNode>(Op2.getOperand(0));
4256 SrcDelta = cast<ConstantSDNode>(Op2.getOperand(1))->getValue();
4259 GlobalVariable *GV = dyn_cast<GlobalVariable>(G->getGlobal());
4260 if (GV && GV->isConstant()) {
4261 Str = GV->getStringValue(false);
4269 for (unsigned i = 0; i < NumMemOps; i++) {
4270 MVT::ValueType VT = MemOps[i];
4271 unsigned VTSize = MVT::getSizeInBits(VT) / 8;
4272 SDOperand Value, Chain, Store;
4275 Value = getMemsetStringVal(VT, DAG, TLI, Str, SrcOff);
4278 DAG.getStore(Chain, Value,
4279 getMemBasePlusOffset(Op1, DstOff, DAG, TLI),
4280 I.getOperand(1), DstOff);
4282 Value = DAG.getLoad(VT, getRoot(),
4283 getMemBasePlusOffset(Op2, SrcOff, DAG, TLI),
4284 I.getOperand(2), SrcOff);
4285 Chain = Value.getValue(1);
4287 DAG.getStore(Chain, Value,
4288 getMemBasePlusOffset(Op1, DstOff, DAG, TLI),
4289 I.getOperand(1), DstOff);
4291 OutChains.push_back(Store);
4300 if (!OutChains.empty()) {
4301 DAG.setRoot(DAG.getNode(ISD::TokenFactor, MVT::Other,
4302 &OutChains[0], OutChains.size()));
4307 DAG.setRoot(DAG.getNode(Op, MVT::Other, getRoot(), Op1, Op2, Op3, Op4));
4310 //===----------------------------------------------------------------------===//
4311 // SelectionDAGISel code
4312 //===----------------------------------------------------------------------===//
4314 unsigned SelectionDAGISel::MakeReg(MVT::ValueType VT) {
4315 return RegMap->createVirtualRegister(TLI.getRegClassFor(VT));
4318 void SelectionDAGISel::getAnalysisUsage(AnalysisUsage &AU) const {
4319 AU.addRequired<AliasAnalysis>();
4320 AU.setPreservesAll();
4325 bool SelectionDAGISel::runOnFunction(Function &Fn) {
4326 // Get alias analysis for load/store combining.
4327 AA = &getAnalysis<AliasAnalysis>();
4329 MachineFunction &MF = MachineFunction::construct(&Fn, TLI.getTargetMachine());
4330 RegMap = MF.getSSARegMap();
4331 DOUT << "\n\n\n=== " << Fn.getName() << "\n";
4333 FunctionLoweringInfo FuncInfo(TLI, Fn, MF);
4335 if (ExceptionHandling)
4336 for (Function::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I)
4337 if (InvokeInst *Invoke = dyn_cast<InvokeInst>(I->getTerminator()))
4338 // Mark landing pad.
4339 FuncInfo.MBBMap[Invoke->getSuccessor(1)]->setIsLandingPad();
4341 for (Function::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I)
4342 SelectBasicBlock(I, MF, FuncInfo);
4344 // Add function live-ins to entry block live-in set.
4345 BasicBlock *EntryBB = &Fn.getEntryBlock();
4346 BB = FuncInfo.MBBMap[EntryBB];
4347 if (!MF.livein_empty())
4348 for (MachineFunction::livein_iterator I = MF.livein_begin(),
4349 E = MF.livein_end(); I != E; ++I)
4350 BB->addLiveIn(I->first);
4353 assert(FuncInfo.CatchInfoFound.size() == FuncInfo.CatchInfoLost.size() &&
4354 "Not all catch info was assigned to a landing pad!");
4360 SDOperand SelectionDAGLowering::CopyValueToVirtualRegister(Value *V,
4362 SDOperand Op = getValue(V);
4363 assert((Op.getOpcode() != ISD::CopyFromReg ||
4364 cast<RegisterSDNode>(Op.getOperand(1))->getReg() != Reg) &&
4365 "Copy from a reg to the same reg!");
4367 MVT::ValueType SrcVT = Op.getValueType();
4368 MVT::ValueType RegisterVT = TLI.getRegisterType(SrcVT);
4369 unsigned NumRegs = TLI.getNumRegisters(SrcVT);
4370 SmallVector<SDOperand, 8> Regs(NumRegs);
4371 SmallVector<SDOperand, 8> Chains(NumRegs);
4373 // Copy the value by legal parts into sequential virtual registers.
4374 getCopyToParts(DAG, Op, &Regs[0], NumRegs, RegisterVT);
4375 for (unsigned i = 0; i != NumRegs; ++i)
4376 Chains[i] = DAG.getCopyToReg(getRoot(), Reg + i, Regs[i]);
4377 return DAG.getNode(ISD::TokenFactor, MVT::Other, &Chains[0], NumRegs);
4380 void SelectionDAGISel::
4381 LowerArguments(BasicBlock *LLVMBB, SelectionDAGLowering &SDL,
4382 std::vector<SDOperand> &UnorderedChains) {
4383 // If this is the entry block, emit arguments.
4384 Function &F = *LLVMBB->getParent();
4385 FunctionLoweringInfo &FuncInfo = SDL.FuncInfo;
4386 SDOperand OldRoot = SDL.DAG.getRoot();
4387 std::vector<SDOperand> Args = TLI.LowerArguments(F, SDL.DAG);
4390 for (Function::arg_iterator AI = F.arg_begin(), E = F.arg_end();
4392 if (!AI->use_empty()) {
4393 SDL.setValue(AI, Args[a]);
4395 // If this argument is live outside of the entry block, insert a copy from
4396 // whereever we got it to the vreg that other BB's will reference it as.
4397 DenseMap<const Value*, unsigned>::iterator VMI=FuncInfo.ValueMap.find(AI);
4398 if (VMI != FuncInfo.ValueMap.end()) {
4399 SDOperand Copy = SDL.CopyValueToVirtualRegister(AI, VMI->second);
4400 UnorderedChains.push_back(Copy);
4404 // Finally, if the target has anything special to do, allow it to do so.
4405 // FIXME: this should insert code into the DAG!
4406 EmitFunctionEntryCode(F, SDL.DAG.getMachineFunction());
4409 static void copyCatchInfo(BasicBlock *SrcBB, BasicBlock *DestBB,
4410 MachineModuleInfo *MMI, FunctionLoweringInfo &FLI) {
4411 assert(!FLI.MBBMap[SrcBB]->isLandingPad() &&
4412 "Copying catch info out of a landing pad!");
4413 for (BasicBlock::iterator I = SrcBB->begin(), E = --SrcBB->end(); I != E; ++I)
4414 if (isSelector(I)) {
4415 // Apply the catch info to DestBB.
4416 addCatchInfo(cast<CallInst>(*I), MMI, FLI.MBBMap[DestBB]);
4418 FLI.CatchInfoFound.insert(I);
4423 void SelectionDAGISel::BuildSelectionDAG(SelectionDAG &DAG, BasicBlock *LLVMBB,
4424 std::vector<std::pair<MachineInstr*, unsigned> > &PHINodesToUpdate,
4425 FunctionLoweringInfo &FuncInfo) {
4426 SelectionDAGLowering SDL(DAG, TLI, *AA, FuncInfo);
4428 std::vector<SDOperand> UnorderedChains;
4430 // Lower any arguments needed in this block if this is the entry block.
4431 if (LLVMBB == &LLVMBB->getParent()->getEntryBlock())
4432 LowerArguments(LLVMBB, SDL, UnorderedChains);
4434 BB = FuncInfo.MBBMap[LLVMBB];
4435 SDL.setCurrentBasicBlock(BB);
4437 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
4439 if (ExceptionHandling && MMI && BB->isLandingPad()) {
4440 // Add a label to mark the beginning of the landing pad. Deletion of the
4441 // landing pad can thus be detected via the MachineModuleInfo.
4442 unsigned LabelID = MMI->addLandingPad(BB);
4443 DAG.setRoot(DAG.getNode(ISD::LABEL, MVT::Other, DAG.getEntryNode(),
4444 DAG.getConstant(LabelID, MVT::i32)));
4446 // Mark exception register as live in.
4447 unsigned Reg = TLI.getExceptionAddressRegister();
4448 if (Reg) BB->addLiveIn(Reg);
4450 // Mark exception selector register as live in.
4451 Reg = TLI.getExceptionSelectorRegister();
4452 if (Reg) BB->addLiveIn(Reg);
4454 // FIXME: Hack around an exception handling flaw (PR1508): the personality
4455 // function and list of typeids logically belong to the invoke (or, if you
4456 // like, the basic block containing the invoke), and need to be associated
4457 // with it in the dwarf exception handling tables. Currently however the
4458 // information is provided by an intrinsic (eh.selector) that can be moved
4459 // to unexpected places by the optimizers: if the unwind edge is critical,
4460 // then breaking it can result in the intrinsics being in the successor of
4461 // the landing pad, not the landing pad itself. This results in exceptions
4462 // not being caught because no typeids are associated with the invoke.
4463 // This may not be the only way things can go wrong, but it is the only way
4464 // we try to work around for the moment.
4465 BranchInst *Br = dyn_cast<BranchInst>(LLVMBB->getTerminator());
4467 if (Br && Br->isUnconditional()) { // Critical edge?
4468 BasicBlock::iterator I, E;
4469 for (I = LLVMBB->begin(), E = --LLVMBB->end(); I != E; ++I)
4474 // No catch info found - try to extract some from the successor.
4475 copyCatchInfo(Br->getSuccessor(0), LLVMBB, MMI, FuncInfo);
4479 // Lower all of the non-terminator instructions.
4480 for (BasicBlock::iterator I = LLVMBB->begin(), E = --LLVMBB->end();
4484 // Ensure that all instructions which are used outside of their defining
4485 // blocks are available as virtual registers. Invoke is handled elsewhere.
4486 for (BasicBlock::iterator I = LLVMBB->begin(), E = LLVMBB->end(); I != E;++I)
4487 if (!I->use_empty() && !isa<PHINode>(I) && !isa<InvokeInst>(I)) {
4488 DenseMap<const Value*, unsigned>::iterator VMI =FuncInfo.ValueMap.find(I);
4489 if (VMI != FuncInfo.ValueMap.end())
4490 UnorderedChains.push_back(
4491 SDL.CopyValueToVirtualRegister(I, VMI->second));
4494 // Handle PHI nodes in successor blocks. Emit code into the SelectionDAG to
4495 // ensure constants are generated when needed. Remember the virtual registers
4496 // that need to be added to the Machine PHI nodes as input. We cannot just
4497 // directly add them, because expansion might result in multiple MBB's for one
4498 // BB. As such, the start of the BB might correspond to a different MBB than
4501 TerminatorInst *TI = LLVMBB->getTerminator();
4503 // Emit constants only once even if used by multiple PHI nodes.
4504 std::map<Constant*, unsigned> ConstantsOut;
4506 // Vector bool would be better, but vector<bool> is really slow.
4507 std::vector<unsigned char> SuccsHandled;
4508 if (TI->getNumSuccessors())
4509 SuccsHandled.resize(BB->getParent()->getNumBlockIDs());
4511 // Check successor nodes' PHI nodes that expect a constant to be available
4513 for (unsigned succ = 0, e = TI->getNumSuccessors(); succ != e; ++succ) {
4514 BasicBlock *SuccBB = TI->getSuccessor(succ);
4515 if (!isa<PHINode>(SuccBB->begin())) continue;
4516 MachineBasicBlock *SuccMBB = FuncInfo.MBBMap[SuccBB];
4518 // If this terminator has multiple identical successors (common for
4519 // switches), only handle each succ once.
4520 unsigned SuccMBBNo = SuccMBB->getNumber();
4521 if (SuccsHandled[SuccMBBNo]) continue;
4522 SuccsHandled[SuccMBBNo] = true;
4524 MachineBasicBlock::iterator MBBI = SuccMBB->begin();
4527 // At this point we know that there is a 1-1 correspondence between LLVM PHI
4528 // nodes and Machine PHI nodes, but the incoming operands have not been
4530 for (BasicBlock::iterator I = SuccBB->begin();
4531 (PN = dyn_cast<PHINode>(I)); ++I) {
4532 // Ignore dead phi's.
4533 if (PN->use_empty()) continue;
4536 Value *PHIOp = PN->getIncomingValueForBlock(LLVMBB);
4538 if (Constant *C = dyn_cast<Constant>(PHIOp)) {
4539 unsigned &RegOut = ConstantsOut[C];
4541 RegOut = FuncInfo.CreateRegForValue(C);
4542 UnorderedChains.push_back(
4543 SDL.CopyValueToVirtualRegister(C, RegOut));
4547 Reg = FuncInfo.ValueMap[PHIOp];
4549 assert(isa<AllocaInst>(PHIOp) &&
4550 FuncInfo.StaticAllocaMap.count(cast<AllocaInst>(PHIOp)) &&
4551 "Didn't codegen value into a register!??");
4552 Reg = FuncInfo.CreateRegForValue(PHIOp);
4553 UnorderedChains.push_back(
4554 SDL.CopyValueToVirtualRegister(PHIOp, Reg));
4558 // Remember that this register needs to added to the machine PHI node as
4559 // the input for this MBB.
4560 MVT::ValueType VT = TLI.getValueType(PN->getType());
4561 unsigned NumRegisters = TLI.getNumRegisters(VT);
4562 for (unsigned i = 0, e = NumRegisters; i != e; ++i)
4563 PHINodesToUpdate.push_back(std::make_pair(MBBI++, Reg+i));
4566 ConstantsOut.clear();
4568 // Turn all of the unordered chains into one factored node.
4569 if (!UnorderedChains.empty()) {
4570 SDOperand Root = SDL.getRoot();
4571 if (Root.getOpcode() != ISD::EntryToken) {
4572 unsigned i = 0, e = UnorderedChains.size();
4573 for (; i != e; ++i) {
4574 assert(UnorderedChains[i].Val->getNumOperands() > 1);
4575 if (UnorderedChains[i].Val->getOperand(0) == Root)
4576 break; // Don't add the root if we already indirectly depend on it.
4580 UnorderedChains.push_back(Root);
4582 DAG.setRoot(DAG.getNode(ISD::TokenFactor, MVT::Other,
4583 &UnorderedChains[0], UnorderedChains.size()));
4586 // Lower the terminator after the copies are emitted.
4587 SDL.visit(*LLVMBB->getTerminator());
4589 // Copy over any CaseBlock records that may now exist due to SwitchInst
4590 // lowering, as well as any jump table information.
4591 SwitchCases.clear();
4592 SwitchCases = SDL.SwitchCases;
4594 JTCases = SDL.JTCases;
4595 BitTestCases.clear();
4596 BitTestCases = SDL.BitTestCases;
4598 // Make sure the root of the DAG is up-to-date.
4599 DAG.setRoot(SDL.getRoot());
4602 void SelectionDAGISel::CodeGenAndEmitDAG(SelectionDAG &DAG) {
4603 // Run the DAG combiner in pre-legalize mode.
4604 DAG.Combine(false, *AA);
4606 DOUT << "Lowered selection DAG:\n";
4609 // Second step, hack on the DAG until it only uses operations and types that
4610 // the target supports.
4613 DOUT << "Legalized selection DAG:\n";
4616 // Run the DAG combiner in post-legalize mode.
4617 DAG.Combine(true, *AA);
4619 if (ViewISelDAGs) DAG.viewGraph();
4621 // Third, instruction select all of the operations to machine code, adding the
4622 // code to the MachineBasicBlock.
4623 InstructionSelectBasicBlock(DAG);
4625 DOUT << "Selected machine code:\n";
4629 void SelectionDAGISel::SelectBasicBlock(BasicBlock *LLVMBB, MachineFunction &MF,
4630 FunctionLoweringInfo &FuncInfo) {
4631 std::vector<std::pair<MachineInstr*, unsigned> > PHINodesToUpdate;
4633 SelectionDAG DAG(TLI, MF, getAnalysisToUpdate<MachineModuleInfo>());
4636 // First step, lower LLVM code to some DAG. This DAG may use operations and
4637 // types that are not supported by the target.
4638 BuildSelectionDAG(DAG, LLVMBB, PHINodesToUpdate, FuncInfo);
4640 // Second step, emit the lowered DAG as machine code.
4641 CodeGenAndEmitDAG(DAG);
4644 DOUT << "Total amount of phi nodes to update: "
4645 << PHINodesToUpdate.size() << "\n";
4646 DEBUG(for (unsigned i = 0, e = PHINodesToUpdate.size(); i != e; ++i)
4647 DOUT << "Node " << i << " : (" << PHINodesToUpdate[i].first
4648 << ", " << PHINodesToUpdate[i].second << ")\n";);
4650 // Next, now that we know what the last MBB the LLVM BB expanded is, update
4651 // PHI nodes in successors.
4652 if (SwitchCases.empty() && JTCases.empty() && BitTestCases.empty()) {
4653 for (unsigned i = 0, e = PHINodesToUpdate.size(); i != e; ++i) {
4654 MachineInstr *PHI = PHINodesToUpdate[i].first;
4655 assert(PHI->getOpcode() == TargetInstrInfo::PHI &&
4656 "This is not a machine PHI node that we are updating!");
4657 PHI->addRegOperand(PHINodesToUpdate[i].second, false);
4658 PHI->addMachineBasicBlockOperand(BB);
4663 for (unsigned i = 0, e = BitTestCases.size(); i != e; ++i) {
4664 // Lower header first, if it wasn't already lowered
4665 if (!BitTestCases[i].Emitted) {
4666 SelectionDAG HSDAG(TLI, MF, getAnalysisToUpdate<MachineModuleInfo>());
4668 SelectionDAGLowering HSDL(HSDAG, TLI, *AA, FuncInfo);
4669 // Set the current basic block to the mbb we wish to insert the code into
4670 BB = BitTestCases[i].Parent;
4671 HSDL.setCurrentBasicBlock(BB);
4673 HSDL.visitBitTestHeader(BitTestCases[i]);
4674 HSDAG.setRoot(HSDL.getRoot());
4675 CodeGenAndEmitDAG(HSDAG);
4678 for (unsigned j = 0, ej = BitTestCases[i].Cases.size(); j != ej; ++j) {
4679 SelectionDAG BSDAG(TLI, MF, getAnalysisToUpdate<MachineModuleInfo>());
4681 SelectionDAGLowering BSDL(BSDAG, TLI, *AA, FuncInfo);
4682 // Set the current basic block to the mbb we wish to insert the code into
4683 BB = BitTestCases[i].Cases[j].ThisBB;
4684 BSDL.setCurrentBasicBlock(BB);
4687 BSDL.visitBitTestCase(BitTestCases[i].Cases[j+1].ThisBB,
4688 BitTestCases[i].Reg,
4689 BitTestCases[i].Cases[j]);
4691 BSDL.visitBitTestCase(BitTestCases[i].Default,
4692 BitTestCases[i].Reg,
4693 BitTestCases[i].Cases[j]);
4696 BSDAG.setRoot(BSDL.getRoot());
4697 CodeGenAndEmitDAG(BSDAG);
4701 for (unsigned pi = 0, pe = PHINodesToUpdate.size(); pi != pe; ++pi) {
4702 MachineInstr *PHI = PHINodesToUpdate[pi].first;
4703 MachineBasicBlock *PHIBB = PHI->getParent();
4704 assert(PHI->getOpcode() == TargetInstrInfo::PHI &&
4705 "This is not a machine PHI node that we are updating!");
4706 // This is "default" BB. We have two jumps to it. From "header" BB and
4707 // from last "case" BB.
4708 if (PHIBB == BitTestCases[i].Default) {
4709 PHI->addRegOperand(PHINodesToUpdate[pi].second, false);
4710 PHI->addMachineBasicBlockOperand(BitTestCases[i].Parent);
4711 PHI->addRegOperand(PHINodesToUpdate[pi].second, false);
4712 PHI->addMachineBasicBlockOperand(BitTestCases[i].Cases.back().ThisBB);
4714 // One of "cases" BB.
4715 for (unsigned j = 0, ej = BitTestCases[i].Cases.size(); j != ej; ++j) {
4716 MachineBasicBlock* cBB = BitTestCases[i].Cases[j].ThisBB;
4717 if (cBB->succ_end() !=
4718 std::find(cBB->succ_begin(),cBB->succ_end(), PHIBB)) {
4719 PHI->addRegOperand(PHINodesToUpdate[pi].second, false);
4720 PHI->addMachineBasicBlockOperand(cBB);
4726 // If the JumpTable record is filled in, then we need to emit a jump table.
4727 // Updating the PHI nodes is tricky in this case, since we need to determine
4728 // whether the PHI is a successor of the range check MBB or the jump table MBB
4729 for (unsigned i = 0, e = JTCases.size(); i != e; ++i) {
4730 // Lower header first, if it wasn't already lowered
4731 if (!JTCases[i].first.Emitted) {
4732 SelectionDAG HSDAG(TLI, MF, getAnalysisToUpdate<MachineModuleInfo>());
4734 SelectionDAGLowering HSDL(HSDAG, TLI, *AA, FuncInfo);
4735 // Set the current basic block to the mbb we wish to insert the code into
4736 BB = JTCases[i].first.HeaderBB;
4737 HSDL.setCurrentBasicBlock(BB);
4739 HSDL.visitJumpTableHeader(JTCases[i].second, JTCases[i].first);
4740 HSDAG.setRoot(HSDL.getRoot());
4741 CodeGenAndEmitDAG(HSDAG);
4744 SelectionDAG JSDAG(TLI, MF, getAnalysisToUpdate<MachineModuleInfo>());
4746 SelectionDAGLowering JSDL(JSDAG, TLI, *AA, FuncInfo);
4747 // Set the current basic block to the mbb we wish to insert the code into
4748 BB = JTCases[i].second.MBB;
4749 JSDL.setCurrentBasicBlock(BB);
4751 JSDL.visitJumpTable(JTCases[i].second);
4752 JSDAG.setRoot(JSDL.getRoot());
4753 CodeGenAndEmitDAG(JSDAG);
4756 for (unsigned pi = 0, pe = PHINodesToUpdate.size(); pi != pe; ++pi) {
4757 MachineInstr *PHI = PHINodesToUpdate[pi].first;
4758 MachineBasicBlock *PHIBB = PHI->getParent();
4759 assert(PHI->getOpcode() == TargetInstrInfo::PHI &&
4760 "This is not a machine PHI node that we are updating!");
4761 // "default" BB. We can go there only from header BB.
4762 if (PHIBB == JTCases[i].second.Default) {
4763 PHI->addRegOperand(PHINodesToUpdate[pi].second, false);
4764 PHI->addMachineBasicBlockOperand(JTCases[i].first.HeaderBB);
4766 // JT BB. Just iterate over successors here
4767 if (BB->succ_end() != std::find(BB->succ_begin(),BB->succ_end(), PHIBB)) {
4768 PHI->addRegOperand(PHINodesToUpdate[pi].second, false);
4769 PHI->addMachineBasicBlockOperand(BB);
4774 // If the switch block involved a branch to one of the actual successors, we
4775 // need to update PHI nodes in that block.
4776 for (unsigned i = 0, e = PHINodesToUpdate.size(); i != e; ++i) {
4777 MachineInstr *PHI = PHINodesToUpdate[i].first;
4778 assert(PHI->getOpcode() == TargetInstrInfo::PHI &&
4779 "This is not a machine PHI node that we are updating!");
4780 if (BB->isSuccessor(PHI->getParent())) {
4781 PHI->addRegOperand(PHINodesToUpdate[i].second, false);
4782 PHI->addMachineBasicBlockOperand(BB);
4786 // If we generated any switch lowering information, build and codegen any
4787 // additional DAGs necessary.
4788 for (unsigned i = 0, e = SwitchCases.size(); i != e; ++i) {
4789 SelectionDAG SDAG(TLI, MF, getAnalysisToUpdate<MachineModuleInfo>());
4791 SelectionDAGLowering SDL(SDAG, TLI, *AA, FuncInfo);
4793 // Set the current basic block to the mbb we wish to insert the code into
4794 BB = SwitchCases[i].ThisBB;
4795 SDL.setCurrentBasicBlock(BB);
4798 SDL.visitSwitchCase(SwitchCases[i]);
4799 SDAG.setRoot(SDL.getRoot());
4800 CodeGenAndEmitDAG(SDAG);
4802 // Handle any PHI nodes in successors of this chunk, as if we were coming
4803 // from the original BB before switch expansion. Note that PHI nodes can
4804 // occur multiple times in PHINodesToUpdate. We have to be very careful to
4805 // handle them the right number of times.
4806 while ((BB = SwitchCases[i].TrueBB)) { // Handle LHS and RHS.
4807 for (MachineBasicBlock::iterator Phi = BB->begin();
4808 Phi != BB->end() && Phi->getOpcode() == TargetInstrInfo::PHI; ++Phi){
4809 // This value for this PHI node is recorded in PHINodesToUpdate, get it.
4810 for (unsigned pn = 0; ; ++pn) {
4811 assert(pn != PHINodesToUpdate.size() && "Didn't find PHI entry!");
4812 if (PHINodesToUpdate[pn].first == Phi) {
4813 Phi->addRegOperand(PHINodesToUpdate[pn].second, false);
4814 Phi->addMachineBasicBlockOperand(SwitchCases[i].ThisBB);
4820 // Don't process RHS if same block as LHS.
4821 if (BB == SwitchCases[i].FalseBB)
4822 SwitchCases[i].FalseBB = 0;
4824 // If we haven't handled the RHS, do so now. Otherwise, we're done.
4825 SwitchCases[i].TrueBB = SwitchCases[i].FalseBB;
4826 SwitchCases[i].FalseBB = 0;
4828 assert(SwitchCases[i].TrueBB == 0 && SwitchCases[i].FalseBB == 0);
4833 //===----------------------------------------------------------------------===//
4834 /// ScheduleAndEmitDAG - Pick a safe ordering and emit instructions for each
4835 /// target node in the graph.
4836 void SelectionDAGISel::ScheduleAndEmitDAG(SelectionDAG &DAG) {
4837 if (ViewSchedDAGs) DAG.viewGraph();
4839 RegisterScheduler::FunctionPassCtor Ctor = RegisterScheduler::getDefault();
4843 RegisterScheduler::setDefault(Ctor);
4846 ScheduleDAG *SL = Ctor(this, &DAG, BB);
4849 if (ViewSUnitDAGs) SL->viewGraph();
4855 HazardRecognizer *SelectionDAGISel::CreateTargetHazardRecognizer() {
4856 return new HazardRecognizer();
4859 //===----------------------------------------------------------------------===//
4860 // Helper functions used by the generated instruction selector.
4861 //===----------------------------------------------------------------------===//
4862 // Calls to these methods are generated by tblgen.
4864 /// CheckAndMask - The isel is trying to match something like (and X, 255). If
4865 /// the dag combiner simplified the 255, we still want to match. RHS is the
4866 /// actual value in the DAG on the RHS of an AND, and DesiredMaskS is the value
4867 /// specified in the .td file (e.g. 255).
4868 bool SelectionDAGISel::CheckAndMask(SDOperand LHS, ConstantSDNode *RHS,
4869 int64_t DesiredMaskS) const {
4870 uint64_t ActualMask = RHS->getValue();
4871 uint64_t DesiredMask =DesiredMaskS & MVT::getIntVTBitMask(LHS.getValueType());
4873 // If the actual mask exactly matches, success!
4874 if (ActualMask == DesiredMask)
4877 // If the actual AND mask is allowing unallowed bits, this doesn't match.
4878 if (ActualMask & ~DesiredMask)
4881 // Otherwise, the DAG Combiner may have proven that the value coming in is
4882 // either already zero or is not demanded. Check for known zero input bits.
4883 uint64_t NeededMask = DesiredMask & ~ActualMask;
4884 if (CurDAG->MaskedValueIsZero(LHS, NeededMask))
4887 // TODO: check to see if missing bits are just not demanded.
4889 // Otherwise, this pattern doesn't match.
4893 /// CheckOrMask - The isel is trying to match something like (or X, 255). If
4894 /// the dag combiner simplified the 255, we still want to match. RHS is the
4895 /// actual value in the DAG on the RHS of an OR, and DesiredMaskS is the value
4896 /// specified in the .td file (e.g. 255).
4897 bool SelectionDAGISel::CheckOrMask(SDOperand LHS, ConstantSDNode *RHS,
4898 int64_t DesiredMaskS) const {
4899 uint64_t ActualMask = RHS->getValue();
4900 uint64_t DesiredMask =DesiredMaskS & MVT::getIntVTBitMask(LHS.getValueType());
4902 // If the actual mask exactly matches, success!
4903 if (ActualMask == DesiredMask)
4906 // If the actual AND mask is allowing unallowed bits, this doesn't match.
4907 if (ActualMask & ~DesiredMask)
4910 // Otherwise, the DAG Combiner may have proven that the value coming in is
4911 // either already zero or is not demanded. Check for known zero input bits.
4912 uint64_t NeededMask = DesiredMask & ~ActualMask;
4914 uint64_t KnownZero, KnownOne;
4915 CurDAG->ComputeMaskedBits(LHS, NeededMask, KnownZero, KnownOne);
4917 // If all the missing bits in the or are already known to be set, match!
4918 if ((NeededMask & KnownOne) == NeededMask)
4921 // TODO: check to see if missing bits are just not demanded.
4923 // Otherwise, this pattern doesn't match.
4928 /// SelectInlineAsmMemoryOperands - Calls to this are automatically generated
4929 /// by tblgen. Others should not call it.
4930 void SelectionDAGISel::
4931 SelectInlineAsmMemoryOperands(std::vector<SDOperand> &Ops, SelectionDAG &DAG) {
4932 std::vector<SDOperand> InOps;
4933 std::swap(InOps, Ops);
4935 Ops.push_back(InOps[0]); // input chain.
4936 Ops.push_back(InOps[1]); // input asm string.
4938 unsigned i = 2, e = InOps.size();
4939 if (InOps[e-1].getValueType() == MVT::Flag)
4940 --e; // Don't process a flag operand if it is here.
4943 unsigned Flags = cast<ConstantSDNode>(InOps[i])->getValue();
4944 if ((Flags & 7) != 4 /*MEM*/) {
4945 // Just skip over this operand, copying the operands verbatim.
4946 Ops.insert(Ops.end(), InOps.begin()+i, InOps.begin()+i+(Flags >> 3) + 1);
4947 i += (Flags >> 3) + 1;
4949 assert((Flags >> 3) == 1 && "Memory operand with multiple values?");
4950 // Otherwise, this is a memory operand. Ask the target to select it.
4951 std::vector<SDOperand> SelOps;
4952 if (SelectInlineAsmMemoryOperand(InOps[i+1], 'm', SelOps, DAG)) {
4953 cerr << "Could not match memory address. Inline asm failure!\n";
4957 // Add this to the output node.
4958 MVT::ValueType IntPtrTy = DAG.getTargetLoweringInfo().getPointerTy();
4959 Ops.push_back(DAG.getTargetConstant(4/*MEM*/ | (SelOps.size() << 3),
4961 Ops.insert(Ops.end(), SelOps.begin(), SelOps.end());
4966 // Add the flag input back if present.
4967 if (e != InOps.size())
4968 Ops.push_back(InOps.back());
4971 char SelectionDAGISel::ID = 0;