1 //===-- SelectionDAGISel.cpp - Implement the SelectionDAGISel class -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements the SelectionDAGISel class.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "isel"
15 #include "llvm/CodeGen/SelectionDAGISel.h"
16 #include "ScheduleDAGSDNodes.h"
17 #include "SelectionDAGBuilder.h"
18 #include "llvm/ADT/PostOrderIterator.h"
19 #include "llvm/ADT/Statistic.h"
20 #include "llvm/Analysis/AliasAnalysis.h"
21 #include "llvm/Analysis/BranchProbabilityInfo.h"
22 #include "llvm/Analysis/TargetTransformInfo.h"
23 #include "llvm/CodeGen/FastISel.h"
24 #include "llvm/CodeGen/FunctionLoweringInfo.h"
25 #include "llvm/CodeGen/GCMetadata.h"
26 #include "llvm/CodeGen/GCStrategy.h"
27 #include "llvm/CodeGen/MachineFrameInfo.h"
28 #include "llvm/CodeGen/MachineFunction.h"
29 #include "llvm/CodeGen/MachineInstrBuilder.h"
30 #include "llvm/CodeGen/MachineModuleInfo.h"
31 #include "llvm/CodeGen/MachineRegisterInfo.h"
32 #include "llvm/CodeGen/ScheduleHazardRecognizer.h"
33 #include "llvm/CodeGen/SchedulerRegistry.h"
34 #include "llvm/CodeGen/SelectionDAG.h"
35 #include "llvm/DebugInfo.h"
36 #include "llvm/IR/Constants.h"
37 #include "llvm/IR/Function.h"
38 #include "llvm/IR/InlineAsm.h"
39 #include "llvm/IR/Instructions.h"
40 #include "llvm/IR/IntrinsicInst.h"
41 #include "llvm/IR/Intrinsics.h"
42 #include "llvm/IR/LLVMContext.h"
43 #include "llvm/IR/Module.h"
44 #include "llvm/Support/Compiler.h"
45 #include "llvm/Support/Debug.h"
46 #include "llvm/Support/ErrorHandling.h"
47 #include "llvm/Support/Timer.h"
48 #include "llvm/Support/raw_ostream.h"
49 #include "llvm/Target/TargetInstrInfo.h"
50 #include "llvm/Target/TargetIntrinsicInfo.h"
51 #include "llvm/Target/TargetLibraryInfo.h"
52 #include "llvm/Target/TargetLowering.h"
53 #include "llvm/Target/TargetMachine.h"
54 #include "llvm/Target/TargetOptions.h"
55 #include "llvm/Target/TargetRegisterInfo.h"
56 #include "llvm/Target/TargetSubtargetInfo.h"
57 #include "llvm/Transforms/Utils/BasicBlockUtils.h"
61 STATISTIC(NumFastIselFailures, "Number of instructions fast isel failed on");
62 STATISTIC(NumFastIselSuccess, "Number of instructions fast isel selected");
63 STATISTIC(NumFastIselBlocks, "Number of blocks selected entirely by fast isel");
64 STATISTIC(NumDAGBlocks, "Number of blocks selected using DAG");
65 STATISTIC(NumDAGIselRetries,"Number of times dag isel has to try another path");
66 STATISTIC(NumEntryBlocks, "Number of entry blocks encountered");
67 STATISTIC(NumFastIselFailLowerArguments,
68 "Number of entry blocks where fast isel failed to lower arguments");
72 EnableFastISelVerbose2("fast-isel-verbose2", cl::Hidden,
73 cl::desc("Enable extra verbose messages in the \"fast\" "
74 "instruction selector"));
77 STATISTIC(NumFastIselFailRet,"Fast isel fails on Ret");
78 STATISTIC(NumFastIselFailBr,"Fast isel fails on Br");
79 STATISTIC(NumFastIselFailSwitch,"Fast isel fails on Switch");
80 STATISTIC(NumFastIselFailIndirectBr,"Fast isel fails on IndirectBr");
81 STATISTIC(NumFastIselFailInvoke,"Fast isel fails on Invoke");
82 STATISTIC(NumFastIselFailResume,"Fast isel fails on Resume");
83 STATISTIC(NumFastIselFailUnreachable,"Fast isel fails on Unreachable");
85 // Standard binary operators...
86 STATISTIC(NumFastIselFailAdd,"Fast isel fails on Add");
87 STATISTIC(NumFastIselFailFAdd,"Fast isel fails on FAdd");
88 STATISTIC(NumFastIselFailSub,"Fast isel fails on Sub");
89 STATISTIC(NumFastIselFailFSub,"Fast isel fails on FSub");
90 STATISTIC(NumFastIselFailMul,"Fast isel fails on Mul");
91 STATISTIC(NumFastIselFailFMul,"Fast isel fails on FMul");
92 STATISTIC(NumFastIselFailUDiv,"Fast isel fails on UDiv");
93 STATISTIC(NumFastIselFailSDiv,"Fast isel fails on SDiv");
94 STATISTIC(NumFastIselFailFDiv,"Fast isel fails on FDiv");
95 STATISTIC(NumFastIselFailURem,"Fast isel fails on URem");
96 STATISTIC(NumFastIselFailSRem,"Fast isel fails on SRem");
97 STATISTIC(NumFastIselFailFRem,"Fast isel fails on FRem");
99 // Logical operators...
100 STATISTIC(NumFastIselFailAnd,"Fast isel fails on And");
101 STATISTIC(NumFastIselFailOr,"Fast isel fails on Or");
102 STATISTIC(NumFastIselFailXor,"Fast isel fails on Xor");
104 // Memory instructions...
105 STATISTIC(NumFastIselFailAlloca,"Fast isel fails on Alloca");
106 STATISTIC(NumFastIselFailLoad,"Fast isel fails on Load");
107 STATISTIC(NumFastIselFailStore,"Fast isel fails on Store");
108 STATISTIC(NumFastIselFailAtomicCmpXchg,"Fast isel fails on AtomicCmpXchg");
109 STATISTIC(NumFastIselFailAtomicRMW,"Fast isel fails on AtomicRWM");
110 STATISTIC(NumFastIselFailFence,"Fast isel fails on Frence");
111 STATISTIC(NumFastIselFailGetElementPtr,"Fast isel fails on GetElementPtr");
113 // Convert instructions...
114 STATISTIC(NumFastIselFailTrunc,"Fast isel fails on Trunc");
115 STATISTIC(NumFastIselFailZExt,"Fast isel fails on ZExt");
116 STATISTIC(NumFastIselFailSExt,"Fast isel fails on SExt");
117 STATISTIC(NumFastIselFailFPTrunc,"Fast isel fails on FPTrunc");
118 STATISTIC(NumFastIselFailFPExt,"Fast isel fails on FPExt");
119 STATISTIC(NumFastIselFailFPToUI,"Fast isel fails on FPToUI");
120 STATISTIC(NumFastIselFailFPToSI,"Fast isel fails on FPToSI");
121 STATISTIC(NumFastIselFailUIToFP,"Fast isel fails on UIToFP");
122 STATISTIC(NumFastIselFailSIToFP,"Fast isel fails on SIToFP");
123 STATISTIC(NumFastIselFailIntToPtr,"Fast isel fails on IntToPtr");
124 STATISTIC(NumFastIselFailPtrToInt,"Fast isel fails on PtrToInt");
125 STATISTIC(NumFastIselFailBitCast,"Fast isel fails on BitCast");
127 // Other instructions...
128 STATISTIC(NumFastIselFailICmp,"Fast isel fails on ICmp");
129 STATISTIC(NumFastIselFailFCmp,"Fast isel fails on FCmp");
130 STATISTIC(NumFastIselFailPHI,"Fast isel fails on PHI");
131 STATISTIC(NumFastIselFailSelect,"Fast isel fails on Select");
132 STATISTIC(NumFastIselFailCall,"Fast isel fails on Call");
133 STATISTIC(NumFastIselFailShl,"Fast isel fails on Shl");
134 STATISTIC(NumFastIselFailLShr,"Fast isel fails on LShr");
135 STATISTIC(NumFastIselFailAShr,"Fast isel fails on AShr");
136 STATISTIC(NumFastIselFailVAArg,"Fast isel fails on VAArg");
137 STATISTIC(NumFastIselFailExtractElement,"Fast isel fails on ExtractElement");
138 STATISTIC(NumFastIselFailInsertElement,"Fast isel fails on InsertElement");
139 STATISTIC(NumFastIselFailShuffleVector,"Fast isel fails on ShuffleVector");
140 STATISTIC(NumFastIselFailExtractValue,"Fast isel fails on ExtractValue");
141 STATISTIC(NumFastIselFailInsertValue,"Fast isel fails on InsertValue");
142 STATISTIC(NumFastIselFailLandingPad,"Fast isel fails on LandingPad");
146 EnableFastISelVerbose("fast-isel-verbose", cl::Hidden,
147 cl::desc("Enable verbose messages in the \"fast\" "
148 "instruction selector"));
150 EnableFastISelAbort("fast-isel-abort", cl::Hidden,
151 cl::desc("Enable abort calls when \"fast\" instruction selection "
152 "fails to lower an instruction"));
154 EnableFastISelAbortArgs("fast-isel-abort-args", cl::Hidden,
155 cl::desc("Enable abort calls when \"fast\" instruction selection "
156 "fails to lower a formal argument"));
160 cl::desc("use Machine Branch Probability Info"),
161 cl::init(true), cl::Hidden);
165 ViewDAGCombine1("view-dag-combine1-dags", cl::Hidden,
166 cl::desc("Pop up a window to show dags before the first "
167 "dag combine pass"));
169 ViewLegalizeTypesDAGs("view-legalize-types-dags", cl::Hidden,
170 cl::desc("Pop up a window to show dags before legalize types"));
172 ViewLegalizeDAGs("view-legalize-dags", cl::Hidden,
173 cl::desc("Pop up a window to show dags before legalize"));
175 ViewDAGCombine2("view-dag-combine2-dags", cl::Hidden,
176 cl::desc("Pop up a window to show dags before the second "
177 "dag combine pass"));
179 ViewDAGCombineLT("view-dag-combine-lt-dags", cl::Hidden,
180 cl::desc("Pop up a window to show dags before the post legalize types"
181 " dag combine pass"));
183 ViewISelDAGs("view-isel-dags", cl::Hidden,
184 cl::desc("Pop up a window to show isel dags as they are selected"));
186 ViewSchedDAGs("view-sched-dags", cl::Hidden,
187 cl::desc("Pop up a window to show sched dags as they are processed"));
189 ViewSUnitDAGs("view-sunit-dags", cl::Hidden,
190 cl::desc("Pop up a window to show SUnit dags after they are processed"));
192 static const bool ViewDAGCombine1 = false,
193 ViewLegalizeTypesDAGs = false, ViewLegalizeDAGs = false,
194 ViewDAGCombine2 = false,
195 ViewDAGCombineLT = false,
196 ViewISelDAGs = false, ViewSchedDAGs = false,
197 ViewSUnitDAGs = false;
200 //===---------------------------------------------------------------------===//
202 /// RegisterScheduler class - Track the registration of instruction schedulers.
204 //===---------------------------------------------------------------------===//
205 MachinePassRegistry RegisterScheduler::Registry;
207 //===---------------------------------------------------------------------===//
209 /// ISHeuristic command line option for instruction schedulers.
211 //===---------------------------------------------------------------------===//
212 static cl::opt<RegisterScheduler::FunctionPassCtor, false,
213 RegisterPassParser<RegisterScheduler> >
214 ISHeuristic("pre-RA-sched",
215 cl::init(&createDefaultScheduler),
216 cl::desc("Instruction schedulers available (before register"
219 static RegisterScheduler
220 defaultListDAGScheduler("default", "Best scheduler for the target",
221 createDefaultScheduler);
224 //===--------------------------------------------------------------------===//
225 /// createDefaultScheduler - This creates an instruction scheduler appropriate
227 ScheduleDAGSDNodes* createDefaultScheduler(SelectionDAGISel *IS,
228 CodeGenOpt::Level OptLevel) {
229 const TargetLowering &TLI = IS->getTargetLowering();
230 const TargetSubtargetInfo &ST = IS->TM.getSubtarget<TargetSubtargetInfo>();
232 if (OptLevel == CodeGenOpt::None || ST.enableMachineScheduler() ||
233 TLI.getSchedulingPreference() == Sched::Source)
234 return createSourceListDAGScheduler(IS, OptLevel);
235 if (TLI.getSchedulingPreference() == Sched::RegPressure)
236 return createBURRListDAGScheduler(IS, OptLevel);
237 if (TLI.getSchedulingPreference() == Sched::Hybrid)
238 return createHybridListDAGScheduler(IS, OptLevel);
239 if (TLI.getSchedulingPreference() == Sched::VLIW)
240 return createVLIWDAGScheduler(IS, OptLevel);
241 assert(TLI.getSchedulingPreference() == Sched::ILP &&
242 "Unknown sched type!");
243 return createILPListDAGScheduler(IS, OptLevel);
247 // EmitInstrWithCustomInserter - This method should be implemented by targets
248 // that mark instructions with the 'usesCustomInserter' flag. These
249 // instructions are special in various ways, which require special support to
250 // insert. The specified MachineInstr is created but not inserted into any
251 // basic blocks, and this method is called to expand it into a sequence of
252 // instructions, potentially also creating new basic blocks and control flow.
253 // When new basic blocks are inserted and the edges from MBB to its successors
254 // are modified, the method should insert pairs of <OldSucc, NewSucc> into the
257 TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
258 MachineBasicBlock *MBB) const {
260 dbgs() << "If a target marks an instruction with "
261 "'usesCustomInserter', it must implement "
262 "TargetLowering::EmitInstrWithCustomInserter!";
267 void TargetLowering::AdjustInstrPostInstrSelection(MachineInstr *MI,
268 SDNode *Node) const {
269 assert(!MI->hasPostISelHook() &&
270 "If a target marks an instruction with 'hasPostISelHook', "
271 "it must implement TargetLowering::AdjustInstrPostInstrSelection!");
274 //===----------------------------------------------------------------------===//
275 // SelectionDAGISel code
276 //===----------------------------------------------------------------------===//
278 SelectionDAGISel::SelectionDAGISel(const TargetMachine &tm,
279 CodeGenOpt::Level OL) :
280 MachineFunctionPass(ID), TM(tm), TLI(*tm.getTargetLowering()),
281 FuncInfo(new FunctionLoweringInfo(TLI)),
282 CurDAG(new SelectionDAG(tm, OL)),
283 SDB(new SelectionDAGBuilder(*CurDAG, *FuncInfo, OL)),
287 initializeGCModuleInfoPass(*PassRegistry::getPassRegistry());
288 initializeAliasAnalysisAnalysisGroup(*PassRegistry::getPassRegistry());
289 initializeBranchProbabilityInfoPass(*PassRegistry::getPassRegistry());
290 initializeTargetLibraryInfoPass(*PassRegistry::getPassRegistry());
293 SelectionDAGISel::~SelectionDAGISel() {
299 void SelectionDAGISel::getAnalysisUsage(AnalysisUsage &AU) const {
300 AU.addRequired<AliasAnalysis>();
301 AU.addPreserved<AliasAnalysis>();
302 AU.addRequired<GCModuleInfo>();
303 AU.addPreserved<GCModuleInfo>();
304 AU.addRequired<TargetLibraryInfo>();
305 if (UseMBPI && OptLevel != CodeGenOpt::None)
306 AU.addRequired<BranchProbabilityInfo>();
307 MachineFunctionPass::getAnalysisUsage(AU);
310 /// SplitCriticalSideEffectEdges - Look for critical edges with a PHI value that
311 /// may trap on it. In this case we have to split the edge so that the path
312 /// through the predecessor block that doesn't go to the phi block doesn't
313 /// execute the possibly trapping instruction.
315 /// This is required for correctness, so it must be done at -O0.
317 static void SplitCriticalSideEffectEdges(Function &Fn, Pass *SDISel) {
318 // Loop for blocks with phi nodes.
319 for (Function::iterator BB = Fn.begin(), E = Fn.end(); BB != E; ++BB) {
320 PHINode *PN = dyn_cast<PHINode>(BB->begin());
321 if (PN == 0) continue;
324 // For each block with a PHI node, check to see if any of the input values
325 // are potentially trapping constant expressions. Constant expressions are
326 // the only potentially trapping value that can occur as the argument to a
328 for (BasicBlock::iterator I = BB->begin(); (PN = dyn_cast<PHINode>(I)); ++I)
329 for (unsigned i = 0, e = PN->getNumIncomingValues(); i != e; ++i) {
330 ConstantExpr *CE = dyn_cast<ConstantExpr>(PN->getIncomingValue(i));
331 if (CE == 0 || !CE->canTrap()) continue;
333 // The only case we have to worry about is when the edge is critical.
334 // Since this block has a PHI Node, we assume it has multiple input
335 // edges: check to see if the pred has multiple successors.
336 BasicBlock *Pred = PN->getIncomingBlock(i);
337 if (Pred->getTerminator()->getNumSuccessors() == 1)
340 // Okay, we have to split this edge.
341 SplitCriticalEdge(Pred->getTerminator(),
342 GetSuccessorNumber(Pred, BB), SDISel, true);
348 bool SelectionDAGISel::runOnMachineFunction(MachineFunction &mf) {
349 // Do some sanity-checking on the command-line options.
350 assert((!EnableFastISelVerbose || TM.Options.EnableFastISel) &&
351 "-fast-isel-verbose requires -fast-isel");
352 assert((!EnableFastISelAbort || TM.Options.EnableFastISel) &&
353 "-fast-isel-abort requires -fast-isel");
355 const Function &Fn = *mf.getFunction();
356 const TargetInstrInfo &TII = *TM.getInstrInfo();
357 const TargetRegisterInfo &TRI = *TM.getRegisterInfo();
360 RegInfo = &MF->getRegInfo();
361 AA = &getAnalysis<AliasAnalysis>();
362 LibInfo = &getAnalysis<TargetLibraryInfo>();
363 TTI = getAnalysisIfAvailable<TargetTransformInfo>();
364 GFI = Fn.hasGC() ? &getAnalysis<GCModuleInfo>().getFunctionInfo(Fn) : 0;
366 TargetSubtargetInfo &ST =
367 const_cast<TargetSubtargetInfo&>(TM.getSubtarget<TargetSubtargetInfo>());
368 ST.resetSubtargetFeatures(MF);
369 TM.resetTargetOptions(MF);
371 DEBUG(dbgs() << "\n\n\n=== " << Fn.getName() << "\n");
373 SplitCriticalSideEffectEdges(const_cast<Function&>(Fn), this);
375 CurDAG->init(*MF, TTI);
376 FuncInfo->set(Fn, *MF);
378 if (UseMBPI && OptLevel != CodeGenOpt::None)
379 FuncInfo->BPI = &getAnalysis<BranchProbabilityInfo>();
383 SDB->init(GFI, *AA, LibInfo);
385 MF->setHasMSInlineAsm(false);
386 SelectAllBasicBlocks(Fn);
388 // If the first basic block in the function has live ins that need to be
389 // copied into vregs, emit the copies into the top of the block before
390 // emitting the code for the block.
391 MachineBasicBlock *EntryMBB = MF->begin();
392 RegInfo->EmitLiveInCopies(EntryMBB, TRI, TII);
394 DenseMap<unsigned, unsigned> LiveInMap;
395 if (!FuncInfo->ArgDbgValues.empty())
396 for (MachineRegisterInfo::livein_iterator LI = RegInfo->livein_begin(),
397 E = RegInfo->livein_end(); LI != E; ++LI)
399 LiveInMap.insert(std::make_pair(LI->first, LI->second));
401 // Insert DBG_VALUE instructions for function arguments to the entry block.
402 for (unsigned i = 0, e = FuncInfo->ArgDbgValues.size(); i != e; ++i) {
403 MachineInstr *MI = FuncInfo->ArgDbgValues[e-i-1];
404 unsigned Reg = MI->getOperand(0).getReg();
405 if (TargetRegisterInfo::isPhysicalRegister(Reg))
406 EntryMBB->insert(EntryMBB->begin(), MI);
408 MachineInstr *Def = RegInfo->getVRegDef(Reg);
409 MachineBasicBlock::iterator InsertPos = Def;
410 // FIXME: VR def may not be in entry block.
411 Def->getParent()->insert(llvm::next(InsertPos), MI);
414 // If Reg is live-in then update debug info to track its copy in a vreg.
415 DenseMap<unsigned, unsigned>::iterator LDI = LiveInMap.find(Reg);
416 if (LDI != LiveInMap.end()) {
417 MachineInstr *Def = RegInfo->getVRegDef(LDI->second);
418 MachineBasicBlock::iterator InsertPos = Def;
419 const MDNode *Variable =
420 MI->getOperand(MI->getNumOperands()-1).getMetadata();
421 unsigned Offset = MI->getOperand(1).getImm();
422 // Def is never a terminator here, so it is ok to increment InsertPos.
423 BuildMI(*EntryMBB, ++InsertPos, MI->getDebugLoc(),
424 TII.get(TargetOpcode::DBG_VALUE))
425 .addReg(LDI->second, RegState::Debug)
426 .addImm(Offset).addMetadata(Variable);
428 // If this vreg is directly copied into an exported register then
429 // that COPY instructions also need DBG_VALUE, if it is the only
430 // user of LDI->second.
431 MachineInstr *CopyUseMI = NULL;
432 for (MachineRegisterInfo::use_iterator
433 UI = RegInfo->use_begin(LDI->second);
434 MachineInstr *UseMI = UI.skipInstruction();) {
435 if (UseMI->isDebugValue()) continue;
436 if (UseMI->isCopy() && !CopyUseMI && UseMI->getParent() == EntryMBB) {
437 CopyUseMI = UseMI; continue;
439 // Otherwise this is another use or second copy use.
440 CopyUseMI = NULL; break;
443 MachineInstr *NewMI =
444 BuildMI(*MF, CopyUseMI->getDebugLoc(),
445 TII.get(TargetOpcode::DBG_VALUE))
446 .addReg(CopyUseMI->getOperand(0).getReg(), RegState::Debug)
447 .addImm(Offset).addMetadata(Variable);
448 MachineBasicBlock::iterator Pos = CopyUseMI;
449 EntryMBB->insertAfter(Pos, NewMI);
454 // Determine if there are any calls in this machine function.
455 MachineFrameInfo *MFI = MF->getFrameInfo();
456 for (MachineFunction::const_iterator I = MF->begin(), E = MF->end(); I != E;
459 if (MFI->hasCalls() && MF->hasMSInlineAsm())
462 const MachineBasicBlock *MBB = I;
463 for (MachineBasicBlock::const_iterator II = MBB->begin(), IE = MBB->end();
465 const MCInstrDesc &MCID = TM.getInstrInfo()->get(II->getOpcode());
466 if ((MCID.isCall() && !MCID.isReturn()) ||
467 II->isStackAligningInlineAsm()) {
468 MFI->setHasCalls(true);
470 if (II->isMSInlineAsm()) {
471 MF->setHasMSInlineAsm(true);
476 // Determine if there is a call to setjmp in the machine function.
477 MF->setExposesReturnsTwice(Fn.callsFunctionThatReturnsTwice());
479 // Replace forward-declared registers with the registers containing
480 // the desired value.
481 MachineRegisterInfo &MRI = MF->getRegInfo();
482 for (DenseMap<unsigned, unsigned>::iterator
483 I = FuncInfo->RegFixups.begin(), E = FuncInfo->RegFixups.end();
485 unsigned From = I->first;
486 unsigned To = I->second;
487 // If To is also scheduled to be replaced, find what its ultimate
490 DenseMap<unsigned, unsigned>::iterator J = FuncInfo->RegFixups.find(To);
495 MRI.replaceRegWith(From, To);
498 // Freeze the set of reserved registers now that MachineFrameInfo has been
499 // set up. All the information required by getReservedRegs() should be
501 MRI.freezeReservedRegs(*MF);
503 // Release function-specific state. SDB and CurDAG are already cleared
510 void SelectionDAGISel::SelectBasicBlock(BasicBlock::const_iterator Begin,
511 BasicBlock::const_iterator End,
513 // Lower all of the non-terminator instructions. If a call is emitted
514 // as a tail call, cease emitting nodes for this block. Terminators
515 // are handled below.
516 for (BasicBlock::const_iterator I = Begin; I != End && !SDB->HasTailCall; ++I)
519 // Make sure the root of the DAG is up-to-date.
520 CurDAG->setRoot(SDB->getControlRoot());
521 HadTailCall = SDB->HasTailCall;
524 // Final step, emit the lowered DAG as machine code.
528 void SelectionDAGISel::ComputeLiveOutVRegInfo() {
529 SmallPtrSet<SDNode*, 128> VisitedNodes;
530 SmallVector<SDNode*, 128> Worklist;
532 Worklist.push_back(CurDAG->getRoot().getNode());
538 SDNode *N = Worklist.pop_back_val();
540 // If we've already seen this node, ignore it.
541 if (!VisitedNodes.insert(N))
544 // Otherwise, add all chain operands to the worklist.
545 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
546 if (N->getOperand(i).getValueType() == MVT::Other)
547 Worklist.push_back(N->getOperand(i).getNode());
549 // If this is a CopyToReg with a vreg dest, process it.
550 if (N->getOpcode() != ISD::CopyToReg)
553 unsigned DestReg = cast<RegisterSDNode>(N->getOperand(1))->getReg();
554 if (!TargetRegisterInfo::isVirtualRegister(DestReg))
557 // Ignore non-scalar or non-integer values.
558 SDValue Src = N->getOperand(2);
559 EVT SrcVT = Src.getValueType();
560 if (!SrcVT.isInteger() || SrcVT.isVector())
563 unsigned NumSignBits = CurDAG->ComputeNumSignBits(Src);
564 CurDAG->ComputeMaskedBits(Src, KnownZero, KnownOne);
565 FuncInfo->AddLiveOutRegInfo(DestReg, NumSignBits, KnownZero, KnownOne);
566 } while (!Worklist.empty());
569 void SelectionDAGISel::CodeGenAndEmitDAG() {
570 std::string GroupName;
571 if (TimePassesIsEnabled)
572 GroupName = "Instruction Selection and Scheduling";
573 std::string BlockName;
574 int BlockNumber = -1;
577 if (ViewDAGCombine1 || ViewLegalizeTypesDAGs || ViewLegalizeDAGs ||
578 ViewDAGCombine2 || ViewDAGCombineLT || ViewISelDAGs || ViewSchedDAGs ||
582 BlockNumber = FuncInfo->MBB->getNumber();
583 BlockName = MF->getName().str() + ":" +
584 FuncInfo->MBB->getBasicBlock()->getName().str();
586 DEBUG(dbgs() << "Initial selection DAG: BB#" << BlockNumber
587 << " '" << BlockName << "'\n"; CurDAG->dump());
589 if (ViewDAGCombine1) CurDAG->viewGraph("dag-combine1 input for " + BlockName);
591 // Run the DAG combiner in pre-legalize mode.
593 NamedRegionTimer T("DAG Combining 1", GroupName, TimePassesIsEnabled);
594 CurDAG->Combine(BeforeLegalizeTypes, *AA, OptLevel);
597 DEBUG(dbgs() << "Optimized lowered selection DAG: BB#" << BlockNumber
598 << " '" << BlockName << "'\n"; CurDAG->dump());
600 // Second step, hack on the DAG until it only uses operations and types that
601 // the target supports.
602 if (ViewLegalizeTypesDAGs) CurDAG->viewGraph("legalize-types input for " +
607 NamedRegionTimer T("Type Legalization", GroupName, TimePassesIsEnabled);
608 Changed = CurDAG->LegalizeTypes();
611 DEBUG(dbgs() << "Type-legalized selection DAG: BB#" << BlockNumber
612 << " '" << BlockName << "'\n"; CurDAG->dump());
615 if (ViewDAGCombineLT)
616 CurDAG->viewGraph("dag-combine-lt input for " + BlockName);
618 // Run the DAG combiner in post-type-legalize mode.
620 NamedRegionTimer T("DAG Combining after legalize types", GroupName,
621 TimePassesIsEnabled);
622 CurDAG->Combine(AfterLegalizeTypes, *AA, OptLevel);
625 DEBUG(dbgs() << "Optimized type-legalized selection DAG: BB#" << BlockNumber
626 << " '" << BlockName << "'\n"; CurDAG->dump());
630 NamedRegionTimer T("Vector Legalization", GroupName, TimePassesIsEnabled);
631 Changed = CurDAG->LegalizeVectors();
636 NamedRegionTimer T("Type Legalization 2", GroupName, TimePassesIsEnabled);
637 CurDAG->LegalizeTypes();
640 if (ViewDAGCombineLT)
641 CurDAG->viewGraph("dag-combine-lv input for " + BlockName);
643 // Run the DAG combiner in post-type-legalize mode.
645 NamedRegionTimer T("DAG Combining after legalize vectors", GroupName,
646 TimePassesIsEnabled);
647 CurDAG->Combine(AfterLegalizeVectorOps, *AA, OptLevel);
650 DEBUG(dbgs() << "Optimized vector-legalized selection DAG: BB#"
651 << BlockNumber << " '" << BlockName << "'\n"; CurDAG->dump());
654 if (ViewLegalizeDAGs) CurDAG->viewGraph("legalize input for " + BlockName);
657 NamedRegionTimer T("DAG Legalization", GroupName, TimePassesIsEnabled);
661 DEBUG(dbgs() << "Legalized selection DAG: BB#" << BlockNumber
662 << " '" << BlockName << "'\n"; CurDAG->dump());
664 if (ViewDAGCombine2) CurDAG->viewGraph("dag-combine2 input for " + BlockName);
666 // Run the DAG combiner in post-legalize mode.
668 NamedRegionTimer T("DAG Combining 2", GroupName, TimePassesIsEnabled);
669 CurDAG->Combine(AfterLegalizeDAG, *AA, OptLevel);
672 DEBUG(dbgs() << "Optimized legalized selection DAG: BB#" << BlockNumber
673 << " '" << BlockName << "'\n"; CurDAG->dump());
675 if (OptLevel != CodeGenOpt::None)
676 ComputeLiveOutVRegInfo();
678 if (ViewISelDAGs) CurDAG->viewGraph("isel input for " + BlockName);
680 // Third, instruction select all of the operations to machine code, adding the
681 // code to the MachineBasicBlock.
683 NamedRegionTimer T("Instruction Selection", GroupName, TimePassesIsEnabled);
684 DoInstructionSelection();
687 DEBUG(dbgs() << "Selected selection DAG: BB#" << BlockNumber
688 << " '" << BlockName << "'\n"; CurDAG->dump());
690 if (ViewSchedDAGs) CurDAG->viewGraph("scheduler input for " + BlockName);
692 // Schedule machine code.
693 ScheduleDAGSDNodes *Scheduler = CreateScheduler();
695 NamedRegionTimer T("Instruction Scheduling", GroupName,
696 TimePassesIsEnabled);
697 Scheduler->Run(CurDAG, FuncInfo->MBB);
700 if (ViewSUnitDAGs) Scheduler->viewGraph();
702 // Emit machine code to BB. This can change 'BB' to the last block being
704 MachineBasicBlock *FirstMBB = FuncInfo->MBB, *LastMBB;
706 NamedRegionTimer T("Instruction Creation", GroupName, TimePassesIsEnabled);
708 // FuncInfo->InsertPt is passed by reference and set to the end of the
709 // scheduled instructions.
710 LastMBB = FuncInfo->MBB = Scheduler->EmitSchedule(FuncInfo->InsertPt);
713 // If the block was split, make sure we update any references that are used to
714 // update PHI nodes later on.
715 if (FirstMBB != LastMBB)
716 SDB->UpdateSplitBlock(FirstMBB, LastMBB);
718 // Free the scheduler state.
720 NamedRegionTimer T("Instruction Scheduling Cleanup", GroupName,
721 TimePassesIsEnabled);
725 // Free the SelectionDAG state, now that we're finished with it.
730 /// ISelUpdater - helper class to handle updates of the instruction selection
732 class ISelUpdater : public SelectionDAG::DAGUpdateListener {
733 SelectionDAG::allnodes_iterator &ISelPosition;
735 ISelUpdater(SelectionDAG &DAG, SelectionDAG::allnodes_iterator &isp)
736 : SelectionDAG::DAGUpdateListener(DAG), ISelPosition(isp) {}
738 /// NodeDeleted - Handle nodes deleted from the graph. If the node being
739 /// deleted is the current ISelPosition node, update ISelPosition.
741 virtual void NodeDeleted(SDNode *N, SDNode *E) {
742 if (ISelPosition == SelectionDAG::allnodes_iterator(N))
746 } // end anonymous namespace
748 void SelectionDAGISel::DoInstructionSelection() {
749 DEBUG(dbgs() << "===== Instruction selection begins: BB#"
750 << FuncInfo->MBB->getNumber()
751 << " '" << FuncInfo->MBB->getName() << "'\n");
755 // Select target instructions for the DAG.
757 // Number all nodes with a topological order and set DAGSize.
758 DAGSize = CurDAG->AssignTopologicalOrder();
760 // Create a dummy node (which is not added to allnodes), that adds
761 // a reference to the root node, preventing it from being deleted,
762 // and tracking any changes of the root.
763 HandleSDNode Dummy(CurDAG->getRoot());
764 SelectionDAG::allnodes_iterator ISelPosition (CurDAG->getRoot().getNode());
767 // Make sure that ISelPosition gets properly updated when nodes are deleted
768 // in calls made from this function.
769 ISelUpdater ISU(*CurDAG, ISelPosition);
771 // The AllNodes list is now topological-sorted. Visit the
772 // nodes by starting at the end of the list (the root of the
773 // graph) and preceding back toward the beginning (the entry
775 while (ISelPosition != CurDAG->allnodes_begin()) {
776 SDNode *Node = --ISelPosition;
777 // Skip dead nodes. DAGCombiner is expected to eliminate all dead nodes,
778 // but there are currently some corner cases that it misses. Also, this
779 // makes it theoretically possible to disable the DAGCombiner.
780 if (Node->use_empty())
783 SDNode *ResNode = Select(Node);
785 // FIXME: This is pretty gross. 'Select' should be changed to not return
786 // anything at all and this code should be nuked with a tactical strike.
788 // If node should not be replaced, continue with the next one.
789 if (ResNode == Node || Node->getOpcode() == ISD::DELETED_NODE)
793 // Propagate ordering
794 CurDAG->AssignOrdering(ResNode, CurDAG->GetOrdering(Node));
796 ReplaceUses(Node, ResNode);
799 // If after the replacement this node is not used any more,
800 // remove this dead node.
801 if (Node->use_empty()) // Don't delete EntryToken, etc.
802 CurDAG->RemoveDeadNode(Node);
805 CurDAG->setRoot(Dummy.getValue());
808 DEBUG(dbgs() << "===== Instruction selection ends:\n");
810 PostprocessISelDAG();
813 /// PrepareEHLandingPad - Emit an EH_LABEL, set up live-in registers, and
814 /// do other setup for EH landing-pad blocks.
815 void SelectionDAGISel::PrepareEHLandingPad() {
816 MachineBasicBlock *MBB = FuncInfo->MBB;
818 // Add a label to mark the beginning of the landing pad. Deletion of the
819 // landing pad can thus be detected via the MachineModuleInfo.
820 MCSymbol *Label = MF->getMMI().addLandingPad(MBB);
822 // Assign the call site to the landing pad's begin label.
823 MF->getMMI().setCallSiteLandingPad(Label, SDB->LPadToCallSiteMap[MBB]);
825 const MCInstrDesc &II = TM.getInstrInfo()->get(TargetOpcode::EH_LABEL);
826 BuildMI(*MBB, FuncInfo->InsertPt, SDB->getCurDebugLoc(), II)
829 // Mark exception register as live in.
830 unsigned Reg = TLI.getExceptionPointerRegister();
831 if (Reg) MBB->addLiveIn(Reg);
833 // Mark exception selector register as live in.
834 Reg = TLI.getExceptionSelectorRegister();
835 if (Reg) MBB->addLiveIn(Reg);
838 /// TryToFoldFastISelLoad - We're checking to see if we can fold the specified
839 /// load into the specified FoldInst. Note that we could have a sequence where
840 /// multiple LLVM IR instructions are folded into the same machineinstr. For
841 /// example we could have:
842 /// A: x = load i32 *P
843 /// B: y = icmp A, 42
846 /// In this scenario, LI is "A", and FoldInst is "C". We know about "B" (and
847 /// any other folded instructions) because it is between A and C.
849 /// If we succeed in folding the load into the operation, return true.
851 bool SelectionDAGISel::TryToFoldFastISelLoad(const LoadInst *LI,
852 const Instruction *FoldInst,
854 // We know that the load has a single use, but don't know what it is. If it
855 // isn't one of the folded instructions, then we can't succeed here. Handle
856 // this by scanning the single-use users of the load until we get to FoldInst.
857 unsigned MaxUsers = 6; // Don't scan down huge single-use chains of instrs.
859 const Instruction *TheUser = LI->use_back();
860 while (TheUser != FoldInst && // Scan up until we find FoldInst.
861 // Stay in the right block.
862 TheUser->getParent() == FoldInst->getParent() &&
863 --MaxUsers) { // Don't scan too far.
864 // If there are multiple or no uses of this instruction, then bail out.
865 if (!TheUser->hasOneUse())
868 TheUser = TheUser->use_back();
871 // If we didn't find the fold instruction, then we failed to collapse the
873 if (TheUser != FoldInst)
876 // Don't try to fold volatile loads. Target has to deal with alignment
878 if (LI->isVolatile()) return false;
880 // Figure out which vreg this is going into. If there is no assigned vreg yet
881 // then there actually was no reference to it. Perhaps the load is referenced
882 // by a dead instruction.
883 unsigned LoadReg = FastIS->getRegForValue(LI);
887 // Check to see what the uses of this vreg are. If it has no uses, or more
888 // than one use (at the machine instr level) then we can't fold it.
889 MachineRegisterInfo::reg_iterator RI = RegInfo->reg_begin(LoadReg);
890 if (RI == RegInfo->reg_end())
893 // See if there is exactly one use of the vreg. If there are multiple uses,
894 // then the instruction got lowered to multiple machine instructions or the
895 // use of the loaded value ended up being multiple operands of the result, in
896 // either case, we can't fold this.
897 MachineRegisterInfo::reg_iterator PostRI = RI; ++PostRI;
898 if (PostRI != RegInfo->reg_end())
901 assert(RI.getOperand().isUse() &&
902 "The only use of the vreg must be a use, we haven't emitted the def!");
904 MachineInstr *User = &*RI;
906 // Set the insertion point properly. Folding the load can cause generation of
907 // other random instructions (like sign extends) for addressing modes, make
908 // sure they get inserted in a logical place before the new instruction.
909 FuncInfo->InsertPt = User;
910 FuncInfo->MBB = User->getParent();
912 // Ask the target to try folding the load.
913 return FastIS->TryToFoldLoad(User, RI.getOperandNo(), LI);
916 /// isFoldedOrDeadInstruction - Return true if the specified instruction is
917 /// side-effect free and is either dead or folded into a generated instruction.
918 /// Return false if it needs to be emitted.
919 static bool isFoldedOrDeadInstruction(const Instruction *I,
920 FunctionLoweringInfo *FuncInfo) {
921 return !I->mayWriteToMemory() && // Side-effecting instructions aren't folded.
922 !isa<TerminatorInst>(I) && // Terminators aren't folded.
923 !isa<DbgInfoIntrinsic>(I) && // Debug instructions aren't folded.
924 !isa<LandingPadInst>(I) && // Landingpad instructions aren't folded.
925 !FuncInfo->isExportedInst(I); // Exported instrs must be computed.
929 // Collect per Instruction statistics for fast-isel misses. Only those
930 // instructions that cause the bail are accounted for. It does not account for
931 // instructions higher in the block. Thus, summing the per instructions stats
932 // will not add up to what is reported by NumFastIselFailures.
933 static void collectFailStats(const Instruction *I) {
934 switch (I->getOpcode()) {
935 default: assert (0 && "<Invalid operator> ");
938 case Instruction::Ret: NumFastIselFailRet++; return;
939 case Instruction::Br: NumFastIselFailBr++; return;
940 case Instruction::Switch: NumFastIselFailSwitch++; return;
941 case Instruction::IndirectBr: NumFastIselFailIndirectBr++; return;
942 case Instruction::Invoke: NumFastIselFailInvoke++; return;
943 case Instruction::Resume: NumFastIselFailResume++; return;
944 case Instruction::Unreachable: NumFastIselFailUnreachable++; return;
946 // Standard binary operators...
947 case Instruction::Add: NumFastIselFailAdd++; return;
948 case Instruction::FAdd: NumFastIselFailFAdd++; return;
949 case Instruction::Sub: NumFastIselFailSub++; return;
950 case Instruction::FSub: NumFastIselFailFSub++; return;
951 case Instruction::Mul: NumFastIselFailMul++; return;
952 case Instruction::FMul: NumFastIselFailFMul++; return;
953 case Instruction::UDiv: NumFastIselFailUDiv++; return;
954 case Instruction::SDiv: NumFastIselFailSDiv++; return;
955 case Instruction::FDiv: NumFastIselFailFDiv++; return;
956 case Instruction::URem: NumFastIselFailURem++; return;
957 case Instruction::SRem: NumFastIselFailSRem++; return;
958 case Instruction::FRem: NumFastIselFailFRem++; return;
960 // Logical operators...
961 case Instruction::And: NumFastIselFailAnd++; return;
962 case Instruction::Or: NumFastIselFailOr++; return;
963 case Instruction::Xor: NumFastIselFailXor++; return;
965 // Memory instructions...
966 case Instruction::Alloca: NumFastIselFailAlloca++; return;
967 case Instruction::Load: NumFastIselFailLoad++; return;
968 case Instruction::Store: NumFastIselFailStore++; return;
969 case Instruction::AtomicCmpXchg: NumFastIselFailAtomicCmpXchg++; return;
970 case Instruction::AtomicRMW: NumFastIselFailAtomicRMW++; return;
971 case Instruction::Fence: NumFastIselFailFence++; return;
972 case Instruction::GetElementPtr: NumFastIselFailGetElementPtr++; return;
974 // Convert instructions...
975 case Instruction::Trunc: NumFastIselFailTrunc++; return;
976 case Instruction::ZExt: NumFastIselFailZExt++; return;
977 case Instruction::SExt: NumFastIselFailSExt++; return;
978 case Instruction::FPTrunc: NumFastIselFailFPTrunc++; return;
979 case Instruction::FPExt: NumFastIselFailFPExt++; return;
980 case Instruction::FPToUI: NumFastIselFailFPToUI++; return;
981 case Instruction::FPToSI: NumFastIselFailFPToSI++; return;
982 case Instruction::UIToFP: NumFastIselFailUIToFP++; return;
983 case Instruction::SIToFP: NumFastIselFailSIToFP++; return;
984 case Instruction::IntToPtr: NumFastIselFailIntToPtr++; return;
985 case Instruction::PtrToInt: NumFastIselFailPtrToInt++; return;
986 case Instruction::BitCast: NumFastIselFailBitCast++; return;
988 // Other instructions...
989 case Instruction::ICmp: NumFastIselFailICmp++; return;
990 case Instruction::FCmp: NumFastIselFailFCmp++; return;
991 case Instruction::PHI: NumFastIselFailPHI++; return;
992 case Instruction::Select: NumFastIselFailSelect++; return;
993 case Instruction::Call: NumFastIselFailCall++; return;
994 case Instruction::Shl: NumFastIselFailShl++; return;
995 case Instruction::LShr: NumFastIselFailLShr++; return;
996 case Instruction::AShr: NumFastIselFailAShr++; return;
997 case Instruction::VAArg: NumFastIselFailVAArg++; return;
998 case Instruction::ExtractElement: NumFastIselFailExtractElement++; return;
999 case Instruction::InsertElement: NumFastIselFailInsertElement++; return;
1000 case Instruction::ShuffleVector: NumFastIselFailShuffleVector++; return;
1001 case Instruction::ExtractValue: NumFastIselFailExtractValue++; return;
1002 case Instruction::InsertValue: NumFastIselFailInsertValue++; return;
1003 case Instruction::LandingPad: NumFastIselFailLandingPad++; return;
1008 void SelectionDAGISel::SelectAllBasicBlocks(const Function &Fn) {
1009 // Initialize the Fast-ISel state, if needed.
1010 FastISel *FastIS = 0;
1011 if (TM.Options.EnableFastISel)
1012 FastIS = TLI.createFastISel(*FuncInfo, LibInfo);
1014 // Iterate over all basic blocks in the function.
1015 ReversePostOrderTraversal<const Function*> RPOT(&Fn);
1016 for (ReversePostOrderTraversal<const Function*>::rpo_iterator
1017 I = RPOT.begin(), E = RPOT.end(); I != E; ++I) {
1018 const BasicBlock *LLVMBB = *I;
1020 if (OptLevel != CodeGenOpt::None) {
1021 bool AllPredsVisited = true;
1022 for (const_pred_iterator PI = pred_begin(LLVMBB), PE = pred_end(LLVMBB);
1024 if (!FuncInfo->VisitedBBs.count(*PI)) {
1025 AllPredsVisited = false;
1030 if (AllPredsVisited) {
1031 for (BasicBlock::const_iterator I = LLVMBB->begin();
1032 const PHINode *PN = dyn_cast<PHINode>(I); ++I)
1033 FuncInfo->ComputePHILiveOutRegInfo(PN);
1035 for (BasicBlock::const_iterator I = LLVMBB->begin();
1036 const PHINode *PN = dyn_cast<PHINode>(I); ++I)
1037 FuncInfo->InvalidatePHILiveOutRegInfo(PN);
1040 FuncInfo->VisitedBBs.insert(LLVMBB);
1043 BasicBlock::const_iterator const Begin = LLVMBB->getFirstNonPHI();
1044 BasicBlock::const_iterator const End = LLVMBB->end();
1045 BasicBlock::const_iterator BI = End;
1047 FuncInfo->MBB = FuncInfo->MBBMap[LLVMBB];
1048 FuncInfo->InsertPt = FuncInfo->MBB->getFirstNonPHI();
1050 // Setup an EH landing-pad block.
1051 if (FuncInfo->MBB->isLandingPad())
1052 PrepareEHLandingPad();
1054 // Before doing SelectionDAG ISel, see if FastISel has been requested.
1056 FastIS->startNewBlock();
1058 // Emit code for any incoming arguments. This must happen before
1059 // beginning FastISel on the entry block.
1060 if (LLVMBB == &Fn.getEntryBlock()) {
1063 // Lower any arguments needed in this block if this is the entry block.
1064 if (!FastIS->LowerArguments()) {
1065 // Fast isel failed to lower these arguments
1066 ++NumFastIselFailLowerArguments;
1067 if (EnableFastISelAbortArgs)
1068 llvm_unreachable("FastISel didn't lower all arguments");
1070 // Use SelectionDAG argument lowering
1072 CurDAG->setRoot(SDB->getControlRoot());
1074 CodeGenAndEmitDAG();
1077 // If we inserted any instructions at the beginning, make a note of
1078 // where they are, so we can be sure to emit subsequent instructions
1080 if (FuncInfo->InsertPt != FuncInfo->MBB->begin())
1081 FastIS->setLastLocalValue(llvm::prior(FuncInfo->InsertPt));
1083 FastIS->setLastLocalValue(0);
1086 unsigned NumFastIselRemaining = std::distance(Begin, End);
1087 // Do FastISel on as many instructions as possible.
1088 for (; BI != Begin; --BI) {
1089 const Instruction *Inst = llvm::prior(BI);
1091 // If we no longer require this instruction, skip it.
1092 if (isFoldedOrDeadInstruction(Inst, FuncInfo)) {
1093 --NumFastIselRemaining;
1097 // Bottom-up: reset the insert pos at the top, after any local-value
1099 FastIS->recomputeInsertPt();
1101 // Try to select the instruction with FastISel.
1102 if (FastIS->SelectInstruction(Inst)) {
1103 --NumFastIselRemaining;
1104 ++NumFastIselSuccess;
1105 // If fast isel succeeded, skip over all the folded instructions, and
1106 // then see if there is a load right before the selected instructions.
1107 // Try to fold the load if so.
1108 const Instruction *BeforeInst = Inst;
1109 while (BeforeInst != Begin) {
1110 BeforeInst = llvm::prior(BasicBlock::const_iterator(BeforeInst));
1111 if (!isFoldedOrDeadInstruction(BeforeInst, FuncInfo))
1114 if (BeforeInst != Inst && isa<LoadInst>(BeforeInst) &&
1115 BeforeInst->hasOneUse() &&
1116 TryToFoldFastISelLoad(cast<LoadInst>(BeforeInst), Inst, FastIS)) {
1117 // If we succeeded, don't re-select the load.
1118 BI = llvm::next(BasicBlock::const_iterator(BeforeInst));
1119 --NumFastIselRemaining;
1120 ++NumFastIselSuccess;
1126 if (EnableFastISelVerbose2)
1127 collectFailStats(Inst);
1130 // Then handle certain instructions as single-LLVM-Instruction blocks.
1131 if (isa<CallInst>(Inst)) {
1133 if (EnableFastISelVerbose || EnableFastISelAbort) {
1134 dbgs() << "FastISel missed call: ";
1138 if (!Inst->getType()->isVoidTy() && !Inst->use_empty()) {
1139 unsigned &R = FuncInfo->ValueMap[Inst];
1141 R = FuncInfo->CreateRegs(Inst->getType());
1144 bool HadTailCall = false;
1145 MachineBasicBlock::iterator SavedInsertPt = FuncInfo->InsertPt;
1146 SelectBasicBlock(Inst, BI, HadTailCall);
1148 // If the call was emitted as a tail call, we're done with the block.
1149 // We also need to delete any previously emitted instructions.
1151 FastIS->removeDeadCode(SavedInsertPt, FuncInfo->MBB->end());
1156 // Recompute NumFastIselRemaining as Selection DAG instruction
1157 // selection may have handled the call, input args, etc.
1158 unsigned RemainingNow = std::distance(Begin, BI);
1159 NumFastIselFailures += NumFastIselRemaining - RemainingNow;
1160 NumFastIselRemaining = RemainingNow;
1164 if (isa<TerminatorInst>(Inst) && !isa<BranchInst>(Inst)) {
1165 // Don't abort, and use a different message for terminator misses.
1166 NumFastIselFailures += NumFastIselRemaining;
1167 if (EnableFastISelVerbose || EnableFastISelAbort) {
1168 dbgs() << "FastISel missed terminator: ";
1172 NumFastIselFailures += NumFastIselRemaining;
1173 if (EnableFastISelVerbose || EnableFastISelAbort) {
1174 dbgs() << "FastISel miss: ";
1177 if (EnableFastISelAbort)
1178 // The "fast" selector couldn't handle something and bailed.
1179 // For the purpose of debugging, just abort.
1180 llvm_unreachable("FastISel didn't select the entire block");
1185 FastIS->recomputeInsertPt();
1187 // Lower any arguments needed in this block if this is the entry block.
1188 if (LLVMBB == &Fn.getEntryBlock()) {
1197 ++NumFastIselBlocks;
1200 // Run SelectionDAG instruction selection on the remainder of the block
1201 // not handled by FastISel. If FastISel is not run, this is the entire
1204 SelectBasicBlock(Begin, BI, HadTailCall);
1208 FuncInfo->PHINodesToUpdate.clear();
1212 SDB->clearDanglingDebugInfo();
1216 SelectionDAGISel::FinishBasicBlock() {
1218 DEBUG(dbgs() << "Total amount of phi nodes to update: "
1219 << FuncInfo->PHINodesToUpdate.size() << "\n";
1220 for (unsigned i = 0, e = FuncInfo->PHINodesToUpdate.size(); i != e; ++i)
1221 dbgs() << "Node " << i << " : ("
1222 << FuncInfo->PHINodesToUpdate[i].first
1223 << ", " << FuncInfo->PHINodesToUpdate[i].second << ")\n");
1225 // Next, now that we know what the last MBB the LLVM BB expanded is, update
1226 // PHI nodes in successors.
1227 if (SDB->SwitchCases.empty() &&
1228 SDB->JTCases.empty() &&
1229 SDB->BitTestCases.empty()) {
1230 for (unsigned i = 0, e = FuncInfo->PHINodesToUpdate.size(); i != e; ++i) {
1231 MachineInstrBuilder PHI(*MF, FuncInfo->PHINodesToUpdate[i].first);
1232 assert(PHI->isPHI() &&
1233 "This is not a machine PHI node that we are updating!");
1234 if (!FuncInfo->MBB->isSuccessor(PHI->getParent()))
1236 PHI.addReg(FuncInfo->PHINodesToUpdate[i].second).addMBB(FuncInfo->MBB);
1241 for (unsigned i = 0, e = SDB->BitTestCases.size(); i != e; ++i) {
1242 // Lower header first, if it wasn't already lowered
1243 if (!SDB->BitTestCases[i].Emitted) {
1244 // Set the current basic block to the mbb we wish to insert the code into
1245 FuncInfo->MBB = SDB->BitTestCases[i].Parent;
1246 FuncInfo->InsertPt = FuncInfo->MBB->end();
1248 SDB->visitBitTestHeader(SDB->BitTestCases[i], FuncInfo->MBB);
1249 CurDAG->setRoot(SDB->getRoot());
1251 CodeGenAndEmitDAG();
1254 uint32_t UnhandledWeight = 0;
1255 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size(); j != ej; ++j)
1256 UnhandledWeight += SDB->BitTestCases[i].Cases[j].ExtraWeight;
1258 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size(); j != ej; ++j) {
1259 UnhandledWeight -= SDB->BitTestCases[i].Cases[j].ExtraWeight;
1260 // Set the current basic block to the mbb we wish to insert the code into
1261 FuncInfo->MBB = SDB->BitTestCases[i].Cases[j].ThisBB;
1262 FuncInfo->InsertPt = FuncInfo->MBB->end();
1265 SDB->visitBitTestCase(SDB->BitTestCases[i],
1266 SDB->BitTestCases[i].Cases[j+1].ThisBB,
1268 SDB->BitTestCases[i].Reg,
1269 SDB->BitTestCases[i].Cases[j],
1272 SDB->visitBitTestCase(SDB->BitTestCases[i],
1273 SDB->BitTestCases[i].Default,
1275 SDB->BitTestCases[i].Reg,
1276 SDB->BitTestCases[i].Cases[j],
1280 CurDAG->setRoot(SDB->getRoot());
1282 CodeGenAndEmitDAG();
1286 for (unsigned pi = 0, pe = FuncInfo->PHINodesToUpdate.size();
1288 MachineInstrBuilder PHI(*MF, FuncInfo->PHINodesToUpdate[pi].first);
1289 MachineBasicBlock *PHIBB = PHI->getParent();
1290 assert(PHI->isPHI() &&
1291 "This is not a machine PHI node that we are updating!");
1292 // This is "default" BB. We have two jumps to it. From "header" BB and
1293 // from last "case" BB.
1294 if (PHIBB == SDB->BitTestCases[i].Default)
1295 PHI.addReg(FuncInfo->PHINodesToUpdate[pi].second)
1296 .addMBB(SDB->BitTestCases[i].Parent)
1297 .addReg(FuncInfo->PHINodesToUpdate[pi].second)
1298 .addMBB(SDB->BitTestCases[i].Cases.back().ThisBB);
1299 // One of "cases" BB.
1300 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size();
1302 MachineBasicBlock* cBB = SDB->BitTestCases[i].Cases[j].ThisBB;
1303 if (cBB->isSuccessor(PHIBB))
1304 PHI.addReg(FuncInfo->PHINodesToUpdate[pi].second).addMBB(cBB);
1308 SDB->BitTestCases.clear();
1310 // If the JumpTable record is filled in, then we need to emit a jump table.
1311 // Updating the PHI nodes is tricky in this case, since we need to determine
1312 // whether the PHI is a successor of the range check MBB or the jump table MBB
1313 for (unsigned i = 0, e = SDB->JTCases.size(); i != e; ++i) {
1314 // Lower header first, if it wasn't already lowered
1315 if (!SDB->JTCases[i].first.Emitted) {
1316 // Set the current basic block to the mbb we wish to insert the code into
1317 FuncInfo->MBB = SDB->JTCases[i].first.HeaderBB;
1318 FuncInfo->InsertPt = FuncInfo->MBB->end();
1320 SDB->visitJumpTableHeader(SDB->JTCases[i].second, SDB->JTCases[i].first,
1322 CurDAG->setRoot(SDB->getRoot());
1324 CodeGenAndEmitDAG();
1327 // Set the current basic block to the mbb we wish to insert the code into
1328 FuncInfo->MBB = SDB->JTCases[i].second.MBB;
1329 FuncInfo->InsertPt = FuncInfo->MBB->end();
1331 SDB->visitJumpTable(SDB->JTCases[i].second);
1332 CurDAG->setRoot(SDB->getRoot());
1334 CodeGenAndEmitDAG();
1337 for (unsigned pi = 0, pe = FuncInfo->PHINodesToUpdate.size();
1339 MachineInstrBuilder PHI(*MF, FuncInfo->PHINodesToUpdate[pi].first);
1340 MachineBasicBlock *PHIBB = PHI->getParent();
1341 assert(PHI->isPHI() &&
1342 "This is not a machine PHI node that we are updating!");
1343 // "default" BB. We can go there only from header BB.
1344 if (PHIBB == SDB->JTCases[i].second.Default)
1345 PHI.addReg(FuncInfo->PHINodesToUpdate[pi].second)
1346 .addMBB(SDB->JTCases[i].first.HeaderBB);
1347 // JT BB. Just iterate over successors here
1348 if (FuncInfo->MBB->isSuccessor(PHIBB))
1349 PHI.addReg(FuncInfo->PHINodesToUpdate[pi].second).addMBB(FuncInfo->MBB);
1352 SDB->JTCases.clear();
1354 // If the switch block involved a branch to one of the actual successors, we
1355 // need to update PHI nodes in that block.
1356 for (unsigned i = 0, e = FuncInfo->PHINodesToUpdate.size(); i != e; ++i) {
1357 MachineInstrBuilder PHI(*MF, FuncInfo->PHINodesToUpdate[i].first);
1358 assert(PHI->isPHI() &&
1359 "This is not a machine PHI node that we are updating!");
1360 if (FuncInfo->MBB->isSuccessor(PHI->getParent()))
1361 PHI.addReg(FuncInfo->PHINodesToUpdate[i].second).addMBB(FuncInfo->MBB);
1364 // If we generated any switch lowering information, build and codegen any
1365 // additional DAGs necessary.
1366 for (unsigned i = 0, e = SDB->SwitchCases.size(); i != e; ++i) {
1367 // Set the current basic block to the mbb we wish to insert the code into
1368 FuncInfo->MBB = SDB->SwitchCases[i].ThisBB;
1369 FuncInfo->InsertPt = FuncInfo->MBB->end();
1371 // Determine the unique successors.
1372 SmallVector<MachineBasicBlock *, 2> Succs;
1373 Succs.push_back(SDB->SwitchCases[i].TrueBB);
1374 if (SDB->SwitchCases[i].TrueBB != SDB->SwitchCases[i].FalseBB)
1375 Succs.push_back(SDB->SwitchCases[i].FalseBB);
1377 // Emit the code. Note that this could result in FuncInfo->MBB being split.
1378 SDB->visitSwitchCase(SDB->SwitchCases[i], FuncInfo->MBB);
1379 CurDAG->setRoot(SDB->getRoot());
1381 CodeGenAndEmitDAG();
1383 // Remember the last block, now that any splitting is done, for use in
1384 // populating PHI nodes in successors.
1385 MachineBasicBlock *ThisBB = FuncInfo->MBB;
1387 // Handle any PHI nodes in successors of this chunk, as if we were coming
1388 // from the original BB before switch expansion. Note that PHI nodes can
1389 // occur multiple times in PHINodesToUpdate. We have to be very careful to
1390 // handle them the right number of times.
1391 for (unsigned i = 0, e = Succs.size(); i != e; ++i) {
1392 FuncInfo->MBB = Succs[i];
1393 FuncInfo->InsertPt = FuncInfo->MBB->end();
1394 // FuncInfo->MBB may have been removed from the CFG if a branch was
1396 if (ThisBB->isSuccessor(FuncInfo->MBB)) {
1397 for (MachineBasicBlock::iterator
1398 MBBI = FuncInfo->MBB->begin(), MBBE = FuncInfo->MBB->end();
1399 MBBI != MBBE && MBBI->isPHI(); ++MBBI) {
1400 MachineInstrBuilder PHI(*MF, MBBI);
1401 // This value for this PHI node is recorded in PHINodesToUpdate.
1402 for (unsigned pn = 0; ; ++pn) {
1403 assert(pn != FuncInfo->PHINodesToUpdate.size() &&
1404 "Didn't find PHI entry!");
1405 if (FuncInfo->PHINodesToUpdate[pn].first == PHI) {
1406 PHI.addReg(FuncInfo->PHINodesToUpdate[pn].second).addMBB(ThisBB);
1414 SDB->SwitchCases.clear();
1418 /// Create the scheduler. If a specific scheduler was specified
1419 /// via the SchedulerRegistry, use it, otherwise select the
1420 /// one preferred by the target.
1422 ScheduleDAGSDNodes *SelectionDAGISel::CreateScheduler() {
1423 RegisterScheduler::FunctionPassCtor Ctor = RegisterScheduler::getDefault();
1427 RegisterScheduler::setDefault(Ctor);
1430 return Ctor(this, OptLevel);
1433 //===----------------------------------------------------------------------===//
1434 // Helper functions used by the generated instruction selector.
1435 //===----------------------------------------------------------------------===//
1436 // Calls to these methods are generated by tblgen.
1438 /// CheckAndMask - The isel is trying to match something like (and X, 255). If
1439 /// the dag combiner simplified the 255, we still want to match. RHS is the
1440 /// actual value in the DAG on the RHS of an AND, and DesiredMaskS is the value
1441 /// specified in the .td file (e.g. 255).
1442 bool SelectionDAGISel::CheckAndMask(SDValue LHS, ConstantSDNode *RHS,
1443 int64_t DesiredMaskS) const {
1444 const APInt &ActualMask = RHS->getAPIntValue();
1445 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS);
1447 // If the actual mask exactly matches, success!
1448 if (ActualMask == DesiredMask)
1451 // If the actual AND mask is allowing unallowed bits, this doesn't match.
1452 if (ActualMask.intersects(~DesiredMask))
1455 // Otherwise, the DAG Combiner may have proven that the value coming in is
1456 // either already zero or is not demanded. Check for known zero input bits.
1457 APInt NeededMask = DesiredMask & ~ActualMask;
1458 if (CurDAG->MaskedValueIsZero(LHS, NeededMask))
1461 // TODO: check to see if missing bits are just not demanded.
1463 // Otherwise, this pattern doesn't match.
1467 /// CheckOrMask - The isel is trying to match something like (or X, 255). If
1468 /// the dag combiner simplified the 255, we still want to match. RHS is the
1469 /// actual value in the DAG on the RHS of an OR, and DesiredMaskS is the value
1470 /// specified in the .td file (e.g. 255).
1471 bool SelectionDAGISel::CheckOrMask(SDValue LHS, ConstantSDNode *RHS,
1472 int64_t DesiredMaskS) const {
1473 const APInt &ActualMask = RHS->getAPIntValue();
1474 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS);
1476 // If the actual mask exactly matches, success!
1477 if (ActualMask == DesiredMask)
1480 // If the actual AND mask is allowing unallowed bits, this doesn't match.
1481 if (ActualMask.intersects(~DesiredMask))
1484 // Otherwise, the DAG Combiner may have proven that the value coming in is
1485 // either already zero or is not demanded. Check for known zero input bits.
1486 APInt NeededMask = DesiredMask & ~ActualMask;
1488 APInt KnownZero, KnownOne;
1489 CurDAG->ComputeMaskedBits(LHS, KnownZero, KnownOne);
1491 // If all the missing bits in the or are already known to be set, match!
1492 if ((NeededMask & KnownOne) == NeededMask)
1495 // TODO: check to see if missing bits are just not demanded.
1497 // Otherwise, this pattern doesn't match.
1502 /// SelectInlineAsmMemoryOperands - Calls to this are automatically generated
1503 /// by tblgen. Others should not call it.
1504 void SelectionDAGISel::
1505 SelectInlineAsmMemoryOperands(std::vector<SDValue> &Ops) {
1506 std::vector<SDValue> InOps;
1507 std::swap(InOps, Ops);
1509 Ops.push_back(InOps[InlineAsm::Op_InputChain]); // 0
1510 Ops.push_back(InOps[InlineAsm::Op_AsmString]); // 1
1511 Ops.push_back(InOps[InlineAsm::Op_MDNode]); // 2, !srcloc
1512 Ops.push_back(InOps[InlineAsm::Op_ExtraInfo]); // 3 (SideEffect, AlignStack)
1514 unsigned i = InlineAsm::Op_FirstOperand, e = InOps.size();
1515 if (InOps[e-1].getValueType() == MVT::Glue)
1516 --e; // Don't process a glue operand if it is here.
1519 unsigned Flags = cast<ConstantSDNode>(InOps[i])->getZExtValue();
1520 if (!InlineAsm::isMemKind(Flags)) {
1521 // Just skip over this operand, copying the operands verbatim.
1522 Ops.insert(Ops.end(), InOps.begin()+i,
1523 InOps.begin()+i+InlineAsm::getNumOperandRegisters(Flags) + 1);
1524 i += InlineAsm::getNumOperandRegisters(Flags) + 1;
1526 assert(InlineAsm::getNumOperandRegisters(Flags) == 1 &&
1527 "Memory operand with multiple values?");
1528 // Otherwise, this is a memory operand. Ask the target to select it.
1529 std::vector<SDValue> SelOps;
1530 if (SelectInlineAsmMemoryOperand(InOps[i+1], 'm', SelOps))
1531 report_fatal_error("Could not match memory address. Inline asm"
1534 // Add this to the output node.
1536 InlineAsm::getFlagWord(InlineAsm::Kind_Mem, SelOps.size());
1537 Ops.push_back(CurDAG->getTargetConstant(NewFlags, MVT::i32));
1538 Ops.insert(Ops.end(), SelOps.begin(), SelOps.end());
1543 // Add the glue input back if present.
1544 if (e != InOps.size())
1545 Ops.push_back(InOps.back());
1548 /// findGlueUse - Return use of MVT::Glue value produced by the specified
1551 static SDNode *findGlueUse(SDNode *N) {
1552 unsigned FlagResNo = N->getNumValues()-1;
1553 for (SDNode::use_iterator I = N->use_begin(), E = N->use_end(); I != E; ++I) {
1554 SDUse &Use = I.getUse();
1555 if (Use.getResNo() == FlagResNo)
1556 return Use.getUser();
1561 /// findNonImmUse - Return true if "Use" is a non-immediate use of "Def".
1562 /// This function recursively traverses up the operand chain, ignoring
1564 static bool findNonImmUse(SDNode *Use, SDNode* Def, SDNode *ImmedUse,
1565 SDNode *Root, SmallPtrSet<SDNode*, 16> &Visited,
1566 bool IgnoreChains) {
1567 // The NodeID's are given uniques ID's where a node ID is guaranteed to be
1568 // greater than all of its (recursive) operands. If we scan to a point where
1569 // 'use' is smaller than the node we're scanning for, then we know we will
1572 // The Use may be -1 (unassigned) if it is a newly allocated node. This can
1573 // happen because we scan down to newly selected nodes in the case of glue
1575 if ((Use->getNodeId() < Def->getNodeId() && Use->getNodeId() != -1))
1578 // Don't revisit nodes if we already scanned it and didn't fail, we know we
1579 // won't fail if we scan it again.
1580 if (!Visited.insert(Use))
1583 for (unsigned i = 0, e = Use->getNumOperands(); i != e; ++i) {
1584 // Ignore chain uses, they are validated by HandleMergeInputChains.
1585 if (Use->getOperand(i).getValueType() == MVT::Other && IgnoreChains)
1588 SDNode *N = Use->getOperand(i).getNode();
1590 if (Use == ImmedUse || Use == Root)
1591 continue; // We are not looking for immediate use.
1596 // Traverse up the operand chain.
1597 if (findNonImmUse(N, Def, ImmedUse, Root, Visited, IgnoreChains))
1603 /// IsProfitableToFold - Returns true if it's profitable to fold the specific
1604 /// operand node N of U during instruction selection that starts at Root.
1605 bool SelectionDAGISel::IsProfitableToFold(SDValue N, SDNode *U,
1606 SDNode *Root) const {
1607 if (OptLevel == CodeGenOpt::None) return false;
1608 return N.hasOneUse();
1611 /// IsLegalToFold - Returns true if the specific operand node N of
1612 /// U can be folded during instruction selection that starts at Root.
1613 bool SelectionDAGISel::IsLegalToFold(SDValue N, SDNode *U, SDNode *Root,
1614 CodeGenOpt::Level OptLevel,
1615 bool IgnoreChains) {
1616 if (OptLevel == CodeGenOpt::None) return false;
1618 // If Root use can somehow reach N through a path that that doesn't contain
1619 // U then folding N would create a cycle. e.g. In the following
1620 // diagram, Root can reach N through X. If N is folded into into Root, then
1621 // X is both a predecessor and a successor of U.
1632 // * indicates nodes to be folded together.
1634 // If Root produces glue, then it gets (even more) interesting. Since it
1635 // will be "glued" together with its glue use in the scheduler, we need to
1636 // check if it might reach N.
1655 // If GU (glue use) indirectly reaches N (the load), and Root folds N
1656 // (call it Fold), then X is a predecessor of GU and a successor of
1657 // Fold. But since Fold and GU are glued together, this will create
1658 // a cycle in the scheduling graph.
1660 // If the node has glue, walk down the graph to the "lowest" node in the
1662 EVT VT = Root->getValueType(Root->getNumValues()-1);
1663 while (VT == MVT::Glue) {
1664 SDNode *GU = findGlueUse(Root);
1668 VT = Root->getValueType(Root->getNumValues()-1);
1670 // If our query node has a glue result with a use, we've walked up it. If
1671 // the user (which has already been selected) has a chain or indirectly uses
1672 // the chain, our WalkChainUsers predicate will not consider it. Because of
1673 // this, we cannot ignore chains in this predicate.
1674 IgnoreChains = false;
1678 SmallPtrSet<SDNode*, 16> Visited;
1679 return !findNonImmUse(Root, N.getNode(), U, Root, Visited, IgnoreChains);
1682 SDNode *SelectionDAGISel::Select_INLINEASM(SDNode *N) {
1683 std::vector<SDValue> Ops(N->op_begin(), N->op_end());
1684 SelectInlineAsmMemoryOperands(Ops);
1686 EVT VTs[] = { MVT::Other, MVT::Glue };
1687 SDValue New = CurDAG->getNode(ISD::INLINEASM, N->getDebugLoc(),
1688 VTs, &Ops[0], Ops.size());
1690 return New.getNode();
1693 SDNode *SelectionDAGISel::Select_UNDEF(SDNode *N) {
1694 return CurDAG->SelectNodeTo(N, TargetOpcode::IMPLICIT_DEF,N->getValueType(0));
1697 /// GetVBR - decode a vbr encoding whose top bit is set.
1698 LLVM_ATTRIBUTE_ALWAYS_INLINE static uint64_t
1699 GetVBR(uint64_t Val, const unsigned char *MatcherTable, unsigned &Idx) {
1700 assert(Val >= 128 && "Not a VBR");
1701 Val &= 127; // Remove first vbr bit.
1706 NextBits = MatcherTable[Idx++];
1707 Val |= (NextBits&127) << Shift;
1709 } while (NextBits & 128);
1715 /// UpdateChainsAndGlue - When a match is complete, this method updates uses of
1716 /// interior glue and chain results to use the new glue and chain results.
1717 void SelectionDAGISel::
1718 UpdateChainsAndGlue(SDNode *NodeToMatch, SDValue InputChain,
1719 const SmallVectorImpl<SDNode*> &ChainNodesMatched,
1721 const SmallVectorImpl<SDNode*> &GlueResultNodesMatched,
1722 bool isMorphNodeTo) {
1723 SmallVector<SDNode*, 4> NowDeadNodes;
1725 // Now that all the normal results are replaced, we replace the chain and
1726 // glue results if present.
1727 if (!ChainNodesMatched.empty()) {
1728 assert(InputChain.getNode() != 0 &&
1729 "Matched input chains but didn't produce a chain");
1730 // Loop over all of the nodes we matched that produced a chain result.
1731 // Replace all the chain results with the final chain we ended up with.
1732 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) {
1733 SDNode *ChainNode = ChainNodesMatched[i];
1735 // If this node was already deleted, don't look at it.
1736 if (ChainNode->getOpcode() == ISD::DELETED_NODE)
1739 // Don't replace the results of the root node if we're doing a
1741 if (ChainNode == NodeToMatch && isMorphNodeTo)
1744 SDValue ChainVal = SDValue(ChainNode, ChainNode->getNumValues()-1);
1745 if (ChainVal.getValueType() == MVT::Glue)
1746 ChainVal = ChainVal.getValue(ChainVal->getNumValues()-2);
1747 assert(ChainVal.getValueType() == MVT::Other && "Not a chain?");
1748 CurDAG->ReplaceAllUsesOfValueWith(ChainVal, InputChain);
1750 // If the node became dead and we haven't already seen it, delete it.
1751 if (ChainNode->use_empty() &&
1752 !std::count(NowDeadNodes.begin(), NowDeadNodes.end(), ChainNode))
1753 NowDeadNodes.push_back(ChainNode);
1757 // If the result produces glue, update any glue results in the matched
1758 // pattern with the glue result.
1759 if (InputGlue.getNode() != 0) {
1760 // Handle any interior nodes explicitly marked.
1761 for (unsigned i = 0, e = GlueResultNodesMatched.size(); i != e; ++i) {
1762 SDNode *FRN = GlueResultNodesMatched[i];
1764 // If this node was already deleted, don't look at it.
1765 if (FRN->getOpcode() == ISD::DELETED_NODE)
1768 assert(FRN->getValueType(FRN->getNumValues()-1) == MVT::Glue &&
1769 "Doesn't have a glue result");
1770 CurDAG->ReplaceAllUsesOfValueWith(SDValue(FRN, FRN->getNumValues()-1),
1773 // If the node became dead and we haven't already seen it, delete it.
1774 if (FRN->use_empty() &&
1775 !std::count(NowDeadNodes.begin(), NowDeadNodes.end(), FRN))
1776 NowDeadNodes.push_back(FRN);
1780 if (!NowDeadNodes.empty())
1781 CurDAG->RemoveDeadNodes(NowDeadNodes);
1783 DEBUG(dbgs() << "ISEL: Match complete!\n");
1789 CR_LeadsToInteriorNode
1792 /// WalkChainUsers - Walk down the users of the specified chained node that is
1793 /// part of the pattern we're matching, looking at all of the users we find.
1794 /// This determines whether something is an interior node, whether we have a
1795 /// non-pattern node in between two pattern nodes (which prevent folding because
1796 /// it would induce a cycle) and whether we have a TokenFactor node sandwiched
1797 /// between pattern nodes (in which case the TF becomes part of the pattern).
1799 /// The walk we do here is guaranteed to be small because we quickly get down to
1800 /// already selected nodes "below" us.
1802 WalkChainUsers(const SDNode *ChainedNode,
1803 SmallVectorImpl<SDNode*> &ChainedNodesInPattern,
1804 SmallVectorImpl<SDNode*> &InteriorChainedNodes) {
1805 ChainResult Result = CR_Simple;
1807 for (SDNode::use_iterator UI = ChainedNode->use_begin(),
1808 E = ChainedNode->use_end(); UI != E; ++UI) {
1809 // Make sure the use is of the chain, not some other value we produce.
1810 if (UI.getUse().getValueType() != MVT::Other) continue;
1814 // If we see an already-selected machine node, then we've gone beyond the
1815 // pattern that we're selecting down into the already selected chunk of the
1817 if (User->isMachineOpcode() ||
1818 User->getOpcode() == ISD::HANDLENODE) // Root of the graph.
1821 unsigned UserOpcode = User->getOpcode();
1822 if (UserOpcode == ISD::CopyToReg ||
1823 UserOpcode == ISD::CopyFromReg ||
1824 UserOpcode == ISD::INLINEASM ||
1825 UserOpcode == ISD::EH_LABEL ||
1826 UserOpcode == ISD::LIFETIME_START ||
1827 UserOpcode == ISD::LIFETIME_END) {
1828 // If their node ID got reset to -1 then they've already been selected.
1829 // Treat them like a MachineOpcode.
1830 if (User->getNodeId() == -1)
1834 // If we have a TokenFactor, we handle it specially.
1835 if (User->getOpcode() != ISD::TokenFactor) {
1836 // If the node isn't a token factor and isn't part of our pattern, then it
1837 // must be a random chained node in between two nodes we're selecting.
1838 // This happens when we have something like:
1843 // Because we structurally match the load/store as a read/modify/write,
1844 // but the call is chained between them. We cannot fold in this case
1845 // because it would induce a cycle in the graph.
1846 if (!std::count(ChainedNodesInPattern.begin(),
1847 ChainedNodesInPattern.end(), User))
1848 return CR_InducesCycle;
1850 // Otherwise we found a node that is part of our pattern. For example in:
1854 // This would happen when we're scanning down from the load and see the
1855 // store as a user. Record that there is a use of ChainedNode that is
1856 // part of the pattern and keep scanning uses.
1857 Result = CR_LeadsToInteriorNode;
1858 InteriorChainedNodes.push_back(User);
1862 // If we found a TokenFactor, there are two cases to consider: first if the
1863 // TokenFactor is just hanging "below" the pattern we're matching (i.e. no
1864 // uses of the TF are in our pattern) we just want to ignore it. Second,
1865 // the TokenFactor can be sandwiched in between two chained nodes, like so:
1871 // | \ DAG's like cheese
1874 // [TokenFactor] [Op]
1881 // In this case, the TokenFactor becomes part of our match and we rewrite it
1882 // as a new TokenFactor.
1884 // To distinguish these two cases, do a recursive walk down the uses.
1885 switch (WalkChainUsers(User, ChainedNodesInPattern, InteriorChainedNodes)) {
1887 // If the uses of the TokenFactor are just already-selected nodes, ignore
1888 // it, it is "below" our pattern.
1890 case CR_InducesCycle:
1891 // If the uses of the TokenFactor lead to nodes that are not part of our
1892 // pattern that are not selected, folding would turn this into a cycle,
1894 return CR_InducesCycle;
1895 case CR_LeadsToInteriorNode:
1896 break; // Otherwise, keep processing.
1899 // Okay, we know we're in the interesting interior case. The TokenFactor
1900 // is now going to be considered part of the pattern so that we rewrite its
1901 // uses (it may have uses that are not part of the pattern) with the
1902 // ultimate chain result of the generated code. We will also add its chain
1903 // inputs as inputs to the ultimate TokenFactor we create.
1904 Result = CR_LeadsToInteriorNode;
1905 ChainedNodesInPattern.push_back(User);
1906 InteriorChainedNodes.push_back(User);
1913 /// HandleMergeInputChains - This implements the OPC_EmitMergeInputChains
1914 /// operation for when the pattern matched at least one node with a chains. The
1915 /// input vector contains a list of all of the chained nodes that we match. We
1916 /// must determine if this is a valid thing to cover (i.e. matching it won't
1917 /// induce cycles in the DAG) and if so, creating a TokenFactor node. that will
1918 /// be used as the input node chain for the generated nodes.
1920 HandleMergeInputChains(SmallVectorImpl<SDNode*> &ChainNodesMatched,
1921 SelectionDAG *CurDAG) {
1922 // Walk all of the chained nodes we've matched, recursively scanning down the
1923 // users of the chain result. This adds any TokenFactor nodes that are caught
1924 // in between chained nodes to the chained and interior nodes list.
1925 SmallVector<SDNode*, 3> InteriorChainedNodes;
1926 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) {
1927 if (WalkChainUsers(ChainNodesMatched[i], ChainNodesMatched,
1928 InteriorChainedNodes) == CR_InducesCycle)
1929 return SDValue(); // Would induce a cycle.
1932 // Okay, we have walked all the matched nodes and collected TokenFactor nodes
1933 // that we are interested in. Form our input TokenFactor node.
1934 SmallVector<SDValue, 3> InputChains;
1935 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) {
1936 // Add the input chain of this node to the InputChains list (which will be
1937 // the operands of the generated TokenFactor) if it's not an interior node.
1938 SDNode *N = ChainNodesMatched[i];
1939 if (N->getOpcode() != ISD::TokenFactor) {
1940 if (std::count(InteriorChainedNodes.begin(),InteriorChainedNodes.end(),N))
1943 // Otherwise, add the input chain.
1944 SDValue InChain = ChainNodesMatched[i]->getOperand(0);
1945 assert(InChain.getValueType() == MVT::Other && "Not a chain");
1946 InputChains.push_back(InChain);
1950 // If we have a token factor, we want to add all inputs of the token factor
1951 // that are not part of the pattern we're matching.
1952 for (unsigned op = 0, e = N->getNumOperands(); op != e; ++op) {
1953 if (!std::count(ChainNodesMatched.begin(), ChainNodesMatched.end(),
1954 N->getOperand(op).getNode()))
1955 InputChains.push_back(N->getOperand(op));
1960 if (InputChains.size() == 1)
1961 return InputChains[0];
1962 return CurDAG->getNode(ISD::TokenFactor, ChainNodesMatched[0]->getDebugLoc(),
1963 MVT::Other, &InputChains[0], InputChains.size());
1966 /// MorphNode - Handle morphing a node in place for the selector.
1967 SDNode *SelectionDAGISel::
1968 MorphNode(SDNode *Node, unsigned TargetOpc, SDVTList VTList,
1969 const SDValue *Ops, unsigned NumOps, unsigned EmitNodeInfo) {
1970 // It is possible we're using MorphNodeTo to replace a node with no
1971 // normal results with one that has a normal result (or we could be
1972 // adding a chain) and the input could have glue and chains as well.
1973 // In this case we need to shift the operands down.
1974 // FIXME: This is a horrible hack and broken in obscure cases, no worse
1975 // than the old isel though.
1976 int OldGlueResultNo = -1, OldChainResultNo = -1;
1978 unsigned NTMNumResults = Node->getNumValues();
1979 if (Node->getValueType(NTMNumResults-1) == MVT::Glue) {
1980 OldGlueResultNo = NTMNumResults-1;
1981 if (NTMNumResults != 1 &&
1982 Node->getValueType(NTMNumResults-2) == MVT::Other)
1983 OldChainResultNo = NTMNumResults-2;
1984 } else if (Node->getValueType(NTMNumResults-1) == MVT::Other)
1985 OldChainResultNo = NTMNumResults-1;
1987 // Call the underlying SelectionDAG routine to do the transmogrification. Note
1988 // that this deletes operands of the old node that become dead.
1989 SDNode *Res = CurDAG->MorphNodeTo(Node, ~TargetOpc, VTList, Ops, NumOps);
1991 // MorphNodeTo can operate in two ways: if an existing node with the
1992 // specified operands exists, it can just return it. Otherwise, it
1993 // updates the node in place to have the requested operands.
1995 // If we updated the node in place, reset the node ID. To the isel,
1996 // this should be just like a newly allocated machine node.
2000 unsigned ResNumResults = Res->getNumValues();
2001 // Move the glue if needed.
2002 if ((EmitNodeInfo & OPFL_GlueOutput) && OldGlueResultNo != -1 &&
2003 (unsigned)OldGlueResultNo != ResNumResults-1)
2004 CurDAG->ReplaceAllUsesOfValueWith(SDValue(Node, OldGlueResultNo),
2005 SDValue(Res, ResNumResults-1));
2007 if ((EmitNodeInfo & OPFL_GlueOutput) != 0)
2010 // Move the chain reference if needed.
2011 if ((EmitNodeInfo & OPFL_Chain) && OldChainResultNo != -1 &&
2012 (unsigned)OldChainResultNo != ResNumResults-1)
2013 CurDAG->ReplaceAllUsesOfValueWith(SDValue(Node, OldChainResultNo),
2014 SDValue(Res, ResNumResults-1));
2016 // Otherwise, no replacement happened because the node already exists. Replace
2017 // Uses of the old node with the new one.
2019 CurDAG->ReplaceAllUsesWith(Node, Res);
2024 /// CheckSame - Implements OP_CheckSame.
2025 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2026 CheckSame(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2028 const SmallVectorImpl<std::pair<SDValue, SDNode*> > &RecordedNodes) {
2029 // Accept if it is exactly the same as a previously recorded node.
2030 unsigned RecNo = MatcherTable[MatcherIndex++];
2031 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2032 return N == RecordedNodes[RecNo].first;
2035 /// CheckPatternPredicate - Implements OP_CheckPatternPredicate.
2036 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2037 CheckPatternPredicate(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2038 const SelectionDAGISel &SDISel) {
2039 return SDISel.CheckPatternPredicate(MatcherTable[MatcherIndex++]);
2042 /// CheckNodePredicate - Implements OP_CheckNodePredicate.
2043 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2044 CheckNodePredicate(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2045 const SelectionDAGISel &SDISel, SDNode *N) {
2046 return SDISel.CheckNodePredicate(N, MatcherTable[MatcherIndex++]);
2049 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2050 CheckOpcode(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2052 uint16_t Opc = MatcherTable[MatcherIndex++];
2053 Opc |= (unsigned short)MatcherTable[MatcherIndex++] << 8;
2054 return N->getOpcode() == Opc;
2057 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2058 CheckType(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2059 SDValue N, const TargetLowering &TLI) {
2060 MVT::SimpleValueType VT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2061 if (N.getValueType() == VT) return true;
2063 // Handle the case when VT is iPTR.
2064 return VT == MVT::iPTR && N.getValueType() == TLI.getPointerTy();
2067 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2068 CheckChildType(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2069 SDValue N, const TargetLowering &TLI,
2071 if (ChildNo >= N.getNumOperands())
2072 return false; // Match fails if out of range child #.
2073 return ::CheckType(MatcherTable, MatcherIndex, N.getOperand(ChildNo), TLI);
2077 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2078 CheckCondCode(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2080 return cast<CondCodeSDNode>(N)->get() ==
2081 (ISD::CondCode)MatcherTable[MatcherIndex++];
2084 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2085 CheckValueType(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2086 SDValue N, const TargetLowering &TLI) {
2087 MVT::SimpleValueType VT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2088 if (cast<VTSDNode>(N)->getVT() == VT)
2091 // Handle the case when VT is iPTR.
2092 return VT == MVT::iPTR && cast<VTSDNode>(N)->getVT() == TLI.getPointerTy();
2095 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2096 CheckInteger(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2098 int64_t Val = MatcherTable[MatcherIndex++];
2100 Val = GetVBR(Val, MatcherTable, MatcherIndex);
2102 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N);
2103 return C != 0 && C->getSExtValue() == Val;
2106 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2107 CheckAndImm(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2108 SDValue N, const SelectionDAGISel &SDISel) {
2109 int64_t Val = MatcherTable[MatcherIndex++];
2111 Val = GetVBR(Val, MatcherTable, MatcherIndex);
2113 if (N->getOpcode() != ISD::AND) return false;
2115 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
2116 return C != 0 && SDISel.CheckAndMask(N.getOperand(0), C, Val);
2119 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2120 CheckOrImm(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2121 SDValue N, const SelectionDAGISel &SDISel) {
2122 int64_t Val = MatcherTable[MatcherIndex++];
2124 Val = GetVBR(Val, MatcherTable, MatcherIndex);
2126 if (N->getOpcode() != ISD::OR) return false;
2128 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
2129 return C != 0 && SDISel.CheckOrMask(N.getOperand(0), C, Val);
2132 /// IsPredicateKnownToFail - If we know how and can do so without pushing a
2133 /// scope, evaluate the current node. If the current predicate is known to
2134 /// fail, set Result=true and return anything. If the current predicate is
2135 /// known to pass, set Result=false and return the MatcherIndex to continue
2136 /// with. If the current predicate is unknown, set Result=false and return the
2137 /// MatcherIndex to continue with.
2138 static unsigned IsPredicateKnownToFail(const unsigned char *Table,
2139 unsigned Index, SDValue N,
2141 const SelectionDAGISel &SDISel,
2142 SmallVectorImpl<std::pair<SDValue, SDNode*> > &RecordedNodes) {
2143 switch (Table[Index++]) {
2146 return Index-1; // Could not evaluate this predicate.
2147 case SelectionDAGISel::OPC_CheckSame:
2148 Result = !::CheckSame(Table, Index, N, RecordedNodes);
2150 case SelectionDAGISel::OPC_CheckPatternPredicate:
2151 Result = !::CheckPatternPredicate(Table, Index, SDISel);
2153 case SelectionDAGISel::OPC_CheckPredicate:
2154 Result = !::CheckNodePredicate(Table, Index, SDISel, N.getNode());
2156 case SelectionDAGISel::OPC_CheckOpcode:
2157 Result = !::CheckOpcode(Table, Index, N.getNode());
2159 case SelectionDAGISel::OPC_CheckType:
2160 Result = !::CheckType(Table, Index, N, SDISel.TLI);
2162 case SelectionDAGISel::OPC_CheckChild0Type:
2163 case SelectionDAGISel::OPC_CheckChild1Type:
2164 case SelectionDAGISel::OPC_CheckChild2Type:
2165 case SelectionDAGISel::OPC_CheckChild3Type:
2166 case SelectionDAGISel::OPC_CheckChild4Type:
2167 case SelectionDAGISel::OPC_CheckChild5Type:
2168 case SelectionDAGISel::OPC_CheckChild6Type:
2169 case SelectionDAGISel::OPC_CheckChild7Type:
2170 Result = !::CheckChildType(Table, Index, N, SDISel.TLI,
2171 Table[Index-1] - SelectionDAGISel::OPC_CheckChild0Type);
2173 case SelectionDAGISel::OPC_CheckCondCode:
2174 Result = !::CheckCondCode(Table, Index, N);
2176 case SelectionDAGISel::OPC_CheckValueType:
2177 Result = !::CheckValueType(Table, Index, N, SDISel.TLI);
2179 case SelectionDAGISel::OPC_CheckInteger:
2180 Result = !::CheckInteger(Table, Index, N);
2182 case SelectionDAGISel::OPC_CheckAndImm:
2183 Result = !::CheckAndImm(Table, Index, N, SDISel);
2185 case SelectionDAGISel::OPC_CheckOrImm:
2186 Result = !::CheckOrImm(Table, Index, N, SDISel);
2194 /// FailIndex - If this match fails, this is the index to continue with.
2197 /// NodeStack - The node stack when the scope was formed.
2198 SmallVector<SDValue, 4> NodeStack;
2200 /// NumRecordedNodes - The number of recorded nodes when the scope was formed.
2201 unsigned NumRecordedNodes;
2203 /// NumMatchedMemRefs - The number of matched memref entries.
2204 unsigned NumMatchedMemRefs;
2206 /// InputChain/InputGlue - The current chain/glue
2207 SDValue InputChain, InputGlue;
2209 /// HasChainNodesMatched - True if the ChainNodesMatched list is non-empty.
2210 bool HasChainNodesMatched, HasGlueResultNodesMatched;
2215 SDNode *SelectionDAGISel::
2216 SelectCodeCommon(SDNode *NodeToMatch, const unsigned char *MatcherTable,
2217 unsigned TableSize) {
2218 // FIXME: Should these even be selected? Handle these cases in the caller?
2219 switch (NodeToMatch->getOpcode()) {
2222 case ISD::EntryToken: // These nodes remain the same.
2223 case ISD::BasicBlock:
2225 case ISD::RegisterMask:
2226 //case ISD::VALUETYPE:
2227 //case ISD::CONDCODE:
2228 case ISD::HANDLENODE:
2229 case ISD::MDNODE_SDNODE:
2230 case ISD::TargetConstant:
2231 case ISD::TargetConstantFP:
2232 case ISD::TargetConstantPool:
2233 case ISD::TargetFrameIndex:
2234 case ISD::TargetExternalSymbol:
2235 case ISD::TargetBlockAddress:
2236 case ISD::TargetJumpTable:
2237 case ISD::TargetGlobalTLSAddress:
2238 case ISD::TargetGlobalAddress:
2239 case ISD::TokenFactor:
2240 case ISD::CopyFromReg:
2241 case ISD::CopyToReg:
2243 case ISD::LIFETIME_START:
2244 case ISD::LIFETIME_END:
2245 NodeToMatch->setNodeId(-1); // Mark selected.
2247 case ISD::AssertSext:
2248 case ISD::AssertZext:
2249 CurDAG->ReplaceAllUsesOfValueWith(SDValue(NodeToMatch, 0),
2250 NodeToMatch->getOperand(0));
2252 case ISD::INLINEASM: return Select_INLINEASM(NodeToMatch);
2253 case ISD::UNDEF: return Select_UNDEF(NodeToMatch);
2256 assert(!NodeToMatch->isMachineOpcode() && "Node already selected!");
2258 // Set up the node stack with NodeToMatch as the only node on the stack.
2259 SmallVector<SDValue, 8> NodeStack;
2260 SDValue N = SDValue(NodeToMatch, 0);
2261 NodeStack.push_back(N);
2263 // MatchScopes - Scopes used when matching, if a match failure happens, this
2264 // indicates where to continue checking.
2265 SmallVector<MatchScope, 8> MatchScopes;
2267 // RecordedNodes - This is the set of nodes that have been recorded by the
2268 // state machine. The second value is the parent of the node, or null if the
2269 // root is recorded.
2270 SmallVector<std::pair<SDValue, SDNode*>, 8> RecordedNodes;
2272 // MatchedMemRefs - This is the set of MemRef's we've seen in the input
2274 SmallVector<MachineMemOperand*, 2> MatchedMemRefs;
2276 // These are the current input chain and glue for use when generating nodes.
2277 // Various Emit operations change these. For example, emitting a copytoreg
2278 // uses and updates these.
2279 SDValue InputChain, InputGlue;
2281 // ChainNodesMatched - If a pattern matches nodes that have input/output
2282 // chains, the OPC_EmitMergeInputChains operation is emitted which indicates
2283 // which ones they are. The result is captured into this list so that we can
2284 // update the chain results when the pattern is complete.
2285 SmallVector<SDNode*, 3> ChainNodesMatched;
2286 SmallVector<SDNode*, 3> GlueResultNodesMatched;
2288 DEBUG(dbgs() << "ISEL: Starting pattern match on root node: ";
2289 NodeToMatch->dump(CurDAG);
2292 // Determine where to start the interpreter. Normally we start at opcode #0,
2293 // but if the state machine starts with an OPC_SwitchOpcode, then we
2294 // accelerate the first lookup (which is guaranteed to be hot) with the
2295 // OpcodeOffset table.
2296 unsigned MatcherIndex = 0;
2298 if (!OpcodeOffset.empty()) {
2299 // Already computed the OpcodeOffset table, just index into it.
2300 if (N.getOpcode() < OpcodeOffset.size())
2301 MatcherIndex = OpcodeOffset[N.getOpcode()];
2302 DEBUG(dbgs() << " Initial Opcode index to " << MatcherIndex << "\n");
2304 } else if (MatcherTable[0] == OPC_SwitchOpcode) {
2305 // Otherwise, the table isn't computed, but the state machine does start
2306 // with an OPC_SwitchOpcode instruction. Populate the table now, since this
2307 // is the first time we're selecting an instruction.
2310 // Get the size of this case.
2311 unsigned CaseSize = MatcherTable[Idx++];
2313 CaseSize = GetVBR(CaseSize, MatcherTable, Idx);
2314 if (CaseSize == 0) break;
2316 // Get the opcode, add the index to the table.
2317 uint16_t Opc = MatcherTable[Idx++];
2318 Opc |= (unsigned short)MatcherTable[Idx++] << 8;
2319 if (Opc >= OpcodeOffset.size())
2320 OpcodeOffset.resize((Opc+1)*2);
2321 OpcodeOffset[Opc] = Idx;
2325 // Okay, do the lookup for the first opcode.
2326 if (N.getOpcode() < OpcodeOffset.size())
2327 MatcherIndex = OpcodeOffset[N.getOpcode()];
2331 assert(MatcherIndex < TableSize && "Invalid index");
2333 unsigned CurrentOpcodeIndex = MatcherIndex;
2335 BuiltinOpcodes Opcode = (BuiltinOpcodes)MatcherTable[MatcherIndex++];
2338 // Okay, the semantics of this operation are that we should push a scope
2339 // then evaluate the first child. However, pushing a scope only to have
2340 // the first check fail (which then pops it) is inefficient. If we can
2341 // determine immediately that the first check (or first several) will
2342 // immediately fail, don't even bother pushing a scope for them.
2346 unsigned NumToSkip = MatcherTable[MatcherIndex++];
2347 if (NumToSkip & 128)
2348 NumToSkip = GetVBR(NumToSkip, MatcherTable, MatcherIndex);
2349 // Found the end of the scope with no match.
2350 if (NumToSkip == 0) {
2355 FailIndex = MatcherIndex+NumToSkip;
2357 unsigned MatcherIndexOfPredicate = MatcherIndex;
2358 (void)MatcherIndexOfPredicate; // silence warning.
2360 // If we can't evaluate this predicate without pushing a scope (e.g. if
2361 // it is a 'MoveParent') or if the predicate succeeds on this node, we
2362 // push the scope and evaluate the full predicate chain.
2364 MatcherIndex = IsPredicateKnownToFail(MatcherTable, MatcherIndex, N,
2365 Result, *this, RecordedNodes);
2369 DEBUG(dbgs() << " Skipped scope entry (due to false predicate) at "
2370 << "index " << MatcherIndexOfPredicate
2371 << ", continuing at " << FailIndex << "\n");
2372 ++NumDAGIselRetries;
2374 // Otherwise, we know that this case of the Scope is guaranteed to fail,
2375 // move to the next case.
2376 MatcherIndex = FailIndex;
2379 // If the whole scope failed to match, bail.
2380 if (FailIndex == 0) break;
2382 // Push a MatchScope which indicates where to go if the first child fails
2384 MatchScope NewEntry;
2385 NewEntry.FailIndex = FailIndex;
2386 NewEntry.NodeStack.append(NodeStack.begin(), NodeStack.end());
2387 NewEntry.NumRecordedNodes = RecordedNodes.size();
2388 NewEntry.NumMatchedMemRefs = MatchedMemRefs.size();
2389 NewEntry.InputChain = InputChain;
2390 NewEntry.InputGlue = InputGlue;
2391 NewEntry.HasChainNodesMatched = !ChainNodesMatched.empty();
2392 NewEntry.HasGlueResultNodesMatched = !GlueResultNodesMatched.empty();
2393 MatchScopes.push_back(NewEntry);
2396 case OPC_RecordNode: {
2397 // Remember this node, it may end up being an operand in the pattern.
2399 if (NodeStack.size() > 1)
2400 Parent = NodeStack[NodeStack.size()-2].getNode();
2401 RecordedNodes.push_back(std::make_pair(N, Parent));
2405 case OPC_RecordChild0: case OPC_RecordChild1:
2406 case OPC_RecordChild2: case OPC_RecordChild3:
2407 case OPC_RecordChild4: case OPC_RecordChild5:
2408 case OPC_RecordChild6: case OPC_RecordChild7: {
2409 unsigned ChildNo = Opcode-OPC_RecordChild0;
2410 if (ChildNo >= N.getNumOperands())
2411 break; // Match fails if out of range child #.
2413 RecordedNodes.push_back(std::make_pair(N->getOperand(ChildNo),
2417 case OPC_RecordMemRef:
2418 MatchedMemRefs.push_back(cast<MemSDNode>(N)->getMemOperand());
2421 case OPC_CaptureGlueInput:
2422 // If the current node has an input glue, capture it in InputGlue.
2423 if (N->getNumOperands() != 0 &&
2424 N->getOperand(N->getNumOperands()-1).getValueType() == MVT::Glue)
2425 InputGlue = N->getOperand(N->getNumOperands()-1);
2428 case OPC_MoveChild: {
2429 unsigned ChildNo = MatcherTable[MatcherIndex++];
2430 if (ChildNo >= N.getNumOperands())
2431 break; // Match fails if out of range child #.
2432 N = N.getOperand(ChildNo);
2433 NodeStack.push_back(N);
2437 case OPC_MoveParent:
2438 // Pop the current node off the NodeStack.
2439 NodeStack.pop_back();
2440 assert(!NodeStack.empty() && "Node stack imbalance!");
2441 N = NodeStack.back();
2445 if (!::CheckSame(MatcherTable, MatcherIndex, N, RecordedNodes)) break;
2447 case OPC_CheckPatternPredicate:
2448 if (!::CheckPatternPredicate(MatcherTable, MatcherIndex, *this)) break;
2450 case OPC_CheckPredicate:
2451 if (!::CheckNodePredicate(MatcherTable, MatcherIndex, *this,
2455 case OPC_CheckComplexPat: {
2456 unsigned CPNum = MatcherTable[MatcherIndex++];
2457 unsigned RecNo = MatcherTable[MatcherIndex++];
2458 assert(RecNo < RecordedNodes.size() && "Invalid CheckComplexPat");
2459 if (!CheckComplexPattern(NodeToMatch, RecordedNodes[RecNo].second,
2460 RecordedNodes[RecNo].first, CPNum,
2465 case OPC_CheckOpcode:
2466 if (!::CheckOpcode(MatcherTable, MatcherIndex, N.getNode())) break;
2470 if (!::CheckType(MatcherTable, MatcherIndex, N, TLI)) break;
2473 case OPC_SwitchOpcode: {
2474 unsigned CurNodeOpcode = N.getOpcode();
2475 unsigned SwitchStart = MatcherIndex-1; (void)SwitchStart;
2478 // Get the size of this case.
2479 CaseSize = MatcherTable[MatcherIndex++];
2481 CaseSize = GetVBR(CaseSize, MatcherTable, MatcherIndex);
2482 if (CaseSize == 0) break;
2484 uint16_t Opc = MatcherTable[MatcherIndex++];
2485 Opc |= (unsigned short)MatcherTable[MatcherIndex++] << 8;
2487 // If the opcode matches, then we will execute this case.
2488 if (CurNodeOpcode == Opc)
2491 // Otherwise, skip over this case.
2492 MatcherIndex += CaseSize;
2495 // If no cases matched, bail out.
2496 if (CaseSize == 0) break;
2498 // Otherwise, execute the case we found.
2499 DEBUG(dbgs() << " OpcodeSwitch from " << SwitchStart
2500 << " to " << MatcherIndex << "\n");
2504 case OPC_SwitchType: {
2505 MVT CurNodeVT = N.getValueType().getSimpleVT();
2506 unsigned SwitchStart = MatcherIndex-1; (void)SwitchStart;
2509 // Get the size of this case.
2510 CaseSize = MatcherTable[MatcherIndex++];
2512 CaseSize = GetVBR(CaseSize, MatcherTable, MatcherIndex);
2513 if (CaseSize == 0) break;
2515 MVT CaseVT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2516 if (CaseVT == MVT::iPTR)
2517 CaseVT = TLI.getPointerTy();
2519 // If the VT matches, then we will execute this case.
2520 if (CurNodeVT == CaseVT)
2523 // Otherwise, skip over this case.
2524 MatcherIndex += CaseSize;
2527 // If no cases matched, bail out.
2528 if (CaseSize == 0) break;
2530 // Otherwise, execute the case we found.
2531 DEBUG(dbgs() << " TypeSwitch[" << EVT(CurNodeVT).getEVTString()
2532 << "] from " << SwitchStart << " to " << MatcherIndex<<'\n');
2535 case OPC_CheckChild0Type: case OPC_CheckChild1Type:
2536 case OPC_CheckChild2Type: case OPC_CheckChild3Type:
2537 case OPC_CheckChild4Type: case OPC_CheckChild5Type:
2538 case OPC_CheckChild6Type: case OPC_CheckChild7Type:
2539 if (!::CheckChildType(MatcherTable, MatcherIndex, N, TLI,
2540 Opcode-OPC_CheckChild0Type))
2543 case OPC_CheckCondCode:
2544 if (!::CheckCondCode(MatcherTable, MatcherIndex, N)) break;
2546 case OPC_CheckValueType:
2547 if (!::CheckValueType(MatcherTable, MatcherIndex, N, TLI)) break;
2549 case OPC_CheckInteger:
2550 if (!::CheckInteger(MatcherTable, MatcherIndex, N)) break;
2552 case OPC_CheckAndImm:
2553 if (!::CheckAndImm(MatcherTable, MatcherIndex, N, *this)) break;
2555 case OPC_CheckOrImm:
2556 if (!::CheckOrImm(MatcherTable, MatcherIndex, N, *this)) break;
2559 case OPC_CheckFoldableChainNode: {
2560 assert(NodeStack.size() != 1 && "No parent node");
2561 // Verify that all intermediate nodes between the root and this one have
2563 bool HasMultipleUses = false;
2564 for (unsigned i = 1, e = NodeStack.size()-1; i != e; ++i)
2565 if (!NodeStack[i].hasOneUse()) {
2566 HasMultipleUses = true;
2569 if (HasMultipleUses) break;
2571 // Check to see that the target thinks this is profitable to fold and that
2572 // we can fold it without inducing cycles in the graph.
2573 if (!IsProfitableToFold(N, NodeStack[NodeStack.size()-2].getNode(),
2575 !IsLegalToFold(N, NodeStack[NodeStack.size()-2].getNode(),
2576 NodeToMatch, OptLevel,
2577 true/*We validate our own chains*/))
2582 case OPC_EmitInteger: {
2583 MVT::SimpleValueType VT =
2584 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2585 int64_t Val = MatcherTable[MatcherIndex++];
2587 Val = GetVBR(Val, MatcherTable, MatcherIndex);
2588 RecordedNodes.push_back(std::pair<SDValue, SDNode*>(
2589 CurDAG->getTargetConstant(Val, VT), (SDNode*)0));
2592 case OPC_EmitRegister: {
2593 MVT::SimpleValueType VT =
2594 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2595 unsigned RegNo = MatcherTable[MatcherIndex++];
2596 RecordedNodes.push_back(std::pair<SDValue, SDNode*>(
2597 CurDAG->getRegister(RegNo, VT), (SDNode*)0));
2600 case OPC_EmitRegister2: {
2601 // For targets w/ more than 256 register names, the register enum
2602 // values are stored in two bytes in the matcher table (just like
2604 MVT::SimpleValueType VT =
2605 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2606 unsigned RegNo = MatcherTable[MatcherIndex++];
2607 RegNo |= MatcherTable[MatcherIndex++] << 8;
2608 RecordedNodes.push_back(std::pair<SDValue, SDNode*>(
2609 CurDAG->getRegister(RegNo, VT), (SDNode*)0));
2613 case OPC_EmitConvertToTarget: {
2614 // Convert from IMM/FPIMM to target version.
2615 unsigned RecNo = MatcherTable[MatcherIndex++];
2616 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2617 SDValue Imm = RecordedNodes[RecNo].first;
2619 if (Imm->getOpcode() == ISD::Constant) {
2620 const ConstantInt *Val=cast<ConstantSDNode>(Imm)->getConstantIntValue();
2621 Imm = CurDAG->getConstant(*Val, Imm.getValueType(), true);
2622 } else if (Imm->getOpcode() == ISD::ConstantFP) {
2623 const ConstantFP *Val=cast<ConstantFPSDNode>(Imm)->getConstantFPValue();
2624 Imm = CurDAG->getConstantFP(*Val, Imm.getValueType(), true);
2627 RecordedNodes.push_back(std::make_pair(Imm, RecordedNodes[RecNo].second));
2631 case OPC_EmitMergeInputChains1_0: // OPC_EmitMergeInputChains, 1, 0
2632 case OPC_EmitMergeInputChains1_1: { // OPC_EmitMergeInputChains, 1, 1
2633 // These are space-optimized forms of OPC_EmitMergeInputChains.
2634 assert(InputChain.getNode() == 0 &&
2635 "EmitMergeInputChains should be the first chain producing node");
2636 assert(ChainNodesMatched.empty() &&
2637 "Should only have one EmitMergeInputChains per match");
2639 // Read all of the chained nodes.
2640 unsigned RecNo = Opcode == OPC_EmitMergeInputChains1_1;
2641 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2642 ChainNodesMatched.push_back(RecordedNodes[RecNo].first.getNode());
2644 // FIXME: What if other value results of the node have uses not matched
2646 if (ChainNodesMatched.back() != NodeToMatch &&
2647 !RecordedNodes[RecNo].first.hasOneUse()) {
2648 ChainNodesMatched.clear();
2652 // Merge the input chains if they are not intra-pattern references.
2653 InputChain = HandleMergeInputChains(ChainNodesMatched, CurDAG);
2655 if (InputChain.getNode() == 0)
2656 break; // Failed to merge.
2660 case OPC_EmitMergeInputChains: {
2661 assert(InputChain.getNode() == 0 &&
2662 "EmitMergeInputChains should be the first chain producing node");
2663 // This node gets a list of nodes we matched in the input that have
2664 // chains. We want to token factor all of the input chains to these nodes
2665 // together. However, if any of the input chains is actually one of the
2666 // nodes matched in this pattern, then we have an intra-match reference.
2667 // Ignore these because the newly token factored chain should not refer to
2669 unsigned NumChains = MatcherTable[MatcherIndex++];
2670 assert(NumChains != 0 && "Can't TF zero chains");
2672 assert(ChainNodesMatched.empty() &&
2673 "Should only have one EmitMergeInputChains per match");
2675 // Read all of the chained nodes.
2676 for (unsigned i = 0; i != NumChains; ++i) {
2677 unsigned RecNo = MatcherTable[MatcherIndex++];
2678 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2679 ChainNodesMatched.push_back(RecordedNodes[RecNo].first.getNode());
2681 // FIXME: What if other value results of the node have uses not matched
2683 if (ChainNodesMatched.back() != NodeToMatch &&
2684 !RecordedNodes[RecNo].first.hasOneUse()) {
2685 ChainNodesMatched.clear();
2690 // If the inner loop broke out, the match fails.
2691 if (ChainNodesMatched.empty())
2694 // Merge the input chains if they are not intra-pattern references.
2695 InputChain = HandleMergeInputChains(ChainNodesMatched, CurDAG);
2697 if (InputChain.getNode() == 0)
2698 break; // Failed to merge.
2703 case OPC_EmitCopyToReg: {
2704 unsigned RecNo = MatcherTable[MatcherIndex++];
2705 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2706 unsigned DestPhysReg = MatcherTable[MatcherIndex++];
2708 if (InputChain.getNode() == 0)
2709 InputChain = CurDAG->getEntryNode();
2711 InputChain = CurDAG->getCopyToReg(InputChain, NodeToMatch->getDebugLoc(),
2712 DestPhysReg, RecordedNodes[RecNo].first,
2715 InputGlue = InputChain.getValue(1);
2719 case OPC_EmitNodeXForm: {
2720 unsigned XFormNo = MatcherTable[MatcherIndex++];
2721 unsigned RecNo = MatcherTable[MatcherIndex++];
2722 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2723 SDValue Res = RunSDNodeXForm(RecordedNodes[RecNo].first, XFormNo);
2724 RecordedNodes.push_back(std::pair<SDValue,SDNode*>(Res, (SDNode*) 0));
2729 case OPC_MorphNodeTo: {
2730 uint16_t TargetOpc = MatcherTable[MatcherIndex++];
2731 TargetOpc |= (unsigned short)MatcherTable[MatcherIndex++] << 8;
2732 unsigned EmitNodeInfo = MatcherTable[MatcherIndex++];
2733 // Get the result VT list.
2734 unsigned NumVTs = MatcherTable[MatcherIndex++];
2735 SmallVector<EVT, 4> VTs;
2736 for (unsigned i = 0; i != NumVTs; ++i) {
2737 MVT::SimpleValueType VT =
2738 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2739 if (VT == MVT::iPTR) VT = TLI.getPointerTy().SimpleTy;
2743 if (EmitNodeInfo & OPFL_Chain)
2744 VTs.push_back(MVT::Other);
2745 if (EmitNodeInfo & OPFL_GlueOutput)
2746 VTs.push_back(MVT::Glue);
2748 // This is hot code, so optimize the two most common cases of 1 and 2
2751 if (VTs.size() == 1)
2752 VTList = CurDAG->getVTList(VTs[0]);
2753 else if (VTs.size() == 2)
2754 VTList = CurDAG->getVTList(VTs[0], VTs[1]);
2756 VTList = CurDAG->getVTList(VTs.data(), VTs.size());
2758 // Get the operand list.
2759 unsigned NumOps = MatcherTable[MatcherIndex++];
2760 SmallVector<SDValue, 8> Ops;
2761 for (unsigned i = 0; i != NumOps; ++i) {
2762 unsigned RecNo = MatcherTable[MatcherIndex++];
2764 RecNo = GetVBR(RecNo, MatcherTable, MatcherIndex);
2766 assert(RecNo < RecordedNodes.size() && "Invalid EmitNode");
2767 Ops.push_back(RecordedNodes[RecNo].first);
2770 // If there are variadic operands to add, handle them now.
2771 if (EmitNodeInfo & OPFL_VariadicInfo) {
2772 // Determine the start index to copy from.
2773 unsigned FirstOpToCopy = getNumFixedFromVariadicInfo(EmitNodeInfo);
2774 FirstOpToCopy += (EmitNodeInfo & OPFL_Chain) ? 1 : 0;
2775 assert(NodeToMatch->getNumOperands() >= FirstOpToCopy &&
2776 "Invalid variadic node");
2777 // Copy all of the variadic operands, not including a potential glue
2779 for (unsigned i = FirstOpToCopy, e = NodeToMatch->getNumOperands();
2781 SDValue V = NodeToMatch->getOperand(i);
2782 if (V.getValueType() == MVT::Glue) break;
2787 // If this has chain/glue inputs, add them.
2788 if (EmitNodeInfo & OPFL_Chain)
2789 Ops.push_back(InputChain);
2790 if ((EmitNodeInfo & OPFL_GlueInput) && InputGlue.getNode() != 0)
2791 Ops.push_back(InputGlue);
2795 if (Opcode != OPC_MorphNodeTo) {
2796 // If this is a normal EmitNode command, just create the new node and
2797 // add the results to the RecordedNodes list.
2798 Res = CurDAG->getMachineNode(TargetOpc, NodeToMatch->getDebugLoc(),
2801 // Add all the non-glue/non-chain results to the RecordedNodes list.
2802 for (unsigned i = 0, e = VTs.size(); i != e; ++i) {
2803 if (VTs[i] == MVT::Other || VTs[i] == MVT::Glue) break;
2804 RecordedNodes.push_back(std::pair<SDValue,SDNode*>(SDValue(Res, i),
2808 } else if (NodeToMatch->getOpcode() != ISD::DELETED_NODE) {
2809 Res = MorphNode(NodeToMatch, TargetOpc, VTList, Ops.data(), Ops.size(),
2812 // NodeToMatch was eliminated by CSE when the target changed the DAG.
2813 // We will visit the equivalent node later.
2814 DEBUG(dbgs() << "Node was eliminated by CSE\n");
2818 // If the node had chain/glue results, update our notion of the current
2820 if (EmitNodeInfo & OPFL_GlueOutput) {
2821 InputGlue = SDValue(Res, VTs.size()-1);
2822 if (EmitNodeInfo & OPFL_Chain)
2823 InputChain = SDValue(Res, VTs.size()-2);
2824 } else if (EmitNodeInfo & OPFL_Chain)
2825 InputChain = SDValue(Res, VTs.size()-1);
2827 // If the OPFL_MemRefs glue is set on this node, slap all of the
2828 // accumulated memrefs onto it.
2830 // FIXME: This is vastly incorrect for patterns with multiple outputs
2831 // instructions that access memory and for ComplexPatterns that match
2833 if (EmitNodeInfo & OPFL_MemRefs) {
2834 // Only attach load or store memory operands if the generated
2835 // instruction may load or store.
2836 const MCInstrDesc &MCID = TM.getInstrInfo()->get(TargetOpc);
2837 bool mayLoad = MCID.mayLoad();
2838 bool mayStore = MCID.mayStore();
2840 unsigned NumMemRefs = 0;
2841 for (SmallVector<MachineMemOperand*, 2>::const_iterator I =
2842 MatchedMemRefs.begin(), E = MatchedMemRefs.end(); I != E; ++I) {
2843 if ((*I)->isLoad()) {
2846 } else if ((*I)->isStore()) {
2854 MachineSDNode::mmo_iterator MemRefs =
2855 MF->allocateMemRefsArray(NumMemRefs);
2857 MachineSDNode::mmo_iterator MemRefsPos = MemRefs;
2858 for (SmallVector<MachineMemOperand*, 2>::const_iterator I =
2859 MatchedMemRefs.begin(), E = MatchedMemRefs.end(); I != E; ++I) {
2860 if ((*I)->isLoad()) {
2863 } else if ((*I)->isStore()) {
2871 cast<MachineSDNode>(Res)
2872 ->setMemRefs(MemRefs, MemRefs + NumMemRefs);
2876 << (Opcode == OPC_MorphNodeTo ? "Morphed" : "Created")
2877 << " node: "; Res->dump(CurDAG); dbgs() << "\n");
2879 // If this was a MorphNodeTo then we're completely done!
2880 if (Opcode == OPC_MorphNodeTo) {
2881 // Update chain and glue uses.
2882 UpdateChainsAndGlue(NodeToMatch, InputChain, ChainNodesMatched,
2883 InputGlue, GlueResultNodesMatched, true);
2890 case OPC_MarkGlueResults: {
2891 unsigned NumNodes = MatcherTable[MatcherIndex++];
2893 // Read and remember all the glue-result nodes.
2894 for (unsigned i = 0; i != NumNodes; ++i) {
2895 unsigned RecNo = MatcherTable[MatcherIndex++];
2897 RecNo = GetVBR(RecNo, MatcherTable, MatcherIndex);
2899 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2900 GlueResultNodesMatched.push_back(RecordedNodes[RecNo].first.getNode());
2905 case OPC_CompleteMatch: {
2906 // The match has been completed, and any new nodes (if any) have been
2907 // created. Patch up references to the matched dag to use the newly
2909 unsigned NumResults = MatcherTable[MatcherIndex++];
2911 for (unsigned i = 0; i != NumResults; ++i) {
2912 unsigned ResSlot = MatcherTable[MatcherIndex++];
2914 ResSlot = GetVBR(ResSlot, MatcherTable, MatcherIndex);
2916 assert(ResSlot < RecordedNodes.size() && "Invalid CheckSame");
2917 SDValue Res = RecordedNodes[ResSlot].first;
2919 assert(i < NodeToMatch->getNumValues() &&
2920 NodeToMatch->getValueType(i) != MVT::Other &&
2921 NodeToMatch->getValueType(i) != MVT::Glue &&
2922 "Invalid number of results to complete!");
2923 assert((NodeToMatch->getValueType(i) == Res.getValueType() ||
2924 NodeToMatch->getValueType(i) == MVT::iPTR ||
2925 Res.getValueType() == MVT::iPTR ||
2926 NodeToMatch->getValueType(i).getSizeInBits() ==
2927 Res.getValueType().getSizeInBits()) &&
2928 "invalid replacement");
2929 CurDAG->ReplaceAllUsesOfValueWith(SDValue(NodeToMatch, i), Res);
2932 // If the root node defines glue, add it to the glue nodes to update list.
2933 if (NodeToMatch->getValueType(NodeToMatch->getNumValues()-1) == MVT::Glue)
2934 GlueResultNodesMatched.push_back(NodeToMatch);
2936 // Update chain and glue uses.
2937 UpdateChainsAndGlue(NodeToMatch, InputChain, ChainNodesMatched,
2938 InputGlue, GlueResultNodesMatched, false);
2940 assert(NodeToMatch->use_empty() &&
2941 "Didn't replace all uses of the node?");
2943 // FIXME: We just return here, which interacts correctly with SelectRoot
2944 // above. We should fix this to not return an SDNode* anymore.
2949 // If the code reached this point, then the match failed. See if there is
2950 // another child to try in the current 'Scope', otherwise pop it until we
2951 // find a case to check.
2952 DEBUG(dbgs() << " Match failed at index " << CurrentOpcodeIndex << "\n");
2953 ++NumDAGIselRetries;
2955 if (MatchScopes.empty()) {
2956 CannotYetSelect(NodeToMatch);
2960 // Restore the interpreter state back to the point where the scope was
2962 MatchScope &LastScope = MatchScopes.back();
2963 RecordedNodes.resize(LastScope.NumRecordedNodes);
2965 NodeStack.append(LastScope.NodeStack.begin(), LastScope.NodeStack.end());
2966 N = NodeStack.back();
2968 if (LastScope.NumMatchedMemRefs != MatchedMemRefs.size())
2969 MatchedMemRefs.resize(LastScope.NumMatchedMemRefs);
2970 MatcherIndex = LastScope.FailIndex;
2972 DEBUG(dbgs() << " Continuing at " << MatcherIndex << "\n");
2974 InputChain = LastScope.InputChain;
2975 InputGlue = LastScope.InputGlue;
2976 if (!LastScope.HasChainNodesMatched)
2977 ChainNodesMatched.clear();
2978 if (!LastScope.HasGlueResultNodesMatched)
2979 GlueResultNodesMatched.clear();
2981 // Check to see what the offset is at the new MatcherIndex. If it is zero
2982 // we have reached the end of this scope, otherwise we have another child
2983 // in the current scope to try.
2984 unsigned NumToSkip = MatcherTable[MatcherIndex++];
2985 if (NumToSkip & 128)
2986 NumToSkip = GetVBR(NumToSkip, MatcherTable, MatcherIndex);
2988 // If we have another child in this scope to match, update FailIndex and
2990 if (NumToSkip != 0) {
2991 LastScope.FailIndex = MatcherIndex+NumToSkip;
2995 // End of this scope, pop it and try the next child in the containing
2997 MatchScopes.pop_back();
3004 void SelectionDAGISel::CannotYetSelect(SDNode *N) {
3006 raw_string_ostream Msg(msg);
3007 Msg << "Cannot select: ";
3009 if (N->getOpcode() != ISD::INTRINSIC_W_CHAIN &&
3010 N->getOpcode() != ISD::INTRINSIC_WO_CHAIN &&
3011 N->getOpcode() != ISD::INTRINSIC_VOID) {
3012 N->printrFull(Msg, CurDAG);
3013 Msg << "\nIn function: " << MF->getName();
3015 bool HasInputChain = N->getOperand(0).getValueType() == MVT::Other;
3017 cast<ConstantSDNode>(N->getOperand(HasInputChain))->getZExtValue();
3018 if (iid < Intrinsic::num_intrinsics)
3019 Msg << "intrinsic %" << Intrinsic::getName((Intrinsic::ID)iid);
3020 else if (const TargetIntrinsicInfo *TII = TM.getIntrinsicInfo())
3021 Msg << "target intrinsic %" << TII->getName(iid);
3023 Msg << "unknown intrinsic #" << iid;
3025 report_fatal_error(Msg.str());
3028 char SelectionDAGISel::ID = 0;