1 //===-- SelectionDAGISel.cpp - Implement the SelectionDAGISel class -------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements the SelectionDAGISel class.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "isel"
15 #include "llvm/ADT/BitVector.h"
16 #include "llvm/Analysis/AliasAnalysis.h"
17 #include "llvm/CodeGen/SelectionDAGISel.h"
18 #include "llvm/CodeGen/ScheduleDAG.h"
19 #include "llvm/Constants.h"
20 #include "llvm/CallingConv.h"
21 #include "llvm/DerivedTypes.h"
22 #include "llvm/Function.h"
23 #include "llvm/GlobalVariable.h"
24 #include "llvm/InlineAsm.h"
25 #include "llvm/Instructions.h"
26 #include "llvm/Intrinsics.h"
27 #include "llvm/IntrinsicInst.h"
28 #include "llvm/ParameterAttributes.h"
29 #include "llvm/CodeGen/MachineModuleInfo.h"
30 #include "llvm/CodeGen/MachineFunction.h"
31 #include "llvm/CodeGen/MachineFrameInfo.h"
32 #include "llvm/CodeGen/MachineJumpTableInfo.h"
33 #include "llvm/CodeGen/MachineInstrBuilder.h"
34 #include "llvm/CodeGen/SchedulerRegistry.h"
35 #include "llvm/CodeGen/SelectionDAG.h"
36 #include "llvm/CodeGen/SSARegMap.h"
37 #include "llvm/Target/MRegisterInfo.h"
38 #include "llvm/Target/TargetData.h"
39 #include "llvm/Target/TargetFrameInfo.h"
40 #include "llvm/Target/TargetInstrInfo.h"
41 #include "llvm/Target/TargetLowering.h"
42 #include "llvm/Target/TargetMachine.h"
43 #include "llvm/Target/TargetOptions.h"
44 #include "llvm/Support/MathExtras.h"
45 #include "llvm/Support/Debug.h"
46 #include "llvm/Support/Compiler.h"
52 ViewISelDAGs("view-isel-dags", cl::Hidden,
53 cl::desc("Pop up a window to show isel dags as they are selected"));
55 ViewSchedDAGs("view-sched-dags", cl::Hidden,
56 cl::desc("Pop up a window to show sched dags as they are processed"));
58 static const bool ViewISelDAGs = 0, ViewSchedDAGs = 0;
61 //===---------------------------------------------------------------------===//
63 /// RegisterScheduler class - Track the registration of instruction schedulers.
65 //===---------------------------------------------------------------------===//
66 MachinePassRegistry RegisterScheduler::Registry;
68 //===---------------------------------------------------------------------===//
70 /// ISHeuristic command line option for instruction schedulers.
72 //===---------------------------------------------------------------------===//
74 cl::opt<RegisterScheduler::FunctionPassCtor, false,
75 RegisterPassParser<RegisterScheduler> >
77 cl::init(&createDefaultScheduler),
78 cl::desc("Instruction schedulers available:"));
80 static RegisterScheduler
81 defaultListDAGScheduler("default", " Best scheduler for the target",
82 createDefaultScheduler);
86 /// RegsForValue - This struct represents the physical registers that a
87 /// particular value is assigned and the type information about the value.
88 /// This is needed because values can be promoted into larger registers and
89 /// expanded into multiple smaller registers than the value.
90 struct VISIBILITY_HIDDEN RegsForValue {
91 /// Regs - This list hold the register (for legal and promoted values)
92 /// or register set (for expanded values) that the value should be assigned
94 std::vector<unsigned> Regs;
96 /// RegVT - The value type of each register.
100 /// ValueVT - The value type of the LLVM value, which may be promoted from
101 /// RegVT or made from merging the two expanded parts.
102 MVT::ValueType ValueVT;
104 RegsForValue() : RegVT(MVT::Other), ValueVT(MVT::Other) {}
106 RegsForValue(unsigned Reg, MVT::ValueType regvt, MVT::ValueType valuevt)
107 : RegVT(regvt), ValueVT(valuevt) {
110 RegsForValue(const std::vector<unsigned> ®s,
111 MVT::ValueType regvt, MVT::ValueType valuevt)
112 : Regs(regs), RegVT(regvt), ValueVT(valuevt) {
115 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from
116 /// this value and returns the result as a ValueVT value. This uses
117 /// Chain/Flag as the input and updates them for the output Chain/Flag.
118 SDOperand getCopyFromRegs(SelectionDAG &DAG,
119 SDOperand &Chain, SDOperand &Flag) const;
121 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
122 /// specified value into the registers specified by this object. This uses
123 /// Chain/Flag as the input and updates them for the output Chain/Flag.
124 void getCopyToRegs(SDOperand Val, SelectionDAG &DAG,
125 SDOperand &Chain, SDOperand &Flag,
126 MVT::ValueType PtrVT) const;
128 /// AddInlineAsmOperands - Add this value to the specified inlineasm node
129 /// operand list. This adds the code marker and includes the number of
130 /// values added into it.
131 void AddInlineAsmOperands(unsigned Code, SelectionDAG &DAG,
132 std::vector<SDOperand> &Ops) const;
137 //===--------------------------------------------------------------------===//
138 /// createDefaultScheduler - This creates an instruction scheduler appropriate
140 ScheduleDAG* createDefaultScheduler(SelectionDAGISel *IS,
142 MachineBasicBlock *BB) {
143 TargetLowering &TLI = IS->getTargetLowering();
145 if (TLI.getSchedulingPreference() == TargetLowering::SchedulingForLatency) {
146 return createTDListDAGScheduler(IS, DAG, BB);
148 assert(TLI.getSchedulingPreference() ==
149 TargetLowering::SchedulingForRegPressure && "Unknown sched type!");
150 return createBURRListDAGScheduler(IS, DAG, BB);
155 //===--------------------------------------------------------------------===//
156 /// FunctionLoweringInfo - This contains information that is global to a
157 /// function that is used when lowering a region of the function.
158 class FunctionLoweringInfo {
165 FunctionLoweringInfo(TargetLowering &TLI, Function &Fn,MachineFunction &MF);
167 /// MBBMap - A mapping from LLVM basic blocks to their machine code entry.
168 std::map<const BasicBlock*, MachineBasicBlock *> MBBMap;
170 /// ValueMap - Since we emit code for the function a basic block at a time,
171 /// we must remember which virtual registers hold the values for
172 /// cross-basic-block values.
173 DenseMap<const Value*, unsigned> ValueMap;
175 /// StaticAllocaMap - Keep track of frame indices for fixed sized allocas in
176 /// the entry block. This allows the allocas to be efficiently referenced
177 /// anywhere in the function.
178 std::map<const AllocaInst*, int> StaticAllocaMap;
180 unsigned MakeReg(MVT::ValueType VT) {
181 return RegMap->createVirtualRegister(TLI.getRegClassFor(VT));
184 /// isExportedInst - Return true if the specified value is an instruction
185 /// exported from its block.
186 bool isExportedInst(const Value *V) {
187 return ValueMap.count(V);
190 unsigned CreateRegForValue(const Value *V);
192 unsigned InitializeRegForValue(const Value *V) {
193 unsigned &R = ValueMap[V];
194 assert(R == 0 && "Already initialized this value register!");
195 return R = CreateRegForValue(V);
200 /// isUsedOutsideOfDefiningBlock - Return true if this instruction is used by
201 /// PHI nodes or outside of the basic block that defines it, or used by a
202 /// switch instruction, which may expand to multiple basic blocks.
203 static bool isUsedOutsideOfDefiningBlock(Instruction *I) {
204 if (isa<PHINode>(I)) return true;
205 BasicBlock *BB = I->getParent();
206 for (Value::use_iterator UI = I->use_begin(), E = I->use_end(); UI != E; ++UI)
207 if (cast<Instruction>(*UI)->getParent() != BB || isa<PHINode>(*UI) ||
208 // FIXME: Remove switchinst special case.
209 isa<SwitchInst>(*UI))
214 /// isOnlyUsedInEntryBlock - If the specified argument is only used in the
215 /// entry block, return true. This includes arguments used by switches, since
216 /// the switch may expand into multiple basic blocks.
217 static bool isOnlyUsedInEntryBlock(Argument *A) {
218 BasicBlock *Entry = A->getParent()->begin();
219 for (Value::use_iterator UI = A->use_begin(), E = A->use_end(); UI != E; ++UI)
220 if (cast<Instruction>(*UI)->getParent() != Entry || isa<SwitchInst>(*UI))
221 return false; // Use not in entry block.
225 FunctionLoweringInfo::FunctionLoweringInfo(TargetLowering &tli,
226 Function &fn, MachineFunction &mf)
227 : TLI(tli), Fn(fn), MF(mf), RegMap(MF.getSSARegMap()) {
229 // Create a vreg for each argument register that is not dead and is used
230 // outside of the entry block for the function.
231 for (Function::arg_iterator AI = Fn.arg_begin(), E = Fn.arg_end();
233 if (!isOnlyUsedInEntryBlock(AI))
234 InitializeRegForValue(AI);
236 // Initialize the mapping of values to registers. This is only set up for
237 // instruction values that are used outside of the block that defines
239 Function::iterator BB = Fn.begin(), EB = Fn.end();
240 for (BasicBlock::iterator I = BB->begin(), E = BB->end(); I != E; ++I)
241 if (AllocaInst *AI = dyn_cast<AllocaInst>(I))
242 if (ConstantInt *CUI = dyn_cast<ConstantInt>(AI->getArraySize())) {
243 const Type *Ty = AI->getAllocatedType();
244 uint64_t TySize = TLI.getTargetData()->getTypeSize(Ty);
246 std::max((unsigned)TLI.getTargetData()->getPrefTypeAlignment(Ty),
249 TySize *= CUI->getZExtValue(); // Get total allocated size.
250 if (TySize == 0) TySize = 1; // Don't create zero-sized stack objects.
251 StaticAllocaMap[AI] =
252 MF.getFrameInfo()->CreateStackObject(TySize, Align);
255 for (; BB != EB; ++BB)
256 for (BasicBlock::iterator I = BB->begin(), E = BB->end(); I != E; ++I)
257 if (!I->use_empty() && isUsedOutsideOfDefiningBlock(I))
258 if (!isa<AllocaInst>(I) ||
259 !StaticAllocaMap.count(cast<AllocaInst>(I)))
260 InitializeRegForValue(I);
262 // Create an initial MachineBasicBlock for each LLVM BasicBlock in F. This
263 // also creates the initial PHI MachineInstrs, though none of the input
264 // operands are populated.
265 for (BB = Fn.begin(), EB = Fn.end(); BB != EB; ++BB) {
266 MachineBasicBlock *MBB = new MachineBasicBlock(BB);
268 MF.getBasicBlockList().push_back(MBB);
270 // Create Machine PHI nodes for LLVM PHI nodes, lowering them as
273 for (BasicBlock::iterator I = BB->begin();(PN = dyn_cast<PHINode>(I)); ++I){
274 if (PN->use_empty()) continue;
276 MVT::ValueType VT = TLI.getValueType(PN->getType());
277 unsigned NumElements;
278 if (VT != MVT::Vector)
279 NumElements = TLI.getNumElements(VT);
281 MVT::ValueType VT1,VT2;
283 TLI.getVectorTypeBreakdown(cast<VectorType>(PN->getType()),
286 unsigned PHIReg = ValueMap[PN];
287 assert(PHIReg && "PHI node does not have an assigned virtual register!");
288 const TargetInstrInfo *TII = TLI.getTargetMachine().getInstrInfo();
289 for (unsigned i = 0; i != NumElements; ++i)
290 BuildMI(MBB, TII->get(TargetInstrInfo::PHI), PHIReg+i);
295 /// CreateRegForValue - Allocate the appropriate number of virtual registers of
296 /// the correctly promoted or expanded types. Assign these registers
297 /// consecutive vreg numbers and return the first assigned number.
298 unsigned FunctionLoweringInfo::CreateRegForValue(const Value *V) {
299 MVT::ValueType VT = TLI.getValueType(V->getType());
301 // The number of multiples of registers that we need, to, e.g., split up
302 // a <2 x int64> -> 4 x i32 registers.
303 unsigned NumVectorRegs = 1;
305 // If this is a vector type, figure out what type it will decompose into
306 // and how many of the elements it will use.
307 if (VT == MVT::Vector) {
308 const VectorType *PTy = cast<VectorType>(V->getType());
309 unsigned NumElts = PTy->getNumElements();
310 MVT::ValueType EltTy = TLI.getValueType(PTy->getElementType());
311 MVT::ValueType VecTy = getVectorType(EltTy, NumElts);
313 // Divide the input until we get to a supported size. This will always
314 // end with a scalar if the target doesn't support vectors.
315 while (NumElts > 1 && !TLI.isTypeLegal(VecTy)) {
318 VecTy = getVectorType(EltTy, NumElts);
321 // Check that VecTy isn't a 1-element vector.
322 if (NumElts == 1 && VecTy == MVT::Other)
328 // The common case is that we will only create one register for this
329 // value. If we have that case, create and return the virtual register.
330 unsigned NV = TLI.getNumElements(VT);
332 // If we are promoting this value, pick the next largest supported type.
333 MVT::ValueType PromotedType = TLI.getTypeToTransformTo(VT);
334 unsigned Reg = MakeReg(PromotedType);
335 // If this is a vector of supported or promoted types (e.g. 4 x i16),
336 // create all of the registers.
337 for (unsigned i = 1; i != NumVectorRegs; ++i)
338 MakeReg(PromotedType);
342 // If this value is represented with multiple target registers, make sure
343 // to create enough consecutive registers of the right (smaller) type.
344 VT = TLI.getTypeToExpandTo(VT);
345 unsigned R = MakeReg(VT);
346 for (unsigned i = 1; i != NV*NumVectorRegs; ++i)
351 //===----------------------------------------------------------------------===//
352 /// SelectionDAGLowering - This is the common target-independent lowering
353 /// implementation that is parameterized by a TargetLowering object.
354 /// Also, targets can overload any lowering method.
357 class SelectionDAGLowering {
358 MachineBasicBlock *CurMBB;
360 DenseMap<const Value*, SDOperand> NodeMap;
362 /// PendingLoads - Loads are not emitted to the program immediately. We bunch
363 /// them up and then emit token factor nodes when possible. This allows us to
364 /// get simple disambiguation between loads without worrying about alias
366 std::vector<SDOperand> PendingLoads;
368 /// Case - A struct to record the Value for a switch case, and the
369 /// case's target basic block.
373 MachineBasicBlock* BB;
375 Case() : Low(0), High(0), BB(0) { }
376 Case(Constant* low, Constant* high, MachineBasicBlock* bb) :
377 Low(low), High(high), BB(bb) { }
378 uint64_t size() const {
379 uint64_t rHigh = cast<ConstantInt>(High)->getSExtValue();
380 uint64_t rLow = cast<ConstantInt>(Low)->getSExtValue();
381 return (rHigh - rLow + 1ULL);
387 MachineBasicBlock* BB;
390 CaseBits(uint64_t mask, MachineBasicBlock* bb, unsigned bits):
391 Mask(mask), BB(bb), Bits(bits) { }
394 typedef std::vector<Case> CaseVector;
395 typedef std::vector<CaseBits> CaseBitsVector;
396 typedef CaseVector::iterator CaseItr;
397 typedef std::pair<CaseItr, CaseItr> CaseRange;
399 /// CaseRec - A struct with ctor used in lowering switches to a binary tree
400 /// of conditional branches.
402 CaseRec(MachineBasicBlock *bb, Constant *lt, Constant *ge, CaseRange r) :
403 CaseBB(bb), LT(lt), GE(ge), Range(r) {}
405 /// CaseBB - The MBB in which to emit the compare and branch
406 MachineBasicBlock *CaseBB;
407 /// LT, GE - If nonzero, we know the current case value must be less-than or
408 /// greater-than-or-equal-to these Constants.
411 /// Range - A pair of iterators representing the range of case values to be
412 /// processed at this point in the binary search tree.
416 typedef std::vector<CaseRec> CaseRecVector;
418 /// The comparison function for sorting the switch case values in the vector.
419 /// WARNING: Case ranges should be disjoint!
421 bool operator () (const Case& C1, const Case& C2) {
422 assert(isa<ConstantInt>(C1.Low) && isa<ConstantInt>(C2.High));
423 const ConstantInt* CI1 = cast<const ConstantInt>(C1.Low);
424 const ConstantInt* CI2 = cast<const ConstantInt>(C2.High);
425 return CI1->getValue().slt(CI2->getValue());
430 bool operator () (const CaseBits& C1, const CaseBits& C2) {
431 return C1.Bits > C2.Bits;
435 unsigned Clusterify(CaseVector& Cases, const SwitchInst &SI);
438 // TLI - This is information that describes the available target features we
439 // need for lowering. This indicates when operations are unavailable,
440 // implemented with a libcall, etc.
443 const TargetData *TD;
445 /// SwitchCases - Vector of CaseBlock structures used to communicate
446 /// SwitchInst code generation information.
447 std::vector<SelectionDAGISel::CaseBlock> SwitchCases;
448 /// JTCases - Vector of JumpTable structures used to communicate
449 /// SwitchInst code generation information.
450 std::vector<SelectionDAGISel::JumpTableBlock> JTCases;
451 std::vector<SelectionDAGISel::BitTestBlock> BitTestCases;
453 /// FuncInfo - Information about the function as a whole.
455 FunctionLoweringInfo &FuncInfo;
457 SelectionDAGLowering(SelectionDAG &dag, TargetLowering &tli,
458 FunctionLoweringInfo &funcinfo)
459 : TLI(tli), DAG(dag), TD(DAG.getTarget().getTargetData()),
463 /// getRoot - Return the current virtual root of the Selection DAG.
465 SDOperand getRoot() {
466 if (PendingLoads.empty())
467 return DAG.getRoot();
469 if (PendingLoads.size() == 1) {
470 SDOperand Root = PendingLoads[0];
472 PendingLoads.clear();
476 // Otherwise, we have to make a token factor node.
477 SDOperand Root = DAG.getNode(ISD::TokenFactor, MVT::Other,
478 &PendingLoads[0], PendingLoads.size());
479 PendingLoads.clear();
484 SDOperand CopyValueToVirtualRegister(Value *V, unsigned Reg);
486 void visit(Instruction &I) { visit(I.getOpcode(), I); }
488 void visit(unsigned Opcode, User &I) {
489 // Note: this doesn't use InstVisitor, because it has to work with
490 // ConstantExpr's in addition to instructions.
492 default: assert(0 && "Unknown instruction type encountered!");
494 // Build the switch statement using the Instruction.def file.
495 #define HANDLE_INST(NUM, OPCODE, CLASS) \
496 case Instruction::OPCODE:return visit##OPCODE((CLASS&)I);
497 #include "llvm/Instruction.def"
501 void setCurrentBasicBlock(MachineBasicBlock *MBB) { CurMBB = MBB; }
503 SDOperand getLoadFrom(const Type *Ty, SDOperand Ptr,
504 const Value *SV, SDOperand Root,
505 bool isVolatile, unsigned Alignment);
507 SDOperand getIntPtrConstant(uint64_t Val) {
508 return DAG.getConstant(Val, TLI.getPointerTy());
511 SDOperand getValue(const Value *V);
513 void setValue(const Value *V, SDOperand NewN) {
514 SDOperand &N = NodeMap[V];
515 assert(N.Val == 0 && "Already set a value for this node!");
519 RegsForValue GetRegistersForValue(const std::string &ConstrCode,
521 bool OutReg, bool InReg,
522 std::set<unsigned> &OutputRegs,
523 std::set<unsigned> &InputRegs);
525 void FindMergedConditions(Value *Cond, MachineBasicBlock *TBB,
526 MachineBasicBlock *FBB, MachineBasicBlock *CurBB,
528 bool isExportableFromCurrentBlock(Value *V, const BasicBlock *FromBB);
529 void ExportFromCurrentBlock(Value *V);
530 void LowerCallTo(Instruction &I,
531 const Type *CalledValueTy, unsigned CallingConv,
532 bool IsTailCall, SDOperand Callee, unsigned OpIdx);
534 // Terminator instructions.
535 void visitRet(ReturnInst &I);
536 void visitBr(BranchInst &I);
537 void visitSwitch(SwitchInst &I);
538 void visitUnreachable(UnreachableInst &I) { /* noop */ }
540 // Helpers for visitSwitch
541 bool handleSmallSwitchRange(CaseRec& CR,
542 CaseRecVector& WorkList,
544 MachineBasicBlock* Default);
545 bool handleJTSwitchCase(CaseRec& CR,
546 CaseRecVector& WorkList,
548 MachineBasicBlock* Default);
549 bool handleBTSplitSwitchCase(CaseRec& CR,
550 CaseRecVector& WorkList,
552 MachineBasicBlock* Default);
553 bool handleBitTestsSwitchCase(CaseRec& CR,
554 CaseRecVector& WorkList,
556 MachineBasicBlock* Default);
557 void visitSwitchCase(SelectionDAGISel::CaseBlock &CB);
558 void visitBitTestHeader(SelectionDAGISel::BitTestBlock &B);
559 void visitBitTestCase(MachineBasicBlock* NextMBB,
561 SelectionDAGISel::BitTestCase &B);
562 void visitJumpTable(SelectionDAGISel::JumpTable &JT);
563 void visitJumpTableHeader(SelectionDAGISel::JumpTable &JT,
564 SelectionDAGISel::JumpTableHeader &JTH);
566 // These all get lowered before this pass.
567 void visitInvoke(InvokeInst &I);
568 void visitInvoke(InvokeInst &I, bool AsTerminator);
569 void visitUnwind(UnwindInst &I);
571 void visitScalarBinary(User &I, unsigned OpCode);
572 void visitVectorBinary(User &I, unsigned OpCode);
573 void visitEitherBinary(User &I, unsigned ScalarOp, unsigned VectorOp);
574 void visitShift(User &I, unsigned Opcode);
575 void visitAdd(User &I) {
576 if (isa<VectorType>(I.getType()))
577 visitVectorBinary(I, ISD::VADD);
578 else if (I.getType()->isFloatingPoint())
579 visitScalarBinary(I, ISD::FADD);
581 visitScalarBinary(I, ISD::ADD);
583 void visitSub(User &I);
584 void visitMul(User &I) {
585 if (isa<VectorType>(I.getType()))
586 visitVectorBinary(I, ISD::VMUL);
587 else if (I.getType()->isFloatingPoint())
588 visitScalarBinary(I, ISD::FMUL);
590 visitScalarBinary(I, ISD::MUL);
592 void visitURem(User &I) { visitScalarBinary(I, ISD::UREM); }
593 void visitSRem(User &I) { visitScalarBinary(I, ISD::SREM); }
594 void visitFRem(User &I) { visitScalarBinary(I, ISD::FREM); }
595 void visitUDiv(User &I) { visitEitherBinary(I, ISD::UDIV, ISD::VUDIV); }
596 void visitSDiv(User &I) { visitEitherBinary(I, ISD::SDIV, ISD::VSDIV); }
597 void visitFDiv(User &I) { visitEitherBinary(I, ISD::FDIV, ISD::VSDIV); }
598 void visitAnd (User &I) { visitEitherBinary(I, ISD::AND, ISD::VAND ); }
599 void visitOr (User &I) { visitEitherBinary(I, ISD::OR, ISD::VOR ); }
600 void visitXor (User &I) { visitEitherBinary(I, ISD::XOR, ISD::VXOR ); }
601 void visitShl (User &I) { visitShift(I, ISD::SHL); }
602 void visitLShr(User &I) { visitShift(I, ISD::SRL); }
603 void visitAShr(User &I) { visitShift(I, ISD::SRA); }
604 void visitICmp(User &I);
605 void visitFCmp(User &I);
606 // Visit the conversion instructions
607 void visitTrunc(User &I);
608 void visitZExt(User &I);
609 void visitSExt(User &I);
610 void visitFPTrunc(User &I);
611 void visitFPExt(User &I);
612 void visitFPToUI(User &I);
613 void visitFPToSI(User &I);
614 void visitUIToFP(User &I);
615 void visitSIToFP(User &I);
616 void visitPtrToInt(User &I);
617 void visitIntToPtr(User &I);
618 void visitBitCast(User &I);
620 void visitExtractElement(User &I);
621 void visitInsertElement(User &I);
622 void visitShuffleVector(User &I);
624 void visitGetElementPtr(User &I);
625 void visitSelect(User &I);
627 void visitMalloc(MallocInst &I);
628 void visitFree(FreeInst &I);
629 void visitAlloca(AllocaInst &I);
630 void visitLoad(LoadInst &I);
631 void visitStore(StoreInst &I);
632 void visitPHI(PHINode &I) { } // PHI nodes are handled specially.
633 void visitCall(CallInst &I);
634 void visitInlineAsm(CallInst &I);
635 const char *visitIntrinsicCall(CallInst &I, unsigned Intrinsic);
636 void visitTargetIntrinsic(CallInst &I, unsigned Intrinsic);
638 void visitVAStart(CallInst &I);
639 void visitVAArg(VAArgInst &I);
640 void visitVAEnd(CallInst &I);
641 void visitVACopy(CallInst &I);
643 void visitMemIntrinsic(CallInst &I, unsigned Op);
645 void visitUserOp1(Instruction &I) {
646 assert(0 && "UserOp1 should not exist at instruction selection time!");
649 void visitUserOp2(Instruction &I) {
650 assert(0 && "UserOp2 should not exist at instruction selection time!");
654 } // end namespace llvm
656 SDOperand SelectionDAGLowering::getValue(const Value *V) {
657 SDOperand &N = NodeMap[V];
660 const Type *VTy = V->getType();
661 MVT::ValueType VT = TLI.getValueType(VTy);
662 if (Constant *C = const_cast<Constant*>(dyn_cast<Constant>(V))) {
663 if (ConstantExpr *CE = dyn_cast<ConstantExpr>(C)) {
664 visit(CE->getOpcode(), *CE);
665 SDOperand N1 = NodeMap[V];
666 assert(N1.Val && "visit didn't populate the ValueMap!");
668 } else if (GlobalValue *GV = dyn_cast<GlobalValue>(C)) {
669 return N = DAG.getGlobalAddress(GV, VT);
670 } else if (isa<ConstantPointerNull>(C)) {
671 return N = DAG.getConstant(0, TLI.getPointerTy());
672 } else if (isa<UndefValue>(C)) {
673 if (!isa<VectorType>(VTy))
674 return N = DAG.getNode(ISD::UNDEF, VT);
676 // Create a VBUILD_VECTOR of undef nodes.
677 const VectorType *PTy = cast<VectorType>(VTy);
678 unsigned NumElements = PTy->getNumElements();
679 MVT::ValueType PVT = TLI.getValueType(PTy->getElementType());
681 SmallVector<SDOperand, 8> Ops;
682 Ops.assign(NumElements, DAG.getNode(ISD::UNDEF, PVT));
684 // Create a VConstant node with generic Vector type.
685 Ops.push_back(DAG.getConstant(NumElements, MVT::i32));
686 Ops.push_back(DAG.getValueType(PVT));
687 return N = DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector,
688 &Ops[0], Ops.size());
689 } else if (ConstantFP *CFP = dyn_cast<ConstantFP>(C)) {
690 return N = DAG.getConstantFP(CFP->getValue(), VT);
691 } else if (const VectorType *PTy = dyn_cast<VectorType>(VTy)) {
692 unsigned NumElements = PTy->getNumElements();
693 MVT::ValueType PVT = TLI.getValueType(PTy->getElementType());
695 // Now that we know the number and type of the elements, push a
696 // Constant or ConstantFP node onto the ops list for each element of
697 // the packed constant.
698 SmallVector<SDOperand, 8> Ops;
699 if (ConstantVector *CP = dyn_cast<ConstantVector>(C)) {
700 for (unsigned i = 0; i != NumElements; ++i)
701 Ops.push_back(getValue(CP->getOperand(i)));
703 assert(isa<ConstantAggregateZero>(C) && "Unknown packed constant!");
705 if (MVT::isFloatingPoint(PVT))
706 Op = DAG.getConstantFP(0, PVT);
708 Op = DAG.getConstant(0, PVT);
709 Ops.assign(NumElements, Op);
712 // Create a VBUILD_VECTOR node with generic Vector type.
713 Ops.push_back(DAG.getConstant(NumElements, MVT::i32));
714 Ops.push_back(DAG.getValueType(PVT));
715 return NodeMap[V] = DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, &Ops[0],
718 // Canonicalize all constant ints to be unsigned.
719 return N = DAG.getConstant(cast<ConstantInt>(C)->getZExtValue(),VT);
723 if (const AllocaInst *AI = dyn_cast<AllocaInst>(V)) {
724 std::map<const AllocaInst*, int>::iterator SI =
725 FuncInfo.StaticAllocaMap.find(AI);
726 if (SI != FuncInfo.StaticAllocaMap.end())
727 return DAG.getFrameIndex(SI->second, TLI.getPointerTy());
730 unsigned InReg = FuncInfo.ValueMap[V];
731 assert(InReg && "Value not in map!");
733 // If this type is not legal, make it so now.
734 if (VT != MVT::Vector) {
735 if (TLI.getTypeAction(VT) == TargetLowering::Expand) {
736 // Source must be expanded. This input value is actually coming from the
737 // register pair InReg and InReg+1.
738 MVT::ValueType DestVT = TLI.getTypeToExpandTo(VT);
739 unsigned NumVals = TLI.getNumElements(VT);
740 N = DAG.getCopyFromReg(DAG.getEntryNode(), InReg, DestVT);
742 N = DAG.getNode(ISD::BIT_CONVERT, VT, N);
744 assert(NumVals == 2 && "1 to 4 (and more) expansion not implemented!");
745 N = DAG.getNode(ISD::BUILD_PAIR, VT, N,
746 DAG.getCopyFromReg(DAG.getEntryNode(), InReg+1, DestVT));
749 MVT::ValueType DestVT = TLI.getTypeToTransformTo(VT);
750 N = DAG.getCopyFromReg(DAG.getEntryNode(), InReg, DestVT);
751 if (TLI.getTypeAction(VT) == TargetLowering::Promote) // Promotion case
752 N = MVT::isFloatingPoint(VT)
753 ? DAG.getNode(ISD::FP_ROUND, VT, N)
754 : DAG.getNode(ISD::TRUNCATE, VT, N);
757 // Otherwise, if this is a vector, make it available as a generic vector
759 MVT::ValueType PTyElementVT, PTyLegalElementVT;
760 const VectorType *PTy = cast<VectorType>(VTy);
761 unsigned NE = TLI.getVectorTypeBreakdown(PTy, PTyElementVT,
764 // Build a VBUILD_VECTOR with the input registers.
765 SmallVector<SDOperand, 8> Ops;
766 if (PTyElementVT == PTyLegalElementVT) {
767 // If the value types are legal, just VBUILD the CopyFromReg nodes.
768 for (unsigned i = 0; i != NE; ++i)
769 Ops.push_back(DAG.getCopyFromReg(DAG.getEntryNode(), InReg++,
771 } else if (PTyElementVT < PTyLegalElementVT) {
772 // If the register was promoted, use TRUNCATE of FP_ROUND as appropriate.
773 for (unsigned i = 0; i != NE; ++i) {
774 SDOperand Op = DAG.getCopyFromReg(DAG.getEntryNode(), InReg++,
776 if (MVT::isFloatingPoint(PTyElementVT))
777 Op = DAG.getNode(ISD::FP_ROUND, PTyElementVT, Op);
779 Op = DAG.getNode(ISD::TRUNCATE, PTyElementVT, Op);
783 // If the register was expanded, use BUILD_PAIR.
784 assert((NE & 1) == 0 && "Must expand into a multiple of 2 elements!");
785 for (unsigned i = 0; i != NE/2; ++i) {
786 SDOperand Op0 = DAG.getCopyFromReg(DAG.getEntryNode(), InReg++,
788 SDOperand Op1 = DAG.getCopyFromReg(DAG.getEntryNode(), InReg++,
790 Ops.push_back(DAG.getNode(ISD::BUILD_PAIR, VT, Op0, Op1));
794 Ops.push_back(DAG.getConstant(NE, MVT::i32));
795 Ops.push_back(DAG.getValueType(PTyLegalElementVT));
796 N = DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, &Ops[0], Ops.size());
798 // Finally, use a VBIT_CONVERT to make this available as the appropriate
800 N = DAG.getNode(ISD::VBIT_CONVERT, MVT::Vector, N,
801 DAG.getConstant(PTy->getNumElements(),
803 DAG.getValueType(TLI.getValueType(PTy->getElementType())));
810 void SelectionDAGLowering::visitRet(ReturnInst &I) {
811 if (I.getNumOperands() == 0) {
812 DAG.setRoot(DAG.getNode(ISD::RET, MVT::Other, getRoot()));
815 SmallVector<SDOperand, 8> NewValues;
816 NewValues.push_back(getRoot());
817 for (unsigned i = 0, e = I.getNumOperands(); i != e; ++i) {
818 SDOperand RetOp = getValue(I.getOperand(i));
820 // If this is an integer return value, we need to promote it ourselves to
821 // the full width of a register, since LegalizeOp will use ANY_EXTEND rather
823 // FIXME: C calling convention requires the return type to be promoted to
824 // at least 32-bit. But this is not necessary for non-C calling conventions.
825 if (MVT::isInteger(RetOp.getValueType()) &&
826 RetOp.getValueType() < MVT::i64) {
827 MVT::ValueType TmpVT;
828 if (TLI.getTypeAction(MVT::i32) == TargetLowering::Promote)
829 TmpVT = TLI.getTypeToTransformTo(MVT::i32);
832 const FunctionType *FTy = I.getParent()->getParent()->getFunctionType();
833 const ParamAttrsList *Attrs = FTy->getParamAttrs();
834 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
835 if (Attrs && Attrs->paramHasAttr(0, ParamAttr::SExt))
836 ExtendKind = ISD::SIGN_EXTEND;
837 if (Attrs && Attrs->paramHasAttr(0, ParamAttr::ZExt))
838 ExtendKind = ISD::ZERO_EXTEND;
839 RetOp = DAG.getNode(ExtendKind, TmpVT, RetOp);
841 NewValues.push_back(RetOp);
842 NewValues.push_back(DAG.getConstant(false, MVT::i32));
844 DAG.setRoot(DAG.getNode(ISD::RET, MVT::Other,
845 &NewValues[0], NewValues.size()));
848 /// ExportFromCurrentBlock - If this condition isn't known to be exported from
849 /// the current basic block, add it to ValueMap now so that we'll get a
851 void SelectionDAGLowering::ExportFromCurrentBlock(Value *V) {
852 // No need to export constants.
853 if (!isa<Instruction>(V) && !isa<Argument>(V)) return;
856 if (FuncInfo.isExportedInst(V)) return;
858 unsigned Reg = FuncInfo.InitializeRegForValue(V);
859 PendingLoads.push_back(CopyValueToVirtualRegister(V, Reg));
862 bool SelectionDAGLowering::isExportableFromCurrentBlock(Value *V,
863 const BasicBlock *FromBB) {
864 // The operands of the setcc have to be in this block. We don't know
865 // how to export them from some other block.
866 if (Instruction *VI = dyn_cast<Instruction>(V)) {
867 // Can export from current BB.
868 if (VI->getParent() == FromBB)
871 // Is already exported, noop.
872 return FuncInfo.isExportedInst(V);
875 // If this is an argument, we can export it if the BB is the entry block or
876 // if it is already exported.
877 if (isa<Argument>(V)) {
878 if (FromBB == &FromBB->getParent()->getEntryBlock())
881 // Otherwise, can only export this if it is already exported.
882 return FuncInfo.isExportedInst(V);
885 // Otherwise, constants can always be exported.
889 static bool InBlock(const Value *V, const BasicBlock *BB) {
890 if (const Instruction *I = dyn_cast<Instruction>(V))
891 return I->getParent() == BB;
895 /// FindMergedConditions - If Cond is an expression like
896 void SelectionDAGLowering::FindMergedConditions(Value *Cond,
897 MachineBasicBlock *TBB,
898 MachineBasicBlock *FBB,
899 MachineBasicBlock *CurBB,
901 // If this node is not part of the or/and tree, emit it as a branch.
902 Instruction *BOp = dyn_cast<Instruction>(Cond);
904 if (!BOp || !(isa<BinaryOperator>(BOp) || isa<CmpInst>(BOp)) ||
905 (unsigned)BOp->getOpcode() != Opc || !BOp->hasOneUse() ||
906 BOp->getParent() != CurBB->getBasicBlock() ||
907 !InBlock(BOp->getOperand(0), CurBB->getBasicBlock()) ||
908 !InBlock(BOp->getOperand(1), CurBB->getBasicBlock())) {
909 const BasicBlock *BB = CurBB->getBasicBlock();
911 // If the leaf of the tree is a comparison, merge the condition into
913 if ((isa<ICmpInst>(Cond) || isa<FCmpInst>(Cond)) &&
914 // The operands of the cmp have to be in this block. We don't know
915 // how to export them from some other block. If this is the first block
916 // of the sequence, no exporting is needed.
918 (isExportableFromCurrentBlock(BOp->getOperand(0), BB) &&
919 isExportableFromCurrentBlock(BOp->getOperand(1), BB)))) {
920 BOp = cast<Instruction>(Cond);
921 ISD::CondCode Condition;
922 if (ICmpInst *IC = dyn_cast<ICmpInst>(Cond)) {
923 switch (IC->getPredicate()) {
924 default: assert(0 && "Unknown icmp predicate opcode!");
925 case ICmpInst::ICMP_EQ: Condition = ISD::SETEQ; break;
926 case ICmpInst::ICMP_NE: Condition = ISD::SETNE; break;
927 case ICmpInst::ICMP_SLE: Condition = ISD::SETLE; break;
928 case ICmpInst::ICMP_ULE: Condition = ISD::SETULE; break;
929 case ICmpInst::ICMP_SGE: Condition = ISD::SETGE; break;
930 case ICmpInst::ICMP_UGE: Condition = ISD::SETUGE; break;
931 case ICmpInst::ICMP_SLT: Condition = ISD::SETLT; break;
932 case ICmpInst::ICMP_ULT: Condition = ISD::SETULT; break;
933 case ICmpInst::ICMP_SGT: Condition = ISD::SETGT; break;
934 case ICmpInst::ICMP_UGT: Condition = ISD::SETUGT; break;
936 } else if (FCmpInst *FC = dyn_cast<FCmpInst>(Cond)) {
937 ISD::CondCode FPC, FOC;
938 switch (FC->getPredicate()) {
939 default: assert(0 && "Unknown fcmp predicate opcode!");
940 case FCmpInst::FCMP_FALSE: FOC = FPC = ISD::SETFALSE; break;
941 case FCmpInst::FCMP_OEQ: FOC = ISD::SETEQ; FPC = ISD::SETOEQ; break;
942 case FCmpInst::FCMP_OGT: FOC = ISD::SETGT; FPC = ISD::SETOGT; break;
943 case FCmpInst::FCMP_OGE: FOC = ISD::SETGE; FPC = ISD::SETOGE; break;
944 case FCmpInst::FCMP_OLT: FOC = ISD::SETLT; FPC = ISD::SETOLT; break;
945 case FCmpInst::FCMP_OLE: FOC = ISD::SETLE; FPC = ISD::SETOLE; break;
946 case FCmpInst::FCMP_ONE: FOC = ISD::SETNE; FPC = ISD::SETONE; break;
947 case FCmpInst::FCMP_ORD: FOC = ISD::SETEQ; FPC = ISD::SETO; break;
948 case FCmpInst::FCMP_UNO: FOC = ISD::SETNE; FPC = ISD::SETUO; break;
949 case FCmpInst::FCMP_UEQ: FOC = ISD::SETEQ; FPC = ISD::SETUEQ; break;
950 case FCmpInst::FCMP_UGT: FOC = ISD::SETGT; FPC = ISD::SETUGT; break;
951 case FCmpInst::FCMP_UGE: FOC = ISD::SETGE; FPC = ISD::SETUGE; break;
952 case FCmpInst::FCMP_ULT: FOC = ISD::SETLT; FPC = ISD::SETULT; break;
953 case FCmpInst::FCMP_ULE: FOC = ISD::SETLE; FPC = ISD::SETULE; break;
954 case FCmpInst::FCMP_UNE: FOC = ISD::SETNE; FPC = ISD::SETUNE; break;
955 case FCmpInst::FCMP_TRUE: FOC = FPC = ISD::SETTRUE; break;
957 if (FiniteOnlyFPMath())
962 Condition = ISD::SETEQ; // silence warning.
963 assert(0 && "Unknown compare instruction");
966 SelectionDAGISel::CaseBlock CB(Condition, BOp->getOperand(0),
967 BOp->getOperand(1), NULL, TBB, FBB, CurBB);
968 SwitchCases.push_back(CB);
972 // Create a CaseBlock record representing this branch.
973 SelectionDAGISel::CaseBlock CB(ISD::SETEQ, Cond, ConstantInt::getTrue(),
974 NULL, TBB, FBB, CurBB);
975 SwitchCases.push_back(CB);
980 // Create TmpBB after CurBB.
981 MachineFunction::iterator BBI = CurBB;
982 MachineBasicBlock *TmpBB = new MachineBasicBlock(CurBB->getBasicBlock());
983 CurBB->getParent()->getBasicBlockList().insert(++BBI, TmpBB);
985 if (Opc == Instruction::Or) {
994 // Emit the LHS condition.
995 FindMergedConditions(BOp->getOperand(0), TBB, TmpBB, CurBB, Opc);
997 // Emit the RHS condition into TmpBB.
998 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, Opc);
1000 assert(Opc == Instruction::And && "Unknown merge op!");
1001 // Codegen X & Y as:
1008 // This requires creation of TmpBB after CurBB.
1010 // Emit the LHS condition.
1011 FindMergedConditions(BOp->getOperand(0), TmpBB, FBB, CurBB, Opc);
1013 // Emit the RHS condition into TmpBB.
1014 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, Opc);
1018 /// If the set of cases should be emitted as a series of branches, return true.
1019 /// If we should emit this as a bunch of and/or'd together conditions, return
1022 ShouldEmitAsBranches(const std::vector<SelectionDAGISel::CaseBlock> &Cases) {
1023 if (Cases.size() != 2) return true;
1025 // If this is two comparisons of the same values or'd or and'd together, they
1026 // will get folded into a single comparison, so don't emit two blocks.
1027 if ((Cases[0].CmpLHS == Cases[1].CmpLHS &&
1028 Cases[0].CmpRHS == Cases[1].CmpRHS) ||
1029 (Cases[0].CmpRHS == Cases[1].CmpLHS &&
1030 Cases[0].CmpLHS == Cases[1].CmpRHS)) {
1037 void SelectionDAGLowering::visitBr(BranchInst &I) {
1038 // Update machine-CFG edges.
1039 MachineBasicBlock *Succ0MBB = FuncInfo.MBBMap[I.getSuccessor(0)];
1041 // Figure out which block is immediately after the current one.
1042 MachineBasicBlock *NextBlock = 0;
1043 MachineFunction::iterator BBI = CurMBB;
1044 if (++BBI != CurMBB->getParent()->end())
1047 if (I.isUnconditional()) {
1048 // If this is not a fall-through branch, emit the branch.
1049 if (Succ0MBB != NextBlock)
1050 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, getRoot(),
1051 DAG.getBasicBlock(Succ0MBB)));
1053 // Update machine-CFG edges.
1054 CurMBB->addSuccessor(Succ0MBB);
1059 // If this condition is one of the special cases we handle, do special stuff
1061 Value *CondVal = I.getCondition();
1062 MachineBasicBlock *Succ1MBB = FuncInfo.MBBMap[I.getSuccessor(1)];
1064 // If this is a series of conditions that are or'd or and'd together, emit
1065 // this as a sequence of branches instead of setcc's with and/or operations.
1066 // For example, instead of something like:
1079 if (BinaryOperator *BOp = dyn_cast<BinaryOperator>(CondVal)) {
1080 if (BOp->hasOneUse() &&
1081 (BOp->getOpcode() == Instruction::And ||
1082 BOp->getOpcode() == Instruction::Or)) {
1083 FindMergedConditions(BOp, Succ0MBB, Succ1MBB, CurMBB, BOp->getOpcode());
1084 // If the compares in later blocks need to use values not currently
1085 // exported from this block, export them now. This block should always
1086 // be the first entry.
1087 assert(SwitchCases[0].ThisBB == CurMBB && "Unexpected lowering!");
1089 // Allow some cases to be rejected.
1090 if (ShouldEmitAsBranches(SwitchCases)) {
1091 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i) {
1092 ExportFromCurrentBlock(SwitchCases[i].CmpLHS);
1093 ExportFromCurrentBlock(SwitchCases[i].CmpRHS);
1096 // Emit the branch for this block.
1097 visitSwitchCase(SwitchCases[0]);
1098 SwitchCases.erase(SwitchCases.begin());
1102 // Okay, we decided not to do this, remove any inserted MBB's and clear
1104 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i)
1105 CurMBB->getParent()->getBasicBlockList().erase(SwitchCases[i].ThisBB);
1107 SwitchCases.clear();
1111 // Create a CaseBlock record representing this branch.
1112 SelectionDAGISel::CaseBlock CB(ISD::SETEQ, CondVal, ConstantInt::getTrue(),
1113 NULL, Succ0MBB, Succ1MBB, CurMBB);
1114 // Use visitSwitchCase to actually insert the fast branch sequence for this
1116 visitSwitchCase(CB);
1119 /// visitSwitchCase - Emits the necessary code to represent a single node in
1120 /// the binary search tree resulting from lowering a switch instruction.
1121 void SelectionDAGLowering::visitSwitchCase(SelectionDAGISel::CaseBlock &CB) {
1123 SDOperand CondLHS = getValue(CB.CmpLHS);
1125 // Build the setcc now.
1126 if (CB.CmpMHS == NULL) {
1127 // Fold "(X == true)" to X and "(X == false)" to !X to
1128 // handle common cases produced by branch lowering.
1129 if (CB.CmpRHS == ConstantInt::getTrue() && CB.CC == ISD::SETEQ)
1131 else if (CB.CmpRHS == ConstantInt::getFalse() && CB.CC == ISD::SETEQ) {
1132 SDOperand True = DAG.getConstant(1, CondLHS.getValueType());
1133 Cond = DAG.getNode(ISD::XOR, CondLHS.getValueType(), CondLHS, True);
1135 Cond = DAG.getSetCC(MVT::i1, CondLHS, getValue(CB.CmpRHS), CB.CC);
1137 assert(CB.CC == ISD::SETLE && "Can handle only LE ranges now");
1139 uint64_t Low = cast<ConstantInt>(CB.CmpLHS)->getSExtValue();
1140 uint64_t High = cast<ConstantInt>(CB.CmpRHS)->getSExtValue();
1142 SDOperand CmpOp = getValue(CB.CmpMHS);
1143 MVT::ValueType VT = CmpOp.getValueType();
1145 if (cast<ConstantInt>(CB.CmpLHS)->isMinValue(true)) {
1146 Cond = DAG.getSetCC(MVT::i1, CmpOp, DAG.getConstant(High, VT), ISD::SETLE);
1148 SDOperand SUB = DAG.getNode(ISD::SUB, VT, CmpOp, DAG.getConstant(Low, VT));
1149 Cond = DAG.getSetCC(MVT::i1, SUB,
1150 DAG.getConstant(High-Low, VT), ISD::SETULE);
1155 // Set NextBlock to be the MBB immediately after the current one, if any.
1156 // This is used to avoid emitting unnecessary branches to the next block.
1157 MachineBasicBlock *NextBlock = 0;
1158 MachineFunction::iterator BBI = CurMBB;
1159 if (++BBI != CurMBB->getParent()->end())
1162 // If the lhs block is the next block, invert the condition so that we can
1163 // fall through to the lhs instead of the rhs block.
1164 if (CB.TrueBB == NextBlock) {
1165 std::swap(CB.TrueBB, CB.FalseBB);
1166 SDOperand True = DAG.getConstant(1, Cond.getValueType());
1167 Cond = DAG.getNode(ISD::XOR, Cond.getValueType(), Cond, True);
1169 SDOperand BrCond = DAG.getNode(ISD::BRCOND, MVT::Other, getRoot(), Cond,
1170 DAG.getBasicBlock(CB.TrueBB));
1171 if (CB.FalseBB == NextBlock)
1172 DAG.setRoot(BrCond);
1174 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, BrCond,
1175 DAG.getBasicBlock(CB.FalseBB)));
1176 // Update successor info
1177 CurMBB->addSuccessor(CB.TrueBB);
1178 CurMBB->addSuccessor(CB.FalseBB);
1181 /// visitJumpTable - Emit JumpTable node in the current MBB
1182 void SelectionDAGLowering::visitJumpTable(SelectionDAGISel::JumpTable &JT) {
1183 // Emit the code for the jump table
1184 assert(JT.Reg != -1U && "Should lower JT Header first!");
1185 MVT::ValueType PTy = TLI.getPointerTy();
1186 SDOperand Index = DAG.getCopyFromReg(getRoot(), JT.Reg, PTy);
1187 SDOperand Table = DAG.getJumpTable(JT.JTI, PTy);
1188 DAG.setRoot(DAG.getNode(ISD::BR_JT, MVT::Other, Index.getValue(1),
1193 /// visitJumpTableHeader - This function emits necessary code to produce index
1194 /// in the JumpTable from switch case.
1195 void SelectionDAGLowering::visitJumpTableHeader(SelectionDAGISel::JumpTable &JT,
1196 SelectionDAGISel::JumpTableHeader &JTH) {
1197 // Subtract the lowest switch case value from the value being switched on
1198 // and conditional branch to default mbb if the result is greater than the
1199 // difference between smallest and largest cases.
1200 SDOperand SwitchOp = getValue(JTH.SValue);
1201 MVT::ValueType VT = SwitchOp.getValueType();
1202 SDOperand SUB = DAG.getNode(ISD::SUB, VT, SwitchOp,
1203 DAG.getConstant(JTH.First, VT));
1205 // The SDNode we just created, which holds the value being switched on
1206 // minus the the smallest case value, needs to be copied to a virtual
1207 // register so it can be used as an index into the jump table in a
1208 // subsequent basic block. This value may be smaller or larger than the
1209 // target's pointer type, and therefore require extension or truncating.
1210 if (VT > TLI.getPointerTy())
1211 SwitchOp = DAG.getNode(ISD::TRUNCATE, TLI.getPointerTy(), SUB);
1213 SwitchOp = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(), SUB);
1215 unsigned JumpTableReg = FuncInfo.MakeReg(TLI.getPointerTy());
1216 SDOperand CopyTo = DAG.getCopyToReg(getRoot(), JumpTableReg, SwitchOp);
1217 JT.Reg = JumpTableReg;
1219 // Emit the range check for the jump table, and branch to the default
1220 // block for the switch statement if the value being switched on exceeds
1221 // the largest case in the switch.
1222 SDOperand CMP = DAG.getSetCC(TLI.getSetCCResultTy(), SUB,
1223 DAG.getConstant(JTH.Last-JTH.First,VT),
1226 // Set NextBlock to be the MBB immediately after the current one, if any.
1227 // This is used to avoid emitting unnecessary branches to the next block.
1228 MachineBasicBlock *NextBlock = 0;
1229 MachineFunction::iterator BBI = CurMBB;
1230 if (++BBI != CurMBB->getParent()->end())
1233 SDOperand BrCond = DAG.getNode(ISD::BRCOND, MVT::Other, CopyTo, CMP,
1234 DAG.getBasicBlock(JT.Default));
1236 if (JT.MBB == NextBlock)
1237 DAG.setRoot(BrCond);
1239 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, BrCond,
1240 DAG.getBasicBlock(JT.MBB)));
1245 /// visitBitTestHeader - This function emits necessary code to produce value
1246 /// suitable for "bit tests"
1247 void SelectionDAGLowering::visitBitTestHeader(SelectionDAGISel::BitTestBlock &B) {
1248 // Subtract the minimum value
1249 SDOperand SwitchOp = getValue(B.SValue);
1250 MVT::ValueType VT = SwitchOp.getValueType();
1251 SDOperand SUB = DAG.getNode(ISD::SUB, VT, SwitchOp,
1252 DAG.getConstant(B.First, VT));
1255 SDOperand RangeCmp = DAG.getSetCC(TLI.getSetCCResultTy(), SUB,
1256 DAG.getConstant(B.Range, VT),
1260 if (VT > TLI.getShiftAmountTy())
1261 ShiftOp = DAG.getNode(ISD::TRUNCATE, TLI.getShiftAmountTy(), SUB);
1263 ShiftOp = DAG.getNode(ISD::ZERO_EXTEND, TLI.getShiftAmountTy(), SUB);
1265 // Make desired shift
1266 SDOperand SwitchVal = DAG.getNode(ISD::SHL, TLI.getPointerTy(),
1267 DAG.getConstant(1, TLI.getPointerTy()),
1270 unsigned SwitchReg = FuncInfo.MakeReg(TLI.getPointerTy());
1271 SDOperand CopyTo = DAG.getCopyToReg(getRoot(), SwitchReg, SwitchVal);
1274 SDOperand BrRange = DAG.getNode(ISD::BRCOND, MVT::Other, CopyTo, RangeCmp,
1275 DAG.getBasicBlock(B.Default));
1277 // Set NextBlock to be the MBB immediately after the current one, if any.
1278 // This is used to avoid emitting unnecessary branches to the next block.
1279 MachineBasicBlock *NextBlock = 0;
1280 MachineFunction::iterator BBI = CurMBB;
1281 if (++BBI != CurMBB->getParent()->end())
1284 MachineBasicBlock* MBB = B.Cases[0].ThisBB;
1285 if (MBB == NextBlock)
1286 DAG.setRoot(BrRange);
1288 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, CopyTo,
1289 DAG.getBasicBlock(MBB)));
1291 CurMBB->addSuccessor(B.Default);
1292 CurMBB->addSuccessor(MBB);
1297 /// visitBitTestCase - this function produces one "bit test"
1298 void SelectionDAGLowering::visitBitTestCase(MachineBasicBlock* NextMBB,
1300 SelectionDAGISel::BitTestCase &B) {
1301 // Emit bit tests and jumps
1302 SDOperand SwitchVal = DAG.getCopyFromReg(getRoot(), Reg, TLI.getPointerTy());
1304 SDOperand AndOp = DAG.getNode(ISD::AND, TLI.getPointerTy(),
1306 DAG.getConstant(B.Mask,
1307 TLI.getPointerTy()));
1308 SDOperand AndCmp = DAG.getSetCC(TLI.getSetCCResultTy(), AndOp,
1309 DAG.getConstant(0, TLI.getPointerTy()),
1311 SDOperand BrAnd = DAG.getNode(ISD::BRCOND, MVT::Other, getRoot(),
1312 AndCmp, DAG.getBasicBlock(B.TargetBB));
1314 // Set NextBlock to be the MBB immediately after the current one, if any.
1315 // This is used to avoid emitting unnecessary branches to the next block.
1316 MachineBasicBlock *NextBlock = 0;
1317 MachineFunction::iterator BBI = CurMBB;
1318 if (++BBI != CurMBB->getParent()->end())
1321 if (NextMBB == NextBlock)
1324 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, BrAnd,
1325 DAG.getBasicBlock(NextMBB)));
1327 CurMBB->addSuccessor(B.TargetBB);
1328 CurMBB->addSuccessor(NextMBB);
1333 void SelectionDAGLowering::visitInvoke(InvokeInst &I) {
1334 assert(0 && "Should never be visited directly");
1336 void SelectionDAGLowering::visitInvoke(InvokeInst &I, bool AsTerminator) {
1337 // Retrieve successors.
1338 MachineBasicBlock *Return = FuncInfo.MBBMap[I.getSuccessor(0)];
1339 MachineBasicBlock *LandingPad = FuncInfo.MBBMap[I.getSuccessor(1)];
1341 if (!AsTerminator) {
1342 // Mark landing pad so that it doesn't get deleted in branch folding.
1343 LandingPad->setIsLandingPad();
1345 // Insert a label before the invoke call to mark the try range.
1346 // This can be used to detect deletion of the invoke via the
1347 // MachineModuleInfo.
1348 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
1349 unsigned BeginLabel = MMI->NextLabelID();
1350 DAG.setRoot(DAG.getNode(ISD::LABEL, MVT::Other, getRoot(),
1351 DAG.getConstant(BeginLabel, MVT::i32)));
1353 LowerCallTo(I, I.getCalledValue()->getType(),
1356 getValue(I.getOperand(0)),
1359 // Insert a label before the invoke call to mark the try range.
1360 // This can be used to detect deletion of the invoke via the
1361 // MachineModuleInfo.
1362 unsigned EndLabel = MMI->NextLabelID();
1363 DAG.setRoot(DAG.getNode(ISD::LABEL, MVT::Other, getRoot(),
1364 DAG.getConstant(EndLabel, MVT::i32)));
1366 // Inform MachineModuleInfo of range.
1367 MMI->addInvoke(LandingPad, BeginLabel, EndLabel);
1369 // Update successor info
1370 CurMBB->addSuccessor(Return);
1371 CurMBB->addSuccessor(LandingPad);
1373 // Drop into normal successor.
1374 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, getRoot(),
1375 DAG.getBasicBlock(Return)));
1379 void SelectionDAGLowering::visitUnwind(UnwindInst &I) {
1382 /// handleSmallSwitchCaseRange - Emit a series of specific tests (suitable for
1383 /// small case ranges).
1384 bool SelectionDAGLowering::handleSmallSwitchRange(CaseRec& CR,
1385 CaseRecVector& WorkList,
1387 MachineBasicBlock* Default) {
1388 Case& BackCase = *(CR.Range.second-1);
1390 // Size is the number of Cases represented by this range.
1391 unsigned Size = CR.Range.second - CR.Range.first;
1395 // Get the MachineFunction which holds the current MBB. This is used when
1396 // inserting any additional MBBs necessary to represent the switch.
1397 MachineFunction *CurMF = CurMBB->getParent();
1399 // Figure out which block is immediately after the current one.
1400 MachineBasicBlock *NextBlock = 0;
1401 MachineFunction::iterator BBI = CR.CaseBB;
1403 if (++BBI != CurMBB->getParent()->end())
1406 // TODO: If any two of the cases has the same destination, and if one value
1407 // is the same as the other, but has one bit unset that the other has set,
1408 // use bit manipulation to do two compares at once. For example:
1409 // "if (X == 6 || X == 4)" -> "if ((X|2) == 6)"
1411 // Rearrange the case blocks so that the last one falls through if possible.
1412 if (NextBlock && Default != NextBlock && BackCase.BB != NextBlock) {
1413 // The last case block won't fall through into 'NextBlock' if we emit the
1414 // branches in this order. See if rearranging a case value would help.
1415 for (CaseItr I = CR.Range.first, E = CR.Range.second-1; I != E; ++I) {
1416 if (I->BB == NextBlock) {
1417 std::swap(*I, BackCase);
1423 // Create a CaseBlock record representing a conditional branch to
1424 // the Case's target mbb if the value being switched on SV is equal
1426 MachineBasicBlock *CurBlock = CR.CaseBB;
1427 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++I) {
1428 MachineBasicBlock *FallThrough;
1430 FallThrough = new MachineBasicBlock(CurBlock->getBasicBlock());
1431 CurMF->getBasicBlockList().insert(BBI, FallThrough);
1433 // If the last case doesn't match, go to the default block.
1434 FallThrough = Default;
1437 Value *RHS, *LHS, *MHS;
1439 if (I->High == I->Low) {
1440 // This is just small small case range :) containing exactly 1 case
1442 LHS = SV; RHS = I->High; MHS = NULL;
1445 LHS = I->Low; MHS = SV; RHS = I->High;
1447 SelectionDAGISel::CaseBlock CB(CC, LHS, RHS, MHS,
1448 I->BB, FallThrough, CurBlock);
1450 // If emitting the first comparison, just call visitSwitchCase to emit the
1451 // code into the current block. Otherwise, push the CaseBlock onto the
1452 // vector to be later processed by SDISel, and insert the node's MBB
1453 // before the next MBB.
1454 if (CurBlock == CurMBB)
1455 visitSwitchCase(CB);
1457 SwitchCases.push_back(CB);
1459 CurBlock = FallThrough;
1465 /// handleJTSwitchCase - Emit jumptable for current switch case range
1466 bool SelectionDAGLowering::handleJTSwitchCase(CaseRec& CR,
1467 CaseRecVector& WorkList,
1469 MachineBasicBlock* Default) {
1470 Case& FrontCase = *CR.Range.first;
1471 Case& BackCase = *(CR.Range.second-1);
1473 int64_t First = cast<ConstantInt>(FrontCase.Low)->getSExtValue();
1474 int64_t Last = cast<ConstantInt>(BackCase.High)->getSExtValue();
1477 for (CaseItr I = CR.Range.first, E = CR.Range.second;
1481 if ((!TLI.isOperationLegal(ISD::BR_JT, MVT::Other) &&
1482 !TLI.isOperationLegal(ISD::BRIND, MVT::Other)) ||
1486 double Density = (double)TSize / (double)((Last - First) + 1ULL);
1490 DOUT << "Lowering jump table\n"
1491 << "First entry: " << First << ". Last entry: " << Last << "\n"
1492 << "Size: " << TSize << ". Density: " << Density << "\n\n";
1494 // Get the MachineFunction which holds the current MBB. This is used when
1495 // inserting any additional MBBs necessary to represent the switch.
1496 MachineFunction *CurMF = CurMBB->getParent();
1498 // Figure out which block is immediately after the current one.
1499 MachineBasicBlock *NextBlock = 0;
1500 MachineFunction::iterator BBI = CR.CaseBB;
1502 if (++BBI != CurMBB->getParent()->end())
1505 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
1507 // Create a new basic block to hold the code for loading the address
1508 // of the jump table, and jumping to it. Update successor information;
1509 // we will either branch to the default case for the switch, or the jump
1511 MachineBasicBlock *JumpTableBB = new MachineBasicBlock(LLVMBB);
1512 CurMF->getBasicBlockList().insert(BBI, JumpTableBB);
1513 CR.CaseBB->addSuccessor(Default);
1514 CR.CaseBB->addSuccessor(JumpTableBB);
1516 // Build a vector of destination BBs, corresponding to each target
1517 // of the jump table. If the value of the jump table slot corresponds to
1518 // a case statement, push the case's BB onto the vector, otherwise, push
1520 std::vector<MachineBasicBlock*> DestBBs;
1521 int64_t TEI = First;
1522 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++TEI) {
1523 int64_t Low = cast<ConstantInt>(I->Low)->getSExtValue();
1524 int64_t High = cast<ConstantInt>(I->High)->getSExtValue();
1526 if ((Low <= TEI) && (TEI <= High)) {
1527 DestBBs.push_back(I->BB);
1531 DestBBs.push_back(Default);
1535 // Update successor info. Add one edge to each unique successor.
1536 BitVector SuccsHandled(CR.CaseBB->getParent()->getNumBlockIDs());
1537 for (std::vector<MachineBasicBlock*>::iterator I = DestBBs.begin(),
1538 E = DestBBs.end(); I != E; ++I) {
1539 if (!SuccsHandled[(*I)->getNumber()]) {
1540 SuccsHandled[(*I)->getNumber()] = true;
1541 JumpTableBB->addSuccessor(*I);
1545 // Create a jump table index for this jump table, or return an existing
1547 unsigned JTI = CurMF->getJumpTableInfo()->getJumpTableIndex(DestBBs);
1549 // Set the jump table information so that we can codegen it as a second
1550 // MachineBasicBlock
1551 SelectionDAGISel::JumpTable JT(-1U, JTI, JumpTableBB, Default);
1552 SelectionDAGISel::JumpTableHeader JTH(First, Last, SV, CR.CaseBB,
1553 (CR.CaseBB == CurMBB));
1554 if (CR.CaseBB == CurMBB)
1555 visitJumpTableHeader(JT, JTH);
1557 JTCases.push_back(SelectionDAGISel::JumpTableBlock(JTH, JT));
1562 /// handleBTSplitSwitchCase - emit comparison and split binary search tree into
1564 bool SelectionDAGLowering::handleBTSplitSwitchCase(CaseRec& CR,
1565 CaseRecVector& WorkList,
1567 MachineBasicBlock* Default) {
1568 // Get the MachineFunction which holds the current MBB. This is used when
1569 // inserting any additional MBBs necessary to represent the switch.
1570 MachineFunction *CurMF = CurMBB->getParent();
1572 // Figure out which block is immediately after the current one.
1573 MachineBasicBlock *NextBlock = 0;
1574 MachineFunction::iterator BBI = CR.CaseBB;
1576 if (++BBI != CurMBB->getParent()->end())
1579 Case& FrontCase = *CR.Range.first;
1580 Case& BackCase = *(CR.Range.second-1);
1581 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
1583 // Size is the number of Cases represented by this range.
1584 unsigned Size = CR.Range.second - CR.Range.first;
1586 int64_t First = cast<ConstantInt>(FrontCase.Low)->getSExtValue();
1587 int64_t Last = cast<ConstantInt>(BackCase.High)->getSExtValue();
1589 CaseItr Pivot = CR.Range.first + Size/2;
1591 // Select optimal pivot, maximizing sum density of LHS and RHS. This will
1592 // (heuristically) allow us to emit JumpTable's later.
1594 for (CaseItr I = CR.Range.first, E = CR.Range.second;
1598 uint64_t LSize = FrontCase.size();
1599 uint64_t RSize = TSize-LSize;
1600 DOUT << "Selecting best pivot: \n"
1601 << "First: " << First << ", Last: " << Last <<"\n"
1602 << "LSize: " << LSize << ", RSize: " << RSize << "\n";
1603 for (CaseItr I = CR.Range.first, J=I+1, E = CR.Range.second;
1605 int64_t LEnd = cast<ConstantInt>(I->High)->getSExtValue();
1606 int64_t RBegin = cast<ConstantInt>(J->Low)->getSExtValue();
1607 assert((RBegin-LEnd>=1) && "Invalid case distance");
1608 double LDensity = (double)LSize / (double)((LEnd - First) + 1ULL);
1609 double RDensity = (double)RSize / (double)((Last - RBegin) + 1ULL);
1610 double Metric = Log2_64(RBegin-LEnd)*(LDensity+RDensity);
1611 // Should always split in some non-trivial place
1613 << "LEnd: " << LEnd << ", RBegin: " << RBegin << "\n"
1614 << "LDensity: " << LDensity << ", RDensity: " << RDensity << "\n"
1615 << "Metric: " << Metric << "\n";
1616 if (FMetric < Metric) {
1619 DOUT << "Current metric set to: " << FMetric << "\n";
1625 // If our case is dense we *really* should handle it earlier!
1626 assert((FMetric > 0) && "Should handle dense range earlier!");
1628 CaseRange LHSR(CR.Range.first, Pivot);
1629 CaseRange RHSR(Pivot, CR.Range.second);
1630 Constant *C = Pivot->Low;
1631 MachineBasicBlock *FalseBB = 0, *TrueBB = 0;
1633 // We know that we branch to the LHS if the Value being switched on is
1634 // less than the Pivot value, C. We use this to optimize our binary
1635 // tree a bit, by recognizing that if SV is greater than or equal to the
1636 // LHS's Case Value, and that Case Value is exactly one less than the
1637 // Pivot's Value, then we can branch directly to the LHS's Target,
1638 // rather than creating a leaf node for it.
1639 if ((LHSR.second - LHSR.first) == 1 &&
1640 LHSR.first->High == CR.GE &&
1641 cast<ConstantInt>(C)->getSExtValue() ==
1642 (cast<ConstantInt>(CR.GE)->getSExtValue() + 1LL)) {
1643 TrueBB = LHSR.first->BB;
1645 TrueBB = new MachineBasicBlock(LLVMBB);
1646 CurMF->getBasicBlockList().insert(BBI, TrueBB);
1647 WorkList.push_back(CaseRec(TrueBB, C, CR.GE, LHSR));
1650 // Similar to the optimization above, if the Value being switched on is
1651 // known to be less than the Constant CR.LT, and the current Case Value
1652 // is CR.LT - 1, then we can branch directly to the target block for
1653 // the current Case Value, rather than emitting a RHS leaf node for it.
1654 if ((RHSR.second - RHSR.first) == 1 && CR.LT &&
1655 cast<ConstantInt>(RHSR.first->Low)->getSExtValue() ==
1656 (cast<ConstantInt>(CR.LT)->getSExtValue() - 1LL)) {
1657 FalseBB = RHSR.first->BB;
1659 FalseBB = new MachineBasicBlock(LLVMBB);
1660 CurMF->getBasicBlockList().insert(BBI, FalseBB);
1661 WorkList.push_back(CaseRec(FalseBB,CR.LT,C,RHSR));
1664 // Create a CaseBlock record representing a conditional branch to
1665 // the LHS node if the value being switched on SV is less than C.
1666 // Otherwise, branch to LHS.
1667 SelectionDAGISel::CaseBlock CB(ISD::SETLT, SV, C, NULL,
1668 TrueBB, FalseBB, CR.CaseBB);
1670 if (CR.CaseBB == CurMBB)
1671 visitSwitchCase(CB);
1673 SwitchCases.push_back(CB);
1678 /// handleBitTestsSwitchCase - if current case range has few destination and
1679 /// range span less, than machine word bitwidth, encode case range into series
1680 /// of masks and emit bit tests with these masks.
1681 bool SelectionDAGLowering::handleBitTestsSwitchCase(CaseRec& CR,
1682 CaseRecVector& WorkList,
1684 MachineBasicBlock* Default){
1685 unsigned IntPtrBits = getSizeInBits(TLI.getPointerTy());
1687 Case& FrontCase = *CR.Range.first;
1688 Case& BackCase = *(CR.Range.second-1);
1690 // Get the MachineFunction which holds the current MBB. This is used when
1691 // inserting any additional MBBs necessary to represent the switch.
1692 MachineFunction *CurMF = CurMBB->getParent();
1694 unsigned numCmps = 0;
1695 for (CaseItr I = CR.Range.first, E = CR.Range.second;
1697 // Single case counts one, case range - two.
1698 if (I->Low == I->High)
1704 // Count unique destinations
1705 SmallSet<MachineBasicBlock*, 4> Dests;
1706 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) {
1707 Dests.insert(I->BB);
1708 if (Dests.size() > 3)
1709 // Don't bother the code below, if there are too much unique destinations
1712 DOUT << "Total number of unique destinations: " << Dests.size() << "\n"
1713 << "Total number of comparisons: " << numCmps << "\n";
1715 // Compute span of values.
1716 Constant* minValue = FrontCase.Low;
1717 Constant* maxValue = BackCase.High;
1718 uint64_t range = cast<ConstantInt>(maxValue)->getSExtValue() -
1719 cast<ConstantInt>(minValue)->getSExtValue();
1720 DOUT << "Compare range: " << range << "\n"
1721 << "Low bound: " << cast<ConstantInt>(minValue)->getSExtValue() << "\n"
1722 << "High bound: " << cast<ConstantInt>(maxValue)->getSExtValue() << "\n";
1724 if (range>=IntPtrBits ||
1725 (!(Dests.size() == 1 && numCmps >= 3) &&
1726 !(Dests.size() == 2 && numCmps >= 5) &&
1727 !(Dests.size() >= 3 && numCmps >= 6)))
1730 DOUT << "Emitting bit tests\n";
1731 int64_t lowBound = 0;
1733 // Optimize the case where all the case values fit in a
1734 // word without having to subtract minValue. In this case,
1735 // we can optimize away the subtraction.
1736 if (cast<ConstantInt>(minValue)->getSExtValue() >= 0 &&
1737 cast<ConstantInt>(maxValue)->getSExtValue() < IntPtrBits) {
1738 range = cast<ConstantInt>(maxValue)->getSExtValue();
1740 lowBound = cast<ConstantInt>(minValue)->getSExtValue();
1743 CaseBitsVector CasesBits;
1744 unsigned i, count = 0;
1746 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) {
1747 MachineBasicBlock* Dest = I->BB;
1748 for (i = 0; i < count; ++i)
1749 if (Dest == CasesBits[i].BB)
1753 assert((count < 3) && "Too much destinations to test!");
1754 CasesBits.push_back(CaseBits(0, Dest, 0));
1758 uint64_t lo = cast<ConstantInt>(I->Low)->getSExtValue() - lowBound;
1759 uint64_t hi = cast<ConstantInt>(I->High)->getSExtValue() - lowBound;
1761 for (uint64_t j = lo; j <= hi; j++) {
1762 CasesBits[i].Mask |= 1ULL << j;
1763 CasesBits[i].Bits++;
1767 std::sort(CasesBits.begin(), CasesBits.end(), CaseBitsCmp());
1769 SelectionDAGISel::BitTestInfo BTC;
1771 // Figure out which block is immediately after the current one.
1772 MachineFunction::iterator BBI = CR.CaseBB;
1775 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
1778 for (unsigned i = 0, e = CasesBits.size(); i!=e; ++i) {
1779 DOUT << "Mask: " << CasesBits[i].Mask << ", Bits: " << CasesBits[i].Bits
1780 << ", BB: " << CasesBits[i].BB << "\n";
1782 MachineBasicBlock *CaseBB = new MachineBasicBlock(LLVMBB);
1783 CurMF->getBasicBlockList().insert(BBI, CaseBB);
1784 BTC.push_back(SelectionDAGISel::BitTestCase(CasesBits[i].Mask,
1789 SelectionDAGISel::BitTestBlock BTB(lowBound, range, SV,
1790 -1U, (CR.CaseBB == CurMBB),
1791 CR.CaseBB, Default, BTC);
1793 if (CR.CaseBB == CurMBB)
1794 visitBitTestHeader(BTB);
1796 BitTestCases.push_back(BTB);
1802 // Clusterify - Transform simple list of Cases into list of CaseRange's
1803 unsigned SelectionDAGLowering::Clusterify(CaseVector& Cases,
1804 const SwitchInst& SI) {
1805 unsigned numCmps = 0;
1807 // Start with "simple" cases
1808 for (unsigned i = 1; i < SI.getNumSuccessors(); ++i) {
1809 MachineBasicBlock *SMBB = FuncInfo.MBBMap[SI.getSuccessor(i)];
1810 Cases.push_back(Case(SI.getSuccessorValue(i),
1811 SI.getSuccessorValue(i),
1814 sort(Cases.begin(), Cases.end(), CaseCmp());
1816 // Merge case into clusters
1817 if (Cases.size()>=2)
1818 for (CaseItr I=Cases.begin(), J=++(Cases.begin()), E=Cases.end(); J!=E; ) {
1819 int64_t nextValue = cast<ConstantInt>(J->Low)->getSExtValue();
1820 int64_t currentValue = cast<ConstantInt>(I->High)->getSExtValue();
1821 MachineBasicBlock* nextBB = J->BB;
1822 MachineBasicBlock* currentBB = I->BB;
1824 // If the two neighboring cases go to the same destination, merge them
1825 // into a single case.
1826 if ((nextValue-currentValue==1) && (currentBB == nextBB)) {
1834 for (CaseItr I=Cases.begin(), E=Cases.end(); I!=E; ++I, ++numCmps) {
1835 if (I->Low != I->High)
1836 // A range counts double, since it requires two compares.
1843 void SelectionDAGLowering::visitSwitch(SwitchInst &SI) {
1844 // Figure out which block is immediately after the current one.
1845 MachineBasicBlock *NextBlock = 0;
1846 MachineFunction::iterator BBI = CurMBB;
1848 MachineBasicBlock *Default = FuncInfo.MBBMap[SI.getDefaultDest()];
1850 // If there is only the default destination, branch to it if it is not the
1851 // next basic block. Otherwise, just fall through.
1852 if (SI.getNumOperands() == 2) {
1853 // Update machine-CFG edges.
1855 // If this is not a fall-through branch, emit the branch.
1856 if (Default != NextBlock)
1857 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, getRoot(),
1858 DAG.getBasicBlock(Default)));
1860 CurMBB->addSuccessor(Default);
1864 // If there are any non-default case statements, create a vector of Cases
1865 // representing each one, and sort the vector so that we can efficiently
1866 // create a binary search tree from them.
1868 unsigned numCmps = Clusterify(Cases, SI);
1869 DOUT << "Clusterify finished. Total clusters: " << Cases.size()
1870 << ". Total compares: " << numCmps << "\n";
1872 // Get the Value to be switched on and default basic blocks, which will be
1873 // inserted into CaseBlock records, representing basic blocks in the binary
1875 Value *SV = SI.getOperand(0);
1877 // Push the initial CaseRec onto the worklist
1878 CaseRecVector WorkList;
1879 WorkList.push_back(CaseRec(CurMBB,0,0,CaseRange(Cases.begin(),Cases.end())));
1881 while (!WorkList.empty()) {
1882 // Grab a record representing a case range to process off the worklist
1883 CaseRec CR = WorkList.back();
1884 WorkList.pop_back();
1886 if (handleBitTestsSwitchCase(CR, WorkList, SV, Default))
1889 // If the range has few cases (two or less) emit a series of specific
1891 if (handleSmallSwitchRange(CR, WorkList, SV, Default))
1894 // If the switch has more than 5 blocks, and at least 40% dense, and the
1895 // target supports indirect branches, then emit a jump table rather than
1896 // lowering the switch to a binary tree of conditional branches.
1897 if (handleJTSwitchCase(CR, WorkList, SV, Default))
1900 // Emit binary tree. We need to pick a pivot, and push left and right ranges
1901 // onto the worklist. Leafs are handled via handleSmallSwitchRange() call.
1902 handleBTSplitSwitchCase(CR, WorkList, SV, Default);
1907 void SelectionDAGLowering::visitSub(User &I) {
1908 // -0.0 - X --> fneg
1909 const Type *Ty = I.getType();
1910 if (isa<VectorType>(Ty)) {
1911 visitVectorBinary(I, ISD::VSUB);
1912 } else if (Ty->isFloatingPoint()) {
1913 if (ConstantFP *CFP = dyn_cast<ConstantFP>(I.getOperand(0)))
1914 if (CFP->isExactlyValue(-0.0)) {
1915 SDOperand Op2 = getValue(I.getOperand(1));
1916 setValue(&I, DAG.getNode(ISD::FNEG, Op2.getValueType(), Op2));
1919 visitScalarBinary(I, ISD::FSUB);
1921 visitScalarBinary(I, ISD::SUB);
1924 void SelectionDAGLowering::visitScalarBinary(User &I, unsigned OpCode) {
1925 SDOperand Op1 = getValue(I.getOperand(0));
1926 SDOperand Op2 = getValue(I.getOperand(1));
1928 setValue(&I, DAG.getNode(OpCode, Op1.getValueType(), Op1, Op2));
1932 SelectionDAGLowering::visitVectorBinary(User &I, unsigned OpCode) {
1933 assert(isa<VectorType>(I.getType()));
1934 const VectorType *Ty = cast<VectorType>(I.getType());
1935 SDOperand Typ = DAG.getValueType(TLI.getValueType(Ty->getElementType()));
1937 setValue(&I, DAG.getNode(OpCode, MVT::Vector,
1938 getValue(I.getOperand(0)),
1939 getValue(I.getOperand(1)),
1940 DAG.getConstant(Ty->getNumElements(), MVT::i32),
1944 void SelectionDAGLowering::visitEitherBinary(User &I, unsigned ScalarOp,
1945 unsigned VectorOp) {
1946 if (isa<VectorType>(I.getType()))
1947 visitVectorBinary(I, VectorOp);
1949 visitScalarBinary(I, ScalarOp);
1952 void SelectionDAGLowering::visitShift(User &I, unsigned Opcode) {
1953 SDOperand Op1 = getValue(I.getOperand(0));
1954 SDOperand Op2 = getValue(I.getOperand(1));
1956 if (TLI.getShiftAmountTy() < Op2.getValueType())
1957 Op2 = DAG.getNode(ISD::TRUNCATE, TLI.getShiftAmountTy(), Op2);
1958 else if (TLI.getShiftAmountTy() > Op2.getValueType())
1959 Op2 = DAG.getNode(ISD::ANY_EXTEND, TLI.getShiftAmountTy(), Op2);
1961 setValue(&I, DAG.getNode(Opcode, Op1.getValueType(), Op1, Op2));
1964 void SelectionDAGLowering::visitICmp(User &I) {
1965 ICmpInst::Predicate predicate = ICmpInst::BAD_ICMP_PREDICATE;
1966 if (ICmpInst *IC = dyn_cast<ICmpInst>(&I))
1967 predicate = IC->getPredicate();
1968 else if (ConstantExpr *IC = dyn_cast<ConstantExpr>(&I))
1969 predicate = ICmpInst::Predicate(IC->getPredicate());
1970 SDOperand Op1 = getValue(I.getOperand(0));
1971 SDOperand Op2 = getValue(I.getOperand(1));
1972 ISD::CondCode Opcode;
1973 switch (predicate) {
1974 case ICmpInst::ICMP_EQ : Opcode = ISD::SETEQ; break;
1975 case ICmpInst::ICMP_NE : Opcode = ISD::SETNE; break;
1976 case ICmpInst::ICMP_UGT : Opcode = ISD::SETUGT; break;
1977 case ICmpInst::ICMP_UGE : Opcode = ISD::SETUGE; break;
1978 case ICmpInst::ICMP_ULT : Opcode = ISD::SETULT; break;
1979 case ICmpInst::ICMP_ULE : Opcode = ISD::SETULE; break;
1980 case ICmpInst::ICMP_SGT : Opcode = ISD::SETGT; break;
1981 case ICmpInst::ICMP_SGE : Opcode = ISD::SETGE; break;
1982 case ICmpInst::ICMP_SLT : Opcode = ISD::SETLT; break;
1983 case ICmpInst::ICMP_SLE : Opcode = ISD::SETLE; break;
1985 assert(!"Invalid ICmp predicate value");
1986 Opcode = ISD::SETEQ;
1989 setValue(&I, DAG.getSetCC(MVT::i1, Op1, Op2, Opcode));
1992 void SelectionDAGLowering::visitFCmp(User &I) {
1993 FCmpInst::Predicate predicate = FCmpInst::BAD_FCMP_PREDICATE;
1994 if (FCmpInst *FC = dyn_cast<FCmpInst>(&I))
1995 predicate = FC->getPredicate();
1996 else if (ConstantExpr *FC = dyn_cast<ConstantExpr>(&I))
1997 predicate = FCmpInst::Predicate(FC->getPredicate());
1998 SDOperand Op1 = getValue(I.getOperand(0));
1999 SDOperand Op2 = getValue(I.getOperand(1));
2000 ISD::CondCode Condition, FOC, FPC;
2001 switch (predicate) {
2002 case FCmpInst::FCMP_FALSE: FOC = FPC = ISD::SETFALSE; break;
2003 case FCmpInst::FCMP_OEQ: FOC = ISD::SETEQ; FPC = ISD::SETOEQ; break;
2004 case FCmpInst::FCMP_OGT: FOC = ISD::SETGT; FPC = ISD::SETOGT; break;
2005 case FCmpInst::FCMP_OGE: FOC = ISD::SETGE; FPC = ISD::SETOGE; break;
2006 case FCmpInst::FCMP_OLT: FOC = ISD::SETLT; FPC = ISD::SETOLT; break;
2007 case FCmpInst::FCMP_OLE: FOC = ISD::SETLE; FPC = ISD::SETOLE; break;
2008 case FCmpInst::FCMP_ONE: FOC = ISD::SETNE; FPC = ISD::SETONE; break;
2009 case FCmpInst::FCMP_ORD: FOC = ISD::SETEQ; FPC = ISD::SETO; break;
2010 case FCmpInst::FCMP_UNO: FOC = ISD::SETNE; FPC = ISD::SETUO; break;
2011 case FCmpInst::FCMP_UEQ: FOC = ISD::SETEQ; FPC = ISD::SETUEQ; break;
2012 case FCmpInst::FCMP_UGT: FOC = ISD::SETGT; FPC = ISD::SETUGT; break;
2013 case FCmpInst::FCMP_UGE: FOC = ISD::SETGE; FPC = ISD::SETUGE; break;
2014 case FCmpInst::FCMP_ULT: FOC = ISD::SETLT; FPC = ISD::SETULT; break;
2015 case FCmpInst::FCMP_ULE: FOC = ISD::SETLE; FPC = ISD::SETULE; break;
2016 case FCmpInst::FCMP_UNE: FOC = ISD::SETNE; FPC = ISD::SETUNE; break;
2017 case FCmpInst::FCMP_TRUE: FOC = FPC = ISD::SETTRUE; break;
2019 assert(!"Invalid FCmp predicate value");
2020 FOC = FPC = ISD::SETFALSE;
2023 if (FiniteOnlyFPMath())
2027 setValue(&I, DAG.getSetCC(MVT::i1, Op1, Op2, Condition));
2030 void SelectionDAGLowering::visitSelect(User &I) {
2031 SDOperand Cond = getValue(I.getOperand(0));
2032 SDOperand TrueVal = getValue(I.getOperand(1));
2033 SDOperand FalseVal = getValue(I.getOperand(2));
2034 if (!isa<VectorType>(I.getType())) {
2035 setValue(&I, DAG.getNode(ISD::SELECT, TrueVal.getValueType(), Cond,
2036 TrueVal, FalseVal));
2038 setValue(&I, DAG.getNode(ISD::VSELECT, MVT::Vector, Cond, TrueVal, FalseVal,
2039 *(TrueVal.Val->op_end()-2),
2040 *(TrueVal.Val->op_end()-1)));
2045 void SelectionDAGLowering::visitTrunc(User &I) {
2046 // TruncInst cannot be a no-op cast because sizeof(src) > sizeof(dest).
2047 SDOperand N = getValue(I.getOperand(0));
2048 MVT::ValueType DestVT = TLI.getValueType(I.getType());
2049 setValue(&I, DAG.getNode(ISD::TRUNCATE, DestVT, N));
2052 void SelectionDAGLowering::visitZExt(User &I) {
2053 // ZExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
2054 // ZExt also can't be a cast to bool for same reason. So, nothing much to do
2055 SDOperand N = getValue(I.getOperand(0));
2056 MVT::ValueType DestVT = TLI.getValueType(I.getType());
2057 setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, DestVT, N));
2060 void SelectionDAGLowering::visitSExt(User &I) {
2061 // SExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
2062 // SExt also can't be a cast to bool for same reason. So, nothing much to do
2063 SDOperand N = getValue(I.getOperand(0));
2064 MVT::ValueType DestVT = TLI.getValueType(I.getType());
2065 setValue(&I, DAG.getNode(ISD::SIGN_EXTEND, DestVT, N));
2068 void SelectionDAGLowering::visitFPTrunc(User &I) {
2069 // FPTrunc is never a no-op cast, no need to check
2070 SDOperand N = getValue(I.getOperand(0));
2071 MVT::ValueType DestVT = TLI.getValueType(I.getType());
2072 setValue(&I, DAG.getNode(ISD::FP_ROUND, DestVT, N));
2075 void SelectionDAGLowering::visitFPExt(User &I){
2076 // FPTrunc is never a no-op cast, no need to check
2077 SDOperand N = getValue(I.getOperand(0));
2078 MVT::ValueType DestVT = TLI.getValueType(I.getType());
2079 setValue(&I, DAG.getNode(ISD::FP_EXTEND, DestVT, N));
2082 void SelectionDAGLowering::visitFPToUI(User &I) {
2083 // FPToUI is never a no-op cast, no need to check
2084 SDOperand N = getValue(I.getOperand(0));
2085 MVT::ValueType DestVT = TLI.getValueType(I.getType());
2086 setValue(&I, DAG.getNode(ISD::FP_TO_UINT, DestVT, N));
2089 void SelectionDAGLowering::visitFPToSI(User &I) {
2090 // FPToSI is never a no-op cast, no need to check
2091 SDOperand N = getValue(I.getOperand(0));
2092 MVT::ValueType DestVT = TLI.getValueType(I.getType());
2093 setValue(&I, DAG.getNode(ISD::FP_TO_SINT, DestVT, N));
2096 void SelectionDAGLowering::visitUIToFP(User &I) {
2097 // UIToFP is never a no-op cast, no need to check
2098 SDOperand N = getValue(I.getOperand(0));
2099 MVT::ValueType DestVT = TLI.getValueType(I.getType());
2100 setValue(&I, DAG.getNode(ISD::UINT_TO_FP, DestVT, N));
2103 void SelectionDAGLowering::visitSIToFP(User &I){
2104 // UIToFP is never a no-op cast, no need to check
2105 SDOperand N = getValue(I.getOperand(0));
2106 MVT::ValueType DestVT = TLI.getValueType(I.getType());
2107 setValue(&I, DAG.getNode(ISD::SINT_TO_FP, DestVT, N));
2110 void SelectionDAGLowering::visitPtrToInt(User &I) {
2111 // What to do depends on the size of the integer and the size of the pointer.
2112 // We can either truncate, zero extend, or no-op, accordingly.
2113 SDOperand N = getValue(I.getOperand(0));
2114 MVT::ValueType SrcVT = N.getValueType();
2115 MVT::ValueType DestVT = TLI.getValueType(I.getType());
2117 if (MVT::getSizeInBits(DestVT) < MVT::getSizeInBits(SrcVT))
2118 Result = DAG.getNode(ISD::TRUNCATE, DestVT, N);
2120 // Note: ZERO_EXTEND can handle cases where the sizes are equal too
2121 Result = DAG.getNode(ISD::ZERO_EXTEND, DestVT, N);
2122 setValue(&I, Result);
2125 void SelectionDAGLowering::visitIntToPtr(User &I) {
2126 // What to do depends on the size of the integer and the size of the pointer.
2127 // We can either truncate, zero extend, or no-op, accordingly.
2128 SDOperand N = getValue(I.getOperand(0));
2129 MVT::ValueType SrcVT = N.getValueType();
2130 MVT::ValueType DestVT = TLI.getValueType(I.getType());
2131 if (MVT::getSizeInBits(DestVT) < MVT::getSizeInBits(SrcVT))
2132 setValue(&I, DAG.getNode(ISD::TRUNCATE, DestVT, N));
2134 // Note: ZERO_EXTEND can handle cases where the sizes are equal too
2135 setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, DestVT, N));
2138 void SelectionDAGLowering::visitBitCast(User &I) {
2139 SDOperand N = getValue(I.getOperand(0));
2140 MVT::ValueType DestVT = TLI.getValueType(I.getType());
2141 if (DestVT == MVT::Vector) {
2142 // This is a cast to a vector from something else.
2143 // Get information about the output vector.
2144 const VectorType *DestTy = cast<VectorType>(I.getType());
2145 MVT::ValueType EltVT = TLI.getValueType(DestTy->getElementType());
2146 setValue(&I, DAG.getNode(ISD::VBIT_CONVERT, DestVT, N,
2147 DAG.getConstant(DestTy->getNumElements(),MVT::i32),
2148 DAG.getValueType(EltVT)));
2151 MVT::ValueType SrcVT = N.getValueType();
2152 if (SrcVT == MVT::Vector) {
2153 // This is a cast from a vctor to something else.
2154 // Get information about the input vector.
2155 setValue(&I, DAG.getNode(ISD::VBIT_CONVERT, DestVT, N));
2159 // BitCast assures us that source and destination are the same size so this
2160 // is either a BIT_CONVERT or a no-op.
2161 if (DestVT != N.getValueType())
2162 setValue(&I, DAG.getNode(ISD::BIT_CONVERT, DestVT, N)); // convert types
2164 setValue(&I, N); // noop cast.
2167 void SelectionDAGLowering::visitInsertElement(User &I) {
2168 SDOperand InVec = getValue(I.getOperand(0));
2169 SDOperand InVal = getValue(I.getOperand(1));
2170 SDOperand InIdx = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(),
2171 getValue(I.getOperand(2)));
2173 SDOperand Num = *(InVec.Val->op_end()-2);
2174 SDOperand Typ = *(InVec.Val->op_end()-1);
2175 setValue(&I, DAG.getNode(ISD::VINSERT_VECTOR_ELT, MVT::Vector,
2176 InVec, InVal, InIdx, Num, Typ));
2179 void SelectionDAGLowering::visitExtractElement(User &I) {
2180 SDOperand InVec = getValue(I.getOperand(0));
2181 SDOperand InIdx = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(),
2182 getValue(I.getOperand(1)));
2183 SDOperand Typ = *(InVec.Val->op_end()-1);
2184 setValue(&I, DAG.getNode(ISD::VEXTRACT_VECTOR_ELT,
2185 TLI.getValueType(I.getType()), InVec, InIdx));
2188 void SelectionDAGLowering::visitShuffleVector(User &I) {
2189 SDOperand V1 = getValue(I.getOperand(0));
2190 SDOperand V2 = getValue(I.getOperand(1));
2191 SDOperand Mask = getValue(I.getOperand(2));
2193 SDOperand Num = *(V1.Val->op_end()-2);
2194 SDOperand Typ = *(V2.Val->op_end()-1);
2195 setValue(&I, DAG.getNode(ISD::VVECTOR_SHUFFLE, MVT::Vector,
2196 V1, V2, Mask, Num, Typ));
2200 void SelectionDAGLowering::visitGetElementPtr(User &I) {
2201 SDOperand N = getValue(I.getOperand(0));
2202 const Type *Ty = I.getOperand(0)->getType();
2204 for (GetElementPtrInst::op_iterator OI = I.op_begin()+1, E = I.op_end();
2207 if (const StructType *StTy = dyn_cast<StructType>(Ty)) {
2208 unsigned Field = cast<ConstantInt>(Idx)->getZExtValue();
2211 uint64_t Offset = TD->getStructLayout(StTy)->getElementOffset(Field);
2212 N = DAG.getNode(ISD::ADD, N.getValueType(), N,
2213 getIntPtrConstant(Offset));
2215 Ty = StTy->getElementType(Field);
2217 Ty = cast<SequentialType>(Ty)->getElementType();
2219 // If this is a constant subscript, handle it quickly.
2220 if (ConstantInt *CI = dyn_cast<ConstantInt>(Idx)) {
2221 if (CI->getZExtValue() == 0) continue;
2223 TD->getTypeSize(Ty)*cast<ConstantInt>(CI)->getSExtValue();
2224 N = DAG.getNode(ISD::ADD, N.getValueType(), N, getIntPtrConstant(Offs));
2228 // N = N + Idx * ElementSize;
2229 uint64_t ElementSize = TD->getTypeSize(Ty);
2230 SDOperand IdxN = getValue(Idx);
2232 // If the index is smaller or larger than intptr_t, truncate or extend
2234 if (IdxN.getValueType() < N.getValueType()) {
2235 IdxN = DAG.getNode(ISD::SIGN_EXTEND, N.getValueType(), IdxN);
2236 } else if (IdxN.getValueType() > N.getValueType())
2237 IdxN = DAG.getNode(ISD::TRUNCATE, N.getValueType(), IdxN);
2239 // If this is a multiply by a power of two, turn it into a shl
2240 // immediately. This is a very common case.
2241 if (isPowerOf2_64(ElementSize)) {
2242 unsigned Amt = Log2_64(ElementSize);
2243 IdxN = DAG.getNode(ISD::SHL, N.getValueType(), IdxN,
2244 DAG.getConstant(Amt, TLI.getShiftAmountTy()));
2245 N = DAG.getNode(ISD::ADD, N.getValueType(), N, IdxN);
2249 SDOperand Scale = getIntPtrConstant(ElementSize);
2250 IdxN = DAG.getNode(ISD::MUL, N.getValueType(), IdxN, Scale);
2251 N = DAG.getNode(ISD::ADD, N.getValueType(), N, IdxN);
2257 void SelectionDAGLowering::visitAlloca(AllocaInst &I) {
2258 // If this is a fixed sized alloca in the entry block of the function,
2259 // allocate it statically on the stack.
2260 if (FuncInfo.StaticAllocaMap.count(&I))
2261 return; // getValue will auto-populate this.
2263 const Type *Ty = I.getAllocatedType();
2264 uint64_t TySize = TLI.getTargetData()->getTypeSize(Ty);
2266 std::max((unsigned)TLI.getTargetData()->getPrefTypeAlignment(Ty),
2269 SDOperand AllocSize = getValue(I.getArraySize());
2270 MVT::ValueType IntPtr = TLI.getPointerTy();
2271 if (IntPtr < AllocSize.getValueType())
2272 AllocSize = DAG.getNode(ISD::TRUNCATE, IntPtr, AllocSize);
2273 else if (IntPtr > AllocSize.getValueType())
2274 AllocSize = DAG.getNode(ISD::ZERO_EXTEND, IntPtr, AllocSize);
2276 AllocSize = DAG.getNode(ISD::MUL, IntPtr, AllocSize,
2277 getIntPtrConstant(TySize));
2279 // Handle alignment. If the requested alignment is less than or equal to the
2280 // stack alignment, ignore it and round the size of the allocation up to the
2281 // stack alignment size. If the size is greater than the stack alignment, we
2282 // note this in the DYNAMIC_STACKALLOC node.
2283 unsigned StackAlign =
2284 TLI.getTargetMachine().getFrameInfo()->getStackAlignment();
2285 if (Align <= StackAlign) {
2287 // Add SA-1 to the size.
2288 AllocSize = DAG.getNode(ISD::ADD, AllocSize.getValueType(), AllocSize,
2289 getIntPtrConstant(StackAlign-1));
2290 // Mask out the low bits for alignment purposes.
2291 AllocSize = DAG.getNode(ISD::AND, AllocSize.getValueType(), AllocSize,
2292 getIntPtrConstant(~(uint64_t)(StackAlign-1)));
2295 SDOperand Ops[] = { getRoot(), AllocSize, getIntPtrConstant(Align) };
2296 const MVT::ValueType *VTs = DAG.getNodeValueTypes(AllocSize.getValueType(),
2298 SDOperand DSA = DAG.getNode(ISD::DYNAMIC_STACKALLOC, VTs, 2, Ops, 3);
2300 DAG.setRoot(DSA.getValue(1));
2302 // Inform the Frame Information that we have just allocated a variable-sized
2304 CurMBB->getParent()->getFrameInfo()->CreateVariableSizedObject();
2307 void SelectionDAGLowering::visitLoad(LoadInst &I) {
2308 SDOperand Ptr = getValue(I.getOperand(0));
2314 // Do not serialize non-volatile loads against each other.
2315 Root = DAG.getRoot();
2318 setValue(&I, getLoadFrom(I.getType(), Ptr, I.getOperand(0),
2319 Root, I.isVolatile(), I.getAlignment()));
2322 SDOperand SelectionDAGLowering::getLoadFrom(const Type *Ty, SDOperand Ptr,
2323 const Value *SV, SDOperand Root,
2325 unsigned Alignment) {
2327 if (const VectorType *PTy = dyn_cast<VectorType>(Ty)) {
2328 MVT::ValueType PVT = TLI.getValueType(PTy->getElementType());
2329 L = DAG.getVecLoad(PTy->getNumElements(), PVT, Root, Ptr,
2330 DAG.getSrcValue(SV));
2332 L = DAG.getLoad(TLI.getValueType(Ty), Root, Ptr, SV, 0,
2333 isVolatile, Alignment);
2337 DAG.setRoot(L.getValue(1));
2339 PendingLoads.push_back(L.getValue(1));
2345 void SelectionDAGLowering::visitStore(StoreInst &I) {
2346 Value *SrcV = I.getOperand(0);
2347 SDOperand Src = getValue(SrcV);
2348 SDOperand Ptr = getValue(I.getOperand(1));
2349 DAG.setRoot(DAG.getStore(getRoot(), Src, Ptr, I.getOperand(1), 0,
2350 I.isVolatile(), I.getAlignment()));
2353 /// IntrinsicCannotAccessMemory - Return true if the specified intrinsic cannot
2354 /// access memory and has no other side effects at all.
2355 static bool IntrinsicCannotAccessMemory(unsigned IntrinsicID) {
2356 #define GET_NO_MEMORY_INTRINSICS
2357 #include "llvm/Intrinsics.gen"
2358 #undef GET_NO_MEMORY_INTRINSICS
2362 // IntrinsicOnlyReadsMemory - Return true if the specified intrinsic doesn't
2363 // have any side-effects or if it only reads memory.
2364 static bool IntrinsicOnlyReadsMemory(unsigned IntrinsicID) {
2365 #define GET_SIDE_EFFECT_INFO
2366 #include "llvm/Intrinsics.gen"
2367 #undef GET_SIDE_EFFECT_INFO
2371 /// visitTargetIntrinsic - Lower a call of a target intrinsic to an INTRINSIC
2373 void SelectionDAGLowering::visitTargetIntrinsic(CallInst &I,
2374 unsigned Intrinsic) {
2375 bool HasChain = !IntrinsicCannotAccessMemory(Intrinsic);
2376 bool OnlyLoad = HasChain && IntrinsicOnlyReadsMemory(Intrinsic);
2378 // Build the operand list.
2379 SmallVector<SDOperand, 8> Ops;
2380 if (HasChain) { // If this intrinsic has side-effects, chainify it.
2382 // We don't need to serialize loads against other loads.
2383 Ops.push_back(DAG.getRoot());
2385 Ops.push_back(getRoot());
2389 // Add the intrinsic ID as an integer operand.
2390 Ops.push_back(DAG.getConstant(Intrinsic, TLI.getPointerTy()));
2392 // Add all operands of the call to the operand list.
2393 for (unsigned i = 1, e = I.getNumOperands(); i != e; ++i) {
2394 SDOperand Op = getValue(I.getOperand(i));
2396 // If this is a vector type, force it to the right vector type.
2397 if (Op.getValueType() == MVT::Vector) {
2398 const VectorType *OpTy = cast<VectorType>(I.getOperand(i)->getType());
2399 MVT::ValueType EltVT = TLI.getValueType(OpTy->getElementType());
2401 MVT::ValueType VVT = MVT::getVectorType(EltVT, OpTy->getNumElements());
2402 assert(VVT != MVT::Other && "Intrinsic uses a non-legal type?");
2403 Op = DAG.getNode(ISD::VBIT_CONVERT, VVT, Op);
2406 assert(TLI.isTypeLegal(Op.getValueType()) &&
2407 "Intrinsic uses a non-legal type?");
2411 std::vector<MVT::ValueType> VTs;
2412 if (I.getType() != Type::VoidTy) {
2413 MVT::ValueType VT = TLI.getValueType(I.getType());
2414 if (VT == MVT::Vector) {
2415 const VectorType *DestTy = cast<VectorType>(I.getType());
2416 MVT::ValueType EltVT = TLI.getValueType(DestTy->getElementType());
2418 VT = MVT::getVectorType(EltVT, DestTy->getNumElements());
2419 assert(VT != MVT::Other && "Intrinsic uses a non-legal type?");
2422 assert(TLI.isTypeLegal(VT) && "Intrinsic uses a non-legal type?");
2426 VTs.push_back(MVT::Other);
2428 const MVT::ValueType *VTList = DAG.getNodeValueTypes(VTs);
2433 Result = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, VTList, VTs.size(),
2434 &Ops[0], Ops.size());
2435 else if (I.getType() != Type::VoidTy)
2436 Result = DAG.getNode(ISD::INTRINSIC_W_CHAIN, VTList, VTs.size(),
2437 &Ops[0], Ops.size());
2439 Result = DAG.getNode(ISD::INTRINSIC_VOID, VTList, VTs.size(),
2440 &Ops[0], Ops.size());
2443 SDOperand Chain = Result.getValue(Result.Val->getNumValues()-1);
2445 PendingLoads.push_back(Chain);
2449 if (I.getType() != Type::VoidTy) {
2450 if (const VectorType *PTy = dyn_cast<VectorType>(I.getType())) {
2451 MVT::ValueType EVT = TLI.getValueType(PTy->getElementType());
2452 Result = DAG.getNode(ISD::VBIT_CONVERT, MVT::Vector, Result,
2453 DAG.getConstant(PTy->getNumElements(), MVT::i32),
2454 DAG.getValueType(EVT));
2456 setValue(&I, Result);
2460 /// visitIntrinsicCall - Lower the call to the specified intrinsic function. If
2461 /// we want to emit this as a call to a named external function, return the name
2462 /// otherwise lower it and return null.
2464 SelectionDAGLowering::visitIntrinsicCall(CallInst &I, unsigned Intrinsic) {
2465 switch (Intrinsic) {
2467 // By default, turn this into a target intrinsic node.
2468 visitTargetIntrinsic(I, Intrinsic);
2470 case Intrinsic::vastart: visitVAStart(I); return 0;
2471 case Intrinsic::vaend: visitVAEnd(I); return 0;
2472 case Intrinsic::vacopy: visitVACopy(I); return 0;
2473 case Intrinsic::returnaddress:
2474 setValue(&I, DAG.getNode(ISD::RETURNADDR, TLI.getPointerTy(),
2475 getValue(I.getOperand(1))));
2477 case Intrinsic::frameaddress:
2478 setValue(&I, DAG.getNode(ISD::FRAMEADDR, TLI.getPointerTy(),
2479 getValue(I.getOperand(1))));
2481 case Intrinsic::setjmp:
2482 return "_setjmp"+!TLI.usesUnderscoreSetJmp();
2484 case Intrinsic::longjmp:
2485 return "_longjmp"+!TLI.usesUnderscoreLongJmp();
2487 case Intrinsic::memcpy_i32:
2488 case Intrinsic::memcpy_i64:
2489 visitMemIntrinsic(I, ISD::MEMCPY);
2491 case Intrinsic::memset_i32:
2492 case Intrinsic::memset_i64:
2493 visitMemIntrinsic(I, ISD::MEMSET);
2495 case Intrinsic::memmove_i32:
2496 case Intrinsic::memmove_i64:
2497 visitMemIntrinsic(I, ISD::MEMMOVE);
2500 case Intrinsic::dbg_stoppoint: {
2501 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
2502 DbgStopPointInst &SPI = cast<DbgStopPointInst>(I);
2503 if (MMI && SPI.getContext() && MMI->Verify(SPI.getContext())) {
2507 Ops[1] = getValue(SPI.getLineValue());
2508 Ops[2] = getValue(SPI.getColumnValue());
2510 DebugInfoDesc *DD = MMI->getDescFor(SPI.getContext());
2511 assert(DD && "Not a debug information descriptor");
2512 CompileUnitDesc *CompileUnit = cast<CompileUnitDesc>(DD);
2514 Ops[3] = DAG.getString(CompileUnit->getFileName());
2515 Ops[4] = DAG.getString(CompileUnit->getDirectory());
2517 DAG.setRoot(DAG.getNode(ISD::LOCATION, MVT::Other, Ops, 5));
2522 case Intrinsic::dbg_region_start: {
2523 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
2524 DbgRegionStartInst &RSI = cast<DbgRegionStartInst>(I);
2525 if (MMI && RSI.getContext() && MMI->Verify(RSI.getContext())) {
2526 unsigned LabelID = MMI->RecordRegionStart(RSI.getContext());
2527 DAG.setRoot(DAG.getNode(ISD::LABEL, MVT::Other, getRoot(),
2528 DAG.getConstant(LabelID, MVT::i32)));
2533 case Intrinsic::dbg_region_end: {
2534 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
2535 DbgRegionEndInst &REI = cast<DbgRegionEndInst>(I);
2536 if (MMI && REI.getContext() && MMI->Verify(REI.getContext())) {
2537 unsigned LabelID = MMI->RecordRegionEnd(REI.getContext());
2538 DAG.setRoot(DAG.getNode(ISD::LABEL, MVT::Other,
2539 getRoot(), DAG.getConstant(LabelID, MVT::i32)));
2544 case Intrinsic::dbg_func_start: {
2545 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
2546 DbgFuncStartInst &FSI = cast<DbgFuncStartInst>(I);
2547 if (MMI && FSI.getSubprogram() &&
2548 MMI->Verify(FSI.getSubprogram())) {
2549 unsigned LabelID = MMI->RecordRegionStart(FSI.getSubprogram());
2550 DAG.setRoot(DAG.getNode(ISD::LABEL, MVT::Other,
2551 getRoot(), DAG.getConstant(LabelID, MVT::i32)));
2556 case Intrinsic::dbg_declare: {
2557 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
2558 DbgDeclareInst &DI = cast<DbgDeclareInst>(I);
2559 if (MMI && DI.getVariable() && MMI->Verify(DI.getVariable())) {
2560 SDOperand AddressOp = getValue(DI.getAddress());
2561 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(AddressOp))
2562 MMI->RecordVariable(DI.getVariable(), FI->getIndex());
2568 case Intrinsic::eh_exception: {
2569 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
2572 // Add a label to mark the beginning of the landing pad. Deletion of the
2573 // landing pad can thus be detected via the MachineModuleInfo.
2574 unsigned LabelID = MMI->addLandingPad(CurMBB);
2575 DAG.setRoot(DAG.getNode(ISD::LABEL, MVT::Other, DAG.getEntryNode(),
2576 DAG.getConstant(LabelID, MVT::i32)));
2578 // Mark exception register as live in.
2579 unsigned Reg = TLI.getExceptionAddressRegister();
2580 if (Reg) CurMBB->addLiveIn(Reg);
2582 // Insert the EXCEPTIONADDR instruction.
2583 SDVTList VTs = DAG.getVTList(TLI.getPointerTy(), MVT::Other);
2585 Ops[0] = DAG.getRoot();
2586 SDOperand Op = DAG.getNode(ISD::EXCEPTIONADDR, VTs, Ops, 1);
2588 DAG.setRoot(Op.getValue(1));
2590 setValue(&I, DAG.getConstant(0, TLI.getPointerTy()));
2595 case Intrinsic::eh_selector:
2596 case Intrinsic::eh_filter:{
2597 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
2600 // Inform the MachineModuleInfo of the personality for this landing pad.
2601 ConstantExpr *CE = dyn_cast<ConstantExpr>(I.getOperand(2));
2602 assert(CE && CE->getOpcode() == Instruction::BitCast &&
2603 isa<Function>(CE->getOperand(0)) &&
2604 "Personality should be a function");
2605 MMI->addPersonality(CurMBB, cast<Function>(CE->getOperand(0)));
2606 if (Intrinsic == Intrinsic::eh_filter)
2607 MMI->setIsFilterLandingPad(CurMBB);
2609 // Gather all the type infos for this landing pad and pass them along to
2610 // MachineModuleInfo.
2611 std::vector<GlobalVariable *> TyInfo;
2612 for (unsigned i = 3, N = I.getNumOperands(); i < N; ++i) {
2613 Constant *C = cast<Constant>(I.getOperand(i));
2614 if (GlobalVariable *GV = dyn_cast<GlobalVariable>(C)) {
2615 TyInfo.push_back(GV);
2616 } else if (ConstantExpr *CE = dyn_cast<ConstantExpr>(C)) {
2617 assert(CE->getOpcode() == Instruction::BitCast &&
2618 isa<GlobalVariable>(CE->getOperand(0))
2619 && "TypeInfo must be a global variable or NULL");
2620 TyInfo.push_back(cast<GlobalVariable>(CE->getOperand(0)));
2622 ConstantInt *CI = dyn_cast<ConstantInt>(C);
2623 assert(CI && CI->isNullValue() &&
2624 "TypeInfo must be a global variable or NULL");
2625 TyInfo.push_back(NULL);
2628 MMI->addCatchTypeInfo(CurMBB, TyInfo);
2630 // Mark exception selector register as live in.
2631 unsigned Reg = TLI.getExceptionSelectorRegister();
2632 if (Reg) CurMBB->addLiveIn(Reg);
2634 // Insert the EHSELECTION instruction.
2635 SDVTList VTs = DAG.getVTList(MVT::i32, MVT::Other);
2637 Ops[0] = getValue(I.getOperand(1));
2639 SDOperand Op = DAG.getNode(ISD::EHSELECTION, VTs, Ops, 2);
2641 DAG.setRoot(Op.getValue(1));
2643 setValue(&I, DAG.getConstant(0, MVT::i32));
2649 case Intrinsic::eh_typeid_for: {
2650 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
2653 // Find the type id for the given typeinfo.
2654 GlobalVariable *GV = NULL;
2655 ConstantExpr *CE = dyn_cast<ConstantExpr>(I.getOperand(1));
2656 if (CE && CE->getOpcode() == Instruction::BitCast &&
2657 isa<GlobalVariable>(CE->getOperand(0))) {
2658 GV = cast<GlobalVariable>(CE->getOperand(0));
2660 ConstantInt *CI = dyn_cast<ConstantInt>(I.getOperand(1));
2661 assert(CI && CI->getZExtValue() == 0 &&
2662 "TypeInfo must be a global variable typeinfo or NULL");
2666 unsigned TypeID = MMI->getTypeIDFor(GV);
2667 setValue(&I, DAG.getConstant(TypeID, MVT::i32));
2669 setValue(&I, DAG.getConstant(0, MVT::i32));
2675 case Intrinsic::sqrt_f32:
2676 case Intrinsic::sqrt_f64:
2677 setValue(&I, DAG.getNode(ISD::FSQRT,
2678 getValue(I.getOperand(1)).getValueType(),
2679 getValue(I.getOperand(1))));
2681 case Intrinsic::powi_f32:
2682 case Intrinsic::powi_f64:
2683 setValue(&I, DAG.getNode(ISD::FPOWI,
2684 getValue(I.getOperand(1)).getValueType(),
2685 getValue(I.getOperand(1)),
2686 getValue(I.getOperand(2))));
2688 case Intrinsic::pcmarker: {
2689 SDOperand Tmp = getValue(I.getOperand(1));
2690 DAG.setRoot(DAG.getNode(ISD::PCMARKER, MVT::Other, getRoot(), Tmp));
2693 case Intrinsic::readcyclecounter: {
2694 SDOperand Op = getRoot();
2695 SDOperand Tmp = DAG.getNode(ISD::READCYCLECOUNTER,
2696 DAG.getNodeValueTypes(MVT::i64, MVT::Other), 2,
2699 DAG.setRoot(Tmp.getValue(1));
2702 case Intrinsic::part_select: {
2703 // Currently not implemented: just abort
2704 assert(0 && "part_select intrinsic not implemented");
2707 case Intrinsic::part_set: {
2708 // Currently not implemented: just abort
2709 assert(0 && "part_set intrinsic not implemented");
2712 case Intrinsic::bswap:
2713 setValue(&I, DAG.getNode(ISD::BSWAP,
2714 getValue(I.getOperand(1)).getValueType(),
2715 getValue(I.getOperand(1))));
2717 case Intrinsic::cttz: {
2718 SDOperand Arg = getValue(I.getOperand(1));
2719 MVT::ValueType Ty = Arg.getValueType();
2720 SDOperand result = DAG.getNode(ISD::CTTZ, Ty, Arg);
2722 result = DAG.getNode(ISD::ZERO_EXTEND, MVT::i32, result);
2723 else if (Ty > MVT::i32)
2724 result = DAG.getNode(ISD::TRUNCATE, MVT::i32, result);
2725 setValue(&I, result);
2728 case Intrinsic::ctlz: {
2729 SDOperand Arg = getValue(I.getOperand(1));
2730 MVT::ValueType Ty = Arg.getValueType();
2731 SDOperand result = DAG.getNode(ISD::CTLZ, Ty, Arg);
2733 result = DAG.getNode(ISD::ZERO_EXTEND, MVT::i32, result);
2734 else if (Ty > MVT::i32)
2735 result = DAG.getNode(ISD::TRUNCATE, MVT::i32, result);
2736 setValue(&I, result);
2739 case Intrinsic::ctpop: {
2740 SDOperand Arg = getValue(I.getOperand(1));
2741 MVT::ValueType Ty = Arg.getValueType();
2742 SDOperand result = DAG.getNode(ISD::CTPOP, Ty, Arg);
2744 result = DAG.getNode(ISD::ZERO_EXTEND, MVT::i32, result);
2745 else if (Ty > MVT::i32)
2746 result = DAG.getNode(ISD::TRUNCATE, MVT::i32, result);
2747 setValue(&I, result);
2750 case Intrinsic::stacksave: {
2751 SDOperand Op = getRoot();
2752 SDOperand Tmp = DAG.getNode(ISD::STACKSAVE,
2753 DAG.getNodeValueTypes(TLI.getPointerTy(), MVT::Other), 2, &Op, 1);
2755 DAG.setRoot(Tmp.getValue(1));
2758 case Intrinsic::stackrestore: {
2759 SDOperand Tmp = getValue(I.getOperand(1));
2760 DAG.setRoot(DAG.getNode(ISD::STACKRESTORE, MVT::Other, getRoot(), Tmp));
2763 case Intrinsic::prefetch:
2764 // FIXME: Currently discarding prefetches.
2770 void SelectionDAGLowering::LowerCallTo(Instruction &I,
2771 const Type *CalledValueTy,
2772 unsigned CallingConv,
2774 SDOperand Callee, unsigned OpIdx) {
2775 const PointerType *PT = cast<PointerType>(CalledValueTy);
2776 const FunctionType *FTy = cast<FunctionType>(PT->getElementType());
2777 const ParamAttrsList *Attrs = FTy->getParamAttrs();
2779 TargetLowering::ArgListTy Args;
2780 TargetLowering::ArgListEntry Entry;
2781 Args.reserve(I.getNumOperands());
2782 for (unsigned i = OpIdx, e = I.getNumOperands(); i != e; ++i) {
2783 Value *Arg = I.getOperand(i);
2784 SDOperand ArgNode = getValue(Arg);
2785 Entry.Node = ArgNode; Entry.Ty = Arg->getType();
2786 Entry.isSExt = Attrs && Attrs->paramHasAttr(i, ParamAttr::SExt);
2787 Entry.isZExt = Attrs && Attrs->paramHasAttr(i, ParamAttr::ZExt);
2788 Entry.isInReg = Attrs && Attrs->paramHasAttr(i, ParamAttr::InReg);
2789 Entry.isSRet = Attrs && Attrs->paramHasAttr(i, ParamAttr::StructRet);
2790 Args.push_back(Entry);
2793 std::pair<SDOperand,SDOperand> Result =
2794 TLI.LowerCallTo(getRoot(), I.getType(),
2795 Attrs && Attrs->paramHasAttr(0, ParamAttr::SExt),
2796 FTy->isVarArg(), CallingConv, IsTailCall,
2798 if (I.getType() != Type::VoidTy)
2799 setValue(&I, Result.first);
2800 DAG.setRoot(Result.second);
2804 void SelectionDAGLowering::visitCall(CallInst &I) {
2805 const char *RenameFn = 0;
2806 if (Function *F = I.getCalledFunction()) {
2807 if (F->isDeclaration())
2808 if (unsigned IID = F->getIntrinsicID()) {
2809 RenameFn = visitIntrinsicCall(I, IID);
2812 } else { // Not an LLVM intrinsic.
2813 const std::string &Name = F->getName();
2814 if (Name[0] == 'c' && (Name == "copysign" || Name == "copysignf")) {
2815 if (I.getNumOperands() == 3 && // Basic sanity checks.
2816 I.getOperand(1)->getType()->isFloatingPoint() &&
2817 I.getType() == I.getOperand(1)->getType() &&
2818 I.getType() == I.getOperand(2)->getType()) {
2819 SDOperand LHS = getValue(I.getOperand(1));
2820 SDOperand RHS = getValue(I.getOperand(2));
2821 setValue(&I, DAG.getNode(ISD::FCOPYSIGN, LHS.getValueType(),
2825 } else if (Name[0] == 'f' && (Name == "fabs" || Name == "fabsf")) {
2826 if (I.getNumOperands() == 2 && // Basic sanity checks.
2827 I.getOperand(1)->getType()->isFloatingPoint() &&
2828 I.getType() == I.getOperand(1)->getType()) {
2829 SDOperand Tmp = getValue(I.getOperand(1));
2830 setValue(&I, DAG.getNode(ISD::FABS, Tmp.getValueType(), Tmp));
2833 } else if (Name[0] == 's' && (Name == "sin" || Name == "sinf")) {
2834 if (I.getNumOperands() == 2 && // Basic sanity checks.
2835 I.getOperand(1)->getType()->isFloatingPoint() &&
2836 I.getType() == I.getOperand(1)->getType()) {
2837 SDOperand Tmp = getValue(I.getOperand(1));
2838 setValue(&I, DAG.getNode(ISD::FSIN, Tmp.getValueType(), Tmp));
2841 } else if (Name[0] == 'c' && (Name == "cos" || Name == "cosf")) {
2842 if (I.getNumOperands() == 2 && // Basic sanity checks.
2843 I.getOperand(1)->getType()->isFloatingPoint() &&
2844 I.getType() == I.getOperand(1)->getType()) {
2845 SDOperand Tmp = getValue(I.getOperand(1));
2846 setValue(&I, DAG.getNode(ISD::FCOS, Tmp.getValueType(), Tmp));
2851 } else if (isa<InlineAsm>(I.getOperand(0))) {
2858 Callee = getValue(I.getOperand(0));
2860 Callee = DAG.getExternalSymbol(RenameFn, TLI.getPointerTy());
2862 LowerCallTo(I, I.getCalledValue()->getType(),
2870 SDOperand RegsForValue::getCopyFromRegs(SelectionDAG &DAG,
2871 SDOperand &Chain, SDOperand &Flag)const{
2872 SDOperand Val = DAG.getCopyFromReg(Chain, Regs[0], RegVT, Flag);
2873 Chain = Val.getValue(1);
2874 Flag = Val.getValue(2);
2876 // If the result was expanded, copy from the top part.
2877 if (Regs.size() > 1) {
2878 assert(Regs.size() == 2 &&
2879 "Cannot expand to more than 2 elts yet!");
2880 SDOperand Hi = DAG.getCopyFromReg(Chain, Regs[1], RegVT, Flag);
2881 Chain = Hi.getValue(1);
2882 Flag = Hi.getValue(2);
2883 if (DAG.getTargetLoweringInfo().isLittleEndian())
2884 return DAG.getNode(ISD::BUILD_PAIR, ValueVT, Val, Hi);
2886 return DAG.getNode(ISD::BUILD_PAIR, ValueVT, Hi, Val);
2889 // Otherwise, if the return value was promoted or extended, truncate it to the
2890 // appropriate type.
2891 if (RegVT == ValueVT)
2894 if (MVT::isVector(RegVT)) {
2895 assert(ValueVT == MVT::Vector && "Unknown vector conversion!");
2896 return DAG.getNode(ISD::VBIT_CONVERT, MVT::Vector, Val,
2897 DAG.getConstant(MVT::getVectorNumElements(RegVT),
2899 DAG.getValueType(MVT::getVectorBaseType(RegVT)));
2902 if (MVT::isInteger(RegVT)) {
2903 if (ValueVT < RegVT)
2904 return DAG.getNode(ISD::TRUNCATE, ValueVT, Val);
2906 return DAG.getNode(ISD::ANY_EXTEND, ValueVT, Val);
2909 assert(MVT::isFloatingPoint(RegVT) && MVT::isFloatingPoint(ValueVT));
2910 return DAG.getNode(ISD::FP_ROUND, ValueVT, Val);
2913 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
2914 /// specified value into the registers specified by this object. This uses
2915 /// Chain/Flag as the input and updates them for the output Chain/Flag.
2916 void RegsForValue::getCopyToRegs(SDOperand Val, SelectionDAG &DAG,
2917 SDOperand &Chain, SDOperand &Flag,
2918 MVT::ValueType PtrVT) const {
2919 if (Regs.size() == 1) {
2920 // If there is a single register and the types differ, this must be
2922 if (RegVT != ValueVT) {
2923 if (MVT::isVector(RegVT)) {
2924 assert(Val.getValueType() == MVT::Vector &&"Not a vector-vector cast?");
2925 Val = DAG.getNode(ISD::VBIT_CONVERT, RegVT, Val);
2926 } else if (MVT::isInteger(RegVT) && MVT::isInteger(Val.getValueType())) {
2927 if (RegVT < ValueVT)
2928 Val = DAG.getNode(ISD::TRUNCATE, RegVT, Val);
2930 Val = DAG.getNode(ISD::ANY_EXTEND, RegVT, Val);
2931 } else if (MVT::isFloatingPoint(RegVT) &&
2932 MVT::isFloatingPoint(Val.getValueType())) {
2933 Val = DAG.getNode(ISD::FP_EXTEND, RegVT, Val);
2934 } else if (MVT::getSizeInBits(RegVT) ==
2935 MVT::getSizeInBits(Val.getValueType())) {
2936 Val = DAG.getNode(ISD::BIT_CONVERT, RegVT, Val);
2938 assert(0 && "Unknown mismatch!");
2941 Chain = DAG.getCopyToReg(Chain, Regs[0], Val, Flag);
2942 Flag = Chain.getValue(1);
2944 std::vector<unsigned> R(Regs);
2945 if (!DAG.getTargetLoweringInfo().isLittleEndian())
2946 std::reverse(R.begin(), R.end());
2948 for (unsigned i = 0, e = R.size(); i != e; ++i) {
2949 SDOperand Part = DAG.getNode(ISD::EXTRACT_ELEMENT, RegVT, Val,
2950 DAG.getConstant(i, PtrVT));
2951 Chain = DAG.getCopyToReg(Chain, R[i], Part, Flag);
2952 Flag = Chain.getValue(1);
2957 /// AddInlineAsmOperands - Add this value to the specified inlineasm node
2958 /// operand list. This adds the code marker and includes the number of
2959 /// values added into it.
2960 void RegsForValue::AddInlineAsmOperands(unsigned Code, SelectionDAG &DAG,
2961 std::vector<SDOperand> &Ops) const {
2962 MVT::ValueType IntPtrTy = DAG.getTargetLoweringInfo().getPointerTy();
2963 Ops.push_back(DAG.getTargetConstant(Code | (Regs.size() << 3), IntPtrTy));
2964 for (unsigned i = 0, e = Regs.size(); i != e; ++i)
2965 Ops.push_back(DAG.getRegister(Regs[i], RegVT));
2968 /// isAllocatableRegister - If the specified register is safe to allocate,
2969 /// i.e. it isn't a stack pointer or some other special register, return the
2970 /// register class for the register. Otherwise, return null.
2971 static const TargetRegisterClass *
2972 isAllocatableRegister(unsigned Reg, MachineFunction &MF,
2973 const TargetLowering &TLI, const MRegisterInfo *MRI) {
2974 MVT::ValueType FoundVT = MVT::Other;
2975 const TargetRegisterClass *FoundRC = 0;
2976 for (MRegisterInfo::regclass_iterator RCI = MRI->regclass_begin(),
2977 E = MRI->regclass_end(); RCI != E; ++RCI) {
2978 MVT::ValueType ThisVT = MVT::Other;
2980 const TargetRegisterClass *RC = *RCI;
2981 // If none of the the value types for this register class are valid, we
2982 // can't use it. For example, 64-bit reg classes on 32-bit targets.
2983 for (TargetRegisterClass::vt_iterator I = RC->vt_begin(), E = RC->vt_end();
2985 if (TLI.isTypeLegal(*I)) {
2986 // If we have already found this register in a different register class,
2987 // choose the one with the largest VT specified. For example, on
2988 // PowerPC, we favor f64 register classes over f32.
2989 if (FoundVT == MVT::Other ||
2990 MVT::getSizeInBits(FoundVT) < MVT::getSizeInBits(*I)) {
2997 if (ThisVT == MVT::Other) continue;
2999 // NOTE: This isn't ideal. In particular, this might allocate the
3000 // frame pointer in functions that need it (due to them not being taken
3001 // out of allocation, because a variable sized allocation hasn't been seen
3002 // yet). This is a slight code pessimization, but should still work.
3003 for (TargetRegisterClass::iterator I = RC->allocation_order_begin(MF),
3004 E = RC->allocation_order_end(MF); I != E; ++I)
3006 // We found a matching register class. Keep looking at others in case
3007 // we find one with larger registers that this physreg is also in.
3016 RegsForValue SelectionDAGLowering::
3017 GetRegistersForValue(const std::string &ConstrCode,
3018 MVT::ValueType VT, bool isOutReg, bool isInReg,
3019 std::set<unsigned> &OutputRegs,
3020 std::set<unsigned> &InputRegs) {
3021 std::pair<unsigned, const TargetRegisterClass*> PhysReg =
3022 TLI.getRegForInlineAsmConstraint(ConstrCode, VT);
3023 std::vector<unsigned> Regs;
3025 unsigned NumRegs = VT != MVT::Other ? TLI.getNumElements(VT) : 1;
3026 MVT::ValueType RegVT;
3027 MVT::ValueType ValueVT = VT;
3029 // If this is a constraint for a specific physical register, like {r17},
3031 if (PhysReg.first) {
3032 if (VT == MVT::Other)
3033 ValueVT = *PhysReg.second->vt_begin();
3035 // Get the actual register value type. This is important, because the user
3036 // may have asked for (e.g.) the AX register in i32 type. We need to
3037 // remember that AX is actually i16 to get the right extension.
3038 RegVT = *PhysReg.second->vt_begin();
3040 // This is a explicit reference to a physical register.
3041 Regs.push_back(PhysReg.first);
3043 // If this is an expanded reference, add the rest of the regs to Regs.
3045 TargetRegisterClass::iterator I = PhysReg.second->begin();
3046 TargetRegisterClass::iterator E = PhysReg.second->end();
3047 for (; *I != PhysReg.first; ++I)
3048 assert(I != E && "Didn't find reg!");
3050 // Already added the first reg.
3052 for (; NumRegs; --NumRegs, ++I) {
3053 assert(I != E && "Ran out of registers to allocate!");
3057 return RegsForValue(Regs, RegVT, ValueVT);
3060 // Otherwise, if this was a reference to an LLVM register class, create vregs
3061 // for this reference.
3062 std::vector<unsigned> RegClassRegs;
3063 if (PhysReg.second) {
3064 // If this is an early clobber or tied register, our regalloc doesn't know
3065 // how to maintain the constraint. If it isn't, go ahead and create vreg
3066 // and let the regalloc do the right thing.
3067 if (!isOutReg || !isInReg) {
3068 RegVT = *PhysReg.second->vt_begin();
3070 if (VT == MVT::Other)
3073 // Create the appropriate number of virtual registers.
3074 SSARegMap *RegMap = DAG.getMachineFunction().getSSARegMap();
3075 for (; NumRegs; --NumRegs)
3076 Regs.push_back(RegMap->createVirtualRegister(PhysReg.second));
3078 return RegsForValue(Regs, RegVT, ValueVT);
3081 // Otherwise, we can't allocate it. Let the code below figure out how to
3082 // maintain these constraints.
3083 RegClassRegs.assign(PhysReg.second->begin(), PhysReg.second->end());
3086 // This is a reference to a register class that doesn't directly correspond
3087 // to an LLVM register class. Allocate NumRegs consecutive, available,
3088 // registers from the class.
3089 RegClassRegs = TLI.getRegClassForInlineAsmConstraint(ConstrCode, VT);
3092 const MRegisterInfo *MRI = DAG.getTarget().getRegisterInfo();
3093 MachineFunction &MF = *CurMBB->getParent();
3094 unsigned NumAllocated = 0;
3095 for (unsigned i = 0, e = RegClassRegs.size(); i != e; ++i) {
3096 unsigned Reg = RegClassRegs[i];
3097 // See if this register is available.
3098 if ((isOutReg && OutputRegs.count(Reg)) || // Already used.
3099 (isInReg && InputRegs.count(Reg))) { // Already used.
3100 // Make sure we find consecutive registers.
3105 // Check to see if this register is allocatable (i.e. don't give out the
3107 const TargetRegisterClass *RC = isAllocatableRegister(Reg, MF, TLI, MRI);
3109 // Make sure we find consecutive registers.
3114 // Okay, this register is good, we can use it.
3117 // If we allocated enough consecutive registers, succeed.
3118 if (NumAllocated == NumRegs) {
3119 unsigned RegStart = (i-NumAllocated)+1;
3120 unsigned RegEnd = i+1;
3121 // Mark all of the allocated registers used.
3122 for (unsigned i = RegStart; i != RegEnd; ++i) {
3123 unsigned Reg = RegClassRegs[i];
3124 Regs.push_back(Reg);
3125 if (isOutReg) OutputRegs.insert(Reg); // Mark reg used.
3126 if (isInReg) InputRegs.insert(Reg); // Mark reg used.
3129 return RegsForValue(Regs, *RC->vt_begin(), VT);
3133 // Otherwise, we couldn't allocate enough registers for this.
3134 return RegsForValue();
3137 /// getConstraintGenerality - Return an integer indicating how general CT is.
3138 static unsigned getConstraintGenerality(TargetLowering::ConstraintType CT) {
3140 default: assert(0 && "Unknown constraint type!");
3141 case TargetLowering::C_Other:
3142 case TargetLowering::C_Unknown:
3144 case TargetLowering::C_Register:
3146 case TargetLowering::C_RegisterClass:
3148 case TargetLowering::C_Memory:
3153 static std::string GetMostGeneralConstraint(std::vector<std::string> &C,
3154 const TargetLowering &TLI) {
3155 assert(!C.empty() && "Must have at least one constraint");
3156 if (C.size() == 1) return C[0];
3158 std::string *Current = &C[0];
3159 // If we have multiple constraints, try to pick the most general one ahead
3160 // of time. This isn't a wonderful solution, but handles common cases.
3161 TargetLowering::ConstraintType Flavor = TLI.getConstraintType(Current[0]);
3162 for (unsigned j = 1, e = C.size(); j != e; ++j) {
3163 TargetLowering::ConstraintType ThisFlavor = TLI.getConstraintType(C[j]);
3164 if (getConstraintGenerality(ThisFlavor) >
3165 getConstraintGenerality(Flavor)) {
3166 // This constraint letter is more general than the previous one,
3168 Flavor = ThisFlavor;
3176 /// AsmOperandInfo - This contains information for each constraint that we are
3178 struct AsmOperandInfo : public InlineAsm::ConstraintInfo {
3179 /// ConstraintCode - This contains the actual string for the code, like "m".
3180 std::string ConstraintCode;
3182 /// ConstraintType - Information about the constraint code, e.g. Register,
3183 /// RegisterClass, Memory, Other, Unknown.
3184 TargetLowering::ConstraintType ConstraintType;
3186 /// CallOperand/CallOperandval - If this is the result output operand or a
3187 /// clobber, this is null, otherwise it is the incoming operand to the
3188 /// CallInst. This gets modified as the asm is processed.
3189 SDOperand CallOperand;
3190 Value *CallOperandVal;
3192 /// ConstraintVT - The ValueType for the operand value.
3193 MVT::ValueType ConstraintVT;
3195 AsmOperandInfo(const InlineAsm::ConstraintInfo &info)
3196 : InlineAsm::ConstraintInfo(info),
3197 ConstraintType(TargetLowering::C_Unknown),
3198 CallOperand(0,0), CallOperandVal(0), ConstraintVT(MVT::Other) {
3201 } // end anon namespace.
3203 /// visitInlineAsm - Handle a call to an InlineAsm object.
3205 void SelectionDAGLowering::visitInlineAsm(CallInst &I) {
3206 InlineAsm *IA = cast<InlineAsm>(I.getOperand(0));
3208 /// ConstraintOperands - Information about all of the constraints.
3209 std::vector<AsmOperandInfo> ConstraintOperands;
3211 SDOperand Chain = getRoot();
3214 std::set<unsigned> OutputRegs, InputRegs;
3216 // Do a prepass over the constraints, canonicalizing them, and building up the
3217 // ConstraintOperands list.
3218 std::vector<InlineAsm::ConstraintInfo>
3219 ConstraintInfos = IA->ParseConstraints();
3221 for (unsigned i = 0, e = ConstraintInfos.size(); i != e; ++i) {
3222 ConstraintOperands.push_back(AsmOperandInfo(ConstraintInfos[i]));
3223 AsmOperandInfo &OpInfo = ConstraintOperands.back();
3225 MVT::ValueType OpVT = MVT::Other;
3227 // Compute the value type for each operand.
3228 switch (OpInfo.Type) {
3229 case InlineAsm::isOutput:
3230 if (!OpInfo.isIndirect) {
3231 // The return value of the call is this value. As such, there is no
3232 // corresponding argument.
3233 assert(I.getType() != Type::VoidTy && "Bad inline asm!");
3234 OpVT = TLI.getValueType(I.getType());
3236 OpInfo.CallOperandVal = I.getOperand(OpNo++);
3239 case InlineAsm::isInput:
3240 OpInfo.CallOperandVal = I.getOperand(OpNo++);
3242 case InlineAsm::isClobber:
3247 // If this is an input or an indirect output, process the call argument.
3248 if (OpInfo.CallOperandVal) {
3249 OpInfo.CallOperand = getValue(OpInfo.CallOperandVal);
3250 const Type *OpTy = OpInfo.CallOperandVal->getType();
3251 if (!OpInfo.isIndirect) {
3252 // Must be an input.
3253 OpVT = TLI.getValueType(OpTy);
3255 OpVT = TLI.getValueType(cast<PointerType>(OpTy)->getElementType(),true);
3259 OpInfo.ConstraintVT = OpVT;
3261 // Compute the constraint code to use.
3262 OpInfo.ConstraintCode = GetMostGeneralConstraint(OpInfo.Codes, TLI);
3264 // Compute the constraint type.
3265 // FIXME: merge this into GetMostGeneralConstraint.
3266 OpInfo.ConstraintType = TLI.getConstraintType(OpInfo.ConstraintCode);
3268 if (TLI.getRegForInlineAsmConstraint(OpInfo.ConstraintCode, OpVT).first ==0)
3269 continue; // Not assigned a fixed reg.
3271 // For GCC register classes where we don't have a direct match, we fully
3272 // assign registers at isel time. This is not optimal, but works.
3274 // Build a list of regs that this operand uses. This always has a single
3275 // element for promoted/expanded operands.
3276 RegsForValue Regs = GetRegistersForValue(OpInfo.ConstraintCode, OpVT,
3278 OutputRegs, InputRegs);
3280 switch (OpInfo.Type) {
3281 case InlineAsm::isOutput:
3282 // We can't assign any other output to this register.
3283 OutputRegs.insert(Regs.Regs.begin(), Regs.Regs.end());
3284 // If this is an early-clobber output, it cannot be assigned to the same
3285 // value as the input reg.
3286 if (OpInfo.isEarlyClobber || OpInfo.hasMatchingInput)
3287 InputRegs.insert(Regs.Regs.begin(), Regs.Regs.end());
3289 case InlineAsm::isInput:
3290 // We can't assign any other input to this register.
3291 InputRegs.insert(Regs.Regs.begin(), Regs.Regs.end());
3293 case InlineAsm::isClobber:
3294 // Clobbered regs cannot be used as inputs or outputs.
3295 InputRegs.insert(Regs.Regs.begin(), Regs.Regs.end());
3296 OutputRegs.insert(Regs.Regs.begin(), Regs.Regs.end());
3301 ConstraintInfos.clear();
3304 // AsmNodeOperands - The operands for the ISD::INLINEASM node.
3305 std::vector<SDOperand> AsmNodeOperands;
3306 AsmNodeOperands.push_back(SDOperand()); // reserve space for input chain
3307 AsmNodeOperands.push_back(
3308 DAG.getTargetExternalSymbol(IA->getAsmString().c_str(), MVT::Other));
3311 // Loop over all of the inputs, copying the operand values into the
3312 // appropriate registers and processing the output regs.
3313 RegsForValue RetValRegs;
3315 // IndirectStoresToEmit - The set of stores to emit after the inline asm node.
3316 std::vector<std::pair<RegsForValue, Value*> > IndirectStoresToEmit;
3318 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
3319 AsmOperandInfo &OpInfo = ConstraintOperands[i];
3321 switch (OpInfo.Type) {
3322 case InlineAsm::isOutput: {
3323 TargetLowering::ConstraintType CTy = TargetLowering::C_RegisterClass;
3324 if (OpInfo.ConstraintCode.size() == 1) // not a physreg name.
3325 CTy = TLI.getConstraintType(OpInfo.ConstraintCode);
3327 if (CTy != TargetLowering::C_RegisterClass &&
3328 CTy != TargetLowering::C_Register) {
3329 // Memory output, or 'other' output (e.g. 'X' constraint).
3330 SDOperand InOperandVal = OpInfo.CallOperand;
3332 // Check that the operand (the address to store to) isn't a float.
3333 if (!MVT::isInteger(InOperandVal.getValueType()))
3334 assert(0 && "MATCH FAIL!");
3336 if (!OpInfo.isIndirect)
3337 assert(0 && "MATCH FAIL!");
3339 // Add information to the INLINEASM node to know about this output.
3340 unsigned ResOpType = 4/*MEM*/ | (1 << 3);
3341 AsmNodeOperands.push_back(DAG.getConstant(ResOpType, MVT::i32));
3342 AsmNodeOperands.push_back(InOperandVal);
3346 // Otherwise, this is a register or register class output.
3348 // If this is an early-clobber output, or if there is an input
3349 // constraint that matches this, we need to reserve the input register
3350 // so no other inputs allocate to it.
3351 bool UsesInputRegister = false;
3352 if (OpInfo.isEarlyClobber || OpInfo.hasMatchingInput)
3353 UsesInputRegister = true;
3355 // Copy the output from the appropriate register. Find a register that
3358 GetRegistersForValue(OpInfo.ConstraintCode, OpInfo.ConstraintVT,
3359 true, UsesInputRegister,
3360 OutputRegs, InputRegs);
3361 if (Regs.Regs.empty()) {
3362 cerr << "Couldn't allocate output reg for contraint '"
3363 << OpInfo.ConstraintCode << "'!\n";
3367 if (!OpInfo.isIndirect) {
3368 // This is the result value of the call.
3369 assert(RetValRegs.Regs.empty() &&
3370 "Cannot have multiple output constraints yet!");
3371 assert(I.getType() != Type::VoidTy && "Bad inline asm!");
3374 IndirectStoresToEmit.push_back(std::make_pair(Regs,
3375 OpInfo.CallOperandVal));
3378 // Add information to the INLINEASM node to know that this register is
3380 Regs.AddInlineAsmOperands(2 /*REGDEF*/, DAG, AsmNodeOperands);
3383 case InlineAsm::isInput: {
3384 SDOperand InOperandVal = OpInfo.CallOperand;
3386 if (isdigit(OpInfo.ConstraintCode[0])) { // Matching constraint?
3387 // If this is required to match an output register we have already set,
3388 // just use its register.
3389 unsigned OperandNo = atoi(OpInfo.ConstraintCode.c_str());
3391 // Scan until we find the definition we already emitted of this operand.
3392 // When we find it, create a RegsForValue operand.
3393 unsigned CurOp = 2; // The first operand.
3394 for (; OperandNo; --OperandNo) {
3395 // Advance to the next operand.
3397 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getValue();
3398 assert(((NumOps & 7) == 2 /*REGDEF*/ ||
3399 (NumOps & 7) == 4 /*MEM*/) &&
3400 "Skipped past definitions?");
3401 CurOp += (NumOps>>3)+1;
3405 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getValue();
3406 if ((NumOps & 7) == 2 /*REGDEF*/) {
3407 // Add NumOps>>3 registers to MatchedRegs.
3408 RegsForValue MatchedRegs;
3409 MatchedRegs.ValueVT = InOperandVal.getValueType();
3410 MatchedRegs.RegVT = AsmNodeOperands[CurOp+1].getValueType();
3411 for (unsigned i = 0, e = NumOps>>3; i != e; ++i) {
3413 cast<RegisterSDNode>(AsmNodeOperands[++CurOp])->getReg();
3414 MatchedRegs.Regs.push_back(Reg);
3417 // Use the produced MatchedRegs object to
3418 MatchedRegs.getCopyToRegs(InOperandVal, DAG, Chain, Flag,
3419 TLI.getPointerTy());
3420 MatchedRegs.AddInlineAsmOperands(1 /*REGUSE*/, DAG, AsmNodeOperands);
3423 assert((NumOps & 7) == 4/*MEM*/ && "Unknown matching constraint!");
3424 assert(0 && "matching constraints for memory operands unimp");
3428 if (OpInfo.ConstraintType == TargetLowering::C_Other) {
3429 assert(!OpInfo.isIndirect &&
3430 "Don't know how to handle indirect other inputs yet!");
3432 InOperandVal = TLI.isOperandValidForConstraint(InOperandVal,
3433 OpInfo.ConstraintCode[0],
3435 if (!InOperandVal.Val) {
3436 cerr << "Invalid operand for inline asm constraint '"
3437 << OpInfo.ConstraintCode << "'!\n";
3441 // Add information to the INLINEASM node to know about this input.
3442 unsigned ResOpType = 3 /*IMM*/ | (1 << 3);
3443 AsmNodeOperands.push_back(DAG.getConstant(ResOpType, MVT::i32));
3444 AsmNodeOperands.push_back(InOperandVal);
3446 } else if (OpInfo.ConstraintType == TargetLowering::C_Memory) {
3447 // Memory input. Memory operands really want the address of the value,
3448 // so we want an indirect input. If we don't have an indirect input,
3449 // spill the value somewhere if we can, otherwise spill it to a stack
3451 if (!OpInfo.isIndirect) {
3452 // If the operand is a float, integer, or vector constant, spill to a
3453 // constant pool entry to get its address.
3454 Value *OpVal = OpInfo.CallOperandVal;
3455 if (isa<ConstantFP>(OpVal) || isa<ConstantInt>(OpVal) ||
3456 isa<ConstantVector>(OpVal)) {
3457 InOperandVal = DAG.getConstantPool(cast<Constant>(OpVal),
3458 TLI.getPointerTy());
3460 // Otherwise, create a stack slot and emit a store to it before the
3462 const Type *Ty = OpVal->getType();
3463 uint64_t TySize = TLI.getTargetData()->getTypeSize(Ty);
3464 unsigned Align = TLI.getTargetData()->getPrefTypeAlignment(Ty);
3465 MachineFunction &MF = DAG.getMachineFunction();
3466 int SSFI = MF.getFrameInfo()->CreateStackObject(TySize, Align);
3467 SDOperand StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy());
3468 Chain = DAG.getStore(Chain, InOperandVal, StackSlot, NULL, 0);
3469 InOperandVal = StackSlot;
3473 assert(InOperandVal.getValueType() == TLI.getPointerTy() &&
3474 "Memory operands expect pointer values");
3476 // Add information to the INLINEASM node to know about this input.
3477 unsigned ResOpType = 4/*MEM*/ | (1 << 3);
3478 AsmNodeOperands.push_back(DAG.getConstant(ResOpType, MVT::i32));
3479 AsmNodeOperands.push_back(InOperandVal);
3483 assert((OpInfo.ConstraintType == TargetLowering::C_RegisterClass ||
3484 OpInfo.ConstraintType == TargetLowering::C_Register) &&
3485 "Unknown constraint type!");
3486 assert(!OpInfo.isIndirect &&
3487 "Don't know how to handle indirect register inputs yet!");
3489 // Copy the input into the appropriate registers.
3490 RegsForValue InRegs =
3491 GetRegistersForValue(OpInfo.ConstraintCode, OpInfo.ConstraintVT,
3492 false, true, OutputRegs, InputRegs);
3493 // FIXME: should be match fail.
3494 assert(!InRegs.Regs.empty() && "Couldn't allocate input reg!");
3496 InRegs.getCopyToRegs(InOperandVal, DAG, Chain, Flag, TLI.getPointerTy());
3498 InRegs.AddInlineAsmOperands(1/*REGUSE*/, DAG, AsmNodeOperands);
3501 case InlineAsm::isClobber: {
3502 RegsForValue ClobberedRegs =
3503 GetRegistersForValue(OpInfo.ConstraintCode, MVT::Other, false, false,
3504 OutputRegs, InputRegs);
3505 // Add the clobbered value to the operand list, so that the register
3506 // allocator is aware that the physreg got clobbered.
3507 if (!ClobberedRegs.Regs.empty())
3508 ClobberedRegs.AddInlineAsmOperands(2/*REGDEF*/, DAG, AsmNodeOperands);
3514 // Finish up input operands.
3515 AsmNodeOperands[0] = Chain;
3516 if (Flag.Val) AsmNodeOperands.push_back(Flag);
3518 Chain = DAG.getNode(ISD::INLINEASM,
3519 DAG.getNodeValueTypes(MVT::Other, MVT::Flag), 2,
3520 &AsmNodeOperands[0], AsmNodeOperands.size());
3521 Flag = Chain.getValue(1);
3523 // If this asm returns a register value, copy the result from that register
3524 // and set it as the value of the call.
3525 if (!RetValRegs.Regs.empty()) {
3526 SDOperand Val = RetValRegs.getCopyFromRegs(DAG, Chain, Flag);
3528 // If the result of the inline asm is a vector, it may have the wrong
3529 // width/num elts. Make sure to convert it to the right type with
3531 if (Val.getValueType() == MVT::Vector) {
3532 const VectorType *VTy = cast<VectorType>(I.getType());
3533 unsigned DesiredNumElts = VTy->getNumElements();
3534 MVT::ValueType DesiredEltVT = TLI.getValueType(VTy->getElementType());
3536 Val = DAG.getNode(ISD::VBIT_CONVERT, MVT::Vector, Val,
3537 DAG.getConstant(DesiredNumElts, MVT::i32),
3538 DAG.getValueType(DesiredEltVT));
3544 std::vector<std::pair<SDOperand, Value*> > StoresToEmit;
3546 // Process indirect outputs, first output all of the flagged copies out of
3548 for (unsigned i = 0, e = IndirectStoresToEmit.size(); i != e; ++i) {
3549 RegsForValue &OutRegs = IndirectStoresToEmit[i].first;
3550 Value *Ptr = IndirectStoresToEmit[i].second;
3551 SDOperand OutVal = OutRegs.getCopyFromRegs(DAG, Chain, Flag);
3552 StoresToEmit.push_back(std::make_pair(OutVal, Ptr));
3555 // Emit the non-flagged stores from the physregs.
3556 SmallVector<SDOperand, 8> OutChains;
3557 for (unsigned i = 0, e = StoresToEmit.size(); i != e; ++i)
3558 OutChains.push_back(DAG.getStore(Chain, StoresToEmit[i].first,
3559 getValue(StoresToEmit[i].second),
3560 StoresToEmit[i].second, 0));
3561 if (!OutChains.empty())
3562 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other,
3563 &OutChains[0], OutChains.size());
3568 void SelectionDAGLowering::visitMalloc(MallocInst &I) {
3569 SDOperand Src = getValue(I.getOperand(0));
3571 MVT::ValueType IntPtr = TLI.getPointerTy();
3573 if (IntPtr < Src.getValueType())
3574 Src = DAG.getNode(ISD::TRUNCATE, IntPtr, Src);
3575 else if (IntPtr > Src.getValueType())
3576 Src = DAG.getNode(ISD::ZERO_EXTEND, IntPtr, Src);
3578 // Scale the source by the type size.
3579 uint64_t ElementSize = TD->getTypeSize(I.getType()->getElementType());
3580 Src = DAG.getNode(ISD::MUL, Src.getValueType(),
3581 Src, getIntPtrConstant(ElementSize));
3583 TargetLowering::ArgListTy Args;
3584 TargetLowering::ArgListEntry Entry;
3586 Entry.Ty = TLI.getTargetData()->getIntPtrType();
3587 Args.push_back(Entry);
3589 std::pair<SDOperand,SDOperand> Result =
3590 TLI.LowerCallTo(getRoot(), I.getType(), false, false, CallingConv::C, true,
3591 DAG.getExternalSymbol("malloc", IntPtr),
3593 setValue(&I, Result.first); // Pointers always fit in registers
3594 DAG.setRoot(Result.second);
3597 void SelectionDAGLowering::visitFree(FreeInst &I) {
3598 TargetLowering::ArgListTy Args;
3599 TargetLowering::ArgListEntry Entry;
3600 Entry.Node = getValue(I.getOperand(0));
3601 Entry.Ty = TLI.getTargetData()->getIntPtrType();
3602 Args.push_back(Entry);
3603 MVT::ValueType IntPtr = TLI.getPointerTy();
3604 std::pair<SDOperand,SDOperand> Result =
3605 TLI.LowerCallTo(getRoot(), Type::VoidTy, false, false, CallingConv::C, true,
3606 DAG.getExternalSymbol("free", IntPtr), Args, DAG);
3607 DAG.setRoot(Result.second);
3610 // InsertAtEndOfBasicBlock - This method should be implemented by targets that
3611 // mark instructions with the 'usesCustomDAGSchedInserter' flag. These
3612 // instructions are special in various ways, which require special support to
3613 // insert. The specified MachineInstr is created but not inserted into any
3614 // basic blocks, and the scheduler passes ownership of it to this method.
3615 MachineBasicBlock *TargetLowering::InsertAtEndOfBasicBlock(MachineInstr *MI,
3616 MachineBasicBlock *MBB) {
3617 cerr << "If a target marks an instruction with "
3618 << "'usesCustomDAGSchedInserter', it must implement "
3619 << "TargetLowering::InsertAtEndOfBasicBlock!\n";
3624 void SelectionDAGLowering::visitVAStart(CallInst &I) {
3625 DAG.setRoot(DAG.getNode(ISD::VASTART, MVT::Other, getRoot(),
3626 getValue(I.getOperand(1)),
3627 DAG.getSrcValue(I.getOperand(1))));
3630 void SelectionDAGLowering::visitVAArg(VAArgInst &I) {
3631 SDOperand V = DAG.getVAArg(TLI.getValueType(I.getType()), getRoot(),
3632 getValue(I.getOperand(0)),
3633 DAG.getSrcValue(I.getOperand(0)));
3635 DAG.setRoot(V.getValue(1));
3638 void SelectionDAGLowering::visitVAEnd(CallInst &I) {
3639 DAG.setRoot(DAG.getNode(ISD::VAEND, MVT::Other, getRoot(),
3640 getValue(I.getOperand(1)),
3641 DAG.getSrcValue(I.getOperand(1))));
3644 void SelectionDAGLowering::visitVACopy(CallInst &I) {
3645 DAG.setRoot(DAG.getNode(ISD::VACOPY, MVT::Other, getRoot(),
3646 getValue(I.getOperand(1)),
3647 getValue(I.getOperand(2)),
3648 DAG.getSrcValue(I.getOperand(1)),
3649 DAG.getSrcValue(I.getOperand(2))));
3652 /// ExpandScalarFormalArgs - Recursively expand the formal_argument node, either
3653 /// bit_convert it or join a pair of them with a BUILD_PAIR when appropriate.
3654 static SDOperand ExpandScalarFormalArgs(MVT::ValueType VT, SDNode *Arg,
3655 unsigned &i, SelectionDAG &DAG,
3656 TargetLowering &TLI) {
3657 if (TLI.getTypeAction(VT) != TargetLowering::Expand)
3658 return SDOperand(Arg, i++);
3660 MVT::ValueType EVT = TLI.getTypeToTransformTo(VT);
3661 unsigned NumVals = MVT::getSizeInBits(VT) / MVT::getSizeInBits(EVT);
3663 return DAG.getNode(ISD::BIT_CONVERT, VT,
3664 ExpandScalarFormalArgs(EVT, Arg, i, DAG, TLI));
3665 } else if (NumVals == 2) {
3666 SDOperand Lo = ExpandScalarFormalArgs(EVT, Arg, i, DAG, TLI);
3667 SDOperand Hi = ExpandScalarFormalArgs(EVT, Arg, i, DAG, TLI);
3668 if (!TLI.isLittleEndian())
3670 return DAG.getNode(ISD::BUILD_PAIR, VT, Lo, Hi);
3672 // Value scalarized into many values. Unimp for now.
3673 assert(0 && "Cannot expand i64 -> i16 yet!");
3678 /// TargetLowering::LowerArguments - This is the default LowerArguments
3679 /// implementation, which just inserts a FORMAL_ARGUMENTS node. FIXME: When all
3680 /// targets are migrated to using FORMAL_ARGUMENTS, this hook should be
3681 /// integrated into SDISel.
3682 std::vector<SDOperand>
3683 TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
3684 const FunctionType *FTy = F.getFunctionType();
3685 const ParamAttrsList *Attrs = FTy->getParamAttrs();
3686 // Add CC# and isVararg as operands to the FORMAL_ARGUMENTS node.
3687 std::vector<SDOperand> Ops;
3688 Ops.push_back(DAG.getRoot());
3689 Ops.push_back(DAG.getConstant(F.getCallingConv(), getPointerTy()));
3690 Ops.push_back(DAG.getConstant(F.isVarArg(), getPointerTy()));
3692 // Add one result value for each formal argument.
3693 std::vector<MVT::ValueType> RetVals;
3695 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end();
3697 MVT::ValueType VT = getValueType(I->getType());
3698 unsigned Flags = ISD::ParamFlags::NoFlagSet;
3699 unsigned OriginalAlignment =
3700 getTargetData()->getABITypeAlignment(I->getType());
3702 // FIXME: Distinguish between a formal with no [sz]ext attribute from one
3703 // that is zero extended!
3704 if (Attrs && Attrs->paramHasAttr(j, ParamAttr::ZExt))
3705 Flags &= ~(ISD::ParamFlags::SExt);
3706 if (Attrs && Attrs->paramHasAttr(j, ParamAttr::SExt))
3707 Flags |= ISD::ParamFlags::SExt;
3708 if (Attrs && Attrs->paramHasAttr(j, ParamAttr::InReg))
3709 Flags |= ISD::ParamFlags::InReg;
3710 if (Attrs && Attrs->paramHasAttr(j, ParamAttr::StructRet))
3711 Flags |= ISD::ParamFlags::StructReturn;
3712 Flags |= (OriginalAlignment << ISD::ParamFlags::OrigAlignmentOffs);
3714 switch (getTypeAction(VT)) {
3715 default: assert(0 && "Unknown type action!");
3717 RetVals.push_back(VT);
3718 Ops.push_back(DAG.getConstant(Flags, MVT::i32));
3721 RetVals.push_back(getTypeToTransformTo(VT));
3722 Ops.push_back(DAG.getConstant(Flags, MVT::i32));
3725 if (VT != MVT::Vector) {
3726 // If this is a large integer, it needs to be broken up into small
3727 // integers. Figure out what the destination type is and how many small
3728 // integers it turns into.
3729 MVT::ValueType NVT = getTypeToExpandTo(VT);
3730 unsigned NumVals = getNumElements(VT);
3731 for (unsigned i = 0; i != NumVals; ++i) {
3732 RetVals.push_back(NVT);
3733 // if it isn't first piece, alignment must be 1
3735 Flags = (Flags & (~ISD::ParamFlags::OrigAlignment)) |
3736 (1 << ISD::ParamFlags::OrigAlignmentOffs);
3737 Ops.push_back(DAG.getConstant(Flags, MVT::i32));
3740 // Otherwise, this is a vector type. We only support legal vectors
3742 unsigned NumElems = cast<VectorType>(I->getType())->getNumElements();
3743 const Type *EltTy = cast<VectorType>(I->getType())->getElementType();
3745 // Figure out if there is a Packed type corresponding to this Vector
3746 // type. If so, convert to the vector type.
3747 MVT::ValueType TVT = MVT::getVectorType(getValueType(EltTy), NumElems);
3748 if (TVT != MVT::Other && isTypeLegal(TVT)) {
3749 RetVals.push_back(TVT);
3750 Ops.push_back(DAG.getConstant(Flags, MVT::i32));
3752 assert(0 && "Don't support illegal by-val vector arguments yet!");
3759 RetVals.push_back(MVT::Other);
3762 SDNode *Result = DAG.getNode(ISD::FORMAL_ARGUMENTS,
3763 DAG.getNodeValueTypes(RetVals), RetVals.size(),
3764 &Ops[0], Ops.size()).Val;
3766 DAG.setRoot(SDOperand(Result, Result->getNumValues()-1));
3768 // Set up the return result vector.
3772 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E;
3774 MVT::ValueType VT = getValueType(I->getType());
3776 switch (getTypeAction(VT)) {
3777 default: assert(0 && "Unknown type action!");
3779 Ops.push_back(SDOperand(Result, i++));
3782 SDOperand Op(Result, i++);
3783 if (MVT::isInteger(VT)) {
3784 if (Attrs && Attrs->paramHasAttr(Idx, ParamAttr::SExt))
3785 Op = DAG.getNode(ISD::AssertSext, Op.getValueType(), Op,
3786 DAG.getValueType(VT));
3787 else if (Attrs && Attrs->paramHasAttr(Idx, ParamAttr::ZExt))
3788 Op = DAG.getNode(ISD::AssertZext, Op.getValueType(), Op,
3789 DAG.getValueType(VT));
3790 Op = DAG.getNode(ISD::TRUNCATE, VT, Op);
3792 assert(MVT::isFloatingPoint(VT) && "Not int or FP?");
3793 Op = DAG.getNode(ISD::FP_ROUND, VT, Op);
3799 if (VT != MVT::Vector) {
3800 // If this is a large integer or a floating point node that needs to be
3801 // expanded, it needs to be reassembled from small integers. Figure out
3802 // what the source elt type is and how many small integers it is.
3803 Ops.push_back(ExpandScalarFormalArgs(VT, Result, i, DAG, *this));
3805 // Otherwise, this is a vector type. We only support legal vectors
3807 const VectorType *PTy = cast<VectorType>(I->getType());
3808 unsigned NumElems = PTy->getNumElements();
3809 const Type *EltTy = PTy->getElementType();
3811 // Figure out if there is a Packed type corresponding to this Vector
3812 // type. If so, convert to the vector type.
3813 MVT::ValueType TVT = MVT::getVectorType(getValueType(EltTy), NumElems);
3814 if (TVT != MVT::Other && isTypeLegal(TVT)) {
3815 SDOperand N = SDOperand(Result, i++);
3816 // Handle copies from generic vectors to registers.
3817 N = DAG.getNode(ISD::VBIT_CONVERT, MVT::Vector, N,
3818 DAG.getConstant(NumElems, MVT::i32),
3819 DAG.getValueType(getValueType(EltTy)));
3822 assert(0 && "Don't support illegal by-val vector arguments yet!");
3833 /// ExpandScalarCallArgs - Recursively expand call argument node by
3834 /// bit_converting it or extract a pair of elements from the larger node.
3835 static void ExpandScalarCallArgs(MVT::ValueType VT, SDOperand Arg,
3837 SmallVector<SDOperand, 32> &Ops,
3839 TargetLowering &TLI,
3840 bool isFirst = true) {
3842 if (TLI.getTypeAction(VT) != TargetLowering::Expand) {
3843 // if it isn't first piece, alignment must be 1
3845 Flags = (Flags & (~ISD::ParamFlags::OrigAlignment)) |
3846 (1 << ISD::ParamFlags::OrigAlignmentOffs);
3848 Ops.push_back(DAG.getConstant(Flags, MVT::i32));
3852 MVT::ValueType EVT = TLI.getTypeToTransformTo(VT);
3853 unsigned NumVals = MVT::getSizeInBits(VT) / MVT::getSizeInBits(EVT);
3855 Arg = DAG.getNode(ISD::BIT_CONVERT, EVT, Arg);
3856 ExpandScalarCallArgs(EVT, Arg, Flags, Ops, DAG, TLI, isFirst);
3857 } else if (NumVals == 2) {
3858 SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, EVT, Arg,
3859 DAG.getConstant(0, TLI.getPointerTy()));
3860 SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, EVT, Arg,
3861 DAG.getConstant(1, TLI.getPointerTy()));
3862 if (!TLI.isLittleEndian())
3864 ExpandScalarCallArgs(EVT, Lo, Flags, Ops, DAG, TLI, isFirst);
3865 ExpandScalarCallArgs(EVT, Hi, Flags, Ops, DAG, TLI, false);
3867 // Value scalarized into many values. Unimp for now.
3868 assert(0 && "Cannot expand i64 -> i16 yet!");
3872 /// TargetLowering::LowerCallTo - This is the default LowerCallTo
3873 /// implementation, which just inserts an ISD::CALL node, which is later custom
3874 /// lowered by the target to something concrete. FIXME: When all targets are
3875 /// migrated to using ISD::CALL, this hook should be integrated into SDISel.
3876 std::pair<SDOperand, SDOperand>
3877 TargetLowering::LowerCallTo(SDOperand Chain, const Type *RetTy,
3878 bool RetTyIsSigned, bool isVarArg,
3879 unsigned CallingConv, bool isTailCall,
3881 ArgListTy &Args, SelectionDAG &DAG) {
3882 SmallVector<SDOperand, 32> Ops;
3883 Ops.push_back(Chain); // Op#0 - Chain
3884 Ops.push_back(DAG.getConstant(CallingConv, getPointerTy())); // Op#1 - CC
3885 Ops.push_back(DAG.getConstant(isVarArg, getPointerTy())); // Op#2 - VarArg
3886 Ops.push_back(DAG.getConstant(isTailCall, getPointerTy())); // Op#3 - Tail
3887 Ops.push_back(Callee);
3889 // Handle all of the outgoing arguments.
3890 for (unsigned i = 0, e = Args.size(); i != e; ++i) {
3891 MVT::ValueType VT = getValueType(Args[i].Ty);
3892 SDOperand Op = Args[i].Node;
3893 unsigned Flags = ISD::ParamFlags::NoFlagSet;
3894 unsigned OriginalAlignment =
3895 getTargetData()->getABITypeAlignment(Args[i].Ty);
3898 Flags |= ISD::ParamFlags::SExt;
3900 Flags |= ISD::ParamFlags::ZExt;
3901 if (Args[i].isInReg)
3902 Flags |= ISD::ParamFlags::InReg;
3904 Flags |= ISD::ParamFlags::StructReturn;
3905 Flags |= OriginalAlignment << ISD::ParamFlags::OrigAlignmentOffs;
3907 switch (getTypeAction(VT)) {
3908 default: assert(0 && "Unknown type action!");
3911 Ops.push_back(DAG.getConstant(Flags, MVT::i32));
3914 if (MVT::isInteger(VT)) {
3917 ExtOp = ISD::SIGN_EXTEND;
3918 else if (Args[i].isZExt)
3919 ExtOp = ISD::ZERO_EXTEND;
3921 ExtOp = ISD::ANY_EXTEND;
3922 Op = DAG.getNode(ExtOp, getTypeToTransformTo(VT), Op);
3924 assert(MVT::isFloatingPoint(VT) && "Not int or FP?");
3925 Op = DAG.getNode(ISD::FP_EXTEND, getTypeToTransformTo(VT), Op);
3928 Ops.push_back(DAG.getConstant(Flags, MVT::i32));
3931 if (VT != MVT::Vector) {
3932 // If this is a large integer, it needs to be broken down into small
3933 // integers. Figure out what the source elt type is and how many small
3935 ExpandScalarCallArgs(VT, Op, Flags, Ops, DAG, *this);
3937 // Otherwise, this is a vector type. We only support legal vectors
3939 const VectorType *PTy = cast<VectorType>(Args[i].Ty);
3940 unsigned NumElems = PTy->getNumElements();
3941 const Type *EltTy = PTy->getElementType();
3943 // Figure out if there is a Packed type corresponding to this Vector
3944 // type. If so, convert to the vector type.
3945 MVT::ValueType TVT = MVT::getVectorType(getValueType(EltTy), NumElems);
3946 if (TVT != MVT::Other && isTypeLegal(TVT)) {
3947 // Insert a VBIT_CONVERT of the MVT::Vector type to the vector type.
3948 Op = DAG.getNode(ISD::VBIT_CONVERT, TVT, Op);
3950 Ops.push_back(DAG.getConstant(Flags, MVT::i32));
3952 assert(0 && "Don't support illegal by-val vector call args yet!");
3960 // Figure out the result value types.
3961 SmallVector<MVT::ValueType, 4> RetTys;
3963 if (RetTy != Type::VoidTy) {
3964 MVT::ValueType VT = getValueType(RetTy);
3965 switch (getTypeAction(VT)) {
3966 default: assert(0 && "Unknown type action!");
3968 RetTys.push_back(VT);
3971 RetTys.push_back(getTypeToTransformTo(VT));
3974 if (VT != MVT::Vector) {
3975 // If this is a large integer, it needs to be reassembled from small
3976 // integers. Figure out what the source elt type is and how many small
3978 MVT::ValueType NVT = getTypeToExpandTo(VT);
3979 unsigned NumVals = getNumElements(VT);
3980 for (unsigned i = 0; i != NumVals; ++i)
3981 RetTys.push_back(NVT);
3983 // Otherwise, this is a vector type. We only support legal vectors
3985 const VectorType *PTy = cast<VectorType>(RetTy);
3986 unsigned NumElems = PTy->getNumElements();
3987 const Type *EltTy = PTy->getElementType();
3989 // Figure out if there is a Packed type corresponding to this Vector
3990 // type. If so, convert to the vector type.
3991 MVT::ValueType TVT = MVT::getVectorType(getValueType(EltTy), NumElems);
3992 if (TVT != MVT::Other && isTypeLegal(TVT)) {
3993 RetTys.push_back(TVT);
3995 assert(0 && "Don't support illegal by-val vector call results yet!");
4002 RetTys.push_back(MVT::Other); // Always has a chain.
4004 // Finally, create the CALL node.
4005 SDOperand Res = DAG.getNode(ISD::CALL,
4006 DAG.getVTList(&RetTys[0], RetTys.size()),
4007 &Ops[0], Ops.size());
4009 // This returns a pair of operands. The first element is the
4010 // return value for the function (if RetTy is not VoidTy). The second
4011 // element is the outgoing token chain.
4013 if (RetTys.size() != 1) {
4014 MVT::ValueType VT = getValueType(RetTy);
4015 if (RetTys.size() == 2) {
4018 // If this value was promoted, truncate it down.
4019 if (ResVal.getValueType() != VT) {
4020 if (VT == MVT::Vector) {
4021 // Insert a VBIT_CONVERT to convert from the packed result type to the
4022 // MVT::Vector type.
4023 unsigned NumElems = cast<VectorType>(RetTy)->getNumElements();
4024 const Type *EltTy = cast<VectorType>(RetTy)->getElementType();
4026 // Figure out if there is a Packed type corresponding to this Vector
4027 // type. If so, convert to the vector type.
4028 MVT::ValueType TVT = MVT::getVectorType(getValueType(EltTy),NumElems);
4029 if (TVT != MVT::Other && isTypeLegal(TVT)) {
4030 // Insert a VBIT_CONVERT of the FORMAL_ARGUMENTS to a
4031 // "N x PTyElementVT" MVT::Vector type.
4032 ResVal = DAG.getNode(ISD::VBIT_CONVERT, MVT::Vector, ResVal,
4033 DAG.getConstant(NumElems, MVT::i32),
4034 DAG.getValueType(getValueType(EltTy)));
4038 } else if (MVT::isInteger(VT)) {
4039 unsigned AssertOp = ISD::AssertSext;
4041 AssertOp = ISD::AssertZext;
4042 ResVal = DAG.getNode(AssertOp, ResVal.getValueType(), ResVal,
4043 DAG.getValueType(VT));
4044 ResVal = DAG.getNode(ISD::TRUNCATE, VT, ResVal);
4046 assert(MVT::isFloatingPoint(VT));
4047 if (getTypeAction(VT) == Expand)
4048 ResVal = DAG.getNode(ISD::BIT_CONVERT, VT, ResVal);
4050 ResVal = DAG.getNode(ISD::FP_ROUND, VT, ResVal);
4053 } else if (RetTys.size() == 3) {
4054 ResVal = DAG.getNode(ISD::BUILD_PAIR, VT,
4055 Res.getValue(0), Res.getValue(1));
4058 assert(0 && "Case not handled yet!");
4062 return std::make_pair(ResVal, Res.getValue(Res.Val->getNumValues()-1));
4065 SDOperand TargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
4066 assert(0 && "LowerOperation not implemented for this target!");
4071 SDOperand TargetLowering::CustomPromoteOperation(SDOperand Op,
4072 SelectionDAG &DAG) {
4073 assert(0 && "CustomPromoteOperation not implemented for this target!");
4078 /// getMemsetValue - Vectorized representation of the memset value
4080 static SDOperand getMemsetValue(SDOperand Value, MVT::ValueType VT,
4081 SelectionDAG &DAG) {
4082 MVT::ValueType CurVT = VT;
4083 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Value)) {
4084 uint64_t Val = C->getValue() & 255;
4086 while (CurVT != MVT::i8) {
4087 Val = (Val << Shift) | Val;
4089 CurVT = (MVT::ValueType)((unsigned)CurVT - 1);
4091 return DAG.getConstant(Val, VT);
4093 Value = DAG.getNode(ISD::ZERO_EXTEND, VT, Value);
4095 while (CurVT != MVT::i8) {
4097 DAG.getNode(ISD::OR, VT,
4098 DAG.getNode(ISD::SHL, VT, Value,
4099 DAG.getConstant(Shift, MVT::i8)), Value);
4101 CurVT = (MVT::ValueType)((unsigned)CurVT - 1);
4108 /// getMemsetStringVal - Similar to getMemsetValue. Except this is only
4109 /// used when a memcpy is turned into a memset when the source is a constant
4111 static SDOperand getMemsetStringVal(MVT::ValueType VT,
4112 SelectionDAG &DAG, TargetLowering &TLI,
4113 std::string &Str, unsigned Offset) {
4115 unsigned MSB = getSizeInBits(VT) / 8;
4116 if (TLI.isLittleEndian())
4117 Offset = Offset + MSB - 1;
4118 for (unsigned i = 0; i != MSB; ++i) {
4119 Val = (Val << 8) | (unsigned char)Str[Offset];
4120 Offset += TLI.isLittleEndian() ? -1 : 1;
4122 return DAG.getConstant(Val, VT);
4125 /// getMemBasePlusOffset - Returns base and offset node for the
4126 static SDOperand getMemBasePlusOffset(SDOperand Base, unsigned Offset,
4127 SelectionDAG &DAG, TargetLowering &TLI) {
4128 MVT::ValueType VT = Base.getValueType();
4129 return DAG.getNode(ISD::ADD, VT, Base, DAG.getConstant(Offset, VT));
4132 /// MeetsMaxMemopRequirement - Determines if the number of memory ops required
4133 /// to replace the memset / memcpy is below the threshold. It also returns the
4134 /// types of the sequence of memory ops to perform memset / memcpy.
4135 static bool MeetsMaxMemopRequirement(std::vector<MVT::ValueType> &MemOps,
4136 unsigned Limit, uint64_t Size,
4137 unsigned Align, TargetLowering &TLI) {
4140 if (TLI.allowsUnalignedMemoryAccesses()) {
4143 switch (Align & 7) {
4159 MVT::ValueType LVT = MVT::i64;
4160 while (!TLI.isTypeLegal(LVT))
4161 LVT = (MVT::ValueType)((unsigned)LVT - 1);
4162 assert(MVT::isInteger(LVT));
4167 unsigned NumMemOps = 0;
4169 unsigned VTSize = getSizeInBits(VT) / 8;
4170 while (VTSize > Size) {
4171 VT = (MVT::ValueType)((unsigned)VT - 1);
4174 assert(MVT::isInteger(VT));
4176 if (++NumMemOps > Limit)
4178 MemOps.push_back(VT);
4185 void SelectionDAGLowering::visitMemIntrinsic(CallInst &I, unsigned Op) {
4186 SDOperand Op1 = getValue(I.getOperand(1));
4187 SDOperand Op2 = getValue(I.getOperand(2));
4188 SDOperand Op3 = getValue(I.getOperand(3));
4189 SDOperand Op4 = getValue(I.getOperand(4));
4190 unsigned Align = (unsigned)cast<ConstantSDNode>(Op4)->getValue();
4191 if (Align == 0) Align = 1;
4193 if (ConstantSDNode *Size = dyn_cast<ConstantSDNode>(Op3)) {
4194 std::vector<MVT::ValueType> MemOps;
4196 // Expand memset / memcpy to a series of load / store ops
4197 // if the size operand falls below a certain threshold.
4198 SmallVector<SDOperand, 8> OutChains;
4200 default: break; // Do nothing for now.
4202 if (MeetsMaxMemopRequirement(MemOps, TLI.getMaxStoresPerMemset(),
4203 Size->getValue(), Align, TLI)) {
4204 unsigned NumMemOps = MemOps.size();
4205 unsigned Offset = 0;
4206 for (unsigned i = 0; i < NumMemOps; i++) {
4207 MVT::ValueType VT = MemOps[i];
4208 unsigned VTSize = getSizeInBits(VT) / 8;
4209 SDOperand Value = getMemsetValue(Op2, VT, DAG);
4210 SDOperand Store = DAG.getStore(getRoot(), Value,
4211 getMemBasePlusOffset(Op1, Offset, DAG, TLI),
4212 I.getOperand(1), Offset);
4213 OutChains.push_back(Store);
4220 if (MeetsMaxMemopRequirement(MemOps, TLI.getMaxStoresPerMemcpy(),
4221 Size->getValue(), Align, TLI)) {
4222 unsigned NumMemOps = MemOps.size();
4223 unsigned SrcOff = 0, DstOff = 0, SrcDelta = 0;
4224 GlobalAddressSDNode *G = NULL;
4226 bool CopyFromStr = false;
4228 if (Op2.getOpcode() == ISD::GlobalAddress)
4229 G = cast<GlobalAddressSDNode>(Op2);
4230 else if (Op2.getOpcode() == ISD::ADD &&
4231 Op2.getOperand(0).getOpcode() == ISD::GlobalAddress &&
4232 Op2.getOperand(1).getOpcode() == ISD::Constant) {
4233 G = cast<GlobalAddressSDNode>(Op2.getOperand(0));
4234 SrcDelta = cast<ConstantSDNode>(Op2.getOperand(1))->getValue();
4237 GlobalVariable *GV = dyn_cast<GlobalVariable>(G->getGlobal());
4238 if (GV && GV->isConstant()) {
4239 Str = GV->getStringValue(false);
4247 for (unsigned i = 0; i < NumMemOps; i++) {
4248 MVT::ValueType VT = MemOps[i];
4249 unsigned VTSize = getSizeInBits(VT) / 8;
4250 SDOperand Value, Chain, Store;
4253 Value = getMemsetStringVal(VT, DAG, TLI, Str, SrcOff);
4256 DAG.getStore(Chain, Value,
4257 getMemBasePlusOffset(Op1, DstOff, DAG, TLI),
4258 I.getOperand(1), DstOff);
4260 Value = DAG.getLoad(VT, getRoot(),
4261 getMemBasePlusOffset(Op2, SrcOff, DAG, TLI),
4262 I.getOperand(2), SrcOff);
4263 Chain = Value.getValue(1);
4265 DAG.getStore(Chain, Value,
4266 getMemBasePlusOffset(Op1, DstOff, DAG, TLI),
4267 I.getOperand(1), DstOff);
4269 OutChains.push_back(Store);
4278 if (!OutChains.empty()) {
4279 DAG.setRoot(DAG.getNode(ISD::TokenFactor, MVT::Other,
4280 &OutChains[0], OutChains.size()));
4285 DAG.setRoot(DAG.getNode(Op, MVT::Other, getRoot(), Op1, Op2, Op3, Op4));
4288 //===----------------------------------------------------------------------===//
4289 // SelectionDAGISel code
4290 //===----------------------------------------------------------------------===//
4292 unsigned SelectionDAGISel::MakeReg(MVT::ValueType VT) {
4293 return RegMap->createVirtualRegister(TLI.getRegClassFor(VT));
4296 void SelectionDAGISel::getAnalysisUsage(AnalysisUsage &AU) const {
4297 AU.addRequired<AliasAnalysis>();
4298 AU.setPreservesAll();
4303 bool SelectionDAGISel::runOnFunction(Function &Fn) {
4304 MachineFunction &MF = MachineFunction::construct(&Fn, TLI.getTargetMachine());
4305 RegMap = MF.getSSARegMap();
4306 DOUT << "\n\n\n=== " << Fn.getName() << "\n";
4308 FunctionLoweringInfo FuncInfo(TLI, Fn, MF);
4310 for (Function::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I)
4311 SelectBasicBlock(I, MF, FuncInfo);
4313 // Add function live-ins to entry block live-in set.
4314 BasicBlock *EntryBB = &Fn.getEntryBlock();
4315 BB = FuncInfo.MBBMap[EntryBB];
4316 if (!MF.livein_empty())
4317 for (MachineFunction::livein_iterator I = MF.livein_begin(),
4318 E = MF.livein_end(); I != E; ++I)
4319 BB->addLiveIn(I->first);
4324 SDOperand SelectionDAGLowering::CopyValueToVirtualRegister(Value *V,
4326 SDOperand Op = getValue(V);
4327 assert((Op.getOpcode() != ISD::CopyFromReg ||
4328 cast<RegisterSDNode>(Op.getOperand(1))->getReg() != Reg) &&
4329 "Copy from a reg to the same reg!");
4331 // If this type is not legal, we must make sure to not create an invalid
4333 MVT::ValueType SrcVT = Op.getValueType();
4334 MVT::ValueType DestVT = TLI.getTypeToTransformTo(SrcVT);
4335 if (SrcVT == DestVT) {
4336 return DAG.getCopyToReg(getRoot(), Reg, Op);
4337 } else if (SrcVT == MVT::Vector) {
4338 // Handle copies from generic vectors to registers.
4339 MVT::ValueType PTyElementVT, PTyLegalElementVT;
4340 unsigned NE = TLI.getVectorTypeBreakdown(cast<VectorType>(V->getType()),
4341 PTyElementVT, PTyLegalElementVT);
4343 // Insert a VBIT_CONVERT of the input vector to a "N x PTyElementVT"
4344 // MVT::Vector type.
4345 Op = DAG.getNode(ISD::VBIT_CONVERT, MVT::Vector, Op,
4346 DAG.getConstant(NE, MVT::i32),
4347 DAG.getValueType(PTyElementVT));
4349 // Loop over all of the elements of the resultant vector,
4350 // VEXTRACT_VECTOR_ELT'ing them, converting them to PTyLegalElementVT, then
4351 // copying them into output registers.
4352 SmallVector<SDOperand, 8> OutChains;
4353 SDOperand Root = getRoot();
4354 for (unsigned i = 0; i != NE; ++i) {
4355 SDOperand Elt = DAG.getNode(ISD::VEXTRACT_VECTOR_ELT, PTyElementVT,
4356 Op, DAG.getConstant(i, TLI.getPointerTy()));
4357 if (PTyElementVT == PTyLegalElementVT) {
4358 // Elements are legal.
4359 OutChains.push_back(DAG.getCopyToReg(Root, Reg++, Elt));
4360 } else if (PTyLegalElementVT > PTyElementVT) {
4361 // Elements are promoted.
4362 if (MVT::isFloatingPoint(PTyLegalElementVT))
4363 Elt = DAG.getNode(ISD::FP_EXTEND, PTyLegalElementVT, Elt);
4365 Elt = DAG.getNode(ISD::ANY_EXTEND, PTyLegalElementVT, Elt);
4366 OutChains.push_back(DAG.getCopyToReg(Root, Reg++, Elt));
4368 // Elements are expanded.
4369 // The src value is expanded into multiple registers.
4370 SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, PTyLegalElementVT,
4371 Elt, DAG.getConstant(0, TLI.getPointerTy()));
4372 SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, PTyLegalElementVT,
4373 Elt, DAG.getConstant(1, TLI.getPointerTy()));
4374 OutChains.push_back(DAG.getCopyToReg(Root, Reg++, Lo));
4375 OutChains.push_back(DAG.getCopyToReg(Root, Reg++, Hi));
4378 return DAG.getNode(ISD::TokenFactor, MVT::Other,
4379 &OutChains[0], OutChains.size());
4380 } else if (TLI.getTypeAction(SrcVT) == TargetLowering::Promote) {
4381 // The src value is promoted to the register.
4382 if (MVT::isFloatingPoint(SrcVT))
4383 Op = DAG.getNode(ISD::FP_EXTEND, DestVT, Op);
4385 Op = DAG.getNode(ISD::ANY_EXTEND, DestVT, Op);
4386 return DAG.getCopyToReg(getRoot(), Reg, Op);
4388 DestVT = TLI.getTypeToExpandTo(SrcVT);
4389 unsigned NumVals = TLI.getNumElements(SrcVT);
4391 return DAG.getCopyToReg(getRoot(), Reg,
4392 DAG.getNode(ISD::BIT_CONVERT, DestVT, Op));
4393 assert(NumVals == 2 && "1 to 4 (and more) expansion not implemented!");
4394 // The src value is expanded into multiple registers.
4395 SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, DestVT,
4396 Op, DAG.getConstant(0, TLI.getPointerTy()));
4397 SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, DestVT,
4398 Op, DAG.getConstant(1, TLI.getPointerTy()));
4399 Op = DAG.getCopyToReg(getRoot(), Reg, Lo);
4400 return DAG.getCopyToReg(Op, Reg+1, Hi);
4404 void SelectionDAGISel::
4405 LowerArguments(BasicBlock *LLVMBB, SelectionDAGLowering &SDL,
4406 std::vector<SDOperand> &UnorderedChains) {
4407 // If this is the entry block, emit arguments.
4408 Function &F = *LLVMBB->getParent();
4409 FunctionLoweringInfo &FuncInfo = SDL.FuncInfo;
4410 SDOperand OldRoot = SDL.DAG.getRoot();
4411 std::vector<SDOperand> Args = TLI.LowerArguments(F, SDL.DAG);
4414 for (Function::arg_iterator AI = F.arg_begin(), E = F.arg_end();
4416 if (!AI->use_empty()) {
4417 SDL.setValue(AI, Args[a]);
4419 // If this argument is live outside of the entry block, insert a copy from
4420 // whereever we got it to the vreg that other BB's will reference it as.
4421 DenseMap<const Value*, unsigned>::iterator VMI=FuncInfo.ValueMap.find(AI);
4422 if (VMI != FuncInfo.ValueMap.end()) {
4423 SDOperand Copy = SDL.CopyValueToVirtualRegister(AI, VMI->second);
4424 UnorderedChains.push_back(Copy);
4428 // Finally, if the target has anything special to do, allow it to do so.
4429 // FIXME: this should insert code into the DAG!
4430 EmitFunctionEntryCode(F, SDL.DAG.getMachineFunction());
4433 void SelectionDAGISel::BuildSelectionDAG(SelectionDAG &DAG, BasicBlock *LLVMBB,
4434 std::vector<std::pair<MachineInstr*, unsigned> > &PHINodesToUpdate,
4435 FunctionLoweringInfo &FuncInfo) {
4436 SelectionDAGLowering SDL(DAG, TLI, FuncInfo);
4438 std::vector<SDOperand> UnorderedChains;
4440 // Lower any arguments needed in this block if this is the entry block.
4441 if (LLVMBB == &LLVMBB->getParent()->getEntryBlock())
4442 LowerArguments(LLVMBB, SDL, UnorderedChains);
4444 BB = FuncInfo.MBBMap[LLVMBB];
4445 SDL.setCurrentBasicBlock(BB);
4447 // Lower all of the non-terminator instructions.
4448 for (BasicBlock::iterator I = LLVMBB->begin(), E = --LLVMBB->end();
4452 // Lower call part of invoke.
4453 InvokeInst *Invoke = dyn_cast<InvokeInst>(LLVMBB->getTerminator());
4454 if (Invoke) SDL.visitInvoke(*Invoke, false);
4456 // Ensure that all instructions which are used outside of their defining
4457 // blocks are available as virtual registers.
4458 for (BasicBlock::iterator I = LLVMBB->begin(), E = LLVMBB->end(); I != E;++I)
4459 if (!I->use_empty() && !isa<PHINode>(I)) {
4460 DenseMap<const Value*, unsigned>::iterator VMI =FuncInfo.ValueMap.find(I);
4461 if (VMI != FuncInfo.ValueMap.end())
4462 UnorderedChains.push_back(
4463 SDL.CopyValueToVirtualRegister(I, VMI->second));
4466 // Handle PHI nodes in successor blocks. Emit code into the SelectionDAG to
4467 // ensure constants are generated when needed. Remember the virtual registers
4468 // that need to be added to the Machine PHI nodes as input. We cannot just
4469 // directly add them, because expansion might result in multiple MBB's for one
4470 // BB. As such, the start of the BB might correspond to a different MBB than
4473 TerminatorInst *TI = LLVMBB->getTerminator();
4475 // Emit constants only once even if used by multiple PHI nodes.
4476 std::map<Constant*, unsigned> ConstantsOut;
4478 // Vector bool would be better, but vector<bool> is really slow.
4479 std::vector<unsigned char> SuccsHandled;
4480 if (TI->getNumSuccessors())
4481 SuccsHandled.resize(BB->getParent()->getNumBlockIDs());
4483 // Check successor nodes PHI nodes that expect a constant to be available from
4485 for (unsigned succ = 0, e = TI->getNumSuccessors(); succ != e; ++succ) {
4486 BasicBlock *SuccBB = TI->getSuccessor(succ);
4487 if (!isa<PHINode>(SuccBB->begin())) continue;
4488 MachineBasicBlock *SuccMBB = FuncInfo.MBBMap[SuccBB];
4490 // If this terminator has multiple identical successors (common for
4491 // switches), only handle each succ once.
4492 unsigned SuccMBBNo = SuccMBB->getNumber();
4493 if (SuccsHandled[SuccMBBNo]) continue;
4494 SuccsHandled[SuccMBBNo] = true;
4496 MachineBasicBlock::iterator MBBI = SuccMBB->begin();
4499 // At this point we know that there is a 1-1 correspondence between LLVM PHI
4500 // nodes and Machine PHI nodes, but the incoming operands have not been
4502 for (BasicBlock::iterator I = SuccBB->begin();
4503 (PN = dyn_cast<PHINode>(I)); ++I) {
4504 // Ignore dead phi's.
4505 if (PN->use_empty()) continue;
4508 Value *PHIOp = PN->getIncomingValueForBlock(LLVMBB);
4510 if (Constant *C = dyn_cast<Constant>(PHIOp)) {
4511 unsigned &RegOut = ConstantsOut[C];
4513 RegOut = FuncInfo.CreateRegForValue(C);
4514 UnorderedChains.push_back(
4515 SDL.CopyValueToVirtualRegister(C, RegOut));
4519 Reg = FuncInfo.ValueMap[PHIOp];
4521 assert(isa<AllocaInst>(PHIOp) &&
4522 FuncInfo.StaticAllocaMap.count(cast<AllocaInst>(PHIOp)) &&
4523 "Didn't codegen value into a register!??");
4524 Reg = FuncInfo.CreateRegForValue(PHIOp);
4525 UnorderedChains.push_back(
4526 SDL.CopyValueToVirtualRegister(PHIOp, Reg));
4530 // Remember that this register needs to added to the machine PHI node as
4531 // the input for this MBB.
4532 MVT::ValueType VT = TLI.getValueType(PN->getType());
4533 unsigned NumElements;
4534 if (VT != MVT::Vector)
4535 NumElements = TLI.getNumElements(VT);
4537 MVT::ValueType VT1,VT2;
4539 TLI.getVectorTypeBreakdown(cast<VectorType>(PN->getType()),
4542 for (unsigned i = 0, e = NumElements; i != e; ++i)
4543 PHINodesToUpdate.push_back(std::make_pair(MBBI++, Reg+i));
4546 ConstantsOut.clear();
4548 // Turn all of the unordered chains into one factored node.
4549 if (!UnorderedChains.empty()) {
4550 SDOperand Root = SDL.getRoot();
4551 if (Root.getOpcode() != ISD::EntryToken) {
4552 unsigned i = 0, e = UnorderedChains.size();
4553 for (; i != e; ++i) {
4554 assert(UnorderedChains[i].Val->getNumOperands() > 1);
4555 if (UnorderedChains[i].Val->getOperand(0) == Root)
4556 break; // Don't add the root if we already indirectly depend on it.
4560 UnorderedChains.push_back(Root);
4562 DAG.setRoot(DAG.getNode(ISD::TokenFactor, MVT::Other,
4563 &UnorderedChains[0], UnorderedChains.size()));
4566 // Lower the terminator after the copies are emitted.
4568 // Just the branch part of invoke.
4569 SDL.visitInvoke(*Invoke, true);
4571 SDL.visit(*LLVMBB->getTerminator());
4574 // Copy over any CaseBlock records that may now exist due to SwitchInst
4575 // lowering, as well as any jump table information.
4576 SwitchCases.clear();
4577 SwitchCases = SDL.SwitchCases;
4579 JTCases = SDL.JTCases;
4580 BitTestCases.clear();
4581 BitTestCases = SDL.BitTestCases;
4583 // Make sure the root of the DAG is up-to-date.
4584 DAG.setRoot(SDL.getRoot());
4587 void SelectionDAGISel::CodeGenAndEmitDAG(SelectionDAG &DAG) {
4588 // Get alias analysis for load/store combining.
4589 AliasAnalysis &AA = getAnalysis<AliasAnalysis>();
4591 // Run the DAG combiner in pre-legalize mode.
4592 DAG.Combine(false, AA);
4594 DOUT << "Lowered selection DAG:\n";
4597 // Second step, hack on the DAG until it only uses operations and types that
4598 // the target supports.
4601 DOUT << "Legalized selection DAG:\n";
4604 // Run the DAG combiner in post-legalize mode.
4605 DAG.Combine(true, AA);
4607 if (ViewISelDAGs) DAG.viewGraph();
4609 // Third, instruction select all of the operations to machine code, adding the
4610 // code to the MachineBasicBlock.
4611 InstructionSelectBasicBlock(DAG);
4613 DOUT << "Selected machine code:\n";
4617 void SelectionDAGISel::SelectBasicBlock(BasicBlock *LLVMBB, MachineFunction &MF,
4618 FunctionLoweringInfo &FuncInfo) {
4619 std::vector<std::pair<MachineInstr*, unsigned> > PHINodesToUpdate;
4621 SelectionDAG DAG(TLI, MF, getAnalysisToUpdate<MachineModuleInfo>());
4624 // First step, lower LLVM code to some DAG. This DAG may use operations and
4625 // types that are not supported by the target.
4626 BuildSelectionDAG(DAG, LLVMBB, PHINodesToUpdate, FuncInfo);
4628 // Second step, emit the lowered DAG as machine code.
4629 CodeGenAndEmitDAG(DAG);
4632 DOUT << "Total amount of phi nodes to update: "
4633 << PHINodesToUpdate.size() << "\n";
4634 DEBUG(for (unsigned i = 0, e = PHINodesToUpdate.size(); i != e; ++i)
4635 DOUT << "Node " << i << " : (" << PHINodesToUpdate[i].first
4636 << ", " << PHINodesToUpdate[i].second << ")\n";);
4638 // Next, now that we know what the last MBB the LLVM BB expanded is, update
4639 // PHI nodes in successors.
4640 if (SwitchCases.empty() && JTCases.empty() && BitTestCases.empty()) {
4641 for (unsigned i = 0, e = PHINodesToUpdate.size(); i != e; ++i) {
4642 MachineInstr *PHI = PHINodesToUpdate[i].first;
4643 assert(PHI->getOpcode() == TargetInstrInfo::PHI &&
4644 "This is not a machine PHI node that we are updating!");
4645 PHI->addRegOperand(PHINodesToUpdate[i].second, false);
4646 PHI->addMachineBasicBlockOperand(BB);
4651 for (unsigned i = 0, e = BitTestCases.size(); i != e; ++i) {
4652 // Lower header first, if it wasn't already lowered
4653 if (!BitTestCases[i].Emitted) {
4654 SelectionDAG HSDAG(TLI, MF, getAnalysisToUpdate<MachineModuleInfo>());
4656 SelectionDAGLowering HSDL(HSDAG, TLI, FuncInfo);
4657 // Set the current basic block to the mbb we wish to insert the code into
4658 BB = BitTestCases[i].Parent;
4659 HSDL.setCurrentBasicBlock(BB);
4661 HSDL.visitBitTestHeader(BitTestCases[i]);
4662 HSDAG.setRoot(HSDL.getRoot());
4663 CodeGenAndEmitDAG(HSDAG);
4666 for (unsigned j = 0, ej = BitTestCases[i].Cases.size(); j != ej; ++j) {
4667 SelectionDAG BSDAG(TLI, MF, getAnalysisToUpdate<MachineModuleInfo>());
4669 SelectionDAGLowering BSDL(BSDAG, TLI, FuncInfo);
4670 // Set the current basic block to the mbb we wish to insert the code into
4671 BB = BitTestCases[i].Cases[j].ThisBB;
4672 BSDL.setCurrentBasicBlock(BB);
4675 BSDL.visitBitTestCase(BitTestCases[i].Cases[j+1].ThisBB,
4676 BitTestCases[i].Reg,
4677 BitTestCases[i].Cases[j]);
4679 BSDL.visitBitTestCase(BitTestCases[i].Default,
4680 BitTestCases[i].Reg,
4681 BitTestCases[i].Cases[j]);
4684 BSDAG.setRoot(BSDL.getRoot());
4685 CodeGenAndEmitDAG(BSDAG);
4689 for (unsigned pi = 0, pe = PHINodesToUpdate.size(); pi != pe; ++pi) {
4690 MachineInstr *PHI = PHINodesToUpdate[pi].first;
4691 MachineBasicBlock *PHIBB = PHI->getParent();
4692 assert(PHI->getOpcode() == TargetInstrInfo::PHI &&
4693 "This is not a machine PHI node that we are updating!");
4694 // This is "default" BB. We have two jumps to it. From "header" BB and
4695 // from last "case" BB.
4696 if (PHIBB == BitTestCases[i].Default) {
4697 PHI->addRegOperand(PHINodesToUpdate[pi].second, false);
4698 PHI->addMachineBasicBlockOperand(BitTestCases[i].Parent);
4699 PHI->addRegOperand(PHINodesToUpdate[pi].second, false);
4700 PHI->addMachineBasicBlockOperand(BitTestCases[i].Cases.back().ThisBB);
4702 // One of "cases" BB.
4703 for (unsigned j = 0, ej = BitTestCases[i].Cases.size(); j != ej; ++j) {
4704 MachineBasicBlock* cBB = BitTestCases[i].Cases[j].ThisBB;
4705 if (cBB->succ_end() !=
4706 std::find(cBB->succ_begin(),cBB->succ_end(), PHIBB)) {
4707 PHI->addRegOperand(PHINodesToUpdate[pi].second, false);
4708 PHI->addMachineBasicBlockOperand(cBB);
4714 // If the JumpTable record is filled in, then we need to emit a jump table.
4715 // Updating the PHI nodes is tricky in this case, since we need to determine
4716 // whether the PHI is a successor of the range check MBB or the jump table MBB
4717 for (unsigned i = 0, e = JTCases.size(); i != e; ++i) {
4718 // Lower header first, if it wasn't already lowered
4719 if (!JTCases[i].first.Emitted) {
4720 SelectionDAG HSDAG(TLI, MF, getAnalysisToUpdate<MachineModuleInfo>());
4722 SelectionDAGLowering HSDL(HSDAG, TLI, FuncInfo);
4723 // Set the current basic block to the mbb we wish to insert the code into
4724 BB = JTCases[i].first.HeaderBB;
4725 HSDL.setCurrentBasicBlock(BB);
4727 HSDL.visitJumpTableHeader(JTCases[i].second, JTCases[i].first);
4728 HSDAG.setRoot(HSDL.getRoot());
4729 CodeGenAndEmitDAG(HSDAG);
4732 SelectionDAG JSDAG(TLI, MF, getAnalysisToUpdate<MachineModuleInfo>());
4734 SelectionDAGLowering JSDL(JSDAG, TLI, FuncInfo);
4735 // Set the current basic block to the mbb we wish to insert the code into
4736 BB = JTCases[i].second.MBB;
4737 JSDL.setCurrentBasicBlock(BB);
4739 JSDL.visitJumpTable(JTCases[i].second);
4740 JSDAG.setRoot(JSDL.getRoot());
4741 CodeGenAndEmitDAG(JSDAG);
4744 for (unsigned pi = 0, pe = PHINodesToUpdate.size(); pi != pe; ++pi) {
4745 MachineInstr *PHI = PHINodesToUpdate[pi].first;
4746 MachineBasicBlock *PHIBB = PHI->getParent();
4747 assert(PHI->getOpcode() == TargetInstrInfo::PHI &&
4748 "This is not a machine PHI node that we are updating!");
4749 // "default" BB. We can go there only from header BB.
4750 if (PHIBB == JTCases[i].second.Default) {
4751 PHI->addRegOperand(PHINodesToUpdate[pi].second, false);
4752 PHI->addMachineBasicBlockOperand(JTCases[i].first.HeaderBB);
4754 // JT BB. Just iterate over successors here
4755 if (BB->succ_end() != std::find(BB->succ_begin(),BB->succ_end(), PHIBB)) {
4756 PHI->addRegOperand(PHINodesToUpdate[pi].second, false);
4757 PHI->addMachineBasicBlockOperand(BB);
4762 // If the switch block involved a branch to one of the actual successors, we
4763 // need to update PHI nodes in that block.
4764 for (unsigned i = 0, e = PHINodesToUpdate.size(); i != e; ++i) {
4765 MachineInstr *PHI = PHINodesToUpdate[i].first;
4766 assert(PHI->getOpcode() == TargetInstrInfo::PHI &&
4767 "This is not a machine PHI node that we are updating!");
4768 if (BB->isSuccessor(PHI->getParent())) {
4769 PHI->addRegOperand(PHINodesToUpdate[i].second, false);
4770 PHI->addMachineBasicBlockOperand(BB);
4774 // If we generated any switch lowering information, build and codegen any
4775 // additional DAGs necessary.
4776 for (unsigned i = 0, e = SwitchCases.size(); i != e; ++i) {
4777 SelectionDAG SDAG(TLI, MF, getAnalysisToUpdate<MachineModuleInfo>());
4779 SelectionDAGLowering SDL(SDAG, TLI, FuncInfo);
4781 // Set the current basic block to the mbb we wish to insert the code into
4782 BB = SwitchCases[i].ThisBB;
4783 SDL.setCurrentBasicBlock(BB);
4786 SDL.visitSwitchCase(SwitchCases[i]);
4787 SDAG.setRoot(SDL.getRoot());
4788 CodeGenAndEmitDAG(SDAG);
4790 // Handle any PHI nodes in successors of this chunk, as if we were coming
4791 // from the original BB before switch expansion. Note that PHI nodes can
4792 // occur multiple times in PHINodesToUpdate. We have to be very careful to
4793 // handle them the right number of times.
4794 while ((BB = SwitchCases[i].TrueBB)) { // Handle LHS and RHS.
4795 for (MachineBasicBlock::iterator Phi = BB->begin();
4796 Phi != BB->end() && Phi->getOpcode() == TargetInstrInfo::PHI; ++Phi){
4797 // This value for this PHI node is recorded in PHINodesToUpdate, get it.
4798 for (unsigned pn = 0; ; ++pn) {
4799 assert(pn != PHINodesToUpdate.size() && "Didn't find PHI entry!");
4800 if (PHINodesToUpdate[pn].first == Phi) {
4801 Phi->addRegOperand(PHINodesToUpdate[pn].second, false);
4802 Phi->addMachineBasicBlockOperand(SwitchCases[i].ThisBB);
4808 // Don't process RHS if same block as LHS.
4809 if (BB == SwitchCases[i].FalseBB)
4810 SwitchCases[i].FalseBB = 0;
4812 // If we haven't handled the RHS, do so now. Otherwise, we're done.
4813 SwitchCases[i].TrueBB = SwitchCases[i].FalseBB;
4814 SwitchCases[i].FalseBB = 0;
4816 assert(SwitchCases[i].TrueBB == 0 && SwitchCases[i].FalseBB == 0);
4821 //===----------------------------------------------------------------------===//
4822 /// ScheduleAndEmitDAG - Pick a safe ordering and emit instructions for each
4823 /// target node in the graph.
4824 void SelectionDAGISel::ScheduleAndEmitDAG(SelectionDAG &DAG) {
4825 if (ViewSchedDAGs) DAG.viewGraph();
4827 RegisterScheduler::FunctionPassCtor Ctor = RegisterScheduler::getDefault();
4831 RegisterScheduler::setDefault(Ctor);
4834 ScheduleDAG *SL = Ctor(this, &DAG, BB);
4840 HazardRecognizer *SelectionDAGISel::CreateTargetHazardRecognizer() {
4841 return new HazardRecognizer();
4844 //===----------------------------------------------------------------------===//
4845 // Helper functions used by the generated instruction selector.
4846 //===----------------------------------------------------------------------===//
4847 // Calls to these methods are generated by tblgen.
4849 /// CheckAndMask - The isel is trying to match something like (and X, 255). If
4850 /// the dag combiner simplified the 255, we still want to match. RHS is the
4851 /// actual value in the DAG on the RHS of an AND, and DesiredMaskS is the value
4852 /// specified in the .td file (e.g. 255).
4853 bool SelectionDAGISel::CheckAndMask(SDOperand LHS, ConstantSDNode *RHS,
4854 int64_t DesiredMaskS) {
4855 uint64_t ActualMask = RHS->getValue();
4856 uint64_t DesiredMask =DesiredMaskS & MVT::getIntVTBitMask(LHS.getValueType());
4858 // If the actual mask exactly matches, success!
4859 if (ActualMask == DesiredMask)
4862 // If the actual AND mask is allowing unallowed bits, this doesn't match.
4863 if (ActualMask & ~DesiredMask)
4866 // Otherwise, the DAG Combiner may have proven that the value coming in is
4867 // either already zero or is not demanded. Check for known zero input bits.
4868 uint64_t NeededMask = DesiredMask & ~ActualMask;
4869 if (getTargetLowering().MaskedValueIsZero(LHS, NeededMask))
4872 // TODO: check to see if missing bits are just not demanded.
4874 // Otherwise, this pattern doesn't match.
4878 /// CheckOrMask - The isel is trying to match something like (or X, 255). If
4879 /// the dag combiner simplified the 255, we still want to match. RHS is the
4880 /// actual value in the DAG on the RHS of an OR, and DesiredMaskS is the value
4881 /// specified in the .td file (e.g. 255).
4882 bool SelectionDAGISel::CheckOrMask(SDOperand LHS, ConstantSDNode *RHS,
4883 int64_t DesiredMaskS) {
4884 uint64_t ActualMask = RHS->getValue();
4885 uint64_t DesiredMask =DesiredMaskS & MVT::getIntVTBitMask(LHS.getValueType());
4887 // If the actual mask exactly matches, success!
4888 if (ActualMask == DesiredMask)
4891 // If the actual AND mask is allowing unallowed bits, this doesn't match.
4892 if (ActualMask & ~DesiredMask)
4895 // Otherwise, the DAG Combiner may have proven that the value coming in is
4896 // either already zero or is not demanded. Check for known zero input bits.
4897 uint64_t NeededMask = DesiredMask & ~ActualMask;
4899 uint64_t KnownZero, KnownOne;
4900 getTargetLowering().ComputeMaskedBits(LHS, NeededMask, KnownZero, KnownOne);
4902 // If all the missing bits in the or are already known to be set, match!
4903 if ((NeededMask & KnownOne) == NeededMask)
4906 // TODO: check to see if missing bits are just not demanded.
4908 // Otherwise, this pattern doesn't match.
4913 /// SelectInlineAsmMemoryOperands - Calls to this are automatically generated
4914 /// by tblgen. Others should not call it.
4915 void SelectionDAGISel::
4916 SelectInlineAsmMemoryOperands(std::vector<SDOperand> &Ops, SelectionDAG &DAG) {
4917 std::vector<SDOperand> InOps;
4918 std::swap(InOps, Ops);
4920 Ops.push_back(InOps[0]); // input chain.
4921 Ops.push_back(InOps[1]); // input asm string.
4923 unsigned i = 2, e = InOps.size();
4924 if (InOps[e-1].getValueType() == MVT::Flag)
4925 --e; // Don't process a flag operand if it is here.
4928 unsigned Flags = cast<ConstantSDNode>(InOps[i])->getValue();
4929 if ((Flags & 7) != 4 /*MEM*/) {
4930 // Just skip over this operand, copying the operands verbatim.
4931 Ops.insert(Ops.end(), InOps.begin()+i, InOps.begin()+i+(Flags >> 3) + 1);
4932 i += (Flags >> 3) + 1;
4934 assert((Flags >> 3) == 1 && "Memory operand with multiple values?");
4935 // Otherwise, this is a memory operand. Ask the target to select it.
4936 std::vector<SDOperand> SelOps;
4937 if (SelectInlineAsmMemoryOperand(InOps[i+1], 'm', SelOps, DAG)) {
4938 cerr << "Could not match memory address. Inline asm failure!\n";
4942 // Add this to the output node.
4943 MVT::ValueType IntPtrTy = DAG.getTargetLoweringInfo().getPointerTy();
4944 Ops.push_back(DAG.getTargetConstant(4/*MEM*/ | (SelOps.size() << 3),
4946 Ops.insert(Ops.end(), SelOps.begin(), SelOps.end());
4951 // Add the flag input back if present.
4952 if (e != InOps.size())
4953 Ops.push_back(InOps.back());