1 //===-- SelectionDAGISel.cpp - Implement the SelectionDAGISel class -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements the SelectionDAGISel class.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "isel"
15 #include "llvm/CodeGen/SelectionDAGISel.h"
16 #include "ScheduleDAGSDNodes.h"
17 #include "SelectionDAGBuilder.h"
18 #include "llvm/ADT/PostOrderIterator.h"
19 #include "llvm/ADT/Statistic.h"
20 #include "llvm/Analysis/AliasAnalysis.h"
21 #include "llvm/Analysis/BranchProbabilityInfo.h"
22 #include "llvm/Analysis/TargetTransformInfo.h"
23 #include "llvm/CodeGen/FastISel.h"
24 #include "llvm/CodeGen/FunctionLoweringInfo.h"
25 #include "llvm/CodeGen/GCMetadata.h"
26 #include "llvm/CodeGen/GCStrategy.h"
27 #include "llvm/CodeGen/MachineFrameInfo.h"
28 #include "llvm/CodeGen/MachineFunction.h"
29 #include "llvm/CodeGen/MachineInstrBuilder.h"
30 #include "llvm/CodeGen/MachineModuleInfo.h"
31 #include "llvm/CodeGen/MachineRegisterInfo.h"
32 #include "llvm/CodeGen/ScheduleHazardRecognizer.h"
33 #include "llvm/CodeGen/SchedulerRegistry.h"
34 #include "llvm/CodeGen/SelectionDAG.h"
35 #include "llvm/DebugInfo.h"
36 #include "llvm/IR/Constants.h"
37 #include "llvm/IR/Function.h"
38 #include "llvm/IR/InlineAsm.h"
39 #include "llvm/IR/Instructions.h"
40 #include "llvm/IR/IntrinsicInst.h"
41 #include "llvm/IR/Intrinsics.h"
42 #include "llvm/IR/LLVMContext.h"
43 #include "llvm/IR/Module.h"
44 #include "llvm/Support/Compiler.h"
45 #include "llvm/Support/Debug.h"
46 #include "llvm/Support/ErrorHandling.h"
47 #include "llvm/Support/Timer.h"
48 #include "llvm/Support/raw_ostream.h"
49 #include "llvm/Target/TargetInstrInfo.h"
50 #include "llvm/Target/TargetIntrinsicInfo.h"
51 #include "llvm/Target/TargetLibraryInfo.h"
52 #include "llvm/Target/TargetLowering.h"
53 #include "llvm/Target/TargetMachine.h"
54 #include "llvm/Target/TargetOptions.h"
55 #include "llvm/Target/TargetRegisterInfo.h"
56 #include "llvm/Target/TargetSubtargetInfo.h"
57 #include "llvm/Transforms/Utils/BasicBlockUtils.h"
61 STATISTIC(NumFastIselBlocks, "Number of blocks selected entirely by fast isel");
62 STATISTIC(NumDAGBlocks, "Number of blocks selected using DAG");
65 STATISTIC(NumDAGIselRetries,"Number of times dag isel has to try another path");
66 STATISTIC(NumFastIselFailures, "Number of instructions fast isel failed on");
67 STATISTIC(NumFastIselSuccess, "Number of instructions fast isel selected");
70 EnableFastISelVerbose2("fast-isel-verbose2", cl::Hidden,
71 cl::desc("Enable extra verbose messages in the \"fast\" "
72 "instruction selector"));
74 STATISTIC(NumFastIselFailRet,"Fast isel fails on Ret");
75 STATISTIC(NumFastIselFailBr,"Fast isel fails on Br");
76 STATISTIC(NumFastIselFailSwitch,"Fast isel fails on Switch");
77 STATISTIC(NumFastIselFailIndirectBr,"Fast isel fails on IndirectBr");
78 STATISTIC(NumFastIselFailInvoke,"Fast isel fails on Invoke");
79 STATISTIC(NumFastIselFailResume,"Fast isel fails on Resume");
80 STATISTIC(NumFastIselFailUnreachable,"Fast isel fails on Unreachable");
82 // Standard binary operators...
83 STATISTIC(NumFastIselFailAdd,"Fast isel fails on Add");
84 STATISTIC(NumFastIselFailFAdd,"Fast isel fails on FAdd");
85 STATISTIC(NumFastIselFailSub,"Fast isel fails on Sub");
86 STATISTIC(NumFastIselFailFSub,"Fast isel fails on FSub");
87 STATISTIC(NumFastIselFailMul,"Fast isel fails on Mul");
88 STATISTIC(NumFastIselFailFMul,"Fast isel fails on FMul");
89 STATISTIC(NumFastIselFailUDiv,"Fast isel fails on UDiv");
90 STATISTIC(NumFastIselFailSDiv,"Fast isel fails on SDiv");
91 STATISTIC(NumFastIselFailFDiv,"Fast isel fails on FDiv");
92 STATISTIC(NumFastIselFailURem,"Fast isel fails on URem");
93 STATISTIC(NumFastIselFailSRem,"Fast isel fails on SRem");
94 STATISTIC(NumFastIselFailFRem,"Fast isel fails on FRem");
96 // Logical operators...
97 STATISTIC(NumFastIselFailAnd,"Fast isel fails on And");
98 STATISTIC(NumFastIselFailOr,"Fast isel fails on Or");
99 STATISTIC(NumFastIselFailXor,"Fast isel fails on Xor");
101 // Memory instructions...
102 STATISTIC(NumFastIselFailAlloca,"Fast isel fails on Alloca");
103 STATISTIC(NumFastIselFailLoad,"Fast isel fails on Load");
104 STATISTIC(NumFastIselFailStore,"Fast isel fails on Store");
105 STATISTIC(NumFastIselFailAtomicCmpXchg,"Fast isel fails on AtomicCmpXchg");
106 STATISTIC(NumFastIselFailAtomicRMW,"Fast isel fails on AtomicRWM");
107 STATISTIC(NumFastIselFailFence,"Fast isel fails on Frence");
108 STATISTIC(NumFastIselFailGetElementPtr,"Fast isel fails on GetElementPtr");
110 // Convert instructions...
111 STATISTIC(NumFastIselFailTrunc,"Fast isel fails on Trunc");
112 STATISTIC(NumFastIselFailZExt,"Fast isel fails on ZExt");
113 STATISTIC(NumFastIselFailSExt,"Fast isel fails on SExt");
114 STATISTIC(NumFastIselFailFPTrunc,"Fast isel fails on FPTrunc");
115 STATISTIC(NumFastIselFailFPExt,"Fast isel fails on FPExt");
116 STATISTIC(NumFastIselFailFPToUI,"Fast isel fails on FPToUI");
117 STATISTIC(NumFastIselFailFPToSI,"Fast isel fails on FPToSI");
118 STATISTIC(NumFastIselFailUIToFP,"Fast isel fails on UIToFP");
119 STATISTIC(NumFastIselFailSIToFP,"Fast isel fails on SIToFP");
120 STATISTIC(NumFastIselFailIntToPtr,"Fast isel fails on IntToPtr");
121 STATISTIC(NumFastIselFailPtrToInt,"Fast isel fails on PtrToInt");
122 STATISTIC(NumFastIselFailBitCast,"Fast isel fails on BitCast");
124 // Other instructions...
125 STATISTIC(NumFastIselFailICmp,"Fast isel fails on ICmp");
126 STATISTIC(NumFastIselFailFCmp,"Fast isel fails on FCmp");
127 STATISTIC(NumFastIselFailPHI,"Fast isel fails on PHI");
128 STATISTIC(NumFastIselFailSelect,"Fast isel fails on Select");
129 STATISTIC(NumFastIselFailCall,"Fast isel fails on Call");
130 STATISTIC(NumFastIselFailShl,"Fast isel fails on Shl");
131 STATISTIC(NumFastIselFailLShr,"Fast isel fails on LShr");
132 STATISTIC(NumFastIselFailAShr,"Fast isel fails on AShr");
133 STATISTIC(NumFastIselFailVAArg,"Fast isel fails on VAArg");
134 STATISTIC(NumFastIselFailExtractElement,"Fast isel fails on ExtractElement");
135 STATISTIC(NumFastIselFailInsertElement,"Fast isel fails on InsertElement");
136 STATISTIC(NumFastIselFailShuffleVector,"Fast isel fails on ShuffleVector");
137 STATISTIC(NumFastIselFailExtractValue,"Fast isel fails on ExtractValue");
138 STATISTIC(NumFastIselFailInsertValue,"Fast isel fails on InsertValue");
139 STATISTIC(NumFastIselFailLandingPad,"Fast isel fails on LandingPad");
143 EnableFastISelVerbose("fast-isel-verbose", cl::Hidden,
144 cl::desc("Enable verbose messages in the \"fast\" "
145 "instruction selector"));
147 EnableFastISelAbort("fast-isel-abort", cl::Hidden,
148 cl::desc("Enable abort calls when \"fast\" instruction selection "
149 "fails to lower an instruction"));
151 EnableFastISelAbortArgs("fast-isel-abort-args", cl::Hidden,
152 cl::desc("Enable abort calls when \"fast\" instruction selection "
153 "fails to lower a formal argument"));
157 cl::desc("use Machine Branch Probability Info"),
158 cl::init(true), cl::Hidden);
162 ViewDAGCombine1("view-dag-combine1-dags", cl::Hidden,
163 cl::desc("Pop up a window to show dags before the first "
164 "dag combine pass"));
166 ViewLegalizeTypesDAGs("view-legalize-types-dags", cl::Hidden,
167 cl::desc("Pop up a window to show dags before legalize types"));
169 ViewLegalizeDAGs("view-legalize-dags", cl::Hidden,
170 cl::desc("Pop up a window to show dags before legalize"));
172 ViewDAGCombine2("view-dag-combine2-dags", cl::Hidden,
173 cl::desc("Pop up a window to show dags before the second "
174 "dag combine pass"));
176 ViewDAGCombineLT("view-dag-combine-lt-dags", cl::Hidden,
177 cl::desc("Pop up a window to show dags before the post legalize types"
178 " dag combine pass"));
180 ViewISelDAGs("view-isel-dags", cl::Hidden,
181 cl::desc("Pop up a window to show isel dags as they are selected"));
183 ViewSchedDAGs("view-sched-dags", cl::Hidden,
184 cl::desc("Pop up a window to show sched dags as they are processed"));
186 ViewSUnitDAGs("view-sunit-dags", cl::Hidden,
187 cl::desc("Pop up a window to show SUnit dags after they are processed"));
189 static const bool ViewDAGCombine1 = false,
190 ViewLegalizeTypesDAGs = false, ViewLegalizeDAGs = false,
191 ViewDAGCombine2 = false,
192 ViewDAGCombineLT = false,
193 ViewISelDAGs = false, ViewSchedDAGs = false,
194 ViewSUnitDAGs = false;
197 //===---------------------------------------------------------------------===//
199 /// RegisterScheduler class - Track the registration of instruction schedulers.
201 //===---------------------------------------------------------------------===//
202 MachinePassRegistry RegisterScheduler::Registry;
204 //===---------------------------------------------------------------------===//
206 /// ISHeuristic command line option for instruction schedulers.
208 //===---------------------------------------------------------------------===//
209 static cl::opt<RegisterScheduler::FunctionPassCtor, false,
210 RegisterPassParser<RegisterScheduler> >
211 ISHeuristic("pre-RA-sched",
212 cl::init(&createDefaultScheduler),
213 cl::desc("Instruction schedulers available (before register"
216 static RegisterScheduler
217 defaultListDAGScheduler("default", "Best scheduler for the target",
218 createDefaultScheduler);
221 //===--------------------------------------------------------------------===//
222 /// createDefaultScheduler - This creates an instruction scheduler appropriate
224 ScheduleDAGSDNodes* createDefaultScheduler(SelectionDAGISel *IS,
225 CodeGenOpt::Level OptLevel) {
226 const TargetLowering &TLI = IS->getTargetLowering();
227 const TargetSubtargetInfo &ST = IS->TM.getSubtarget<TargetSubtargetInfo>();
229 if (OptLevel == CodeGenOpt::None || ST.enableMachineScheduler() ||
230 TLI.getSchedulingPreference() == Sched::Source)
231 return createSourceListDAGScheduler(IS, OptLevel);
232 if (TLI.getSchedulingPreference() == Sched::RegPressure)
233 return createBURRListDAGScheduler(IS, OptLevel);
234 if (TLI.getSchedulingPreference() == Sched::Hybrid)
235 return createHybridListDAGScheduler(IS, OptLevel);
236 if (TLI.getSchedulingPreference() == Sched::VLIW)
237 return createVLIWDAGScheduler(IS, OptLevel);
238 assert(TLI.getSchedulingPreference() == Sched::ILP &&
239 "Unknown sched type!");
240 return createILPListDAGScheduler(IS, OptLevel);
244 // EmitInstrWithCustomInserter - This method should be implemented by targets
245 // that mark instructions with the 'usesCustomInserter' flag. These
246 // instructions are special in various ways, which require special support to
247 // insert. The specified MachineInstr is created but not inserted into any
248 // basic blocks, and this method is called to expand it into a sequence of
249 // instructions, potentially also creating new basic blocks and control flow.
250 // When new basic blocks are inserted and the edges from MBB to its successors
251 // are modified, the method should insert pairs of <OldSucc, NewSucc> into the
254 TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
255 MachineBasicBlock *MBB) const {
257 dbgs() << "If a target marks an instruction with "
258 "'usesCustomInserter', it must implement "
259 "TargetLowering::EmitInstrWithCustomInserter!";
264 void TargetLowering::AdjustInstrPostInstrSelection(MachineInstr *MI,
265 SDNode *Node) const {
266 assert(!MI->hasPostISelHook() &&
267 "If a target marks an instruction with 'hasPostISelHook', "
268 "it must implement TargetLowering::AdjustInstrPostInstrSelection!");
271 //===----------------------------------------------------------------------===//
272 // SelectionDAGISel code
273 //===----------------------------------------------------------------------===//
275 SelectionDAGISel::SelectionDAGISel(const TargetMachine &tm,
276 CodeGenOpt::Level OL) :
277 MachineFunctionPass(ID), TM(tm), TLI(*tm.getTargetLowering()),
278 FuncInfo(new FunctionLoweringInfo(TLI)),
279 CurDAG(new SelectionDAG(tm, OL)),
280 SDB(new SelectionDAGBuilder(*CurDAG, *FuncInfo, OL)),
284 initializeGCModuleInfoPass(*PassRegistry::getPassRegistry());
285 initializeAliasAnalysisAnalysisGroup(*PassRegistry::getPassRegistry());
286 initializeBranchProbabilityInfoPass(*PassRegistry::getPassRegistry());
287 initializeTargetLibraryInfoPass(*PassRegistry::getPassRegistry());
290 SelectionDAGISel::~SelectionDAGISel() {
296 void SelectionDAGISel::getAnalysisUsage(AnalysisUsage &AU) const {
297 AU.addRequired<AliasAnalysis>();
298 AU.addPreserved<AliasAnalysis>();
299 AU.addRequired<GCModuleInfo>();
300 AU.addPreserved<GCModuleInfo>();
301 AU.addRequired<TargetLibraryInfo>();
302 if (UseMBPI && OptLevel != CodeGenOpt::None)
303 AU.addRequired<BranchProbabilityInfo>();
304 MachineFunctionPass::getAnalysisUsage(AU);
307 /// SplitCriticalSideEffectEdges - Look for critical edges with a PHI value that
308 /// may trap on it. In this case we have to split the edge so that the path
309 /// through the predecessor block that doesn't go to the phi block doesn't
310 /// execute the possibly trapping instruction.
312 /// This is required for correctness, so it must be done at -O0.
314 static void SplitCriticalSideEffectEdges(Function &Fn, Pass *SDISel) {
315 // Loop for blocks with phi nodes.
316 for (Function::iterator BB = Fn.begin(), E = Fn.end(); BB != E; ++BB) {
317 PHINode *PN = dyn_cast<PHINode>(BB->begin());
318 if (PN == 0) continue;
321 // For each block with a PHI node, check to see if any of the input values
322 // are potentially trapping constant expressions. Constant expressions are
323 // the only potentially trapping value that can occur as the argument to a
325 for (BasicBlock::iterator I = BB->begin(); (PN = dyn_cast<PHINode>(I)); ++I)
326 for (unsigned i = 0, e = PN->getNumIncomingValues(); i != e; ++i) {
327 ConstantExpr *CE = dyn_cast<ConstantExpr>(PN->getIncomingValue(i));
328 if (CE == 0 || !CE->canTrap()) continue;
330 // The only case we have to worry about is when the edge is critical.
331 // Since this block has a PHI Node, we assume it has multiple input
332 // edges: check to see if the pred has multiple successors.
333 BasicBlock *Pred = PN->getIncomingBlock(i);
334 if (Pred->getTerminator()->getNumSuccessors() == 1)
337 // Okay, we have to split this edge.
338 SplitCriticalEdge(Pred->getTerminator(),
339 GetSuccessorNumber(Pred, BB), SDISel, true);
345 bool SelectionDAGISel::runOnMachineFunction(MachineFunction &mf) {
346 // Do some sanity-checking on the command-line options.
347 assert((!EnableFastISelVerbose || TM.Options.EnableFastISel) &&
348 "-fast-isel-verbose requires -fast-isel");
349 assert((!EnableFastISelAbort || TM.Options.EnableFastISel) &&
350 "-fast-isel-abort requires -fast-isel");
352 const Function &Fn = *mf.getFunction();
353 const TargetInstrInfo &TII = *TM.getInstrInfo();
354 const TargetRegisterInfo &TRI = *TM.getRegisterInfo();
357 RegInfo = &MF->getRegInfo();
358 AA = &getAnalysis<AliasAnalysis>();
359 LibInfo = &getAnalysis<TargetLibraryInfo>();
360 TTI = getAnalysisIfAvailable<TargetTransformInfo>();
361 GFI = Fn.hasGC() ? &getAnalysis<GCModuleInfo>().getFunctionInfo(Fn) : 0;
363 TargetSubtargetInfo &ST =
364 const_cast<TargetSubtargetInfo&>(TM.getSubtarget<TargetSubtargetInfo>());
365 ST.resetSubtargetFeatures(MF);
367 DEBUG(dbgs() << "\n\n\n=== " << Fn.getName() << "\n");
369 SplitCriticalSideEffectEdges(const_cast<Function&>(Fn), this);
371 CurDAG->init(*MF, TTI);
372 FuncInfo->set(Fn, *MF);
374 if (UseMBPI && OptLevel != CodeGenOpt::None)
375 FuncInfo->BPI = &getAnalysis<BranchProbabilityInfo>();
379 SDB->init(GFI, *AA, LibInfo);
381 MF->setHasMSInlineAsm(false);
382 SelectAllBasicBlocks(Fn);
384 // If the first basic block in the function has live ins that need to be
385 // copied into vregs, emit the copies into the top of the block before
386 // emitting the code for the block.
387 MachineBasicBlock *EntryMBB = MF->begin();
388 RegInfo->EmitLiveInCopies(EntryMBB, TRI, TII);
390 DenseMap<unsigned, unsigned> LiveInMap;
391 if (!FuncInfo->ArgDbgValues.empty())
392 for (MachineRegisterInfo::livein_iterator LI = RegInfo->livein_begin(),
393 E = RegInfo->livein_end(); LI != E; ++LI)
395 LiveInMap.insert(std::make_pair(LI->first, LI->second));
397 // Insert DBG_VALUE instructions for function arguments to the entry block.
398 for (unsigned i = 0, e = FuncInfo->ArgDbgValues.size(); i != e; ++i) {
399 MachineInstr *MI = FuncInfo->ArgDbgValues[e-i-1];
400 unsigned Reg = MI->getOperand(0).getReg();
401 if (TargetRegisterInfo::isPhysicalRegister(Reg))
402 EntryMBB->insert(EntryMBB->begin(), MI);
404 MachineInstr *Def = RegInfo->getVRegDef(Reg);
405 MachineBasicBlock::iterator InsertPos = Def;
406 // FIXME: VR def may not be in entry block.
407 Def->getParent()->insert(llvm::next(InsertPos), MI);
410 // If Reg is live-in then update debug info to track its copy in a vreg.
411 DenseMap<unsigned, unsigned>::iterator LDI = LiveInMap.find(Reg);
412 if (LDI != LiveInMap.end()) {
413 MachineInstr *Def = RegInfo->getVRegDef(LDI->second);
414 MachineBasicBlock::iterator InsertPos = Def;
415 const MDNode *Variable =
416 MI->getOperand(MI->getNumOperands()-1).getMetadata();
417 unsigned Offset = MI->getOperand(1).getImm();
418 // Def is never a terminator here, so it is ok to increment InsertPos.
419 BuildMI(*EntryMBB, ++InsertPos, MI->getDebugLoc(),
420 TII.get(TargetOpcode::DBG_VALUE))
421 .addReg(LDI->second, RegState::Debug)
422 .addImm(Offset).addMetadata(Variable);
424 // If this vreg is directly copied into an exported register then
425 // that COPY instructions also need DBG_VALUE, if it is the only
426 // user of LDI->second.
427 MachineInstr *CopyUseMI = NULL;
428 for (MachineRegisterInfo::use_iterator
429 UI = RegInfo->use_begin(LDI->second);
430 MachineInstr *UseMI = UI.skipInstruction();) {
431 if (UseMI->isDebugValue()) continue;
432 if (UseMI->isCopy() && !CopyUseMI && UseMI->getParent() == EntryMBB) {
433 CopyUseMI = UseMI; continue;
435 // Otherwise this is another use or second copy use.
436 CopyUseMI = NULL; break;
439 MachineInstr *NewMI =
440 BuildMI(*MF, CopyUseMI->getDebugLoc(),
441 TII.get(TargetOpcode::DBG_VALUE))
442 .addReg(CopyUseMI->getOperand(0).getReg(), RegState::Debug)
443 .addImm(Offset).addMetadata(Variable);
444 MachineBasicBlock::iterator Pos = CopyUseMI;
445 EntryMBB->insertAfter(Pos, NewMI);
450 // Determine if there are any calls in this machine function.
451 MachineFrameInfo *MFI = MF->getFrameInfo();
452 for (MachineFunction::const_iterator I = MF->begin(), E = MF->end(); I != E;
455 if (MFI->hasCalls() && MF->hasMSInlineAsm())
458 const MachineBasicBlock *MBB = I;
459 for (MachineBasicBlock::const_iterator II = MBB->begin(), IE = MBB->end();
461 const MCInstrDesc &MCID = TM.getInstrInfo()->get(II->getOpcode());
462 if ((MCID.isCall() && !MCID.isReturn()) ||
463 II->isStackAligningInlineAsm()) {
464 MFI->setHasCalls(true);
466 if (II->isMSInlineAsm()) {
467 MF->setHasMSInlineAsm(true);
472 // Determine if there is a call to setjmp in the machine function.
473 MF->setExposesReturnsTwice(Fn.callsFunctionThatReturnsTwice());
475 // Replace forward-declared registers with the registers containing
476 // the desired value.
477 MachineRegisterInfo &MRI = MF->getRegInfo();
478 for (DenseMap<unsigned, unsigned>::iterator
479 I = FuncInfo->RegFixups.begin(), E = FuncInfo->RegFixups.end();
481 unsigned From = I->first;
482 unsigned To = I->second;
483 // If To is also scheduled to be replaced, find what its ultimate
486 DenseMap<unsigned, unsigned>::iterator J = FuncInfo->RegFixups.find(To);
491 MRI.replaceRegWith(From, To);
494 // Freeze the set of reserved registers now that MachineFrameInfo has been
495 // set up. All the information required by getReservedRegs() should be
497 MRI.freezeReservedRegs(*MF);
499 // Release function-specific state. SDB and CurDAG are already cleared
506 void SelectionDAGISel::SelectBasicBlock(BasicBlock::const_iterator Begin,
507 BasicBlock::const_iterator End,
509 // Lower all of the non-terminator instructions. If a call is emitted
510 // as a tail call, cease emitting nodes for this block. Terminators
511 // are handled below.
512 for (BasicBlock::const_iterator I = Begin; I != End && !SDB->HasTailCall; ++I)
515 // Make sure the root of the DAG is up-to-date.
516 CurDAG->setRoot(SDB->getControlRoot());
517 HadTailCall = SDB->HasTailCall;
520 // Final step, emit the lowered DAG as machine code.
524 void SelectionDAGISel::ComputeLiveOutVRegInfo() {
525 SmallPtrSet<SDNode*, 128> VisitedNodes;
526 SmallVector<SDNode*, 128> Worklist;
528 Worklist.push_back(CurDAG->getRoot().getNode());
534 SDNode *N = Worklist.pop_back_val();
536 // If we've already seen this node, ignore it.
537 if (!VisitedNodes.insert(N))
540 // Otherwise, add all chain operands to the worklist.
541 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
542 if (N->getOperand(i).getValueType() == MVT::Other)
543 Worklist.push_back(N->getOperand(i).getNode());
545 // If this is a CopyToReg with a vreg dest, process it.
546 if (N->getOpcode() != ISD::CopyToReg)
549 unsigned DestReg = cast<RegisterSDNode>(N->getOperand(1))->getReg();
550 if (!TargetRegisterInfo::isVirtualRegister(DestReg))
553 // Ignore non-scalar or non-integer values.
554 SDValue Src = N->getOperand(2);
555 EVT SrcVT = Src.getValueType();
556 if (!SrcVT.isInteger() || SrcVT.isVector())
559 unsigned NumSignBits = CurDAG->ComputeNumSignBits(Src);
560 CurDAG->ComputeMaskedBits(Src, KnownZero, KnownOne);
561 FuncInfo->AddLiveOutRegInfo(DestReg, NumSignBits, KnownZero, KnownOne);
562 } while (!Worklist.empty());
565 void SelectionDAGISel::CodeGenAndEmitDAG() {
566 std::string GroupName;
567 if (TimePassesIsEnabled)
568 GroupName = "Instruction Selection and Scheduling";
569 std::string BlockName;
570 int BlockNumber = -1;
573 if (ViewDAGCombine1 || ViewLegalizeTypesDAGs || ViewLegalizeDAGs ||
574 ViewDAGCombine2 || ViewDAGCombineLT || ViewISelDAGs || ViewSchedDAGs ||
578 BlockNumber = FuncInfo->MBB->getNumber();
579 BlockName = MF->getName().str() + ":" +
580 FuncInfo->MBB->getBasicBlock()->getName().str();
582 DEBUG(dbgs() << "Initial selection DAG: BB#" << BlockNumber
583 << " '" << BlockName << "'\n"; CurDAG->dump());
585 if (ViewDAGCombine1) CurDAG->viewGraph("dag-combine1 input for " + BlockName);
587 // Run the DAG combiner in pre-legalize mode.
589 NamedRegionTimer T("DAG Combining 1", GroupName, TimePassesIsEnabled);
590 CurDAG->Combine(BeforeLegalizeTypes, *AA, OptLevel);
593 DEBUG(dbgs() << "Optimized lowered selection DAG: BB#" << BlockNumber
594 << " '" << BlockName << "'\n"; CurDAG->dump());
596 // Second step, hack on the DAG until it only uses operations and types that
597 // the target supports.
598 if (ViewLegalizeTypesDAGs) CurDAG->viewGraph("legalize-types input for " +
603 NamedRegionTimer T("Type Legalization", GroupName, TimePassesIsEnabled);
604 Changed = CurDAG->LegalizeTypes();
607 DEBUG(dbgs() << "Type-legalized selection DAG: BB#" << BlockNumber
608 << " '" << BlockName << "'\n"; CurDAG->dump());
611 if (ViewDAGCombineLT)
612 CurDAG->viewGraph("dag-combine-lt input for " + BlockName);
614 // Run the DAG combiner in post-type-legalize mode.
616 NamedRegionTimer T("DAG Combining after legalize types", GroupName,
617 TimePassesIsEnabled);
618 CurDAG->Combine(AfterLegalizeTypes, *AA, OptLevel);
621 DEBUG(dbgs() << "Optimized type-legalized selection DAG: BB#" << BlockNumber
622 << " '" << BlockName << "'\n"; CurDAG->dump());
626 NamedRegionTimer T("Vector Legalization", GroupName, TimePassesIsEnabled);
627 Changed = CurDAG->LegalizeVectors();
632 NamedRegionTimer T("Type Legalization 2", GroupName, TimePassesIsEnabled);
633 CurDAG->LegalizeTypes();
636 if (ViewDAGCombineLT)
637 CurDAG->viewGraph("dag-combine-lv input for " + BlockName);
639 // Run the DAG combiner in post-type-legalize mode.
641 NamedRegionTimer T("DAG Combining after legalize vectors", GroupName,
642 TimePassesIsEnabled);
643 CurDAG->Combine(AfterLegalizeVectorOps, *AA, OptLevel);
646 DEBUG(dbgs() << "Optimized vector-legalized selection DAG: BB#"
647 << BlockNumber << " '" << BlockName << "'\n"; CurDAG->dump());
650 if (ViewLegalizeDAGs) CurDAG->viewGraph("legalize input for " + BlockName);
653 NamedRegionTimer T("DAG Legalization", GroupName, TimePassesIsEnabled);
657 DEBUG(dbgs() << "Legalized selection DAG: BB#" << BlockNumber
658 << " '" << BlockName << "'\n"; CurDAG->dump());
660 if (ViewDAGCombine2) CurDAG->viewGraph("dag-combine2 input for " + BlockName);
662 // Run the DAG combiner in post-legalize mode.
664 NamedRegionTimer T("DAG Combining 2", GroupName, TimePassesIsEnabled);
665 CurDAG->Combine(AfterLegalizeDAG, *AA, OptLevel);
668 DEBUG(dbgs() << "Optimized legalized selection DAG: BB#" << BlockNumber
669 << " '" << BlockName << "'\n"; CurDAG->dump());
671 if (OptLevel != CodeGenOpt::None)
672 ComputeLiveOutVRegInfo();
674 if (ViewISelDAGs) CurDAG->viewGraph("isel input for " + BlockName);
676 // Third, instruction select all of the operations to machine code, adding the
677 // code to the MachineBasicBlock.
679 NamedRegionTimer T("Instruction Selection", GroupName, TimePassesIsEnabled);
680 DoInstructionSelection();
683 DEBUG(dbgs() << "Selected selection DAG: BB#" << BlockNumber
684 << " '" << BlockName << "'\n"; CurDAG->dump());
686 if (ViewSchedDAGs) CurDAG->viewGraph("scheduler input for " + BlockName);
688 // Schedule machine code.
689 ScheduleDAGSDNodes *Scheduler = CreateScheduler();
691 NamedRegionTimer T("Instruction Scheduling", GroupName,
692 TimePassesIsEnabled);
693 Scheduler->Run(CurDAG, FuncInfo->MBB);
696 if (ViewSUnitDAGs) Scheduler->viewGraph();
698 // Emit machine code to BB. This can change 'BB' to the last block being
700 MachineBasicBlock *FirstMBB = FuncInfo->MBB, *LastMBB;
702 NamedRegionTimer T("Instruction Creation", GroupName, TimePassesIsEnabled);
704 // FuncInfo->InsertPt is passed by reference and set to the end of the
705 // scheduled instructions.
706 LastMBB = FuncInfo->MBB = Scheduler->EmitSchedule(FuncInfo->InsertPt);
709 // If the block was split, make sure we update any references that are used to
710 // update PHI nodes later on.
711 if (FirstMBB != LastMBB)
712 SDB->UpdateSplitBlock(FirstMBB, LastMBB);
714 // Free the scheduler state.
716 NamedRegionTimer T("Instruction Scheduling Cleanup", GroupName,
717 TimePassesIsEnabled);
721 // Free the SelectionDAG state, now that we're finished with it.
726 /// ISelUpdater - helper class to handle updates of the instruction selection
728 class ISelUpdater : public SelectionDAG::DAGUpdateListener {
729 SelectionDAG::allnodes_iterator &ISelPosition;
731 ISelUpdater(SelectionDAG &DAG, SelectionDAG::allnodes_iterator &isp)
732 : SelectionDAG::DAGUpdateListener(DAG), ISelPosition(isp) {}
734 /// NodeDeleted - Handle nodes deleted from the graph. If the node being
735 /// deleted is the current ISelPosition node, update ISelPosition.
737 virtual void NodeDeleted(SDNode *N, SDNode *E) {
738 if (ISelPosition == SelectionDAG::allnodes_iterator(N))
742 } // end anonymous namespace
744 void SelectionDAGISel::DoInstructionSelection() {
745 DEBUG(errs() << "===== Instruction selection begins: BB#"
746 << FuncInfo->MBB->getNumber()
747 << " '" << FuncInfo->MBB->getName() << "'\n");
751 // Select target instructions for the DAG.
753 // Number all nodes with a topological order and set DAGSize.
754 DAGSize = CurDAG->AssignTopologicalOrder();
756 // Create a dummy node (which is not added to allnodes), that adds
757 // a reference to the root node, preventing it from being deleted,
758 // and tracking any changes of the root.
759 HandleSDNode Dummy(CurDAG->getRoot());
760 SelectionDAG::allnodes_iterator ISelPosition (CurDAG->getRoot().getNode());
763 // Make sure that ISelPosition gets properly updated when nodes are deleted
764 // in calls made from this function.
765 ISelUpdater ISU(*CurDAG, ISelPosition);
767 // The AllNodes list is now topological-sorted. Visit the
768 // nodes by starting at the end of the list (the root of the
769 // graph) and preceding back toward the beginning (the entry
771 while (ISelPosition != CurDAG->allnodes_begin()) {
772 SDNode *Node = --ISelPosition;
773 // Skip dead nodes. DAGCombiner is expected to eliminate all dead nodes,
774 // but there are currently some corner cases that it misses. Also, this
775 // makes it theoretically possible to disable the DAGCombiner.
776 if (Node->use_empty())
779 SDNode *ResNode = Select(Node);
781 // FIXME: This is pretty gross. 'Select' should be changed to not return
782 // anything at all and this code should be nuked with a tactical strike.
784 // If node should not be replaced, continue with the next one.
785 if (ResNode == Node || Node->getOpcode() == ISD::DELETED_NODE)
789 ReplaceUses(Node, ResNode);
791 // If after the replacement this node is not used any more,
792 // remove this dead node.
793 if (Node->use_empty()) // Don't delete EntryToken, etc.
794 CurDAG->RemoveDeadNode(Node);
797 CurDAG->setRoot(Dummy.getValue());
800 DEBUG(errs() << "===== Instruction selection ends:\n");
802 PostprocessISelDAG();
805 /// PrepareEHLandingPad - Emit an EH_LABEL, set up live-in registers, and
806 /// do other setup for EH landing-pad blocks.
807 void SelectionDAGISel::PrepareEHLandingPad() {
808 MachineBasicBlock *MBB = FuncInfo->MBB;
810 // Add a label to mark the beginning of the landing pad. Deletion of the
811 // landing pad can thus be detected via the MachineModuleInfo.
812 MCSymbol *Label = MF->getMMI().addLandingPad(MBB);
814 // Assign the call site to the landing pad's begin label.
815 MF->getMMI().setCallSiteLandingPad(Label, SDB->LPadToCallSiteMap[MBB]);
817 const MCInstrDesc &II = TM.getInstrInfo()->get(TargetOpcode::EH_LABEL);
818 BuildMI(*MBB, FuncInfo->InsertPt, SDB->getCurDebugLoc(), II)
821 // Mark exception register as live in.
822 unsigned Reg = TLI.getExceptionPointerRegister();
823 if (Reg) MBB->addLiveIn(Reg);
825 // Mark exception selector register as live in.
826 Reg = TLI.getExceptionSelectorRegister();
827 if (Reg) MBB->addLiveIn(Reg);
830 /// TryToFoldFastISelLoad - We're checking to see if we can fold the specified
831 /// load into the specified FoldInst. Note that we could have a sequence where
832 /// multiple LLVM IR instructions are folded into the same machineinstr. For
833 /// example we could have:
834 /// A: x = load i32 *P
835 /// B: y = icmp A, 42
838 /// In this scenario, LI is "A", and FoldInst is "C". We know about "B" (and
839 /// any other folded instructions) because it is between A and C.
841 /// If we succeed in folding the load into the operation, return true.
843 bool SelectionDAGISel::TryToFoldFastISelLoad(const LoadInst *LI,
844 const Instruction *FoldInst,
846 // We know that the load has a single use, but don't know what it is. If it
847 // isn't one of the folded instructions, then we can't succeed here. Handle
848 // this by scanning the single-use users of the load until we get to FoldInst.
849 unsigned MaxUsers = 6; // Don't scan down huge single-use chains of instrs.
851 const Instruction *TheUser = LI->use_back();
852 while (TheUser != FoldInst && // Scan up until we find FoldInst.
853 // Stay in the right block.
854 TheUser->getParent() == FoldInst->getParent() &&
855 --MaxUsers) { // Don't scan too far.
856 // If there are multiple or no uses of this instruction, then bail out.
857 if (!TheUser->hasOneUse())
860 TheUser = TheUser->use_back();
863 // If we didn't find the fold instruction, then we failed to collapse the
865 if (TheUser != FoldInst)
868 // Don't try to fold volatile loads. Target has to deal with alignment
870 if (LI->isVolatile()) return false;
872 // Figure out which vreg this is going into. If there is no assigned vreg yet
873 // then there actually was no reference to it. Perhaps the load is referenced
874 // by a dead instruction.
875 unsigned LoadReg = FastIS->getRegForValue(LI);
879 // Check to see what the uses of this vreg are. If it has no uses, or more
880 // than one use (at the machine instr level) then we can't fold it.
881 MachineRegisterInfo::reg_iterator RI = RegInfo->reg_begin(LoadReg);
882 if (RI == RegInfo->reg_end())
885 // See if there is exactly one use of the vreg. If there are multiple uses,
886 // then the instruction got lowered to multiple machine instructions or the
887 // use of the loaded value ended up being multiple operands of the result, in
888 // either case, we can't fold this.
889 MachineRegisterInfo::reg_iterator PostRI = RI; ++PostRI;
890 if (PostRI != RegInfo->reg_end())
893 assert(RI.getOperand().isUse() &&
894 "The only use of the vreg must be a use, we haven't emitted the def!");
896 MachineInstr *User = &*RI;
898 // Set the insertion point properly. Folding the load can cause generation of
899 // other random instructions (like sign extends) for addressing modes, make
900 // sure they get inserted in a logical place before the new instruction.
901 FuncInfo->InsertPt = User;
902 FuncInfo->MBB = User->getParent();
904 // Ask the target to try folding the load.
905 return FastIS->TryToFoldLoad(User, RI.getOperandNo(), LI);
908 /// isFoldedOrDeadInstruction - Return true if the specified instruction is
909 /// side-effect free and is either dead or folded into a generated instruction.
910 /// Return false if it needs to be emitted.
911 static bool isFoldedOrDeadInstruction(const Instruction *I,
912 FunctionLoweringInfo *FuncInfo) {
913 return !I->mayWriteToMemory() && // Side-effecting instructions aren't folded.
914 !isa<TerminatorInst>(I) && // Terminators aren't folded.
915 !isa<DbgInfoIntrinsic>(I) && // Debug instructions aren't folded.
916 !isa<LandingPadInst>(I) && // Landingpad instructions aren't folded.
917 !FuncInfo->isExportedInst(I); // Exported instrs must be computed.
921 // Collect per Instruction statistics for fast-isel misses. Only those
922 // instructions that cause the bail are accounted for. It does not account for
923 // instructions higher in the block. Thus, summing the per instructions stats
924 // will not add up to what is reported by NumFastIselFailures.
925 static void collectFailStats(const Instruction *I) {
926 switch (I->getOpcode()) {
927 default: assert (0 && "<Invalid operator> ");
930 case Instruction::Ret: NumFastIselFailRet++; return;
931 case Instruction::Br: NumFastIselFailBr++; return;
932 case Instruction::Switch: NumFastIselFailSwitch++; return;
933 case Instruction::IndirectBr: NumFastIselFailIndirectBr++; return;
934 case Instruction::Invoke: NumFastIselFailInvoke++; return;
935 case Instruction::Resume: NumFastIselFailResume++; return;
936 case Instruction::Unreachable: NumFastIselFailUnreachable++; return;
938 // Standard binary operators...
939 case Instruction::Add: NumFastIselFailAdd++; return;
940 case Instruction::FAdd: NumFastIselFailFAdd++; return;
941 case Instruction::Sub: NumFastIselFailSub++; return;
942 case Instruction::FSub: NumFastIselFailFSub++; return;
943 case Instruction::Mul: NumFastIselFailMul++; return;
944 case Instruction::FMul: NumFastIselFailFMul++; return;
945 case Instruction::UDiv: NumFastIselFailUDiv++; return;
946 case Instruction::SDiv: NumFastIselFailSDiv++; return;
947 case Instruction::FDiv: NumFastIselFailFDiv++; return;
948 case Instruction::URem: NumFastIselFailURem++; return;
949 case Instruction::SRem: NumFastIselFailSRem++; return;
950 case Instruction::FRem: NumFastIselFailFRem++; return;
952 // Logical operators...
953 case Instruction::And: NumFastIselFailAnd++; return;
954 case Instruction::Or: NumFastIselFailOr++; return;
955 case Instruction::Xor: NumFastIselFailXor++; return;
957 // Memory instructions...
958 case Instruction::Alloca: NumFastIselFailAlloca++; return;
959 case Instruction::Load: NumFastIselFailLoad++; return;
960 case Instruction::Store: NumFastIselFailStore++; return;
961 case Instruction::AtomicCmpXchg: NumFastIselFailAtomicCmpXchg++; return;
962 case Instruction::AtomicRMW: NumFastIselFailAtomicRMW++; return;
963 case Instruction::Fence: NumFastIselFailFence++; return;
964 case Instruction::GetElementPtr: NumFastIselFailGetElementPtr++; return;
966 // Convert instructions...
967 case Instruction::Trunc: NumFastIselFailTrunc++; return;
968 case Instruction::ZExt: NumFastIselFailZExt++; return;
969 case Instruction::SExt: NumFastIselFailSExt++; return;
970 case Instruction::FPTrunc: NumFastIselFailFPTrunc++; return;
971 case Instruction::FPExt: NumFastIselFailFPExt++; return;
972 case Instruction::FPToUI: NumFastIselFailFPToUI++; return;
973 case Instruction::FPToSI: NumFastIselFailFPToSI++; return;
974 case Instruction::UIToFP: NumFastIselFailUIToFP++; return;
975 case Instruction::SIToFP: NumFastIselFailSIToFP++; return;
976 case Instruction::IntToPtr: NumFastIselFailIntToPtr++; return;
977 case Instruction::PtrToInt: NumFastIselFailPtrToInt++; return;
978 case Instruction::BitCast: NumFastIselFailBitCast++; return;
980 // Other instructions...
981 case Instruction::ICmp: NumFastIselFailICmp++; return;
982 case Instruction::FCmp: NumFastIselFailFCmp++; return;
983 case Instruction::PHI: NumFastIselFailPHI++; return;
984 case Instruction::Select: NumFastIselFailSelect++; return;
985 case Instruction::Call: NumFastIselFailCall++; return;
986 case Instruction::Shl: NumFastIselFailShl++; return;
987 case Instruction::LShr: NumFastIselFailLShr++; return;
988 case Instruction::AShr: NumFastIselFailAShr++; return;
989 case Instruction::VAArg: NumFastIselFailVAArg++; return;
990 case Instruction::ExtractElement: NumFastIselFailExtractElement++; return;
991 case Instruction::InsertElement: NumFastIselFailInsertElement++; return;
992 case Instruction::ShuffleVector: NumFastIselFailShuffleVector++; return;
993 case Instruction::ExtractValue: NumFastIselFailExtractValue++; return;
994 case Instruction::InsertValue: NumFastIselFailInsertValue++; return;
995 case Instruction::LandingPad: NumFastIselFailLandingPad++; return;
1000 void SelectionDAGISel::SelectAllBasicBlocks(const Function &Fn) {
1001 // Initialize the Fast-ISel state, if needed.
1002 FastISel *FastIS = 0;
1003 if (TM.Options.EnableFastISel)
1004 FastIS = TLI.createFastISel(*FuncInfo, LibInfo);
1006 // Iterate over all basic blocks in the function.
1007 ReversePostOrderTraversal<const Function*> RPOT(&Fn);
1008 for (ReversePostOrderTraversal<const Function*>::rpo_iterator
1009 I = RPOT.begin(), E = RPOT.end(); I != E; ++I) {
1010 const BasicBlock *LLVMBB = *I;
1012 if (OptLevel != CodeGenOpt::None) {
1013 bool AllPredsVisited = true;
1014 for (const_pred_iterator PI = pred_begin(LLVMBB), PE = pred_end(LLVMBB);
1016 if (!FuncInfo->VisitedBBs.count(*PI)) {
1017 AllPredsVisited = false;
1022 if (AllPredsVisited) {
1023 for (BasicBlock::const_iterator I = LLVMBB->begin();
1024 const PHINode *PN = dyn_cast<PHINode>(I); ++I)
1025 FuncInfo->ComputePHILiveOutRegInfo(PN);
1027 for (BasicBlock::const_iterator I = LLVMBB->begin();
1028 const PHINode *PN = dyn_cast<PHINode>(I); ++I)
1029 FuncInfo->InvalidatePHILiveOutRegInfo(PN);
1032 FuncInfo->VisitedBBs.insert(LLVMBB);
1035 BasicBlock::const_iterator const Begin = LLVMBB->getFirstNonPHI();
1036 BasicBlock::const_iterator const End = LLVMBB->end();
1037 BasicBlock::const_iterator BI = End;
1039 FuncInfo->MBB = FuncInfo->MBBMap[LLVMBB];
1040 FuncInfo->InsertPt = FuncInfo->MBB->getFirstNonPHI();
1042 // Setup an EH landing-pad block.
1043 if (FuncInfo->MBB->isLandingPad())
1044 PrepareEHLandingPad();
1046 // Before doing SelectionDAG ISel, see if FastISel has been requested.
1048 FastIS->startNewBlock();
1050 // Emit code for any incoming arguments. This must happen before
1051 // beginning FastISel on the entry block.
1052 if (LLVMBB == &Fn.getEntryBlock()) {
1053 // Lower any arguments needed in this block if this is the entry block.
1054 if (!FastIS->LowerArguments()) {
1055 // Fast isel failed to lower these arguments
1056 if (EnableFastISelAbortArgs)
1057 llvm_unreachable("FastISel didn't lower all arguments");
1059 // Use SelectionDAG argument lowering
1061 CurDAG->setRoot(SDB->getControlRoot());
1063 CodeGenAndEmitDAG();
1066 // If we inserted any instructions at the beginning, make a note of
1067 // where they are, so we can be sure to emit subsequent instructions
1069 if (FuncInfo->InsertPt != FuncInfo->MBB->begin())
1070 FastIS->setLastLocalValue(llvm::prior(FuncInfo->InsertPt));
1072 FastIS->setLastLocalValue(0);
1075 unsigned NumFastIselRemaining = std::distance(Begin, End);
1076 // Do FastISel on as many instructions as possible.
1077 for (; BI != Begin; --BI) {
1078 const Instruction *Inst = llvm::prior(BI);
1080 // If we no longer require this instruction, skip it.
1081 if (isFoldedOrDeadInstruction(Inst, FuncInfo)) {
1082 --NumFastIselRemaining;
1086 // Bottom-up: reset the insert pos at the top, after any local-value
1088 FastIS->recomputeInsertPt();
1090 // Try to select the instruction with FastISel.
1091 if (FastIS->SelectInstruction(Inst)) {
1092 --NumFastIselRemaining;
1093 DEBUG(++NumFastIselSuccess);
1094 // If fast isel succeeded, skip over all the folded instructions, and
1095 // then see if there is a load right before the selected instructions.
1096 // Try to fold the load if so.
1097 const Instruction *BeforeInst = Inst;
1098 while (BeforeInst != Begin) {
1099 BeforeInst = llvm::prior(BasicBlock::const_iterator(BeforeInst));
1100 if (!isFoldedOrDeadInstruction(BeforeInst, FuncInfo))
1103 if (BeforeInst != Inst && isa<LoadInst>(BeforeInst) &&
1104 BeforeInst->hasOneUse() &&
1105 TryToFoldFastISelLoad(cast<LoadInst>(BeforeInst), Inst, FastIS)) {
1106 // If we succeeded, don't re-select the load.
1107 BI = llvm::next(BasicBlock::const_iterator(BeforeInst));
1108 --NumFastIselRemaining;
1109 DEBUG(++NumFastIselSuccess);
1115 if (EnableFastISelVerbose2)
1116 collectFailStats(Inst);
1119 // Then handle certain instructions as single-LLVM-Instruction blocks.
1120 if (isa<CallInst>(Inst)) {
1122 if (EnableFastISelVerbose || EnableFastISelAbort) {
1123 dbgs() << "FastISel missed call: ";
1127 if (!Inst->getType()->isVoidTy() && !Inst->use_empty()) {
1128 unsigned &R = FuncInfo->ValueMap[Inst];
1130 R = FuncInfo->CreateRegs(Inst->getType());
1133 bool HadTailCall = false;
1134 MachineBasicBlock::iterator SavedInsertPt = FuncInfo->InsertPt;
1135 SelectBasicBlock(Inst, BI, HadTailCall);
1137 // If the call was emitted as a tail call, we're done with the block.
1138 // We also need to delete any previously emitted instructions.
1140 FastIS->removeDeadCode(SavedInsertPt, FuncInfo->MBB->end());
1145 // Recompute NumFastIselRemaining as Selection DAG instruction
1146 // selection may have handled the call, input args, etc.
1147 unsigned RemainingNow = std::distance(Begin, BI);
1148 (void) RemainingNow;
1149 DEBUG(NumFastIselFailures += NumFastIselRemaining - RemainingNow);
1150 DEBUG(NumFastIselRemaining = RemainingNow);
1154 if (isa<TerminatorInst>(Inst) && !isa<BranchInst>(Inst)) {
1155 // Don't abort, and use a different message for terminator misses.
1156 DEBUG(NumFastIselFailures += NumFastIselRemaining);
1157 if (EnableFastISelVerbose || EnableFastISelAbort) {
1158 dbgs() << "FastISel missed terminator: ";
1162 DEBUG(NumFastIselFailures += NumFastIselRemaining);
1163 if (EnableFastISelVerbose || EnableFastISelAbort) {
1164 dbgs() << "FastISel miss: ";
1167 if (EnableFastISelAbort)
1168 // The "fast" selector couldn't handle something and bailed.
1169 // For the purpose of debugging, just abort.
1170 llvm_unreachable("FastISel didn't select the entire block");
1175 FastIS->recomputeInsertPt();
1177 // Lower any arguments needed in this block if this is the entry block.
1178 if (LLVMBB == &Fn.getEntryBlock())
1185 ++NumFastIselBlocks;
1188 // Run SelectionDAG instruction selection on the remainder of the block
1189 // not handled by FastISel. If FastISel is not run, this is the entire
1192 SelectBasicBlock(Begin, BI, HadTailCall);
1196 FuncInfo->PHINodesToUpdate.clear();
1200 SDB->clearDanglingDebugInfo();
1204 SelectionDAGISel::FinishBasicBlock() {
1206 DEBUG(dbgs() << "Total amount of phi nodes to update: "
1207 << FuncInfo->PHINodesToUpdate.size() << "\n";
1208 for (unsigned i = 0, e = FuncInfo->PHINodesToUpdate.size(); i != e; ++i)
1209 dbgs() << "Node " << i << " : ("
1210 << FuncInfo->PHINodesToUpdate[i].first
1211 << ", " << FuncInfo->PHINodesToUpdate[i].second << ")\n");
1213 // Next, now that we know what the last MBB the LLVM BB expanded is, update
1214 // PHI nodes in successors.
1215 if (SDB->SwitchCases.empty() &&
1216 SDB->JTCases.empty() &&
1217 SDB->BitTestCases.empty()) {
1218 for (unsigned i = 0, e = FuncInfo->PHINodesToUpdate.size(); i != e; ++i) {
1219 MachineInstrBuilder PHI(*MF, FuncInfo->PHINodesToUpdate[i].first);
1220 assert(PHI->isPHI() &&
1221 "This is not a machine PHI node that we are updating!");
1222 if (!FuncInfo->MBB->isSuccessor(PHI->getParent()))
1224 PHI.addReg(FuncInfo->PHINodesToUpdate[i].second).addMBB(FuncInfo->MBB);
1229 for (unsigned i = 0, e = SDB->BitTestCases.size(); i != e; ++i) {
1230 // Lower header first, if it wasn't already lowered
1231 if (!SDB->BitTestCases[i].Emitted) {
1232 // Set the current basic block to the mbb we wish to insert the code into
1233 FuncInfo->MBB = SDB->BitTestCases[i].Parent;
1234 FuncInfo->InsertPt = FuncInfo->MBB->end();
1236 SDB->visitBitTestHeader(SDB->BitTestCases[i], FuncInfo->MBB);
1237 CurDAG->setRoot(SDB->getRoot());
1239 CodeGenAndEmitDAG();
1242 uint32_t UnhandledWeight = 0;
1243 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size(); j != ej; ++j)
1244 UnhandledWeight += SDB->BitTestCases[i].Cases[j].ExtraWeight;
1246 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size(); j != ej; ++j) {
1247 UnhandledWeight -= SDB->BitTestCases[i].Cases[j].ExtraWeight;
1248 // Set the current basic block to the mbb we wish to insert the code into
1249 FuncInfo->MBB = SDB->BitTestCases[i].Cases[j].ThisBB;
1250 FuncInfo->InsertPt = FuncInfo->MBB->end();
1253 SDB->visitBitTestCase(SDB->BitTestCases[i],
1254 SDB->BitTestCases[i].Cases[j+1].ThisBB,
1256 SDB->BitTestCases[i].Reg,
1257 SDB->BitTestCases[i].Cases[j],
1260 SDB->visitBitTestCase(SDB->BitTestCases[i],
1261 SDB->BitTestCases[i].Default,
1263 SDB->BitTestCases[i].Reg,
1264 SDB->BitTestCases[i].Cases[j],
1268 CurDAG->setRoot(SDB->getRoot());
1270 CodeGenAndEmitDAG();
1274 for (unsigned pi = 0, pe = FuncInfo->PHINodesToUpdate.size();
1276 MachineInstrBuilder PHI(*MF, FuncInfo->PHINodesToUpdate[pi].first);
1277 MachineBasicBlock *PHIBB = PHI->getParent();
1278 assert(PHI->isPHI() &&
1279 "This is not a machine PHI node that we are updating!");
1280 // This is "default" BB. We have two jumps to it. From "header" BB and
1281 // from last "case" BB.
1282 if (PHIBB == SDB->BitTestCases[i].Default)
1283 PHI.addReg(FuncInfo->PHINodesToUpdate[pi].second)
1284 .addMBB(SDB->BitTestCases[i].Parent)
1285 .addReg(FuncInfo->PHINodesToUpdate[pi].second)
1286 .addMBB(SDB->BitTestCases[i].Cases.back().ThisBB);
1287 // One of "cases" BB.
1288 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size();
1290 MachineBasicBlock* cBB = SDB->BitTestCases[i].Cases[j].ThisBB;
1291 if (cBB->isSuccessor(PHIBB))
1292 PHI.addReg(FuncInfo->PHINodesToUpdate[pi].second).addMBB(cBB);
1296 SDB->BitTestCases.clear();
1298 // If the JumpTable record is filled in, then we need to emit a jump table.
1299 // Updating the PHI nodes is tricky in this case, since we need to determine
1300 // whether the PHI is a successor of the range check MBB or the jump table MBB
1301 for (unsigned i = 0, e = SDB->JTCases.size(); i != e; ++i) {
1302 // Lower header first, if it wasn't already lowered
1303 if (!SDB->JTCases[i].first.Emitted) {
1304 // Set the current basic block to the mbb we wish to insert the code into
1305 FuncInfo->MBB = SDB->JTCases[i].first.HeaderBB;
1306 FuncInfo->InsertPt = FuncInfo->MBB->end();
1308 SDB->visitJumpTableHeader(SDB->JTCases[i].second, SDB->JTCases[i].first,
1310 CurDAG->setRoot(SDB->getRoot());
1312 CodeGenAndEmitDAG();
1315 // Set the current basic block to the mbb we wish to insert the code into
1316 FuncInfo->MBB = SDB->JTCases[i].second.MBB;
1317 FuncInfo->InsertPt = FuncInfo->MBB->end();
1319 SDB->visitJumpTable(SDB->JTCases[i].second);
1320 CurDAG->setRoot(SDB->getRoot());
1322 CodeGenAndEmitDAG();
1325 for (unsigned pi = 0, pe = FuncInfo->PHINodesToUpdate.size();
1327 MachineInstrBuilder PHI(*MF, FuncInfo->PHINodesToUpdate[pi].first);
1328 MachineBasicBlock *PHIBB = PHI->getParent();
1329 assert(PHI->isPHI() &&
1330 "This is not a machine PHI node that we are updating!");
1331 // "default" BB. We can go there only from header BB.
1332 if (PHIBB == SDB->JTCases[i].second.Default)
1333 PHI.addReg(FuncInfo->PHINodesToUpdate[pi].second)
1334 .addMBB(SDB->JTCases[i].first.HeaderBB);
1335 // JT BB. Just iterate over successors here
1336 if (FuncInfo->MBB->isSuccessor(PHIBB))
1337 PHI.addReg(FuncInfo->PHINodesToUpdate[pi].second).addMBB(FuncInfo->MBB);
1340 SDB->JTCases.clear();
1342 // If the switch block involved a branch to one of the actual successors, we
1343 // need to update PHI nodes in that block.
1344 for (unsigned i = 0, e = FuncInfo->PHINodesToUpdate.size(); i != e; ++i) {
1345 MachineInstrBuilder PHI(*MF, FuncInfo->PHINodesToUpdate[i].first);
1346 assert(PHI->isPHI() &&
1347 "This is not a machine PHI node that we are updating!");
1348 if (FuncInfo->MBB->isSuccessor(PHI->getParent()))
1349 PHI.addReg(FuncInfo->PHINodesToUpdate[i].second).addMBB(FuncInfo->MBB);
1352 // If we generated any switch lowering information, build and codegen any
1353 // additional DAGs necessary.
1354 for (unsigned i = 0, e = SDB->SwitchCases.size(); i != e; ++i) {
1355 // Set the current basic block to the mbb we wish to insert the code into
1356 FuncInfo->MBB = SDB->SwitchCases[i].ThisBB;
1357 FuncInfo->InsertPt = FuncInfo->MBB->end();
1359 // Determine the unique successors.
1360 SmallVector<MachineBasicBlock *, 2> Succs;
1361 Succs.push_back(SDB->SwitchCases[i].TrueBB);
1362 if (SDB->SwitchCases[i].TrueBB != SDB->SwitchCases[i].FalseBB)
1363 Succs.push_back(SDB->SwitchCases[i].FalseBB);
1365 // Emit the code. Note that this could result in FuncInfo->MBB being split.
1366 SDB->visitSwitchCase(SDB->SwitchCases[i], FuncInfo->MBB);
1367 CurDAG->setRoot(SDB->getRoot());
1369 CodeGenAndEmitDAG();
1371 // Remember the last block, now that any splitting is done, for use in
1372 // populating PHI nodes in successors.
1373 MachineBasicBlock *ThisBB = FuncInfo->MBB;
1375 // Handle any PHI nodes in successors of this chunk, as if we were coming
1376 // from the original BB before switch expansion. Note that PHI nodes can
1377 // occur multiple times in PHINodesToUpdate. We have to be very careful to
1378 // handle them the right number of times.
1379 for (unsigned i = 0, e = Succs.size(); i != e; ++i) {
1380 FuncInfo->MBB = Succs[i];
1381 FuncInfo->InsertPt = FuncInfo->MBB->end();
1382 // FuncInfo->MBB may have been removed from the CFG if a branch was
1384 if (ThisBB->isSuccessor(FuncInfo->MBB)) {
1385 for (MachineBasicBlock::iterator
1386 MBBI = FuncInfo->MBB->begin(), MBBE = FuncInfo->MBB->end();
1387 MBBI != MBBE && MBBI->isPHI(); ++MBBI) {
1388 MachineInstrBuilder PHI(*MF, MBBI);
1389 // This value for this PHI node is recorded in PHINodesToUpdate.
1390 for (unsigned pn = 0; ; ++pn) {
1391 assert(pn != FuncInfo->PHINodesToUpdate.size() &&
1392 "Didn't find PHI entry!");
1393 if (FuncInfo->PHINodesToUpdate[pn].first == PHI) {
1394 PHI.addReg(FuncInfo->PHINodesToUpdate[pn].second).addMBB(ThisBB);
1402 SDB->SwitchCases.clear();
1406 /// Create the scheduler. If a specific scheduler was specified
1407 /// via the SchedulerRegistry, use it, otherwise select the
1408 /// one preferred by the target.
1410 ScheduleDAGSDNodes *SelectionDAGISel::CreateScheduler() {
1411 RegisterScheduler::FunctionPassCtor Ctor = RegisterScheduler::getDefault();
1415 RegisterScheduler::setDefault(Ctor);
1418 return Ctor(this, OptLevel);
1421 //===----------------------------------------------------------------------===//
1422 // Helper functions used by the generated instruction selector.
1423 //===----------------------------------------------------------------------===//
1424 // Calls to these methods are generated by tblgen.
1426 /// CheckAndMask - The isel is trying to match something like (and X, 255). If
1427 /// the dag combiner simplified the 255, we still want to match. RHS is the
1428 /// actual value in the DAG on the RHS of an AND, and DesiredMaskS is the value
1429 /// specified in the .td file (e.g. 255).
1430 bool SelectionDAGISel::CheckAndMask(SDValue LHS, ConstantSDNode *RHS,
1431 int64_t DesiredMaskS) const {
1432 const APInt &ActualMask = RHS->getAPIntValue();
1433 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS);
1435 // If the actual mask exactly matches, success!
1436 if (ActualMask == DesiredMask)
1439 // If the actual AND mask is allowing unallowed bits, this doesn't match.
1440 if (ActualMask.intersects(~DesiredMask))
1443 // Otherwise, the DAG Combiner may have proven that the value coming in is
1444 // either already zero or is not demanded. Check for known zero input bits.
1445 APInt NeededMask = DesiredMask & ~ActualMask;
1446 if (CurDAG->MaskedValueIsZero(LHS, NeededMask))
1449 // TODO: check to see if missing bits are just not demanded.
1451 // Otherwise, this pattern doesn't match.
1455 /// CheckOrMask - The isel is trying to match something like (or X, 255). If
1456 /// the dag combiner simplified the 255, we still want to match. RHS is the
1457 /// actual value in the DAG on the RHS of an OR, and DesiredMaskS is the value
1458 /// specified in the .td file (e.g. 255).
1459 bool SelectionDAGISel::CheckOrMask(SDValue LHS, ConstantSDNode *RHS,
1460 int64_t DesiredMaskS) const {
1461 const APInt &ActualMask = RHS->getAPIntValue();
1462 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS);
1464 // If the actual mask exactly matches, success!
1465 if (ActualMask == DesiredMask)
1468 // If the actual AND mask is allowing unallowed bits, this doesn't match.
1469 if (ActualMask.intersects(~DesiredMask))
1472 // Otherwise, the DAG Combiner may have proven that the value coming in is
1473 // either already zero or is not demanded. Check for known zero input bits.
1474 APInt NeededMask = DesiredMask & ~ActualMask;
1476 APInt KnownZero, KnownOne;
1477 CurDAG->ComputeMaskedBits(LHS, KnownZero, KnownOne);
1479 // If all the missing bits in the or are already known to be set, match!
1480 if ((NeededMask & KnownOne) == NeededMask)
1483 // TODO: check to see if missing bits are just not demanded.
1485 // Otherwise, this pattern doesn't match.
1490 /// SelectInlineAsmMemoryOperands - Calls to this are automatically generated
1491 /// by tblgen. Others should not call it.
1492 void SelectionDAGISel::
1493 SelectInlineAsmMemoryOperands(std::vector<SDValue> &Ops) {
1494 std::vector<SDValue> InOps;
1495 std::swap(InOps, Ops);
1497 Ops.push_back(InOps[InlineAsm::Op_InputChain]); // 0
1498 Ops.push_back(InOps[InlineAsm::Op_AsmString]); // 1
1499 Ops.push_back(InOps[InlineAsm::Op_MDNode]); // 2, !srcloc
1500 Ops.push_back(InOps[InlineAsm::Op_ExtraInfo]); // 3 (SideEffect, AlignStack)
1502 unsigned i = InlineAsm::Op_FirstOperand, e = InOps.size();
1503 if (InOps[e-1].getValueType() == MVT::Glue)
1504 --e; // Don't process a glue operand if it is here.
1507 unsigned Flags = cast<ConstantSDNode>(InOps[i])->getZExtValue();
1508 if (!InlineAsm::isMemKind(Flags)) {
1509 // Just skip over this operand, copying the operands verbatim.
1510 Ops.insert(Ops.end(), InOps.begin()+i,
1511 InOps.begin()+i+InlineAsm::getNumOperandRegisters(Flags) + 1);
1512 i += InlineAsm::getNumOperandRegisters(Flags) + 1;
1514 assert(InlineAsm::getNumOperandRegisters(Flags) == 1 &&
1515 "Memory operand with multiple values?");
1516 // Otherwise, this is a memory operand. Ask the target to select it.
1517 std::vector<SDValue> SelOps;
1518 if (SelectInlineAsmMemoryOperand(InOps[i+1], 'm', SelOps))
1519 report_fatal_error("Could not match memory address. Inline asm"
1522 // Add this to the output node.
1524 InlineAsm::getFlagWord(InlineAsm::Kind_Mem, SelOps.size());
1525 Ops.push_back(CurDAG->getTargetConstant(NewFlags, MVT::i32));
1526 Ops.insert(Ops.end(), SelOps.begin(), SelOps.end());
1531 // Add the glue input back if present.
1532 if (e != InOps.size())
1533 Ops.push_back(InOps.back());
1536 /// findGlueUse - Return use of MVT::Glue value produced by the specified
1539 static SDNode *findGlueUse(SDNode *N) {
1540 unsigned FlagResNo = N->getNumValues()-1;
1541 for (SDNode::use_iterator I = N->use_begin(), E = N->use_end(); I != E; ++I) {
1542 SDUse &Use = I.getUse();
1543 if (Use.getResNo() == FlagResNo)
1544 return Use.getUser();
1549 /// findNonImmUse - Return true if "Use" is a non-immediate use of "Def".
1550 /// This function recursively traverses up the operand chain, ignoring
1552 static bool findNonImmUse(SDNode *Use, SDNode* Def, SDNode *ImmedUse,
1553 SDNode *Root, SmallPtrSet<SDNode*, 16> &Visited,
1554 bool IgnoreChains) {
1555 // The NodeID's are given uniques ID's where a node ID is guaranteed to be
1556 // greater than all of its (recursive) operands. If we scan to a point where
1557 // 'use' is smaller than the node we're scanning for, then we know we will
1560 // The Use may be -1 (unassigned) if it is a newly allocated node. This can
1561 // happen because we scan down to newly selected nodes in the case of glue
1563 if ((Use->getNodeId() < Def->getNodeId() && Use->getNodeId() != -1))
1566 // Don't revisit nodes if we already scanned it and didn't fail, we know we
1567 // won't fail if we scan it again.
1568 if (!Visited.insert(Use))
1571 for (unsigned i = 0, e = Use->getNumOperands(); i != e; ++i) {
1572 // Ignore chain uses, they are validated by HandleMergeInputChains.
1573 if (Use->getOperand(i).getValueType() == MVT::Other && IgnoreChains)
1576 SDNode *N = Use->getOperand(i).getNode();
1578 if (Use == ImmedUse || Use == Root)
1579 continue; // We are not looking for immediate use.
1584 // Traverse up the operand chain.
1585 if (findNonImmUse(N, Def, ImmedUse, Root, Visited, IgnoreChains))
1591 /// IsProfitableToFold - Returns true if it's profitable to fold the specific
1592 /// operand node N of U during instruction selection that starts at Root.
1593 bool SelectionDAGISel::IsProfitableToFold(SDValue N, SDNode *U,
1594 SDNode *Root) const {
1595 if (OptLevel == CodeGenOpt::None) return false;
1596 return N.hasOneUse();
1599 /// IsLegalToFold - Returns true if the specific operand node N of
1600 /// U can be folded during instruction selection that starts at Root.
1601 bool SelectionDAGISel::IsLegalToFold(SDValue N, SDNode *U, SDNode *Root,
1602 CodeGenOpt::Level OptLevel,
1603 bool IgnoreChains) {
1604 if (OptLevel == CodeGenOpt::None) return false;
1606 // If Root use can somehow reach N through a path that that doesn't contain
1607 // U then folding N would create a cycle. e.g. In the following
1608 // diagram, Root can reach N through X. If N is folded into into Root, then
1609 // X is both a predecessor and a successor of U.
1620 // * indicates nodes to be folded together.
1622 // If Root produces glue, then it gets (even more) interesting. Since it
1623 // will be "glued" together with its glue use in the scheduler, we need to
1624 // check if it might reach N.
1643 // If GU (glue use) indirectly reaches N (the load), and Root folds N
1644 // (call it Fold), then X is a predecessor of GU and a successor of
1645 // Fold. But since Fold and GU are glued together, this will create
1646 // a cycle in the scheduling graph.
1648 // If the node has glue, walk down the graph to the "lowest" node in the
1650 EVT VT = Root->getValueType(Root->getNumValues()-1);
1651 while (VT == MVT::Glue) {
1652 SDNode *GU = findGlueUse(Root);
1656 VT = Root->getValueType(Root->getNumValues()-1);
1658 // If our query node has a glue result with a use, we've walked up it. If
1659 // the user (which has already been selected) has a chain or indirectly uses
1660 // the chain, our WalkChainUsers predicate will not consider it. Because of
1661 // this, we cannot ignore chains in this predicate.
1662 IgnoreChains = false;
1666 SmallPtrSet<SDNode*, 16> Visited;
1667 return !findNonImmUse(Root, N.getNode(), U, Root, Visited, IgnoreChains);
1670 SDNode *SelectionDAGISel::Select_INLINEASM(SDNode *N) {
1671 std::vector<SDValue> Ops(N->op_begin(), N->op_end());
1672 SelectInlineAsmMemoryOperands(Ops);
1674 EVT VTs[] = { MVT::Other, MVT::Glue };
1675 SDValue New = CurDAG->getNode(ISD::INLINEASM, N->getDebugLoc(),
1676 VTs, &Ops[0], Ops.size());
1678 return New.getNode();
1681 SDNode *SelectionDAGISel::Select_UNDEF(SDNode *N) {
1682 return CurDAG->SelectNodeTo(N, TargetOpcode::IMPLICIT_DEF,N->getValueType(0));
1685 /// GetVBR - decode a vbr encoding whose top bit is set.
1686 LLVM_ATTRIBUTE_ALWAYS_INLINE static uint64_t
1687 GetVBR(uint64_t Val, const unsigned char *MatcherTable, unsigned &Idx) {
1688 assert(Val >= 128 && "Not a VBR");
1689 Val &= 127; // Remove first vbr bit.
1694 NextBits = MatcherTable[Idx++];
1695 Val |= (NextBits&127) << Shift;
1697 } while (NextBits & 128);
1703 /// UpdateChainsAndGlue - When a match is complete, this method updates uses of
1704 /// interior glue and chain results to use the new glue and chain results.
1705 void SelectionDAGISel::
1706 UpdateChainsAndGlue(SDNode *NodeToMatch, SDValue InputChain,
1707 const SmallVectorImpl<SDNode*> &ChainNodesMatched,
1709 const SmallVectorImpl<SDNode*> &GlueResultNodesMatched,
1710 bool isMorphNodeTo) {
1711 SmallVector<SDNode*, 4> NowDeadNodes;
1713 // Now that all the normal results are replaced, we replace the chain and
1714 // glue results if present.
1715 if (!ChainNodesMatched.empty()) {
1716 assert(InputChain.getNode() != 0 &&
1717 "Matched input chains but didn't produce a chain");
1718 // Loop over all of the nodes we matched that produced a chain result.
1719 // Replace all the chain results with the final chain we ended up with.
1720 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) {
1721 SDNode *ChainNode = ChainNodesMatched[i];
1723 // If this node was already deleted, don't look at it.
1724 if (ChainNode->getOpcode() == ISD::DELETED_NODE)
1727 // Don't replace the results of the root node if we're doing a
1729 if (ChainNode == NodeToMatch && isMorphNodeTo)
1732 SDValue ChainVal = SDValue(ChainNode, ChainNode->getNumValues()-1);
1733 if (ChainVal.getValueType() == MVT::Glue)
1734 ChainVal = ChainVal.getValue(ChainVal->getNumValues()-2);
1735 assert(ChainVal.getValueType() == MVT::Other && "Not a chain?");
1736 CurDAG->ReplaceAllUsesOfValueWith(ChainVal, InputChain);
1738 // If the node became dead and we haven't already seen it, delete it.
1739 if (ChainNode->use_empty() &&
1740 !std::count(NowDeadNodes.begin(), NowDeadNodes.end(), ChainNode))
1741 NowDeadNodes.push_back(ChainNode);
1745 // If the result produces glue, update any glue results in the matched
1746 // pattern with the glue result.
1747 if (InputGlue.getNode() != 0) {
1748 // Handle any interior nodes explicitly marked.
1749 for (unsigned i = 0, e = GlueResultNodesMatched.size(); i != e; ++i) {
1750 SDNode *FRN = GlueResultNodesMatched[i];
1752 // If this node was already deleted, don't look at it.
1753 if (FRN->getOpcode() == ISD::DELETED_NODE)
1756 assert(FRN->getValueType(FRN->getNumValues()-1) == MVT::Glue &&
1757 "Doesn't have a glue result");
1758 CurDAG->ReplaceAllUsesOfValueWith(SDValue(FRN, FRN->getNumValues()-1),
1761 // If the node became dead and we haven't already seen it, delete it.
1762 if (FRN->use_empty() &&
1763 !std::count(NowDeadNodes.begin(), NowDeadNodes.end(), FRN))
1764 NowDeadNodes.push_back(FRN);
1768 if (!NowDeadNodes.empty())
1769 CurDAG->RemoveDeadNodes(NowDeadNodes);
1771 DEBUG(errs() << "ISEL: Match complete!\n");
1777 CR_LeadsToInteriorNode
1780 /// WalkChainUsers - Walk down the users of the specified chained node that is
1781 /// part of the pattern we're matching, looking at all of the users we find.
1782 /// This determines whether something is an interior node, whether we have a
1783 /// non-pattern node in between two pattern nodes (which prevent folding because
1784 /// it would induce a cycle) and whether we have a TokenFactor node sandwiched
1785 /// between pattern nodes (in which case the TF becomes part of the pattern).
1787 /// The walk we do here is guaranteed to be small because we quickly get down to
1788 /// already selected nodes "below" us.
1790 WalkChainUsers(const SDNode *ChainedNode,
1791 SmallVectorImpl<SDNode*> &ChainedNodesInPattern,
1792 SmallVectorImpl<SDNode*> &InteriorChainedNodes) {
1793 ChainResult Result = CR_Simple;
1795 for (SDNode::use_iterator UI = ChainedNode->use_begin(),
1796 E = ChainedNode->use_end(); UI != E; ++UI) {
1797 // Make sure the use is of the chain, not some other value we produce.
1798 if (UI.getUse().getValueType() != MVT::Other) continue;
1802 // If we see an already-selected machine node, then we've gone beyond the
1803 // pattern that we're selecting down into the already selected chunk of the
1805 if (User->isMachineOpcode() ||
1806 User->getOpcode() == ISD::HANDLENODE) // Root of the graph.
1809 unsigned UserOpcode = User->getOpcode();
1810 if (UserOpcode == ISD::CopyToReg ||
1811 UserOpcode == ISD::CopyFromReg ||
1812 UserOpcode == ISD::INLINEASM ||
1813 UserOpcode == ISD::EH_LABEL ||
1814 UserOpcode == ISD::LIFETIME_START ||
1815 UserOpcode == ISD::LIFETIME_END) {
1816 // If their node ID got reset to -1 then they've already been selected.
1817 // Treat them like a MachineOpcode.
1818 if (User->getNodeId() == -1)
1822 // If we have a TokenFactor, we handle it specially.
1823 if (User->getOpcode() != ISD::TokenFactor) {
1824 // If the node isn't a token factor and isn't part of our pattern, then it
1825 // must be a random chained node in between two nodes we're selecting.
1826 // This happens when we have something like:
1831 // Because we structurally match the load/store as a read/modify/write,
1832 // but the call is chained between them. We cannot fold in this case
1833 // because it would induce a cycle in the graph.
1834 if (!std::count(ChainedNodesInPattern.begin(),
1835 ChainedNodesInPattern.end(), User))
1836 return CR_InducesCycle;
1838 // Otherwise we found a node that is part of our pattern. For example in:
1842 // This would happen when we're scanning down from the load and see the
1843 // store as a user. Record that there is a use of ChainedNode that is
1844 // part of the pattern and keep scanning uses.
1845 Result = CR_LeadsToInteriorNode;
1846 InteriorChainedNodes.push_back(User);
1850 // If we found a TokenFactor, there are two cases to consider: first if the
1851 // TokenFactor is just hanging "below" the pattern we're matching (i.e. no
1852 // uses of the TF are in our pattern) we just want to ignore it. Second,
1853 // the TokenFactor can be sandwiched in between two chained nodes, like so:
1859 // | \ DAG's like cheese
1862 // [TokenFactor] [Op]
1869 // In this case, the TokenFactor becomes part of our match and we rewrite it
1870 // as a new TokenFactor.
1872 // To distinguish these two cases, do a recursive walk down the uses.
1873 switch (WalkChainUsers(User, ChainedNodesInPattern, InteriorChainedNodes)) {
1875 // If the uses of the TokenFactor are just already-selected nodes, ignore
1876 // it, it is "below" our pattern.
1878 case CR_InducesCycle:
1879 // If the uses of the TokenFactor lead to nodes that are not part of our
1880 // pattern that are not selected, folding would turn this into a cycle,
1882 return CR_InducesCycle;
1883 case CR_LeadsToInteriorNode:
1884 break; // Otherwise, keep processing.
1887 // Okay, we know we're in the interesting interior case. The TokenFactor
1888 // is now going to be considered part of the pattern so that we rewrite its
1889 // uses (it may have uses that are not part of the pattern) with the
1890 // ultimate chain result of the generated code. We will also add its chain
1891 // inputs as inputs to the ultimate TokenFactor we create.
1892 Result = CR_LeadsToInteriorNode;
1893 ChainedNodesInPattern.push_back(User);
1894 InteriorChainedNodes.push_back(User);
1901 /// HandleMergeInputChains - This implements the OPC_EmitMergeInputChains
1902 /// operation for when the pattern matched at least one node with a chains. The
1903 /// input vector contains a list of all of the chained nodes that we match. We
1904 /// must determine if this is a valid thing to cover (i.e. matching it won't
1905 /// induce cycles in the DAG) and if so, creating a TokenFactor node. that will
1906 /// be used as the input node chain for the generated nodes.
1908 HandleMergeInputChains(SmallVectorImpl<SDNode*> &ChainNodesMatched,
1909 SelectionDAG *CurDAG) {
1910 // Walk all of the chained nodes we've matched, recursively scanning down the
1911 // users of the chain result. This adds any TokenFactor nodes that are caught
1912 // in between chained nodes to the chained and interior nodes list.
1913 SmallVector<SDNode*, 3> InteriorChainedNodes;
1914 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) {
1915 if (WalkChainUsers(ChainNodesMatched[i], ChainNodesMatched,
1916 InteriorChainedNodes) == CR_InducesCycle)
1917 return SDValue(); // Would induce a cycle.
1920 // Okay, we have walked all the matched nodes and collected TokenFactor nodes
1921 // that we are interested in. Form our input TokenFactor node.
1922 SmallVector<SDValue, 3> InputChains;
1923 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) {
1924 // Add the input chain of this node to the InputChains list (which will be
1925 // the operands of the generated TokenFactor) if it's not an interior node.
1926 SDNode *N = ChainNodesMatched[i];
1927 if (N->getOpcode() != ISD::TokenFactor) {
1928 if (std::count(InteriorChainedNodes.begin(),InteriorChainedNodes.end(),N))
1931 // Otherwise, add the input chain.
1932 SDValue InChain = ChainNodesMatched[i]->getOperand(0);
1933 assert(InChain.getValueType() == MVT::Other && "Not a chain");
1934 InputChains.push_back(InChain);
1938 // If we have a token factor, we want to add all inputs of the token factor
1939 // that are not part of the pattern we're matching.
1940 for (unsigned op = 0, e = N->getNumOperands(); op != e; ++op) {
1941 if (!std::count(ChainNodesMatched.begin(), ChainNodesMatched.end(),
1942 N->getOperand(op).getNode()))
1943 InputChains.push_back(N->getOperand(op));
1948 if (InputChains.size() == 1)
1949 return InputChains[0];
1950 return CurDAG->getNode(ISD::TokenFactor, ChainNodesMatched[0]->getDebugLoc(),
1951 MVT::Other, &InputChains[0], InputChains.size());
1954 /// MorphNode - Handle morphing a node in place for the selector.
1955 SDNode *SelectionDAGISel::
1956 MorphNode(SDNode *Node, unsigned TargetOpc, SDVTList VTList,
1957 const SDValue *Ops, unsigned NumOps, unsigned EmitNodeInfo) {
1958 // It is possible we're using MorphNodeTo to replace a node with no
1959 // normal results with one that has a normal result (or we could be
1960 // adding a chain) and the input could have glue and chains as well.
1961 // In this case we need to shift the operands down.
1962 // FIXME: This is a horrible hack and broken in obscure cases, no worse
1963 // than the old isel though.
1964 int OldGlueResultNo = -1, OldChainResultNo = -1;
1966 unsigned NTMNumResults = Node->getNumValues();
1967 if (Node->getValueType(NTMNumResults-1) == MVT::Glue) {
1968 OldGlueResultNo = NTMNumResults-1;
1969 if (NTMNumResults != 1 &&
1970 Node->getValueType(NTMNumResults-2) == MVT::Other)
1971 OldChainResultNo = NTMNumResults-2;
1972 } else if (Node->getValueType(NTMNumResults-1) == MVT::Other)
1973 OldChainResultNo = NTMNumResults-1;
1975 // Call the underlying SelectionDAG routine to do the transmogrification. Note
1976 // that this deletes operands of the old node that become dead.
1977 SDNode *Res = CurDAG->MorphNodeTo(Node, ~TargetOpc, VTList, Ops, NumOps);
1979 // MorphNodeTo can operate in two ways: if an existing node with the
1980 // specified operands exists, it can just return it. Otherwise, it
1981 // updates the node in place to have the requested operands.
1983 // If we updated the node in place, reset the node ID. To the isel,
1984 // this should be just like a newly allocated machine node.
1988 unsigned ResNumResults = Res->getNumValues();
1989 // Move the glue if needed.
1990 if ((EmitNodeInfo & OPFL_GlueOutput) && OldGlueResultNo != -1 &&
1991 (unsigned)OldGlueResultNo != ResNumResults-1)
1992 CurDAG->ReplaceAllUsesOfValueWith(SDValue(Node, OldGlueResultNo),
1993 SDValue(Res, ResNumResults-1));
1995 if ((EmitNodeInfo & OPFL_GlueOutput) != 0)
1998 // Move the chain reference if needed.
1999 if ((EmitNodeInfo & OPFL_Chain) && OldChainResultNo != -1 &&
2000 (unsigned)OldChainResultNo != ResNumResults-1)
2001 CurDAG->ReplaceAllUsesOfValueWith(SDValue(Node, OldChainResultNo),
2002 SDValue(Res, ResNumResults-1));
2004 // Otherwise, no replacement happened because the node already exists. Replace
2005 // Uses of the old node with the new one.
2007 CurDAG->ReplaceAllUsesWith(Node, Res);
2012 /// CheckSame - Implements OP_CheckSame.
2013 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2014 CheckSame(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2016 const SmallVectorImpl<std::pair<SDValue, SDNode*> > &RecordedNodes) {
2017 // Accept if it is exactly the same as a previously recorded node.
2018 unsigned RecNo = MatcherTable[MatcherIndex++];
2019 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2020 return N == RecordedNodes[RecNo].first;
2023 /// CheckPatternPredicate - Implements OP_CheckPatternPredicate.
2024 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2025 CheckPatternPredicate(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2026 const SelectionDAGISel &SDISel) {
2027 return SDISel.CheckPatternPredicate(MatcherTable[MatcherIndex++]);
2030 /// CheckNodePredicate - Implements OP_CheckNodePredicate.
2031 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2032 CheckNodePredicate(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2033 const SelectionDAGISel &SDISel, SDNode *N) {
2034 return SDISel.CheckNodePredicate(N, MatcherTable[MatcherIndex++]);
2037 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2038 CheckOpcode(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2040 uint16_t Opc = MatcherTable[MatcherIndex++];
2041 Opc |= (unsigned short)MatcherTable[MatcherIndex++] << 8;
2042 return N->getOpcode() == Opc;
2045 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2046 CheckType(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2047 SDValue N, const TargetLowering &TLI) {
2048 MVT::SimpleValueType VT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2049 if (N.getValueType() == VT) return true;
2051 // Handle the case when VT is iPTR.
2052 return VT == MVT::iPTR && N.getValueType() == TLI.getPointerTy();
2055 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2056 CheckChildType(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2057 SDValue N, const TargetLowering &TLI,
2059 if (ChildNo >= N.getNumOperands())
2060 return false; // Match fails if out of range child #.
2061 return ::CheckType(MatcherTable, MatcherIndex, N.getOperand(ChildNo), TLI);
2065 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2066 CheckCondCode(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2068 return cast<CondCodeSDNode>(N)->get() ==
2069 (ISD::CondCode)MatcherTable[MatcherIndex++];
2072 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2073 CheckValueType(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2074 SDValue N, const TargetLowering &TLI) {
2075 MVT::SimpleValueType VT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2076 if (cast<VTSDNode>(N)->getVT() == VT)
2079 // Handle the case when VT is iPTR.
2080 return VT == MVT::iPTR && cast<VTSDNode>(N)->getVT() == TLI.getPointerTy();
2083 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2084 CheckInteger(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2086 int64_t Val = MatcherTable[MatcherIndex++];
2088 Val = GetVBR(Val, MatcherTable, MatcherIndex);
2090 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N);
2091 return C != 0 && C->getSExtValue() == Val;
2094 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2095 CheckAndImm(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2096 SDValue N, const SelectionDAGISel &SDISel) {
2097 int64_t Val = MatcherTable[MatcherIndex++];
2099 Val = GetVBR(Val, MatcherTable, MatcherIndex);
2101 if (N->getOpcode() != ISD::AND) return false;
2103 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
2104 return C != 0 && SDISel.CheckAndMask(N.getOperand(0), C, Val);
2107 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2108 CheckOrImm(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2109 SDValue N, const SelectionDAGISel &SDISel) {
2110 int64_t Val = MatcherTable[MatcherIndex++];
2112 Val = GetVBR(Val, MatcherTable, MatcherIndex);
2114 if (N->getOpcode() != ISD::OR) return false;
2116 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
2117 return C != 0 && SDISel.CheckOrMask(N.getOperand(0), C, Val);
2120 /// IsPredicateKnownToFail - If we know how and can do so without pushing a
2121 /// scope, evaluate the current node. If the current predicate is known to
2122 /// fail, set Result=true and return anything. If the current predicate is
2123 /// known to pass, set Result=false and return the MatcherIndex to continue
2124 /// with. If the current predicate is unknown, set Result=false and return the
2125 /// MatcherIndex to continue with.
2126 static unsigned IsPredicateKnownToFail(const unsigned char *Table,
2127 unsigned Index, SDValue N,
2129 const SelectionDAGISel &SDISel,
2130 SmallVectorImpl<std::pair<SDValue, SDNode*> > &RecordedNodes) {
2131 switch (Table[Index++]) {
2134 return Index-1; // Could not evaluate this predicate.
2135 case SelectionDAGISel::OPC_CheckSame:
2136 Result = !::CheckSame(Table, Index, N, RecordedNodes);
2138 case SelectionDAGISel::OPC_CheckPatternPredicate:
2139 Result = !::CheckPatternPredicate(Table, Index, SDISel);
2141 case SelectionDAGISel::OPC_CheckPredicate:
2142 Result = !::CheckNodePredicate(Table, Index, SDISel, N.getNode());
2144 case SelectionDAGISel::OPC_CheckOpcode:
2145 Result = !::CheckOpcode(Table, Index, N.getNode());
2147 case SelectionDAGISel::OPC_CheckType:
2148 Result = !::CheckType(Table, Index, N, SDISel.TLI);
2150 case SelectionDAGISel::OPC_CheckChild0Type:
2151 case SelectionDAGISel::OPC_CheckChild1Type:
2152 case SelectionDAGISel::OPC_CheckChild2Type:
2153 case SelectionDAGISel::OPC_CheckChild3Type:
2154 case SelectionDAGISel::OPC_CheckChild4Type:
2155 case SelectionDAGISel::OPC_CheckChild5Type:
2156 case SelectionDAGISel::OPC_CheckChild6Type:
2157 case SelectionDAGISel::OPC_CheckChild7Type:
2158 Result = !::CheckChildType(Table, Index, N, SDISel.TLI,
2159 Table[Index-1] - SelectionDAGISel::OPC_CheckChild0Type);
2161 case SelectionDAGISel::OPC_CheckCondCode:
2162 Result = !::CheckCondCode(Table, Index, N);
2164 case SelectionDAGISel::OPC_CheckValueType:
2165 Result = !::CheckValueType(Table, Index, N, SDISel.TLI);
2167 case SelectionDAGISel::OPC_CheckInteger:
2168 Result = !::CheckInteger(Table, Index, N);
2170 case SelectionDAGISel::OPC_CheckAndImm:
2171 Result = !::CheckAndImm(Table, Index, N, SDISel);
2173 case SelectionDAGISel::OPC_CheckOrImm:
2174 Result = !::CheckOrImm(Table, Index, N, SDISel);
2182 /// FailIndex - If this match fails, this is the index to continue with.
2185 /// NodeStack - The node stack when the scope was formed.
2186 SmallVector<SDValue, 4> NodeStack;
2188 /// NumRecordedNodes - The number of recorded nodes when the scope was formed.
2189 unsigned NumRecordedNodes;
2191 /// NumMatchedMemRefs - The number of matched memref entries.
2192 unsigned NumMatchedMemRefs;
2194 /// InputChain/InputGlue - The current chain/glue
2195 SDValue InputChain, InputGlue;
2197 /// HasChainNodesMatched - True if the ChainNodesMatched list is non-empty.
2198 bool HasChainNodesMatched, HasGlueResultNodesMatched;
2203 SDNode *SelectionDAGISel::
2204 SelectCodeCommon(SDNode *NodeToMatch, const unsigned char *MatcherTable,
2205 unsigned TableSize) {
2206 // FIXME: Should these even be selected? Handle these cases in the caller?
2207 switch (NodeToMatch->getOpcode()) {
2210 case ISD::EntryToken: // These nodes remain the same.
2211 case ISD::BasicBlock:
2213 case ISD::RegisterMask:
2214 //case ISD::VALUETYPE:
2215 //case ISD::CONDCODE:
2216 case ISD::HANDLENODE:
2217 case ISD::MDNODE_SDNODE:
2218 case ISD::TargetConstant:
2219 case ISD::TargetConstantFP:
2220 case ISD::TargetConstantPool:
2221 case ISD::TargetFrameIndex:
2222 case ISD::TargetExternalSymbol:
2223 case ISD::TargetBlockAddress:
2224 case ISD::TargetJumpTable:
2225 case ISD::TargetGlobalTLSAddress:
2226 case ISD::TargetGlobalAddress:
2227 case ISD::TokenFactor:
2228 case ISD::CopyFromReg:
2229 case ISD::CopyToReg:
2231 case ISD::LIFETIME_START:
2232 case ISD::LIFETIME_END:
2233 NodeToMatch->setNodeId(-1); // Mark selected.
2235 case ISD::AssertSext:
2236 case ISD::AssertZext:
2237 CurDAG->ReplaceAllUsesOfValueWith(SDValue(NodeToMatch, 0),
2238 NodeToMatch->getOperand(0));
2240 case ISD::INLINEASM: return Select_INLINEASM(NodeToMatch);
2241 case ISD::UNDEF: return Select_UNDEF(NodeToMatch);
2244 assert(!NodeToMatch->isMachineOpcode() && "Node already selected!");
2246 // Set up the node stack with NodeToMatch as the only node on the stack.
2247 SmallVector<SDValue, 8> NodeStack;
2248 SDValue N = SDValue(NodeToMatch, 0);
2249 NodeStack.push_back(N);
2251 // MatchScopes - Scopes used when matching, if a match failure happens, this
2252 // indicates where to continue checking.
2253 SmallVector<MatchScope, 8> MatchScopes;
2255 // RecordedNodes - This is the set of nodes that have been recorded by the
2256 // state machine. The second value is the parent of the node, or null if the
2257 // root is recorded.
2258 SmallVector<std::pair<SDValue, SDNode*>, 8> RecordedNodes;
2260 // MatchedMemRefs - This is the set of MemRef's we've seen in the input
2262 SmallVector<MachineMemOperand*, 2> MatchedMemRefs;
2264 // These are the current input chain and glue for use when generating nodes.
2265 // Various Emit operations change these. For example, emitting a copytoreg
2266 // uses and updates these.
2267 SDValue InputChain, InputGlue;
2269 // ChainNodesMatched - If a pattern matches nodes that have input/output
2270 // chains, the OPC_EmitMergeInputChains operation is emitted which indicates
2271 // which ones they are. The result is captured into this list so that we can
2272 // update the chain results when the pattern is complete.
2273 SmallVector<SDNode*, 3> ChainNodesMatched;
2274 SmallVector<SDNode*, 3> GlueResultNodesMatched;
2276 DEBUG(errs() << "ISEL: Starting pattern match on root node: ";
2277 NodeToMatch->dump(CurDAG);
2280 // Determine where to start the interpreter. Normally we start at opcode #0,
2281 // but if the state machine starts with an OPC_SwitchOpcode, then we
2282 // accelerate the first lookup (which is guaranteed to be hot) with the
2283 // OpcodeOffset table.
2284 unsigned MatcherIndex = 0;
2286 if (!OpcodeOffset.empty()) {
2287 // Already computed the OpcodeOffset table, just index into it.
2288 if (N.getOpcode() < OpcodeOffset.size())
2289 MatcherIndex = OpcodeOffset[N.getOpcode()];
2290 DEBUG(errs() << " Initial Opcode index to " << MatcherIndex << "\n");
2292 } else if (MatcherTable[0] == OPC_SwitchOpcode) {
2293 // Otherwise, the table isn't computed, but the state machine does start
2294 // with an OPC_SwitchOpcode instruction. Populate the table now, since this
2295 // is the first time we're selecting an instruction.
2298 // Get the size of this case.
2299 unsigned CaseSize = MatcherTable[Idx++];
2301 CaseSize = GetVBR(CaseSize, MatcherTable, Idx);
2302 if (CaseSize == 0) break;
2304 // Get the opcode, add the index to the table.
2305 uint16_t Opc = MatcherTable[Idx++];
2306 Opc |= (unsigned short)MatcherTable[Idx++] << 8;
2307 if (Opc >= OpcodeOffset.size())
2308 OpcodeOffset.resize((Opc+1)*2);
2309 OpcodeOffset[Opc] = Idx;
2313 // Okay, do the lookup for the first opcode.
2314 if (N.getOpcode() < OpcodeOffset.size())
2315 MatcherIndex = OpcodeOffset[N.getOpcode()];
2319 assert(MatcherIndex < TableSize && "Invalid index");
2321 unsigned CurrentOpcodeIndex = MatcherIndex;
2323 BuiltinOpcodes Opcode = (BuiltinOpcodes)MatcherTable[MatcherIndex++];
2326 // Okay, the semantics of this operation are that we should push a scope
2327 // then evaluate the first child. However, pushing a scope only to have
2328 // the first check fail (which then pops it) is inefficient. If we can
2329 // determine immediately that the first check (or first several) will
2330 // immediately fail, don't even bother pushing a scope for them.
2334 unsigned NumToSkip = MatcherTable[MatcherIndex++];
2335 if (NumToSkip & 128)
2336 NumToSkip = GetVBR(NumToSkip, MatcherTable, MatcherIndex);
2337 // Found the end of the scope with no match.
2338 if (NumToSkip == 0) {
2343 FailIndex = MatcherIndex+NumToSkip;
2345 unsigned MatcherIndexOfPredicate = MatcherIndex;
2346 (void)MatcherIndexOfPredicate; // silence warning.
2348 // If we can't evaluate this predicate without pushing a scope (e.g. if
2349 // it is a 'MoveParent') or if the predicate succeeds on this node, we
2350 // push the scope and evaluate the full predicate chain.
2352 MatcherIndex = IsPredicateKnownToFail(MatcherTable, MatcherIndex, N,
2353 Result, *this, RecordedNodes);
2357 DEBUG(errs() << " Skipped scope entry (due to false predicate) at "
2358 << "index " << MatcherIndexOfPredicate
2359 << ", continuing at " << FailIndex << "\n");
2360 DEBUG(++NumDAGIselRetries);
2362 // Otherwise, we know that this case of the Scope is guaranteed to fail,
2363 // move to the next case.
2364 MatcherIndex = FailIndex;
2367 // If the whole scope failed to match, bail.
2368 if (FailIndex == 0) break;
2370 // Push a MatchScope which indicates where to go if the first child fails
2372 MatchScope NewEntry;
2373 NewEntry.FailIndex = FailIndex;
2374 NewEntry.NodeStack.append(NodeStack.begin(), NodeStack.end());
2375 NewEntry.NumRecordedNodes = RecordedNodes.size();
2376 NewEntry.NumMatchedMemRefs = MatchedMemRefs.size();
2377 NewEntry.InputChain = InputChain;
2378 NewEntry.InputGlue = InputGlue;
2379 NewEntry.HasChainNodesMatched = !ChainNodesMatched.empty();
2380 NewEntry.HasGlueResultNodesMatched = !GlueResultNodesMatched.empty();
2381 MatchScopes.push_back(NewEntry);
2384 case OPC_RecordNode: {
2385 // Remember this node, it may end up being an operand in the pattern.
2387 if (NodeStack.size() > 1)
2388 Parent = NodeStack[NodeStack.size()-2].getNode();
2389 RecordedNodes.push_back(std::make_pair(N, Parent));
2393 case OPC_RecordChild0: case OPC_RecordChild1:
2394 case OPC_RecordChild2: case OPC_RecordChild3:
2395 case OPC_RecordChild4: case OPC_RecordChild5:
2396 case OPC_RecordChild6: case OPC_RecordChild7: {
2397 unsigned ChildNo = Opcode-OPC_RecordChild0;
2398 if (ChildNo >= N.getNumOperands())
2399 break; // Match fails if out of range child #.
2401 RecordedNodes.push_back(std::make_pair(N->getOperand(ChildNo),
2405 case OPC_RecordMemRef:
2406 MatchedMemRefs.push_back(cast<MemSDNode>(N)->getMemOperand());
2409 case OPC_CaptureGlueInput:
2410 // If the current node has an input glue, capture it in InputGlue.
2411 if (N->getNumOperands() != 0 &&
2412 N->getOperand(N->getNumOperands()-1).getValueType() == MVT::Glue)
2413 InputGlue = N->getOperand(N->getNumOperands()-1);
2416 case OPC_MoveChild: {
2417 unsigned ChildNo = MatcherTable[MatcherIndex++];
2418 if (ChildNo >= N.getNumOperands())
2419 break; // Match fails if out of range child #.
2420 N = N.getOperand(ChildNo);
2421 NodeStack.push_back(N);
2425 case OPC_MoveParent:
2426 // Pop the current node off the NodeStack.
2427 NodeStack.pop_back();
2428 assert(!NodeStack.empty() && "Node stack imbalance!");
2429 N = NodeStack.back();
2433 if (!::CheckSame(MatcherTable, MatcherIndex, N, RecordedNodes)) break;
2435 case OPC_CheckPatternPredicate:
2436 if (!::CheckPatternPredicate(MatcherTable, MatcherIndex, *this)) break;
2438 case OPC_CheckPredicate:
2439 if (!::CheckNodePredicate(MatcherTable, MatcherIndex, *this,
2443 case OPC_CheckComplexPat: {
2444 unsigned CPNum = MatcherTable[MatcherIndex++];
2445 unsigned RecNo = MatcherTable[MatcherIndex++];
2446 assert(RecNo < RecordedNodes.size() && "Invalid CheckComplexPat");
2447 if (!CheckComplexPattern(NodeToMatch, RecordedNodes[RecNo].second,
2448 RecordedNodes[RecNo].first, CPNum,
2453 case OPC_CheckOpcode:
2454 if (!::CheckOpcode(MatcherTable, MatcherIndex, N.getNode())) break;
2458 if (!::CheckType(MatcherTable, MatcherIndex, N, TLI)) break;
2461 case OPC_SwitchOpcode: {
2462 unsigned CurNodeOpcode = N.getOpcode();
2463 unsigned SwitchStart = MatcherIndex-1; (void)SwitchStart;
2466 // Get the size of this case.
2467 CaseSize = MatcherTable[MatcherIndex++];
2469 CaseSize = GetVBR(CaseSize, MatcherTable, MatcherIndex);
2470 if (CaseSize == 0) break;
2472 uint16_t Opc = MatcherTable[MatcherIndex++];
2473 Opc |= (unsigned short)MatcherTable[MatcherIndex++] << 8;
2475 // If the opcode matches, then we will execute this case.
2476 if (CurNodeOpcode == Opc)
2479 // Otherwise, skip over this case.
2480 MatcherIndex += CaseSize;
2483 // If no cases matched, bail out.
2484 if (CaseSize == 0) break;
2486 // Otherwise, execute the case we found.
2487 DEBUG(errs() << " OpcodeSwitch from " << SwitchStart
2488 << " to " << MatcherIndex << "\n");
2492 case OPC_SwitchType: {
2493 MVT CurNodeVT = N.getValueType().getSimpleVT();
2494 unsigned SwitchStart = MatcherIndex-1; (void)SwitchStart;
2497 // Get the size of this case.
2498 CaseSize = MatcherTable[MatcherIndex++];
2500 CaseSize = GetVBR(CaseSize, MatcherTable, MatcherIndex);
2501 if (CaseSize == 0) break;
2503 MVT CaseVT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2504 if (CaseVT == MVT::iPTR)
2505 CaseVT = TLI.getPointerTy();
2507 // If the VT matches, then we will execute this case.
2508 if (CurNodeVT == CaseVT)
2511 // Otherwise, skip over this case.
2512 MatcherIndex += CaseSize;
2515 // If no cases matched, bail out.
2516 if (CaseSize == 0) break;
2518 // Otherwise, execute the case we found.
2519 DEBUG(errs() << " TypeSwitch[" << EVT(CurNodeVT).getEVTString()
2520 << "] from " << SwitchStart << " to " << MatcherIndex<<'\n');
2523 case OPC_CheckChild0Type: case OPC_CheckChild1Type:
2524 case OPC_CheckChild2Type: case OPC_CheckChild3Type:
2525 case OPC_CheckChild4Type: case OPC_CheckChild5Type:
2526 case OPC_CheckChild6Type: case OPC_CheckChild7Type:
2527 if (!::CheckChildType(MatcherTable, MatcherIndex, N, TLI,
2528 Opcode-OPC_CheckChild0Type))
2531 case OPC_CheckCondCode:
2532 if (!::CheckCondCode(MatcherTable, MatcherIndex, N)) break;
2534 case OPC_CheckValueType:
2535 if (!::CheckValueType(MatcherTable, MatcherIndex, N, TLI)) break;
2537 case OPC_CheckInteger:
2538 if (!::CheckInteger(MatcherTable, MatcherIndex, N)) break;
2540 case OPC_CheckAndImm:
2541 if (!::CheckAndImm(MatcherTable, MatcherIndex, N, *this)) break;
2543 case OPC_CheckOrImm:
2544 if (!::CheckOrImm(MatcherTable, MatcherIndex, N, *this)) break;
2547 case OPC_CheckFoldableChainNode: {
2548 assert(NodeStack.size() != 1 && "No parent node");
2549 // Verify that all intermediate nodes between the root and this one have
2551 bool HasMultipleUses = false;
2552 for (unsigned i = 1, e = NodeStack.size()-1; i != e; ++i)
2553 if (!NodeStack[i].hasOneUse()) {
2554 HasMultipleUses = true;
2557 if (HasMultipleUses) break;
2559 // Check to see that the target thinks this is profitable to fold and that
2560 // we can fold it without inducing cycles in the graph.
2561 if (!IsProfitableToFold(N, NodeStack[NodeStack.size()-2].getNode(),
2563 !IsLegalToFold(N, NodeStack[NodeStack.size()-2].getNode(),
2564 NodeToMatch, OptLevel,
2565 true/*We validate our own chains*/))
2570 case OPC_EmitInteger: {
2571 MVT::SimpleValueType VT =
2572 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2573 int64_t Val = MatcherTable[MatcherIndex++];
2575 Val = GetVBR(Val, MatcherTable, MatcherIndex);
2576 RecordedNodes.push_back(std::pair<SDValue, SDNode*>(
2577 CurDAG->getTargetConstant(Val, VT), (SDNode*)0));
2580 case OPC_EmitRegister: {
2581 MVT::SimpleValueType VT =
2582 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2583 unsigned RegNo = MatcherTable[MatcherIndex++];
2584 RecordedNodes.push_back(std::pair<SDValue, SDNode*>(
2585 CurDAG->getRegister(RegNo, VT), (SDNode*)0));
2588 case OPC_EmitRegister2: {
2589 // For targets w/ more than 256 register names, the register enum
2590 // values are stored in two bytes in the matcher table (just like
2592 MVT::SimpleValueType VT =
2593 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2594 unsigned RegNo = MatcherTable[MatcherIndex++];
2595 RegNo |= MatcherTable[MatcherIndex++] << 8;
2596 RecordedNodes.push_back(std::pair<SDValue, SDNode*>(
2597 CurDAG->getRegister(RegNo, VT), (SDNode*)0));
2601 case OPC_EmitConvertToTarget: {
2602 // Convert from IMM/FPIMM to target version.
2603 unsigned RecNo = MatcherTable[MatcherIndex++];
2604 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2605 SDValue Imm = RecordedNodes[RecNo].first;
2607 if (Imm->getOpcode() == ISD::Constant) {
2608 const ConstantInt *Val=cast<ConstantSDNode>(Imm)->getConstantIntValue();
2609 Imm = CurDAG->getConstant(*Val, Imm.getValueType(), true);
2610 } else if (Imm->getOpcode() == ISD::ConstantFP) {
2611 const ConstantFP *Val=cast<ConstantFPSDNode>(Imm)->getConstantFPValue();
2612 Imm = CurDAG->getConstantFP(*Val, Imm.getValueType(), true);
2615 RecordedNodes.push_back(std::make_pair(Imm, RecordedNodes[RecNo].second));
2619 case OPC_EmitMergeInputChains1_0: // OPC_EmitMergeInputChains, 1, 0
2620 case OPC_EmitMergeInputChains1_1: { // OPC_EmitMergeInputChains, 1, 1
2621 // These are space-optimized forms of OPC_EmitMergeInputChains.
2622 assert(InputChain.getNode() == 0 &&
2623 "EmitMergeInputChains should be the first chain producing node");
2624 assert(ChainNodesMatched.empty() &&
2625 "Should only have one EmitMergeInputChains per match");
2627 // Read all of the chained nodes.
2628 unsigned RecNo = Opcode == OPC_EmitMergeInputChains1_1;
2629 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2630 ChainNodesMatched.push_back(RecordedNodes[RecNo].first.getNode());
2632 // FIXME: What if other value results of the node have uses not matched
2634 if (ChainNodesMatched.back() != NodeToMatch &&
2635 !RecordedNodes[RecNo].first.hasOneUse()) {
2636 ChainNodesMatched.clear();
2640 // Merge the input chains if they are not intra-pattern references.
2641 InputChain = HandleMergeInputChains(ChainNodesMatched, CurDAG);
2643 if (InputChain.getNode() == 0)
2644 break; // Failed to merge.
2648 case OPC_EmitMergeInputChains: {
2649 assert(InputChain.getNode() == 0 &&
2650 "EmitMergeInputChains should be the first chain producing node");
2651 // This node gets a list of nodes we matched in the input that have
2652 // chains. We want to token factor all of the input chains to these nodes
2653 // together. However, if any of the input chains is actually one of the
2654 // nodes matched in this pattern, then we have an intra-match reference.
2655 // Ignore these because the newly token factored chain should not refer to
2657 unsigned NumChains = MatcherTable[MatcherIndex++];
2658 assert(NumChains != 0 && "Can't TF zero chains");
2660 assert(ChainNodesMatched.empty() &&
2661 "Should only have one EmitMergeInputChains per match");
2663 // Read all of the chained nodes.
2664 for (unsigned i = 0; i != NumChains; ++i) {
2665 unsigned RecNo = MatcherTable[MatcherIndex++];
2666 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2667 ChainNodesMatched.push_back(RecordedNodes[RecNo].first.getNode());
2669 // FIXME: What if other value results of the node have uses not matched
2671 if (ChainNodesMatched.back() != NodeToMatch &&
2672 !RecordedNodes[RecNo].first.hasOneUse()) {
2673 ChainNodesMatched.clear();
2678 // If the inner loop broke out, the match fails.
2679 if (ChainNodesMatched.empty())
2682 // Merge the input chains if they are not intra-pattern references.
2683 InputChain = HandleMergeInputChains(ChainNodesMatched, CurDAG);
2685 if (InputChain.getNode() == 0)
2686 break; // Failed to merge.
2691 case OPC_EmitCopyToReg: {
2692 unsigned RecNo = MatcherTable[MatcherIndex++];
2693 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2694 unsigned DestPhysReg = MatcherTable[MatcherIndex++];
2696 if (InputChain.getNode() == 0)
2697 InputChain = CurDAG->getEntryNode();
2699 InputChain = CurDAG->getCopyToReg(InputChain, NodeToMatch->getDebugLoc(),
2700 DestPhysReg, RecordedNodes[RecNo].first,
2703 InputGlue = InputChain.getValue(1);
2707 case OPC_EmitNodeXForm: {
2708 unsigned XFormNo = MatcherTable[MatcherIndex++];
2709 unsigned RecNo = MatcherTable[MatcherIndex++];
2710 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2711 SDValue Res = RunSDNodeXForm(RecordedNodes[RecNo].first, XFormNo);
2712 RecordedNodes.push_back(std::pair<SDValue,SDNode*>(Res, (SDNode*) 0));
2717 case OPC_MorphNodeTo: {
2718 uint16_t TargetOpc = MatcherTable[MatcherIndex++];
2719 TargetOpc |= (unsigned short)MatcherTable[MatcherIndex++] << 8;
2720 unsigned EmitNodeInfo = MatcherTable[MatcherIndex++];
2721 // Get the result VT list.
2722 unsigned NumVTs = MatcherTable[MatcherIndex++];
2723 SmallVector<EVT, 4> VTs;
2724 for (unsigned i = 0; i != NumVTs; ++i) {
2725 MVT::SimpleValueType VT =
2726 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2727 if (VT == MVT::iPTR) VT = TLI.getPointerTy().SimpleTy;
2731 if (EmitNodeInfo & OPFL_Chain)
2732 VTs.push_back(MVT::Other);
2733 if (EmitNodeInfo & OPFL_GlueOutput)
2734 VTs.push_back(MVT::Glue);
2736 // This is hot code, so optimize the two most common cases of 1 and 2
2739 if (VTs.size() == 1)
2740 VTList = CurDAG->getVTList(VTs[0]);
2741 else if (VTs.size() == 2)
2742 VTList = CurDAG->getVTList(VTs[0], VTs[1]);
2744 VTList = CurDAG->getVTList(VTs.data(), VTs.size());
2746 // Get the operand list.
2747 unsigned NumOps = MatcherTable[MatcherIndex++];
2748 SmallVector<SDValue, 8> Ops;
2749 for (unsigned i = 0; i != NumOps; ++i) {
2750 unsigned RecNo = MatcherTable[MatcherIndex++];
2752 RecNo = GetVBR(RecNo, MatcherTable, MatcherIndex);
2754 assert(RecNo < RecordedNodes.size() && "Invalid EmitNode");
2755 Ops.push_back(RecordedNodes[RecNo].first);
2758 // If there are variadic operands to add, handle them now.
2759 if (EmitNodeInfo & OPFL_VariadicInfo) {
2760 // Determine the start index to copy from.
2761 unsigned FirstOpToCopy = getNumFixedFromVariadicInfo(EmitNodeInfo);
2762 FirstOpToCopy += (EmitNodeInfo & OPFL_Chain) ? 1 : 0;
2763 assert(NodeToMatch->getNumOperands() >= FirstOpToCopy &&
2764 "Invalid variadic node");
2765 // Copy all of the variadic operands, not including a potential glue
2767 for (unsigned i = FirstOpToCopy, e = NodeToMatch->getNumOperands();
2769 SDValue V = NodeToMatch->getOperand(i);
2770 if (V.getValueType() == MVT::Glue) break;
2775 // If this has chain/glue inputs, add them.
2776 if (EmitNodeInfo & OPFL_Chain)
2777 Ops.push_back(InputChain);
2778 if ((EmitNodeInfo & OPFL_GlueInput) && InputGlue.getNode() != 0)
2779 Ops.push_back(InputGlue);
2783 if (Opcode != OPC_MorphNodeTo) {
2784 // If this is a normal EmitNode command, just create the new node and
2785 // add the results to the RecordedNodes list.
2786 Res = CurDAG->getMachineNode(TargetOpc, NodeToMatch->getDebugLoc(),
2787 VTList, Ops.data(), Ops.size());
2789 // Add all the non-glue/non-chain results to the RecordedNodes list.
2790 for (unsigned i = 0, e = VTs.size(); i != e; ++i) {
2791 if (VTs[i] == MVT::Other || VTs[i] == MVT::Glue) break;
2792 RecordedNodes.push_back(std::pair<SDValue,SDNode*>(SDValue(Res, i),
2796 } else if (NodeToMatch->getOpcode() != ISD::DELETED_NODE) {
2797 Res = MorphNode(NodeToMatch, TargetOpc, VTList, Ops.data(), Ops.size(),
2800 // NodeToMatch was eliminated by CSE when the target changed the DAG.
2801 // We will visit the equivalent node later.
2802 DEBUG(dbgs() << "Node was eliminated by CSE\n");
2806 // If the node had chain/glue results, update our notion of the current
2808 if (EmitNodeInfo & OPFL_GlueOutput) {
2809 InputGlue = SDValue(Res, VTs.size()-1);
2810 if (EmitNodeInfo & OPFL_Chain)
2811 InputChain = SDValue(Res, VTs.size()-2);
2812 } else if (EmitNodeInfo & OPFL_Chain)
2813 InputChain = SDValue(Res, VTs.size()-1);
2815 // If the OPFL_MemRefs glue is set on this node, slap all of the
2816 // accumulated memrefs onto it.
2818 // FIXME: This is vastly incorrect for patterns with multiple outputs
2819 // instructions that access memory and for ComplexPatterns that match
2821 if (EmitNodeInfo & OPFL_MemRefs) {
2822 // Only attach load or store memory operands if the generated
2823 // instruction may load or store.
2824 const MCInstrDesc &MCID = TM.getInstrInfo()->get(TargetOpc);
2825 bool mayLoad = MCID.mayLoad();
2826 bool mayStore = MCID.mayStore();
2828 unsigned NumMemRefs = 0;
2829 for (SmallVector<MachineMemOperand*, 2>::const_iterator I =
2830 MatchedMemRefs.begin(), E = MatchedMemRefs.end(); I != E; ++I) {
2831 if ((*I)->isLoad()) {
2834 } else if ((*I)->isStore()) {
2842 MachineSDNode::mmo_iterator MemRefs =
2843 MF->allocateMemRefsArray(NumMemRefs);
2845 MachineSDNode::mmo_iterator MemRefsPos = MemRefs;
2846 for (SmallVector<MachineMemOperand*, 2>::const_iterator I =
2847 MatchedMemRefs.begin(), E = MatchedMemRefs.end(); I != E; ++I) {
2848 if ((*I)->isLoad()) {
2851 } else if ((*I)->isStore()) {
2859 cast<MachineSDNode>(Res)
2860 ->setMemRefs(MemRefs, MemRefs + NumMemRefs);
2864 << (Opcode == OPC_MorphNodeTo ? "Morphed" : "Created")
2865 << " node: "; Res->dump(CurDAG); errs() << "\n");
2867 // If this was a MorphNodeTo then we're completely done!
2868 if (Opcode == OPC_MorphNodeTo) {
2869 // Update chain and glue uses.
2870 UpdateChainsAndGlue(NodeToMatch, InputChain, ChainNodesMatched,
2871 InputGlue, GlueResultNodesMatched, true);
2878 case OPC_MarkGlueResults: {
2879 unsigned NumNodes = MatcherTable[MatcherIndex++];
2881 // Read and remember all the glue-result nodes.
2882 for (unsigned i = 0; i != NumNodes; ++i) {
2883 unsigned RecNo = MatcherTable[MatcherIndex++];
2885 RecNo = GetVBR(RecNo, MatcherTable, MatcherIndex);
2887 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2888 GlueResultNodesMatched.push_back(RecordedNodes[RecNo].first.getNode());
2893 case OPC_CompleteMatch: {
2894 // The match has been completed, and any new nodes (if any) have been
2895 // created. Patch up references to the matched dag to use the newly
2897 unsigned NumResults = MatcherTable[MatcherIndex++];
2899 for (unsigned i = 0; i != NumResults; ++i) {
2900 unsigned ResSlot = MatcherTable[MatcherIndex++];
2902 ResSlot = GetVBR(ResSlot, MatcherTable, MatcherIndex);
2904 assert(ResSlot < RecordedNodes.size() && "Invalid CheckSame");
2905 SDValue Res = RecordedNodes[ResSlot].first;
2907 assert(i < NodeToMatch->getNumValues() &&
2908 NodeToMatch->getValueType(i) != MVT::Other &&
2909 NodeToMatch->getValueType(i) != MVT::Glue &&
2910 "Invalid number of results to complete!");
2911 assert((NodeToMatch->getValueType(i) == Res.getValueType() ||
2912 NodeToMatch->getValueType(i) == MVT::iPTR ||
2913 Res.getValueType() == MVT::iPTR ||
2914 NodeToMatch->getValueType(i).getSizeInBits() ==
2915 Res.getValueType().getSizeInBits()) &&
2916 "invalid replacement");
2917 CurDAG->ReplaceAllUsesOfValueWith(SDValue(NodeToMatch, i), Res);
2920 // If the root node defines glue, add it to the glue nodes to update list.
2921 if (NodeToMatch->getValueType(NodeToMatch->getNumValues()-1) == MVT::Glue)
2922 GlueResultNodesMatched.push_back(NodeToMatch);
2924 // Update chain and glue uses.
2925 UpdateChainsAndGlue(NodeToMatch, InputChain, ChainNodesMatched,
2926 InputGlue, GlueResultNodesMatched, false);
2928 assert(NodeToMatch->use_empty() &&
2929 "Didn't replace all uses of the node?");
2931 // FIXME: We just return here, which interacts correctly with SelectRoot
2932 // above. We should fix this to not return an SDNode* anymore.
2937 // If the code reached this point, then the match failed. See if there is
2938 // another child to try in the current 'Scope', otherwise pop it until we
2939 // find a case to check.
2940 DEBUG(errs() << " Match failed at index " << CurrentOpcodeIndex << "\n");
2941 DEBUG(++NumDAGIselRetries);
2943 if (MatchScopes.empty()) {
2944 CannotYetSelect(NodeToMatch);
2948 // Restore the interpreter state back to the point where the scope was
2950 MatchScope &LastScope = MatchScopes.back();
2951 RecordedNodes.resize(LastScope.NumRecordedNodes);
2953 NodeStack.append(LastScope.NodeStack.begin(), LastScope.NodeStack.end());
2954 N = NodeStack.back();
2956 if (LastScope.NumMatchedMemRefs != MatchedMemRefs.size())
2957 MatchedMemRefs.resize(LastScope.NumMatchedMemRefs);
2958 MatcherIndex = LastScope.FailIndex;
2960 DEBUG(errs() << " Continuing at " << MatcherIndex << "\n");
2962 InputChain = LastScope.InputChain;
2963 InputGlue = LastScope.InputGlue;
2964 if (!LastScope.HasChainNodesMatched)
2965 ChainNodesMatched.clear();
2966 if (!LastScope.HasGlueResultNodesMatched)
2967 GlueResultNodesMatched.clear();
2969 // Check to see what the offset is at the new MatcherIndex. If it is zero
2970 // we have reached the end of this scope, otherwise we have another child
2971 // in the current scope to try.
2972 unsigned NumToSkip = MatcherTable[MatcherIndex++];
2973 if (NumToSkip & 128)
2974 NumToSkip = GetVBR(NumToSkip, MatcherTable, MatcherIndex);
2976 // If we have another child in this scope to match, update FailIndex and
2978 if (NumToSkip != 0) {
2979 LastScope.FailIndex = MatcherIndex+NumToSkip;
2983 // End of this scope, pop it and try the next child in the containing
2985 MatchScopes.pop_back();
2992 void SelectionDAGISel::CannotYetSelect(SDNode *N) {
2994 raw_string_ostream Msg(msg);
2995 Msg << "Cannot select: ";
2997 if (N->getOpcode() != ISD::INTRINSIC_W_CHAIN &&
2998 N->getOpcode() != ISD::INTRINSIC_WO_CHAIN &&
2999 N->getOpcode() != ISD::INTRINSIC_VOID) {
3000 N->printrFull(Msg, CurDAG);
3001 Msg << "\nIn function: " << MF->getName();
3003 bool HasInputChain = N->getOperand(0).getValueType() == MVT::Other;
3005 cast<ConstantSDNode>(N->getOperand(HasInputChain))->getZExtValue();
3006 if (iid < Intrinsic::num_intrinsics)
3007 Msg << "intrinsic %" << Intrinsic::getName((Intrinsic::ID)iid);
3008 else if (const TargetIntrinsicInfo *TII = TM.getIntrinsicInfo())
3009 Msg << "target intrinsic %" << TII->getName(iid);
3011 Msg << "unknown intrinsic #" << iid;
3013 report_fatal_error(Msg.str());
3016 char SelectionDAGISel::ID = 0;