1 //===-- SelectionDAGISel.cpp - Implement the SelectionDAGISel class -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements the SelectionDAGISel class.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "isel"
15 #include "llvm/CodeGen/SelectionDAGISel.h"
16 #include "ScheduleDAGSDNodes.h"
17 #include "SelectionDAGBuilder.h"
18 #include "llvm/ADT/PostOrderIterator.h"
19 #include "llvm/ADT/Statistic.h"
20 #include "llvm/Analysis/AliasAnalysis.h"
21 #include "llvm/Analysis/BranchProbabilityInfo.h"
22 #include "llvm/Analysis/CFG.h"
23 #include "llvm/Analysis/TargetTransformInfo.h"
24 #include "llvm/CodeGen/FastISel.h"
25 #include "llvm/CodeGen/FunctionLoweringInfo.h"
26 #include "llvm/CodeGen/GCMetadata.h"
27 #include "llvm/CodeGen/GCStrategy.h"
28 #include "llvm/CodeGen/MachineFrameInfo.h"
29 #include "llvm/CodeGen/MachineFunction.h"
30 #include "llvm/CodeGen/MachineInstrBuilder.h"
31 #include "llvm/CodeGen/MachineModuleInfo.h"
32 #include "llvm/CodeGen/MachineRegisterInfo.h"
33 #include "llvm/CodeGen/ScheduleHazardRecognizer.h"
34 #include "llvm/CodeGen/SchedulerRegistry.h"
35 #include "llvm/CodeGen/SelectionDAG.h"
36 #include "llvm/DebugInfo.h"
37 #include "llvm/IR/Constants.h"
38 #include "llvm/IR/Function.h"
39 #include "llvm/IR/InlineAsm.h"
40 #include "llvm/IR/Instructions.h"
41 #include "llvm/IR/IntrinsicInst.h"
42 #include "llvm/IR/Intrinsics.h"
43 #include "llvm/IR/LLVMContext.h"
44 #include "llvm/IR/Module.h"
45 #include "llvm/Support/Compiler.h"
46 #include "llvm/Support/Debug.h"
47 #include "llvm/Support/ErrorHandling.h"
48 #include "llvm/Support/Timer.h"
49 #include "llvm/Support/raw_ostream.h"
50 #include "llvm/Target/TargetInstrInfo.h"
51 #include "llvm/Target/TargetIntrinsicInfo.h"
52 #include "llvm/Target/TargetLibraryInfo.h"
53 #include "llvm/Target/TargetLowering.h"
54 #include "llvm/Target/TargetMachine.h"
55 #include "llvm/Target/TargetOptions.h"
56 #include "llvm/Target/TargetRegisterInfo.h"
57 #include "llvm/Target/TargetSubtargetInfo.h"
58 #include "llvm/Transforms/Utils/BasicBlockUtils.h"
62 STATISTIC(NumFastIselFailures, "Number of instructions fast isel failed on");
63 STATISTIC(NumFastIselSuccess, "Number of instructions fast isel selected");
64 STATISTIC(NumFastIselBlocks, "Number of blocks selected entirely by fast isel");
65 STATISTIC(NumDAGBlocks, "Number of blocks selected using DAG");
66 STATISTIC(NumDAGIselRetries,"Number of times dag isel has to try another path");
67 STATISTIC(NumEntryBlocks, "Number of entry blocks encountered");
68 STATISTIC(NumFastIselFailLowerArguments,
69 "Number of entry blocks where fast isel failed to lower arguments");
73 EnableFastISelVerbose2("fast-isel-verbose2", cl::Hidden,
74 cl::desc("Enable extra verbose messages in the \"fast\" "
75 "instruction selector"));
78 STATISTIC(NumFastIselFailRet,"Fast isel fails on Ret");
79 STATISTIC(NumFastIselFailBr,"Fast isel fails on Br");
80 STATISTIC(NumFastIselFailSwitch,"Fast isel fails on Switch");
81 STATISTIC(NumFastIselFailIndirectBr,"Fast isel fails on IndirectBr");
82 STATISTIC(NumFastIselFailInvoke,"Fast isel fails on Invoke");
83 STATISTIC(NumFastIselFailResume,"Fast isel fails on Resume");
84 STATISTIC(NumFastIselFailUnreachable,"Fast isel fails on Unreachable");
86 // Standard binary operators...
87 STATISTIC(NumFastIselFailAdd,"Fast isel fails on Add");
88 STATISTIC(NumFastIselFailFAdd,"Fast isel fails on FAdd");
89 STATISTIC(NumFastIselFailSub,"Fast isel fails on Sub");
90 STATISTIC(NumFastIselFailFSub,"Fast isel fails on FSub");
91 STATISTIC(NumFastIselFailMul,"Fast isel fails on Mul");
92 STATISTIC(NumFastIselFailFMul,"Fast isel fails on FMul");
93 STATISTIC(NumFastIselFailUDiv,"Fast isel fails on UDiv");
94 STATISTIC(NumFastIselFailSDiv,"Fast isel fails on SDiv");
95 STATISTIC(NumFastIselFailFDiv,"Fast isel fails on FDiv");
96 STATISTIC(NumFastIselFailURem,"Fast isel fails on URem");
97 STATISTIC(NumFastIselFailSRem,"Fast isel fails on SRem");
98 STATISTIC(NumFastIselFailFRem,"Fast isel fails on FRem");
100 // Logical operators...
101 STATISTIC(NumFastIselFailAnd,"Fast isel fails on And");
102 STATISTIC(NumFastIselFailOr,"Fast isel fails on Or");
103 STATISTIC(NumFastIselFailXor,"Fast isel fails on Xor");
105 // Memory instructions...
106 STATISTIC(NumFastIselFailAlloca,"Fast isel fails on Alloca");
107 STATISTIC(NumFastIselFailLoad,"Fast isel fails on Load");
108 STATISTIC(NumFastIselFailStore,"Fast isel fails on Store");
109 STATISTIC(NumFastIselFailAtomicCmpXchg,"Fast isel fails on AtomicCmpXchg");
110 STATISTIC(NumFastIselFailAtomicRMW,"Fast isel fails on AtomicRWM");
111 STATISTIC(NumFastIselFailFence,"Fast isel fails on Frence");
112 STATISTIC(NumFastIselFailGetElementPtr,"Fast isel fails on GetElementPtr");
114 // Convert instructions...
115 STATISTIC(NumFastIselFailTrunc,"Fast isel fails on Trunc");
116 STATISTIC(NumFastIselFailZExt,"Fast isel fails on ZExt");
117 STATISTIC(NumFastIselFailSExt,"Fast isel fails on SExt");
118 STATISTIC(NumFastIselFailFPTrunc,"Fast isel fails on FPTrunc");
119 STATISTIC(NumFastIselFailFPExt,"Fast isel fails on FPExt");
120 STATISTIC(NumFastIselFailFPToUI,"Fast isel fails on FPToUI");
121 STATISTIC(NumFastIselFailFPToSI,"Fast isel fails on FPToSI");
122 STATISTIC(NumFastIselFailUIToFP,"Fast isel fails on UIToFP");
123 STATISTIC(NumFastIselFailSIToFP,"Fast isel fails on SIToFP");
124 STATISTIC(NumFastIselFailIntToPtr,"Fast isel fails on IntToPtr");
125 STATISTIC(NumFastIselFailPtrToInt,"Fast isel fails on PtrToInt");
126 STATISTIC(NumFastIselFailBitCast,"Fast isel fails on BitCast");
128 // Other instructions...
129 STATISTIC(NumFastIselFailICmp,"Fast isel fails on ICmp");
130 STATISTIC(NumFastIselFailFCmp,"Fast isel fails on FCmp");
131 STATISTIC(NumFastIselFailPHI,"Fast isel fails on PHI");
132 STATISTIC(NumFastIselFailSelect,"Fast isel fails on Select");
133 STATISTIC(NumFastIselFailCall,"Fast isel fails on Call");
134 STATISTIC(NumFastIselFailShl,"Fast isel fails on Shl");
135 STATISTIC(NumFastIselFailLShr,"Fast isel fails on LShr");
136 STATISTIC(NumFastIselFailAShr,"Fast isel fails on AShr");
137 STATISTIC(NumFastIselFailVAArg,"Fast isel fails on VAArg");
138 STATISTIC(NumFastIselFailExtractElement,"Fast isel fails on ExtractElement");
139 STATISTIC(NumFastIselFailInsertElement,"Fast isel fails on InsertElement");
140 STATISTIC(NumFastIselFailShuffleVector,"Fast isel fails on ShuffleVector");
141 STATISTIC(NumFastIselFailExtractValue,"Fast isel fails on ExtractValue");
142 STATISTIC(NumFastIselFailInsertValue,"Fast isel fails on InsertValue");
143 STATISTIC(NumFastIselFailLandingPad,"Fast isel fails on LandingPad");
147 EnableFastISelVerbose("fast-isel-verbose", cl::Hidden,
148 cl::desc("Enable verbose messages in the \"fast\" "
149 "instruction selector"));
151 EnableFastISelAbort("fast-isel-abort", cl::Hidden,
152 cl::desc("Enable abort calls when \"fast\" instruction selection "
153 "fails to lower an instruction"));
155 EnableFastISelAbortArgs("fast-isel-abort-args", cl::Hidden,
156 cl::desc("Enable abort calls when \"fast\" instruction selection "
157 "fails to lower a formal argument"));
161 cl::desc("use Machine Branch Probability Info"),
162 cl::init(true), cl::Hidden);
166 ViewDAGCombine1("view-dag-combine1-dags", cl::Hidden,
167 cl::desc("Pop up a window to show dags before the first "
168 "dag combine pass"));
170 ViewLegalizeTypesDAGs("view-legalize-types-dags", cl::Hidden,
171 cl::desc("Pop up a window to show dags before legalize types"));
173 ViewLegalizeDAGs("view-legalize-dags", cl::Hidden,
174 cl::desc("Pop up a window to show dags before legalize"));
176 ViewDAGCombine2("view-dag-combine2-dags", cl::Hidden,
177 cl::desc("Pop up a window to show dags before the second "
178 "dag combine pass"));
180 ViewDAGCombineLT("view-dag-combine-lt-dags", cl::Hidden,
181 cl::desc("Pop up a window to show dags before the post legalize types"
182 " dag combine pass"));
184 ViewISelDAGs("view-isel-dags", cl::Hidden,
185 cl::desc("Pop up a window to show isel dags as they are selected"));
187 ViewSchedDAGs("view-sched-dags", cl::Hidden,
188 cl::desc("Pop up a window to show sched dags as they are processed"));
190 ViewSUnitDAGs("view-sunit-dags", cl::Hidden,
191 cl::desc("Pop up a window to show SUnit dags after they are processed"));
193 static const bool ViewDAGCombine1 = false,
194 ViewLegalizeTypesDAGs = false, ViewLegalizeDAGs = false,
195 ViewDAGCombine2 = false,
196 ViewDAGCombineLT = false,
197 ViewISelDAGs = false, ViewSchedDAGs = false,
198 ViewSUnitDAGs = false;
201 //===---------------------------------------------------------------------===//
203 /// RegisterScheduler class - Track the registration of instruction schedulers.
205 //===---------------------------------------------------------------------===//
206 MachinePassRegistry RegisterScheduler::Registry;
208 //===---------------------------------------------------------------------===//
210 /// ISHeuristic command line option for instruction schedulers.
212 //===---------------------------------------------------------------------===//
213 static cl::opt<RegisterScheduler::FunctionPassCtor, false,
214 RegisterPassParser<RegisterScheduler> >
215 ISHeuristic("pre-RA-sched",
216 cl::init(&createDefaultScheduler),
217 cl::desc("Instruction schedulers available (before register"
220 static RegisterScheduler
221 defaultListDAGScheduler("default", "Best scheduler for the target",
222 createDefaultScheduler);
225 //===--------------------------------------------------------------------===//
226 /// createDefaultScheduler - This creates an instruction scheduler appropriate
228 ScheduleDAGSDNodes* createDefaultScheduler(SelectionDAGISel *IS,
229 CodeGenOpt::Level OptLevel) {
230 const TargetLowering *TLI = IS->getTargetLowering();
231 const TargetSubtargetInfo &ST = IS->TM.getSubtarget<TargetSubtargetInfo>();
233 if (OptLevel == CodeGenOpt::None || ST.enableMachineScheduler() ||
234 TLI->getSchedulingPreference() == Sched::Source)
235 return createSourceListDAGScheduler(IS, OptLevel);
236 if (TLI->getSchedulingPreference() == Sched::RegPressure)
237 return createBURRListDAGScheduler(IS, OptLevel);
238 if (TLI->getSchedulingPreference() == Sched::Hybrid)
239 return createHybridListDAGScheduler(IS, OptLevel);
240 if (TLI->getSchedulingPreference() == Sched::VLIW)
241 return createVLIWDAGScheduler(IS, OptLevel);
242 assert(TLI->getSchedulingPreference() == Sched::ILP &&
243 "Unknown sched type!");
244 return createILPListDAGScheduler(IS, OptLevel);
248 // EmitInstrWithCustomInserter - This method should be implemented by targets
249 // that mark instructions with the 'usesCustomInserter' flag. These
250 // instructions are special in various ways, which require special support to
251 // insert. The specified MachineInstr is created but not inserted into any
252 // basic blocks, and this method is called to expand it into a sequence of
253 // instructions, potentially also creating new basic blocks and control flow.
254 // When new basic blocks are inserted and the edges from MBB to its successors
255 // are modified, the method should insert pairs of <OldSucc, NewSucc> into the
258 TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
259 MachineBasicBlock *MBB) const {
261 dbgs() << "If a target marks an instruction with "
262 "'usesCustomInserter', it must implement "
263 "TargetLowering::EmitInstrWithCustomInserter!";
268 void TargetLowering::AdjustInstrPostInstrSelection(MachineInstr *MI,
269 SDNode *Node) const {
270 assert(!MI->hasPostISelHook() &&
271 "If a target marks an instruction with 'hasPostISelHook', "
272 "it must implement TargetLowering::AdjustInstrPostInstrSelection!");
275 //===----------------------------------------------------------------------===//
276 // SelectionDAGISel code
277 //===----------------------------------------------------------------------===//
279 SelectionDAGISel::SelectionDAGISel(TargetMachine &tm,
280 CodeGenOpt::Level OL) :
281 MachineFunctionPass(ID), TM(tm),
282 FuncInfo(new FunctionLoweringInfo(TM)),
283 CurDAG(new SelectionDAG(tm, OL)),
284 SDB(new SelectionDAGBuilder(*CurDAG, *FuncInfo, OL)),
288 initializeGCModuleInfoPass(*PassRegistry::getPassRegistry());
289 initializeAliasAnalysisAnalysisGroup(*PassRegistry::getPassRegistry());
290 initializeBranchProbabilityInfoPass(*PassRegistry::getPassRegistry());
291 initializeTargetLibraryInfoPass(*PassRegistry::getPassRegistry());
294 SelectionDAGISel::~SelectionDAGISel() {
300 void SelectionDAGISel::getAnalysisUsage(AnalysisUsage &AU) const {
301 AU.addRequired<AliasAnalysis>();
302 AU.addPreserved<AliasAnalysis>();
303 AU.addRequired<GCModuleInfo>();
304 AU.addPreserved<GCModuleInfo>();
305 AU.addRequired<TargetLibraryInfo>();
306 if (UseMBPI && OptLevel != CodeGenOpt::None)
307 AU.addRequired<BranchProbabilityInfo>();
308 MachineFunctionPass::getAnalysisUsage(AU);
311 /// SplitCriticalSideEffectEdges - Look for critical edges with a PHI value that
312 /// may trap on it. In this case we have to split the edge so that the path
313 /// through the predecessor block that doesn't go to the phi block doesn't
314 /// execute the possibly trapping instruction.
316 /// This is required for correctness, so it must be done at -O0.
318 static void SplitCriticalSideEffectEdges(Function &Fn, Pass *SDISel) {
319 // Loop for blocks with phi nodes.
320 for (Function::iterator BB = Fn.begin(), E = Fn.end(); BB != E; ++BB) {
321 PHINode *PN = dyn_cast<PHINode>(BB->begin());
322 if (PN == 0) continue;
325 // For each block with a PHI node, check to see if any of the input values
326 // are potentially trapping constant expressions. Constant expressions are
327 // the only potentially trapping value that can occur as the argument to a
329 for (BasicBlock::iterator I = BB->begin(); (PN = dyn_cast<PHINode>(I)); ++I)
330 for (unsigned i = 0, e = PN->getNumIncomingValues(); i != e; ++i) {
331 ConstantExpr *CE = dyn_cast<ConstantExpr>(PN->getIncomingValue(i));
332 if (CE == 0 || !CE->canTrap()) continue;
334 // The only case we have to worry about is when the edge is critical.
335 // Since this block has a PHI Node, we assume it has multiple input
336 // edges: check to see if the pred has multiple successors.
337 BasicBlock *Pred = PN->getIncomingBlock(i);
338 if (Pred->getTerminator()->getNumSuccessors() == 1)
341 // Okay, we have to split this edge.
342 SplitCriticalEdge(Pred->getTerminator(),
343 GetSuccessorNumber(Pred, BB), SDISel, true);
349 bool SelectionDAGISel::runOnMachineFunction(MachineFunction &mf) {
350 // Do some sanity-checking on the command-line options.
351 assert((!EnableFastISelVerbose || TM.Options.EnableFastISel) &&
352 "-fast-isel-verbose requires -fast-isel");
353 assert((!EnableFastISelAbort || TM.Options.EnableFastISel) &&
354 "-fast-isel-abort requires -fast-isel");
356 const Function &Fn = *mf.getFunction();
357 const TargetInstrInfo &TII = *TM.getInstrInfo();
358 const TargetRegisterInfo &TRI = *TM.getRegisterInfo();
361 RegInfo = &MF->getRegInfo();
362 AA = &getAnalysis<AliasAnalysis>();
363 LibInfo = &getAnalysis<TargetLibraryInfo>();
364 TTI = getAnalysisIfAvailable<TargetTransformInfo>();
365 GFI = Fn.hasGC() ? &getAnalysis<GCModuleInfo>().getFunctionInfo(Fn) : 0;
367 TargetSubtargetInfo &ST =
368 const_cast<TargetSubtargetInfo&>(TM.getSubtarget<TargetSubtargetInfo>());
369 ST.resetSubtargetFeatures(MF);
370 TM.resetTargetOptions(MF);
372 DEBUG(dbgs() << "\n\n\n=== " << Fn.getName() << "\n");
374 SplitCriticalSideEffectEdges(const_cast<Function&>(Fn), this);
376 CurDAG->init(*MF, TTI);
377 FuncInfo->set(Fn, *MF);
379 if (UseMBPI && OptLevel != CodeGenOpt::None)
380 FuncInfo->BPI = &getAnalysis<BranchProbabilityInfo>();
384 SDB->init(GFI, *AA, LibInfo);
386 MF->setHasMSInlineAsm(false);
387 SelectAllBasicBlocks(Fn);
389 // If the first basic block in the function has live ins that need to be
390 // copied into vregs, emit the copies into the top of the block before
391 // emitting the code for the block.
392 MachineBasicBlock *EntryMBB = MF->begin();
393 RegInfo->EmitLiveInCopies(EntryMBB, TRI, TII);
395 DenseMap<unsigned, unsigned> LiveInMap;
396 if (!FuncInfo->ArgDbgValues.empty())
397 for (MachineRegisterInfo::livein_iterator LI = RegInfo->livein_begin(),
398 E = RegInfo->livein_end(); LI != E; ++LI)
400 LiveInMap.insert(std::make_pair(LI->first, LI->second));
402 // Insert DBG_VALUE instructions for function arguments to the entry block.
403 for (unsigned i = 0, e = FuncInfo->ArgDbgValues.size(); i != e; ++i) {
404 MachineInstr *MI = FuncInfo->ArgDbgValues[e-i-1];
405 bool hasFI = MI->getOperand(0).isFI();
406 unsigned Reg = hasFI ? TRI.getFrameRegister(*MF) : MI->getOperand(0).getReg();
407 if (TargetRegisterInfo::isPhysicalRegister(Reg))
408 EntryMBB->insert(EntryMBB->begin(), MI);
410 MachineInstr *Def = RegInfo->getVRegDef(Reg);
411 MachineBasicBlock::iterator InsertPos = Def;
412 // FIXME: VR def may not be in entry block.
413 Def->getParent()->insert(llvm::next(InsertPos), MI);
416 // If Reg is live-in then update debug info to track its copy in a vreg.
417 DenseMap<unsigned, unsigned>::iterator LDI = LiveInMap.find(Reg);
418 if (LDI != LiveInMap.end()) {
419 assert(!hasFI && "There's no handling of frame pointer updating here yet "
421 MachineInstr *Def = RegInfo->getVRegDef(LDI->second);
422 MachineBasicBlock::iterator InsertPos = Def;
423 const MDNode *Variable =
424 MI->getOperand(MI->getNumOperands()-1).getMetadata();
425 bool IsIndirect = MI->getOperand(1).isImm();
426 unsigned Offset = IsIndirect ? MI->getOperand(1).getImm() : 0;
427 // Def is never a terminator here, so it is ok to increment InsertPos.
428 BuildMI(*EntryMBB, ++InsertPos, MI->getDebugLoc(),
429 TII.get(TargetOpcode::DBG_VALUE),
431 LDI->second, Offset, Variable);
433 // If this vreg is directly copied into an exported register then
434 // that COPY instructions also need DBG_VALUE, if it is the only
435 // user of LDI->second.
436 MachineInstr *CopyUseMI = NULL;
437 for (MachineRegisterInfo::use_iterator
438 UI = RegInfo->use_begin(LDI->second);
439 MachineInstr *UseMI = UI.skipInstruction();) {
440 if (UseMI->isDebugValue()) continue;
441 if (UseMI->isCopy() && !CopyUseMI && UseMI->getParent() == EntryMBB) {
442 CopyUseMI = UseMI; continue;
444 // Otherwise this is another use or second copy use.
445 CopyUseMI = NULL; break;
448 MachineInstr *NewMI =
449 BuildMI(*MF, CopyUseMI->getDebugLoc(),
450 TII.get(TargetOpcode::DBG_VALUE),
452 CopyUseMI->getOperand(0).getReg(),
454 MachineBasicBlock::iterator Pos = CopyUseMI;
455 EntryMBB->insertAfter(Pos, NewMI);
460 // Determine if there are any calls in this machine function.
461 MachineFrameInfo *MFI = MF->getFrameInfo();
462 for (MachineFunction::const_iterator I = MF->begin(), E = MF->end(); I != E;
465 if (MFI->hasCalls() && MF->hasMSInlineAsm())
468 const MachineBasicBlock *MBB = I;
469 for (MachineBasicBlock::const_iterator II = MBB->begin(), IE = MBB->end();
471 const MCInstrDesc &MCID = TM.getInstrInfo()->get(II->getOpcode());
472 if ((MCID.isCall() && !MCID.isReturn()) ||
473 II->isStackAligningInlineAsm()) {
474 MFI->setHasCalls(true);
476 if (II->isMSInlineAsm()) {
477 MF->setHasMSInlineAsm(true);
482 // Determine if there is a call to setjmp in the machine function.
483 MF->setExposesReturnsTwice(Fn.callsFunctionThatReturnsTwice());
485 // Replace forward-declared registers with the registers containing
486 // the desired value.
487 MachineRegisterInfo &MRI = MF->getRegInfo();
488 for (DenseMap<unsigned, unsigned>::iterator
489 I = FuncInfo->RegFixups.begin(), E = FuncInfo->RegFixups.end();
491 unsigned From = I->first;
492 unsigned To = I->second;
493 // If To is also scheduled to be replaced, find what its ultimate
496 DenseMap<unsigned, unsigned>::iterator J = FuncInfo->RegFixups.find(To);
500 // Make sure the new register has a sufficiently constrained register class.
501 if (TargetRegisterInfo::isVirtualRegister(From) &&
502 TargetRegisterInfo::isVirtualRegister(To))
503 MRI.constrainRegClass(To, MRI.getRegClass(From));
505 MRI.replaceRegWith(From, To);
508 // Freeze the set of reserved registers now that MachineFrameInfo has been
509 // set up. All the information required by getReservedRegs() should be
511 MRI.freezeReservedRegs(*MF);
513 // Release function-specific state. SDB and CurDAG are already cleared
520 void SelectionDAGISel::SelectBasicBlock(BasicBlock::const_iterator Begin,
521 BasicBlock::const_iterator End,
523 // Lower all of the non-terminator instructions. If a call is emitted
524 // as a tail call, cease emitting nodes for this block. Terminators
525 // are handled below.
526 for (BasicBlock::const_iterator I = Begin; I != End && !SDB->HasTailCall; ++I)
529 // Make sure the root of the DAG is up-to-date.
530 CurDAG->setRoot(SDB->getControlRoot());
531 HadTailCall = SDB->HasTailCall;
534 // Final step, emit the lowered DAG as machine code.
538 void SelectionDAGISel::ComputeLiveOutVRegInfo() {
539 SmallPtrSet<SDNode*, 128> VisitedNodes;
540 SmallVector<SDNode*, 128> Worklist;
542 Worklist.push_back(CurDAG->getRoot().getNode());
548 SDNode *N = Worklist.pop_back_val();
550 // If we've already seen this node, ignore it.
551 if (!VisitedNodes.insert(N))
554 // Otherwise, add all chain operands to the worklist.
555 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
556 if (N->getOperand(i).getValueType() == MVT::Other)
557 Worklist.push_back(N->getOperand(i).getNode());
559 // If this is a CopyToReg with a vreg dest, process it.
560 if (N->getOpcode() != ISD::CopyToReg)
563 unsigned DestReg = cast<RegisterSDNode>(N->getOperand(1))->getReg();
564 if (!TargetRegisterInfo::isVirtualRegister(DestReg))
567 // Ignore non-scalar or non-integer values.
568 SDValue Src = N->getOperand(2);
569 EVT SrcVT = Src.getValueType();
570 if (!SrcVT.isInteger() || SrcVT.isVector())
573 unsigned NumSignBits = CurDAG->ComputeNumSignBits(Src);
574 CurDAG->ComputeMaskedBits(Src, KnownZero, KnownOne);
575 FuncInfo->AddLiveOutRegInfo(DestReg, NumSignBits, KnownZero, KnownOne);
576 } while (!Worklist.empty());
579 void SelectionDAGISel::CodeGenAndEmitDAG() {
580 std::string GroupName;
581 if (TimePassesIsEnabled)
582 GroupName = "Instruction Selection and Scheduling";
583 std::string BlockName;
584 int BlockNumber = -1;
587 if (ViewDAGCombine1 || ViewLegalizeTypesDAGs || ViewLegalizeDAGs ||
588 ViewDAGCombine2 || ViewDAGCombineLT || ViewISelDAGs || ViewSchedDAGs ||
592 BlockNumber = FuncInfo->MBB->getNumber();
593 BlockName = MF->getName().str() + ":" +
594 FuncInfo->MBB->getBasicBlock()->getName().str();
596 DEBUG(dbgs() << "Initial selection DAG: BB#" << BlockNumber
597 << " '" << BlockName << "'\n"; CurDAG->dump());
599 if (ViewDAGCombine1) CurDAG->viewGraph("dag-combine1 input for " + BlockName);
601 // Run the DAG combiner in pre-legalize mode.
603 NamedRegionTimer T("DAG Combining 1", GroupName, TimePassesIsEnabled);
604 CurDAG->Combine(BeforeLegalizeTypes, *AA, OptLevel);
607 DEBUG(dbgs() << "Optimized lowered selection DAG: BB#" << BlockNumber
608 << " '" << BlockName << "'\n"; CurDAG->dump());
610 // Second step, hack on the DAG until it only uses operations and types that
611 // the target supports.
612 if (ViewLegalizeTypesDAGs) CurDAG->viewGraph("legalize-types input for " +
617 NamedRegionTimer T("Type Legalization", GroupName, TimePassesIsEnabled);
618 Changed = CurDAG->LegalizeTypes();
621 DEBUG(dbgs() << "Type-legalized selection DAG: BB#" << BlockNumber
622 << " '" << BlockName << "'\n"; CurDAG->dump());
625 if (ViewDAGCombineLT)
626 CurDAG->viewGraph("dag-combine-lt input for " + BlockName);
628 // Run the DAG combiner in post-type-legalize mode.
630 NamedRegionTimer T("DAG Combining after legalize types", GroupName,
631 TimePassesIsEnabled);
632 CurDAG->Combine(AfterLegalizeTypes, *AA, OptLevel);
635 DEBUG(dbgs() << "Optimized type-legalized selection DAG: BB#" << BlockNumber
636 << " '" << BlockName << "'\n"; CurDAG->dump());
641 NamedRegionTimer T("Vector Legalization", GroupName, TimePassesIsEnabled);
642 Changed = CurDAG->LegalizeVectors();
647 NamedRegionTimer T("Type Legalization 2", GroupName, TimePassesIsEnabled);
648 CurDAG->LegalizeTypes();
651 if (ViewDAGCombineLT)
652 CurDAG->viewGraph("dag-combine-lv input for " + BlockName);
654 // Run the DAG combiner in post-type-legalize mode.
656 NamedRegionTimer T("DAG Combining after legalize vectors", GroupName,
657 TimePassesIsEnabled);
658 CurDAG->Combine(AfterLegalizeVectorOps, *AA, OptLevel);
661 DEBUG(dbgs() << "Optimized vector-legalized selection DAG: BB#"
662 << BlockNumber << " '" << BlockName << "'\n"; CurDAG->dump());
665 if (ViewLegalizeDAGs) CurDAG->viewGraph("legalize input for " + BlockName);
668 NamedRegionTimer T("DAG Legalization", GroupName, TimePassesIsEnabled);
672 DEBUG(dbgs() << "Legalized selection DAG: BB#" << BlockNumber
673 << " '" << BlockName << "'\n"; CurDAG->dump());
675 if (ViewDAGCombine2) CurDAG->viewGraph("dag-combine2 input for " + BlockName);
677 // Run the DAG combiner in post-legalize mode.
679 NamedRegionTimer T("DAG Combining 2", GroupName, TimePassesIsEnabled);
680 CurDAG->Combine(AfterLegalizeDAG, *AA, OptLevel);
683 DEBUG(dbgs() << "Optimized legalized selection DAG: BB#" << BlockNumber
684 << " '" << BlockName << "'\n"; CurDAG->dump());
686 if (OptLevel != CodeGenOpt::None)
687 ComputeLiveOutVRegInfo();
689 if (ViewISelDAGs) CurDAG->viewGraph("isel input for " + BlockName);
691 // Third, instruction select all of the operations to machine code, adding the
692 // code to the MachineBasicBlock.
694 NamedRegionTimer T("Instruction Selection", GroupName, TimePassesIsEnabled);
695 DoInstructionSelection();
698 DEBUG(dbgs() << "Selected selection DAG: BB#" << BlockNumber
699 << " '" << BlockName << "'\n"; CurDAG->dump());
701 if (ViewSchedDAGs) CurDAG->viewGraph("scheduler input for " + BlockName);
703 // Schedule machine code.
704 ScheduleDAGSDNodes *Scheduler = CreateScheduler();
706 NamedRegionTimer T("Instruction Scheduling", GroupName,
707 TimePassesIsEnabled);
708 Scheduler->Run(CurDAG, FuncInfo->MBB);
711 if (ViewSUnitDAGs) Scheduler->viewGraph();
713 // Emit machine code to BB. This can change 'BB' to the last block being
715 MachineBasicBlock *FirstMBB = FuncInfo->MBB, *LastMBB;
717 NamedRegionTimer T("Instruction Creation", GroupName, TimePassesIsEnabled);
719 // FuncInfo->InsertPt is passed by reference and set to the end of the
720 // scheduled instructions.
721 LastMBB = FuncInfo->MBB = Scheduler->EmitSchedule(FuncInfo->InsertPt);
724 // If the block was split, make sure we update any references that are used to
725 // update PHI nodes later on.
726 if (FirstMBB != LastMBB)
727 SDB->UpdateSplitBlock(FirstMBB, LastMBB);
729 // Free the scheduler state.
731 NamedRegionTimer T("Instruction Scheduling Cleanup", GroupName,
732 TimePassesIsEnabled);
736 // Free the SelectionDAG state, now that we're finished with it.
741 /// ISelUpdater - helper class to handle updates of the instruction selection
743 class ISelUpdater : public SelectionDAG::DAGUpdateListener {
744 SelectionDAG::allnodes_iterator &ISelPosition;
746 ISelUpdater(SelectionDAG &DAG, SelectionDAG::allnodes_iterator &isp)
747 : SelectionDAG::DAGUpdateListener(DAG), ISelPosition(isp) {}
749 /// NodeDeleted - Handle nodes deleted from the graph. If the node being
750 /// deleted is the current ISelPosition node, update ISelPosition.
752 virtual void NodeDeleted(SDNode *N, SDNode *E) {
753 if (ISelPosition == SelectionDAG::allnodes_iterator(N))
757 } // end anonymous namespace
759 void SelectionDAGISel::DoInstructionSelection() {
760 DEBUG(dbgs() << "===== Instruction selection begins: BB#"
761 << FuncInfo->MBB->getNumber()
762 << " '" << FuncInfo->MBB->getName() << "'\n");
766 // Select target instructions for the DAG.
768 // Number all nodes with a topological order and set DAGSize.
769 DAGSize = CurDAG->AssignTopologicalOrder();
771 // Create a dummy node (which is not added to allnodes), that adds
772 // a reference to the root node, preventing it from being deleted,
773 // and tracking any changes of the root.
774 HandleSDNode Dummy(CurDAG->getRoot());
775 SelectionDAG::allnodes_iterator ISelPosition (CurDAG->getRoot().getNode());
778 // Make sure that ISelPosition gets properly updated when nodes are deleted
779 // in calls made from this function.
780 ISelUpdater ISU(*CurDAG, ISelPosition);
782 // The AllNodes list is now topological-sorted. Visit the
783 // nodes by starting at the end of the list (the root of the
784 // graph) and preceding back toward the beginning (the entry
786 while (ISelPosition != CurDAG->allnodes_begin()) {
787 SDNode *Node = --ISelPosition;
788 // Skip dead nodes. DAGCombiner is expected to eliminate all dead nodes,
789 // but there are currently some corner cases that it misses. Also, this
790 // makes it theoretically possible to disable the DAGCombiner.
791 if (Node->use_empty())
794 SDNode *ResNode = Select(Node);
796 // FIXME: This is pretty gross. 'Select' should be changed to not return
797 // anything at all and this code should be nuked with a tactical strike.
799 // If node should not be replaced, continue with the next one.
800 if (ResNode == Node || Node->getOpcode() == ISD::DELETED_NODE)
804 ReplaceUses(Node, ResNode);
807 // If after the replacement this node is not used any more,
808 // remove this dead node.
809 if (Node->use_empty()) // Don't delete EntryToken, etc.
810 CurDAG->RemoveDeadNode(Node);
813 CurDAG->setRoot(Dummy.getValue());
816 DEBUG(dbgs() << "===== Instruction selection ends:\n");
818 PostprocessISelDAG();
821 /// PrepareEHLandingPad - Emit an EH_LABEL, set up live-in registers, and
822 /// do other setup for EH landing-pad blocks.
823 void SelectionDAGISel::PrepareEHLandingPad() {
824 MachineBasicBlock *MBB = FuncInfo->MBB;
826 // Add a label to mark the beginning of the landing pad. Deletion of the
827 // landing pad can thus be detected via the MachineModuleInfo.
828 MCSymbol *Label = MF->getMMI().addLandingPad(MBB);
830 // Assign the call site to the landing pad's begin label.
831 MF->getMMI().setCallSiteLandingPad(Label, SDB->LPadToCallSiteMap[MBB]);
833 const MCInstrDesc &II = TM.getInstrInfo()->get(TargetOpcode::EH_LABEL);
834 BuildMI(*MBB, FuncInfo->InsertPt, SDB->getCurDebugLoc(), II)
837 // Mark exception register as live in.
838 const TargetLowering *TLI = getTargetLowering();
839 const TargetRegisterClass *PtrRC = TLI->getRegClassFor(TLI->getPointerTy());
840 if (unsigned Reg = TLI->getExceptionPointerRegister())
841 FuncInfo->ExceptionPointerVirtReg = MBB->addLiveIn(Reg, PtrRC);
843 // Mark exception selector register as live in.
844 if (unsigned Reg = TLI->getExceptionSelectorRegister())
845 FuncInfo->ExceptionSelectorVirtReg = MBB->addLiveIn(Reg, PtrRC);
848 /// isFoldedOrDeadInstruction - Return true if the specified instruction is
849 /// side-effect free and is either dead or folded into a generated instruction.
850 /// Return false if it needs to be emitted.
851 static bool isFoldedOrDeadInstruction(const Instruction *I,
852 FunctionLoweringInfo *FuncInfo) {
853 return !I->mayWriteToMemory() && // Side-effecting instructions aren't folded.
854 !isa<TerminatorInst>(I) && // Terminators aren't folded.
855 !isa<DbgInfoIntrinsic>(I) && // Debug instructions aren't folded.
856 !isa<LandingPadInst>(I) && // Landingpad instructions aren't folded.
857 !FuncInfo->isExportedInst(I); // Exported instrs must be computed.
861 // Collect per Instruction statistics for fast-isel misses. Only those
862 // instructions that cause the bail are accounted for. It does not account for
863 // instructions higher in the block. Thus, summing the per instructions stats
864 // will not add up to what is reported by NumFastIselFailures.
865 static void collectFailStats(const Instruction *I) {
866 switch (I->getOpcode()) {
867 default: assert (0 && "<Invalid operator> ");
870 case Instruction::Ret: NumFastIselFailRet++; return;
871 case Instruction::Br: NumFastIselFailBr++; return;
872 case Instruction::Switch: NumFastIselFailSwitch++; return;
873 case Instruction::IndirectBr: NumFastIselFailIndirectBr++; return;
874 case Instruction::Invoke: NumFastIselFailInvoke++; return;
875 case Instruction::Resume: NumFastIselFailResume++; return;
876 case Instruction::Unreachable: NumFastIselFailUnreachable++; return;
878 // Standard binary operators...
879 case Instruction::Add: NumFastIselFailAdd++; return;
880 case Instruction::FAdd: NumFastIselFailFAdd++; return;
881 case Instruction::Sub: NumFastIselFailSub++; return;
882 case Instruction::FSub: NumFastIselFailFSub++; return;
883 case Instruction::Mul: NumFastIselFailMul++; return;
884 case Instruction::FMul: NumFastIselFailFMul++; return;
885 case Instruction::UDiv: NumFastIselFailUDiv++; return;
886 case Instruction::SDiv: NumFastIselFailSDiv++; return;
887 case Instruction::FDiv: NumFastIselFailFDiv++; return;
888 case Instruction::URem: NumFastIselFailURem++; return;
889 case Instruction::SRem: NumFastIselFailSRem++; return;
890 case Instruction::FRem: NumFastIselFailFRem++; return;
892 // Logical operators...
893 case Instruction::And: NumFastIselFailAnd++; return;
894 case Instruction::Or: NumFastIselFailOr++; return;
895 case Instruction::Xor: NumFastIselFailXor++; return;
897 // Memory instructions...
898 case Instruction::Alloca: NumFastIselFailAlloca++; return;
899 case Instruction::Load: NumFastIselFailLoad++; return;
900 case Instruction::Store: NumFastIselFailStore++; return;
901 case Instruction::AtomicCmpXchg: NumFastIselFailAtomicCmpXchg++; return;
902 case Instruction::AtomicRMW: NumFastIselFailAtomicRMW++; return;
903 case Instruction::Fence: NumFastIselFailFence++; return;
904 case Instruction::GetElementPtr: NumFastIselFailGetElementPtr++; return;
906 // Convert instructions...
907 case Instruction::Trunc: NumFastIselFailTrunc++; return;
908 case Instruction::ZExt: NumFastIselFailZExt++; return;
909 case Instruction::SExt: NumFastIselFailSExt++; return;
910 case Instruction::FPTrunc: NumFastIselFailFPTrunc++; return;
911 case Instruction::FPExt: NumFastIselFailFPExt++; return;
912 case Instruction::FPToUI: NumFastIselFailFPToUI++; return;
913 case Instruction::FPToSI: NumFastIselFailFPToSI++; return;
914 case Instruction::UIToFP: NumFastIselFailUIToFP++; return;
915 case Instruction::SIToFP: NumFastIselFailSIToFP++; return;
916 case Instruction::IntToPtr: NumFastIselFailIntToPtr++; return;
917 case Instruction::PtrToInt: NumFastIselFailPtrToInt++; return;
918 case Instruction::BitCast: NumFastIselFailBitCast++; return;
920 // Other instructions...
921 case Instruction::ICmp: NumFastIselFailICmp++; return;
922 case Instruction::FCmp: NumFastIselFailFCmp++; return;
923 case Instruction::PHI: NumFastIselFailPHI++; return;
924 case Instruction::Select: NumFastIselFailSelect++; return;
925 case Instruction::Call: NumFastIselFailCall++; return;
926 case Instruction::Shl: NumFastIselFailShl++; return;
927 case Instruction::LShr: NumFastIselFailLShr++; return;
928 case Instruction::AShr: NumFastIselFailAShr++; return;
929 case Instruction::VAArg: NumFastIselFailVAArg++; return;
930 case Instruction::ExtractElement: NumFastIselFailExtractElement++; return;
931 case Instruction::InsertElement: NumFastIselFailInsertElement++; return;
932 case Instruction::ShuffleVector: NumFastIselFailShuffleVector++; return;
933 case Instruction::ExtractValue: NumFastIselFailExtractValue++; return;
934 case Instruction::InsertValue: NumFastIselFailInsertValue++; return;
935 case Instruction::LandingPad: NumFastIselFailLandingPad++; return;
940 void SelectionDAGISel::SelectAllBasicBlocks(const Function &Fn) {
941 // Initialize the Fast-ISel state, if needed.
942 FastISel *FastIS = 0;
943 if (TM.Options.EnableFastISel)
944 FastIS = getTargetLowering()->createFastISel(*FuncInfo, LibInfo);
946 // Iterate over all basic blocks in the function.
947 ReversePostOrderTraversal<const Function*> RPOT(&Fn);
948 for (ReversePostOrderTraversal<const Function*>::rpo_iterator
949 I = RPOT.begin(), E = RPOT.end(); I != E; ++I) {
950 const BasicBlock *LLVMBB = *I;
952 if (OptLevel != CodeGenOpt::None) {
953 bool AllPredsVisited = true;
954 for (const_pred_iterator PI = pred_begin(LLVMBB), PE = pred_end(LLVMBB);
956 if (!FuncInfo->VisitedBBs.count(*PI)) {
957 AllPredsVisited = false;
962 if (AllPredsVisited) {
963 for (BasicBlock::const_iterator I = LLVMBB->begin();
964 const PHINode *PN = dyn_cast<PHINode>(I); ++I)
965 FuncInfo->ComputePHILiveOutRegInfo(PN);
967 for (BasicBlock::const_iterator I = LLVMBB->begin();
968 const PHINode *PN = dyn_cast<PHINode>(I); ++I)
969 FuncInfo->InvalidatePHILiveOutRegInfo(PN);
972 FuncInfo->VisitedBBs.insert(LLVMBB);
975 BasicBlock::const_iterator const Begin = LLVMBB->getFirstNonPHI();
976 BasicBlock::const_iterator const End = LLVMBB->end();
977 BasicBlock::const_iterator BI = End;
979 FuncInfo->MBB = FuncInfo->MBBMap[LLVMBB];
980 FuncInfo->InsertPt = FuncInfo->MBB->getFirstNonPHI();
982 // Setup an EH landing-pad block.
983 FuncInfo->ExceptionPointerVirtReg = 0;
984 FuncInfo->ExceptionSelectorVirtReg = 0;
985 if (FuncInfo->MBB->isLandingPad())
986 PrepareEHLandingPad();
988 // Before doing SelectionDAG ISel, see if FastISel has been requested.
990 FastIS->startNewBlock();
992 // Emit code for any incoming arguments. This must happen before
993 // beginning FastISel on the entry block.
994 if (LLVMBB == &Fn.getEntryBlock()) {
997 // Lower any arguments needed in this block if this is the entry block.
998 if (!FastIS->LowerArguments()) {
999 // Fast isel failed to lower these arguments
1000 ++NumFastIselFailLowerArguments;
1001 if (EnableFastISelAbortArgs)
1002 llvm_unreachable("FastISel didn't lower all arguments");
1004 // Use SelectionDAG argument lowering
1006 CurDAG->setRoot(SDB->getControlRoot());
1008 CodeGenAndEmitDAG();
1011 // If we inserted any instructions at the beginning, make a note of
1012 // where they are, so we can be sure to emit subsequent instructions
1014 if (FuncInfo->InsertPt != FuncInfo->MBB->begin())
1015 FastIS->setLastLocalValue(llvm::prior(FuncInfo->InsertPt));
1017 FastIS->setLastLocalValue(0);
1020 unsigned NumFastIselRemaining = std::distance(Begin, End);
1021 // Do FastISel on as many instructions as possible.
1022 for (; BI != Begin; --BI) {
1023 const Instruction *Inst = llvm::prior(BI);
1025 // If we no longer require this instruction, skip it.
1026 if (isFoldedOrDeadInstruction(Inst, FuncInfo)) {
1027 --NumFastIselRemaining;
1031 // Bottom-up: reset the insert pos at the top, after any local-value
1033 FastIS->recomputeInsertPt();
1035 // Try to select the instruction with FastISel.
1036 if (FastIS->SelectInstruction(Inst)) {
1037 --NumFastIselRemaining;
1038 ++NumFastIselSuccess;
1039 // If fast isel succeeded, skip over all the folded instructions, and
1040 // then see if there is a load right before the selected instructions.
1041 // Try to fold the load if so.
1042 const Instruction *BeforeInst = Inst;
1043 while (BeforeInst != Begin) {
1044 BeforeInst = llvm::prior(BasicBlock::const_iterator(BeforeInst));
1045 if (!isFoldedOrDeadInstruction(BeforeInst, FuncInfo))
1048 if (BeforeInst != Inst && isa<LoadInst>(BeforeInst) &&
1049 BeforeInst->hasOneUse() &&
1050 FastIS->tryToFoldLoad(cast<LoadInst>(BeforeInst), Inst)) {
1051 // If we succeeded, don't re-select the load.
1052 BI = llvm::next(BasicBlock::const_iterator(BeforeInst));
1053 --NumFastIselRemaining;
1054 ++NumFastIselSuccess;
1060 if (EnableFastISelVerbose2)
1061 collectFailStats(Inst);
1064 // Then handle certain instructions as single-LLVM-Instruction blocks.
1065 if (isa<CallInst>(Inst)) {
1067 if (EnableFastISelVerbose || EnableFastISelAbort) {
1068 dbgs() << "FastISel missed call: ";
1072 if (!Inst->getType()->isVoidTy() && !Inst->use_empty()) {
1073 unsigned &R = FuncInfo->ValueMap[Inst];
1075 R = FuncInfo->CreateRegs(Inst->getType());
1078 bool HadTailCall = false;
1079 MachineBasicBlock::iterator SavedInsertPt = FuncInfo->InsertPt;
1080 SelectBasicBlock(Inst, BI, HadTailCall);
1082 // If the call was emitted as a tail call, we're done with the block.
1083 // We also need to delete any previously emitted instructions.
1085 FastIS->removeDeadCode(SavedInsertPt, FuncInfo->MBB->end());
1090 // Recompute NumFastIselRemaining as Selection DAG instruction
1091 // selection may have handled the call, input args, etc.
1092 unsigned RemainingNow = std::distance(Begin, BI);
1093 NumFastIselFailures += NumFastIselRemaining - RemainingNow;
1094 NumFastIselRemaining = RemainingNow;
1098 if (isa<TerminatorInst>(Inst) && !isa<BranchInst>(Inst)) {
1099 // Don't abort, and use a different message for terminator misses.
1100 NumFastIselFailures += NumFastIselRemaining;
1101 if (EnableFastISelVerbose || EnableFastISelAbort) {
1102 dbgs() << "FastISel missed terminator: ";
1106 NumFastIselFailures += NumFastIselRemaining;
1107 if (EnableFastISelVerbose || EnableFastISelAbort) {
1108 dbgs() << "FastISel miss: ";
1111 if (EnableFastISelAbort)
1112 // The "fast" selector couldn't handle something and bailed.
1113 // For the purpose of debugging, just abort.
1114 llvm_unreachable("FastISel didn't select the entire block");
1119 FastIS->recomputeInsertPt();
1121 // Lower any arguments needed in this block if this is the entry block.
1122 if (LLVMBB == &Fn.getEntryBlock()) {
1131 ++NumFastIselBlocks;
1134 // Run SelectionDAG instruction selection on the remainder of the block
1135 // not handled by FastISel. If FastISel is not run, this is the entire
1138 SelectBasicBlock(Begin, BI, HadTailCall);
1142 FuncInfo->PHINodesToUpdate.clear();
1146 SDB->clearDanglingDebugInfo();
1150 SelectionDAGISel::FinishBasicBlock() {
1152 DEBUG(dbgs() << "Total amount of phi nodes to update: "
1153 << FuncInfo->PHINodesToUpdate.size() << "\n";
1154 for (unsigned i = 0, e = FuncInfo->PHINodesToUpdate.size(); i != e; ++i)
1155 dbgs() << "Node " << i << " : ("
1156 << FuncInfo->PHINodesToUpdate[i].first
1157 << ", " << FuncInfo->PHINodesToUpdate[i].second << ")\n");
1159 // Next, now that we know what the last MBB the LLVM BB expanded is, update
1160 // PHI nodes in successors.
1161 if (SDB->SwitchCases.empty() &&
1162 SDB->JTCases.empty() &&
1163 SDB->BitTestCases.empty()) {
1164 for (unsigned i = 0, e = FuncInfo->PHINodesToUpdate.size(); i != e; ++i) {
1165 MachineInstrBuilder PHI(*MF, FuncInfo->PHINodesToUpdate[i].first);
1166 assert(PHI->isPHI() &&
1167 "This is not a machine PHI node that we are updating!");
1168 if (!FuncInfo->MBB->isSuccessor(PHI->getParent()))
1170 PHI.addReg(FuncInfo->PHINodesToUpdate[i].second).addMBB(FuncInfo->MBB);
1175 for (unsigned i = 0, e = SDB->BitTestCases.size(); i != e; ++i) {
1176 // Lower header first, if it wasn't already lowered
1177 if (!SDB->BitTestCases[i].Emitted) {
1178 // Set the current basic block to the mbb we wish to insert the code into
1179 FuncInfo->MBB = SDB->BitTestCases[i].Parent;
1180 FuncInfo->InsertPt = FuncInfo->MBB->end();
1182 SDB->visitBitTestHeader(SDB->BitTestCases[i], FuncInfo->MBB);
1183 CurDAG->setRoot(SDB->getRoot());
1185 CodeGenAndEmitDAG();
1188 uint32_t UnhandledWeight = 0;
1189 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size(); j != ej; ++j)
1190 UnhandledWeight += SDB->BitTestCases[i].Cases[j].ExtraWeight;
1192 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size(); j != ej; ++j) {
1193 UnhandledWeight -= SDB->BitTestCases[i].Cases[j].ExtraWeight;
1194 // Set the current basic block to the mbb we wish to insert the code into
1195 FuncInfo->MBB = SDB->BitTestCases[i].Cases[j].ThisBB;
1196 FuncInfo->InsertPt = FuncInfo->MBB->end();
1199 SDB->visitBitTestCase(SDB->BitTestCases[i],
1200 SDB->BitTestCases[i].Cases[j+1].ThisBB,
1202 SDB->BitTestCases[i].Reg,
1203 SDB->BitTestCases[i].Cases[j],
1206 SDB->visitBitTestCase(SDB->BitTestCases[i],
1207 SDB->BitTestCases[i].Default,
1209 SDB->BitTestCases[i].Reg,
1210 SDB->BitTestCases[i].Cases[j],
1214 CurDAG->setRoot(SDB->getRoot());
1216 CodeGenAndEmitDAG();
1220 for (unsigned pi = 0, pe = FuncInfo->PHINodesToUpdate.size();
1222 MachineInstrBuilder PHI(*MF, FuncInfo->PHINodesToUpdate[pi].first);
1223 MachineBasicBlock *PHIBB = PHI->getParent();
1224 assert(PHI->isPHI() &&
1225 "This is not a machine PHI node that we are updating!");
1226 // This is "default" BB. We have two jumps to it. From "header" BB and
1227 // from last "case" BB.
1228 if (PHIBB == SDB->BitTestCases[i].Default)
1229 PHI.addReg(FuncInfo->PHINodesToUpdate[pi].second)
1230 .addMBB(SDB->BitTestCases[i].Parent)
1231 .addReg(FuncInfo->PHINodesToUpdate[pi].second)
1232 .addMBB(SDB->BitTestCases[i].Cases.back().ThisBB);
1233 // One of "cases" BB.
1234 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size();
1236 MachineBasicBlock* cBB = SDB->BitTestCases[i].Cases[j].ThisBB;
1237 if (cBB->isSuccessor(PHIBB))
1238 PHI.addReg(FuncInfo->PHINodesToUpdate[pi].second).addMBB(cBB);
1242 SDB->BitTestCases.clear();
1244 // If the JumpTable record is filled in, then we need to emit a jump table.
1245 // Updating the PHI nodes is tricky in this case, since we need to determine
1246 // whether the PHI is a successor of the range check MBB or the jump table MBB
1247 for (unsigned i = 0, e = SDB->JTCases.size(); i != e; ++i) {
1248 // Lower header first, if it wasn't already lowered
1249 if (!SDB->JTCases[i].first.Emitted) {
1250 // Set the current basic block to the mbb we wish to insert the code into
1251 FuncInfo->MBB = SDB->JTCases[i].first.HeaderBB;
1252 FuncInfo->InsertPt = FuncInfo->MBB->end();
1254 SDB->visitJumpTableHeader(SDB->JTCases[i].second, SDB->JTCases[i].first,
1256 CurDAG->setRoot(SDB->getRoot());
1258 CodeGenAndEmitDAG();
1261 // Set the current basic block to the mbb we wish to insert the code into
1262 FuncInfo->MBB = SDB->JTCases[i].second.MBB;
1263 FuncInfo->InsertPt = FuncInfo->MBB->end();
1265 SDB->visitJumpTable(SDB->JTCases[i].second);
1266 CurDAG->setRoot(SDB->getRoot());
1268 CodeGenAndEmitDAG();
1271 for (unsigned pi = 0, pe = FuncInfo->PHINodesToUpdate.size();
1273 MachineInstrBuilder PHI(*MF, FuncInfo->PHINodesToUpdate[pi].first);
1274 MachineBasicBlock *PHIBB = PHI->getParent();
1275 assert(PHI->isPHI() &&
1276 "This is not a machine PHI node that we are updating!");
1277 // "default" BB. We can go there only from header BB.
1278 if (PHIBB == SDB->JTCases[i].second.Default)
1279 PHI.addReg(FuncInfo->PHINodesToUpdate[pi].second)
1280 .addMBB(SDB->JTCases[i].first.HeaderBB);
1281 // JT BB. Just iterate over successors here
1282 if (FuncInfo->MBB->isSuccessor(PHIBB))
1283 PHI.addReg(FuncInfo->PHINodesToUpdate[pi].second).addMBB(FuncInfo->MBB);
1286 SDB->JTCases.clear();
1288 // If the switch block involved a branch to one of the actual successors, we
1289 // need to update PHI nodes in that block.
1290 for (unsigned i = 0, e = FuncInfo->PHINodesToUpdate.size(); i != e; ++i) {
1291 MachineInstrBuilder PHI(*MF, FuncInfo->PHINodesToUpdate[i].first);
1292 assert(PHI->isPHI() &&
1293 "This is not a machine PHI node that we are updating!");
1294 if (FuncInfo->MBB->isSuccessor(PHI->getParent()))
1295 PHI.addReg(FuncInfo->PHINodesToUpdate[i].second).addMBB(FuncInfo->MBB);
1298 // If we generated any switch lowering information, build and codegen any
1299 // additional DAGs necessary.
1300 for (unsigned i = 0, e = SDB->SwitchCases.size(); i != e; ++i) {
1301 // Set the current basic block to the mbb we wish to insert the code into
1302 FuncInfo->MBB = SDB->SwitchCases[i].ThisBB;
1303 FuncInfo->InsertPt = FuncInfo->MBB->end();
1305 // Determine the unique successors.
1306 SmallVector<MachineBasicBlock *, 2> Succs;
1307 Succs.push_back(SDB->SwitchCases[i].TrueBB);
1308 if (SDB->SwitchCases[i].TrueBB != SDB->SwitchCases[i].FalseBB)
1309 Succs.push_back(SDB->SwitchCases[i].FalseBB);
1311 // Emit the code. Note that this could result in FuncInfo->MBB being split.
1312 SDB->visitSwitchCase(SDB->SwitchCases[i], FuncInfo->MBB);
1313 CurDAG->setRoot(SDB->getRoot());
1315 CodeGenAndEmitDAG();
1317 // Remember the last block, now that any splitting is done, for use in
1318 // populating PHI nodes in successors.
1319 MachineBasicBlock *ThisBB = FuncInfo->MBB;
1321 // Handle any PHI nodes in successors of this chunk, as if we were coming
1322 // from the original BB before switch expansion. Note that PHI nodes can
1323 // occur multiple times in PHINodesToUpdate. We have to be very careful to
1324 // handle them the right number of times.
1325 for (unsigned i = 0, e = Succs.size(); i != e; ++i) {
1326 FuncInfo->MBB = Succs[i];
1327 FuncInfo->InsertPt = FuncInfo->MBB->end();
1328 // FuncInfo->MBB may have been removed from the CFG if a branch was
1330 if (ThisBB->isSuccessor(FuncInfo->MBB)) {
1331 for (MachineBasicBlock::iterator
1332 MBBI = FuncInfo->MBB->begin(), MBBE = FuncInfo->MBB->end();
1333 MBBI != MBBE && MBBI->isPHI(); ++MBBI) {
1334 MachineInstrBuilder PHI(*MF, MBBI);
1335 // This value for this PHI node is recorded in PHINodesToUpdate.
1336 for (unsigned pn = 0; ; ++pn) {
1337 assert(pn != FuncInfo->PHINodesToUpdate.size() &&
1338 "Didn't find PHI entry!");
1339 if (FuncInfo->PHINodesToUpdate[pn].first == PHI) {
1340 PHI.addReg(FuncInfo->PHINodesToUpdate[pn].second).addMBB(ThisBB);
1348 SDB->SwitchCases.clear();
1352 /// Create the scheduler. If a specific scheduler was specified
1353 /// via the SchedulerRegistry, use it, otherwise select the
1354 /// one preferred by the target.
1356 ScheduleDAGSDNodes *SelectionDAGISel::CreateScheduler() {
1357 RegisterScheduler::FunctionPassCtor Ctor = RegisterScheduler::getDefault();
1361 RegisterScheduler::setDefault(Ctor);
1364 return Ctor(this, OptLevel);
1367 //===----------------------------------------------------------------------===//
1368 // Helper functions used by the generated instruction selector.
1369 //===----------------------------------------------------------------------===//
1370 // Calls to these methods are generated by tblgen.
1372 /// CheckAndMask - The isel is trying to match something like (and X, 255). If
1373 /// the dag combiner simplified the 255, we still want to match. RHS is the
1374 /// actual value in the DAG on the RHS of an AND, and DesiredMaskS is the value
1375 /// specified in the .td file (e.g. 255).
1376 bool SelectionDAGISel::CheckAndMask(SDValue LHS, ConstantSDNode *RHS,
1377 int64_t DesiredMaskS) const {
1378 const APInt &ActualMask = RHS->getAPIntValue();
1379 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS);
1381 // If the actual mask exactly matches, success!
1382 if (ActualMask == DesiredMask)
1385 // If the actual AND mask is allowing unallowed bits, this doesn't match.
1386 if (ActualMask.intersects(~DesiredMask))
1389 // Otherwise, the DAG Combiner may have proven that the value coming in is
1390 // either already zero or is not demanded. Check for known zero input bits.
1391 APInt NeededMask = DesiredMask & ~ActualMask;
1392 if (CurDAG->MaskedValueIsZero(LHS, NeededMask))
1395 // TODO: check to see if missing bits are just not demanded.
1397 // Otherwise, this pattern doesn't match.
1401 /// CheckOrMask - The isel is trying to match something like (or X, 255). If
1402 /// the dag combiner simplified the 255, we still want to match. RHS is the
1403 /// actual value in the DAG on the RHS of an OR, and DesiredMaskS is the value
1404 /// specified in the .td file (e.g. 255).
1405 bool SelectionDAGISel::CheckOrMask(SDValue LHS, ConstantSDNode *RHS,
1406 int64_t DesiredMaskS) const {
1407 const APInt &ActualMask = RHS->getAPIntValue();
1408 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS);
1410 // If the actual mask exactly matches, success!
1411 if (ActualMask == DesiredMask)
1414 // If the actual AND mask is allowing unallowed bits, this doesn't match.
1415 if (ActualMask.intersects(~DesiredMask))
1418 // Otherwise, the DAG Combiner may have proven that the value coming in is
1419 // either already zero or is not demanded. Check for known zero input bits.
1420 APInt NeededMask = DesiredMask & ~ActualMask;
1422 APInt KnownZero, KnownOne;
1423 CurDAG->ComputeMaskedBits(LHS, KnownZero, KnownOne);
1425 // If all the missing bits in the or are already known to be set, match!
1426 if ((NeededMask & KnownOne) == NeededMask)
1429 // TODO: check to see if missing bits are just not demanded.
1431 // Otherwise, this pattern doesn't match.
1436 /// SelectInlineAsmMemoryOperands - Calls to this are automatically generated
1437 /// by tblgen. Others should not call it.
1438 void SelectionDAGISel::
1439 SelectInlineAsmMemoryOperands(std::vector<SDValue> &Ops) {
1440 std::vector<SDValue> InOps;
1441 std::swap(InOps, Ops);
1443 Ops.push_back(InOps[InlineAsm::Op_InputChain]); // 0
1444 Ops.push_back(InOps[InlineAsm::Op_AsmString]); // 1
1445 Ops.push_back(InOps[InlineAsm::Op_MDNode]); // 2, !srcloc
1446 Ops.push_back(InOps[InlineAsm::Op_ExtraInfo]); // 3 (SideEffect, AlignStack)
1448 unsigned i = InlineAsm::Op_FirstOperand, e = InOps.size();
1449 if (InOps[e-1].getValueType() == MVT::Glue)
1450 --e; // Don't process a glue operand if it is here.
1453 unsigned Flags = cast<ConstantSDNode>(InOps[i])->getZExtValue();
1454 if (!InlineAsm::isMemKind(Flags)) {
1455 // Just skip over this operand, copying the operands verbatim.
1456 Ops.insert(Ops.end(), InOps.begin()+i,
1457 InOps.begin()+i+InlineAsm::getNumOperandRegisters(Flags) + 1);
1458 i += InlineAsm::getNumOperandRegisters(Flags) + 1;
1460 assert(InlineAsm::getNumOperandRegisters(Flags) == 1 &&
1461 "Memory operand with multiple values?");
1462 // Otherwise, this is a memory operand. Ask the target to select it.
1463 std::vector<SDValue> SelOps;
1464 if (SelectInlineAsmMemoryOperand(InOps[i+1], 'm', SelOps))
1465 report_fatal_error("Could not match memory address. Inline asm"
1468 // Add this to the output node.
1470 InlineAsm::getFlagWord(InlineAsm::Kind_Mem, SelOps.size());
1471 Ops.push_back(CurDAG->getTargetConstant(NewFlags, MVT::i32));
1472 Ops.insert(Ops.end(), SelOps.begin(), SelOps.end());
1477 // Add the glue input back if present.
1478 if (e != InOps.size())
1479 Ops.push_back(InOps.back());
1482 /// findGlueUse - Return use of MVT::Glue value produced by the specified
1485 static SDNode *findGlueUse(SDNode *N) {
1486 unsigned FlagResNo = N->getNumValues()-1;
1487 for (SDNode::use_iterator I = N->use_begin(), E = N->use_end(); I != E; ++I) {
1488 SDUse &Use = I.getUse();
1489 if (Use.getResNo() == FlagResNo)
1490 return Use.getUser();
1495 /// findNonImmUse - Return true if "Use" is a non-immediate use of "Def".
1496 /// This function recursively traverses up the operand chain, ignoring
1498 static bool findNonImmUse(SDNode *Use, SDNode* Def, SDNode *ImmedUse,
1499 SDNode *Root, SmallPtrSet<SDNode*, 16> &Visited,
1500 bool IgnoreChains) {
1501 // The NodeID's are given uniques ID's where a node ID is guaranteed to be
1502 // greater than all of its (recursive) operands. If we scan to a point where
1503 // 'use' is smaller than the node we're scanning for, then we know we will
1506 // The Use may be -1 (unassigned) if it is a newly allocated node. This can
1507 // happen because we scan down to newly selected nodes in the case of glue
1509 if ((Use->getNodeId() < Def->getNodeId() && Use->getNodeId() != -1))
1512 // Don't revisit nodes if we already scanned it and didn't fail, we know we
1513 // won't fail if we scan it again.
1514 if (!Visited.insert(Use))
1517 for (unsigned i = 0, e = Use->getNumOperands(); i != e; ++i) {
1518 // Ignore chain uses, they are validated by HandleMergeInputChains.
1519 if (Use->getOperand(i).getValueType() == MVT::Other && IgnoreChains)
1522 SDNode *N = Use->getOperand(i).getNode();
1524 if (Use == ImmedUse || Use == Root)
1525 continue; // We are not looking for immediate use.
1530 // Traverse up the operand chain.
1531 if (findNonImmUse(N, Def, ImmedUse, Root, Visited, IgnoreChains))
1537 /// IsProfitableToFold - Returns true if it's profitable to fold the specific
1538 /// operand node N of U during instruction selection that starts at Root.
1539 bool SelectionDAGISel::IsProfitableToFold(SDValue N, SDNode *U,
1540 SDNode *Root) const {
1541 if (OptLevel == CodeGenOpt::None) return false;
1542 return N.hasOneUse();
1545 /// IsLegalToFold - Returns true if the specific operand node N of
1546 /// U can be folded during instruction selection that starts at Root.
1547 bool SelectionDAGISel::IsLegalToFold(SDValue N, SDNode *U, SDNode *Root,
1548 CodeGenOpt::Level OptLevel,
1549 bool IgnoreChains) {
1550 if (OptLevel == CodeGenOpt::None) return false;
1552 // If Root use can somehow reach N through a path that that doesn't contain
1553 // U then folding N would create a cycle. e.g. In the following
1554 // diagram, Root can reach N through X. If N is folded into into Root, then
1555 // X is both a predecessor and a successor of U.
1566 // * indicates nodes to be folded together.
1568 // If Root produces glue, then it gets (even more) interesting. Since it
1569 // will be "glued" together with its glue use in the scheduler, we need to
1570 // check if it might reach N.
1589 // If GU (glue use) indirectly reaches N (the load), and Root folds N
1590 // (call it Fold), then X is a predecessor of GU and a successor of
1591 // Fold. But since Fold and GU are glued together, this will create
1592 // a cycle in the scheduling graph.
1594 // If the node has glue, walk down the graph to the "lowest" node in the
1596 EVT VT = Root->getValueType(Root->getNumValues()-1);
1597 while (VT == MVT::Glue) {
1598 SDNode *GU = findGlueUse(Root);
1602 VT = Root->getValueType(Root->getNumValues()-1);
1604 // If our query node has a glue result with a use, we've walked up it. If
1605 // the user (which has already been selected) has a chain or indirectly uses
1606 // the chain, our WalkChainUsers predicate will not consider it. Because of
1607 // this, we cannot ignore chains in this predicate.
1608 IgnoreChains = false;
1612 SmallPtrSet<SDNode*, 16> Visited;
1613 return !findNonImmUse(Root, N.getNode(), U, Root, Visited, IgnoreChains);
1616 SDNode *SelectionDAGISel::Select_INLINEASM(SDNode *N) {
1617 std::vector<SDValue> Ops(N->op_begin(), N->op_end());
1618 SelectInlineAsmMemoryOperands(Ops);
1620 EVT VTs[] = { MVT::Other, MVT::Glue };
1621 SDValue New = CurDAG->getNode(ISD::INLINEASM, SDLoc(N),
1622 VTs, &Ops[0], Ops.size());
1624 return New.getNode();
1627 SDNode *SelectionDAGISel::Select_UNDEF(SDNode *N) {
1628 return CurDAG->SelectNodeTo(N, TargetOpcode::IMPLICIT_DEF,N->getValueType(0));
1631 /// GetVBR - decode a vbr encoding whose top bit is set.
1632 LLVM_ATTRIBUTE_ALWAYS_INLINE static uint64_t
1633 GetVBR(uint64_t Val, const unsigned char *MatcherTable, unsigned &Idx) {
1634 assert(Val >= 128 && "Not a VBR");
1635 Val &= 127; // Remove first vbr bit.
1640 NextBits = MatcherTable[Idx++];
1641 Val |= (NextBits&127) << Shift;
1643 } while (NextBits & 128);
1649 /// UpdateChainsAndGlue - When a match is complete, this method updates uses of
1650 /// interior glue and chain results to use the new glue and chain results.
1651 void SelectionDAGISel::
1652 UpdateChainsAndGlue(SDNode *NodeToMatch, SDValue InputChain,
1653 const SmallVectorImpl<SDNode*> &ChainNodesMatched,
1655 const SmallVectorImpl<SDNode*> &GlueResultNodesMatched,
1656 bool isMorphNodeTo) {
1657 SmallVector<SDNode*, 4> NowDeadNodes;
1659 // Now that all the normal results are replaced, we replace the chain and
1660 // glue results if present.
1661 if (!ChainNodesMatched.empty()) {
1662 assert(InputChain.getNode() != 0 &&
1663 "Matched input chains but didn't produce a chain");
1664 // Loop over all of the nodes we matched that produced a chain result.
1665 // Replace all the chain results with the final chain we ended up with.
1666 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) {
1667 SDNode *ChainNode = ChainNodesMatched[i];
1669 // If this node was already deleted, don't look at it.
1670 if (ChainNode->getOpcode() == ISD::DELETED_NODE)
1673 // Don't replace the results of the root node if we're doing a
1675 if (ChainNode == NodeToMatch && isMorphNodeTo)
1678 SDValue ChainVal = SDValue(ChainNode, ChainNode->getNumValues()-1);
1679 if (ChainVal.getValueType() == MVT::Glue)
1680 ChainVal = ChainVal.getValue(ChainVal->getNumValues()-2);
1681 assert(ChainVal.getValueType() == MVT::Other && "Not a chain?");
1682 CurDAG->ReplaceAllUsesOfValueWith(ChainVal, InputChain);
1684 // If the node became dead and we haven't already seen it, delete it.
1685 if (ChainNode->use_empty() &&
1686 !std::count(NowDeadNodes.begin(), NowDeadNodes.end(), ChainNode))
1687 NowDeadNodes.push_back(ChainNode);
1691 // If the result produces glue, update any glue results in the matched
1692 // pattern with the glue result.
1693 if (InputGlue.getNode() != 0) {
1694 // Handle any interior nodes explicitly marked.
1695 for (unsigned i = 0, e = GlueResultNodesMatched.size(); i != e; ++i) {
1696 SDNode *FRN = GlueResultNodesMatched[i];
1698 // If this node was already deleted, don't look at it.
1699 if (FRN->getOpcode() == ISD::DELETED_NODE)
1702 assert(FRN->getValueType(FRN->getNumValues()-1) == MVT::Glue &&
1703 "Doesn't have a glue result");
1704 CurDAG->ReplaceAllUsesOfValueWith(SDValue(FRN, FRN->getNumValues()-1),
1707 // If the node became dead and we haven't already seen it, delete it.
1708 if (FRN->use_empty() &&
1709 !std::count(NowDeadNodes.begin(), NowDeadNodes.end(), FRN))
1710 NowDeadNodes.push_back(FRN);
1714 if (!NowDeadNodes.empty())
1715 CurDAG->RemoveDeadNodes(NowDeadNodes);
1717 DEBUG(dbgs() << "ISEL: Match complete!\n");
1723 CR_LeadsToInteriorNode
1726 /// WalkChainUsers - Walk down the users of the specified chained node that is
1727 /// part of the pattern we're matching, looking at all of the users we find.
1728 /// This determines whether something is an interior node, whether we have a
1729 /// non-pattern node in between two pattern nodes (which prevent folding because
1730 /// it would induce a cycle) and whether we have a TokenFactor node sandwiched
1731 /// between pattern nodes (in which case the TF becomes part of the pattern).
1733 /// The walk we do here is guaranteed to be small because we quickly get down to
1734 /// already selected nodes "below" us.
1736 WalkChainUsers(const SDNode *ChainedNode,
1737 SmallVectorImpl<SDNode*> &ChainedNodesInPattern,
1738 SmallVectorImpl<SDNode*> &InteriorChainedNodes) {
1739 ChainResult Result = CR_Simple;
1741 for (SDNode::use_iterator UI = ChainedNode->use_begin(),
1742 E = ChainedNode->use_end(); UI != E; ++UI) {
1743 // Make sure the use is of the chain, not some other value we produce.
1744 if (UI.getUse().getValueType() != MVT::Other) continue;
1748 // If we see an already-selected machine node, then we've gone beyond the
1749 // pattern that we're selecting down into the already selected chunk of the
1751 if (User->isMachineOpcode() ||
1752 User->getOpcode() == ISD::HANDLENODE) // Root of the graph.
1755 unsigned UserOpcode = User->getOpcode();
1756 if (UserOpcode == ISD::CopyToReg ||
1757 UserOpcode == ISD::CopyFromReg ||
1758 UserOpcode == ISD::INLINEASM ||
1759 UserOpcode == ISD::EH_LABEL ||
1760 UserOpcode == ISD::LIFETIME_START ||
1761 UserOpcode == ISD::LIFETIME_END) {
1762 // If their node ID got reset to -1 then they've already been selected.
1763 // Treat them like a MachineOpcode.
1764 if (User->getNodeId() == -1)
1768 // If we have a TokenFactor, we handle it specially.
1769 if (User->getOpcode() != ISD::TokenFactor) {
1770 // If the node isn't a token factor and isn't part of our pattern, then it
1771 // must be a random chained node in between two nodes we're selecting.
1772 // This happens when we have something like:
1777 // Because we structurally match the load/store as a read/modify/write,
1778 // but the call is chained between them. We cannot fold in this case
1779 // because it would induce a cycle in the graph.
1780 if (!std::count(ChainedNodesInPattern.begin(),
1781 ChainedNodesInPattern.end(), User))
1782 return CR_InducesCycle;
1784 // Otherwise we found a node that is part of our pattern. For example in:
1788 // This would happen when we're scanning down from the load and see the
1789 // store as a user. Record that there is a use of ChainedNode that is
1790 // part of the pattern and keep scanning uses.
1791 Result = CR_LeadsToInteriorNode;
1792 InteriorChainedNodes.push_back(User);
1796 // If we found a TokenFactor, there are two cases to consider: first if the
1797 // TokenFactor is just hanging "below" the pattern we're matching (i.e. no
1798 // uses of the TF are in our pattern) we just want to ignore it. Second,
1799 // the TokenFactor can be sandwiched in between two chained nodes, like so:
1805 // | \ DAG's like cheese
1808 // [TokenFactor] [Op]
1815 // In this case, the TokenFactor becomes part of our match and we rewrite it
1816 // as a new TokenFactor.
1818 // To distinguish these two cases, do a recursive walk down the uses.
1819 switch (WalkChainUsers(User, ChainedNodesInPattern, InteriorChainedNodes)) {
1821 // If the uses of the TokenFactor are just already-selected nodes, ignore
1822 // it, it is "below" our pattern.
1824 case CR_InducesCycle:
1825 // If the uses of the TokenFactor lead to nodes that are not part of our
1826 // pattern that are not selected, folding would turn this into a cycle,
1828 return CR_InducesCycle;
1829 case CR_LeadsToInteriorNode:
1830 break; // Otherwise, keep processing.
1833 // Okay, we know we're in the interesting interior case. The TokenFactor
1834 // is now going to be considered part of the pattern so that we rewrite its
1835 // uses (it may have uses that are not part of the pattern) with the
1836 // ultimate chain result of the generated code. We will also add its chain
1837 // inputs as inputs to the ultimate TokenFactor we create.
1838 Result = CR_LeadsToInteriorNode;
1839 ChainedNodesInPattern.push_back(User);
1840 InteriorChainedNodes.push_back(User);
1847 /// HandleMergeInputChains - This implements the OPC_EmitMergeInputChains
1848 /// operation for when the pattern matched at least one node with a chains. The
1849 /// input vector contains a list of all of the chained nodes that we match. We
1850 /// must determine if this is a valid thing to cover (i.e. matching it won't
1851 /// induce cycles in the DAG) and if so, creating a TokenFactor node. that will
1852 /// be used as the input node chain for the generated nodes.
1854 HandleMergeInputChains(SmallVectorImpl<SDNode*> &ChainNodesMatched,
1855 SelectionDAG *CurDAG) {
1856 // Walk all of the chained nodes we've matched, recursively scanning down the
1857 // users of the chain result. This adds any TokenFactor nodes that are caught
1858 // in between chained nodes to the chained and interior nodes list.
1859 SmallVector<SDNode*, 3> InteriorChainedNodes;
1860 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) {
1861 if (WalkChainUsers(ChainNodesMatched[i], ChainNodesMatched,
1862 InteriorChainedNodes) == CR_InducesCycle)
1863 return SDValue(); // Would induce a cycle.
1866 // Okay, we have walked all the matched nodes and collected TokenFactor nodes
1867 // that we are interested in. Form our input TokenFactor node.
1868 SmallVector<SDValue, 3> InputChains;
1869 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) {
1870 // Add the input chain of this node to the InputChains list (which will be
1871 // the operands of the generated TokenFactor) if it's not an interior node.
1872 SDNode *N = ChainNodesMatched[i];
1873 if (N->getOpcode() != ISD::TokenFactor) {
1874 if (std::count(InteriorChainedNodes.begin(),InteriorChainedNodes.end(),N))
1877 // Otherwise, add the input chain.
1878 SDValue InChain = ChainNodesMatched[i]->getOperand(0);
1879 assert(InChain.getValueType() == MVT::Other && "Not a chain");
1880 InputChains.push_back(InChain);
1884 // If we have a token factor, we want to add all inputs of the token factor
1885 // that are not part of the pattern we're matching.
1886 for (unsigned op = 0, e = N->getNumOperands(); op != e; ++op) {
1887 if (!std::count(ChainNodesMatched.begin(), ChainNodesMatched.end(),
1888 N->getOperand(op).getNode()))
1889 InputChains.push_back(N->getOperand(op));
1894 if (InputChains.size() == 1)
1895 return InputChains[0];
1896 return CurDAG->getNode(ISD::TokenFactor, SDLoc(ChainNodesMatched[0]),
1897 MVT::Other, &InputChains[0], InputChains.size());
1900 /// MorphNode - Handle morphing a node in place for the selector.
1901 SDNode *SelectionDAGISel::
1902 MorphNode(SDNode *Node, unsigned TargetOpc, SDVTList VTList,
1903 const SDValue *Ops, unsigned NumOps, unsigned EmitNodeInfo) {
1904 // It is possible we're using MorphNodeTo to replace a node with no
1905 // normal results with one that has a normal result (or we could be
1906 // adding a chain) and the input could have glue and chains as well.
1907 // In this case we need to shift the operands down.
1908 // FIXME: This is a horrible hack and broken in obscure cases, no worse
1909 // than the old isel though.
1910 int OldGlueResultNo = -1, OldChainResultNo = -1;
1912 unsigned NTMNumResults = Node->getNumValues();
1913 if (Node->getValueType(NTMNumResults-1) == MVT::Glue) {
1914 OldGlueResultNo = NTMNumResults-1;
1915 if (NTMNumResults != 1 &&
1916 Node->getValueType(NTMNumResults-2) == MVT::Other)
1917 OldChainResultNo = NTMNumResults-2;
1918 } else if (Node->getValueType(NTMNumResults-1) == MVT::Other)
1919 OldChainResultNo = NTMNumResults-1;
1921 // Call the underlying SelectionDAG routine to do the transmogrification. Note
1922 // that this deletes operands of the old node that become dead.
1923 SDNode *Res = CurDAG->MorphNodeTo(Node, ~TargetOpc, VTList, Ops, NumOps);
1925 // MorphNodeTo can operate in two ways: if an existing node with the
1926 // specified operands exists, it can just return it. Otherwise, it
1927 // updates the node in place to have the requested operands.
1929 // If we updated the node in place, reset the node ID. To the isel,
1930 // this should be just like a newly allocated machine node.
1934 unsigned ResNumResults = Res->getNumValues();
1935 // Move the glue if needed.
1936 if ((EmitNodeInfo & OPFL_GlueOutput) && OldGlueResultNo != -1 &&
1937 (unsigned)OldGlueResultNo != ResNumResults-1)
1938 CurDAG->ReplaceAllUsesOfValueWith(SDValue(Node, OldGlueResultNo),
1939 SDValue(Res, ResNumResults-1));
1941 if ((EmitNodeInfo & OPFL_GlueOutput) != 0)
1944 // Move the chain reference if needed.
1945 if ((EmitNodeInfo & OPFL_Chain) && OldChainResultNo != -1 &&
1946 (unsigned)OldChainResultNo != ResNumResults-1)
1947 CurDAG->ReplaceAllUsesOfValueWith(SDValue(Node, OldChainResultNo),
1948 SDValue(Res, ResNumResults-1));
1950 // Otherwise, no replacement happened because the node already exists. Replace
1951 // Uses of the old node with the new one.
1953 CurDAG->ReplaceAllUsesWith(Node, Res);
1958 /// CheckSame - Implements OP_CheckSame.
1959 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
1960 CheckSame(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1962 const SmallVectorImpl<std::pair<SDValue, SDNode*> > &RecordedNodes) {
1963 // Accept if it is exactly the same as a previously recorded node.
1964 unsigned RecNo = MatcherTable[MatcherIndex++];
1965 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
1966 return N == RecordedNodes[RecNo].first;
1969 /// CheckPatternPredicate - Implements OP_CheckPatternPredicate.
1970 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
1971 CheckPatternPredicate(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1972 const SelectionDAGISel &SDISel) {
1973 return SDISel.CheckPatternPredicate(MatcherTable[MatcherIndex++]);
1976 /// CheckNodePredicate - Implements OP_CheckNodePredicate.
1977 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
1978 CheckNodePredicate(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1979 const SelectionDAGISel &SDISel, SDNode *N) {
1980 return SDISel.CheckNodePredicate(N, MatcherTable[MatcherIndex++]);
1983 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
1984 CheckOpcode(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1986 uint16_t Opc = MatcherTable[MatcherIndex++];
1987 Opc |= (unsigned short)MatcherTable[MatcherIndex++] << 8;
1988 return N->getOpcode() == Opc;
1991 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
1992 CheckType(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1993 SDValue N, const TargetLowering *TLI) {
1994 MVT::SimpleValueType VT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
1995 if (N.getValueType() == VT) return true;
1997 // Handle the case when VT is iPTR.
1998 return VT == MVT::iPTR && N.getValueType() == TLI->getPointerTy();
2001 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2002 CheckChildType(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2003 SDValue N, const TargetLowering *TLI,
2005 if (ChildNo >= N.getNumOperands())
2006 return false; // Match fails if out of range child #.
2007 return ::CheckType(MatcherTable, MatcherIndex, N.getOperand(ChildNo), TLI);
2010 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2011 CheckCondCode(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2013 return cast<CondCodeSDNode>(N)->get() ==
2014 (ISD::CondCode)MatcherTable[MatcherIndex++];
2017 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2018 CheckValueType(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2019 SDValue N, const TargetLowering *TLI) {
2020 MVT::SimpleValueType VT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2021 if (cast<VTSDNode>(N)->getVT() == VT)
2024 // Handle the case when VT is iPTR.
2025 return VT == MVT::iPTR && cast<VTSDNode>(N)->getVT() == TLI->getPointerTy();
2028 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2029 CheckInteger(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2031 int64_t Val = MatcherTable[MatcherIndex++];
2033 Val = GetVBR(Val, MatcherTable, MatcherIndex);
2035 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N);
2036 return C != 0 && C->getSExtValue() == Val;
2039 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2040 CheckAndImm(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2041 SDValue N, const SelectionDAGISel &SDISel) {
2042 int64_t Val = MatcherTable[MatcherIndex++];
2044 Val = GetVBR(Val, MatcherTable, MatcherIndex);
2046 if (N->getOpcode() != ISD::AND) return false;
2048 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
2049 return C != 0 && SDISel.CheckAndMask(N.getOperand(0), C, Val);
2052 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2053 CheckOrImm(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2054 SDValue N, const SelectionDAGISel &SDISel) {
2055 int64_t Val = MatcherTable[MatcherIndex++];
2057 Val = GetVBR(Val, MatcherTable, MatcherIndex);
2059 if (N->getOpcode() != ISD::OR) return false;
2061 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
2062 return C != 0 && SDISel.CheckOrMask(N.getOperand(0), C, Val);
2065 /// IsPredicateKnownToFail - If we know how and can do so without pushing a
2066 /// scope, evaluate the current node. If the current predicate is known to
2067 /// fail, set Result=true and return anything. If the current predicate is
2068 /// known to pass, set Result=false and return the MatcherIndex to continue
2069 /// with. If the current predicate is unknown, set Result=false and return the
2070 /// MatcherIndex to continue with.
2071 static unsigned IsPredicateKnownToFail(const unsigned char *Table,
2072 unsigned Index, SDValue N,
2074 const SelectionDAGISel &SDISel,
2075 SmallVectorImpl<std::pair<SDValue, SDNode*> > &RecordedNodes) {
2076 switch (Table[Index++]) {
2079 return Index-1; // Could not evaluate this predicate.
2080 case SelectionDAGISel::OPC_CheckSame:
2081 Result = !::CheckSame(Table, Index, N, RecordedNodes);
2083 case SelectionDAGISel::OPC_CheckPatternPredicate:
2084 Result = !::CheckPatternPredicate(Table, Index, SDISel);
2086 case SelectionDAGISel::OPC_CheckPredicate:
2087 Result = !::CheckNodePredicate(Table, Index, SDISel, N.getNode());
2089 case SelectionDAGISel::OPC_CheckOpcode:
2090 Result = !::CheckOpcode(Table, Index, N.getNode());
2092 case SelectionDAGISel::OPC_CheckType:
2093 Result = !::CheckType(Table, Index, N, SDISel.getTargetLowering());
2095 case SelectionDAGISel::OPC_CheckChild0Type:
2096 case SelectionDAGISel::OPC_CheckChild1Type:
2097 case SelectionDAGISel::OPC_CheckChild2Type:
2098 case SelectionDAGISel::OPC_CheckChild3Type:
2099 case SelectionDAGISel::OPC_CheckChild4Type:
2100 case SelectionDAGISel::OPC_CheckChild5Type:
2101 case SelectionDAGISel::OPC_CheckChild6Type:
2102 case SelectionDAGISel::OPC_CheckChild7Type:
2103 Result = !::CheckChildType(Table, Index, N, SDISel.getTargetLowering(),
2104 Table[Index-1] - SelectionDAGISel::OPC_CheckChild0Type);
2106 case SelectionDAGISel::OPC_CheckCondCode:
2107 Result = !::CheckCondCode(Table, Index, N);
2109 case SelectionDAGISel::OPC_CheckValueType:
2110 Result = !::CheckValueType(Table, Index, N, SDISel.getTargetLowering());
2112 case SelectionDAGISel::OPC_CheckInteger:
2113 Result = !::CheckInteger(Table, Index, N);
2115 case SelectionDAGISel::OPC_CheckAndImm:
2116 Result = !::CheckAndImm(Table, Index, N, SDISel);
2118 case SelectionDAGISel::OPC_CheckOrImm:
2119 Result = !::CheckOrImm(Table, Index, N, SDISel);
2127 /// FailIndex - If this match fails, this is the index to continue with.
2130 /// NodeStack - The node stack when the scope was formed.
2131 SmallVector<SDValue, 4> NodeStack;
2133 /// NumRecordedNodes - The number of recorded nodes when the scope was formed.
2134 unsigned NumRecordedNodes;
2136 /// NumMatchedMemRefs - The number of matched memref entries.
2137 unsigned NumMatchedMemRefs;
2139 /// InputChain/InputGlue - The current chain/glue
2140 SDValue InputChain, InputGlue;
2142 /// HasChainNodesMatched - True if the ChainNodesMatched list is non-empty.
2143 bool HasChainNodesMatched, HasGlueResultNodesMatched;
2148 SDNode *SelectionDAGISel::
2149 SelectCodeCommon(SDNode *NodeToMatch, const unsigned char *MatcherTable,
2150 unsigned TableSize) {
2151 // FIXME: Should these even be selected? Handle these cases in the caller?
2152 switch (NodeToMatch->getOpcode()) {
2155 case ISD::EntryToken: // These nodes remain the same.
2156 case ISD::BasicBlock:
2158 case ISD::RegisterMask:
2159 //case ISD::VALUETYPE:
2160 //case ISD::CONDCODE:
2161 case ISD::HANDLENODE:
2162 case ISD::MDNODE_SDNODE:
2163 case ISD::TargetConstant:
2164 case ISD::TargetConstantFP:
2165 case ISD::TargetConstantPool:
2166 case ISD::TargetFrameIndex:
2167 case ISD::TargetExternalSymbol:
2168 case ISD::TargetBlockAddress:
2169 case ISD::TargetJumpTable:
2170 case ISD::TargetGlobalTLSAddress:
2171 case ISD::TargetGlobalAddress:
2172 case ISD::TokenFactor:
2173 case ISD::CopyFromReg:
2174 case ISD::CopyToReg:
2176 case ISD::LIFETIME_START:
2177 case ISD::LIFETIME_END:
2178 NodeToMatch->setNodeId(-1); // Mark selected.
2180 case ISD::AssertSext:
2181 case ISD::AssertZext:
2182 CurDAG->ReplaceAllUsesOfValueWith(SDValue(NodeToMatch, 0),
2183 NodeToMatch->getOperand(0));
2185 case ISD::INLINEASM: return Select_INLINEASM(NodeToMatch);
2186 case ISD::UNDEF: return Select_UNDEF(NodeToMatch);
2189 assert(!NodeToMatch->isMachineOpcode() && "Node already selected!");
2191 // Set up the node stack with NodeToMatch as the only node on the stack.
2192 SmallVector<SDValue, 8> NodeStack;
2193 SDValue N = SDValue(NodeToMatch, 0);
2194 NodeStack.push_back(N);
2196 // MatchScopes - Scopes used when matching, if a match failure happens, this
2197 // indicates where to continue checking.
2198 SmallVector<MatchScope, 8> MatchScopes;
2200 // RecordedNodes - This is the set of nodes that have been recorded by the
2201 // state machine. The second value is the parent of the node, or null if the
2202 // root is recorded.
2203 SmallVector<std::pair<SDValue, SDNode*>, 8> RecordedNodes;
2205 // MatchedMemRefs - This is the set of MemRef's we've seen in the input
2207 SmallVector<MachineMemOperand*, 2> MatchedMemRefs;
2209 // These are the current input chain and glue for use when generating nodes.
2210 // Various Emit operations change these. For example, emitting a copytoreg
2211 // uses and updates these.
2212 SDValue InputChain, InputGlue;
2214 // ChainNodesMatched - If a pattern matches nodes that have input/output
2215 // chains, the OPC_EmitMergeInputChains operation is emitted which indicates
2216 // which ones they are. The result is captured into this list so that we can
2217 // update the chain results when the pattern is complete.
2218 SmallVector<SDNode*, 3> ChainNodesMatched;
2219 SmallVector<SDNode*, 3> GlueResultNodesMatched;
2221 DEBUG(dbgs() << "ISEL: Starting pattern match on root node: ";
2222 NodeToMatch->dump(CurDAG);
2225 // Determine where to start the interpreter. Normally we start at opcode #0,
2226 // but if the state machine starts with an OPC_SwitchOpcode, then we
2227 // accelerate the first lookup (which is guaranteed to be hot) with the
2228 // OpcodeOffset table.
2229 unsigned MatcherIndex = 0;
2231 if (!OpcodeOffset.empty()) {
2232 // Already computed the OpcodeOffset table, just index into it.
2233 if (N.getOpcode() < OpcodeOffset.size())
2234 MatcherIndex = OpcodeOffset[N.getOpcode()];
2235 DEBUG(dbgs() << " Initial Opcode index to " << MatcherIndex << "\n");
2237 } else if (MatcherTable[0] == OPC_SwitchOpcode) {
2238 // Otherwise, the table isn't computed, but the state machine does start
2239 // with an OPC_SwitchOpcode instruction. Populate the table now, since this
2240 // is the first time we're selecting an instruction.
2243 // Get the size of this case.
2244 unsigned CaseSize = MatcherTable[Idx++];
2246 CaseSize = GetVBR(CaseSize, MatcherTable, Idx);
2247 if (CaseSize == 0) break;
2249 // Get the opcode, add the index to the table.
2250 uint16_t Opc = MatcherTable[Idx++];
2251 Opc |= (unsigned short)MatcherTable[Idx++] << 8;
2252 if (Opc >= OpcodeOffset.size())
2253 OpcodeOffset.resize((Opc+1)*2);
2254 OpcodeOffset[Opc] = Idx;
2258 // Okay, do the lookup for the first opcode.
2259 if (N.getOpcode() < OpcodeOffset.size())
2260 MatcherIndex = OpcodeOffset[N.getOpcode()];
2264 assert(MatcherIndex < TableSize && "Invalid index");
2266 unsigned CurrentOpcodeIndex = MatcherIndex;
2268 BuiltinOpcodes Opcode = (BuiltinOpcodes)MatcherTable[MatcherIndex++];
2271 // Okay, the semantics of this operation are that we should push a scope
2272 // then evaluate the first child. However, pushing a scope only to have
2273 // the first check fail (which then pops it) is inefficient. If we can
2274 // determine immediately that the first check (or first several) will
2275 // immediately fail, don't even bother pushing a scope for them.
2279 unsigned NumToSkip = MatcherTable[MatcherIndex++];
2280 if (NumToSkip & 128)
2281 NumToSkip = GetVBR(NumToSkip, MatcherTable, MatcherIndex);
2282 // Found the end of the scope with no match.
2283 if (NumToSkip == 0) {
2288 FailIndex = MatcherIndex+NumToSkip;
2290 unsigned MatcherIndexOfPredicate = MatcherIndex;
2291 (void)MatcherIndexOfPredicate; // silence warning.
2293 // If we can't evaluate this predicate without pushing a scope (e.g. if
2294 // it is a 'MoveParent') or if the predicate succeeds on this node, we
2295 // push the scope and evaluate the full predicate chain.
2297 MatcherIndex = IsPredicateKnownToFail(MatcherTable, MatcherIndex, N,
2298 Result, *this, RecordedNodes);
2302 DEBUG(dbgs() << " Skipped scope entry (due to false predicate) at "
2303 << "index " << MatcherIndexOfPredicate
2304 << ", continuing at " << FailIndex << "\n");
2305 ++NumDAGIselRetries;
2307 // Otherwise, we know that this case of the Scope is guaranteed to fail,
2308 // move to the next case.
2309 MatcherIndex = FailIndex;
2312 // If the whole scope failed to match, bail.
2313 if (FailIndex == 0) break;
2315 // Push a MatchScope which indicates where to go if the first child fails
2317 MatchScope NewEntry;
2318 NewEntry.FailIndex = FailIndex;
2319 NewEntry.NodeStack.append(NodeStack.begin(), NodeStack.end());
2320 NewEntry.NumRecordedNodes = RecordedNodes.size();
2321 NewEntry.NumMatchedMemRefs = MatchedMemRefs.size();
2322 NewEntry.InputChain = InputChain;
2323 NewEntry.InputGlue = InputGlue;
2324 NewEntry.HasChainNodesMatched = !ChainNodesMatched.empty();
2325 NewEntry.HasGlueResultNodesMatched = !GlueResultNodesMatched.empty();
2326 MatchScopes.push_back(NewEntry);
2329 case OPC_RecordNode: {
2330 // Remember this node, it may end up being an operand in the pattern.
2332 if (NodeStack.size() > 1)
2333 Parent = NodeStack[NodeStack.size()-2].getNode();
2334 RecordedNodes.push_back(std::make_pair(N, Parent));
2338 case OPC_RecordChild0: case OPC_RecordChild1:
2339 case OPC_RecordChild2: case OPC_RecordChild3:
2340 case OPC_RecordChild4: case OPC_RecordChild5:
2341 case OPC_RecordChild6: case OPC_RecordChild7: {
2342 unsigned ChildNo = Opcode-OPC_RecordChild0;
2343 if (ChildNo >= N.getNumOperands())
2344 break; // Match fails if out of range child #.
2346 RecordedNodes.push_back(std::make_pair(N->getOperand(ChildNo),
2350 case OPC_RecordMemRef:
2351 MatchedMemRefs.push_back(cast<MemSDNode>(N)->getMemOperand());
2354 case OPC_CaptureGlueInput:
2355 // If the current node has an input glue, capture it in InputGlue.
2356 if (N->getNumOperands() != 0 &&
2357 N->getOperand(N->getNumOperands()-1).getValueType() == MVT::Glue)
2358 InputGlue = N->getOperand(N->getNumOperands()-1);
2361 case OPC_MoveChild: {
2362 unsigned ChildNo = MatcherTable[MatcherIndex++];
2363 if (ChildNo >= N.getNumOperands())
2364 break; // Match fails if out of range child #.
2365 N = N.getOperand(ChildNo);
2366 NodeStack.push_back(N);
2370 case OPC_MoveParent:
2371 // Pop the current node off the NodeStack.
2372 NodeStack.pop_back();
2373 assert(!NodeStack.empty() && "Node stack imbalance!");
2374 N = NodeStack.back();
2378 if (!::CheckSame(MatcherTable, MatcherIndex, N, RecordedNodes)) break;
2380 case OPC_CheckPatternPredicate:
2381 if (!::CheckPatternPredicate(MatcherTable, MatcherIndex, *this)) break;
2383 case OPC_CheckPredicate:
2384 if (!::CheckNodePredicate(MatcherTable, MatcherIndex, *this,
2388 case OPC_CheckComplexPat: {
2389 unsigned CPNum = MatcherTable[MatcherIndex++];
2390 unsigned RecNo = MatcherTable[MatcherIndex++];
2391 assert(RecNo < RecordedNodes.size() && "Invalid CheckComplexPat");
2392 if (!CheckComplexPattern(NodeToMatch, RecordedNodes[RecNo].second,
2393 RecordedNodes[RecNo].first, CPNum,
2398 case OPC_CheckOpcode:
2399 if (!::CheckOpcode(MatcherTable, MatcherIndex, N.getNode())) break;
2403 if (!::CheckType(MatcherTable, MatcherIndex, N, getTargetLowering()))
2407 case OPC_SwitchOpcode: {
2408 unsigned CurNodeOpcode = N.getOpcode();
2409 unsigned SwitchStart = MatcherIndex-1; (void)SwitchStart;
2412 // Get the size of this case.
2413 CaseSize = MatcherTable[MatcherIndex++];
2415 CaseSize = GetVBR(CaseSize, MatcherTable, MatcherIndex);
2416 if (CaseSize == 0) break;
2418 uint16_t Opc = MatcherTable[MatcherIndex++];
2419 Opc |= (unsigned short)MatcherTable[MatcherIndex++] << 8;
2421 // If the opcode matches, then we will execute this case.
2422 if (CurNodeOpcode == Opc)
2425 // Otherwise, skip over this case.
2426 MatcherIndex += CaseSize;
2429 // If no cases matched, bail out.
2430 if (CaseSize == 0) break;
2432 // Otherwise, execute the case we found.
2433 DEBUG(dbgs() << " OpcodeSwitch from " << SwitchStart
2434 << " to " << MatcherIndex << "\n");
2438 case OPC_SwitchType: {
2439 MVT CurNodeVT = N.getSimpleValueType();
2440 unsigned SwitchStart = MatcherIndex-1; (void)SwitchStart;
2443 // Get the size of this case.
2444 CaseSize = MatcherTable[MatcherIndex++];
2446 CaseSize = GetVBR(CaseSize, MatcherTable, MatcherIndex);
2447 if (CaseSize == 0) break;
2449 MVT CaseVT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2450 if (CaseVT == MVT::iPTR)
2451 CaseVT = getTargetLowering()->getPointerTy();
2453 // If the VT matches, then we will execute this case.
2454 if (CurNodeVT == CaseVT)
2457 // Otherwise, skip over this case.
2458 MatcherIndex += CaseSize;
2461 // If no cases matched, bail out.
2462 if (CaseSize == 0) break;
2464 // Otherwise, execute the case we found.
2465 DEBUG(dbgs() << " TypeSwitch[" << EVT(CurNodeVT).getEVTString()
2466 << "] from " << SwitchStart << " to " << MatcherIndex<<'\n');
2469 case OPC_CheckChild0Type: case OPC_CheckChild1Type:
2470 case OPC_CheckChild2Type: case OPC_CheckChild3Type:
2471 case OPC_CheckChild4Type: case OPC_CheckChild5Type:
2472 case OPC_CheckChild6Type: case OPC_CheckChild7Type:
2473 if (!::CheckChildType(MatcherTable, MatcherIndex, N, getTargetLowering(),
2474 Opcode-OPC_CheckChild0Type))
2477 case OPC_CheckCondCode:
2478 if (!::CheckCondCode(MatcherTable, MatcherIndex, N)) break;
2480 case OPC_CheckValueType:
2481 if (!::CheckValueType(MatcherTable, MatcherIndex, N, getTargetLowering()))
2484 case OPC_CheckInteger:
2485 if (!::CheckInteger(MatcherTable, MatcherIndex, N)) break;
2487 case OPC_CheckAndImm:
2488 if (!::CheckAndImm(MatcherTable, MatcherIndex, N, *this)) break;
2490 case OPC_CheckOrImm:
2491 if (!::CheckOrImm(MatcherTable, MatcherIndex, N, *this)) break;
2494 case OPC_CheckFoldableChainNode: {
2495 assert(NodeStack.size() != 1 && "No parent node");
2496 // Verify that all intermediate nodes between the root and this one have
2498 bool HasMultipleUses = false;
2499 for (unsigned i = 1, e = NodeStack.size()-1; i != e; ++i)
2500 if (!NodeStack[i].hasOneUse()) {
2501 HasMultipleUses = true;
2504 if (HasMultipleUses) break;
2506 // Check to see that the target thinks this is profitable to fold and that
2507 // we can fold it without inducing cycles in the graph.
2508 if (!IsProfitableToFold(N, NodeStack[NodeStack.size()-2].getNode(),
2510 !IsLegalToFold(N, NodeStack[NodeStack.size()-2].getNode(),
2511 NodeToMatch, OptLevel,
2512 true/*We validate our own chains*/))
2517 case OPC_EmitInteger: {
2518 MVT::SimpleValueType VT =
2519 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2520 int64_t Val = MatcherTable[MatcherIndex++];
2522 Val = GetVBR(Val, MatcherTable, MatcherIndex);
2523 RecordedNodes.push_back(std::pair<SDValue, SDNode*>(
2524 CurDAG->getTargetConstant(Val, VT), (SDNode*)0));
2527 case OPC_EmitRegister: {
2528 MVT::SimpleValueType VT =
2529 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2530 unsigned RegNo = MatcherTable[MatcherIndex++];
2531 RecordedNodes.push_back(std::pair<SDValue, SDNode*>(
2532 CurDAG->getRegister(RegNo, VT), (SDNode*)0));
2535 case OPC_EmitRegister2: {
2536 // For targets w/ more than 256 register names, the register enum
2537 // values are stored in two bytes in the matcher table (just like
2539 MVT::SimpleValueType VT =
2540 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2541 unsigned RegNo = MatcherTable[MatcherIndex++];
2542 RegNo |= MatcherTable[MatcherIndex++] << 8;
2543 RecordedNodes.push_back(std::pair<SDValue, SDNode*>(
2544 CurDAG->getRegister(RegNo, VT), (SDNode*)0));
2548 case OPC_EmitConvertToTarget: {
2549 // Convert from IMM/FPIMM to target version.
2550 unsigned RecNo = MatcherTable[MatcherIndex++];
2551 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2552 SDValue Imm = RecordedNodes[RecNo].first;
2554 if (Imm->getOpcode() == ISD::Constant) {
2555 const ConstantInt *Val=cast<ConstantSDNode>(Imm)->getConstantIntValue();
2556 Imm = CurDAG->getConstant(*Val, Imm.getValueType(), true);
2557 } else if (Imm->getOpcode() == ISD::ConstantFP) {
2558 const ConstantFP *Val=cast<ConstantFPSDNode>(Imm)->getConstantFPValue();
2559 Imm = CurDAG->getConstantFP(*Val, Imm.getValueType(), true);
2562 RecordedNodes.push_back(std::make_pair(Imm, RecordedNodes[RecNo].second));
2566 case OPC_EmitMergeInputChains1_0: // OPC_EmitMergeInputChains, 1, 0
2567 case OPC_EmitMergeInputChains1_1: { // OPC_EmitMergeInputChains, 1, 1
2568 // These are space-optimized forms of OPC_EmitMergeInputChains.
2569 assert(InputChain.getNode() == 0 &&
2570 "EmitMergeInputChains should be the first chain producing node");
2571 assert(ChainNodesMatched.empty() &&
2572 "Should only have one EmitMergeInputChains per match");
2574 // Read all of the chained nodes.
2575 unsigned RecNo = Opcode == OPC_EmitMergeInputChains1_1;
2576 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2577 ChainNodesMatched.push_back(RecordedNodes[RecNo].first.getNode());
2579 // FIXME: What if other value results of the node have uses not matched
2581 if (ChainNodesMatched.back() != NodeToMatch &&
2582 !RecordedNodes[RecNo].first.hasOneUse()) {
2583 ChainNodesMatched.clear();
2587 // Merge the input chains if they are not intra-pattern references.
2588 InputChain = HandleMergeInputChains(ChainNodesMatched, CurDAG);
2590 if (InputChain.getNode() == 0)
2591 break; // Failed to merge.
2595 case OPC_EmitMergeInputChains: {
2596 assert(InputChain.getNode() == 0 &&
2597 "EmitMergeInputChains should be the first chain producing node");
2598 // This node gets a list of nodes we matched in the input that have
2599 // chains. We want to token factor all of the input chains to these nodes
2600 // together. However, if any of the input chains is actually one of the
2601 // nodes matched in this pattern, then we have an intra-match reference.
2602 // Ignore these because the newly token factored chain should not refer to
2604 unsigned NumChains = MatcherTable[MatcherIndex++];
2605 assert(NumChains != 0 && "Can't TF zero chains");
2607 assert(ChainNodesMatched.empty() &&
2608 "Should only have one EmitMergeInputChains per match");
2610 // Read all of the chained nodes.
2611 for (unsigned i = 0; i != NumChains; ++i) {
2612 unsigned RecNo = MatcherTable[MatcherIndex++];
2613 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2614 ChainNodesMatched.push_back(RecordedNodes[RecNo].first.getNode());
2616 // FIXME: What if other value results of the node have uses not matched
2618 if (ChainNodesMatched.back() != NodeToMatch &&
2619 !RecordedNodes[RecNo].first.hasOneUse()) {
2620 ChainNodesMatched.clear();
2625 // If the inner loop broke out, the match fails.
2626 if (ChainNodesMatched.empty())
2629 // Merge the input chains if they are not intra-pattern references.
2630 InputChain = HandleMergeInputChains(ChainNodesMatched, CurDAG);
2632 if (InputChain.getNode() == 0)
2633 break; // Failed to merge.
2638 case OPC_EmitCopyToReg: {
2639 unsigned RecNo = MatcherTable[MatcherIndex++];
2640 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2641 unsigned DestPhysReg = MatcherTable[MatcherIndex++];
2643 if (InputChain.getNode() == 0)
2644 InputChain = CurDAG->getEntryNode();
2646 InputChain = CurDAG->getCopyToReg(InputChain, SDLoc(NodeToMatch),
2647 DestPhysReg, RecordedNodes[RecNo].first,
2650 InputGlue = InputChain.getValue(1);
2654 case OPC_EmitNodeXForm: {
2655 unsigned XFormNo = MatcherTable[MatcherIndex++];
2656 unsigned RecNo = MatcherTable[MatcherIndex++];
2657 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2658 SDValue Res = RunSDNodeXForm(RecordedNodes[RecNo].first, XFormNo);
2659 RecordedNodes.push_back(std::pair<SDValue,SDNode*>(Res, (SDNode*) 0));
2664 case OPC_MorphNodeTo: {
2665 uint16_t TargetOpc = MatcherTable[MatcherIndex++];
2666 TargetOpc |= (unsigned short)MatcherTable[MatcherIndex++] << 8;
2667 unsigned EmitNodeInfo = MatcherTable[MatcherIndex++];
2668 // Get the result VT list.
2669 unsigned NumVTs = MatcherTable[MatcherIndex++];
2670 SmallVector<EVT, 4> VTs;
2671 for (unsigned i = 0; i != NumVTs; ++i) {
2672 MVT::SimpleValueType VT =
2673 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2674 if (VT == MVT::iPTR) VT = getTargetLowering()->getPointerTy().SimpleTy;
2678 if (EmitNodeInfo & OPFL_Chain)
2679 VTs.push_back(MVT::Other);
2680 if (EmitNodeInfo & OPFL_GlueOutput)
2681 VTs.push_back(MVT::Glue);
2683 // This is hot code, so optimize the two most common cases of 1 and 2
2686 if (VTs.size() == 1)
2687 VTList = CurDAG->getVTList(VTs[0]);
2688 else if (VTs.size() == 2)
2689 VTList = CurDAG->getVTList(VTs[0], VTs[1]);
2691 VTList = CurDAG->getVTList(VTs.data(), VTs.size());
2693 // Get the operand list.
2694 unsigned NumOps = MatcherTable[MatcherIndex++];
2695 SmallVector<SDValue, 8> Ops;
2696 for (unsigned i = 0; i != NumOps; ++i) {
2697 unsigned RecNo = MatcherTable[MatcherIndex++];
2699 RecNo = GetVBR(RecNo, MatcherTable, MatcherIndex);
2701 assert(RecNo < RecordedNodes.size() && "Invalid EmitNode");
2702 Ops.push_back(RecordedNodes[RecNo].first);
2705 // If there are variadic operands to add, handle them now.
2706 if (EmitNodeInfo & OPFL_VariadicInfo) {
2707 // Determine the start index to copy from.
2708 unsigned FirstOpToCopy = getNumFixedFromVariadicInfo(EmitNodeInfo);
2709 FirstOpToCopy += (EmitNodeInfo & OPFL_Chain) ? 1 : 0;
2710 assert(NodeToMatch->getNumOperands() >= FirstOpToCopy &&
2711 "Invalid variadic node");
2712 // Copy all of the variadic operands, not including a potential glue
2714 for (unsigned i = FirstOpToCopy, e = NodeToMatch->getNumOperands();
2716 SDValue V = NodeToMatch->getOperand(i);
2717 if (V.getValueType() == MVT::Glue) break;
2722 // If this has chain/glue inputs, add them.
2723 if (EmitNodeInfo & OPFL_Chain)
2724 Ops.push_back(InputChain);
2725 if ((EmitNodeInfo & OPFL_GlueInput) && InputGlue.getNode() != 0)
2726 Ops.push_back(InputGlue);
2730 if (Opcode != OPC_MorphNodeTo) {
2731 // If this is a normal EmitNode command, just create the new node and
2732 // add the results to the RecordedNodes list.
2733 Res = CurDAG->getMachineNode(TargetOpc, SDLoc(NodeToMatch),
2736 // Add all the non-glue/non-chain results to the RecordedNodes list.
2737 for (unsigned i = 0, e = VTs.size(); i != e; ++i) {
2738 if (VTs[i] == MVT::Other || VTs[i] == MVT::Glue) break;
2739 RecordedNodes.push_back(std::pair<SDValue,SDNode*>(SDValue(Res, i),
2743 } else if (NodeToMatch->getOpcode() != ISD::DELETED_NODE) {
2744 Res = MorphNode(NodeToMatch, TargetOpc, VTList, Ops.data(), Ops.size(),
2747 // NodeToMatch was eliminated by CSE when the target changed the DAG.
2748 // We will visit the equivalent node later.
2749 DEBUG(dbgs() << "Node was eliminated by CSE\n");
2753 // If the node had chain/glue results, update our notion of the current
2755 if (EmitNodeInfo & OPFL_GlueOutput) {
2756 InputGlue = SDValue(Res, VTs.size()-1);
2757 if (EmitNodeInfo & OPFL_Chain)
2758 InputChain = SDValue(Res, VTs.size()-2);
2759 } else if (EmitNodeInfo & OPFL_Chain)
2760 InputChain = SDValue(Res, VTs.size()-1);
2762 // If the OPFL_MemRefs glue is set on this node, slap all of the
2763 // accumulated memrefs onto it.
2765 // FIXME: This is vastly incorrect for patterns with multiple outputs
2766 // instructions that access memory and for ComplexPatterns that match
2768 if (EmitNodeInfo & OPFL_MemRefs) {
2769 // Only attach load or store memory operands if the generated
2770 // instruction may load or store.
2771 const MCInstrDesc &MCID = TM.getInstrInfo()->get(TargetOpc);
2772 bool mayLoad = MCID.mayLoad();
2773 bool mayStore = MCID.mayStore();
2775 unsigned NumMemRefs = 0;
2776 for (SmallVectorImpl<MachineMemOperand *>::const_iterator I =
2777 MatchedMemRefs.begin(), E = MatchedMemRefs.end(); I != E; ++I) {
2778 if ((*I)->isLoad()) {
2781 } else if ((*I)->isStore()) {
2789 MachineSDNode::mmo_iterator MemRefs =
2790 MF->allocateMemRefsArray(NumMemRefs);
2792 MachineSDNode::mmo_iterator MemRefsPos = MemRefs;
2793 for (SmallVectorImpl<MachineMemOperand *>::const_iterator I =
2794 MatchedMemRefs.begin(), E = MatchedMemRefs.end(); I != E; ++I) {
2795 if ((*I)->isLoad()) {
2798 } else if ((*I)->isStore()) {
2806 cast<MachineSDNode>(Res)
2807 ->setMemRefs(MemRefs, MemRefs + NumMemRefs);
2811 << (Opcode == OPC_MorphNodeTo ? "Morphed" : "Created")
2812 << " node: "; Res->dump(CurDAG); dbgs() << "\n");
2814 // If this was a MorphNodeTo then we're completely done!
2815 if (Opcode == OPC_MorphNodeTo) {
2816 // Update chain and glue uses.
2817 UpdateChainsAndGlue(NodeToMatch, InputChain, ChainNodesMatched,
2818 InputGlue, GlueResultNodesMatched, true);
2825 case OPC_MarkGlueResults: {
2826 unsigned NumNodes = MatcherTable[MatcherIndex++];
2828 // Read and remember all the glue-result nodes.
2829 for (unsigned i = 0; i != NumNodes; ++i) {
2830 unsigned RecNo = MatcherTable[MatcherIndex++];
2832 RecNo = GetVBR(RecNo, MatcherTable, MatcherIndex);
2834 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2835 GlueResultNodesMatched.push_back(RecordedNodes[RecNo].first.getNode());
2840 case OPC_CompleteMatch: {
2841 // The match has been completed, and any new nodes (if any) have been
2842 // created. Patch up references to the matched dag to use the newly
2844 unsigned NumResults = MatcherTable[MatcherIndex++];
2846 for (unsigned i = 0; i != NumResults; ++i) {
2847 unsigned ResSlot = MatcherTable[MatcherIndex++];
2849 ResSlot = GetVBR(ResSlot, MatcherTable, MatcherIndex);
2851 assert(ResSlot < RecordedNodes.size() && "Invalid CheckSame");
2852 SDValue Res = RecordedNodes[ResSlot].first;
2854 assert(i < NodeToMatch->getNumValues() &&
2855 NodeToMatch->getValueType(i) != MVT::Other &&
2856 NodeToMatch->getValueType(i) != MVT::Glue &&
2857 "Invalid number of results to complete!");
2858 assert((NodeToMatch->getValueType(i) == Res.getValueType() ||
2859 NodeToMatch->getValueType(i) == MVT::iPTR ||
2860 Res.getValueType() == MVT::iPTR ||
2861 NodeToMatch->getValueType(i).getSizeInBits() ==
2862 Res.getValueType().getSizeInBits()) &&
2863 "invalid replacement");
2864 CurDAG->ReplaceAllUsesOfValueWith(SDValue(NodeToMatch, i), Res);
2867 // If the root node defines glue, add it to the glue nodes to update list.
2868 if (NodeToMatch->getValueType(NodeToMatch->getNumValues()-1) == MVT::Glue)
2869 GlueResultNodesMatched.push_back(NodeToMatch);
2871 // Update chain and glue uses.
2872 UpdateChainsAndGlue(NodeToMatch, InputChain, ChainNodesMatched,
2873 InputGlue, GlueResultNodesMatched, false);
2875 assert(NodeToMatch->use_empty() &&
2876 "Didn't replace all uses of the node?");
2878 // FIXME: We just return here, which interacts correctly with SelectRoot
2879 // above. We should fix this to not return an SDNode* anymore.
2884 // If the code reached this point, then the match failed. See if there is
2885 // another child to try in the current 'Scope', otherwise pop it until we
2886 // find a case to check.
2887 DEBUG(dbgs() << " Match failed at index " << CurrentOpcodeIndex << "\n");
2888 ++NumDAGIselRetries;
2890 if (MatchScopes.empty()) {
2891 CannotYetSelect(NodeToMatch);
2895 // Restore the interpreter state back to the point where the scope was
2897 MatchScope &LastScope = MatchScopes.back();
2898 RecordedNodes.resize(LastScope.NumRecordedNodes);
2900 NodeStack.append(LastScope.NodeStack.begin(), LastScope.NodeStack.end());
2901 N = NodeStack.back();
2903 if (LastScope.NumMatchedMemRefs != MatchedMemRefs.size())
2904 MatchedMemRefs.resize(LastScope.NumMatchedMemRefs);
2905 MatcherIndex = LastScope.FailIndex;
2907 DEBUG(dbgs() << " Continuing at " << MatcherIndex << "\n");
2909 InputChain = LastScope.InputChain;
2910 InputGlue = LastScope.InputGlue;
2911 if (!LastScope.HasChainNodesMatched)
2912 ChainNodesMatched.clear();
2913 if (!LastScope.HasGlueResultNodesMatched)
2914 GlueResultNodesMatched.clear();
2916 // Check to see what the offset is at the new MatcherIndex. If it is zero
2917 // we have reached the end of this scope, otherwise we have another child
2918 // in the current scope to try.
2919 unsigned NumToSkip = MatcherTable[MatcherIndex++];
2920 if (NumToSkip & 128)
2921 NumToSkip = GetVBR(NumToSkip, MatcherTable, MatcherIndex);
2923 // If we have another child in this scope to match, update FailIndex and
2925 if (NumToSkip != 0) {
2926 LastScope.FailIndex = MatcherIndex+NumToSkip;
2930 // End of this scope, pop it and try the next child in the containing
2932 MatchScopes.pop_back();
2939 void SelectionDAGISel::CannotYetSelect(SDNode *N) {
2941 raw_string_ostream Msg(msg);
2942 Msg << "Cannot select: ";
2944 if (N->getOpcode() != ISD::INTRINSIC_W_CHAIN &&
2945 N->getOpcode() != ISD::INTRINSIC_WO_CHAIN &&
2946 N->getOpcode() != ISD::INTRINSIC_VOID) {
2947 N->printrFull(Msg, CurDAG);
2948 Msg << "\nIn function: " << MF->getName();
2950 bool HasInputChain = N->getOperand(0).getValueType() == MVT::Other;
2952 cast<ConstantSDNode>(N->getOperand(HasInputChain))->getZExtValue();
2953 if (iid < Intrinsic::num_intrinsics)
2954 Msg << "intrinsic %" << Intrinsic::getName((Intrinsic::ID)iid);
2955 else if (const TargetIntrinsicInfo *TII = TM.getIntrinsicInfo())
2956 Msg << "target intrinsic %" << TII->getName(iid);
2958 Msg << "unknown intrinsic #" << iid;
2960 report_fatal_error(Msg.str());
2963 char SelectionDAGISel::ID = 0;