1 //===-- SelectionDAGBuilder.cpp - Selection-DAG building ------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements routines for translating from LLVM IR into SelectionDAG IR.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "isel"
15 #include "SDNodeDbgValue.h"
16 #include "SelectionDAGBuilder.h"
17 #include "FunctionLoweringInfo.h"
18 #include "llvm/ADT/BitVector.h"
19 #include "llvm/ADT/SmallSet.h"
20 #include "llvm/Analysis/AliasAnalysis.h"
21 #include "llvm/Analysis/ConstantFolding.h"
22 #include "llvm/Constants.h"
23 #include "llvm/CallingConv.h"
24 #include "llvm/DerivedTypes.h"
25 #include "llvm/Function.h"
26 #include "llvm/GlobalVariable.h"
27 #include "llvm/InlineAsm.h"
28 #include "llvm/Instructions.h"
29 #include "llvm/Intrinsics.h"
30 #include "llvm/IntrinsicInst.h"
31 #include "llvm/LLVMContext.h"
32 #include "llvm/Module.h"
33 #include "llvm/CodeGen/Analysis.h"
34 #include "llvm/CodeGen/FastISel.h"
35 #include "llvm/CodeGen/GCStrategy.h"
36 #include "llvm/CodeGen/GCMetadata.h"
37 #include "llvm/CodeGen/MachineFunction.h"
38 #include "llvm/CodeGen/MachineFrameInfo.h"
39 #include "llvm/CodeGen/MachineInstrBuilder.h"
40 #include "llvm/CodeGen/MachineJumpTableInfo.h"
41 #include "llvm/CodeGen/MachineModuleInfo.h"
42 #include "llvm/CodeGen/MachineRegisterInfo.h"
43 #include "llvm/CodeGen/PseudoSourceValue.h"
44 #include "llvm/CodeGen/SelectionDAG.h"
45 #include "llvm/Analysis/DebugInfo.h"
46 #include "llvm/Target/TargetRegisterInfo.h"
47 #include "llvm/Target/TargetData.h"
48 #include "llvm/Target/TargetFrameInfo.h"
49 #include "llvm/Target/TargetInstrInfo.h"
50 #include "llvm/Target/TargetIntrinsicInfo.h"
51 #include "llvm/Target/TargetLowering.h"
52 #include "llvm/Target/TargetOptions.h"
53 #include "llvm/Support/Compiler.h"
54 #include "llvm/Support/CommandLine.h"
55 #include "llvm/Support/Debug.h"
56 #include "llvm/Support/ErrorHandling.h"
57 #include "llvm/Support/MathExtras.h"
58 #include "llvm/Support/raw_ostream.h"
62 /// LimitFloatPrecision - Generate low-precision inline sequences for
63 /// some float libcalls (6, 8 or 12 bits).
64 static unsigned LimitFloatPrecision;
66 static cl::opt<unsigned, true>
67 LimitFPPrecision("limit-float-precision",
68 cl::desc("Generate low-precision inline sequences "
69 "for some float libcalls"),
70 cl::location(LimitFloatPrecision),
74 /// RegsForValue - This struct represents the registers (physical or virtual)
75 /// that a particular set of values is assigned, and the type information
76 /// about the value. The most common situation is to represent one value at a
77 /// time, but struct or array values are handled element-wise as multiple
78 /// values. The splitting of aggregates is performed recursively, so that we
79 /// never have aggregate-typed registers. The values at this point do not
80 /// necessarily have legal types, so each value may require one or more
81 /// registers of some legal type.
84 /// TLI - The TargetLowering object.
86 const TargetLowering *TLI;
88 /// ValueVTs - The value types of the values, which may not be legal, and
89 /// may need be promoted or synthesized from one or more registers.
91 SmallVector<EVT, 4> ValueVTs;
93 /// RegVTs - The value types of the registers. This is the same size as
94 /// ValueVTs and it records, for each value, what the type of the assigned
95 /// register or registers are. (Individual values are never synthesized
96 /// from more than one type of register.)
98 /// With virtual registers, the contents of RegVTs is redundant with TLI's
99 /// getRegisterType member function, however when with physical registers
100 /// it is necessary to have a separate record of the types.
102 SmallVector<EVT, 4> RegVTs;
104 /// Regs - This list holds the registers assigned to the values.
105 /// Each legal or promoted value requires one register, and each
106 /// expanded value requires multiple registers.
108 SmallVector<unsigned, 4> Regs;
110 RegsForValue() : TLI(0) {}
112 RegsForValue(const TargetLowering &tli,
113 const SmallVector<unsigned, 4> ®s,
114 EVT regvt, EVT valuevt)
115 : TLI(&tli), ValueVTs(1, valuevt), RegVTs(1, regvt), Regs(regs) {}
116 RegsForValue(const TargetLowering &tli,
117 const SmallVector<unsigned, 4> ®s,
118 const SmallVector<EVT, 4> ®vts,
119 const SmallVector<EVT, 4> &valuevts)
120 : TLI(&tli), ValueVTs(valuevts), RegVTs(regvts), Regs(regs) {}
121 RegsForValue(LLVMContext &Context, const TargetLowering &tli,
122 unsigned Reg, const Type *Ty) : TLI(&tli) {
123 ComputeValueVTs(tli, Ty, ValueVTs);
125 for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) {
126 EVT ValueVT = ValueVTs[Value];
127 unsigned NumRegs = TLI->getNumRegisters(Context, ValueVT);
128 EVT RegisterVT = TLI->getRegisterType(Context, ValueVT);
129 for (unsigned i = 0; i != NumRegs; ++i)
130 Regs.push_back(Reg + i);
131 RegVTs.push_back(RegisterVT);
136 /// areValueTypesLegal - Return true if types of all the values are legal.
137 bool areValueTypesLegal() {
138 for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) {
139 EVT RegisterVT = RegVTs[Value];
140 if (!TLI->isTypeLegal(RegisterVT))
147 /// append - Add the specified values to this one.
148 void append(const RegsForValue &RHS) {
150 ValueVTs.append(RHS.ValueVTs.begin(), RHS.ValueVTs.end());
151 RegVTs.append(RHS.RegVTs.begin(), RHS.RegVTs.end());
152 Regs.append(RHS.Regs.begin(), RHS.Regs.end());
156 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from
157 /// this value and returns the result as a ValueVTs value. This uses
158 /// Chain/Flag as the input and updates them for the output Chain/Flag.
159 /// If the Flag pointer is NULL, no flag is used.
160 SDValue getCopyFromRegs(SelectionDAG &DAG, DebugLoc dl,
161 SDValue &Chain, SDValue *Flag) const;
163 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
164 /// specified value into the registers specified by this object. This uses
165 /// Chain/Flag as the input and updates them for the output Chain/Flag.
166 /// If the Flag pointer is NULL, no flag is used.
167 void getCopyToRegs(SDValue Val, SelectionDAG &DAG, DebugLoc dl,
168 SDValue &Chain, SDValue *Flag) const;
170 /// AddInlineAsmOperands - Add this value to the specified inlineasm node
171 /// operand list. This adds the code marker, matching input operand index
172 /// (if applicable), and includes the number of values added into it.
173 void AddInlineAsmOperands(unsigned Kind,
174 bool HasMatching, unsigned MatchingIdx,
176 std::vector<SDValue> &Ops) const;
180 /// getCopyFromParts - Create a value that contains the specified legal parts
181 /// combined into the value they represent. If the parts combine to a type
182 /// larger then ValueVT then AssertOp can be used to specify whether the extra
183 /// bits are known to be zero (ISD::AssertZext) or sign extended from ValueVT
184 /// (ISD::AssertSext).
185 static SDValue getCopyFromParts(SelectionDAG &DAG, DebugLoc dl,
186 const SDValue *Parts,
187 unsigned NumParts, EVT PartVT, EVT ValueVT,
188 ISD::NodeType AssertOp = ISD::DELETED_NODE) {
189 assert(NumParts > 0 && "No parts to assemble!");
190 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
191 SDValue Val = Parts[0];
194 // Assemble the value from multiple parts.
195 if (!ValueVT.isVector() && ValueVT.isInteger()) {
196 unsigned PartBits = PartVT.getSizeInBits();
197 unsigned ValueBits = ValueVT.getSizeInBits();
199 // Assemble the power of 2 part.
200 unsigned RoundParts = NumParts & (NumParts - 1) ?
201 1 << Log2_32(NumParts) : NumParts;
202 unsigned RoundBits = PartBits * RoundParts;
203 EVT RoundVT = RoundBits == ValueBits ?
204 ValueVT : EVT::getIntegerVT(*DAG.getContext(), RoundBits);
207 EVT HalfVT = EVT::getIntegerVT(*DAG.getContext(), RoundBits/2);
209 if (RoundParts > 2) {
210 Lo = getCopyFromParts(DAG, dl, Parts, RoundParts / 2,
212 Hi = getCopyFromParts(DAG, dl, Parts + RoundParts / 2,
213 RoundParts / 2, PartVT, HalfVT);
215 Lo = DAG.getNode(ISD::BIT_CONVERT, dl, HalfVT, Parts[0]);
216 Hi = DAG.getNode(ISD::BIT_CONVERT, dl, HalfVT, Parts[1]);
219 if (TLI.isBigEndian())
222 Val = DAG.getNode(ISD::BUILD_PAIR, dl, RoundVT, Lo, Hi);
224 if (RoundParts < NumParts) {
225 // Assemble the trailing non-power-of-2 part.
226 unsigned OddParts = NumParts - RoundParts;
227 EVT OddVT = EVT::getIntegerVT(*DAG.getContext(), OddParts * PartBits);
228 Hi = getCopyFromParts(DAG, dl,
229 Parts + RoundParts, OddParts, PartVT, OddVT);
231 // Combine the round and odd parts.
233 if (TLI.isBigEndian())
235 EVT TotalVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
236 Hi = DAG.getNode(ISD::ANY_EXTEND, dl, TotalVT, Hi);
237 Hi = DAG.getNode(ISD::SHL, dl, TotalVT, Hi,
238 DAG.getConstant(Lo.getValueType().getSizeInBits(),
239 TLI.getPointerTy()));
240 Lo = DAG.getNode(ISD::ZERO_EXTEND, dl, TotalVT, Lo);
241 Val = DAG.getNode(ISD::OR, dl, TotalVT, Lo, Hi);
243 } else if (ValueVT.isVector()) {
244 // Handle a multi-element vector.
245 EVT IntermediateVT, RegisterVT;
246 unsigned NumIntermediates;
248 TLI.getVectorTypeBreakdown(*DAG.getContext(), ValueVT, IntermediateVT,
249 NumIntermediates, RegisterVT);
250 assert(NumRegs == NumParts
251 && "Part count doesn't match vector breakdown!");
252 NumParts = NumRegs; // Silence a compiler warning.
253 assert(RegisterVT == PartVT
254 && "Part type doesn't match vector breakdown!");
255 assert(RegisterVT == Parts[0].getValueType() &&
256 "Part type doesn't match part!");
258 // Assemble the parts into intermediate operands.
259 SmallVector<SDValue, 8> Ops(NumIntermediates);
260 if (NumIntermediates == NumParts) {
261 // If the register was not expanded, truncate or copy the value,
263 for (unsigned i = 0; i != NumParts; ++i)
264 Ops[i] = getCopyFromParts(DAG, dl, &Parts[i], 1,
265 PartVT, IntermediateVT);
266 } else if (NumParts > 0) {
267 // If the intermediate type was expanded, build the intermediate
268 // operands from the parts.
269 assert(NumParts % NumIntermediates == 0 &&
270 "Must expand into a divisible number of parts!");
271 unsigned Factor = NumParts / NumIntermediates;
272 for (unsigned i = 0; i != NumIntermediates; ++i)
273 Ops[i] = getCopyFromParts(DAG, dl, &Parts[i * Factor], Factor,
274 PartVT, IntermediateVT);
277 // Build a vector with BUILD_VECTOR or CONCAT_VECTORS from the
278 // intermediate operands.
279 Val = DAG.getNode(IntermediateVT.isVector() ?
280 ISD::CONCAT_VECTORS : ISD::BUILD_VECTOR, dl,
281 ValueVT, &Ops[0], NumIntermediates);
282 } else if (PartVT.isFloatingPoint()) {
283 // FP split into multiple FP parts (for ppcf128)
284 assert(ValueVT == EVT(MVT::ppcf128) && PartVT == EVT(MVT::f64) &&
287 Lo = DAG.getNode(ISD::BIT_CONVERT, dl, EVT(MVT::f64), Parts[0]);
288 Hi = DAG.getNode(ISD::BIT_CONVERT, dl, EVT(MVT::f64), Parts[1]);
289 if (TLI.isBigEndian())
291 Val = DAG.getNode(ISD::BUILD_PAIR, dl, ValueVT, Lo, Hi);
293 // FP split into integer parts (soft fp)
294 assert(ValueVT.isFloatingPoint() && PartVT.isInteger() &&
295 !PartVT.isVector() && "Unexpected split");
296 EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), ValueVT.getSizeInBits());
297 Val = getCopyFromParts(DAG, dl, Parts, NumParts, PartVT, IntVT);
301 // There is now one part, held in Val. Correct it to match ValueVT.
302 PartVT = Val.getValueType();
304 if (PartVT == ValueVT)
307 if (PartVT.isVector()) {
308 assert(ValueVT.isVector() && "Unknown vector conversion!");
309 return DAG.getNode(ISD::BIT_CONVERT, dl, ValueVT, Val);
312 if (ValueVT.isVector()) {
313 assert(ValueVT.getVectorElementType() == PartVT &&
314 ValueVT.getVectorNumElements() == 1 &&
315 "Only trivial scalar-to-vector conversions should get here!");
316 return DAG.getNode(ISD::BUILD_VECTOR, dl, ValueVT, Val);
319 if (PartVT.isInteger() &&
320 ValueVT.isInteger()) {
321 if (ValueVT.bitsLT(PartVT)) {
322 // For a truncate, see if we have any information to
323 // indicate whether the truncated bits will always be
324 // zero or sign-extension.
325 if (AssertOp != ISD::DELETED_NODE)
326 Val = DAG.getNode(AssertOp, dl, PartVT, Val,
327 DAG.getValueType(ValueVT));
328 return DAG.getNode(ISD::TRUNCATE, dl, ValueVT, Val);
330 return DAG.getNode(ISD::ANY_EXTEND, dl, ValueVT, Val);
334 if (PartVT.isFloatingPoint() && ValueVT.isFloatingPoint()) {
335 if (ValueVT.bitsLT(Val.getValueType())) {
336 // FP_ROUND's are always exact here.
337 return DAG.getNode(ISD::FP_ROUND, dl, ValueVT, Val,
338 DAG.getIntPtrConstant(1));
341 return DAG.getNode(ISD::FP_EXTEND, dl, ValueVT, Val);
344 if (PartVT.getSizeInBits() == ValueVT.getSizeInBits())
345 return DAG.getNode(ISD::BIT_CONVERT, dl, ValueVT, Val);
347 llvm_unreachable("Unknown mismatch!");
351 /// getCopyToParts - Create a series of nodes that contain the specified value
352 /// split into legal parts. If the parts contain more bits than Val, then, for
353 /// integers, ExtendKind can be used to specify how to generate the extra bits.
354 static void getCopyToParts(SelectionDAG &DAG, DebugLoc dl,
355 SDValue Val, SDValue *Parts, unsigned NumParts,
357 ISD::NodeType ExtendKind = ISD::ANY_EXTEND) {
358 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
359 EVT PtrVT = TLI.getPointerTy();
360 EVT ValueVT = Val.getValueType();
361 unsigned PartBits = PartVT.getSizeInBits();
362 unsigned OrigNumParts = NumParts;
363 assert(TLI.isTypeLegal(PartVT) && "Copying to an illegal type!");
368 if (!ValueVT.isVector()) {
369 if (PartVT == ValueVT) {
370 assert(NumParts == 1 && "No-op copy with multiple parts!");
375 if (NumParts * PartBits > ValueVT.getSizeInBits()) {
376 // If the parts cover more bits than the value has, promote the value.
377 if (PartVT.isFloatingPoint() && ValueVT.isFloatingPoint()) {
378 assert(NumParts == 1 && "Do not know what to promote to!");
379 Val = DAG.getNode(ISD::FP_EXTEND, dl, PartVT, Val);
380 } else if (PartVT.isInteger() && ValueVT.isInteger()) {
381 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
382 Val = DAG.getNode(ExtendKind, dl, ValueVT, Val);
384 llvm_unreachable("Unknown mismatch!");
386 } else if (PartBits == ValueVT.getSizeInBits()) {
387 // Different types of the same size.
388 assert(NumParts == 1 && PartVT != ValueVT);
389 Val = DAG.getNode(ISD::BIT_CONVERT, dl, PartVT, Val);
390 } else if (NumParts * PartBits < ValueVT.getSizeInBits()) {
391 // If the parts cover less bits than value has, truncate the value.
392 if (PartVT.isInteger() && ValueVT.isInteger()) {
393 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
394 Val = DAG.getNode(ISD::TRUNCATE, dl, ValueVT, Val);
396 llvm_unreachable("Unknown mismatch!");
400 // The value may have changed - recompute ValueVT.
401 ValueVT = Val.getValueType();
402 assert(NumParts * PartBits == ValueVT.getSizeInBits() &&
403 "Failed to tile the value with PartVT!");
406 assert(PartVT == ValueVT && "Type conversion failed!");
411 // Expand the value into multiple parts.
412 if (NumParts & (NumParts - 1)) {
413 // The number of parts is not a power of 2. Split off and copy the tail.
414 assert(PartVT.isInteger() && ValueVT.isInteger() &&
415 "Do not know what to expand to!");
416 unsigned RoundParts = 1 << Log2_32(NumParts);
417 unsigned RoundBits = RoundParts * PartBits;
418 unsigned OddParts = NumParts - RoundParts;
419 SDValue OddVal = DAG.getNode(ISD::SRL, dl, ValueVT, Val,
420 DAG.getConstant(RoundBits,
421 TLI.getPointerTy()));
422 getCopyToParts(DAG, dl, OddVal, Parts + RoundParts,
425 if (TLI.isBigEndian())
426 // The odd parts were reversed by getCopyToParts - unreverse them.
427 std::reverse(Parts + RoundParts, Parts + NumParts);
429 NumParts = RoundParts;
430 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
431 Val = DAG.getNode(ISD::TRUNCATE, dl, ValueVT, Val);
434 // The number of parts is a power of 2. Repeatedly bisect the value using
436 Parts[0] = DAG.getNode(ISD::BIT_CONVERT, dl,
437 EVT::getIntegerVT(*DAG.getContext(),
438 ValueVT.getSizeInBits()),
441 for (unsigned StepSize = NumParts; StepSize > 1; StepSize /= 2) {
442 for (unsigned i = 0; i < NumParts; i += StepSize) {
443 unsigned ThisBits = StepSize * PartBits / 2;
444 EVT ThisVT = EVT::getIntegerVT(*DAG.getContext(), ThisBits);
445 SDValue &Part0 = Parts[i];
446 SDValue &Part1 = Parts[i+StepSize/2];
448 Part1 = DAG.getNode(ISD::EXTRACT_ELEMENT, dl,
450 DAG.getConstant(1, PtrVT));
451 Part0 = DAG.getNode(ISD::EXTRACT_ELEMENT, dl,
453 DAG.getConstant(0, PtrVT));
455 if (ThisBits == PartBits && ThisVT != PartVT) {
456 Part0 = DAG.getNode(ISD::BIT_CONVERT, dl,
458 Part1 = DAG.getNode(ISD::BIT_CONVERT, dl,
464 if (TLI.isBigEndian())
465 std::reverse(Parts, Parts + OrigNumParts);
472 if (PartVT != ValueVT) {
473 if (PartVT.getSizeInBits() == ValueVT.getSizeInBits()) {
474 Val = DAG.getNode(ISD::BIT_CONVERT, dl, PartVT, Val);
476 assert(ValueVT.getVectorElementType() == PartVT &&
477 ValueVT.getVectorNumElements() == 1 &&
478 "Only trivial vector-to-scalar conversions should get here!");
479 Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
481 DAG.getConstant(0, PtrVT));
489 // Handle a multi-element vector.
490 EVT IntermediateVT, RegisterVT;
491 unsigned NumIntermediates;
492 unsigned NumRegs = TLI.getVectorTypeBreakdown(*DAG.getContext(), ValueVT,
493 IntermediateVT, NumIntermediates, RegisterVT);
494 unsigned NumElements = ValueVT.getVectorNumElements();
496 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!");
497 NumParts = NumRegs; // Silence a compiler warning.
498 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!");
500 // Split the vector into intermediate operands.
501 SmallVector<SDValue, 8> Ops(NumIntermediates);
502 for (unsigned i = 0; i != NumIntermediates; ++i) {
503 if (IntermediateVT.isVector())
504 Ops[i] = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl,
506 DAG.getConstant(i * (NumElements / NumIntermediates),
509 Ops[i] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
511 DAG.getConstant(i, PtrVT));
514 // Split the intermediate operands into legal parts.
515 if (NumParts == NumIntermediates) {
516 // If the register was not expanded, promote or copy the value,
518 for (unsigned i = 0; i != NumParts; ++i)
519 getCopyToParts(DAG, dl, Ops[i], &Parts[i], 1, PartVT);
520 } else if (NumParts > 0) {
521 // If the intermediate type was expanded, split each the value into
523 assert(NumParts % NumIntermediates == 0 &&
524 "Must expand into a divisible number of parts!");
525 unsigned Factor = NumParts / NumIntermediates;
526 for (unsigned i = 0; i != NumIntermediates; ++i)
527 getCopyToParts(DAG, dl, Ops[i], &Parts[i*Factor], Factor, PartVT);
532 void SelectionDAGBuilder::init(GCFunctionInfo *gfi, AliasAnalysis &aa) {
535 TD = DAG.getTarget().getTargetData();
538 /// clear - Clear out the current SelectionDAG and the associated
539 /// state and prepare this SelectionDAGBuilder object to be used
540 /// for a new block. This doesn't clear out information about
541 /// additional blocks that are needed to complete switch lowering
542 /// or PHI node updating; that information is cleared out as it is
544 void SelectionDAGBuilder::clear() {
546 PendingLoads.clear();
547 PendingExports.clear();
548 CurDebugLoc = DebugLoc();
552 /// getRoot - Return the current virtual root of the Selection DAG,
553 /// flushing any PendingLoad items. This must be done before emitting
554 /// a store or any other node that may need to be ordered after any
555 /// prior load instructions.
557 SDValue SelectionDAGBuilder::getRoot() {
558 if (PendingLoads.empty())
559 return DAG.getRoot();
561 if (PendingLoads.size() == 1) {
562 SDValue Root = PendingLoads[0];
564 PendingLoads.clear();
568 // Otherwise, we have to make a token factor node.
569 SDValue Root = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), MVT::Other,
570 &PendingLoads[0], PendingLoads.size());
571 PendingLoads.clear();
576 /// getControlRoot - Similar to getRoot, but instead of flushing all the
577 /// PendingLoad items, flush all the PendingExports items. It is necessary
578 /// to do this before emitting a terminator instruction.
580 SDValue SelectionDAGBuilder::getControlRoot() {
581 SDValue Root = DAG.getRoot();
583 if (PendingExports.empty())
586 // Turn all of the CopyToReg chains into one factored node.
587 if (Root.getOpcode() != ISD::EntryToken) {
588 unsigned i = 0, e = PendingExports.size();
589 for (; i != e; ++i) {
590 assert(PendingExports[i].getNode()->getNumOperands() > 1);
591 if (PendingExports[i].getNode()->getOperand(0) == Root)
592 break; // Don't add the root if we already indirectly depend on it.
596 PendingExports.push_back(Root);
599 Root = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), MVT::Other,
601 PendingExports.size());
602 PendingExports.clear();
607 void SelectionDAGBuilder::AssignOrderingToNode(const SDNode *Node) {
608 if (DAG.GetOrdering(Node) != 0) return; // Already has ordering.
609 DAG.AssignOrdering(Node, SDNodeOrder);
611 for (unsigned I = 0, E = Node->getNumOperands(); I != E; ++I)
612 AssignOrderingToNode(Node->getOperand(I).getNode());
615 void SelectionDAGBuilder::visit(const Instruction &I) {
616 // Set up outgoing PHI node register values before emitting the terminator.
617 if (isa<TerminatorInst>(&I))
618 HandlePHINodesInSuccessorBlocks(I.getParent());
620 CurDebugLoc = I.getDebugLoc();
622 visit(I.getOpcode(), I);
624 if (!isa<TerminatorInst>(&I) && !HasTailCall)
625 CopyToExportRegsIfNeeded(&I);
627 CurDebugLoc = DebugLoc();
630 void SelectionDAGBuilder::visitPHI(const PHINode &) {
631 llvm_unreachable("SelectionDAGBuilder shouldn't visit PHI nodes!");
634 void SelectionDAGBuilder::visit(unsigned Opcode, const User &I) {
635 // Note: this doesn't use InstVisitor, because it has to work with
636 // ConstantExpr's in addition to instructions.
638 default: llvm_unreachable("Unknown instruction type encountered!");
639 // Build the switch statement using the Instruction.def file.
640 #define HANDLE_INST(NUM, OPCODE, CLASS) \
641 case Instruction::OPCODE: visit##OPCODE((CLASS&)I); break;
642 #include "llvm/Instruction.def"
645 // Assign the ordering to the freshly created DAG nodes.
646 if (NodeMap.count(&I)) {
648 AssignOrderingToNode(getValue(&I).getNode());
652 SDValue SelectionDAGBuilder::getValue(const Value *V) {
653 SDValue &N = NodeMap[V];
654 if (N.getNode()) return N;
656 if (const Constant *C = dyn_cast<Constant>(V)) {
657 EVT VT = TLI.getValueType(V->getType(), true);
659 if (const ConstantInt *CI = dyn_cast<ConstantInt>(C))
660 return N = DAG.getConstant(*CI, VT);
662 if (const GlobalValue *GV = dyn_cast<GlobalValue>(C))
663 return N = DAG.getGlobalAddress(GV, VT);
665 if (isa<ConstantPointerNull>(C))
666 return N = DAG.getConstant(0, TLI.getPointerTy());
668 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(C))
669 return N = DAG.getConstantFP(*CFP, VT);
671 if (isa<UndefValue>(C) && !V->getType()->isAggregateType())
672 return N = DAG.getUNDEF(VT);
674 if (const ConstantExpr *CE = dyn_cast<ConstantExpr>(C)) {
675 visit(CE->getOpcode(), *CE);
676 SDValue N1 = NodeMap[V];
677 assert(N1.getNode() && "visit didn't populate the NodeMap!");
681 if (isa<ConstantStruct>(C) || isa<ConstantArray>(C)) {
682 SmallVector<SDValue, 4> Constants;
683 for (User::const_op_iterator OI = C->op_begin(), OE = C->op_end();
685 SDNode *Val = getValue(*OI).getNode();
686 // If the operand is an empty aggregate, there are no values.
688 // Add each leaf value from the operand to the Constants list
689 // to form a flattened list of all the values.
690 for (unsigned i = 0, e = Val->getNumValues(); i != e; ++i)
691 Constants.push_back(SDValue(Val, i));
694 return DAG.getMergeValues(&Constants[0], Constants.size(),
698 if (C->getType()->isStructTy() || C->getType()->isArrayTy()) {
699 assert((isa<ConstantAggregateZero>(C) || isa<UndefValue>(C)) &&
700 "Unknown struct or array constant!");
702 SmallVector<EVT, 4> ValueVTs;
703 ComputeValueVTs(TLI, C->getType(), ValueVTs);
704 unsigned NumElts = ValueVTs.size();
706 return SDValue(); // empty struct
707 SmallVector<SDValue, 4> Constants(NumElts);
708 for (unsigned i = 0; i != NumElts; ++i) {
709 EVT EltVT = ValueVTs[i];
710 if (isa<UndefValue>(C))
711 Constants[i] = DAG.getUNDEF(EltVT);
712 else if (EltVT.isFloatingPoint())
713 Constants[i] = DAG.getConstantFP(0, EltVT);
715 Constants[i] = DAG.getConstant(0, EltVT);
718 return DAG.getMergeValues(&Constants[0], NumElts,
722 if (const BlockAddress *BA = dyn_cast<BlockAddress>(C))
723 return DAG.getBlockAddress(BA, VT);
725 const VectorType *VecTy = cast<VectorType>(V->getType());
726 unsigned NumElements = VecTy->getNumElements();
728 // Now that we know the number and type of the elements, get that number of
729 // elements into the Ops array based on what kind of constant it is.
730 SmallVector<SDValue, 16> Ops;
731 if (const ConstantVector *CP = dyn_cast<ConstantVector>(C)) {
732 for (unsigned i = 0; i != NumElements; ++i)
733 Ops.push_back(getValue(CP->getOperand(i)));
735 assert(isa<ConstantAggregateZero>(C) && "Unknown vector constant!");
736 EVT EltVT = TLI.getValueType(VecTy->getElementType());
739 if (EltVT.isFloatingPoint())
740 Op = DAG.getConstantFP(0, EltVT);
742 Op = DAG.getConstant(0, EltVT);
743 Ops.assign(NumElements, Op);
746 // Create a BUILD_VECTOR node.
747 return NodeMap[V] = DAG.getNode(ISD::BUILD_VECTOR, getCurDebugLoc(),
748 VT, &Ops[0], Ops.size());
751 // If this is a static alloca, generate it as the frameindex instead of
753 if (const AllocaInst *AI = dyn_cast<AllocaInst>(V)) {
754 DenseMap<const AllocaInst*, int>::iterator SI =
755 FuncInfo.StaticAllocaMap.find(AI);
756 if (SI != FuncInfo.StaticAllocaMap.end())
757 return DAG.getFrameIndex(SI->second, TLI.getPointerTy());
760 unsigned InReg = FuncInfo.ValueMap[V];
761 assert(InReg && "Value not in map!");
763 RegsForValue RFV(*DAG.getContext(), TLI, InReg, V->getType());
764 SDValue Chain = DAG.getEntryNode();
765 return RFV.getCopyFromRegs(DAG, getCurDebugLoc(), Chain, NULL);
768 /// Get the EVTs and ArgFlags collections that represent the legalized return
769 /// type of the given function. This does not require a DAG or a return value,
770 /// and is suitable for use before any DAGs for the function are constructed.
771 static void getReturnInfo(const Type* ReturnType,
772 Attributes attr, SmallVectorImpl<EVT> &OutVTs,
773 SmallVectorImpl<ISD::ArgFlagsTy> &OutFlags,
774 const TargetLowering &TLI,
775 SmallVectorImpl<uint64_t> *Offsets = 0) {
776 SmallVector<EVT, 4> ValueVTs;
777 ComputeValueVTs(TLI, ReturnType, ValueVTs);
778 unsigned NumValues = ValueVTs.size();
779 if (NumValues == 0) return;
782 for (unsigned j = 0, f = NumValues; j != f; ++j) {
783 EVT VT = ValueVTs[j];
784 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
786 if (attr & Attribute::SExt)
787 ExtendKind = ISD::SIGN_EXTEND;
788 else if (attr & Attribute::ZExt)
789 ExtendKind = ISD::ZERO_EXTEND;
791 // FIXME: C calling convention requires the return type to be promoted to
792 // at least 32-bit. But this is not necessary for non-C calling
793 // conventions. The frontend should mark functions whose return values
794 // require promoting with signext or zeroext attributes.
795 if (ExtendKind != ISD::ANY_EXTEND && VT.isInteger()) {
796 EVT MinVT = TLI.getRegisterType(ReturnType->getContext(), MVT::i32);
797 if (VT.bitsLT(MinVT))
801 unsigned NumParts = TLI.getNumRegisters(ReturnType->getContext(), VT);
802 EVT PartVT = TLI.getRegisterType(ReturnType->getContext(), VT);
803 unsigned PartSize = TLI.getTargetData()->getTypeAllocSize(
804 PartVT.getTypeForEVT(ReturnType->getContext()));
806 // 'inreg' on function refers to return value
807 ISD::ArgFlagsTy Flags = ISD::ArgFlagsTy();
808 if (attr & Attribute::InReg)
811 // Propagate extension type if any
812 if (attr & Attribute::SExt)
814 else if (attr & Attribute::ZExt)
817 for (unsigned i = 0; i < NumParts; ++i) {
818 OutVTs.push_back(PartVT);
819 OutFlags.push_back(Flags);
822 Offsets->push_back(Offset);
829 void SelectionDAGBuilder::visitRet(const ReturnInst &I) {
830 SDValue Chain = getControlRoot();
831 SmallVector<ISD::OutputArg, 8> Outs;
832 FunctionLoweringInfo &FLI = DAG.getFunctionLoweringInfo();
834 if (!FLI.CanLowerReturn) {
835 unsigned DemoteReg = FLI.DemoteRegister;
836 const Function *F = I.getParent()->getParent();
838 // Emit a store of the return value through the virtual register.
839 // Leave Outs empty so that LowerReturn won't try to load return
840 // registers the usual way.
841 SmallVector<EVT, 1> PtrValueVTs;
842 ComputeValueVTs(TLI, PointerType::getUnqual(F->getReturnType()),
845 SDValue RetPtr = DAG.getRegister(DemoteReg, PtrValueVTs[0]);
846 SDValue RetOp = getValue(I.getOperand(0));
848 SmallVector<EVT, 4> ValueVTs;
849 SmallVector<uint64_t, 4> Offsets;
850 ComputeValueVTs(TLI, I.getOperand(0)->getType(), ValueVTs, &Offsets);
851 unsigned NumValues = ValueVTs.size();
853 SmallVector<SDValue, 4> Chains(NumValues);
854 EVT PtrVT = PtrValueVTs[0];
855 for (unsigned i = 0; i != NumValues; ++i) {
856 SDValue Add = DAG.getNode(ISD::ADD, getCurDebugLoc(), PtrVT, RetPtr,
857 DAG.getConstant(Offsets[i], PtrVT));
859 DAG.getStore(Chain, getCurDebugLoc(),
860 SDValue(RetOp.getNode(), RetOp.getResNo() + i),
861 Add, NULL, Offsets[i], false, false, 0);
864 Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(),
865 MVT::Other, &Chains[0], NumValues);
866 } else if (I.getNumOperands() != 0) {
867 SmallVector<EVT, 4> ValueVTs;
868 ComputeValueVTs(TLI, I.getOperand(0)->getType(), ValueVTs);
869 unsigned NumValues = ValueVTs.size();
871 SDValue RetOp = getValue(I.getOperand(0));
872 for (unsigned j = 0, f = NumValues; j != f; ++j) {
873 EVT VT = ValueVTs[j];
875 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
877 const Function *F = I.getParent()->getParent();
878 if (F->paramHasAttr(0, Attribute::SExt))
879 ExtendKind = ISD::SIGN_EXTEND;
880 else if (F->paramHasAttr(0, Attribute::ZExt))
881 ExtendKind = ISD::ZERO_EXTEND;
883 // FIXME: C calling convention requires the return type to be promoted
884 // to at least 32-bit. But this is not necessary for non-C calling
885 // conventions. The frontend should mark functions whose return values
886 // require promoting with signext or zeroext attributes.
887 if (ExtendKind != ISD::ANY_EXTEND && VT.isInteger()) {
888 EVT MinVT = TLI.getRegisterType(*DAG.getContext(), MVT::i32);
889 if (VT.bitsLT(MinVT))
893 unsigned NumParts = TLI.getNumRegisters(*DAG.getContext(), VT);
894 EVT PartVT = TLI.getRegisterType(*DAG.getContext(), VT);
895 SmallVector<SDValue, 4> Parts(NumParts);
896 getCopyToParts(DAG, getCurDebugLoc(),
897 SDValue(RetOp.getNode(), RetOp.getResNo() + j),
898 &Parts[0], NumParts, PartVT, ExtendKind);
900 // 'inreg' on function refers to return value
901 ISD::ArgFlagsTy Flags = ISD::ArgFlagsTy();
902 if (F->paramHasAttr(0, Attribute::InReg))
905 // Propagate extension type if any
906 if (F->paramHasAttr(0, Attribute::SExt))
908 else if (F->paramHasAttr(0, Attribute::ZExt))
911 for (unsigned i = 0; i < NumParts; ++i)
912 Outs.push_back(ISD::OutputArg(Flags, Parts[i], /*isfixed=*/true));
917 bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg();
918 CallingConv::ID CallConv =
919 DAG.getMachineFunction().getFunction()->getCallingConv();
920 Chain = TLI.LowerReturn(Chain, CallConv, isVarArg,
921 Outs, getCurDebugLoc(), DAG);
923 // Verify that the target's LowerReturn behaved as expected.
924 assert(Chain.getNode() && Chain.getValueType() == MVT::Other &&
925 "LowerReturn didn't return a valid chain!");
927 // Update the DAG with the new chain value resulting from return lowering.
931 /// CopyToExportRegsIfNeeded - If the given value has virtual registers
932 /// created for it, emit nodes to copy the value into the virtual
934 void SelectionDAGBuilder::CopyToExportRegsIfNeeded(const Value *V) {
935 DenseMap<const Value *, unsigned>::iterator VMI = FuncInfo.ValueMap.find(V);
936 if (VMI != FuncInfo.ValueMap.end()) {
937 assert(!V->use_empty() && "Unused value assigned virtual registers!");
938 CopyValueToVirtualRegister(V, VMI->second);
942 /// ExportFromCurrentBlock - If this condition isn't known to be exported from
943 /// the current basic block, add it to ValueMap now so that we'll get a
945 void SelectionDAGBuilder::ExportFromCurrentBlock(const Value *V) {
946 // No need to export constants.
947 if (!isa<Instruction>(V) && !isa<Argument>(V)) return;
950 if (FuncInfo.isExportedInst(V)) return;
952 unsigned Reg = FuncInfo.InitializeRegForValue(V);
953 CopyValueToVirtualRegister(V, Reg);
956 bool SelectionDAGBuilder::isExportableFromCurrentBlock(const Value *V,
957 const BasicBlock *FromBB) {
958 // The operands of the setcc have to be in this block. We don't know
959 // how to export them from some other block.
960 if (const Instruction *VI = dyn_cast<Instruction>(V)) {
961 // Can export from current BB.
962 if (VI->getParent() == FromBB)
965 // Is already exported, noop.
966 return FuncInfo.isExportedInst(V);
969 // If this is an argument, we can export it if the BB is the entry block or
970 // if it is already exported.
971 if (isa<Argument>(V)) {
972 if (FromBB == &FromBB->getParent()->getEntryBlock())
975 // Otherwise, can only export this if it is already exported.
976 return FuncInfo.isExportedInst(V);
979 // Otherwise, constants can always be exported.
983 static bool InBlock(const Value *V, const BasicBlock *BB) {
984 if (const Instruction *I = dyn_cast<Instruction>(V))
985 return I->getParent() == BB;
989 /// EmitBranchForMergedCondition - Helper method for FindMergedConditions.
990 /// This function emits a branch and is used at the leaves of an OR or an
991 /// AND operator tree.
994 SelectionDAGBuilder::EmitBranchForMergedCondition(const Value *Cond,
995 MachineBasicBlock *TBB,
996 MachineBasicBlock *FBB,
997 MachineBasicBlock *CurBB,
998 MachineBasicBlock *SwitchBB) {
999 const BasicBlock *BB = CurBB->getBasicBlock();
1001 // If the leaf of the tree is a comparison, merge the condition into
1003 if (const CmpInst *BOp = dyn_cast<CmpInst>(Cond)) {
1004 // The operands of the cmp have to be in this block. We don't know
1005 // how to export them from some other block. If this is the first block
1006 // of the sequence, no exporting is needed.
1007 if (CurBB == SwitchBB ||
1008 (isExportableFromCurrentBlock(BOp->getOperand(0), BB) &&
1009 isExportableFromCurrentBlock(BOp->getOperand(1), BB))) {
1010 ISD::CondCode Condition;
1011 if (const ICmpInst *IC = dyn_cast<ICmpInst>(Cond)) {
1012 Condition = getICmpCondCode(IC->getPredicate());
1013 } else if (const FCmpInst *FC = dyn_cast<FCmpInst>(Cond)) {
1014 Condition = getFCmpCondCode(FC->getPredicate());
1016 Condition = ISD::SETEQ; // silence warning.
1017 llvm_unreachable("Unknown compare instruction");
1020 CaseBlock CB(Condition, BOp->getOperand(0),
1021 BOp->getOperand(1), NULL, TBB, FBB, CurBB);
1022 SwitchCases.push_back(CB);
1027 // Create a CaseBlock record representing this branch.
1028 CaseBlock CB(ISD::SETEQ, Cond, ConstantInt::getTrue(*DAG.getContext()),
1029 NULL, TBB, FBB, CurBB);
1030 SwitchCases.push_back(CB);
1033 /// FindMergedConditions - If Cond is an expression like
1034 void SelectionDAGBuilder::FindMergedConditions(const Value *Cond,
1035 MachineBasicBlock *TBB,
1036 MachineBasicBlock *FBB,
1037 MachineBasicBlock *CurBB,
1038 MachineBasicBlock *SwitchBB,
1040 // If this node is not part of the or/and tree, emit it as a branch.
1041 const Instruction *BOp = dyn_cast<Instruction>(Cond);
1042 if (!BOp || !(isa<BinaryOperator>(BOp) || isa<CmpInst>(BOp)) ||
1043 (unsigned)BOp->getOpcode() != Opc || !BOp->hasOneUse() ||
1044 BOp->getParent() != CurBB->getBasicBlock() ||
1045 !InBlock(BOp->getOperand(0), CurBB->getBasicBlock()) ||
1046 !InBlock(BOp->getOperand(1), CurBB->getBasicBlock())) {
1047 EmitBranchForMergedCondition(Cond, TBB, FBB, CurBB, SwitchBB);
1051 // Create TmpBB after CurBB.
1052 MachineFunction::iterator BBI = CurBB;
1053 MachineFunction &MF = DAG.getMachineFunction();
1054 MachineBasicBlock *TmpBB = MF.CreateMachineBasicBlock(CurBB->getBasicBlock());
1055 CurBB->getParent()->insert(++BBI, TmpBB);
1057 if (Opc == Instruction::Or) {
1058 // Codegen X | Y as:
1066 // Emit the LHS condition.
1067 FindMergedConditions(BOp->getOperand(0), TBB, TmpBB, CurBB, SwitchBB, Opc);
1069 // Emit the RHS condition into TmpBB.
1070 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, SwitchBB, Opc);
1072 assert(Opc == Instruction::And && "Unknown merge op!");
1073 // Codegen X & Y as:
1080 // This requires creation of TmpBB after CurBB.
1082 // Emit the LHS condition.
1083 FindMergedConditions(BOp->getOperand(0), TmpBB, FBB, CurBB, SwitchBB, Opc);
1085 // Emit the RHS condition into TmpBB.
1086 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, SwitchBB, Opc);
1090 /// If the set of cases should be emitted as a series of branches, return true.
1091 /// If we should emit this as a bunch of and/or'd together conditions, return
1094 SelectionDAGBuilder::ShouldEmitAsBranches(const std::vector<CaseBlock> &Cases){
1095 if (Cases.size() != 2) return true;
1097 // If this is two comparisons of the same values or'd or and'd together, they
1098 // will get folded into a single comparison, so don't emit two blocks.
1099 if ((Cases[0].CmpLHS == Cases[1].CmpLHS &&
1100 Cases[0].CmpRHS == Cases[1].CmpRHS) ||
1101 (Cases[0].CmpRHS == Cases[1].CmpLHS &&
1102 Cases[0].CmpLHS == Cases[1].CmpRHS)) {
1106 // Handle: (X != null) | (Y != null) --> (X|Y) != 0
1107 // Handle: (X == null) & (Y == null) --> (X|Y) == 0
1108 if (Cases[0].CmpRHS == Cases[1].CmpRHS &&
1109 Cases[0].CC == Cases[1].CC &&
1110 isa<Constant>(Cases[0].CmpRHS) &&
1111 cast<Constant>(Cases[0].CmpRHS)->isNullValue()) {
1112 if (Cases[0].CC == ISD::SETEQ && Cases[0].TrueBB == Cases[1].ThisBB)
1114 if (Cases[0].CC == ISD::SETNE && Cases[0].FalseBB == Cases[1].ThisBB)
1121 void SelectionDAGBuilder::visitBr(const BranchInst &I) {
1122 MachineBasicBlock *BrMBB = FuncInfo.MBBMap[I.getParent()];
1124 // Update machine-CFG edges.
1125 MachineBasicBlock *Succ0MBB = FuncInfo.MBBMap[I.getSuccessor(0)];
1127 // Figure out which block is immediately after the current one.
1128 MachineBasicBlock *NextBlock = 0;
1129 MachineFunction::iterator BBI = BrMBB;
1130 if (++BBI != FuncInfo.MF->end())
1133 if (I.isUnconditional()) {
1134 // Update machine-CFG edges.
1135 BrMBB->addSuccessor(Succ0MBB);
1137 // If this is not a fall-through branch, emit the branch.
1138 if (Succ0MBB != NextBlock)
1139 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(),
1140 MVT::Other, getControlRoot(),
1141 DAG.getBasicBlock(Succ0MBB)));
1146 // If this condition is one of the special cases we handle, do special stuff
1148 const Value *CondVal = I.getCondition();
1149 MachineBasicBlock *Succ1MBB = FuncInfo.MBBMap[I.getSuccessor(1)];
1151 // If this is a series of conditions that are or'd or and'd together, emit
1152 // this as a sequence of branches instead of setcc's with and/or operations.
1153 // For example, instead of something like:
1166 if (const BinaryOperator *BOp = dyn_cast<BinaryOperator>(CondVal)) {
1167 if (BOp->hasOneUse() &&
1168 (BOp->getOpcode() == Instruction::And ||
1169 BOp->getOpcode() == Instruction::Or)) {
1170 FindMergedConditions(BOp, Succ0MBB, Succ1MBB, BrMBB, BrMBB,
1172 // If the compares in later blocks need to use values not currently
1173 // exported from this block, export them now. This block should always
1174 // be the first entry.
1175 assert(SwitchCases[0].ThisBB == BrMBB && "Unexpected lowering!");
1177 // Allow some cases to be rejected.
1178 if (ShouldEmitAsBranches(SwitchCases)) {
1179 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i) {
1180 ExportFromCurrentBlock(SwitchCases[i].CmpLHS);
1181 ExportFromCurrentBlock(SwitchCases[i].CmpRHS);
1184 // Emit the branch for this block.
1185 visitSwitchCase(SwitchCases[0], BrMBB);
1186 SwitchCases.erase(SwitchCases.begin());
1190 // Okay, we decided not to do this, remove any inserted MBB's and clear
1192 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i)
1193 FuncInfo.MF->erase(SwitchCases[i].ThisBB);
1195 SwitchCases.clear();
1199 // Create a CaseBlock record representing this branch.
1200 CaseBlock CB(ISD::SETEQ, CondVal, ConstantInt::getTrue(*DAG.getContext()),
1201 NULL, Succ0MBB, Succ1MBB, BrMBB);
1203 // Use visitSwitchCase to actually insert the fast branch sequence for this
1205 visitSwitchCase(CB, BrMBB);
1208 /// visitSwitchCase - Emits the necessary code to represent a single node in
1209 /// the binary search tree resulting from lowering a switch instruction.
1210 void SelectionDAGBuilder::visitSwitchCase(CaseBlock &CB,
1211 MachineBasicBlock *SwitchBB) {
1213 SDValue CondLHS = getValue(CB.CmpLHS);
1214 DebugLoc dl = getCurDebugLoc();
1216 // Build the setcc now.
1217 if (CB.CmpMHS == NULL) {
1218 // Fold "(X == true)" to X and "(X == false)" to !X to
1219 // handle common cases produced by branch lowering.
1220 if (CB.CmpRHS == ConstantInt::getTrue(*DAG.getContext()) &&
1221 CB.CC == ISD::SETEQ)
1223 else if (CB.CmpRHS == ConstantInt::getFalse(*DAG.getContext()) &&
1224 CB.CC == ISD::SETEQ) {
1225 SDValue True = DAG.getConstant(1, CondLHS.getValueType());
1226 Cond = DAG.getNode(ISD::XOR, dl, CondLHS.getValueType(), CondLHS, True);
1228 Cond = DAG.getSetCC(dl, MVT::i1, CondLHS, getValue(CB.CmpRHS), CB.CC);
1230 assert(CB.CC == ISD::SETLE && "Can handle only LE ranges now");
1232 const APInt& Low = cast<ConstantInt>(CB.CmpLHS)->getValue();
1233 const APInt& High = cast<ConstantInt>(CB.CmpRHS)->getValue();
1235 SDValue CmpOp = getValue(CB.CmpMHS);
1236 EVT VT = CmpOp.getValueType();
1238 if (cast<ConstantInt>(CB.CmpLHS)->isMinValue(true)) {
1239 Cond = DAG.getSetCC(dl, MVT::i1, CmpOp, DAG.getConstant(High, VT),
1242 SDValue SUB = DAG.getNode(ISD::SUB, dl,
1243 VT, CmpOp, DAG.getConstant(Low, VT));
1244 Cond = DAG.getSetCC(dl, MVT::i1, SUB,
1245 DAG.getConstant(High-Low, VT), ISD::SETULE);
1249 // Update successor info
1250 SwitchBB->addSuccessor(CB.TrueBB);
1251 SwitchBB->addSuccessor(CB.FalseBB);
1253 // Set NextBlock to be the MBB immediately after the current one, if any.
1254 // This is used to avoid emitting unnecessary branches to the next block.
1255 MachineBasicBlock *NextBlock = 0;
1256 MachineFunction::iterator BBI = SwitchBB;
1257 if (++BBI != FuncInfo.MF->end())
1260 // If the lhs block is the next block, invert the condition so that we can
1261 // fall through to the lhs instead of the rhs block.
1262 if (CB.TrueBB == NextBlock) {
1263 std::swap(CB.TrueBB, CB.FalseBB);
1264 SDValue True = DAG.getConstant(1, Cond.getValueType());
1265 Cond = DAG.getNode(ISD::XOR, dl, Cond.getValueType(), Cond, True);
1268 SDValue BrCond = DAG.getNode(ISD::BRCOND, dl,
1269 MVT::Other, getControlRoot(), Cond,
1270 DAG.getBasicBlock(CB.TrueBB));
1272 // If the branch was constant folded, fix up the CFG.
1273 if (BrCond.getOpcode() == ISD::BR) {
1274 SwitchBB->removeSuccessor(CB.FalseBB);
1276 // Otherwise, go ahead and insert the false branch.
1277 if (BrCond == getControlRoot())
1278 SwitchBB->removeSuccessor(CB.TrueBB);
1280 if (CB.FalseBB != NextBlock)
1281 BrCond = DAG.getNode(ISD::BR, dl, MVT::Other, BrCond,
1282 DAG.getBasicBlock(CB.FalseBB));
1285 DAG.setRoot(BrCond);
1288 /// visitJumpTable - Emit JumpTable node in the current MBB
1289 void SelectionDAGBuilder::visitJumpTable(JumpTable &JT) {
1290 // Emit the code for the jump table
1291 assert(JT.Reg != -1U && "Should lower JT Header first!");
1292 EVT PTy = TLI.getPointerTy();
1293 SDValue Index = DAG.getCopyFromReg(getControlRoot(), getCurDebugLoc(),
1295 SDValue Table = DAG.getJumpTable(JT.JTI, PTy);
1296 SDValue BrJumpTable = DAG.getNode(ISD::BR_JT, getCurDebugLoc(),
1297 MVT::Other, Index.getValue(1),
1299 DAG.setRoot(BrJumpTable);
1302 /// visitJumpTableHeader - This function emits necessary code to produce index
1303 /// in the JumpTable from switch case.
1304 void SelectionDAGBuilder::visitJumpTableHeader(JumpTable &JT,
1305 JumpTableHeader &JTH,
1306 MachineBasicBlock *SwitchBB) {
1307 // Subtract the lowest switch case value from the value being switched on and
1308 // conditional branch to default mbb if the result is greater than the
1309 // difference between smallest and largest cases.
1310 SDValue SwitchOp = getValue(JTH.SValue);
1311 EVT VT = SwitchOp.getValueType();
1312 SDValue Sub = DAG.getNode(ISD::SUB, getCurDebugLoc(), VT, SwitchOp,
1313 DAG.getConstant(JTH.First, VT));
1315 // The SDNode we just created, which holds the value being switched on minus
1316 // the smallest case value, needs to be copied to a virtual register so it
1317 // can be used as an index into the jump table in a subsequent basic block.
1318 // This value may be smaller or larger than the target's pointer type, and
1319 // therefore require extension or truncating.
1320 SwitchOp = DAG.getZExtOrTrunc(Sub, getCurDebugLoc(), TLI.getPointerTy());
1322 unsigned JumpTableReg = FuncInfo.MakeReg(TLI.getPointerTy());
1323 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), getCurDebugLoc(),
1324 JumpTableReg, SwitchOp);
1325 JT.Reg = JumpTableReg;
1327 // Emit the range check for the jump table, and branch to the default block
1328 // for the switch statement if the value being switched on exceeds the largest
1329 // case in the switch.
1330 SDValue CMP = DAG.getSetCC(getCurDebugLoc(),
1331 TLI.getSetCCResultType(Sub.getValueType()), Sub,
1332 DAG.getConstant(JTH.Last-JTH.First,VT),
1335 // Set NextBlock to be the MBB immediately after the current one, if any.
1336 // This is used to avoid emitting unnecessary branches to the next block.
1337 MachineBasicBlock *NextBlock = 0;
1338 MachineFunction::iterator BBI = SwitchBB;
1340 if (++BBI != FuncInfo.MF->end())
1343 SDValue BrCond = DAG.getNode(ISD::BRCOND, getCurDebugLoc(),
1344 MVT::Other, CopyTo, CMP,
1345 DAG.getBasicBlock(JT.Default));
1347 if (JT.MBB != NextBlock)
1348 BrCond = DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, BrCond,
1349 DAG.getBasicBlock(JT.MBB));
1351 DAG.setRoot(BrCond);
1354 /// visitBitTestHeader - This function emits necessary code to produce value
1355 /// suitable for "bit tests"
1356 void SelectionDAGBuilder::visitBitTestHeader(BitTestBlock &B,
1357 MachineBasicBlock *SwitchBB) {
1358 // Subtract the minimum value
1359 SDValue SwitchOp = getValue(B.SValue);
1360 EVT VT = SwitchOp.getValueType();
1361 SDValue Sub = DAG.getNode(ISD::SUB, getCurDebugLoc(), VT, SwitchOp,
1362 DAG.getConstant(B.First, VT));
1365 SDValue RangeCmp = DAG.getSetCC(getCurDebugLoc(),
1366 TLI.getSetCCResultType(Sub.getValueType()),
1367 Sub, DAG.getConstant(B.Range, VT),
1370 SDValue ShiftOp = DAG.getZExtOrTrunc(Sub, getCurDebugLoc(),
1371 TLI.getPointerTy());
1373 B.Reg = FuncInfo.MakeReg(TLI.getPointerTy());
1374 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), getCurDebugLoc(),
1377 // Set NextBlock to be the MBB immediately after the current one, if any.
1378 // This is used to avoid emitting unnecessary branches to the next block.
1379 MachineBasicBlock *NextBlock = 0;
1380 MachineFunction::iterator BBI = SwitchBB;
1381 if (++BBI != FuncInfo.MF->end())
1384 MachineBasicBlock* MBB = B.Cases[0].ThisBB;
1386 SwitchBB->addSuccessor(B.Default);
1387 SwitchBB->addSuccessor(MBB);
1389 SDValue BrRange = DAG.getNode(ISD::BRCOND, getCurDebugLoc(),
1390 MVT::Other, CopyTo, RangeCmp,
1391 DAG.getBasicBlock(B.Default));
1393 if (MBB != NextBlock)
1394 BrRange = DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, CopyTo,
1395 DAG.getBasicBlock(MBB));
1397 DAG.setRoot(BrRange);
1400 /// visitBitTestCase - this function produces one "bit test"
1401 void SelectionDAGBuilder::visitBitTestCase(MachineBasicBlock* NextMBB,
1404 MachineBasicBlock *SwitchBB) {
1405 // Make desired shift
1406 SDValue ShiftOp = DAG.getCopyFromReg(getControlRoot(), getCurDebugLoc(), Reg,
1407 TLI.getPointerTy());
1408 SDValue SwitchVal = DAG.getNode(ISD::SHL, getCurDebugLoc(),
1410 DAG.getConstant(1, TLI.getPointerTy()),
1413 // Emit bit tests and jumps
1414 SDValue AndOp = DAG.getNode(ISD::AND, getCurDebugLoc(),
1415 TLI.getPointerTy(), SwitchVal,
1416 DAG.getConstant(B.Mask, TLI.getPointerTy()));
1417 SDValue AndCmp = DAG.getSetCC(getCurDebugLoc(),
1418 TLI.getSetCCResultType(AndOp.getValueType()),
1419 AndOp, DAG.getConstant(0, TLI.getPointerTy()),
1422 SwitchBB->addSuccessor(B.TargetBB);
1423 SwitchBB->addSuccessor(NextMBB);
1425 SDValue BrAnd = DAG.getNode(ISD::BRCOND, getCurDebugLoc(),
1426 MVT::Other, getControlRoot(),
1427 AndCmp, DAG.getBasicBlock(B.TargetBB));
1429 // Set NextBlock to be the MBB immediately after the current one, if any.
1430 // This is used to avoid emitting unnecessary branches to the next block.
1431 MachineBasicBlock *NextBlock = 0;
1432 MachineFunction::iterator BBI = SwitchBB;
1433 if (++BBI != FuncInfo.MF->end())
1436 if (NextMBB != NextBlock)
1437 BrAnd = DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, BrAnd,
1438 DAG.getBasicBlock(NextMBB));
1443 void SelectionDAGBuilder::visitInvoke(const InvokeInst &I) {
1444 MachineBasicBlock *InvokeMBB = FuncInfo.MBBMap[I.getParent()];
1446 // Retrieve successors.
1447 MachineBasicBlock *Return = FuncInfo.MBBMap[I.getSuccessor(0)];
1448 MachineBasicBlock *LandingPad = FuncInfo.MBBMap[I.getSuccessor(1)];
1450 const Value *Callee(I.getCalledValue());
1451 if (isa<InlineAsm>(Callee))
1454 LowerCallTo(&I, getValue(Callee), false, LandingPad);
1456 // If the value of the invoke is used outside of its defining block, make it
1457 // available as a virtual register.
1458 CopyToExportRegsIfNeeded(&I);
1460 // Update successor info
1461 InvokeMBB->addSuccessor(Return);
1462 InvokeMBB->addSuccessor(LandingPad);
1464 // Drop into normal successor.
1465 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(),
1466 MVT::Other, getControlRoot(),
1467 DAG.getBasicBlock(Return)));
1470 void SelectionDAGBuilder::visitUnwind(const UnwindInst &I) {
1473 /// handleSmallSwitchCaseRange - Emit a series of specific tests (suitable for
1474 /// small case ranges).
1475 bool SelectionDAGBuilder::handleSmallSwitchRange(CaseRec& CR,
1476 CaseRecVector& WorkList,
1478 MachineBasicBlock *Default,
1479 MachineBasicBlock *SwitchBB) {
1480 Case& BackCase = *(CR.Range.second-1);
1482 // Size is the number of Cases represented by this range.
1483 size_t Size = CR.Range.second - CR.Range.first;
1487 // Get the MachineFunction which holds the current MBB. This is used when
1488 // inserting any additional MBBs necessary to represent the switch.
1489 MachineFunction *CurMF = FuncInfo.MF;
1491 // Figure out which block is immediately after the current one.
1492 MachineBasicBlock *NextBlock = 0;
1493 MachineFunction::iterator BBI = CR.CaseBB;
1495 if (++BBI != FuncInfo.MF->end())
1498 // TODO: If any two of the cases has the same destination, and if one value
1499 // is the same as the other, but has one bit unset that the other has set,
1500 // use bit manipulation to do two compares at once. For example:
1501 // "if (X == 6 || X == 4)" -> "if ((X|2) == 6)"
1503 // Rearrange the case blocks so that the last one falls through if possible.
1504 if (NextBlock && Default != NextBlock && BackCase.BB != NextBlock) {
1505 // The last case block won't fall through into 'NextBlock' if we emit the
1506 // branches in this order. See if rearranging a case value would help.
1507 for (CaseItr I = CR.Range.first, E = CR.Range.second-1; I != E; ++I) {
1508 if (I->BB == NextBlock) {
1509 std::swap(*I, BackCase);
1515 // Create a CaseBlock record representing a conditional branch to
1516 // the Case's target mbb if the value being switched on SV is equal
1518 MachineBasicBlock *CurBlock = CR.CaseBB;
1519 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++I) {
1520 MachineBasicBlock *FallThrough;
1522 FallThrough = CurMF->CreateMachineBasicBlock(CurBlock->getBasicBlock());
1523 CurMF->insert(BBI, FallThrough);
1525 // Put SV in a virtual register to make it available from the new blocks.
1526 ExportFromCurrentBlock(SV);
1528 // If the last case doesn't match, go to the default block.
1529 FallThrough = Default;
1532 const Value *RHS, *LHS, *MHS;
1534 if (I->High == I->Low) {
1535 // This is just small small case range :) containing exactly 1 case
1537 LHS = SV; RHS = I->High; MHS = NULL;
1540 LHS = I->Low; MHS = SV; RHS = I->High;
1542 CaseBlock CB(CC, LHS, RHS, MHS, I->BB, FallThrough, CurBlock);
1544 // If emitting the first comparison, just call visitSwitchCase to emit the
1545 // code into the current block. Otherwise, push the CaseBlock onto the
1546 // vector to be later processed by SDISel, and insert the node's MBB
1547 // before the next MBB.
1548 if (CurBlock == SwitchBB)
1549 visitSwitchCase(CB, SwitchBB);
1551 SwitchCases.push_back(CB);
1553 CurBlock = FallThrough;
1559 static inline bool areJTsAllowed(const TargetLowering &TLI) {
1560 return !DisableJumpTables &&
1561 (TLI.isOperationLegalOrCustom(ISD::BR_JT, MVT::Other) ||
1562 TLI.isOperationLegalOrCustom(ISD::BRIND, MVT::Other));
1565 static APInt ComputeRange(const APInt &First, const APInt &Last) {
1566 APInt LastExt(Last), FirstExt(First);
1567 uint32_t BitWidth = std::max(Last.getBitWidth(), First.getBitWidth()) + 1;
1568 LastExt.sext(BitWidth); FirstExt.sext(BitWidth);
1569 return (LastExt - FirstExt + 1ULL);
1572 /// handleJTSwitchCase - Emit jumptable for current switch case range
1573 bool SelectionDAGBuilder::handleJTSwitchCase(CaseRec& CR,
1574 CaseRecVector& WorkList,
1576 MachineBasicBlock* Default,
1577 MachineBasicBlock *SwitchBB) {
1578 Case& FrontCase = *CR.Range.first;
1579 Case& BackCase = *(CR.Range.second-1);
1581 const APInt &First = cast<ConstantInt>(FrontCase.Low)->getValue();
1582 const APInt &Last = cast<ConstantInt>(BackCase.High)->getValue();
1584 APInt TSize(First.getBitWidth(), 0);
1585 for (CaseItr I = CR.Range.first, E = CR.Range.second;
1589 if (!areJTsAllowed(TLI) || TSize.ult(4))
1592 APInt Range = ComputeRange(First, Last);
1593 double Density = TSize.roundToDouble() / Range.roundToDouble();
1597 DEBUG(dbgs() << "Lowering jump table\n"
1598 << "First entry: " << First << ". Last entry: " << Last << '\n'
1599 << "Range: " << Range
1600 << "Size: " << TSize << ". Density: " << Density << "\n\n");
1602 // Get the MachineFunction which holds the current MBB. This is used when
1603 // inserting any additional MBBs necessary to represent the switch.
1604 MachineFunction *CurMF = FuncInfo.MF;
1606 // Figure out which block is immediately after the current one.
1607 MachineFunction::iterator BBI = CR.CaseBB;
1610 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
1612 // Create a new basic block to hold the code for loading the address
1613 // of the jump table, and jumping to it. Update successor information;
1614 // we will either branch to the default case for the switch, or the jump
1616 MachineBasicBlock *JumpTableBB = CurMF->CreateMachineBasicBlock(LLVMBB);
1617 CurMF->insert(BBI, JumpTableBB);
1618 CR.CaseBB->addSuccessor(Default);
1619 CR.CaseBB->addSuccessor(JumpTableBB);
1621 // Build a vector of destination BBs, corresponding to each target
1622 // of the jump table. If the value of the jump table slot corresponds to
1623 // a case statement, push the case's BB onto the vector, otherwise, push
1625 std::vector<MachineBasicBlock*> DestBBs;
1627 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++TEI) {
1628 const APInt &Low = cast<ConstantInt>(I->Low)->getValue();
1629 const APInt &High = cast<ConstantInt>(I->High)->getValue();
1631 if (Low.sle(TEI) && TEI.sle(High)) {
1632 DestBBs.push_back(I->BB);
1636 DestBBs.push_back(Default);
1640 // Update successor info. Add one edge to each unique successor.
1641 BitVector SuccsHandled(CR.CaseBB->getParent()->getNumBlockIDs());
1642 for (std::vector<MachineBasicBlock*>::iterator I = DestBBs.begin(),
1643 E = DestBBs.end(); I != E; ++I) {
1644 if (!SuccsHandled[(*I)->getNumber()]) {
1645 SuccsHandled[(*I)->getNumber()] = true;
1646 JumpTableBB->addSuccessor(*I);
1650 // Create a jump table index for this jump table.
1651 unsigned JTEncoding = TLI.getJumpTableEncoding();
1652 unsigned JTI = CurMF->getOrCreateJumpTableInfo(JTEncoding)
1653 ->createJumpTableIndex(DestBBs);
1655 // Set the jump table information so that we can codegen it as a second
1656 // MachineBasicBlock
1657 JumpTable JT(-1U, JTI, JumpTableBB, Default);
1658 JumpTableHeader JTH(First, Last, SV, CR.CaseBB, (CR.CaseBB == SwitchBB));
1659 if (CR.CaseBB == SwitchBB)
1660 visitJumpTableHeader(JT, JTH, SwitchBB);
1662 JTCases.push_back(JumpTableBlock(JTH, JT));
1667 /// handleBTSplitSwitchCase - emit comparison and split binary search tree into
1669 bool SelectionDAGBuilder::handleBTSplitSwitchCase(CaseRec& CR,
1670 CaseRecVector& WorkList,
1672 MachineBasicBlock *Default,
1673 MachineBasicBlock *SwitchBB) {
1674 // Get the MachineFunction which holds the current MBB. This is used when
1675 // inserting any additional MBBs necessary to represent the switch.
1676 MachineFunction *CurMF = FuncInfo.MF;
1678 // Figure out which block is immediately after the current one.
1679 MachineFunction::iterator BBI = CR.CaseBB;
1682 Case& FrontCase = *CR.Range.first;
1683 Case& BackCase = *(CR.Range.second-1);
1684 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
1686 // Size is the number of Cases represented by this range.
1687 unsigned Size = CR.Range.second - CR.Range.first;
1689 const APInt &First = cast<ConstantInt>(FrontCase.Low)->getValue();
1690 const APInt &Last = cast<ConstantInt>(BackCase.High)->getValue();
1692 CaseItr Pivot = CR.Range.first + Size/2;
1694 // Select optimal pivot, maximizing sum density of LHS and RHS. This will
1695 // (heuristically) allow us to emit JumpTable's later.
1696 APInt TSize(First.getBitWidth(), 0);
1697 for (CaseItr I = CR.Range.first, E = CR.Range.second;
1701 APInt LSize = FrontCase.size();
1702 APInt RSize = TSize-LSize;
1703 DEBUG(dbgs() << "Selecting best pivot: \n"
1704 << "First: " << First << ", Last: " << Last <<'\n'
1705 << "LSize: " << LSize << ", RSize: " << RSize << '\n');
1706 for (CaseItr I = CR.Range.first, J=I+1, E = CR.Range.second;
1708 const APInt &LEnd = cast<ConstantInt>(I->High)->getValue();
1709 const APInt &RBegin = cast<ConstantInt>(J->Low)->getValue();
1710 APInt Range = ComputeRange(LEnd, RBegin);
1711 assert((Range - 2ULL).isNonNegative() &&
1712 "Invalid case distance");
1713 double LDensity = (double)LSize.roundToDouble() /
1714 (LEnd - First + 1ULL).roundToDouble();
1715 double RDensity = (double)RSize.roundToDouble() /
1716 (Last - RBegin + 1ULL).roundToDouble();
1717 double Metric = Range.logBase2()*(LDensity+RDensity);
1718 // Should always split in some non-trivial place
1719 DEBUG(dbgs() <<"=>Step\n"
1720 << "LEnd: " << LEnd << ", RBegin: " << RBegin << '\n'
1721 << "LDensity: " << LDensity
1722 << ", RDensity: " << RDensity << '\n'
1723 << "Metric: " << Metric << '\n');
1724 if (FMetric < Metric) {
1727 DEBUG(dbgs() << "Current metric set to: " << FMetric << '\n');
1733 if (areJTsAllowed(TLI)) {
1734 // If our case is dense we *really* should handle it earlier!
1735 assert((FMetric > 0) && "Should handle dense range earlier!");
1737 Pivot = CR.Range.first + Size/2;
1740 CaseRange LHSR(CR.Range.first, Pivot);
1741 CaseRange RHSR(Pivot, CR.Range.second);
1742 Constant *C = Pivot->Low;
1743 MachineBasicBlock *FalseBB = 0, *TrueBB = 0;
1745 // We know that we branch to the LHS if the Value being switched on is
1746 // less than the Pivot value, C. We use this to optimize our binary
1747 // tree a bit, by recognizing that if SV is greater than or equal to the
1748 // LHS's Case Value, and that Case Value is exactly one less than the
1749 // Pivot's Value, then we can branch directly to the LHS's Target,
1750 // rather than creating a leaf node for it.
1751 if ((LHSR.second - LHSR.first) == 1 &&
1752 LHSR.first->High == CR.GE &&
1753 cast<ConstantInt>(C)->getValue() ==
1754 (cast<ConstantInt>(CR.GE)->getValue() + 1LL)) {
1755 TrueBB = LHSR.first->BB;
1757 TrueBB = CurMF->CreateMachineBasicBlock(LLVMBB);
1758 CurMF->insert(BBI, TrueBB);
1759 WorkList.push_back(CaseRec(TrueBB, C, CR.GE, LHSR));
1761 // Put SV in a virtual register to make it available from the new blocks.
1762 ExportFromCurrentBlock(SV);
1765 // Similar to the optimization above, if the Value being switched on is
1766 // known to be less than the Constant CR.LT, and the current Case Value
1767 // is CR.LT - 1, then we can branch directly to the target block for
1768 // the current Case Value, rather than emitting a RHS leaf node for it.
1769 if ((RHSR.second - RHSR.first) == 1 && CR.LT &&
1770 cast<ConstantInt>(RHSR.first->Low)->getValue() ==
1771 (cast<ConstantInt>(CR.LT)->getValue() - 1LL)) {
1772 FalseBB = RHSR.first->BB;
1774 FalseBB = CurMF->CreateMachineBasicBlock(LLVMBB);
1775 CurMF->insert(BBI, FalseBB);
1776 WorkList.push_back(CaseRec(FalseBB,CR.LT,C,RHSR));
1778 // Put SV in a virtual register to make it available from the new blocks.
1779 ExportFromCurrentBlock(SV);
1782 // Create a CaseBlock record representing a conditional branch to
1783 // the LHS node if the value being switched on SV is less than C.
1784 // Otherwise, branch to LHS.
1785 CaseBlock CB(ISD::SETLT, SV, C, NULL, TrueBB, FalseBB, CR.CaseBB);
1787 if (CR.CaseBB == SwitchBB)
1788 visitSwitchCase(CB, SwitchBB);
1790 SwitchCases.push_back(CB);
1795 /// handleBitTestsSwitchCase - if current case range has few destination and
1796 /// range span less, than machine word bitwidth, encode case range into series
1797 /// of masks and emit bit tests with these masks.
1798 bool SelectionDAGBuilder::handleBitTestsSwitchCase(CaseRec& CR,
1799 CaseRecVector& WorkList,
1801 MachineBasicBlock* Default,
1802 MachineBasicBlock *SwitchBB){
1803 EVT PTy = TLI.getPointerTy();
1804 unsigned IntPtrBits = PTy.getSizeInBits();
1806 Case& FrontCase = *CR.Range.first;
1807 Case& BackCase = *(CR.Range.second-1);
1809 // Get the MachineFunction which holds the current MBB. This is used when
1810 // inserting any additional MBBs necessary to represent the switch.
1811 MachineFunction *CurMF = FuncInfo.MF;
1813 // If target does not have legal shift left, do not emit bit tests at all.
1814 if (!TLI.isOperationLegal(ISD::SHL, TLI.getPointerTy()))
1818 for (CaseItr I = CR.Range.first, E = CR.Range.second;
1820 // Single case counts one, case range - two.
1821 numCmps += (I->Low == I->High ? 1 : 2);
1824 // Count unique destinations
1825 SmallSet<MachineBasicBlock*, 4> Dests;
1826 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) {
1827 Dests.insert(I->BB);
1828 if (Dests.size() > 3)
1829 // Don't bother the code below, if there are too much unique destinations
1832 DEBUG(dbgs() << "Total number of unique destinations: "
1833 << Dests.size() << '\n'
1834 << "Total number of comparisons: " << numCmps << '\n');
1836 // Compute span of values.
1837 const APInt& minValue = cast<ConstantInt>(FrontCase.Low)->getValue();
1838 const APInt& maxValue = cast<ConstantInt>(BackCase.High)->getValue();
1839 APInt cmpRange = maxValue - minValue;
1841 DEBUG(dbgs() << "Compare range: " << cmpRange << '\n'
1842 << "Low bound: " << minValue << '\n'
1843 << "High bound: " << maxValue << '\n');
1845 if (cmpRange.uge(IntPtrBits) ||
1846 (!(Dests.size() == 1 && numCmps >= 3) &&
1847 !(Dests.size() == 2 && numCmps >= 5) &&
1848 !(Dests.size() >= 3 && numCmps >= 6)))
1851 DEBUG(dbgs() << "Emitting bit tests\n");
1852 APInt lowBound = APInt::getNullValue(cmpRange.getBitWidth());
1854 // Optimize the case where all the case values fit in a
1855 // word without having to subtract minValue. In this case,
1856 // we can optimize away the subtraction.
1857 if (minValue.isNonNegative() && maxValue.slt(IntPtrBits)) {
1858 cmpRange = maxValue;
1860 lowBound = minValue;
1863 CaseBitsVector CasesBits;
1864 unsigned i, count = 0;
1866 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) {
1867 MachineBasicBlock* Dest = I->BB;
1868 for (i = 0; i < count; ++i)
1869 if (Dest == CasesBits[i].BB)
1873 assert((count < 3) && "Too much destinations to test!");
1874 CasesBits.push_back(CaseBits(0, Dest, 0));
1878 const APInt& lowValue = cast<ConstantInt>(I->Low)->getValue();
1879 const APInt& highValue = cast<ConstantInt>(I->High)->getValue();
1881 uint64_t lo = (lowValue - lowBound).getZExtValue();
1882 uint64_t hi = (highValue - lowBound).getZExtValue();
1884 for (uint64_t j = lo; j <= hi; j++) {
1885 CasesBits[i].Mask |= 1ULL << j;
1886 CasesBits[i].Bits++;
1890 std::sort(CasesBits.begin(), CasesBits.end(), CaseBitsCmp());
1894 // Figure out which block is immediately after the current one.
1895 MachineFunction::iterator BBI = CR.CaseBB;
1898 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
1900 DEBUG(dbgs() << "Cases:\n");
1901 for (unsigned i = 0, e = CasesBits.size(); i!=e; ++i) {
1902 DEBUG(dbgs() << "Mask: " << CasesBits[i].Mask
1903 << ", Bits: " << CasesBits[i].Bits
1904 << ", BB: " << CasesBits[i].BB << '\n');
1906 MachineBasicBlock *CaseBB = CurMF->CreateMachineBasicBlock(LLVMBB);
1907 CurMF->insert(BBI, CaseBB);
1908 BTC.push_back(BitTestCase(CasesBits[i].Mask,
1912 // Put SV in a virtual register to make it available from the new blocks.
1913 ExportFromCurrentBlock(SV);
1916 BitTestBlock BTB(lowBound, cmpRange, SV,
1917 -1U, (CR.CaseBB == SwitchBB),
1918 CR.CaseBB, Default, BTC);
1920 if (CR.CaseBB == SwitchBB)
1921 visitBitTestHeader(BTB, SwitchBB);
1923 BitTestCases.push_back(BTB);
1928 /// Clusterify - Transform simple list of Cases into list of CaseRange's
1929 size_t SelectionDAGBuilder::Clusterify(CaseVector& Cases,
1930 const SwitchInst& SI) {
1933 // Start with "simple" cases
1934 for (size_t i = 1; i < SI.getNumSuccessors(); ++i) {
1935 MachineBasicBlock *SMBB = FuncInfo.MBBMap[SI.getSuccessor(i)];
1936 Cases.push_back(Case(SI.getSuccessorValue(i),
1937 SI.getSuccessorValue(i),
1940 std::sort(Cases.begin(), Cases.end(), CaseCmp());
1942 // Merge case into clusters
1943 if (Cases.size() >= 2)
1944 // Must recompute end() each iteration because it may be
1945 // invalidated by erase if we hold on to it
1946 for (CaseItr I = Cases.begin(), J = ++(Cases.begin()); J != Cases.end(); ) {
1947 const APInt& nextValue = cast<ConstantInt>(J->Low)->getValue();
1948 const APInt& currentValue = cast<ConstantInt>(I->High)->getValue();
1949 MachineBasicBlock* nextBB = J->BB;
1950 MachineBasicBlock* currentBB = I->BB;
1952 // If the two neighboring cases go to the same destination, merge them
1953 // into a single case.
1954 if ((nextValue - currentValue == 1) && (currentBB == nextBB)) {
1962 for (CaseItr I=Cases.begin(), E=Cases.end(); I!=E; ++I, ++numCmps) {
1963 if (I->Low != I->High)
1964 // A range counts double, since it requires two compares.
1971 void SelectionDAGBuilder::visitSwitch(const SwitchInst &SI) {
1972 MachineBasicBlock *SwitchMBB = FuncInfo.MBBMap[SI.getParent()];
1974 // Figure out which block is immediately after the current one.
1975 MachineBasicBlock *NextBlock = 0;
1976 MachineBasicBlock *Default = FuncInfo.MBBMap[SI.getDefaultDest()];
1978 // If there is only the default destination, branch to it if it is not the
1979 // next basic block. Otherwise, just fall through.
1980 if (SI.getNumOperands() == 2) {
1981 // Update machine-CFG edges.
1983 // If this is not a fall-through branch, emit the branch.
1984 SwitchMBB->addSuccessor(Default);
1985 if (Default != NextBlock)
1986 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(),
1987 MVT::Other, getControlRoot(),
1988 DAG.getBasicBlock(Default)));
1993 // If there are any non-default case statements, create a vector of Cases
1994 // representing each one, and sort the vector so that we can efficiently
1995 // create a binary search tree from them.
1997 size_t numCmps = Clusterify(Cases, SI);
1998 DEBUG(dbgs() << "Clusterify finished. Total clusters: " << Cases.size()
1999 << ". Total compares: " << numCmps << '\n');
2002 // Get the Value to be switched on and default basic blocks, which will be
2003 // inserted into CaseBlock records, representing basic blocks in the binary
2005 const Value *SV = SI.getOperand(0);
2007 // Push the initial CaseRec onto the worklist
2008 CaseRecVector WorkList;
2009 WorkList.push_back(CaseRec(SwitchMBB,0,0,
2010 CaseRange(Cases.begin(),Cases.end())));
2012 while (!WorkList.empty()) {
2013 // Grab a record representing a case range to process off the worklist
2014 CaseRec CR = WorkList.back();
2015 WorkList.pop_back();
2017 if (handleBitTestsSwitchCase(CR, WorkList, SV, Default, SwitchMBB))
2020 // If the range has few cases (two or less) emit a series of specific
2022 if (handleSmallSwitchRange(CR, WorkList, SV, Default, SwitchMBB))
2025 // If the switch has more than 5 blocks, and at least 40% dense, and the
2026 // target supports indirect branches, then emit a jump table rather than
2027 // lowering the switch to a binary tree of conditional branches.
2028 if (handleJTSwitchCase(CR, WorkList, SV, Default, SwitchMBB))
2031 // Emit binary tree. We need to pick a pivot, and push left and right ranges
2032 // onto the worklist. Leafs are handled via handleSmallSwitchRange() call.
2033 handleBTSplitSwitchCase(CR, WorkList, SV, Default, SwitchMBB);
2037 void SelectionDAGBuilder::visitIndirectBr(const IndirectBrInst &I) {
2038 MachineBasicBlock *IndirectBrMBB = FuncInfo.MBBMap[I.getParent()];
2040 // Update machine-CFG edges with unique successors.
2041 SmallVector<BasicBlock*, 32> succs;
2042 succs.reserve(I.getNumSuccessors());
2043 for (unsigned i = 0, e = I.getNumSuccessors(); i != e; ++i)
2044 succs.push_back(I.getSuccessor(i));
2045 array_pod_sort(succs.begin(), succs.end());
2046 succs.erase(std::unique(succs.begin(), succs.end()), succs.end());
2047 for (unsigned i = 0, e = succs.size(); i != e; ++i)
2048 IndirectBrMBB->addSuccessor(FuncInfo.MBBMap[succs[i]]);
2050 DAG.setRoot(DAG.getNode(ISD::BRIND, getCurDebugLoc(),
2051 MVT::Other, getControlRoot(),
2052 getValue(I.getAddress())));
2055 void SelectionDAGBuilder::visitFSub(const User &I) {
2056 // -0.0 - X --> fneg
2057 const Type *Ty = I.getType();
2058 if (Ty->isVectorTy()) {
2059 if (ConstantVector *CV = dyn_cast<ConstantVector>(I.getOperand(0))) {
2060 const VectorType *DestTy = cast<VectorType>(I.getType());
2061 const Type *ElTy = DestTy->getElementType();
2062 unsigned VL = DestTy->getNumElements();
2063 std::vector<Constant*> NZ(VL, ConstantFP::getNegativeZero(ElTy));
2064 Constant *CNZ = ConstantVector::get(&NZ[0], NZ.size());
2066 SDValue Op2 = getValue(I.getOperand(1));
2067 setValue(&I, DAG.getNode(ISD::FNEG, getCurDebugLoc(),
2068 Op2.getValueType(), Op2));
2074 if (ConstantFP *CFP = dyn_cast<ConstantFP>(I.getOperand(0)))
2075 if (CFP->isExactlyValue(ConstantFP::getNegativeZero(Ty)->getValueAPF())) {
2076 SDValue Op2 = getValue(I.getOperand(1));
2077 setValue(&I, DAG.getNode(ISD::FNEG, getCurDebugLoc(),
2078 Op2.getValueType(), Op2));
2082 visitBinary(I, ISD::FSUB);
2085 void SelectionDAGBuilder::visitBinary(const User &I, unsigned OpCode) {
2086 SDValue Op1 = getValue(I.getOperand(0));
2087 SDValue Op2 = getValue(I.getOperand(1));
2088 setValue(&I, DAG.getNode(OpCode, getCurDebugLoc(),
2089 Op1.getValueType(), Op1, Op2));
2092 void SelectionDAGBuilder::visitShift(const User &I, unsigned Opcode) {
2093 SDValue Op1 = getValue(I.getOperand(0));
2094 SDValue Op2 = getValue(I.getOperand(1));
2095 if (!I.getType()->isVectorTy() &&
2096 Op2.getValueType() != TLI.getShiftAmountTy()) {
2097 // If the operand is smaller than the shift count type, promote it.
2098 EVT PTy = TLI.getPointerTy();
2099 EVT STy = TLI.getShiftAmountTy();
2100 if (STy.bitsGT(Op2.getValueType()))
2101 Op2 = DAG.getNode(ISD::ANY_EXTEND, getCurDebugLoc(),
2102 TLI.getShiftAmountTy(), Op2);
2103 // If the operand is larger than the shift count type but the shift
2104 // count type has enough bits to represent any shift value, truncate
2105 // it now. This is a common case and it exposes the truncate to
2106 // optimization early.
2107 else if (STy.getSizeInBits() >=
2108 Log2_32_Ceil(Op2.getValueType().getSizeInBits()))
2109 Op2 = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(),
2110 TLI.getShiftAmountTy(), Op2);
2111 // Otherwise we'll need to temporarily settle for some other
2112 // convenient type; type legalization will make adjustments as
2114 else if (PTy.bitsLT(Op2.getValueType()))
2115 Op2 = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(),
2116 TLI.getPointerTy(), Op2);
2117 else if (PTy.bitsGT(Op2.getValueType()))
2118 Op2 = DAG.getNode(ISD::ANY_EXTEND, getCurDebugLoc(),
2119 TLI.getPointerTy(), Op2);
2122 setValue(&I, DAG.getNode(Opcode, getCurDebugLoc(),
2123 Op1.getValueType(), Op1, Op2));
2126 void SelectionDAGBuilder::visitICmp(const User &I) {
2127 ICmpInst::Predicate predicate = ICmpInst::BAD_ICMP_PREDICATE;
2128 if (const ICmpInst *IC = dyn_cast<ICmpInst>(&I))
2129 predicate = IC->getPredicate();
2130 else if (const ConstantExpr *IC = dyn_cast<ConstantExpr>(&I))
2131 predicate = ICmpInst::Predicate(IC->getPredicate());
2132 SDValue Op1 = getValue(I.getOperand(0));
2133 SDValue Op2 = getValue(I.getOperand(1));
2134 ISD::CondCode Opcode = getICmpCondCode(predicate);
2136 EVT DestVT = TLI.getValueType(I.getType());
2137 setValue(&I, DAG.getSetCC(getCurDebugLoc(), DestVT, Op1, Op2, Opcode));
2140 void SelectionDAGBuilder::visitFCmp(const User &I) {
2141 FCmpInst::Predicate predicate = FCmpInst::BAD_FCMP_PREDICATE;
2142 if (const FCmpInst *FC = dyn_cast<FCmpInst>(&I))
2143 predicate = FC->getPredicate();
2144 else if (const ConstantExpr *FC = dyn_cast<ConstantExpr>(&I))
2145 predicate = FCmpInst::Predicate(FC->getPredicate());
2146 SDValue Op1 = getValue(I.getOperand(0));
2147 SDValue Op2 = getValue(I.getOperand(1));
2148 ISD::CondCode Condition = getFCmpCondCode(predicate);
2149 EVT DestVT = TLI.getValueType(I.getType());
2150 setValue(&I, DAG.getSetCC(getCurDebugLoc(), DestVT, Op1, Op2, Condition));
2153 void SelectionDAGBuilder::visitSelect(const User &I) {
2154 SmallVector<EVT, 4> ValueVTs;
2155 ComputeValueVTs(TLI, I.getType(), ValueVTs);
2156 unsigned NumValues = ValueVTs.size();
2157 if (NumValues == 0) return;
2159 SmallVector<SDValue, 4> Values(NumValues);
2160 SDValue Cond = getValue(I.getOperand(0));
2161 SDValue TrueVal = getValue(I.getOperand(1));
2162 SDValue FalseVal = getValue(I.getOperand(2));
2164 for (unsigned i = 0; i != NumValues; ++i)
2165 Values[i] = DAG.getNode(ISD::SELECT, getCurDebugLoc(),
2166 TrueVal.getNode()->getValueType(TrueVal.getResNo()+i),
2168 SDValue(TrueVal.getNode(),
2169 TrueVal.getResNo() + i),
2170 SDValue(FalseVal.getNode(),
2171 FalseVal.getResNo() + i));
2173 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(),
2174 DAG.getVTList(&ValueVTs[0], NumValues),
2175 &Values[0], NumValues));
2178 void SelectionDAGBuilder::visitTrunc(const User &I) {
2179 // TruncInst cannot be a no-op cast because sizeof(src) > sizeof(dest).
2180 SDValue N = getValue(I.getOperand(0));
2181 EVT DestVT = TLI.getValueType(I.getType());
2182 setValue(&I, DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), DestVT, N));
2185 void SelectionDAGBuilder::visitZExt(const User &I) {
2186 // ZExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
2187 // ZExt also can't be a cast to bool for same reason. So, nothing much to do
2188 SDValue N = getValue(I.getOperand(0));
2189 EVT DestVT = TLI.getValueType(I.getType());
2190 setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(), DestVT, N));
2193 void SelectionDAGBuilder::visitSExt(const User &I) {
2194 // SExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
2195 // SExt also can't be a cast to bool for same reason. So, nothing much to do
2196 SDValue N = getValue(I.getOperand(0));
2197 EVT DestVT = TLI.getValueType(I.getType());
2198 setValue(&I, DAG.getNode(ISD::SIGN_EXTEND, getCurDebugLoc(), DestVT, N));
2201 void SelectionDAGBuilder::visitFPTrunc(const User &I) {
2202 // FPTrunc is never a no-op cast, no need to check
2203 SDValue N = getValue(I.getOperand(0));
2204 EVT DestVT = TLI.getValueType(I.getType());
2205 setValue(&I, DAG.getNode(ISD::FP_ROUND, getCurDebugLoc(),
2206 DestVT, N, DAG.getIntPtrConstant(0)));
2209 void SelectionDAGBuilder::visitFPExt(const User &I){
2210 // FPTrunc is never a no-op cast, no need to check
2211 SDValue N = getValue(I.getOperand(0));
2212 EVT DestVT = TLI.getValueType(I.getType());
2213 setValue(&I, DAG.getNode(ISD::FP_EXTEND, getCurDebugLoc(), DestVT, N));
2216 void SelectionDAGBuilder::visitFPToUI(const User &I) {
2217 // FPToUI is never a no-op cast, no need to check
2218 SDValue N = getValue(I.getOperand(0));
2219 EVT DestVT = TLI.getValueType(I.getType());
2220 setValue(&I, DAG.getNode(ISD::FP_TO_UINT, getCurDebugLoc(), DestVT, N));
2223 void SelectionDAGBuilder::visitFPToSI(const User &I) {
2224 // FPToSI is never a no-op cast, no need to check
2225 SDValue N = getValue(I.getOperand(0));
2226 EVT DestVT = TLI.getValueType(I.getType());
2227 setValue(&I, DAG.getNode(ISD::FP_TO_SINT, getCurDebugLoc(), DestVT, N));
2230 void SelectionDAGBuilder::visitUIToFP(const User &I) {
2231 // UIToFP is never a no-op cast, no need to check
2232 SDValue N = getValue(I.getOperand(0));
2233 EVT DestVT = TLI.getValueType(I.getType());
2234 setValue(&I, DAG.getNode(ISD::UINT_TO_FP, getCurDebugLoc(), DestVT, N));
2237 void SelectionDAGBuilder::visitSIToFP(const User &I){
2238 // SIToFP is never a no-op cast, no need to check
2239 SDValue N = getValue(I.getOperand(0));
2240 EVT DestVT = TLI.getValueType(I.getType());
2241 setValue(&I, DAG.getNode(ISD::SINT_TO_FP, getCurDebugLoc(), DestVT, N));
2244 void SelectionDAGBuilder::visitPtrToInt(const User &I) {
2245 // What to do depends on the size of the integer and the size of the pointer.
2246 // We can either truncate, zero extend, or no-op, accordingly.
2247 SDValue N = getValue(I.getOperand(0));
2248 EVT SrcVT = N.getValueType();
2249 EVT DestVT = TLI.getValueType(I.getType());
2250 setValue(&I, DAG.getZExtOrTrunc(N, getCurDebugLoc(), DestVT));
2253 void SelectionDAGBuilder::visitIntToPtr(const User &I) {
2254 // What to do depends on the size of the integer and the size of the pointer.
2255 // We can either truncate, zero extend, or no-op, accordingly.
2256 SDValue N = getValue(I.getOperand(0));
2257 EVT SrcVT = N.getValueType();
2258 EVT DestVT = TLI.getValueType(I.getType());
2259 setValue(&I, DAG.getZExtOrTrunc(N, getCurDebugLoc(), DestVT));
2262 void SelectionDAGBuilder::visitBitCast(const User &I) {
2263 SDValue N = getValue(I.getOperand(0));
2264 EVT DestVT = TLI.getValueType(I.getType());
2266 // BitCast assures us that source and destination are the same size so this is
2267 // either a BIT_CONVERT or a no-op.
2268 if (DestVT != N.getValueType())
2269 setValue(&I, DAG.getNode(ISD::BIT_CONVERT, getCurDebugLoc(),
2270 DestVT, N)); // convert types.
2272 setValue(&I, N); // noop cast.
2275 void SelectionDAGBuilder::visitInsertElement(const User &I) {
2276 SDValue InVec = getValue(I.getOperand(0));
2277 SDValue InVal = getValue(I.getOperand(1));
2278 SDValue InIdx = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(),
2280 getValue(I.getOperand(2)));
2281 setValue(&I, DAG.getNode(ISD::INSERT_VECTOR_ELT, getCurDebugLoc(),
2282 TLI.getValueType(I.getType()),
2283 InVec, InVal, InIdx));
2286 void SelectionDAGBuilder::visitExtractElement(const User &I) {
2287 SDValue InVec = getValue(I.getOperand(0));
2288 SDValue InIdx = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(),
2290 getValue(I.getOperand(1)));
2291 setValue(&I, DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurDebugLoc(),
2292 TLI.getValueType(I.getType()), InVec, InIdx));
2295 // Utility for visitShuffleVector - Returns true if the mask is mask starting
2296 // from SIndx and increasing to the element length (undefs are allowed).
2297 static bool SequentialMask(SmallVectorImpl<int> &Mask, unsigned SIndx) {
2298 unsigned MaskNumElts = Mask.size();
2299 for (unsigned i = 0; i != MaskNumElts; ++i)
2300 if ((Mask[i] >= 0) && (Mask[i] != (int)(i + SIndx)))
2305 void SelectionDAGBuilder::visitShuffleVector(const User &I) {
2306 SmallVector<int, 8> Mask;
2307 SDValue Src1 = getValue(I.getOperand(0));
2308 SDValue Src2 = getValue(I.getOperand(1));
2310 // Convert the ConstantVector mask operand into an array of ints, with -1
2311 // representing undef values.
2312 SmallVector<Constant*, 8> MaskElts;
2313 cast<Constant>(I.getOperand(2))->getVectorElements(MaskElts);
2314 unsigned MaskNumElts = MaskElts.size();
2315 for (unsigned i = 0; i != MaskNumElts; ++i) {
2316 if (isa<UndefValue>(MaskElts[i]))
2319 Mask.push_back(cast<ConstantInt>(MaskElts[i])->getSExtValue());
2322 EVT VT = TLI.getValueType(I.getType());
2323 EVT SrcVT = Src1.getValueType();
2324 unsigned SrcNumElts = SrcVT.getVectorNumElements();
2326 if (SrcNumElts == MaskNumElts) {
2327 setValue(&I, DAG.getVectorShuffle(VT, getCurDebugLoc(), Src1, Src2,
2332 // Normalize the shuffle vector since mask and vector length don't match.
2333 if (SrcNumElts < MaskNumElts && MaskNumElts % SrcNumElts == 0) {
2334 // Mask is longer than the source vectors and is a multiple of the source
2335 // vectors. We can use concatenate vector to make the mask and vectors
2337 if (SrcNumElts*2 == MaskNumElts && SequentialMask(Mask, 0)) {
2338 // The shuffle is concatenating two vectors together.
2339 setValue(&I, DAG.getNode(ISD::CONCAT_VECTORS, getCurDebugLoc(),
2344 // Pad both vectors with undefs to make them the same length as the mask.
2345 unsigned NumConcat = MaskNumElts / SrcNumElts;
2346 bool Src1U = Src1.getOpcode() == ISD::UNDEF;
2347 bool Src2U = Src2.getOpcode() == ISD::UNDEF;
2348 SDValue UndefVal = DAG.getUNDEF(SrcVT);
2350 SmallVector<SDValue, 8> MOps1(NumConcat, UndefVal);
2351 SmallVector<SDValue, 8> MOps2(NumConcat, UndefVal);
2355 Src1 = Src1U ? DAG.getUNDEF(VT) : DAG.getNode(ISD::CONCAT_VECTORS,
2356 getCurDebugLoc(), VT,
2357 &MOps1[0], NumConcat);
2358 Src2 = Src2U ? DAG.getUNDEF(VT) : DAG.getNode(ISD::CONCAT_VECTORS,
2359 getCurDebugLoc(), VT,
2360 &MOps2[0], NumConcat);
2362 // Readjust mask for new input vector length.
2363 SmallVector<int, 8> MappedOps;
2364 for (unsigned i = 0; i != MaskNumElts; ++i) {
2366 if (Idx < (int)SrcNumElts)
2367 MappedOps.push_back(Idx);
2369 MappedOps.push_back(Idx + MaskNumElts - SrcNumElts);
2372 setValue(&I, DAG.getVectorShuffle(VT, getCurDebugLoc(), Src1, Src2,
2377 if (SrcNumElts > MaskNumElts) {
2378 // Analyze the access pattern of the vector to see if we can extract
2379 // two subvectors and do the shuffle. The analysis is done by calculating
2380 // the range of elements the mask access on both vectors.
2381 int MinRange[2] = { SrcNumElts+1, SrcNumElts+1};
2382 int MaxRange[2] = {-1, -1};
2384 for (unsigned i = 0; i != MaskNumElts; ++i) {
2390 if (Idx >= (int)SrcNumElts) {
2394 if (Idx > MaxRange[Input])
2395 MaxRange[Input] = Idx;
2396 if (Idx < MinRange[Input])
2397 MinRange[Input] = Idx;
2400 // Check if the access is smaller than the vector size and can we find
2401 // a reasonable extract index.
2402 int RangeUse[2] = { 2, 2 }; // 0 = Unused, 1 = Extract, 2 = Can not
2404 int StartIdx[2]; // StartIdx to extract from
2405 for (int Input=0; Input < 2; ++Input) {
2406 if (MinRange[Input] == (int)(SrcNumElts+1) && MaxRange[Input] == -1) {
2407 RangeUse[Input] = 0; // Unused
2408 StartIdx[Input] = 0;
2409 } else if (MaxRange[Input] - MinRange[Input] < (int)MaskNumElts) {
2410 // Fits within range but we should see if we can find a good
2411 // start index that is a multiple of the mask length.
2412 if (MaxRange[Input] < (int)MaskNumElts) {
2413 RangeUse[Input] = 1; // Extract from beginning of the vector
2414 StartIdx[Input] = 0;
2416 StartIdx[Input] = (MinRange[Input]/MaskNumElts)*MaskNumElts;
2417 if (MaxRange[Input] - StartIdx[Input] < (int)MaskNumElts &&
2418 StartIdx[Input] + MaskNumElts < SrcNumElts)
2419 RangeUse[Input] = 1; // Extract from a multiple of the mask length.
2424 if (RangeUse[0] == 0 && RangeUse[1] == 0) {
2425 setValue(&I, DAG.getUNDEF(VT)); // Vectors are not used.
2428 else if (RangeUse[0] < 2 && RangeUse[1] < 2) {
2429 // Extract appropriate subvector and generate a vector shuffle
2430 for (int Input=0; Input < 2; ++Input) {
2431 SDValue &Src = Input == 0 ? Src1 : Src2;
2432 if (RangeUse[Input] == 0)
2433 Src = DAG.getUNDEF(VT);
2435 Src = DAG.getNode(ISD::EXTRACT_SUBVECTOR, getCurDebugLoc(), VT,
2436 Src, DAG.getIntPtrConstant(StartIdx[Input]));
2439 // Calculate new mask.
2440 SmallVector<int, 8> MappedOps;
2441 for (unsigned i = 0; i != MaskNumElts; ++i) {
2444 MappedOps.push_back(Idx);
2445 else if (Idx < (int)SrcNumElts)
2446 MappedOps.push_back(Idx - StartIdx[0]);
2448 MappedOps.push_back(Idx - SrcNumElts - StartIdx[1] + MaskNumElts);
2451 setValue(&I, DAG.getVectorShuffle(VT, getCurDebugLoc(), Src1, Src2,
2457 // We can't use either concat vectors or extract subvectors so fall back to
2458 // replacing the shuffle with extract and build vector.
2459 // to insert and build vector.
2460 EVT EltVT = VT.getVectorElementType();
2461 EVT PtrVT = TLI.getPointerTy();
2462 SmallVector<SDValue,8> Ops;
2463 for (unsigned i = 0; i != MaskNumElts; ++i) {
2465 Ops.push_back(DAG.getUNDEF(EltVT));
2470 if (Idx < (int)SrcNumElts)
2471 Res = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurDebugLoc(),
2472 EltVT, Src1, DAG.getConstant(Idx, PtrVT));
2474 Res = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurDebugLoc(),
2476 DAG.getConstant(Idx - SrcNumElts, PtrVT));
2482 setValue(&I, DAG.getNode(ISD::BUILD_VECTOR, getCurDebugLoc(),
2483 VT, &Ops[0], Ops.size()));
2486 void SelectionDAGBuilder::visitInsertValue(const InsertValueInst &I) {
2487 const Value *Op0 = I.getOperand(0);
2488 const Value *Op1 = I.getOperand(1);
2489 const Type *AggTy = I.getType();
2490 const Type *ValTy = Op1->getType();
2491 bool IntoUndef = isa<UndefValue>(Op0);
2492 bool FromUndef = isa<UndefValue>(Op1);
2494 unsigned LinearIndex = ComputeLinearIndex(TLI, AggTy,
2495 I.idx_begin(), I.idx_end());
2497 SmallVector<EVT, 4> AggValueVTs;
2498 ComputeValueVTs(TLI, AggTy, AggValueVTs);
2499 SmallVector<EVT, 4> ValValueVTs;
2500 ComputeValueVTs(TLI, ValTy, ValValueVTs);
2502 unsigned NumAggValues = AggValueVTs.size();
2503 unsigned NumValValues = ValValueVTs.size();
2504 SmallVector<SDValue, 4> Values(NumAggValues);
2506 SDValue Agg = getValue(Op0);
2507 SDValue Val = getValue(Op1);
2509 // Copy the beginning value(s) from the original aggregate.
2510 for (; i != LinearIndex; ++i)
2511 Values[i] = IntoUndef ? DAG.getUNDEF(AggValueVTs[i]) :
2512 SDValue(Agg.getNode(), Agg.getResNo() + i);
2513 // Copy values from the inserted value(s).
2514 for (; i != LinearIndex + NumValValues; ++i)
2515 Values[i] = FromUndef ? DAG.getUNDEF(AggValueVTs[i]) :
2516 SDValue(Val.getNode(), Val.getResNo() + i - LinearIndex);
2517 // Copy remaining value(s) from the original aggregate.
2518 for (; i != NumAggValues; ++i)
2519 Values[i] = IntoUndef ? DAG.getUNDEF(AggValueVTs[i]) :
2520 SDValue(Agg.getNode(), Agg.getResNo() + i);
2522 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(),
2523 DAG.getVTList(&AggValueVTs[0], NumAggValues),
2524 &Values[0], NumAggValues));
2527 void SelectionDAGBuilder::visitExtractValue(const ExtractValueInst &I) {
2528 const Value *Op0 = I.getOperand(0);
2529 const Type *AggTy = Op0->getType();
2530 const Type *ValTy = I.getType();
2531 bool OutOfUndef = isa<UndefValue>(Op0);
2533 unsigned LinearIndex = ComputeLinearIndex(TLI, AggTy,
2534 I.idx_begin(), I.idx_end());
2536 SmallVector<EVT, 4> ValValueVTs;
2537 ComputeValueVTs(TLI, ValTy, ValValueVTs);
2539 unsigned NumValValues = ValValueVTs.size();
2540 SmallVector<SDValue, 4> Values(NumValValues);
2542 SDValue Agg = getValue(Op0);
2543 // Copy out the selected value(s).
2544 for (unsigned i = LinearIndex; i != LinearIndex + NumValValues; ++i)
2545 Values[i - LinearIndex] =
2547 DAG.getUNDEF(Agg.getNode()->getValueType(Agg.getResNo() + i)) :
2548 SDValue(Agg.getNode(), Agg.getResNo() + i);
2550 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(),
2551 DAG.getVTList(&ValValueVTs[0], NumValValues),
2552 &Values[0], NumValValues));
2555 void SelectionDAGBuilder::visitGetElementPtr(const User &I) {
2556 SDValue N = getValue(I.getOperand(0));
2557 const Type *Ty = I.getOperand(0)->getType();
2559 for (GetElementPtrInst::const_op_iterator OI = I.op_begin()+1, E = I.op_end();
2561 const Value *Idx = *OI;
2562 if (const StructType *StTy = dyn_cast<StructType>(Ty)) {
2563 unsigned Field = cast<ConstantInt>(Idx)->getZExtValue();
2566 uint64_t Offset = TD->getStructLayout(StTy)->getElementOffset(Field);
2567 N = DAG.getNode(ISD::ADD, getCurDebugLoc(), N.getValueType(), N,
2568 DAG.getIntPtrConstant(Offset));
2571 Ty = StTy->getElementType(Field);
2572 } else if (const UnionType *UnTy = dyn_cast<UnionType>(Ty)) {
2573 unsigned Field = cast<ConstantInt>(Idx)->getZExtValue();
2575 // Offset canonically 0 for unions, but type changes
2576 Ty = UnTy->getElementType(Field);
2578 Ty = cast<SequentialType>(Ty)->getElementType();
2580 // If this is a constant subscript, handle it quickly.
2581 if (const ConstantInt *CI = dyn_cast<ConstantInt>(Idx)) {
2582 if (CI->getZExtValue() == 0) continue;
2584 TD->getTypeAllocSize(Ty)*cast<ConstantInt>(CI)->getSExtValue();
2586 EVT PTy = TLI.getPointerTy();
2587 unsigned PtrBits = PTy.getSizeInBits();
2589 OffsVal = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(),
2591 DAG.getConstant(Offs, MVT::i64));
2593 OffsVal = DAG.getIntPtrConstant(Offs);
2595 N = DAG.getNode(ISD::ADD, getCurDebugLoc(), N.getValueType(), N,
2600 // N = N + Idx * ElementSize;
2601 APInt ElementSize = APInt(TLI.getPointerTy().getSizeInBits(),
2602 TD->getTypeAllocSize(Ty));
2603 SDValue IdxN = getValue(Idx);
2605 // If the index is smaller or larger than intptr_t, truncate or extend
2607 IdxN = DAG.getSExtOrTrunc(IdxN, getCurDebugLoc(), N.getValueType());
2609 // If this is a multiply by a power of two, turn it into a shl
2610 // immediately. This is a very common case.
2611 if (ElementSize != 1) {
2612 if (ElementSize.isPowerOf2()) {
2613 unsigned Amt = ElementSize.logBase2();
2614 IdxN = DAG.getNode(ISD::SHL, getCurDebugLoc(),
2615 N.getValueType(), IdxN,
2616 DAG.getConstant(Amt, TLI.getPointerTy()));
2618 SDValue Scale = DAG.getConstant(ElementSize, TLI.getPointerTy());
2619 IdxN = DAG.getNode(ISD::MUL, getCurDebugLoc(),
2620 N.getValueType(), IdxN, Scale);
2624 N = DAG.getNode(ISD::ADD, getCurDebugLoc(),
2625 N.getValueType(), N, IdxN);
2632 void SelectionDAGBuilder::visitAlloca(const AllocaInst &I) {
2633 // If this is a fixed sized alloca in the entry block of the function,
2634 // allocate it statically on the stack.
2635 if (FuncInfo.StaticAllocaMap.count(&I))
2636 return; // getValue will auto-populate this.
2638 const Type *Ty = I.getAllocatedType();
2639 uint64_t TySize = TLI.getTargetData()->getTypeAllocSize(Ty);
2641 std::max((unsigned)TLI.getTargetData()->getPrefTypeAlignment(Ty),
2644 SDValue AllocSize = getValue(I.getArraySize());
2646 AllocSize = DAG.getNode(ISD::MUL, getCurDebugLoc(), AllocSize.getValueType(),
2648 DAG.getConstant(TySize, AllocSize.getValueType()));
2650 EVT IntPtr = TLI.getPointerTy();
2651 AllocSize = DAG.getZExtOrTrunc(AllocSize, getCurDebugLoc(), IntPtr);
2653 // Handle alignment. If the requested alignment is less than or equal to
2654 // the stack alignment, ignore it. If the size is greater than or equal to
2655 // the stack alignment, we note this in the DYNAMIC_STACKALLOC node.
2656 unsigned StackAlign = TM.getFrameInfo()->getStackAlignment();
2657 if (Align <= StackAlign)
2660 // Round the size of the allocation up to the stack alignment size
2661 // by add SA-1 to the size.
2662 AllocSize = DAG.getNode(ISD::ADD, getCurDebugLoc(),
2663 AllocSize.getValueType(), AllocSize,
2664 DAG.getIntPtrConstant(StackAlign-1));
2666 // Mask out the low bits for alignment purposes.
2667 AllocSize = DAG.getNode(ISD::AND, getCurDebugLoc(),
2668 AllocSize.getValueType(), AllocSize,
2669 DAG.getIntPtrConstant(~(uint64_t)(StackAlign-1)));
2671 SDValue Ops[] = { getRoot(), AllocSize, DAG.getIntPtrConstant(Align) };
2672 SDVTList VTs = DAG.getVTList(AllocSize.getValueType(), MVT::Other);
2673 SDValue DSA = DAG.getNode(ISD::DYNAMIC_STACKALLOC, getCurDebugLoc(),
2676 DAG.setRoot(DSA.getValue(1));
2678 // Inform the Frame Information that we have just allocated a variable-sized
2680 FuncInfo.MF->getFrameInfo()->CreateVariableSizedObject();
2683 void SelectionDAGBuilder::visitLoad(const LoadInst &I) {
2684 const Value *SV = I.getOperand(0);
2685 SDValue Ptr = getValue(SV);
2687 const Type *Ty = I.getType();
2689 bool isVolatile = I.isVolatile();
2690 bool isNonTemporal = I.getMetadata("nontemporal") != 0;
2691 unsigned Alignment = I.getAlignment();
2693 SmallVector<EVT, 4> ValueVTs;
2694 SmallVector<uint64_t, 4> Offsets;
2695 ComputeValueVTs(TLI, Ty, ValueVTs, &Offsets);
2696 unsigned NumValues = ValueVTs.size();
2701 bool ConstantMemory = false;
2703 // Serialize volatile loads with other side effects.
2705 else if (AA->pointsToConstantMemory(SV)) {
2706 // Do not serialize (non-volatile) loads of constant memory with anything.
2707 Root = DAG.getEntryNode();
2708 ConstantMemory = true;
2710 // Do not serialize non-volatile loads against each other.
2711 Root = DAG.getRoot();
2714 SmallVector<SDValue, 4> Values(NumValues);
2715 SmallVector<SDValue, 4> Chains(NumValues);
2716 EVT PtrVT = Ptr.getValueType();
2717 for (unsigned i = 0; i != NumValues; ++i) {
2718 SDValue A = DAG.getNode(ISD::ADD, getCurDebugLoc(),
2720 DAG.getConstant(Offsets[i], PtrVT));
2721 SDValue L = DAG.getLoad(ValueVTs[i], getCurDebugLoc(), Root,
2722 A, SV, Offsets[i], isVolatile,
2723 isNonTemporal, Alignment);
2726 Chains[i] = L.getValue(1);
2729 if (!ConstantMemory) {
2730 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(),
2731 MVT::Other, &Chains[0], NumValues);
2735 PendingLoads.push_back(Chain);
2738 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(),
2739 DAG.getVTList(&ValueVTs[0], NumValues),
2740 &Values[0], NumValues));
2743 void SelectionDAGBuilder::visitStore(const StoreInst &I) {
2744 const Value *SrcV = I.getOperand(0);
2745 const Value *PtrV = I.getOperand(1);
2747 SmallVector<EVT, 4> ValueVTs;
2748 SmallVector<uint64_t, 4> Offsets;
2749 ComputeValueVTs(TLI, SrcV->getType(), ValueVTs, &Offsets);
2750 unsigned NumValues = ValueVTs.size();
2754 // Get the lowered operands. Note that we do this after
2755 // checking if NumResults is zero, because with zero results
2756 // the operands won't have values in the map.
2757 SDValue Src = getValue(SrcV);
2758 SDValue Ptr = getValue(PtrV);
2760 SDValue Root = getRoot();
2761 SmallVector<SDValue, 4> Chains(NumValues);
2762 EVT PtrVT = Ptr.getValueType();
2763 bool isVolatile = I.isVolatile();
2764 bool isNonTemporal = I.getMetadata("nontemporal") != 0;
2765 unsigned Alignment = I.getAlignment();
2767 for (unsigned i = 0; i != NumValues; ++i) {
2768 SDValue Add = DAG.getNode(ISD::ADD, getCurDebugLoc(), PtrVT, Ptr,
2769 DAG.getConstant(Offsets[i], PtrVT));
2770 Chains[i] = DAG.getStore(Root, getCurDebugLoc(),
2771 SDValue(Src.getNode(), Src.getResNo() + i),
2772 Add, PtrV, Offsets[i], isVolatile,
2773 isNonTemporal, Alignment);
2776 DAG.setRoot(DAG.getNode(ISD::TokenFactor, getCurDebugLoc(),
2777 MVT::Other, &Chains[0], NumValues));
2780 /// visitTargetIntrinsic - Lower a call of a target intrinsic to an INTRINSIC
2782 void SelectionDAGBuilder::visitTargetIntrinsic(const CallInst &I,
2783 unsigned Intrinsic) {
2784 bool HasChain = !I.doesNotAccessMemory();
2785 bool OnlyLoad = HasChain && I.onlyReadsMemory();
2787 // Build the operand list.
2788 SmallVector<SDValue, 8> Ops;
2789 if (HasChain) { // If this intrinsic has side-effects, chainify it.
2791 // We don't need to serialize loads against other loads.
2792 Ops.push_back(DAG.getRoot());
2794 Ops.push_back(getRoot());
2798 // Info is set by getTgtMemInstrinsic
2799 TargetLowering::IntrinsicInfo Info;
2800 bool IsTgtIntrinsic = TLI.getTgtMemIntrinsic(Info, I, Intrinsic);
2802 // Add the intrinsic ID as an integer operand if it's not a target intrinsic.
2803 if (!IsTgtIntrinsic)
2804 Ops.push_back(DAG.getConstant(Intrinsic, TLI.getPointerTy()));
2806 // Add all operands of the call to the operand list.
2807 for (unsigned i = 1, e = I.getNumOperands(); i != e; ++i) {
2808 SDValue Op = getValue(I.getOperand(i));
2809 assert(TLI.isTypeLegal(Op.getValueType()) &&
2810 "Intrinsic uses a non-legal type?");
2814 SmallVector<EVT, 4> ValueVTs;
2815 ComputeValueVTs(TLI, I.getType(), ValueVTs);
2817 for (unsigned Val = 0, E = ValueVTs.size(); Val != E; ++Val) {
2818 assert(TLI.isTypeLegal(ValueVTs[Val]) &&
2819 "Intrinsic uses a non-legal type?");
2824 ValueVTs.push_back(MVT::Other);
2826 SDVTList VTs = DAG.getVTList(ValueVTs.data(), ValueVTs.size());
2830 if (IsTgtIntrinsic) {
2831 // This is target intrinsic that touches memory
2832 Result = DAG.getMemIntrinsicNode(Info.opc, getCurDebugLoc(),
2833 VTs, &Ops[0], Ops.size(),
2834 Info.memVT, Info.ptrVal, Info.offset,
2835 Info.align, Info.vol,
2836 Info.readMem, Info.writeMem);
2837 } else if (!HasChain) {
2838 Result = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, getCurDebugLoc(),
2839 VTs, &Ops[0], Ops.size());
2840 } else if (!I.getType()->isVoidTy()) {
2841 Result = DAG.getNode(ISD::INTRINSIC_W_CHAIN, getCurDebugLoc(),
2842 VTs, &Ops[0], Ops.size());
2844 Result = DAG.getNode(ISD::INTRINSIC_VOID, getCurDebugLoc(),
2845 VTs, &Ops[0], Ops.size());
2849 SDValue Chain = Result.getValue(Result.getNode()->getNumValues()-1);
2851 PendingLoads.push_back(Chain);
2856 if (!I.getType()->isVoidTy()) {
2857 if (const VectorType *PTy = dyn_cast<VectorType>(I.getType())) {
2858 EVT VT = TLI.getValueType(PTy);
2859 Result = DAG.getNode(ISD::BIT_CONVERT, getCurDebugLoc(), VT, Result);
2862 setValue(&I, Result);
2866 /// GetSignificand - Get the significand and build it into a floating-point
2867 /// number with exponent of 1:
2869 /// Op = (Op & 0x007fffff) | 0x3f800000;
2871 /// where Op is the hexidecimal representation of floating point value.
2873 GetSignificand(SelectionDAG &DAG, SDValue Op, DebugLoc dl) {
2874 SDValue t1 = DAG.getNode(ISD::AND, dl, MVT::i32, Op,
2875 DAG.getConstant(0x007fffff, MVT::i32));
2876 SDValue t2 = DAG.getNode(ISD::OR, dl, MVT::i32, t1,
2877 DAG.getConstant(0x3f800000, MVT::i32));
2878 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, t2);
2881 /// GetExponent - Get the exponent:
2883 /// (float)(int)(((Op & 0x7f800000) >> 23) - 127);
2885 /// where Op is the hexidecimal representation of floating point value.
2887 GetExponent(SelectionDAG &DAG, SDValue Op, const TargetLowering &TLI,
2889 SDValue t0 = DAG.getNode(ISD::AND, dl, MVT::i32, Op,
2890 DAG.getConstant(0x7f800000, MVT::i32));
2891 SDValue t1 = DAG.getNode(ISD::SRL, dl, MVT::i32, t0,
2892 DAG.getConstant(23, TLI.getPointerTy()));
2893 SDValue t2 = DAG.getNode(ISD::SUB, dl, MVT::i32, t1,
2894 DAG.getConstant(127, MVT::i32));
2895 return DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, t2);
2898 /// getF32Constant - Get 32-bit floating point constant.
2900 getF32Constant(SelectionDAG &DAG, unsigned Flt) {
2901 return DAG.getConstantFP(APFloat(APInt(32, Flt)), MVT::f32);
2904 /// Inlined utility function to implement binary input atomic intrinsics for
2905 /// visitIntrinsicCall: I is a call instruction
2906 /// Op is the associated NodeType for I
2908 SelectionDAGBuilder::implVisitBinaryAtomic(const CallInst& I,
2910 SDValue Root = getRoot();
2912 DAG.getAtomic(Op, getCurDebugLoc(),
2913 getValue(I.getOperand(2)).getValueType().getSimpleVT(),
2915 getValue(I.getOperand(1)),
2916 getValue(I.getOperand(2)),
2919 DAG.setRoot(L.getValue(1));
2923 // implVisitAluOverflow - Lower arithmetic overflow instrinsics.
2925 SelectionDAGBuilder::implVisitAluOverflow(const CallInst &I, ISD::NodeType Op) {
2926 SDValue Op1 = getValue(I.getOperand(1));
2927 SDValue Op2 = getValue(I.getOperand(2));
2929 SDVTList VTs = DAG.getVTList(Op1.getValueType(), MVT::i1);
2930 setValue(&I, DAG.getNode(Op, getCurDebugLoc(), VTs, Op1, Op2));
2934 /// visitExp - Lower an exp intrinsic. Handles the special sequences for
2935 /// limited-precision mode.
2937 SelectionDAGBuilder::visitExp(const CallInst &I) {
2939 DebugLoc dl = getCurDebugLoc();
2941 if (getValue(I.getOperand(1)).getValueType() == MVT::f32 &&
2942 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
2943 SDValue Op = getValue(I.getOperand(1));
2945 // Put the exponent in the right bit position for later addition to the
2948 // #define LOG2OFe 1.4426950f
2949 // IntegerPartOfX = ((int32_t)(X * LOG2OFe));
2950 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, Op,
2951 getF32Constant(DAG, 0x3fb8aa3b));
2952 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, t0);
2954 // FractionalPartOfX = (X * LOG2OFe) - (float)IntegerPartOfX;
2955 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX);
2956 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, t1);
2958 // IntegerPartOfX <<= 23;
2959 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX,
2960 DAG.getConstant(23, TLI.getPointerTy()));
2962 if (LimitFloatPrecision <= 6) {
2963 // For floating-point precision of 6:
2965 // TwoToFractionalPartOfX =
2967 // (0.735607626f + 0.252464424f * x) * x;
2969 // error 0.0144103317, which is 6 bits
2970 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
2971 getF32Constant(DAG, 0x3e814304));
2972 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
2973 getF32Constant(DAG, 0x3f3c50c8));
2974 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
2975 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
2976 getF32Constant(DAG, 0x3f7f5e7e));
2977 SDValue TwoToFracPartOfX = DAG.getNode(ISD::BIT_CONVERT, dl,MVT::i32, t5);
2979 // Add the exponent into the result in integer domain.
2980 SDValue t6 = DAG.getNode(ISD::ADD, dl, MVT::i32,
2981 TwoToFracPartOfX, IntegerPartOfX);
2983 result = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, t6);
2984 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
2985 // For floating-point precision of 12:
2987 // TwoToFractionalPartOfX =
2990 // (0.224338339f + 0.792043434e-1f * x) * x) * x;
2992 // 0.000107046256 error, which is 13 to 14 bits
2993 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
2994 getF32Constant(DAG, 0x3da235e3));
2995 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
2996 getF32Constant(DAG, 0x3e65b8f3));
2997 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
2998 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
2999 getF32Constant(DAG, 0x3f324b07));
3000 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3001 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3002 getF32Constant(DAG, 0x3f7ff8fd));
3003 SDValue TwoToFracPartOfX = DAG.getNode(ISD::BIT_CONVERT, dl,MVT::i32, t7);
3005 // Add the exponent into the result in integer domain.
3006 SDValue t8 = DAG.getNode(ISD::ADD, dl, MVT::i32,
3007 TwoToFracPartOfX, IntegerPartOfX);
3009 result = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, t8);
3010 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
3011 // For floating-point precision of 18:
3013 // TwoToFractionalPartOfX =
3017 // (0.554906021e-1f +
3018 // (0.961591928e-2f +
3019 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x;
3021 // error 2.47208000*10^(-7), which is better than 18 bits
3022 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3023 getF32Constant(DAG, 0x3924b03e));
3024 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3025 getF32Constant(DAG, 0x3ab24b87));
3026 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3027 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3028 getF32Constant(DAG, 0x3c1d8c17));
3029 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3030 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3031 getF32Constant(DAG, 0x3d634a1d));
3032 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3033 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3034 getF32Constant(DAG, 0x3e75fe14));
3035 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3036 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10,
3037 getF32Constant(DAG, 0x3f317234));
3038 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X);
3039 SDValue t13 = DAG.getNode(ISD::FADD, dl, MVT::f32, t12,
3040 getF32Constant(DAG, 0x3f800000));
3041 SDValue TwoToFracPartOfX = DAG.getNode(ISD::BIT_CONVERT, dl,
3044 // Add the exponent into the result in integer domain.
3045 SDValue t14 = DAG.getNode(ISD::ADD, dl, MVT::i32,
3046 TwoToFracPartOfX, IntegerPartOfX);
3048 result = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, t14);
3051 // No special expansion.
3052 result = DAG.getNode(ISD::FEXP, dl,
3053 getValue(I.getOperand(1)).getValueType(),
3054 getValue(I.getOperand(1)));
3057 setValue(&I, result);
3060 /// visitLog - Lower a log intrinsic. Handles the special sequences for
3061 /// limited-precision mode.
3063 SelectionDAGBuilder::visitLog(const CallInst &I) {
3065 DebugLoc dl = getCurDebugLoc();
3067 if (getValue(I.getOperand(1)).getValueType() == MVT::f32 &&
3068 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3069 SDValue Op = getValue(I.getOperand(1));
3070 SDValue Op1 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, Op);
3072 // Scale the exponent by log(2) [0.69314718f].
3073 SDValue Exp = GetExponent(DAG, Op1, TLI, dl);
3074 SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp,
3075 getF32Constant(DAG, 0x3f317218));
3077 // Get the significand and build it into a floating-point number with
3079 SDValue X = GetSignificand(DAG, Op1, dl);
3081 if (LimitFloatPrecision <= 6) {
3082 // For floating-point precision of 6:
3086 // (1.4034025f - 0.23903021f * x) * x;
3088 // error 0.0034276066, which is better than 8 bits
3089 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3090 getF32Constant(DAG, 0xbe74c456));
3091 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3092 getF32Constant(DAG, 0x3fb3a2b1));
3093 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3094 SDValue LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3095 getF32Constant(DAG, 0x3f949a29));
3097 result = DAG.getNode(ISD::FADD, dl,
3098 MVT::f32, LogOfExponent, LogOfMantissa);
3099 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
3100 // For floating-point precision of 12:
3106 // (0.44717955f - 0.56570851e-1f * x) * x) * x) * x;
3108 // error 0.000061011436, which is 14 bits
3109 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3110 getF32Constant(DAG, 0xbd67b6d6));
3111 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3112 getF32Constant(DAG, 0x3ee4f4b8));
3113 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3114 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3115 getF32Constant(DAG, 0x3fbc278b));
3116 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3117 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3118 getF32Constant(DAG, 0x40348e95));
3119 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3120 SDValue LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3121 getF32Constant(DAG, 0x3fdef31a));
3123 result = DAG.getNode(ISD::FADD, dl,
3124 MVT::f32, LogOfExponent, LogOfMantissa);
3125 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
3126 // For floating-point precision of 18:
3134 // (0.19073739f - 0.17809712e-1f * x) * x) * x) * x) * x)*x;
3136 // error 0.0000023660568, which is better than 18 bits
3137 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3138 getF32Constant(DAG, 0xbc91e5ac));
3139 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3140 getF32Constant(DAG, 0x3e4350aa));
3141 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3142 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3143 getF32Constant(DAG, 0x3f60d3e3));
3144 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3145 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3146 getF32Constant(DAG, 0x4011cdf0));
3147 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3148 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3149 getF32Constant(DAG, 0x406cfd1c));
3150 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3151 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3152 getF32Constant(DAG, 0x408797cb));
3153 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3154 SDValue LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10,
3155 getF32Constant(DAG, 0x4006dcab));
3157 result = DAG.getNode(ISD::FADD, dl,
3158 MVT::f32, LogOfExponent, LogOfMantissa);
3161 // No special expansion.
3162 result = DAG.getNode(ISD::FLOG, dl,
3163 getValue(I.getOperand(1)).getValueType(),
3164 getValue(I.getOperand(1)));
3167 setValue(&I, result);
3170 /// visitLog2 - Lower a log2 intrinsic. Handles the special sequences for
3171 /// limited-precision mode.
3173 SelectionDAGBuilder::visitLog2(const CallInst &I) {
3175 DebugLoc dl = getCurDebugLoc();
3177 if (getValue(I.getOperand(1)).getValueType() == MVT::f32 &&
3178 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3179 SDValue Op = getValue(I.getOperand(1));
3180 SDValue Op1 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, Op);
3182 // Get the exponent.
3183 SDValue LogOfExponent = GetExponent(DAG, Op1, TLI, dl);
3185 // Get the significand and build it into a floating-point number with
3187 SDValue X = GetSignificand(DAG, Op1, dl);
3189 // Different possible minimax approximations of significand in
3190 // floating-point for various degrees of accuracy over [1,2].
3191 if (LimitFloatPrecision <= 6) {
3192 // For floating-point precision of 6:
3194 // Log2ofMantissa = -1.6749035f + (2.0246817f - .34484768f * x) * x;
3196 // error 0.0049451742, which is more than 7 bits
3197 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3198 getF32Constant(DAG, 0xbeb08fe0));
3199 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3200 getF32Constant(DAG, 0x40019463));
3201 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3202 SDValue Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3203 getF32Constant(DAG, 0x3fd6633d));
3205 result = DAG.getNode(ISD::FADD, dl,
3206 MVT::f32, LogOfExponent, Log2ofMantissa);
3207 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
3208 // For floating-point precision of 12:
3214 // (.645142248f - 0.816157886e-1f * x) * x) * x) * x;
3216 // error 0.0000876136000, which is better than 13 bits
3217 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3218 getF32Constant(DAG, 0xbda7262e));
3219 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3220 getF32Constant(DAG, 0x3f25280b));
3221 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3222 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3223 getF32Constant(DAG, 0x4007b923));
3224 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3225 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3226 getF32Constant(DAG, 0x40823e2f));
3227 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3228 SDValue Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3229 getF32Constant(DAG, 0x4020d29c));
3231 result = DAG.getNode(ISD::FADD, dl,
3232 MVT::f32, LogOfExponent, Log2ofMantissa);
3233 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
3234 // For floating-point precision of 18:
3243 // 0.25691327e-1f * x) * x) * x) * x) * x) * x;
3245 // error 0.0000018516, which is better than 18 bits
3246 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3247 getF32Constant(DAG, 0xbcd2769e));
3248 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3249 getF32Constant(DAG, 0x3e8ce0b9));
3250 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3251 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3252 getF32Constant(DAG, 0x3fa22ae7));
3253 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3254 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3255 getF32Constant(DAG, 0x40525723));
3256 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3257 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3258 getF32Constant(DAG, 0x40aaf200));
3259 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3260 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3261 getF32Constant(DAG, 0x40c39dad));
3262 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3263 SDValue Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10,
3264 getF32Constant(DAG, 0x4042902c));
3266 result = DAG.getNode(ISD::FADD, dl,
3267 MVT::f32, LogOfExponent, Log2ofMantissa);
3270 // No special expansion.
3271 result = DAG.getNode(ISD::FLOG2, dl,
3272 getValue(I.getOperand(1)).getValueType(),
3273 getValue(I.getOperand(1)));
3276 setValue(&I, result);
3279 /// visitLog10 - Lower a log10 intrinsic. Handles the special sequences for
3280 /// limited-precision mode.
3282 SelectionDAGBuilder::visitLog10(const CallInst &I) {
3284 DebugLoc dl = getCurDebugLoc();
3286 if (getValue(I.getOperand(1)).getValueType() == MVT::f32 &&
3287 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3288 SDValue Op = getValue(I.getOperand(1));
3289 SDValue Op1 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, Op);
3291 // Scale the exponent by log10(2) [0.30102999f].
3292 SDValue Exp = GetExponent(DAG, Op1, TLI, dl);
3293 SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp,
3294 getF32Constant(DAG, 0x3e9a209a));
3296 // Get the significand and build it into a floating-point number with
3298 SDValue X = GetSignificand(DAG, Op1, dl);
3300 if (LimitFloatPrecision <= 6) {
3301 // For floating-point precision of 6:
3303 // Log10ofMantissa =
3305 // (0.60948995f - 0.10380950f * x) * x;
3307 // error 0.0014886165, which is 6 bits
3308 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3309 getF32Constant(DAG, 0xbdd49a13));
3310 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3311 getF32Constant(DAG, 0x3f1c0789));
3312 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3313 SDValue Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3314 getF32Constant(DAG, 0x3f011300));
3316 result = DAG.getNode(ISD::FADD, dl,
3317 MVT::f32, LogOfExponent, Log10ofMantissa);
3318 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
3319 // For floating-point precision of 12:
3321 // Log10ofMantissa =
3324 // (-0.31664806f + 0.47637168e-1f * x) * x) * x;
3326 // error 0.00019228036, which is better than 12 bits
3327 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3328 getF32Constant(DAG, 0x3d431f31));
3329 SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0,
3330 getF32Constant(DAG, 0x3ea21fb2));
3331 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3332 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3333 getF32Constant(DAG, 0x3f6ae232));
3334 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3335 SDValue Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4,
3336 getF32Constant(DAG, 0x3f25f7c3));
3338 result = DAG.getNode(ISD::FADD, dl,
3339 MVT::f32, LogOfExponent, Log10ofMantissa);
3340 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
3341 // For floating-point precision of 18:
3343 // Log10ofMantissa =
3348 // (-0.12539807f + 0.13508273e-1f * x) * x) * x) * x) * x;
3350 // error 0.0000037995730, which is better than 18 bits
3351 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3352 getF32Constant(DAG, 0x3c5d51ce));
3353 SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0,
3354 getF32Constant(DAG, 0x3e00685a));
3355 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3356 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3357 getF32Constant(DAG, 0x3efb6798));
3358 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3359 SDValue t5 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4,
3360 getF32Constant(DAG, 0x3f88d192));
3361 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3362 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3363 getF32Constant(DAG, 0x3fc4316c));
3364 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3365 SDValue Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t8,
3366 getF32Constant(DAG, 0x3f57ce70));
3368 result = DAG.getNode(ISD::FADD, dl,
3369 MVT::f32, LogOfExponent, Log10ofMantissa);
3372 // No special expansion.
3373 result = DAG.getNode(ISD::FLOG10, dl,
3374 getValue(I.getOperand(1)).getValueType(),
3375 getValue(I.getOperand(1)));
3378 setValue(&I, result);
3381 /// visitExp2 - Lower an exp2 intrinsic. Handles the special sequences for
3382 /// limited-precision mode.
3384 SelectionDAGBuilder::visitExp2(const CallInst &I) {
3386 DebugLoc dl = getCurDebugLoc();
3388 if (getValue(I.getOperand(1)).getValueType() == MVT::f32 &&
3389 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3390 SDValue Op = getValue(I.getOperand(1));
3392 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, Op);
3394 // FractionalPartOfX = x - (float)IntegerPartOfX;
3395 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX);
3396 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, Op, t1);
3398 // IntegerPartOfX <<= 23;
3399 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX,
3400 DAG.getConstant(23, TLI.getPointerTy()));
3402 if (LimitFloatPrecision <= 6) {
3403 // For floating-point precision of 6:
3405 // TwoToFractionalPartOfX =
3407 // (0.735607626f + 0.252464424f * x) * x;
3409 // error 0.0144103317, which is 6 bits
3410 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3411 getF32Constant(DAG, 0x3e814304));
3412 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3413 getF32Constant(DAG, 0x3f3c50c8));
3414 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3415 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3416 getF32Constant(DAG, 0x3f7f5e7e));
3417 SDValue t6 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, t5);
3418 SDValue TwoToFractionalPartOfX =
3419 DAG.getNode(ISD::ADD, dl, MVT::i32, t6, IntegerPartOfX);
3421 result = DAG.getNode(ISD::BIT_CONVERT, dl,
3422 MVT::f32, TwoToFractionalPartOfX);
3423 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
3424 // For floating-point precision of 12:
3426 // TwoToFractionalPartOfX =
3429 // (0.224338339f + 0.792043434e-1f * x) * x) * x;
3431 // error 0.000107046256, which is 13 to 14 bits
3432 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3433 getF32Constant(DAG, 0x3da235e3));
3434 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3435 getF32Constant(DAG, 0x3e65b8f3));
3436 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3437 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3438 getF32Constant(DAG, 0x3f324b07));
3439 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3440 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3441 getF32Constant(DAG, 0x3f7ff8fd));
3442 SDValue t8 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, t7);
3443 SDValue TwoToFractionalPartOfX =
3444 DAG.getNode(ISD::ADD, dl, MVT::i32, t8, IntegerPartOfX);
3446 result = DAG.getNode(ISD::BIT_CONVERT, dl,
3447 MVT::f32, TwoToFractionalPartOfX);
3448 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
3449 // For floating-point precision of 18:
3451 // TwoToFractionalPartOfX =
3455 // (0.554906021e-1f +
3456 // (0.961591928e-2f +
3457 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x;
3458 // error 2.47208000*10^(-7), which is better than 18 bits
3459 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3460 getF32Constant(DAG, 0x3924b03e));
3461 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3462 getF32Constant(DAG, 0x3ab24b87));
3463 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3464 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3465 getF32Constant(DAG, 0x3c1d8c17));
3466 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3467 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3468 getF32Constant(DAG, 0x3d634a1d));
3469 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3470 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3471 getF32Constant(DAG, 0x3e75fe14));
3472 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3473 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10,
3474 getF32Constant(DAG, 0x3f317234));
3475 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X);
3476 SDValue t13 = DAG.getNode(ISD::FADD, dl, MVT::f32, t12,
3477 getF32Constant(DAG, 0x3f800000));
3478 SDValue t14 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, t13);
3479 SDValue TwoToFractionalPartOfX =
3480 DAG.getNode(ISD::ADD, dl, MVT::i32, t14, IntegerPartOfX);
3482 result = DAG.getNode(ISD::BIT_CONVERT, dl,
3483 MVT::f32, TwoToFractionalPartOfX);
3486 // No special expansion.
3487 result = DAG.getNode(ISD::FEXP2, dl,
3488 getValue(I.getOperand(1)).getValueType(),
3489 getValue(I.getOperand(1)));
3492 setValue(&I, result);
3495 /// visitPow - Lower a pow intrinsic. Handles the special sequences for
3496 /// limited-precision mode with x == 10.0f.
3498 SelectionDAGBuilder::visitPow(const CallInst &I) {
3500 const Value *Val = I.getOperand(1);
3501 DebugLoc dl = getCurDebugLoc();
3502 bool IsExp10 = false;
3504 if (getValue(Val).getValueType() == MVT::f32 &&
3505 getValue(I.getOperand(2)).getValueType() == MVT::f32 &&
3506 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3507 if (Constant *C = const_cast<Constant*>(dyn_cast<Constant>(Val))) {
3508 if (ConstantFP *CFP = dyn_cast<ConstantFP>(C)) {
3510 IsExp10 = CFP->getValueAPF().bitwiseIsEqual(Ten);
3515 if (IsExp10 && LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3516 SDValue Op = getValue(I.getOperand(2));
3518 // Put the exponent in the right bit position for later addition to the
3521 // #define LOG2OF10 3.3219281f
3522 // IntegerPartOfX = (int32_t)(x * LOG2OF10);
3523 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, Op,
3524 getF32Constant(DAG, 0x40549a78));
3525 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, t0);
3527 // FractionalPartOfX = x - (float)IntegerPartOfX;
3528 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX);
3529 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, t1);
3531 // IntegerPartOfX <<= 23;
3532 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX,
3533 DAG.getConstant(23, TLI.getPointerTy()));
3535 if (LimitFloatPrecision <= 6) {
3536 // For floating-point precision of 6:
3538 // twoToFractionalPartOfX =
3540 // (0.735607626f + 0.252464424f * x) * x;
3542 // error 0.0144103317, which is 6 bits
3543 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3544 getF32Constant(DAG, 0x3e814304));
3545 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3546 getF32Constant(DAG, 0x3f3c50c8));
3547 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3548 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3549 getF32Constant(DAG, 0x3f7f5e7e));
3550 SDValue t6 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, t5);
3551 SDValue TwoToFractionalPartOfX =
3552 DAG.getNode(ISD::ADD, dl, MVT::i32, t6, IntegerPartOfX);
3554 result = DAG.getNode(ISD::BIT_CONVERT, dl,
3555 MVT::f32, TwoToFractionalPartOfX);
3556 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
3557 // For floating-point precision of 12:
3559 // TwoToFractionalPartOfX =
3562 // (0.224338339f + 0.792043434e-1f * x) * x) * x;
3564 // error 0.000107046256, which is 13 to 14 bits
3565 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3566 getF32Constant(DAG, 0x3da235e3));
3567 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3568 getF32Constant(DAG, 0x3e65b8f3));
3569 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3570 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3571 getF32Constant(DAG, 0x3f324b07));
3572 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3573 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3574 getF32Constant(DAG, 0x3f7ff8fd));
3575 SDValue t8 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, t7);
3576 SDValue TwoToFractionalPartOfX =
3577 DAG.getNode(ISD::ADD, dl, MVT::i32, t8, IntegerPartOfX);
3579 result = DAG.getNode(ISD::BIT_CONVERT, dl,
3580 MVT::f32, TwoToFractionalPartOfX);
3581 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
3582 // For floating-point precision of 18:
3584 // TwoToFractionalPartOfX =
3588 // (0.554906021e-1f +
3589 // (0.961591928e-2f +
3590 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x;
3591 // error 2.47208000*10^(-7), which is better than 18 bits
3592 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3593 getF32Constant(DAG, 0x3924b03e));
3594 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3595 getF32Constant(DAG, 0x3ab24b87));
3596 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3597 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3598 getF32Constant(DAG, 0x3c1d8c17));
3599 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3600 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3601 getF32Constant(DAG, 0x3d634a1d));
3602 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3603 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3604 getF32Constant(DAG, 0x3e75fe14));
3605 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3606 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10,
3607 getF32Constant(DAG, 0x3f317234));
3608 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X);
3609 SDValue t13 = DAG.getNode(ISD::FADD, dl, MVT::f32, t12,
3610 getF32Constant(DAG, 0x3f800000));
3611 SDValue t14 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, t13);
3612 SDValue TwoToFractionalPartOfX =
3613 DAG.getNode(ISD::ADD, dl, MVT::i32, t14, IntegerPartOfX);
3615 result = DAG.getNode(ISD::BIT_CONVERT, dl,
3616 MVT::f32, TwoToFractionalPartOfX);
3619 // No special expansion.
3620 result = DAG.getNode(ISD::FPOW, dl,
3621 getValue(I.getOperand(1)).getValueType(),
3622 getValue(I.getOperand(1)),
3623 getValue(I.getOperand(2)));
3626 setValue(&I, result);
3630 /// ExpandPowI - Expand a llvm.powi intrinsic.
3631 static SDValue ExpandPowI(DebugLoc DL, SDValue LHS, SDValue RHS,
3632 SelectionDAG &DAG) {
3633 // If RHS is a constant, we can expand this out to a multiplication tree,
3634 // otherwise we end up lowering to a call to __powidf2 (for example). When
3635 // optimizing for size, we only want to do this if the expansion would produce
3636 // a small number of multiplies, otherwise we do the full expansion.
3637 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
3638 // Get the exponent as a positive value.
3639 unsigned Val = RHSC->getSExtValue();
3640 if ((int)Val < 0) Val = -Val;
3642 // powi(x, 0) -> 1.0
3644 return DAG.getConstantFP(1.0, LHS.getValueType());
3646 const Function *F = DAG.getMachineFunction().getFunction();
3647 if (!F->hasFnAttr(Attribute::OptimizeForSize) ||
3648 // If optimizing for size, don't insert too many multiplies. This
3649 // inserts up to 5 multiplies.
3650 CountPopulation_32(Val)+Log2_32(Val) < 7) {
3651 // We use the simple binary decomposition method to generate the multiply
3652 // sequence. There are more optimal ways to do this (for example,
3653 // powi(x,15) generates one more multiply than it should), but this has
3654 // the benefit of being both really simple and much better than a libcall.
3655 SDValue Res; // Logically starts equal to 1.0
3656 SDValue CurSquare = LHS;
3660 Res = DAG.getNode(ISD::FMUL, DL,Res.getValueType(), Res, CurSquare);
3662 Res = CurSquare; // 1.0*CurSquare.
3665 CurSquare = DAG.getNode(ISD::FMUL, DL, CurSquare.getValueType(),
3666 CurSquare, CurSquare);
3670 // If the original was negative, invert the result, producing 1/(x*x*x).
3671 if (RHSC->getSExtValue() < 0)
3672 Res = DAG.getNode(ISD::FDIV, DL, LHS.getValueType(),
3673 DAG.getConstantFP(1.0, LHS.getValueType()), Res);
3678 // Otherwise, expand to a libcall.
3679 return DAG.getNode(ISD::FPOWI, DL, LHS.getValueType(), LHS, RHS);
3682 /// EmitFuncArgumentDbgValue - If the DbgValueInst is a dbg_value of a function
3683 /// argument, create the corresponding DBG_VALUE machine instruction for it now.
3684 /// At the end of instruction selection, they will be inserted to the entry BB.
3686 SelectionDAGBuilder::EmitFuncArgumentDbgValue(const DbgValueInst &DI,
3687 const Value *V, MDNode *Variable,
3690 if (!isa<Argument>(V))
3693 MachineFunction &MF = DAG.getMachineFunction();
3694 // Ignore inlined function arguments here.
3695 DIVariable DV(Variable);
3696 if (DV.isInlinedFnArgument(MF.getFunction()))
3699 MachineBasicBlock *MBB = FuncInfo.MBBMap[DI.getParent()];
3700 if (MBB != &MF.front())
3704 if (N.getOpcode() == ISD::CopyFromReg) {
3705 Reg = cast<RegisterSDNode>(N.getOperand(1))->getReg();
3706 if (Reg && TargetRegisterInfo::isVirtualRegister(Reg)) {
3707 MachineRegisterInfo &RegInfo = MF.getRegInfo();
3708 unsigned PR = RegInfo.getLiveInPhysReg(Reg);
3715 DenseMap<const Value *, unsigned>::iterator VMI = FuncInfo.ValueMap.find(V);
3716 if (VMI == FuncInfo.ValueMap.end())
3721 const TargetInstrInfo *TII = DAG.getTarget().getInstrInfo();
3722 MachineInstrBuilder MIB = BuildMI(MF, getCurDebugLoc(),
3723 TII->get(TargetOpcode::DBG_VALUE))
3724 .addReg(Reg, RegState::Debug).addImm(Offset).addMetadata(Variable);
3725 FuncInfo.ArgDbgValues.push_back(&*MIB);
3729 /// visitIntrinsicCall - Lower the call to the specified intrinsic function. If
3730 /// we want to emit this as a call to a named external function, return the name
3731 /// otherwise lower it and return null.
3733 SelectionDAGBuilder::visitIntrinsicCall(const CallInst &I, unsigned Intrinsic) {
3734 DebugLoc dl = getCurDebugLoc();
3737 switch (Intrinsic) {
3739 // By default, turn this into a target intrinsic node.
3740 visitTargetIntrinsic(I, Intrinsic);
3742 case Intrinsic::vastart: visitVAStart(I); return 0;
3743 case Intrinsic::vaend: visitVAEnd(I); return 0;
3744 case Intrinsic::vacopy: visitVACopy(I); return 0;
3745 case Intrinsic::returnaddress:
3746 setValue(&I, DAG.getNode(ISD::RETURNADDR, dl, TLI.getPointerTy(),
3747 getValue(I.getOperand(1))));
3749 case Intrinsic::frameaddress:
3750 setValue(&I, DAG.getNode(ISD::FRAMEADDR, dl, TLI.getPointerTy(),
3751 getValue(I.getOperand(1))));
3753 case Intrinsic::setjmp:
3754 return "_setjmp"+!TLI.usesUnderscoreSetJmp();
3755 case Intrinsic::longjmp:
3756 return "_longjmp"+!TLI.usesUnderscoreLongJmp();
3757 case Intrinsic::memcpy: {
3758 // Assert for address < 256 since we support only user defined address
3760 assert(cast<PointerType>(I.getOperand(1)->getType())->getAddressSpace()
3762 cast<PointerType>(I.getOperand(2)->getType())->getAddressSpace()
3764 "Unknown address space");
3765 SDValue Op1 = getValue(I.getOperand(1));
3766 SDValue Op2 = getValue(I.getOperand(2));
3767 SDValue Op3 = getValue(I.getOperand(3));
3768 unsigned Align = cast<ConstantInt>(I.getOperand(4))->getZExtValue();
3769 bool isVol = cast<ConstantInt>(I.getOperand(5))->getZExtValue();
3770 DAG.setRoot(DAG.getMemcpy(getRoot(), dl, Op1, Op2, Op3, Align, isVol, false,
3771 I.getOperand(1), 0, I.getOperand(2), 0));
3774 case Intrinsic::memset: {
3775 // Assert for address < 256 since we support only user defined address
3777 assert(cast<PointerType>(I.getOperand(1)->getType())->getAddressSpace()
3779 "Unknown address space");
3780 SDValue Op1 = getValue(I.getOperand(1));
3781 SDValue Op2 = getValue(I.getOperand(2));
3782 SDValue Op3 = getValue(I.getOperand(3));
3783 unsigned Align = cast<ConstantInt>(I.getOperand(4))->getZExtValue();
3784 bool isVol = cast<ConstantInt>(I.getOperand(5))->getZExtValue();
3785 DAG.setRoot(DAG.getMemset(getRoot(), dl, Op1, Op2, Op3, Align, isVol,
3786 I.getOperand(1), 0));
3789 case Intrinsic::memmove: {
3790 // Assert for address < 256 since we support only user defined address
3792 assert(cast<PointerType>(I.getOperand(1)->getType())->getAddressSpace()
3794 cast<PointerType>(I.getOperand(2)->getType())->getAddressSpace()
3796 "Unknown address space");
3797 SDValue Op1 = getValue(I.getOperand(1));
3798 SDValue Op2 = getValue(I.getOperand(2));
3799 SDValue Op3 = getValue(I.getOperand(3));
3800 unsigned Align = cast<ConstantInt>(I.getOperand(4))->getZExtValue();
3801 bool isVol = cast<ConstantInt>(I.getOperand(5))->getZExtValue();
3803 // If the source and destination are known to not be aliases, we can
3804 // lower memmove as memcpy.
3805 uint64_t Size = -1ULL;
3806 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op3))
3807 Size = C->getZExtValue();
3808 if (AA->alias(I.getOperand(1), Size, I.getOperand(2), Size) ==
3809 AliasAnalysis::NoAlias) {
3810 DAG.setRoot(DAG.getMemcpy(getRoot(), dl, Op1, Op2, Op3, Align, isVol,
3811 false, I.getOperand(1), 0, I.getOperand(2), 0));
3815 DAG.setRoot(DAG.getMemmove(getRoot(), dl, Op1, Op2, Op3, Align, isVol,
3816 I.getOperand(1), 0, I.getOperand(2), 0));
3819 case Intrinsic::dbg_declare: {
3820 const DbgDeclareInst &DI = cast<DbgDeclareInst>(I);
3821 if (!DIDescriptor::ValidDebugInfo(DI.getVariable(), CodeGenOpt::None))
3824 MDNode *Variable = DI.getVariable();
3825 // Parameters are handled specially.
3827 DIVariable(Variable).getTag() == dwarf::DW_TAG_arg_variable;
3828 const Value *Address = DI.getAddress();
3831 if (const BitCastInst *BCI = dyn_cast<BitCastInst>(Address))
3832 Address = BCI->getOperand(0);
3833 const AllocaInst *AI = dyn_cast<AllocaInst>(Address);
3835 // Don't handle byval arguments or VLAs, for example.
3836 // Non-byval arguments are handled here (they refer to the stack temporary
3837 // alloca at this point).
3838 DenseMap<const AllocaInst*, int>::iterator SI =
3839 FuncInfo.StaticAllocaMap.find(AI);
3840 if (SI == FuncInfo.StaticAllocaMap.end())
3842 int FI = SI->second;
3844 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
3845 if (!DI.getDebugLoc().isUnknown() && MMI.hasDebugInfo())
3846 MMI.setVariableDbgInfo(Variable, FI, DI.getDebugLoc());
3849 // Build an entry in DbgOrdering. Debug info input nodes get an SDNodeOrder
3850 // but do not always have a corresponding SDNode built. The SDNodeOrder
3851 // absolute, but not relative, values are different depending on whether
3852 // debug info exists.
3854 SDValue &N = NodeMap[Address];
3857 if (isParameter && !AI) {
3858 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(N.getNode());
3860 // Byval parameter. We have a frame index at this point.
3861 SDV = DAG.getDbgValue(Variable, FINode->getIndex(),
3862 0, dl, SDNodeOrder);
3864 // Can't do anything with other non-AI cases yet. This might be a
3865 // parameter of a callee function that got inlined, for example.
3868 SDV = DAG.getDbgValue(Variable, N.getNode(), N.getResNo(),
3869 0, dl, SDNodeOrder);
3871 // Can't do anything with other non-AI cases yet.
3873 DAG.AddDbgValue(SDV, N.getNode(), isParameter);
3875 // This isn't useful, but it shows what we're missing.
3876 SDV = DAG.getDbgValue(Variable, UndefValue::get(Address->getType()),
3877 0, dl, SDNodeOrder);
3878 DAG.AddDbgValue(SDV, 0, isParameter);
3882 case Intrinsic::dbg_value: {
3883 const DbgValueInst &DI = cast<DbgValueInst>(I);
3884 if (!DIDescriptor::ValidDebugInfo(DI.getVariable(), CodeGenOpt::None))
3887 MDNode *Variable = DI.getVariable();
3888 uint64_t Offset = DI.getOffset();
3889 const Value *V = DI.getValue();
3893 // Build an entry in DbgOrdering. Debug info input nodes get an SDNodeOrder
3894 // but do not always have a corresponding SDNode built. The SDNodeOrder
3895 // absolute, but not relative, values are different depending on whether
3896 // debug info exists.
3899 if (isa<ConstantInt>(V) || isa<ConstantFP>(V)) {
3900 SDV = DAG.getDbgValue(Variable, V, Offset, dl, SDNodeOrder);
3901 DAG.AddDbgValue(SDV, 0, false);
3903 SDValue &N = NodeMap[V];
3905 if (!EmitFuncArgumentDbgValue(DI, V, Variable, Offset, N)) {
3906 SDV = DAG.getDbgValue(Variable, N.getNode(),
3907 N.getResNo(), Offset, dl, SDNodeOrder);
3908 DAG.AddDbgValue(SDV, N.getNode(), false);
3911 // We may expand this to cover more cases. One case where we have no
3912 // data available is an unreferenced parameter; we need this fallback.
3913 SDV = DAG.getDbgValue(Variable, UndefValue::get(V->getType()),
3914 Offset, dl, SDNodeOrder);
3915 DAG.AddDbgValue(SDV, 0, false);
3919 // Build a debug info table entry.
3920 if (const BitCastInst *BCI = dyn_cast<BitCastInst>(V))
3921 V = BCI->getOperand(0);
3922 const AllocaInst *AI = dyn_cast<AllocaInst>(V);
3923 // Don't handle byval struct arguments or VLAs, for example.
3926 DenseMap<const AllocaInst*, int>::iterator SI =
3927 FuncInfo.StaticAllocaMap.find(AI);
3928 if (SI == FuncInfo.StaticAllocaMap.end())
3930 int FI = SI->second;
3932 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
3933 if (!DI.getDebugLoc().isUnknown() && MMI.hasDebugInfo())
3934 MMI.setVariableDbgInfo(Variable, FI, DI.getDebugLoc());
3937 case Intrinsic::eh_exception: {
3938 // Insert the EXCEPTIONADDR instruction.
3939 assert(FuncInfo.MBBMap[I.getParent()]->isLandingPad() &&
3940 "Call to eh.exception not in landing pad!");
3941 SDVTList VTs = DAG.getVTList(TLI.getPointerTy(), MVT::Other);
3943 Ops[0] = DAG.getRoot();
3944 SDValue Op = DAG.getNode(ISD::EXCEPTIONADDR, dl, VTs, Ops, 1);
3946 DAG.setRoot(Op.getValue(1));
3950 case Intrinsic::eh_selector: {
3951 MachineBasicBlock *CallMBB = FuncInfo.MBBMap[I.getParent()];
3952 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
3953 if (CallMBB->isLandingPad())
3954 AddCatchInfo(I, &MMI, CallMBB);
3957 FuncInfo.CatchInfoLost.insert(&I);
3959 // FIXME: Mark exception selector register as live in. Hack for PR1508.
3960 unsigned Reg = TLI.getExceptionSelectorRegister();
3961 if (Reg) FuncInfo.MBBMap[I.getParent()]->addLiveIn(Reg);
3964 // Insert the EHSELECTION instruction.
3965 SDVTList VTs = DAG.getVTList(TLI.getPointerTy(), MVT::Other);
3967 Ops[0] = getValue(I.getOperand(1));
3969 SDValue Op = DAG.getNode(ISD::EHSELECTION, dl, VTs, Ops, 2);
3970 DAG.setRoot(Op.getValue(1));
3971 setValue(&I, DAG.getSExtOrTrunc(Op, dl, MVT::i32));
3975 case Intrinsic::eh_typeid_for: {
3976 // Find the type id for the given typeinfo.
3977 GlobalVariable *GV = ExtractTypeInfo(I.getOperand(1));
3978 unsigned TypeID = DAG.getMachineFunction().getMMI().getTypeIDFor(GV);
3979 Res = DAG.getConstant(TypeID, MVT::i32);
3984 case Intrinsic::eh_return_i32:
3985 case Intrinsic::eh_return_i64:
3986 DAG.getMachineFunction().getMMI().setCallsEHReturn(true);
3987 DAG.setRoot(DAG.getNode(ISD::EH_RETURN, dl,
3990 getValue(I.getOperand(1)),
3991 getValue(I.getOperand(2))));
3993 case Intrinsic::eh_unwind_init:
3994 DAG.getMachineFunction().getMMI().setCallsUnwindInit(true);
3996 case Intrinsic::eh_dwarf_cfa: {
3997 EVT VT = getValue(I.getOperand(1)).getValueType();
3998 SDValue CfaArg = DAG.getSExtOrTrunc(getValue(I.getOperand(1)), dl,
3999 TLI.getPointerTy());
4000 SDValue Offset = DAG.getNode(ISD::ADD, dl,
4002 DAG.getNode(ISD::FRAME_TO_ARGS_OFFSET, dl,
4003 TLI.getPointerTy()),
4005 SDValue FA = DAG.getNode(ISD::FRAMEADDR, dl,
4007 DAG.getConstant(0, TLI.getPointerTy()));
4008 setValue(&I, DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(),
4012 case Intrinsic::eh_sjlj_callsite: {
4013 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
4014 ConstantInt *CI = dyn_cast<ConstantInt>(I.getOperand(1));
4015 assert(CI && "Non-constant call site value in eh.sjlj.callsite!");
4016 assert(MMI.getCurrentCallSite() == 0 && "Overlapping call sites!");
4018 MMI.setCurrentCallSite(CI->getZExtValue());
4022 case Intrinsic::convertff:
4023 case Intrinsic::convertfsi:
4024 case Intrinsic::convertfui:
4025 case Intrinsic::convertsif:
4026 case Intrinsic::convertuif:
4027 case Intrinsic::convertss:
4028 case Intrinsic::convertsu:
4029 case Intrinsic::convertus:
4030 case Intrinsic::convertuu: {
4031 ISD::CvtCode Code = ISD::CVT_INVALID;
4032 switch (Intrinsic) {
4033 case Intrinsic::convertff: Code = ISD::CVT_FF; break;
4034 case Intrinsic::convertfsi: Code = ISD::CVT_FS; break;
4035 case Intrinsic::convertfui: Code = ISD::CVT_FU; break;
4036 case Intrinsic::convertsif: Code = ISD::CVT_SF; break;
4037 case Intrinsic::convertuif: Code = ISD::CVT_UF; break;
4038 case Intrinsic::convertss: Code = ISD::CVT_SS; break;
4039 case Intrinsic::convertsu: Code = ISD::CVT_SU; break;
4040 case Intrinsic::convertus: Code = ISD::CVT_US; break;
4041 case Intrinsic::convertuu: Code = ISD::CVT_UU; break;
4043 EVT DestVT = TLI.getValueType(I.getType());
4044 const Value *Op1 = I.getOperand(1);
4045 Res = DAG.getConvertRndSat(DestVT, getCurDebugLoc(), getValue(Op1),
4046 DAG.getValueType(DestVT),
4047 DAG.getValueType(getValue(Op1).getValueType()),
4048 getValue(I.getOperand(2)),
4049 getValue(I.getOperand(3)),
4054 case Intrinsic::sqrt:
4055 setValue(&I, DAG.getNode(ISD::FSQRT, dl,
4056 getValue(I.getOperand(1)).getValueType(),
4057 getValue(I.getOperand(1))));
4059 case Intrinsic::powi:
4060 setValue(&I, ExpandPowI(dl, getValue(I.getOperand(1)),
4061 getValue(I.getOperand(2)), DAG));
4063 case Intrinsic::sin:
4064 setValue(&I, DAG.getNode(ISD::FSIN, dl,
4065 getValue(I.getOperand(1)).getValueType(),
4066 getValue(I.getOperand(1))));
4068 case Intrinsic::cos:
4069 setValue(&I, DAG.getNode(ISD::FCOS, dl,
4070 getValue(I.getOperand(1)).getValueType(),
4071 getValue(I.getOperand(1))));
4073 case Intrinsic::log:
4076 case Intrinsic::log2:
4079 case Intrinsic::log10:
4082 case Intrinsic::exp:
4085 case Intrinsic::exp2:
4088 case Intrinsic::pow:
4091 case Intrinsic::convert_to_fp16:
4092 setValue(&I, DAG.getNode(ISD::FP32_TO_FP16, dl,
4093 MVT::i16, getValue(I.getOperand(1))));
4095 case Intrinsic::convert_from_fp16:
4096 setValue(&I, DAG.getNode(ISD::FP16_TO_FP32, dl,
4097 MVT::f32, getValue(I.getOperand(1))));
4099 case Intrinsic::pcmarker: {
4100 SDValue Tmp = getValue(I.getOperand(1));
4101 DAG.setRoot(DAG.getNode(ISD::PCMARKER, dl, MVT::Other, getRoot(), Tmp));
4104 case Intrinsic::readcyclecounter: {
4105 SDValue Op = getRoot();
4106 Res = DAG.getNode(ISD::READCYCLECOUNTER, dl,
4107 DAG.getVTList(MVT::i64, MVT::Other),
4110 DAG.setRoot(Res.getValue(1));
4113 case Intrinsic::bswap:
4114 setValue(&I, DAG.getNode(ISD::BSWAP, dl,
4115 getValue(I.getOperand(1)).getValueType(),
4116 getValue(I.getOperand(1))));
4118 case Intrinsic::cttz: {
4119 SDValue Arg = getValue(I.getOperand(1));
4120 EVT Ty = Arg.getValueType();
4121 setValue(&I, DAG.getNode(ISD::CTTZ, dl, Ty, Arg));
4124 case Intrinsic::ctlz: {
4125 SDValue Arg = getValue(I.getOperand(1));
4126 EVT Ty = Arg.getValueType();
4127 setValue(&I, DAG.getNode(ISD::CTLZ, dl, Ty, Arg));
4130 case Intrinsic::ctpop: {
4131 SDValue Arg = getValue(I.getOperand(1));
4132 EVT Ty = Arg.getValueType();
4133 setValue(&I, DAG.getNode(ISD::CTPOP, dl, Ty, Arg));
4136 case Intrinsic::stacksave: {
4137 SDValue Op = getRoot();
4138 Res = DAG.getNode(ISD::STACKSAVE, dl,
4139 DAG.getVTList(TLI.getPointerTy(), MVT::Other), &Op, 1);
4141 DAG.setRoot(Res.getValue(1));
4144 case Intrinsic::stackrestore: {
4145 Res = getValue(I.getOperand(1));
4146 DAG.setRoot(DAG.getNode(ISD::STACKRESTORE, dl, MVT::Other, getRoot(), Res));
4149 case Intrinsic::stackprotector: {
4150 // Emit code into the DAG to store the stack guard onto the stack.
4151 MachineFunction &MF = DAG.getMachineFunction();
4152 MachineFrameInfo *MFI = MF.getFrameInfo();
4153 EVT PtrTy = TLI.getPointerTy();
4155 SDValue Src = getValue(I.getOperand(1)); // The guard's value.
4156 AllocaInst *Slot = cast<AllocaInst>(I.getOperand(2));
4158 int FI = FuncInfo.StaticAllocaMap[Slot];
4159 MFI->setStackProtectorIndex(FI);
4161 SDValue FIN = DAG.getFrameIndex(FI, PtrTy);
4163 // Store the stack protector onto the stack.
4164 Res = DAG.getStore(getRoot(), getCurDebugLoc(), Src, FIN,
4165 PseudoSourceValue::getFixedStack(FI),
4171 case Intrinsic::objectsize: {
4172 // If we don't know by now, we're never going to know.
4173 ConstantInt *CI = dyn_cast<ConstantInt>(I.getOperand(2));
4175 assert(CI && "Non-constant type in __builtin_object_size?");
4177 SDValue Arg = getValue(I.getOperand(0));
4178 EVT Ty = Arg.getValueType();
4180 if (CI->getZExtValue() == 0)
4181 Res = DAG.getConstant(-1ULL, Ty);
4183 Res = DAG.getConstant(0, Ty);
4188 case Intrinsic::var_annotation:
4189 // Discard annotate attributes
4192 case Intrinsic::init_trampoline: {
4193 const Function *F = cast<Function>(I.getOperand(2)->stripPointerCasts());
4197 Ops[1] = getValue(I.getOperand(1));
4198 Ops[2] = getValue(I.getOperand(2));
4199 Ops[3] = getValue(I.getOperand(3));
4200 Ops[4] = DAG.getSrcValue(I.getOperand(1));
4201 Ops[5] = DAG.getSrcValue(F);
4203 Res = DAG.getNode(ISD::TRAMPOLINE, dl,
4204 DAG.getVTList(TLI.getPointerTy(), MVT::Other),
4208 DAG.setRoot(Res.getValue(1));
4211 case Intrinsic::gcroot:
4213 const Value *Alloca = I.getOperand(1);
4214 const Constant *TypeMap = cast<Constant>(I.getOperand(2));
4216 FrameIndexSDNode *FI = cast<FrameIndexSDNode>(getValue(Alloca).getNode());
4217 GFI->addStackRoot(FI->getIndex(), TypeMap);
4220 case Intrinsic::gcread:
4221 case Intrinsic::gcwrite:
4222 llvm_unreachable("GC failed to lower gcread/gcwrite intrinsics!");
4224 case Intrinsic::flt_rounds:
4225 setValue(&I, DAG.getNode(ISD::FLT_ROUNDS_, dl, MVT::i32));
4227 case Intrinsic::trap:
4228 DAG.setRoot(DAG.getNode(ISD::TRAP, dl,MVT::Other, getRoot()));
4230 case Intrinsic::uadd_with_overflow:
4231 return implVisitAluOverflow(I, ISD::UADDO);
4232 case Intrinsic::sadd_with_overflow:
4233 return implVisitAluOverflow(I, ISD::SADDO);
4234 case Intrinsic::usub_with_overflow:
4235 return implVisitAluOverflow(I, ISD::USUBO);
4236 case Intrinsic::ssub_with_overflow:
4237 return implVisitAluOverflow(I, ISD::SSUBO);
4238 case Intrinsic::umul_with_overflow:
4239 return implVisitAluOverflow(I, ISD::UMULO);
4240 case Intrinsic::smul_with_overflow:
4241 return implVisitAluOverflow(I, ISD::SMULO);
4243 case Intrinsic::prefetch: {
4246 Ops[1] = getValue(I.getOperand(1));
4247 Ops[2] = getValue(I.getOperand(2));
4248 Ops[3] = getValue(I.getOperand(3));
4249 DAG.setRoot(DAG.getNode(ISD::PREFETCH, dl, MVT::Other, &Ops[0], 4));
4253 case Intrinsic::memory_barrier: {
4256 for (int x = 1; x < 6; ++x)
4257 Ops[x] = getValue(I.getOperand(x));
4259 DAG.setRoot(DAG.getNode(ISD::MEMBARRIER, dl, MVT::Other, &Ops[0], 6));
4262 case Intrinsic::atomic_cmp_swap: {
4263 SDValue Root = getRoot();
4265 DAG.getAtomic(ISD::ATOMIC_CMP_SWAP, getCurDebugLoc(),
4266 getValue(I.getOperand(2)).getValueType().getSimpleVT(),
4268 getValue(I.getOperand(1)),
4269 getValue(I.getOperand(2)),
4270 getValue(I.getOperand(3)),
4273 DAG.setRoot(L.getValue(1));
4276 case Intrinsic::atomic_load_add:
4277 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_ADD);
4278 case Intrinsic::atomic_load_sub:
4279 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_SUB);
4280 case Intrinsic::atomic_load_or:
4281 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_OR);
4282 case Intrinsic::atomic_load_xor:
4283 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_XOR);
4284 case Intrinsic::atomic_load_and:
4285 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_AND);
4286 case Intrinsic::atomic_load_nand:
4287 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_NAND);
4288 case Intrinsic::atomic_load_max:
4289 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_MAX);
4290 case Intrinsic::atomic_load_min:
4291 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_MIN);
4292 case Intrinsic::atomic_load_umin:
4293 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_UMIN);
4294 case Intrinsic::atomic_load_umax:
4295 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_UMAX);
4296 case Intrinsic::atomic_swap:
4297 return implVisitBinaryAtomic(I, ISD::ATOMIC_SWAP);
4299 case Intrinsic::invariant_start:
4300 case Intrinsic::lifetime_start:
4301 // Discard region information.
4302 setValue(&I, DAG.getUNDEF(TLI.getPointerTy()));
4304 case Intrinsic::invariant_end:
4305 case Intrinsic::lifetime_end:
4306 // Discard region information.
4311 void SelectionDAGBuilder::LowerCallTo(ImmutableCallSite CS, SDValue Callee,
4313 MachineBasicBlock *LandingPad) {
4314 const PointerType *PT = cast<PointerType>(CS.getCalledValue()->getType());
4315 const FunctionType *FTy = cast<FunctionType>(PT->getElementType());
4316 const Type *RetTy = FTy->getReturnType();
4317 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
4318 MCSymbol *BeginLabel = 0;
4320 TargetLowering::ArgListTy Args;
4321 TargetLowering::ArgListEntry Entry;
4322 Args.reserve(CS.arg_size());
4324 // Check whether the function can return without sret-demotion.
4325 SmallVector<EVT, 4> OutVTs;
4326 SmallVector<ISD::ArgFlagsTy, 4> OutsFlags;
4327 SmallVector<uint64_t, 4> Offsets;
4328 getReturnInfo(RetTy, CS.getAttributes().getRetAttributes(),
4329 OutVTs, OutsFlags, TLI, &Offsets);
4331 bool CanLowerReturn = TLI.CanLowerReturn(CS.getCallingConv(),
4332 FTy->isVarArg(), OutVTs, OutsFlags, DAG);
4334 SDValue DemoteStackSlot;
4336 if (!CanLowerReturn) {
4337 uint64_t TySize = TLI.getTargetData()->getTypeAllocSize(
4338 FTy->getReturnType());
4339 unsigned Align = TLI.getTargetData()->getPrefTypeAlignment(
4340 FTy->getReturnType());
4341 MachineFunction &MF = DAG.getMachineFunction();
4342 int SSFI = MF.getFrameInfo()->CreateStackObject(TySize, Align, false);
4343 const Type *StackSlotPtrType = PointerType::getUnqual(FTy->getReturnType());
4345 DemoteStackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy());
4346 Entry.Node = DemoteStackSlot;
4347 Entry.Ty = StackSlotPtrType;
4348 Entry.isSExt = false;
4349 Entry.isZExt = false;
4350 Entry.isInReg = false;
4351 Entry.isSRet = true;
4352 Entry.isNest = false;
4353 Entry.isByVal = false;
4354 Entry.Alignment = Align;
4355 Args.push_back(Entry);
4356 RetTy = Type::getVoidTy(FTy->getContext());
4359 for (ImmutableCallSite::arg_iterator i = CS.arg_begin(), e = CS.arg_end();
4361 SDValue ArgNode = getValue(*i);
4362 Entry.Node = ArgNode; Entry.Ty = (*i)->getType();
4364 unsigned attrInd = i - CS.arg_begin() + 1;
4365 Entry.isSExt = CS.paramHasAttr(attrInd, Attribute::SExt);
4366 Entry.isZExt = CS.paramHasAttr(attrInd, Attribute::ZExt);
4367 Entry.isInReg = CS.paramHasAttr(attrInd, Attribute::InReg);
4368 Entry.isSRet = CS.paramHasAttr(attrInd, Attribute::StructRet);
4369 Entry.isNest = CS.paramHasAttr(attrInd, Attribute::Nest);
4370 Entry.isByVal = CS.paramHasAttr(attrInd, Attribute::ByVal);
4371 Entry.Alignment = CS.getParamAlignment(attrInd);
4372 Args.push_back(Entry);
4376 // Insert a label before the invoke call to mark the try range. This can be
4377 // used to detect deletion of the invoke via the MachineModuleInfo.
4378 BeginLabel = MMI.getContext().CreateTempSymbol();
4380 // For SjLj, keep track of which landing pads go with which invokes
4381 // so as to maintain the ordering of pads in the LSDA.
4382 unsigned CallSiteIndex = MMI.getCurrentCallSite();
4383 if (CallSiteIndex) {
4384 MMI.setCallSiteBeginLabel(BeginLabel, CallSiteIndex);
4385 // Now that the call site is handled, stop tracking it.
4386 MMI.setCurrentCallSite(0);
4389 // Both PendingLoads and PendingExports must be flushed here;
4390 // this call might not return.
4392 DAG.setRoot(DAG.getEHLabel(getCurDebugLoc(), getControlRoot(), BeginLabel));
4395 // Check if target-independent constraints permit a tail call here.
4396 // Target-dependent constraints are checked within TLI.LowerCallTo.
4398 !isInTailCallPosition(CS, CS.getAttributes().getRetAttributes(), TLI))
4401 std::pair<SDValue,SDValue> Result =
4402 TLI.LowerCallTo(getRoot(), RetTy,
4403 CS.paramHasAttr(0, Attribute::SExt),
4404 CS.paramHasAttr(0, Attribute::ZExt), FTy->isVarArg(),
4405 CS.paramHasAttr(0, Attribute::InReg), FTy->getNumParams(),
4406 CS.getCallingConv(),
4408 !CS.getInstruction()->use_empty(),
4409 Callee, Args, DAG, getCurDebugLoc());
4410 assert((isTailCall || Result.second.getNode()) &&
4411 "Non-null chain expected with non-tail call!");
4412 assert((Result.second.getNode() || !Result.first.getNode()) &&
4413 "Null value expected with tail call!");
4414 if (Result.first.getNode()) {
4415 setValue(CS.getInstruction(), Result.first);
4416 } else if (!CanLowerReturn && Result.second.getNode()) {
4417 // The instruction result is the result of loading from the
4418 // hidden sret parameter.
4419 SmallVector<EVT, 1> PVTs;
4420 const Type *PtrRetTy = PointerType::getUnqual(FTy->getReturnType());
4422 ComputeValueVTs(TLI, PtrRetTy, PVTs);
4423 assert(PVTs.size() == 1 && "Pointers should fit in one register");
4424 EVT PtrVT = PVTs[0];
4425 unsigned NumValues = OutVTs.size();
4426 SmallVector<SDValue, 4> Values(NumValues);
4427 SmallVector<SDValue, 4> Chains(NumValues);
4429 for (unsigned i = 0; i < NumValues; ++i) {
4430 SDValue Add = DAG.getNode(ISD::ADD, getCurDebugLoc(), PtrVT,
4432 DAG.getConstant(Offsets[i], PtrVT));
4433 SDValue L = DAG.getLoad(OutVTs[i], getCurDebugLoc(), Result.second,
4434 Add, NULL, Offsets[i], false, false, 1);
4436 Chains[i] = L.getValue(1);
4439 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(),
4440 MVT::Other, &Chains[0], NumValues);
4441 PendingLoads.push_back(Chain);
4443 // Collect the legal value parts into potentially illegal values
4444 // that correspond to the original function's return values.
4445 SmallVector<EVT, 4> RetTys;
4446 RetTy = FTy->getReturnType();
4447 ComputeValueVTs(TLI, RetTy, RetTys);
4448 ISD::NodeType AssertOp = ISD::DELETED_NODE;
4449 SmallVector<SDValue, 4> ReturnValues;
4450 unsigned CurReg = 0;
4451 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
4453 EVT RegisterVT = TLI.getRegisterType(RetTy->getContext(), VT);
4454 unsigned NumRegs = TLI.getNumRegisters(RetTy->getContext(), VT);
4456 SDValue ReturnValue =
4457 getCopyFromParts(DAG, getCurDebugLoc(), &Values[CurReg], NumRegs,
4458 RegisterVT, VT, AssertOp);
4459 ReturnValues.push_back(ReturnValue);
4463 setValue(CS.getInstruction(),
4464 DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(),
4465 DAG.getVTList(&RetTys[0], RetTys.size()),
4466 &ReturnValues[0], ReturnValues.size()));
4470 // As a special case, a null chain means that a tail call has been emitted and
4471 // the DAG root is already updated.
4472 if (Result.second.getNode())
4473 DAG.setRoot(Result.second);
4478 // Insert a label at the end of the invoke call to mark the try range. This
4479 // can be used to detect deletion of the invoke via the MachineModuleInfo.
4480 MCSymbol *EndLabel = MMI.getContext().CreateTempSymbol();
4481 DAG.setRoot(DAG.getEHLabel(getCurDebugLoc(), getRoot(), EndLabel));
4483 // Inform MachineModuleInfo of range.
4484 MMI.addInvoke(LandingPad, BeginLabel, EndLabel);
4488 /// IsOnlyUsedInZeroEqualityComparison - Return true if it only matters that the
4489 /// value is equal or not-equal to zero.
4490 static bool IsOnlyUsedInZeroEqualityComparison(const Value *V) {
4491 for (Value::const_use_iterator UI = V->use_begin(), E = V->use_end();
4493 if (const ICmpInst *IC = dyn_cast<ICmpInst>(*UI))
4494 if (IC->isEquality())
4495 if (const Constant *C = dyn_cast<Constant>(IC->getOperand(1)))
4496 if (C->isNullValue())
4498 // Unknown instruction.
4504 static SDValue getMemCmpLoad(const Value *PtrVal, MVT LoadVT,
4506 SelectionDAGBuilder &Builder) {
4508 // Check to see if this load can be trivially constant folded, e.g. if the
4509 // input is from a string literal.
4510 if (const Constant *LoadInput = dyn_cast<Constant>(PtrVal)) {
4511 // Cast pointer to the type we really want to load.
4512 LoadInput = ConstantExpr::getBitCast(const_cast<Constant *>(LoadInput),
4513 PointerType::getUnqual(LoadTy));
4515 if (const Constant *LoadCst =
4516 ConstantFoldLoadFromConstPtr(const_cast<Constant *>(LoadInput),
4518 return Builder.getValue(LoadCst);
4521 // Otherwise, we have to emit the load. If the pointer is to unfoldable but
4522 // still constant memory, the input chain can be the entry node.
4524 bool ConstantMemory = false;
4526 // Do not serialize (non-volatile) loads of constant memory with anything.
4527 if (Builder.AA->pointsToConstantMemory(PtrVal)) {
4528 Root = Builder.DAG.getEntryNode();
4529 ConstantMemory = true;
4531 // Do not serialize non-volatile loads against each other.
4532 Root = Builder.DAG.getRoot();
4535 SDValue Ptr = Builder.getValue(PtrVal);
4536 SDValue LoadVal = Builder.DAG.getLoad(LoadVT, Builder.getCurDebugLoc(), Root,
4537 Ptr, PtrVal /*SrcValue*/, 0/*SVOffset*/,
4539 false /*nontemporal*/, 1 /* align=1 */);
4541 if (!ConstantMemory)
4542 Builder.PendingLoads.push_back(LoadVal.getValue(1));
4547 /// visitMemCmpCall - See if we can lower a call to memcmp in an optimized form.
4548 /// If so, return true and lower it, otherwise return false and it will be
4549 /// lowered like a normal call.
4550 bool SelectionDAGBuilder::visitMemCmpCall(const CallInst &I) {
4551 // Verify that the prototype makes sense. int memcmp(void*,void*,size_t)
4552 if (I.getNumOperands() != 4)
4555 const Value *LHS = I.getOperand(1), *RHS = I.getOperand(2);
4556 if (!LHS->getType()->isPointerTy() || !RHS->getType()->isPointerTy() ||
4557 !I.getOperand(3)->getType()->isIntegerTy() ||
4558 !I.getType()->isIntegerTy())
4561 const ConstantInt *Size = dyn_cast<ConstantInt>(I.getOperand(3));
4563 // memcmp(S1,S2,2) != 0 -> (*(short*)LHS != *(short*)RHS) != 0
4564 // memcmp(S1,S2,4) != 0 -> (*(int*)LHS != *(int*)RHS) != 0
4565 if (Size && IsOnlyUsedInZeroEqualityComparison(&I)) {
4566 bool ActuallyDoIt = true;
4569 switch (Size->getZExtValue()) {
4571 LoadVT = MVT::Other;
4573 ActuallyDoIt = false;
4577 LoadTy = Type::getInt16Ty(Size->getContext());
4581 LoadTy = Type::getInt32Ty(Size->getContext());
4585 LoadTy = Type::getInt64Ty(Size->getContext());
4589 LoadVT = MVT::v4i32;
4590 LoadTy = Type::getInt32Ty(Size->getContext());
4591 LoadTy = VectorType::get(LoadTy, 4);
4596 // This turns into unaligned loads. We only do this if the target natively
4597 // supports the MVT we'll be loading or if it is small enough (<= 4) that
4598 // we'll only produce a small number of byte loads.
4600 // Require that we can find a legal MVT, and only do this if the target
4601 // supports unaligned loads of that type. Expanding into byte loads would
4603 if (ActuallyDoIt && Size->getZExtValue() > 4) {
4604 // TODO: Handle 5 byte compare as 4-byte + 1 byte.
4605 // TODO: Handle 8 byte compare on x86-32 as two 32-bit loads.
4606 if (!TLI.isTypeLegal(LoadVT) ||!TLI.allowsUnalignedMemoryAccesses(LoadVT))
4607 ActuallyDoIt = false;
4611 SDValue LHSVal = getMemCmpLoad(LHS, LoadVT, LoadTy, *this);
4612 SDValue RHSVal = getMemCmpLoad(RHS, LoadVT, LoadTy, *this);
4614 SDValue Res = DAG.getSetCC(getCurDebugLoc(), MVT::i1, LHSVal, RHSVal,
4616 EVT CallVT = TLI.getValueType(I.getType(), true);
4617 setValue(&I, DAG.getZExtOrTrunc(Res, getCurDebugLoc(), CallVT));
4627 void SelectionDAGBuilder::visitCall(const CallInst &I) {
4628 const char *RenameFn = 0;
4629 if (Function *F = I.getCalledFunction()) {
4630 if (F->isDeclaration()) {
4631 const TargetIntrinsicInfo *II = TM.getIntrinsicInfo();
4633 if (unsigned IID = II->getIntrinsicID(F)) {
4634 RenameFn = visitIntrinsicCall(I, IID);
4639 if (unsigned IID = F->getIntrinsicID()) {
4640 RenameFn = visitIntrinsicCall(I, IID);
4646 // Check for well-known libc/libm calls. If the function is internal, it
4647 // can't be a library call.
4648 if (!F->hasLocalLinkage() && F->hasName()) {
4649 StringRef Name = F->getName();
4650 if (Name == "copysign" || Name == "copysignf" || Name == "copysignl") {
4651 if (I.getNumOperands() == 3 && // Basic sanity checks.
4652 I.getOperand(1)->getType()->isFloatingPointTy() &&
4653 I.getType() == I.getOperand(1)->getType() &&
4654 I.getType() == I.getOperand(2)->getType()) {
4655 SDValue LHS = getValue(I.getOperand(1));
4656 SDValue RHS = getValue(I.getOperand(2));
4657 setValue(&I, DAG.getNode(ISD::FCOPYSIGN, getCurDebugLoc(),
4658 LHS.getValueType(), LHS, RHS));
4661 } else if (Name == "fabs" || Name == "fabsf" || Name == "fabsl") {
4662 if (I.getNumOperands() == 2 && // Basic sanity checks.
4663 I.getOperand(1)->getType()->isFloatingPointTy() &&
4664 I.getType() == I.getOperand(1)->getType()) {
4665 SDValue Tmp = getValue(I.getOperand(1));
4666 setValue(&I, DAG.getNode(ISD::FABS, getCurDebugLoc(),
4667 Tmp.getValueType(), Tmp));
4670 } else if (Name == "sin" || Name == "sinf" || Name == "sinl") {
4671 if (I.getNumOperands() == 2 && // Basic sanity checks.
4672 I.getOperand(1)->getType()->isFloatingPointTy() &&
4673 I.getType() == I.getOperand(1)->getType() &&
4674 I.onlyReadsMemory()) {
4675 SDValue Tmp = getValue(I.getOperand(1));
4676 setValue(&I, DAG.getNode(ISD::FSIN, getCurDebugLoc(),
4677 Tmp.getValueType(), Tmp));
4680 } else if (Name == "cos" || Name == "cosf" || Name == "cosl") {
4681 if (I.getNumOperands() == 2 && // Basic sanity checks.
4682 I.getOperand(1)->getType()->isFloatingPointTy() &&
4683 I.getType() == I.getOperand(1)->getType() &&
4684 I.onlyReadsMemory()) {
4685 SDValue Tmp = getValue(I.getOperand(1));
4686 setValue(&I, DAG.getNode(ISD::FCOS, getCurDebugLoc(),
4687 Tmp.getValueType(), Tmp));
4690 } else if (Name == "sqrt" || Name == "sqrtf" || Name == "sqrtl") {
4691 if (I.getNumOperands() == 2 && // Basic sanity checks.
4692 I.getOperand(1)->getType()->isFloatingPointTy() &&
4693 I.getType() == I.getOperand(1)->getType() &&
4694 I.onlyReadsMemory()) {
4695 SDValue Tmp = getValue(I.getOperand(1));
4696 setValue(&I, DAG.getNode(ISD::FSQRT, getCurDebugLoc(),
4697 Tmp.getValueType(), Tmp));
4700 } else if (Name == "memcmp") {
4701 if (visitMemCmpCall(I))
4705 } else if (isa<InlineAsm>(I.getOperand(0))) {
4712 Callee = getValue(I.getOperand(0));
4714 Callee = DAG.getExternalSymbol(RenameFn, TLI.getPointerTy());
4716 // Check if we can potentially perform a tail call. More detailed checking is
4717 // be done within LowerCallTo, after more information about the call is known.
4718 LowerCallTo(&I, Callee, I.isTailCall());
4721 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from
4722 /// this value and returns the result as a ValueVT value. This uses
4723 /// Chain/Flag as the input and updates them for the output Chain/Flag.
4724 /// If the Flag pointer is NULL, no flag is used.
4725 SDValue RegsForValue::getCopyFromRegs(SelectionDAG &DAG, DebugLoc dl,
4726 SDValue &Chain, SDValue *Flag) const {
4727 // Assemble the legal parts into the final values.
4728 SmallVector<SDValue, 4> Values(ValueVTs.size());
4729 SmallVector<SDValue, 8> Parts;
4730 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) {
4731 // Copy the legal parts from the registers.
4732 EVT ValueVT = ValueVTs[Value];
4733 unsigned NumRegs = TLI->getNumRegisters(*DAG.getContext(), ValueVT);
4734 EVT RegisterVT = RegVTs[Value];
4736 Parts.resize(NumRegs);
4737 for (unsigned i = 0; i != NumRegs; ++i) {
4740 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT);
4742 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT, *Flag);
4743 *Flag = P.getValue(2);
4746 Chain = P.getValue(1);
4748 // If the source register was virtual and if we know something about it,
4749 // add an assert node.
4750 if (TargetRegisterInfo::isVirtualRegister(Regs[Part+i]) &&
4751 RegisterVT.isInteger() && !RegisterVT.isVector()) {
4752 unsigned SlotNo = Regs[Part+i]-TargetRegisterInfo::FirstVirtualRegister;
4753 FunctionLoweringInfo &FLI = DAG.getFunctionLoweringInfo();
4754 if (FLI.LiveOutRegInfo.size() > SlotNo) {
4755 FunctionLoweringInfo::LiveOutInfo &LOI = FLI.LiveOutRegInfo[SlotNo];
4757 unsigned RegSize = RegisterVT.getSizeInBits();
4758 unsigned NumSignBits = LOI.NumSignBits;
4759 unsigned NumZeroBits = LOI.KnownZero.countLeadingOnes();
4761 // FIXME: We capture more information than the dag can represent. For
4762 // now, just use the tightest assertzext/assertsext possible.
4764 EVT FromVT(MVT::Other);
4765 if (NumSignBits == RegSize)
4766 isSExt = true, FromVT = MVT::i1; // ASSERT SEXT 1
4767 else if (NumZeroBits >= RegSize-1)
4768 isSExt = false, FromVT = MVT::i1; // ASSERT ZEXT 1
4769 else if (NumSignBits > RegSize-8)
4770 isSExt = true, FromVT = MVT::i8; // ASSERT SEXT 8
4771 else if (NumZeroBits >= RegSize-8)
4772 isSExt = false, FromVT = MVT::i8; // ASSERT ZEXT 8
4773 else if (NumSignBits > RegSize-16)
4774 isSExt = true, FromVT = MVT::i16; // ASSERT SEXT 16
4775 else if (NumZeroBits >= RegSize-16)
4776 isSExt = false, FromVT = MVT::i16; // ASSERT ZEXT 16
4777 else if (NumSignBits > RegSize-32)
4778 isSExt = true, FromVT = MVT::i32; // ASSERT SEXT 32
4779 else if (NumZeroBits >= RegSize-32)
4780 isSExt = false, FromVT = MVT::i32; // ASSERT ZEXT 32
4782 if (FromVT != MVT::Other)
4783 P = DAG.getNode(isSExt ? ISD::AssertSext : ISD::AssertZext, dl,
4784 RegisterVT, P, DAG.getValueType(FromVT));
4791 Values[Value] = getCopyFromParts(DAG, dl, Parts.begin(),
4792 NumRegs, RegisterVT, ValueVT);
4797 return DAG.getNode(ISD::MERGE_VALUES, dl,
4798 DAG.getVTList(&ValueVTs[0], ValueVTs.size()),
4799 &Values[0], ValueVTs.size());
4802 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
4803 /// specified value into the registers specified by this object. This uses
4804 /// Chain/Flag as the input and updates them for the output Chain/Flag.
4805 /// If the Flag pointer is NULL, no flag is used.
4806 void RegsForValue::getCopyToRegs(SDValue Val, SelectionDAG &DAG, DebugLoc dl,
4807 SDValue &Chain, SDValue *Flag) const {
4808 // Get the list of the values's legal parts.
4809 unsigned NumRegs = Regs.size();
4810 SmallVector<SDValue, 8> Parts(NumRegs);
4811 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) {
4812 EVT ValueVT = ValueVTs[Value];
4813 unsigned NumParts = TLI->getNumRegisters(*DAG.getContext(), ValueVT);
4814 EVT RegisterVT = RegVTs[Value];
4816 getCopyToParts(DAG, dl,
4817 Val.getValue(Val.getResNo() + Value),
4818 &Parts[Part], NumParts, RegisterVT);
4822 // Copy the parts into the registers.
4823 SmallVector<SDValue, 8> Chains(NumRegs);
4824 for (unsigned i = 0; i != NumRegs; ++i) {
4827 Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i]);
4829 Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i], *Flag);
4830 *Flag = Part.getValue(1);
4833 Chains[i] = Part.getValue(0);
4836 if (NumRegs == 1 || Flag)
4837 // If NumRegs > 1 && Flag is used then the use of the last CopyToReg is
4838 // flagged to it. That is the CopyToReg nodes and the user are considered
4839 // a single scheduling unit. If we create a TokenFactor and return it as
4840 // chain, then the TokenFactor is both a predecessor (operand) of the
4841 // user as well as a successor (the TF operands are flagged to the user).
4842 // c1, f1 = CopyToReg
4843 // c2, f2 = CopyToReg
4844 // c3 = TokenFactor c1, c2
4847 Chain = Chains[NumRegs-1];
4849 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Chains[0], NumRegs);
4852 /// AddInlineAsmOperands - Add this value to the specified inlineasm node
4853 /// operand list. This adds the code marker and includes the number of
4854 /// values added into it.
4855 void RegsForValue::AddInlineAsmOperands(unsigned Code, bool HasMatching,
4856 unsigned MatchingIdx,
4858 std::vector<SDValue> &Ops) const {
4859 unsigned Flag = InlineAsm::getFlagWord(Code, Regs.size());
4861 Flag = InlineAsm::getFlagWordForMatchingOp(Flag, MatchingIdx);
4862 SDValue Res = DAG.getTargetConstant(Flag, MVT::i32);
4865 for (unsigned Value = 0, Reg = 0, e = ValueVTs.size(); Value != e; ++Value) {
4866 unsigned NumRegs = TLI->getNumRegisters(*DAG.getContext(), ValueVTs[Value]);
4867 EVT RegisterVT = RegVTs[Value];
4868 for (unsigned i = 0; i != NumRegs; ++i) {
4869 assert(Reg < Regs.size() && "Mismatch in # registers expected");
4870 Ops.push_back(DAG.getRegister(Regs[Reg++], RegisterVT));
4875 /// isAllocatableRegister - If the specified register is safe to allocate,
4876 /// i.e. it isn't a stack pointer or some other special register, return the
4877 /// register class for the register. Otherwise, return null.
4878 static const TargetRegisterClass *
4879 isAllocatableRegister(unsigned Reg, MachineFunction &MF,
4880 const TargetLowering &TLI,
4881 const TargetRegisterInfo *TRI) {
4882 EVT FoundVT = MVT::Other;
4883 const TargetRegisterClass *FoundRC = 0;
4884 for (TargetRegisterInfo::regclass_iterator RCI = TRI->regclass_begin(),
4885 E = TRI->regclass_end(); RCI != E; ++RCI) {
4886 EVT ThisVT = MVT::Other;
4888 const TargetRegisterClass *RC = *RCI;
4889 // If none of the value types for this register class are valid, we
4890 // can't use it. For example, 64-bit reg classes on 32-bit targets.
4891 for (TargetRegisterClass::vt_iterator I = RC->vt_begin(), E = RC->vt_end();
4893 if (TLI.isTypeLegal(*I)) {
4894 // If we have already found this register in a different register class,
4895 // choose the one with the largest VT specified. For example, on
4896 // PowerPC, we favor f64 register classes over f32.
4897 if (FoundVT == MVT::Other || FoundVT.bitsLT(*I)) {
4904 if (ThisVT == MVT::Other) continue;
4906 // NOTE: This isn't ideal. In particular, this might allocate the
4907 // frame pointer in functions that need it (due to them not being taken
4908 // out of allocation, because a variable sized allocation hasn't been seen
4909 // yet). This is a slight code pessimization, but should still work.
4910 for (TargetRegisterClass::iterator I = RC->allocation_order_begin(MF),
4911 E = RC->allocation_order_end(MF); I != E; ++I)
4913 // We found a matching register class. Keep looking at others in case
4914 // we find one with larger registers that this physreg is also in.
4925 /// AsmOperandInfo - This contains information for each constraint that we are
4927 class VISIBILITY_HIDDEN SDISelAsmOperandInfo :
4928 public TargetLowering::AsmOperandInfo {
4930 /// CallOperand - If this is the result output operand or a clobber
4931 /// this is null, otherwise it is the incoming operand to the CallInst.
4932 /// This gets modified as the asm is processed.
4933 SDValue CallOperand;
4935 /// AssignedRegs - If this is a register or register class operand, this
4936 /// contains the set of register corresponding to the operand.
4937 RegsForValue AssignedRegs;
4939 explicit SDISelAsmOperandInfo(const InlineAsm::ConstraintInfo &info)
4940 : TargetLowering::AsmOperandInfo(info), CallOperand(0,0) {
4943 /// MarkAllocatedRegs - Once AssignedRegs is set, mark the assigned registers
4944 /// busy in OutputRegs/InputRegs.
4945 void MarkAllocatedRegs(bool isOutReg, bool isInReg,
4946 std::set<unsigned> &OutputRegs,
4947 std::set<unsigned> &InputRegs,
4948 const TargetRegisterInfo &TRI) const {
4950 for (unsigned i = 0, e = AssignedRegs.Regs.size(); i != e; ++i)
4951 MarkRegAndAliases(AssignedRegs.Regs[i], OutputRegs, TRI);
4954 for (unsigned i = 0, e = AssignedRegs.Regs.size(); i != e; ++i)
4955 MarkRegAndAliases(AssignedRegs.Regs[i], InputRegs, TRI);
4959 /// getCallOperandValEVT - Return the EVT of the Value* that this operand
4960 /// corresponds to. If there is no Value* for this operand, it returns
4962 EVT getCallOperandValEVT(LLVMContext &Context,
4963 const TargetLowering &TLI,
4964 const TargetData *TD) const {
4965 if (CallOperandVal == 0) return MVT::Other;
4967 if (isa<BasicBlock>(CallOperandVal))
4968 return TLI.getPointerTy();
4970 const llvm::Type *OpTy = CallOperandVal->getType();
4972 // If this is an indirect operand, the operand is a pointer to the
4975 const llvm::PointerType *PtrTy = dyn_cast<PointerType>(OpTy);
4977 report_fatal_error("Indirect operand for inline asm not a pointer!");
4978 OpTy = PtrTy->getElementType();
4981 // If OpTy is not a single value, it may be a struct/union that we
4982 // can tile with integers.
4983 if (!OpTy->isSingleValueType() && OpTy->isSized()) {
4984 unsigned BitSize = TD->getTypeSizeInBits(OpTy);
4993 OpTy = IntegerType::get(Context, BitSize);
4998 return TLI.getValueType(OpTy, true);
5002 /// MarkRegAndAliases - Mark the specified register and all aliases in the
5004 static void MarkRegAndAliases(unsigned Reg, std::set<unsigned> &Regs,
5005 const TargetRegisterInfo &TRI) {
5006 assert(TargetRegisterInfo::isPhysicalRegister(Reg) && "Isn't a physreg");
5008 if (const unsigned *Aliases = TRI.getAliasSet(Reg))
5009 for (; *Aliases; ++Aliases)
5010 Regs.insert(*Aliases);
5013 } // end llvm namespace.
5016 /// GetRegistersForValue - Assign registers (virtual or physical) for the
5017 /// specified operand. We prefer to assign virtual registers, to allow the
5018 /// register allocator to handle the assignment process. However, if the asm
5019 /// uses features that we can't model on machineinstrs, we have SDISel do the
5020 /// allocation. This produces generally horrible, but correct, code.
5022 /// OpInfo describes the operand.
5023 /// Input and OutputRegs are the set of already allocated physical registers.
5025 void SelectionDAGBuilder::
5026 GetRegistersForValue(SDISelAsmOperandInfo &OpInfo,
5027 std::set<unsigned> &OutputRegs,
5028 std::set<unsigned> &InputRegs) {
5029 LLVMContext &Context = FuncInfo.Fn->getContext();
5031 // Compute whether this value requires an input register, an output register,
5033 bool isOutReg = false;
5034 bool isInReg = false;
5035 switch (OpInfo.Type) {
5036 case InlineAsm::isOutput:
5039 // If there is an input constraint that matches this, we need to reserve
5040 // the input register so no other inputs allocate to it.
5041 isInReg = OpInfo.hasMatchingInput();
5043 case InlineAsm::isInput:
5047 case InlineAsm::isClobber:
5054 MachineFunction &MF = DAG.getMachineFunction();
5055 SmallVector<unsigned, 4> Regs;
5057 // If this is a constraint for a single physreg, or a constraint for a
5058 // register class, find it.
5059 std::pair<unsigned, const TargetRegisterClass*> PhysReg =
5060 TLI.getRegForInlineAsmConstraint(OpInfo.ConstraintCode,
5061 OpInfo.ConstraintVT);
5063 unsigned NumRegs = 1;
5064 if (OpInfo.ConstraintVT != MVT::Other) {
5065 // If this is a FP input in an integer register (or visa versa) insert a bit
5066 // cast of the input value. More generally, handle any case where the input
5067 // value disagrees with the register class we plan to stick this in.
5068 if (OpInfo.Type == InlineAsm::isInput &&
5069 PhysReg.second && !PhysReg.second->hasType(OpInfo.ConstraintVT)) {
5070 // Try to convert to the first EVT that the reg class contains. If the
5071 // types are identical size, use a bitcast to convert (e.g. two differing
5073 EVT RegVT = *PhysReg.second->vt_begin();
5074 if (RegVT.getSizeInBits() == OpInfo.ConstraintVT.getSizeInBits()) {
5075 OpInfo.CallOperand = DAG.getNode(ISD::BIT_CONVERT, getCurDebugLoc(),
5076 RegVT, OpInfo.CallOperand);
5077 OpInfo.ConstraintVT = RegVT;
5078 } else if (RegVT.isInteger() && OpInfo.ConstraintVT.isFloatingPoint()) {
5079 // If the input is a FP value and we want it in FP registers, do a
5080 // bitcast to the corresponding integer type. This turns an f64 value
5081 // into i64, which can be passed with two i32 values on a 32-bit
5083 RegVT = EVT::getIntegerVT(Context,
5084 OpInfo.ConstraintVT.getSizeInBits());
5085 OpInfo.CallOperand = DAG.getNode(ISD::BIT_CONVERT, getCurDebugLoc(),
5086 RegVT, OpInfo.CallOperand);
5087 OpInfo.ConstraintVT = RegVT;
5091 NumRegs = TLI.getNumRegisters(Context, OpInfo.ConstraintVT);
5095 EVT ValueVT = OpInfo.ConstraintVT;
5097 // If this is a constraint for a specific physical register, like {r17},
5099 if (unsigned AssignedReg = PhysReg.first) {
5100 const TargetRegisterClass *RC = PhysReg.second;
5101 if (OpInfo.ConstraintVT == MVT::Other)
5102 ValueVT = *RC->vt_begin();
5104 // Get the actual register value type. This is important, because the user
5105 // may have asked for (e.g.) the AX register in i32 type. We need to
5106 // remember that AX is actually i16 to get the right extension.
5107 RegVT = *RC->vt_begin();
5109 // This is a explicit reference to a physical register.
5110 Regs.push_back(AssignedReg);
5112 // If this is an expanded reference, add the rest of the regs to Regs.
5114 TargetRegisterClass::iterator I = RC->begin();
5115 for (; *I != AssignedReg; ++I)
5116 assert(I != RC->end() && "Didn't find reg!");
5118 // Already added the first reg.
5120 for (; NumRegs; --NumRegs, ++I) {
5121 assert(I != RC->end() && "Ran out of registers to allocate!");
5126 OpInfo.AssignedRegs = RegsForValue(TLI, Regs, RegVT, ValueVT);
5127 const TargetRegisterInfo *TRI = DAG.getTarget().getRegisterInfo();
5128 OpInfo.MarkAllocatedRegs(isOutReg, isInReg, OutputRegs, InputRegs, *TRI);
5132 // Otherwise, if this was a reference to an LLVM register class, create vregs
5133 // for this reference.
5134 if (const TargetRegisterClass *RC = PhysReg.second) {
5135 RegVT = *RC->vt_begin();
5136 if (OpInfo.ConstraintVT == MVT::Other)
5139 // Create the appropriate number of virtual registers.
5140 MachineRegisterInfo &RegInfo = MF.getRegInfo();
5141 for (; NumRegs; --NumRegs)
5142 Regs.push_back(RegInfo.createVirtualRegister(RC));
5144 OpInfo.AssignedRegs = RegsForValue(TLI, Regs, RegVT, ValueVT);
5148 // This is a reference to a register class that doesn't directly correspond
5149 // to an LLVM register class. Allocate NumRegs consecutive, available,
5150 // registers from the class.
5151 std::vector<unsigned> RegClassRegs
5152 = TLI.getRegClassForInlineAsmConstraint(OpInfo.ConstraintCode,
5153 OpInfo.ConstraintVT);
5155 const TargetRegisterInfo *TRI = DAG.getTarget().getRegisterInfo();
5156 unsigned NumAllocated = 0;
5157 for (unsigned i = 0, e = RegClassRegs.size(); i != e; ++i) {
5158 unsigned Reg = RegClassRegs[i];
5159 // See if this register is available.
5160 if ((isOutReg && OutputRegs.count(Reg)) || // Already used.
5161 (isInReg && InputRegs.count(Reg))) { // Already used.
5162 // Make sure we find consecutive registers.
5167 // Check to see if this register is allocatable (i.e. don't give out the
5169 const TargetRegisterClass *RC = isAllocatableRegister(Reg, MF, TLI, TRI);
5170 if (!RC) { // Couldn't allocate this register.
5171 // Reset NumAllocated to make sure we return consecutive registers.
5176 // Okay, this register is good, we can use it.
5179 // If we allocated enough consecutive registers, succeed.
5180 if (NumAllocated == NumRegs) {
5181 unsigned RegStart = (i-NumAllocated)+1;
5182 unsigned RegEnd = i+1;
5183 // Mark all of the allocated registers used.
5184 for (unsigned i = RegStart; i != RegEnd; ++i)
5185 Regs.push_back(RegClassRegs[i]);
5187 OpInfo.AssignedRegs = RegsForValue(TLI, Regs, *RC->vt_begin(),
5188 OpInfo.ConstraintVT);
5189 OpInfo.MarkAllocatedRegs(isOutReg, isInReg, OutputRegs, InputRegs, *TRI);
5194 // Otherwise, we couldn't allocate enough registers for this.
5197 /// visitInlineAsm - Handle a call to an InlineAsm object.
5199 void SelectionDAGBuilder::visitInlineAsm(ImmutableCallSite CS) {
5200 const InlineAsm *IA = cast<InlineAsm>(CS.getCalledValue());
5202 /// ConstraintOperands - Information about all of the constraints.
5203 std::vector<SDISelAsmOperandInfo> ConstraintOperands;
5205 std::set<unsigned> OutputRegs, InputRegs;
5207 // Do a prepass over the constraints, canonicalizing them, and building up the
5208 // ConstraintOperands list.
5209 std::vector<InlineAsm::ConstraintInfo>
5210 ConstraintInfos = IA->ParseConstraints();
5212 bool hasMemory = hasInlineAsmMemConstraint(ConstraintInfos, TLI);
5214 SDValue Chain, Flag;
5216 // We won't need to flush pending loads if this asm doesn't touch
5217 // memory and is nonvolatile.
5218 if (hasMemory || IA->hasSideEffects())
5221 Chain = DAG.getRoot();
5223 unsigned ArgNo = 0; // ArgNo - The argument of the CallInst.
5224 unsigned ResNo = 0; // ResNo - The result number of the next output.
5225 for (unsigned i = 0, e = ConstraintInfos.size(); i != e; ++i) {
5226 ConstraintOperands.push_back(SDISelAsmOperandInfo(ConstraintInfos[i]));
5227 SDISelAsmOperandInfo &OpInfo = ConstraintOperands.back();
5229 EVT OpVT = MVT::Other;
5231 // Compute the value type for each operand.
5232 switch (OpInfo.Type) {
5233 case InlineAsm::isOutput:
5234 // Indirect outputs just consume an argument.
5235 if (OpInfo.isIndirect) {
5236 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++));
5240 // The return value of the call is this value. As such, there is no
5241 // corresponding argument.
5242 assert(!CS.getType()->isVoidTy() &&
5244 if (const StructType *STy = dyn_cast<StructType>(CS.getType())) {
5245 OpVT = TLI.getValueType(STy->getElementType(ResNo));
5247 assert(ResNo == 0 && "Asm only has one result!");
5248 OpVT = TLI.getValueType(CS.getType());
5252 case InlineAsm::isInput:
5253 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++));
5255 case InlineAsm::isClobber:
5260 // If this is an input or an indirect output, process the call argument.
5261 // BasicBlocks are labels, currently appearing only in asm's.
5262 if (OpInfo.CallOperandVal) {
5263 // Strip bitcasts, if any. This mostly comes up for functions.
5264 OpInfo.CallOperandVal = OpInfo.CallOperandVal->stripPointerCasts();
5266 if (const BasicBlock *BB = dyn_cast<BasicBlock>(OpInfo.CallOperandVal)) {
5267 OpInfo.CallOperand = DAG.getBasicBlock(FuncInfo.MBBMap[BB]);
5269 OpInfo.CallOperand = getValue(OpInfo.CallOperandVal);
5272 OpVT = OpInfo.getCallOperandValEVT(*DAG.getContext(), TLI, TD);
5275 OpInfo.ConstraintVT = OpVT;
5278 // Second pass over the constraints: compute which constraint option to use
5279 // and assign registers to constraints that want a specific physreg.
5280 for (unsigned i = 0, e = ConstraintInfos.size(); i != e; ++i) {
5281 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
5283 // If this is an output operand with a matching input operand, look up the
5284 // matching input. If their types mismatch, e.g. one is an integer, the
5285 // other is floating point, or their sizes are different, flag it as an
5287 if (OpInfo.hasMatchingInput()) {
5288 SDISelAsmOperandInfo &Input = ConstraintOperands[OpInfo.MatchingInput];
5290 if (OpInfo.ConstraintVT != Input.ConstraintVT) {
5291 if ((OpInfo.ConstraintVT.isInteger() !=
5292 Input.ConstraintVT.isInteger()) ||
5293 (OpInfo.ConstraintVT.getSizeInBits() !=
5294 Input.ConstraintVT.getSizeInBits())) {
5295 report_fatal_error("Unsupported asm: input constraint"
5296 " with a matching output constraint of"
5297 " incompatible type!");
5299 Input.ConstraintVT = OpInfo.ConstraintVT;
5303 // Compute the constraint code and ConstraintType to use.
5304 TLI.ComputeConstraintToUse(OpInfo, OpInfo.CallOperand, hasMemory, &DAG);
5306 // If this is a memory input, and if the operand is not indirect, do what we
5307 // need to to provide an address for the memory input.
5308 if (OpInfo.ConstraintType == TargetLowering::C_Memory &&
5309 !OpInfo.isIndirect) {
5310 assert(OpInfo.Type == InlineAsm::isInput &&
5311 "Can only indirectify direct input operands!");
5313 // Memory operands really want the address of the value. If we don't have
5314 // an indirect input, put it in the constpool if we can, otherwise spill
5315 // it to a stack slot.
5317 // If the operand is a float, integer, or vector constant, spill to a
5318 // constant pool entry to get its address.
5319 const Value *OpVal = OpInfo.CallOperandVal;
5320 if (isa<ConstantFP>(OpVal) || isa<ConstantInt>(OpVal) ||
5321 isa<ConstantVector>(OpVal)) {
5322 OpInfo.CallOperand = DAG.getConstantPool(cast<Constant>(OpVal),
5323 TLI.getPointerTy());
5325 // Otherwise, create a stack slot and emit a store to it before the
5327 const Type *Ty = OpVal->getType();
5328 uint64_t TySize = TLI.getTargetData()->getTypeAllocSize(Ty);
5329 unsigned Align = TLI.getTargetData()->getPrefTypeAlignment(Ty);
5330 MachineFunction &MF = DAG.getMachineFunction();
5331 int SSFI = MF.getFrameInfo()->CreateStackObject(TySize, Align, false);
5332 SDValue StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy());
5333 Chain = DAG.getStore(Chain, getCurDebugLoc(),
5334 OpInfo.CallOperand, StackSlot, NULL, 0,
5336 OpInfo.CallOperand = StackSlot;
5339 // There is no longer a Value* corresponding to this operand.
5340 OpInfo.CallOperandVal = 0;
5342 // It is now an indirect operand.
5343 OpInfo.isIndirect = true;
5346 // If this constraint is for a specific register, allocate it before
5348 if (OpInfo.ConstraintType == TargetLowering::C_Register)
5349 GetRegistersForValue(OpInfo, OutputRegs, InputRegs);
5352 ConstraintInfos.clear();
5354 // Second pass - Loop over all of the operands, assigning virtual or physregs
5355 // to register class operands.
5356 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
5357 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
5359 // C_Register operands have already been allocated, Other/Memory don't need
5361 if (OpInfo.ConstraintType == TargetLowering::C_RegisterClass)
5362 GetRegistersForValue(OpInfo, OutputRegs, InputRegs);
5365 // AsmNodeOperands - The operands for the ISD::INLINEASM node.
5366 std::vector<SDValue> AsmNodeOperands;
5367 AsmNodeOperands.push_back(SDValue()); // reserve space for input chain
5368 AsmNodeOperands.push_back(
5369 DAG.getTargetExternalSymbol(IA->getAsmString().c_str(),
5370 TLI.getPointerTy()));
5372 // If we have a !srcloc metadata node associated with it, we want to attach
5373 // this to the ultimately generated inline asm machineinstr. To do this, we
5374 // pass in the third operand as this (potentially null) inline asm MDNode.
5375 const MDNode *SrcLoc = CS.getInstruction()->getMetadata("srcloc");
5376 AsmNodeOperands.push_back(DAG.getMDNode(SrcLoc));
5378 // Loop over all of the inputs, copying the operand values into the
5379 // appropriate registers and processing the output regs.
5380 RegsForValue RetValRegs;
5382 // IndirectStoresToEmit - The set of stores to emit after the inline asm node.
5383 std::vector<std::pair<RegsForValue, Value*> > IndirectStoresToEmit;
5385 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
5386 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
5388 switch (OpInfo.Type) {
5389 case InlineAsm::isOutput: {
5390 if (OpInfo.ConstraintType != TargetLowering::C_RegisterClass &&
5391 OpInfo.ConstraintType != TargetLowering::C_Register) {
5392 // Memory output, or 'other' output (e.g. 'X' constraint).
5393 assert(OpInfo.isIndirect && "Memory output must be indirect operand");
5395 // Add information to the INLINEASM node to know about this output.
5396 unsigned OpFlags = InlineAsm::getFlagWord(InlineAsm::Kind_Mem, 1);
5397 AsmNodeOperands.push_back(DAG.getTargetConstant(OpFlags,
5398 TLI.getPointerTy()));
5399 AsmNodeOperands.push_back(OpInfo.CallOperand);
5403 // Otherwise, this is a register or register class output.
5405 // Copy the output from the appropriate register. Find a register that
5407 if (OpInfo.AssignedRegs.Regs.empty())
5408 report_fatal_error("Couldn't allocate output reg for constraint '" +
5409 Twine(OpInfo.ConstraintCode) + "'!");
5411 // If this is an indirect operand, store through the pointer after the
5413 if (OpInfo.isIndirect) {
5414 IndirectStoresToEmit.push_back(std::make_pair(OpInfo.AssignedRegs,
5415 OpInfo.CallOperandVal));
5417 // This is the result value of the call.
5418 assert(!CS.getType()->isVoidTy() && "Bad inline asm!");
5419 // Concatenate this output onto the outputs list.
5420 RetValRegs.append(OpInfo.AssignedRegs);
5423 // Add information to the INLINEASM node to know that this register is
5425 OpInfo.AssignedRegs.AddInlineAsmOperands(OpInfo.isEarlyClobber ?
5426 InlineAsm::Kind_RegDefEarlyClobber :
5427 InlineAsm::Kind_RegDef,
5434 case InlineAsm::isInput: {
5435 SDValue InOperandVal = OpInfo.CallOperand;
5437 if (OpInfo.isMatchingInputConstraint()) { // Matching constraint?
5438 // If this is required to match an output register we have already set,
5439 // just use its register.
5440 unsigned OperandNo = OpInfo.getMatchedOperand();
5442 // Scan until we find the definition we already emitted of this operand.
5443 // When we find it, create a RegsForValue operand.
5444 unsigned CurOp = InlineAsm::Op_FirstOperand;
5445 for (; OperandNo; --OperandNo) {
5446 // Advance to the next operand.
5448 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue();
5449 assert((InlineAsm::isRegDefKind(OpFlag) ||
5450 InlineAsm::isRegDefEarlyClobberKind(OpFlag) ||
5451 InlineAsm::isMemKind(OpFlag)) && "Skipped past definitions?");
5452 CurOp += InlineAsm::getNumOperandRegisters(OpFlag)+1;
5456 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue();
5457 if (InlineAsm::isRegDefKind(OpFlag) ||
5458 InlineAsm::isRegDefEarlyClobberKind(OpFlag)) {
5459 // Add (OpFlag&0xffff)>>3 registers to MatchedRegs.
5460 if (OpInfo.isIndirect) {
5461 // This happens on gcc/testsuite/gcc.dg/pr8788-1.c
5462 LLVMContext &Ctx = *DAG.getContext();
5463 Ctx.emitError(CS.getInstruction(), "inline asm not supported yet:"
5464 " don't know how to handle tied "
5465 "indirect register inputs");
5468 RegsForValue MatchedRegs;
5469 MatchedRegs.TLI = &TLI;
5470 MatchedRegs.ValueVTs.push_back(InOperandVal.getValueType());
5471 EVT RegVT = AsmNodeOperands[CurOp+1].getValueType();
5472 MatchedRegs.RegVTs.push_back(RegVT);
5473 MachineRegisterInfo &RegInfo = DAG.getMachineFunction().getRegInfo();
5474 for (unsigned i = 0, e = InlineAsm::getNumOperandRegisters(OpFlag);
5476 MatchedRegs.Regs.push_back
5477 (RegInfo.createVirtualRegister(TLI.getRegClassFor(RegVT)));
5479 // Use the produced MatchedRegs object to
5480 MatchedRegs.getCopyToRegs(InOperandVal, DAG, getCurDebugLoc(),
5482 MatchedRegs.AddInlineAsmOperands(InlineAsm::Kind_RegUse,
5483 true, OpInfo.getMatchedOperand(),
5484 DAG, AsmNodeOperands);
5488 assert(InlineAsm::isMemKind(OpFlag) && "Unknown matching constraint!");
5489 assert(InlineAsm::getNumOperandRegisters(OpFlag) == 1 &&
5490 "Unexpected number of operands");
5491 // Add information to the INLINEASM node to know about this input.
5492 // See InlineAsm.h isUseOperandTiedToDef.
5493 OpFlag = InlineAsm::getFlagWordForMatchingOp(OpFlag,
5494 OpInfo.getMatchedOperand());
5495 AsmNodeOperands.push_back(DAG.getTargetConstant(OpFlag,
5496 TLI.getPointerTy()));
5497 AsmNodeOperands.push_back(AsmNodeOperands[CurOp+1]);
5501 if (OpInfo.ConstraintType == TargetLowering::C_Other) {
5502 assert(!OpInfo.isIndirect &&
5503 "Don't know how to handle indirect other inputs yet!");
5505 std::vector<SDValue> Ops;
5506 TLI.LowerAsmOperandForConstraint(InOperandVal, OpInfo.ConstraintCode[0],
5507 hasMemory, Ops, DAG);
5509 report_fatal_error("Invalid operand for inline asm constraint '" +
5510 Twine(OpInfo.ConstraintCode) + "'!");
5512 // Add information to the INLINEASM node to know about this input.
5513 unsigned ResOpType =
5514 InlineAsm::getFlagWord(InlineAsm::Kind_Imm, Ops.size());
5515 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
5516 TLI.getPointerTy()));
5517 AsmNodeOperands.insert(AsmNodeOperands.end(), Ops.begin(), Ops.end());
5521 if (OpInfo.ConstraintType == TargetLowering::C_Memory) {
5522 assert(OpInfo.isIndirect && "Operand must be indirect to be a mem!");
5523 assert(InOperandVal.getValueType() == TLI.getPointerTy() &&
5524 "Memory operands expect pointer values");
5526 // Add information to the INLINEASM node to know about this input.
5527 unsigned ResOpType = InlineAsm::getFlagWord(InlineAsm::Kind_Mem, 1);
5528 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
5529 TLI.getPointerTy()));
5530 AsmNodeOperands.push_back(InOperandVal);
5534 assert((OpInfo.ConstraintType == TargetLowering::C_RegisterClass ||
5535 OpInfo.ConstraintType == TargetLowering::C_Register) &&
5536 "Unknown constraint type!");
5537 assert(!OpInfo.isIndirect &&
5538 "Don't know how to handle indirect register inputs yet!");
5540 // Copy the input into the appropriate registers.
5541 if (OpInfo.AssignedRegs.Regs.empty() ||
5542 !OpInfo.AssignedRegs.areValueTypesLegal())
5543 report_fatal_error("Couldn't allocate input reg for constraint '" +
5544 Twine(OpInfo.ConstraintCode) + "'!");
5546 OpInfo.AssignedRegs.getCopyToRegs(InOperandVal, DAG, getCurDebugLoc(),
5549 OpInfo.AssignedRegs.AddInlineAsmOperands(InlineAsm::Kind_RegUse, false, 0,
5550 DAG, AsmNodeOperands);
5553 case InlineAsm::isClobber: {
5554 // Add the clobbered value to the operand list, so that the register
5555 // allocator is aware that the physreg got clobbered.
5556 if (!OpInfo.AssignedRegs.Regs.empty())
5557 OpInfo.AssignedRegs.AddInlineAsmOperands(
5558 InlineAsm::Kind_RegDefEarlyClobber,
5566 // Finish up input operands. Set the input chain and add the flag last.
5567 AsmNodeOperands[0] = Chain;
5568 if (Flag.getNode()) AsmNodeOperands.push_back(Flag);
5570 Chain = DAG.getNode(ISD::INLINEASM, getCurDebugLoc(),
5571 DAG.getVTList(MVT::Other, MVT::Flag),
5572 &AsmNodeOperands[0], AsmNodeOperands.size());
5573 Flag = Chain.getValue(1);
5575 // If this asm returns a register value, copy the result from that register
5576 // and set it as the value of the call.
5577 if (!RetValRegs.Regs.empty()) {
5578 SDValue Val = RetValRegs.getCopyFromRegs(DAG, getCurDebugLoc(),
5581 // FIXME: Why don't we do this for inline asms with MRVs?
5582 if (CS.getType()->isSingleValueType() && CS.getType()->isSized()) {
5583 EVT ResultType = TLI.getValueType(CS.getType());
5585 // If any of the results of the inline asm is a vector, it may have the
5586 // wrong width/num elts. This can happen for register classes that can
5587 // contain multiple different value types. The preg or vreg allocated may
5588 // not have the same VT as was expected. Convert it to the right type
5589 // with bit_convert.
5590 if (ResultType != Val.getValueType() && Val.getValueType().isVector()) {
5591 Val = DAG.getNode(ISD::BIT_CONVERT, getCurDebugLoc(),
5594 } else if (ResultType != Val.getValueType() &&
5595 ResultType.isInteger() && Val.getValueType().isInteger()) {
5596 // If a result value was tied to an input value, the computed result may
5597 // have a wider width than the expected result. Extract the relevant
5599 Val = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), ResultType, Val);
5602 assert(ResultType == Val.getValueType() && "Asm result value mismatch!");
5605 setValue(CS.getInstruction(), Val);
5606 // Don't need to use this as a chain in this case.
5607 if (!IA->hasSideEffects() && !hasMemory && IndirectStoresToEmit.empty())
5611 std::vector<std::pair<SDValue, const Value *> > StoresToEmit;
5613 // Process indirect outputs, first output all of the flagged copies out of
5615 for (unsigned i = 0, e = IndirectStoresToEmit.size(); i != e; ++i) {
5616 RegsForValue &OutRegs = IndirectStoresToEmit[i].first;
5617 const Value *Ptr = IndirectStoresToEmit[i].second;
5618 SDValue OutVal = OutRegs.getCopyFromRegs(DAG, getCurDebugLoc(),
5620 StoresToEmit.push_back(std::make_pair(OutVal, Ptr));
5623 // Emit the non-flagged stores from the physregs.
5624 SmallVector<SDValue, 8> OutChains;
5625 for (unsigned i = 0, e = StoresToEmit.size(); i != e; ++i) {
5626 SDValue Val = DAG.getStore(Chain, getCurDebugLoc(),
5627 StoresToEmit[i].first,
5628 getValue(StoresToEmit[i].second),
5629 StoresToEmit[i].second, 0,
5631 OutChains.push_back(Val);
5634 if (!OutChains.empty())
5635 Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), MVT::Other,
5636 &OutChains[0], OutChains.size());
5641 void SelectionDAGBuilder::visitVAStart(const CallInst &I) {
5642 DAG.setRoot(DAG.getNode(ISD::VASTART, getCurDebugLoc(),
5643 MVT::Other, getRoot(),
5644 getValue(I.getOperand(1)),
5645 DAG.getSrcValue(I.getOperand(1))));
5648 void SelectionDAGBuilder::visitVAArg(const VAArgInst &I) {
5649 SDValue V = DAG.getVAArg(TLI.getValueType(I.getType()), getCurDebugLoc(),
5650 getRoot(), getValue(I.getOperand(0)),
5651 DAG.getSrcValue(I.getOperand(0)));
5653 DAG.setRoot(V.getValue(1));
5656 void SelectionDAGBuilder::visitVAEnd(const CallInst &I) {
5657 DAG.setRoot(DAG.getNode(ISD::VAEND, getCurDebugLoc(),
5658 MVT::Other, getRoot(),
5659 getValue(I.getOperand(1)),
5660 DAG.getSrcValue(I.getOperand(1))));
5663 void SelectionDAGBuilder::visitVACopy(const CallInst &I) {
5664 DAG.setRoot(DAG.getNode(ISD::VACOPY, getCurDebugLoc(),
5665 MVT::Other, getRoot(),
5666 getValue(I.getOperand(1)),
5667 getValue(I.getOperand(2)),
5668 DAG.getSrcValue(I.getOperand(1)),
5669 DAG.getSrcValue(I.getOperand(2))));
5672 /// TargetLowering::LowerCallTo - This is the default LowerCallTo
5673 /// implementation, which just calls LowerCall.
5674 /// FIXME: When all targets are
5675 /// migrated to using LowerCall, this hook should be integrated into SDISel.
5676 std::pair<SDValue, SDValue>
5677 TargetLowering::LowerCallTo(SDValue Chain, const Type *RetTy,
5678 bool RetSExt, bool RetZExt, bool isVarArg,
5679 bool isInreg, unsigned NumFixedArgs,
5680 CallingConv::ID CallConv, bool isTailCall,
5681 bool isReturnValueUsed,
5683 ArgListTy &Args, SelectionDAG &DAG,
5684 DebugLoc dl) const {
5685 // Handle all of the outgoing arguments.
5686 SmallVector<ISD::OutputArg, 32> Outs;
5687 for (unsigned i = 0, e = Args.size(); i != e; ++i) {
5688 SmallVector<EVT, 4> ValueVTs;
5689 ComputeValueVTs(*this, Args[i].Ty, ValueVTs);
5690 for (unsigned Value = 0, NumValues = ValueVTs.size();
5691 Value != NumValues; ++Value) {
5692 EVT VT = ValueVTs[Value];
5693 const Type *ArgTy = VT.getTypeForEVT(RetTy->getContext());
5694 SDValue Op = SDValue(Args[i].Node.getNode(),
5695 Args[i].Node.getResNo() + Value);
5696 ISD::ArgFlagsTy Flags;
5697 unsigned OriginalAlignment =
5698 getTargetData()->getABITypeAlignment(ArgTy);
5704 if (Args[i].isInReg)
5708 if (Args[i].isByVal) {
5710 const PointerType *Ty = cast<PointerType>(Args[i].Ty);
5711 const Type *ElementTy = Ty->getElementType();
5712 unsigned FrameAlign = getByValTypeAlignment(ElementTy);
5713 unsigned FrameSize = getTargetData()->getTypeAllocSize(ElementTy);
5714 // For ByVal, alignment should come from FE. BE will guess if this
5715 // info is not there but there are cases it cannot get right.
5716 if (Args[i].Alignment)
5717 FrameAlign = Args[i].Alignment;
5718 Flags.setByValAlign(FrameAlign);
5719 Flags.setByValSize(FrameSize);
5723 Flags.setOrigAlign(OriginalAlignment);
5725 EVT PartVT = getRegisterType(RetTy->getContext(), VT);
5726 unsigned NumParts = getNumRegisters(RetTy->getContext(), VT);
5727 SmallVector<SDValue, 4> Parts(NumParts);
5728 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
5731 ExtendKind = ISD::SIGN_EXTEND;
5732 else if (Args[i].isZExt)
5733 ExtendKind = ISD::ZERO_EXTEND;
5735 getCopyToParts(DAG, dl, Op, &Parts[0], NumParts,
5736 PartVT, ExtendKind);
5738 for (unsigned j = 0; j != NumParts; ++j) {
5739 // if it isn't first piece, alignment must be 1
5740 ISD::OutputArg MyFlags(Flags, Parts[j], i < NumFixedArgs);
5741 if (NumParts > 1 && j == 0)
5742 MyFlags.Flags.setSplit();
5744 MyFlags.Flags.setOrigAlign(1);
5746 Outs.push_back(MyFlags);
5751 // Handle the incoming return values from the call.
5752 SmallVector<ISD::InputArg, 32> Ins;
5753 SmallVector<EVT, 4> RetTys;
5754 ComputeValueVTs(*this, RetTy, RetTys);
5755 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
5757 EVT RegisterVT = getRegisterType(RetTy->getContext(), VT);
5758 unsigned NumRegs = getNumRegisters(RetTy->getContext(), VT);
5759 for (unsigned i = 0; i != NumRegs; ++i) {
5760 ISD::InputArg MyFlags;
5761 MyFlags.VT = RegisterVT;
5762 MyFlags.Used = isReturnValueUsed;
5764 MyFlags.Flags.setSExt();
5766 MyFlags.Flags.setZExt();
5768 MyFlags.Flags.setInReg();
5769 Ins.push_back(MyFlags);
5773 SmallVector<SDValue, 4> InVals;
5774 Chain = LowerCall(Chain, Callee, CallConv, isVarArg, isTailCall,
5775 Outs, Ins, dl, DAG, InVals);
5777 // Verify that the target's LowerCall behaved as expected.
5778 assert(Chain.getNode() && Chain.getValueType() == MVT::Other &&
5779 "LowerCall didn't return a valid chain!");
5780 assert((!isTailCall || InVals.empty()) &&
5781 "LowerCall emitted a return value for a tail call!");
5782 assert((isTailCall || InVals.size() == Ins.size()) &&
5783 "LowerCall didn't emit the correct number of values!");
5785 // For a tail call, the return value is merely live-out and there aren't
5786 // any nodes in the DAG representing it. Return a special value to
5787 // indicate that a tail call has been emitted and no more Instructions
5788 // should be processed in the current block.
5791 return std::make_pair(SDValue(), SDValue());
5794 DEBUG(for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
5795 assert(InVals[i].getNode() &&
5796 "LowerCall emitted a null value!");
5797 assert(Ins[i].VT == InVals[i].getValueType() &&
5798 "LowerCall emitted a value with the wrong type!");
5801 // Collect the legal value parts into potentially illegal values
5802 // that correspond to the original function's return values.
5803 ISD::NodeType AssertOp = ISD::DELETED_NODE;
5805 AssertOp = ISD::AssertSext;
5807 AssertOp = ISD::AssertZext;
5808 SmallVector<SDValue, 4> ReturnValues;
5809 unsigned CurReg = 0;
5810 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
5812 EVT RegisterVT = getRegisterType(RetTy->getContext(), VT);
5813 unsigned NumRegs = getNumRegisters(RetTy->getContext(), VT);
5815 ReturnValues.push_back(getCopyFromParts(DAG, dl, &InVals[CurReg],
5816 NumRegs, RegisterVT, VT,
5821 // For a function returning void, there is no return value. We can't create
5822 // such a node, so we just return a null return value in that case. In
5823 // that case, nothing will actualy look at the value.
5824 if (ReturnValues.empty())
5825 return std::make_pair(SDValue(), Chain);
5827 SDValue Res = DAG.getNode(ISD::MERGE_VALUES, dl,
5828 DAG.getVTList(&RetTys[0], RetTys.size()),
5829 &ReturnValues[0], ReturnValues.size());
5830 return std::make_pair(Res, Chain);
5833 void TargetLowering::LowerOperationWrapper(SDNode *N,
5834 SmallVectorImpl<SDValue> &Results,
5835 SelectionDAG &DAG) const {
5836 SDValue Res = LowerOperation(SDValue(N, 0), DAG);
5838 Results.push_back(Res);
5841 SDValue TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
5842 llvm_unreachable("LowerOperation not implemented for this target!");
5847 SelectionDAGBuilder::CopyValueToVirtualRegister(const Value *V, unsigned Reg) {
5848 SDValue Op = getValue(V);
5849 assert((Op.getOpcode() != ISD::CopyFromReg ||
5850 cast<RegisterSDNode>(Op.getOperand(1))->getReg() != Reg) &&
5851 "Copy from a reg to the same reg!");
5852 assert(!TargetRegisterInfo::isPhysicalRegister(Reg) && "Is a physreg");
5854 RegsForValue RFV(V->getContext(), TLI, Reg, V->getType());
5855 SDValue Chain = DAG.getEntryNode();
5856 RFV.getCopyToRegs(Op, DAG, getCurDebugLoc(), Chain, 0);
5857 PendingExports.push_back(Chain);
5860 #include "llvm/CodeGen/SelectionDAGISel.h"
5862 void SelectionDAGISel::LowerArguments(const BasicBlock *LLVMBB) {
5863 // If this is the entry block, emit arguments.
5864 const Function &F = *LLVMBB->getParent();
5865 SelectionDAG &DAG = SDB->DAG;
5866 SDValue OldRoot = DAG.getRoot();
5867 DebugLoc dl = SDB->getCurDebugLoc();
5868 const TargetData *TD = TLI.getTargetData();
5869 SmallVector<ISD::InputArg, 16> Ins;
5871 // Check whether the function can return without sret-demotion.
5872 SmallVector<EVT, 4> OutVTs;
5873 SmallVector<ISD::ArgFlagsTy, 4> OutsFlags;
5874 getReturnInfo(F.getReturnType(), F.getAttributes().getRetAttributes(),
5875 OutVTs, OutsFlags, TLI);
5876 FunctionLoweringInfo &FLI = DAG.getFunctionLoweringInfo();
5878 FLI.CanLowerReturn = TLI.CanLowerReturn(F.getCallingConv(), F.isVarArg(),
5879 OutVTs, OutsFlags, DAG);
5880 if (!FLI.CanLowerReturn) {
5881 // Put in an sret pointer parameter before all the other parameters.
5882 SmallVector<EVT, 1> ValueVTs;
5883 ComputeValueVTs(TLI, PointerType::getUnqual(F.getReturnType()), ValueVTs);
5885 // NOTE: Assuming that a pointer will never break down to more than one VT
5887 ISD::ArgFlagsTy Flags;
5889 EVT RegisterVT = TLI.getRegisterType(*DAG.getContext(), ValueVTs[0]);
5890 ISD::InputArg RetArg(Flags, RegisterVT, true);
5891 Ins.push_back(RetArg);
5894 // Set up the incoming argument description vector.
5896 for (Function::const_arg_iterator I = F.arg_begin(), E = F.arg_end();
5897 I != E; ++I, ++Idx) {
5898 SmallVector<EVT, 4> ValueVTs;
5899 ComputeValueVTs(TLI, I->getType(), ValueVTs);
5900 bool isArgValueUsed = !I->use_empty();
5901 for (unsigned Value = 0, NumValues = ValueVTs.size();
5902 Value != NumValues; ++Value) {
5903 EVT VT = ValueVTs[Value];
5904 const Type *ArgTy = VT.getTypeForEVT(*DAG.getContext());
5905 ISD::ArgFlagsTy Flags;
5906 unsigned OriginalAlignment =
5907 TD->getABITypeAlignment(ArgTy);
5909 if (F.paramHasAttr(Idx, Attribute::ZExt))
5911 if (F.paramHasAttr(Idx, Attribute::SExt))
5913 if (F.paramHasAttr(Idx, Attribute::InReg))
5915 if (F.paramHasAttr(Idx, Attribute::StructRet))
5917 if (F.paramHasAttr(Idx, Attribute::ByVal)) {
5919 const PointerType *Ty = cast<PointerType>(I->getType());
5920 const Type *ElementTy = Ty->getElementType();
5921 unsigned FrameAlign = TLI.getByValTypeAlignment(ElementTy);
5922 unsigned FrameSize = TD->getTypeAllocSize(ElementTy);
5923 // For ByVal, alignment should be passed from FE. BE will guess if
5924 // this info is not there but there are cases it cannot get right.
5925 if (F.getParamAlignment(Idx))
5926 FrameAlign = F.getParamAlignment(Idx);
5927 Flags.setByValAlign(FrameAlign);
5928 Flags.setByValSize(FrameSize);
5930 if (F.paramHasAttr(Idx, Attribute::Nest))
5932 Flags.setOrigAlign(OriginalAlignment);
5934 EVT RegisterVT = TLI.getRegisterType(*CurDAG->getContext(), VT);
5935 unsigned NumRegs = TLI.getNumRegisters(*CurDAG->getContext(), VT);
5936 for (unsigned i = 0; i != NumRegs; ++i) {
5937 ISD::InputArg MyFlags(Flags, RegisterVT, isArgValueUsed);
5938 if (NumRegs > 1 && i == 0)
5939 MyFlags.Flags.setSplit();
5940 // if it isn't first piece, alignment must be 1
5942 MyFlags.Flags.setOrigAlign(1);
5943 Ins.push_back(MyFlags);
5948 // Call the target to set up the argument values.
5949 SmallVector<SDValue, 8> InVals;
5950 SDValue NewRoot = TLI.LowerFormalArguments(DAG.getRoot(), F.getCallingConv(),
5954 // Verify that the target's LowerFormalArguments behaved as expected.
5955 assert(NewRoot.getNode() && NewRoot.getValueType() == MVT::Other &&
5956 "LowerFormalArguments didn't return a valid chain!");
5957 assert(InVals.size() == Ins.size() &&
5958 "LowerFormalArguments didn't emit the correct number of values!");
5960 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
5961 assert(InVals[i].getNode() &&
5962 "LowerFormalArguments emitted a null value!");
5963 assert(Ins[i].VT == InVals[i].getValueType() &&
5964 "LowerFormalArguments emitted a value with the wrong type!");
5968 // Update the DAG with the new chain value resulting from argument lowering.
5969 DAG.setRoot(NewRoot);
5971 // Set up the argument values.
5974 if (!FLI.CanLowerReturn) {
5975 // Create a virtual register for the sret pointer, and put in a copy
5976 // from the sret argument into it.
5977 SmallVector<EVT, 1> ValueVTs;
5978 ComputeValueVTs(TLI, PointerType::getUnqual(F.getReturnType()), ValueVTs);
5979 EVT VT = ValueVTs[0];
5980 EVT RegVT = TLI.getRegisterType(*CurDAG->getContext(), VT);
5981 ISD::NodeType AssertOp = ISD::DELETED_NODE;
5982 SDValue ArgValue = getCopyFromParts(DAG, dl, &InVals[0], 1,
5983 RegVT, VT, AssertOp);
5985 MachineFunction& MF = SDB->DAG.getMachineFunction();
5986 MachineRegisterInfo& RegInfo = MF.getRegInfo();
5987 unsigned SRetReg = RegInfo.createVirtualRegister(TLI.getRegClassFor(RegVT));
5988 FLI.DemoteRegister = SRetReg;
5989 NewRoot = SDB->DAG.getCopyToReg(NewRoot, SDB->getCurDebugLoc(),
5991 DAG.setRoot(NewRoot);
5993 // i indexes lowered arguments. Bump it past the hidden sret argument.
5994 // Idx indexes LLVM arguments. Don't touch it.
5998 for (Function::const_arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E;
6000 SmallVector<SDValue, 4> ArgValues;
6001 SmallVector<EVT, 4> ValueVTs;
6002 ComputeValueVTs(TLI, I->getType(), ValueVTs);
6003 unsigned NumValues = ValueVTs.size();
6004 for (unsigned Value = 0; Value != NumValues; ++Value) {
6005 EVT VT = ValueVTs[Value];
6006 EVT PartVT = TLI.getRegisterType(*CurDAG->getContext(), VT);
6007 unsigned NumParts = TLI.getNumRegisters(*CurDAG->getContext(), VT);
6009 if (!I->use_empty()) {
6010 ISD::NodeType AssertOp = ISD::DELETED_NODE;
6011 if (F.paramHasAttr(Idx, Attribute::SExt))
6012 AssertOp = ISD::AssertSext;
6013 else if (F.paramHasAttr(Idx, Attribute::ZExt))
6014 AssertOp = ISD::AssertZext;
6016 ArgValues.push_back(getCopyFromParts(DAG, dl, &InVals[i],
6017 NumParts, PartVT, VT,
6024 if (!I->use_empty()) {
6026 if (!ArgValues.empty())
6027 Res = DAG.getMergeValues(&ArgValues[0], NumValues,
6028 SDB->getCurDebugLoc());
6029 SDB->setValue(I, Res);
6031 // If this argument is live outside of the entry block, insert a copy from
6032 // whereever we got it to the vreg that other BB's will reference it as.
6033 SDB->CopyToExportRegsIfNeeded(I);
6037 assert(i == InVals.size() && "Argument register count mismatch!");
6039 // Finally, if the target has anything special to do, allow it to do so.
6040 // FIXME: this should insert code into the DAG!
6041 EmitFunctionEntryCode();
6044 /// Handle PHI nodes in successor blocks. Emit code into the SelectionDAG to
6045 /// ensure constants are generated when needed. Remember the virtual registers
6046 /// that need to be added to the Machine PHI nodes as input. We cannot just
6047 /// directly add them, because expansion might result in multiple MBB's for one
6048 /// BB. As such, the start of the BB might correspond to a different MBB than
6052 SelectionDAGBuilder::HandlePHINodesInSuccessorBlocks(const BasicBlock *LLVMBB) {
6053 const TerminatorInst *TI = LLVMBB->getTerminator();
6055 SmallPtrSet<MachineBasicBlock *, 4> SuccsHandled;
6057 // Check successor nodes' PHI nodes that expect a constant to be available
6059 for (unsigned succ = 0, e = TI->getNumSuccessors(); succ != e; ++succ) {
6060 const BasicBlock *SuccBB = TI->getSuccessor(succ);
6061 if (!isa<PHINode>(SuccBB->begin())) continue;
6062 MachineBasicBlock *SuccMBB = FuncInfo.MBBMap[SuccBB];
6064 // If this terminator has multiple identical successors (common for
6065 // switches), only handle each succ once.
6066 if (!SuccsHandled.insert(SuccMBB)) continue;
6068 MachineBasicBlock::iterator MBBI = SuccMBB->begin();
6070 // At this point we know that there is a 1-1 correspondence between LLVM PHI
6071 // nodes and Machine PHI nodes, but the incoming operands have not been
6073 for (BasicBlock::const_iterator I = SuccBB->begin();
6074 const PHINode *PN = dyn_cast<PHINode>(I); ++I) {
6075 // Ignore dead phi's.
6076 if (PN->use_empty()) continue;
6079 const Value *PHIOp = PN->getIncomingValueForBlock(LLVMBB);
6081 if (const Constant *C = dyn_cast<Constant>(PHIOp)) {
6082 unsigned &RegOut = ConstantsOut[C];
6084 RegOut = FuncInfo.CreateRegForValue(C);
6085 CopyValueToVirtualRegister(C, RegOut);
6089 Reg = FuncInfo.ValueMap[PHIOp];
6091 assert(isa<AllocaInst>(PHIOp) &&
6092 FuncInfo.StaticAllocaMap.count(cast<AllocaInst>(PHIOp)) &&
6093 "Didn't codegen value into a register!??");
6094 Reg = FuncInfo.CreateRegForValue(PHIOp);
6095 CopyValueToVirtualRegister(PHIOp, Reg);
6099 // Remember that this register needs to added to the machine PHI node as
6100 // the input for this MBB.
6101 SmallVector<EVT, 4> ValueVTs;
6102 ComputeValueVTs(TLI, PN->getType(), ValueVTs);
6103 for (unsigned vti = 0, vte = ValueVTs.size(); vti != vte; ++vti) {
6104 EVT VT = ValueVTs[vti];
6105 unsigned NumRegisters = TLI.getNumRegisters(*DAG.getContext(), VT);
6106 for (unsigned i = 0, e = NumRegisters; i != e; ++i)
6107 FuncInfo.PHINodesToUpdate.push_back(std::make_pair(MBBI++, Reg+i));
6108 Reg += NumRegisters;
6112 ConstantsOut.clear();