1 //===-- SelectionDAGBuilder.cpp - Selection-DAG building ------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements routines for translating from LLVM IR into SelectionDAG IR.
12 //===----------------------------------------------------------------------===//
14 #include "SelectionDAGBuilder.h"
15 #include "SDNodeDbgValue.h"
16 #include "llvm/ADT/BitVector.h"
17 #include "llvm/ADT/Optional.h"
18 #include "llvm/ADT/SmallSet.h"
19 #include "llvm/ADT/Statistic.h"
20 #include "llvm/Analysis/AliasAnalysis.h"
21 #include "llvm/Analysis/BranchProbabilityInfo.h"
22 #include "llvm/Analysis/ConstantFolding.h"
23 #include "llvm/Analysis/TargetLibraryInfo.h"
24 #include "llvm/Analysis/ValueTracking.h"
25 #include "llvm/CodeGen/FastISel.h"
26 #include "llvm/CodeGen/FunctionLoweringInfo.h"
27 #include "llvm/CodeGen/GCMetadata.h"
28 #include "llvm/CodeGen/GCStrategy.h"
29 #include "llvm/CodeGen/MachineFrameInfo.h"
30 #include "llvm/CodeGen/MachineFunction.h"
31 #include "llvm/CodeGen/MachineInstrBuilder.h"
32 #include "llvm/CodeGen/MachineJumpTableInfo.h"
33 #include "llvm/CodeGen/MachineModuleInfo.h"
34 #include "llvm/CodeGen/MachineRegisterInfo.h"
35 #include "llvm/CodeGen/SelectionDAG.h"
36 #include "llvm/CodeGen/StackMaps.h"
37 #include "llvm/CodeGen/WinEHFuncInfo.h"
38 #include "llvm/IR/CallingConv.h"
39 #include "llvm/IR/Constants.h"
40 #include "llvm/IR/DataLayout.h"
41 #include "llvm/IR/DebugInfo.h"
42 #include "llvm/IR/DerivedTypes.h"
43 #include "llvm/IR/Function.h"
44 #include "llvm/IR/GlobalVariable.h"
45 #include "llvm/IR/InlineAsm.h"
46 #include "llvm/IR/Instructions.h"
47 #include "llvm/IR/IntrinsicInst.h"
48 #include "llvm/IR/Intrinsics.h"
49 #include "llvm/IR/LLVMContext.h"
50 #include "llvm/IR/Module.h"
51 #include "llvm/IR/Statepoint.h"
52 #include "llvm/MC/MCSymbol.h"
53 #include "llvm/Support/CommandLine.h"
54 #include "llvm/Support/Debug.h"
55 #include "llvm/Support/ErrorHandling.h"
56 #include "llvm/Support/MathExtras.h"
57 #include "llvm/Support/raw_ostream.h"
58 #include "llvm/Target/TargetFrameLowering.h"
59 #include "llvm/Target/TargetInstrInfo.h"
60 #include "llvm/Target/TargetIntrinsicInfo.h"
61 #include "llvm/Target/TargetLowering.h"
62 #include "llvm/Target/TargetOptions.h"
63 #include "llvm/Target/TargetSelectionDAGInfo.h"
64 #include "llvm/Target/TargetSubtargetInfo.h"
68 #define DEBUG_TYPE "isel"
70 /// LimitFloatPrecision - Generate low-precision inline sequences for
71 /// some float libcalls (6, 8 or 12 bits).
72 static unsigned LimitFloatPrecision;
74 static cl::opt<unsigned, true>
75 LimitFPPrecision("limit-float-precision",
76 cl::desc("Generate low-precision inline sequences "
77 "for some float libcalls"),
78 cl::location(LimitFloatPrecision),
82 EnableFMFInDAG("enable-fmf-dag", cl::init(false), cl::Hidden,
83 cl::desc("Enable fast-math-flags for DAG nodes"));
85 // Limit the width of DAG chains. This is important in general to prevent
86 // prevent DAG-based analysis from blowing up. For example, alias analysis and
87 // load clustering may not complete in reasonable time. It is difficult to
88 // recognize and avoid this situation within each individual analysis, and
89 // future analyses are likely to have the same behavior. Limiting DAG width is
90 // the safe approach, and will be especially important with global DAGs.
92 // MaxParallelChains default is arbitrarily high to avoid affecting
93 // optimization, but could be lowered to improve compile time. Any ld-ld-st-st
94 // sequence over this should have been converted to llvm.memcpy by the
95 // frontend. It easy to induce this behavior with .ll code such as:
96 // %buffer = alloca [4096 x i8]
97 // %data = load [4096 x i8]* %argPtr
98 // store [4096 x i8] %data, [4096 x i8]* %buffer
99 static const unsigned MaxParallelChains = 64;
101 static SDValue getCopyFromPartsVector(SelectionDAG &DAG, SDLoc DL,
102 const SDValue *Parts, unsigned NumParts,
103 MVT PartVT, EVT ValueVT, const Value *V);
105 /// getCopyFromParts - Create a value that contains the specified legal parts
106 /// combined into the value they represent. If the parts combine to a type
107 /// larger then ValueVT then AssertOp can be used to specify whether the extra
108 /// bits are known to be zero (ISD::AssertZext) or sign extended from ValueVT
109 /// (ISD::AssertSext).
110 static SDValue getCopyFromParts(SelectionDAG &DAG, SDLoc DL,
111 const SDValue *Parts,
112 unsigned NumParts, MVT PartVT, EVT ValueVT,
114 ISD::NodeType AssertOp = ISD::DELETED_NODE) {
115 if (ValueVT.isVector())
116 return getCopyFromPartsVector(DAG, DL, Parts, NumParts,
119 assert(NumParts > 0 && "No parts to assemble!");
120 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
121 SDValue Val = Parts[0];
124 // Assemble the value from multiple parts.
125 if (ValueVT.isInteger()) {
126 unsigned PartBits = PartVT.getSizeInBits();
127 unsigned ValueBits = ValueVT.getSizeInBits();
129 // Assemble the power of 2 part.
130 unsigned RoundParts = NumParts & (NumParts - 1) ?
131 1 << Log2_32(NumParts) : NumParts;
132 unsigned RoundBits = PartBits * RoundParts;
133 EVT RoundVT = RoundBits == ValueBits ?
134 ValueVT : EVT::getIntegerVT(*DAG.getContext(), RoundBits);
137 EVT HalfVT = EVT::getIntegerVT(*DAG.getContext(), RoundBits/2);
139 if (RoundParts > 2) {
140 Lo = getCopyFromParts(DAG, DL, Parts, RoundParts / 2,
142 Hi = getCopyFromParts(DAG, DL, Parts + RoundParts / 2,
143 RoundParts / 2, PartVT, HalfVT, V);
145 Lo = DAG.getNode(ISD::BITCAST, DL, HalfVT, Parts[0]);
146 Hi = DAG.getNode(ISD::BITCAST, DL, HalfVT, Parts[1]);
149 if (TLI.isBigEndian())
152 Val = DAG.getNode(ISD::BUILD_PAIR, DL, RoundVT, Lo, Hi);
154 if (RoundParts < NumParts) {
155 // Assemble the trailing non-power-of-2 part.
156 unsigned OddParts = NumParts - RoundParts;
157 EVT OddVT = EVT::getIntegerVT(*DAG.getContext(), OddParts * PartBits);
158 Hi = getCopyFromParts(DAG, DL,
159 Parts + RoundParts, OddParts, PartVT, OddVT, V);
161 // Combine the round and odd parts.
163 if (TLI.isBigEndian())
165 EVT TotalVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
166 Hi = DAG.getNode(ISD::ANY_EXTEND, DL, TotalVT, Hi);
167 Hi = DAG.getNode(ISD::SHL, DL, TotalVT, Hi,
168 DAG.getConstant(Lo.getValueType().getSizeInBits(), DL,
169 TLI.getPointerTy()));
170 Lo = DAG.getNode(ISD::ZERO_EXTEND, DL, TotalVT, Lo);
171 Val = DAG.getNode(ISD::OR, DL, TotalVT, Lo, Hi);
173 } else if (PartVT.isFloatingPoint()) {
174 // FP split into multiple FP parts (for ppcf128)
175 assert(ValueVT == EVT(MVT::ppcf128) && PartVT == MVT::f64 &&
178 Lo = DAG.getNode(ISD::BITCAST, DL, EVT(MVT::f64), Parts[0]);
179 Hi = DAG.getNode(ISD::BITCAST, DL, EVT(MVT::f64), Parts[1]);
180 if (TLI.hasBigEndianPartOrdering(ValueVT))
182 Val = DAG.getNode(ISD::BUILD_PAIR, DL, ValueVT, Lo, Hi);
184 // FP split into integer parts (soft fp)
185 assert(ValueVT.isFloatingPoint() && PartVT.isInteger() &&
186 !PartVT.isVector() && "Unexpected split");
187 EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), ValueVT.getSizeInBits());
188 Val = getCopyFromParts(DAG, DL, Parts, NumParts, PartVT, IntVT, V);
192 // There is now one part, held in Val. Correct it to match ValueVT.
193 EVT PartEVT = Val.getValueType();
195 if (PartEVT == ValueVT)
198 if (PartEVT.isInteger() && ValueVT.isInteger()) {
199 if (ValueVT.bitsLT(PartEVT)) {
200 // For a truncate, see if we have any information to
201 // indicate whether the truncated bits will always be
202 // zero or sign-extension.
203 if (AssertOp != ISD::DELETED_NODE)
204 Val = DAG.getNode(AssertOp, DL, PartEVT, Val,
205 DAG.getValueType(ValueVT));
206 return DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val);
208 return DAG.getNode(ISD::ANY_EXTEND, DL, ValueVT, Val);
211 if (PartEVT.isFloatingPoint() && ValueVT.isFloatingPoint()) {
212 // FP_ROUND's are always exact here.
213 if (ValueVT.bitsLT(Val.getValueType()))
214 return DAG.getNode(ISD::FP_ROUND, DL, ValueVT, Val,
215 DAG.getTargetConstant(1, DL, TLI.getPointerTy()));
217 return DAG.getNode(ISD::FP_EXTEND, DL, ValueVT, Val);
220 if (PartEVT.getSizeInBits() == ValueVT.getSizeInBits())
221 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val);
223 llvm_unreachable("Unknown mismatch!");
226 static void diagnosePossiblyInvalidConstraint(LLVMContext &Ctx, const Value *V,
227 const Twine &ErrMsg) {
228 const Instruction *I = dyn_cast_or_null<Instruction>(V);
230 return Ctx.emitError(ErrMsg);
232 const char *AsmError = ", possible invalid constraint for vector type";
233 if (const CallInst *CI = dyn_cast<CallInst>(I))
234 if (isa<InlineAsm>(CI->getCalledValue()))
235 return Ctx.emitError(I, ErrMsg + AsmError);
237 return Ctx.emitError(I, ErrMsg);
240 /// getCopyFromPartsVector - Create a value that contains the specified legal
241 /// parts combined into the value they represent. If the parts combine to a
242 /// type larger then ValueVT then AssertOp can be used to specify whether the
243 /// extra bits are known to be zero (ISD::AssertZext) or sign extended from
244 /// ValueVT (ISD::AssertSext).
245 static SDValue getCopyFromPartsVector(SelectionDAG &DAG, SDLoc DL,
246 const SDValue *Parts, unsigned NumParts,
247 MVT PartVT, EVT ValueVT, const Value *V) {
248 assert(ValueVT.isVector() && "Not a vector value");
249 assert(NumParts > 0 && "No parts to assemble!");
250 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
251 SDValue Val = Parts[0];
253 // Handle a multi-element vector.
257 unsigned NumIntermediates;
259 TLI.getVectorTypeBreakdown(*DAG.getContext(), ValueVT, IntermediateVT,
260 NumIntermediates, RegisterVT);
261 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!");
262 NumParts = NumRegs; // Silence a compiler warning.
263 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!");
264 assert(RegisterVT == Parts[0].getSimpleValueType() &&
265 "Part type doesn't match part!");
267 // Assemble the parts into intermediate operands.
268 SmallVector<SDValue, 8> Ops(NumIntermediates);
269 if (NumIntermediates == NumParts) {
270 // If the register was not expanded, truncate or copy the value,
272 for (unsigned i = 0; i != NumParts; ++i)
273 Ops[i] = getCopyFromParts(DAG, DL, &Parts[i], 1,
274 PartVT, IntermediateVT, V);
275 } else if (NumParts > 0) {
276 // If the intermediate type was expanded, build the intermediate
277 // operands from the parts.
278 assert(NumParts % NumIntermediates == 0 &&
279 "Must expand into a divisible number of parts!");
280 unsigned Factor = NumParts / NumIntermediates;
281 for (unsigned i = 0; i != NumIntermediates; ++i)
282 Ops[i] = getCopyFromParts(DAG, DL, &Parts[i * Factor], Factor,
283 PartVT, IntermediateVT, V);
286 // Build a vector with BUILD_VECTOR or CONCAT_VECTORS from the
287 // intermediate operands.
288 Val = DAG.getNode(IntermediateVT.isVector() ? ISD::CONCAT_VECTORS
293 // There is now one part, held in Val. Correct it to match ValueVT.
294 EVT PartEVT = Val.getValueType();
296 if (PartEVT == ValueVT)
299 if (PartEVT.isVector()) {
300 // If the element type of the source/dest vectors are the same, but the
301 // parts vector has more elements than the value vector, then we have a
302 // vector widening case (e.g. <2 x float> -> <4 x float>). Extract the
304 if (PartEVT.getVectorElementType() == ValueVT.getVectorElementType()) {
305 assert(PartEVT.getVectorNumElements() > ValueVT.getVectorNumElements() &&
306 "Cannot narrow, it would be a lossy transformation");
307 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, ValueVT, Val,
308 DAG.getConstant(0, DL, TLI.getVectorIdxTy()));
311 // Vector/Vector bitcast.
312 if (ValueVT.getSizeInBits() == PartEVT.getSizeInBits())
313 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val);
315 assert(PartEVT.getVectorNumElements() == ValueVT.getVectorNumElements() &&
316 "Cannot handle this kind of promotion");
317 // Promoted vector extract
318 bool Smaller = ValueVT.bitsLE(PartEVT);
319 return DAG.getNode((Smaller ? ISD::TRUNCATE : ISD::ANY_EXTEND),
324 // Trivial bitcast if the types are the same size and the destination
325 // vector type is legal.
326 if (PartEVT.getSizeInBits() == ValueVT.getSizeInBits() &&
327 TLI.isTypeLegal(ValueVT))
328 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val);
330 // Handle cases such as i8 -> <1 x i1>
331 if (ValueVT.getVectorNumElements() != 1) {
332 diagnosePossiblyInvalidConstraint(*DAG.getContext(), V,
333 "non-trivial scalar-to-vector conversion");
334 return DAG.getUNDEF(ValueVT);
337 if (ValueVT.getVectorNumElements() == 1 &&
338 ValueVT.getVectorElementType() != PartEVT) {
339 bool Smaller = ValueVT.bitsLE(PartEVT);
340 Val = DAG.getNode((Smaller ? ISD::TRUNCATE : ISD::ANY_EXTEND),
341 DL, ValueVT.getScalarType(), Val);
344 return DAG.getNode(ISD::BUILD_VECTOR, DL, ValueVT, Val);
347 static void getCopyToPartsVector(SelectionDAG &DAG, SDLoc dl,
348 SDValue Val, SDValue *Parts, unsigned NumParts,
349 MVT PartVT, const Value *V);
351 /// getCopyToParts - Create a series of nodes that contain the specified value
352 /// split into legal parts. If the parts contain more bits than Val, then, for
353 /// integers, ExtendKind can be used to specify how to generate the extra bits.
354 static void getCopyToParts(SelectionDAG &DAG, SDLoc DL,
355 SDValue Val, SDValue *Parts, unsigned NumParts,
356 MVT PartVT, const Value *V,
357 ISD::NodeType ExtendKind = ISD::ANY_EXTEND) {
358 EVT ValueVT = Val.getValueType();
360 // Handle the vector case separately.
361 if (ValueVT.isVector())
362 return getCopyToPartsVector(DAG, DL, Val, Parts, NumParts, PartVT, V);
364 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
365 unsigned PartBits = PartVT.getSizeInBits();
366 unsigned OrigNumParts = NumParts;
367 assert(TLI.isTypeLegal(PartVT) && "Copying to an illegal type!");
372 assert(!ValueVT.isVector() && "Vector case handled elsewhere");
373 EVT PartEVT = PartVT;
374 if (PartEVT == ValueVT) {
375 assert(NumParts == 1 && "No-op copy with multiple parts!");
380 if (NumParts * PartBits > ValueVT.getSizeInBits()) {
381 // If the parts cover more bits than the value has, promote the value.
382 if (PartVT.isFloatingPoint() && ValueVT.isFloatingPoint()) {
383 assert(NumParts == 1 && "Do not know what to promote to!");
384 Val = DAG.getNode(ISD::FP_EXTEND, DL, PartVT, Val);
386 assert((PartVT.isInteger() || PartVT == MVT::x86mmx) &&
387 ValueVT.isInteger() &&
388 "Unknown mismatch!");
389 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
390 Val = DAG.getNode(ExtendKind, DL, ValueVT, Val);
391 if (PartVT == MVT::x86mmx)
392 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
394 } else if (PartBits == ValueVT.getSizeInBits()) {
395 // Different types of the same size.
396 assert(NumParts == 1 && PartEVT != ValueVT);
397 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
398 } else if (NumParts * PartBits < ValueVT.getSizeInBits()) {
399 // If the parts cover less bits than value has, truncate the value.
400 assert((PartVT.isInteger() || PartVT == MVT::x86mmx) &&
401 ValueVT.isInteger() &&
402 "Unknown mismatch!");
403 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
404 Val = DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val);
405 if (PartVT == MVT::x86mmx)
406 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
409 // The value may have changed - recompute ValueVT.
410 ValueVT = Val.getValueType();
411 assert(NumParts * PartBits == ValueVT.getSizeInBits() &&
412 "Failed to tile the value with PartVT!");
415 if (PartEVT != ValueVT)
416 diagnosePossiblyInvalidConstraint(*DAG.getContext(), V,
417 "scalar-to-vector conversion failed");
423 // Expand the value into multiple parts.
424 if (NumParts & (NumParts - 1)) {
425 // The number of parts is not a power of 2. Split off and copy the tail.
426 assert(PartVT.isInteger() && ValueVT.isInteger() &&
427 "Do not know what to expand to!");
428 unsigned RoundParts = 1 << Log2_32(NumParts);
429 unsigned RoundBits = RoundParts * PartBits;
430 unsigned OddParts = NumParts - RoundParts;
431 SDValue OddVal = DAG.getNode(ISD::SRL, DL, ValueVT, Val,
432 DAG.getIntPtrConstant(RoundBits, DL));
433 getCopyToParts(DAG, DL, OddVal, Parts + RoundParts, OddParts, PartVT, V);
435 if (TLI.isBigEndian())
436 // The odd parts were reversed by getCopyToParts - unreverse them.
437 std::reverse(Parts + RoundParts, Parts + NumParts);
439 NumParts = RoundParts;
440 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
441 Val = DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val);
444 // The number of parts is a power of 2. Repeatedly bisect the value using
446 Parts[0] = DAG.getNode(ISD::BITCAST, DL,
447 EVT::getIntegerVT(*DAG.getContext(),
448 ValueVT.getSizeInBits()),
451 for (unsigned StepSize = NumParts; StepSize > 1; StepSize /= 2) {
452 for (unsigned i = 0; i < NumParts; i += StepSize) {
453 unsigned ThisBits = StepSize * PartBits / 2;
454 EVT ThisVT = EVT::getIntegerVT(*DAG.getContext(), ThisBits);
455 SDValue &Part0 = Parts[i];
456 SDValue &Part1 = Parts[i+StepSize/2];
458 Part1 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL,
459 ThisVT, Part0, DAG.getIntPtrConstant(1, DL));
460 Part0 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL,
461 ThisVT, Part0, DAG.getIntPtrConstant(0, DL));
463 if (ThisBits == PartBits && ThisVT != PartVT) {
464 Part0 = DAG.getNode(ISD::BITCAST, DL, PartVT, Part0);
465 Part1 = DAG.getNode(ISD::BITCAST, DL, PartVT, Part1);
470 if (TLI.isBigEndian())
471 std::reverse(Parts, Parts + OrigNumParts);
475 /// getCopyToPartsVector - Create a series of nodes that contain the specified
476 /// value split into legal parts.
477 static void getCopyToPartsVector(SelectionDAG &DAG, SDLoc DL,
478 SDValue Val, SDValue *Parts, unsigned NumParts,
479 MVT PartVT, const Value *V) {
480 EVT ValueVT = Val.getValueType();
481 assert(ValueVT.isVector() && "Not a vector");
482 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
485 EVT PartEVT = PartVT;
486 if (PartEVT == ValueVT) {
488 } else if (PartVT.getSizeInBits() == ValueVT.getSizeInBits()) {
489 // Bitconvert vector->vector case.
490 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
491 } else if (PartVT.isVector() &&
492 PartEVT.getVectorElementType() == ValueVT.getVectorElementType() &&
493 PartEVT.getVectorNumElements() > ValueVT.getVectorNumElements()) {
494 EVT ElementVT = PartVT.getVectorElementType();
495 // Vector widening case, e.g. <2 x float> -> <4 x float>. Shuffle in
497 SmallVector<SDValue, 16> Ops;
498 for (unsigned i = 0, e = ValueVT.getVectorNumElements(); i != e; ++i)
499 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL,
500 ElementVT, Val, DAG.getConstant(i, DL,
501 TLI.getVectorIdxTy())));
503 for (unsigned i = ValueVT.getVectorNumElements(),
504 e = PartVT.getVectorNumElements(); i != e; ++i)
505 Ops.push_back(DAG.getUNDEF(ElementVT));
507 Val = DAG.getNode(ISD::BUILD_VECTOR, DL, PartVT, Ops);
509 // FIXME: Use CONCAT for 2x -> 4x.
511 //SDValue UndefElts = DAG.getUNDEF(VectorTy);
512 //Val = DAG.getNode(ISD::CONCAT_VECTORS, DL, PartVT, Val, UndefElts);
513 } else if (PartVT.isVector() &&
514 PartEVT.getVectorElementType().bitsGE(
515 ValueVT.getVectorElementType()) &&
516 PartEVT.getVectorNumElements() == ValueVT.getVectorNumElements()) {
518 // Promoted vector extract
519 bool Smaller = PartEVT.bitsLE(ValueVT);
520 Val = DAG.getNode((Smaller ? ISD::TRUNCATE : ISD::ANY_EXTEND),
523 // Vector -> scalar conversion.
524 assert(ValueVT.getVectorNumElements() == 1 &&
525 "Only trivial vector-to-scalar conversions should get here!");
526 Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL,
528 DAG.getConstant(0, DL, TLI.getVectorIdxTy()));
530 bool Smaller = ValueVT.bitsLE(PartVT);
531 Val = DAG.getNode((Smaller ? ISD::TRUNCATE : ISD::ANY_EXTEND),
539 // Handle a multi-element vector.
542 unsigned NumIntermediates;
543 unsigned NumRegs = TLI.getVectorTypeBreakdown(*DAG.getContext(), ValueVT,
545 NumIntermediates, RegisterVT);
546 unsigned NumElements = ValueVT.getVectorNumElements();
548 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!");
549 NumParts = NumRegs; // Silence a compiler warning.
550 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!");
552 // Split the vector into intermediate operands.
553 SmallVector<SDValue, 8> Ops(NumIntermediates);
554 for (unsigned i = 0; i != NumIntermediates; ++i) {
555 if (IntermediateVT.isVector())
556 Ops[i] = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL,
558 DAG.getConstant(i * (NumElements / NumIntermediates), DL,
559 TLI.getVectorIdxTy()));
561 Ops[i] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL,
563 DAG.getConstant(i, DL, TLI.getVectorIdxTy()));
566 // Split the intermediate operands into legal parts.
567 if (NumParts == NumIntermediates) {
568 // If the register was not expanded, promote or copy the value,
570 for (unsigned i = 0; i != NumParts; ++i)
571 getCopyToParts(DAG, DL, Ops[i], &Parts[i], 1, PartVT, V);
572 } else if (NumParts > 0) {
573 // If the intermediate type was expanded, split each the value into
575 assert(NumIntermediates != 0 && "division by zero");
576 assert(NumParts % NumIntermediates == 0 &&
577 "Must expand into a divisible number of parts!");
578 unsigned Factor = NumParts / NumIntermediates;
579 for (unsigned i = 0; i != NumIntermediates; ++i)
580 getCopyToParts(DAG, DL, Ops[i], &Parts[i*Factor], Factor, PartVT, V);
584 RegsForValue::RegsForValue() {}
586 RegsForValue::RegsForValue(const SmallVector<unsigned, 4> ®s, MVT regvt,
588 : ValueVTs(1, valuevt), RegVTs(1, regvt), Regs(regs) {}
590 RegsForValue::RegsForValue(LLVMContext &Context, const TargetLowering &tli,
591 unsigned Reg, Type *Ty) {
592 ComputeValueVTs(tli, Ty, ValueVTs);
594 for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) {
595 EVT ValueVT = ValueVTs[Value];
596 unsigned NumRegs = tli.getNumRegisters(Context, ValueVT);
597 MVT RegisterVT = tli.getRegisterType(Context, ValueVT);
598 for (unsigned i = 0; i != NumRegs; ++i)
599 Regs.push_back(Reg + i);
600 RegVTs.push_back(RegisterVT);
605 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from
606 /// this value and returns the result as a ValueVT value. This uses
607 /// Chain/Flag as the input and updates them for the output Chain/Flag.
608 /// If the Flag pointer is NULL, no flag is used.
609 SDValue RegsForValue::getCopyFromRegs(SelectionDAG &DAG,
610 FunctionLoweringInfo &FuncInfo,
612 SDValue &Chain, SDValue *Flag,
613 const Value *V) const {
614 // A Value with type {} or [0 x %t] needs no registers.
615 if (ValueVTs.empty())
618 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
620 // Assemble the legal parts into the final values.
621 SmallVector<SDValue, 4> Values(ValueVTs.size());
622 SmallVector<SDValue, 8> Parts;
623 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) {
624 // Copy the legal parts from the registers.
625 EVT ValueVT = ValueVTs[Value];
626 unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), ValueVT);
627 MVT RegisterVT = RegVTs[Value];
629 Parts.resize(NumRegs);
630 for (unsigned i = 0; i != NumRegs; ++i) {
633 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT);
635 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT, *Flag);
636 *Flag = P.getValue(2);
639 Chain = P.getValue(1);
642 // If the source register was virtual and if we know something about it,
643 // add an assert node.
644 if (!TargetRegisterInfo::isVirtualRegister(Regs[Part+i]) ||
645 !RegisterVT.isInteger() || RegisterVT.isVector())
648 const FunctionLoweringInfo::LiveOutInfo *LOI =
649 FuncInfo.GetLiveOutRegInfo(Regs[Part+i]);
653 unsigned RegSize = RegisterVT.getSizeInBits();
654 unsigned NumSignBits = LOI->NumSignBits;
655 unsigned NumZeroBits = LOI->KnownZero.countLeadingOnes();
657 if (NumZeroBits == RegSize) {
658 // The current value is a zero.
659 // Explicitly express that as it would be easier for
660 // optimizations to kick in.
661 Parts[i] = DAG.getConstant(0, dl, RegisterVT);
665 // FIXME: We capture more information than the dag can represent. For
666 // now, just use the tightest assertzext/assertsext possible.
668 EVT FromVT(MVT::Other);
669 if (NumSignBits == RegSize)
670 isSExt = true, FromVT = MVT::i1; // ASSERT SEXT 1
671 else if (NumZeroBits >= RegSize-1)
672 isSExt = false, FromVT = MVT::i1; // ASSERT ZEXT 1
673 else if (NumSignBits > RegSize-8)
674 isSExt = true, FromVT = MVT::i8; // ASSERT SEXT 8
675 else if (NumZeroBits >= RegSize-8)
676 isSExt = false, FromVT = MVT::i8; // ASSERT ZEXT 8
677 else if (NumSignBits > RegSize-16)
678 isSExt = true, FromVT = MVT::i16; // ASSERT SEXT 16
679 else if (NumZeroBits >= RegSize-16)
680 isSExt = false, FromVT = MVT::i16; // ASSERT ZEXT 16
681 else if (NumSignBits > RegSize-32)
682 isSExt = true, FromVT = MVT::i32; // ASSERT SEXT 32
683 else if (NumZeroBits >= RegSize-32)
684 isSExt = false, FromVT = MVT::i32; // ASSERT ZEXT 32
688 // Add an assertion node.
689 assert(FromVT != MVT::Other);
690 Parts[i] = DAG.getNode(isSExt ? ISD::AssertSext : ISD::AssertZext, dl,
691 RegisterVT, P, DAG.getValueType(FromVT));
694 Values[Value] = getCopyFromParts(DAG, dl, Parts.begin(),
695 NumRegs, RegisterVT, ValueVT, V);
700 return DAG.getNode(ISD::MERGE_VALUES, dl, DAG.getVTList(ValueVTs), Values);
703 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
704 /// specified value into the registers specified by this object. This uses
705 /// Chain/Flag as the input and updates them for the output Chain/Flag.
706 /// If the Flag pointer is NULL, no flag is used.
707 void RegsForValue::getCopyToRegs(SDValue Val, SelectionDAG &DAG, SDLoc dl,
708 SDValue &Chain, SDValue *Flag, const Value *V,
709 ISD::NodeType PreferredExtendType) const {
710 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
711 ISD::NodeType ExtendKind = PreferredExtendType;
713 // Get the list of the values's legal parts.
714 unsigned NumRegs = Regs.size();
715 SmallVector<SDValue, 8> Parts(NumRegs);
716 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) {
717 EVT ValueVT = ValueVTs[Value];
718 unsigned NumParts = TLI.getNumRegisters(*DAG.getContext(), ValueVT);
719 MVT RegisterVT = RegVTs[Value];
721 if (ExtendKind == ISD::ANY_EXTEND && TLI.isZExtFree(Val, RegisterVT))
722 ExtendKind = ISD::ZERO_EXTEND;
724 getCopyToParts(DAG, dl, Val.getValue(Val.getResNo() + Value),
725 &Parts[Part], NumParts, RegisterVT, V, ExtendKind);
729 // Copy the parts into the registers.
730 SmallVector<SDValue, 8> Chains(NumRegs);
731 for (unsigned i = 0; i != NumRegs; ++i) {
734 Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i]);
736 Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i], *Flag);
737 *Flag = Part.getValue(1);
740 Chains[i] = Part.getValue(0);
743 if (NumRegs == 1 || Flag)
744 // If NumRegs > 1 && Flag is used then the use of the last CopyToReg is
745 // flagged to it. That is the CopyToReg nodes and the user are considered
746 // a single scheduling unit. If we create a TokenFactor and return it as
747 // chain, then the TokenFactor is both a predecessor (operand) of the
748 // user as well as a successor (the TF operands are flagged to the user).
749 // c1, f1 = CopyToReg
750 // c2, f2 = CopyToReg
751 // c3 = TokenFactor c1, c2
754 Chain = Chains[NumRegs-1];
756 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Chains);
759 /// AddInlineAsmOperands - Add this value to the specified inlineasm node
760 /// operand list. This adds the code marker and includes the number of
761 /// values added into it.
762 void RegsForValue::AddInlineAsmOperands(unsigned Code, bool HasMatching,
763 unsigned MatchingIdx, SDLoc dl,
765 std::vector<SDValue> &Ops) const {
766 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
768 unsigned Flag = InlineAsm::getFlagWord(Code, Regs.size());
770 Flag = InlineAsm::getFlagWordForMatchingOp(Flag, MatchingIdx);
771 else if (!Regs.empty() &&
772 TargetRegisterInfo::isVirtualRegister(Regs.front())) {
773 // Put the register class of the virtual registers in the flag word. That
774 // way, later passes can recompute register class constraints for inline
775 // assembly as well as normal instructions.
776 // Don't do this for tied operands that can use the regclass information
778 const MachineRegisterInfo &MRI = DAG.getMachineFunction().getRegInfo();
779 const TargetRegisterClass *RC = MRI.getRegClass(Regs.front());
780 Flag = InlineAsm::getFlagWordForRegClass(Flag, RC->getID());
783 SDValue Res = DAG.getTargetConstant(Flag, dl, MVT::i32);
786 unsigned SP = TLI.getStackPointerRegisterToSaveRestore();
787 for (unsigned Value = 0, Reg = 0, e = ValueVTs.size(); Value != e; ++Value) {
788 unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), ValueVTs[Value]);
789 MVT RegisterVT = RegVTs[Value];
790 for (unsigned i = 0; i != NumRegs; ++i) {
791 assert(Reg < Regs.size() && "Mismatch in # registers expected");
792 unsigned TheReg = Regs[Reg++];
793 Ops.push_back(DAG.getRegister(TheReg, RegisterVT));
795 if (TheReg == SP && Code == InlineAsm::Kind_Clobber) {
796 // If we clobbered the stack pointer, MFI should know about it.
797 assert(DAG.getMachineFunction().getFrameInfo()->
798 hasInlineAsmWithSPAdjust());
804 void SelectionDAGBuilder::init(GCFunctionInfo *gfi, AliasAnalysis &aa,
805 const TargetLibraryInfo *li) {
809 DL = DAG.getTarget().getDataLayout();
810 Context = DAG.getContext();
811 LPadToCallSiteMap.clear();
814 /// clear - Clear out the current SelectionDAG and the associated
815 /// state and prepare this SelectionDAGBuilder object to be used
816 /// for a new block. This doesn't clear out information about
817 /// additional blocks that are needed to complete switch lowering
818 /// or PHI node updating; that information is cleared out as it is
820 void SelectionDAGBuilder::clear() {
822 UnusedArgNodeMap.clear();
823 PendingLoads.clear();
824 PendingExports.clear();
827 SDNodeOrder = LowestSDNodeOrder;
828 StatepointLowering.clear();
831 /// clearDanglingDebugInfo - Clear the dangling debug information
832 /// map. This function is separated from the clear so that debug
833 /// information that is dangling in a basic block can be properly
834 /// resolved in a different basic block. This allows the
835 /// SelectionDAG to resolve dangling debug information attached
837 void SelectionDAGBuilder::clearDanglingDebugInfo() {
838 DanglingDebugInfoMap.clear();
841 /// getRoot - Return the current virtual root of the Selection DAG,
842 /// flushing any PendingLoad items. This must be done before emitting
843 /// a store or any other node that may need to be ordered after any
844 /// prior load instructions.
846 SDValue SelectionDAGBuilder::getRoot() {
847 if (PendingLoads.empty())
848 return DAG.getRoot();
850 if (PendingLoads.size() == 1) {
851 SDValue Root = PendingLoads[0];
853 PendingLoads.clear();
857 // Otherwise, we have to make a token factor node.
858 SDValue Root = DAG.getNode(ISD::TokenFactor, getCurSDLoc(), MVT::Other,
860 PendingLoads.clear();
865 /// getControlRoot - Similar to getRoot, but instead of flushing all the
866 /// PendingLoad items, flush all the PendingExports items. It is necessary
867 /// to do this before emitting a terminator instruction.
869 SDValue SelectionDAGBuilder::getControlRoot() {
870 SDValue Root = DAG.getRoot();
872 if (PendingExports.empty())
875 // Turn all of the CopyToReg chains into one factored node.
876 if (Root.getOpcode() != ISD::EntryToken) {
877 unsigned i = 0, e = PendingExports.size();
878 for (; i != e; ++i) {
879 assert(PendingExports[i].getNode()->getNumOperands() > 1);
880 if (PendingExports[i].getNode()->getOperand(0) == Root)
881 break; // Don't add the root if we already indirectly depend on it.
885 PendingExports.push_back(Root);
888 Root = DAG.getNode(ISD::TokenFactor, getCurSDLoc(), MVT::Other,
890 PendingExports.clear();
895 void SelectionDAGBuilder::visit(const Instruction &I) {
896 // Set up outgoing PHI node register values before emitting the terminator.
897 if (isa<TerminatorInst>(&I))
898 HandlePHINodesInSuccessorBlocks(I.getParent());
904 visit(I.getOpcode(), I);
906 if (!isa<TerminatorInst>(&I) && !HasTailCall)
907 CopyToExportRegsIfNeeded(&I);
912 void SelectionDAGBuilder::visitPHI(const PHINode &) {
913 llvm_unreachable("SelectionDAGBuilder shouldn't visit PHI nodes!");
916 void SelectionDAGBuilder::visit(unsigned Opcode, const User &I) {
917 // Note: this doesn't use InstVisitor, because it has to work with
918 // ConstantExpr's in addition to instructions.
920 default: llvm_unreachable("Unknown instruction type encountered!");
921 // Build the switch statement using the Instruction.def file.
922 #define HANDLE_INST(NUM, OPCODE, CLASS) \
923 case Instruction::OPCODE: visit##OPCODE((const CLASS&)I); break;
924 #include "llvm/IR/Instruction.def"
928 // resolveDanglingDebugInfo - if we saw an earlier dbg_value referring to V,
929 // generate the debug data structures now that we've seen its definition.
930 void SelectionDAGBuilder::resolveDanglingDebugInfo(const Value *V,
932 DanglingDebugInfo &DDI = DanglingDebugInfoMap[V];
934 const DbgValueInst *DI = DDI.getDI();
935 DebugLoc dl = DDI.getdl();
936 unsigned DbgSDNodeOrder = DDI.getSDNodeOrder();
937 DILocalVariable *Variable = DI->getVariable();
938 DIExpression *Expr = DI->getExpression();
939 assert(Variable->isValidLocationForIntrinsic(dl) &&
940 "Expected inlined-at fields to agree");
941 uint64_t Offset = DI->getOffset();
942 // A dbg.value for an alloca is always indirect.
943 bool IsIndirect = isa<AllocaInst>(V) || Offset != 0;
946 if (!EmitFuncArgumentDbgValue(V, Variable, Expr, dl, Offset, IsIndirect,
948 SDV = DAG.getDbgValue(Variable, Expr, Val.getNode(), Val.getResNo(),
949 IsIndirect, Offset, dl, DbgSDNodeOrder);
950 DAG.AddDbgValue(SDV, Val.getNode(), false);
953 DEBUG(dbgs() << "Dropping debug info for " << *DI << "\n");
954 DanglingDebugInfoMap[V] = DanglingDebugInfo();
958 /// getCopyFromRegs - If there was virtual register allocated for the value V
959 /// emit CopyFromReg of the specified type Ty. Return empty SDValue() otherwise.
960 SDValue SelectionDAGBuilder::getCopyFromRegs(const Value *V, Type *Ty) {
961 DenseMap<const Value *, unsigned>::iterator It = FuncInfo.ValueMap.find(V);
964 if (It != FuncInfo.ValueMap.end()) {
965 unsigned InReg = It->second;
966 RegsForValue RFV(*DAG.getContext(), DAG.getTargetLoweringInfo(), InReg,
968 SDValue Chain = DAG.getEntryNode();
969 Result = RFV.getCopyFromRegs(DAG, FuncInfo, getCurSDLoc(), Chain, nullptr, V);
970 resolveDanglingDebugInfo(V, Result);
976 /// getValue - Return an SDValue for the given Value.
977 SDValue SelectionDAGBuilder::getValue(const Value *V) {
978 // If we already have an SDValue for this value, use it. It's important
979 // to do this first, so that we don't create a CopyFromReg if we already
980 // have a regular SDValue.
981 SDValue &N = NodeMap[V];
982 if (N.getNode()) return N;
984 // If there's a virtual register allocated and initialized for this
986 SDValue copyFromReg = getCopyFromRegs(V, V->getType());
987 if (copyFromReg.getNode()) {
991 // Otherwise create a new SDValue and remember it.
992 SDValue Val = getValueImpl(V);
994 resolveDanglingDebugInfo(V, Val);
998 // Return true if SDValue exists for the given Value
999 bool SelectionDAGBuilder::findValue(const Value *V) const {
1000 return (NodeMap.find(V) != NodeMap.end()) ||
1001 (FuncInfo.ValueMap.find(V) != FuncInfo.ValueMap.end());
1004 /// getNonRegisterValue - Return an SDValue for the given Value, but
1005 /// don't look in FuncInfo.ValueMap for a virtual register.
1006 SDValue SelectionDAGBuilder::getNonRegisterValue(const Value *V) {
1007 // If we already have an SDValue for this value, use it.
1008 SDValue &N = NodeMap[V];
1010 if (isa<ConstantSDNode>(N) || isa<ConstantFPSDNode>(N)) {
1011 // Remove the debug location from the node as the node is about to be used
1012 // in a location which may differ from the original debug location. This
1013 // is relevant to Constant and ConstantFP nodes because they can appear
1014 // as constant expressions inside PHI nodes.
1015 N->setDebugLoc(DebugLoc());
1020 // Otherwise create a new SDValue and remember it.
1021 SDValue Val = getValueImpl(V);
1023 resolveDanglingDebugInfo(V, Val);
1027 /// getValueImpl - Helper function for getValue and getNonRegisterValue.
1028 /// Create an SDValue for the given value.
1029 SDValue SelectionDAGBuilder::getValueImpl(const Value *V) {
1030 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1032 if (const Constant *C = dyn_cast<Constant>(V)) {
1033 EVT VT = TLI.getValueType(V->getType(), true);
1035 if (const ConstantInt *CI = dyn_cast<ConstantInt>(C))
1036 return DAG.getConstant(*CI, getCurSDLoc(), VT);
1038 if (const GlobalValue *GV = dyn_cast<GlobalValue>(C))
1039 return DAG.getGlobalAddress(GV, getCurSDLoc(), VT);
1041 if (isa<ConstantPointerNull>(C)) {
1042 unsigned AS = V->getType()->getPointerAddressSpace();
1043 return DAG.getConstant(0, getCurSDLoc(), TLI.getPointerTy(AS));
1046 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(C))
1047 return DAG.getConstantFP(*CFP, getCurSDLoc(), VT);
1049 if (isa<UndefValue>(C) && !V->getType()->isAggregateType())
1050 return DAG.getUNDEF(VT);
1052 if (const ConstantExpr *CE = dyn_cast<ConstantExpr>(C)) {
1053 visit(CE->getOpcode(), *CE);
1054 SDValue N1 = NodeMap[V];
1055 assert(N1.getNode() && "visit didn't populate the NodeMap!");
1059 if (isa<ConstantStruct>(C) || isa<ConstantArray>(C)) {
1060 SmallVector<SDValue, 4> Constants;
1061 for (User::const_op_iterator OI = C->op_begin(), OE = C->op_end();
1063 SDNode *Val = getValue(*OI).getNode();
1064 // If the operand is an empty aggregate, there are no values.
1066 // Add each leaf value from the operand to the Constants list
1067 // to form a flattened list of all the values.
1068 for (unsigned i = 0, e = Val->getNumValues(); i != e; ++i)
1069 Constants.push_back(SDValue(Val, i));
1072 return DAG.getMergeValues(Constants, getCurSDLoc());
1075 if (const ConstantDataSequential *CDS =
1076 dyn_cast<ConstantDataSequential>(C)) {
1077 SmallVector<SDValue, 4> Ops;
1078 for (unsigned i = 0, e = CDS->getNumElements(); i != e; ++i) {
1079 SDNode *Val = getValue(CDS->getElementAsConstant(i)).getNode();
1080 // Add each leaf value from the operand to the Constants list
1081 // to form a flattened list of all the values.
1082 for (unsigned i = 0, e = Val->getNumValues(); i != e; ++i)
1083 Ops.push_back(SDValue(Val, i));
1086 if (isa<ArrayType>(CDS->getType()))
1087 return DAG.getMergeValues(Ops, getCurSDLoc());
1088 return NodeMap[V] = DAG.getNode(ISD::BUILD_VECTOR, getCurSDLoc(),
1092 if (C->getType()->isStructTy() || C->getType()->isArrayTy()) {
1093 assert((isa<ConstantAggregateZero>(C) || isa<UndefValue>(C)) &&
1094 "Unknown struct or array constant!");
1096 SmallVector<EVT, 4> ValueVTs;
1097 ComputeValueVTs(TLI, C->getType(), ValueVTs);
1098 unsigned NumElts = ValueVTs.size();
1100 return SDValue(); // empty struct
1101 SmallVector<SDValue, 4> Constants(NumElts);
1102 for (unsigned i = 0; i != NumElts; ++i) {
1103 EVT EltVT = ValueVTs[i];
1104 if (isa<UndefValue>(C))
1105 Constants[i] = DAG.getUNDEF(EltVT);
1106 else if (EltVT.isFloatingPoint())
1107 Constants[i] = DAG.getConstantFP(0, getCurSDLoc(), EltVT);
1109 Constants[i] = DAG.getConstant(0, getCurSDLoc(), EltVT);
1112 return DAG.getMergeValues(Constants, getCurSDLoc());
1115 if (const BlockAddress *BA = dyn_cast<BlockAddress>(C))
1116 return DAG.getBlockAddress(BA, VT);
1118 VectorType *VecTy = cast<VectorType>(V->getType());
1119 unsigned NumElements = VecTy->getNumElements();
1121 // Now that we know the number and type of the elements, get that number of
1122 // elements into the Ops array based on what kind of constant it is.
1123 SmallVector<SDValue, 16> Ops;
1124 if (const ConstantVector *CV = dyn_cast<ConstantVector>(C)) {
1125 for (unsigned i = 0; i != NumElements; ++i)
1126 Ops.push_back(getValue(CV->getOperand(i)));
1128 assert(isa<ConstantAggregateZero>(C) && "Unknown vector constant!");
1129 EVT EltVT = TLI.getValueType(VecTy->getElementType());
1132 if (EltVT.isFloatingPoint())
1133 Op = DAG.getConstantFP(0, getCurSDLoc(), EltVT);
1135 Op = DAG.getConstant(0, getCurSDLoc(), EltVT);
1136 Ops.assign(NumElements, Op);
1139 // Create a BUILD_VECTOR node.
1140 return NodeMap[V] = DAG.getNode(ISD::BUILD_VECTOR, getCurSDLoc(), VT, Ops);
1143 // If this is a static alloca, generate it as the frameindex instead of
1145 if (const AllocaInst *AI = dyn_cast<AllocaInst>(V)) {
1146 DenseMap<const AllocaInst*, int>::iterator SI =
1147 FuncInfo.StaticAllocaMap.find(AI);
1148 if (SI != FuncInfo.StaticAllocaMap.end())
1149 return DAG.getFrameIndex(SI->second, TLI.getPointerTy());
1152 // If this is an instruction which fast-isel has deferred, select it now.
1153 if (const Instruction *Inst = dyn_cast<Instruction>(V)) {
1154 unsigned InReg = FuncInfo.InitializeRegForValue(Inst);
1155 RegsForValue RFV(*DAG.getContext(), TLI, InReg, Inst->getType());
1156 SDValue Chain = DAG.getEntryNode();
1157 return RFV.getCopyFromRegs(DAG, FuncInfo, getCurSDLoc(), Chain, nullptr, V);
1160 llvm_unreachable("Can't get register for value!");
1163 void SelectionDAGBuilder::visitRet(const ReturnInst &I) {
1164 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1165 SDValue Chain = getControlRoot();
1166 SmallVector<ISD::OutputArg, 8> Outs;
1167 SmallVector<SDValue, 8> OutVals;
1169 if (!FuncInfo.CanLowerReturn) {
1170 unsigned DemoteReg = FuncInfo.DemoteRegister;
1171 const Function *F = I.getParent()->getParent();
1173 // Emit a store of the return value through the virtual register.
1174 // Leave Outs empty so that LowerReturn won't try to load return
1175 // registers the usual way.
1176 SmallVector<EVT, 1> PtrValueVTs;
1177 ComputeValueVTs(TLI, PointerType::getUnqual(F->getReturnType()),
1180 SDValue RetPtr = DAG.getRegister(DemoteReg, PtrValueVTs[0]);
1181 SDValue RetOp = getValue(I.getOperand(0));
1183 SmallVector<EVT, 4> ValueVTs;
1184 SmallVector<uint64_t, 4> Offsets;
1185 ComputeValueVTs(TLI, I.getOperand(0)->getType(), ValueVTs, &Offsets);
1186 unsigned NumValues = ValueVTs.size();
1188 SmallVector<SDValue, 4> Chains(NumValues);
1189 for (unsigned i = 0; i != NumValues; ++i) {
1190 SDValue Add = DAG.getNode(ISD::ADD, getCurSDLoc(),
1191 RetPtr.getValueType(), RetPtr,
1192 DAG.getIntPtrConstant(Offsets[i],
1195 DAG.getStore(Chain, getCurSDLoc(),
1196 SDValue(RetOp.getNode(), RetOp.getResNo() + i),
1197 // FIXME: better loc info would be nice.
1198 Add, MachinePointerInfo(), false, false, 0);
1201 Chain = DAG.getNode(ISD::TokenFactor, getCurSDLoc(),
1202 MVT::Other, Chains);
1203 } else if (I.getNumOperands() != 0) {
1204 SmallVector<EVT, 4> ValueVTs;
1205 ComputeValueVTs(TLI, I.getOperand(0)->getType(), ValueVTs);
1206 unsigned NumValues = ValueVTs.size();
1208 SDValue RetOp = getValue(I.getOperand(0));
1210 const Function *F = I.getParent()->getParent();
1212 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
1213 if (F->getAttributes().hasAttribute(AttributeSet::ReturnIndex,
1215 ExtendKind = ISD::SIGN_EXTEND;
1216 else if (F->getAttributes().hasAttribute(AttributeSet::ReturnIndex,
1218 ExtendKind = ISD::ZERO_EXTEND;
1220 LLVMContext &Context = F->getContext();
1221 bool RetInReg = F->getAttributes().hasAttribute(AttributeSet::ReturnIndex,
1224 for (unsigned j = 0; j != NumValues; ++j) {
1225 EVT VT = ValueVTs[j];
1227 if (ExtendKind != ISD::ANY_EXTEND && VT.isInteger())
1228 VT = TLI.getTypeForExtArgOrReturn(Context, VT, ExtendKind);
1230 unsigned NumParts = TLI.getNumRegisters(Context, VT);
1231 MVT PartVT = TLI.getRegisterType(Context, VT);
1232 SmallVector<SDValue, 4> Parts(NumParts);
1233 getCopyToParts(DAG, getCurSDLoc(),
1234 SDValue(RetOp.getNode(), RetOp.getResNo() + j),
1235 &Parts[0], NumParts, PartVT, &I, ExtendKind);
1237 // 'inreg' on function refers to return value
1238 ISD::ArgFlagsTy Flags = ISD::ArgFlagsTy();
1242 // Propagate extension type if any
1243 if (ExtendKind == ISD::SIGN_EXTEND)
1245 else if (ExtendKind == ISD::ZERO_EXTEND)
1248 for (unsigned i = 0; i < NumParts; ++i) {
1249 Outs.push_back(ISD::OutputArg(Flags, Parts[i].getValueType(),
1250 VT, /*isfixed=*/true, 0, 0));
1251 OutVals.push_back(Parts[i]);
1257 bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg();
1258 CallingConv::ID CallConv =
1259 DAG.getMachineFunction().getFunction()->getCallingConv();
1260 Chain = DAG.getTargetLoweringInfo().LowerReturn(
1261 Chain, CallConv, isVarArg, Outs, OutVals, getCurSDLoc(), DAG);
1263 // Verify that the target's LowerReturn behaved as expected.
1264 assert(Chain.getNode() && Chain.getValueType() == MVT::Other &&
1265 "LowerReturn didn't return a valid chain!");
1267 // Update the DAG with the new chain value resulting from return lowering.
1271 /// CopyToExportRegsIfNeeded - If the given value has virtual registers
1272 /// created for it, emit nodes to copy the value into the virtual
1274 void SelectionDAGBuilder::CopyToExportRegsIfNeeded(const Value *V) {
1276 if (V->getType()->isEmptyTy())
1279 DenseMap<const Value *, unsigned>::iterator VMI = FuncInfo.ValueMap.find(V);
1280 if (VMI != FuncInfo.ValueMap.end()) {
1281 assert(!V->use_empty() && "Unused value assigned virtual registers!");
1282 CopyValueToVirtualRegister(V, VMI->second);
1286 /// ExportFromCurrentBlock - If this condition isn't known to be exported from
1287 /// the current basic block, add it to ValueMap now so that we'll get a
1289 void SelectionDAGBuilder::ExportFromCurrentBlock(const Value *V) {
1290 // No need to export constants.
1291 if (!isa<Instruction>(V) && !isa<Argument>(V)) return;
1293 // Already exported?
1294 if (FuncInfo.isExportedInst(V)) return;
1296 unsigned Reg = FuncInfo.InitializeRegForValue(V);
1297 CopyValueToVirtualRegister(V, Reg);
1300 bool SelectionDAGBuilder::isExportableFromCurrentBlock(const Value *V,
1301 const BasicBlock *FromBB) {
1302 // The operands of the setcc have to be in this block. We don't know
1303 // how to export them from some other block.
1304 if (const Instruction *VI = dyn_cast<Instruction>(V)) {
1305 // Can export from current BB.
1306 if (VI->getParent() == FromBB)
1309 // Is already exported, noop.
1310 return FuncInfo.isExportedInst(V);
1313 // If this is an argument, we can export it if the BB is the entry block or
1314 // if it is already exported.
1315 if (isa<Argument>(V)) {
1316 if (FromBB == &FromBB->getParent()->getEntryBlock())
1319 // Otherwise, can only export this if it is already exported.
1320 return FuncInfo.isExportedInst(V);
1323 // Otherwise, constants can always be exported.
1327 /// Return branch probability calculated by BranchProbabilityInfo for IR blocks.
1328 uint32_t SelectionDAGBuilder::getEdgeWeight(const MachineBasicBlock *Src,
1329 const MachineBasicBlock *Dst) const {
1330 BranchProbabilityInfo *BPI = FuncInfo.BPI;
1333 const BasicBlock *SrcBB = Src->getBasicBlock();
1334 const BasicBlock *DstBB = Dst->getBasicBlock();
1335 return BPI->getEdgeWeight(SrcBB, DstBB);
1338 void SelectionDAGBuilder::
1339 addSuccessorWithWeight(MachineBasicBlock *Src, MachineBasicBlock *Dst,
1340 uint32_t Weight /* = 0 */) {
1342 Weight = getEdgeWeight(Src, Dst);
1343 Src->addSuccessor(Dst, Weight);
1347 static bool InBlock(const Value *V, const BasicBlock *BB) {
1348 if (const Instruction *I = dyn_cast<Instruction>(V))
1349 return I->getParent() == BB;
1353 /// EmitBranchForMergedCondition - Helper method for FindMergedConditions.
1354 /// This function emits a branch and is used at the leaves of an OR or an
1355 /// AND operator tree.
1358 SelectionDAGBuilder::EmitBranchForMergedCondition(const Value *Cond,
1359 MachineBasicBlock *TBB,
1360 MachineBasicBlock *FBB,
1361 MachineBasicBlock *CurBB,
1362 MachineBasicBlock *SwitchBB,
1365 const BasicBlock *BB = CurBB->getBasicBlock();
1367 // If the leaf of the tree is a comparison, merge the condition into
1369 if (const CmpInst *BOp = dyn_cast<CmpInst>(Cond)) {
1370 // The operands of the cmp have to be in this block. We don't know
1371 // how to export them from some other block. If this is the first block
1372 // of the sequence, no exporting is needed.
1373 if (CurBB == SwitchBB ||
1374 (isExportableFromCurrentBlock(BOp->getOperand(0), BB) &&
1375 isExportableFromCurrentBlock(BOp->getOperand(1), BB))) {
1376 ISD::CondCode Condition;
1377 if (const ICmpInst *IC = dyn_cast<ICmpInst>(Cond)) {
1378 Condition = getICmpCondCode(IC->getPredicate());
1379 } else if (const FCmpInst *FC = dyn_cast<FCmpInst>(Cond)) {
1380 Condition = getFCmpCondCode(FC->getPredicate());
1381 if (TM.Options.NoNaNsFPMath)
1382 Condition = getFCmpCodeWithoutNaN(Condition);
1384 (void)Condition; // silence warning.
1385 llvm_unreachable("Unknown compare instruction");
1388 CaseBlock CB(Condition, BOp->getOperand(0), BOp->getOperand(1), nullptr,
1389 TBB, FBB, CurBB, TWeight, FWeight);
1390 SwitchCases.push_back(CB);
1395 // Create a CaseBlock record representing this branch.
1396 CaseBlock CB(ISD::SETEQ, Cond, ConstantInt::getTrue(*DAG.getContext()),
1397 nullptr, TBB, FBB, CurBB, TWeight, FWeight);
1398 SwitchCases.push_back(CB);
1401 /// Scale down both weights to fit into uint32_t.
1402 static void ScaleWeights(uint64_t &NewTrue, uint64_t &NewFalse) {
1403 uint64_t NewMax = (NewTrue > NewFalse) ? NewTrue : NewFalse;
1404 uint32_t Scale = (NewMax / UINT32_MAX) + 1;
1405 NewTrue = NewTrue / Scale;
1406 NewFalse = NewFalse / Scale;
1409 /// FindMergedConditions - If Cond is an expression like
1410 void SelectionDAGBuilder::FindMergedConditions(const Value *Cond,
1411 MachineBasicBlock *TBB,
1412 MachineBasicBlock *FBB,
1413 MachineBasicBlock *CurBB,
1414 MachineBasicBlock *SwitchBB,
1415 unsigned Opc, uint32_t TWeight,
1417 // If this node is not part of the or/and tree, emit it as a branch.
1418 const Instruction *BOp = dyn_cast<Instruction>(Cond);
1419 if (!BOp || !(isa<BinaryOperator>(BOp) || isa<CmpInst>(BOp)) ||
1420 (unsigned)BOp->getOpcode() != Opc || !BOp->hasOneUse() ||
1421 BOp->getParent() != CurBB->getBasicBlock() ||
1422 !InBlock(BOp->getOperand(0), CurBB->getBasicBlock()) ||
1423 !InBlock(BOp->getOperand(1), CurBB->getBasicBlock())) {
1424 EmitBranchForMergedCondition(Cond, TBB, FBB, CurBB, SwitchBB,
1429 // Create TmpBB after CurBB.
1430 MachineFunction::iterator BBI = CurBB;
1431 MachineFunction &MF = DAG.getMachineFunction();
1432 MachineBasicBlock *TmpBB = MF.CreateMachineBasicBlock(CurBB->getBasicBlock());
1433 CurBB->getParent()->insert(++BBI, TmpBB);
1435 if (Opc == Instruction::Or) {
1436 // Codegen X | Y as:
1445 // We have flexibility in setting Prob for BB1 and Prob for TmpBB.
1446 // The requirement is that
1447 // TrueProb for BB1 + (FalseProb for BB1 * TrueProb for TmpBB)
1448 // = TrueProb for orignal BB.
1449 // Assuming the orignal weights are A and B, one choice is to set BB1's
1450 // weights to A and A+2B, and set TmpBB's weights to A and 2B. This choice
1452 // TrueProb for BB1 == FalseProb for BB1 * TrueProb for TmpBB.
1453 // Another choice is to assume TrueProb for BB1 equals to TrueProb for
1454 // TmpBB, but the math is more complicated.
1456 uint64_t NewTrueWeight = TWeight;
1457 uint64_t NewFalseWeight = (uint64_t)TWeight + 2 * (uint64_t)FWeight;
1458 ScaleWeights(NewTrueWeight, NewFalseWeight);
1459 // Emit the LHS condition.
1460 FindMergedConditions(BOp->getOperand(0), TBB, TmpBB, CurBB, SwitchBB, Opc,
1461 NewTrueWeight, NewFalseWeight);
1463 NewTrueWeight = TWeight;
1464 NewFalseWeight = 2 * (uint64_t)FWeight;
1465 ScaleWeights(NewTrueWeight, NewFalseWeight);
1466 // Emit the RHS condition into TmpBB.
1467 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, SwitchBB, Opc,
1468 NewTrueWeight, NewFalseWeight);
1470 assert(Opc == Instruction::And && "Unknown merge op!");
1471 // Codegen X & Y as:
1479 // This requires creation of TmpBB after CurBB.
1481 // We have flexibility in setting Prob for BB1 and Prob for TmpBB.
1482 // The requirement is that
1483 // FalseProb for BB1 + (TrueProb for BB1 * FalseProb for TmpBB)
1484 // = FalseProb for orignal BB.
1485 // Assuming the orignal weights are A and B, one choice is to set BB1's
1486 // weights to 2A+B and B, and set TmpBB's weights to 2A and B. This choice
1488 // FalseProb for BB1 == TrueProb for BB1 * FalseProb for TmpBB.
1490 uint64_t NewTrueWeight = 2 * (uint64_t)TWeight + (uint64_t)FWeight;
1491 uint64_t NewFalseWeight = FWeight;
1492 ScaleWeights(NewTrueWeight, NewFalseWeight);
1493 // Emit the LHS condition.
1494 FindMergedConditions(BOp->getOperand(0), TmpBB, FBB, CurBB, SwitchBB, Opc,
1495 NewTrueWeight, NewFalseWeight);
1497 NewTrueWeight = 2 * (uint64_t)TWeight;
1498 NewFalseWeight = FWeight;
1499 ScaleWeights(NewTrueWeight, NewFalseWeight);
1500 // Emit the RHS condition into TmpBB.
1501 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, SwitchBB, Opc,
1502 NewTrueWeight, NewFalseWeight);
1506 /// If the set of cases should be emitted as a series of branches, return true.
1507 /// If we should emit this as a bunch of and/or'd together conditions, return
1510 SelectionDAGBuilder::ShouldEmitAsBranches(const std::vector<CaseBlock> &Cases) {
1511 if (Cases.size() != 2) return true;
1513 // If this is two comparisons of the same values or'd or and'd together, they
1514 // will get folded into a single comparison, so don't emit two blocks.
1515 if ((Cases[0].CmpLHS == Cases[1].CmpLHS &&
1516 Cases[0].CmpRHS == Cases[1].CmpRHS) ||
1517 (Cases[0].CmpRHS == Cases[1].CmpLHS &&
1518 Cases[0].CmpLHS == Cases[1].CmpRHS)) {
1522 // Handle: (X != null) | (Y != null) --> (X|Y) != 0
1523 // Handle: (X == null) & (Y == null) --> (X|Y) == 0
1524 if (Cases[0].CmpRHS == Cases[1].CmpRHS &&
1525 Cases[0].CC == Cases[1].CC &&
1526 isa<Constant>(Cases[0].CmpRHS) &&
1527 cast<Constant>(Cases[0].CmpRHS)->isNullValue()) {
1528 if (Cases[0].CC == ISD::SETEQ && Cases[0].TrueBB == Cases[1].ThisBB)
1530 if (Cases[0].CC == ISD::SETNE && Cases[0].FalseBB == Cases[1].ThisBB)
1537 void SelectionDAGBuilder::visitBr(const BranchInst &I) {
1538 MachineBasicBlock *BrMBB = FuncInfo.MBB;
1540 // Update machine-CFG edges.
1541 MachineBasicBlock *Succ0MBB = FuncInfo.MBBMap[I.getSuccessor(0)];
1543 if (I.isUnconditional()) {
1544 // Update machine-CFG edges.
1545 BrMBB->addSuccessor(Succ0MBB);
1547 // If this is not a fall-through branch or optimizations are switched off,
1549 if (Succ0MBB != NextBlock(BrMBB) || TM.getOptLevel() == CodeGenOpt::None)
1550 DAG.setRoot(DAG.getNode(ISD::BR, getCurSDLoc(),
1551 MVT::Other, getControlRoot(),
1552 DAG.getBasicBlock(Succ0MBB)));
1557 // If this condition is one of the special cases we handle, do special stuff
1559 const Value *CondVal = I.getCondition();
1560 MachineBasicBlock *Succ1MBB = FuncInfo.MBBMap[I.getSuccessor(1)];
1562 // If this is a series of conditions that are or'd or and'd together, emit
1563 // this as a sequence of branches instead of setcc's with and/or operations.
1564 // As long as jumps are not expensive, this should improve performance.
1565 // For example, instead of something like:
1578 if (const BinaryOperator *BOp = dyn_cast<BinaryOperator>(CondVal)) {
1579 if (!DAG.getTargetLoweringInfo().isJumpExpensive() &&
1580 BOp->hasOneUse() && (BOp->getOpcode() == Instruction::And ||
1581 BOp->getOpcode() == Instruction::Or)) {
1582 FindMergedConditions(BOp, Succ0MBB, Succ1MBB, BrMBB, BrMBB,
1583 BOp->getOpcode(), getEdgeWeight(BrMBB, Succ0MBB),
1584 getEdgeWeight(BrMBB, Succ1MBB));
1585 // If the compares in later blocks need to use values not currently
1586 // exported from this block, export them now. This block should always
1587 // be the first entry.
1588 assert(SwitchCases[0].ThisBB == BrMBB && "Unexpected lowering!");
1590 // Allow some cases to be rejected.
1591 if (ShouldEmitAsBranches(SwitchCases)) {
1592 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i) {
1593 ExportFromCurrentBlock(SwitchCases[i].CmpLHS);
1594 ExportFromCurrentBlock(SwitchCases[i].CmpRHS);
1597 // Emit the branch for this block.
1598 visitSwitchCase(SwitchCases[0], BrMBB);
1599 SwitchCases.erase(SwitchCases.begin());
1603 // Okay, we decided not to do this, remove any inserted MBB's and clear
1605 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i)
1606 FuncInfo.MF->erase(SwitchCases[i].ThisBB);
1608 SwitchCases.clear();
1612 // Create a CaseBlock record representing this branch.
1613 CaseBlock CB(ISD::SETEQ, CondVal, ConstantInt::getTrue(*DAG.getContext()),
1614 nullptr, Succ0MBB, Succ1MBB, BrMBB);
1616 // Use visitSwitchCase to actually insert the fast branch sequence for this
1618 visitSwitchCase(CB, BrMBB);
1621 /// visitSwitchCase - Emits the necessary code to represent a single node in
1622 /// the binary search tree resulting from lowering a switch instruction.
1623 void SelectionDAGBuilder::visitSwitchCase(CaseBlock &CB,
1624 MachineBasicBlock *SwitchBB) {
1626 SDValue CondLHS = getValue(CB.CmpLHS);
1627 SDLoc dl = getCurSDLoc();
1629 // Build the setcc now.
1631 // Fold "(X == true)" to X and "(X == false)" to !X to
1632 // handle common cases produced by branch lowering.
1633 if (CB.CmpRHS == ConstantInt::getTrue(*DAG.getContext()) &&
1634 CB.CC == ISD::SETEQ)
1636 else if (CB.CmpRHS == ConstantInt::getFalse(*DAG.getContext()) &&
1637 CB.CC == ISD::SETEQ) {
1638 SDValue True = DAG.getConstant(1, dl, CondLHS.getValueType());
1639 Cond = DAG.getNode(ISD::XOR, dl, CondLHS.getValueType(), CondLHS, True);
1641 Cond = DAG.getSetCC(dl, MVT::i1, CondLHS, getValue(CB.CmpRHS), CB.CC);
1643 assert(CB.CC == ISD::SETLE && "Can handle only LE ranges now");
1645 const APInt& Low = cast<ConstantInt>(CB.CmpLHS)->getValue();
1646 const APInt& High = cast<ConstantInt>(CB.CmpRHS)->getValue();
1648 SDValue CmpOp = getValue(CB.CmpMHS);
1649 EVT VT = CmpOp.getValueType();
1651 if (cast<ConstantInt>(CB.CmpLHS)->isMinValue(true)) {
1652 Cond = DAG.getSetCC(dl, MVT::i1, CmpOp, DAG.getConstant(High, dl, VT),
1655 SDValue SUB = DAG.getNode(ISD::SUB, dl,
1656 VT, CmpOp, DAG.getConstant(Low, dl, VT));
1657 Cond = DAG.getSetCC(dl, MVT::i1, SUB,
1658 DAG.getConstant(High-Low, dl, VT), ISD::SETULE);
1662 // Update successor info
1663 addSuccessorWithWeight(SwitchBB, CB.TrueBB, CB.TrueWeight);
1664 // TrueBB and FalseBB are always different unless the incoming IR is
1665 // degenerate. This only happens when running llc on weird IR.
1666 if (CB.TrueBB != CB.FalseBB)
1667 addSuccessorWithWeight(SwitchBB, CB.FalseBB, CB.FalseWeight);
1669 // If the lhs block is the next block, invert the condition so that we can
1670 // fall through to the lhs instead of the rhs block.
1671 if (CB.TrueBB == NextBlock(SwitchBB)) {
1672 std::swap(CB.TrueBB, CB.FalseBB);
1673 SDValue True = DAG.getConstant(1, dl, Cond.getValueType());
1674 Cond = DAG.getNode(ISD::XOR, dl, Cond.getValueType(), Cond, True);
1677 SDValue BrCond = DAG.getNode(ISD::BRCOND, dl,
1678 MVT::Other, getControlRoot(), Cond,
1679 DAG.getBasicBlock(CB.TrueBB));
1681 // Insert the false branch. Do this even if it's a fall through branch,
1682 // this makes it easier to do DAG optimizations which require inverting
1683 // the branch condition.
1684 BrCond = DAG.getNode(ISD::BR, dl, MVT::Other, BrCond,
1685 DAG.getBasicBlock(CB.FalseBB));
1687 DAG.setRoot(BrCond);
1690 /// visitJumpTable - Emit JumpTable node in the current MBB
1691 void SelectionDAGBuilder::visitJumpTable(JumpTable &JT) {
1692 // Emit the code for the jump table
1693 assert(JT.Reg != -1U && "Should lower JT Header first!");
1694 EVT PTy = DAG.getTargetLoweringInfo().getPointerTy();
1695 SDValue Index = DAG.getCopyFromReg(getControlRoot(), getCurSDLoc(),
1697 SDValue Table = DAG.getJumpTable(JT.JTI, PTy);
1698 SDValue BrJumpTable = DAG.getNode(ISD::BR_JT, getCurSDLoc(),
1699 MVT::Other, Index.getValue(1),
1701 DAG.setRoot(BrJumpTable);
1704 /// visitJumpTableHeader - This function emits necessary code to produce index
1705 /// in the JumpTable from switch case.
1706 void SelectionDAGBuilder::visitJumpTableHeader(JumpTable &JT,
1707 JumpTableHeader &JTH,
1708 MachineBasicBlock *SwitchBB) {
1709 SDLoc dl = getCurSDLoc();
1711 // Subtract the lowest switch case value from the value being switched on and
1712 // conditional branch to default mbb if the result is greater than the
1713 // difference between smallest and largest cases.
1714 SDValue SwitchOp = getValue(JTH.SValue);
1715 EVT VT = SwitchOp.getValueType();
1716 SDValue Sub = DAG.getNode(ISD::SUB, dl, VT, SwitchOp,
1717 DAG.getConstant(JTH.First, dl, VT));
1719 // The SDNode we just created, which holds the value being switched on minus
1720 // the smallest case value, needs to be copied to a virtual register so it
1721 // can be used as an index into the jump table in a subsequent basic block.
1722 // This value may be smaller or larger than the target's pointer type, and
1723 // therefore require extension or truncating.
1724 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1725 SwitchOp = DAG.getZExtOrTrunc(Sub, dl, TLI.getPointerTy());
1727 unsigned JumpTableReg = FuncInfo.CreateReg(TLI.getPointerTy());
1728 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), dl,
1729 JumpTableReg, SwitchOp);
1730 JT.Reg = JumpTableReg;
1732 // Emit the range check for the jump table, and branch to the default block
1733 // for the switch statement if the value being switched on exceeds the largest
1734 // case in the switch.
1736 DAG.getSetCC(dl, TLI.getSetCCResultType(*DAG.getContext(),
1737 Sub.getValueType()),
1738 Sub, DAG.getConstant(JTH.Last - JTH.First, dl, VT),
1741 SDValue BrCond = DAG.getNode(ISD::BRCOND, dl,
1742 MVT::Other, CopyTo, CMP,
1743 DAG.getBasicBlock(JT.Default));
1745 // Avoid emitting unnecessary branches to the next block.
1746 if (JT.MBB != NextBlock(SwitchBB))
1747 BrCond = DAG.getNode(ISD::BR, dl, MVT::Other, BrCond,
1748 DAG.getBasicBlock(JT.MBB));
1750 DAG.setRoot(BrCond);
1753 /// Codegen a new tail for a stack protector check ParentMBB which has had its
1754 /// tail spliced into a stack protector check success bb.
1756 /// For a high level explanation of how this fits into the stack protector
1757 /// generation see the comment on the declaration of class
1758 /// StackProtectorDescriptor.
1759 void SelectionDAGBuilder::visitSPDescriptorParent(StackProtectorDescriptor &SPD,
1760 MachineBasicBlock *ParentBB) {
1762 // First create the loads to the guard/stack slot for the comparison.
1763 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1764 EVT PtrTy = TLI.getPointerTy();
1766 MachineFrameInfo *MFI = ParentBB->getParent()->getFrameInfo();
1767 int FI = MFI->getStackProtectorIndex();
1769 const Value *IRGuard = SPD.getGuard();
1770 SDValue GuardPtr = getValue(IRGuard);
1771 SDValue StackSlotPtr = DAG.getFrameIndex(FI, PtrTy);
1774 TLI.getDataLayout()->getPrefTypeAlignment(IRGuard->getType());
1777 SDLoc dl = getCurSDLoc();
1779 // If GuardReg is set and useLoadStackGuardNode returns true, retrieve the
1780 // guard value from the virtual register holding the value. Otherwise, emit a
1781 // volatile load to retrieve the stack guard value.
1782 unsigned GuardReg = SPD.getGuardReg();
1784 if (GuardReg && TLI.useLoadStackGuardNode())
1785 Guard = DAG.getCopyFromReg(DAG.getEntryNode(), dl, GuardReg,
1788 Guard = DAG.getLoad(PtrTy, dl, DAG.getEntryNode(),
1789 GuardPtr, MachinePointerInfo(IRGuard, 0),
1790 true, false, false, Align);
1792 SDValue StackSlot = DAG.getLoad(PtrTy, dl, DAG.getEntryNode(),
1794 MachinePointerInfo::getFixedStack(FI),
1795 true, false, false, Align);
1797 // Perform the comparison via a subtract/getsetcc.
1798 EVT VT = Guard.getValueType();
1799 SDValue Sub = DAG.getNode(ISD::SUB, dl, VT, Guard, StackSlot);
1802 DAG.getSetCC(dl, TLI.getSetCCResultType(*DAG.getContext(),
1803 Sub.getValueType()),
1804 Sub, DAG.getConstant(0, dl, VT), ISD::SETNE);
1806 // If the sub is not 0, then we know the guard/stackslot do not equal, so
1807 // branch to failure MBB.
1808 SDValue BrCond = DAG.getNode(ISD::BRCOND, dl,
1809 MVT::Other, StackSlot.getOperand(0),
1810 Cmp, DAG.getBasicBlock(SPD.getFailureMBB()));
1811 // Otherwise branch to success MBB.
1812 SDValue Br = DAG.getNode(ISD::BR, dl,
1814 DAG.getBasicBlock(SPD.getSuccessMBB()));
1819 /// Codegen the failure basic block for a stack protector check.
1821 /// A failure stack protector machine basic block consists simply of a call to
1822 /// __stack_chk_fail().
1824 /// For a high level explanation of how this fits into the stack protector
1825 /// generation see the comment on the declaration of class
1826 /// StackProtectorDescriptor.
1828 SelectionDAGBuilder::visitSPDescriptorFailure(StackProtectorDescriptor &SPD) {
1829 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1831 TLI.makeLibCall(DAG, RTLIB::STACKPROTECTOR_CHECK_FAIL, MVT::isVoid,
1832 nullptr, 0, false, getCurSDLoc(), false, false).second;
1836 /// visitBitTestHeader - This function emits necessary code to produce value
1837 /// suitable for "bit tests"
1838 void SelectionDAGBuilder::visitBitTestHeader(BitTestBlock &B,
1839 MachineBasicBlock *SwitchBB) {
1840 SDLoc dl = getCurSDLoc();
1842 // Subtract the minimum value
1843 SDValue SwitchOp = getValue(B.SValue);
1844 EVT VT = SwitchOp.getValueType();
1845 SDValue Sub = DAG.getNode(ISD::SUB, dl, VT, SwitchOp,
1846 DAG.getConstant(B.First, dl, VT));
1849 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1851 DAG.getSetCC(dl, TLI.getSetCCResultType(*DAG.getContext(),
1852 Sub.getValueType()),
1853 Sub, DAG.getConstant(B.Range, dl, VT), ISD::SETUGT);
1855 // Determine the type of the test operands.
1856 bool UsePtrType = false;
1857 if (!TLI.isTypeLegal(VT))
1860 for (unsigned i = 0, e = B.Cases.size(); i != e; ++i)
1861 if (!isUIntN(VT.getSizeInBits(), B.Cases[i].Mask)) {
1862 // Switch table case range are encoded into series of masks.
1863 // Just use pointer type, it's guaranteed to fit.
1869 VT = TLI.getPointerTy();
1870 Sub = DAG.getZExtOrTrunc(Sub, dl, VT);
1873 B.RegVT = VT.getSimpleVT();
1874 B.Reg = FuncInfo.CreateReg(B.RegVT);
1875 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), dl, B.Reg, Sub);
1877 MachineBasicBlock* MBB = B.Cases[0].ThisBB;
1879 addSuccessorWithWeight(SwitchBB, B.Default);
1880 addSuccessorWithWeight(SwitchBB, MBB);
1882 SDValue BrRange = DAG.getNode(ISD::BRCOND, dl,
1883 MVT::Other, CopyTo, RangeCmp,
1884 DAG.getBasicBlock(B.Default));
1886 // Avoid emitting unnecessary branches to the next block.
1887 if (MBB != NextBlock(SwitchBB))
1888 BrRange = DAG.getNode(ISD::BR, dl, MVT::Other, BrRange,
1889 DAG.getBasicBlock(MBB));
1891 DAG.setRoot(BrRange);
1894 /// visitBitTestCase - this function produces one "bit test"
1895 void SelectionDAGBuilder::visitBitTestCase(BitTestBlock &BB,
1896 MachineBasicBlock* NextMBB,
1897 uint32_t BranchWeightToNext,
1900 MachineBasicBlock *SwitchBB) {
1901 SDLoc dl = getCurSDLoc();
1903 SDValue ShiftOp = DAG.getCopyFromReg(getControlRoot(), dl, Reg, VT);
1905 unsigned PopCount = countPopulation(B.Mask);
1906 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1907 if (PopCount == 1) {
1908 // Testing for a single bit; just compare the shift count with what it
1909 // would need to be to shift a 1 bit in that position.
1911 dl, TLI.getSetCCResultType(*DAG.getContext(), VT), ShiftOp,
1912 DAG.getConstant(countTrailingZeros(B.Mask), dl, VT), ISD::SETEQ);
1913 } else if (PopCount == BB.Range) {
1914 // There is only one zero bit in the range, test for it directly.
1916 dl, TLI.getSetCCResultType(*DAG.getContext(), VT), ShiftOp,
1917 DAG.getConstant(countTrailingOnes(B.Mask), dl, VT), ISD::SETNE);
1919 // Make desired shift
1920 SDValue SwitchVal = DAG.getNode(ISD::SHL, dl, VT,
1921 DAG.getConstant(1, dl, VT), ShiftOp);
1923 // Emit bit tests and jumps
1924 SDValue AndOp = DAG.getNode(ISD::AND, dl,
1925 VT, SwitchVal, DAG.getConstant(B.Mask, dl, VT));
1926 Cmp = DAG.getSetCC(dl, TLI.getSetCCResultType(*DAG.getContext(), VT), AndOp,
1927 DAG.getConstant(0, dl, VT), ISD::SETNE);
1930 // The branch weight from SwitchBB to B.TargetBB is B.ExtraWeight.
1931 addSuccessorWithWeight(SwitchBB, B.TargetBB, B.ExtraWeight);
1932 // The branch weight from SwitchBB to NextMBB is BranchWeightToNext.
1933 addSuccessorWithWeight(SwitchBB, NextMBB, BranchWeightToNext);
1935 SDValue BrAnd = DAG.getNode(ISD::BRCOND, dl,
1936 MVT::Other, getControlRoot(),
1937 Cmp, DAG.getBasicBlock(B.TargetBB));
1939 // Avoid emitting unnecessary branches to the next block.
1940 if (NextMBB != NextBlock(SwitchBB))
1941 BrAnd = DAG.getNode(ISD::BR, dl, MVT::Other, BrAnd,
1942 DAG.getBasicBlock(NextMBB));
1947 void SelectionDAGBuilder::visitInvoke(const InvokeInst &I) {
1948 MachineBasicBlock *InvokeMBB = FuncInfo.MBB;
1950 // Retrieve successors.
1951 MachineBasicBlock *Return = FuncInfo.MBBMap[I.getSuccessor(0)];
1952 MachineBasicBlock *LandingPad = FuncInfo.MBBMap[I.getSuccessor(1)];
1954 const Value *Callee(I.getCalledValue());
1955 const Function *Fn = dyn_cast<Function>(Callee);
1956 if (isa<InlineAsm>(Callee))
1958 else if (Fn && Fn->isIntrinsic()) {
1959 switch (Fn->getIntrinsicID()) {
1961 llvm_unreachable("Cannot invoke this intrinsic");
1962 case Intrinsic::donothing:
1963 // Ignore invokes to @llvm.donothing: jump directly to the next BB.
1965 case Intrinsic::experimental_patchpoint_void:
1966 case Intrinsic::experimental_patchpoint_i64:
1967 visitPatchpoint(&I, LandingPad);
1969 case Intrinsic::experimental_gc_statepoint:
1970 LowerStatepoint(ImmutableStatepoint(&I), LandingPad);
1974 LowerCallTo(&I, getValue(Callee), false, LandingPad);
1976 // If the value of the invoke is used outside of its defining block, make it
1977 // available as a virtual register.
1978 // We already took care of the exported value for the statepoint instruction
1979 // during call to the LowerStatepoint.
1980 if (!isStatepoint(I)) {
1981 CopyToExportRegsIfNeeded(&I);
1984 // Update successor info
1985 addSuccessorWithWeight(InvokeMBB, Return);
1986 addSuccessorWithWeight(InvokeMBB, LandingPad);
1988 // Drop into normal successor.
1989 DAG.setRoot(DAG.getNode(ISD::BR, getCurSDLoc(),
1990 MVT::Other, getControlRoot(),
1991 DAG.getBasicBlock(Return)));
1994 void SelectionDAGBuilder::visitResume(const ResumeInst &RI) {
1995 llvm_unreachable("SelectionDAGBuilder shouldn't visit resume instructions!");
1998 void SelectionDAGBuilder::visitLandingPad(const LandingPadInst &LP) {
1999 assert(FuncInfo.MBB->isLandingPad() &&
2000 "Call to landingpad not in landing pad!");
2002 MachineBasicBlock *MBB = FuncInfo.MBB;
2003 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
2004 AddLandingPadInfo(LP, MMI, MBB);
2006 // If there aren't registers to copy the values into (e.g., during SjLj
2007 // exceptions), then don't bother to create these DAG nodes.
2008 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2009 if (TLI.getExceptionPointerRegister() == 0 &&
2010 TLI.getExceptionSelectorRegister() == 0)
2013 SmallVector<EVT, 2> ValueVTs;
2014 SDLoc dl = getCurSDLoc();
2015 ComputeValueVTs(TLI, LP.getType(), ValueVTs);
2016 assert(ValueVTs.size() == 2 && "Only two-valued landingpads are supported");
2018 // Get the two live-in registers as SDValues. The physregs have already been
2019 // copied into virtual registers.
2021 if (FuncInfo.ExceptionPointerVirtReg) {
2022 Ops[0] = DAG.getZExtOrTrunc(
2023 DAG.getCopyFromReg(DAG.getEntryNode(), dl,
2024 FuncInfo.ExceptionPointerVirtReg, TLI.getPointerTy()),
2027 Ops[0] = DAG.getConstant(0, dl, TLI.getPointerTy());
2029 Ops[1] = DAG.getZExtOrTrunc(
2030 DAG.getCopyFromReg(DAG.getEntryNode(), dl,
2031 FuncInfo.ExceptionSelectorVirtReg, TLI.getPointerTy()),
2035 SDValue Res = DAG.getNode(ISD::MERGE_VALUES, dl,
2036 DAG.getVTList(ValueVTs), Ops);
2041 SelectionDAGBuilder::visitLandingPadClauseBB(GlobalValue *ClauseGV,
2042 MachineBasicBlock *LPadBB) {
2043 SDValue Chain = getControlRoot();
2044 SDLoc dl = getCurSDLoc();
2046 // Get the typeid that we will dispatch on later.
2047 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2048 const TargetRegisterClass *RC = TLI.getRegClassFor(TLI.getPointerTy());
2049 unsigned VReg = FuncInfo.MF->getRegInfo().createVirtualRegister(RC);
2050 unsigned TypeID = DAG.getMachineFunction().getMMI().getTypeIDFor(ClauseGV);
2051 SDValue Sel = DAG.getConstant(TypeID, dl, TLI.getPointerTy());
2052 Chain = DAG.getCopyToReg(Chain, dl, VReg, Sel);
2054 // Branch to the main landing pad block.
2055 MachineBasicBlock *ClauseMBB = FuncInfo.MBB;
2056 ClauseMBB->addSuccessor(LPadBB);
2057 DAG.setRoot(DAG.getNode(ISD::BR, dl, MVT::Other, Chain,
2058 DAG.getBasicBlock(LPadBB)));
2062 void SelectionDAGBuilder::sortAndRangeify(CaseClusterVector &Clusters) {
2064 for (const CaseCluster &CC : Clusters)
2065 assert(CC.Low == CC.High && "Input clusters must be single-case");
2068 std::sort(Clusters.begin(), Clusters.end(),
2069 [](const CaseCluster &a, const CaseCluster &b) {
2070 return a.Low->getValue().slt(b.Low->getValue());
2073 // Merge adjacent clusters with the same destination.
2074 const unsigned N = Clusters.size();
2075 unsigned DstIndex = 0;
2076 for (unsigned SrcIndex = 0; SrcIndex < N; ++SrcIndex) {
2077 CaseCluster &CC = Clusters[SrcIndex];
2078 const ConstantInt *CaseVal = CC.Low;
2079 MachineBasicBlock *Succ = CC.MBB;
2081 if (DstIndex != 0 && Clusters[DstIndex - 1].MBB == Succ &&
2082 (CaseVal->getValue() - Clusters[DstIndex - 1].High->getValue()) == 1) {
2083 // If this case has the same successor and is a neighbour, merge it into
2084 // the previous cluster.
2085 Clusters[DstIndex - 1].High = CaseVal;
2086 Clusters[DstIndex - 1].Weight += CC.Weight;
2087 assert(Clusters[DstIndex - 1].Weight >= CC.Weight && "Weight overflow!");
2089 std::memmove(&Clusters[DstIndex++], &Clusters[SrcIndex],
2090 sizeof(Clusters[SrcIndex]));
2093 Clusters.resize(DstIndex);
2096 void SelectionDAGBuilder::UpdateSplitBlock(MachineBasicBlock *First,
2097 MachineBasicBlock *Last) {
2099 for (unsigned i = 0, e = JTCases.size(); i != e; ++i)
2100 if (JTCases[i].first.HeaderBB == First)
2101 JTCases[i].first.HeaderBB = Last;
2103 // Update BitTestCases.
2104 for (unsigned i = 0, e = BitTestCases.size(); i != e; ++i)
2105 if (BitTestCases[i].Parent == First)
2106 BitTestCases[i].Parent = Last;
2109 void SelectionDAGBuilder::visitIndirectBr(const IndirectBrInst &I) {
2110 MachineBasicBlock *IndirectBrMBB = FuncInfo.MBB;
2112 // Update machine-CFG edges with unique successors.
2113 SmallSet<BasicBlock*, 32> Done;
2114 for (unsigned i = 0, e = I.getNumSuccessors(); i != e; ++i) {
2115 BasicBlock *BB = I.getSuccessor(i);
2116 bool Inserted = Done.insert(BB).second;
2120 MachineBasicBlock *Succ = FuncInfo.MBBMap[BB];
2121 addSuccessorWithWeight(IndirectBrMBB, Succ);
2124 DAG.setRoot(DAG.getNode(ISD::BRIND, getCurSDLoc(),
2125 MVT::Other, getControlRoot(),
2126 getValue(I.getAddress())));
2129 void SelectionDAGBuilder::visitUnreachable(const UnreachableInst &I) {
2130 if (DAG.getTarget().Options.TrapUnreachable)
2131 DAG.setRoot(DAG.getNode(ISD::TRAP, getCurSDLoc(), MVT::Other, DAG.getRoot()));
2134 void SelectionDAGBuilder::visitFSub(const User &I) {
2135 // -0.0 - X --> fneg
2136 Type *Ty = I.getType();
2137 if (isa<Constant>(I.getOperand(0)) &&
2138 I.getOperand(0) == ConstantFP::getZeroValueForNegation(Ty)) {
2139 SDValue Op2 = getValue(I.getOperand(1));
2140 setValue(&I, DAG.getNode(ISD::FNEG, getCurSDLoc(),
2141 Op2.getValueType(), Op2));
2145 visitBinary(I, ISD::FSUB);
2148 void SelectionDAGBuilder::visitBinary(const User &I, unsigned OpCode) {
2149 SDValue Op1 = getValue(I.getOperand(0));
2150 SDValue Op2 = getValue(I.getOperand(1));
2157 if (const OverflowingBinaryOperator *OFBinOp =
2158 dyn_cast<const OverflowingBinaryOperator>(&I)) {
2159 nuw = OFBinOp->hasNoUnsignedWrap();
2160 nsw = OFBinOp->hasNoSignedWrap();
2162 if (const PossiblyExactOperator *ExactOp =
2163 dyn_cast<const PossiblyExactOperator>(&I))
2164 exact = ExactOp->isExact();
2165 if (const FPMathOperator *FPOp = dyn_cast<const FPMathOperator>(&I))
2166 FMF = FPOp->getFastMathFlags();
2169 Flags.setExact(exact);
2170 Flags.setNoSignedWrap(nsw);
2171 Flags.setNoUnsignedWrap(nuw);
2172 if (EnableFMFInDAG) {
2173 Flags.setAllowReciprocal(FMF.allowReciprocal());
2174 Flags.setNoInfs(FMF.noInfs());
2175 Flags.setNoNaNs(FMF.noNaNs());
2176 Flags.setNoSignedZeros(FMF.noSignedZeros());
2177 Flags.setUnsafeAlgebra(FMF.unsafeAlgebra());
2179 SDValue BinNodeValue = DAG.getNode(OpCode, getCurSDLoc(), Op1.getValueType(),
2181 setValue(&I, BinNodeValue);
2184 void SelectionDAGBuilder::visitShift(const User &I, unsigned Opcode) {
2185 SDValue Op1 = getValue(I.getOperand(0));
2186 SDValue Op2 = getValue(I.getOperand(1));
2189 DAG.getTargetLoweringInfo().getShiftAmountTy(Op2.getValueType());
2191 // Coerce the shift amount to the right type if we can.
2192 if (!I.getType()->isVectorTy() && Op2.getValueType() != ShiftTy) {
2193 unsigned ShiftSize = ShiftTy.getSizeInBits();
2194 unsigned Op2Size = Op2.getValueType().getSizeInBits();
2195 SDLoc DL = getCurSDLoc();
2197 // If the operand is smaller than the shift count type, promote it.
2198 if (ShiftSize > Op2Size)
2199 Op2 = DAG.getNode(ISD::ZERO_EXTEND, DL, ShiftTy, Op2);
2201 // If the operand is larger than the shift count type but the shift
2202 // count type has enough bits to represent any shift value, truncate
2203 // it now. This is a common case and it exposes the truncate to
2204 // optimization early.
2205 else if (ShiftSize >= Log2_32_Ceil(Op2.getValueType().getSizeInBits()))
2206 Op2 = DAG.getNode(ISD::TRUNCATE, DL, ShiftTy, Op2);
2207 // Otherwise we'll need to temporarily settle for some other convenient
2208 // type. Type legalization will make adjustments once the shiftee is split.
2210 Op2 = DAG.getZExtOrTrunc(Op2, DL, MVT::i32);
2217 if (Opcode == ISD::SRL || Opcode == ISD::SRA || Opcode == ISD::SHL) {
2219 if (const OverflowingBinaryOperator *OFBinOp =
2220 dyn_cast<const OverflowingBinaryOperator>(&I)) {
2221 nuw = OFBinOp->hasNoUnsignedWrap();
2222 nsw = OFBinOp->hasNoSignedWrap();
2224 if (const PossiblyExactOperator *ExactOp =
2225 dyn_cast<const PossiblyExactOperator>(&I))
2226 exact = ExactOp->isExact();
2229 Flags.setExact(exact);
2230 Flags.setNoSignedWrap(nsw);
2231 Flags.setNoUnsignedWrap(nuw);
2232 SDValue Res = DAG.getNode(Opcode, getCurSDLoc(), Op1.getValueType(), Op1, Op2,
2237 void SelectionDAGBuilder::visitSDiv(const User &I) {
2238 SDValue Op1 = getValue(I.getOperand(0));
2239 SDValue Op2 = getValue(I.getOperand(1));
2241 // Turn exact SDivs into multiplications.
2242 // FIXME: This should be in DAGCombiner, but it doesn't have access to the
2244 if (isa<BinaryOperator>(&I) && cast<BinaryOperator>(&I)->isExact() &&
2245 !isa<ConstantSDNode>(Op1) &&
2246 isa<ConstantSDNode>(Op2) && !cast<ConstantSDNode>(Op2)->isNullValue())
2247 setValue(&I, DAG.getTargetLoweringInfo()
2248 .BuildExactSDIV(Op1, Op2, getCurSDLoc(), DAG));
2250 setValue(&I, DAG.getNode(ISD::SDIV, getCurSDLoc(), Op1.getValueType(),
2254 void SelectionDAGBuilder::visitICmp(const User &I) {
2255 ICmpInst::Predicate predicate = ICmpInst::BAD_ICMP_PREDICATE;
2256 if (const ICmpInst *IC = dyn_cast<ICmpInst>(&I))
2257 predicate = IC->getPredicate();
2258 else if (const ConstantExpr *IC = dyn_cast<ConstantExpr>(&I))
2259 predicate = ICmpInst::Predicate(IC->getPredicate());
2260 SDValue Op1 = getValue(I.getOperand(0));
2261 SDValue Op2 = getValue(I.getOperand(1));
2262 ISD::CondCode Opcode = getICmpCondCode(predicate);
2264 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(I.getType());
2265 setValue(&I, DAG.getSetCC(getCurSDLoc(), DestVT, Op1, Op2, Opcode));
2268 void SelectionDAGBuilder::visitFCmp(const User &I) {
2269 FCmpInst::Predicate predicate = FCmpInst::BAD_FCMP_PREDICATE;
2270 if (const FCmpInst *FC = dyn_cast<FCmpInst>(&I))
2271 predicate = FC->getPredicate();
2272 else if (const ConstantExpr *FC = dyn_cast<ConstantExpr>(&I))
2273 predicate = FCmpInst::Predicate(FC->getPredicate());
2274 SDValue Op1 = getValue(I.getOperand(0));
2275 SDValue Op2 = getValue(I.getOperand(1));
2276 ISD::CondCode Condition = getFCmpCondCode(predicate);
2277 if (TM.Options.NoNaNsFPMath)
2278 Condition = getFCmpCodeWithoutNaN(Condition);
2279 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(I.getType());
2280 setValue(&I, DAG.getSetCC(getCurSDLoc(), DestVT, Op1, Op2, Condition));
2283 void SelectionDAGBuilder::visitSelect(const User &I) {
2284 SmallVector<EVT, 4> ValueVTs;
2285 ComputeValueVTs(DAG.getTargetLoweringInfo(), I.getType(), ValueVTs);
2286 unsigned NumValues = ValueVTs.size();
2287 if (NumValues == 0) return;
2289 SmallVector<SDValue, 4> Values(NumValues);
2290 SDValue Cond = getValue(I.getOperand(0));
2291 SDValue LHSVal = getValue(I.getOperand(1));
2292 SDValue RHSVal = getValue(I.getOperand(2));
2293 auto BaseOps = {Cond};
2294 ISD::NodeType OpCode = Cond.getValueType().isVector() ?
2295 ISD::VSELECT : ISD::SELECT;
2297 // Min/max matching is only viable if all output VTs are the same.
2298 if (std::equal(ValueVTs.begin(), ValueVTs.end(), ValueVTs.begin())) {
2300 SelectPatternFlavor SPF = matchSelectPattern(const_cast<User*>(&I), LHS, RHS);
2301 ISD::NodeType Opc = ISD::DELETED_NODE;
2303 case SPF_UMAX: Opc = ISD::UMAX; break;
2304 case SPF_UMIN: Opc = ISD::UMIN; break;
2305 case SPF_SMAX: Opc = ISD::SMAX; break;
2306 case SPF_SMIN: Opc = ISD::SMIN; break;
2310 EVT VT = ValueVTs[0];
2311 LLVMContext &Ctx = *DAG.getContext();
2312 auto &TLI = DAG.getTargetLoweringInfo();
2313 while (TLI.getTypeAction(Ctx, VT) == TargetLoweringBase::TypeSplitVector)
2314 VT = TLI.getTypeToTransformTo(Ctx, VT);
2316 if (Opc != ISD::DELETED_NODE && TLI.isOperationLegalOrCustom(Opc, VT) &&
2317 // If the underlying comparison instruction is used by any other instruction,
2318 // the consumed instructions won't be destroyed, so it is not profitable
2319 // to convert to a min/max.
2320 cast<SelectInst>(&I)->getCondition()->hasOneUse()) {
2322 LHSVal = getValue(LHS);
2323 RHSVal = getValue(RHS);
2328 for (unsigned i = 0; i != NumValues; ++i) {
2329 SmallVector<SDValue, 3> Ops(BaseOps.begin(), BaseOps.end());
2330 Ops.push_back(SDValue(LHSVal.getNode(), LHSVal.getResNo() + i));
2331 Ops.push_back(SDValue(RHSVal.getNode(), RHSVal.getResNo() + i));
2332 Values[i] = DAG.getNode(OpCode, getCurSDLoc(),
2333 LHSVal.getNode()->getValueType(LHSVal.getResNo()+i),
2337 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(),
2338 DAG.getVTList(ValueVTs), Values));
2341 void SelectionDAGBuilder::visitTrunc(const User &I) {
2342 // TruncInst cannot be a no-op cast because sizeof(src) > sizeof(dest).
2343 SDValue N = getValue(I.getOperand(0));
2344 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(I.getType());
2345 setValue(&I, DAG.getNode(ISD::TRUNCATE, getCurSDLoc(), DestVT, N));
2348 void SelectionDAGBuilder::visitZExt(const User &I) {
2349 // ZExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
2350 // ZExt also can't be a cast to bool for same reason. So, nothing much to do
2351 SDValue N = getValue(I.getOperand(0));
2352 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(I.getType());
2353 setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, getCurSDLoc(), DestVT, N));
2356 void SelectionDAGBuilder::visitSExt(const User &I) {
2357 // SExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
2358 // SExt also can't be a cast to bool for same reason. So, nothing much to do
2359 SDValue N = getValue(I.getOperand(0));
2360 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(I.getType());
2361 setValue(&I, DAG.getNode(ISD::SIGN_EXTEND, getCurSDLoc(), DestVT, N));
2364 void SelectionDAGBuilder::visitFPTrunc(const User &I) {
2365 // FPTrunc is never a no-op cast, no need to check
2366 SDValue N = getValue(I.getOperand(0));
2367 SDLoc dl = getCurSDLoc();
2368 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2369 EVT DestVT = TLI.getValueType(I.getType());
2370 setValue(&I, DAG.getNode(ISD::FP_ROUND, dl, DestVT, N,
2371 DAG.getTargetConstant(0, dl, TLI.getPointerTy())));
2374 void SelectionDAGBuilder::visitFPExt(const User &I) {
2375 // FPExt is never a no-op cast, no need to check
2376 SDValue N = getValue(I.getOperand(0));
2377 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(I.getType());
2378 setValue(&I, DAG.getNode(ISD::FP_EXTEND, getCurSDLoc(), DestVT, N));
2381 void SelectionDAGBuilder::visitFPToUI(const User &I) {
2382 // FPToUI is never a no-op cast, no need to check
2383 SDValue N = getValue(I.getOperand(0));
2384 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(I.getType());
2385 setValue(&I, DAG.getNode(ISD::FP_TO_UINT, getCurSDLoc(), DestVT, N));
2388 void SelectionDAGBuilder::visitFPToSI(const User &I) {
2389 // FPToSI is never a no-op cast, no need to check
2390 SDValue N = getValue(I.getOperand(0));
2391 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(I.getType());
2392 setValue(&I, DAG.getNode(ISD::FP_TO_SINT, getCurSDLoc(), DestVT, N));
2395 void SelectionDAGBuilder::visitUIToFP(const User &I) {
2396 // UIToFP is never a no-op cast, no need to check
2397 SDValue N = getValue(I.getOperand(0));
2398 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(I.getType());
2399 setValue(&I, DAG.getNode(ISD::UINT_TO_FP, getCurSDLoc(), DestVT, N));
2402 void SelectionDAGBuilder::visitSIToFP(const User &I) {
2403 // SIToFP is never a no-op cast, no need to check
2404 SDValue N = getValue(I.getOperand(0));
2405 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(I.getType());
2406 setValue(&I, DAG.getNode(ISD::SINT_TO_FP, getCurSDLoc(), DestVT, N));
2409 void SelectionDAGBuilder::visitPtrToInt(const User &I) {
2410 // What to do depends on the size of the integer and the size of the pointer.
2411 // We can either truncate, zero extend, or no-op, accordingly.
2412 SDValue N = getValue(I.getOperand(0));
2413 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(I.getType());
2414 setValue(&I, DAG.getZExtOrTrunc(N, getCurSDLoc(), DestVT));
2417 void SelectionDAGBuilder::visitIntToPtr(const User &I) {
2418 // What to do depends on the size of the integer and the size of the pointer.
2419 // We can either truncate, zero extend, or no-op, accordingly.
2420 SDValue N = getValue(I.getOperand(0));
2421 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(I.getType());
2422 setValue(&I, DAG.getZExtOrTrunc(N, getCurSDLoc(), DestVT));
2425 void SelectionDAGBuilder::visitBitCast(const User &I) {
2426 SDValue N = getValue(I.getOperand(0));
2427 SDLoc dl = getCurSDLoc();
2428 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(I.getType());
2430 // BitCast assures us that source and destination are the same size so this is
2431 // either a BITCAST or a no-op.
2432 if (DestVT != N.getValueType())
2433 setValue(&I, DAG.getNode(ISD::BITCAST, dl,
2434 DestVT, N)); // convert types.
2435 // Check if the original LLVM IR Operand was a ConstantInt, because getValue()
2436 // might fold any kind of constant expression to an integer constant and that
2437 // is not what we are looking for. Only regcognize a bitcast of a genuine
2438 // constant integer as an opaque constant.
2439 else if(ConstantInt *C = dyn_cast<ConstantInt>(I.getOperand(0)))
2440 setValue(&I, DAG.getConstant(C->getValue(), dl, DestVT, /*isTarget=*/false,
2443 setValue(&I, N); // noop cast.
2446 void SelectionDAGBuilder::visitAddrSpaceCast(const User &I) {
2447 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2448 const Value *SV = I.getOperand(0);
2449 SDValue N = getValue(SV);
2450 EVT DestVT = TLI.getValueType(I.getType());
2452 unsigned SrcAS = SV->getType()->getPointerAddressSpace();
2453 unsigned DestAS = I.getType()->getPointerAddressSpace();
2455 if (!TLI.isNoopAddrSpaceCast(SrcAS, DestAS))
2456 N = DAG.getAddrSpaceCast(getCurSDLoc(), DestVT, N, SrcAS, DestAS);
2461 void SelectionDAGBuilder::visitInsertElement(const User &I) {
2462 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2463 SDValue InVec = getValue(I.getOperand(0));
2464 SDValue InVal = getValue(I.getOperand(1));
2465 SDValue InIdx = DAG.getSExtOrTrunc(getValue(I.getOperand(2)),
2466 getCurSDLoc(), TLI.getVectorIdxTy());
2467 setValue(&I, DAG.getNode(ISD::INSERT_VECTOR_ELT, getCurSDLoc(),
2468 TLI.getValueType(I.getType()), InVec, InVal, InIdx));
2471 void SelectionDAGBuilder::visitExtractElement(const User &I) {
2472 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2473 SDValue InVec = getValue(I.getOperand(0));
2474 SDValue InIdx = DAG.getSExtOrTrunc(getValue(I.getOperand(1)),
2475 getCurSDLoc(), TLI.getVectorIdxTy());
2476 setValue(&I, DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurSDLoc(),
2477 TLI.getValueType(I.getType()), InVec, InIdx));
2480 // Utility for visitShuffleVector - Return true if every element in Mask,
2481 // beginning from position Pos and ending in Pos+Size, falls within the
2482 // specified sequential range [L, L+Pos). or is undef.
2483 static bool isSequentialInRange(const SmallVectorImpl<int> &Mask,
2484 unsigned Pos, unsigned Size, int Low) {
2485 for (unsigned i = Pos, e = Pos+Size; i != e; ++i, ++Low)
2486 if (Mask[i] >= 0 && Mask[i] != Low)
2491 void SelectionDAGBuilder::visitShuffleVector(const User &I) {
2492 SDValue Src1 = getValue(I.getOperand(0));
2493 SDValue Src2 = getValue(I.getOperand(1));
2495 SmallVector<int, 8> Mask;
2496 ShuffleVectorInst::getShuffleMask(cast<Constant>(I.getOperand(2)), Mask);
2497 unsigned MaskNumElts = Mask.size();
2499 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2500 EVT VT = TLI.getValueType(I.getType());
2501 EVT SrcVT = Src1.getValueType();
2502 unsigned SrcNumElts = SrcVT.getVectorNumElements();
2504 if (SrcNumElts == MaskNumElts) {
2505 setValue(&I, DAG.getVectorShuffle(VT, getCurSDLoc(), Src1, Src2,
2510 // Normalize the shuffle vector since mask and vector length don't match.
2511 if (SrcNumElts < MaskNumElts && MaskNumElts % SrcNumElts == 0) {
2512 // Mask is longer than the source vectors and is a multiple of the source
2513 // vectors. We can use concatenate vector to make the mask and vectors
2515 if (SrcNumElts*2 == MaskNumElts) {
2516 // First check for Src1 in low and Src2 in high
2517 if (isSequentialInRange(Mask, 0, SrcNumElts, 0) &&
2518 isSequentialInRange(Mask, SrcNumElts, SrcNumElts, SrcNumElts)) {
2519 // The shuffle is concatenating two vectors together.
2520 setValue(&I, DAG.getNode(ISD::CONCAT_VECTORS, getCurSDLoc(),
2524 // Then check for Src2 in low and Src1 in high
2525 if (isSequentialInRange(Mask, 0, SrcNumElts, SrcNumElts) &&
2526 isSequentialInRange(Mask, SrcNumElts, SrcNumElts, 0)) {
2527 // The shuffle is concatenating two vectors together.
2528 setValue(&I, DAG.getNode(ISD::CONCAT_VECTORS, getCurSDLoc(),
2534 // Pad both vectors with undefs to make them the same length as the mask.
2535 unsigned NumConcat = MaskNumElts / SrcNumElts;
2536 bool Src1U = Src1.getOpcode() == ISD::UNDEF;
2537 bool Src2U = Src2.getOpcode() == ISD::UNDEF;
2538 SDValue UndefVal = DAG.getUNDEF(SrcVT);
2540 SmallVector<SDValue, 8> MOps1(NumConcat, UndefVal);
2541 SmallVector<SDValue, 8> MOps2(NumConcat, UndefVal);
2545 Src1 = Src1U ? DAG.getUNDEF(VT) : DAG.getNode(ISD::CONCAT_VECTORS,
2546 getCurSDLoc(), VT, MOps1);
2547 Src2 = Src2U ? DAG.getUNDEF(VT) : DAG.getNode(ISD::CONCAT_VECTORS,
2548 getCurSDLoc(), VT, MOps2);
2550 // Readjust mask for new input vector length.
2551 SmallVector<int, 8> MappedOps;
2552 for (unsigned i = 0; i != MaskNumElts; ++i) {
2554 if (Idx >= (int)SrcNumElts)
2555 Idx -= SrcNumElts - MaskNumElts;
2556 MappedOps.push_back(Idx);
2559 setValue(&I, DAG.getVectorShuffle(VT, getCurSDLoc(), Src1, Src2,
2564 if (SrcNumElts > MaskNumElts) {
2565 // Analyze the access pattern of the vector to see if we can extract
2566 // two subvectors and do the shuffle. The analysis is done by calculating
2567 // the range of elements the mask access on both vectors.
2568 int MinRange[2] = { static_cast<int>(SrcNumElts),
2569 static_cast<int>(SrcNumElts)};
2570 int MaxRange[2] = {-1, -1};
2572 for (unsigned i = 0; i != MaskNumElts; ++i) {
2578 if (Idx >= (int)SrcNumElts) {
2582 if (Idx > MaxRange[Input])
2583 MaxRange[Input] = Idx;
2584 if (Idx < MinRange[Input])
2585 MinRange[Input] = Idx;
2588 // Check if the access is smaller than the vector size and can we find
2589 // a reasonable extract index.
2590 int RangeUse[2] = { -1, -1 }; // 0 = Unused, 1 = Extract, -1 = Can not
2592 int StartIdx[2]; // StartIdx to extract from
2593 for (unsigned Input = 0; Input < 2; ++Input) {
2594 if (MinRange[Input] >= (int)SrcNumElts && MaxRange[Input] < 0) {
2595 RangeUse[Input] = 0; // Unused
2596 StartIdx[Input] = 0;
2600 // Find a good start index that is a multiple of the mask length. Then
2601 // see if the rest of the elements are in range.
2602 StartIdx[Input] = (MinRange[Input]/MaskNumElts)*MaskNumElts;
2603 if (MaxRange[Input] - StartIdx[Input] < (int)MaskNumElts &&
2604 StartIdx[Input] + MaskNumElts <= SrcNumElts)
2605 RangeUse[Input] = 1; // Extract from a multiple of the mask length.
2608 if (RangeUse[0] == 0 && RangeUse[1] == 0) {
2609 setValue(&I, DAG.getUNDEF(VT)); // Vectors are not used.
2612 if (RangeUse[0] >= 0 && RangeUse[1] >= 0) {
2613 // Extract appropriate subvector and generate a vector shuffle
2614 for (unsigned Input = 0; Input < 2; ++Input) {
2615 SDValue &Src = Input == 0 ? Src1 : Src2;
2616 if (RangeUse[Input] == 0)
2617 Src = DAG.getUNDEF(VT);
2619 SDLoc dl = getCurSDLoc();
2621 ISD::EXTRACT_SUBVECTOR, dl, VT, Src,
2622 DAG.getConstant(StartIdx[Input], dl, TLI.getVectorIdxTy()));
2626 // Calculate new mask.
2627 SmallVector<int, 8> MappedOps;
2628 for (unsigned i = 0; i != MaskNumElts; ++i) {
2631 if (Idx < (int)SrcNumElts)
2634 Idx -= SrcNumElts + StartIdx[1] - MaskNumElts;
2636 MappedOps.push_back(Idx);
2639 setValue(&I, DAG.getVectorShuffle(VT, getCurSDLoc(), Src1, Src2,
2645 // We can't use either concat vectors or extract subvectors so fall back to
2646 // replacing the shuffle with extract and build vector.
2647 // to insert and build vector.
2648 EVT EltVT = VT.getVectorElementType();
2649 EVT IdxVT = TLI.getVectorIdxTy();
2650 SDLoc dl = getCurSDLoc();
2651 SmallVector<SDValue,8> Ops;
2652 for (unsigned i = 0; i != MaskNumElts; ++i) {
2657 Res = DAG.getUNDEF(EltVT);
2659 SDValue &Src = Idx < (int)SrcNumElts ? Src1 : Src2;
2660 if (Idx >= (int)SrcNumElts) Idx -= SrcNumElts;
2662 Res = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
2663 EltVT, Src, DAG.getConstant(Idx, dl, IdxVT));
2669 setValue(&I, DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops));
2672 void SelectionDAGBuilder::visitInsertValue(const InsertValueInst &I) {
2673 const Value *Op0 = I.getOperand(0);
2674 const Value *Op1 = I.getOperand(1);
2675 Type *AggTy = I.getType();
2676 Type *ValTy = Op1->getType();
2677 bool IntoUndef = isa<UndefValue>(Op0);
2678 bool FromUndef = isa<UndefValue>(Op1);
2680 unsigned LinearIndex = ComputeLinearIndex(AggTy, I.getIndices());
2682 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2683 SmallVector<EVT, 4> AggValueVTs;
2684 ComputeValueVTs(TLI, AggTy, AggValueVTs);
2685 SmallVector<EVT, 4> ValValueVTs;
2686 ComputeValueVTs(TLI, ValTy, ValValueVTs);
2688 unsigned NumAggValues = AggValueVTs.size();
2689 unsigned NumValValues = ValValueVTs.size();
2690 SmallVector<SDValue, 4> Values(NumAggValues);
2692 // Ignore an insertvalue that produces an empty object
2693 if (!NumAggValues) {
2694 setValue(&I, DAG.getUNDEF(MVT(MVT::Other)));
2698 SDValue Agg = getValue(Op0);
2700 // Copy the beginning value(s) from the original aggregate.
2701 for (; i != LinearIndex; ++i)
2702 Values[i] = IntoUndef ? DAG.getUNDEF(AggValueVTs[i]) :
2703 SDValue(Agg.getNode(), Agg.getResNo() + i);
2704 // Copy values from the inserted value(s).
2706 SDValue Val = getValue(Op1);
2707 for (; i != LinearIndex + NumValValues; ++i)
2708 Values[i] = FromUndef ? DAG.getUNDEF(AggValueVTs[i]) :
2709 SDValue(Val.getNode(), Val.getResNo() + i - LinearIndex);
2711 // Copy remaining value(s) from the original aggregate.
2712 for (; i != NumAggValues; ++i)
2713 Values[i] = IntoUndef ? DAG.getUNDEF(AggValueVTs[i]) :
2714 SDValue(Agg.getNode(), Agg.getResNo() + i);
2716 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(),
2717 DAG.getVTList(AggValueVTs), Values));
2720 void SelectionDAGBuilder::visitExtractValue(const ExtractValueInst &I) {
2721 const Value *Op0 = I.getOperand(0);
2722 Type *AggTy = Op0->getType();
2723 Type *ValTy = I.getType();
2724 bool OutOfUndef = isa<UndefValue>(Op0);
2726 unsigned LinearIndex = ComputeLinearIndex(AggTy, I.getIndices());
2728 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2729 SmallVector<EVT, 4> ValValueVTs;
2730 ComputeValueVTs(TLI, ValTy, ValValueVTs);
2732 unsigned NumValValues = ValValueVTs.size();
2734 // Ignore a extractvalue that produces an empty object
2735 if (!NumValValues) {
2736 setValue(&I, DAG.getUNDEF(MVT(MVT::Other)));
2740 SmallVector<SDValue, 4> Values(NumValValues);
2742 SDValue Agg = getValue(Op0);
2743 // Copy out the selected value(s).
2744 for (unsigned i = LinearIndex; i != LinearIndex + NumValValues; ++i)
2745 Values[i - LinearIndex] =
2747 DAG.getUNDEF(Agg.getNode()->getValueType(Agg.getResNo() + i)) :
2748 SDValue(Agg.getNode(), Agg.getResNo() + i);
2750 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(),
2751 DAG.getVTList(ValValueVTs), Values));
2754 void SelectionDAGBuilder::visitGetElementPtr(const User &I) {
2755 Value *Op0 = I.getOperand(0);
2756 // Note that the pointer operand may be a vector of pointers. Take the scalar
2757 // element which holds a pointer.
2758 Type *Ty = Op0->getType()->getScalarType();
2759 unsigned AS = Ty->getPointerAddressSpace();
2760 SDValue N = getValue(Op0);
2761 SDLoc dl = getCurSDLoc();
2763 for (GetElementPtrInst::const_op_iterator OI = I.op_begin()+1, E = I.op_end();
2765 const Value *Idx = *OI;
2766 if (StructType *StTy = dyn_cast<StructType>(Ty)) {
2767 unsigned Field = cast<Constant>(Idx)->getUniqueInteger().getZExtValue();
2770 uint64_t Offset = DL->getStructLayout(StTy)->getElementOffset(Field);
2771 N = DAG.getNode(ISD::ADD, dl, N.getValueType(), N,
2772 DAG.getConstant(Offset, dl, N.getValueType()));
2775 Ty = StTy->getElementType(Field);
2777 Ty = cast<SequentialType>(Ty)->getElementType();
2778 MVT PtrTy = DAG.getTargetLoweringInfo().getPointerTy(AS);
2779 unsigned PtrSize = PtrTy.getSizeInBits();
2780 APInt ElementSize(PtrSize, DL->getTypeAllocSize(Ty));
2782 // If this is a constant subscript, handle it quickly.
2783 if (const auto *CI = dyn_cast<ConstantInt>(Idx)) {
2786 APInt Offs = ElementSize * CI->getValue().sextOrTrunc(PtrSize);
2787 SDValue OffsVal = DAG.getConstant(Offs, dl, PtrTy);
2788 N = DAG.getNode(ISD::ADD, dl, N.getValueType(), N, OffsVal);
2792 // N = N + Idx * ElementSize;
2793 SDValue IdxN = getValue(Idx);
2795 // If the index is smaller or larger than intptr_t, truncate or extend
2797 IdxN = DAG.getSExtOrTrunc(IdxN, dl, N.getValueType());
2799 // If this is a multiply by a power of two, turn it into a shl
2800 // immediately. This is a very common case.
2801 if (ElementSize != 1) {
2802 if (ElementSize.isPowerOf2()) {
2803 unsigned Amt = ElementSize.logBase2();
2804 IdxN = DAG.getNode(ISD::SHL, dl,
2805 N.getValueType(), IdxN,
2806 DAG.getConstant(Amt, dl, IdxN.getValueType()));
2808 SDValue Scale = DAG.getConstant(ElementSize, dl, IdxN.getValueType());
2809 IdxN = DAG.getNode(ISD::MUL, dl,
2810 N.getValueType(), IdxN, Scale);
2814 N = DAG.getNode(ISD::ADD, dl,
2815 N.getValueType(), N, IdxN);
2822 void SelectionDAGBuilder::visitAlloca(const AllocaInst &I) {
2823 // If this is a fixed sized alloca in the entry block of the function,
2824 // allocate it statically on the stack.
2825 if (FuncInfo.StaticAllocaMap.count(&I))
2826 return; // getValue will auto-populate this.
2828 SDLoc dl = getCurSDLoc();
2829 Type *Ty = I.getAllocatedType();
2830 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2831 uint64_t TySize = TLI.getDataLayout()->getTypeAllocSize(Ty);
2833 std::max((unsigned)TLI.getDataLayout()->getPrefTypeAlignment(Ty),
2836 SDValue AllocSize = getValue(I.getArraySize());
2838 EVT IntPtr = TLI.getPointerTy();
2839 if (AllocSize.getValueType() != IntPtr)
2840 AllocSize = DAG.getZExtOrTrunc(AllocSize, dl, IntPtr);
2842 AllocSize = DAG.getNode(ISD::MUL, dl, IntPtr,
2844 DAG.getConstant(TySize, dl, IntPtr));
2846 // Handle alignment. If the requested alignment is less than or equal to
2847 // the stack alignment, ignore it. If the size is greater than or equal to
2848 // the stack alignment, we note this in the DYNAMIC_STACKALLOC node.
2849 unsigned StackAlign =
2850 DAG.getSubtarget().getFrameLowering()->getStackAlignment();
2851 if (Align <= StackAlign)
2854 // Round the size of the allocation up to the stack alignment size
2855 // by add SA-1 to the size.
2856 AllocSize = DAG.getNode(ISD::ADD, dl,
2857 AllocSize.getValueType(), AllocSize,
2858 DAG.getIntPtrConstant(StackAlign - 1, dl));
2860 // Mask out the low bits for alignment purposes.
2861 AllocSize = DAG.getNode(ISD::AND, dl,
2862 AllocSize.getValueType(), AllocSize,
2863 DAG.getIntPtrConstant(~(uint64_t)(StackAlign - 1),
2866 SDValue Ops[] = { getRoot(), AllocSize, DAG.getIntPtrConstant(Align, dl) };
2867 SDVTList VTs = DAG.getVTList(AllocSize.getValueType(), MVT::Other);
2868 SDValue DSA = DAG.getNode(ISD::DYNAMIC_STACKALLOC, dl, VTs, Ops);
2870 DAG.setRoot(DSA.getValue(1));
2872 assert(FuncInfo.MF->getFrameInfo()->hasVarSizedObjects());
2875 void SelectionDAGBuilder::visitLoad(const LoadInst &I) {
2877 return visitAtomicLoad(I);
2879 const Value *SV = I.getOperand(0);
2880 SDValue Ptr = getValue(SV);
2882 Type *Ty = I.getType();
2884 bool isVolatile = I.isVolatile();
2885 bool isNonTemporal = I.getMetadata(LLVMContext::MD_nontemporal) != nullptr;
2887 // The IR notion of invariant_load only guarantees that all *non-faulting*
2888 // invariant loads result in the same value. The MI notion of invariant load
2889 // guarantees that the load can be legally moved to any location within its
2890 // containing function. The MI notion of invariant_load is stronger than the
2891 // IR notion of invariant_load -- an MI invariant_load is an IR invariant_load
2892 // with a guarantee that the location being loaded from is dereferenceable
2893 // throughout the function's lifetime.
2895 bool isInvariant = I.getMetadata(LLVMContext::MD_invariant_load) != nullptr &&
2896 isDereferenceablePointer(SV, *DAG.getTarget().getDataLayout());
2897 unsigned Alignment = I.getAlignment();
2900 I.getAAMetadata(AAInfo);
2901 const MDNode *Ranges = I.getMetadata(LLVMContext::MD_range);
2903 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2904 SmallVector<EVT, 4> ValueVTs;
2905 SmallVector<uint64_t, 4> Offsets;
2906 ComputeValueVTs(TLI, Ty, ValueVTs, &Offsets);
2907 unsigned NumValues = ValueVTs.size();
2912 bool ConstantMemory = false;
2913 if (isVolatile || NumValues > MaxParallelChains)
2914 // Serialize volatile loads with other side effects.
2916 else if (AA->pointsToConstantMemory(
2917 AliasAnalysis::Location(SV, AA->getTypeStoreSize(Ty), AAInfo))) {
2918 // Do not serialize (non-volatile) loads of constant memory with anything.
2919 Root = DAG.getEntryNode();
2920 ConstantMemory = true;
2922 // Do not serialize non-volatile loads against each other.
2923 Root = DAG.getRoot();
2926 SDLoc dl = getCurSDLoc();
2929 Root = TLI.prepareVolatileOrAtomicLoad(Root, dl, DAG);
2931 SmallVector<SDValue, 4> Values(NumValues);
2932 SmallVector<SDValue, 4> Chains(std::min(unsigned(MaxParallelChains),
2934 EVT PtrVT = Ptr.getValueType();
2935 unsigned ChainI = 0;
2936 for (unsigned i = 0; i != NumValues; ++i, ++ChainI) {
2937 // Serializing loads here may result in excessive register pressure, and
2938 // TokenFactor places arbitrary choke points on the scheduler. SD scheduling
2939 // could recover a bit by hoisting nodes upward in the chain by recognizing
2940 // they are side-effect free or do not alias. The optimizer should really
2941 // avoid this case by converting large object/array copies to llvm.memcpy
2942 // (MaxParallelChains should always remain as failsafe).
2943 if (ChainI == MaxParallelChains) {
2944 assert(PendingLoads.empty() && "PendingLoads must be serialized first");
2945 SDValue Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2946 makeArrayRef(Chains.data(), ChainI));
2950 SDValue A = DAG.getNode(ISD::ADD, dl,
2952 DAG.getConstant(Offsets[i], dl, PtrVT));
2953 SDValue L = DAG.getLoad(ValueVTs[i], dl, Root,
2954 A, MachinePointerInfo(SV, Offsets[i]), isVolatile,
2955 isNonTemporal, isInvariant, Alignment, AAInfo,
2959 Chains[ChainI] = L.getValue(1);
2962 if (!ConstantMemory) {
2963 SDValue Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2964 makeArrayRef(Chains.data(), ChainI));
2968 PendingLoads.push_back(Chain);
2971 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, dl,
2972 DAG.getVTList(ValueVTs), Values));
2975 void SelectionDAGBuilder::visitStore(const StoreInst &I) {
2977 return visitAtomicStore(I);
2979 const Value *SrcV = I.getOperand(0);
2980 const Value *PtrV = I.getOperand(1);
2982 SmallVector<EVT, 4> ValueVTs;
2983 SmallVector<uint64_t, 4> Offsets;
2984 ComputeValueVTs(DAG.getTargetLoweringInfo(), SrcV->getType(),
2985 ValueVTs, &Offsets);
2986 unsigned NumValues = ValueVTs.size();
2990 // Get the lowered operands. Note that we do this after
2991 // checking if NumResults is zero, because with zero results
2992 // the operands won't have values in the map.
2993 SDValue Src = getValue(SrcV);
2994 SDValue Ptr = getValue(PtrV);
2996 SDValue Root = getRoot();
2997 SmallVector<SDValue, 4> Chains(std::min(unsigned(MaxParallelChains),
2999 EVT PtrVT = Ptr.getValueType();
3000 bool isVolatile = I.isVolatile();
3001 bool isNonTemporal = I.getMetadata(LLVMContext::MD_nontemporal) != nullptr;
3002 unsigned Alignment = I.getAlignment();
3003 SDLoc dl = getCurSDLoc();
3006 I.getAAMetadata(AAInfo);
3008 unsigned ChainI = 0;
3009 for (unsigned i = 0; i != NumValues; ++i, ++ChainI) {
3010 // See visitLoad comments.
3011 if (ChainI == MaxParallelChains) {
3012 SDValue Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
3013 makeArrayRef(Chains.data(), ChainI));
3017 SDValue Add = DAG.getNode(ISD::ADD, dl, PtrVT, Ptr,
3018 DAG.getConstant(Offsets[i], dl, PtrVT));
3019 SDValue St = DAG.getStore(Root, dl,
3020 SDValue(Src.getNode(), Src.getResNo() + i),
3021 Add, MachinePointerInfo(PtrV, Offsets[i]),
3022 isVolatile, isNonTemporal, Alignment, AAInfo);
3023 Chains[ChainI] = St;
3026 SDValue StoreNode = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
3027 makeArrayRef(Chains.data(), ChainI));
3028 DAG.setRoot(StoreNode);
3031 void SelectionDAGBuilder::visitMaskedStore(const CallInst &I) {
3032 SDLoc sdl = getCurSDLoc();
3034 // llvm.masked.store.*(Src0, Ptr, alignemt, Mask)
3035 Value *PtrOperand = I.getArgOperand(1);
3036 SDValue Ptr = getValue(PtrOperand);
3037 SDValue Src0 = getValue(I.getArgOperand(0));
3038 SDValue Mask = getValue(I.getArgOperand(3));
3039 EVT VT = Src0.getValueType();
3040 unsigned Alignment = (cast<ConstantInt>(I.getArgOperand(2)))->getZExtValue();
3042 Alignment = DAG.getEVTAlignment(VT);
3045 I.getAAMetadata(AAInfo);
3047 MachineMemOperand *MMO =
3048 DAG.getMachineFunction().
3049 getMachineMemOperand(MachinePointerInfo(PtrOperand),
3050 MachineMemOperand::MOStore, VT.getStoreSize(),
3052 SDValue StoreNode = DAG.getMaskedStore(getRoot(), sdl, Src0, Ptr, Mask, VT,
3054 DAG.setRoot(StoreNode);
3055 setValue(&I, StoreNode);
3058 // Gather/scatter receive a vector of pointers.
3059 // This vector of pointers may be represented as a base pointer + vector of
3060 // indices, it depends on GEP and instruction preceeding GEP
3061 // that calculates indices
3062 static bool getUniformBase(Value *& Ptr, SDValue& Base, SDValue& Index,
3063 SelectionDAGBuilder* SDB) {
3065 assert (Ptr->getType()->isVectorTy() && "Uexpected pointer type");
3066 GetElementPtrInst *Gep = dyn_cast<GetElementPtrInst>(Ptr);
3067 if (!Gep || Gep->getNumOperands() > 2)
3069 ShuffleVectorInst *ShuffleInst =
3070 dyn_cast<ShuffleVectorInst>(Gep->getPointerOperand());
3071 if (!ShuffleInst || !ShuffleInst->getMask()->isNullValue() ||
3072 cast<Instruction>(ShuffleInst->getOperand(0))->getOpcode() !=
3073 Instruction::InsertElement)
3076 Ptr = cast<InsertElementInst>(ShuffleInst->getOperand(0))->getOperand(1);
3078 SelectionDAG& DAG = SDB->DAG;
3079 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3080 // Check is the Ptr is inside current basic block
3081 // If not, look for the shuffle instruction
3082 if (SDB->findValue(Ptr))
3083 Base = SDB->getValue(Ptr);
3084 else if (SDB->findValue(ShuffleInst)) {
3085 SDValue ShuffleNode = SDB->getValue(ShuffleInst);
3086 SDLoc sdl = ShuffleNode;
3087 Base = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, sdl,
3088 ShuffleNode.getValueType().getScalarType(), ShuffleNode,
3089 DAG.getConstant(0, sdl, TLI.getVectorIdxTy()));
3090 SDB->setValue(Ptr, Base);
3095 Value *IndexVal = Gep->getOperand(1);
3096 if (SDB->findValue(IndexVal)) {
3097 Index = SDB->getValue(IndexVal);
3099 if (SExtInst* Sext = dyn_cast<SExtInst>(IndexVal)) {
3100 IndexVal = Sext->getOperand(0);
3101 if (SDB->findValue(IndexVal))
3102 Index = SDB->getValue(IndexVal);
3109 void SelectionDAGBuilder::visitMaskedScatter(const CallInst &I) {
3110 SDLoc sdl = getCurSDLoc();
3112 // llvm.masked.scatter.*(Src0, Ptrs, alignemt, Mask)
3113 Value *Ptr = I.getArgOperand(1);
3114 SDValue Src0 = getValue(I.getArgOperand(0));
3115 SDValue Mask = getValue(I.getArgOperand(3));
3116 EVT VT = Src0.getValueType();
3117 unsigned Alignment = (cast<ConstantInt>(I.getArgOperand(2)))->getZExtValue();
3119 Alignment = DAG.getEVTAlignment(VT);
3120 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3123 I.getAAMetadata(AAInfo);
3127 Value *BasePtr = Ptr;
3128 bool UniformBase = getUniformBase(BasePtr, Base, Index, this);
3130 Value *MemOpBasePtr = UniformBase ? BasePtr : nullptr;
3131 MachineMemOperand *MMO = DAG.getMachineFunction().
3132 getMachineMemOperand(MachinePointerInfo(MemOpBasePtr),
3133 MachineMemOperand::MOStore, VT.getStoreSize(),
3136 Base = DAG.getTargetConstant(0, sdl, TLI.getPointerTy());
3137 Index = getValue(Ptr);
3139 SDValue Ops[] = { getRoot(), Src0, Mask, Base, Index };
3140 SDValue Scatter = DAG.getMaskedScatter(DAG.getVTList(MVT::Other), VT, sdl,
3142 DAG.setRoot(Scatter);
3143 setValue(&I, Scatter);
3146 void SelectionDAGBuilder::visitMaskedLoad(const CallInst &I) {
3147 SDLoc sdl = getCurSDLoc();
3149 // @llvm.masked.load.*(Ptr, alignment, Mask, Src0)
3150 Value *PtrOperand = I.getArgOperand(0);
3151 SDValue Ptr = getValue(PtrOperand);
3152 SDValue Src0 = getValue(I.getArgOperand(3));
3153 SDValue Mask = getValue(I.getArgOperand(2));
3155 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3156 EVT VT = TLI.getValueType(I.getType());
3157 unsigned Alignment = (cast<ConstantInt>(I.getArgOperand(1)))->getZExtValue();
3159 Alignment = DAG.getEVTAlignment(VT);
3162 I.getAAMetadata(AAInfo);
3163 const MDNode *Ranges = I.getMetadata(LLVMContext::MD_range);
3165 SDValue InChain = DAG.getRoot();
3166 if (AA->pointsToConstantMemory(
3167 AliasAnalysis::Location(PtrOperand,
3168 AA->getTypeStoreSize(I.getType()),
3170 // Do not serialize (non-volatile) loads of constant memory with anything.
3171 InChain = DAG.getEntryNode();
3174 MachineMemOperand *MMO =
3175 DAG.getMachineFunction().
3176 getMachineMemOperand(MachinePointerInfo(PtrOperand),
3177 MachineMemOperand::MOLoad, VT.getStoreSize(),
3178 Alignment, AAInfo, Ranges);
3180 SDValue Load = DAG.getMaskedLoad(VT, sdl, InChain, Ptr, Mask, Src0, VT, MMO,
3182 SDValue OutChain = Load.getValue(1);
3183 DAG.setRoot(OutChain);
3187 void SelectionDAGBuilder::visitMaskedGather(const CallInst &I) {
3188 SDLoc sdl = getCurSDLoc();
3190 // @llvm.masked.gather.*(Ptrs, alignment, Mask, Src0)
3191 Value *Ptr = I.getArgOperand(0);
3192 SDValue Src0 = getValue(I.getArgOperand(3));
3193 SDValue Mask = getValue(I.getArgOperand(2));
3195 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3196 EVT VT = TLI.getValueType(I.getType());
3197 unsigned Alignment = (cast<ConstantInt>(I.getArgOperand(1)))->getZExtValue();
3199 Alignment = DAG.getEVTAlignment(VT);
3202 I.getAAMetadata(AAInfo);
3203 const MDNode *Ranges = I.getMetadata(LLVMContext::MD_range);
3205 SDValue Root = DAG.getRoot();
3208 Value *BasePtr = Ptr;
3209 bool UniformBase = getUniformBase(BasePtr, Base, Index, this);
3210 bool ConstantMemory = false;
3211 if (UniformBase && AA->pointsToConstantMemory(
3212 AliasAnalysis::Location(BasePtr,
3213 AA->getTypeStoreSize(I.getType()),
3215 // Do not serialize (non-volatile) loads of constant memory with anything.
3216 Root = DAG.getEntryNode();
3217 ConstantMemory = true;
3220 MachineMemOperand *MMO =
3221 DAG.getMachineFunction().
3222 getMachineMemOperand(MachinePointerInfo(UniformBase ? BasePtr : nullptr),
3223 MachineMemOperand::MOLoad, VT.getStoreSize(),
3224 Alignment, AAInfo, Ranges);
3227 Base = DAG.getTargetConstant(0, sdl, TLI.getPointerTy());
3228 Index = getValue(Ptr);
3230 SDValue Ops[] = { Root, Src0, Mask, Base, Index };
3231 SDValue Gather = DAG.getMaskedGather(DAG.getVTList(VT, MVT::Other), VT, sdl,
3234 SDValue OutChain = Gather.getValue(1);
3235 if (!ConstantMemory)
3236 PendingLoads.push_back(OutChain);
3237 setValue(&I, Gather);
3240 void SelectionDAGBuilder::visitAtomicCmpXchg(const AtomicCmpXchgInst &I) {
3241 SDLoc dl = getCurSDLoc();
3242 AtomicOrdering SuccessOrder = I.getSuccessOrdering();
3243 AtomicOrdering FailureOrder = I.getFailureOrdering();
3244 SynchronizationScope Scope = I.getSynchScope();
3246 SDValue InChain = getRoot();
3248 MVT MemVT = getValue(I.getCompareOperand()).getSimpleValueType();
3249 SDVTList VTs = DAG.getVTList(MemVT, MVT::i1, MVT::Other);
3250 SDValue L = DAG.getAtomicCmpSwap(
3251 ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, dl, MemVT, VTs, InChain,
3252 getValue(I.getPointerOperand()), getValue(I.getCompareOperand()),
3253 getValue(I.getNewValOperand()), MachinePointerInfo(I.getPointerOperand()),
3254 /*Alignment=*/ 0, SuccessOrder, FailureOrder, Scope);
3256 SDValue OutChain = L.getValue(2);
3259 DAG.setRoot(OutChain);
3262 void SelectionDAGBuilder::visitAtomicRMW(const AtomicRMWInst &I) {
3263 SDLoc dl = getCurSDLoc();
3265 switch (I.getOperation()) {
3266 default: llvm_unreachable("Unknown atomicrmw operation");
3267 case AtomicRMWInst::Xchg: NT = ISD::ATOMIC_SWAP; break;
3268 case AtomicRMWInst::Add: NT = ISD::ATOMIC_LOAD_ADD; break;
3269 case AtomicRMWInst::Sub: NT = ISD::ATOMIC_LOAD_SUB; break;
3270 case AtomicRMWInst::And: NT = ISD::ATOMIC_LOAD_AND; break;
3271 case AtomicRMWInst::Nand: NT = ISD::ATOMIC_LOAD_NAND; break;
3272 case AtomicRMWInst::Or: NT = ISD::ATOMIC_LOAD_OR; break;
3273 case AtomicRMWInst::Xor: NT = ISD::ATOMIC_LOAD_XOR; break;
3274 case AtomicRMWInst::Max: NT = ISD::ATOMIC_LOAD_MAX; break;
3275 case AtomicRMWInst::Min: NT = ISD::ATOMIC_LOAD_MIN; break;
3276 case AtomicRMWInst::UMax: NT = ISD::ATOMIC_LOAD_UMAX; break;
3277 case AtomicRMWInst::UMin: NT = ISD::ATOMIC_LOAD_UMIN; break;
3279 AtomicOrdering Order = I.getOrdering();
3280 SynchronizationScope Scope = I.getSynchScope();
3282 SDValue InChain = getRoot();
3285 DAG.getAtomic(NT, dl,
3286 getValue(I.getValOperand()).getSimpleValueType(),
3288 getValue(I.getPointerOperand()),
3289 getValue(I.getValOperand()),
3290 I.getPointerOperand(),
3291 /* Alignment=*/ 0, Order, Scope);
3293 SDValue OutChain = L.getValue(1);
3296 DAG.setRoot(OutChain);
3299 void SelectionDAGBuilder::visitFence(const FenceInst &I) {
3300 SDLoc dl = getCurSDLoc();
3301 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3304 Ops[1] = DAG.getConstant(I.getOrdering(), dl, TLI.getPointerTy());
3305 Ops[2] = DAG.getConstant(I.getSynchScope(), dl, TLI.getPointerTy());
3306 DAG.setRoot(DAG.getNode(ISD::ATOMIC_FENCE, dl, MVT::Other, Ops));
3309 void SelectionDAGBuilder::visitAtomicLoad(const LoadInst &I) {
3310 SDLoc dl = getCurSDLoc();
3311 AtomicOrdering Order = I.getOrdering();
3312 SynchronizationScope Scope = I.getSynchScope();
3314 SDValue InChain = getRoot();
3316 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3317 EVT VT = TLI.getValueType(I.getType());
3319 if (I.getAlignment() < VT.getSizeInBits() / 8)
3320 report_fatal_error("Cannot generate unaligned atomic load");
3322 MachineMemOperand *MMO =
3323 DAG.getMachineFunction().
3324 getMachineMemOperand(MachinePointerInfo(I.getPointerOperand()),
3325 MachineMemOperand::MOVolatile |
3326 MachineMemOperand::MOLoad,
3328 I.getAlignment() ? I.getAlignment() :
3329 DAG.getEVTAlignment(VT));
3331 InChain = TLI.prepareVolatileOrAtomicLoad(InChain, dl, DAG);
3333 DAG.getAtomic(ISD::ATOMIC_LOAD, dl, VT, VT, InChain,
3334 getValue(I.getPointerOperand()), MMO,
3337 SDValue OutChain = L.getValue(1);
3340 DAG.setRoot(OutChain);
3343 void SelectionDAGBuilder::visitAtomicStore(const StoreInst &I) {
3344 SDLoc dl = getCurSDLoc();
3346 AtomicOrdering Order = I.getOrdering();
3347 SynchronizationScope Scope = I.getSynchScope();
3349 SDValue InChain = getRoot();
3351 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3352 EVT VT = TLI.getValueType(I.getValueOperand()->getType());
3354 if (I.getAlignment() < VT.getSizeInBits() / 8)
3355 report_fatal_error("Cannot generate unaligned atomic store");
3358 DAG.getAtomic(ISD::ATOMIC_STORE, dl, VT,
3360 getValue(I.getPointerOperand()),
3361 getValue(I.getValueOperand()),
3362 I.getPointerOperand(), I.getAlignment(),
3365 DAG.setRoot(OutChain);
3368 /// visitTargetIntrinsic - Lower a call of a target intrinsic to an INTRINSIC
3370 void SelectionDAGBuilder::visitTargetIntrinsic(const CallInst &I,
3371 unsigned Intrinsic) {
3372 bool HasChain = !I.doesNotAccessMemory();
3373 bool OnlyLoad = HasChain && I.onlyReadsMemory();
3375 // Build the operand list.
3376 SmallVector<SDValue, 8> Ops;
3377 if (HasChain) { // If this intrinsic has side-effects, chainify it.
3379 // We don't need to serialize loads against other loads.
3380 Ops.push_back(DAG.getRoot());
3382 Ops.push_back(getRoot());
3386 // Info is set by getTgtMemInstrinsic
3387 TargetLowering::IntrinsicInfo Info;
3388 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3389 bool IsTgtIntrinsic = TLI.getTgtMemIntrinsic(Info, I, Intrinsic);
3391 // Add the intrinsic ID as an integer operand if it's not a target intrinsic.
3392 if (!IsTgtIntrinsic || Info.opc == ISD::INTRINSIC_VOID ||
3393 Info.opc == ISD::INTRINSIC_W_CHAIN)
3394 Ops.push_back(DAG.getTargetConstant(Intrinsic, getCurSDLoc(),
3395 TLI.getPointerTy()));
3397 // Add all operands of the call to the operand list.
3398 for (unsigned i = 0, e = I.getNumArgOperands(); i != e; ++i) {
3399 SDValue Op = getValue(I.getArgOperand(i));
3403 SmallVector<EVT, 4> ValueVTs;
3404 ComputeValueVTs(TLI, I.getType(), ValueVTs);
3407 ValueVTs.push_back(MVT::Other);
3409 SDVTList VTs = DAG.getVTList(ValueVTs);
3413 if (IsTgtIntrinsic) {
3414 // This is target intrinsic that touches memory
3415 Result = DAG.getMemIntrinsicNode(Info.opc, getCurSDLoc(),
3416 VTs, Ops, Info.memVT,
3417 MachinePointerInfo(Info.ptrVal, Info.offset),
3418 Info.align, Info.vol,
3419 Info.readMem, Info.writeMem, Info.size);
3420 } else if (!HasChain) {
3421 Result = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, getCurSDLoc(), VTs, Ops);
3422 } else if (!I.getType()->isVoidTy()) {
3423 Result = DAG.getNode(ISD::INTRINSIC_W_CHAIN, getCurSDLoc(), VTs, Ops);
3425 Result = DAG.getNode(ISD::INTRINSIC_VOID, getCurSDLoc(), VTs, Ops);
3429 SDValue Chain = Result.getValue(Result.getNode()->getNumValues()-1);
3431 PendingLoads.push_back(Chain);
3436 if (!I.getType()->isVoidTy()) {
3437 if (VectorType *PTy = dyn_cast<VectorType>(I.getType())) {
3438 EVT VT = TLI.getValueType(PTy);
3439 Result = DAG.getNode(ISD::BITCAST, getCurSDLoc(), VT, Result);
3442 setValue(&I, Result);
3446 /// GetSignificand - Get the significand and build it into a floating-point
3447 /// number with exponent of 1:
3449 /// Op = (Op & 0x007fffff) | 0x3f800000;
3451 /// where Op is the hexadecimal representation of floating point value.
3453 GetSignificand(SelectionDAG &DAG, SDValue Op, SDLoc dl) {
3454 SDValue t1 = DAG.getNode(ISD::AND, dl, MVT::i32, Op,
3455 DAG.getConstant(0x007fffff, dl, MVT::i32));
3456 SDValue t2 = DAG.getNode(ISD::OR, dl, MVT::i32, t1,
3457 DAG.getConstant(0x3f800000, dl, MVT::i32));
3458 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, t2);
3461 /// GetExponent - Get the exponent:
3463 /// (float)(int)(((Op & 0x7f800000) >> 23) - 127);
3465 /// where Op is the hexadecimal representation of floating point value.
3467 GetExponent(SelectionDAG &DAG, SDValue Op, const TargetLowering &TLI,
3469 SDValue t0 = DAG.getNode(ISD::AND, dl, MVT::i32, Op,
3470 DAG.getConstant(0x7f800000, dl, MVT::i32));
3471 SDValue t1 = DAG.getNode(ISD::SRL, dl, MVT::i32, t0,
3472 DAG.getConstant(23, dl, TLI.getPointerTy()));
3473 SDValue t2 = DAG.getNode(ISD::SUB, dl, MVT::i32, t1,
3474 DAG.getConstant(127, dl, MVT::i32));
3475 return DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, t2);
3478 /// getF32Constant - Get 32-bit floating point constant.
3480 getF32Constant(SelectionDAG &DAG, unsigned Flt, SDLoc dl) {
3481 return DAG.getConstantFP(APFloat(APFloat::IEEEsingle, APInt(32, Flt)), dl,
3485 static SDValue getLimitedPrecisionExp2(SDValue t0, SDLoc dl,
3486 SelectionDAG &DAG) {
3487 // IntegerPartOfX = ((int32_t)(t0);
3488 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, t0);
3490 // FractionalPartOfX = t0 - (float)IntegerPartOfX;
3491 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX);
3492 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, t1);
3494 // IntegerPartOfX <<= 23;
3495 IntegerPartOfX = DAG.getNode(
3496 ISD::SHL, dl, MVT::i32, IntegerPartOfX,
3497 DAG.getConstant(23, dl, DAG.getTargetLoweringInfo().getPointerTy()));
3499 SDValue TwoToFractionalPartOfX;
3500 if (LimitFloatPrecision <= 6) {
3501 // For floating-point precision of 6:
3503 // TwoToFractionalPartOfX =
3505 // (0.735607626f + 0.252464424f * x) * x;
3507 // error 0.0144103317, which is 6 bits
3508 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3509 getF32Constant(DAG, 0x3e814304, dl));
3510 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3511 getF32Constant(DAG, 0x3f3c50c8, dl));
3512 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3513 TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3514 getF32Constant(DAG, 0x3f7f5e7e, dl));
3515 } else if (LimitFloatPrecision <= 12) {
3516 // For floating-point precision of 12:
3518 // TwoToFractionalPartOfX =
3521 // (0.224338339f + 0.792043434e-1f * x) * x) * x;
3523 // error 0.000107046256, which is 13 to 14 bits
3524 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3525 getF32Constant(DAG, 0x3da235e3, dl));
3526 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3527 getF32Constant(DAG, 0x3e65b8f3, dl));
3528 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3529 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3530 getF32Constant(DAG, 0x3f324b07, dl));
3531 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3532 TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3533 getF32Constant(DAG, 0x3f7ff8fd, dl));
3534 } else { // LimitFloatPrecision <= 18
3535 // For floating-point precision of 18:
3537 // TwoToFractionalPartOfX =
3541 // (0.554906021e-1f +
3542 // (0.961591928e-2f +
3543 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x;
3544 // error 2.47208000*10^(-7), which is better than 18 bits
3545 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3546 getF32Constant(DAG, 0x3924b03e, dl));
3547 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3548 getF32Constant(DAG, 0x3ab24b87, dl));
3549 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3550 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3551 getF32Constant(DAG, 0x3c1d8c17, dl));
3552 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3553 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3554 getF32Constant(DAG, 0x3d634a1d, dl));
3555 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3556 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3557 getF32Constant(DAG, 0x3e75fe14, dl));
3558 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3559 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10,
3560 getF32Constant(DAG, 0x3f317234, dl));
3561 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X);
3562 TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t12,
3563 getF32Constant(DAG, 0x3f800000, dl));
3566 // Add the exponent into the result in integer domain.
3567 SDValue t13 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, TwoToFractionalPartOfX);
3568 return DAG.getNode(ISD::BITCAST, dl, MVT::f32,
3569 DAG.getNode(ISD::ADD, dl, MVT::i32, t13, IntegerPartOfX));
3572 /// expandExp - Lower an exp intrinsic. Handles the special sequences for
3573 /// limited-precision mode.
3574 static SDValue expandExp(SDLoc dl, SDValue Op, SelectionDAG &DAG,
3575 const TargetLowering &TLI) {
3576 if (Op.getValueType() == MVT::f32 &&
3577 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3579 // Put the exponent in the right bit position for later addition to the
3582 // #define LOG2OFe 1.4426950f
3583 // t0 = Op * LOG2OFe
3584 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, Op,
3585 getF32Constant(DAG, 0x3fb8aa3b, dl));
3586 return getLimitedPrecisionExp2(t0, dl, DAG);
3589 // No special expansion.
3590 return DAG.getNode(ISD::FEXP, dl, Op.getValueType(), Op);
3593 /// expandLog - Lower a log intrinsic. Handles the special sequences for
3594 /// limited-precision mode.
3595 static SDValue expandLog(SDLoc dl, SDValue Op, SelectionDAG &DAG,
3596 const TargetLowering &TLI) {
3597 if (Op.getValueType() == MVT::f32 &&
3598 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3599 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op);
3601 // Scale the exponent by log(2) [0.69314718f].
3602 SDValue Exp = GetExponent(DAG, Op1, TLI, dl);
3603 SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp,
3604 getF32Constant(DAG, 0x3f317218, dl));
3606 // Get the significand and build it into a floating-point number with
3608 SDValue X = GetSignificand(DAG, Op1, dl);
3610 SDValue LogOfMantissa;
3611 if (LimitFloatPrecision <= 6) {
3612 // For floating-point precision of 6:
3616 // (1.4034025f - 0.23903021f * x) * x;
3618 // error 0.0034276066, which is better than 8 bits
3619 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3620 getF32Constant(DAG, 0xbe74c456, dl));
3621 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3622 getF32Constant(DAG, 0x3fb3a2b1, dl));
3623 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3624 LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3625 getF32Constant(DAG, 0x3f949a29, dl));
3626 } else if (LimitFloatPrecision <= 12) {
3627 // For floating-point precision of 12:
3633 // (0.44717955f - 0.56570851e-1f * x) * x) * x) * x;
3635 // error 0.000061011436, which is 14 bits
3636 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3637 getF32Constant(DAG, 0xbd67b6d6, dl));
3638 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3639 getF32Constant(DAG, 0x3ee4f4b8, dl));
3640 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3641 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3642 getF32Constant(DAG, 0x3fbc278b, dl));
3643 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3644 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3645 getF32Constant(DAG, 0x40348e95, dl));
3646 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3647 LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3648 getF32Constant(DAG, 0x3fdef31a, dl));
3649 } else { // LimitFloatPrecision <= 18
3650 // For floating-point precision of 18:
3658 // (0.19073739f - 0.17809712e-1f * x) * x) * x) * x) * x)*x;
3660 // error 0.0000023660568, which is better than 18 bits
3661 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3662 getF32Constant(DAG, 0xbc91e5ac, dl));
3663 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3664 getF32Constant(DAG, 0x3e4350aa, dl));
3665 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3666 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3667 getF32Constant(DAG, 0x3f60d3e3, dl));
3668 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3669 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3670 getF32Constant(DAG, 0x4011cdf0, dl));
3671 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3672 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3673 getF32Constant(DAG, 0x406cfd1c, dl));
3674 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3675 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3676 getF32Constant(DAG, 0x408797cb, dl));
3677 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3678 LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10,
3679 getF32Constant(DAG, 0x4006dcab, dl));
3682 return DAG.getNode(ISD::FADD, dl, MVT::f32, LogOfExponent, LogOfMantissa);
3685 // No special expansion.
3686 return DAG.getNode(ISD::FLOG, dl, Op.getValueType(), Op);
3689 /// expandLog2 - Lower a log2 intrinsic. Handles the special sequences for
3690 /// limited-precision mode.
3691 static SDValue expandLog2(SDLoc dl, SDValue Op, SelectionDAG &DAG,
3692 const TargetLowering &TLI) {
3693 if (Op.getValueType() == MVT::f32 &&
3694 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3695 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op);
3697 // Get the exponent.
3698 SDValue LogOfExponent = GetExponent(DAG, Op1, TLI, dl);
3700 // Get the significand and build it into a floating-point number with
3702 SDValue X = GetSignificand(DAG, Op1, dl);
3704 // Different possible minimax approximations of significand in
3705 // floating-point for various degrees of accuracy over [1,2].
3706 SDValue Log2ofMantissa;
3707 if (LimitFloatPrecision <= 6) {
3708 // For floating-point precision of 6:
3710 // Log2ofMantissa = -1.6749035f + (2.0246817f - .34484768f * x) * x;
3712 // error 0.0049451742, which is more than 7 bits
3713 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3714 getF32Constant(DAG, 0xbeb08fe0, dl));
3715 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3716 getF32Constant(DAG, 0x40019463, dl));
3717 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3718 Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3719 getF32Constant(DAG, 0x3fd6633d, dl));
3720 } else if (LimitFloatPrecision <= 12) {
3721 // For floating-point precision of 12:
3727 // (.645142248f - 0.816157886e-1f * x) * x) * x) * x;
3729 // error 0.0000876136000, which is better than 13 bits
3730 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3731 getF32Constant(DAG, 0xbda7262e, dl));
3732 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3733 getF32Constant(DAG, 0x3f25280b, dl));
3734 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3735 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3736 getF32Constant(DAG, 0x4007b923, dl));
3737 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3738 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3739 getF32Constant(DAG, 0x40823e2f, dl));
3740 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3741 Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3742 getF32Constant(DAG, 0x4020d29c, dl));
3743 } else { // LimitFloatPrecision <= 18
3744 // For floating-point precision of 18:
3753 // 0.25691327e-1f * x) * x) * x) * x) * x) * x;
3755 // error 0.0000018516, which is better than 18 bits
3756 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3757 getF32Constant(DAG, 0xbcd2769e, dl));
3758 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3759 getF32Constant(DAG, 0x3e8ce0b9, dl));
3760 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3761 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3762 getF32Constant(DAG, 0x3fa22ae7, dl));
3763 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3764 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3765 getF32Constant(DAG, 0x40525723, dl));
3766 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3767 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3768 getF32Constant(DAG, 0x40aaf200, dl));
3769 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3770 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3771 getF32Constant(DAG, 0x40c39dad, dl));
3772 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3773 Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10,
3774 getF32Constant(DAG, 0x4042902c, dl));
3777 return DAG.getNode(ISD::FADD, dl, MVT::f32, LogOfExponent, Log2ofMantissa);
3780 // No special expansion.
3781 return DAG.getNode(ISD::FLOG2, dl, Op.getValueType(), Op);
3784 /// expandLog10 - Lower a log10 intrinsic. Handles the special sequences for
3785 /// limited-precision mode.
3786 static SDValue expandLog10(SDLoc dl, SDValue Op, SelectionDAG &DAG,
3787 const TargetLowering &TLI) {
3788 if (Op.getValueType() == MVT::f32 &&
3789 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3790 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op);
3792 // Scale the exponent by log10(2) [0.30102999f].
3793 SDValue Exp = GetExponent(DAG, Op1, TLI, dl);
3794 SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp,
3795 getF32Constant(DAG, 0x3e9a209a, dl));
3797 // Get the significand and build it into a floating-point number with
3799 SDValue X = GetSignificand(DAG, Op1, dl);
3801 SDValue Log10ofMantissa;
3802 if (LimitFloatPrecision <= 6) {
3803 // For floating-point precision of 6:
3805 // Log10ofMantissa =
3807 // (0.60948995f - 0.10380950f * x) * x;
3809 // error 0.0014886165, which is 6 bits
3810 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3811 getF32Constant(DAG, 0xbdd49a13, dl));
3812 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3813 getF32Constant(DAG, 0x3f1c0789, dl));
3814 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3815 Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3816 getF32Constant(DAG, 0x3f011300, dl));
3817 } else if (LimitFloatPrecision <= 12) {
3818 // For floating-point precision of 12:
3820 // Log10ofMantissa =
3823 // (-0.31664806f + 0.47637168e-1f * x) * x) * x;
3825 // error 0.00019228036, which is better than 12 bits
3826 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3827 getF32Constant(DAG, 0x3d431f31, dl));
3828 SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0,
3829 getF32Constant(DAG, 0x3ea21fb2, dl));
3830 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3831 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3832 getF32Constant(DAG, 0x3f6ae232, dl));
3833 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3834 Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4,
3835 getF32Constant(DAG, 0x3f25f7c3, dl));
3836 } else { // LimitFloatPrecision <= 18
3837 // For floating-point precision of 18:
3839 // Log10ofMantissa =
3844 // (-0.12539807f + 0.13508273e-1f * x) * x) * x) * x) * x;
3846 // error 0.0000037995730, which is better than 18 bits
3847 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3848 getF32Constant(DAG, 0x3c5d51ce, dl));
3849 SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0,
3850 getF32Constant(DAG, 0x3e00685a, dl));
3851 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3852 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3853 getF32Constant(DAG, 0x3efb6798, dl));
3854 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3855 SDValue t5 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4,
3856 getF32Constant(DAG, 0x3f88d192, dl));
3857 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3858 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3859 getF32Constant(DAG, 0x3fc4316c, dl));
3860 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3861 Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t8,
3862 getF32Constant(DAG, 0x3f57ce70, dl));
3865 return DAG.getNode(ISD::FADD, dl, MVT::f32, LogOfExponent, Log10ofMantissa);
3868 // No special expansion.
3869 return DAG.getNode(ISD::FLOG10, dl, Op.getValueType(), Op);
3872 /// expandExp2 - Lower an exp2 intrinsic. Handles the special sequences for
3873 /// limited-precision mode.
3874 static SDValue expandExp2(SDLoc dl, SDValue Op, SelectionDAG &DAG,
3875 const TargetLowering &TLI) {
3876 if (Op.getValueType() == MVT::f32 &&
3877 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18)
3878 return getLimitedPrecisionExp2(Op, dl, DAG);
3880 // No special expansion.
3881 return DAG.getNode(ISD::FEXP2, dl, Op.getValueType(), Op);
3884 /// visitPow - Lower a pow intrinsic. Handles the special sequences for
3885 /// limited-precision mode with x == 10.0f.
3886 static SDValue expandPow(SDLoc dl, SDValue LHS, SDValue RHS,
3887 SelectionDAG &DAG, const TargetLowering &TLI) {
3888 bool IsExp10 = false;
3889 if (LHS.getValueType() == MVT::f32 && RHS.getValueType() == MVT::f32 &&
3890 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3891 if (ConstantFPSDNode *LHSC = dyn_cast<ConstantFPSDNode>(LHS)) {
3893 IsExp10 = LHSC->isExactlyValue(Ten);
3898 // Put the exponent in the right bit position for later addition to the
3901 // #define LOG2OF10 3.3219281f
3902 // t0 = Op * LOG2OF10;
3903 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, RHS,
3904 getF32Constant(DAG, 0x40549a78, dl));
3905 return getLimitedPrecisionExp2(t0, dl, DAG);
3908 // No special expansion.
3909 return DAG.getNode(ISD::FPOW, dl, LHS.getValueType(), LHS, RHS);
3913 /// ExpandPowI - Expand a llvm.powi intrinsic.
3914 static SDValue ExpandPowI(SDLoc DL, SDValue LHS, SDValue RHS,
3915 SelectionDAG &DAG) {
3916 // If RHS is a constant, we can expand this out to a multiplication tree,
3917 // otherwise we end up lowering to a call to __powidf2 (for example). When
3918 // optimizing for size, we only want to do this if the expansion would produce
3919 // a small number of multiplies, otherwise we do the full expansion.
3920 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
3921 // Get the exponent as a positive value.
3922 unsigned Val = RHSC->getSExtValue();
3923 if ((int)Val < 0) Val = -Val;
3925 // powi(x, 0) -> 1.0
3927 return DAG.getConstantFP(1.0, DL, LHS.getValueType());
3929 const Function *F = DAG.getMachineFunction().getFunction();
3930 if (!F->hasFnAttribute(Attribute::OptimizeForSize) ||
3931 // If optimizing for size, don't insert too many multiplies. This
3932 // inserts up to 5 multiplies.
3933 countPopulation(Val) + Log2_32(Val) < 7) {
3934 // We use the simple binary decomposition method to generate the multiply
3935 // sequence. There are more optimal ways to do this (for example,
3936 // powi(x,15) generates one more multiply than it should), but this has
3937 // the benefit of being both really simple and much better than a libcall.
3938 SDValue Res; // Logically starts equal to 1.0
3939 SDValue CurSquare = LHS;
3943 Res = DAG.getNode(ISD::FMUL, DL,Res.getValueType(), Res, CurSquare);
3945 Res = CurSquare; // 1.0*CurSquare.
3948 CurSquare = DAG.getNode(ISD::FMUL, DL, CurSquare.getValueType(),
3949 CurSquare, CurSquare);
3953 // If the original was negative, invert the result, producing 1/(x*x*x).
3954 if (RHSC->getSExtValue() < 0)
3955 Res = DAG.getNode(ISD::FDIV, DL, LHS.getValueType(),
3956 DAG.getConstantFP(1.0, DL, LHS.getValueType()), Res);
3961 // Otherwise, expand to a libcall.
3962 return DAG.getNode(ISD::FPOWI, DL, LHS.getValueType(), LHS, RHS);
3965 // getTruncatedArgReg - Find underlying register used for an truncated
3967 static unsigned getTruncatedArgReg(const SDValue &N) {
3968 if (N.getOpcode() != ISD::TRUNCATE)
3971 const SDValue &Ext = N.getOperand(0);
3972 if (Ext.getOpcode() == ISD::AssertZext ||
3973 Ext.getOpcode() == ISD::AssertSext) {
3974 const SDValue &CFR = Ext.getOperand(0);
3975 if (CFR.getOpcode() == ISD::CopyFromReg)
3976 return cast<RegisterSDNode>(CFR.getOperand(1))->getReg();
3977 if (CFR.getOpcode() == ISD::TRUNCATE)
3978 return getTruncatedArgReg(CFR);
3983 /// EmitFuncArgumentDbgValue - If the DbgValueInst is a dbg_value of a function
3984 /// argument, create the corresponding DBG_VALUE machine instruction for it now.
3985 /// At the end of instruction selection, they will be inserted to the entry BB.
3986 bool SelectionDAGBuilder::EmitFuncArgumentDbgValue(
3987 const Value *V, DILocalVariable *Variable, DIExpression *Expr,
3988 DILocation *DL, int64_t Offset, bool IsIndirect, const SDValue &N) {
3989 const Argument *Arg = dyn_cast<Argument>(V);
3993 MachineFunction &MF = DAG.getMachineFunction();
3994 const TargetInstrInfo *TII = DAG.getSubtarget().getInstrInfo();
3996 // Ignore inlined function arguments here.
3998 // FIXME: Should we be checking DL->inlinedAt() to determine this?
3999 if (!Variable->getScope()->getSubprogram()->describes(MF.getFunction()))
4002 Optional<MachineOperand> Op;
4003 // Some arguments' frame index is recorded during argument lowering.
4004 if (int FI = FuncInfo.getArgumentFrameIndex(Arg))
4005 Op = MachineOperand::CreateFI(FI);
4007 if (!Op && N.getNode()) {
4009 if (N.getOpcode() == ISD::CopyFromReg)
4010 Reg = cast<RegisterSDNode>(N.getOperand(1))->getReg();
4012 Reg = getTruncatedArgReg(N);
4013 if (Reg && TargetRegisterInfo::isVirtualRegister(Reg)) {
4014 MachineRegisterInfo &RegInfo = MF.getRegInfo();
4015 unsigned PR = RegInfo.getLiveInPhysReg(Reg);
4020 Op = MachineOperand::CreateReg(Reg, false);
4024 // Check if ValueMap has reg number.
4025 DenseMap<const Value *, unsigned>::iterator VMI = FuncInfo.ValueMap.find(V);
4026 if (VMI != FuncInfo.ValueMap.end())
4027 Op = MachineOperand::CreateReg(VMI->second, false);
4030 if (!Op && N.getNode())
4031 // Check if frame index is available.
4032 if (LoadSDNode *LNode = dyn_cast<LoadSDNode>(N.getNode()))
4033 if (FrameIndexSDNode *FINode =
4034 dyn_cast<FrameIndexSDNode>(LNode->getBasePtr().getNode()))
4035 Op = MachineOperand::CreateFI(FINode->getIndex());
4040 assert(Variable->isValidLocationForIntrinsic(DL) &&
4041 "Expected inlined-at fields to agree");
4043 FuncInfo.ArgDbgValues.push_back(
4044 BuildMI(MF, DL, TII->get(TargetOpcode::DBG_VALUE), IsIndirect,
4045 Op->getReg(), Offset, Variable, Expr));
4047 FuncInfo.ArgDbgValues.push_back(
4048 BuildMI(MF, DL, TII->get(TargetOpcode::DBG_VALUE))
4051 .addMetadata(Variable)
4052 .addMetadata(Expr));
4057 // VisualStudio defines setjmp as _setjmp
4058 #if defined(_MSC_VER) && defined(setjmp) && \
4059 !defined(setjmp_undefined_for_msvc)
4060 # pragma push_macro("setjmp")
4062 # define setjmp_undefined_for_msvc
4065 /// visitIntrinsicCall - Lower the call to the specified intrinsic function. If
4066 /// we want to emit this as a call to a named external function, return the name
4067 /// otherwise lower it and return null.
4069 SelectionDAGBuilder::visitIntrinsicCall(const CallInst &I, unsigned Intrinsic) {
4070 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
4071 SDLoc sdl = getCurSDLoc();
4072 DebugLoc dl = getCurDebugLoc();
4075 switch (Intrinsic) {
4077 // By default, turn this into a target intrinsic node.
4078 visitTargetIntrinsic(I, Intrinsic);
4080 case Intrinsic::vastart: visitVAStart(I); return nullptr;
4081 case Intrinsic::vaend: visitVAEnd(I); return nullptr;
4082 case Intrinsic::vacopy: visitVACopy(I); return nullptr;
4083 case Intrinsic::returnaddress:
4084 setValue(&I, DAG.getNode(ISD::RETURNADDR, sdl, TLI.getPointerTy(),
4085 getValue(I.getArgOperand(0))));
4087 case Intrinsic::frameaddress:
4088 setValue(&I, DAG.getNode(ISD::FRAMEADDR, sdl, TLI.getPointerTy(),
4089 getValue(I.getArgOperand(0))));
4091 case Intrinsic::read_register: {
4092 Value *Reg = I.getArgOperand(0);
4093 SDValue Chain = getRoot();
4095 DAG.getMDNode(cast<MDNode>(cast<MetadataAsValue>(Reg)->getMetadata()));
4096 EVT VT = TLI.getValueType(I.getType());
4097 Res = DAG.getNode(ISD::READ_REGISTER, sdl,
4098 DAG.getVTList(VT, MVT::Other), Chain, RegName);
4100 DAG.setRoot(Res.getValue(1));
4103 case Intrinsic::write_register: {
4104 Value *Reg = I.getArgOperand(0);
4105 Value *RegValue = I.getArgOperand(1);
4106 SDValue Chain = getRoot();
4108 DAG.getMDNode(cast<MDNode>(cast<MetadataAsValue>(Reg)->getMetadata()));
4109 DAG.setRoot(DAG.getNode(ISD::WRITE_REGISTER, sdl, MVT::Other, Chain,
4110 RegName, getValue(RegValue)));
4113 case Intrinsic::setjmp:
4114 return &"_setjmp"[!TLI.usesUnderscoreSetJmp()];
4115 case Intrinsic::longjmp:
4116 return &"_longjmp"[!TLI.usesUnderscoreLongJmp()];
4117 case Intrinsic::memcpy: {
4118 // FIXME: this definition of "user defined address space" is x86-specific
4119 // Assert for address < 256 since we support only user defined address
4121 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace()
4123 cast<PointerType>(I.getArgOperand(1)->getType())->getAddressSpace()
4125 "Unknown address space");
4126 SDValue Op1 = getValue(I.getArgOperand(0));
4127 SDValue Op2 = getValue(I.getArgOperand(1));
4128 SDValue Op3 = getValue(I.getArgOperand(2));
4129 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue();
4131 Align = 1; // @llvm.memcpy defines 0 and 1 to both mean no alignment.
4132 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue();
4133 bool isTC = I.isTailCall() && isInTailCallPosition(&I, DAG.getTarget());
4134 SDValue MC = DAG.getMemcpy(getRoot(), sdl, Op1, Op2, Op3, Align, isVol,
4136 MachinePointerInfo(I.getArgOperand(0)),
4137 MachinePointerInfo(I.getArgOperand(1)));
4138 updateDAGForMaybeTailCall(MC);
4141 case Intrinsic::memset: {
4142 // FIXME: this definition of "user defined address space" is x86-specific
4143 // Assert for address < 256 since we support only user defined address
4145 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace()
4147 "Unknown address space");
4148 SDValue Op1 = getValue(I.getArgOperand(0));
4149 SDValue Op2 = getValue(I.getArgOperand(1));
4150 SDValue Op3 = getValue(I.getArgOperand(2));
4151 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue();
4153 Align = 1; // @llvm.memset defines 0 and 1 to both mean no alignment.
4154 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue();
4155 bool isTC = I.isTailCall() && isInTailCallPosition(&I, DAG.getTarget());
4156 SDValue MS = DAG.getMemset(getRoot(), sdl, Op1, Op2, Op3, Align, isVol,
4157 isTC, MachinePointerInfo(I.getArgOperand(0)));
4158 updateDAGForMaybeTailCall(MS);
4161 case Intrinsic::memmove: {
4162 // FIXME: this definition of "user defined address space" is x86-specific
4163 // Assert for address < 256 since we support only user defined address
4165 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace()
4167 cast<PointerType>(I.getArgOperand(1)->getType())->getAddressSpace()
4169 "Unknown address space");
4170 SDValue Op1 = getValue(I.getArgOperand(0));
4171 SDValue Op2 = getValue(I.getArgOperand(1));
4172 SDValue Op3 = getValue(I.getArgOperand(2));
4173 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue();
4175 Align = 1; // @llvm.memmove defines 0 and 1 to both mean no alignment.
4176 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue();
4177 bool isTC = I.isTailCall() && isInTailCallPosition(&I, DAG.getTarget());
4178 SDValue MM = DAG.getMemmove(getRoot(), sdl, Op1, Op2, Op3, Align, isVol,
4179 isTC, MachinePointerInfo(I.getArgOperand(0)),
4180 MachinePointerInfo(I.getArgOperand(1)));
4181 updateDAGForMaybeTailCall(MM);
4184 case Intrinsic::dbg_declare: {
4185 const DbgDeclareInst &DI = cast<DbgDeclareInst>(I);
4186 DILocalVariable *Variable = DI.getVariable();
4187 DIExpression *Expression = DI.getExpression();
4188 const Value *Address = DI.getAddress();
4189 assert(Variable && "Missing variable");
4191 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
4195 // Check if address has undef value.
4196 if (isa<UndefValue>(Address) ||
4197 (Address->use_empty() && !isa<Argument>(Address))) {
4198 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
4202 SDValue &N = NodeMap[Address];
4203 if (!N.getNode() && isa<Argument>(Address))
4204 // Check unused arguments map.
4205 N = UnusedArgNodeMap[Address];
4208 if (const BitCastInst *BCI = dyn_cast<BitCastInst>(Address))
4209 Address = BCI->getOperand(0);
4210 // Parameters are handled specially.
4211 bool isParameter = Variable->getTag() == dwarf::DW_TAG_arg_variable ||
4212 isa<Argument>(Address);
4214 const AllocaInst *AI = dyn_cast<AllocaInst>(Address);
4216 if (isParameter && !AI) {
4217 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(N.getNode());
4219 // Byval parameter. We have a frame index at this point.
4220 SDV = DAG.getFrameIndexDbgValue(
4221 Variable, Expression, FINode->getIndex(), 0, dl, SDNodeOrder);
4223 // Address is an argument, so try to emit its dbg value using
4224 // virtual register info from the FuncInfo.ValueMap.
4225 EmitFuncArgumentDbgValue(Address, Variable, Expression, dl, 0, false,
4230 SDV = DAG.getDbgValue(Variable, Expression, N.getNode(), N.getResNo(),
4231 true, 0, dl, SDNodeOrder);
4233 // Can't do anything with other non-AI cases yet.
4234 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
4235 DEBUG(dbgs() << "non-AllocaInst issue for Address: \n\t");
4236 DEBUG(Address->dump());
4239 DAG.AddDbgValue(SDV, N.getNode(), isParameter);
4241 // If Address is an argument then try to emit its dbg value using
4242 // virtual register info from the FuncInfo.ValueMap.
4243 if (!EmitFuncArgumentDbgValue(Address, Variable, Expression, dl, 0, false,
4245 // If variable is pinned by a alloca in dominating bb then
4246 // use StaticAllocaMap.
4247 if (const AllocaInst *AI = dyn_cast<AllocaInst>(Address)) {
4248 if (AI->getParent() != DI.getParent()) {
4249 DenseMap<const AllocaInst*, int>::iterator SI =
4250 FuncInfo.StaticAllocaMap.find(AI);
4251 if (SI != FuncInfo.StaticAllocaMap.end()) {
4252 SDV = DAG.getFrameIndexDbgValue(Variable, Expression, SI->second,
4253 0, dl, SDNodeOrder);
4254 DAG.AddDbgValue(SDV, nullptr, false);
4259 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
4264 case Intrinsic::dbg_value: {
4265 const DbgValueInst &DI = cast<DbgValueInst>(I);
4266 assert(DI.getVariable() && "Missing variable");
4268 DILocalVariable *Variable = DI.getVariable();
4269 DIExpression *Expression = DI.getExpression();
4270 uint64_t Offset = DI.getOffset();
4271 const Value *V = DI.getValue();
4276 if (isa<ConstantInt>(V) || isa<ConstantFP>(V) || isa<UndefValue>(V)) {
4277 SDV = DAG.getConstantDbgValue(Variable, Expression, V, Offset, dl,
4279 DAG.AddDbgValue(SDV, nullptr, false);
4281 // Do not use getValue() in here; we don't want to generate code at
4282 // this point if it hasn't been done yet.
4283 SDValue N = NodeMap[V];
4284 if (!N.getNode() && isa<Argument>(V))
4285 // Check unused arguments map.
4286 N = UnusedArgNodeMap[V];
4288 // A dbg.value for an alloca is always indirect.
4289 bool IsIndirect = isa<AllocaInst>(V) || Offset != 0;
4290 if (!EmitFuncArgumentDbgValue(V, Variable, Expression, dl, Offset,
4292 SDV = DAG.getDbgValue(Variable, Expression, N.getNode(), N.getResNo(),
4293 IsIndirect, Offset, dl, SDNodeOrder);
4294 DAG.AddDbgValue(SDV, N.getNode(), false);
4296 } else if (!V->use_empty() ) {
4297 // Do not call getValue(V) yet, as we don't want to generate code.
4298 // Remember it for later.
4299 DanglingDebugInfo DDI(&DI, dl, SDNodeOrder);
4300 DanglingDebugInfoMap[V] = DDI;
4302 // We may expand this to cover more cases. One case where we have no
4303 // data available is an unreferenced parameter.
4304 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
4308 // Build a debug info table entry.
4309 if (const BitCastInst *BCI = dyn_cast<BitCastInst>(V))
4310 V = BCI->getOperand(0);
4311 const AllocaInst *AI = dyn_cast<AllocaInst>(V);
4312 // Don't handle byval struct arguments or VLAs, for example.
4314 DEBUG(dbgs() << "Dropping debug location info for:\n " << DI << "\n");
4315 DEBUG(dbgs() << " Last seen at:\n " << *V << "\n");
4318 DenseMap<const AllocaInst*, int>::iterator SI =
4319 FuncInfo.StaticAllocaMap.find(AI);
4320 if (SI == FuncInfo.StaticAllocaMap.end())
4321 return nullptr; // VLAs.
4325 case Intrinsic::eh_typeid_for: {
4326 // Find the type id for the given typeinfo.
4327 GlobalValue *GV = ExtractTypeInfo(I.getArgOperand(0));
4328 unsigned TypeID = DAG.getMachineFunction().getMMI().getTypeIDFor(GV);
4329 Res = DAG.getConstant(TypeID, sdl, MVT::i32);
4334 case Intrinsic::eh_return_i32:
4335 case Intrinsic::eh_return_i64:
4336 DAG.getMachineFunction().getMMI().setCallsEHReturn(true);
4337 DAG.setRoot(DAG.getNode(ISD::EH_RETURN, sdl,
4340 getValue(I.getArgOperand(0)),
4341 getValue(I.getArgOperand(1))));
4343 case Intrinsic::eh_unwind_init:
4344 DAG.getMachineFunction().getMMI().setCallsUnwindInit(true);
4346 case Intrinsic::eh_dwarf_cfa: {
4347 SDValue CfaArg = DAG.getSExtOrTrunc(getValue(I.getArgOperand(0)), sdl,
4348 TLI.getPointerTy());
4349 SDValue Offset = DAG.getNode(ISD::ADD, sdl,
4350 CfaArg.getValueType(),
4351 DAG.getNode(ISD::FRAME_TO_ARGS_OFFSET, sdl,
4352 CfaArg.getValueType()),
4354 SDValue FA = DAG.getNode(ISD::FRAMEADDR, sdl, TLI.getPointerTy(),
4355 DAG.getConstant(0, sdl, TLI.getPointerTy()));
4356 setValue(&I, DAG.getNode(ISD::ADD, sdl, FA.getValueType(),
4360 case Intrinsic::eh_sjlj_callsite: {
4361 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
4362 ConstantInt *CI = dyn_cast<ConstantInt>(I.getArgOperand(0));
4363 assert(CI && "Non-constant call site value in eh.sjlj.callsite!");
4364 assert(MMI.getCurrentCallSite() == 0 && "Overlapping call sites!");
4366 MMI.setCurrentCallSite(CI->getZExtValue());
4369 case Intrinsic::eh_sjlj_functioncontext: {
4370 // Get and store the index of the function context.
4371 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
4373 cast<AllocaInst>(I.getArgOperand(0)->stripPointerCasts());
4374 int FI = FuncInfo.StaticAllocaMap[FnCtx];
4375 MFI->setFunctionContextIndex(FI);
4378 case Intrinsic::eh_sjlj_setjmp: {
4381 Ops[1] = getValue(I.getArgOperand(0));
4382 SDValue Op = DAG.getNode(ISD::EH_SJLJ_SETJMP, sdl,
4383 DAG.getVTList(MVT::i32, MVT::Other), Ops);
4384 setValue(&I, Op.getValue(0));
4385 DAG.setRoot(Op.getValue(1));
4388 case Intrinsic::eh_sjlj_longjmp: {
4389 DAG.setRoot(DAG.getNode(ISD::EH_SJLJ_LONGJMP, sdl, MVT::Other,
4390 getRoot(), getValue(I.getArgOperand(0))));
4394 case Intrinsic::masked_gather:
4395 visitMaskedGather(I);
4397 case Intrinsic::masked_load:
4400 case Intrinsic::masked_scatter:
4401 visitMaskedScatter(I);
4403 case Intrinsic::masked_store:
4404 visitMaskedStore(I);
4406 case Intrinsic::x86_mmx_pslli_w:
4407 case Intrinsic::x86_mmx_pslli_d:
4408 case Intrinsic::x86_mmx_pslli_q:
4409 case Intrinsic::x86_mmx_psrli_w:
4410 case Intrinsic::x86_mmx_psrli_d:
4411 case Intrinsic::x86_mmx_psrli_q:
4412 case Intrinsic::x86_mmx_psrai_w:
4413 case Intrinsic::x86_mmx_psrai_d: {
4414 SDValue ShAmt = getValue(I.getArgOperand(1));
4415 if (isa<ConstantSDNode>(ShAmt)) {
4416 visitTargetIntrinsic(I, Intrinsic);
4419 unsigned NewIntrinsic = 0;
4420 EVT ShAmtVT = MVT::v2i32;
4421 switch (Intrinsic) {
4422 case Intrinsic::x86_mmx_pslli_w:
4423 NewIntrinsic = Intrinsic::x86_mmx_psll_w;
4425 case Intrinsic::x86_mmx_pslli_d:
4426 NewIntrinsic = Intrinsic::x86_mmx_psll_d;
4428 case Intrinsic::x86_mmx_pslli_q:
4429 NewIntrinsic = Intrinsic::x86_mmx_psll_q;
4431 case Intrinsic::x86_mmx_psrli_w:
4432 NewIntrinsic = Intrinsic::x86_mmx_psrl_w;
4434 case Intrinsic::x86_mmx_psrli_d:
4435 NewIntrinsic = Intrinsic::x86_mmx_psrl_d;
4437 case Intrinsic::x86_mmx_psrli_q:
4438 NewIntrinsic = Intrinsic::x86_mmx_psrl_q;
4440 case Intrinsic::x86_mmx_psrai_w:
4441 NewIntrinsic = Intrinsic::x86_mmx_psra_w;
4443 case Intrinsic::x86_mmx_psrai_d:
4444 NewIntrinsic = Intrinsic::x86_mmx_psra_d;
4446 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
4449 // The vector shift intrinsics with scalars uses 32b shift amounts but
4450 // the sse2/mmx shift instructions reads 64 bits. Set the upper 32 bits
4452 // We must do this early because v2i32 is not a legal type.
4455 ShOps[1] = DAG.getConstant(0, sdl, MVT::i32);
4456 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, sdl, ShAmtVT, ShOps);
4457 EVT DestVT = TLI.getValueType(I.getType());
4458 ShAmt = DAG.getNode(ISD::BITCAST, sdl, DestVT, ShAmt);
4459 Res = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, sdl, DestVT,
4460 DAG.getConstant(NewIntrinsic, sdl, MVT::i32),
4461 getValue(I.getArgOperand(0)), ShAmt);
4465 case Intrinsic::convertff:
4466 case Intrinsic::convertfsi:
4467 case Intrinsic::convertfui:
4468 case Intrinsic::convertsif:
4469 case Intrinsic::convertuif:
4470 case Intrinsic::convertss:
4471 case Intrinsic::convertsu:
4472 case Intrinsic::convertus:
4473 case Intrinsic::convertuu: {
4474 ISD::CvtCode Code = ISD::CVT_INVALID;
4475 switch (Intrinsic) {
4476 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
4477 case Intrinsic::convertff: Code = ISD::CVT_FF; break;
4478 case Intrinsic::convertfsi: Code = ISD::CVT_FS; break;
4479 case Intrinsic::convertfui: Code = ISD::CVT_FU; break;
4480 case Intrinsic::convertsif: Code = ISD::CVT_SF; break;
4481 case Intrinsic::convertuif: Code = ISD::CVT_UF; break;
4482 case Intrinsic::convertss: Code = ISD::CVT_SS; break;
4483 case Intrinsic::convertsu: Code = ISD::CVT_SU; break;
4484 case Intrinsic::convertus: Code = ISD::CVT_US; break;
4485 case Intrinsic::convertuu: Code = ISD::CVT_UU; break;
4487 EVT DestVT = TLI.getValueType(I.getType());
4488 const Value *Op1 = I.getArgOperand(0);
4489 Res = DAG.getConvertRndSat(DestVT, sdl, getValue(Op1),
4490 DAG.getValueType(DestVT),
4491 DAG.getValueType(getValue(Op1).getValueType()),
4492 getValue(I.getArgOperand(1)),
4493 getValue(I.getArgOperand(2)),
4498 case Intrinsic::powi:
4499 setValue(&I, ExpandPowI(sdl, getValue(I.getArgOperand(0)),
4500 getValue(I.getArgOperand(1)), DAG));
4502 case Intrinsic::log:
4503 setValue(&I, expandLog(sdl, getValue(I.getArgOperand(0)), DAG, TLI));
4505 case Intrinsic::log2:
4506 setValue(&I, expandLog2(sdl, getValue(I.getArgOperand(0)), DAG, TLI));
4508 case Intrinsic::log10:
4509 setValue(&I, expandLog10(sdl, getValue(I.getArgOperand(0)), DAG, TLI));
4511 case Intrinsic::exp:
4512 setValue(&I, expandExp(sdl, getValue(I.getArgOperand(0)), DAG, TLI));
4514 case Intrinsic::exp2:
4515 setValue(&I, expandExp2(sdl, getValue(I.getArgOperand(0)), DAG, TLI));
4517 case Intrinsic::pow:
4518 setValue(&I, expandPow(sdl, getValue(I.getArgOperand(0)),
4519 getValue(I.getArgOperand(1)), DAG, TLI));
4521 case Intrinsic::sqrt:
4522 case Intrinsic::fabs:
4523 case Intrinsic::sin:
4524 case Intrinsic::cos:
4525 case Intrinsic::floor:
4526 case Intrinsic::ceil:
4527 case Intrinsic::trunc:
4528 case Intrinsic::rint:
4529 case Intrinsic::nearbyint:
4530 case Intrinsic::round: {
4532 switch (Intrinsic) {
4533 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
4534 case Intrinsic::sqrt: Opcode = ISD::FSQRT; break;
4535 case Intrinsic::fabs: Opcode = ISD::FABS; break;
4536 case Intrinsic::sin: Opcode = ISD::FSIN; break;
4537 case Intrinsic::cos: Opcode = ISD::FCOS; break;
4538 case Intrinsic::floor: Opcode = ISD::FFLOOR; break;
4539 case Intrinsic::ceil: Opcode = ISD::FCEIL; break;
4540 case Intrinsic::trunc: Opcode = ISD::FTRUNC; break;
4541 case Intrinsic::rint: Opcode = ISD::FRINT; break;
4542 case Intrinsic::nearbyint: Opcode = ISD::FNEARBYINT; break;
4543 case Intrinsic::round: Opcode = ISD::FROUND; break;
4546 setValue(&I, DAG.getNode(Opcode, sdl,
4547 getValue(I.getArgOperand(0)).getValueType(),
4548 getValue(I.getArgOperand(0))));
4551 case Intrinsic::minnum:
4552 setValue(&I, DAG.getNode(ISD::FMINNUM, sdl,
4553 getValue(I.getArgOperand(0)).getValueType(),
4554 getValue(I.getArgOperand(0)),
4555 getValue(I.getArgOperand(1))));
4557 case Intrinsic::maxnum:
4558 setValue(&I, DAG.getNode(ISD::FMAXNUM, sdl,
4559 getValue(I.getArgOperand(0)).getValueType(),
4560 getValue(I.getArgOperand(0)),
4561 getValue(I.getArgOperand(1))));
4563 case Intrinsic::copysign:
4564 setValue(&I, DAG.getNode(ISD::FCOPYSIGN, sdl,
4565 getValue(I.getArgOperand(0)).getValueType(),
4566 getValue(I.getArgOperand(0)),
4567 getValue(I.getArgOperand(1))));
4569 case Intrinsic::fma:
4570 setValue(&I, DAG.getNode(ISD::FMA, sdl,
4571 getValue(I.getArgOperand(0)).getValueType(),
4572 getValue(I.getArgOperand(0)),
4573 getValue(I.getArgOperand(1)),
4574 getValue(I.getArgOperand(2))));
4576 case Intrinsic::fmuladd: {
4577 EVT VT = TLI.getValueType(I.getType());
4578 if (TM.Options.AllowFPOpFusion != FPOpFusion::Strict &&
4579 TLI.isFMAFasterThanFMulAndFAdd(VT)) {
4580 setValue(&I, DAG.getNode(ISD::FMA, sdl,
4581 getValue(I.getArgOperand(0)).getValueType(),
4582 getValue(I.getArgOperand(0)),
4583 getValue(I.getArgOperand(1)),
4584 getValue(I.getArgOperand(2))));
4586 SDValue Mul = DAG.getNode(ISD::FMUL, sdl,
4587 getValue(I.getArgOperand(0)).getValueType(),
4588 getValue(I.getArgOperand(0)),
4589 getValue(I.getArgOperand(1)));
4590 SDValue Add = DAG.getNode(ISD::FADD, sdl,
4591 getValue(I.getArgOperand(0)).getValueType(),
4593 getValue(I.getArgOperand(2)));
4598 case Intrinsic::convert_to_fp16:
4599 setValue(&I, DAG.getNode(ISD::BITCAST, sdl, MVT::i16,
4600 DAG.getNode(ISD::FP_ROUND, sdl, MVT::f16,
4601 getValue(I.getArgOperand(0)),
4602 DAG.getTargetConstant(0, sdl,
4605 case Intrinsic::convert_from_fp16:
4607 DAG.getNode(ISD::FP_EXTEND, sdl, TLI.getValueType(I.getType()),
4608 DAG.getNode(ISD::BITCAST, sdl, MVT::f16,
4609 getValue(I.getArgOperand(0)))));
4611 case Intrinsic::pcmarker: {
4612 SDValue Tmp = getValue(I.getArgOperand(0));
4613 DAG.setRoot(DAG.getNode(ISD::PCMARKER, sdl, MVT::Other, getRoot(), Tmp));
4616 case Intrinsic::readcyclecounter: {
4617 SDValue Op = getRoot();
4618 Res = DAG.getNode(ISD::READCYCLECOUNTER, sdl,
4619 DAG.getVTList(MVT::i64, MVT::Other), Op);
4621 DAG.setRoot(Res.getValue(1));
4624 case Intrinsic::bswap:
4625 setValue(&I, DAG.getNode(ISD::BSWAP, sdl,
4626 getValue(I.getArgOperand(0)).getValueType(),
4627 getValue(I.getArgOperand(0))));
4629 case Intrinsic::cttz: {
4630 SDValue Arg = getValue(I.getArgOperand(0));
4631 ConstantInt *CI = cast<ConstantInt>(I.getArgOperand(1));
4632 EVT Ty = Arg.getValueType();
4633 setValue(&I, DAG.getNode(CI->isZero() ? ISD::CTTZ : ISD::CTTZ_ZERO_UNDEF,
4637 case Intrinsic::ctlz: {
4638 SDValue Arg = getValue(I.getArgOperand(0));
4639 ConstantInt *CI = cast<ConstantInt>(I.getArgOperand(1));
4640 EVT Ty = Arg.getValueType();
4641 setValue(&I, DAG.getNode(CI->isZero() ? ISD::CTLZ : ISD::CTLZ_ZERO_UNDEF,
4645 case Intrinsic::ctpop: {
4646 SDValue Arg = getValue(I.getArgOperand(0));
4647 EVT Ty = Arg.getValueType();
4648 setValue(&I, DAG.getNode(ISD::CTPOP, sdl, Ty, Arg));
4651 case Intrinsic::stacksave: {
4652 SDValue Op = getRoot();
4653 Res = DAG.getNode(ISD::STACKSAVE, sdl,
4654 DAG.getVTList(TLI.getPointerTy(), MVT::Other), Op);
4656 DAG.setRoot(Res.getValue(1));
4659 case Intrinsic::stackrestore: {
4660 Res = getValue(I.getArgOperand(0));
4661 DAG.setRoot(DAG.getNode(ISD::STACKRESTORE, sdl, MVT::Other, getRoot(), Res));
4664 case Intrinsic::stackprotector: {
4665 // Emit code into the DAG to store the stack guard onto the stack.
4666 MachineFunction &MF = DAG.getMachineFunction();
4667 MachineFrameInfo *MFI = MF.getFrameInfo();
4668 EVT PtrTy = TLI.getPointerTy();
4669 SDValue Src, Chain = getRoot();
4670 const Value *Ptr = cast<LoadInst>(I.getArgOperand(0))->getPointerOperand();
4671 const GlobalVariable *GV = dyn_cast<GlobalVariable>(Ptr);
4673 // See if Ptr is a bitcast. If it is, look through it and see if we can get
4674 // global variable __stack_chk_guard.
4676 if (const Operator *BC = dyn_cast<Operator>(Ptr))
4677 if (BC->getOpcode() == Instruction::BitCast)
4678 GV = dyn_cast<GlobalVariable>(BC->getOperand(0));
4680 if (GV && TLI.useLoadStackGuardNode()) {
4681 // Emit a LOAD_STACK_GUARD node.
4682 MachineSDNode *Node = DAG.getMachineNode(TargetOpcode::LOAD_STACK_GUARD,
4684 MachinePointerInfo MPInfo(GV);
4685 MachineInstr::mmo_iterator MemRefs = MF.allocateMemRefsArray(1);
4686 unsigned Flags = MachineMemOperand::MOLoad |
4687 MachineMemOperand::MOInvariant;
4688 *MemRefs = MF.getMachineMemOperand(MPInfo, Flags,
4689 PtrTy.getSizeInBits() / 8,
4690 DAG.getEVTAlignment(PtrTy));
4691 Node->setMemRefs(MemRefs, MemRefs + 1);
4693 // Copy the guard value to a virtual register so that it can be
4694 // retrieved in the epilogue.
4695 Src = SDValue(Node, 0);
4696 const TargetRegisterClass *RC =
4697 TLI.getRegClassFor(Src.getSimpleValueType());
4698 unsigned Reg = MF.getRegInfo().createVirtualRegister(RC);
4700 SPDescriptor.setGuardReg(Reg);
4701 Chain = DAG.getCopyToReg(Chain, sdl, Reg, Src);
4703 Src = getValue(I.getArgOperand(0)); // The guard's value.
4706 AllocaInst *Slot = cast<AllocaInst>(I.getArgOperand(1));
4708 int FI = FuncInfo.StaticAllocaMap[Slot];
4709 MFI->setStackProtectorIndex(FI);
4711 SDValue FIN = DAG.getFrameIndex(FI, PtrTy);
4713 // Store the stack protector onto the stack.
4714 Res = DAG.getStore(Chain, sdl, Src, FIN,
4715 MachinePointerInfo::getFixedStack(FI),
4721 case Intrinsic::objectsize: {
4722 // If we don't know by now, we're never going to know.
4723 ConstantInt *CI = dyn_cast<ConstantInt>(I.getArgOperand(1));
4725 assert(CI && "Non-constant type in __builtin_object_size?");
4727 SDValue Arg = getValue(I.getCalledValue());
4728 EVT Ty = Arg.getValueType();
4731 Res = DAG.getConstant(-1ULL, sdl, Ty);
4733 Res = DAG.getConstant(0, sdl, Ty);
4738 case Intrinsic::annotation:
4739 case Intrinsic::ptr_annotation:
4740 // Drop the intrinsic, but forward the value
4741 setValue(&I, getValue(I.getOperand(0)));
4743 case Intrinsic::assume:
4744 case Intrinsic::var_annotation:
4745 // Discard annotate attributes and assumptions
4748 case Intrinsic::init_trampoline: {
4749 const Function *F = cast<Function>(I.getArgOperand(1)->stripPointerCasts());
4753 Ops[1] = getValue(I.getArgOperand(0));
4754 Ops[2] = getValue(I.getArgOperand(1));
4755 Ops[3] = getValue(I.getArgOperand(2));
4756 Ops[4] = DAG.getSrcValue(I.getArgOperand(0));
4757 Ops[5] = DAG.getSrcValue(F);
4759 Res = DAG.getNode(ISD::INIT_TRAMPOLINE, sdl, MVT::Other, Ops);
4764 case Intrinsic::adjust_trampoline: {
4765 setValue(&I, DAG.getNode(ISD::ADJUST_TRAMPOLINE, sdl,
4767 getValue(I.getArgOperand(0))));
4770 case Intrinsic::gcroot:
4772 const Value *Alloca = I.getArgOperand(0)->stripPointerCasts();
4773 const Constant *TypeMap = cast<Constant>(I.getArgOperand(1));
4775 FrameIndexSDNode *FI = cast<FrameIndexSDNode>(getValue(Alloca).getNode());
4776 GFI->addStackRoot(FI->getIndex(), TypeMap);
4779 case Intrinsic::gcread:
4780 case Intrinsic::gcwrite:
4781 llvm_unreachable("GC failed to lower gcread/gcwrite intrinsics!");
4782 case Intrinsic::flt_rounds:
4783 setValue(&I, DAG.getNode(ISD::FLT_ROUNDS_, sdl, MVT::i32));
4786 case Intrinsic::expect: {
4787 // Just replace __builtin_expect(exp, c) with EXP.
4788 setValue(&I, getValue(I.getArgOperand(0)));
4792 case Intrinsic::debugtrap:
4793 case Intrinsic::trap: {
4794 StringRef TrapFuncName = TM.Options.getTrapFunctionName();
4795 if (TrapFuncName.empty()) {
4796 ISD::NodeType Op = (Intrinsic == Intrinsic::trap) ?
4797 ISD::TRAP : ISD::DEBUGTRAP;
4798 DAG.setRoot(DAG.getNode(Op, sdl,MVT::Other, getRoot()));
4801 TargetLowering::ArgListTy Args;
4803 TargetLowering::CallLoweringInfo CLI(DAG);
4804 CLI.setDebugLoc(sdl).setChain(getRoot())
4805 .setCallee(CallingConv::C, I.getType(),
4806 DAG.getExternalSymbol(TrapFuncName.data(), TLI.getPointerTy()),
4807 std::move(Args), 0);
4809 std::pair<SDValue, SDValue> Result = TLI.LowerCallTo(CLI);
4810 DAG.setRoot(Result.second);
4814 case Intrinsic::uadd_with_overflow:
4815 case Intrinsic::sadd_with_overflow:
4816 case Intrinsic::usub_with_overflow:
4817 case Intrinsic::ssub_with_overflow:
4818 case Intrinsic::umul_with_overflow:
4819 case Intrinsic::smul_with_overflow: {
4821 switch (Intrinsic) {
4822 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
4823 case Intrinsic::uadd_with_overflow: Op = ISD::UADDO; break;
4824 case Intrinsic::sadd_with_overflow: Op = ISD::SADDO; break;
4825 case Intrinsic::usub_with_overflow: Op = ISD::USUBO; break;
4826 case Intrinsic::ssub_with_overflow: Op = ISD::SSUBO; break;
4827 case Intrinsic::umul_with_overflow: Op = ISD::UMULO; break;
4828 case Intrinsic::smul_with_overflow: Op = ISD::SMULO; break;
4830 SDValue Op1 = getValue(I.getArgOperand(0));
4831 SDValue Op2 = getValue(I.getArgOperand(1));
4833 SDVTList VTs = DAG.getVTList(Op1.getValueType(), MVT::i1);
4834 setValue(&I, DAG.getNode(Op, sdl, VTs, Op1, Op2));
4837 case Intrinsic::prefetch: {
4839 unsigned rw = cast<ConstantInt>(I.getArgOperand(1))->getZExtValue();
4841 Ops[1] = getValue(I.getArgOperand(0));
4842 Ops[2] = getValue(I.getArgOperand(1));
4843 Ops[3] = getValue(I.getArgOperand(2));
4844 Ops[4] = getValue(I.getArgOperand(3));
4845 DAG.setRoot(DAG.getMemIntrinsicNode(ISD::PREFETCH, sdl,
4846 DAG.getVTList(MVT::Other), Ops,
4847 EVT::getIntegerVT(*Context, 8),
4848 MachinePointerInfo(I.getArgOperand(0)),
4850 false, /* volatile */
4852 rw==1)); /* write */
4855 case Intrinsic::lifetime_start:
4856 case Intrinsic::lifetime_end: {
4857 bool IsStart = (Intrinsic == Intrinsic::lifetime_start);
4858 // Stack coloring is not enabled in O0, discard region information.
4859 if (TM.getOptLevel() == CodeGenOpt::None)
4862 SmallVector<Value *, 4> Allocas;
4863 GetUnderlyingObjects(I.getArgOperand(1), Allocas, *DL);
4865 for (SmallVectorImpl<Value*>::iterator Object = Allocas.begin(),
4866 E = Allocas.end(); Object != E; ++Object) {
4867 AllocaInst *LifetimeObject = dyn_cast_or_null<AllocaInst>(*Object);
4869 // Could not find an Alloca.
4870 if (!LifetimeObject)
4873 // First check that the Alloca is static, otherwise it won't have a
4874 // valid frame index.
4875 auto SI = FuncInfo.StaticAllocaMap.find(LifetimeObject);
4876 if (SI == FuncInfo.StaticAllocaMap.end())
4879 int FI = SI->second;
4883 Ops[1] = DAG.getFrameIndex(FI, TLI.getPointerTy(), true);
4884 unsigned Opcode = (IsStart ? ISD::LIFETIME_START : ISD::LIFETIME_END);
4886 Res = DAG.getNode(Opcode, sdl, MVT::Other, Ops);
4891 case Intrinsic::invariant_start:
4892 // Discard region information.
4893 setValue(&I, DAG.getUNDEF(TLI.getPointerTy()));
4895 case Intrinsic::invariant_end:
4896 // Discard region information.
4898 case Intrinsic::stackprotectorcheck: {
4899 // Do not actually emit anything for this basic block. Instead we initialize
4900 // the stack protector descriptor and export the guard variable so we can
4901 // access it in FinishBasicBlock.
4902 const BasicBlock *BB = I.getParent();
4903 SPDescriptor.initialize(BB, FuncInfo.MBBMap[BB], I);
4904 ExportFromCurrentBlock(SPDescriptor.getGuard());
4906 // Flush our exports since we are going to process a terminator.
4907 (void)getControlRoot();
4910 case Intrinsic::clear_cache:
4911 return TLI.getClearCacheBuiltinName();
4912 case Intrinsic::eh_actions:
4913 setValue(&I, DAG.getUNDEF(TLI.getPointerTy()));
4915 case Intrinsic::donothing:
4918 case Intrinsic::experimental_stackmap: {
4922 case Intrinsic::experimental_patchpoint_void:
4923 case Intrinsic::experimental_patchpoint_i64: {
4924 visitPatchpoint(&I);
4927 case Intrinsic::experimental_gc_statepoint: {
4931 case Intrinsic::experimental_gc_result_int:
4932 case Intrinsic::experimental_gc_result_float:
4933 case Intrinsic::experimental_gc_result_ptr:
4934 case Intrinsic::experimental_gc_result: {
4938 case Intrinsic::experimental_gc_relocate: {
4942 case Intrinsic::instrprof_increment:
4943 llvm_unreachable("instrprof failed to lower an increment");
4945 case Intrinsic::frameescape: {
4946 MachineFunction &MF = DAG.getMachineFunction();
4947 const TargetInstrInfo *TII = DAG.getSubtarget().getInstrInfo();
4949 // Directly emit some FRAME_ALLOC machine instrs. Label assignment emission
4950 // is the same on all targets.
4951 for (unsigned Idx = 0, E = I.getNumArgOperands(); Idx < E; ++Idx) {
4952 Value *Arg = I.getArgOperand(Idx)->stripPointerCasts();
4953 if (isa<ConstantPointerNull>(Arg))
4954 continue; // Skip null pointers. They represent a hole in index space.
4955 AllocaInst *Slot = cast<AllocaInst>(Arg);
4956 assert(FuncInfo.StaticAllocaMap.count(Slot) &&
4957 "can only escape static allocas");
4958 int FI = FuncInfo.StaticAllocaMap[Slot];
4959 MCSymbol *FrameAllocSym =
4960 MF.getMMI().getContext().getOrCreateFrameAllocSymbol(
4961 GlobalValue::getRealLinkageName(MF.getName()), Idx);
4962 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, dl,
4963 TII->get(TargetOpcode::FRAME_ALLOC))
4964 .addSym(FrameAllocSym)
4971 case Intrinsic::framerecover: {
4972 // i8* @llvm.framerecover(i8* %fn, i8* %fp, i32 %idx)
4973 MachineFunction &MF = DAG.getMachineFunction();
4974 MVT PtrVT = TLI.getPointerTy(0);
4976 // Get the symbol that defines the frame offset.
4977 auto *Fn = cast<Function>(I.getArgOperand(0)->stripPointerCasts());
4978 auto *Idx = cast<ConstantInt>(I.getArgOperand(2));
4979 unsigned IdxVal = unsigned(Idx->getLimitedValue(INT_MAX));
4980 MCSymbol *FrameAllocSym =
4981 MF.getMMI().getContext().getOrCreateFrameAllocSymbol(
4982 GlobalValue::getRealLinkageName(Fn->getName()), IdxVal);
4984 // Create a TargetExternalSymbol for the label to avoid any target lowering
4985 // that would make this PC relative.
4986 StringRef Name = FrameAllocSym->getName();
4987 assert(Name.data()[Name.size()] == '\0' && "not null terminated");
4988 SDValue OffsetSym = DAG.getTargetExternalSymbol(Name.data(), PtrVT);
4990 DAG.getNode(ISD::FRAME_ALLOC_RECOVER, sdl, PtrVT, OffsetSym);
4992 // Add the offset to the FP.
4993 Value *FP = I.getArgOperand(1);
4994 SDValue FPVal = getValue(FP);
4995 SDValue Add = DAG.getNode(ISD::ADD, sdl, PtrVT, FPVal, OffsetVal);
5000 case Intrinsic::eh_begincatch:
5001 case Intrinsic::eh_endcatch:
5002 llvm_unreachable("begin/end catch intrinsics not lowered in codegen");
5003 case Intrinsic::eh_exceptioncode: {
5004 unsigned Reg = TLI.getExceptionPointerRegister();
5005 assert(Reg && "cannot get exception code on this platform");
5006 MVT PtrVT = TLI.getPointerTy();
5007 const TargetRegisterClass *PtrRC = TLI.getRegClassFor(PtrVT);
5008 assert(FuncInfo.MBB->isLandingPad() && "eh.exceptioncode in non-lpad");
5009 unsigned VReg = FuncInfo.MBB->addLiveIn(Reg, PtrRC);
5011 DAG.getCopyFromReg(DAG.getEntryNode(), getCurSDLoc(), VReg, PtrVT);
5012 N = DAG.getZExtOrTrunc(N, getCurSDLoc(), MVT::i32);
5019 std::pair<SDValue, SDValue>
5020 SelectionDAGBuilder::lowerInvokable(TargetLowering::CallLoweringInfo &CLI,
5021 MachineBasicBlock *LandingPad) {
5022 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
5023 MCSymbol *BeginLabel = nullptr;
5026 // Insert a label before the invoke call to mark the try range. This can be
5027 // used to detect deletion of the invoke via the MachineModuleInfo.
5028 BeginLabel = MMI.getContext().createTempSymbol();
5030 // For SjLj, keep track of which landing pads go with which invokes
5031 // so as to maintain the ordering of pads in the LSDA.
5032 unsigned CallSiteIndex = MMI.getCurrentCallSite();
5033 if (CallSiteIndex) {
5034 MMI.setCallSiteBeginLabel(BeginLabel, CallSiteIndex);
5035 LPadToCallSiteMap[LandingPad].push_back(CallSiteIndex);
5037 // Now that the call site is handled, stop tracking it.
5038 MMI.setCurrentCallSite(0);
5041 // Both PendingLoads and PendingExports must be flushed here;
5042 // this call might not return.
5044 DAG.setRoot(DAG.getEHLabel(getCurSDLoc(), getControlRoot(), BeginLabel));
5046 CLI.setChain(getRoot());
5048 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5049 std::pair<SDValue, SDValue> Result = TLI.LowerCallTo(CLI);
5051 assert((CLI.IsTailCall || Result.second.getNode()) &&
5052 "Non-null chain expected with non-tail call!");
5053 assert((Result.second.getNode() || !Result.first.getNode()) &&
5054 "Null value expected with tail call!");
5056 if (!Result.second.getNode()) {
5057 // As a special case, a null chain means that a tail call has been emitted
5058 // and the DAG root is already updated.
5061 // Since there's no actual continuation from this block, nothing can be
5062 // relying on us setting vregs for them.
5063 PendingExports.clear();
5065 DAG.setRoot(Result.second);
5069 // Insert a label at the end of the invoke call to mark the try range. This
5070 // can be used to detect deletion of the invoke via the MachineModuleInfo.
5071 MCSymbol *EndLabel = MMI.getContext().createTempSymbol();
5072 DAG.setRoot(DAG.getEHLabel(getCurSDLoc(), getRoot(), EndLabel));
5074 // Inform MachineModuleInfo of range.
5075 MMI.addInvoke(LandingPad, BeginLabel, EndLabel);
5081 void SelectionDAGBuilder::LowerCallTo(ImmutableCallSite CS, SDValue Callee,
5083 MachineBasicBlock *LandingPad) {
5084 PointerType *PT = cast<PointerType>(CS.getCalledValue()->getType());
5085 FunctionType *FTy = cast<FunctionType>(PT->getElementType());
5086 Type *RetTy = FTy->getReturnType();
5088 TargetLowering::ArgListTy Args;
5089 TargetLowering::ArgListEntry Entry;
5090 Args.reserve(CS.arg_size());
5092 for (ImmutableCallSite::arg_iterator i = CS.arg_begin(), e = CS.arg_end();
5094 const Value *V = *i;
5097 if (V->getType()->isEmptyTy())
5100 SDValue ArgNode = getValue(V);
5101 Entry.Node = ArgNode; Entry.Ty = V->getType();
5103 // Skip the first return-type Attribute to get to params.
5104 Entry.setAttributes(&CS, i - CS.arg_begin() + 1);
5105 Args.push_back(Entry);
5107 // If we have an explicit sret argument that is an Instruction, (i.e., it
5108 // might point to function-local memory), we can't meaningfully tail-call.
5109 if (Entry.isSRet && isa<Instruction>(V))
5113 // Check if target-independent constraints permit a tail call here.
5114 // Target-dependent constraints are checked within TLI->LowerCallTo.
5115 if (isTailCall && !isInTailCallPosition(CS, DAG.getTarget()))
5118 TargetLowering::CallLoweringInfo CLI(DAG);
5119 CLI.setDebugLoc(getCurSDLoc()).setChain(getRoot())
5120 .setCallee(RetTy, FTy, Callee, std::move(Args), CS)
5121 .setTailCall(isTailCall);
5122 std::pair<SDValue,SDValue> Result = lowerInvokable(CLI, LandingPad);
5124 if (Result.first.getNode())
5125 setValue(CS.getInstruction(), Result.first);
5128 /// IsOnlyUsedInZeroEqualityComparison - Return true if it only matters that the
5129 /// value is equal or not-equal to zero.
5130 static bool IsOnlyUsedInZeroEqualityComparison(const Value *V) {
5131 for (const User *U : V->users()) {
5132 if (const ICmpInst *IC = dyn_cast<ICmpInst>(U))
5133 if (IC->isEquality())
5134 if (const Constant *C = dyn_cast<Constant>(IC->getOperand(1)))
5135 if (C->isNullValue())
5137 // Unknown instruction.
5143 static SDValue getMemCmpLoad(const Value *PtrVal, MVT LoadVT,
5145 SelectionDAGBuilder &Builder) {
5147 // Check to see if this load can be trivially constant folded, e.g. if the
5148 // input is from a string literal.
5149 if (const Constant *LoadInput = dyn_cast<Constant>(PtrVal)) {
5150 // Cast pointer to the type we really want to load.
5151 LoadInput = ConstantExpr::getBitCast(const_cast<Constant *>(LoadInput),
5152 PointerType::getUnqual(LoadTy));
5154 if (const Constant *LoadCst = ConstantFoldLoadFromConstPtr(
5155 const_cast<Constant *>(LoadInput), *Builder.DL))
5156 return Builder.getValue(LoadCst);
5159 // Otherwise, we have to emit the load. If the pointer is to unfoldable but
5160 // still constant memory, the input chain can be the entry node.
5162 bool ConstantMemory = false;
5164 // Do not serialize (non-volatile) loads of constant memory with anything.
5165 if (Builder.AA->pointsToConstantMemory(PtrVal)) {
5166 Root = Builder.DAG.getEntryNode();
5167 ConstantMemory = true;
5169 // Do not serialize non-volatile loads against each other.
5170 Root = Builder.DAG.getRoot();
5173 SDValue Ptr = Builder.getValue(PtrVal);
5174 SDValue LoadVal = Builder.DAG.getLoad(LoadVT, Builder.getCurSDLoc(), Root,
5175 Ptr, MachinePointerInfo(PtrVal),
5177 false /*nontemporal*/,
5178 false /*isinvariant*/, 1 /* align=1 */);
5180 if (!ConstantMemory)
5181 Builder.PendingLoads.push_back(LoadVal.getValue(1));
5185 /// processIntegerCallValue - Record the value for an instruction that
5186 /// produces an integer result, converting the type where necessary.
5187 void SelectionDAGBuilder::processIntegerCallValue(const Instruction &I,
5190 EVT VT = DAG.getTargetLoweringInfo().getValueType(I.getType(), true);
5192 Value = DAG.getSExtOrTrunc(Value, getCurSDLoc(), VT);
5194 Value = DAG.getZExtOrTrunc(Value, getCurSDLoc(), VT);
5195 setValue(&I, Value);
5198 /// visitMemCmpCall - See if we can lower a call to memcmp in an optimized form.
5199 /// If so, return true and lower it, otherwise return false and it will be
5200 /// lowered like a normal call.
5201 bool SelectionDAGBuilder::visitMemCmpCall(const CallInst &I) {
5202 // Verify that the prototype makes sense. int memcmp(void*,void*,size_t)
5203 if (I.getNumArgOperands() != 3)
5206 const Value *LHS = I.getArgOperand(0), *RHS = I.getArgOperand(1);
5207 if (!LHS->getType()->isPointerTy() || !RHS->getType()->isPointerTy() ||
5208 !I.getArgOperand(2)->getType()->isIntegerTy() ||
5209 !I.getType()->isIntegerTy())
5212 const Value *Size = I.getArgOperand(2);
5213 const ConstantInt *CSize = dyn_cast<ConstantInt>(Size);
5214 if (CSize && CSize->getZExtValue() == 0) {
5215 EVT CallVT = DAG.getTargetLoweringInfo().getValueType(I.getType(), true);
5216 setValue(&I, DAG.getConstant(0, getCurSDLoc(), CallVT));
5220 const TargetSelectionDAGInfo &TSI = DAG.getSelectionDAGInfo();
5221 std::pair<SDValue, SDValue> Res =
5222 TSI.EmitTargetCodeForMemcmp(DAG, getCurSDLoc(), DAG.getRoot(),
5223 getValue(LHS), getValue(RHS), getValue(Size),
5224 MachinePointerInfo(LHS),
5225 MachinePointerInfo(RHS));
5226 if (Res.first.getNode()) {
5227 processIntegerCallValue(I, Res.first, true);
5228 PendingLoads.push_back(Res.second);
5232 // memcmp(S1,S2,2) != 0 -> (*(short*)LHS != *(short*)RHS) != 0
5233 // memcmp(S1,S2,4) != 0 -> (*(int*)LHS != *(int*)RHS) != 0
5234 if (CSize && IsOnlyUsedInZeroEqualityComparison(&I)) {
5235 bool ActuallyDoIt = true;
5238 switch (CSize->getZExtValue()) {
5240 LoadVT = MVT::Other;
5242 ActuallyDoIt = false;
5246 LoadTy = Type::getInt16Ty(CSize->getContext());
5250 LoadTy = Type::getInt32Ty(CSize->getContext());
5254 LoadTy = Type::getInt64Ty(CSize->getContext());
5258 LoadVT = MVT::v4i32;
5259 LoadTy = Type::getInt32Ty(CSize->getContext());
5260 LoadTy = VectorType::get(LoadTy, 4);
5265 // This turns into unaligned loads. We only do this if the target natively
5266 // supports the MVT we'll be loading or if it is small enough (<= 4) that
5267 // we'll only produce a small number of byte loads.
5269 // Require that we can find a legal MVT, and only do this if the target
5270 // supports unaligned loads of that type. Expanding into byte loads would
5272 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5273 if (ActuallyDoIt && CSize->getZExtValue() > 4) {
5274 unsigned DstAS = LHS->getType()->getPointerAddressSpace();
5275 unsigned SrcAS = RHS->getType()->getPointerAddressSpace();
5276 // TODO: Handle 5 byte compare as 4-byte + 1 byte.
5277 // TODO: Handle 8 byte compare on x86-32 as two 32-bit loads.
5278 // TODO: Check alignment of src and dest ptrs.
5279 if (!TLI.isTypeLegal(LoadVT) ||
5280 !TLI.allowsMisalignedMemoryAccesses(LoadVT, SrcAS) ||
5281 !TLI.allowsMisalignedMemoryAccesses(LoadVT, DstAS))
5282 ActuallyDoIt = false;
5286 SDValue LHSVal = getMemCmpLoad(LHS, LoadVT, LoadTy, *this);
5287 SDValue RHSVal = getMemCmpLoad(RHS, LoadVT, LoadTy, *this);
5289 SDValue Res = DAG.getSetCC(getCurSDLoc(), MVT::i1, LHSVal, RHSVal,
5291 processIntegerCallValue(I, Res, false);
5300 /// visitMemChrCall -- See if we can lower a memchr call into an optimized
5301 /// form. If so, return true and lower it, otherwise return false and it
5302 /// will be lowered like a normal call.
5303 bool SelectionDAGBuilder::visitMemChrCall(const CallInst &I) {
5304 // Verify that the prototype makes sense. void *memchr(void *, int, size_t)
5305 if (I.getNumArgOperands() != 3)
5308 const Value *Src = I.getArgOperand(0);
5309 const Value *Char = I.getArgOperand(1);
5310 const Value *Length = I.getArgOperand(2);
5311 if (!Src->getType()->isPointerTy() ||
5312 !Char->getType()->isIntegerTy() ||
5313 !Length->getType()->isIntegerTy() ||
5314 !I.getType()->isPointerTy())
5317 const TargetSelectionDAGInfo &TSI = DAG.getSelectionDAGInfo();
5318 std::pair<SDValue, SDValue> Res =
5319 TSI.EmitTargetCodeForMemchr(DAG, getCurSDLoc(), DAG.getRoot(),
5320 getValue(Src), getValue(Char), getValue(Length),
5321 MachinePointerInfo(Src));
5322 if (Res.first.getNode()) {
5323 setValue(&I, Res.first);
5324 PendingLoads.push_back(Res.second);
5331 /// visitStrCpyCall -- See if we can lower a strcpy or stpcpy call into an
5332 /// optimized form. If so, return true and lower it, otherwise return false
5333 /// and it will be lowered like a normal call.
5334 bool SelectionDAGBuilder::visitStrCpyCall(const CallInst &I, bool isStpcpy) {
5335 // Verify that the prototype makes sense. char *strcpy(char *, char *)
5336 if (I.getNumArgOperands() != 2)
5339 const Value *Arg0 = I.getArgOperand(0), *Arg1 = I.getArgOperand(1);
5340 if (!Arg0->getType()->isPointerTy() ||
5341 !Arg1->getType()->isPointerTy() ||
5342 !I.getType()->isPointerTy())
5345 const TargetSelectionDAGInfo &TSI = DAG.getSelectionDAGInfo();
5346 std::pair<SDValue, SDValue> Res =
5347 TSI.EmitTargetCodeForStrcpy(DAG, getCurSDLoc(), getRoot(),
5348 getValue(Arg0), getValue(Arg1),
5349 MachinePointerInfo(Arg0),
5350 MachinePointerInfo(Arg1), isStpcpy);
5351 if (Res.first.getNode()) {
5352 setValue(&I, Res.first);
5353 DAG.setRoot(Res.second);
5360 /// visitStrCmpCall - See if we can lower a call to strcmp in an optimized form.
5361 /// If so, return true and lower it, otherwise return false and it will be
5362 /// lowered like a normal call.
5363 bool SelectionDAGBuilder::visitStrCmpCall(const CallInst &I) {
5364 // Verify that the prototype makes sense. int strcmp(void*,void*)
5365 if (I.getNumArgOperands() != 2)
5368 const Value *Arg0 = I.getArgOperand(0), *Arg1 = I.getArgOperand(1);
5369 if (!Arg0->getType()->isPointerTy() ||
5370 !Arg1->getType()->isPointerTy() ||
5371 !I.getType()->isIntegerTy())
5374 const TargetSelectionDAGInfo &TSI = DAG.getSelectionDAGInfo();
5375 std::pair<SDValue, SDValue> Res =
5376 TSI.EmitTargetCodeForStrcmp(DAG, getCurSDLoc(), DAG.getRoot(),
5377 getValue(Arg0), getValue(Arg1),
5378 MachinePointerInfo(Arg0),
5379 MachinePointerInfo(Arg1));
5380 if (Res.first.getNode()) {
5381 processIntegerCallValue(I, Res.first, true);
5382 PendingLoads.push_back(Res.second);
5389 /// visitStrLenCall -- See if we can lower a strlen call into an optimized
5390 /// form. If so, return true and lower it, otherwise return false and it
5391 /// will be lowered like a normal call.
5392 bool SelectionDAGBuilder::visitStrLenCall(const CallInst &I) {
5393 // Verify that the prototype makes sense. size_t strlen(char *)
5394 if (I.getNumArgOperands() != 1)
5397 const Value *Arg0 = I.getArgOperand(0);
5398 if (!Arg0->getType()->isPointerTy() || !I.getType()->isIntegerTy())
5401 const TargetSelectionDAGInfo &TSI = DAG.getSelectionDAGInfo();
5402 std::pair<SDValue, SDValue> Res =
5403 TSI.EmitTargetCodeForStrlen(DAG, getCurSDLoc(), DAG.getRoot(),
5404 getValue(Arg0), MachinePointerInfo(Arg0));
5405 if (Res.first.getNode()) {
5406 processIntegerCallValue(I, Res.first, false);
5407 PendingLoads.push_back(Res.second);
5414 /// visitStrNLenCall -- See if we can lower a strnlen call into an optimized
5415 /// form. If so, return true and lower it, otherwise return false and it
5416 /// will be lowered like a normal call.
5417 bool SelectionDAGBuilder::visitStrNLenCall(const CallInst &I) {
5418 // Verify that the prototype makes sense. size_t strnlen(char *, size_t)
5419 if (I.getNumArgOperands() != 2)
5422 const Value *Arg0 = I.getArgOperand(0), *Arg1 = I.getArgOperand(1);
5423 if (!Arg0->getType()->isPointerTy() ||
5424 !Arg1->getType()->isIntegerTy() ||
5425 !I.getType()->isIntegerTy())
5428 const TargetSelectionDAGInfo &TSI = DAG.getSelectionDAGInfo();
5429 std::pair<SDValue, SDValue> Res =
5430 TSI.EmitTargetCodeForStrnlen(DAG, getCurSDLoc(), DAG.getRoot(),
5431 getValue(Arg0), getValue(Arg1),
5432 MachinePointerInfo(Arg0));
5433 if (Res.first.getNode()) {
5434 processIntegerCallValue(I, Res.first, false);
5435 PendingLoads.push_back(Res.second);
5442 /// visitUnaryFloatCall - If a call instruction is a unary floating-point
5443 /// operation (as expected), translate it to an SDNode with the specified opcode
5444 /// and return true.
5445 bool SelectionDAGBuilder::visitUnaryFloatCall(const CallInst &I,
5447 // Sanity check that it really is a unary floating-point call.
5448 if (I.getNumArgOperands() != 1 ||
5449 !I.getArgOperand(0)->getType()->isFloatingPointTy() ||
5450 I.getType() != I.getArgOperand(0)->getType() ||
5451 !I.onlyReadsMemory())
5454 SDValue Tmp = getValue(I.getArgOperand(0));
5455 setValue(&I, DAG.getNode(Opcode, getCurSDLoc(), Tmp.getValueType(), Tmp));
5459 /// visitBinaryFloatCall - If a call instruction is a binary floating-point
5460 /// operation (as expected), translate it to an SDNode with the specified opcode
5461 /// and return true.
5462 bool SelectionDAGBuilder::visitBinaryFloatCall(const CallInst &I,
5464 // Sanity check that it really is a binary floating-point call.
5465 if (I.getNumArgOperands() != 2 ||
5466 !I.getArgOperand(0)->getType()->isFloatingPointTy() ||
5467 I.getType() != I.getArgOperand(0)->getType() ||
5468 I.getType() != I.getArgOperand(1)->getType() ||
5469 !I.onlyReadsMemory())
5472 SDValue Tmp0 = getValue(I.getArgOperand(0));
5473 SDValue Tmp1 = getValue(I.getArgOperand(1));
5474 EVT VT = Tmp0.getValueType();
5475 setValue(&I, DAG.getNode(Opcode, getCurSDLoc(), VT, Tmp0, Tmp1));
5479 void SelectionDAGBuilder::visitCall(const CallInst &I) {
5480 // Handle inline assembly differently.
5481 if (isa<InlineAsm>(I.getCalledValue())) {
5486 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
5487 ComputeUsesVAFloatArgument(I, &MMI);
5489 const char *RenameFn = nullptr;
5490 if (Function *F = I.getCalledFunction()) {
5491 if (F->isDeclaration()) {
5492 if (const TargetIntrinsicInfo *II = TM.getIntrinsicInfo()) {
5493 if (unsigned IID = II->getIntrinsicID(F)) {
5494 RenameFn = visitIntrinsicCall(I, IID);
5499 if (Intrinsic::ID IID = F->getIntrinsicID()) {
5500 RenameFn = visitIntrinsicCall(I, IID);
5506 // Check for well-known libc/libm calls. If the function is internal, it
5507 // can't be a library call.
5509 if (!F->hasLocalLinkage() && F->hasName() &&
5510 LibInfo->getLibFunc(F->getName(), Func) &&
5511 LibInfo->hasOptimizedCodeGen(Func)) {
5514 case LibFunc::copysign:
5515 case LibFunc::copysignf:
5516 case LibFunc::copysignl:
5517 if (I.getNumArgOperands() == 2 && // Basic sanity checks.
5518 I.getArgOperand(0)->getType()->isFloatingPointTy() &&
5519 I.getType() == I.getArgOperand(0)->getType() &&
5520 I.getType() == I.getArgOperand(1)->getType() &&
5521 I.onlyReadsMemory()) {
5522 SDValue LHS = getValue(I.getArgOperand(0));
5523 SDValue RHS = getValue(I.getArgOperand(1));
5524 setValue(&I, DAG.getNode(ISD::FCOPYSIGN, getCurSDLoc(),
5525 LHS.getValueType(), LHS, RHS));
5530 case LibFunc::fabsf:
5531 case LibFunc::fabsl:
5532 if (visitUnaryFloatCall(I, ISD::FABS))
5536 case LibFunc::fminf:
5537 case LibFunc::fminl:
5538 if (visitBinaryFloatCall(I, ISD::FMINNUM))
5542 case LibFunc::fmaxf:
5543 case LibFunc::fmaxl:
5544 if (visitBinaryFloatCall(I, ISD::FMAXNUM))
5550 if (visitUnaryFloatCall(I, ISD::FSIN))
5556 if (visitUnaryFloatCall(I, ISD::FCOS))
5560 case LibFunc::sqrtf:
5561 case LibFunc::sqrtl:
5562 case LibFunc::sqrt_finite:
5563 case LibFunc::sqrtf_finite:
5564 case LibFunc::sqrtl_finite:
5565 if (visitUnaryFloatCall(I, ISD::FSQRT))
5568 case LibFunc::floor:
5569 case LibFunc::floorf:
5570 case LibFunc::floorl:
5571 if (visitUnaryFloatCall(I, ISD::FFLOOR))
5574 case LibFunc::nearbyint:
5575 case LibFunc::nearbyintf:
5576 case LibFunc::nearbyintl:
5577 if (visitUnaryFloatCall(I, ISD::FNEARBYINT))
5581 case LibFunc::ceilf:
5582 case LibFunc::ceill:
5583 if (visitUnaryFloatCall(I, ISD::FCEIL))
5587 case LibFunc::rintf:
5588 case LibFunc::rintl:
5589 if (visitUnaryFloatCall(I, ISD::FRINT))
5592 case LibFunc::round:
5593 case LibFunc::roundf:
5594 case LibFunc::roundl:
5595 if (visitUnaryFloatCall(I, ISD::FROUND))
5598 case LibFunc::trunc:
5599 case LibFunc::truncf:
5600 case LibFunc::truncl:
5601 if (visitUnaryFloatCall(I, ISD::FTRUNC))
5605 case LibFunc::log2f:
5606 case LibFunc::log2l:
5607 if (visitUnaryFloatCall(I, ISD::FLOG2))
5611 case LibFunc::exp2f:
5612 case LibFunc::exp2l:
5613 if (visitUnaryFloatCall(I, ISD::FEXP2))
5616 case LibFunc::memcmp:
5617 if (visitMemCmpCall(I))
5620 case LibFunc::memchr:
5621 if (visitMemChrCall(I))
5624 case LibFunc::strcpy:
5625 if (visitStrCpyCall(I, false))
5628 case LibFunc::stpcpy:
5629 if (visitStrCpyCall(I, true))
5632 case LibFunc::strcmp:
5633 if (visitStrCmpCall(I))
5636 case LibFunc::strlen:
5637 if (visitStrLenCall(I))
5640 case LibFunc::strnlen:
5641 if (visitStrNLenCall(I))
5650 Callee = getValue(I.getCalledValue());
5652 Callee = DAG.getExternalSymbol(RenameFn,
5653 DAG.getTargetLoweringInfo().getPointerTy());
5655 // Check if we can potentially perform a tail call. More detailed checking is
5656 // be done within LowerCallTo, after more information about the call is known.
5657 LowerCallTo(&I, Callee, I.isTailCall());
5662 /// AsmOperandInfo - This contains information for each constraint that we are
5664 class SDISelAsmOperandInfo : public TargetLowering::AsmOperandInfo {
5666 /// CallOperand - If this is the result output operand or a clobber
5667 /// this is null, otherwise it is the incoming operand to the CallInst.
5668 /// This gets modified as the asm is processed.
5669 SDValue CallOperand;
5671 /// AssignedRegs - If this is a register or register class operand, this
5672 /// contains the set of register corresponding to the operand.
5673 RegsForValue AssignedRegs;
5675 explicit SDISelAsmOperandInfo(const TargetLowering::AsmOperandInfo &info)
5676 : TargetLowering::AsmOperandInfo(info), CallOperand(nullptr,0) {
5679 /// getCallOperandValEVT - Return the EVT of the Value* that this operand
5680 /// corresponds to. If there is no Value* for this operand, it returns
5682 EVT getCallOperandValEVT(LLVMContext &Context,
5683 const TargetLowering &TLI,
5684 const DataLayout *DL) const {
5685 if (!CallOperandVal) return MVT::Other;
5687 if (isa<BasicBlock>(CallOperandVal))
5688 return TLI.getPointerTy();
5690 llvm::Type *OpTy = CallOperandVal->getType();
5692 // FIXME: code duplicated from TargetLowering::ParseConstraints().
5693 // If this is an indirect operand, the operand is a pointer to the
5696 llvm::PointerType *PtrTy = dyn_cast<PointerType>(OpTy);
5698 report_fatal_error("Indirect operand for inline asm not a pointer!");
5699 OpTy = PtrTy->getElementType();
5702 // Look for vector wrapped in a struct. e.g. { <16 x i8> }.
5703 if (StructType *STy = dyn_cast<StructType>(OpTy))
5704 if (STy->getNumElements() == 1)
5705 OpTy = STy->getElementType(0);
5707 // If OpTy is not a single value, it may be a struct/union that we
5708 // can tile with integers.
5709 if (!OpTy->isSingleValueType() && OpTy->isSized()) {
5710 unsigned BitSize = DL->getTypeSizeInBits(OpTy);
5719 OpTy = IntegerType::get(Context, BitSize);
5724 return TLI.getValueType(OpTy, true);
5728 typedef SmallVector<SDISelAsmOperandInfo,16> SDISelAsmOperandInfoVector;
5730 } // end anonymous namespace
5732 /// GetRegistersForValue - Assign registers (virtual or physical) for the
5733 /// specified operand. We prefer to assign virtual registers, to allow the
5734 /// register allocator to handle the assignment process. However, if the asm
5735 /// uses features that we can't model on machineinstrs, we have SDISel do the
5736 /// allocation. This produces generally horrible, but correct, code.
5738 /// OpInfo describes the operand.
5740 static void GetRegistersForValue(SelectionDAG &DAG,
5741 const TargetLowering &TLI,
5743 SDISelAsmOperandInfo &OpInfo) {
5744 LLVMContext &Context = *DAG.getContext();
5746 MachineFunction &MF = DAG.getMachineFunction();
5747 SmallVector<unsigned, 4> Regs;
5749 // If this is a constraint for a single physreg, or a constraint for a
5750 // register class, find it.
5751 std::pair<unsigned, const TargetRegisterClass *> PhysReg =
5752 TLI.getRegForInlineAsmConstraint(MF.getSubtarget().getRegisterInfo(),
5753 OpInfo.ConstraintCode,
5754 OpInfo.ConstraintVT);
5756 unsigned NumRegs = 1;
5757 if (OpInfo.ConstraintVT != MVT::Other) {
5758 // If this is a FP input in an integer register (or visa versa) insert a bit
5759 // cast of the input value. More generally, handle any case where the input
5760 // value disagrees with the register class we plan to stick this in.
5761 if (OpInfo.Type == InlineAsm::isInput &&
5762 PhysReg.second && !PhysReg.second->hasType(OpInfo.ConstraintVT)) {
5763 // Try to convert to the first EVT that the reg class contains. If the
5764 // types are identical size, use a bitcast to convert (e.g. two differing
5766 MVT RegVT = *PhysReg.second->vt_begin();
5767 if (RegVT.getSizeInBits() == OpInfo.CallOperand.getValueSizeInBits()) {
5768 OpInfo.CallOperand = DAG.getNode(ISD::BITCAST, DL,
5769 RegVT, OpInfo.CallOperand);
5770 OpInfo.ConstraintVT = RegVT;
5771 } else if (RegVT.isInteger() && OpInfo.ConstraintVT.isFloatingPoint()) {
5772 // If the input is a FP value and we want it in FP registers, do a
5773 // bitcast to the corresponding integer type. This turns an f64 value
5774 // into i64, which can be passed with two i32 values on a 32-bit
5776 RegVT = MVT::getIntegerVT(OpInfo.ConstraintVT.getSizeInBits());
5777 OpInfo.CallOperand = DAG.getNode(ISD::BITCAST, DL,
5778 RegVT, OpInfo.CallOperand);
5779 OpInfo.ConstraintVT = RegVT;
5783 NumRegs = TLI.getNumRegisters(Context, OpInfo.ConstraintVT);
5787 EVT ValueVT = OpInfo.ConstraintVT;
5789 // If this is a constraint for a specific physical register, like {r17},
5791 if (unsigned AssignedReg = PhysReg.first) {
5792 const TargetRegisterClass *RC = PhysReg.second;
5793 if (OpInfo.ConstraintVT == MVT::Other)
5794 ValueVT = *RC->vt_begin();
5796 // Get the actual register value type. This is important, because the user
5797 // may have asked for (e.g.) the AX register in i32 type. We need to
5798 // remember that AX is actually i16 to get the right extension.
5799 RegVT = *RC->vt_begin();
5801 // This is a explicit reference to a physical register.
5802 Regs.push_back(AssignedReg);
5804 // If this is an expanded reference, add the rest of the regs to Regs.
5806 TargetRegisterClass::iterator I = RC->begin();
5807 for (; *I != AssignedReg; ++I)
5808 assert(I != RC->end() && "Didn't find reg!");
5810 // Already added the first reg.
5812 for (; NumRegs; --NumRegs, ++I) {
5813 assert(I != RC->end() && "Ran out of registers to allocate!");
5818 OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT);
5822 // Otherwise, if this was a reference to an LLVM register class, create vregs
5823 // for this reference.
5824 if (const TargetRegisterClass *RC = PhysReg.second) {
5825 RegVT = *RC->vt_begin();
5826 if (OpInfo.ConstraintVT == MVT::Other)
5829 // Create the appropriate number of virtual registers.
5830 MachineRegisterInfo &RegInfo = MF.getRegInfo();
5831 for (; NumRegs; --NumRegs)
5832 Regs.push_back(RegInfo.createVirtualRegister(RC));
5834 OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT);
5838 // Otherwise, we couldn't allocate enough registers for this.
5841 /// visitInlineAsm - Handle a call to an InlineAsm object.
5843 void SelectionDAGBuilder::visitInlineAsm(ImmutableCallSite CS) {
5844 const InlineAsm *IA = cast<InlineAsm>(CS.getCalledValue());
5846 /// ConstraintOperands - Information about all of the constraints.
5847 SDISelAsmOperandInfoVector ConstraintOperands;
5849 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5850 TargetLowering::AsmOperandInfoVector TargetConstraints =
5851 TLI.ParseConstraints(DAG.getSubtarget().getRegisterInfo(), CS);
5853 bool hasMemory = false;
5855 unsigned ArgNo = 0; // ArgNo - The argument of the CallInst.
5856 unsigned ResNo = 0; // ResNo - The result number of the next output.
5857 for (unsigned i = 0, e = TargetConstraints.size(); i != e; ++i) {
5858 ConstraintOperands.push_back(SDISelAsmOperandInfo(TargetConstraints[i]));
5859 SDISelAsmOperandInfo &OpInfo = ConstraintOperands.back();
5861 MVT OpVT = MVT::Other;
5863 // Compute the value type for each operand.
5864 switch (OpInfo.Type) {
5865 case InlineAsm::isOutput:
5866 // Indirect outputs just consume an argument.
5867 if (OpInfo.isIndirect) {
5868 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++));
5872 // The return value of the call is this value. As such, there is no
5873 // corresponding argument.
5874 assert(!CS.getType()->isVoidTy() && "Bad inline asm!");
5875 if (StructType *STy = dyn_cast<StructType>(CS.getType())) {
5876 OpVT = TLI.getSimpleValueType(STy->getElementType(ResNo));
5878 assert(ResNo == 0 && "Asm only has one result!");
5879 OpVT = TLI.getSimpleValueType(CS.getType());
5883 case InlineAsm::isInput:
5884 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++));
5886 case InlineAsm::isClobber:
5891 // If this is an input or an indirect output, process the call argument.
5892 // BasicBlocks are labels, currently appearing only in asm's.
5893 if (OpInfo.CallOperandVal) {
5894 if (const BasicBlock *BB = dyn_cast<BasicBlock>(OpInfo.CallOperandVal)) {
5895 OpInfo.CallOperand = DAG.getBasicBlock(FuncInfo.MBBMap[BB]);
5897 OpInfo.CallOperand = getValue(OpInfo.CallOperandVal);
5901 OpInfo.getCallOperandValEVT(*DAG.getContext(), TLI, DL).getSimpleVT();
5904 OpInfo.ConstraintVT = OpVT;
5906 // Indirect operand accesses access memory.
5907 if (OpInfo.isIndirect)
5910 for (unsigned j = 0, ee = OpInfo.Codes.size(); j != ee; ++j) {
5911 TargetLowering::ConstraintType
5912 CType = TLI.getConstraintType(OpInfo.Codes[j]);
5913 if (CType == TargetLowering::C_Memory) {
5921 SDValue Chain, Flag;
5923 // We won't need to flush pending loads if this asm doesn't touch
5924 // memory and is nonvolatile.
5925 if (hasMemory || IA->hasSideEffects())
5928 Chain = DAG.getRoot();
5930 // Second pass over the constraints: compute which constraint option to use
5931 // and assign registers to constraints that want a specific physreg.
5932 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
5933 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
5935 // If this is an output operand with a matching input operand, look up the
5936 // matching input. If their types mismatch, e.g. one is an integer, the
5937 // other is floating point, or their sizes are different, flag it as an
5939 if (OpInfo.hasMatchingInput()) {
5940 SDISelAsmOperandInfo &Input = ConstraintOperands[OpInfo.MatchingInput];
5942 if (OpInfo.ConstraintVT != Input.ConstraintVT) {
5943 const TargetRegisterInfo *TRI = DAG.getSubtarget().getRegisterInfo();
5944 std::pair<unsigned, const TargetRegisterClass *> MatchRC =
5945 TLI.getRegForInlineAsmConstraint(TRI, OpInfo.ConstraintCode,
5946 OpInfo.ConstraintVT);
5947 std::pair<unsigned, const TargetRegisterClass *> InputRC =
5948 TLI.getRegForInlineAsmConstraint(TRI, Input.ConstraintCode,
5949 Input.ConstraintVT);
5950 if ((OpInfo.ConstraintVT.isInteger() !=
5951 Input.ConstraintVT.isInteger()) ||
5952 (MatchRC.second != InputRC.second)) {
5953 report_fatal_error("Unsupported asm: input constraint"
5954 " with a matching output constraint of"
5955 " incompatible type!");
5957 Input.ConstraintVT = OpInfo.ConstraintVT;
5961 // Compute the constraint code and ConstraintType to use.
5962 TLI.ComputeConstraintToUse(OpInfo, OpInfo.CallOperand, &DAG);
5964 if (OpInfo.ConstraintType == TargetLowering::C_Memory &&
5965 OpInfo.Type == InlineAsm::isClobber)
5968 // If this is a memory input, and if the operand is not indirect, do what we
5969 // need to to provide an address for the memory input.
5970 if (OpInfo.ConstraintType == TargetLowering::C_Memory &&
5971 !OpInfo.isIndirect) {
5972 assert((OpInfo.isMultipleAlternative ||
5973 (OpInfo.Type == InlineAsm::isInput)) &&
5974 "Can only indirectify direct input operands!");
5976 // Memory operands really want the address of the value. If we don't have
5977 // an indirect input, put it in the constpool if we can, otherwise spill
5978 // it to a stack slot.
5979 // TODO: This isn't quite right. We need to handle these according to
5980 // the addressing mode that the constraint wants. Also, this may take
5981 // an additional register for the computation and we don't want that
5984 // If the operand is a float, integer, or vector constant, spill to a
5985 // constant pool entry to get its address.
5986 const Value *OpVal = OpInfo.CallOperandVal;
5987 if (isa<ConstantFP>(OpVal) || isa<ConstantInt>(OpVal) ||
5988 isa<ConstantVector>(OpVal) || isa<ConstantDataVector>(OpVal)) {
5989 OpInfo.CallOperand = DAG.getConstantPool(cast<Constant>(OpVal),
5990 TLI.getPointerTy());
5992 // Otherwise, create a stack slot and emit a store to it before the
5994 Type *Ty = OpVal->getType();
5995 uint64_t TySize = TLI.getDataLayout()->getTypeAllocSize(Ty);
5996 unsigned Align = TLI.getDataLayout()->getPrefTypeAlignment(Ty);
5997 MachineFunction &MF = DAG.getMachineFunction();
5998 int SSFI = MF.getFrameInfo()->CreateStackObject(TySize, Align, false);
5999 SDValue StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy());
6000 Chain = DAG.getStore(Chain, getCurSDLoc(),
6001 OpInfo.CallOperand, StackSlot,
6002 MachinePointerInfo::getFixedStack(SSFI),
6004 OpInfo.CallOperand = StackSlot;
6007 // There is no longer a Value* corresponding to this operand.
6008 OpInfo.CallOperandVal = nullptr;
6010 // It is now an indirect operand.
6011 OpInfo.isIndirect = true;
6014 // If this constraint is for a specific register, allocate it before
6016 if (OpInfo.ConstraintType == TargetLowering::C_Register)
6017 GetRegistersForValue(DAG, TLI, getCurSDLoc(), OpInfo);
6020 // Second pass - Loop over all of the operands, assigning virtual or physregs
6021 // to register class operands.
6022 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
6023 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
6025 // C_Register operands have already been allocated, Other/Memory don't need
6027 if (OpInfo.ConstraintType == TargetLowering::C_RegisterClass)
6028 GetRegistersForValue(DAG, TLI, getCurSDLoc(), OpInfo);
6031 // AsmNodeOperands - The operands for the ISD::INLINEASM node.
6032 std::vector<SDValue> AsmNodeOperands;
6033 AsmNodeOperands.push_back(SDValue()); // reserve space for input chain
6034 AsmNodeOperands.push_back(
6035 DAG.getTargetExternalSymbol(IA->getAsmString().c_str(),
6036 TLI.getPointerTy()));
6038 // If we have a !srcloc metadata node associated with it, we want to attach
6039 // this to the ultimately generated inline asm machineinstr. To do this, we
6040 // pass in the third operand as this (potentially null) inline asm MDNode.
6041 const MDNode *SrcLoc = CS.getInstruction()->getMetadata("srcloc");
6042 AsmNodeOperands.push_back(DAG.getMDNode(SrcLoc));
6044 // Remember the HasSideEffect, AlignStack, AsmDialect, MayLoad and MayStore
6045 // bits as operand 3.
6046 unsigned ExtraInfo = 0;
6047 if (IA->hasSideEffects())
6048 ExtraInfo |= InlineAsm::Extra_HasSideEffects;
6049 if (IA->isAlignStack())
6050 ExtraInfo |= InlineAsm::Extra_IsAlignStack;
6051 // Set the asm dialect.
6052 ExtraInfo |= IA->getDialect() * InlineAsm::Extra_AsmDialect;
6054 // Determine if this InlineAsm MayLoad or MayStore based on the constraints.
6055 for (unsigned i = 0, e = TargetConstraints.size(); i != e; ++i) {
6056 TargetLowering::AsmOperandInfo &OpInfo = TargetConstraints[i];
6058 // Compute the constraint code and ConstraintType to use.
6059 TLI.ComputeConstraintToUse(OpInfo, SDValue());
6061 // Ideally, we would only check against memory constraints. However, the
6062 // meaning of an other constraint can be target-specific and we can't easily
6063 // reason about it. Therefore, be conservative and set MayLoad/MayStore
6064 // for other constriants as well.
6065 if (OpInfo.ConstraintType == TargetLowering::C_Memory ||
6066 OpInfo.ConstraintType == TargetLowering::C_Other) {
6067 if (OpInfo.Type == InlineAsm::isInput)
6068 ExtraInfo |= InlineAsm::Extra_MayLoad;
6069 else if (OpInfo.Type == InlineAsm::isOutput)
6070 ExtraInfo |= InlineAsm::Extra_MayStore;
6071 else if (OpInfo.Type == InlineAsm::isClobber)
6072 ExtraInfo |= (InlineAsm::Extra_MayLoad | InlineAsm::Extra_MayStore);
6076 AsmNodeOperands.push_back(DAG.getTargetConstant(ExtraInfo, getCurSDLoc(),
6077 TLI.getPointerTy()));
6079 // Loop over all of the inputs, copying the operand values into the
6080 // appropriate registers and processing the output regs.
6081 RegsForValue RetValRegs;
6083 // IndirectStoresToEmit - The set of stores to emit after the inline asm node.
6084 std::vector<std::pair<RegsForValue, Value*> > IndirectStoresToEmit;
6086 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
6087 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
6089 switch (OpInfo.Type) {
6090 case InlineAsm::isOutput: {
6091 if (OpInfo.ConstraintType != TargetLowering::C_RegisterClass &&
6092 OpInfo.ConstraintType != TargetLowering::C_Register) {
6093 // Memory output, or 'other' output (e.g. 'X' constraint).
6094 assert(OpInfo.isIndirect && "Memory output must be indirect operand");
6096 unsigned ConstraintID =
6097 TLI.getInlineAsmMemConstraint(OpInfo.ConstraintCode);
6098 assert(ConstraintID != InlineAsm::Constraint_Unknown &&
6099 "Failed to convert memory constraint code to constraint id.");
6101 // Add information to the INLINEASM node to know about this output.
6102 unsigned OpFlags = InlineAsm::getFlagWord(InlineAsm::Kind_Mem, 1);
6103 OpFlags = InlineAsm::getFlagWordForMem(OpFlags, ConstraintID);
6104 AsmNodeOperands.push_back(DAG.getTargetConstant(OpFlags, getCurSDLoc(),
6106 AsmNodeOperands.push_back(OpInfo.CallOperand);
6110 // Otherwise, this is a register or register class output.
6112 // Copy the output from the appropriate register. Find a register that
6114 if (OpInfo.AssignedRegs.Regs.empty()) {
6115 LLVMContext &Ctx = *DAG.getContext();
6116 Ctx.emitError(CS.getInstruction(),
6117 "couldn't allocate output register for constraint '" +
6118 Twine(OpInfo.ConstraintCode) + "'");
6122 // If this is an indirect operand, store through the pointer after the
6124 if (OpInfo.isIndirect) {
6125 IndirectStoresToEmit.push_back(std::make_pair(OpInfo.AssignedRegs,
6126 OpInfo.CallOperandVal));
6128 // This is the result value of the call.
6129 assert(!CS.getType()->isVoidTy() && "Bad inline asm!");
6130 // Concatenate this output onto the outputs list.
6131 RetValRegs.append(OpInfo.AssignedRegs);
6134 // Add information to the INLINEASM node to know that this register is
6137 .AddInlineAsmOperands(OpInfo.isEarlyClobber
6138 ? InlineAsm::Kind_RegDefEarlyClobber
6139 : InlineAsm::Kind_RegDef,
6140 false, 0, getCurSDLoc(), DAG, AsmNodeOperands);
6143 case InlineAsm::isInput: {
6144 SDValue InOperandVal = OpInfo.CallOperand;
6146 if (OpInfo.isMatchingInputConstraint()) { // Matching constraint?
6147 // If this is required to match an output register we have already set,
6148 // just use its register.
6149 unsigned OperandNo = OpInfo.getMatchedOperand();
6151 // Scan until we find the definition we already emitted of this operand.
6152 // When we find it, create a RegsForValue operand.
6153 unsigned CurOp = InlineAsm::Op_FirstOperand;
6154 for (; OperandNo; --OperandNo) {
6155 // Advance to the next operand.
6157 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue();
6158 assert((InlineAsm::isRegDefKind(OpFlag) ||
6159 InlineAsm::isRegDefEarlyClobberKind(OpFlag) ||
6160 InlineAsm::isMemKind(OpFlag)) && "Skipped past definitions?");
6161 CurOp += InlineAsm::getNumOperandRegisters(OpFlag)+1;
6165 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue();
6166 if (InlineAsm::isRegDefKind(OpFlag) ||
6167 InlineAsm::isRegDefEarlyClobberKind(OpFlag)) {
6168 // Add (OpFlag&0xffff)>>3 registers to MatchedRegs.
6169 if (OpInfo.isIndirect) {
6170 // This happens on gcc/testsuite/gcc.dg/pr8788-1.c
6171 LLVMContext &Ctx = *DAG.getContext();
6172 Ctx.emitError(CS.getInstruction(), "inline asm not supported yet:"
6173 " don't know how to handle tied "
6174 "indirect register inputs");
6178 RegsForValue MatchedRegs;
6179 MatchedRegs.ValueVTs.push_back(InOperandVal.getValueType());
6180 MVT RegVT = AsmNodeOperands[CurOp+1].getSimpleValueType();
6181 MatchedRegs.RegVTs.push_back(RegVT);
6182 MachineRegisterInfo &RegInfo = DAG.getMachineFunction().getRegInfo();
6183 for (unsigned i = 0, e = InlineAsm::getNumOperandRegisters(OpFlag);
6185 if (const TargetRegisterClass *RC = TLI.getRegClassFor(RegVT))
6186 MatchedRegs.Regs.push_back(RegInfo.createVirtualRegister(RC));
6188 LLVMContext &Ctx = *DAG.getContext();
6189 Ctx.emitError(CS.getInstruction(),
6190 "inline asm error: This value"
6191 " type register class is not natively supported!");
6195 SDLoc dl = getCurSDLoc();
6196 // Use the produced MatchedRegs object to
6197 MatchedRegs.getCopyToRegs(InOperandVal, DAG, dl,
6198 Chain, &Flag, CS.getInstruction());
6199 MatchedRegs.AddInlineAsmOperands(InlineAsm::Kind_RegUse,
6200 true, OpInfo.getMatchedOperand(), dl,
6201 DAG, AsmNodeOperands);
6205 assert(InlineAsm::isMemKind(OpFlag) && "Unknown matching constraint!");
6206 assert(InlineAsm::getNumOperandRegisters(OpFlag) == 1 &&
6207 "Unexpected number of operands");
6208 // Add information to the INLINEASM node to know about this input.
6209 // See InlineAsm.h isUseOperandTiedToDef.
6210 OpFlag = InlineAsm::convertMemFlagWordToMatchingFlagWord(OpFlag);
6211 OpFlag = InlineAsm::getFlagWordForMatchingOp(OpFlag,
6212 OpInfo.getMatchedOperand());
6213 AsmNodeOperands.push_back(DAG.getTargetConstant(OpFlag, getCurSDLoc(),
6214 TLI.getPointerTy()));
6215 AsmNodeOperands.push_back(AsmNodeOperands[CurOp+1]);
6219 // Treat indirect 'X' constraint as memory.
6220 if (OpInfo.ConstraintType == TargetLowering::C_Other &&
6222 OpInfo.ConstraintType = TargetLowering::C_Memory;
6224 if (OpInfo.ConstraintType == TargetLowering::C_Other) {
6225 std::vector<SDValue> Ops;
6226 TLI.LowerAsmOperandForConstraint(InOperandVal, OpInfo.ConstraintCode,
6229 LLVMContext &Ctx = *DAG.getContext();
6230 Ctx.emitError(CS.getInstruction(),
6231 "invalid operand for inline asm constraint '" +
6232 Twine(OpInfo.ConstraintCode) + "'");
6236 // Add information to the INLINEASM node to know about this input.
6237 unsigned ResOpType =
6238 InlineAsm::getFlagWord(InlineAsm::Kind_Imm, Ops.size());
6239 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
6241 TLI.getPointerTy()));
6242 AsmNodeOperands.insert(AsmNodeOperands.end(), Ops.begin(), Ops.end());
6246 if (OpInfo.ConstraintType == TargetLowering::C_Memory) {
6247 assert(OpInfo.isIndirect && "Operand must be indirect to be a mem!");
6248 assert(InOperandVal.getValueType() == TLI.getPointerTy() &&
6249 "Memory operands expect pointer values");
6251 unsigned ConstraintID =
6252 TLI.getInlineAsmMemConstraint(OpInfo.ConstraintCode);
6253 assert(ConstraintID != InlineAsm::Constraint_Unknown &&
6254 "Failed to convert memory constraint code to constraint id.");
6256 // Add information to the INLINEASM node to know about this input.
6257 unsigned ResOpType = InlineAsm::getFlagWord(InlineAsm::Kind_Mem, 1);
6258 ResOpType = InlineAsm::getFlagWordForMem(ResOpType, ConstraintID);
6259 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
6262 AsmNodeOperands.push_back(InOperandVal);
6266 assert((OpInfo.ConstraintType == TargetLowering::C_RegisterClass ||
6267 OpInfo.ConstraintType == TargetLowering::C_Register) &&
6268 "Unknown constraint type!");
6270 // TODO: Support this.
6271 if (OpInfo.isIndirect) {
6272 LLVMContext &Ctx = *DAG.getContext();
6273 Ctx.emitError(CS.getInstruction(),
6274 "Don't know how to handle indirect register inputs yet "
6275 "for constraint '" +
6276 Twine(OpInfo.ConstraintCode) + "'");
6280 // Copy the input into the appropriate registers.
6281 if (OpInfo.AssignedRegs.Regs.empty()) {
6282 LLVMContext &Ctx = *DAG.getContext();
6283 Ctx.emitError(CS.getInstruction(),
6284 "couldn't allocate input reg for constraint '" +
6285 Twine(OpInfo.ConstraintCode) + "'");
6289 SDLoc dl = getCurSDLoc();
6291 OpInfo.AssignedRegs.getCopyToRegs(InOperandVal, DAG, dl,
6292 Chain, &Flag, CS.getInstruction());
6294 OpInfo.AssignedRegs.AddInlineAsmOperands(InlineAsm::Kind_RegUse, false, 0,
6295 dl, DAG, AsmNodeOperands);
6298 case InlineAsm::isClobber: {
6299 // Add the clobbered value to the operand list, so that the register
6300 // allocator is aware that the physreg got clobbered.
6301 if (!OpInfo.AssignedRegs.Regs.empty())
6302 OpInfo.AssignedRegs.AddInlineAsmOperands(InlineAsm::Kind_Clobber,
6303 false, 0, getCurSDLoc(), DAG,
6310 // Finish up input operands. Set the input chain and add the flag last.
6311 AsmNodeOperands[InlineAsm::Op_InputChain] = Chain;
6312 if (Flag.getNode()) AsmNodeOperands.push_back(Flag);
6314 Chain = DAG.getNode(ISD::INLINEASM, getCurSDLoc(),
6315 DAG.getVTList(MVT::Other, MVT::Glue), AsmNodeOperands);
6316 Flag = Chain.getValue(1);
6318 // If this asm returns a register value, copy the result from that register
6319 // and set it as the value of the call.
6320 if (!RetValRegs.Regs.empty()) {
6321 SDValue Val = RetValRegs.getCopyFromRegs(DAG, FuncInfo, getCurSDLoc(),
6322 Chain, &Flag, CS.getInstruction());
6324 // FIXME: Why don't we do this for inline asms with MRVs?
6325 if (CS.getType()->isSingleValueType() && CS.getType()->isSized()) {
6326 EVT ResultType = TLI.getValueType(CS.getType());
6328 // If any of the results of the inline asm is a vector, it may have the
6329 // wrong width/num elts. This can happen for register classes that can
6330 // contain multiple different value types. The preg or vreg allocated may
6331 // not have the same VT as was expected. Convert it to the right type
6332 // with bit_convert.
6333 if (ResultType != Val.getValueType() && Val.getValueType().isVector()) {
6334 Val = DAG.getNode(ISD::BITCAST, getCurSDLoc(),
6337 } else if (ResultType != Val.getValueType() &&
6338 ResultType.isInteger() && Val.getValueType().isInteger()) {
6339 // If a result value was tied to an input value, the computed result may
6340 // have a wider width than the expected result. Extract the relevant
6342 Val = DAG.getNode(ISD::TRUNCATE, getCurSDLoc(), ResultType, Val);
6345 assert(ResultType == Val.getValueType() && "Asm result value mismatch!");
6348 setValue(CS.getInstruction(), Val);
6349 // Don't need to use this as a chain in this case.
6350 if (!IA->hasSideEffects() && !hasMemory && IndirectStoresToEmit.empty())
6354 std::vector<std::pair<SDValue, const Value *> > StoresToEmit;
6356 // Process indirect outputs, first output all of the flagged copies out of
6358 for (unsigned i = 0, e = IndirectStoresToEmit.size(); i != e; ++i) {
6359 RegsForValue &OutRegs = IndirectStoresToEmit[i].first;
6360 const Value *Ptr = IndirectStoresToEmit[i].second;
6361 SDValue OutVal = OutRegs.getCopyFromRegs(DAG, FuncInfo, getCurSDLoc(),
6363 StoresToEmit.push_back(std::make_pair(OutVal, Ptr));
6366 // Emit the non-flagged stores from the physregs.
6367 SmallVector<SDValue, 8> OutChains;
6368 for (unsigned i = 0, e = StoresToEmit.size(); i != e; ++i) {
6369 SDValue Val = DAG.getStore(Chain, getCurSDLoc(),
6370 StoresToEmit[i].first,
6371 getValue(StoresToEmit[i].second),
6372 MachinePointerInfo(StoresToEmit[i].second),
6374 OutChains.push_back(Val);
6377 if (!OutChains.empty())
6378 Chain = DAG.getNode(ISD::TokenFactor, getCurSDLoc(), MVT::Other, OutChains);
6383 void SelectionDAGBuilder::visitVAStart(const CallInst &I) {
6384 DAG.setRoot(DAG.getNode(ISD::VASTART, getCurSDLoc(),
6385 MVT::Other, getRoot(),
6386 getValue(I.getArgOperand(0)),
6387 DAG.getSrcValue(I.getArgOperand(0))));
6390 void SelectionDAGBuilder::visitVAArg(const VAArgInst &I) {
6391 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6392 const DataLayout &DL = *TLI.getDataLayout();
6393 SDValue V = DAG.getVAArg(TLI.getValueType(I.getType()), getCurSDLoc(),
6394 getRoot(), getValue(I.getOperand(0)),
6395 DAG.getSrcValue(I.getOperand(0)),
6396 DL.getABITypeAlignment(I.getType()));
6398 DAG.setRoot(V.getValue(1));
6401 void SelectionDAGBuilder::visitVAEnd(const CallInst &I) {
6402 DAG.setRoot(DAG.getNode(ISD::VAEND, getCurSDLoc(),
6403 MVT::Other, getRoot(),
6404 getValue(I.getArgOperand(0)),
6405 DAG.getSrcValue(I.getArgOperand(0))));
6408 void SelectionDAGBuilder::visitVACopy(const CallInst &I) {
6409 DAG.setRoot(DAG.getNode(ISD::VACOPY, getCurSDLoc(),
6410 MVT::Other, getRoot(),
6411 getValue(I.getArgOperand(0)),
6412 getValue(I.getArgOperand(1)),
6413 DAG.getSrcValue(I.getArgOperand(0)),
6414 DAG.getSrcValue(I.getArgOperand(1))));
6417 /// \brief Lower an argument list according to the target calling convention.
6419 /// \return A tuple of <return-value, token-chain>
6421 /// This is a helper for lowering intrinsics that follow a target calling
6422 /// convention or require stack pointer adjustment. Only a subset of the
6423 /// intrinsic's operands need to participate in the calling convention.
6424 std::pair<SDValue, SDValue>
6425 SelectionDAGBuilder::lowerCallOperands(ImmutableCallSite CS, unsigned ArgIdx,
6426 unsigned NumArgs, SDValue Callee,
6428 MachineBasicBlock *LandingPad,
6429 bool IsPatchPoint) {
6430 TargetLowering::ArgListTy Args;
6431 Args.reserve(NumArgs);
6433 // Populate the argument list.
6434 // Attributes for args start at offset 1, after the return attribute.
6435 for (unsigned ArgI = ArgIdx, ArgE = ArgIdx + NumArgs, AttrI = ArgIdx + 1;
6436 ArgI != ArgE; ++ArgI) {
6437 const Value *V = CS->getOperand(ArgI);
6439 assert(!V->getType()->isEmptyTy() && "Empty type passed to intrinsic.");
6441 TargetLowering::ArgListEntry Entry;
6442 Entry.Node = getValue(V);
6443 Entry.Ty = V->getType();
6444 Entry.setAttributes(&CS, AttrI);
6445 Args.push_back(Entry);
6448 TargetLowering::CallLoweringInfo CLI(DAG);
6449 CLI.setDebugLoc(getCurSDLoc()).setChain(getRoot())
6450 .setCallee(CS.getCallingConv(), ReturnTy, Callee, std::move(Args), NumArgs)
6451 .setDiscardResult(CS->use_empty()).setIsPatchPoint(IsPatchPoint);
6453 return lowerInvokable(CLI, LandingPad);
6456 /// \brief Add a stack map intrinsic call's live variable operands to a stackmap
6457 /// or patchpoint target node's operand list.
6459 /// Constants are converted to TargetConstants purely as an optimization to
6460 /// avoid constant materialization and register allocation.
6462 /// FrameIndex operands are converted to TargetFrameIndex so that ISEL does not
6463 /// generate addess computation nodes, and so ExpandISelPseudo can convert the
6464 /// TargetFrameIndex into a DirectMemRefOp StackMap location. This avoids
6465 /// address materialization and register allocation, but may also be required
6466 /// for correctness. If a StackMap (or PatchPoint) intrinsic directly uses an
6467 /// alloca in the entry block, then the runtime may assume that the alloca's
6468 /// StackMap location can be read immediately after compilation and that the
6469 /// location is valid at any point during execution (this is similar to the
6470 /// assumption made by the llvm.gcroot intrinsic). If the alloca's location were
6471 /// only available in a register, then the runtime would need to trap when
6472 /// execution reaches the StackMap in order to read the alloca's location.
6473 static void addStackMapLiveVars(ImmutableCallSite CS, unsigned StartIdx,
6474 SDLoc DL, SmallVectorImpl<SDValue> &Ops,
6475 SelectionDAGBuilder &Builder) {
6476 for (unsigned i = StartIdx, e = CS.arg_size(); i != e; ++i) {
6477 SDValue OpVal = Builder.getValue(CS.getArgument(i));
6478 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(OpVal)) {
6480 Builder.DAG.getTargetConstant(StackMaps::ConstantOp, DL, MVT::i64));
6482 Builder.DAG.getTargetConstant(C->getSExtValue(), DL, MVT::i64));
6483 } else if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(OpVal)) {
6484 const TargetLowering &TLI = Builder.DAG.getTargetLoweringInfo();
6486 Builder.DAG.getTargetFrameIndex(FI->getIndex(), TLI.getPointerTy()));
6488 Ops.push_back(OpVal);
6492 /// \brief Lower llvm.experimental.stackmap directly to its target opcode.
6493 void SelectionDAGBuilder::visitStackmap(const CallInst &CI) {
6494 // void @llvm.experimental.stackmap(i32 <id>, i32 <numShadowBytes>,
6495 // [live variables...])
6497 assert(CI.getType()->isVoidTy() && "Stackmap cannot return a value.");
6499 SDValue Chain, InFlag, Callee, NullPtr;
6500 SmallVector<SDValue, 32> Ops;
6502 SDLoc DL = getCurSDLoc();
6503 Callee = getValue(CI.getCalledValue());
6504 NullPtr = DAG.getIntPtrConstant(0, DL, true);
6506 // The stackmap intrinsic only records the live variables (the arguemnts
6507 // passed to it) and emits NOPS (if requested). Unlike the patchpoint
6508 // intrinsic, this won't be lowered to a function call. This means we don't
6509 // have to worry about calling conventions and target specific lowering code.
6510 // Instead we perform the call lowering right here.
6512 // chain, flag = CALLSEQ_START(chain, 0)
6513 // chain, flag = STACKMAP(id, nbytes, ..., chain, flag)
6514 // chain, flag = CALLSEQ_END(chain, 0, 0, flag)
6516 Chain = DAG.getCALLSEQ_START(getRoot(), NullPtr, DL);
6517 InFlag = Chain.getValue(1);
6519 // Add the <id> and <numBytes> constants.
6520 SDValue IDVal = getValue(CI.getOperand(PatchPointOpers::IDPos));
6521 Ops.push_back(DAG.getTargetConstant(
6522 cast<ConstantSDNode>(IDVal)->getZExtValue(), DL, MVT::i64));
6523 SDValue NBytesVal = getValue(CI.getOperand(PatchPointOpers::NBytesPos));
6524 Ops.push_back(DAG.getTargetConstant(
6525 cast<ConstantSDNode>(NBytesVal)->getZExtValue(), DL,
6528 // Push live variables for the stack map.
6529 addStackMapLiveVars(&CI, 2, DL, Ops, *this);
6531 // We are not pushing any register mask info here on the operands list,
6532 // because the stackmap doesn't clobber anything.
6534 // Push the chain and the glue flag.
6535 Ops.push_back(Chain);
6536 Ops.push_back(InFlag);
6538 // Create the STACKMAP node.
6539 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
6540 SDNode *SM = DAG.getMachineNode(TargetOpcode::STACKMAP, DL, NodeTys, Ops);
6541 Chain = SDValue(SM, 0);
6542 InFlag = Chain.getValue(1);
6544 Chain = DAG.getCALLSEQ_END(Chain, NullPtr, NullPtr, InFlag, DL);
6546 // Stackmaps don't generate values, so nothing goes into the NodeMap.
6548 // Set the root to the target-lowered call chain.
6551 // Inform the Frame Information that we have a stackmap in this function.
6552 FuncInfo.MF->getFrameInfo()->setHasStackMap();
6555 /// \brief Lower llvm.experimental.patchpoint directly to its target opcode.
6556 void SelectionDAGBuilder::visitPatchpoint(ImmutableCallSite CS,
6557 MachineBasicBlock *LandingPad) {
6558 // void|i64 @llvm.experimental.patchpoint.void|i64(i64 <id>,
6563 // [live variables...])
6565 CallingConv::ID CC = CS.getCallingConv();
6566 bool IsAnyRegCC = CC == CallingConv::AnyReg;
6567 bool HasDef = !CS->getType()->isVoidTy();
6568 SDLoc dl = getCurSDLoc();
6569 SDValue Callee = getValue(CS->getOperand(PatchPointOpers::TargetPos));
6571 // Handle immediate and symbolic callees.
6572 if (auto* ConstCallee = dyn_cast<ConstantSDNode>(Callee))
6573 Callee = DAG.getIntPtrConstant(ConstCallee->getZExtValue(), dl,
6575 else if (auto* SymbolicCallee = dyn_cast<GlobalAddressSDNode>(Callee))
6576 Callee = DAG.getTargetGlobalAddress(SymbolicCallee->getGlobal(),
6577 SDLoc(SymbolicCallee),
6578 SymbolicCallee->getValueType(0));
6580 // Get the real number of arguments participating in the call <numArgs>
6581 SDValue NArgVal = getValue(CS.getArgument(PatchPointOpers::NArgPos));
6582 unsigned NumArgs = cast<ConstantSDNode>(NArgVal)->getZExtValue();
6584 // Skip the four meta args: <id>, <numNopBytes>, <target>, <numArgs>
6585 // Intrinsics include all meta-operands up to but not including CC.
6586 unsigned NumMetaOpers = PatchPointOpers::CCPos;
6587 assert(CS.arg_size() >= NumMetaOpers + NumArgs &&
6588 "Not enough arguments provided to the patchpoint intrinsic");
6590 // For AnyRegCC the arguments are lowered later on manually.
6591 unsigned NumCallArgs = IsAnyRegCC ? 0 : NumArgs;
6593 IsAnyRegCC ? Type::getVoidTy(*DAG.getContext()) : CS->getType();
6594 std::pair<SDValue, SDValue> Result =
6595 lowerCallOperands(CS, NumMetaOpers, NumCallArgs, Callee, ReturnTy,
6598 SDNode *CallEnd = Result.second.getNode();
6599 if (HasDef && (CallEnd->getOpcode() == ISD::CopyFromReg))
6600 CallEnd = CallEnd->getOperand(0).getNode();
6602 /// Get a call instruction from the call sequence chain.
6603 /// Tail calls are not allowed.
6604 assert(CallEnd->getOpcode() == ISD::CALLSEQ_END &&
6605 "Expected a callseq node.");
6606 SDNode *Call = CallEnd->getOperand(0).getNode();
6607 bool HasGlue = Call->getGluedNode();
6609 // Replace the target specific call node with the patchable intrinsic.
6610 SmallVector<SDValue, 8> Ops;
6612 // Add the <id> and <numBytes> constants.
6613 SDValue IDVal = getValue(CS->getOperand(PatchPointOpers::IDPos));
6614 Ops.push_back(DAG.getTargetConstant(
6615 cast<ConstantSDNode>(IDVal)->getZExtValue(), dl, MVT::i64));
6616 SDValue NBytesVal = getValue(CS->getOperand(PatchPointOpers::NBytesPos));
6617 Ops.push_back(DAG.getTargetConstant(
6618 cast<ConstantSDNode>(NBytesVal)->getZExtValue(), dl,
6622 Ops.push_back(Callee);
6624 // Adjust <numArgs> to account for any arguments that have been passed on the
6626 // Call Node: Chain, Target, {Args}, RegMask, [Glue]
6627 unsigned NumCallRegArgs = Call->getNumOperands() - (HasGlue ? 4 : 3);
6628 NumCallRegArgs = IsAnyRegCC ? NumArgs : NumCallRegArgs;
6629 Ops.push_back(DAG.getTargetConstant(NumCallRegArgs, dl, MVT::i32));
6631 // Add the calling convention
6632 Ops.push_back(DAG.getTargetConstant((unsigned)CC, dl, MVT::i32));
6634 // Add the arguments we omitted previously. The register allocator should
6635 // place these in any free register.
6637 for (unsigned i = NumMetaOpers, e = NumMetaOpers + NumArgs; i != e; ++i)
6638 Ops.push_back(getValue(CS.getArgument(i)));
6640 // Push the arguments from the call instruction up to the register mask.
6641 SDNode::op_iterator e = HasGlue ? Call->op_end()-2 : Call->op_end()-1;
6642 Ops.append(Call->op_begin() + 2, e);
6644 // Push live variables for the stack map.
6645 addStackMapLiveVars(CS, NumMetaOpers + NumArgs, dl, Ops, *this);
6647 // Push the register mask info.
6649 Ops.push_back(*(Call->op_end()-2));
6651 Ops.push_back(*(Call->op_end()-1));
6653 // Push the chain (this is originally the first operand of the call, but
6654 // becomes now the last or second to last operand).
6655 Ops.push_back(*(Call->op_begin()));
6657 // Push the glue flag (last operand).
6659 Ops.push_back(*(Call->op_end()-1));
6662 if (IsAnyRegCC && HasDef) {
6663 // Create the return types based on the intrinsic definition
6664 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6665 SmallVector<EVT, 3> ValueVTs;
6666 ComputeValueVTs(TLI, CS->getType(), ValueVTs);
6667 assert(ValueVTs.size() == 1 && "Expected only one return value type.");
6669 // There is always a chain and a glue type at the end
6670 ValueVTs.push_back(MVT::Other);
6671 ValueVTs.push_back(MVT::Glue);
6672 NodeTys = DAG.getVTList(ValueVTs);
6674 NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
6676 // Replace the target specific call node with a PATCHPOINT node.
6677 MachineSDNode *MN = DAG.getMachineNode(TargetOpcode::PATCHPOINT,
6680 // Update the NodeMap.
6683 setValue(CS.getInstruction(), SDValue(MN, 0));
6685 setValue(CS.getInstruction(), Result.first);
6688 // Fixup the consumers of the intrinsic. The chain and glue may be used in the
6689 // call sequence. Furthermore the location of the chain and glue can change
6690 // when the AnyReg calling convention is used and the intrinsic returns a
6692 if (IsAnyRegCC && HasDef) {
6693 SDValue From[] = {SDValue(Call, 0), SDValue(Call, 1)};
6694 SDValue To[] = {SDValue(MN, 1), SDValue(MN, 2)};
6695 DAG.ReplaceAllUsesOfValuesWith(From, To, 2);
6697 DAG.ReplaceAllUsesWith(Call, MN);
6698 DAG.DeleteNode(Call);
6700 // Inform the Frame Information that we have a patchpoint in this function.
6701 FuncInfo.MF->getFrameInfo()->setHasPatchPoint();
6704 /// Returns an AttributeSet representing the attributes applied to the return
6705 /// value of the given call.
6706 static AttributeSet getReturnAttrs(TargetLowering::CallLoweringInfo &CLI) {
6707 SmallVector<Attribute::AttrKind, 2> Attrs;
6709 Attrs.push_back(Attribute::SExt);
6711 Attrs.push_back(Attribute::ZExt);
6713 Attrs.push_back(Attribute::InReg);
6715 return AttributeSet::get(CLI.RetTy->getContext(), AttributeSet::ReturnIndex,
6719 /// TargetLowering::LowerCallTo - This is the default LowerCallTo
6720 /// implementation, which just calls LowerCall.
6721 /// FIXME: When all targets are
6722 /// migrated to using LowerCall, this hook should be integrated into SDISel.
6723 std::pair<SDValue, SDValue>
6724 TargetLowering::LowerCallTo(TargetLowering::CallLoweringInfo &CLI) const {
6725 // Handle the incoming return values from the call.
6727 Type *OrigRetTy = CLI.RetTy;
6728 SmallVector<EVT, 4> RetTys;
6729 SmallVector<uint64_t, 4> Offsets;
6730 ComputeValueVTs(*this, CLI.RetTy, RetTys, &Offsets);
6732 SmallVector<ISD::OutputArg, 4> Outs;
6733 GetReturnInfo(CLI.RetTy, getReturnAttrs(CLI), Outs, *this);
6735 bool CanLowerReturn =
6736 this->CanLowerReturn(CLI.CallConv, CLI.DAG.getMachineFunction(),
6737 CLI.IsVarArg, Outs, CLI.RetTy->getContext());
6739 SDValue DemoteStackSlot;
6740 int DemoteStackIdx = -100;
6741 if (!CanLowerReturn) {
6742 // FIXME: equivalent assert?
6743 // assert(!CS.hasInAllocaArgument() &&
6744 // "sret demotion is incompatible with inalloca");
6745 uint64_t TySize = getDataLayout()->getTypeAllocSize(CLI.RetTy);
6746 unsigned Align = getDataLayout()->getPrefTypeAlignment(CLI.RetTy);
6747 MachineFunction &MF = CLI.DAG.getMachineFunction();
6748 DemoteStackIdx = MF.getFrameInfo()->CreateStackObject(TySize, Align, false);
6749 Type *StackSlotPtrType = PointerType::getUnqual(CLI.RetTy);
6751 DemoteStackSlot = CLI.DAG.getFrameIndex(DemoteStackIdx, getPointerTy());
6753 Entry.Node = DemoteStackSlot;
6754 Entry.Ty = StackSlotPtrType;
6755 Entry.isSExt = false;
6756 Entry.isZExt = false;
6757 Entry.isInReg = false;
6758 Entry.isSRet = true;
6759 Entry.isNest = false;
6760 Entry.isByVal = false;
6761 Entry.isReturned = false;
6762 Entry.Alignment = Align;
6763 CLI.getArgs().insert(CLI.getArgs().begin(), Entry);
6764 CLI.RetTy = Type::getVoidTy(CLI.RetTy->getContext());
6766 // sret demotion isn't compatible with tail-calls, since the sret argument
6767 // points into the callers stack frame.
6768 CLI.IsTailCall = false;
6770 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
6772 MVT RegisterVT = getRegisterType(CLI.RetTy->getContext(), VT);
6773 unsigned NumRegs = getNumRegisters(CLI.RetTy->getContext(), VT);
6774 for (unsigned i = 0; i != NumRegs; ++i) {
6775 ISD::InputArg MyFlags;
6776 MyFlags.VT = RegisterVT;
6778 MyFlags.Used = CLI.IsReturnValueUsed;
6780 MyFlags.Flags.setSExt();
6782 MyFlags.Flags.setZExt();
6784 MyFlags.Flags.setInReg();
6785 CLI.Ins.push_back(MyFlags);
6790 // Handle all of the outgoing arguments.
6792 CLI.OutVals.clear();
6793 ArgListTy &Args = CLI.getArgs();
6794 for (unsigned i = 0, e = Args.size(); i != e; ++i) {
6795 SmallVector<EVT, 4> ValueVTs;
6796 ComputeValueVTs(*this, Args[i].Ty, ValueVTs);
6797 Type *FinalType = Args[i].Ty;
6798 if (Args[i].isByVal)
6799 FinalType = cast<PointerType>(Args[i].Ty)->getElementType();
6800 bool NeedsRegBlock = functionArgumentNeedsConsecutiveRegisters(
6801 FinalType, CLI.CallConv, CLI.IsVarArg);
6802 for (unsigned Value = 0, NumValues = ValueVTs.size(); Value != NumValues;
6804 EVT VT = ValueVTs[Value];
6805 Type *ArgTy = VT.getTypeForEVT(CLI.RetTy->getContext());
6806 SDValue Op = SDValue(Args[i].Node.getNode(),
6807 Args[i].Node.getResNo() + Value);
6808 ISD::ArgFlagsTy Flags;
6809 unsigned OriginalAlignment = getDataLayout()->getABITypeAlignment(ArgTy);
6815 if (Args[i].isInReg)
6819 if (Args[i].isByVal)
6821 if (Args[i].isInAlloca) {
6822 Flags.setInAlloca();
6823 // Set the byval flag for CCAssignFn callbacks that don't know about
6824 // inalloca. This way we can know how many bytes we should've allocated
6825 // and how many bytes a callee cleanup function will pop. If we port
6826 // inalloca to more targets, we'll have to add custom inalloca handling
6827 // in the various CC lowering callbacks.
6830 if (Args[i].isByVal || Args[i].isInAlloca) {
6831 PointerType *Ty = cast<PointerType>(Args[i].Ty);
6832 Type *ElementTy = Ty->getElementType();
6833 Flags.setByValSize(getDataLayout()->getTypeAllocSize(ElementTy));
6834 // For ByVal, alignment should come from FE. BE will guess if this
6835 // info is not there but there are cases it cannot get right.
6836 unsigned FrameAlign;
6837 if (Args[i].Alignment)
6838 FrameAlign = Args[i].Alignment;
6840 FrameAlign = getByValTypeAlignment(ElementTy);
6841 Flags.setByValAlign(FrameAlign);
6846 Flags.setInConsecutiveRegs();
6847 Flags.setOrigAlign(OriginalAlignment);
6849 MVT PartVT = getRegisterType(CLI.RetTy->getContext(), VT);
6850 unsigned NumParts = getNumRegisters(CLI.RetTy->getContext(), VT);
6851 SmallVector<SDValue, 4> Parts(NumParts);
6852 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
6855 ExtendKind = ISD::SIGN_EXTEND;
6856 else if (Args[i].isZExt)
6857 ExtendKind = ISD::ZERO_EXTEND;
6859 // Conservatively only handle 'returned' on non-vectors for now
6860 if (Args[i].isReturned && !Op.getValueType().isVector()) {
6861 assert(CLI.RetTy == Args[i].Ty && RetTys.size() == NumValues &&
6862 "unexpected use of 'returned'");
6863 // Before passing 'returned' to the target lowering code, ensure that
6864 // either the register MVT and the actual EVT are the same size or that
6865 // the return value and argument are extended in the same way; in these
6866 // cases it's safe to pass the argument register value unchanged as the
6867 // return register value (although it's at the target's option whether
6869 // TODO: allow code generation to take advantage of partially preserved
6870 // registers rather than clobbering the entire register when the
6871 // parameter extension method is not compatible with the return
6873 if ((NumParts * PartVT.getSizeInBits() == VT.getSizeInBits()) ||
6874 (ExtendKind != ISD::ANY_EXTEND &&
6875 CLI.RetSExt == Args[i].isSExt && CLI.RetZExt == Args[i].isZExt))
6876 Flags.setReturned();
6879 getCopyToParts(CLI.DAG, CLI.DL, Op, &Parts[0], NumParts, PartVT,
6880 CLI.CS ? CLI.CS->getInstruction() : nullptr, ExtendKind);
6882 for (unsigned j = 0; j != NumParts; ++j) {
6883 // if it isn't first piece, alignment must be 1
6884 ISD::OutputArg MyFlags(Flags, Parts[j].getValueType(), VT,
6885 i < CLI.NumFixedArgs,
6886 i, j*Parts[j].getValueType().getStoreSize());
6887 if (NumParts > 1 && j == 0)
6888 MyFlags.Flags.setSplit();
6890 MyFlags.Flags.setOrigAlign(1);
6892 CLI.Outs.push_back(MyFlags);
6893 CLI.OutVals.push_back(Parts[j]);
6896 if (NeedsRegBlock && Value == NumValues - 1)
6897 CLI.Outs[CLI.Outs.size() - 1].Flags.setInConsecutiveRegsLast();
6901 SmallVector<SDValue, 4> InVals;
6902 CLI.Chain = LowerCall(CLI, InVals);
6904 // Verify that the target's LowerCall behaved as expected.
6905 assert(CLI.Chain.getNode() && CLI.Chain.getValueType() == MVT::Other &&
6906 "LowerCall didn't return a valid chain!");
6907 assert((!CLI.IsTailCall || InVals.empty()) &&
6908 "LowerCall emitted a return value for a tail call!");
6909 assert((CLI.IsTailCall || InVals.size() == CLI.Ins.size()) &&
6910 "LowerCall didn't emit the correct number of values!");
6912 // For a tail call, the return value is merely live-out and there aren't
6913 // any nodes in the DAG representing it. Return a special value to
6914 // indicate that a tail call has been emitted and no more Instructions
6915 // should be processed in the current block.
6916 if (CLI.IsTailCall) {
6917 CLI.DAG.setRoot(CLI.Chain);
6918 return std::make_pair(SDValue(), SDValue());
6921 DEBUG(for (unsigned i = 0, e = CLI.Ins.size(); i != e; ++i) {
6922 assert(InVals[i].getNode() &&
6923 "LowerCall emitted a null value!");
6924 assert(EVT(CLI.Ins[i].VT) == InVals[i].getValueType() &&
6925 "LowerCall emitted a value with the wrong type!");
6928 SmallVector<SDValue, 4> ReturnValues;
6929 if (!CanLowerReturn) {
6930 // The instruction result is the result of loading from the
6931 // hidden sret parameter.
6932 SmallVector<EVT, 1> PVTs;
6933 Type *PtrRetTy = PointerType::getUnqual(OrigRetTy);
6935 ComputeValueVTs(*this, PtrRetTy, PVTs);
6936 assert(PVTs.size() == 1 && "Pointers should fit in one register");
6937 EVT PtrVT = PVTs[0];
6939 unsigned NumValues = RetTys.size();
6940 ReturnValues.resize(NumValues);
6941 SmallVector<SDValue, 4> Chains(NumValues);
6943 for (unsigned i = 0; i < NumValues; ++i) {
6944 SDValue Add = CLI.DAG.getNode(ISD::ADD, CLI.DL, PtrVT, DemoteStackSlot,
6945 CLI.DAG.getConstant(Offsets[i], CLI.DL,
6947 SDValue L = CLI.DAG.getLoad(
6948 RetTys[i], CLI.DL, CLI.Chain, Add,
6949 MachinePointerInfo::getFixedStack(DemoteStackIdx, Offsets[i]), false,
6951 ReturnValues[i] = L;
6952 Chains[i] = L.getValue(1);
6955 CLI.Chain = CLI.DAG.getNode(ISD::TokenFactor, CLI.DL, MVT::Other, Chains);
6957 // Collect the legal value parts into potentially illegal values
6958 // that correspond to the original function's return values.
6959 ISD::NodeType AssertOp = ISD::DELETED_NODE;
6961 AssertOp = ISD::AssertSext;
6962 else if (CLI.RetZExt)
6963 AssertOp = ISD::AssertZext;
6964 unsigned CurReg = 0;
6965 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
6967 MVT RegisterVT = getRegisterType(CLI.RetTy->getContext(), VT);
6968 unsigned NumRegs = getNumRegisters(CLI.RetTy->getContext(), VT);
6970 ReturnValues.push_back(getCopyFromParts(CLI.DAG, CLI.DL, &InVals[CurReg],
6971 NumRegs, RegisterVT, VT, nullptr,
6976 // For a function returning void, there is no return value. We can't create
6977 // such a node, so we just return a null return value in that case. In
6978 // that case, nothing will actually look at the value.
6979 if (ReturnValues.empty())
6980 return std::make_pair(SDValue(), CLI.Chain);
6983 SDValue Res = CLI.DAG.getNode(ISD::MERGE_VALUES, CLI.DL,
6984 CLI.DAG.getVTList(RetTys), ReturnValues);
6985 return std::make_pair(Res, CLI.Chain);
6988 void TargetLowering::LowerOperationWrapper(SDNode *N,
6989 SmallVectorImpl<SDValue> &Results,
6990 SelectionDAG &DAG) const {
6991 SDValue Res = LowerOperation(SDValue(N, 0), DAG);
6993 Results.push_back(Res);
6996 SDValue TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
6997 llvm_unreachable("LowerOperation not implemented for this target!");
7001 SelectionDAGBuilder::CopyValueToVirtualRegister(const Value *V, unsigned Reg) {
7002 SDValue Op = getNonRegisterValue(V);
7003 assert((Op.getOpcode() != ISD::CopyFromReg ||
7004 cast<RegisterSDNode>(Op.getOperand(1))->getReg() != Reg) &&
7005 "Copy from a reg to the same reg!");
7006 assert(!TargetRegisterInfo::isPhysicalRegister(Reg) && "Is a physreg");
7008 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
7009 RegsForValue RFV(V->getContext(), TLI, Reg, V->getType());
7010 SDValue Chain = DAG.getEntryNode();
7012 ISD::NodeType ExtendType = (FuncInfo.PreferredExtendType.find(V) ==
7013 FuncInfo.PreferredExtendType.end())
7015 : FuncInfo.PreferredExtendType[V];
7016 RFV.getCopyToRegs(Op, DAG, getCurSDLoc(), Chain, nullptr, V, ExtendType);
7017 PendingExports.push_back(Chain);
7020 #include "llvm/CodeGen/SelectionDAGISel.h"
7022 /// isOnlyUsedInEntryBlock - If the specified argument is only used in the
7023 /// entry block, return true. This includes arguments used by switches, since
7024 /// the switch may expand into multiple basic blocks.
7025 static bool isOnlyUsedInEntryBlock(const Argument *A, bool FastISel) {
7026 // With FastISel active, we may be splitting blocks, so force creation
7027 // of virtual registers for all non-dead arguments.
7029 return A->use_empty();
7031 const BasicBlock *Entry = A->getParent()->begin();
7032 for (const User *U : A->users())
7033 if (cast<Instruction>(U)->getParent() != Entry || isa<SwitchInst>(U))
7034 return false; // Use not in entry block.
7039 void SelectionDAGISel::LowerArguments(const Function &F) {
7040 SelectionDAG &DAG = SDB->DAG;
7041 SDLoc dl = SDB->getCurSDLoc();
7042 const DataLayout *DL = TLI->getDataLayout();
7043 SmallVector<ISD::InputArg, 16> Ins;
7045 if (!FuncInfo->CanLowerReturn) {
7046 // Put in an sret pointer parameter before all the other parameters.
7047 SmallVector<EVT, 1> ValueVTs;
7048 ComputeValueVTs(*TLI, PointerType::getUnqual(F.getReturnType()), ValueVTs);
7050 // NOTE: Assuming that a pointer will never break down to more than one VT
7052 ISD::ArgFlagsTy Flags;
7054 MVT RegisterVT = TLI->getRegisterType(*DAG.getContext(), ValueVTs[0]);
7055 ISD::InputArg RetArg(Flags, RegisterVT, ValueVTs[0], true,
7056 ISD::InputArg::NoArgIndex, 0);
7057 Ins.push_back(RetArg);
7060 // Set up the incoming argument description vector.
7062 for (Function::const_arg_iterator I = F.arg_begin(), E = F.arg_end();
7063 I != E; ++I, ++Idx) {
7064 SmallVector<EVT, 4> ValueVTs;
7065 ComputeValueVTs(*TLI, I->getType(), ValueVTs);
7066 bool isArgValueUsed = !I->use_empty();
7067 unsigned PartBase = 0;
7068 Type *FinalType = I->getType();
7069 if (F.getAttributes().hasAttribute(Idx, Attribute::ByVal))
7070 FinalType = cast<PointerType>(FinalType)->getElementType();
7071 bool NeedsRegBlock = TLI->functionArgumentNeedsConsecutiveRegisters(
7072 FinalType, F.getCallingConv(), F.isVarArg());
7073 for (unsigned Value = 0, NumValues = ValueVTs.size();
7074 Value != NumValues; ++Value) {
7075 EVT VT = ValueVTs[Value];
7076 Type *ArgTy = VT.getTypeForEVT(*DAG.getContext());
7077 ISD::ArgFlagsTy Flags;
7078 unsigned OriginalAlignment = DL->getABITypeAlignment(ArgTy);
7080 if (F.getAttributes().hasAttribute(Idx, Attribute::ZExt))
7082 if (F.getAttributes().hasAttribute(Idx, Attribute::SExt))
7084 if (F.getAttributes().hasAttribute(Idx, Attribute::InReg))
7086 if (F.getAttributes().hasAttribute(Idx, Attribute::StructRet))
7088 if (F.getAttributes().hasAttribute(Idx, Attribute::ByVal))
7090 if (F.getAttributes().hasAttribute(Idx, Attribute::InAlloca)) {
7091 Flags.setInAlloca();
7092 // Set the byval flag for CCAssignFn callbacks that don't know about
7093 // inalloca. This way we can know how many bytes we should've allocated
7094 // and how many bytes a callee cleanup function will pop. If we port
7095 // inalloca to more targets, we'll have to add custom inalloca handling
7096 // in the various CC lowering callbacks.
7099 if (Flags.isByVal() || Flags.isInAlloca()) {
7100 PointerType *Ty = cast<PointerType>(I->getType());
7101 Type *ElementTy = Ty->getElementType();
7102 Flags.setByValSize(DL->getTypeAllocSize(ElementTy));
7103 // For ByVal, alignment should be passed from FE. BE will guess if
7104 // this info is not there but there are cases it cannot get right.
7105 unsigned FrameAlign;
7106 if (F.getParamAlignment(Idx))
7107 FrameAlign = F.getParamAlignment(Idx);
7109 FrameAlign = TLI->getByValTypeAlignment(ElementTy);
7110 Flags.setByValAlign(FrameAlign);
7112 if (F.getAttributes().hasAttribute(Idx, Attribute::Nest))
7115 Flags.setInConsecutiveRegs();
7116 Flags.setOrigAlign(OriginalAlignment);
7118 MVT RegisterVT = TLI->getRegisterType(*CurDAG->getContext(), VT);
7119 unsigned NumRegs = TLI->getNumRegisters(*CurDAG->getContext(), VT);
7120 for (unsigned i = 0; i != NumRegs; ++i) {
7121 ISD::InputArg MyFlags(Flags, RegisterVT, VT, isArgValueUsed,
7122 Idx-1, PartBase+i*RegisterVT.getStoreSize());
7123 if (NumRegs > 1 && i == 0)
7124 MyFlags.Flags.setSplit();
7125 // if it isn't first piece, alignment must be 1
7127 MyFlags.Flags.setOrigAlign(1);
7128 Ins.push_back(MyFlags);
7130 if (NeedsRegBlock && Value == NumValues - 1)
7131 Ins[Ins.size() - 1].Flags.setInConsecutiveRegsLast();
7132 PartBase += VT.getStoreSize();
7136 // Call the target to set up the argument values.
7137 SmallVector<SDValue, 8> InVals;
7138 SDValue NewRoot = TLI->LowerFormalArguments(
7139 DAG.getRoot(), F.getCallingConv(), F.isVarArg(), Ins, dl, DAG, InVals);
7141 // Verify that the target's LowerFormalArguments behaved as expected.
7142 assert(NewRoot.getNode() && NewRoot.getValueType() == MVT::Other &&
7143 "LowerFormalArguments didn't return a valid chain!");
7144 assert(InVals.size() == Ins.size() &&
7145 "LowerFormalArguments didn't emit the correct number of values!");
7147 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
7148 assert(InVals[i].getNode() &&
7149 "LowerFormalArguments emitted a null value!");
7150 assert(EVT(Ins[i].VT) == InVals[i].getValueType() &&
7151 "LowerFormalArguments emitted a value with the wrong type!");
7155 // Update the DAG with the new chain value resulting from argument lowering.
7156 DAG.setRoot(NewRoot);
7158 // Set up the argument values.
7161 if (!FuncInfo->CanLowerReturn) {
7162 // Create a virtual register for the sret pointer, and put in a copy
7163 // from the sret argument into it.
7164 SmallVector<EVT, 1> ValueVTs;
7165 ComputeValueVTs(*TLI, PointerType::getUnqual(F.getReturnType()), ValueVTs);
7166 MVT VT = ValueVTs[0].getSimpleVT();
7167 MVT RegVT = TLI->getRegisterType(*CurDAG->getContext(), VT);
7168 ISD::NodeType AssertOp = ISD::DELETED_NODE;
7169 SDValue ArgValue = getCopyFromParts(DAG, dl, &InVals[0], 1,
7170 RegVT, VT, nullptr, AssertOp);
7172 MachineFunction& MF = SDB->DAG.getMachineFunction();
7173 MachineRegisterInfo& RegInfo = MF.getRegInfo();
7174 unsigned SRetReg = RegInfo.createVirtualRegister(TLI->getRegClassFor(RegVT));
7175 FuncInfo->DemoteRegister = SRetReg;
7177 SDB->DAG.getCopyToReg(NewRoot, SDB->getCurSDLoc(), SRetReg, ArgValue);
7178 DAG.setRoot(NewRoot);
7180 // i indexes lowered arguments. Bump it past the hidden sret argument.
7181 // Idx indexes LLVM arguments. Don't touch it.
7185 for (Function::const_arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E;
7187 SmallVector<SDValue, 4> ArgValues;
7188 SmallVector<EVT, 4> ValueVTs;
7189 ComputeValueVTs(*TLI, I->getType(), ValueVTs);
7190 unsigned NumValues = ValueVTs.size();
7192 // If this argument is unused then remember its value. It is used to generate
7193 // debugging information.
7194 if (I->use_empty() && NumValues) {
7195 SDB->setUnusedArgValue(I, InVals[i]);
7197 // Also remember any frame index for use in FastISel.
7198 if (FrameIndexSDNode *FI =
7199 dyn_cast<FrameIndexSDNode>(InVals[i].getNode()))
7200 FuncInfo->setArgumentFrameIndex(I, FI->getIndex());
7203 for (unsigned Val = 0; Val != NumValues; ++Val) {
7204 EVT VT = ValueVTs[Val];
7205 MVT PartVT = TLI->getRegisterType(*CurDAG->getContext(), VT);
7206 unsigned NumParts = TLI->getNumRegisters(*CurDAG->getContext(), VT);
7208 if (!I->use_empty()) {
7209 ISD::NodeType AssertOp = ISD::DELETED_NODE;
7210 if (F.getAttributes().hasAttribute(Idx, Attribute::SExt))
7211 AssertOp = ISD::AssertSext;
7212 else if (F.getAttributes().hasAttribute(Idx, Attribute::ZExt))
7213 AssertOp = ISD::AssertZext;
7215 ArgValues.push_back(getCopyFromParts(DAG, dl, &InVals[i],
7216 NumParts, PartVT, VT,
7217 nullptr, AssertOp));
7223 // We don't need to do anything else for unused arguments.
7224 if (ArgValues.empty())
7227 // Note down frame index.
7228 if (FrameIndexSDNode *FI =
7229 dyn_cast<FrameIndexSDNode>(ArgValues[0].getNode()))
7230 FuncInfo->setArgumentFrameIndex(I, FI->getIndex());
7232 SDValue Res = DAG.getMergeValues(makeArrayRef(ArgValues.data(), NumValues),
7233 SDB->getCurSDLoc());
7235 SDB->setValue(I, Res);
7236 if (!TM.Options.EnableFastISel && Res.getOpcode() == ISD::BUILD_PAIR) {
7237 if (LoadSDNode *LNode =
7238 dyn_cast<LoadSDNode>(Res.getOperand(0).getNode()))
7239 if (FrameIndexSDNode *FI =
7240 dyn_cast<FrameIndexSDNode>(LNode->getBasePtr().getNode()))
7241 FuncInfo->setArgumentFrameIndex(I, FI->getIndex());
7244 // If this argument is live outside of the entry block, insert a copy from
7245 // wherever we got it to the vreg that other BB's will reference it as.
7246 if (!TM.Options.EnableFastISel && Res.getOpcode() == ISD::CopyFromReg) {
7247 // If we can, though, try to skip creating an unnecessary vreg.
7248 // FIXME: This isn't very clean... it would be nice to make this more
7249 // general. It's also subtly incompatible with the hacks FastISel
7251 unsigned Reg = cast<RegisterSDNode>(Res.getOperand(1))->getReg();
7252 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
7253 FuncInfo->ValueMap[I] = Reg;
7257 if (!isOnlyUsedInEntryBlock(I, TM.Options.EnableFastISel)) {
7258 FuncInfo->InitializeRegForValue(I);
7259 SDB->CopyToExportRegsIfNeeded(I);
7263 assert(i == InVals.size() && "Argument register count mismatch!");
7265 // Finally, if the target has anything special to do, allow it to do so.
7266 EmitFunctionEntryCode();
7269 /// Handle PHI nodes in successor blocks. Emit code into the SelectionDAG to
7270 /// ensure constants are generated when needed. Remember the virtual registers
7271 /// that need to be added to the Machine PHI nodes as input. We cannot just
7272 /// directly add them, because expansion might result in multiple MBB's for one
7273 /// BB. As such, the start of the BB might correspond to a different MBB than
7277 SelectionDAGBuilder::HandlePHINodesInSuccessorBlocks(const BasicBlock *LLVMBB) {
7278 const TerminatorInst *TI = LLVMBB->getTerminator();
7280 SmallPtrSet<MachineBasicBlock *, 4> SuccsHandled;
7282 // Check PHI nodes in successors that expect a value to be available from this
7284 for (unsigned succ = 0, e = TI->getNumSuccessors(); succ != e; ++succ) {
7285 const BasicBlock *SuccBB = TI->getSuccessor(succ);
7286 if (!isa<PHINode>(SuccBB->begin())) continue;
7287 MachineBasicBlock *SuccMBB = FuncInfo.MBBMap[SuccBB];
7289 // If this terminator has multiple identical successors (common for
7290 // switches), only handle each succ once.
7291 if (!SuccsHandled.insert(SuccMBB).second)
7294 MachineBasicBlock::iterator MBBI = SuccMBB->begin();
7296 // At this point we know that there is a 1-1 correspondence between LLVM PHI
7297 // nodes and Machine PHI nodes, but the incoming operands have not been
7299 for (BasicBlock::const_iterator I = SuccBB->begin();
7300 const PHINode *PN = dyn_cast<PHINode>(I); ++I) {
7301 // Ignore dead phi's.
7302 if (PN->use_empty()) continue;
7305 if (PN->getType()->isEmptyTy())
7309 const Value *PHIOp = PN->getIncomingValueForBlock(LLVMBB);
7311 if (const Constant *C = dyn_cast<Constant>(PHIOp)) {
7312 unsigned &RegOut = ConstantsOut[C];
7314 RegOut = FuncInfo.CreateRegs(C->getType());
7315 CopyValueToVirtualRegister(C, RegOut);
7319 DenseMap<const Value *, unsigned>::iterator I =
7320 FuncInfo.ValueMap.find(PHIOp);
7321 if (I != FuncInfo.ValueMap.end())
7324 assert(isa<AllocaInst>(PHIOp) &&
7325 FuncInfo.StaticAllocaMap.count(cast<AllocaInst>(PHIOp)) &&
7326 "Didn't codegen value into a register!??");
7327 Reg = FuncInfo.CreateRegs(PHIOp->getType());
7328 CopyValueToVirtualRegister(PHIOp, Reg);
7332 // Remember that this register needs to added to the machine PHI node as
7333 // the input for this MBB.
7334 SmallVector<EVT, 4> ValueVTs;
7335 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
7336 ComputeValueVTs(TLI, PN->getType(), ValueVTs);
7337 for (unsigned vti = 0, vte = ValueVTs.size(); vti != vte; ++vti) {
7338 EVT VT = ValueVTs[vti];
7339 unsigned NumRegisters = TLI.getNumRegisters(*DAG.getContext(), VT);
7340 for (unsigned i = 0, e = NumRegisters; i != e; ++i)
7341 FuncInfo.PHINodesToUpdate.push_back(std::make_pair(MBBI++, Reg+i));
7342 Reg += NumRegisters;
7347 ConstantsOut.clear();
7350 /// Add a successor MBB to ParentMBB< creating a new MachineBB for BB if SuccMBB
7353 SelectionDAGBuilder::StackProtectorDescriptor::
7354 AddSuccessorMBB(const BasicBlock *BB,
7355 MachineBasicBlock *ParentMBB,
7357 MachineBasicBlock *SuccMBB) {
7358 // If SuccBB has not been created yet, create it.
7360 MachineFunction *MF = ParentMBB->getParent();
7361 MachineFunction::iterator BBI = ParentMBB;
7362 SuccMBB = MF->CreateMachineBasicBlock(BB);
7363 MF->insert(++BBI, SuccMBB);
7365 // Add it as a successor of ParentMBB.
7366 ParentMBB->addSuccessor(
7367 SuccMBB, BranchProbabilityInfo::getBranchWeightStackProtector(IsLikely));
7371 MachineBasicBlock *SelectionDAGBuilder::NextBlock(MachineBasicBlock *MBB) {
7372 MachineFunction::iterator I = MBB;
7373 if (++I == FuncInfo.MF->end())
7378 /// During lowering new call nodes can be created (such as memset, etc.).
7379 /// Those will become new roots of the current DAG, but complications arise
7380 /// when they are tail calls. In such cases, the call lowering will update
7381 /// the root, but the builder still needs to know that a tail call has been
7382 /// lowered in order to avoid generating an additional return.
7383 void SelectionDAGBuilder::updateDAGForMaybeTailCall(SDValue MaybeTC) {
7384 // If the node is null, we do have a tail call.
7385 if (MaybeTC.getNode() != nullptr)
7386 DAG.setRoot(MaybeTC);
7391 bool SelectionDAGBuilder::isDense(const CaseClusterVector &Clusters,
7392 unsigned *TotalCases, unsigned First,
7394 assert(Last >= First);
7395 assert(TotalCases[Last] >= TotalCases[First]);
7397 APInt LowCase = Clusters[First].Low->getValue();
7398 APInt HighCase = Clusters[Last].High->getValue();
7399 assert(LowCase.getBitWidth() == HighCase.getBitWidth());
7401 // FIXME: A range of consecutive cases has 100% density, but only requires one
7402 // comparison to lower. We should discriminate against such consecutive ranges
7405 uint64_t Diff = (HighCase - LowCase).getLimitedValue((UINT64_MAX - 1) / 100);
7406 uint64_t Range = Diff + 1;
7409 TotalCases[Last] - (First == 0 ? 0 : TotalCases[First - 1]);
7411 assert(NumCases < UINT64_MAX / 100);
7412 assert(Range >= NumCases);
7414 return NumCases * 100 >= Range * MinJumpTableDensity;
7417 static inline bool areJTsAllowed(const TargetLowering &TLI) {
7418 return TLI.isOperationLegalOrCustom(ISD::BR_JT, MVT::Other) ||
7419 TLI.isOperationLegalOrCustom(ISD::BRIND, MVT::Other);
7422 bool SelectionDAGBuilder::buildJumpTable(CaseClusterVector &Clusters,
7423 unsigned First, unsigned Last,
7424 const SwitchInst *SI,
7425 MachineBasicBlock *DefaultMBB,
7426 CaseCluster &JTCluster) {
7427 assert(First <= Last);
7429 uint32_t Weight = 0;
7430 unsigned NumCmps = 0;
7431 std::vector<MachineBasicBlock*> Table;
7432 DenseMap<MachineBasicBlock*, uint32_t> JTWeights;
7433 for (unsigned I = First; I <= Last; ++I) {
7434 assert(Clusters[I].Kind == CC_Range);
7435 Weight += Clusters[I].Weight;
7436 assert(Weight >= Clusters[I].Weight && "Weight overflow!");
7437 APInt Low = Clusters[I].Low->getValue();
7438 APInt High = Clusters[I].High->getValue();
7439 NumCmps += (Low == High) ? 1 : 2;
7441 // Fill the gap between this and the previous cluster.
7442 APInt PreviousHigh = Clusters[I - 1].High->getValue();
7443 assert(PreviousHigh.slt(Low));
7444 uint64_t Gap = (Low - PreviousHigh).getLimitedValue() - 1;
7445 for (uint64_t J = 0; J < Gap; J++)
7446 Table.push_back(DefaultMBB);
7448 uint64_t ClusterSize = (High - Low).getLimitedValue() + 1;
7449 for (uint64_t J = 0; J < ClusterSize; ++J)
7450 Table.push_back(Clusters[I].MBB);
7451 JTWeights[Clusters[I].MBB] += Clusters[I].Weight;
7454 unsigned NumDests = JTWeights.size();
7455 if (isSuitableForBitTests(NumDests, NumCmps,
7456 Clusters[First].Low->getValue(),
7457 Clusters[Last].High->getValue())) {
7458 // Clusters[First..Last] should be lowered as bit tests instead.
7462 // Create the MBB that will load from and jump through the table.
7463 // Note: We create it here, but it's not inserted into the function yet.
7464 MachineFunction *CurMF = FuncInfo.MF;
7465 MachineBasicBlock *JumpTableMBB =
7466 CurMF->CreateMachineBasicBlock(SI->getParent());
7468 // Add successors. Note: use table order for determinism.
7469 SmallPtrSet<MachineBasicBlock *, 8> Done;
7470 for (MachineBasicBlock *Succ : Table) {
7471 if (Done.count(Succ))
7473 addSuccessorWithWeight(JumpTableMBB, Succ, JTWeights[Succ]);
7477 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
7478 unsigned JTI = CurMF->getOrCreateJumpTableInfo(TLI.getJumpTableEncoding())
7479 ->createJumpTableIndex(Table);
7481 // Set up the jump table info.
7482 JumpTable JT(-1U, JTI, JumpTableMBB, nullptr);
7483 JumpTableHeader JTH(Clusters[First].Low->getValue(),
7484 Clusters[Last].High->getValue(), SI->getCondition(),
7486 JTCases.emplace_back(std::move(JTH), std::move(JT));
7488 JTCluster = CaseCluster::jumpTable(Clusters[First].Low, Clusters[Last].High,
7489 JTCases.size() - 1, Weight);
7493 void SelectionDAGBuilder::findJumpTables(CaseClusterVector &Clusters,
7494 const SwitchInst *SI,
7495 MachineBasicBlock *DefaultMBB) {
7497 // Clusters must be non-empty, sorted, and only contain Range clusters.
7498 assert(!Clusters.empty());
7499 for (CaseCluster &C : Clusters)
7500 assert(C.Kind == CC_Range);
7501 for (unsigned i = 1, e = Clusters.size(); i < e; ++i)
7502 assert(Clusters[i - 1].High->getValue().slt(Clusters[i].Low->getValue()));
7505 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
7506 if (!areJTsAllowed(TLI))
7509 const int64_t N = Clusters.size();
7510 const unsigned MinJumpTableSize = TLI.getMinimumJumpTableEntries();
7512 // Split Clusters into minimum number of dense partitions. The algorithm uses
7513 // the same idea as Kannan & Proebsting "Correction to 'Producing Good Code
7514 // for the Case Statement'" (1994), but builds the MinPartitions array in
7515 // reverse order to make it easier to reconstruct the partitions in ascending
7516 // order. In the choice between two optimal partitionings, it picks the one
7517 // which yields more jump tables.
7519 // MinPartitions[i] is the minimum nbr of partitions of Clusters[i..N-1].
7520 SmallVector<unsigned, 8> MinPartitions(N);
7521 // LastElement[i] is the last element of the partition starting at i.
7522 SmallVector<unsigned, 8> LastElement(N);
7523 // NumTables[i]: nbr of >= MinJumpTableSize partitions from Clusters[i..N-1].
7524 SmallVector<unsigned, 8> NumTables(N);
7525 // TotalCases[i]: Total nbr of cases in Clusters[0..i].
7526 SmallVector<unsigned, 8> TotalCases(N);
7528 for (unsigned i = 0; i < N; ++i) {
7529 APInt Hi = Clusters[i].High->getValue();
7530 APInt Lo = Clusters[i].Low->getValue();
7531 TotalCases[i] = (Hi - Lo).getLimitedValue() + 1;
7533 TotalCases[i] += TotalCases[i - 1];
7536 // Base case: There is only one way to partition Clusters[N-1].
7537 MinPartitions[N - 1] = 1;
7538 LastElement[N - 1] = N - 1;
7539 assert(MinJumpTableSize > 1);
7540 NumTables[N - 1] = 0;
7542 // Note: loop indexes are signed to avoid underflow.
7543 for (int64_t i = N - 2; i >= 0; i--) {
7544 // Find optimal partitioning of Clusters[i..N-1].
7545 // Baseline: Put Clusters[i] into a partition on its own.
7546 MinPartitions[i] = MinPartitions[i + 1] + 1;
7548 NumTables[i] = NumTables[i + 1];
7550 // Search for a solution that results in fewer partitions.
7551 for (int64_t j = N - 1; j > i; j--) {
7552 // Try building a partition from Clusters[i..j].
7553 if (isDense(Clusters, &TotalCases[0], i, j)) {
7554 unsigned NumPartitions = 1 + (j == N - 1 ? 0 : MinPartitions[j + 1]);
7555 bool IsTable = j - i + 1 >= MinJumpTableSize;
7556 unsigned Tables = IsTable + (j == N - 1 ? 0 : NumTables[j + 1]);
7558 // If this j leads to fewer partitions, or same number of partitions
7559 // with more lookup tables, it is a better partitioning.
7560 if (NumPartitions < MinPartitions[i] ||
7561 (NumPartitions == MinPartitions[i] && Tables > NumTables[i])) {
7562 MinPartitions[i] = NumPartitions;
7564 NumTables[i] = Tables;
7570 // Iterate over the partitions, replacing some with jump tables in-place.
7571 unsigned DstIndex = 0;
7572 for (unsigned First = 0, Last; First < N; First = Last + 1) {
7573 Last = LastElement[First];
7574 assert(Last >= First);
7575 assert(DstIndex <= First);
7576 unsigned NumClusters = Last - First + 1;
7578 CaseCluster JTCluster;
7579 if (NumClusters >= MinJumpTableSize &&
7580 buildJumpTable(Clusters, First, Last, SI, DefaultMBB, JTCluster)) {
7581 Clusters[DstIndex++] = JTCluster;
7583 for (unsigned I = First; I <= Last; ++I)
7584 std::memmove(&Clusters[DstIndex++], &Clusters[I], sizeof(Clusters[I]));
7587 Clusters.resize(DstIndex);
7590 bool SelectionDAGBuilder::rangeFitsInWord(const APInt &Low, const APInt &High) {
7591 // FIXME: Using the pointer type doesn't seem ideal.
7592 uint64_t BW = DAG.getTargetLoweringInfo().getPointerTy().getSizeInBits();
7593 uint64_t Range = (High - Low).getLimitedValue(UINT64_MAX - 1) + 1;
7597 bool SelectionDAGBuilder::isSuitableForBitTests(unsigned NumDests,
7600 const APInt &High) {
7601 // FIXME: I don't think NumCmps is the correct metric: a single case and a
7602 // range of cases both require only one branch to lower. Just looking at the
7603 // number of clusters and destinations should be enough to decide whether to
7606 // To lower a range with bit tests, the range must fit the bitwidth of a
7608 if (!rangeFitsInWord(Low, High))
7611 // Decide whether it's profitable to lower this range with bit tests. Each
7612 // destination requires a bit test and branch, and there is an overall range
7613 // check branch. For a small number of clusters, separate comparisons might be
7614 // cheaper, and for many destinations, splitting the range might be better.
7615 return (NumDests == 1 && NumCmps >= 3) ||
7616 (NumDests == 2 && NumCmps >= 5) ||
7617 (NumDests == 3 && NumCmps >= 6);
7620 bool SelectionDAGBuilder::buildBitTests(CaseClusterVector &Clusters,
7621 unsigned First, unsigned Last,
7622 const SwitchInst *SI,
7623 CaseCluster &BTCluster) {
7624 assert(First <= Last);
7628 BitVector Dests(FuncInfo.MF->getNumBlockIDs());
7629 unsigned NumCmps = 0;
7630 for (int64_t I = First; I <= Last; ++I) {
7631 assert(Clusters[I].Kind == CC_Range);
7632 Dests.set(Clusters[I].MBB->getNumber());
7633 NumCmps += (Clusters[I].Low == Clusters[I].High) ? 1 : 2;
7635 unsigned NumDests = Dests.count();
7637 APInt Low = Clusters[First].Low->getValue();
7638 APInt High = Clusters[Last].High->getValue();
7639 assert(Low.slt(High));
7641 if (!isSuitableForBitTests(NumDests, NumCmps, Low, High))
7647 const int BitWidth =
7648 DAG.getTargetLoweringInfo().getPointerTy().getSizeInBits();
7649 assert(rangeFitsInWord(Low, High) && "Case range must fit in bit mask!");
7651 if (Low.isNonNegative() && High.slt(BitWidth)) {
7652 // Optimize the case where all the case values fit in a
7653 // word without having to subtract minValue. In this case,
7654 // we can optimize away the subtraction.
7655 LowBound = APInt::getNullValue(Low.getBitWidth());
7659 CmpRange = High - Low;
7663 uint32_t TotalWeight = 0;
7664 for (unsigned i = First; i <= Last; ++i) {
7665 // Find the CaseBits for this destination.
7667 for (j = 0; j < CBV.size(); ++j)
7668 if (CBV[j].BB == Clusters[i].MBB)
7670 if (j == CBV.size())
7671 CBV.push_back(CaseBits(0, Clusters[i].MBB, 0, 0));
7672 CaseBits *CB = &CBV[j];
7674 // Update Mask, Bits and ExtraWeight.
7675 uint64_t Lo = (Clusters[i].Low->getValue() - LowBound).getZExtValue();
7676 uint64_t Hi = (Clusters[i].High->getValue() - LowBound).getZExtValue();
7677 assert(Hi >= Lo && Hi < 64 && "Invalid bit case!");
7678 CB->Mask |= (-1ULL >> (63 - (Hi - Lo))) << Lo;
7679 CB->Bits += Hi - Lo + 1;
7680 CB->ExtraWeight += Clusters[i].Weight;
7681 TotalWeight += Clusters[i].Weight;
7682 assert(TotalWeight >= Clusters[i].Weight && "Weight overflow!");
7686 std::sort(CBV.begin(), CBV.end(), [](const CaseBits &a, const CaseBits &b) {
7687 // Sort by weight first, number of bits second.
7688 if (a.ExtraWeight != b.ExtraWeight)
7689 return a.ExtraWeight > b.ExtraWeight;
7690 return a.Bits > b.Bits;
7693 for (auto &CB : CBV) {
7694 MachineBasicBlock *BitTestBB =
7695 FuncInfo.MF->CreateMachineBasicBlock(SI->getParent());
7696 BTI.push_back(BitTestCase(CB.Mask, BitTestBB, CB.BB, CB.ExtraWeight));
7698 BitTestCases.emplace_back(std::move(LowBound), std::move(CmpRange),
7699 SI->getCondition(), -1U, MVT::Other, false, nullptr,
7700 nullptr, std::move(BTI));
7702 BTCluster = CaseCluster::bitTests(Clusters[First].Low, Clusters[Last].High,
7703 BitTestCases.size() - 1, TotalWeight);
7707 void SelectionDAGBuilder::findBitTestClusters(CaseClusterVector &Clusters,
7708 const SwitchInst *SI) {
7709 // Partition Clusters into as few subsets as possible, where each subset has a
7710 // range that fits in a machine word and has <= 3 unique destinations.
7713 // Clusters must be sorted and contain Range or JumpTable clusters.
7714 assert(!Clusters.empty());
7715 assert(Clusters[0].Kind == CC_Range || Clusters[0].Kind == CC_JumpTable);
7716 for (const CaseCluster &C : Clusters)
7717 assert(C.Kind == CC_Range || C.Kind == CC_JumpTable);
7718 for (unsigned i = 1; i < Clusters.size(); ++i)
7719 assert(Clusters[i-1].High->getValue().slt(Clusters[i].Low->getValue()));
7722 // If target does not have legal shift left, do not emit bit tests at all.
7723 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
7724 EVT PTy = TLI.getPointerTy();
7725 if (!TLI.isOperationLegal(ISD::SHL, PTy))
7728 int BitWidth = PTy.getSizeInBits();
7729 const int64_t N = Clusters.size();
7731 // MinPartitions[i] is the minimum nbr of partitions of Clusters[i..N-1].
7732 SmallVector<unsigned, 8> MinPartitions(N);
7733 // LastElement[i] is the last element of the partition starting at i.
7734 SmallVector<unsigned, 8> LastElement(N);
7736 // FIXME: This might not be the best algorithm for finding bit test clusters.
7738 // Base case: There is only one way to partition Clusters[N-1].
7739 MinPartitions[N - 1] = 1;
7740 LastElement[N - 1] = N - 1;
7742 // Note: loop indexes are signed to avoid underflow.
7743 for (int64_t i = N - 2; i >= 0; --i) {
7744 // Find optimal partitioning of Clusters[i..N-1].
7745 // Baseline: Put Clusters[i] into a partition on its own.
7746 MinPartitions[i] = MinPartitions[i + 1] + 1;
7749 // Search for a solution that results in fewer partitions.
7750 // Note: the search is limited by BitWidth, reducing time complexity.
7751 for (int64_t j = std::min(N - 1, i + BitWidth - 1); j > i; --j) {
7752 // Try building a partition from Clusters[i..j].
7755 if (!rangeFitsInWord(Clusters[i].Low->getValue(),
7756 Clusters[j].High->getValue()))
7759 // Check nbr of destinations and cluster types.
7760 // FIXME: This works, but doesn't seem very efficient.
7761 bool RangesOnly = true;
7762 BitVector Dests(FuncInfo.MF->getNumBlockIDs());
7763 for (int64_t k = i; k <= j; k++) {
7764 if (Clusters[k].Kind != CC_Range) {
7768 Dests.set(Clusters[k].MBB->getNumber());
7770 if (!RangesOnly || Dests.count() > 3)
7773 // Check if it's a better partition.
7774 unsigned NumPartitions = 1 + (j == N - 1 ? 0 : MinPartitions[j + 1]);
7775 if (NumPartitions < MinPartitions[i]) {
7776 // Found a better partition.
7777 MinPartitions[i] = NumPartitions;
7783 // Iterate over the partitions, replacing with bit-test clusters in-place.
7784 unsigned DstIndex = 0;
7785 for (unsigned First = 0, Last; First < N; First = Last + 1) {
7786 Last = LastElement[First];
7787 assert(First <= Last);
7788 assert(DstIndex <= First);
7790 CaseCluster BitTestCluster;
7791 if (buildBitTests(Clusters, First, Last, SI, BitTestCluster)) {
7792 Clusters[DstIndex++] = BitTestCluster;
7794 size_t NumClusters = Last - First + 1;
7795 std::memmove(&Clusters[DstIndex], &Clusters[First],
7796 sizeof(Clusters[0]) * NumClusters);
7797 DstIndex += NumClusters;
7800 Clusters.resize(DstIndex);
7803 void SelectionDAGBuilder::lowerWorkItem(SwitchWorkListItem W, Value *Cond,
7804 MachineBasicBlock *SwitchMBB,
7805 MachineBasicBlock *DefaultMBB) {
7806 MachineFunction *CurMF = FuncInfo.MF;
7807 MachineBasicBlock *NextMBB = nullptr;
7808 MachineFunction::iterator BBI = W.MBB;
7809 if (++BBI != FuncInfo.MF->end())
7812 unsigned Size = W.LastCluster - W.FirstCluster + 1;
7814 BranchProbabilityInfo *BPI = FuncInfo.BPI;
7816 if (Size == 2 && W.MBB == SwitchMBB) {
7817 // If any two of the cases has the same destination, and if one value
7818 // is the same as the other, but has one bit unset that the other has set,
7819 // use bit manipulation to do two compares at once. For example:
7820 // "if (X == 6 || X == 4)" -> "if ((X|2) == 6)"
7821 // TODO: This could be extended to merge any 2 cases in switches with 3
7823 // TODO: Handle cases where W.CaseBB != SwitchBB.
7824 CaseCluster &Small = *W.FirstCluster;
7825 CaseCluster &Big = *W.LastCluster;
7827 if (Small.Low == Small.High && Big.Low == Big.High &&
7828 Small.MBB == Big.MBB) {
7829 const APInt &SmallValue = Small.Low->getValue();
7830 const APInt &BigValue = Big.Low->getValue();
7832 // Check that there is only one bit different.
7833 APInt CommonBit = BigValue ^ SmallValue;
7834 if (CommonBit.isPowerOf2()) {
7835 SDValue CondLHS = getValue(Cond);
7836 EVT VT = CondLHS.getValueType();
7837 SDLoc DL = getCurSDLoc();
7839 SDValue Or = DAG.getNode(ISD::OR, DL, VT, CondLHS,
7840 DAG.getConstant(CommonBit, DL, VT));
7841 SDValue Cond = DAG.getSetCC(
7842 DL, MVT::i1, Or, DAG.getConstant(BigValue | SmallValue, DL, VT),
7845 // Update successor info.
7846 // Both Small and Big will jump to Small.BB, so we sum up the weights.
7847 addSuccessorWithWeight(SwitchMBB, Small.MBB, Small.Weight + Big.Weight);
7848 addSuccessorWithWeight(
7849 SwitchMBB, DefaultMBB,
7850 // The default destination is the first successor in IR.
7851 BPI ? BPI->getEdgeWeight(SwitchMBB->getBasicBlock(), (unsigned)0)
7854 // Insert the true branch.
7856 DAG.getNode(ISD::BRCOND, DL, MVT::Other, getControlRoot(), Cond,
7857 DAG.getBasicBlock(Small.MBB));
7858 // Insert the false branch.
7859 BrCond = DAG.getNode(ISD::BR, DL, MVT::Other, BrCond,
7860 DAG.getBasicBlock(DefaultMBB));
7862 DAG.setRoot(BrCond);
7868 if (TM.getOptLevel() != CodeGenOpt::None) {
7869 // Order cases by weight so the most likely case will be checked first.
7870 std::sort(W.FirstCluster, W.LastCluster + 1,
7871 [](const CaseCluster &a, const CaseCluster &b) {
7872 return a.Weight > b.Weight;
7875 // Rearrange the case blocks so that the last one falls through if possible
7876 // without without changing the order of weights.
7877 for (CaseClusterIt I = W.LastCluster; I > W.FirstCluster; ) {
7879 if (I->Weight > W.LastCluster->Weight)
7881 if (I->Kind == CC_Range && I->MBB == NextMBB) {
7882 std::swap(*I, *W.LastCluster);
7888 // Compute total weight.
7889 uint32_t UnhandledWeights = 0;
7890 for (CaseClusterIt I = W.FirstCluster; I <= W.LastCluster; ++I) {
7891 UnhandledWeights += I->Weight;
7892 assert(UnhandledWeights >= I->Weight && "Weight overflow!");
7895 MachineBasicBlock *CurMBB = W.MBB;
7896 for (CaseClusterIt I = W.FirstCluster, E = W.LastCluster; I <= E; ++I) {
7897 MachineBasicBlock *Fallthrough;
7898 if (I == W.LastCluster) {
7899 // For the last cluster, fall through to the default destination.
7900 Fallthrough = DefaultMBB;
7902 Fallthrough = CurMF->CreateMachineBasicBlock(CurMBB->getBasicBlock());
7903 CurMF->insert(BBI, Fallthrough);
7904 // Put Cond in a virtual register to make it available from the new blocks.
7905 ExportFromCurrentBlock(Cond);
7909 case CC_JumpTable: {
7910 // FIXME: Optimize away range check based on pivot comparisons.
7911 JumpTableHeader *JTH = &JTCases[I->JTCasesIndex].first;
7912 JumpTable *JT = &JTCases[I->JTCasesIndex].second;
7914 // The jump block hasn't been inserted yet; insert it here.
7915 MachineBasicBlock *JumpMBB = JT->MBB;
7916 CurMF->insert(BBI, JumpMBB);
7917 addSuccessorWithWeight(CurMBB, Fallthrough);
7918 addSuccessorWithWeight(CurMBB, JumpMBB);
7920 // The jump table header will be inserted in our current block, do the
7921 // range check, and fall through to our fallthrough block.
7922 JTH->HeaderBB = CurMBB;
7923 JT->Default = Fallthrough; // FIXME: Move Default to JumpTableHeader.
7925 // If we're in the right place, emit the jump table header right now.
7926 if (CurMBB == SwitchMBB) {
7927 visitJumpTableHeader(*JT, *JTH, SwitchMBB);
7928 JTH->Emitted = true;
7933 // FIXME: Optimize away range check based on pivot comparisons.
7934 BitTestBlock *BTB = &BitTestCases[I->BTCasesIndex];
7936 // The bit test blocks haven't been inserted yet; insert them here.
7937 for (BitTestCase &BTC : BTB->Cases)
7938 CurMF->insert(BBI, BTC.ThisBB);
7940 // Fill in fields of the BitTestBlock.
7941 BTB->Parent = CurMBB;
7942 BTB->Default = Fallthrough;
7944 // If we're in the right place, emit the bit test header header right now.
7945 if (CurMBB ==SwitchMBB) {
7946 visitBitTestHeader(*BTB, SwitchMBB);
7947 BTB->Emitted = true;
7952 const Value *RHS, *LHS, *MHS;
7954 if (I->Low == I->High) {
7955 // Check Cond == I->Low.
7961 // Check I->Low <= Cond <= I->High.
7968 // The false weight is the sum of all unhandled cases.
7969 UnhandledWeights -= I->Weight;
7970 CaseBlock CB(CC, LHS, RHS, MHS, I->MBB, Fallthrough, CurMBB, I->Weight,
7973 if (CurMBB == SwitchMBB)
7974 visitSwitchCase(CB, SwitchMBB);
7976 SwitchCases.push_back(CB);
7981 CurMBB = Fallthrough;
7985 void SelectionDAGBuilder::splitWorkItem(SwitchWorkList &WorkList,
7986 const SwitchWorkListItem &W,
7988 MachineBasicBlock *SwitchMBB) {
7989 assert(W.FirstCluster->Low->getValue().slt(W.LastCluster->Low->getValue()) &&
7990 "Clusters not sorted?");
7992 assert(W.LastCluster - W.FirstCluster + 1 >= 2 && "Too small to split!");
7994 // Balance the tree based on branch weights to create a near-optimal (in terms
7995 // of search time given key frequency) binary search tree. See e.g. Kurt
7996 // Mehlhorn "Nearly Optimal Binary Search Trees" (1975).
7997 CaseClusterIt LastLeft = W.FirstCluster;
7998 CaseClusterIt FirstRight = W.LastCluster;
7999 uint32_t LeftWeight = LastLeft->Weight;
8000 uint32_t RightWeight = FirstRight->Weight;
8002 // Move LastLeft and FirstRight towards each other from opposite directions to
8003 // find a partitioning of the clusters which balances the weight on both
8004 // sides. If LeftWeight and RightWeight are equal, alternate which side is
8005 // taken to ensure 0-weight nodes are distributed evenly.
8007 while (LastLeft + 1 < FirstRight) {
8008 if (LeftWeight < RightWeight || (LeftWeight == RightWeight && (I & 1)))
8009 LeftWeight += (++LastLeft)->Weight;
8011 RightWeight += (--FirstRight)->Weight;
8014 assert(LastLeft + 1 == FirstRight);
8015 assert(LastLeft >= W.FirstCluster);
8016 assert(FirstRight <= W.LastCluster);
8018 // Use the first element on the right as pivot since we will make less-than
8019 // comparisons against it.
8020 CaseClusterIt PivotCluster = FirstRight;
8021 assert(PivotCluster > W.FirstCluster);
8022 assert(PivotCluster <= W.LastCluster);
8024 CaseClusterIt FirstLeft = W.FirstCluster;
8025 CaseClusterIt LastRight = W.LastCluster;
8027 const ConstantInt *Pivot = PivotCluster->Low;
8029 // New blocks will be inserted immediately after the current one.
8030 MachineFunction::iterator BBI = W.MBB;
8033 // We will branch to the LHS if Value < Pivot. If LHS is a single cluster,
8034 // we can branch to its destination directly if it's squeezed exactly in
8035 // between the known lower bound and Pivot - 1.
8036 MachineBasicBlock *LeftMBB;
8037 if (FirstLeft == LastLeft && FirstLeft->Kind == CC_Range &&
8038 FirstLeft->Low == W.GE &&
8039 (FirstLeft->High->getValue() + 1LL) == Pivot->getValue()) {
8040 LeftMBB = FirstLeft->MBB;
8042 LeftMBB = FuncInfo.MF->CreateMachineBasicBlock(W.MBB->getBasicBlock());
8043 FuncInfo.MF->insert(BBI, LeftMBB);
8044 WorkList.push_back({LeftMBB, FirstLeft, LastLeft, W.GE, Pivot});
8045 // Put Cond in a virtual register to make it available from the new blocks.
8046 ExportFromCurrentBlock(Cond);
8049 // Similarly, we will branch to the RHS if Value >= Pivot. If RHS is a
8050 // single cluster, RHS.Low == Pivot, and we can branch to its destination
8051 // directly if RHS.High equals the current upper bound.
8052 MachineBasicBlock *RightMBB;
8053 if (FirstRight == LastRight && FirstRight->Kind == CC_Range &&
8054 W.LT && (FirstRight->High->getValue() + 1ULL) == W.LT->getValue()) {
8055 RightMBB = FirstRight->MBB;
8057 RightMBB = FuncInfo.MF->CreateMachineBasicBlock(W.MBB->getBasicBlock());
8058 FuncInfo.MF->insert(BBI, RightMBB);
8059 WorkList.push_back({RightMBB, FirstRight, LastRight, Pivot, W.LT});
8060 // Put Cond in a virtual register to make it available from the new blocks.
8061 ExportFromCurrentBlock(Cond);
8064 // Create the CaseBlock record that will be used to lower the branch.
8065 CaseBlock CB(ISD::SETLT, Cond, Pivot, nullptr, LeftMBB, RightMBB, W.MBB,
8066 LeftWeight, RightWeight);
8068 if (W.MBB == SwitchMBB)
8069 visitSwitchCase(CB, SwitchMBB);
8071 SwitchCases.push_back(CB);
8074 void SelectionDAGBuilder::visitSwitch(const SwitchInst &SI) {
8075 // Extract cases from the switch.
8076 BranchProbabilityInfo *BPI = FuncInfo.BPI;
8077 CaseClusterVector Clusters;
8078 Clusters.reserve(SI.getNumCases());
8079 for (auto I : SI.cases()) {
8080 MachineBasicBlock *Succ = FuncInfo.MBBMap[I.getCaseSuccessor()];
8081 const ConstantInt *CaseVal = I.getCaseValue();
8083 BPI ? BPI->getEdgeWeight(SI.getParent(), I.getSuccessorIndex()) : 0;
8084 Clusters.push_back(CaseCluster::range(CaseVal, CaseVal, Succ, Weight));
8087 MachineBasicBlock *DefaultMBB = FuncInfo.MBBMap[SI.getDefaultDest()];
8089 // Cluster adjacent cases with the same destination. We do this at all
8090 // optimization levels because it's cheap to do and will make codegen faster
8091 // if there are many clusters.
8092 sortAndRangeify(Clusters);
8094 if (TM.getOptLevel() != CodeGenOpt::None) {
8095 // Replace an unreachable default with the most popular destination.
8096 // FIXME: Exploit unreachable default more aggressively.
8097 bool UnreachableDefault =
8098 isa<UnreachableInst>(SI.getDefaultDest()->getFirstNonPHIOrDbg());
8099 if (UnreachableDefault && !Clusters.empty()) {
8100 DenseMap<const BasicBlock *, unsigned> Popularity;
8101 unsigned MaxPop = 0;
8102 const BasicBlock *MaxBB = nullptr;
8103 for (auto I : SI.cases()) {
8104 const BasicBlock *BB = I.getCaseSuccessor();
8105 if (++Popularity[BB] > MaxPop) {
8106 MaxPop = Popularity[BB];
8111 assert(MaxPop > 0 && MaxBB);
8112 DefaultMBB = FuncInfo.MBBMap[MaxBB];
8114 // Remove cases that were pointing to the destination that is now the
8116 CaseClusterVector New;
8117 New.reserve(Clusters.size());
8118 for (CaseCluster &CC : Clusters) {
8119 if (CC.MBB != DefaultMBB)
8122 Clusters = std::move(New);
8126 // If there is only the default destination, jump there directly.
8127 MachineBasicBlock *SwitchMBB = FuncInfo.MBB;
8128 if (Clusters.empty()) {
8129 SwitchMBB->addSuccessor(DefaultMBB);
8130 if (DefaultMBB != NextBlock(SwitchMBB)) {
8131 DAG.setRoot(DAG.getNode(ISD::BR, getCurSDLoc(), MVT::Other,
8132 getControlRoot(), DAG.getBasicBlock(DefaultMBB)));
8137 if (TM.getOptLevel() != CodeGenOpt::None) {
8138 findJumpTables(Clusters, &SI, DefaultMBB);
8139 findBitTestClusters(Clusters, &SI);
8144 dbgs() << "Case clusters: ";
8145 for (const CaseCluster &C : Clusters) {
8146 if (C.Kind == CC_JumpTable) dbgs() << "JT:";
8147 if (C.Kind == CC_BitTests) dbgs() << "BT:";
8149 C.Low->getValue().print(dbgs(), true);
8150 if (C.Low != C.High) {
8152 C.High->getValue().print(dbgs(), true);
8159 assert(!Clusters.empty());
8160 SwitchWorkList WorkList;
8161 CaseClusterIt First = Clusters.begin();
8162 CaseClusterIt Last = Clusters.end() - 1;
8163 WorkList.push_back({SwitchMBB, First, Last, nullptr, nullptr});
8165 while (!WorkList.empty()) {
8166 SwitchWorkListItem W = WorkList.back();
8167 WorkList.pop_back();
8168 unsigned NumClusters = W.LastCluster - W.FirstCluster + 1;
8170 if (NumClusters > 3 && TM.getOptLevel() != CodeGenOpt::None) {
8171 // For optimized builds, lower large range as a balanced binary tree.
8172 splitWorkItem(WorkList, W, SI.getCondition(), SwitchMBB);
8176 lowerWorkItem(W, SI.getCondition(), SwitchMBB, DefaultMBB);