1 //===-- SelectionDAGBuilder.cpp - Selection-DAG building ------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements routines for translating from LLVM IR into SelectionDAG IR.
12 //===----------------------------------------------------------------------===//
14 #include "SelectionDAGBuilder.h"
15 #include "SDNodeDbgValue.h"
16 #include "llvm/ADT/BitVector.h"
17 #include "llvm/ADT/Optional.h"
18 #include "llvm/ADT/SmallSet.h"
19 #include "llvm/ADT/Statistic.h"
20 #include "llvm/Analysis/AliasAnalysis.h"
21 #include "llvm/Analysis/BranchProbabilityInfo.h"
22 #include "llvm/Analysis/ConstantFolding.h"
23 #include "llvm/Analysis/TargetLibraryInfo.h"
24 #include "llvm/Analysis/ValueTracking.h"
25 #include "llvm/CodeGen/FastISel.h"
26 #include "llvm/CodeGen/FunctionLoweringInfo.h"
27 #include "llvm/CodeGen/GCMetadata.h"
28 #include "llvm/CodeGen/GCStrategy.h"
29 #include "llvm/CodeGen/MachineFrameInfo.h"
30 #include "llvm/CodeGen/MachineFunction.h"
31 #include "llvm/CodeGen/MachineInstrBuilder.h"
32 #include "llvm/CodeGen/MachineJumpTableInfo.h"
33 #include "llvm/CodeGen/MachineModuleInfo.h"
34 #include "llvm/CodeGen/MachineRegisterInfo.h"
35 #include "llvm/CodeGen/SelectionDAG.h"
36 #include "llvm/CodeGen/StackMaps.h"
37 #include "llvm/CodeGen/WinEHFuncInfo.h"
38 #include "llvm/IR/CallingConv.h"
39 #include "llvm/IR/Constants.h"
40 #include "llvm/IR/DataLayout.h"
41 #include "llvm/IR/DebugInfo.h"
42 #include "llvm/IR/DerivedTypes.h"
43 #include "llvm/IR/Function.h"
44 #include "llvm/IR/GlobalVariable.h"
45 #include "llvm/IR/InlineAsm.h"
46 #include "llvm/IR/Instructions.h"
47 #include "llvm/IR/IntrinsicInst.h"
48 #include "llvm/IR/Intrinsics.h"
49 #include "llvm/IR/LLVMContext.h"
50 #include "llvm/IR/Module.h"
51 #include "llvm/IR/Statepoint.h"
52 #include "llvm/MC/MCSymbol.h"
53 #include "llvm/Support/CommandLine.h"
54 #include "llvm/Support/Debug.h"
55 #include "llvm/Support/ErrorHandling.h"
56 #include "llvm/Support/MathExtras.h"
57 #include "llvm/Support/raw_ostream.h"
58 #include "llvm/Target/TargetFrameLowering.h"
59 #include "llvm/Target/TargetInstrInfo.h"
60 #include "llvm/Target/TargetIntrinsicInfo.h"
61 #include "llvm/Target/TargetLowering.h"
62 #include "llvm/Target/TargetOptions.h"
63 #include "llvm/Target/TargetSelectionDAGInfo.h"
64 #include "llvm/Target/TargetSubtargetInfo.h"
68 #define DEBUG_TYPE "isel"
70 /// LimitFloatPrecision - Generate low-precision inline sequences for
71 /// some float libcalls (6, 8 or 12 bits).
72 static unsigned LimitFloatPrecision;
74 static cl::opt<unsigned, true>
75 LimitFPPrecision("limit-float-precision",
76 cl::desc("Generate low-precision inline sequences "
77 "for some float libcalls"),
78 cl::location(LimitFloatPrecision),
82 EnableFMFInDAG("enable-fmf-dag", cl::init(false), cl::Hidden,
83 cl::desc("Enable fast-math-flags for DAG nodes"));
85 // Limit the width of DAG chains. This is important in general to prevent
86 // DAG-based analysis from blowing up. For example, alias analysis and
87 // load clustering may not complete in reasonable time. It is difficult to
88 // recognize and avoid this situation within each individual analysis, and
89 // future analyses are likely to have the same behavior. Limiting DAG width is
90 // the safe approach and will be especially important with global DAGs.
92 // MaxParallelChains default is arbitrarily high to avoid affecting
93 // optimization, but could be lowered to improve compile time. Any ld-ld-st-st
94 // sequence over this should have been converted to llvm.memcpy by the
95 // frontend. It easy to induce this behavior with .ll code such as:
96 // %buffer = alloca [4096 x i8]
97 // %data = load [4096 x i8]* %argPtr
98 // store [4096 x i8] %data, [4096 x i8]* %buffer
99 static const unsigned MaxParallelChains = 64;
101 static SDValue getCopyFromPartsVector(SelectionDAG &DAG, SDLoc DL,
102 const SDValue *Parts, unsigned NumParts,
103 MVT PartVT, EVT ValueVT, const Value *V);
105 /// getCopyFromParts - Create a value that contains the specified legal parts
106 /// combined into the value they represent. If the parts combine to a type
107 /// larger then ValueVT then AssertOp can be used to specify whether the extra
108 /// bits are known to be zero (ISD::AssertZext) or sign extended from ValueVT
109 /// (ISD::AssertSext).
110 static SDValue getCopyFromParts(SelectionDAG &DAG, SDLoc DL,
111 const SDValue *Parts,
112 unsigned NumParts, MVT PartVT, EVT ValueVT,
114 ISD::NodeType AssertOp = ISD::DELETED_NODE) {
115 if (ValueVT.isVector())
116 return getCopyFromPartsVector(DAG, DL, Parts, NumParts,
119 assert(NumParts > 0 && "No parts to assemble!");
120 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
121 SDValue Val = Parts[0];
124 // Assemble the value from multiple parts.
125 if (ValueVT.isInteger()) {
126 unsigned PartBits = PartVT.getSizeInBits();
127 unsigned ValueBits = ValueVT.getSizeInBits();
129 // Assemble the power of 2 part.
130 unsigned RoundParts = NumParts & (NumParts - 1) ?
131 1 << Log2_32(NumParts) : NumParts;
132 unsigned RoundBits = PartBits * RoundParts;
133 EVT RoundVT = RoundBits == ValueBits ?
134 ValueVT : EVT::getIntegerVT(*DAG.getContext(), RoundBits);
137 EVT HalfVT = EVT::getIntegerVT(*DAG.getContext(), RoundBits/2);
139 if (RoundParts > 2) {
140 Lo = getCopyFromParts(DAG, DL, Parts, RoundParts / 2,
142 Hi = getCopyFromParts(DAG, DL, Parts + RoundParts / 2,
143 RoundParts / 2, PartVT, HalfVT, V);
145 Lo = DAG.getNode(ISD::BITCAST, DL, HalfVT, Parts[0]);
146 Hi = DAG.getNode(ISD::BITCAST, DL, HalfVT, Parts[1]);
149 if (DAG.getDataLayout().isBigEndian())
152 Val = DAG.getNode(ISD::BUILD_PAIR, DL, RoundVT, Lo, Hi);
154 if (RoundParts < NumParts) {
155 // Assemble the trailing non-power-of-2 part.
156 unsigned OddParts = NumParts - RoundParts;
157 EVT OddVT = EVT::getIntegerVT(*DAG.getContext(), OddParts * PartBits);
158 Hi = getCopyFromParts(DAG, DL,
159 Parts + RoundParts, OddParts, PartVT, OddVT, V);
161 // Combine the round and odd parts.
163 if (DAG.getDataLayout().isBigEndian())
165 EVT TotalVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
166 Hi = DAG.getNode(ISD::ANY_EXTEND, DL, TotalVT, Hi);
168 DAG.getNode(ISD::SHL, DL, TotalVT, Hi,
169 DAG.getConstant(Lo.getValueType().getSizeInBits(), DL,
170 TLI.getPointerTy(DAG.getDataLayout())));
171 Lo = DAG.getNode(ISD::ZERO_EXTEND, DL, TotalVT, Lo);
172 Val = DAG.getNode(ISD::OR, DL, TotalVT, Lo, Hi);
174 } else if (PartVT.isFloatingPoint()) {
175 // FP split into multiple FP parts (for ppcf128)
176 assert(ValueVT == EVT(MVT::ppcf128) && PartVT == MVT::f64 &&
179 Lo = DAG.getNode(ISD::BITCAST, DL, EVT(MVT::f64), Parts[0]);
180 Hi = DAG.getNode(ISD::BITCAST, DL, EVT(MVT::f64), Parts[1]);
181 if (TLI.hasBigEndianPartOrdering(ValueVT, DAG.getDataLayout()))
183 Val = DAG.getNode(ISD::BUILD_PAIR, DL, ValueVT, Lo, Hi);
185 // FP split into integer parts (soft fp)
186 assert(ValueVT.isFloatingPoint() && PartVT.isInteger() &&
187 !PartVT.isVector() && "Unexpected split");
188 EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), ValueVT.getSizeInBits());
189 Val = getCopyFromParts(DAG, DL, Parts, NumParts, PartVT, IntVT, V);
193 // There is now one part, held in Val. Correct it to match ValueVT.
194 EVT PartEVT = Val.getValueType();
196 if (PartEVT == ValueVT)
199 if (PartEVT.isInteger() && ValueVT.isInteger()) {
200 if (ValueVT.bitsLT(PartEVT)) {
201 // For a truncate, see if we have any information to
202 // indicate whether the truncated bits will always be
203 // zero or sign-extension.
204 if (AssertOp != ISD::DELETED_NODE)
205 Val = DAG.getNode(AssertOp, DL, PartEVT, Val,
206 DAG.getValueType(ValueVT));
207 return DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val);
209 return DAG.getNode(ISD::ANY_EXTEND, DL, ValueVT, Val);
212 if (PartEVT.isFloatingPoint() && ValueVT.isFloatingPoint()) {
213 // FP_ROUND's are always exact here.
214 if (ValueVT.bitsLT(Val.getValueType()))
216 ISD::FP_ROUND, DL, ValueVT, Val,
217 DAG.getTargetConstant(1, DL, TLI.getPointerTy(DAG.getDataLayout())));
219 return DAG.getNode(ISD::FP_EXTEND, DL, ValueVT, Val);
222 if (PartEVT.getSizeInBits() == ValueVT.getSizeInBits())
223 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val);
225 llvm_unreachable("Unknown mismatch!");
228 static void diagnosePossiblyInvalidConstraint(LLVMContext &Ctx, const Value *V,
229 const Twine &ErrMsg) {
230 const Instruction *I = dyn_cast_or_null<Instruction>(V);
232 return Ctx.emitError(ErrMsg);
234 const char *AsmError = ", possible invalid constraint for vector type";
235 if (const CallInst *CI = dyn_cast<CallInst>(I))
236 if (isa<InlineAsm>(CI->getCalledValue()))
237 return Ctx.emitError(I, ErrMsg + AsmError);
239 return Ctx.emitError(I, ErrMsg);
242 /// getCopyFromPartsVector - Create a value that contains the specified legal
243 /// parts combined into the value they represent. If the parts combine to a
244 /// type larger then ValueVT then AssertOp can be used to specify whether the
245 /// extra bits are known to be zero (ISD::AssertZext) or sign extended from
246 /// ValueVT (ISD::AssertSext).
247 static SDValue getCopyFromPartsVector(SelectionDAG &DAG, SDLoc DL,
248 const SDValue *Parts, unsigned NumParts,
249 MVT PartVT, EVT ValueVT, const Value *V) {
250 assert(ValueVT.isVector() && "Not a vector value");
251 assert(NumParts > 0 && "No parts to assemble!");
252 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
253 SDValue Val = Parts[0];
255 // Handle a multi-element vector.
259 unsigned NumIntermediates;
261 TLI.getVectorTypeBreakdown(*DAG.getContext(), ValueVT, IntermediateVT,
262 NumIntermediates, RegisterVT);
263 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!");
264 NumParts = NumRegs; // Silence a compiler warning.
265 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!");
266 assert(RegisterVT.getSizeInBits() ==
267 Parts[0].getSimpleValueType().getSizeInBits() &&
268 "Part type sizes don't match!");
270 // Assemble the parts into intermediate operands.
271 SmallVector<SDValue, 8> Ops(NumIntermediates);
272 if (NumIntermediates == NumParts) {
273 // If the register was not expanded, truncate or copy the value,
275 for (unsigned i = 0; i != NumParts; ++i)
276 Ops[i] = getCopyFromParts(DAG, DL, &Parts[i], 1,
277 PartVT, IntermediateVT, V);
278 } else if (NumParts > 0) {
279 // If the intermediate type was expanded, build the intermediate
280 // operands from the parts.
281 assert(NumParts % NumIntermediates == 0 &&
282 "Must expand into a divisible number of parts!");
283 unsigned Factor = NumParts / NumIntermediates;
284 for (unsigned i = 0; i != NumIntermediates; ++i)
285 Ops[i] = getCopyFromParts(DAG, DL, &Parts[i * Factor], Factor,
286 PartVT, IntermediateVT, V);
289 // Build a vector with BUILD_VECTOR or CONCAT_VECTORS from the
290 // intermediate operands.
291 Val = DAG.getNode(IntermediateVT.isVector() ? ISD::CONCAT_VECTORS
296 // There is now one part, held in Val. Correct it to match ValueVT.
297 EVT PartEVT = Val.getValueType();
299 if (PartEVT == ValueVT)
302 if (PartEVT.isVector()) {
303 // If the element type of the source/dest vectors are the same, but the
304 // parts vector has more elements than the value vector, then we have a
305 // vector widening case (e.g. <2 x float> -> <4 x float>). Extract the
307 if (PartEVT.getVectorElementType() == ValueVT.getVectorElementType()) {
308 assert(PartEVT.getVectorNumElements() > ValueVT.getVectorNumElements() &&
309 "Cannot narrow, it would be a lossy transformation");
311 ISD::EXTRACT_SUBVECTOR, DL, ValueVT, Val,
312 DAG.getConstant(0, DL, TLI.getVectorIdxTy(DAG.getDataLayout())));
315 // Vector/Vector bitcast.
316 if (ValueVT.getSizeInBits() == PartEVT.getSizeInBits())
317 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val);
319 assert(PartEVT.getVectorNumElements() == ValueVT.getVectorNumElements() &&
320 "Cannot handle this kind of promotion");
321 // Promoted vector extract
322 return DAG.getAnyExtOrTrunc(Val, DL, ValueVT);
326 // Trivial bitcast if the types are the same size and the destination
327 // vector type is legal.
328 if (PartEVT.getSizeInBits() == ValueVT.getSizeInBits() &&
329 TLI.isTypeLegal(ValueVT))
330 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val);
332 // Handle cases such as i8 -> <1 x i1>
333 if (ValueVT.getVectorNumElements() != 1) {
334 diagnosePossiblyInvalidConstraint(*DAG.getContext(), V,
335 "non-trivial scalar-to-vector conversion");
336 return DAG.getUNDEF(ValueVT);
339 if (ValueVT.getVectorNumElements() == 1 &&
340 ValueVT.getVectorElementType() != PartEVT)
341 Val = DAG.getAnyExtOrTrunc(Val, DL, ValueVT.getScalarType());
343 return DAG.getNode(ISD::BUILD_VECTOR, DL, ValueVT, Val);
346 static void getCopyToPartsVector(SelectionDAG &DAG, SDLoc dl,
347 SDValue Val, SDValue *Parts, unsigned NumParts,
348 MVT PartVT, const Value *V);
350 /// getCopyToParts - Create a series of nodes that contain the specified value
351 /// split into legal parts. If the parts contain more bits than Val, then, for
352 /// integers, ExtendKind can be used to specify how to generate the extra bits.
353 static void getCopyToParts(SelectionDAG &DAG, SDLoc DL,
354 SDValue Val, SDValue *Parts, unsigned NumParts,
355 MVT PartVT, const Value *V,
356 ISD::NodeType ExtendKind = ISD::ANY_EXTEND) {
357 EVT ValueVT = Val.getValueType();
359 // Handle the vector case separately.
360 if (ValueVT.isVector())
361 return getCopyToPartsVector(DAG, DL, Val, Parts, NumParts, PartVT, V);
363 unsigned PartBits = PartVT.getSizeInBits();
364 unsigned OrigNumParts = NumParts;
365 assert(DAG.getTargetLoweringInfo().isTypeLegal(PartVT) &&
366 "Copying to an illegal type!");
371 assert(!ValueVT.isVector() && "Vector case handled elsewhere");
372 EVT PartEVT = PartVT;
373 if (PartEVT == ValueVT) {
374 assert(NumParts == 1 && "No-op copy with multiple parts!");
379 if (NumParts * PartBits > ValueVT.getSizeInBits()) {
380 // If the parts cover more bits than the value has, promote the value.
381 if (PartVT.isFloatingPoint() && ValueVT.isFloatingPoint()) {
382 assert(NumParts == 1 && "Do not know what to promote to!");
383 Val = DAG.getNode(ISD::FP_EXTEND, DL, PartVT, Val);
385 assert((PartVT.isInteger() || PartVT == MVT::x86mmx) &&
386 ValueVT.isInteger() &&
387 "Unknown mismatch!");
388 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
389 Val = DAG.getNode(ExtendKind, DL, ValueVT, Val);
390 if (PartVT == MVT::x86mmx)
391 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
393 } else if (PartBits == ValueVT.getSizeInBits()) {
394 // Different types of the same size.
395 assert(NumParts == 1 && PartEVT != ValueVT);
396 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
397 } else if (NumParts * PartBits < ValueVT.getSizeInBits()) {
398 // If the parts cover less bits than value has, truncate the value.
399 assert((PartVT.isInteger() || PartVT == MVT::x86mmx) &&
400 ValueVT.isInteger() &&
401 "Unknown mismatch!");
402 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
403 Val = DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val);
404 if (PartVT == MVT::x86mmx)
405 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
408 // The value may have changed - recompute ValueVT.
409 ValueVT = Val.getValueType();
410 assert(NumParts * PartBits == ValueVT.getSizeInBits() &&
411 "Failed to tile the value with PartVT!");
414 if (PartEVT != ValueVT)
415 diagnosePossiblyInvalidConstraint(*DAG.getContext(), V,
416 "scalar-to-vector conversion failed");
422 // Expand the value into multiple parts.
423 if (NumParts & (NumParts - 1)) {
424 // The number of parts is not a power of 2. Split off and copy the tail.
425 assert(PartVT.isInteger() && ValueVT.isInteger() &&
426 "Do not know what to expand to!");
427 unsigned RoundParts = 1 << Log2_32(NumParts);
428 unsigned RoundBits = RoundParts * PartBits;
429 unsigned OddParts = NumParts - RoundParts;
430 SDValue OddVal = DAG.getNode(ISD::SRL, DL, ValueVT, Val,
431 DAG.getIntPtrConstant(RoundBits, DL));
432 getCopyToParts(DAG, DL, OddVal, Parts + RoundParts, OddParts, PartVT, V);
434 if (DAG.getDataLayout().isBigEndian())
435 // The odd parts were reversed by getCopyToParts - unreverse them.
436 std::reverse(Parts + RoundParts, Parts + NumParts);
438 NumParts = RoundParts;
439 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
440 Val = DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val);
443 // The number of parts is a power of 2. Repeatedly bisect the value using
445 Parts[0] = DAG.getNode(ISD::BITCAST, DL,
446 EVT::getIntegerVT(*DAG.getContext(),
447 ValueVT.getSizeInBits()),
450 for (unsigned StepSize = NumParts; StepSize > 1; StepSize /= 2) {
451 for (unsigned i = 0; i < NumParts; i += StepSize) {
452 unsigned ThisBits = StepSize * PartBits / 2;
453 EVT ThisVT = EVT::getIntegerVT(*DAG.getContext(), ThisBits);
454 SDValue &Part0 = Parts[i];
455 SDValue &Part1 = Parts[i+StepSize/2];
457 Part1 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL,
458 ThisVT, Part0, DAG.getIntPtrConstant(1, DL));
459 Part0 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL,
460 ThisVT, Part0, DAG.getIntPtrConstant(0, DL));
462 if (ThisBits == PartBits && ThisVT != PartVT) {
463 Part0 = DAG.getNode(ISD::BITCAST, DL, PartVT, Part0);
464 Part1 = DAG.getNode(ISD::BITCAST, DL, PartVT, Part1);
469 if (DAG.getDataLayout().isBigEndian())
470 std::reverse(Parts, Parts + OrigNumParts);
474 /// getCopyToPartsVector - Create a series of nodes that contain the specified
475 /// value split into legal parts.
476 static void getCopyToPartsVector(SelectionDAG &DAG, SDLoc DL,
477 SDValue Val, SDValue *Parts, unsigned NumParts,
478 MVT PartVT, const Value *V) {
479 EVT ValueVT = Val.getValueType();
480 assert(ValueVT.isVector() && "Not a vector");
481 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
484 EVT PartEVT = PartVT;
485 if (PartEVT == ValueVT) {
487 } else if (PartVT.getSizeInBits() == ValueVT.getSizeInBits()) {
488 // Bitconvert vector->vector case.
489 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
490 } else if (PartVT.isVector() &&
491 PartEVT.getVectorElementType() == ValueVT.getVectorElementType() &&
492 PartEVT.getVectorNumElements() > ValueVT.getVectorNumElements()) {
493 EVT ElementVT = PartVT.getVectorElementType();
494 // Vector widening case, e.g. <2 x float> -> <4 x float>. Shuffle in
496 SmallVector<SDValue, 16> Ops;
497 for (unsigned i = 0, e = ValueVT.getVectorNumElements(); i != e; ++i)
498 Ops.push_back(DAG.getNode(
499 ISD::EXTRACT_VECTOR_ELT, DL, ElementVT, Val,
500 DAG.getConstant(i, DL, TLI.getVectorIdxTy(DAG.getDataLayout()))));
502 for (unsigned i = ValueVT.getVectorNumElements(),
503 e = PartVT.getVectorNumElements(); i != e; ++i)
504 Ops.push_back(DAG.getUNDEF(ElementVT));
506 Val = DAG.getNode(ISD::BUILD_VECTOR, DL, PartVT, Ops);
508 // FIXME: Use CONCAT for 2x -> 4x.
510 //SDValue UndefElts = DAG.getUNDEF(VectorTy);
511 //Val = DAG.getNode(ISD::CONCAT_VECTORS, DL, PartVT, Val, UndefElts);
512 } else if (PartVT.isVector() &&
513 PartEVT.getVectorElementType().bitsGE(
514 ValueVT.getVectorElementType()) &&
515 PartEVT.getVectorNumElements() == ValueVT.getVectorNumElements()) {
517 // Promoted vector extract
518 Val = DAG.getAnyExtOrTrunc(Val, DL, PartVT);
520 // Vector -> scalar conversion.
521 assert(ValueVT.getVectorNumElements() == 1 &&
522 "Only trivial vector-to-scalar conversions should get here!");
524 ISD::EXTRACT_VECTOR_ELT, DL, PartVT, Val,
525 DAG.getConstant(0, DL, TLI.getVectorIdxTy(DAG.getDataLayout())));
527 Val = DAG.getAnyExtOrTrunc(Val, DL, PartVT);
534 // Handle a multi-element vector.
537 unsigned NumIntermediates;
538 unsigned NumRegs = TLI.getVectorTypeBreakdown(*DAG.getContext(), ValueVT,
540 NumIntermediates, RegisterVT);
541 unsigned NumElements = ValueVT.getVectorNumElements();
543 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!");
544 NumParts = NumRegs; // Silence a compiler warning.
545 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!");
547 // Split the vector into intermediate operands.
548 SmallVector<SDValue, 8> Ops(NumIntermediates);
549 for (unsigned i = 0; i != NumIntermediates; ++i) {
550 if (IntermediateVT.isVector())
552 DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, IntermediateVT, Val,
553 DAG.getConstant(i * (NumElements / NumIntermediates), DL,
554 TLI.getVectorIdxTy(DAG.getDataLayout())));
556 Ops[i] = DAG.getNode(
557 ISD::EXTRACT_VECTOR_ELT, DL, IntermediateVT, Val,
558 DAG.getConstant(i, DL, TLI.getVectorIdxTy(DAG.getDataLayout())));
561 // Split the intermediate operands into legal parts.
562 if (NumParts == NumIntermediates) {
563 // If the register was not expanded, promote or copy the value,
565 for (unsigned i = 0; i != NumParts; ++i)
566 getCopyToParts(DAG, DL, Ops[i], &Parts[i], 1, PartVT, V);
567 } else if (NumParts > 0) {
568 // If the intermediate type was expanded, split each the value into
570 assert(NumIntermediates != 0 && "division by zero");
571 assert(NumParts % NumIntermediates == 0 &&
572 "Must expand into a divisible number of parts!");
573 unsigned Factor = NumParts / NumIntermediates;
574 for (unsigned i = 0; i != NumIntermediates; ++i)
575 getCopyToParts(DAG, DL, Ops[i], &Parts[i*Factor], Factor, PartVT, V);
579 RegsForValue::RegsForValue() {}
581 RegsForValue::RegsForValue(const SmallVector<unsigned, 4> ®s, MVT regvt,
583 : ValueVTs(1, valuevt), RegVTs(1, regvt), Regs(regs) {}
585 RegsForValue::RegsForValue(LLVMContext &Context, const TargetLowering &TLI,
586 const DataLayout &DL, unsigned Reg, Type *Ty) {
587 ComputeValueVTs(TLI, DL, Ty, ValueVTs);
589 for (EVT ValueVT : ValueVTs) {
590 unsigned NumRegs = TLI.getNumRegisters(Context, ValueVT);
591 MVT RegisterVT = TLI.getRegisterType(Context, ValueVT);
592 for (unsigned i = 0; i != NumRegs; ++i)
593 Regs.push_back(Reg + i);
594 RegVTs.push_back(RegisterVT);
599 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from
600 /// this value and returns the result as a ValueVT value. This uses
601 /// Chain/Flag as the input and updates them for the output Chain/Flag.
602 /// If the Flag pointer is NULL, no flag is used.
603 SDValue RegsForValue::getCopyFromRegs(SelectionDAG &DAG,
604 FunctionLoweringInfo &FuncInfo,
606 SDValue &Chain, SDValue *Flag,
607 const Value *V) const {
608 // A Value with type {} or [0 x %t] needs no registers.
609 if (ValueVTs.empty())
612 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
614 // Assemble the legal parts into the final values.
615 SmallVector<SDValue, 4> Values(ValueVTs.size());
616 SmallVector<SDValue, 8> Parts;
617 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) {
618 // Copy the legal parts from the registers.
619 EVT ValueVT = ValueVTs[Value];
620 unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), ValueVT);
621 MVT RegisterVT = RegVTs[Value];
623 Parts.resize(NumRegs);
624 for (unsigned i = 0; i != NumRegs; ++i) {
627 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT);
629 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT, *Flag);
630 *Flag = P.getValue(2);
633 Chain = P.getValue(1);
636 // If the source register was virtual and if we know something about it,
637 // add an assert node.
638 if (!TargetRegisterInfo::isVirtualRegister(Regs[Part+i]) ||
639 !RegisterVT.isInteger() || RegisterVT.isVector())
642 const FunctionLoweringInfo::LiveOutInfo *LOI =
643 FuncInfo.GetLiveOutRegInfo(Regs[Part+i]);
647 unsigned RegSize = RegisterVT.getSizeInBits();
648 unsigned NumSignBits = LOI->NumSignBits;
649 unsigned NumZeroBits = LOI->KnownZero.countLeadingOnes();
651 if (NumZeroBits == RegSize) {
652 // The current value is a zero.
653 // Explicitly express that as it would be easier for
654 // optimizations to kick in.
655 Parts[i] = DAG.getConstant(0, dl, RegisterVT);
659 // FIXME: We capture more information than the dag can represent. For
660 // now, just use the tightest assertzext/assertsext possible.
662 EVT FromVT(MVT::Other);
663 if (NumSignBits == RegSize)
664 isSExt = true, FromVT = MVT::i1; // ASSERT SEXT 1
665 else if (NumZeroBits >= RegSize-1)
666 isSExt = false, FromVT = MVT::i1; // ASSERT ZEXT 1
667 else if (NumSignBits > RegSize-8)
668 isSExt = true, FromVT = MVT::i8; // ASSERT SEXT 8
669 else if (NumZeroBits >= RegSize-8)
670 isSExt = false, FromVT = MVT::i8; // ASSERT ZEXT 8
671 else if (NumSignBits > RegSize-16)
672 isSExt = true, FromVT = MVT::i16; // ASSERT SEXT 16
673 else if (NumZeroBits >= RegSize-16)
674 isSExt = false, FromVT = MVT::i16; // ASSERT ZEXT 16
675 else if (NumSignBits > RegSize-32)
676 isSExt = true, FromVT = MVT::i32; // ASSERT SEXT 32
677 else if (NumZeroBits >= RegSize-32)
678 isSExt = false, FromVT = MVT::i32; // ASSERT ZEXT 32
682 // Add an assertion node.
683 assert(FromVT != MVT::Other);
684 Parts[i] = DAG.getNode(isSExt ? ISD::AssertSext : ISD::AssertZext, dl,
685 RegisterVT, P, DAG.getValueType(FromVT));
688 Values[Value] = getCopyFromParts(DAG, dl, Parts.begin(),
689 NumRegs, RegisterVT, ValueVT, V);
694 return DAG.getNode(ISD::MERGE_VALUES, dl, DAG.getVTList(ValueVTs), Values);
697 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
698 /// specified value into the registers specified by this object. This uses
699 /// Chain/Flag as the input and updates them for the output Chain/Flag.
700 /// If the Flag pointer is NULL, no flag is used.
701 void RegsForValue::getCopyToRegs(SDValue Val, SelectionDAG &DAG, SDLoc dl,
702 SDValue &Chain, SDValue *Flag, const Value *V,
703 ISD::NodeType PreferredExtendType) const {
704 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
705 ISD::NodeType ExtendKind = PreferredExtendType;
707 // Get the list of the values's legal parts.
708 unsigned NumRegs = Regs.size();
709 SmallVector<SDValue, 8> Parts(NumRegs);
710 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) {
711 EVT ValueVT = ValueVTs[Value];
712 unsigned NumParts = TLI.getNumRegisters(*DAG.getContext(), ValueVT);
713 MVT RegisterVT = RegVTs[Value];
715 if (ExtendKind == ISD::ANY_EXTEND && TLI.isZExtFree(Val, RegisterVT))
716 ExtendKind = ISD::ZERO_EXTEND;
718 getCopyToParts(DAG, dl, Val.getValue(Val.getResNo() + Value),
719 &Parts[Part], NumParts, RegisterVT, V, ExtendKind);
723 // Copy the parts into the registers.
724 SmallVector<SDValue, 8> Chains(NumRegs);
725 for (unsigned i = 0; i != NumRegs; ++i) {
728 Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i]);
730 Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i], *Flag);
731 *Flag = Part.getValue(1);
734 Chains[i] = Part.getValue(0);
737 if (NumRegs == 1 || Flag)
738 // If NumRegs > 1 && Flag is used then the use of the last CopyToReg is
739 // flagged to it. That is the CopyToReg nodes and the user are considered
740 // a single scheduling unit. If we create a TokenFactor and return it as
741 // chain, then the TokenFactor is both a predecessor (operand) of the
742 // user as well as a successor (the TF operands are flagged to the user).
743 // c1, f1 = CopyToReg
744 // c2, f2 = CopyToReg
745 // c3 = TokenFactor c1, c2
748 Chain = Chains[NumRegs-1];
750 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Chains);
753 /// AddInlineAsmOperands - Add this value to the specified inlineasm node
754 /// operand list. This adds the code marker and includes the number of
755 /// values added into it.
756 void RegsForValue::AddInlineAsmOperands(unsigned Code, bool HasMatching,
757 unsigned MatchingIdx, SDLoc dl,
759 std::vector<SDValue> &Ops) const {
760 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
762 unsigned Flag = InlineAsm::getFlagWord(Code, Regs.size());
764 Flag = InlineAsm::getFlagWordForMatchingOp(Flag, MatchingIdx);
765 else if (!Regs.empty() &&
766 TargetRegisterInfo::isVirtualRegister(Regs.front())) {
767 // Put the register class of the virtual registers in the flag word. That
768 // way, later passes can recompute register class constraints for inline
769 // assembly as well as normal instructions.
770 // Don't do this for tied operands that can use the regclass information
772 const MachineRegisterInfo &MRI = DAG.getMachineFunction().getRegInfo();
773 const TargetRegisterClass *RC = MRI.getRegClass(Regs.front());
774 Flag = InlineAsm::getFlagWordForRegClass(Flag, RC->getID());
777 SDValue Res = DAG.getTargetConstant(Flag, dl, MVT::i32);
780 unsigned SP = TLI.getStackPointerRegisterToSaveRestore();
781 for (unsigned Value = 0, Reg = 0, e = ValueVTs.size(); Value != e; ++Value) {
782 unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), ValueVTs[Value]);
783 MVT RegisterVT = RegVTs[Value];
784 for (unsigned i = 0; i != NumRegs; ++i) {
785 assert(Reg < Regs.size() && "Mismatch in # registers expected");
786 unsigned TheReg = Regs[Reg++];
787 Ops.push_back(DAG.getRegister(TheReg, RegisterVT));
789 if (TheReg == SP && Code == InlineAsm::Kind_Clobber) {
790 // If we clobbered the stack pointer, MFI should know about it.
791 assert(DAG.getMachineFunction().getFrameInfo()->
792 hasOpaqueSPAdjustment());
798 void SelectionDAGBuilder::init(GCFunctionInfo *gfi, AliasAnalysis &aa,
799 const TargetLibraryInfo *li) {
803 DL = &DAG.getDataLayout();
804 Context = DAG.getContext();
805 LPadToCallSiteMap.clear();
808 /// clear - Clear out the current SelectionDAG and the associated
809 /// state and prepare this SelectionDAGBuilder object to be used
810 /// for a new block. This doesn't clear out information about
811 /// additional blocks that are needed to complete switch lowering
812 /// or PHI node updating; that information is cleared out as it is
814 void SelectionDAGBuilder::clear() {
816 UnusedArgNodeMap.clear();
817 PendingLoads.clear();
818 PendingExports.clear();
821 SDNodeOrder = LowestSDNodeOrder;
822 StatepointLowering.clear();
825 /// clearDanglingDebugInfo - Clear the dangling debug information
826 /// map. This function is separated from the clear so that debug
827 /// information that is dangling in a basic block can be properly
828 /// resolved in a different basic block. This allows the
829 /// SelectionDAG to resolve dangling debug information attached
831 void SelectionDAGBuilder::clearDanglingDebugInfo() {
832 DanglingDebugInfoMap.clear();
835 /// getRoot - Return the current virtual root of the Selection DAG,
836 /// flushing any PendingLoad items. This must be done before emitting
837 /// a store or any other node that may need to be ordered after any
838 /// prior load instructions.
840 SDValue SelectionDAGBuilder::getRoot() {
841 if (PendingLoads.empty())
842 return DAG.getRoot();
844 if (PendingLoads.size() == 1) {
845 SDValue Root = PendingLoads[0];
847 PendingLoads.clear();
851 // Otherwise, we have to make a token factor node.
852 SDValue Root = DAG.getNode(ISD::TokenFactor, getCurSDLoc(), MVT::Other,
854 PendingLoads.clear();
859 /// getControlRoot - Similar to getRoot, but instead of flushing all the
860 /// PendingLoad items, flush all the PendingExports items. It is necessary
861 /// to do this before emitting a terminator instruction.
863 SDValue SelectionDAGBuilder::getControlRoot() {
864 SDValue Root = DAG.getRoot();
866 if (PendingExports.empty())
869 // Turn all of the CopyToReg chains into one factored node.
870 if (Root.getOpcode() != ISD::EntryToken) {
871 unsigned i = 0, e = PendingExports.size();
872 for (; i != e; ++i) {
873 assert(PendingExports[i].getNode()->getNumOperands() > 1);
874 if (PendingExports[i].getNode()->getOperand(0) == Root)
875 break; // Don't add the root if we already indirectly depend on it.
879 PendingExports.push_back(Root);
882 Root = DAG.getNode(ISD::TokenFactor, getCurSDLoc(), MVT::Other,
884 PendingExports.clear();
889 void SelectionDAGBuilder::visit(const Instruction &I) {
890 // Set up outgoing PHI node register values before emitting the terminator.
891 if (isa<TerminatorInst>(&I))
892 HandlePHINodesInSuccessorBlocks(I.getParent());
898 visit(I.getOpcode(), I);
900 if (!isa<TerminatorInst>(&I) && !HasTailCall)
901 CopyToExportRegsIfNeeded(&I);
906 void SelectionDAGBuilder::visitPHI(const PHINode &) {
907 llvm_unreachable("SelectionDAGBuilder shouldn't visit PHI nodes!");
910 void SelectionDAGBuilder::visit(unsigned Opcode, const User &I) {
911 // Note: this doesn't use InstVisitor, because it has to work with
912 // ConstantExpr's in addition to instructions.
914 default: llvm_unreachable("Unknown instruction type encountered!");
915 // Build the switch statement using the Instruction.def file.
916 #define HANDLE_INST(NUM, OPCODE, CLASS) \
917 case Instruction::OPCODE: visit##OPCODE((const CLASS&)I); break;
918 #include "llvm/IR/Instruction.def"
922 // resolveDanglingDebugInfo - if we saw an earlier dbg_value referring to V,
923 // generate the debug data structures now that we've seen its definition.
924 void SelectionDAGBuilder::resolveDanglingDebugInfo(const Value *V,
926 DanglingDebugInfo &DDI = DanglingDebugInfoMap[V];
928 const DbgValueInst *DI = DDI.getDI();
929 DebugLoc dl = DDI.getdl();
930 unsigned DbgSDNodeOrder = DDI.getSDNodeOrder();
931 DILocalVariable *Variable = DI->getVariable();
932 DIExpression *Expr = DI->getExpression();
933 assert(Variable->isValidLocationForIntrinsic(dl) &&
934 "Expected inlined-at fields to agree");
935 uint64_t Offset = DI->getOffset();
936 // A dbg.value for an alloca is always indirect.
937 bool IsIndirect = isa<AllocaInst>(V) || Offset != 0;
940 if (!EmitFuncArgumentDbgValue(V, Variable, Expr, dl, Offset, IsIndirect,
942 SDV = DAG.getDbgValue(Variable, Expr, Val.getNode(), Val.getResNo(),
943 IsIndirect, Offset, dl, DbgSDNodeOrder);
944 DAG.AddDbgValue(SDV, Val.getNode(), false);
947 DEBUG(dbgs() << "Dropping debug info for " << *DI << "\n");
948 DanglingDebugInfoMap[V] = DanglingDebugInfo();
952 /// getCopyFromRegs - If there was virtual register allocated for the value V
953 /// emit CopyFromReg of the specified type Ty. Return empty SDValue() otherwise.
954 SDValue SelectionDAGBuilder::getCopyFromRegs(const Value *V, Type *Ty) {
955 DenseMap<const Value *, unsigned>::iterator It = FuncInfo.ValueMap.find(V);
958 if (It != FuncInfo.ValueMap.end()) {
959 unsigned InReg = It->second;
960 RegsForValue RFV(*DAG.getContext(), DAG.getTargetLoweringInfo(),
961 DAG.getDataLayout(), InReg, Ty);
962 SDValue Chain = DAG.getEntryNode();
963 Result = RFV.getCopyFromRegs(DAG, FuncInfo, getCurSDLoc(), Chain, nullptr, V);
964 resolveDanglingDebugInfo(V, Result);
970 /// getValue - Return an SDValue for the given Value.
971 SDValue SelectionDAGBuilder::getValue(const Value *V) {
972 // If we already have an SDValue for this value, use it. It's important
973 // to do this first, so that we don't create a CopyFromReg if we already
974 // have a regular SDValue.
975 SDValue &N = NodeMap[V];
976 if (N.getNode()) return N;
978 // If there's a virtual register allocated and initialized for this
980 SDValue copyFromReg = getCopyFromRegs(V, V->getType());
981 if (copyFromReg.getNode()) {
985 // Otherwise create a new SDValue and remember it.
986 SDValue Val = getValueImpl(V);
988 resolveDanglingDebugInfo(V, Val);
992 // Return true if SDValue exists for the given Value
993 bool SelectionDAGBuilder::findValue(const Value *V) const {
994 return (NodeMap.find(V) != NodeMap.end()) ||
995 (FuncInfo.ValueMap.find(V) != FuncInfo.ValueMap.end());
998 /// getNonRegisterValue - Return an SDValue for the given Value, but
999 /// don't look in FuncInfo.ValueMap for a virtual register.
1000 SDValue SelectionDAGBuilder::getNonRegisterValue(const Value *V) {
1001 // If we already have an SDValue for this value, use it.
1002 SDValue &N = NodeMap[V];
1004 if (isa<ConstantSDNode>(N) || isa<ConstantFPSDNode>(N)) {
1005 // Remove the debug location from the node as the node is about to be used
1006 // in a location which may differ from the original debug location. This
1007 // is relevant to Constant and ConstantFP nodes because they can appear
1008 // as constant expressions inside PHI nodes.
1009 N->setDebugLoc(DebugLoc());
1014 // Otherwise create a new SDValue and remember it.
1015 SDValue Val = getValueImpl(V);
1017 resolveDanglingDebugInfo(V, Val);
1021 /// getValueImpl - Helper function for getValue and getNonRegisterValue.
1022 /// Create an SDValue for the given value.
1023 SDValue SelectionDAGBuilder::getValueImpl(const Value *V) {
1024 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1026 if (const Constant *C = dyn_cast<Constant>(V)) {
1027 EVT VT = TLI.getValueType(DAG.getDataLayout(), V->getType(), true);
1029 if (const ConstantInt *CI = dyn_cast<ConstantInt>(C))
1030 return DAG.getConstant(*CI, getCurSDLoc(), VT);
1032 if (const GlobalValue *GV = dyn_cast<GlobalValue>(C))
1033 return DAG.getGlobalAddress(GV, getCurSDLoc(), VT);
1035 if (isa<ConstantPointerNull>(C)) {
1036 unsigned AS = V->getType()->getPointerAddressSpace();
1037 return DAG.getConstant(0, getCurSDLoc(),
1038 TLI.getPointerTy(DAG.getDataLayout(), AS));
1041 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(C))
1042 return DAG.getConstantFP(*CFP, getCurSDLoc(), VT);
1044 if (isa<UndefValue>(C) && !V->getType()->isAggregateType())
1045 return DAG.getUNDEF(VT);
1047 if (const ConstantExpr *CE = dyn_cast<ConstantExpr>(C)) {
1048 visit(CE->getOpcode(), *CE);
1049 SDValue N1 = NodeMap[V];
1050 assert(N1.getNode() && "visit didn't populate the NodeMap!");
1054 if (isa<ConstantStruct>(C) || isa<ConstantArray>(C)) {
1055 SmallVector<SDValue, 4> Constants;
1056 for (User::const_op_iterator OI = C->op_begin(), OE = C->op_end();
1058 SDNode *Val = getValue(*OI).getNode();
1059 // If the operand is an empty aggregate, there are no values.
1061 // Add each leaf value from the operand to the Constants list
1062 // to form a flattened list of all the values.
1063 for (unsigned i = 0, e = Val->getNumValues(); i != e; ++i)
1064 Constants.push_back(SDValue(Val, i));
1067 return DAG.getMergeValues(Constants, getCurSDLoc());
1070 if (const ConstantDataSequential *CDS =
1071 dyn_cast<ConstantDataSequential>(C)) {
1072 SmallVector<SDValue, 4> Ops;
1073 for (unsigned i = 0, e = CDS->getNumElements(); i != e; ++i) {
1074 SDNode *Val = getValue(CDS->getElementAsConstant(i)).getNode();
1075 // Add each leaf value from the operand to the Constants list
1076 // to form a flattened list of all the values.
1077 for (unsigned i = 0, e = Val->getNumValues(); i != e; ++i)
1078 Ops.push_back(SDValue(Val, i));
1081 if (isa<ArrayType>(CDS->getType()))
1082 return DAG.getMergeValues(Ops, getCurSDLoc());
1083 return NodeMap[V] = DAG.getNode(ISD::BUILD_VECTOR, getCurSDLoc(),
1087 if (C->getType()->isStructTy() || C->getType()->isArrayTy()) {
1088 assert((isa<ConstantAggregateZero>(C) || isa<UndefValue>(C)) &&
1089 "Unknown struct or array constant!");
1091 SmallVector<EVT, 4> ValueVTs;
1092 ComputeValueVTs(TLI, DAG.getDataLayout(), C->getType(), ValueVTs);
1093 unsigned NumElts = ValueVTs.size();
1095 return SDValue(); // empty struct
1096 SmallVector<SDValue, 4> Constants(NumElts);
1097 for (unsigned i = 0; i != NumElts; ++i) {
1098 EVT EltVT = ValueVTs[i];
1099 if (isa<UndefValue>(C))
1100 Constants[i] = DAG.getUNDEF(EltVT);
1101 else if (EltVT.isFloatingPoint())
1102 Constants[i] = DAG.getConstantFP(0, getCurSDLoc(), EltVT);
1104 Constants[i] = DAG.getConstant(0, getCurSDLoc(), EltVT);
1107 return DAG.getMergeValues(Constants, getCurSDLoc());
1110 if (const BlockAddress *BA = dyn_cast<BlockAddress>(C))
1111 return DAG.getBlockAddress(BA, VT);
1113 VectorType *VecTy = cast<VectorType>(V->getType());
1114 unsigned NumElements = VecTy->getNumElements();
1116 // Now that we know the number and type of the elements, get that number of
1117 // elements into the Ops array based on what kind of constant it is.
1118 SmallVector<SDValue, 16> Ops;
1119 if (const ConstantVector *CV = dyn_cast<ConstantVector>(C)) {
1120 for (unsigned i = 0; i != NumElements; ++i)
1121 Ops.push_back(getValue(CV->getOperand(i)));
1123 assert(isa<ConstantAggregateZero>(C) && "Unknown vector constant!");
1125 TLI.getValueType(DAG.getDataLayout(), VecTy->getElementType());
1128 if (EltVT.isFloatingPoint())
1129 Op = DAG.getConstantFP(0, getCurSDLoc(), EltVT);
1131 Op = DAG.getConstant(0, getCurSDLoc(), EltVT);
1132 Ops.assign(NumElements, Op);
1135 // Create a BUILD_VECTOR node.
1136 return NodeMap[V] = DAG.getNode(ISD::BUILD_VECTOR, getCurSDLoc(), VT, Ops);
1139 // If this is a static alloca, generate it as the frameindex instead of
1141 if (const AllocaInst *AI = dyn_cast<AllocaInst>(V)) {
1142 DenseMap<const AllocaInst*, int>::iterator SI =
1143 FuncInfo.StaticAllocaMap.find(AI);
1144 if (SI != FuncInfo.StaticAllocaMap.end())
1145 return DAG.getFrameIndex(SI->second,
1146 TLI.getPointerTy(DAG.getDataLayout()));
1149 // If this is an instruction which fast-isel has deferred, select it now.
1150 if (const Instruction *Inst = dyn_cast<Instruction>(V)) {
1151 unsigned InReg = FuncInfo.InitializeRegForValue(Inst);
1152 RegsForValue RFV(*DAG.getContext(), TLI, DAG.getDataLayout(), InReg,
1154 SDValue Chain = DAG.getEntryNode();
1155 return RFV.getCopyFromRegs(DAG, FuncInfo, getCurSDLoc(), Chain, nullptr, V);
1158 llvm_unreachable("Can't get register for value!");
1161 void SelectionDAGBuilder::visitCleanupRet(const CleanupReturnInst &I) {
1162 report_fatal_error("visitCleanupRet not yet implemented!");
1165 void SelectionDAGBuilder::visitCatchEndPad(const CatchEndPadInst &I) {
1166 report_fatal_error("visitCatchEndPad not yet implemented!");
1169 void SelectionDAGBuilder::visitCatchRet(const CatchReturnInst &I) {
1170 report_fatal_error("visitCatchRet not yet implemented!");
1173 void SelectionDAGBuilder::visitCatchPad(const CatchPadInst &I) {
1174 report_fatal_error("visitCatchPad not yet implemented!");
1177 void SelectionDAGBuilder::visitTerminatePad(const TerminatePadInst &TPI) {
1178 report_fatal_error("visitTerminatePad not yet implemented!");
1181 void SelectionDAGBuilder::visitCleanupPad(const CleanupPadInst &CPI) {
1182 report_fatal_error("visitCleanupPad not yet implemented!");
1185 void SelectionDAGBuilder::visitRet(const ReturnInst &I) {
1186 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1187 auto &DL = DAG.getDataLayout();
1188 SDValue Chain = getControlRoot();
1189 SmallVector<ISD::OutputArg, 8> Outs;
1190 SmallVector<SDValue, 8> OutVals;
1192 if (!FuncInfo.CanLowerReturn) {
1193 unsigned DemoteReg = FuncInfo.DemoteRegister;
1194 const Function *F = I.getParent()->getParent();
1196 // Emit a store of the return value through the virtual register.
1197 // Leave Outs empty so that LowerReturn won't try to load return
1198 // registers the usual way.
1199 SmallVector<EVT, 1> PtrValueVTs;
1200 ComputeValueVTs(TLI, DL, PointerType::getUnqual(F->getReturnType()),
1203 SDValue RetPtr = DAG.getRegister(DemoteReg, PtrValueVTs[0]);
1204 SDValue RetOp = getValue(I.getOperand(0));
1206 SmallVector<EVT, 4> ValueVTs;
1207 SmallVector<uint64_t, 4> Offsets;
1208 ComputeValueVTs(TLI, DL, I.getOperand(0)->getType(), ValueVTs, &Offsets);
1209 unsigned NumValues = ValueVTs.size();
1211 SmallVector<SDValue, 4> Chains(NumValues);
1212 for (unsigned i = 0; i != NumValues; ++i) {
1213 SDValue Add = DAG.getNode(ISD::ADD, getCurSDLoc(),
1214 RetPtr.getValueType(), RetPtr,
1215 DAG.getIntPtrConstant(Offsets[i],
1218 DAG.getStore(Chain, getCurSDLoc(),
1219 SDValue(RetOp.getNode(), RetOp.getResNo() + i),
1220 // FIXME: better loc info would be nice.
1221 Add, MachinePointerInfo(), false, false, 0);
1224 Chain = DAG.getNode(ISD::TokenFactor, getCurSDLoc(),
1225 MVT::Other, Chains);
1226 } else if (I.getNumOperands() != 0) {
1227 SmallVector<EVT, 4> ValueVTs;
1228 ComputeValueVTs(TLI, DL, I.getOperand(0)->getType(), ValueVTs);
1229 unsigned NumValues = ValueVTs.size();
1231 SDValue RetOp = getValue(I.getOperand(0));
1233 const Function *F = I.getParent()->getParent();
1235 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
1236 if (F->getAttributes().hasAttribute(AttributeSet::ReturnIndex,
1238 ExtendKind = ISD::SIGN_EXTEND;
1239 else if (F->getAttributes().hasAttribute(AttributeSet::ReturnIndex,
1241 ExtendKind = ISD::ZERO_EXTEND;
1243 LLVMContext &Context = F->getContext();
1244 bool RetInReg = F->getAttributes().hasAttribute(AttributeSet::ReturnIndex,
1247 for (unsigned j = 0; j != NumValues; ++j) {
1248 EVT VT = ValueVTs[j];
1250 if (ExtendKind != ISD::ANY_EXTEND && VT.isInteger())
1251 VT = TLI.getTypeForExtArgOrReturn(Context, VT, ExtendKind);
1253 unsigned NumParts = TLI.getNumRegisters(Context, VT);
1254 MVT PartVT = TLI.getRegisterType(Context, VT);
1255 SmallVector<SDValue, 4> Parts(NumParts);
1256 getCopyToParts(DAG, getCurSDLoc(),
1257 SDValue(RetOp.getNode(), RetOp.getResNo() + j),
1258 &Parts[0], NumParts, PartVT, &I, ExtendKind);
1260 // 'inreg' on function refers to return value
1261 ISD::ArgFlagsTy Flags = ISD::ArgFlagsTy();
1265 // Propagate extension type if any
1266 if (ExtendKind == ISD::SIGN_EXTEND)
1268 else if (ExtendKind == ISD::ZERO_EXTEND)
1271 for (unsigned i = 0; i < NumParts; ++i) {
1272 Outs.push_back(ISD::OutputArg(Flags, Parts[i].getValueType(),
1273 VT, /*isfixed=*/true, 0, 0));
1274 OutVals.push_back(Parts[i]);
1280 bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg();
1281 CallingConv::ID CallConv =
1282 DAG.getMachineFunction().getFunction()->getCallingConv();
1283 Chain = DAG.getTargetLoweringInfo().LowerReturn(
1284 Chain, CallConv, isVarArg, Outs, OutVals, getCurSDLoc(), DAG);
1286 // Verify that the target's LowerReturn behaved as expected.
1287 assert(Chain.getNode() && Chain.getValueType() == MVT::Other &&
1288 "LowerReturn didn't return a valid chain!");
1290 // Update the DAG with the new chain value resulting from return lowering.
1294 /// CopyToExportRegsIfNeeded - If the given value has virtual registers
1295 /// created for it, emit nodes to copy the value into the virtual
1297 void SelectionDAGBuilder::CopyToExportRegsIfNeeded(const Value *V) {
1299 if (V->getType()->isEmptyTy())
1302 DenseMap<const Value *, unsigned>::iterator VMI = FuncInfo.ValueMap.find(V);
1303 if (VMI != FuncInfo.ValueMap.end()) {
1304 assert(!V->use_empty() && "Unused value assigned virtual registers!");
1305 CopyValueToVirtualRegister(V, VMI->second);
1309 /// ExportFromCurrentBlock - If this condition isn't known to be exported from
1310 /// the current basic block, add it to ValueMap now so that we'll get a
1312 void SelectionDAGBuilder::ExportFromCurrentBlock(const Value *V) {
1313 // No need to export constants.
1314 if (!isa<Instruction>(V) && !isa<Argument>(V)) return;
1316 // Already exported?
1317 if (FuncInfo.isExportedInst(V)) return;
1319 unsigned Reg = FuncInfo.InitializeRegForValue(V);
1320 CopyValueToVirtualRegister(V, Reg);
1323 bool SelectionDAGBuilder::isExportableFromCurrentBlock(const Value *V,
1324 const BasicBlock *FromBB) {
1325 // The operands of the setcc have to be in this block. We don't know
1326 // how to export them from some other block.
1327 if (const Instruction *VI = dyn_cast<Instruction>(V)) {
1328 // Can export from current BB.
1329 if (VI->getParent() == FromBB)
1332 // Is already exported, noop.
1333 return FuncInfo.isExportedInst(V);
1336 // If this is an argument, we can export it if the BB is the entry block or
1337 // if it is already exported.
1338 if (isa<Argument>(V)) {
1339 if (FromBB == &FromBB->getParent()->getEntryBlock())
1342 // Otherwise, can only export this if it is already exported.
1343 return FuncInfo.isExportedInst(V);
1346 // Otherwise, constants can always be exported.
1350 /// Return branch probability calculated by BranchProbabilityInfo for IR blocks.
1351 uint32_t SelectionDAGBuilder::getEdgeWeight(const MachineBasicBlock *Src,
1352 const MachineBasicBlock *Dst) const {
1353 BranchProbabilityInfo *BPI = FuncInfo.BPI;
1356 const BasicBlock *SrcBB = Src->getBasicBlock();
1357 const BasicBlock *DstBB = Dst->getBasicBlock();
1358 return BPI->getEdgeWeight(SrcBB, DstBB);
1361 void SelectionDAGBuilder::
1362 addSuccessorWithWeight(MachineBasicBlock *Src, MachineBasicBlock *Dst,
1363 uint32_t Weight /* = 0 */) {
1365 Weight = getEdgeWeight(Src, Dst);
1366 Src->addSuccessor(Dst, Weight);
1370 static bool InBlock(const Value *V, const BasicBlock *BB) {
1371 if (const Instruction *I = dyn_cast<Instruction>(V))
1372 return I->getParent() == BB;
1376 /// EmitBranchForMergedCondition - Helper method for FindMergedConditions.
1377 /// This function emits a branch and is used at the leaves of an OR or an
1378 /// AND operator tree.
1381 SelectionDAGBuilder::EmitBranchForMergedCondition(const Value *Cond,
1382 MachineBasicBlock *TBB,
1383 MachineBasicBlock *FBB,
1384 MachineBasicBlock *CurBB,
1385 MachineBasicBlock *SwitchBB,
1388 const BasicBlock *BB = CurBB->getBasicBlock();
1390 // If the leaf of the tree is a comparison, merge the condition into
1392 if (const CmpInst *BOp = dyn_cast<CmpInst>(Cond)) {
1393 // The operands of the cmp have to be in this block. We don't know
1394 // how to export them from some other block. If this is the first block
1395 // of the sequence, no exporting is needed.
1396 if (CurBB == SwitchBB ||
1397 (isExportableFromCurrentBlock(BOp->getOperand(0), BB) &&
1398 isExportableFromCurrentBlock(BOp->getOperand(1), BB))) {
1399 ISD::CondCode Condition;
1400 if (const ICmpInst *IC = dyn_cast<ICmpInst>(Cond)) {
1401 Condition = getICmpCondCode(IC->getPredicate());
1403 const FCmpInst *FC = cast<FCmpInst>(Cond);
1404 Condition = getFCmpCondCode(FC->getPredicate());
1405 if (TM.Options.NoNaNsFPMath)
1406 Condition = getFCmpCodeWithoutNaN(Condition);
1409 CaseBlock CB(Condition, BOp->getOperand(0), BOp->getOperand(1), nullptr,
1410 TBB, FBB, CurBB, TWeight, FWeight);
1411 SwitchCases.push_back(CB);
1416 // Create a CaseBlock record representing this branch.
1417 CaseBlock CB(ISD::SETEQ, Cond, ConstantInt::getTrue(*DAG.getContext()),
1418 nullptr, TBB, FBB, CurBB, TWeight, FWeight);
1419 SwitchCases.push_back(CB);
1422 /// Scale down both weights to fit into uint32_t.
1423 static void ScaleWeights(uint64_t &NewTrue, uint64_t &NewFalse) {
1424 uint64_t NewMax = (NewTrue > NewFalse) ? NewTrue : NewFalse;
1425 uint32_t Scale = (NewMax / UINT32_MAX) + 1;
1426 NewTrue = NewTrue / Scale;
1427 NewFalse = NewFalse / Scale;
1430 /// FindMergedConditions - If Cond is an expression like
1431 void SelectionDAGBuilder::FindMergedConditions(const Value *Cond,
1432 MachineBasicBlock *TBB,
1433 MachineBasicBlock *FBB,
1434 MachineBasicBlock *CurBB,
1435 MachineBasicBlock *SwitchBB,
1436 Instruction::BinaryOps Opc,
1439 // If this node is not part of the or/and tree, emit it as a branch.
1440 const Instruction *BOp = dyn_cast<Instruction>(Cond);
1441 if (!BOp || !(isa<BinaryOperator>(BOp) || isa<CmpInst>(BOp)) ||
1442 (unsigned)BOp->getOpcode() != Opc || !BOp->hasOneUse() ||
1443 BOp->getParent() != CurBB->getBasicBlock() ||
1444 !InBlock(BOp->getOperand(0), CurBB->getBasicBlock()) ||
1445 !InBlock(BOp->getOperand(1), CurBB->getBasicBlock())) {
1446 EmitBranchForMergedCondition(Cond, TBB, FBB, CurBB, SwitchBB,
1451 // Create TmpBB after CurBB.
1452 MachineFunction::iterator BBI = CurBB;
1453 MachineFunction &MF = DAG.getMachineFunction();
1454 MachineBasicBlock *TmpBB = MF.CreateMachineBasicBlock(CurBB->getBasicBlock());
1455 CurBB->getParent()->insert(++BBI, TmpBB);
1457 if (Opc == Instruction::Or) {
1458 // Codegen X | Y as:
1467 // We have flexibility in setting Prob for BB1 and Prob for TmpBB.
1468 // The requirement is that
1469 // TrueProb for BB1 + (FalseProb for BB1 * TrueProb for TmpBB)
1470 // = TrueProb for original BB.
1471 // Assuming the original weights are A and B, one choice is to set BB1's
1472 // weights to A and A+2B, and set TmpBB's weights to A and 2B. This choice
1474 // TrueProb for BB1 == FalseProb for BB1 * TrueProb for TmpBB.
1475 // Another choice is to assume TrueProb for BB1 equals to TrueProb for
1476 // TmpBB, but the math is more complicated.
1478 uint64_t NewTrueWeight = TWeight;
1479 uint64_t NewFalseWeight = (uint64_t)TWeight + 2 * (uint64_t)FWeight;
1480 ScaleWeights(NewTrueWeight, NewFalseWeight);
1481 // Emit the LHS condition.
1482 FindMergedConditions(BOp->getOperand(0), TBB, TmpBB, CurBB, SwitchBB, Opc,
1483 NewTrueWeight, NewFalseWeight);
1485 NewTrueWeight = TWeight;
1486 NewFalseWeight = 2 * (uint64_t)FWeight;
1487 ScaleWeights(NewTrueWeight, NewFalseWeight);
1488 // Emit the RHS condition into TmpBB.
1489 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, SwitchBB, Opc,
1490 NewTrueWeight, NewFalseWeight);
1492 assert(Opc == Instruction::And && "Unknown merge op!");
1493 // Codegen X & Y as:
1501 // This requires creation of TmpBB after CurBB.
1503 // We have flexibility in setting Prob for BB1 and Prob for TmpBB.
1504 // The requirement is that
1505 // FalseProb for BB1 + (TrueProb for BB1 * FalseProb for TmpBB)
1506 // = FalseProb for original BB.
1507 // Assuming the original weights are A and B, one choice is to set BB1's
1508 // weights to 2A+B and B, and set TmpBB's weights to 2A and B. This choice
1510 // FalseProb for BB1 == TrueProb for BB1 * FalseProb for TmpBB.
1512 uint64_t NewTrueWeight = 2 * (uint64_t)TWeight + (uint64_t)FWeight;
1513 uint64_t NewFalseWeight = FWeight;
1514 ScaleWeights(NewTrueWeight, NewFalseWeight);
1515 // Emit the LHS condition.
1516 FindMergedConditions(BOp->getOperand(0), TmpBB, FBB, CurBB, SwitchBB, Opc,
1517 NewTrueWeight, NewFalseWeight);
1519 NewTrueWeight = 2 * (uint64_t)TWeight;
1520 NewFalseWeight = FWeight;
1521 ScaleWeights(NewTrueWeight, NewFalseWeight);
1522 // Emit the RHS condition into TmpBB.
1523 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, SwitchBB, Opc,
1524 NewTrueWeight, NewFalseWeight);
1528 /// If the set of cases should be emitted as a series of branches, return true.
1529 /// If we should emit this as a bunch of and/or'd together conditions, return
1532 SelectionDAGBuilder::ShouldEmitAsBranches(const std::vector<CaseBlock> &Cases) {
1533 if (Cases.size() != 2) return true;
1535 // If this is two comparisons of the same values or'd or and'd together, they
1536 // will get folded into a single comparison, so don't emit two blocks.
1537 if ((Cases[0].CmpLHS == Cases[1].CmpLHS &&
1538 Cases[0].CmpRHS == Cases[1].CmpRHS) ||
1539 (Cases[0].CmpRHS == Cases[1].CmpLHS &&
1540 Cases[0].CmpLHS == Cases[1].CmpRHS)) {
1544 // Handle: (X != null) | (Y != null) --> (X|Y) != 0
1545 // Handle: (X == null) & (Y == null) --> (X|Y) == 0
1546 if (Cases[0].CmpRHS == Cases[1].CmpRHS &&
1547 Cases[0].CC == Cases[1].CC &&
1548 isa<Constant>(Cases[0].CmpRHS) &&
1549 cast<Constant>(Cases[0].CmpRHS)->isNullValue()) {
1550 if (Cases[0].CC == ISD::SETEQ && Cases[0].TrueBB == Cases[1].ThisBB)
1552 if (Cases[0].CC == ISD::SETNE && Cases[0].FalseBB == Cases[1].ThisBB)
1559 void SelectionDAGBuilder::visitBr(const BranchInst &I) {
1560 MachineBasicBlock *BrMBB = FuncInfo.MBB;
1562 // Update machine-CFG edges.
1563 MachineBasicBlock *Succ0MBB = FuncInfo.MBBMap[I.getSuccessor(0)];
1565 if (I.isUnconditional()) {
1566 // Update machine-CFG edges.
1567 BrMBB->addSuccessor(Succ0MBB);
1569 // If this is not a fall-through branch or optimizations are switched off,
1571 if (Succ0MBB != NextBlock(BrMBB) || TM.getOptLevel() == CodeGenOpt::None)
1572 DAG.setRoot(DAG.getNode(ISD::BR, getCurSDLoc(),
1573 MVT::Other, getControlRoot(),
1574 DAG.getBasicBlock(Succ0MBB)));
1579 // If this condition is one of the special cases we handle, do special stuff
1581 const Value *CondVal = I.getCondition();
1582 MachineBasicBlock *Succ1MBB = FuncInfo.MBBMap[I.getSuccessor(1)];
1584 // If this is a series of conditions that are or'd or and'd together, emit
1585 // this as a sequence of branches instead of setcc's with and/or operations.
1586 // As long as jumps are not expensive, this should improve performance.
1587 // For example, instead of something like:
1600 if (const BinaryOperator *BOp = dyn_cast<BinaryOperator>(CondVal)) {
1601 if (!DAG.getTargetLoweringInfo().isJumpExpensive() &&
1602 BOp->hasOneUse() && (BOp->getOpcode() == Instruction::And ||
1603 BOp->getOpcode() == Instruction::Or)) {
1604 FindMergedConditions(BOp, Succ0MBB, Succ1MBB, BrMBB, BrMBB,
1605 BOp->getOpcode(), getEdgeWeight(BrMBB, Succ0MBB),
1606 getEdgeWeight(BrMBB, Succ1MBB));
1607 // If the compares in later blocks need to use values not currently
1608 // exported from this block, export them now. This block should always
1609 // be the first entry.
1610 assert(SwitchCases[0].ThisBB == BrMBB && "Unexpected lowering!");
1612 // Allow some cases to be rejected.
1613 if (ShouldEmitAsBranches(SwitchCases)) {
1614 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i) {
1615 ExportFromCurrentBlock(SwitchCases[i].CmpLHS);
1616 ExportFromCurrentBlock(SwitchCases[i].CmpRHS);
1619 // Emit the branch for this block.
1620 visitSwitchCase(SwitchCases[0], BrMBB);
1621 SwitchCases.erase(SwitchCases.begin());
1625 // Okay, we decided not to do this, remove any inserted MBB's and clear
1627 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i)
1628 FuncInfo.MF->erase(SwitchCases[i].ThisBB);
1630 SwitchCases.clear();
1634 // Create a CaseBlock record representing this branch.
1635 CaseBlock CB(ISD::SETEQ, CondVal, ConstantInt::getTrue(*DAG.getContext()),
1636 nullptr, Succ0MBB, Succ1MBB, BrMBB);
1638 // Use visitSwitchCase to actually insert the fast branch sequence for this
1640 visitSwitchCase(CB, BrMBB);
1643 /// visitSwitchCase - Emits the necessary code to represent a single node in
1644 /// the binary search tree resulting from lowering a switch instruction.
1645 void SelectionDAGBuilder::visitSwitchCase(CaseBlock &CB,
1646 MachineBasicBlock *SwitchBB) {
1648 SDValue CondLHS = getValue(CB.CmpLHS);
1649 SDLoc dl = getCurSDLoc();
1651 // Build the setcc now.
1653 // Fold "(X == true)" to X and "(X == false)" to !X to
1654 // handle common cases produced by branch lowering.
1655 if (CB.CmpRHS == ConstantInt::getTrue(*DAG.getContext()) &&
1656 CB.CC == ISD::SETEQ)
1658 else if (CB.CmpRHS == ConstantInt::getFalse(*DAG.getContext()) &&
1659 CB.CC == ISD::SETEQ) {
1660 SDValue True = DAG.getConstant(1, dl, CondLHS.getValueType());
1661 Cond = DAG.getNode(ISD::XOR, dl, CondLHS.getValueType(), CondLHS, True);
1663 Cond = DAG.getSetCC(dl, MVT::i1, CondLHS, getValue(CB.CmpRHS), CB.CC);
1665 assert(CB.CC == ISD::SETLE && "Can handle only LE ranges now");
1667 const APInt& Low = cast<ConstantInt>(CB.CmpLHS)->getValue();
1668 const APInt& High = cast<ConstantInt>(CB.CmpRHS)->getValue();
1670 SDValue CmpOp = getValue(CB.CmpMHS);
1671 EVT VT = CmpOp.getValueType();
1673 if (cast<ConstantInt>(CB.CmpLHS)->isMinValue(true)) {
1674 Cond = DAG.getSetCC(dl, MVT::i1, CmpOp, DAG.getConstant(High, dl, VT),
1677 SDValue SUB = DAG.getNode(ISD::SUB, dl,
1678 VT, CmpOp, DAG.getConstant(Low, dl, VT));
1679 Cond = DAG.getSetCC(dl, MVT::i1, SUB,
1680 DAG.getConstant(High-Low, dl, VT), ISD::SETULE);
1684 // Update successor info
1685 addSuccessorWithWeight(SwitchBB, CB.TrueBB, CB.TrueWeight);
1686 // TrueBB and FalseBB are always different unless the incoming IR is
1687 // degenerate. This only happens when running llc on weird IR.
1688 if (CB.TrueBB != CB.FalseBB)
1689 addSuccessorWithWeight(SwitchBB, CB.FalseBB, CB.FalseWeight);
1691 // If the lhs block is the next block, invert the condition so that we can
1692 // fall through to the lhs instead of the rhs block.
1693 if (CB.TrueBB == NextBlock(SwitchBB)) {
1694 std::swap(CB.TrueBB, CB.FalseBB);
1695 SDValue True = DAG.getConstant(1, dl, Cond.getValueType());
1696 Cond = DAG.getNode(ISD::XOR, dl, Cond.getValueType(), Cond, True);
1699 SDValue BrCond = DAG.getNode(ISD::BRCOND, dl,
1700 MVT::Other, getControlRoot(), Cond,
1701 DAG.getBasicBlock(CB.TrueBB));
1703 // Insert the false branch. Do this even if it's a fall through branch,
1704 // this makes it easier to do DAG optimizations which require inverting
1705 // the branch condition.
1706 BrCond = DAG.getNode(ISD::BR, dl, MVT::Other, BrCond,
1707 DAG.getBasicBlock(CB.FalseBB));
1709 DAG.setRoot(BrCond);
1712 /// visitJumpTable - Emit JumpTable node in the current MBB
1713 void SelectionDAGBuilder::visitJumpTable(JumpTable &JT) {
1714 // Emit the code for the jump table
1715 assert(JT.Reg != -1U && "Should lower JT Header first!");
1716 EVT PTy = DAG.getTargetLoweringInfo().getPointerTy(DAG.getDataLayout());
1717 SDValue Index = DAG.getCopyFromReg(getControlRoot(), getCurSDLoc(),
1719 SDValue Table = DAG.getJumpTable(JT.JTI, PTy);
1720 SDValue BrJumpTable = DAG.getNode(ISD::BR_JT, getCurSDLoc(),
1721 MVT::Other, Index.getValue(1),
1723 DAG.setRoot(BrJumpTable);
1726 /// visitJumpTableHeader - This function emits necessary code to produce index
1727 /// in the JumpTable from switch case.
1728 void SelectionDAGBuilder::visitJumpTableHeader(JumpTable &JT,
1729 JumpTableHeader &JTH,
1730 MachineBasicBlock *SwitchBB) {
1731 SDLoc dl = getCurSDLoc();
1733 // Subtract the lowest switch case value from the value being switched on and
1734 // conditional branch to default mbb if the result is greater than the
1735 // difference between smallest and largest cases.
1736 SDValue SwitchOp = getValue(JTH.SValue);
1737 EVT VT = SwitchOp.getValueType();
1738 SDValue Sub = DAG.getNode(ISD::SUB, dl, VT, SwitchOp,
1739 DAG.getConstant(JTH.First, dl, VT));
1741 // The SDNode we just created, which holds the value being switched on minus
1742 // the smallest case value, needs to be copied to a virtual register so it
1743 // can be used as an index into the jump table in a subsequent basic block.
1744 // This value may be smaller or larger than the target's pointer type, and
1745 // therefore require extension or truncating.
1746 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1747 SwitchOp = DAG.getZExtOrTrunc(Sub, dl, TLI.getPointerTy(DAG.getDataLayout()));
1749 unsigned JumpTableReg =
1750 FuncInfo.CreateReg(TLI.getPointerTy(DAG.getDataLayout()));
1751 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), dl,
1752 JumpTableReg, SwitchOp);
1753 JT.Reg = JumpTableReg;
1755 // Emit the range check for the jump table, and branch to the default block
1756 // for the switch statement if the value being switched on exceeds the largest
1757 // case in the switch.
1758 SDValue CMP = DAG.getSetCC(
1759 dl, TLI.getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(),
1760 Sub.getValueType()),
1761 Sub, DAG.getConstant(JTH.Last - JTH.First, dl, VT), ISD::SETUGT);
1763 SDValue BrCond = DAG.getNode(ISD::BRCOND, dl,
1764 MVT::Other, CopyTo, CMP,
1765 DAG.getBasicBlock(JT.Default));
1767 // Avoid emitting unnecessary branches to the next block.
1768 if (JT.MBB != NextBlock(SwitchBB))
1769 BrCond = DAG.getNode(ISD::BR, dl, MVT::Other, BrCond,
1770 DAG.getBasicBlock(JT.MBB));
1772 DAG.setRoot(BrCond);
1775 /// Codegen a new tail for a stack protector check ParentMBB which has had its
1776 /// tail spliced into a stack protector check success bb.
1778 /// For a high level explanation of how this fits into the stack protector
1779 /// generation see the comment on the declaration of class
1780 /// StackProtectorDescriptor.
1781 void SelectionDAGBuilder::visitSPDescriptorParent(StackProtectorDescriptor &SPD,
1782 MachineBasicBlock *ParentBB) {
1784 // First create the loads to the guard/stack slot for the comparison.
1785 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1786 EVT PtrTy = TLI.getPointerTy(DAG.getDataLayout());
1788 MachineFrameInfo *MFI = ParentBB->getParent()->getFrameInfo();
1789 int FI = MFI->getStackProtectorIndex();
1791 const Value *IRGuard = SPD.getGuard();
1792 SDValue GuardPtr = getValue(IRGuard);
1793 SDValue StackSlotPtr = DAG.getFrameIndex(FI, PtrTy);
1795 unsigned Align = DL->getPrefTypeAlignment(IRGuard->getType());
1798 SDLoc dl = getCurSDLoc();
1800 // If GuardReg is set and useLoadStackGuardNode returns true, retrieve the
1801 // guard value from the virtual register holding the value. Otherwise, emit a
1802 // volatile load to retrieve the stack guard value.
1803 unsigned GuardReg = SPD.getGuardReg();
1805 if (GuardReg && TLI.useLoadStackGuardNode())
1806 Guard = DAG.getCopyFromReg(DAG.getEntryNode(), dl, GuardReg,
1809 Guard = DAG.getLoad(PtrTy, dl, DAG.getEntryNode(),
1810 GuardPtr, MachinePointerInfo(IRGuard, 0),
1811 true, false, false, Align);
1813 SDValue StackSlot = DAG.getLoad(
1814 PtrTy, dl, DAG.getEntryNode(), StackSlotPtr,
1815 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI), true,
1816 false, false, Align);
1818 // Perform the comparison via a subtract/getsetcc.
1819 EVT VT = Guard.getValueType();
1820 SDValue Sub = DAG.getNode(ISD::SUB, dl, VT, Guard, StackSlot);
1822 SDValue Cmp = DAG.getSetCC(dl, TLI.getSetCCResultType(DAG.getDataLayout(),
1824 Sub.getValueType()),
1825 Sub, DAG.getConstant(0, dl, VT), ISD::SETNE);
1827 // If the sub is not 0, then we know the guard/stackslot do not equal, so
1828 // branch to failure MBB.
1829 SDValue BrCond = DAG.getNode(ISD::BRCOND, dl,
1830 MVT::Other, StackSlot.getOperand(0),
1831 Cmp, DAG.getBasicBlock(SPD.getFailureMBB()));
1832 // Otherwise branch to success MBB.
1833 SDValue Br = DAG.getNode(ISD::BR, dl,
1835 DAG.getBasicBlock(SPD.getSuccessMBB()));
1840 /// Codegen the failure basic block for a stack protector check.
1842 /// A failure stack protector machine basic block consists simply of a call to
1843 /// __stack_chk_fail().
1845 /// For a high level explanation of how this fits into the stack protector
1846 /// generation see the comment on the declaration of class
1847 /// StackProtectorDescriptor.
1849 SelectionDAGBuilder::visitSPDescriptorFailure(StackProtectorDescriptor &SPD) {
1850 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1852 TLI.makeLibCall(DAG, RTLIB::STACKPROTECTOR_CHECK_FAIL, MVT::isVoid,
1853 nullptr, 0, false, getCurSDLoc(), false, false).second;
1857 /// visitBitTestHeader - This function emits necessary code to produce value
1858 /// suitable for "bit tests"
1859 void SelectionDAGBuilder::visitBitTestHeader(BitTestBlock &B,
1860 MachineBasicBlock *SwitchBB) {
1861 SDLoc dl = getCurSDLoc();
1863 // Subtract the minimum value
1864 SDValue SwitchOp = getValue(B.SValue);
1865 EVT VT = SwitchOp.getValueType();
1866 SDValue Sub = DAG.getNode(ISD::SUB, dl, VT, SwitchOp,
1867 DAG.getConstant(B.First, dl, VT));
1870 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1871 SDValue RangeCmp = DAG.getSetCC(
1872 dl, TLI.getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(),
1873 Sub.getValueType()),
1874 Sub, DAG.getConstant(B.Range, dl, VT), ISD::SETUGT);
1876 // Determine the type of the test operands.
1877 bool UsePtrType = false;
1878 if (!TLI.isTypeLegal(VT))
1881 for (unsigned i = 0, e = B.Cases.size(); i != e; ++i)
1882 if (!isUIntN(VT.getSizeInBits(), B.Cases[i].Mask)) {
1883 // Switch table case range are encoded into series of masks.
1884 // Just use pointer type, it's guaranteed to fit.
1890 VT = TLI.getPointerTy(DAG.getDataLayout());
1891 Sub = DAG.getZExtOrTrunc(Sub, dl, VT);
1894 B.RegVT = VT.getSimpleVT();
1895 B.Reg = FuncInfo.CreateReg(B.RegVT);
1896 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), dl, B.Reg, Sub);
1898 MachineBasicBlock* MBB = B.Cases[0].ThisBB;
1900 uint32_t DefaultWeight = getEdgeWeight(SwitchBB, B.Default);
1901 addSuccessorWithWeight(SwitchBB, B.Default, DefaultWeight);
1902 addSuccessorWithWeight(SwitchBB, MBB, B.Weight);
1904 SDValue BrRange = DAG.getNode(ISD::BRCOND, dl,
1905 MVT::Other, CopyTo, RangeCmp,
1906 DAG.getBasicBlock(B.Default));
1908 // Avoid emitting unnecessary branches to the next block.
1909 if (MBB != NextBlock(SwitchBB))
1910 BrRange = DAG.getNode(ISD::BR, dl, MVT::Other, BrRange,
1911 DAG.getBasicBlock(MBB));
1913 DAG.setRoot(BrRange);
1916 /// visitBitTestCase - this function produces one "bit test"
1917 void SelectionDAGBuilder::visitBitTestCase(BitTestBlock &BB,
1918 MachineBasicBlock* NextMBB,
1919 uint32_t BranchWeightToNext,
1922 MachineBasicBlock *SwitchBB) {
1923 SDLoc dl = getCurSDLoc();
1925 SDValue ShiftOp = DAG.getCopyFromReg(getControlRoot(), dl, Reg, VT);
1927 unsigned PopCount = countPopulation(B.Mask);
1928 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1929 if (PopCount == 1) {
1930 // Testing for a single bit; just compare the shift count with what it
1931 // would need to be to shift a 1 bit in that position.
1933 dl, TLI.getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT),
1934 ShiftOp, DAG.getConstant(countTrailingZeros(B.Mask), dl, VT),
1936 } else if (PopCount == BB.Range) {
1937 // There is only one zero bit in the range, test for it directly.
1939 dl, TLI.getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT),
1940 ShiftOp, DAG.getConstant(countTrailingOnes(B.Mask), dl, VT),
1943 // Make desired shift
1944 SDValue SwitchVal = DAG.getNode(ISD::SHL, dl, VT,
1945 DAG.getConstant(1, dl, VT), ShiftOp);
1947 // Emit bit tests and jumps
1948 SDValue AndOp = DAG.getNode(ISD::AND, dl,
1949 VT, SwitchVal, DAG.getConstant(B.Mask, dl, VT));
1951 dl, TLI.getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT),
1952 AndOp, DAG.getConstant(0, dl, VT), ISD::SETNE);
1955 // The branch weight from SwitchBB to B.TargetBB is B.ExtraWeight.
1956 addSuccessorWithWeight(SwitchBB, B.TargetBB, B.ExtraWeight);
1957 // The branch weight from SwitchBB to NextMBB is BranchWeightToNext.
1958 addSuccessorWithWeight(SwitchBB, NextMBB, BranchWeightToNext);
1960 SDValue BrAnd = DAG.getNode(ISD::BRCOND, dl,
1961 MVT::Other, getControlRoot(),
1962 Cmp, DAG.getBasicBlock(B.TargetBB));
1964 // Avoid emitting unnecessary branches to the next block.
1965 if (NextMBB != NextBlock(SwitchBB))
1966 BrAnd = DAG.getNode(ISD::BR, dl, MVT::Other, BrAnd,
1967 DAG.getBasicBlock(NextMBB));
1972 void SelectionDAGBuilder::visitInvoke(const InvokeInst &I) {
1973 MachineBasicBlock *InvokeMBB = FuncInfo.MBB;
1975 // Retrieve successors.
1976 MachineBasicBlock *Return = FuncInfo.MBBMap[I.getSuccessor(0)];
1977 MachineBasicBlock *LandingPad = FuncInfo.MBBMap[I.getSuccessor(1)];
1979 const Value *Callee(I.getCalledValue());
1980 const Function *Fn = dyn_cast<Function>(Callee);
1981 if (isa<InlineAsm>(Callee))
1983 else if (Fn && Fn->isIntrinsic()) {
1984 switch (Fn->getIntrinsicID()) {
1986 llvm_unreachable("Cannot invoke this intrinsic");
1987 case Intrinsic::donothing:
1988 // Ignore invokes to @llvm.donothing: jump directly to the next BB.
1990 case Intrinsic::experimental_patchpoint_void:
1991 case Intrinsic::experimental_patchpoint_i64:
1992 visitPatchpoint(&I, LandingPad);
1994 case Intrinsic::experimental_gc_statepoint:
1995 LowerStatepoint(ImmutableStatepoint(&I), LandingPad);
1999 LowerCallTo(&I, getValue(Callee), false, LandingPad);
2001 // If the value of the invoke is used outside of its defining block, make it
2002 // available as a virtual register.
2003 // We already took care of the exported value for the statepoint instruction
2004 // during call to the LowerStatepoint.
2005 if (!isStatepoint(I)) {
2006 CopyToExportRegsIfNeeded(&I);
2009 // Update successor info
2010 addSuccessorWithWeight(InvokeMBB, Return);
2011 addSuccessorWithWeight(InvokeMBB, LandingPad);
2013 // Drop into normal successor.
2014 DAG.setRoot(DAG.getNode(ISD::BR, getCurSDLoc(),
2015 MVT::Other, getControlRoot(),
2016 DAG.getBasicBlock(Return)));
2019 void SelectionDAGBuilder::visitResume(const ResumeInst &RI) {
2020 llvm_unreachable("SelectionDAGBuilder shouldn't visit resume instructions!");
2023 void SelectionDAGBuilder::visitLandingPad(const LandingPadInst &LP) {
2024 assert(FuncInfo.MBB->isLandingPad() &&
2025 "Call to landingpad not in landing pad!");
2027 MachineBasicBlock *MBB = FuncInfo.MBB;
2028 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
2029 AddLandingPadInfo(LP, MMI, MBB);
2031 // If there aren't registers to copy the values into (e.g., during SjLj
2032 // exceptions), then don't bother to create these DAG nodes.
2033 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2034 if (TLI.getExceptionPointerRegister() == 0 &&
2035 TLI.getExceptionSelectorRegister() == 0)
2038 SmallVector<EVT, 2> ValueVTs;
2039 SDLoc dl = getCurSDLoc();
2040 ComputeValueVTs(TLI, DAG.getDataLayout(), LP.getType(), ValueVTs);
2041 assert(ValueVTs.size() == 2 && "Only two-valued landingpads are supported");
2043 // Get the two live-in registers as SDValues. The physregs have already been
2044 // copied into virtual registers.
2046 if (FuncInfo.ExceptionPointerVirtReg) {
2047 Ops[0] = DAG.getZExtOrTrunc(
2048 DAG.getCopyFromReg(DAG.getEntryNode(), dl,
2049 FuncInfo.ExceptionPointerVirtReg,
2050 TLI.getPointerTy(DAG.getDataLayout())),
2053 Ops[0] = DAG.getConstant(0, dl, TLI.getPointerTy(DAG.getDataLayout()));
2055 Ops[1] = DAG.getZExtOrTrunc(
2056 DAG.getCopyFromReg(DAG.getEntryNode(), dl,
2057 FuncInfo.ExceptionSelectorVirtReg,
2058 TLI.getPointerTy(DAG.getDataLayout())),
2062 SDValue Res = DAG.getNode(ISD::MERGE_VALUES, dl,
2063 DAG.getVTList(ValueVTs), Ops);
2067 void SelectionDAGBuilder::sortAndRangeify(CaseClusterVector &Clusters) {
2069 for (const CaseCluster &CC : Clusters)
2070 assert(CC.Low == CC.High && "Input clusters must be single-case");
2073 std::sort(Clusters.begin(), Clusters.end(),
2074 [](const CaseCluster &a, const CaseCluster &b) {
2075 return a.Low->getValue().slt(b.Low->getValue());
2078 // Merge adjacent clusters with the same destination.
2079 const unsigned N = Clusters.size();
2080 unsigned DstIndex = 0;
2081 for (unsigned SrcIndex = 0; SrcIndex < N; ++SrcIndex) {
2082 CaseCluster &CC = Clusters[SrcIndex];
2083 const ConstantInt *CaseVal = CC.Low;
2084 MachineBasicBlock *Succ = CC.MBB;
2086 if (DstIndex != 0 && Clusters[DstIndex - 1].MBB == Succ &&
2087 (CaseVal->getValue() - Clusters[DstIndex - 1].High->getValue()) == 1) {
2088 // If this case has the same successor and is a neighbour, merge it into
2089 // the previous cluster.
2090 Clusters[DstIndex - 1].High = CaseVal;
2091 Clusters[DstIndex - 1].Weight += CC.Weight;
2092 assert(Clusters[DstIndex - 1].Weight >= CC.Weight && "Weight overflow!");
2094 std::memmove(&Clusters[DstIndex++], &Clusters[SrcIndex],
2095 sizeof(Clusters[SrcIndex]));
2098 Clusters.resize(DstIndex);
2101 void SelectionDAGBuilder::UpdateSplitBlock(MachineBasicBlock *First,
2102 MachineBasicBlock *Last) {
2104 for (unsigned i = 0, e = JTCases.size(); i != e; ++i)
2105 if (JTCases[i].first.HeaderBB == First)
2106 JTCases[i].first.HeaderBB = Last;
2108 // Update BitTestCases.
2109 for (unsigned i = 0, e = BitTestCases.size(); i != e; ++i)
2110 if (BitTestCases[i].Parent == First)
2111 BitTestCases[i].Parent = Last;
2114 void SelectionDAGBuilder::visitIndirectBr(const IndirectBrInst &I) {
2115 MachineBasicBlock *IndirectBrMBB = FuncInfo.MBB;
2117 // Update machine-CFG edges with unique successors.
2118 SmallSet<BasicBlock*, 32> Done;
2119 for (unsigned i = 0, e = I.getNumSuccessors(); i != e; ++i) {
2120 BasicBlock *BB = I.getSuccessor(i);
2121 bool Inserted = Done.insert(BB).second;
2125 MachineBasicBlock *Succ = FuncInfo.MBBMap[BB];
2126 addSuccessorWithWeight(IndirectBrMBB, Succ);
2129 DAG.setRoot(DAG.getNode(ISD::BRIND, getCurSDLoc(),
2130 MVT::Other, getControlRoot(),
2131 getValue(I.getAddress())));
2134 void SelectionDAGBuilder::visitUnreachable(const UnreachableInst &I) {
2135 if (DAG.getTarget().Options.TrapUnreachable)
2136 DAG.setRoot(DAG.getNode(ISD::TRAP, getCurSDLoc(), MVT::Other, DAG.getRoot()));
2139 void SelectionDAGBuilder::visitFSub(const User &I) {
2140 // -0.0 - X --> fneg
2141 Type *Ty = I.getType();
2142 if (isa<Constant>(I.getOperand(0)) &&
2143 I.getOperand(0) == ConstantFP::getZeroValueForNegation(Ty)) {
2144 SDValue Op2 = getValue(I.getOperand(1));
2145 setValue(&I, DAG.getNode(ISD::FNEG, getCurSDLoc(),
2146 Op2.getValueType(), Op2));
2150 visitBinary(I, ISD::FSUB);
2153 void SelectionDAGBuilder::visitBinary(const User &I, unsigned OpCode) {
2154 SDValue Op1 = getValue(I.getOperand(0));
2155 SDValue Op2 = getValue(I.getOperand(1));
2162 if (const OverflowingBinaryOperator *OFBinOp =
2163 dyn_cast<const OverflowingBinaryOperator>(&I)) {
2164 nuw = OFBinOp->hasNoUnsignedWrap();
2165 nsw = OFBinOp->hasNoSignedWrap();
2167 if (const PossiblyExactOperator *ExactOp =
2168 dyn_cast<const PossiblyExactOperator>(&I))
2169 exact = ExactOp->isExact();
2170 if (const FPMathOperator *FPOp = dyn_cast<const FPMathOperator>(&I))
2171 FMF = FPOp->getFastMathFlags();
2174 Flags.setExact(exact);
2175 Flags.setNoSignedWrap(nsw);
2176 Flags.setNoUnsignedWrap(nuw);
2177 if (EnableFMFInDAG) {
2178 Flags.setAllowReciprocal(FMF.allowReciprocal());
2179 Flags.setNoInfs(FMF.noInfs());
2180 Flags.setNoNaNs(FMF.noNaNs());
2181 Flags.setNoSignedZeros(FMF.noSignedZeros());
2182 Flags.setUnsafeAlgebra(FMF.unsafeAlgebra());
2184 SDValue BinNodeValue = DAG.getNode(OpCode, getCurSDLoc(), Op1.getValueType(),
2186 setValue(&I, BinNodeValue);
2189 void SelectionDAGBuilder::visitShift(const User &I, unsigned Opcode) {
2190 SDValue Op1 = getValue(I.getOperand(0));
2191 SDValue Op2 = getValue(I.getOperand(1));
2193 EVT ShiftTy = DAG.getTargetLoweringInfo().getShiftAmountTy(
2194 Op2.getValueType(), DAG.getDataLayout());
2196 // Coerce the shift amount to the right type if we can.
2197 if (!I.getType()->isVectorTy() && Op2.getValueType() != ShiftTy) {
2198 unsigned ShiftSize = ShiftTy.getSizeInBits();
2199 unsigned Op2Size = Op2.getValueType().getSizeInBits();
2200 SDLoc DL = getCurSDLoc();
2202 // If the operand is smaller than the shift count type, promote it.
2203 if (ShiftSize > Op2Size)
2204 Op2 = DAG.getNode(ISD::ZERO_EXTEND, DL, ShiftTy, Op2);
2206 // If the operand is larger than the shift count type but the shift
2207 // count type has enough bits to represent any shift value, truncate
2208 // it now. This is a common case and it exposes the truncate to
2209 // optimization early.
2210 else if (ShiftSize >= Log2_32_Ceil(Op2.getValueType().getSizeInBits()))
2211 Op2 = DAG.getNode(ISD::TRUNCATE, DL, ShiftTy, Op2);
2212 // Otherwise we'll need to temporarily settle for some other convenient
2213 // type. Type legalization will make adjustments once the shiftee is split.
2215 Op2 = DAG.getZExtOrTrunc(Op2, DL, MVT::i32);
2222 if (Opcode == ISD::SRL || Opcode == ISD::SRA || Opcode == ISD::SHL) {
2224 if (const OverflowingBinaryOperator *OFBinOp =
2225 dyn_cast<const OverflowingBinaryOperator>(&I)) {
2226 nuw = OFBinOp->hasNoUnsignedWrap();
2227 nsw = OFBinOp->hasNoSignedWrap();
2229 if (const PossiblyExactOperator *ExactOp =
2230 dyn_cast<const PossiblyExactOperator>(&I))
2231 exact = ExactOp->isExact();
2234 Flags.setExact(exact);
2235 Flags.setNoSignedWrap(nsw);
2236 Flags.setNoUnsignedWrap(nuw);
2237 SDValue Res = DAG.getNode(Opcode, getCurSDLoc(), Op1.getValueType(), Op1, Op2,
2242 void SelectionDAGBuilder::visitSDiv(const User &I) {
2243 SDValue Op1 = getValue(I.getOperand(0));
2244 SDValue Op2 = getValue(I.getOperand(1));
2247 Flags.setExact(isa<PossiblyExactOperator>(&I) &&
2248 cast<PossiblyExactOperator>(&I)->isExact());
2249 setValue(&I, DAG.getNode(ISD::SDIV, getCurSDLoc(), Op1.getValueType(), Op1,
2253 void SelectionDAGBuilder::visitICmp(const User &I) {
2254 ICmpInst::Predicate predicate = ICmpInst::BAD_ICMP_PREDICATE;
2255 if (const ICmpInst *IC = dyn_cast<ICmpInst>(&I))
2256 predicate = IC->getPredicate();
2257 else if (const ConstantExpr *IC = dyn_cast<ConstantExpr>(&I))
2258 predicate = ICmpInst::Predicate(IC->getPredicate());
2259 SDValue Op1 = getValue(I.getOperand(0));
2260 SDValue Op2 = getValue(I.getOperand(1));
2261 ISD::CondCode Opcode = getICmpCondCode(predicate);
2263 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2265 setValue(&I, DAG.getSetCC(getCurSDLoc(), DestVT, Op1, Op2, Opcode));
2268 void SelectionDAGBuilder::visitFCmp(const User &I) {
2269 FCmpInst::Predicate predicate = FCmpInst::BAD_FCMP_PREDICATE;
2270 if (const FCmpInst *FC = dyn_cast<FCmpInst>(&I))
2271 predicate = FC->getPredicate();
2272 else if (const ConstantExpr *FC = dyn_cast<ConstantExpr>(&I))
2273 predicate = FCmpInst::Predicate(FC->getPredicate());
2274 SDValue Op1 = getValue(I.getOperand(0));
2275 SDValue Op2 = getValue(I.getOperand(1));
2276 ISD::CondCode Condition = getFCmpCondCode(predicate);
2277 if (TM.Options.NoNaNsFPMath)
2278 Condition = getFCmpCodeWithoutNaN(Condition);
2279 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2281 setValue(&I, DAG.getSetCC(getCurSDLoc(), DestVT, Op1, Op2, Condition));
2284 void SelectionDAGBuilder::visitSelect(const User &I) {
2285 SmallVector<EVT, 4> ValueVTs;
2286 ComputeValueVTs(DAG.getTargetLoweringInfo(), DAG.getDataLayout(), I.getType(),
2288 unsigned NumValues = ValueVTs.size();
2289 if (NumValues == 0) return;
2291 SmallVector<SDValue, 4> Values(NumValues);
2292 SDValue Cond = getValue(I.getOperand(0));
2293 SDValue LHSVal = getValue(I.getOperand(1));
2294 SDValue RHSVal = getValue(I.getOperand(2));
2295 auto BaseOps = {Cond};
2296 ISD::NodeType OpCode = Cond.getValueType().isVector() ?
2297 ISD::VSELECT : ISD::SELECT;
2299 // Min/max matching is only viable if all output VTs are the same.
2300 if (std::equal(ValueVTs.begin(), ValueVTs.end(), ValueVTs.begin())) {
2301 EVT VT = ValueVTs[0];
2302 LLVMContext &Ctx = *DAG.getContext();
2303 auto &TLI = DAG.getTargetLoweringInfo();
2304 while (TLI.getTypeAction(Ctx, VT) == TargetLoweringBase::TypeSplitVector)
2305 VT = TLI.getTypeToTransformTo(Ctx, VT);
2308 auto SPR = matchSelectPattern(const_cast<User*>(&I), LHS, RHS);
2309 ISD::NodeType Opc = ISD::DELETED_NODE;
2310 switch (SPR.Flavor) {
2311 case SPF_UMAX: Opc = ISD::UMAX; break;
2312 case SPF_UMIN: Opc = ISD::UMIN; break;
2313 case SPF_SMAX: Opc = ISD::SMAX; break;
2314 case SPF_SMIN: Opc = ISD::SMIN; break;
2316 switch (SPR.NaNBehavior) {
2317 case SPNB_NA: llvm_unreachable("No NaN behavior for FP op?");
2318 case SPNB_RETURNS_NAN: Opc = ISD::FMINNAN; break;
2319 case SPNB_RETURNS_OTHER: Opc = ISD::FMINNUM; break;
2320 case SPNB_RETURNS_ANY:
2321 Opc = TLI.isOperationLegalOrCustom(ISD::FMINNUM, VT) ? ISD::FMINNUM
2327 switch (SPR.NaNBehavior) {
2328 case SPNB_NA: llvm_unreachable("No NaN behavior for FP op?");
2329 case SPNB_RETURNS_NAN: Opc = ISD::FMAXNAN; break;
2330 case SPNB_RETURNS_OTHER: Opc = ISD::FMAXNUM; break;
2331 case SPNB_RETURNS_ANY:
2332 Opc = TLI.isOperationLegalOrCustom(ISD::FMAXNUM, VT) ? ISD::FMAXNUM
2340 if (Opc != ISD::DELETED_NODE && TLI.isOperationLegalOrCustom(Opc, VT) &&
2341 // If the underlying comparison instruction is used by any other instruction,
2342 // the consumed instructions won't be destroyed, so it is not profitable
2343 // to convert to a min/max.
2344 cast<SelectInst>(&I)->getCondition()->hasOneUse()) {
2346 LHSVal = getValue(LHS);
2347 RHSVal = getValue(RHS);
2352 for (unsigned i = 0; i != NumValues; ++i) {
2353 SmallVector<SDValue, 3> Ops(BaseOps.begin(), BaseOps.end());
2354 Ops.push_back(SDValue(LHSVal.getNode(), LHSVal.getResNo() + i));
2355 Ops.push_back(SDValue(RHSVal.getNode(), RHSVal.getResNo() + i));
2356 Values[i] = DAG.getNode(OpCode, getCurSDLoc(),
2357 LHSVal.getNode()->getValueType(LHSVal.getResNo()+i),
2361 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(),
2362 DAG.getVTList(ValueVTs), Values));
2365 void SelectionDAGBuilder::visitTrunc(const User &I) {
2366 // TruncInst cannot be a no-op cast because sizeof(src) > sizeof(dest).
2367 SDValue N = getValue(I.getOperand(0));
2368 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2370 setValue(&I, DAG.getNode(ISD::TRUNCATE, getCurSDLoc(), DestVT, N));
2373 void SelectionDAGBuilder::visitZExt(const User &I) {
2374 // ZExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
2375 // ZExt also can't be a cast to bool for same reason. So, nothing much to do
2376 SDValue N = getValue(I.getOperand(0));
2377 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2379 setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, getCurSDLoc(), DestVT, N));
2382 void SelectionDAGBuilder::visitSExt(const User &I) {
2383 // SExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
2384 // SExt also can't be a cast to bool for same reason. So, nothing much to do
2385 SDValue N = getValue(I.getOperand(0));
2386 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2388 setValue(&I, DAG.getNode(ISD::SIGN_EXTEND, getCurSDLoc(), DestVT, N));
2391 void SelectionDAGBuilder::visitFPTrunc(const User &I) {
2392 // FPTrunc is never a no-op cast, no need to check
2393 SDValue N = getValue(I.getOperand(0));
2394 SDLoc dl = getCurSDLoc();
2395 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2396 EVT DestVT = TLI.getValueType(DAG.getDataLayout(), I.getType());
2397 setValue(&I, DAG.getNode(ISD::FP_ROUND, dl, DestVT, N,
2398 DAG.getTargetConstant(
2399 0, dl, TLI.getPointerTy(DAG.getDataLayout()))));
2402 void SelectionDAGBuilder::visitFPExt(const User &I) {
2403 // FPExt is never a no-op cast, no need to check
2404 SDValue N = getValue(I.getOperand(0));
2405 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2407 setValue(&I, DAG.getNode(ISD::FP_EXTEND, getCurSDLoc(), DestVT, N));
2410 void SelectionDAGBuilder::visitFPToUI(const User &I) {
2411 // FPToUI is never a no-op cast, no need to check
2412 SDValue N = getValue(I.getOperand(0));
2413 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2415 setValue(&I, DAG.getNode(ISD::FP_TO_UINT, getCurSDLoc(), DestVT, N));
2418 void SelectionDAGBuilder::visitFPToSI(const User &I) {
2419 // FPToSI is never a no-op cast, no need to check
2420 SDValue N = getValue(I.getOperand(0));
2421 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2423 setValue(&I, DAG.getNode(ISD::FP_TO_SINT, getCurSDLoc(), DestVT, N));
2426 void SelectionDAGBuilder::visitUIToFP(const User &I) {
2427 // UIToFP is never a no-op cast, no need to check
2428 SDValue N = getValue(I.getOperand(0));
2429 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2431 setValue(&I, DAG.getNode(ISD::UINT_TO_FP, getCurSDLoc(), DestVT, N));
2434 void SelectionDAGBuilder::visitSIToFP(const User &I) {
2435 // SIToFP is never a no-op cast, no need to check
2436 SDValue N = getValue(I.getOperand(0));
2437 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2439 setValue(&I, DAG.getNode(ISD::SINT_TO_FP, getCurSDLoc(), DestVT, N));
2442 void SelectionDAGBuilder::visitPtrToInt(const User &I) {
2443 // What to do depends on the size of the integer and the size of the pointer.
2444 // We can either truncate, zero extend, or no-op, accordingly.
2445 SDValue N = getValue(I.getOperand(0));
2446 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2448 setValue(&I, DAG.getZExtOrTrunc(N, getCurSDLoc(), DestVT));
2451 void SelectionDAGBuilder::visitIntToPtr(const User &I) {
2452 // What to do depends on the size of the integer and the size of the pointer.
2453 // We can either truncate, zero extend, or no-op, accordingly.
2454 SDValue N = getValue(I.getOperand(0));
2455 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2457 setValue(&I, DAG.getZExtOrTrunc(N, getCurSDLoc(), DestVT));
2460 void SelectionDAGBuilder::visitBitCast(const User &I) {
2461 SDValue N = getValue(I.getOperand(0));
2462 SDLoc dl = getCurSDLoc();
2463 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2466 // BitCast assures us that source and destination are the same size so this is
2467 // either a BITCAST or a no-op.
2468 if (DestVT != N.getValueType())
2469 setValue(&I, DAG.getNode(ISD::BITCAST, dl,
2470 DestVT, N)); // convert types.
2471 // Check if the original LLVM IR Operand was a ConstantInt, because getValue()
2472 // might fold any kind of constant expression to an integer constant and that
2473 // is not what we are looking for. Only regcognize a bitcast of a genuine
2474 // constant integer as an opaque constant.
2475 else if(ConstantInt *C = dyn_cast<ConstantInt>(I.getOperand(0)))
2476 setValue(&I, DAG.getConstant(C->getValue(), dl, DestVT, /*isTarget=*/false,
2479 setValue(&I, N); // noop cast.
2482 void SelectionDAGBuilder::visitAddrSpaceCast(const User &I) {
2483 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2484 const Value *SV = I.getOperand(0);
2485 SDValue N = getValue(SV);
2486 EVT DestVT = TLI.getValueType(DAG.getDataLayout(), I.getType());
2488 unsigned SrcAS = SV->getType()->getPointerAddressSpace();
2489 unsigned DestAS = I.getType()->getPointerAddressSpace();
2491 if (!TLI.isNoopAddrSpaceCast(SrcAS, DestAS))
2492 N = DAG.getAddrSpaceCast(getCurSDLoc(), DestVT, N, SrcAS, DestAS);
2497 void SelectionDAGBuilder::visitInsertElement(const User &I) {
2498 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2499 SDValue InVec = getValue(I.getOperand(0));
2500 SDValue InVal = getValue(I.getOperand(1));
2501 SDValue InIdx = DAG.getSExtOrTrunc(getValue(I.getOperand(2)), getCurSDLoc(),
2502 TLI.getVectorIdxTy(DAG.getDataLayout()));
2503 setValue(&I, DAG.getNode(ISD::INSERT_VECTOR_ELT, getCurSDLoc(),
2504 TLI.getValueType(DAG.getDataLayout(), I.getType()),
2505 InVec, InVal, InIdx));
2508 void SelectionDAGBuilder::visitExtractElement(const User &I) {
2509 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2510 SDValue InVec = getValue(I.getOperand(0));
2511 SDValue InIdx = DAG.getSExtOrTrunc(getValue(I.getOperand(1)), getCurSDLoc(),
2512 TLI.getVectorIdxTy(DAG.getDataLayout()));
2513 setValue(&I, DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurSDLoc(),
2514 TLI.getValueType(DAG.getDataLayout(), I.getType()),
2518 // Utility for visitShuffleVector - Return true if every element in Mask,
2519 // beginning from position Pos and ending in Pos+Size, falls within the
2520 // specified sequential range [L, L+Pos). or is undef.
2521 static bool isSequentialInRange(const SmallVectorImpl<int> &Mask,
2522 unsigned Pos, unsigned Size, int Low) {
2523 for (unsigned i = Pos, e = Pos+Size; i != e; ++i, ++Low)
2524 if (Mask[i] >= 0 && Mask[i] != Low)
2529 void SelectionDAGBuilder::visitShuffleVector(const User &I) {
2530 SDValue Src1 = getValue(I.getOperand(0));
2531 SDValue Src2 = getValue(I.getOperand(1));
2533 SmallVector<int, 8> Mask;
2534 ShuffleVectorInst::getShuffleMask(cast<Constant>(I.getOperand(2)), Mask);
2535 unsigned MaskNumElts = Mask.size();
2537 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2538 EVT VT = TLI.getValueType(DAG.getDataLayout(), I.getType());
2539 EVT SrcVT = Src1.getValueType();
2540 unsigned SrcNumElts = SrcVT.getVectorNumElements();
2542 if (SrcNumElts == MaskNumElts) {
2543 setValue(&I, DAG.getVectorShuffle(VT, getCurSDLoc(), Src1, Src2,
2548 // Normalize the shuffle vector since mask and vector length don't match.
2549 if (SrcNumElts < MaskNumElts && MaskNumElts % SrcNumElts == 0) {
2550 // Mask is longer than the source vectors and is a multiple of the source
2551 // vectors. We can use concatenate vector to make the mask and vectors
2553 if (SrcNumElts*2 == MaskNumElts) {
2554 // First check for Src1 in low and Src2 in high
2555 if (isSequentialInRange(Mask, 0, SrcNumElts, 0) &&
2556 isSequentialInRange(Mask, SrcNumElts, SrcNumElts, SrcNumElts)) {
2557 // The shuffle is concatenating two vectors together.
2558 setValue(&I, DAG.getNode(ISD::CONCAT_VECTORS, getCurSDLoc(),
2562 // Then check for Src2 in low and Src1 in high
2563 if (isSequentialInRange(Mask, 0, SrcNumElts, SrcNumElts) &&
2564 isSequentialInRange(Mask, SrcNumElts, SrcNumElts, 0)) {
2565 // The shuffle is concatenating two vectors together.
2566 setValue(&I, DAG.getNode(ISD::CONCAT_VECTORS, getCurSDLoc(),
2572 // Pad both vectors with undefs to make them the same length as the mask.
2573 unsigned NumConcat = MaskNumElts / SrcNumElts;
2574 bool Src1U = Src1.getOpcode() == ISD::UNDEF;
2575 bool Src2U = Src2.getOpcode() == ISD::UNDEF;
2576 SDValue UndefVal = DAG.getUNDEF(SrcVT);
2578 SmallVector<SDValue, 8> MOps1(NumConcat, UndefVal);
2579 SmallVector<SDValue, 8> MOps2(NumConcat, UndefVal);
2583 Src1 = Src1U ? DAG.getUNDEF(VT) : DAG.getNode(ISD::CONCAT_VECTORS,
2584 getCurSDLoc(), VT, MOps1);
2585 Src2 = Src2U ? DAG.getUNDEF(VT) : DAG.getNode(ISD::CONCAT_VECTORS,
2586 getCurSDLoc(), VT, MOps2);
2588 // Readjust mask for new input vector length.
2589 SmallVector<int, 8> MappedOps;
2590 for (unsigned i = 0; i != MaskNumElts; ++i) {
2592 if (Idx >= (int)SrcNumElts)
2593 Idx -= SrcNumElts - MaskNumElts;
2594 MappedOps.push_back(Idx);
2597 setValue(&I, DAG.getVectorShuffle(VT, getCurSDLoc(), Src1, Src2,
2602 if (SrcNumElts > MaskNumElts) {
2603 // Analyze the access pattern of the vector to see if we can extract
2604 // two subvectors and do the shuffle. The analysis is done by calculating
2605 // the range of elements the mask access on both vectors.
2606 int MinRange[2] = { static_cast<int>(SrcNumElts),
2607 static_cast<int>(SrcNumElts)};
2608 int MaxRange[2] = {-1, -1};
2610 for (unsigned i = 0; i != MaskNumElts; ++i) {
2616 if (Idx >= (int)SrcNumElts) {
2620 if (Idx > MaxRange[Input])
2621 MaxRange[Input] = Idx;
2622 if (Idx < MinRange[Input])
2623 MinRange[Input] = Idx;
2626 // Check if the access is smaller than the vector size and can we find
2627 // a reasonable extract index.
2628 int RangeUse[2] = { -1, -1 }; // 0 = Unused, 1 = Extract, -1 = Can not
2630 int StartIdx[2]; // StartIdx to extract from
2631 for (unsigned Input = 0; Input < 2; ++Input) {
2632 if (MinRange[Input] >= (int)SrcNumElts && MaxRange[Input] < 0) {
2633 RangeUse[Input] = 0; // Unused
2634 StartIdx[Input] = 0;
2638 // Find a good start index that is a multiple of the mask length. Then
2639 // see if the rest of the elements are in range.
2640 StartIdx[Input] = (MinRange[Input]/MaskNumElts)*MaskNumElts;
2641 if (MaxRange[Input] - StartIdx[Input] < (int)MaskNumElts &&
2642 StartIdx[Input] + MaskNumElts <= SrcNumElts)
2643 RangeUse[Input] = 1; // Extract from a multiple of the mask length.
2646 if (RangeUse[0] == 0 && RangeUse[1] == 0) {
2647 setValue(&I, DAG.getUNDEF(VT)); // Vectors are not used.
2650 if (RangeUse[0] >= 0 && RangeUse[1] >= 0) {
2651 // Extract appropriate subvector and generate a vector shuffle
2652 for (unsigned Input = 0; Input < 2; ++Input) {
2653 SDValue &Src = Input == 0 ? Src1 : Src2;
2654 if (RangeUse[Input] == 0)
2655 Src = DAG.getUNDEF(VT);
2657 SDLoc dl = getCurSDLoc();
2659 ISD::EXTRACT_SUBVECTOR, dl, VT, Src,
2660 DAG.getConstant(StartIdx[Input], dl,
2661 TLI.getVectorIdxTy(DAG.getDataLayout())));
2665 // Calculate new mask.
2666 SmallVector<int, 8> MappedOps;
2667 for (unsigned i = 0; i != MaskNumElts; ++i) {
2670 if (Idx < (int)SrcNumElts)
2673 Idx -= SrcNumElts + StartIdx[1] - MaskNumElts;
2675 MappedOps.push_back(Idx);
2678 setValue(&I, DAG.getVectorShuffle(VT, getCurSDLoc(), Src1, Src2,
2684 // We can't use either concat vectors or extract subvectors so fall back to
2685 // replacing the shuffle with extract and build vector.
2686 // to insert and build vector.
2687 EVT EltVT = VT.getVectorElementType();
2688 EVT IdxVT = TLI.getVectorIdxTy(DAG.getDataLayout());
2689 SDLoc dl = getCurSDLoc();
2690 SmallVector<SDValue,8> Ops;
2691 for (unsigned i = 0; i != MaskNumElts; ++i) {
2696 Res = DAG.getUNDEF(EltVT);
2698 SDValue &Src = Idx < (int)SrcNumElts ? Src1 : Src2;
2699 if (Idx >= (int)SrcNumElts) Idx -= SrcNumElts;
2701 Res = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
2702 EltVT, Src, DAG.getConstant(Idx, dl, IdxVT));
2708 setValue(&I, DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops));
2711 void SelectionDAGBuilder::visitInsertValue(const InsertValueInst &I) {
2712 const Value *Op0 = I.getOperand(0);
2713 const Value *Op1 = I.getOperand(1);
2714 Type *AggTy = I.getType();
2715 Type *ValTy = Op1->getType();
2716 bool IntoUndef = isa<UndefValue>(Op0);
2717 bool FromUndef = isa<UndefValue>(Op1);
2719 unsigned LinearIndex = ComputeLinearIndex(AggTy, I.getIndices());
2721 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2722 SmallVector<EVT, 4> AggValueVTs;
2723 ComputeValueVTs(TLI, DAG.getDataLayout(), AggTy, AggValueVTs);
2724 SmallVector<EVT, 4> ValValueVTs;
2725 ComputeValueVTs(TLI, DAG.getDataLayout(), ValTy, ValValueVTs);
2727 unsigned NumAggValues = AggValueVTs.size();
2728 unsigned NumValValues = ValValueVTs.size();
2729 SmallVector<SDValue, 4> Values(NumAggValues);
2731 // Ignore an insertvalue that produces an empty object
2732 if (!NumAggValues) {
2733 setValue(&I, DAG.getUNDEF(MVT(MVT::Other)));
2737 SDValue Agg = getValue(Op0);
2739 // Copy the beginning value(s) from the original aggregate.
2740 for (; i != LinearIndex; ++i)
2741 Values[i] = IntoUndef ? DAG.getUNDEF(AggValueVTs[i]) :
2742 SDValue(Agg.getNode(), Agg.getResNo() + i);
2743 // Copy values from the inserted value(s).
2745 SDValue Val = getValue(Op1);
2746 for (; i != LinearIndex + NumValValues; ++i)
2747 Values[i] = FromUndef ? DAG.getUNDEF(AggValueVTs[i]) :
2748 SDValue(Val.getNode(), Val.getResNo() + i - LinearIndex);
2750 // Copy remaining value(s) from the original aggregate.
2751 for (; i != NumAggValues; ++i)
2752 Values[i] = IntoUndef ? DAG.getUNDEF(AggValueVTs[i]) :
2753 SDValue(Agg.getNode(), Agg.getResNo() + i);
2755 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(),
2756 DAG.getVTList(AggValueVTs), Values));
2759 void SelectionDAGBuilder::visitExtractValue(const ExtractValueInst &I) {
2760 const Value *Op0 = I.getOperand(0);
2761 Type *AggTy = Op0->getType();
2762 Type *ValTy = I.getType();
2763 bool OutOfUndef = isa<UndefValue>(Op0);
2765 unsigned LinearIndex = ComputeLinearIndex(AggTy, I.getIndices());
2767 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2768 SmallVector<EVT, 4> ValValueVTs;
2769 ComputeValueVTs(TLI, DAG.getDataLayout(), ValTy, ValValueVTs);
2771 unsigned NumValValues = ValValueVTs.size();
2773 // Ignore a extractvalue that produces an empty object
2774 if (!NumValValues) {
2775 setValue(&I, DAG.getUNDEF(MVT(MVT::Other)));
2779 SmallVector<SDValue, 4> Values(NumValValues);
2781 SDValue Agg = getValue(Op0);
2782 // Copy out the selected value(s).
2783 for (unsigned i = LinearIndex; i != LinearIndex + NumValValues; ++i)
2784 Values[i - LinearIndex] =
2786 DAG.getUNDEF(Agg.getNode()->getValueType(Agg.getResNo() + i)) :
2787 SDValue(Agg.getNode(), Agg.getResNo() + i);
2789 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(),
2790 DAG.getVTList(ValValueVTs), Values));
2793 void SelectionDAGBuilder::visitGetElementPtr(const User &I) {
2794 Value *Op0 = I.getOperand(0);
2795 // Note that the pointer operand may be a vector of pointers. Take the scalar
2796 // element which holds a pointer.
2797 Type *Ty = Op0->getType()->getScalarType();
2798 unsigned AS = Ty->getPointerAddressSpace();
2799 SDValue N = getValue(Op0);
2800 SDLoc dl = getCurSDLoc();
2802 // Normalize Vector GEP - all scalar operands should be converted to the
2804 unsigned VectorWidth = I.getType()->isVectorTy() ?
2805 cast<VectorType>(I.getType())->getVectorNumElements() : 0;
2807 if (VectorWidth && !N.getValueType().isVector()) {
2808 MVT VT = MVT::getVectorVT(N.getValueType().getSimpleVT(), VectorWidth);
2809 SmallVector<SDValue, 16> Ops(VectorWidth, N);
2810 N = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
2812 for (GetElementPtrInst::const_op_iterator OI = I.op_begin()+1, E = I.op_end();
2814 const Value *Idx = *OI;
2815 if (StructType *StTy = dyn_cast<StructType>(Ty)) {
2816 unsigned Field = cast<Constant>(Idx)->getUniqueInteger().getZExtValue();
2819 uint64_t Offset = DL->getStructLayout(StTy)->getElementOffset(Field);
2820 N = DAG.getNode(ISD::ADD, dl, N.getValueType(), N,
2821 DAG.getConstant(Offset, dl, N.getValueType()));
2824 Ty = StTy->getElementType(Field);
2826 Ty = cast<SequentialType>(Ty)->getElementType();
2828 DAG.getTargetLoweringInfo().getPointerTy(DAG.getDataLayout(), AS);
2829 unsigned PtrSize = PtrTy.getSizeInBits();
2830 APInt ElementSize(PtrSize, DL->getTypeAllocSize(Ty));
2832 // If this is a scalar constant or a splat vector of constants,
2833 // handle it quickly.
2834 const auto *CI = dyn_cast<ConstantInt>(Idx);
2835 if (!CI && isa<ConstantDataVector>(Idx) &&
2836 cast<ConstantDataVector>(Idx)->getSplatValue())
2837 CI = cast<ConstantInt>(cast<ConstantDataVector>(Idx)->getSplatValue());
2842 APInt Offs = ElementSize * CI->getValue().sextOrTrunc(PtrSize);
2843 SDValue OffsVal = VectorWidth ?
2844 DAG.getConstant(Offs, dl, MVT::getVectorVT(PtrTy, VectorWidth)) :
2845 DAG.getConstant(Offs, dl, PtrTy);
2846 N = DAG.getNode(ISD::ADD, dl, N.getValueType(), N, OffsVal);
2850 // N = N + Idx * ElementSize;
2851 SDValue IdxN = getValue(Idx);
2853 if (!IdxN.getValueType().isVector() && VectorWidth) {
2854 MVT VT = MVT::getVectorVT(IdxN.getValueType().getSimpleVT(), VectorWidth);
2855 SmallVector<SDValue, 16> Ops(VectorWidth, IdxN);
2856 IdxN = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
2858 // If the index is smaller or larger than intptr_t, truncate or extend
2860 IdxN = DAG.getSExtOrTrunc(IdxN, dl, N.getValueType());
2862 // If this is a multiply by a power of two, turn it into a shl
2863 // immediately. This is a very common case.
2864 if (ElementSize != 1) {
2865 if (ElementSize.isPowerOf2()) {
2866 unsigned Amt = ElementSize.logBase2();
2867 IdxN = DAG.getNode(ISD::SHL, dl,
2868 N.getValueType(), IdxN,
2869 DAG.getConstant(Amt, dl, IdxN.getValueType()));
2871 SDValue Scale = DAG.getConstant(ElementSize, dl, IdxN.getValueType());
2872 IdxN = DAG.getNode(ISD::MUL, dl,
2873 N.getValueType(), IdxN, Scale);
2877 N = DAG.getNode(ISD::ADD, dl,
2878 N.getValueType(), N, IdxN);
2885 void SelectionDAGBuilder::visitAlloca(const AllocaInst &I) {
2886 // If this is a fixed sized alloca in the entry block of the function,
2887 // allocate it statically on the stack.
2888 if (FuncInfo.StaticAllocaMap.count(&I))
2889 return; // getValue will auto-populate this.
2891 SDLoc dl = getCurSDLoc();
2892 Type *Ty = I.getAllocatedType();
2893 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2894 auto &DL = DAG.getDataLayout();
2895 uint64_t TySize = DL.getTypeAllocSize(Ty);
2897 std::max((unsigned)DL.getPrefTypeAlignment(Ty), I.getAlignment());
2899 SDValue AllocSize = getValue(I.getArraySize());
2901 EVT IntPtr = TLI.getPointerTy(DAG.getDataLayout());
2902 if (AllocSize.getValueType() != IntPtr)
2903 AllocSize = DAG.getZExtOrTrunc(AllocSize, dl, IntPtr);
2905 AllocSize = DAG.getNode(ISD::MUL, dl, IntPtr,
2907 DAG.getConstant(TySize, dl, IntPtr));
2909 // Handle alignment. If the requested alignment is less than or equal to
2910 // the stack alignment, ignore it. If the size is greater than or equal to
2911 // the stack alignment, we note this in the DYNAMIC_STACKALLOC node.
2912 unsigned StackAlign =
2913 DAG.getSubtarget().getFrameLowering()->getStackAlignment();
2914 if (Align <= StackAlign)
2917 // Round the size of the allocation up to the stack alignment size
2918 // by add SA-1 to the size.
2919 AllocSize = DAG.getNode(ISD::ADD, dl,
2920 AllocSize.getValueType(), AllocSize,
2921 DAG.getIntPtrConstant(StackAlign - 1, dl));
2923 // Mask out the low bits for alignment purposes.
2924 AllocSize = DAG.getNode(ISD::AND, dl,
2925 AllocSize.getValueType(), AllocSize,
2926 DAG.getIntPtrConstant(~(uint64_t)(StackAlign - 1),
2929 SDValue Ops[] = { getRoot(), AllocSize, DAG.getIntPtrConstant(Align, dl) };
2930 SDVTList VTs = DAG.getVTList(AllocSize.getValueType(), MVT::Other);
2931 SDValue DSA = DAG.getNode(ISD::DYNAMIC_STACKALLOC, dl, VTs, Ops);
2933 DAG.setRoot(DSA.getValue(1));
2935 assert(FuncInfo.MF->getFrameInfo()->hasVarSizedObjects());
2938 void SelectionDAGBuilder::visitLoad(const LoadInst &I) {
2940 return visitAtomicLoad(I);
2942 const Value *SV = I.getOperand(0);
2943 SDValue Ptr = getValue(SV);
2945 Type *Ty = I.getType();
2947 bool isVolatile = I.isVolatile();
2948 bool isNonTemporal = I.getMetadata(LLVMContext::MD_nontemporal) != nullptr;
2950 // The IR notion of invariant_load only guarantees that all *non-faulting*
2951 // invariant loads result in the same value. The MI notion of invariant load
2952 // guarantees that the load can be legally moved to any location within its
2953 // containing function. The MI notion of invariant_load is stronger than the
2954 // IR notion of invariant_load -- an MI invariant_load is an IR invariant_load
2955 // with a guarantee that the location being loaded from is dereferenceable
2956 // throughout the function's lifetime.
2958 bool isInvariant = I.getMetadata(LLVMContext::MD_invariant_load) != nullptr &&
2959 isDereferenceablePointer(SV, DAG.getDataLayout());
2960 unsigned Alignment = I.getAlignment();
2963 I.getAAMetadata(AAInfo);
2964 const MDNode *Ranges = I.getMetadata(LLVMContext::MD_range);
2966 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2967 SmallVector<EVT, 4> ValueVTs;
2968 SmallVector<uint64_t, 4> Offsets;
2969 ComputeValueVTs(TLI, DAG.getDataLayout(), Ty, ValueVTs, &Offsets);
2970 unsigned NumValues = ValueVTs.size();
2975 bool ConstantMemory = false;
2976 if (isVolatile || NumValues > MaxParallelChains)
2977 // Serialize volatile loads with other side effects.
2979 else if (AA->pointsToConstantMemory(MemoryLocation(
2980 SV, DAG.getDataLayout().getTypeStoreSize(Ty), AAInfo))) {
2981 // Do not serialize (non-volatile) loads of constant memory with anything.
2982 Root = DAG.getEntryNode();
2983 ConstantMemory = true;
2985 // Do not serialize non-volatile loads against each other.
2986 Root = DAG.getRoot();
2989 SDLoc dl = getCurSDLoc();
2992 Root = TLI.prepareVolatileOrAtomicLoad(Root, dl, DAG);
2994 SmallVector<SDValue, 4> Values(NumValues);
2995 SmallVector<SDValue, 4> Chains(std::min(MaxParallelChains, NumValues));
2996 EVT PtrVT = Ptr.getValueType();
2997 unsigned ChainI = 0;
2998 for (unsigned i = 0; i != NumValues; ++i, ++ChainI) {
2999 // Serializing loads here may result in excessive register pressure, and
3000 // TokenFactor places arbitrary choke points on the scheduler. SD scheduling
3001 // could recover a bit by hoisting nodes upward in the chain by recognizing
3002 // they are side-effect free or do not alias. The optimizer should really
3003 // avoid this case by converting large object/array copies to llvm.memcpy
3004 // (MaxParallelChains should always remain as failsafe).
3005 if (ChainI == MaxParallelChains) {
3006 assert(PendingLoads.empty() && "PendingLoads must be serialized first");
3007 SDValue Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
3008 makeArrayRef(Chains.data(), ChainI));
3012 SDValue A = DAG.getNode(ISD::ADD, dl,
3014 DAG.getConstant(Offsets[i], dl, PtrVT));
3015 SDValue L = DAG.getLoad(ValueVTs[i], dl, Root,
3016 A, MachinePointerInfo(SV, Offsets[i]), isVolatile,
3017 isNonTemporal, isInvariant, Alignment, AAInfo,
3021 Chains[ChainI] = L.getValue(1);
3024 if (!ConstantMemory) {
3025 SDValue Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
3026 makeArrayRef(Chains.data(), ChainI));
3030 PendingLoads.push_back(Chain);
3033 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, dl,
3034 DAG.getVTList(ValueVTs), Values));
3037 void SelectionDAGBuilder::visitStore(const StoreInst &I) {
3039 return visitAtomicStore(I);
3041 const Value *SrcV = I.getOperand(0);
3042 const Value *PtrV = I.getOperand(1);
3044 SmallVector<EVT, 4> ValueVTs;
3045 SmallVector<uint64_t, 4> Offsets;
3046 ComputeValueVTs(DAG.getTargetLoweringInfo(), DAG.getDataLayout(),
3047 SrcV->getType(), ValueVTs, &Offsets);
3048 unsigned NumValues = ValueVTs.size();
3052 // Get the lowered operands. Note that we do this after
3053 // checking if NumResults is zero, because with zero results
3054 // the operands won't have values in the map.
3055 SDValue Src = getValue(SrcV);
3056 SDValue Ptr = getValue(PtrV);
3058 SDValue Root = getRoot();
3059 SmallVector<SDValue, 4> Chains(std::min(MaxParallelChains, NumValues));
3060 EVT PtrVT = Ptr.getValueType();
3061 bool isVolatile = I.isVolatile();
3062 bool isNonTemporal = I.getMetadata(LLVMContext::MD_nontemporal) != nullptr;
3063 unsigned Alignment = I.getAlignment();
3064 SDLoc dl = getCurSDLoc();
3067 I.getAAMetadata(AAInfo);
3069 unsigned ChainI = 0;
3070 for (unsigned i = 0; i != NumValues; ++i, ++ChainI) {
3071 // See visitLoad comments.
3072 if (ChainI == MaxParallelChains) {
3073 SDValue Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
3074 makeArrayRef(Chains.data(), ChainI));
3078 SDValue Add = DAG.getNode(ISD::ADD, dl, PtrVT, Ptr,
3079 DAG.getConstant(Offsets[i], dl, PtrVT));
3080 SDValue St = DAG.getStore(Root, dl,
3081 SDValue(Src.getNode(), Src.getResNo() + i),
3082 Add, MachinePointerInfo(PtrV, Offsets[i]),
3083 isVolatile, isNonTemporal, Alignment, AAInfo);
3084 Chains[ChainI] = St;
3087 SDValue StoreNode = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
3088 makeArrayRef(Chains.data(), ChainI));
3089 DAG.setRoot(StoreNode);
3092 void SelectionDAGBuilder::visitMaskedStore(const CallInst &I) {
3093 SDLoc sdl = getCurSDLoc();
3095 // llvm.masked.store.*(Src0, Ptr, alignment, Mask)
3096 Value *PtrOperand = I.getArgOperand(1);
3097 SDValue Ptr = getValue(PtrOperand);
3098 SDValue Src0 = getValue(I.getArgOperand(0));
3099 SDValue Mask = getValue(I.getArgOperand(3));
3100 EVT VT = Src0.getValueType();
3101 unsigned Alignment = (cast<ConstantInt>(I.getArgOperand(2)))->getZExtValue();
3103 Alignment = DAG.getEVTAlignment(VT);
3106 I.getAAMetadata(AAInfo);
3108 MachineMemOperand *MMO =
3109 DAG.getMachineFunction().
3110 getMachineMemOperand(MachinePointerInfo(PtrOperand),
3111 MachineMemOperand::MOStore, VT.getStoreSize(),
3113 SDValue StoreNode = DAG.getMaskedStore(getRoot(), sdl, Src0, Ptr, Mask, VT,
3115 DAG.setRoot(StoreNode);
3116 setValue(&I, StoreNode);
3119 // Gather/scatter receive a vector of pointers.
3120 // This vector of pointers may be represented as a base pointer + vector of
3121 // indices, it depends on GEP and instruction preceding GEP
3122 // that calculates indices
3123 static bool getUniformBase(Value *& Ptr, SDValue& Base, SDValue& Index,
3124 SelectionDAGBuilder* SDB) {
3126 assert(Ptr->getType()->isVectorTy() && "Unexpected pointer type");
3127 GetElementPtrInst *Gep = dyn_cast<GetElementPtrInst>(Ptr);
3128 if (!Gep || Gep->getNumOperands() > 2)
3130 ShuffleVectorInst *ShuffleInst =
3131 dyn_cast<ShuffleVectorInst>(Gep->getPointerOperand());
3132 if (!ShuffleInst || !ShuffleInst->getMask()->isNullValue() ||
3133 cast<Instruction>(ShuffleInst->getOperand(0))->getOpcode() !=
3134 Instruction::InsertElement)
3137 Ptr = cast<InsertElementInst>(ShuffleInst->getOperand(0))->getOperand(1);
3139 SelectionDAG& DAG = SDB->DAG;
3140 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3141 // Check is the Ptr is inside current basic block
3142 // If not, look for the shuffle instruction
3143 if (SDB->findValue(Ptr))
3144 Base = SDB->getValue(Ptr);
3145 else if (SDB->findValue(ShuffleInst)) {
3146 SDValue ShuffleNode = SDB->getValue(ShuffleInst);
3147 SDLoc sdl = ShuffleNode;
3149 ISD::EXTRACT_VECTOR_ELT, sdl,
3150 ShuffleNode.getValueType().getScalarType(), ShuffleNode,
3151 DAG.getConstant(0, sdl, TLI.getVectorIdxTy(DAG.getDataLayout())));
3152 SDB->setValue(Ptr, Base);
3157 Value *IndexVal = Gep->getOperand(1);
3158 if (SDB->findValue(IndexVal)) {
3159 Index = SDB->getValue(IndexVal);
3161 if (SExtInst* Sext = dyn_cast<SExtInst>(IndexVal)) {
3162 IndexVal = Sext->getOperand(0);
3163 if (SDB->findValue(IndexVal))
3164 Index = SDB->getValue(IndexVal);
3171 void SelectionDAGBuilder::visitMaskedScatter(const CallInst &I) {
3172 SDLoc sdl = getCurSDLoc();
3174 // llvm.masked.scatter.*(Src0, Ptrs, alignemt, Mask)
3175 Value *Ptr = I.getArgOperand(1);
3176 SDValue Src0 = getValue(I.getArgOperand(0));
3177 SDValue Mask = getValue(I.getArgOperand(3));
3178 EVT VT = Src0.getValueType();
3179 unsigned Alignment = (cast<ConstantInt>(I.getArgOperand(2)))->getZExtValue();
3181 Alignment = DAG.getEVTAlignment(VT);
3182 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3185 I.getAAMetadata(AAInfo);
3189 Value *BasePtr = Ptr;
3190 bool UniformBase = getUniformBase(BasePtr, Base, Index, this);
3192 Value *MemOpBasePtr = UniformBase ? BasePtr : nullptr;
3193 MachineMemOperand *MMO = DAG.getMachineFunction().
3194 getMachineMemOperand(MachinePointerInfo(MemOpBasePtr),
3195 MachineMemOperand::MOStore, VT.getStoreSize(),
3198 Base = DAG.getTargetConstant(0, sdl, TLI.getPointerTy(DAG.getDataLayout()));
3199 Index = getValue(Ptr);
3201 SDValue Ops[] = { getRoot(), Src0, Mask, Base, Index };
3202 SDValue Scatter = DAG.getMaskedScatter(DAG.getVTList(MVT::Other), VT, sdl,
3204 DAG.setRoot(Scatter);
3205 setValue(&I, Scatter);
3208 void SelectionDAGBuilder::visitMaskedLoad(const CallInst &I) {
3209 SDLoc sdl = getCurSDLoc();
3211 // @llvm.masked.load.*(Ptr, alignment, Mask, Src0)
3212 Value *PtrOperand = I.getArgOperand(0);
3213 SDValue Ptr = getValue(PtrOperand);
3214 SDValue Src0 = getValue(I.getArgOperand(3));
3215 SDValue Mask = getValue(I.getArgOperand(2));
3217 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3218 EVT VT = TLI.getValueType(DAG.getDataLayout(), I.getType());
3219 unsigned Alignment = (cast<ConstantInt>(I.getArgOperand(1)))->getZExtValue();
3221 Alignment = DAG.getEVTAlignment(VT);
3224 I.getAAMetadata(AAInfo);
3225 const MDNode *Ranges = I.getMetadata(LLVMContext::MD_range);
3227 SDValue InChain = DAG.getRoot();
3228 if (AA->pointsToConstantMemory(MemoryLocation(
3229 PtrOperand, DAG.getDataLayout().getTypeStoreSize(I.getType()),
3231 // Do not serialize (non-volatile) loads of constant memory with anything.
3232 InChain = DAG.getEntryNode();
3235 MachineMemOperand *MMO =
3236 DAG.getMachineFunction().
3237 getMachineMemOperand(MachinePointerInfo(PtrOperand),
3238 MachineMemOperand::MOLoad, VT.getStoreSize(),
3239 Alignment, AAInfo, Ranges);
3241 SDValue Load = DAG.getMaskedLoad(VT, sdl, InChain, Ptr, Mask, Src0, VT, MMO,
3243 SDValue OutChain = Load.getValue(1);
3244 DAG.setRoot(OutChain);
3248 void SelectionDAGBuilder::visitMaskedGather(const CallInst &I) {
3249 SDLoc sdl = getCurSDLoc();
3251 // @llvm.masked.gather.*(Ptrs, alignment, Mask, Src0)
3252 Value *Ptr = I.getArgOperand(0);
3253 SDValue Src0 = getValue(I.getArgOperand(3));
3254 SDValue Mask = getValue(I.getArgOperand(2));
3256 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3257 EVT VT = TLI.getValueType(DAG.getDataLayout(), I.getType());
3258 unsigned Alignment = (cast<ConstantInt>(I.getArgOperand(1)))->getZExtValue();
3260 Alignment = DAG.getEVTAlignment(VT);
3263 I.getAAMetadata(AAInfo);
3264 const MDNode *Ranges = I.getMetadata(LLVMContext::MD_range);
3266 SDValue Root = DAG.getRoot();
3269 Value *BasePtr = Ptr;
3270 bool UniformBase = getUniformBase(BasePtr, Base, Index, this);
3271 bool ConstantMemory = false;
3273 AA->pointsToConstantMemory(MemoryLocation(
3274 BasePtr, DAG.getDataLayout().getTypeStoreSize(I.getType()),
3276 // Do not serialize (non-volatile) loads of constant memory with anything.
3277 Root = DAG.getEntryNode();
3278 ConstantMemory = true;
3281 MachineMemOperand *MMO =
3282 DAG.getMachineFunction().
3283 getMachineMemOperand(MachinePointerInfo(UniformBase ? BasePtr : nullptr),
3284 MachineMemOperand::MOLoad, VT.getStoreSize(),
3285 Alignment, AAInfo, Ranges);
3288 Base = DAG.getTargetConstant(0, sdl, TLI.getPointerTy(DAG.getDataLayout()));
3289 Index = getValue(Ptr);
3291 SDValue Ops[] = { Root, Src0, Mask, Base, Index };
3292 SDValue Gather = DAG.getMaskedGather(DAG.getVTList(VT, MVT::Other), VT, sdl,
3295 SDValue OutChain = Gather.getValue(1);
3296 if (!ConstantMemory)
3297 PendingLoads.push_back(OutChain);
3298 setValue(&I, Gather);
3301 void SelectionDAGBuilder::visitAtomicCmpXchg(const AtomicCmpXchgInst &I) {
3302 SDLoc dl = getCurSDLoc();
3303 AtomicOrdering SuccessOrder = I.getSuccessOrdering();
3304 AtomicOrdering FailureOrder = I.getFailureOrdering();
3305 SynchronizationScope Scope = I.getSynchScope();
3307 SDValue InChain = getRoot();
3309 MVT MemVT = getValue(I.getCompareOperand()).getSimpleValueType();
3310 SDVTList VTs = DAG.getVTList(MemVT, MVT::i1, MVT::Other);
3311 SDValue L = DAG.getAtomicCmpSwap(
3312 ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, dl, MemVT, VTs, InChain,
3313 getValue(I.getPointerOperand()), getValue(I.getCompareOperand()),
3314 getValue(I.getNewValOperand()), MachinePointerInfo(I.getPointerOperand()),
3315 /*Alignment=*/ 0, SuccessOrder, FailureOrder, Scope);
3317 SDValue OutChain = L.getValue(2);
3320 DAG.setRoot(OutChain);
3323 void SelectionDAGBuilder::visitAtomicRMW(const AtomicRMWInst &I) {
3324 SDLoc dl = getCurSDLoc();
3326 switch (I.getOperation()) {
3327 default: llvm_unreachable("Unknown atomicrmw operation");
3328 case AtomicRMWInst::Xchg: NT = ISD::ATOMIC_SWAP; break;
3329 case AtomicRMWInst::Add: NT = ISD::ATOMIC_LOAD_ADD; break;
3330 case AtomicRMWInst::Sub: NT = ISD::ATOMIC_LOAD_SUB; break;
3331 case AtomicRMWInst::And: NT = ISD::ATOMIC_LOAD_AND; break;
3332 case AtomicRMWInst::Nand: NT = ISD::ATOMIC_LOAD_NAND; break;
3333 case AtomicRMWInst::Or: NT = ISD::ATOMIC_LOAD_OR; break;
3334 case AtomicRMWInst::Xor: NT = ISD::ATOMIC_LOAD_XOR; break;
3335 case AtomicRMWInst::Max: NT = ISD::ATOMIC_LOAD_MAX; break;
3336 case AtomicRMWInst::Min: NT = ISD::ATOMIC_LOAD_MIN; break;
3337 case AtomicRMWInst::UMax: NT = ISD::ATOMIC_LOAD_UMAX; break;
3338 case AtomicRMWInst::UMin: NT = ISD::ATOMIC_LOAD_UMIN; break;
3340 AtomicOrdering Order = I.getOrdering();
3341 SynchronizationScope Scope = I.getSynchScope();
3343 SDValue InChain = getRoot();
3346 DAG.getAtomic(NT, dl,
3347 getValue(I.getValOperand()).getSimpleValueType(),
3349 getValue(I.getPointerOperand()),
3350 getValue(I.getValOperand()),
3351 I.getPointerOperand(),
3352 /* Alignment=*/ 0, Order, Scope);
3354 SDValue OutChain = L.getValue(1);
3357 DAG.setRoot(OutChain);
3360 void SelectionDAGBuilder::visitFence(const FenceInst &I) {
3361 SDLoc dl = getCurSDLoc();
3362 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3365 Ops[1] = DAG.getConstant(I.getOrdering(), dl,
3366 TLI.getPointerTy(DAG.getDataLayout()));
3367 Ops[2] = DAG.getConstant(I.getSynchScope(), dl,
3368 TLI.getPointerTy(DAG.getDataLayout()));
3369 DAG.setRoot(DAG.getNode(ISD::ATOMIC_FENCE, dl, MVT::Other, Ops));
3372 void SelectionDAGBuilder::visitAtomicLoad(const LoadInst &I) {
3373 SDLoc dl = getCurSDLoc();
3374 AtomicOrdering Order = I.getOrdering();
3375 SynchronizationScope Scope = I.getSynchScope();
3377 SDValue InChain = getRoot();
3379 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3380 EVT VT = TLI.getValueType(DAG.getDataLayout(), I.getType());
3382 if (I.getAlignment() < VT.getSizeInBits() / 8)
3383 report_fatal_error("Cannot generate unaligned atomic load");
3385 MachineMemOperand *MMO =
3386 DAG.getMachineFunction().
3387 getMachineMemOperand(MachinePointerInfo(I.getPointerOperand()),
3388 MachineMemOperand::MOVolatile |
3389 MachineMemOperand::MOLoad,
3391 I.getAlignment() ? I.getAlignment() :
3392 DAG.getEVTAlignment(VT));
3394 InChain = TLI.prepareVolatileOrAtomicLoad(InChain, dl, DAG);
3396 DAG.getAtomic(ISD::ATOMIC_LOAD, dl, VT, VT, InChain,
3397 getValue(I.getPointerOperand()), MMO,
3400 SDValue OutChain = L.getValue(1);
3403 DAG.setRoot(OutChain);
3406 void SelectionDAGBuilder::visitAtomicStore(const StoreInst &I) {
3407 SDLoc dl = getCurSDLoc();
3409 AtomicOrdering Order = I.getOrdering();
3410 SynchronizationScope Scope = I.getSynchScope();
3412 SDValue InChain = getRoot();
3414 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3416 TLI.getValueType(DAG.getDataLayout(), I.getValueOperand()->getType());
3418 if (I.getAlignment() < VT.getSizeInBits() / 8)
3419 report_fatal_error("Cannot generate unaligned atomic store");
3422 DAG.getAtomic(ISD::ATOMIC_STORE, dl, VT,
3424 getValue(I.getPointerOperand()),
3425 getValue(I.getValueOperand()),
3426 I.getPointerOperand(), I.getAlignment(),
3429 DAG.setRoot(OutChain);
3432 /// visitTargetIntrinsic - Lower a call of a target intrinsic to an INTRINSIC
3434 void SelectionDAGBuilder::visitTargetIntrinsic(const CallInst &I,
3435 unsigned Intrinsic) {
3436 bool HasChain = !I.doesNotAccessMemory();
3437 bool OnlyLoad = HasChain && I.onlyReadsMemory();
3439 // Build the operand list.
3440 SmallVector<SDValue, 8> Ops;
3441 if (HasChain) { // If this intrinsic has side-effects, chainify it.
3443 // We don't need to serialize loads against other loads.
3444 Ops.push_back(DAG.getRoot());
3446 Ops.push_back(getRoot());
3450 // Info is set by getTgtMemInstrinsic
3451 TargetLowering::IntrinsicInfo Info;
3452 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3453 bool IsTgtIntrinsic = TLI.getTgtMemIntrinsic(Info, I, Intrinsic);
3455 // Add the intrinsic ID as an integer operand if it's not a target intrinsic.
3456 if (!IsTgtIntrinsic || Info.opc == ISD::INTRINSIC_VOID ||
3457 Info.opc == ISD::INTRINSIC_W_CHAIN)
3458 Ops.push_back(DAG.getTargetConstant(Intrinsic, getCurSDLoc(),
3459 TLI.getPointerTy(DAG.getDataLayout())));
3461 // Add all operands of the call to the operand list.
3462 for (unsigned i = 0, e = I.getNumArgOperands(); i != e; ++i) {
3463 SDValue Op = getValue(I.getArgOperand(i));
3467 SmallVector<EVT, 4> ValueVTs;
3468 ComputeValueVTs(TLI, DAG.getDataLayout(), I.getType(), ValueVTs);
3471 ValueVTs.push_back(MVT::Other);
3473 SDVTList VTs = DAG.getVTList(ValueVTs);
3477 if (IsTgtIntrinsic) {
3478 // This is target intrinsic that touches memory
3479 Result = DAG.getMemIntrinsicNode(Info.opc, getCurSDLoc(),
3480 VTs, Ops, Info.memVT,
3481 MachinePointerInfo(Info.ptrVal, Info.offset),
3482 Info.align, Info.vol,
3483 Info.readMem, Info.writeMem, Info.size);
3484 } else if (!HasChain) {
3485 Result = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, getCurSDLoc(), VTs, Ops);
3486 } else if (!I.getType()->isVoidTy()) {
3487 Result = DAG.getNode(ISD::INTRINSIC_W_CHAIN, getCurSDLoc(), VTs, Ops);
3489 Result = DAG.getNode(ISD::INTRINSIC_VOID, getCurSDLoc(), VTs, Ops);
3493 SDValue Chain = Result.getValue(Result.getNode()->getNumValues()-1);
3495 PendingLoads.push_back(Chain);
3500 if (!I.getType()->isVoidTy()) {
3501 if (VectorType *PTy = dyn_cast<VectorType>(I.getType())) {
3502 EVT VT = TLI.getValueType(DAG.getDataLayout(), PTy);
3503 Result = DAG.getNode(ISD::BITCAST, getCurSDLoc(), VT, Result);
3506 setValue(&I, Result);
3510 /// GetSignificand - Get the significand and build it into a floating-point
3511 /// number with exponent of 1:
3513 /// Op = (Op & 0x007fffff) | 0x3f800000;
3515 /// where Op is the hexadecimal representation of floating point value.
3517 GetSignificand(SelectionDAG &DAG, SDValue Op, SDLoc dl) {
3518 SDValue t1 = DAG.getNode(ISD::AND, dl, MVT::i32, Op,
3519 DAG.getConstant(0x007fffff, dl, MVT::i32));
3520 SDValue t2 = DAG.getNode(ISD::OR, dl, MVT::i32, t1,
3521 DAG.getConstant(0x3f800000, dl, MVT::i32));
3522 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, t2);
3525 /// GetExponent - Get the exponent:
3527 /// (float)(int)(((Op & 0x7f800000) >> 23) - 127);
3529 /// where Op is the hexadecimal representation of floating point value.
3531 GetExponent(SelectionDAG &DAG, SDValue Op, const TargetLowering &TLI,
3533 SDValue t0 = DAG.getNode(ISD::AND, dl, MVT::i32, Op,
3534 DAG.getConstant(0x7f800000, dl, MVT::i32));
3535 SDValue t1 = DAG.getNode(
3536 ISD::SRL, dl, MVT::i32, t0,
3537 DAG.getConstant(23, dl, TLI.getPointerTy(DAG.getDataLayout())));
3538 SDValue t2 = DAG.getNode(ISD::SUB, dl, MVT::i32, t1,
3539 DAG.getConstant(127, dl, MVT::i32));
3540 return DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, t2);
3543 /// getF32Constant - Get 32-bit floating point constant.
3545 getF32Constant(SelectionDAG &DAG, unsigned Flt, SDLoc dl) {
3546 return DAG.getConstantFP(APFloat(APFloat::IEEEsingle, APInt(32, Flt)), dl,
3550 static SDValue getLimitedPrecisionExp2(SDValue t0, SDLoc dl,
3551 SelectionDAG &DAG) {
3552 // IntegerPartOfX = ((int32_t)(t0);
3553 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, t0);
3555 // FractionalPartOfX = t0 - (float)IntegerPartOfX;
3556 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX);
3557 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, t1);
3559 // IntegerPartOfX <<= 23;
3560 IntegerPartOfX = DAG.getNode(
3561 ISD::SHL, dl, MVT::i32, IntegerPartOfX,
3562 DAG.getConstant(23, dl, DAG.getTargetLoweringInfo().getPointerTy(
3563 DAG.getDataLayout())));
3565 SDValue TwoToFractionalPartOfX;
3566 if (LimitFloatPrecision <= 6) {
3567 // For floating-point precision of 6:
3569 // TwoToFractionalPartOfX =
3571 // (0.735607626f + 0.252464424f * x) * x;
3573 // error 0.0144103317, which is 6 bits
3574 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3575 getF32Constant(DAG, 0x3e814304, dl));
3576 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3577 getF32Constant(DAG, 0x3f3c50c8, dl));
3578 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3579 TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3580 getF32Constant(DAG, 0x3f7f5e7e, dl));
3581 } else if (LimitFloatPrecision <= 12) {
3582 // For floating-point precision of 12:
3584 // TwoToFractionalPartOfX =
3587 // (0.224338339f + 0.792043434e-1f * x) * x) * x;
3589 // error 0.000107046256, which is 13 to 14 bits
3590 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3591 getF32Constant(DAG, 0x3da235e3, dl));
3592 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3593 getF32Constant(DAG, 0x3e65b8f3, dl));
3594 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3595 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3596 getF32Constant(DAG, 0x3f324b07, dl));
3597 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3598 TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3599 getF32Constant(DAG, 0x3f7ff8fd, dl));
3600 } else { // LimitFloatPrecision <= 18
3601 // For floating-point precision of 18:
3603 // TwoToFractionalPartOfX =
3607 // (0.554906021e-1f +
3608 // (0.961591928e-2f +
3609 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x;
3610 // error 2.47208000*10^(-7), which is better than 18 bits
3611 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3612 getF32Constant(DAG, 0x3924b03e, dl));
3613 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3614 getF32Constant(DAG, 0x3ab24b87, dl));
3615 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3616 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3617 getF32Constant(DAG, 0x3c1d8c17, dl));
3618 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3619 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3620 getF32Constant(DAG, 0x3d634a1d, dl));
3621 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3622 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3623 getF32Constant(DAG, 0x3e75fe14, dl));
3624 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3625 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10,
3626 getF32Constant(DAG, 0x3f317234, dl));
3627 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X);
3628 TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t12,
3629 getF32Constant(DAG, 0x3f800000, dl));
3632 // Add the exponent into the result in integer domain.
3633 SDValue t13 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, TwoToFractionalPartOfX);
3634 return DAG.getNode(ISD::BITCAST, dl, MVT::f32,
3635 DAG.getNode(ISD::ADD, dl, MVT::i32, t13, IntegerPartOfX));
3638 /// expandExp - Lower an exp intrinsic. Handles the special sequences for
3639 /// limited-precision mode.
3640 static SDValue expandExp(SDLoc dl, SDValue Op, SelectionDAG &DAG,
3641 const TargetLowering &TLI) {
3642 if (Op.getValueType() == MVT::f32 &&
3643 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3645 // Put the exponent in the right bit position for later addition to the
3648 // #define LOG2OFe 1.4426950f
3649 // t0 = Op * LOG2OFe
3650 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, Op,
3651 getF32Constant(DAG, 0x3fb8aa3b, dl));
3652 return getLimitedPrecisionExp2(t0, dl, DAG);
3655 // No special expansion.
3656 return DAG.getNode(ISD::FEXP, dl, Op.getValueType(), Op);
3659 /// expandLog - Lower a log intrinsic. Handles the special sequences for
3660 /// limited-precision mode.
3661 static SDValue expandLog(SDLoc dl, SDValue Op, SelectionDAG &DAG,
3662 const TargetLowering &TLI) {
3663 if (Op.getValueType() == MVT::f32 &&
3664 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3665 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op);
3667 // Scale the exponent by log(2) [0.69314718f].
3668 SDValue Exp = GetExponent(DAG, Op1, TLI, dl);
3669 SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp,
3670 getF32Constant(DAG, 0x3f317218, dl));
3672 // Get the significand and build it into a floating-point number with
3674 SDValue X = GetSignificand(DAG, Op1, dl);
3676 SDValue LogOfMantissa;
3677 if (LimitFloatPrecision <= 6) {
3678 // For floating-point precision of 6:
3682 // (1.4034025f - 0.23903021f * x) * x;
3684 // error 0.0034276066, which is better than 8 bits
3685 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3686 getF32Constant(DAG, 0xbe74c456, dl));
3687 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3688 getF32Constant(DAG, 0x3fb3a2b1, dl));
3689 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3690 LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3691 getF32Constant(DAG, 0x3f949a29, dl));
3692 } else if (LimitFloatPrecision <= 12) {
3693 // For floating-point precision of 12:
3699 // (0.44717955f - 0.56570851e-1f * x) * x) * x) * x;
3701 // error 0.000061011436, which is 14 bits
3702 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3703 getF32Constant(DAG, 0xbd67b6d6, dl));
3704 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3705 getF32Constant(DAG, 0x3ee4f4b8, dl));
3706 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3707 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3708 getF32Constant(DAG, 0x3fbc278b, dl));
3709 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3710 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3711 getF32Constant(DAG, 0x40348e95, dl));
3712 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3713 LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3714 getF32Constant(DAG, 0x3fdef31a, dl));
3715 } else { // LimitFloatPrecision <= 18
3716 // For floating-point precision of 18:
3724 // (0.19073739f - 0.17809712e-1f * x) * x) * x) * x) * x)*x;
3726 // error 0.0000023660568, which is better than 18 bits
3727 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3728 getF32Constant(DAG, 0xbc91e5ac, dl));
3729 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3730 getF32Constant(DAG, 0x3e4350aa, dl));
3731 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3732 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3733 getF32Constant(DAG, 0x3f60d3e3, dl));
3734 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3735 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3736 getF32Constant(DAG, 0x4011cdf0, dl));
3737 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3738 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3739 getF32Constant(DAG, 0x406cfd1c, dl));
3740 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3741 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3742 getF32Constant(DAG, 0x408797cb, dl));
3743 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3744 LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10,
3745 getF32Constant(DAG, 0x4006dcab, dl));
3748 return DAG.getNode(ISD::FADD, dl, MVT::f32, LogOfExponent, LogOfMantissa);
3751 // No special expansion.
3752 return DAG.getNode(ISD::FLOG, dl, Op.getValueType(), Op);
3755 /// expandLog2 - Lower a log2 intrinsic. Handles the special sequences for
3756 /// limited-precision mode.
3757 static SDValue expandLog2(SDLoc dl, SDValue Op, SelectionDAG &DAG,
3758 const TargetLowering &TLI) {
3759 if (Op.getValueType() == MVT::f32 &&
3760 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3761 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op);
3763 // Get the exponent.
3764 SDValue LogOfExponent = GetExponent(DAG, Op1, TLI, dl);
3766 // Get the significand and build it into a floating-point number with
3768 SDValue X = GetSignificand(DAG, Op1, dl);
3770 // Different possible minimax approximations of significand in
3771 // floating-point for various degrees of accuracy over [1,2].
3772 SDValue Log2ofMantissa;
3773 if (LimitFloatPrecision <= 6) {
3774 // For floating-point precision of 6:
3776 // Log2ofMantissa = -1.6749035f + (2.0246817f - .34484768f * x) * x;
3778 // error 0.0049451742, which is more than 7 bits
3779 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3780 getF32Constant(DAG, 0xbeb08fe0, dl));
3781 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3782 getF32Constant(DAG, 0x40019463, dl));
3783 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3784 Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3785 getF32Constant(DAG, 0x3fd6633d, dl));
3786 } else if (LimitFloatPrecision <= 12) {
3787 // For floating-point precision of 12:
3793 // (.645142248f - 0.816157886e-1f * x) * x) * x) * x;
3795 // error 0.0000876136000, which is better than 13 bits
3796 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3797 getF32Constant(DAG, 0xbda7262e, dl));
3798 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3799 getF32Constant(DAG, 0x3f25280b, dl));
3800 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3801 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3802 getF32Constant(DAG, 0x4007b923, dl));
3803 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3804 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3805 getF32Constant(DAG, 0x40823e2f, dl));
3806 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3807 Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3808 getF32Constant(DAG, 0x4020d29c, dl));
3809 } else { // LimitFloatPrecision <= 18
3810 // For floating-point precision of 18:
3819 // 0.25691327e-1f * x) * x) * x) * x) * x) * x;
3821 // error 0.0000018516, which is better than 18 bits
3822 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3823 getF32Constant(DAG, 0xbcd2769e, dl));
3824 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3825 getF32Constant(DAG, 0x3e8ce0b9, dl));
3826 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3827 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3828 getF32Constant(DAG, 0x3fa22ae7, dl));
3829 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3830 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3831 getF32Constant(DAG, 0x40525723, dl));
3832 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3833 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3834 getF32Constant(DAG, 0x40aaf200, dl));
3835 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3836 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3837 getF32Constant(DAG, 0x40c39dad, dl));
3838 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3839 Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10,
3840 getF32Constant(DAG, 0x4042902c, dl));
3843 return DAG.getNode(ISD::FADD, dl, MVT::f32, LogOfExponent, Log2ofMantissa);
3846 // No special expansion.
3847 return DAG.getNode(ISD::FLOG2, dl, Op.getValueType(), Op);
3850 /// expandLog10 - Lower a log10 intrinsic. Handles the special sequences for
3851 /// limited-precision mode.
3852 static SDValue expandLog10(SDLoc dl, SDValue Op, SelectionDAG &DAG,
3853 const TargetLowering &TLI) {
3854 if (Op.getValueType() == MVT::f32 &&
3855 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3856 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op);
3858 // Scale the exponent by log10(2) [0.30102999f].
3859 SDValue Exp = GetExponent(DAG, Op1, TLI, dl);
3860 SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp,
3861 getF32Constant(DAG, 0x3e9a209a, dl));
3863 // Get the significand and build it into a floating-point number with
3865 SDValue X = GetSignificand(DAG, Op1, dl);
3867 SDValue Log10ofMantissa;
3868 if (LimitFloatPrecision <= 6) {
3869 // For floating-point precision of 6:
3871 // Log10ofMantissa =
3873 // (0.60948995f - 0.10380950f * x) * x;
3875 // error 0.0014886165, which is 6 bits
3876 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3877 getF32Constant(DAG, 0xbdd49a13, dl));
3878 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3879 getF32Constant(DAG, 0x3f1c0789, dl));
3880 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3881 Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3882 getF32Constant(DAG, 0x3f011300, dl));
3883 } else if (LimitFloatPrecision <= 12) {
3884 // For floating-point precision of 12:
3886 // Log10ofMantissa =
3889 // (-0.31664806f + 0.47637168e-1f * x) * x) * x;
3891 // error 0.00019228036, which is better than 12 bits
3892 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3893 getF32Constant(DAG, 0x3d431f31, dl));
3894 SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0,
3895 getF32Constant(DAG, 0x3ea21fb2, dl));
3896 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3897 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3898 getF32Constant(DAG, 0x3f6ae232, dl));
3899 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3900 Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4,
3901 getF32Constant(DAG, 0x3f25f7c3, dl));
3902 } else { // LimitFloatPrecision <= 18
3903 // For floating-point precision of 18:
3905 // Log10ofMantissa =
3910 // (-0.12539807f + 0.13508273e-1f * x) * x) * x) * x) * x;
3912 // error 0.0000037995730, which is better than 18 bits
3913 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3914 getF32Constant(DAG, 0x3c5d51ce, dl));
3915 SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0,
3916 getF32Constant(DAG, 0x3e00685a, dl));
3917 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3918 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3919 getF32Constant(DAG, 0x3efb6798, dl));
3920 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3921 SDValue t5 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4,
3922 getF32Constant(DAG, 0x3f88d192, dl));
3923 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3924 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3925 getF32Constant(DAG, 0x3fc4316c, dl));
3926 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3927 Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t8,
3928 getF32Constant(DAG, 0x3f57ce70, dl));
3931 return DAG.getNode(ISD::FADD, dl, MVT::f32, LogOfExponent, Log10ofMantissa);
3934 // No special expansion.
3935 return DAG.getNode(ISD::FLOG10, dl, Op.getValueType(), Op);
3938 /// expandExp2 - Lower an exp2 intrinsic. Handles the special sequences for
3939 /// limited-precision mode.
3940 static SDValue expandExp2(SDLoc dl, SDValue Op, SelectionDAG &DAG,
3941 const TargetLowering &TLI) {
3942 if (Op.getValueType() == MVT::f32 &&
3943 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18)
3944 return getLimitedPrecisionExp2(Op, dl, DAG);
3946 // No special expansion.
3947 return DAG.getNode(ISD::FEXP2, dl, Op.getValueType(), Op);
3950 /// visitPow - Lower a pow intrinsic. Handles the special sequences for
3951 /// limited-precision mode with x == 10.0f.
3952 static SDValue expandPow(SDLoc dl, SDValue LHS, SDValue RHS,
3953 SelectionDAG &DAG, const TargetLowering &TLI) {
3954 bool IsExp10 = false;
3955 if (LHS.getValueType() == MVT::f32 && RHS.getValueType() == MVT::f32 &&
3956 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3957 if (ConstantFPSDNode *LHSC = dyn_cast<ConstantFPSDNode>(LHS)) {
3959 IsExp10 = LHSC->isExactlyValue(Ten);
3964 // Put the exponent in the right bit position for later addition to the
3967 // #define LOG2OF10 3.3219281f
3968 // t0 = Op * LOG2OF10;
3969 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, RHS,
3970 getF32Constant(DAG, 0x40549a78, dl));
3971 return getLimitedPrecisionExp2(t0, dl, DAG);
3974 // No special expansion.
3975 return DAG.getNode(ISD::FPOW, dl, LHS.getValueType(), LHS, RHS);
3979 /// ExpandPowI - Expand a llvm.powi intrinsic.
3980 static SDValue ExpandPowI(SDLoc DL, SDValue LHS, SDValue RHS,
3981 SelectionDAG &DAG) {
3982 // If RHS is a constant, we can expand this out to a multiplication tree,
3983 // otherwise we end up lowering to a call to __powidf2 (for example). When
3984 // optimizing for size, we only want to do this if the expansion would produce
3985 // a small number of multiplies, otherwise we do the full expansion.
3986 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
3987 // Get the exponent as a positive value.
3988 unsigned Val = RHSC->getSExtValue();
3989 if ((int)Val < 0) Val = -Val;
3991 // powi(x, 0) -> 1.0
3993 return DAG.getConstantFP(1.0, DL, LHS.getValueType());
3995 const Function *F = DAG.getMachineFunction().getFunction();
3996 if (!F->optForSize() ||
3997 // If optimizing for size, don't insert too many multiplies.
3998 // This inserts up to 5 multiplies.
3999 countPopulation(Val) + Log2_32(Val) < 7) {
4000 // We use the simple binary decomposition method to generate the multiply
4001 // sequence. There are more optimal ways to do this (for example,
4002 // powi(x,15) generates one more multiply than it should), but this has
4003 // the benefit of being both really simple and much better than a libcall.
4004 SDValue Res; // Logically starts equal to 1.0
4005 SDValue CurSquare = LHS;
4009 Res = DAG.getNode(ISD::FMUL, DL,Res.getValueType(), Res, CurSquare);
4011 Res = CurSquare; // 1.0*CurSquare.
4014 CurSquare = DAG.getNode(ISD::FMUL, DL, CurSquare.getValueType(),
4015 CurSquare, CurSquare);
4019 // If the original was negative, invert the result, producing 1/(x*x*x).
4020 if (RHSC->getSExtValue() < 0)
4021 Res = DAG.getNode(ISD::FDIV, DL, LHS.getValueType(),
4022 DAG.getConstantFP(1.0, DL, LHS.getValueType()), Res);
4027 // Otherwise, expand to a libcall.
4028 return DAG.getNode(ISD::FPOWI, DL, LHS.getValueType(), LHS, RHS);
4031 // getTruncatedArgReg - Find underlying register used for an truncated
4033 static unsigned getTruncatedArgReg(const SDValue &N) {
4034 if (N.getOpcode() != ISD::TRUNCATE)
4037 const SDValue &Ext = N.getOperand(0);
4038 if (Ext.getOpcode() == ISD::AssertZext ||
4039 Ext.getOpcode() == ISD::AssertSext) {
4040 const SDValue &CFR = Ext.getOperand(0);
4041 if (CFR.getOpcode() == ISD::CopyFromReg)
4042 return cast<RegisterSDNode>(CFR.getOperand(1))->getReg();
4043 if (CFR.getOpcode() == ISD::TRUNCATE)
4044 return getTruncatedArgReg(CFR);
4049 /// EmitFuncArgumentDbgValue - If the DbgValueInst is a dbg_value of a function
4050 /// argument, create the corresponding DBG_VALUE machine instruction for it now.
4051 /// At the end of instruction selection, they will be inserted to the entry BB.
4052 bool SelectionDAGBuilder::EmitFuncArgumentDbgValue(
4053 const Value *V, DILocalVariable *Variable, DIExpression *Expr,
4054 DILocation *DL, int64_t Offset, bool IsIndirect, const SDValue &N) {
4055 const Argument *Arg = dyn_cast<Argument>(V);
4059 MachineFunction &MF = DAG.getMachineFunction();
4060 const TargetInstrInfo *TII = DAG.getSubtarget().getInstrInfo();
4062 // Ignore inlined function arguments here.
4064 // FIXME: Should we be checking DL->inlinedAt() to determine this?
4065 if (!Variable->getScope()->getSubprogram()->describes(MF.getFunction()))
4068 Optional<MachineOperand> Op;
4069 // Some arguments' frame index is recorded during argument lowering.
4070 if (int FI = FuncInfo.getArgumentFrameIndex(Arg))
4071 Op = MachineOperand::CreateFI(FI);
4073 if (!Op && N.getNode()) {
4075 if (N.getOpcode() == ISD::CopyFromReg)
4076 Reg = cast<RegisterSDNode>(N.getOperand(1))->getReg();
4078 Reg = getTruncatedArgReg(N);
4079 if (Reg && TargetRegisterInfo::isVirtualRegister(Reg)) {
4080 MachineRegisterInfo &RegInfo = MF.getRegInfo();
4081 unsigned PR = RegInfo.getLiveInPhysReg(Reg);
4086 Op = MachineOperand::CreateReg(Reg, false);
4090 // Check if ValueMap has reg number.
4091 DenseMap<const Value *, unsigned>::iterator VMI = FuncInfo.ValueMap.find(V);
4092 if (VMI != FuncInfo.ValueMap.end())
4093 Op = MachineOperand::CreateReg(VMI->second, false);
4096 if (!Op && N.getNode())
4097 // Check if frame index is available.
4098 if (LoadSDNode *LNode = dyn_cast<LoadSDNode>(N.getNode()))
4099 if (FrameIndexSDNode *FINode =
4100 dyn_cast<FrameIndexSDNode>(LNode->getBasePtr().getNode()))
4101 Op = MachineOperand::CreateFI(FINode->getIndex());
4106 assert(Variable->isValidLocationForIntrinsic(DL) &&
4107 "Expected inlined-at fields to agree");
4109 FuncInfo.ArgDbgValues.push_back(
4110 BuildMI(MF, DL, TII->get(TargetOpcode::DBG_VALUE), IsIndirect,
4111 Op->getReg(), Offset, Variable, Expr));
4113 FuncInfo.ArgDbgValues.push_back(
4114 BuildMI(MF, DL, TII->get(TargetOpcode::DBG_VALUE))
4117 .addMetadata(Variable)
4118 .addMetadata(Expr));
4123 // VisualStudio defines setjmp as _setjmp
4124 #if defined(_MSC_VER) && defined(setjmp) && \
4125 !defined(setjmp_undefined_for_msvc)
4126 # pragma push_macro("setjmp")
4128 # define setjmp_undefined_for_msvc
4131 /// visitIntrinsicCall - Lower the call to the specified intrinsic function. If
4132 /// we want to emit this as a call to a named external function, return the name
4133 /// otherwise lower it and return null.
4135 SelectionDAGBuilder::visitIntrinsicCall(const CallInst &I, unsigned Intrinsic) {
4136 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
4137 SDLoc sdl = getCurSDLoc();
4138 DebugLoc dl = getCurDebugLoc();
4141 switch (Intrinsic) {
4143 // By default, turn this into a target intrinsic node.
4144 visitTargetIntrinsic(I, Intrinsic);
4146 case Intrinsic::vastart: visitVAStart(I); return nullptr;
4147 case Intrinsic::vaend: visitVAEnd(I); return nullptr;
4148 case Intrinsic::vacopy: visitVACopy(I); return nullptr;
4149 case Intrinsic::returnaddress:
4150 setValue(&I, DAG.getNode(ISD::RETURNADDR, sdl,
4151 TLI.getPointerTy(DAG.getDataLayout()),
4152 getValue(I.getArgOperand(0))));
4154 case Intrinsic::frameaddress:
4155 setValue(&I, DAG.getNode(ISD::FRAMEADDR, sdl,
4156 TLI.getPointerTy(DAG.getDataLayout()),
4157 getValue(I.getArgOperand(0))));
4159 case Intrinsic::read_register: {
4160 Value *Reg = I.getArgOperand(0);
4161 SDValue Chain = getRoot();
4163 DAG.getMDNode(cast<MDNode>(cast<MetadataAsValue>(Reg)->getMetadata()));
4164 EVT VT = TLI.getValueType(DAG.getDataLayout(), I.getType());
4165 Res = DAG.getNode(ISD::READ_REGISTER, sdl,
4166 DAG.getVTList(VT, MVT::Other), Chain, RegName);
4168 DAG.setRoot(Res.getValue(1));
4171 case Intrinsic::write_register: {
4172 Value *Reg = I.getArgOperand(0);
4173 Value *RegValue = I.getArgOperand(1);
4174 SDValue Chain = getRoot();
4176 DAG.getMDNode(cast<MDNode>(cast<MetadataAsValue>(Reg)->getMetadata()));
4177 DAG.setRoot(DAG.getNode(ISD::WRITE_REGISTER, sdl, MVT::Other, Chain,
4178 RegName, getValue(RegValue)));
4181 case Intrinsic::setjmp:
4182 return &"_setjmp"[!TLI.usesUnderscoreSetJmp()];
4183 case Intrinsic::longjmp:
4184 return &"_longjmp"[!TLI.usesUnderscoreLongJmp()];
4185 case Intrinsic::memcpy: {
4186 // FIXME: this definition of "user defined address space" is x86-specific
4187 // Assert for address < 256 since we support only user defined address
4189 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace()
4191 cast<PointerType>(I.getArgOperand(1)->getType())->getAddressSpace()
4193 "Unknown address space");
4194 SDValue Op1 = getValue(I.getArgOperand(0));
4195 SDValue Op2 = getValue(I.getArgOperand(1));
4196 SDValue Op3 = getValue(I.getArgOperand(2));
4197 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue();
4199 Align = 1; // @llvm.memcpy defines 0 and 1 to both mean no alignment.
4200 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue();
4201 bool isTC = I.isTailCall() && isInTailCallPosition(&I, DAG.getTarget());
4202 SDValue MC = DAG.getMemcpy(getRoot(), sdl, Op1, Op2, Op3, Align, isVol,
4204 MachinePointerInfo(I.getArgOperand(0)),
4205 MachinePointerInfo(I.getArgOperand(1)));
4206 updateDAGForMaybeTailCall(MC);
4209 case Intrinsic::memset: {
4210 // FIXME: this definition of "user defined address space" is x86-specific
4211 // Assert for address < 256 since we support only user defined address
4213 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace()
4215 "Unknown address space");
4216 SDValue Op1 = getValue(I.getArgOperand(0));
4217 SDValue Op2 = getValue(I.getArgOperand(1));
4218 SDValue Op3 = getValue(I.getArgOperand(2));
4219 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue();
4221 Align = 1; // @llvm.memset defines 0 and 1 to both mean no alignment.
4222 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue();
4223 bool isTC = I.isTailCall() && isInTailCallPosition(&I, DAG.getTarget());
4224 SDValue MS = DAG.getMemset(getRoot(), sdl, Op1, Op2, Op3, Align, isVol,
4225 isTC, MachinePointerInfo(I.getArgOperand(0)));
4226 updateDAGForMaybeTailCall(MS);
4229 case Intrinsic::memmove: {
4230 // FIXME: this definition of "user defined address space" is x86-specific
4231 // Assert for address < 256 since we support only user defined address
4233 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace()
4235 cast<PointerType>(I.getArgOperand(1)->getType())->getAddressSpace()
4237 "Unknown address space");
4238 SDValue Op1 = getValue(I.getArgOperand(0));
4239 SDValue Op2 = getValue(I.getArgOperand(1));
4240 SDValue Op3 = getValue(I.getArgOperand(2));
4241 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue();
4243 Align = 1; // @llvm.memmove defines 0 and 1 to both mean no alignment.
4244 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue();
4245 bool isTC = I.isTailCall() && isInTailCallPosition(&I, DAG.getTarget());
4246 SDValue MM = DAG.getMemmove(getRoot(), sdl, Op1, Op2, Op3, Align, isVol,
4247 isTC, MachinePointerInfo(I.getArgOperand(0)),
4248 MachinePointerInfo(I.getArgOperand(1)));
4249 updateDAGForMaybeTailCall(MM);
4252 case Intrinsic::dbg_declare: {
4253 const DbgDeclareInst &DI = cast<DbgDeclareInst>(I);
4254 DILocalVariable *Variable = DI.getVariable();
4255 DIExpression *Expression = DI.getExpression();
4256 const Value *Address = DI.getAddress();
4257 assert(Variable && "Missing variable");
4259 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
4263 // Check if address has undef value.
4264 if (isa<UndefValue>(Address) ||
4265 (Address->use_empty() && !isa<Argument>(Address))) {
4266 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
4270 SDValue &N = NodeMap[Address];
4271 if (!N.getNode() && isa<Argument>(Address))
4272 // Check unused arguments map.
4273 N = UnusedArgNodeMap[Address];
4276 if (const BitCastInst *BCI = dyn_cast<BitCastInst>(Address))
4277 Address = BCI->getOperand(0);
4278 // Parameters are handled specially.
4279 bool isParameter = Variable->isParameter() || isa<Argument>(Address);
4281 const AllocaInst *AI = dyn_cast<AllocaInst>(Address);
4283 if (isParameter && !AI) {
4284 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(N.getNode());
4286 // Byval parameter. We have a frame index at this point.
4287 SDV = DAG.getFrameIndexDbgValue(
4288 Variable, Expression, FINode->getIndex(), 0, dl, SDNodeOrder);
4290 // Address is an argument, so try to emit its dbg value using
4291 // virtual register info from the FuncInfo.ValueMap.
4292 EmitFuncArgumentDbgValue(Address, Variable, Expression, dl, 0, false,
4297 SDV = DAG.getDbgValue(Variable, Expression, N.getNode(), N.getResNo(),
4298 true, 0, dl, SDNodeOrder);
4300 // Can't do anything with other non-AI cases yet.
4301 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
4302 DEBUG(dbgs() << "non-AllocaInst issue for Address: \n\t");
4303 DEBUG(Address->dump());
4306 DAG.AddDbgValue(SDV, N.getNode(), isParameter);
4308 // If Address is an argument then try to emit its dbg value using
4309 // virtual register info from the FuncInfo.ValueMap.
4310 if (!EmitFuncArgumentDbgValue(Address, Variable, Expression, dl, 0, false,
4312 // If variable is pinned by a alloca in dominating bb then
4313 // use StaticAllocaMap.
4314 if (const AllocaInst *AI = dyn_cast<AllocaInst>(Address)) {
4315 if (AI->getParent() != DI.getParent()) {
4316 DenseMap<const AllocaInst*, int>::iterator SI =
4317 FuncInfo.StaticAllocaMap.find(AI);
4318 if (SI != FuncInfo.StaticAllocaMap.end()) {
4319 SDV = DAG.getFrameIndexDbgValue(Variable, Expression, SI->second,
4320 0, dl, SDNodeOrder);
4321 DAG.AddDbgValue(SDV, nullptr, false);
4326 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
4331 case Intrinsic::dbg_value: {
4332 const DbgValueInst &DI = cast<DbgValueInst>(I);
4333 assert(DI.getVariable() && "Missing variable");
4335 DILocalVariable *Variable = DI.getVariable();
4336 DIExpression *Expression = DI.getExpression();
4337 uint64_t Offset = DI.getOffset();
4338 const Value *V = DI.getValue();
4343 if (isa<ConstantInt>(V) || isa<ConstantFP>(V) || isa<UndefValue>(V)) {
4344 SDV = DAG.getConstantDbgValue(Variable, Expression, V, Offset, dl,
4346 DAG.AddDbgValue(SDV, nullptr, false);
4348 // Do not use getValue() in here; we don't want to generate code at
4349 // this point if it hasn't been done yet.
4350 SDValue N = NodeMap[V];
4351 if (!N.getNode() && isa<Argument>(V))
4352 // Check unused arguments map.
4353 N = UnusedArgNodeMap[V];
4355 // A dbg.value for an alloca is always indirect.
4356 bool IsIndirect = isa<AllocaInst>(V) || Offset != 0;
4357 if (!EmitFuncArgumentDbgValue(V, Variable, Expression, dl, Offset,
4359 SDV = DAG.getDbgValue(Variable, Expression, N.getNode(), N.getResNo(),
4360 IsIndirect, Offset, dl, SDNodeOrder);
4361 DAG.AddDbgValue(SDV, N.getNode(), false);
4363 } else if (!V->use_empty() ) {
4364 // Do not call getValue(V) yet, as we don't want to generate code.
4365 // Remember it for later.
4366 DanglingDebugInfo DDI(&DI, dl, SDNodeOrder);
4367 DanglingDebugInfoMap[V] = DDI;
4369 // We may expand this to cover more cases. One case where we have no
4370 // data available is an unreferenced parameter.
4371 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
4375 // Build a debug info table entry.
4376 if (const BitCastInst *BCI = dyn_cast<BitCastInst>(V))
4377 V = BCI->getOperand(0);
4378 const AllocaInst *AI = dyn_cast<AllocaInst>(V);
4379 // Don't handle byval struct arguments or VLAs, for example.
4381 DEBUG(dbgs() << "Dropping debug location info for:\n " << DI << "\n");
4382 DEBUG(dbgs() << " Last seen at:\n " << *V << "\n");
4385 DenseMap<const AllocaInst*, int>::iterator SI =
4386 FuncInfo.StaticAllocaMap.find(AI);
4387 if (SI == FuncInfo.StaticAllocaMap.end())
4388 return nullptr; // VLAs.
4392 case Intrinsic::eh_typeid_for: {
4393 // Find the type id for the given typeinfo.
4394 GlobalValue *GV = ExtractTypeInfo(I.getArgOperand(0));
4395 unsigned TypeID = DAG.getMachineFunction().getMMI().getTypeIDFor(GV);
4396 Res = DAG.getConstant(TypeID, sdl, MVT::i32);
4401 case Intrinsic::eh_return_i32:
4402 case Intrinsic::eh_return_i64:
4403 DAG.getMachineFunction().getMMI().setCallsEHReturn(true);
4404 DAG.setRoot(DAG.getNode(ISD::EH_RETURN, sdl,
4407 getValue(I.getArgOperand(0)),
4408 getValue(I.getArgOperand(1))));
4410 case Intrinsic::eh_unwind_init:
4411 DAG.getMachineFunction().getMMI().setCallsUnwindInit(true);
4413 case Intrinsic::eh_dwarf_cfa: {
4414 SDValue CfaArg = DAG.getSExtOrTrunc(getValue(I.getArgOperand(0)), sdl,
4415 TLI.getPointerTy(DAG.getDataLayout()));
4416 SDValue Offset = DAG.getNode(ISD::ADD, sdl,
4417 CfaArg.getValueType(),
4418 DAG.getNode(ISD::FRAME_TO_ARGS_OFFSET, sdl,
4419 CfaArg.getValueType()),
4421 SDValue FA = DAG.getNode(
4422 ISD::FRAMEADDR, sdl, TLI.getPointerTy(DAG.getDataLayout()),
4423 DAG.getConstant(0, sdl, TLI.getPointerTy(DAG.getDataLayout())));
4424 setValue(&I, DAG.getNode(ISD::ADD, sdl, FA.getValueType(),
4428 case Intrinsic::eh_sjlj_callsite: {
4429 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
4430 ConstantInt *CI = dyn_cast<ConstantInt>(I.getArgOperand(0));
4431 assert(CI && "Non-constant call site value in eh.sjlj.callsite!");
4432 assert(MMI.getCurrentCallSite() == 0 && "Overlapping call sites!");
4434 MMI.setCurrentCallSite(CI->getZExtValue());
4437 case Intrinsic::eh_sjlj_functioncontext: {
4438 // Get and store the index of the function context.
4439 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
4441 cast<AllocaInst>(I.getArgOperand(0)->stripPointerCasts());
4442 int FI = FuncInfo.StaticAllocaMap[FnCtx];
4443 MFI->setFunctionContextIndex(FI);
4446 case Intrinsic::eh_sjlj_setjmp: {
4449 Ops[1] = getValue(I.getArgOperand(0));
4450 SDValue Op = DAG.getNode(ISD::EH_SJLJ_SETJMP, sdl,
4451 DAG.getVTList(MVT::i32, MVT::Other), Ops);
4452 setValue(&I, Op.getValue(0));
4453 DAG.setRoot(Op.getValue(1));
4456 case Intrinsic::eh_sjlj_longjmp: {
4457 DAG.setRoot(DAG.getNode(ISD::EH_SJLJ_LONGJMP, sdl, MVT::Other,
4458 getRoot(), getValue(I.getArgOperand(0))));
4461 case Intrinsic::eh_sjlj_setup_dispatch: {
4462 DAG.setRoot(DAG.getNode(ISD::EH_SJLJ_SETUP_DISPATCH, sdl, MVT::Other,
4467 case Intrinsic::masked_gather:
4468 visitMaskedGather(I);
4470 case Intrinsic::masked_load:
4473 case Intrinsic::masked_scatter:
4474 visitMaskedScatter(I);
4476 case Intrinsic::masked_store:
4477 visitMaskedStore(I);
4479 case Intrinsic::x86_mmx_pslli_w:
4480 case Intrinsic::x86_mmx_pslli_d:
4481 case Intrinsic::x86_mmx_pslli_q:
4482 case Intrinsic::x86_mmx_psrli_w:
4483 case Intrinsic::x86_mmx_psrli_d:
4484 case Intrinsic::x86_mmx_psrli_q:
4485 case Intrinsic::x86_mmx_psrai_w:
4486 case Intrinsic::x86_mmx_psrai_d: {
4487 SDValue ShAmt = getValue(I.getArgOperand(1));
4488 if (isa<ConstantSDNode>(ShAmt)) {
4489 visitTargetIntrinsic(I, Intrinsic);
4492 unsigned NewIntrinsic = 0;
4493 EVT ShAmtVT = MVT::v2i32;
4494 switch (Intrinsic) {
4495 case Intrinsic::x86_mmx_pslli_w:
4496 NewIntrinsic = Intrinsic::x86_mmx_psll_w;
4498 case Intrinsic::x86_mmx_pslli_d:
4499 NewIntrinsic = Intrinsic::x86_mmx_psll_d;
4501 case Intrinsic::x86_mmx_pslli_q:
4502 NewIntrinsic = Intrinsic::x86_mmx_psll_q;
4504 case Intrinsic::x86_mmx_psrli_w:
4505 NewIntrinsic = Intrinsic::x86_mmx_psrl_w;
4507 case Intrinsic::x86_mmx_psrli_d:
4508 NewIntrinsic = Intrinsic::x86_mmx_psrl_d;
4510 case Intrinsic::x86_mmx_psrli_q:
4511 NewIntrinsic = Intrinsic::x86_mmx_psrl_q;
4513 case Intrinsic::x86_mmx_psrai_w:
4514 NewIntrinsic = Intrinsic::x86_mmx_psra_w;
4516 case Intrinsic::x86_mmx_psrai_d:
4517 NewIntrinsic = Intrinsic::x86_mmx_psra_d;
4519 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
4522 // The vector shift intrinsics with scalars uses 32b shift amounts but
4523 // the sse2/mmx shift instructions reads 64 bits. Set the upper 32 bits
4525 // We must do this early because v2i32 is not a legal type.
4528 ShOps[1] = DAG.getConstant(0, sdl, MVT::i32);
4529 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, sdl, ShAmtVT, ShOps);
4530 EVT DestVT = TLI.getValueType(DAG.getDataLayout(), I.getType());
4531 ShAmt = DAG.getNode(ISD::BITCAST, sdl, DestVT, ShAmt);
4532 Res = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, sdl, DestVT,
4533 DAG.getConstant(NewIntrinsic, sdl, MVT::i32),
4534 getValue(I.getArgOperand(0)), ShAmt);
4538 case Intrinsic::convertff:
4539 case Intrinsic::convertfsi:
4540 case Intrinsic::convertfui:
4541 case Intrinsic::convertsif:
4542 case Intrinsic::convertuif:
4543 case Intrinsic::convertss:
4544 case Intrinsic::convertsu:
4545 case Intrinsic::convertus:
4546 case Intrinsic::convertuu: {
4547 ISD::CvtCode Code = ISD::CVT_INVALID;
4548 switch (Intrinsic) {
4549 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
4550 case Intrinsic::convertff: Code = ISD::CVT_FF; break;
4551 case Intrinsic::convertfsi: Code = ISD::CVT_FS; break;
4552 case Intrinsic::convertfui: Code = ISD::CVT_FU; break;
4553 case Intrinsic::convertsif: Code = ISD::CVT_SF; break;
4554 case Intrinsic::convertuif: Code = ISD::CVT_UF; break;
4555 case Intrinsic::convertss: Code = ISD::CVT_SS; break;
4556 case Intrinsic::convertsu: Code = ISD::CVT_SU; break;
4557 case Intrinsic::convertus: Code = ISD::CVT_US; break;
4558 case Intrinsic::convertuu: Code = ISD::CVT_UU; break;
4560 EVT DestVT = TLI.getValueType(DAG.getDataLayout(), I.getType());
4561 const Value *Op1 = I.getArgOperand(0);
4562 Res = DAG.getConvertRndSat(DestVT, sdl, getValue(Op1),
4563 DAG.getValueType(DestVT),
4564 DAG.getValueType(getValue(Op1).getValueType()),
4565 getValue(I.getArgOperand(1)),
4566 getValue(I.getArgOperand(2)),
4571 case Intrinsic::powi:
4572 setValue(&I, ExpandPowI(sdl, getValue(I.getArgOperand(0)),
4573 getValue(I.getArgOperand(1)), DAG));
4575 case Intrinsic::log:
4576 setValue(&I, expandLog(sdl, getValue(I.getArgOperand(0)), DAG, TLI));
4578 case Intrinsic::log2:
4579 setValue(&I, expandLog2(sdl, getValue(I.getArgOperand(0)), DAG, TLI));
4581 case Intrinsic::log10:
4582 setValue(&I, expandLog10(sdl, getValue(I.getArgOperand(0)), DAG, TLI));
4584 case Intrinsic::exp:
4585 setValue(&I, expandExp(sdl, getValue(I.getArgOperand(0)), DAG, TLI));
4587 case Intrinsic::exp2:
4588 setValue(&I, expandExp2(sdl, getValue(I.getArgOperand(0)), DAG, TLI));
4590 case Intrinsic::pow:
4591 setValue(&I, expandPow(sdl, getValue(I.getArgOperand(0)),
4592 getValue(I.getArgOperand(1)), DAG, TLI));
4594 case Intrinsic::sqrt:
4595 case Intrinsic::fabs:
4596 case Intrinsic::sin:
4597 case Intrinsic::cos:
4598 case Intrinsic::floor:
4599 case Intrinsic::ceil:
4600 case Intrinsic::trunc:
4601 case Intrinsic::rint:
4602 case Intrinsic::nearbyint:
4603 case Intrinsic::round: {
4605 switch (Intrinsic) {
4606 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
4607 case Intrinsic::sqrt: Opcode = ISD::FSQRT; break;
4608 case Intrinsic::fabs: Opcode = ISD::FABS; break;
4609 case Intrinsic::sin: Opcode = ISD::FSIN; break;
4610 case Intrinsic::cos: Opcode = ISD::FCOS; break;
4611 case Intrinsic::floor: Opcode = ISD::FFLOOR; break;
4612 case Intrinsic::ceil: Opcode = ISD::FCEIL; break;
4613 case Intrinsic::trunc: Opcode = ISD::FTRUNC; break;
4614 case Intrinsic::rint: Opcode = ISD::FRINT; break;
4615 case Intrinsic::nearbyint: Opcode = ISD::FNEARBYINT; break;
4616 case Intrinsic::round: Opcode = ISD::FROUND; break;
4619 setValue(&I, DAG.getNode(Opcode, sdl,
4620 getValue(I.getArgOperand(0)).getValueType(),
4621 getValue(I.getArgOperand(0))));
4624 case Intrinsic::minnum:
4625 setValue(&I, DAG.getNode(ISD::FMINNUM, sdl,
4626 getValue(I.getArgOperand(0)).getValueType(),
4627 getValue(I.getArgOperand(0)),
4628 getValue(I.getArgOperand(1))));
4630 case Intrinsic::maxnum:
4631 setValue(&I, DAG.getNode(ISD::FMAXNUM, sdl,
4632 getValue(I.getArgOperand(0)).getValueType(),
4633 getValue(I.getArgOperand(0)),
4634 getValue(I.getArgOperand(1))));
4636 case Intrinsic::copysign:
4637 setValue(&I, DAG.getNode(ISD::FCOPYSIGN, sdl,
4638 getValue(I.getArgOperand(0)).getValueType(),
4639 getValue(I.getArgOperand(0)),
4640 getValue(I.getArgOperand(1))));
4642 case Intrinsic::fma:
4643 setValue(&I, DAG.getNode(ISD::FMA, sdl,
4644 getValue(I.getArgOperand(0)).getValueType(),
4645 getValue(I.getArgOperand(0)),
4646 getValue(I.getArgOperand(1)),
4647 getValue(I.getArgOperand(2))));
4649 case Intrinsic::fmuladd: {
4650 EVT VT = TLI.getValueType(DAG.getDataLayout(), I.getType());
4651 if (TM.Options.AllowFPOpFusion != FPOpFusion::Strict &&
4652 TLI.isFMAFasterThanFMulAndFAdd(VT)) {
4653 setValue(&I, DAG.getNode(ISD::FMA, sdl,
4654 getValue(I.getArgOperand(0)).getValueType(),
4655 getValue(I.getArgOperand(0)),
4656 getValue(I.getArgOperand(1)),
4657 getValue(I.getArgOperand(2))));
4659 SDValue Mul = DAG.getNode(ISD::FMUL, sdl,
4660 getValue(I.getArgOperand(0)).getValueType(),
4661 getValue(I.getArgOperand(0)),
4662 getValue(I.getArgOperand(1)));
4663 SDValue Add = DAG.getNode(ISD::FADD, sdl,
4664 getValue(I.getArgOperand(0)).getValueType(),
4666 getValue(I.getArgOperand(2)));
4671 case Intrinsic::convert_to_fp16:
4672 setValue(&I, DAG.getNode(ISD::BITCAST, sdl, MVT::i16,
4673 DAG.getNode(ISD::FP_ROUND, sdl, MVT::f16,
4674 getValue(I.getArgOperand(0)),
4675 DAG.getTargetConstant(0, sdl,
4678 case Intrinsic::convert_from_fp16:
4679 setValue(&I, DAG.getNode(ISD::FP_EXTEND, sdl,
4680 TLI.getValueType(DAG.getDataLayout(), I.getType()),
4681 DAG.getNode(ISD::BITCAST, sdl, MVT::f16,
4682 getValue(I.getArgOperand(0)))));
4684 case Intrinsic::pcmarker: {
4685 SDValue Tmp = getValue(I.getArgOperand(0));
4686 DAG.setRoot(DAG.getNode(ISD::PCMARKER, sdl, MVT::Other, getRoot(), Tmp));
4689 case Intrinsic::readcyclecounter: {
4690 SDValue Op = getRoot();
4691 Res = DAG.getNode(ISD::READCYCLECOUNTER, sdl,
4692 DAG.getVTList(MVT::i64, MVT::Other), Op);
4694 DAG.setRoot(Res.getValue(1));
4697 case Intrinsic::bswap:
4698 setValue(&I, DAG.getNode(ISD::BSWAP, sdl,
4699 getValue(I.getArgOperand(0)).getValueType(),
4700 getValue(I.getArgOperand(0))));
4702 case Intrinsic::uabsdiff:
4703 setValue(&I, DAG.getNode(ISD::UABSDIFF, sdl,
4704 getValue(I.getArgOperand(0)).getValueType(),
4705 getValue(I.getArgOperand(0)),
4706 getValue(I.getArgOperand(1))));
4708 case Intrinsic::sabsdiff:
4709 setValue(&I, DAG.getNode(ISD::SABSDIFF, sdl,
4710 getValue(I.getArgOperand(0)).getValueType(),
4711 getValue(I.getArgOperand(0)),
4712 getValue(I.getArgOperand(1))));
4714 case Intrinsic::cttz: {
4715 SDValue Arg = getValue(I.getArgOperand(0));
4716 ConstantInt *CI = cast<ConstantInt>(I.getArgOperand(1));
4717 EVT Ty = Arg.getValueType();
4718 setValue(&I, DAG.getNode(CI->isZero() ? ISD::CTTZ : ISD::CTTZ_ZERO_UNDEF,
4722 case Intrinsic::ctlz: {
4723 SDValue Arg = getValue(I.getArgOperand(0));
4724 ConstantInt *CI = cast<ConstantInt>(I.getArgOperand(1));
4725 EVT Ty = Arg.getValueType();
4726 setValue(&I, DAG.getNode(CI->isZero() ? ISD::CTLZ : ISD::CTLZ_ZERO_UNDEF,
4730 case Intrinsic::ctpop: {
4731 SDValue Arg = getValue(I.getArgOperand(0));
4732 EVT Ty = Arg.getValueType();
4733 setValue(&I, DAG.getNode(ISD::CTPOP, sdl, Ty, Arg));
4736 case Intrinsic::stacksave: {
4737 SDValue Op = getRoot();
4739 ISD::STACKSAVE, sdl,
4740 DAG.getVTList(TLI.getPointerTy(DAG.getDataLayout()), MVT::Other), Op);
4742 DAG.setRoot(Res.getValue(1));
4745 case Intrinsic::stackrestore: {
4746 Res = getValue(I.getArgOperand(0));
4747 DAG.setRoot(DAG.getNode(ISD::STACKRESTORE, sdl, MVT::Other, getRoot(), Res));
4750 case Intrinsic::stackprotector: {
4751 // Emit code into the DAG to store the stack guard onto the stack.
4752 MachineFunction &MF = DAG.getMachineFunction();
4753 MachineFrameInfo *MFI = MF.getFrameInfo();
4754 EVT PtrTy = TLI.getPointerTy(DAG.getDataLayout());
4755 SDValue Src, Chain = getRoot();
4756 const Value *Ptr = cast<LoadInst>(I.getArgOperand(0))->getPointerOperand();
4757 const GlobalVariable *GV = dyn_cast<GlobalVariable>(Ptr);
4759 // See if Ptr is a bitcast. If it is, look through it and see if we can get
4760 // global variable __stack_chk_guard.
4762 if (const Operator *BC = dyn_cast<Operator>(Ptr))
4763 if (BC->getOpcode() == Instruction::BitCast)
4764 GV = dyn_cast<GlobalVariable>(BC->getOperand(0));
4766 if (GV && TLI.useLoadStackGuardNode()) {
4767 // Emit a LOAD_STACK_GUARD node.
4768 MachineSDNode *Node = DAG.getMachineNode(TargetOpcode::LOAD_STACK_GUARD,
4770 MachinePointerInfo MPInfo(GV);
4771 MachineInstr::mmo_iterator MemRefs = MF.allocateMemRefsArray(1);
4772 unsigned Flags = MachineMemOperand::MOLoad |
4773 MachineMemOperand::MOInvariant;
4774 *MemRefs = MF.getMachineMemOperand(MPInfo, Flags,
4775 PtrTy.getSizeInBits() / 8,
4776 DAG.getEVTAlignment(PtrTy));
4777 Node->setMemRefs(MemRefs, MemRefs + 1);
4779 // Copy the guard value to a virtual register so that it can be
4780 // retrieved in the epilogue.
4781 Src = SDValue(Node, 0);
4782 const TargetRegisterClass *RC =
4783 TLI.getRegClassFor(Src.getSimpleValueType());
4784 unsigned Reg = MF.getRegInfo().createVirtualRegister(RC);
4786 SPDescriptor.setGuardReg(Reg);
4787 Chain = DAG.getCopyToReg(Chain, sdl, Reg, Src);
4789 Src = getValue(I.getArgOperand(0)); // The guard's value.
4792 AllocaInst *Slot = cast<AllocaInst>(I.getArgOperand(1));
4794 int FI = FuncInfo.StaticAllocaMap[Slot];
4795 MFI->setStackProtectorIndex(FI);
4797 SDValue FIN = DAG.getFrameIndex(FI, PtrTy);
4799 // Store the stack protector onto the stack.
4800 Res = DAG.getStore(Chain, sdl, Src, FIN, MachinePointerInfo::getFixedStack(
4801 DAG.getMachineFunction(), FI),
4807 case Intrinsic::objectsize: {
4808 // If we don't know by now, we're never going to know.
4809 ConstantInt *CI = dyn_cast<ConstantInt>(I.getArgOperand(1));
4811 assert(CI && "Non-constant type in __builtin_object_size?");
4813 SDValue Arg = getValue(I.getCalledValue());
4814 EVT Ty = Arg.getValueType();
4817 Res = DAG.getConstant(-1ULL, sdl, Ty);
4819 Res = DAG.getConstant(0, sdl, Ty);
4824 case Intrinsic::annotation:
4825 case Intrinsic::ptr_annotation:
4826 // Drop the intrinsic, but forward the value
4827 setValue(&I, getValue(I.getOperand(0)));
4829 case Intrinsic::assume:
4830 case Intrinsic::var_annotation:
4831 // Discard annotate attributes and assumptions
4834 case Intrinsic::init_trampoline: {
4835 const Function *F = cast<Function>(I.getArgOperand(1)->stripPointerCasts());
4839 Ops[1] = getValue(I.getArgOperand(0));
4840 Ops[2] = getValue(I.getArgOperand(1));
4841 Ops[3] = getValue(I.getArgOperand(2));
4842 Ops[4] = DAG.getSrcValue(I.getArgOperand(0));
4843 Ops[5] = DAG.getSrcValue(F);
4845 Res = DAG.getNode(ISD::INIT_TRAMPOLINE, sdl, MVT::Other, Ops);
4850 case Intrinsic::adjust_trampoline: {
4851 setValue(&I, DAG.getNode(ISD::ADJUST_TRAMPOLINE, sdl,
4852 TLI.getPointerTy(DAG.getDataLayout()),
4853 getValue(I.getArgOperand(0))));
4856 case Intrinsic::gcroot:
4858 const Value *Alloca = I.getArgOperand(0)->stripPointerCasts();
4859 const Constant *TypeMap = cast<Constant>(I.getArgOperand(1));
4861 FrameIndexSDNode *FI = cast<FrameIndexSDNode>(getValue(Alloca).getNode());
4862 GFI->addStackRoot(FI->getIndex(), TypeMap);
4865 case Intrinsic::gcread:
4866 case Intrinsic::gcwrite:
4867 llvm_unreachable("GC failed to lower gcread/gcwrite intrinsics!");
4868 case Intrinsic::flt_rounds:
4869 setValue(&I, DAG.getNode(ISD::FLT_ROUNDS_, sdl, MVT::i32));
4872 case Intrinsic::expect: {
4873 // Just replace __builtin_expect(exp, c) with EXP.
4874 setValue(&I, getValue(I.getArgOperand(0)));
4878 case Intrinsic::debugtrap:
4879 case Intrinsic::trap: {
4880 StringRef TrapFuncName =
4882 .getAttribute(AttributeSet::FunctionIndex, "trap-func-name")
4883 .getValueAsString();
4884 if (TrapFuncName.empty()) {
4885 ISD::NodeType Op = (Intrinsic == Intrinsic::trap) ?
4886 ISD::TRAP : ISD::DEBUGTRAP;
4887 DAG.setRoot(DAG.getNode(Op, sdl,MVT::Other, getRoot()));
4890 TargetLowering::ArgListTy Args;
4892 TargetLowering::CallLoweringInfo CLI(DAG);
4893 CLI.setDebugLoc(sdl).setChain(getRoot()).setCallee(
4894 CallingConv::C, I.getType(),
4895 DAG.getExternalSymbol(TrapFuncName.data(),
4896 TLI.getPointerTy(DAG.getDataLayout())),
4897 std::move(Args), 0);
4899 std::pair<SDValue, SDValue> Result = TLI.LowerCallTo(CLI);
4900 DAG.setRoot(Result.second);
4904 case Intrinsic::uadd_with_overflow:
4905 case Intrinsic::sadd_with_overflow:
4906 case Intrinsic::usub_with_overflow:
4907 case Intrinsic::ssub_with_overflow:
4908 case Intrinsic::umul_with_overflow:
4909 case Intrinsic::smul_with_overflow: {
4911 switch (Intrinsic) {
4912 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
4913 case Intrinsic::uadd_with_overflow: Op = ISD::UADDO; break;
4914 case Intrinsic::sadd_with_overflow: Op = ISD::SADDO; break;
4915 case Intrinsic::usub_with_overflow: Op = ISD::USUBO; break;
4916 case Intrinsic::ssub_with_overflow: Op = ISD::SSUBO; break;
4917 case Intrinsic::umul_with_overflow: Op = ISD::UMULO; break;
4918 case Intrinsic::smul_with_overflow: Op = ISD::SMULO; break;
4920 SDValue Op1 = getValue(I.getArgOperand(0));
4921 SDValue Op2 = getValue(I.getArgOperand(1));
4923 SDVTList VTs = DAG.getVTList(Op1.getValueType(), MVT::i1);
4924 setValue(&I, DAG.getNode(Op, sdl, VTs, Op1, Op2));
4927 case Intrinsic::prefetch: {
4929 unsigned rw = cast<ConstantInt>(I.getArgOperand(1))->getZExtValue();
4931 Ops[1] = getValue(I.getArgOperand(0));
4932 Ops[2] = getValue(I.getArgOperand(1));
4933 Ops[3] = getValue(I.getArgOperand(2));
4934 Ops[4] = getValue(I.getArgOperand(3));
4935 DAG.setRoot(DAG.getMemIntrinsicNode(ISD::PREFETCH, sdl,
4936 DAG.getVTList(MVT::Other), Ops,
4937 EVT::getIntegerVT(*Context, 8),
4938 MachinePointerInfo(I.getArgOperand(0)),
4940 false, /* volatile */
4942 rw==1)); /* write */
4945 case Intrinsic::lifetime_start:
4946 case Intrinsic::lifetime_end: {
4947 bool IsStart = (Intrinsic == Intrinsic::lifetime_start);
4948 // Stack coloring is not enabled in O0, discard region information.
4949 if (TM.getOptLevel() == CodeGenOpt::None)
4952 SmallVector<Value *, 4> Allocas;
4953 GetUnderlyingObjects(I.getArgOperand(1), Allocas, *DL);
4955 for (SmallVectorImpl<Value*>::iterator Object = Allocas.begin(),
4956 E = Allocas.end(); Object != E; ++Object) {
4957 AllocaInst *LifetimeObject = dyn_cast_or_null<AllocaInst>(*Object);
4959 // Could not find an Alloca.
4960 if (!LifetimeObject)
4963 // First check that the Alloca is static, otherwise it won't have a
4964 // valid frame index.
4965 auto SI = FuncInfo.StaticAllocaMap.find(LifetimeObject);
4966 if (SI == FuncInfo.StaticAllocaMap.end())
4969 int FI = SI->second;
4974 DAG.getFrameIndex(FI, TLI.getPointerTy(DAG.getDataLayout()), true);
4975 unsigned Opcode = (IsStart ? ISD::LIFETIME_START : ISD::LIFETIME_END);
4977 Res = DAG.getNode(Opcode, sdl, MVT::Other, Ops);
4982 case Intrinsic::invariant_start:
4983 // Discard region information.
4984 setValue(&I, DAG.getUNDEF(TLI.getPointerTy(DAG.getDataLayout())));
4986 case Intrinsic::invariant_end:
4987 // Discard region information.
4989 case Intrinsic::stackprotectorcheck: {
4990 // Do not actually emit anything for this basic block. Instead we initialize
4991 // the stack protector descriptor and export the guard variable so we can
4992 // access it in FinishBasicBlock.
4993 const BasicBlock *BB = I.getParent();
4994 SPDescriptor.initialize(BB, FuncInfo.MBBMap[BB], I);
4995 ExportFromCurrentBlock(SPDescriptor.getGuard());
4997 // Flush our exports since we are going to process a terminator.
4998 (void)getControlRoot();
5001 case Intrinsic::clear_cache:
5002 return TLI.getClearCacheBuiltinName();
5003 case Intrinsic::eh_actions:
5004 setValue(&I, DAG.getUNDEF(TLI.getPointerTy(DAG.getDataLayout())));
5006 case Intrinsic::donothing:
5009 case Intrinsic::experimental_stackmap: {
5013 case Intrinsic::experimental_patchpoint_void:
5014 case Intrinsic::experimental_patchpoint_i64: {
5015 visitPatchpoint(&I);
5018 case Intrinsic::experimental_gc_statepoint: {
5022 case Intrinsic::experimental_gc_result_int:
5023 case Intrinsic::experimental_gc_result_float:
5024 case Intrinsic::experimental_gc_result_ptr:
5025 case Intrinsic::experimental_gc_result: {
5029 case Intrinsic::experimental_gc_relocate: {
5033 case Intrinsic::instrprof_increment:
5034 llvm_unreachable("instrprof failed to lower an increment");
5036 case Intrinsic::localescape: {
5037 MachineFunction &MF = DAG.getMachineFunction();
5038 const TargetInstrInfo *TII = DAG.getSubtarget().getInstrInfo();
5040 // Directly emit some LOCAL_ESCAPE machine instrs. Label assignment emission
5041 // is the same on all targets.
5042 for (unsigned Idx = 0, E = I.getNumArgOperands(); Idx < E; ++Idx) {
5043 Value *Arg = I.getArgOperand(Idx)->stripPointerCasts();
5044 if (isa<ConstantPointerNull>(Arg))
5045 continue; // Skip null pointers. They represent a hole in index space.
5046 AllocaInst *Slot = cast<AllocaInst>(Arg);
5047 assert(FuncInfo.StaticAllocaMap.count(Slot) &&
5048 "can only escape static allocas");
5049 int FI = FuncInfo.StaticAllocaMap[Slot];
5050 MCSymbol *FrameAllocSym =
5051 MF.getMMI().getContext().getOrCreateFrameAllocSymbol(
5052 GlobalValue::getRealLinkageName(MF.getName()), Idx);
5053 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, dl,
5054 TII->get(TargetOpcode::LOCAL_ESCAPE))
5055 .addSym(FrameAllocSym)
5062 case Intrinsic::localrecover: {
5063 // i8* @llvm.localrecover(i8* %fn, i8* %fp, i32 %idx)
5064 MachineFunction &MF = DAG.getMachineFunction();
5065 MVT PtrVT = TLI.getPointerTy(DAG.getDataLayout(), 0);
5067 // Get the symbol that defines the frame offset.
5068 auto *Fn = cast<Function>(I.getArgOperand(0)->stripPointerCasts());
5069 auto *Idx = cast<ConstantInt>(I.getArgOperand(2));
5070 unsigned IdxVal = unsigned(Idx->getLimitedValue(INT_MAX));
5071 MCSymbol *FrameAllocSym =
5072 MF.getMMI().getContext().getOrCreateFrameAllocSymbol(
5073 GlobalValue::getRealLinkageName(Fn->getName()), IdxVal);
5075 // Create a MCSymbol for the label to avoid any target lowering
5076 // that would make this PC relative.
5077 SDValue OffsetSym = DAG.getMCSymbol(FrameAllocSym, PtrVT);
5079 DAG.getNode(ISD::LOCAL_RECOVER, sdl, PtrVT, OffsetSym);
5081 // Add the offset to the FP.
5082 Value *FP = I.getArgOperand(1);
5083 SDValue FPVal = getValue(FP);
5084 SDValue Add = DAG.getNode(ISD::ADD, sdl, PtrVT, FPVal, OffsetVal);
5089 case Intrinsic::eh_begincatch:
5090 case Intrinsic::eh_endcatch:
5091 llvm_unreachable("begin/end catch intrinsics not lowered in codegen");
5092 case Intrinsic::eh_exceptioncode: {
5093 unsigned Reg = TLI.getExceptionPointerRegister();
5094 assert(Reg && "cannot get exception code on this platform");
5095 MVT PtrVT = TLI.getPointerTy(DAG.getDataLayout());
5096 const TargetRegisterClass *PtrRC = TLI.getRegClassFor(PtrVT);
5097 assert(FuncInfo.MBB->isLandingPad() && "eh.exceptioncode in non-lpad");
5098 unsigned VReg = FuncInfo.MBB->addLiveIn(Reg, PtrRC);
5100 DAG.getCopyFromReg(DAG.getEntryNode(), getCurSDLoc(), VReg, PtrVT);
5101 N = DAG.getZExtOrTrunc(N, getCurSDLoc(), MVT::i32);
5108 std::pair<SDValue, SDValue>
5109 SelectionDAGBuilder::lowerInvokable(TargetLowering::CallLoweringInfo &CLI,
5110 MachineBasicBlock *LandingPad) {
5111 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
5112 MCSymbol *BeginLabel = nullptr;
5115 // Insert a label before the invoke call to mark the try range. This can be
5116 // used to detect deletion of the invoke via the MachineModuleInfo.
5117 BeginLabel = MMI.getContext().createTempSymbol();
5119 // For SjLj, keep track of which landing pads go with which invokes
5120 // so as to maintain the ordering of pads in the LSDA.
5121 unsigned CallSiteIndex = MMI.getCurrentCallSite();
5122 if (CallSiteIndex) {
5123 MMI.setCallSiteBeginLabel(BeginLabel, CallSiteIndex);
5124 LPadToCallSiteMap[LandingPad].push_back(CallSiteIndex);
5126 // Now that the call site is handled, stop tracking it.
5127 MMI.setCurrentCallSite(0);
5130 // Both PendingLoads and PendingExports must be flushed here;
5131 // this call might not return.
5133 DAG.setRoot(DAG.getEHLabel(getCurSDLoc(), getControlRoot(), BeginLabel));
5135 CLI.setChain(getRoot());
5137 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5138 std::pair<SDValue, SDValue> Result = TLI.LowerCallTo(CLI);
5140 assert((CLI.IsTailCall || Result.second.getNode()) &&
5141 "Non-null chain expected with non-tail call!");
5142 assert((Result.second.getNode() || !Result.first.getNode()) &&
5143 "Null value expected with tail call!");
5145 if (!Result.second.getNode()) {
5146 // As a special case, a null chain means that a tail call has been emitted
5147 // and the DAG root is already updated.
5150 // Since there's no actual continuation from this block, nothing can be
5151 // relying on us setting vregs for them.
5152 PendingExports.clear();
5154 DAG.setRoot(Result.second);
5158 // Insert a label at the end of the invoke call to mark the try range. This
5159 // can be used to detect deletion of the invoke via the MachineModuleInfo.
5160 MCSymbol *EndLabel = MMI.getContext().createTempSymbol();
5161 DAG.setRoot(DAG.getEHLabel(getCurSDLoc(), getRoot(), EndLabel));
5163 // Inform MachineModuleInfo of range.
5164 MMI.addInvoke(LandingPad, BeginLabel, EndLabel);
5170 void SelectionDAGBuilder::LowerCallTo(ImmutableCallSite CS, SDValue Callee,
5172 MachineBasicBlock *LandingPad) {
5173 PointerType *PT = cast<PointerType>(CS.getCalledValue()->getType());
5174 FunctionType *FTy = cast<FunctionType>(PT->getElementType());
5175 Type *RetTy = FTy->getReturnType();
5177 TargetLowering::ArgListTy Args;
5178 TargetLowering::ArgListEntry Entry;
5179 Args.reserve(CS.arg_size());
5181 for (ImmutableCallSite::arg_iterator i = CS.arg_begin(), e = CS.arg_end();
5183 const Value *V = *i;
5186 if (V->getType()->isEmptyTy())
5189 SDValue ArgNode = getValue(V);
5190 Entry.Node = ArgNode; Entry.Ty = V->getType();
5192 // Skip the first return-type Attribute to get to params.
5193 Entry.setAttributes(&CS, i - CS.arg_begin() + 1);
5194 Args.push_back(Entry);
5196 // If we have an explicit sret argument that is an Instruction, (i.e., it
5197 // might point to function-local memory), we can't meaningfully tail-call.
5198 if (Entry.isSRet && isa<Instruction>(V))
5202 // Check if target-independent constraints permit a tail call here.
5203 // Target-dependent constraints are checked within TLI->LowerCallTo.
5204 if (isTailCall && !isInTailCallPosition(CS, DAG.getTarget()))
5207 TargetLowering::CallLoweringInfo CLI(DAG);
5208 CLI.setDebugLoc(getCurSDLoc()).setChain(getRoot())
5209 .setCallee(RetTy, FTy, Callee, std::move(Args), CS)
5210 .setTailCall(isTailCall);
5211 std::pair<SDValue,SDValue> Result = lowerInvokable(CLI, LandingPad);
5213 if (Result.first.getNode())
5214 setValue(CS.getInstruction(), Result.first);
5217 /// IsOnlyUsedInZeroEqualityComparison - Return true if it only matters that the
5218 /// value is equal or not-equal to zero.
5219 static bool IsOnlyUsedInZeroEqualityComparison(const Value *V) {
5220 for (const User *U : V->users()) {
5221 if (const ICmpInst *IC = dyn_cast<ICmpInst>(U))
5222 if (IC->isEquality())
5223 if (const Constant *C = dyn_cast<Constant>(IC->getOperand(1)))
5224 if (C->isNullValue())
5226 // Unknown instruction.
5232 static SDValue getMemCmpLoad(const Value *PtrVal, MVT LoadVT,
5234 SelectionDAGBuilder &Builder) {
5236 // Check to see if this load can be trivially constant folded, e.g. if the
5237 // input is from a string literal.
5238 if (const Constant *LoadInput = dyn_cast<Constant>(PtrVal)) {
5239 // Cast pointer to the type we really want to load.
5240 LoadInput = ConstantExpr::getBitCast(const_cast<Constant *>(LoadInput),
5241 PointerType::getUnqual(LoadTy));
5243 if (const Constant *LoadCst = ConstantFoldLoadFromConstPtr(
5244 const_cast<Constant *>(LoadInput), *Builder.DL))
5245 return Builder.getValue(LoadCst);
5248 // Otherwise, we have to emit the load. If the pointer is to unfoldable but
5249 // still constant memory, the input chain can be the entry node.
5251 bool ConstantMemory = false;
5253 // Do not serialize (non-volatile) loads of constant memory with anything.
5254 if (Builder.AA->pointsToConstantMemory(PtrVal)) {
5255 Root = Builder.DAG.getEntryNode();
5256 ConstantMemory = true;
5258 // Do not serialize non-volatile loads against each other.
5259 Root = Builder.DAG.getRoot();
5262 SDValue Ptr = Builder.getValue(PtrVal);
5263 SDValue LoadVal = Builder.DAG.getLoad(LoadVT, Builder.getCurSDLoc(), Root,
5264 Ptr, MachinePointerInfo(PtrVal),
5266 false /*nontemporal*/,
5267 false /*isinvariant*/, 1 /* align=1 */);
5269 if (!ConstantMemory)
5270 Builder.PendingLoads.push_back(LoadVal.getValue(1));
5274 /// processIntegerCallValue - Record the value for an instruction that
5275 /// produces an integer result, converting the type where necessary.
5276 void SelectionDAGBuilder::processIntegerCallValue(const Instruction &I,
5279 EVT VT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
5282 Value = DAG.getSExtOrTrunc(Value, getCurSDLoc(), VT);
5284 Value = DAG.getZExtOrTrunc(Value, getCurSDLoc(), VT);
5285 setValue(&I, Value);
5288 /// visitMemCmpCall - See if we can lower a call to memcmp in an optimized form.
5289 /// If so, return true and lower it, otherwise return false and it will be
5290 /// lowered like a normal call.
5291 bool SelectionDAGBuilder::visitMemCmpCall(const CallInst &I) {
5292 // Verify that the prototype makes sense. int memcmp(void*,void*,size_t)
5293 if (I.getNumArgOperands() != 3)
5296 const Value *LHS = I.getArgOperand(0), *RHS = I.getArgOperand(1);
5297 if (!LHS->getType()->isPointerTy() || !RHS->getType()->isPointerTy() ||
5298 !I.getArgOperand(2)->getType()->isIntegerTy() ||
5299 !I.getType()->isIntegerTy())
5302 const Value *Size = I.getArgOperand(2);
5303 const ConstantInt *CSize = dyn_cast<ConstantInt>(Size);
5304 if (CSize && CSize->getZExtValue() == 0) {
5305 EVT CallVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
5307 setValue(&I, DAG.getConstant(0, getCurSDLoc(), CallVT));
5311 const TargetSelectionDAGInfo &TSI = DAG.getSelectionDAGInfo();
5312 std::pair<SDValue, SDValue> Res =
5313 TSI.EmitTargetCodeForMemcmp(DAG, getCurSDLoc(), DAG.getRoot(),
5314 getValue(LHS), getValue(RHS), getValue(Size),
5315 MachinePointerInfo(LHS),
5316 MachinePointerInfo(RHS));
5317 if (Res.first.getNode()) {
5318 processIntegerCallValue(I, Res.first, true);
5319 PendingLoads.push_back(Res.second);
5323 // memcmp(S1,S2,2) != 0 -> (*(short*)LHS != *(short*)RHS) != 0
5324 // memcmp(S1,S2,4) != 0 -> (*(int*)LHS != *(int*)RHS) != 0
5325 if (CSize && IsOnlyUsedInZeroEqualityComparison(&I)) {
5326 bool ActuallyDoIt = true;
5329 switch (CSize->getZExtValue()) {
5331 LoadVT = MVT::Other;
5333 ActuallyDoIt = false;
5337 LoadTy = Type::getInt16Ty(CSize->getContext());
5341 LoadTy = Type::getInt32Ty(CSize->getContext());
5345 LoadTy = Type::getInt64Ty(CSize->getContext());
5349 LoadVT = MVT::v4i32;
5350 LoadTy = Type::getInt32Ty(CSize->getContext());
5351 LoadTy = VectorType::get(LoadTy, 4);
5356 // This turns into unaligned loads. We only do this if the target natively
5357 // supports the MVT we'll be loading or if it is small enough (<= 4) that
5358 // we'll only produce a small number of byte loads.
5360 // Require that we can find a legal MVT, and only do this if the target
5361 // supports unaligned loads of that type. Expanding into byte loads would
5363 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5364 if (ActuallyDoIt && CSize->getZExtValue() > 4) {
5365 unsigned DstAS = LHS->getType()->getPointerAddressSpace();
5366 unsigned SrcAS = RHS->getType()->getPointerAddressSpace();
5367 // TODO: Handle 5 byte compare as 4-byte + 1 byte.
5368 // TODO: Handle 8 byte compare on x86-32 as two 32-bit loads.
5369 // TODO: Check alignment of src and dest ptrs.
5370 if (!TLI.isTypeLegal(LoadVT) ||
5371 !TLI.allowsMisalignedMemoryAccesses(LoadVT, SrcAS) ||
5372 !TLI.allowsMisalignedMemoryAccesses(LoadVT, DstAS))
5373 ActuallyDoIt = false;
5377 SDValue LHSVal = getMemCmpLoad(LHS, LoadVT, LoadTy, *this);
5378 SDValue RHSVal = getMemCmpLoad(RHS, LoadVT, LoadTy, *this);
5380 SDValue Res = DAG.getSetCC(getCurSDLoc(), MVT::i1, LHSVal, RHSVal,
5382 processIntegerCallValue(I, Res, false);
5391 /// visitMemChrCall -- See if we can lower a memchr call into an optimized
5392 /// form. If so, return true and lower it, otherwise return false and it
5393 /// will be lowered like a normal call.
5394 bool SelectionDAGBuilder::visitMemChrCall(const CallInst &I) {
5395 // Verify that the prototype makes sense. void *memchr(void *, int, size_t)
5396 if (I.getNumArgOperands() != 3)
5399 const Value *Src = I.getArgOperand(0);
5400 const Value *Char = I.getArgOperand(1);
5401 const Value *Length = I.getArgOperand(2);
5402 if (!Src->getType()->isPointerTy() ||
5403 !Char->getType()->isIntegerTy() ||
5404 !Length->getType()->isIntegerTy() ||
5405 !I.getType()->isPointerTy())
5408 const TargetSelectionDAGInfo &TSI = DAG.getSelectionDAGInfo();
5409 std::pair<SDValue, SDValue> Res =
5410 TSI.EmitTargetCodeForMemchr(DAG, getCurSDLoc(), DAG.getRoot(),
5411 getValue(Src), getValue(Char), getValue(Length),
5412 MachinePointerInfo(Src));
5413 if (Res.first.getNode()) {
5414 setValue(&I, Res.first);
5415 PendingLoads.push_back(Res.second);
5422 /// visitStrCpyCall -- See if we can lower a strcpy or stpcpy call into an
5423 /// optimized form. If so, return true and lower it, otherwise return false
5424 /// and it will be lowered like a normal call.
5425 bool SelectionDAGBuilder::visitStrCpyCall(const CallInst &I, bool isStpcpy) {
5426 // Verify that the prototype makes sense. char *strcpy(char *, char *)
5427 if (I.getNumArgOperands() != 2)
5430 const Value *Arg0 = I.getArgOperand(0), *Arg1 = I.getArgOperand(1);
5431 if (!Arg0->getType()->isPointerTy() ||
5432 !Arg1->getType()->isPointerTy() ||
5433 !I.getType()->isPointerTy())
5436 const TargetSelectionDAGInfo &TSI = DAG.getSelectionDAGInfo();
5437 std::pair<SDValue, SDValue> Res =
5438 TSI.EmitTargetCodeForStrcpy(DAG, getCurSDLoc(), getRoot(),
5439 getValue(Arg0), getValue(Arg1),
5440 MachinePointerInfo(Arg0),
5441 MachinePointerInfo(Arg1), isStpcpy);
5442 if (Res.first.getNode()) {
5443 setValue(&I, Res.first);
5444 DAG.setRoot(Res.second);
5451 /// visitStrCmpCall - See if we can lower a call to strcmp in an optimized form.
5452 /// If so, return true and lower it, otherwise return false and it will be
5453 /// lowered like a normal call.
5454 bool SelectionDAGBuilder::visitStrCmpCall(const CallInst &I) {
5455 // Verify that the prototype makes sense. int strcmp(void*,void*)
5456 if (I.getNumArgOperands() != 2)
5459 const Value *Arg0 = I.getArgOperand(0), *Arg1 = I.getArgOperand(1);
5460 if (!Arg0->getType()->isPointerTy() ||
5461 !Arg1->getType()->isPointerTy() ||
5462 !I.getType()->isIntegerTy())
5465 const TargetSelectionDAGInfo &TSI = DAG.getSelectionDAGInfo();
5466 std::pair<SDValue, SDValue> Res =
5467 TSI.EmitTargetCodeForStrcmp(DAG, getCurSDLoc(), DAG.getRoot(),
5468 getValue(Arg0), getValue(Arg1),
5469 MachinePointerInfo(Arg0),
5470 MachinePointerInfo(Arg1));
5471 if (Res.first.getNode()) {
5472 processIntegerCallValue(I, Res.first, true);
5473 PendingLoads.push_back(Res.second);
5480 /// visitStrLenCall -- See if we can lower a strlen call into an optimized
5481 /// form. If so, return true and lower it, otherwise return false and it
5482 /// will be lowered like a normal call.
5483 bool SelectionDAGBuilder::visitStrLenCall(const CallInst &I) {
5484 // Verify that the prototype makes sense. size_t strlen(char *)
5485 if (I.getNumArgOperands() != 1)
5488 const Value *Arg0 = I.getArgOperand(0);
5489 if (!Arg0->getType()->isPointerTy() || !I.getType()->isIntegerTy())
5492 const TargetSelectionDAGInfo &TSI = DAG.getSelectionDAGInfo();
5493 std::pair<SDValue, SDValue> Res =
5494 TSI.EmitTargetCodeForStrlen(DAG, getCurSDLoc(), DAG.getRoot(),
5495 getValue(Arg0), MachinePointerInfo(Arg0));
5496 if (Res.first.getNode()) {
5497 processIntegerCallValue(I, Res.first, false);
5498 PendingLoads.push_back(Res.second);
5505 /// visitStrNLenCall -- See if we can lower a strnlen call into an optimized
5506 /// form. If so, return true and lower it, otherwise return false and it
5507 /// will be lowered like a normal call.
5508 bool SelectionDAGBuilder::visitStrNLenCall(const CallInst &I) {
5509 // Verify that the prototype makes sense. size_t strnlen(char *, size_t)
5510 if (I.getNumArgOperands() != 2)
5513 const Value *Arg0 = I.getArgOperand(0), *Arg1 = I.getArgOperand(1);
5514 if (!Arg0->getType()->isPointerTy() ||
5515 !Arg1->getType()->isIntegerTy() ||
5516 !I.getType()->isIntegerTy())
5519 const TargetSelectionDAGInfo &TSI = DAG.getSelectionDAGInfo();
5520 std::pair<SDValue, SDValue> Res =
5521 TSI.EmitTargetCodeForStrnlen(DAG, getCurSDLoc(), DAG.getRoot(),
5522 getValue(Arg0), getValue(Arg1),
5523 MachinePointerInfo(Arg0));
5524 if (Res.first.getNode()) {
5525 processIntegerCallValue(I, Res.first, false);
5526 PendingLoads.push_back(Res.second);
5533 /// visitUnaryFloatCall - If a call instruction is a unary floating-point
5534 /// operation (as expected), translate it to an SDNode with the specified opcode
5535 /// and return true.
5536 bool SelectionDAGBuilder::visitUnaryFloatCall(const CallInst &I,
5538 // Sanity check that it really is a unary floating-point call.
5539 if (I.getNumArgOperands() != 1 ||
5540 !I.getArgOperand(0)->getType()->isFloatingPointTy() ||
5541 I.getType() != I.getArgOperand(0)->getType() ||
5542 !I.onlyReadsMemory())
5545 SDValue Tmp = getValue(I.getArgOperand(0));
5546 setValue(&I, DAG.getNode(Opcode, getCurSDLoc(), Tmp.getValueType(), Tmp));
5550 /// visitBinaryFloatCall - If a call instruction is a binary floating-point
5551 /// operation (as expected), translate it to an SDNode with the specified opcode
5552 /// and return true.
5553 bool SelectionDAGBuilder::visitBinaryFloatCall(const CallInst &I,
5555 // Sanity check that it really is a binary floating-point call.
5556 if (I.getNumArgOperands() != 2 ||
5557 !I.getArgOperand(0)->getType()->isFloatingPointTy() ||
5558 I.getType() != I.getArgOperand(0)->getType() ||
5559 I.getType() != I.getArgOperand(1)->getType() ||
5560 !I.onlyReadsMemory())
5563 SDValue Tmp0 = getValue(I.getArgOperand(0));
5564 SDValue Tmp1 = getValue(I.getArgOperand(1));
5565 EVT VT = Tmp0.getValueType();
5566 setValue(&I, DAG.getNode(Opcode, getCurSDLoc(), VT, Tmp0, Tmp1));
5570 void SelectionDAGBuilder::visitCall(const CallInst &I) {
5571 // Handle inline assembly differently.
5572 if (isa<InlineAsm>(I.getCalledValue())) {
5577 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
5578 ComputeUsesVAFloatArgument(I, &MMI);
5580 const char *RenameFn = nullptr;
5581 if (Function *F = I.getCalledFunction()) {
5582 if (F->isDeclaration()) {
5583 if (const TargetIntrinsicInfo *II = TM.getIntrinsicInfo()) {
5584 if (unsigned IID = II->getIntrinsicID(F)) {
5585 RenameFn = visitIntrinsicCall(I, IID);
5590 if (Intrinsic::ID IID = F->getIntrinsicID()) {
5591 RenameFn = visitIntrinsicCall(I, IID);
5597 // Check for well-known libc/libm calls. If the function is internal, it
5598 // can't be a library call.
5600 if (!F->hasLocalLinkage() && F->hasName() &&
5601 LibInfo->getLibFunc(F->getName(), Func) &&
5602 LibInfo->hasOptimizedCodeGen(Func)) {
5605 case LibFunc::copysign:
5606 case LibFunc::copysignf:
5607 case LibFunc::copysignl:
5608 if (I.getNumArgOperands() == 2 && // Basic sanity checks.
5609 I.getArgOperand(0)->getType()->isFloatingPointTy() &&
5610 I.getType() == I.getArgOperand(0)->getType() &&
5611 I.getType() == I.getArgOperand(1)->getType() &&
5612 I.onlyReadsMemory()) {
5613 SDValue LHS = getValue(I.getArgOperand(0));
5614 SDValue RHS = getValue(I.getArgOperand(1));
5615 setValue(&I, DAG.getNode(ISD::FCOPYSIGN, getCurSDLoc(),
5616 LHS.getValueType(), LHS, RHS));
5621 case LibFunc::fabsf:
5622 case LibFunc::fabsl:
5623 if (visitUnaryFloatCall(I, ISD::FABS))
5627 case LibFunc::fminf:
5628 case LibFunc::fminl:
5629 if (visitBinaryFloatCall(I, ISD::FMINNUM))
5633 case LibFunc::fmaxf:
5634 case LibFunc::fmaxl:
5635 if (visitBinaryFloatCall(I, ISD::FMAXNUM))
5641 if (visitUnaryFloatCall(I, ISD::FSIN))
5647 if (visitUnaryFloatCall(I, ISD::FCOS))
5651 case LibFunc::sqrtf:
5652 case LibFunc::sqrtl:
5653 case LibFunc::sqrt_finite:
5654 case LibFunc::sqrtf_finite:
5655 case LibFunc::sqrtl_finite:
5656 if (visitUnaryFloatCall(I, ISD::FSQRT))
5659 case LibFunc::floor:
5660 case LibFunc::floorf:
5661 case LibFunc::floorl:
5662 if (visitUnaryFloatCall(I, ISD::FFLOOR))
5665 case LibFunc::nearbyint:
5666 case LibFunc::nearbyintf:
5667 case LibFunc::nearbyintl:
5668 if (visitUnaryFloatCall(I, ISD::FNEARBYINT))
5672 case LibFunc::ceilf:
5673 case LibFunc::ceill:
5674 if (visitUnaryFloatCall(I, ISD::FCEIL))
5678 case LibFunc::rintf:
5679 case LibFunc::rintl:
5680 if (visitUnaryFloatCall(I, ISD::FRINT))
5683 case LibFunc::round:
5684 case LibFunc::roundf:
5685 case LibFunc::roundl:
5686 if (visitUnaryFloatCall(I, ISD::FROUND))
5689 case LibFunc::trunc:
5690 case LibFunc::truncf:
5691 case LibFunc::truncl:
5692 if (visitUnaryFloatCall(I, ISD::FTRUNC))
5696 case LibFunc::log2f:
5697 case LibFunc::log2l:
5698 if (visitUnaryFloatCall(I, ISD::FLOG2))
5702 case LibFunc::exp2f:
5703 case LibFunc::exp2l:
5704 if (visitUnaryFloatCall(I, ISD::FEXP2))
5707 case LibFunc::memcmp:
5708 if (visitMemCmpCall(I))
5711 case LibFunc::memchr:
5712 if (visitMemChrCall(I))
5715 case LibFunc::strcpy:
5716 if (visitStrCpyCall(I, false))
5719 case LibFunc::stpcpy:
5720 if (visitStrCpyCall(I, true))
5723 case LibFunc::strcmp:
5724 if (visitStrCmpCall(I))
5727 case LibFunc::strlen:
5728 if (visitStrLenCall(I))
5731 case LibFunc::strnlen:
5732 if (visitStrNLenCall(I))
5741 Callee = getValue(I.getCalledValue());
5743 Callee = DAG.getExternalSymbol(
5745 DAG.getTargetLoweringInfo().getPointerTy(DAG.getDataLayout()));
5747 // Check if we can potentially perform a tail call. More detailed checking is
5748 // be done within LowerCallTo, after more information about the call is known.
5749 LowerCallTo(&I, Callee, I.isTailCall());
5754 /// AsmOperandInfo - This contains information for each constraint that we are
5756 class SDISelAsmOperandInfo : public TargetLowering::AsmOperandInfo {
5758 /// CallOperand - If this is the result output operand or a clobber
5759 /// this is null, otherwise it is the incoming operand to the CallInst.
5760 /// This gets modified as the asm is processed.
5761 SDValue CallOperand;
5763 /// AssignedRegs - If this is a register or register class operand, this
5764 /// contains the set of register corresponding to the operand.
5765 RegsForValue AssignedRegs;
5767 explicit SDISelAsmOperandInfo(const TargetLowering::AsmOperandInfo &info)
5768 : TargetLowering::AsmOperandInfo(info), CallOperand(nullptr,0) {
5771 /// getCallOperandValEVT - Return the EVT of the Value* that this operand
5772 /// corresponds to. If there is no Value* for this operand, it returns
5774 EVT getCallOperandValEVT(LLVMContext &Context, const TargetLowering &TLI,
5775 const DataLayout &DL) const {
5776 if (!CallOperandVal) return MVT::Other;
5778 if (isa<BasicBlock>(CallOperandVal))
5779 return TLI.getPointerTy(DL);
5781 llvm::Type *OpTy = CallOperandVal->getType();
5783 // FIXME: code duplicated from TargetLowering::ParseConstraints().
5784 // If this is an indirect operand, the operand is a pointer to the
5787 llvm::PointerType *PtrTy = dyn_cast<PointerType>(OpTy);
5789 report_fatal_error("Indirect operand for inline asm not a pointer!");
5790 OpTy = PtrTy->getElementType();
5793 // Look for vector wrapped in a struct. e.g. { <16 x i8> }.
5794 if (StructType *STy = dyn_cast<StructType>(OpTy))
5795 if (STy->getNumElements() == 1)
5796 OpTy = STy->getElementType(0);
5798 // If OpTy is not a single value, it may be a struct/union that we
5799 // can tile with integers.
5800 if (!OpTy->isSingleValueType() && OpTy->isSized()) {
5801 unsigned BitSize = DL.getTypeSizeInBits(OpTy);
5810 OpTy = IntegerType::get(Context, BitSize);
5815 return TLI.getValueType(DL, OpTy, true);
5819 typedef SmallVector<SDISelAsmOperandInfo,16> SDISelAsmOperandInfoVector;
5821 } // end anonymous namespace
5823 /// GetRegistersForValue - Assign registers (virtual or physical) for the
5824 /// specified operand. We prefer to assign virtual registers, to allow the
5825 /// register allocator to handle the assignment process. However, if the asm
5826 /// uses features that we can't model on machineinstrs, we have SDISel do the
5827 /// allocation. This produces generally horrible, but correct, code.
5829 /// OpInfo describes the operand.
5831 static void GetRegistersForValue(SelectionDAG &DAG,
5832 const TargetLowering &TLI,
5834 SDISelAsmOperandInfo &OpInfo) {
5835 LLVMContext &Context = *DAG.getContext();
5837 MachineFunction &MF = DAG.getMachineFunction();
5838 SmallVector<unsigned, 4> Regs;
5840 // If this is a constraint for a single physreg, or a constraint for a
5841 // register class, find it.
5842 std::pair<unsigned, const TargetRegisterClass *> PhysReg =
5843 TLI.getRegForInlineAsmConstraint(MF.getSubtarget().getRegisterInfo(),
5844 OpInfo.ConstraintCode,
5845 OpInfo.ConstraintVT);
5847 unsigned NumRegs = 1;
5848 if (OpInfo.ConstraintVT != MVT::Other) {
5849 // If this is a FP input in an integer register (or visa versa) insert a bit
5850 // cast of the input value. More generally, handle any case where the input
5851 // value disagrees with the register class we plan to stick this in.
5852 if (OpInfo.Type == InlineAsm::isInput &&
5853 PhysReg.second && !PhysReg.second->hasType(OpInfo.ConstraintVT)) {
5854 // Try to convert to the first EVT that the reg class contains. If the
5855 // types are identical size, use a bitcast to convert (e.g. two differing
5857 MVT RegVT = *PhysReg.second->vt_begin();
5858 if (RegVT.getSizeInBits() == OpInfo.CallOperand.getValueSizeInBits()) {
5859 OpInfo.CallOperand = DAG.getNode(ISD::BITCAST, DL,
5860 RegVT, OpInfo.CallOperand);
5861 OpInfo.ConstraintVT = RegVT;
5862 } else if (RegVT.isInteger() && OpInfo.ConstraintVT.isFloatingPoint()) {
5863 // If the input is a FP value and we want it in FP registers, do a
5864 // bitcast to the corresponding integer type. This turns an f64 value
5865 // into i64, which can be passed with two i32 values on a 32-bit
5867 RegVT = MVT::getIntegerVT(OpInfo.ConstraintVT.getSizeInBits());
5868 OpInfo.CallOperand = DAG.getNode(ISD::BITCAST, DL,
5869 RegVT, OpInfo.CallOperand);
5870 OpInfo.ConstraintVT = RegVT;
5874 NumRegs = TLI.getNumRegisters(Context, OpInfo.ConstraintVT);
5878 EVT ValueVT = OpInfo.ConstraintVT;
5880 // If this is a constraint for a specific physical register, like {r17},
5882 if (unsigned AssignedReg = PhysReg.first) {
5883 const TargetRegisterClass *RC = PhysReg.second;
5884 if (OpInfo.ConstraintVT == MVT::Other)
5885 ValueVT = *RC->vt_begin();
5887 // Get the actual register value type. This is important, because the user
5888 // may have asked for (e.g.) the AX register in i32 type. We need to
5889 // remember that AX is actually i16 to get the right extension.
5890 RegVT = *RC->vt_begin();
5892 // This is a explicit reference to a physical register.
5893 Regs.push_back(AssignedReg);
5895 // If this is an expanded reference, add the rest of the regs to Regs.
5897 TargetRegisterClass::iterator I = RC->begin();
5898 for (; *I != AssignedReg; ++I)
5899 assert(I != RC->end() && "Didn't find reg!");
5901 // Already added the first reg.
5903 for (; NumRegs; --NumRegs, ++I) {
5904 assert(I != RC->end() && "Ran out of registers to allocate!");
5909 OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT);
5913 // Otherwise, if this was a reference to an LLVM register class, create vregs
5914 // for this reference.
5915 if (const TargetRegisterClass *RC = PhysReg.second) {
5916 RegVT = *RC->vt_begin();
5917 if (OpInfo.ConstraintVT == MVT::Other)
5920 // Create the appropriate number of virtual registers.
5921 MachineRegisterInfo &RegInfo = MF.getRegInfo();
5922 for (; NumRegs; --NumRegs)
5923 Regs.push_back(RegInfo.createVirtualRegister(RC));
5925 OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT);
5929 // Otherwise, we couldn't allocate enough registers for this.
5932 /// visitInlineAsm - Handle a call to an InlineAsm object.
5934 void SelectionDAGBuilder::visitInlineAsm(ImmutableCallSite CS) {
5935 const InlineAsm *IA = cast<InlineAsm>(CS.getCalledValue());
5937 /// ConstraintOperands - Information about all of the constraints.
5938 SDISelAsmOperandInfoVector ConstraintOperands;
5940 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5941 TargetLowering::AsmOperandInfoVector TargetConstraints = TLI.ParseConstraints(
5942 DAG.getDataLayout(), DAG.getSubtarget().getRegisterInfo(), CS);
5944 bool hasMemory = false;
5946 unsigned ArgNo = 0; // ArgNo - The argument of the CallInst.
5947 unsigned ResNo = 0; // ResNo - The result number of the next output.
5948 for (unsigned i = 0, e = TargetConstraints.size(); i != e; ++i) {
5949 ConstraintOperands.push_back(SDISelAsmOperandInfo(TargetConstraints[i]));
5950 SDISelAsmOperandInfo &OpInfo = ConstraintOperands.back();
5952 MVT OpVT = MVT::Other;
5954 // Compute the value type for each operand.
5955 switch (OpInfo.Type) {
5956 case InlineAsm::isOutput:
5957 // Indirect outputs just consume an argument.
5958 if (OpInfo.isIndirect) {
5959 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++));
5963 // The return value of the call is this value. As such, there is no
5964 // corresponding argument.
5965 assert(!CS.getType()->isVoidTy() && "Bad inline asm!");
5966 if (StructType *STy = dyn_cast<StructType>(CS.getType())) {
5967 OpVT = TLI.getSimpleValueType(DAG.getDataLayout(),
5968 STy->getElementType(ResNo));
5970 assert(ResNo == 0 && "Asm only has one result!");
5971 OpVT = TLI.getSimpleValueType(DAG.getDataLayout(), CS.getType());
5975 case InlineAsm::isInput:
5976 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++));
5978 case InlineAsm::isClobber:
5983 // If this is an input or an indirect output, process the call argument.
5984 // BasicBlocks are labels, currently appearing only in asm's.
5985 if (OpInfo.CallOperandVal) {
5986 if (const BasicBlock *BB = dyn_cast<BasicBlock>(OpInfo.CallOperandVal)) {
5987 OpInfo.CallOperand = DAG.getBasicBlock(FuncInfo.MBBMap[BB]);
5989 OpInfo.CallOperand = getValue(OpInfo.CallOperandVal);
5992 OpVT = OpInfo.getCallOperandValEVT(*DAG.getContext(), TLI,
5993 DAG.getDataLayout()).getSimpleVT();
5996 OpInfo.ConstraintVT = OpVT;
5998 // Indirect operand accesses access memory.
5999 if (OpInfo.isIndirect)
6002 for (unsigned j = 0, ee = OpInfo.Codes.size(); j != ee; ++j) {
6003 TargetLowering::ConstraintType
6004 CType = TLI.getConstraintType(OpInfo.Codes[j]);
6005 if (CType == TargetLowering::C_Memory) {
6013 SDValue Chain, Flag;
6015 // We won't need to flush pending loads if this asm doesn't touch
6016 // memory and is nonvolatile.
6017 if (hasMemory || IA->hasSideEffects())
6020 Chain = DAG.getRoot();
6022 // Second pass over the constraints: compute which constraint option to use
6023 // and assign registers to constraints that want a specific physreg.
6024 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
6025 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
6027 // If this is an output operand with a matching input operand, look up the
6028 // matching input. If their types mismatch, e.g. one is an integer, the
6029 // other is floating point, or their sizes are different, flag it as an
6031 if (OpInfo.hasMatchingInput()) {
6032 SDISelAsmOperandInfo &Input = ConstraintOperands[OpInfo.MatchingInput];
6034 if (OpInfo.ConstraintVT != Input.ConstraintVT) {
6035 const TargetRegisterInfo *TRI = DAG.getSubtarget().getRegisterInfo();
6036 std::pair<unsigned, const TargetRegisterClass *> MatchRC =
6037 TLI.getRegForInlineAsmConstraint(TRI, OpInfo.ConstraintCode,
6038 OpInfo.ConstraintVT);
6039 std::pair<unsigned, const TargetRegisterClass *> InputRC =
6040 TLI.getRegForInlineAsmConstraint(TRI, Input.ConstraintCode,
6041 Input.ConstraintVT);
6042 if ((OpInfo.ConstraintVT.isInteger() !=
6043 Input.ConstraintVT.isInteger()) ||
6044 (MatchRC.second != InputRC.second)) {
6045 report_fatal_error("Unsupported asm: input constraint"
6046 " with a matching output constraint of"
6047 " incompatible type!");
6049 Input.ConstraintVT = OpInfo.ConstraintVT;
6053 // Compute the constraint code and ConstraintType to use.
6054 TLI.ComputeConstraintToUse(OpInfo, OpInfo.CallOperand, &DAG);
6056 if (OpInfo.ConstraintType == TargetLowering::C_Memory &&
6057 OpInfo.Type == InlineAsm::isClobber)
6060 // If this is a memory input, and if the operand is not indirect, do what we
6061 // need to to provide an address for the memory input.
6062 if (OpInfo.ConstraintType == TargetLowering::C_Memory &&
6063 !OpInfo.isIndirect) {
6064 assert((OpInfo.isMultipleAlternative ||
6065 (OpInfo.Type == InlineAsm::isInput)) &&
6066 "Can only indirectify direct input operands!");
6068 // Memory operands really want the address of the value. If we don't have
6069 // an indirect input, put it in the constpool if we can, otherwise spill
6070 // it to a stack slot.
6071 // TODO: This isn't quite right. We need to handle these according to
6072 // the addressing mode that the constraint wants. Also, this may take
6073 // an additional register for the computation and we don't want that
6076 // If the operand is a float, integer, or vector constant, spill to a
6077 // constant pool entry to get its address.
6078 const Value *OpVal = OpInfo.CallOperandVal;
6079 if (isa<ConstantFP>(OpVal) || isa<ConstantInt>(OpVal) ||
6080 isa<ConstantVector>(OpVal) || isa<ConstantDataVector>(OpVal)) {
6081 OpInfo.CallOperand = DAG.getConstantPool(
6082 cast<Constant>(OpVal), TLI.getPointerTy(DAG.getDataLayout()));
6084 // Otherwise, create a stack slot and emit a store to it before the
6086 Type *Ty = OpVal->getType();
6087 auto &DL = DAG.getDataLayout();
6088 uint64_t TySize = DL.getTypeAllocSize(Ty);
6089 unsigned Align = DL.getPrefTypeAlignment(Ty);
6090 MachineFunction &MF = DAG.getMachineFunction();
6091 int SSFI = MF.getFrameInfo()->CreateStackObject(TySize, Align, false);
6093 DAG.getFrameIndex(SSFI, TLI.getPointerTy(DAG.getDataLayout()));
6094 Chain = DAG.getStore(
6095 Chain, getCurSDLoc(), OpInfo.CallOperand, StackSlot,
6096 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), SSFI),
6098 OpInfo.CallOperand = StackSlot;
6101 // There is no longer a Value* corresponding to this operand.
6102 OpInfo.CallOperandVal = nullptr;
6104 // It is now an indirect operand.
6105 OpInfo.isIndirect = true;
6108 // If this constraint is for a specific register, allocate it before
6110 if (OpInfo.ConstraintType == TargetLowering::C_Register)
6111 GetRegistersForValue(DAG, TLI, getCurSDLoc(), OpInfo);
6114 // Second pass - Loop over all of the operands, assigning virtual or physregs
6115 // to register class operands.
6116 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
6117 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
6119 // C_Register operands have already been allocated, Other/Memory don't need
6121 if (OpInfo.ConstraintType == TargetLowering::C_RegisterClass)
6122 GetRegistersForValue(DAG, TLI, getCurSDLoc(), OpInfo);
6125 // AsmNodeOperands - The operands for the ISD::INLINEASM node.
6126 std::vector<SDValue> AsmNodeOperands;
6127 AsmNodeOperands.push_back(SDValue()); // reserve space for input chain
6128 AsmNodeOperands.push_back(DAG.getTargetExternalSymbol(
6129 IA->getAsmString().c_str(), TLI.getPointerTy(DAG.getDataLayout())));
6131 // If we have a !srcloc metadata node associated with it, we want to attach
6132 // this to the ultimately generated inline asm machineinstr. To do this, we
6133 // pass in the third operand as this (potentially null) inline asm MDNode.
6134 const MDNode *SrcLoc = CS.getInstruction()->getMetadata("srcloc");
6135 AsmNodeOperands.push_back(DAG.getMDNode(SrcLoc));
6137 // Remember the HasSideEffect, AlignStack, AsmDialect, MayLoad and MayStore
6138 // bits as operand 3.
6139 unsigned ExtraInfo = 0;
6140 if (IA->hasSideEffects())
6141 ExtraInfo |= InlineAsm::Extra_HasSideEffects;
6142 if (IA->isAlignStack())
6143 ExtraInfo |= InlineAsm::Extra_IsAlignStack;
6144 // Set the asm dialect.
6145 ExtraInfo |= IA->getDialect() * InlineAsm::Extra_AsmDialect;
6147 // Determine if this InlineAsm MayLoad or MayStore based on the constraints.
6148 for (unsigned i = 0, e = TargetConstraints.size(); i != e; ++i) {
6149 TargetLowering::AsmOperandInfo &OpInfo = TargetConstraints[i];
6151 // Compute the constraint code and ConstraintType to use.
6152 TLI.ComputeConstraintToUse(OpInfo, SDValue());
6154 // Ideally, we would only check against memory constraints. However, the
6155 // meaning of an other constraint can be target-specific and we can't easily
6156 // reason about it. Therefore, be conservative and set MayLoad/MayStore
6157 // for other constriants as well.
6158 if (OpInfo.ConstraintType == TargetLowering::C_Memory ||
6159 OpInfo.ConstraintType == TargetLowering::C_Other) {
6160 if (OpInfo.Type == InlineAsm::isInput)
6161 ExtraInfo |= InlineAsm::Extra_MayLoad;
6162 else if (OpInfo.Type == InlineAsm::isOutput)
6163 ExtraInfo |= InlineAsm::Extra_MayStore;
6164 else if (OpInfo.Type == InlineAsm::isClobber)
6165 ExtraInfo |= (InlineAsm::Extra_MayLoad | InlineAsm::Extra_MayStore);
6169 AsmNodeOperands.push_back(DAG.getTargetConstant(
6170 ExtraInfo, getCurSDLoc(), TLI.getPointerTy(DAG.getDataLayout())));
6172 // Loop over all of the inputs, copying the operand values into the
6173 // appropriate registers and processing the output regs.
6174 RegsForValue RetValRegs;
6176 // IndirectStoresToEmit - The set of stores to emit after the inline asm node.
6177 std::vector<std::pair<RegsForValue, Value*> > IndirectStoresToEmit;
6179 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
6180 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
6182 switch (OpInfo.Type) {
6183 case InlineAsm::isOutput: {
6184 if (OpInfo.ConstraintType != TargetLowering::C_RegisterClass &&
6185 OpInfo.ConstraintType != TargetLowering::C_Register) {
6186 // Memory output, or 'other' output (e.g. 'X' constraint).
6187 assert(OpInfo.isIndirect && "Memory output must be indirect operand");
6189 unsigned ConstraintID =
6190 TLI.getInlineAsmMemConstraint(OpInfo.ConstraintCode);
6191 assert(ConstraintID != InlineAsm::Constraint_Unknown &&
6192 "Failed to convert memory constraint code to constraint id.");
6194 // Add information to the INLINEASM node to know about this output.
6195 unsigned OpFlags = InlineAsm::getFlagWord(InlineAsm::Kind_Mem, 1);
6196 OpFlags = InlineAsm::getFlagWordForMem(OpFlags, ConstraintID);
6197 AsmNodeOperands.push_back(DAG.getTargetConstant(OpFlags, getCurSDLoc(),
6199 AsmNodeOperands.push_back(OpInfo.CallOperand);
6203 // Otherwise, this is a register or register class output.
6205 // Copy the output from the appropriate register. Find a register that
6207 if (OpInfo.AssignedRegs.Regs.empty()) {
6208 LLVMContext &Ctx = *DAG.getContext();
6209 Ctx.emitError(CS.getInstruction(),
6210 "couldn't allocate output register for constraint '" +
6211 Twine(OpInfo.ConstraintCode) + "'");
6215 // If this is an indirect operand, store through the pointer after the
6217 if (OpInfo.isIndirect) {
6218 IndirectStoresToEmit.push_back(std::make_pair(OpInfo.AssignedRegs,
6219 OpInfo.CallOperandVal));
6221 // This is the result value of the call.
6222 assert(!CS.getType()->isVoidTy() && "Bad inline asm!");
6223 // Concatenate this output onto the outputs list.
6224 RetValRegs.append(OpInfo.AssignedRegs);
6227 // Add information to the INLINEASM node to know that this register is
6230 .AddInlineAsmOperands(OpInfo.isEarlyClobber
6231 ? InlineAsm::Kind_RegDefEarlyClobber
6232 : InlineAsm::Kind_RegDef,
6233 false, 0, getCurSDLoc(), DAG, AsmNodeOperands);
6236 case InlineAsm::isInput: {
6237 SDValue InOperandVal = OpInfo.CallOperand;
6239 if (OpInfo.isMatchingInputConstraint()) { // Matching constraint?
6240 // If this is required to match an output register we have already set,
6241 // just use its register.
6242 unsigned OperandNo = OpInfo.getMatchedOperand();
6244 // Scan until we find the definition we already emitted of this operand.
6245 // When we find it, create a RegsForValue operand.
6246 unsigned CurOp = InlineAsm::Op_FirstOperand;
6247 for (; OperandNo; --OperandNo) {
6248 // Advance to the next operand.
6250 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue();
6251 assert((InlineAsm::isRegDefKind(OpFlag) ||
6252 InlineAsm::isRegDefEarlyClobberKind(OpFlag) ||
6253 InlineAsm::isMemKind(OpFlag)) && "Skipped past definitions?");
6254 CurOp += InlineAsm::getNumOperandRegisters(OpFlag)+1;
6258 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue();
6259 if (InlineAsm::isRegDefKind(OpFlag) ||
6260 InlineAsm::isRegDefEarlyClobberKind(OpFlag)) {
6261 // Add (OpFlag&0xffff)>>3 registers to MatchedRegs.
6262 if (OpInfo.isIndirect) {
6263 // This happens on gcc/testsuite/gcc.dg/pr8788-1.c
6264 LLVMContext &Ctx = *DAG.getContext();
6265 Ctx.emitError(CS.getInstruction(), "inline asm not supported yet:"
6266 " don't know how to handle tied "
6267 "indirect register inputs");
6271 RegsForValue MatchedRegs;
6272 MatchedRegs.ValueVTs.push_back(InOperandVal.getValueType());
6273 MVT RegVT = AsmNodeOperands[CurOp+1].getSimpleValueType();
6274 MatchedRegs.RegVTs.push_back(RegVT);
6275 MachineRegisterInfo &RegInfo = DAG.getMachineFunction().getRegInfo();
6276 for (unsigned i = 0, e = InlineAsm::getNumOperandRegisters(OpFlag);
6278 if (const TargetRegisterClass *RC = TLI.getRegClassFor(RegVT))
6279 MatchedRegs.Regs.push_back(RegInfo.createVirtualRegister(RC));
6281 LLVMContext &Ctx = *DAG.getContext();
6282 Ctx.emitError(CS.getInstruction(),
6283 "inline asm error: This value"
6284 " type register class is not natively supported!");
6288 SDLoc dl = getCurSDLoc();
6289 // Use the produced MatchedRegs object to
6290 MatchedRegs.getCopyToRegs(InOperandVal, DAG, dl,
6291 Chain, &Flag, CS.getInstruction());
6292 MatchedRegs.AddInlineAsmOperands(InlineAsm::Kind_RegUse,
6293 true, OpInfo.getMatchedOperand(), dl,
6294 DAG, AsmNodeOperands);
6298 assert(InlineAsm::isMemKind(OpFlag) && "Unknown matching constraint!");
6299 assert(InlineAsm::getNumOperandRegisters(OpFlag) == 1 &&
6300 "Unexpected number of operands");
6301 // Add information to the INLINEASM node to know about this input.
6302 // See InlineAsm.h isUseOperandTiedToDef.
6303 OpFlag = InlineAsm::convertMemFlagWordToMatchingFlagWord(OpFlag);
6304 OpFlag = InlineAsm::getFlagWordForMatchingOp(OpFlag,
6305 OpInfo.getMatchedOperand());
6306 AsmNodeOperands.push_back(DAG.getTargetConstant(
6307 OpFlag, getCurSDLoc(), TLI.getPointerTy(DAG.getDataLayout())));
6308 AsmNodeOperands.push_back(AsmNodeOperands[CurOp+1]);
6312 // Treat indirect 'X' constraint as memory.
6313 if (OpInfo.ConstraintType == TargetLowering::C_Other &&
6315 OpInfo.ConstraintType = TargetLowering::C_Memory;
6317 if (OpInfo.ConstraintType == TargetLowering::C_Other) {
6318 std::vector<SDValue> Ops;
6319 TLI.LowerAsmOperandForConstraint(InOperandVal, OpInfo.ConstraintCode,
6322 LLVMContext &Ctx = *DAG.getContext();
6323 Ctx.emitError(CS.getInstruction(),
6324 "invalid operand for inline asm constraint '" +
6325 Twine(OpInfo.ConstraintCode) + "'");
6329 // Add information to the INLINEASM node to know about this input.
6330 unsigned ResOpType =
6331 InlineAsm::getFlagWord(InlineAsm::Kind_Imm, Ops.size());
6332 AsmNodeOperands.push_back(DAG.getTargetConstant(
6333 ResOpType, getCurSDLoc(), TLI.getPointerTy(DAG.getDataLayout())));
6334 AsmNodeOperands.insert(AsmNodeOperands.end(), Ops.begin(), Ops.end());
6338 if (OpInfo.ConstraintType == TargetLowering::C_Memory) {
6339 assert(OpInfo.isIndirect && "Operand must be indirect to be a mem!");
6340 assert(InOperandVal.getValueType() ==
6341 TLI.getPointerTy(DAG.getDataLayout()) &&
6342 "Memory operands expect pointer values");
6344 unsigned ConstraintID =
6345 TLI.getInlineAsmMemConstraint(OpInfo.ConstraintCode);
6346 assert(ConstraintID != InlineAsm::Constraint_Unknown &&
6347 "Failed to convert memory constraint code to constraint id.");
6349 // Add information to the INLINEASM node to know about this input.
6350 unsigned ResOpType = InlineAsm::getFlagWord(InlineAsm::Kind_Mem, 1);
6351 ResOpType = InlineAsm::getFlagWordForMem(ResOpType, ConstraintID);
6352 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
6355 AsmNodeOperands.push_back(InOperandVal);
6359 assert((OpInfo.ConstraintType == TargetLowering::C_RegisterClass ||
6360 OpInfo.ConstraintType == TargetLowering::C_Register) &&
6361 "Unknown constraint type!");
6363 // TODO: Support this.
6364 if (OpInfo.isIndirect) {
6365 LLVMContext &Ctx = *DAG.getContext();
6366 Ctx.emitError(CS.getInstruction(),
6367 "Don't know how to handle indirect register inputs yet "
6368 "for constraint '" +
6369 Twine(OpInfo.ConstraintCode) + "'");
6373 // Copy the input into the appropriate registers.
6374 if (OpInfo.AssignedRegs.Regs.empty()) {
6375 LLVMContext &Ctx = *DAG.getContext();
6376 Ctx.emitError(CS.getInstruction(),
6377 "couldn't allocate input reg for constraint '" +
6378 Twine(OpInfo.ConstraintCode) + "'");
6382 SDLoc dl = getCurSDLoc();
6384 OpInfo.AssignedRegs.getCopyToRegs(InOperandVal, DAG, dl,
6385 Chain, &Flag, CS.getInstruction());
6387 OpInfo.AssignedRegs.AddInlineAsmOperands(InlineAsm::Kind_RegUse, false, 0,
6388 dl, DAG, AsmNodeOperands);
6391 case InlineAsm::isClobber: {
6392 // Add the clobbered value to the operand list, so that the register
6393 // allocator is aware that the physreg got clobbered.
6394 if (!OpInfo.AssignedRegs.Regs.empty())
6395 OpInfo.AssignedRegs.AddInlineAsmOperands(InlineAsm::Kind_Clobber,
6396 false, 0, getCurSDLoc(), DAG,
6403 // Finish up input operands. Set the input chain and add the flag last.
6404 AsmNodeOperands[InlineAsm::Op_InputChain] = Chain;
6405 if (Flag.getNode()) AsmNodeOperands.push_back(Flag);
6407 Chain = DAG.getNode(ISD::INLINEASM, getCurSDLoc(),
6408 DAG.getVTList(MVT::Other, MVT::Glue), AsmNodeOperands);
6409 Flag = Chain.getValue(1);
6411 // If this asm returns a register value, copy the result from that register
6412 // and set it as the value of the call.
6413 if (!RetValRegs.Regs.empty()) {
6414 SDValue Val = RetValRegs.getCopyFromRegs(DAG, FuncInfo, getCurSDLoc(),
6415 Chain, &Flag, CS.getInstruction());
6417 // FIXME: Why don't we do this for inline asms with MRVs?
6418 if (CS.getType()->isSingleValueType() && CS.getType()->isSized()) {
6419 EVT ResultType = TLI.getValueType(DAG.getDataLayout(), CS.getType());
6421 // If any of the results of the inline asm is a vector, it may have the
6422 // wrong width/num elts. This can happen for register classes that can
6423 // contain multiple different value types. The preg or vreg allocated may
6424 // not have the same VT as was expected. Convert it to the right type
6425 // with bit_convert.
6426 if (ResultType != Val.getValueType() && Val.getValueType().isVector()) {
6427 Val = DAG.getNode(ISD::BITCAST, getCurSDLoc(),
6430 } else if (ResultType != Val.getValueType() &&
6431 ResultType.isInteger() && Val.getValueType().isInteger()) {
6432 // If a result value was tied to an input value, the computed result may
6433 // have a wider width than the expected result. Extract the relevant
6435 Val = DAG.getNode(ISD::TRUNCATE, getCurSDLoc(), ResultType, Val);
6438 assert(ResultType == Val.getValueType() && "Asm result value mismatch!");
6441 setValue(CS.getInstruction(), Val);
6442 // Don't need to use this as a chain in this case.
6443 if (!IA->hasSideEffects() && !hasMemory && IndirectStoresToEmit.empty())
6447 std::vector<std::pair<SDValue, const Value *> > StoresToEmit;
6449 // Process indirect outputs, first output all of the flagged copies out of
6451 for (unsigned i = 0, e = IndirectStoresToEmit.size(); i != e; ++i) {
6452 RegsForValue &OutRegs = IndirectStoresToEmit[i].first;
6453 const Value *Ptr = IndirectStoresToEmit[i].second;
6454 SDValue OutVal = OutRegs.getCopyFromRegs(DAG, FuncInfo, getCurSDLoc(),
6456 StoresToEmit.push_back(std::make_pair(OutVal, Ptr));
6459 // Emit the non-flagged stores from the physregs.
6460 SmallVector<SDValue, 8> OutChains;
6461 for (unsigned i = 0, e = StoresToEmit.size(); i != e; ++i) {
6462 SDValue Val = DAG.getStore(Chain, getCurSDLoc(),
6463 StoresToEmit[i].first,
6464 getValue(StoresToEmit[i].second),
6465 MachinePointerInfo(StoresToEmit[i].second),
6467 OutChains.push_back(Val);
6470 if (!OutChains.empty())
6471 Chain = DAG.getNode(ISD::TokenFactor, getCurSDLoc(), MVT::Other, OutChains);
6476 void SelectionDAGBuilder::visitVAStart(const CallInst &I) {
6477 DAG.setRoot(DAG.getNode(ISD::VASTART, getCurSDLoc(),
6478 MVT::Other, getRoot(),
6479 getValue(I.getArgOperand(0)),
6480 DAG.getSrcValue(I.getArgOperand(0))));
6483 void SelectionDAGBuilder::visitVAArg(const VAArgInst &I) {
6484 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6485 const DataLayout &DL = DAG.getDataLayout();
6486 SDValue V = DAG.getVAArg(TLI.getValueType(DAG.getDataLayout(), I.getType()),
6487 getCurSDLoc(), getRoot(), getValue(I.getOperand(0)),
6488 DAG.getSrcValue(I.getOperand(0)),
6489 DL.getABITypeAlignment(I.getType()));
6491 DAG.setRoot(V.getValue(1));
6494 void SelectionDAGBuilder::visitVAEnd(const CallInst &I) {
6495 DAG.setRoot(DAG.getNode(ISD::VAEND, getCurSDLoc(),
6496 MVT::Other, getRoot(),
6497 getValue(I.getArgOperand(0)),
6498 DAG.getSrcValue(I.getArgOperand(0))));
6501 void SelectionDAGBuilder::visitVACopy(const CallInst &I) {
6502 DAG.setRoot(DAG.getNode(ISD::VACOPY, getCurSDLoc(),
6503 MVT::Other, getRoot(),
6504 getValue(I.getArgOperand(0)),
6505 getValue(I.getArgOperand(1)),
6506 DAG.getSrcValue(I.getArgOperand(0)),
6507 DAG.getSrcValue(I.getArgOperand(1))));
6510 /// \brief Lower an argument list according to the target calling convention.
6512 /// \return A tuple of <return-value, token-chain>
6514 /// This is a helper for lowering intrinsics that follow a target calling
6515 /// convention or require stack pointer adjustment. Only a subset of the
6516 /// intrinsic's operands need to participate in the calling convention.
6517 std::pair<SDValue, SDValue>
6518 SelectionDAGBuilder::lowerCallOperands(ImmutableCallSite CS, unsigned ArgIdx,
6519 unsigned NumArgs, SDValue Callee,
6521 MachineBasicBlock *LandingPad,
6522 bool IsPatchPoint) {
6523 TargetLowering::ArgListTy Args;
6524 Args.reserve(NumArgs);
6526 // Populate the argument list.
6527 // Attributes for args start at offset 1, after the return attribute.
6528 for (unsigned ArgI = ArgIdx, ArgE = ArgIdx + NumArgs, AttrI = ArgIdx + 1;
6529 ArgI != ArgE; ++ArgI) {
6530 const Value *V = CS->getOperand(ArgI);
6532 assert(!V->getType()->isEmptyTy() && "Empty type passed to intrinsic.");
6534 TargetLowering::ArgListEntry Entry;
6535 Entry.Node = getValue(V);
6536 Entry.Ty = V->getType();
6537 Entry.setAttributes(&CS, AttrI);
6538 Args.push_back(Entry);
6541 TargetLowering::CallLoweringInfo CLI(DAG);
6542 CLI.setDebugLoc(getCurSDLoc()).setChain(getRoot())
6543 .setCallee(CS.getCallingConv(), ReturnTy, Callee, std::move(Args), NumArgs)
6544 .setDiscardResult(CS->use_empty()).setIsPatchPoint(IsPatchPoint);
6546 return lowerInvokable(CLI, LandingPad);
6549 /// \brief Add a stack map intrinsic call's live variable operands to a stackmap
6550 /// or patchpoint target node's operand list.
6552 /// Constants are converted to TargetConstants purely as an optimization to
6553 /// avoid constant materialization and register allocation.
6555 /// FrameIndex operands are converted to TargetFrameIndex so that ISEL does not
6556 /// generate addess computation nodes, and so ExpandISelPseudo can convert the
6557 /// TargetFrameIndex into a DirectMemRefOp StackMap location. This avoids
6558 /// address materialization and register allocation, but may also be required
6559 /// for correctness. If a StackMap (or PatchPoint) intrinsic directly uses an
6560 /// alloca in the entry block, then the runtime may assume that the alloca's
6561 /// StackMap location can be read immediately after compilation and that the
6562 /// location is valid at any point during execution (this is similar to the
6563 /// assumption made by the llvm.gcroot intrinsic). If the alloca's location were
6564 /// only available in a register, then the runtime would need to trap when
6565 /// execution reaches the StackMap in order to read the alloca's location.
6566 static void addStackMapLiveVars(ImmutableCallSite CS, unsigned StartIdx,
6567 SDLoc DL, SmallVectorImpl<SDValue> &Ops,
6568 SelectionDAGBuilder &Builder) {
6569 for (unsigned i = StartIdx, e = CS.arg_size(); i != e; ++i) {
6570 SDValue OpVal = Builder.getValue(CS.getArgument(i));
6571 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(OpVal)) {
6573 Builder.DAG.getTargetConstant(StackMaps::ConstantOp, DL, MVT::i64));
6575 Builder.DAG.getTargetConstant(C->getSExtValue(), DL, MVT::i64));
6576 } else if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(OpVal)) {
6577 const TargetLowering &TLI = Builder.DAG.getTargetLoweringInfo();
6578 Ops.push_back(Builder.DAG.getTargetFrameIndex(
6579 FI->getIndex(), TLI.getPointerTy(Builder.DAG.getDataLayout())));
6581 Ops.push_back(OpVal);
6585 /// \brief Lower llvm.experimental.stackmap directly to its target opcode.
6586 void SelectionDAGBuilder::visitStackmap(const CallInst &CI) {
6587 // void @llvm.experimental.stackmap(i32 <id>, i32 <numShadowBytes>,
6588 // [live variables...])
6590 assert(CI.getType()->isVoidTy() && "Stackmap cannot return a value.");
6592 SDValue Chain, InFlag, Callee, NullPtr;
6593 SmallVector<SDValue, 32> Ops;
6595 SDLoc DL = getCurSDLoc();
6596 Callee = getValue(CI.getCalledValue());
6597 NullPtr = DAG.getIntPtrConstant(0, DL, true);
6599 // The stackmap intrinsic only records the live variables (the arguemnts
6600 // passed to it) and emits NOPS (if requested). Unlike the patchpoint
6601 // intrinsic, this won't be lowered to a function call. This means we don't
6602 // have to worry about calling conventions and target specific lowering code.
6603 // Instead we perform the call lowering right here.
6605 // chain, flag = CALLSEQ_START(chain, 0)
6606 // chain, flag = STACKMAP(id, nbytes, ..., chain, flag)
6607 // chain, flag = CALLSEQ_END(chain, 0, 0, flag)
6609 Chain = DAG.getCALLSEQ_START(getRoot(), NullPtr, DL);
6610 InFlag = Chain.getValue(1);
6612 // Add the <id> and <numBytes> constants.
6613 SDValue IDVal = getValue(CI.getOperand(PatchPointOpers::IDPos));
6614 Ops.push_back(DAG.getTargetConstant(
6615 cast<ConstantSDNode>(IDVal)->getZExtValue(), DL, MVT::i64));
6616 SDValue NBytesVal = getValue(CI.getOperand(PatchPointOpers::NBytesPos));
6617 Ops.push_back(DAG.getTargetConstant(
6618 cast<ConstantSDNode>(NBytesVal)->getZExtValue(), DL,
6621 // Push live variables for the stack map.
6622 addStackMapLiveVars(&CI, 2, DL, Ops, *this);
6624 // We are not pushing any register mask info here on the operands list,
6625 // because the stackmap doesn't clobber anything.
6627 // Push the chain and the glue flag.
6628 Ops.push_back(Chain);
6629 Ops.push_back(InFlag);
6631 // Create the STACKMAP node.
6632 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
6633 SDNode *SM = DAG.getMachineNode(TargetOpcode::STACKMAP, DL, NodeTys, Ops);
6634 Chain = SDValue(SM, 0);
6635 InFlag = Chain.getValue(1);
6637 Chain = DAG.getCALLSEQ_END(Chain, NullPtr, NullPtr, InFlag, DL);
6639 // Stackmaps don't generate values, so nothing goes into the NodeMap.
6641 // Set the root to the target-lowered call chain.
6644 // Inform the Frame Information that we have a stackmap in this function.
6645 FuncInfo.MF->getFrameInfo()->setHasStackMap();
6648 /// \brief Lower llvm.experimental.patchpoint directly to its target opcode.
6649 void SelectionDAGBuilder::visitPatchpoint(ImmutableCallSite CS,
6650 MachineBasicBlock *LandingPad) {
6651 // void|i64 @llvm.experimental.patchpoint.void|i64(i64 <id>,
6656 // [live variables...])
6658 CallingConv::ID CC = CS.getCallingConv();
6659 bool IsAnyRegCC = CC == CallingConv::AnyReg;
6660 bool HasDef = !CS->getType()->isVoidTy();
6661 SDLoc dl = getCurSDLoc();
6662 SDValue Callee = getValue(CS->getOperand(PatchPointOpers::TargetPos));
6664 // Handle immediate and symbolic callees.
6665 if (auto* ConstCallee = dyn_cast<ConstantSDNode>(Callee))
6666 Callee = DAG.getIntPtrConstant(ConstCallee->getZExtValue(), dl,
6668 else if (auto* SymbolicCallee = dyn_cast<GlobalAddressSDNode>(Callee))
6669 Callee = DAG.getTargetGlobalAddress(SymbolicCallee->getGlobal(),
6670 SDLoc(SymbolicCallee),
6671 SymbolicCallee->getValueType(0));
6673 // Get the real number of arguments participating in the call <numArgs>
6674 SDValue NArgVal = getValue(CS.getArgument(PatchPointOpers::NArgPos));
6675 unsigned NumArgs = cast<ConstantSDNode>(NArgVal)->getZExtValue();
6677 // Skip the four meta args: <id>, <numNopBytes>, <target>, <numArgs>
6678 // Intrinsics include all meta-operands up to but not including CC.
6679 unsigned NumMetaOpers = PatchPointOpers::CCPos;
6680 assert(CS.arg_size() >= NumMetaOpers + NumArgs &&
6681 "Not enough arguments provided to the patchpoint intrinsic");
6683 // For AnyRegCC the arguments are lowered later on manually.
6684 unsigned NumCallArgs = IsAnyRegCC ? 0 : NumArgs;
6686 IsAnyRegCC ? Type::getVoidTy(*DAG.getContext()) : CS->getType();
6687 std::pair<SDValue, SDValue> Result =
6688 lowerCallOperands(CS, NumMetaOpers, NumCallArgs, Callee, ReturnTy,
6691 SDNode *CallEnd = Result.second.getNode();
6692 if (HasDef && (CallEnd->getOpcode() == ISD::CopyFromReg))
6693 CallEnd = CallEnd->getOperand(0).getNode();
6695 /// Get a call instruction from the call sequence chain.
6696 /// Tail calls are not allowed.
6697 assert(CallEnd->getOpcode() == ISD::CALLSEQ_END &&
6698 "Expected a callseq node.");
6699 SDNode *Call = CallEnd->getOperand(0).getNode();
6700 bool HasGlue = Call->getGluedNode();
6702 // Replace the target specific call node with the patchable intrinsic.
6703 SmallVector<SDValue, 8> Ops;
6705 // Add the <id> and <numBytes> constants.
6706 SDValue IDVal = getValue(CS->getOperand(PatchPointOpers::IDPos));
6707 Ops.push_back(DAG.getTargetConstant(
6708 cast<ConstantSDNode>(IDVal)->getZExtValue(), dl, MVT::i64));
6709 SDValue NBytesVal = getValue(CS->getOperand(PatchPointOpers::NBytesPos));
6710 Ops.push_back(DAG.getTargetConstant(
6711 cast<ConstantSDNode>(NBytesVal)->getZExtValue(), dl,
6715 Ops.push_back(Callee);
6717 // Adjust <numArgs> to account for any arguments that have been passed on the
6719 // Call Node: Chain, Target, {Args}, RegMask, [Glue]
6720 unsigned NumCallRegArgs = Call->getNumOperands() - (HasGlue ? 4 : 3);
6721 NumCallRegArgs = IsAnyRegCC ? NumArgs : NumCallRegArgs;
6722 Ops.push_back(DAG.getTargetConstant(NumCallRegArgs, dl, MVT::i32));
6724 // Add the calling convention
6725 Ops.push_back(DAG.getTargetConstant((unsigned)CC, dl, MVT::i32));
6727 // Add the arguments we omitted previously. The register allocator should
6728 // place these in any free register.
6730 for (unsigned i = NumMetaOpers, e = NumMetaOpers + NumArgs; i != e; ++i)
6731 Ops.push_back(getValue(CS.getArgument(i)));
6733 // Push the arguments from the call instruction up to the register mask.
6734 SDNode::op_iterator e = HasGlue ? Call->op_end()-2 : Call->op_end()-1;
6735 Ops.append(Call->op_begin() + 2, e);
6737 // Push live variables for the stack map.
6738 addStackMapLiveVars(CS, NumMetaOpers + NumArgs, dl, Ops, *this);
6740 // Push the register mask info.
6742 Ops.push_back(*(Call->op_end()-2));
6744 Ops.push_back(*(Call->op_end()-1));
6746 // Push the chain (this is originally the first operand of the call, but
6747 // becomes now the last or second to last operand).
6748 Ops.push_back(*(Call->op_begin()));
6750 // Push the glue flag (last operand).
6752 Ops.push_back(*(Call->op_end()-1));
6755 if (IsAnyRegCC && HasDef) {
6756 // Create the return types based on the intrinsic definition
6757 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6758 SmallVector<EVT, 3> ValueVTs;
6759 ComputeValueVTs(TLI, DAG.getDataLayout(), CS->getType(), ValueVTs);
6760 assert(ValueVTs.size() == 1 && "Expected only one return value type.");
6762 // There is always a chain and a glue type at the end
6763 ValueVTs.push_back(MVT::Other);
6764 ValueVTs.push_back(MVT::Glue);
6765 NodeTys = DAG.getVTList(ValueVTs);
6767 NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
6769 // Replace the target specific call node with a PATCHPOINT node.
6770 MachineSDNode *MN = DAG.getMachineNode(TargetOpcode::PATCHPOINT,
6773 // Update the NodeMap.
6776 setValue(CS.getInstruction(), SDValue(MN, 0));
6778 setValue(CS.getInstruction(), Result.first);
6781 // Fixup the consumers of the intrinsic. The chain and glue may be used in the
6782 // call sequence. Furthermore the location of the chain and glue can change
6783 // when the AnyReg calling convention is used and the intrinsic returns a
6785 if (IsAnyRegCC && HasDef) {
6786 SDValue From[] = {SDValue(Call, 0), SDValue(Call, 1)};
6787 SDValue To[] = {SDValue(MN, 1), SDValue(MN, 2)};
6788 DAG.ReplaceAllUsesOfValuesWith(From, To, 2);
6790 DAG.ReplaceAllUsesWith(Call, MN);
6791 DAG.DeleteNode(Call);
6793 // Inform the Frame Information that we have a patchpoint in this function.
6794 FuncInfo.MF->getFrameInfo()->setHasPatchPoint();
6797 /// Returns an AttributeSet representing the attributes applied to the return
6798 /// value of the given call.
6799 static AttributeSet getReturnAttrs(TargetLowering::CallLoweringInfo &CLI) {
6800 SmallVector<Attribute::AttrKind, 2> Attrs;
6802 Attrs.push_back(Attribute::SExt);
6804 Attrs.push_back(Attribute::ZExt);
6806 Attrs.push_back(Attribute::InReg);
6808 return AttributeSet::get(CLI.RetTy->getContext(), AttributeSet::ReturnIndex,
6812 /// TargetLowering::LowerCallTo - This is the default LowerCallTo
6813 /// implementation, which just calls LowerCall.
6814 /// FIXME: When all targets are
6815 /// migrated to using LowerCall, this hook should be integrated into SDISel.
6816 std::pair<SDValue, SDValue>
6817 TargetLowering::LowerCallTo(TargetLowering::CallLoweringInfo &CLI) const {
6818 // Handle the incoming return values from the call.
6820 Type *OrigRetTy = CLI.RetTy;
6821 SmallVector<EVT, 4> RetTys;
6822 SmallVector<uint64_t, 4> Offsets;
6823 auto &DL = CLI.DAG.getDataLayout();
6824 ComputeValueVTs(*this, DL, CLI.RetTy, RetTys, &Offsets);
6826 SmallVector<ISD::OutputArg, 4> Outs;
6827 GetReturnInfo(CLI.RetTy, getReturnAttrs(CLI), Outs, *this, DL);
6829 bool CanLowerReturn =
6830 this->CanLowerReturn(CLI.CallConv, CLI.DAG.getMachineFunction(),
6831 CLI.IsVarArg, Outs, CLI.RetTy->getContext());
6833 SDValue DemoteStackSlot;
6834 int DemoteStackIdx = -100;
6835 if (!CanLowerReturn) {
6836 // FIXME: equivalent assert?
6837 // assert(!CS.hasInAllocaArgument() &&
6838 // "sret demotion is incompatible with inalloca");
6839 uint64_t TySize = DL.getTypeAllocSize(CLI.RetTy);
6840 unsigned Align = DL.getPrefTypeAlignment(CLI.RetTy);
6841 MachineFunction &MF = CLI.DAG.getMachineFunction();
6842 DemoteStackIdx = MF.getFrameInfo()->CreateStackObject(TySize, Align, false);
6843 Type *StackSlotPtrType = PointerType::getUnqual(CLI.RetTy);
6845 DemoteStackSlot = CLI.DAG.getFrameIndex(DemoteStackIdx, getPointerTy(DL));
6847 Entry.Node = DemoteStackSlot;
6848 Entry.Ty = StackSlotPtrType;
6849 Entry.isSExt = false;
6850 Entry.isZExt = false;
6851 Entry.isInReg = false;
6852 Entry.isSRet = true;
6853 Entry.isNest = false;
6854 Entry.isByVal = false;
6855 Entry.isReturned = false;
6856 Entry.Alignment = Align;
6857 CLI.getArgs().insert(CLI.getArgs().begin(), Entry);
6858 CLI.RetTy = Type::getVoidTy(CLI.RetTy->getContext());
6860 // sret demotion isn't compatible with tail-calls, since the sret argument
6861 // points into the callers stack frame.
6862 CLI.IsTailCall = false;
6864 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
6866 MVT RegisterVT = getRegisterType(CLI.RetTy->getContext(), VT);
6867 unsigned NumRegs = getNumRegisters(CLI.RetTy->getContext(), VT);
6868 for (unsigned i = 0; i != NumRegs; ++i) {
6869 ISD::InputArg MyFlags;
6870 MyFlags.VT = RegisterVT;
6872 MyFlags.Used = CLI.IsReturnValueUsed;
6874 MyFlags.Flags.setSExt();
6876 MyFlags.Flags.setZExt();
6878 MyFlags.Flags.setInReg();
6879 CLI.Ins.push_back(MyFlags);
6884 // Handle all of the outgoing arguments.
6886 CLI.OutVals.clear();
6887 ArgListTy &Args = CLI.getArgs();
6888 for (unsigned i = 0, e = Args.size(); i != e; ++i) {
6889 SmallVector<EVT, 4> ValueVTs;
6890 ComputeValueVTs(*this, DL, Args[i].Ty, ValueVTs);
6891 Type *FinalType = Args[i].Ty;
6892 if (Args[i].isByVal)
6893 FinalType = cast<PointerType>(Args[i].Ty)->getElementType();
6894 bool NeedsRegBlock = functionArgumentNeedsConsecutiveRegisters(
6895 FinalType, CLI.CallConv, CLI.IsVarArg);
6896 for (unsigned Value = 0, NumValues = ValueVTs.size(); Value != NumValues;
6898 EVT VT = ValueVTs[Value];
6899 Type *ArgTy = VT.getTypeForEVT(CLI.RetTy->getContext());
6900 SDValue Op = SDValue(Args[i].Node.getNode(),
6901 Args[i].Node.getResNo() + Value);
6902 ISD::ArgFlagsTy Flags;
6903 unsigned OriginalAlignment = DL.getABITypeAlignment(ArgTy);
6909 if (Args[i].isInReg)
6913 if (Args[i].isByVal)
6915 if (Args[i].isInAlloca) {
6916 Flags.setInAlloca();
6917 // Set the byval flag for CCAssignFn callbacks that don't know about
6918 // inalloca. This way we can know how many bytes we should've allocated
6919 // and how many bytes a callee cleanup function will pop. If we port
6920 // inalloca to more targets, we'll have to add custom inalloca handling
6921 // in the various CC lowering callbacks.
6924 if (Args[i].isByVal || Args[i].isInAlloca) {
6925 PointerType *Ty = cast<PointerType>(Args[i].Ty);
6926 Type *ElementTy = Ty->getElementType();
6927 Flags.setByValSize(DL.getTypeAllocSize(ElementTy));
6928 // For ByVal, alignment should come from FE. BE will guess if this
6929 // info is not there but there are cases it cannot get right.
6930 unsigned FrameAlign;
6931 if (Args[i].Alignment)
6932 FrameAlign = Args[i].Alignment;
6934 FrameAlign = getByValTypeAlignment(ElementTy, DL);
6935 Flags.setByValAlign(FrameAlign);
6940 Flags.setInConsecutiveRegs();
6941 Flags.setOrigAlign(OriginalAlignment);
6943 MVT PartVT = getRegisterType(CLI.RetTy->getContext(), VT);
6944 unsigned NumParts = getNumRegisters(CLI.RetTy->getContext(), VT);
6945 SmallVector<SDValue, 4> Parts(NumParts);
6946 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
6949 ExtendKind = ISD::SIGN_EXTEND;
6950 else if (Args[i].isZExt)
6951 ExtendKind = ISD::ZERO_EXTEND;
6953 // Conservatively only handle 'returned' on non-vectors for now
6954 if (Args[i].isReturned && !Op.getValueType().isVector()) {
6955 assert(CLI.RetTy == Args[i].Ty && RetTys.size() == NumValues &&
6956 "unexpected use of 'returned'");
6957 // Before passing 'returned' to the target lowering code, ensure that
6958 // either the register MVT and the actual EVT are the same size or that
6959 // the return value and argument are extended in the same way; in these
6960 // cases it's safe to pass the argument register value unchanged as the
6961 // return register value (although it's at the target's option whether
6963 // TODO: allow code generation to take advantage of partially preserved
6964 // registers rather than clobbering the entire register when the
6965 // parameter extension method is not compatible with the return
6967 if ((NumParts * PartVT.getSizeInBits() == VT.getSizeInBits()) ||
6968 (ExtendKind != ISD::ANY_EXTEND &&
6969 CLI.RetSExt == Args[i].isSExt && CLI.RetZExt == Args[i].isZExt))
6970 Flags.setReturned();
6973 getCopyToParts(CLI.DAG, CLI.DL, Op, &Parts[0], NumParts, PartVT,
6974 CLI.CS ? CLI.CS->getInstruction() : nullptr, ExtendKind);
6976 for (unsigned j = 0; j != NumParts; ++j) {
6977 // if it isn't first piece, alignment must be 1
6978 ISD::OutputArg MyFlags(Flags, Parts[j].getValueType(), VT,
6979 i < CLI.NumFixedArgs,
6980 i, j*Parts[j].getValueType().getStoreSize());
6981 if (NumParts > 1 && j == 0)
6982 MyFlags.Flags.setSplit();
6984 MyFlags.Flags.setOrigAlign(1);
6986 CLI.Outs.push_back(MyFlags);
6987 CLI.OutVals.push_back(Parts[j]);
6990 if (NeedsRegBlock && Value == NumValues - 1)
6991 CLI.Outs[CLI.Outs.size() - 1].Flags.setInConsecutiveRegsLast();
6995 SmallVector<SDValue, 4> InVals;
6996 CLI.Chain = LowerCall(CLI, InVals);
6998 // Verify that the target's LowerCall behaved as expected.
6999 assert(CLI.Chain.getNode() && CLI.Chain.getValueType() == MVT::Other &&
7000 "LowerCall didn't return a valid chain!");
7001 assert((!CLI.IsTailCall || InVals.empty()) &&
7002 "LowerCall emitted a return value for a tail call!");
7003 assert((CLI.IsTailCall || InVals.size() == CLI.Ins.size()) &&
7004 "LowerCall didn't emit the correct number of values!");
7006 // For a tail call, the return value is merely live-out and there aren't
7007 // any nodes in the DAG representing it. Return a special value to
7008 // indicate that a tail call has been emitted and no more Instructions
7009 // should be processed in the current block.
7010 if (CLI.IsTailCall) {
7011 CLI.DAG.setRoot(CLI.Chain);
7012 return std::make_pair(SDValue(), SDValue());
7015 DEBUG(for (unsigned i = 0, e = CLI.Ins.size(); i != e; ++i) {
7016 assert(InVals[i].getNode() &&
7017 "LowerCall emitted a null value!");
7018 assert(EVT(CLI.Ins[i].VT) == InVals[i].getValueType() &&
7019 "LowerCall emitted a value with the wrong type!");
7022 SmallVector<SDValue, 4> ReturnValues;
7023 if (!CanLowerReturn) {
7024 // The instruction result is the result of loading from the
7025 // hidden sret parameter.
7026 SmallVector<EVT, 1> PVTs;
7027 Type *PtrRetTy = PointerType::getUnqual(OrigRetTy);
7029 ComputeValueVTs(*this, DL, PtrRetTy, PVTs);
7030 assert(PVTs.size() == 1 && "Pointers should fit in one register");
7031 EVT PtrVT = PVTs[0];
7033 unsigned NumValues = RetTys.size();
7034 ReturnValues.resize(NumValues);
7035 SmallVector<SDValue, 4> Chains(NumValues);
7037 for (unsigned i = 0; i < NumValues; ++i) {
7038 SDValue Add = CLI.DAG.getNode(ISD::ADD, CLI.DL, PtrVT, DemoteStackSlot,
7039 CLI.DAG.getConstant(Offsets[i], CLI.DL,
7041 SDValue L = CLI.DAG.getLoad(
7042 RetTys[i], CLI.DL, CLI.Chain, Add,
7043 MachinePointerInfo::getFixedStack(CLI.DAG.getMachineFunction(),
7044 DemoteStackIdx, Offsets[i]),
7045 false, false, false, 1);
7046 ReturnValues[i] = L;
7047 Chains[i] = L.getValue(1);
7050 CLI.Chain = CLI.DAG.getNode(ISD::TokenFactor, CLI.DL, MVT::Other, Chains);
7052 // Collect the legal value parts into potentially illegal values
7053 // that correspond to the original function's return values.
7054 ISD::NodeType AssertOp = ISD::DELETED_NODE;
7056 AssertOp = ISD::AssertSext;
7057 else if (CLI.RetZExt)
7058 AssertOp = ISD::AssertZext;
7059 unsigned CurReg = 0;
7060 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
7062 MVT RegisterVT = getRegisterType(CLI.RetTy->getContext(), VT);
7063 unsigned NumRegs = getNumRegisters(CLI.RetTy->getContext(), VT);
7065 ReturnValues.push_back(getCopyFromParts(CLI.DAG, CLI.DL, &InVals[CurReg],
7066 NumRegs, RegisterVT, VT, nullptr,
7071 // For a function returning void, there is no return value. We can't create
7072 // such a node, so we just return a null return value in that case. In
7073 // that case, nothing will actually look at the value.
7074 if (ReturnValues.empty())
7075 return std::make_pair(SDValue(), CLI.Chain);
7078 SDValue Res = CLI.DAG.getNode(ISD::MERGE_VALUES, CLI.DL,
7079 CLI.DAG.getVTList(RetTys), ReturnValues);
7080 return std::make_pair(Res, CLI.Chain);
7083 void TargetLowering::LowerOperationWrapper(SDNode *N,
7084 SmallVectorImpl<SDValue> &Results,
7085 SelectionDAG &DAG) const {
7086 SDValue Res = LowerOperation(SDValue(N, 0), DAG);
7088 Results.push_back(Res);
7091 SDValue TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
7092 llvm_unreachable("LowerOperation not implemented for this target!");
7096 SelectionDAGBuilder::CopyValueToVirtualRegister(const Value *V, unsigned Reg) {
7097 SDValue Op = getNonRegisterValue(V);
7098 assert((Op.getOpcode() != ISD::CopyFromReg ||
7099 cast<RegisterSDNode>(Op.getOperand(1))->getReg() != Reg) &&
7100 "Copy from a reg to the same reg!");
7101 assert(!TargetRegisterInfo::isPhysicalRegister(Reg) && "Is a physreg");
7103 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
7104 RegsForValue RFV(V->getContext(), TLI, DAG.getDataLayout(), Reg,
7106 SDValue Chain = DAG.getEntryNode();
7108 ISD::NodeType ExtendType = (FuncInfo.PreferredExtendType.find(V) ==
7109 FuncInfo.PreferredExtendType.end())
7111 : FuncInfo.PreferredExtendType[V];
7112 RFV.getCopyToRegs(Op, DAG, getCurSDLoc(), Chain, nullptr, V, ExtendType);
7113 PendingExports.push_back(Chain);
7116 #include "llvm/CodeGen/SelectionDAGISel.h"
7118 /// isOnlyUsedInEntryBlock - If the specified argument is only used in the
7119 /// entry block, return true. This includes arguments used by switches, since
7120 /// the switch may expand into multiple basic blocks.
7121 static bool isOnlyUsedInEntryBlock(const Argument *A, bool FastISel) {
7122 // With FastISel active, we may be splitting blocks, so force creation
7123 // of virtual registers for all non-dead arguments.
7125 return A->use_empty();
7127 const BasicBlock *Entry = A->getParent()->begin();
7128 for (const User *U : A->users())
7129 if (cast<Instruction>(U)->getParent() != Entry || isa<SwitchInst>(U))
7130 return false; // Use not in entry block.
7135 void SelectionDAGISel::LowerArguments(const Function &F) {
7136 SelectionDAG &DAG = SDB->DAG;
7137 SDLoc dl = SDB->getCurSDLoc();
7138 const DataLayout &DL = DAG.getDataLayout();
7139 SmallVector<ISD::InputArg, 16> Ins;
7141 if (!FuncInfo->CanLowerReturn) {
7142 // Put in an sret pointer parameter before all the other parameters.
7143 SmallVector<EVT, 1> ValueVTs;
7144 ComputeValueVTs(*TLI, DAG.getDataLayout(),
7145 PointerType::getUnqual(F.getReturnType()), ValueVTs);
7147 // NOTE: Assuming that a pointer will never break down to more than one VT
7149 ISD::ArgFlagsTy Flags;
7151 MVT RegisterVT = TLI->getRegisterType(*DAG.getContext(), ValueVTs[0]);
7152 ISD::InputArg RetArg(Flags, RegisterVT, ValueVTs[0], true,
7153 ISD::InputArg::NoArgIndex, 0);
7154 Ins.push_back(RetArg);
7157 // Set up the incoming argument description vector.
7159 for (Function::const_arg_iterator I = F.arg_begin(), E = F.arg_end();
7160 I != E; ++I, ++Idx) {
7161 SmallVector<EVT, 4> ValueVTs;
7162 ComputeValueVTs(*TLI, DAG.getDataLayout(), I->getType(), ValueVTs);
7163 bool isArgValueUsed = !I->use_empty();
7164 unsigned PartBase = 0;
7165 Type *FinalType = I->getType();
7166 if (F.getAttributes().hasAttribute(Idx, Attribute::ByVal))
7167 FinalType = cast<PointerType>(FinalType)->getElementType();
7168 bool NeedsRegBlock = TLI->functionArgumentNeedsConsecutiveRegisters(
7169 FinalType, F.getCallingConv(), F.isVarArg());
7170 for (unsigned Value = 0, NumValues = ValueVTs.size();
7171 Value != NumValues; ++Value) {
7172 EVT VT = ValueVTs[Value];
7173 Type *ArgTy = VT.getTypeForEVT(*DAG.getContext());
7174 ISD::ArgFlagsTy Flags;
7175 unsigned OriginalAlignment = DL.getABITypeAlignment(ArgTy);
7177 if (F.getAttributes().hasAttribute(Idx, Attribute::ZExt))
7179 if (F.getAttributes().hasAttribute(Idx, Attribute::SExt))
7181 if (F.getAttributes().hasAttribute(Idx, Attribute::InReg))
7183 if (F.getAttributes().hasAttribute(Idx, Attribute::StructRet))
7185 if (F.getAttributes().hasAttribute(Idx, Attribute::ByVal))
7187 if (F.getAttributes().hasAttribute(Idx, Attribute::InAlloca)) {
7188 Flags.setInAlloca();
7189 // Set the byval flag for CCAssignFn callbacks that don't know about
7190 // inalloca. This way we can know how many bytes we should've allocated
7191 // and how many bytes a callee cleanup function will pop. If we port
7192 // inalloca to more targets, we'll have to add custom inalloca handling
7193 // in the various CC lowering callbacks.
7196 if (Flags.isByVal() || Flags.isInAlloca()) {
7197 PointerType *Ty = cast<PointerType>(I->getType());
7198 Type *ElementTy = Ty->getElementType();
7199 Flags.setByValSize(DL.getTypeAllocSize(ElementTy));
7200 // For ByVal, alignment should be passed from FE. BE will guess if
7201 // this info is not there but there are cases it cannot get right.
7202 unsigned FrameAlign;
7203 if (F.getParamAlignment(Idx))
7204 FrameAlign = F.getParamAlignment(Idx);
7206 FrameAlign = TLI->getByValTypeAlignment(ElementTy, DL);
7207 Flags.setByValAlign(FrameAlign);
7209 if (F.getAttributes().hasAttribute(Idx, Attribute::Nest))
7212 Flags.setInConsecutiveRegs();
7213 Flags.setOrigAlign(OriginalAlignment);
7215 MVT RegisterVT = TLI->getRegisterType(*CurDAG->getContext(), VT);
7216 unsigned NumRegs = TLI->getNumRegisters(*CurDAG->getContext(), VT);
7217 for (unsigned i = 0; i != NumRegs; ++i) {
7218 ISD::InputArg MyFlags(Flags, RegisterVT, VT, isArgValueUsed,
7219 Idx-1, PartBase+i*RegisterVT.getStoreSize());
7220 if (NumRegs > 1 && i == 0)
7221 MyFlags.Flags.setSplit();
7222 // if it isn't first piece, alignment must be 1
7224 MyFlags.Flags.setOrigAlign(1);
7225 Ins.push_back(MyFlags);
7227 if (NeedsRegBlock && Value == NumValues - 1)
7228 Ins[Ins.size() - 1].Flags.setInConsecutiveRegsLast();
7229 PartBase += VT.getStoreSize();
7233 // Call the target to set up the argument values.
7234 SmallVector<SDValue, 8> InVals;
7235 SDValue NewRoot = TLI->LowerFormalArguments(
7236 DAG.getRoot(), F.getCallingConv(), F.isVarArg(), Ins, dl, DAG, InVals);
7238 // Verify that the target's LowerFormalArguments behaved as expected.
7239 assert(NewRoot.getNode() && NewRoot.getValueType() == MVT::Other &&
7240 "LowerFormalArguments didn't return a valid chain!");
7241 assert(InVals.size() == Ins.size() &&
7242 "LowerFormalArguments didn't emit the correct number of values!");
7244 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
7245 assert(InVals[i].getNode() &&
7246 "LowerFormalArguments emitted a null value!");
7247 assert(EVT(Ins[i].VT) == InVals[i].getValueType() &&
7248 "LowerFormalArguments emitted a value with the wrong type!");
7252 // Update the DAG with the new chain value resulting from argument lowering.
7253 DAG.setRoot(NewRoot);
7255 // Set up the argument values.
7258 if (!FuncInfo->CanLowerReturn) {
7259 // Create a virtual register for the sret pointer, and put in a copy
7260 // from the sret argument into it.
7261 SmallVector<EVT, 1> ValueVTs;
7262 ComputeValueVTs(*TLI, DAG.getDataLayout(),
7263 PointerType::getUnqual(F.getReturnType()), ValueVTs);
7264 MVT VT = ValueVTs[0].getSimpleVT();
7265 MVT RegVT = TLI->getRegisterType(*CurDAG->getContext(), VT);
7266 ISD::NodeType AssertOp = ISD::DELETED_NODE;
7267 SDValue ArgValue = getCopyFromParts(DAG, dl, &InVals[0], 1,
7268 RegVT, VT, nullptr, AssertOp);
7270 MachineFunction& MF = SDB->DAG.getMachineFunction();
7271 MachineRegisterInfo& RegInfo = MF.getRegInfo();
7272 unsigned SRetReg = RegInfo.createVirtualRegister(TLI->getRegClassFor(RegVT));
7273 FuncInfo->DemoteRegister = SRetReg;
7275 SDB->DAG.getCopyToReg(NewRoot, SDB->getCurSDLoc(), SRetReg, ArgValue);
7276 DAG.setRoot(NewRoot);
7278 // i indexes lowered arguments. Bump it past the hidden sret argument.
7279 // Idx indexes LLVM arguments. Don't touch it.
7283 for (Function::const_arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E;
7285 SmallVector<SDValue, 4> ArgValues;
7286 SmallVector<EVT, 4> ValueVTs;
7287 ComputeValueVTs(*TLI, DAG.getDataLayout(), I->getType(), ValueVTs);
7288 unsigned NumValues = ValueVTs.size();
7290 // If this argument is unused then remember its value. It is used to generate
7291 // debugging information.
7292 if (I->use_empty() && NumValues) {
7293 SDB->setUnusedArgValue(I, InVals[i]);
7295 // Also remember any frame index for use in FastISel.
7296 if (FrameIndexSDNode *FI =
7297 dyn_cast<FrameIndexSDNode>(InVals[i].getNode()))
7298 FuncInfo->setArgumentFrameIndex(I, FI->getIndex());
7301 for (unsigned Val = 0; Val != NumValues; ++Val) {
7302 EVT VT = ValueVTs[Val];
7303 MVT PartVT = TLI->getRegisterType(*CurDAG->getContext(), VT);
7304 unsigned NumParts = TLI->getNumRegisters(*CurDAG->getContext(), VT);
7306 if (!I->use_empty()) {
7307 ISD::NodeType AssertOp = ISD::DELETED_NODE;
7308 if (F.getAttributes().hasAttribute(Idx, Attribute::SExt))
7309 AssertOp = ISD::AssertSext;
7310 else if (F.getAttributes().hasAttribute(Idx, Attribute::ZExt))
7311 AssertOp = ISD::AssertZext;
7313 ArgValues.push_back(getCopyFromParts(DAG, dl, &InVals[i],
7314 NumParts, PartVT, VT,
7315 nullptr, AssertOp));
7321 // We don't need to do anything else for unused arguments.
7322 if (ArgValues.empty())
7325 // Note down frame index.
7326 if (FrameIndexSDNode *FI =
7327 dyn_cast<FrameIndexSDNode>(ArgValues[0].getNode()))
7328 FuncInfo->setArgumentFrameIndex(I, FI->getIndex());
7330 SDValue Res = DAG.getMergeValues(makeArrayRef(ArgValues.data(), NumValues),
7331 SDB->getCurSDLoc());
7333 SDB->setValue(I, Res);
7334 if (!TM.Options.EnableFastISel && Res.getOpcode() == ISD::BUILD_PAIR) {
7335 if (LoadSDNode *LNode =
7336 dyn_cast<LoadSDNode>(Res.getOperand(0).getNode()))
7337 if (FrameIndexSDNode *FI =
7338 dyn_cast<FrameIndexSDNode>(LNode->getBasePtr().getNode()))
7339 FuncInfo->setArgumentFrameIndex(I, FI->getIndex());
7342 // If this argument is live outside of the entry block, insert a copy from
7343 // wherever we got it to the vreg that other BB's will reference it as.
7344 if (!TM.Options.EnableFastISel && Res.getOpcode() == ISD::CopyFromReg) {
7345 // If we can, though, try to skip creating an unnecessary vreg.
7346 // FIXME: This isn't very clean... it would be nice to make this more
7347 // general. It's also subtly incompatible with the hacks FastISel
7349 unsigned Reg = cast<RegisterSDNode>(Res.getOperand(1))->getReg();
7350 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
7351 FuncInfo->ValueMap[I] = Reg;
7355 if (!isOnlyUsedInEntryBlock(I, TM.Options.EnableFastISel)) {
7356 FuncInfo->InitializeRegForValue(I);
7357 SDB->CopyToExportRegsIfNeeded(I);
7361 assert(i == InVals.size() && "Argument register count mismatch!");
7363 // Finally, if the target has anything special to do, allow it to do so.
7364 EmitFunctionEntryCode();
7367 /// Handle PHI nodes in successor blocks. Emit code into the SelectionDAG to
7368 /// ensure constants are generated when needed. Remember the virtual registers
7369 /// that need to be added to the Machine PHI nodes as input. We cannot just
7370 /// directly add them, because expansion might result in multiple MBB's for one
7371 /// BB. As such, the start of the BB might correspond to a different MBB than
7375 SelectionDAGBuilder::HandlePHINodesInSuccessorBlocks(const BasicBlock *LLVMBB) {
7376 const TerminatorInst *TI = LLVMBB->getTerminator();
7378 SmallPtrSet<MachineBasicBlock *, 4> SuccsHandled;
7380 // Check PHI nodes in successors that expect a value to be available from this
7382 for (unsigned succ = 0, e = TI->getNumSuccessors(); succ != e; ++succ) {
7383 const BasicBlock *SuccBB = TI->getSuccessor(succ);
7384 if (!isa<PHINode>(SuccBB->begin())) continue;
7385 MachineBasicBlock *SuccMBB = FuncInfo.MBBMap[SuccBB];
7387 // If this terminator has multiple identical successors (common for
7388 // switches), only handle each succ once.
7389 if (!SuccsHandled.insert(SuccMBB).second)
7392 MachineBasicBlock::iterator MBBI = SuccMBB->begin();
7394 // At this point we know that there is a 1-1 correspondence between LLVM PHI
7395 // nodes and Machine PHI nodes, but the incoming operands have not been
7397 for (BasicBlock::const_iterator I = SuccBB->begin();
7398 const PHINode *PN = dyn_cast<PHINode>(I); ++I) {
7399 // Ignore dead phi's.
7400 if (PN->use_empty()) continue;
7403 if (PN->getType()->isEmptyTy())
7407 const Value *PHIOp = PN->getIncomingValueForBlock(LLVMBB);
7409 if (const Constant *C = dyn_cast<Constant>(PHIOp)) {
7410 unsigned &RegOut = ConstantsOut[C];
7412 RegOut = FuncInfo.CreateRegs(C->getType());
7413 CopyValueToVirtualRegister(C, RegOut);
7417 DenseMap<const Value *, unsigned>::iterator I =
7418 FuncInfo.ValueMap.find(PHIOp);
7419 if (I != FuncInfo.ValueMap.end())
7422 assert(isa<AllocaInst>(PHIOp) &&
7423 FuncInfo.StaticAllocaMap.count(cast<AllocaInst>(PHIOp)) &&
7424 "Didn't codegen value into a register!??");
7425 Reg = FuncInfo.CreateRegs(PHIOp->getType());
7426 CopyValueToVirtualRegister(PHIOp, Reg);
7430 // Remember that this register needs to added to the machine PHI node as
7431 // the input for this MBB.
7432 SmallVector<EVT, 4> ValueVTs;
7433 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
7434 ComputeValueVTs(TLI, DAG.getDataLayout(), PN->getType(), ValueVTs);
7435 for (unsigned vti = 0, vte = ValueVTs.size(); vti != vte; ++vti) {
7436 EVT VT = ValueVTs[vti];
7437 unsigned NumRegisters = TLI.getNumRegisters(*DAG.getContext(), VT);
7438 for (unsigned i = 0, e = NumRegisters; i != e; ++i)
7439 FuncInfo.PHINodesToUpdate.push_back(std::make_pair(MBBI++, Reg+i));
7440 Reg += NumRegisters;
7445 ConstantsOut.clear();
7448 /// Add a successor MBB to ParentMBB< creating a new MachineBB for BB if SuccMBB
7451 SelectionDAGBuilder::StackProtectorDescriptor::
7452 AddSuccessorMBB(const BasicBlock *BB,
7453 MachineBasicBlock *ParentMBB,
7455 MachineBasicBlock *SuccMBB) {
7456 // If SuccBB has not been created yet, create it.
7458 MachineFunction *MF = ParentMBB->getParent();
7459 MachineFunction::iterator BBI = ParentMBB;
7460 SuccMBB = MF->CreateMachineBasicBlock(BB);
7461 MF->insert(++BBI, SuccMBB);
7463 // Add it as a successor of ParentMBB.
7464 ParentMBB->addSuccessor(
7465 SuccMBB, BranchProbabilityInfo::getBranchWeightStackProtector(IsLikely));
7469 MachineBasicBlock *SelectionDAGBuilder::NextBlock(MachineBasicBlock *MBB) {
7470 MachineFunction::iterator I = MBB;
7471 if (++I == FuncInfo.MF->end())
7476 /// During lowering new call nodes can be created (such as memset, etc.).
7477 /// Those will become new roots of the current DAG, but complications arise
7478 /// when they are tail calls. In such cases, the call lowering will update
7479 /// the root, but the builder still needs to know that a tail call has been
7480 /// lowered in order to avoid generating an additional return.
7481 void SelectionDAGBuilder::updateDAGForMaybeTailCall(SDValue MaybeTC) {
7482 // If the node is null, we do have a tail call.
7483 if (MaybeTC.getNode() != nullptr)
7484 DAG.setRoot(MaybeTC);
7489 bool SelectionDAGBuilder::isDense(const CaseClusterVector &Clusters,
7490 unsigned *TotalCases, unsigned First,
7492 assert(Last >= First);
7493 assert(TotalCases[Last] >= TotalCases[First]);
7495 APInt LowCase = Clusters[First].Low->getValue();
7496 APInt HighCase = Clusters[Last].High->getValue();
7497 assert(LowCase.getBitWidth() == HighCase.getBitWidth());
7499 // FIXME: A range of consecutive cases has 100% density, but only requires one
7500 // comparison to lower. We should discriminate against such consecutive ranges
7503 uint64_t Diff = (HighCase - LowCase).getLimitedValue((UINT64_MAX - 1) / 100);
7504 uint64_t Range = Diff + 1;
7507 TotalCases[Last] - (First == 0 ? 0 : TotalCases[First - 1]);
7509 assert(NumCases < UINT64_MAX / 100);
7510 assert(Range >= NumCases);
7512 return NumCases * 100 >= Range * MinJumpTableDensity;
7515 static inline bool areJTsAllowed(const TargetLowering &TLI) {
7516 return TLI.isOperationLegalOrCustom(ISD::BR_JT, MVT::Other) ||
7517 TLI.isOperationLegalOrCustom(ISD::BRIND, MVT::Other);
7520 bool SelectionDAGBuilder::buildJumpTable(CaseClusterVector &Clusters,
7521 unsigned First, unsigned Last,
7522 const SwitchInst *SI,
7523 MachineBasicBlock *DefaultMBB,
7524 CaseCluster &JTCluster) {
7525 assert(First <= Last);
7527 uint32_t Weight = 0;
7528 unsigned NumCmps = 0;
7529 std::vector<MachineBasicBlock*> Table;
7530 DenseMap<MachineBasicBlock*, uint32_t> JTWeights;
7531 for (unsigned I = First; I <= Last; ++I) {
7532 assert(Clusters[I].Kind == CC_Range);
7533 Weight += Clusters[I].Weight;
7534 assert(Weight >= Clusters[I].Weight && "Weight overflow!");
7535 APInt Low = Clusters[I].Low->getValue();
7536 APInt High = Clusters[I].High->getValue();
7537 NumCmps += (Low == High) ? 1 : 2;
7539 // Fill the gap between this and the previous cluster.
7540 APInt PreviousHigh = Clusters[I - 1].High->getValue();
7541 assert(PreviousHigh.slt(Low));
7542 uint64_t Gap = (Low - PreviousHigh).getLimitedValue() - 1;
7543 for (uint64_t J = 0; J < Gap; J++)
7544 Table.push_back(DefaultMBB);
7546 uint64_t ClusterSize = (High - Low).getLimitedValue() + 1;
7547 for (uint64_t J = 0; J < ClusterSize; ++J)
7548 Table.push_back(Clusters[I].MBB);
7549 JTWeights[Clusters[I].MBB] += Clusters[I].Weight;
7552 unsigned NumDests = JTWeights.size();
7553 if (isSuitableForBitTests(NumDests, NumCmps,
7554 Clusters[First].Low->getValue(),
7555 Clusters[Last].High->getValue())) {
7556 // Clusters[First..Last] should be lowered as bit tests instead.
7560 // Create the MBB that will load from and jump through the table.
7561 // Note: We create it here, but it's not inserted into the function yet.
7562 MachineFunction *CurMF = FuncInfo.MF;
7563 MachineBasicBlock *JumpTableMBB =
7564 CurMF->CreateMachineBasicBlock(SI->getParent());
7566 // Add successors. Note: use table order for determinism.
7567 SmallPtrSet<MachineBasicBlock *, 8> Done;
7568 for (MachineBasicBlock *Succ : Table) {
7569 if (Done.count(Succ))
7571 addSuccessorWithWeight(JumpTableMBB, Succ, JTWeights[Succ]);
7575 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
7576 unsigned JTI = CurMF->getOrCreateJumpTableInfo(TLI.getJumpTableEncoding())
7577 ->createJumpTableIndex(Table);
7579 // Set up the jump table info.
7580 JumpTable JT(-1U, JTI, JumpTableMBB, nullptr);
7581 JumpTableHeader JTH(Clusters[First].Low->getValue(),
7582 Clusters[Last].High->getValue(), SI->getCondition(),
7584 JTCases.emplace_back(std::move(JTH), std::move(JT));
7586 JTCluster = CaseCluster::jumpTable(Clusters[First].Low, Clusters[Last].High,
7587 JTCases.size() - 1, Weight);
7591 void SelectionDAGBuilder::findJumpTables(CaseClusterVector &Clusters,
7592 const SwitchInst *SI,
7593 MachineBasicBlock *DefaultMBB) {
7595 // Clusters must be non-empty, sorted, and only contain Range clusters.
7596 assert(!Clusters.empty());
7597 for (CaseCluster &C : Clusters)
7598 assert(C.Kind == CC_Range);
7599 for (unsigned i = 1, e = Clusters.size(); i < e; ++i)
7600 assert(Clusters[i - 1].High->getValue().slt(Clusters[i].Low->getValue()));
7603 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
7604 if (!areJTsAllowed(TLI))
7607 const int64_t N = Clusters.size();
7608 const unsigned MinJumpTableSize = TLI.getMinimumJumpTableEntries();
7610 // TotalCases[i]: Total nbr of cases in Clusters[0..i].
7611 SmallVector<unsigned, 8> TotalCases(N);
7613 for (unsigned i = 0; i < N; ++i) {
7614 APInt Hi = Clusters[i].High->getValue();
7615 APInt Lo = Clusters[i].Low->getValue();
7616 TotalCases[i] = (Hi - Lo).getLimitedValue() + 1;
7618 TotalCases[i] += TotalCases[i - 1];
7621 if (N >= MinJumpTableSize && isDense(Clusters, &TotalCases[0], 0, N - 1)) {
7622 // Cheap case: the whole range might be suitable for jump table.
7623 CaseCluster JTCluster;
7624 if (buildJumpTable(Clusters, 0, N - 1, SI, DefaultMBB, JTCluster)) {
7625 Clusters[0] = JTCluster;
7631 // The algorithm below is not suitable for -O0.
7632 if (TM.getOptLevel() == CodeGenOpt::None)
7635 // Split Clusters into minimum number of dense partitions. The algorithm uses
7636 // the same idea as Kannan & Proebsting "Correction to 'Producing Good Code
7637 // for the Case Statement'" (1994), but builds the MinPartitions array in
7638 // reverse order to make it easier to reconstruct the partitions in ascending
7639 // order. In the choice between two optimal partitionings, it picks the one
7640 // which yields more jump tables.
7642 // MinPartitions[i] is the minimum nbr of partitions of Clusters[i..N-1].
7643 SmallVector<unsigned, 8> MinPartitions(N);
7644 // LastElement[i] is the last element of the partition starting at i.
7645 SmallVector<unsigned, 8> LastElement(N);
7646 // NumTables[i]: nbr of >= MinJumpTableSize partitions from Clusters[i..N-1].
7647 SmallVector<unsigned, 8> NumTables(N);
7649 // Base case: There is only one way to partition Clusters[N-1].
7650 MinPartitions[N - 1] = 1;
7651 LastElement[N - 1] = N - 1;
7652 assert(MinJumpTableSize > 1);
7653 NumTables[N - 1] = 0;
7655 // Note: loop indexes are signed to avoid underflow.
7656 for (int64_t i = N - 2; i >= 0; i--) {
7657 // Find optimal partitioning of Clusters[i..N-1].
7658 // Baseline: Put Clusters[i] into a partition on its own.
7659 MinPartitions[i] = MinPartitions[i + 1] + 1;
7661 NumTables[i] = NumTables[i + 1];
7663 // Search for a solution that results in fewer partitions.
7664 for (int64_t j = N - 1; j > i; j--) {
7665 // Try building a partition from Clusters[i..j].
7666 if (isDense(Clusters, &TotalCases[0], i, j)) {
7667 unsigned NumPartitions = 1 + (j == N - 1 ? 0 : MinPartitions[j + 1]);
7668 bool IsTable = j - i + 1 >= MinJumpTableSize;
7669 unsigned Tables = IsTable + (j == N - 1 ? 0 : NumTables[j + 1]);
7671 // If this j leads to fewer partitions, or same number of partitions
7672 // with more lookup tables, it is a better partitioning.
7673 if (NumPartitions < MinPartitions[i] ||
7674 (NumPartitions == MinPartitions[i] && Tables > NumTables[i])) {
7675 MinPartitions[i] = NumPartitions;
7677 NumTables[i] = Tables;
7683 // Iterate over the partitions, replacing some with jump tables in-place.
7684 unsigned DstIndex = 0;
7685 for (unsigned First = 0, Last; First < N; First = Last + 1) {
7686 Last = LastElement[First];
7687 assert(Last >= First);
7688 assert(DstIndex <= First);
7689 unsigned NumClusters = Last - First + 1;
7691 CaseCluster JTCluster;
7692 if (NumClusters >= MinJumpTableSize &&
7693 buildJumpTable(Clusters, First, Last, SI, DefaultMBB, JTCluster)) {
7694 Clusters[DstIndex++] = JTCluster;
7696 for (unsigned I = First; I <= Last; ++I)
7697 std::memmove(&Clusters[DstIndex++], &Clusters[I], sizeof(Clusters[I]));
7700 Clusters.resize(DstIndex);
7703 bool SelectionDAGBuilder::rangeFitsInWord(const APInt &Low, const APInt &High) {
7704 // FIXME: Using the pointer type doesn't seem ideal.
7705 uint64_t BW = DAG.getDataLayout().getPointerSizeInBits();
7706 uint64_t Range = (High - Low).getLimitedValue(UINT64_MAX - 1) + 1;
7710 bool SelectionDAGBuilder::isSuitableForBitTests(unsigned NumDests,
7713 const APInt &High) {
7714 // FIXME: I don't think NumCmps is the correct metric: a single case and a
7715 // range of cases both require only one branch to lower. Just looking at the
7716 // number of clusters and destinations should be enough to decide whether to
7719 // To lower a range with bit tests, the range must fit the bitwidth of a
7721 if (!rangeFitsInWord(Low, High))
7724 // Decide whether it's profitable to lower this range with bit tests. Each
7725 // destination requires a bit test and branch, and there is an overall range
7726 // check branch. For a small number of clusters, separate comparisons might be
7727 // cheaper, and for many destinations, splitting the range might be better.
7728 return (NumDests == 1 && NumCmps >= 3) ||
7729 (NumDests == 2 && NumCmps >= 5) ||
7730 (NumDests == 3 && NumCmps >= 6);
7733 bool SelectionDAGBuilder::buildBitTests(CaseClusterVector &Clusters,
7734 unsigned First, unsigned Last,
7735 const SwitchInst *SI,
7736 CaseCluster &BTCluster) {
7737 assert(First <= Last);
7741 BitVector Dests(FuncInfo.MF->getNumBlockIDs());
7742 unsigned NumCmps = 0;
7743 for (int64_t I = First; I <= Last; ++I) {
7744 assert(Clusters[I].Kind == CC_Range);
7745 Dests.set(Clusters[I].MBB->getNumber());
7746 NumCmps += (Clusters[I].Low == Clusters[I].High) ? 1 : 2;
7748 unsigned NumDests = Dests.count();
7750 APInt Low = Clusters[First].Low->getValue();
7751 APInt High = Clusters[Last].High->getValue();
7752 assert(Low.slt(High));
7754 if (!isSuitableForBitTests(NumDests, NumCmps, Low, High))
7760 const int BitWidth = DAG.getTargetLoweringInfo()
7761 .getPointerTy(DAG.getDataLayout())
7763 assert(rangeFitsInWord(Low, High) && "Case range must fit in bit mask!");
7765 // Check if the clusters cover a contiguous range such that no value in the
7766 // range will jump to the default statement.
7767 bool ContiguousRange = true;
7768 for (int64_t I = First + 1; I <= Last; ++I) {
7769 if (Clusters[I].Low->getValue() != Clusters[I - 1].High->getValue() + 1) {
7770 ContiguousRange = false;
7775 if (Low.isStrictlyPositive() && High.slt(BitWidth)) {
7776 // Optimize the case where all the case values fit in a word without having
7777 // to subtract minValue. In this case, we can optimize away the subtraction.
7778 LowBound = APInt::getNullValue(Low.getBitWidth());
7780 ContiguousRange = false;
7783 CmpRange = High - Low;
7787 uint32_t TotalWeight = 0;
7788 for (unsigned i = First; i <= Last; ++i) {
7789 // Find the CaseBits for this destination.
7791 for (j = 0; j < CBV.size(); ++j)
7792 if (CBV[j].BB == Clusters[i].MBB)
7794 if (j == CBV.size())
7795 CBV.push_back(CaseBits(0, Clusters[i].MBB, 0, 0));
7796 CaseBits *CB = &CBV[j];
7798 // Update Mask, Bits and ExtraWeight.
7799 uint64_t Lo = (Clusters[i].Low->getValue() - LowBound).getZExtValue();
7800 uint64_t Hi = (Clusters[i].High->getValue() - LowBound).getZExtValue();
7801 assert(Hi >= Lo && Hi < 64 && "Invalid bit case!");
7802 CB->Mask |= (-1ULL >> (63 - (Hi - Lo))) << Lo;
7803 CB->Bits += Hi - Lo + 1;
7804 CB->ExtraWeight += Clusters[i].Weight;
7805 TotalWeight += Clusters[i].Weight;
7806 assert(TotalWeight >= Clusters[i].Weight && "Weight overflow!");
7810 std::sort(CBV.begin(), CBV.end(), [](const CaseBits &a, const CaseBits &b) {
7811 // Sort by weight first, number of bits second.
7812 if (a.ExtraWeight != b.ExtraWeight)
7813 return a.ExtraWeight > b.ExtraWeight;
7814 return a.Bits > b.Bits;
7817 for (auto &CB : CBV) {
7818 MachineBasicBlock *BitTestBB =
7819 FuncInfo.MF->CreateMachineBasicBlock(SI->getParent());
7820 BTI.push_back(BitTestCase(CB.Mask, BitTestBB, CB.BB, CB.ExtraWeight));
7822 BitTestCases.emplace_back(std::move(LowBound), std::move(CmpRange),
7823 SI->getCondition(), -1U, MVT::Other, false,
7824 ContiguousRange, nullptr, nullptr, std::move(BTI),
7827 BTCluster = CaseCluster::bitTests(Clusters[First].Low, Clusters[Last].High,
7828 BitTestCases.size() - 1, TotalWeight);
7832 void SelectionDAGBuilder::findBitTestClusters(CaseClusterVector &Clusters,
7833 const SwitchInst *SI) {
7834 // Partition Clusters into as few subsets as possible, where each subset has a
7835 // range that fits in a machine word and has <= 3 unique destinations.
7838 // Clusters must be sorted and contain Range or JumpTable clusters.
7839 assert(!Clusters.empty());
7840 assert(Clusters[0].Kind == CC_Range || Clusters[0].Kind == CC_JumpTable);
7841 for (const CaseCluster &C : Clusters)
7842 assert(C.Kind == CC_Range || C.Kind == CC_JumpTable);
7843 for (unsigned i = 1; i < Clusters.size(); ++i)
7844 assert(Clusters[i-1].High->getValue().slt(Clusters[i].Low->getValue()));
7847 // The algorithm below is not suitable for -O0.
7848 if (TM.getOptLevel() == CodeGenOpt::None)
7851 // If target does not have legal shift left, do not emit bit tests at all.
7852 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
7853 EVT PTy = TLI.getPointerTy(DAG.getDataLayout());
7854 if (!TLI.isOperationLegal(ISD::SHL, PTy))
7857 int BitWidth = PTy.getSizeInBits();
7858 const int64_t N = Clusters.size();
7860 // MinPartitions[i] is the minimum nbr of partitions of Clusters[i..N-1].
7861 SmallVector<unsigned, 8> MinPartitions(N);
7862 // LastElement[i] is the last element of the partition starting at i.
7863 SmallVector<unsigned, 8> LastElement(N);
7865 // FIXME: This might not be the best algorithm for finding bit test clusters.
7867 // Base case: There is only one way to partition Clusters[N-1].
7868 MinPartitions[N - 1] = 1;
7869 LastElement[N - 1] = N - 1;
7871 // Note: loop indexes are signed to avoid underflow.
7872 for (int64_t i = N - 2; i >= 0; --i) {
7873 // Find optimal partitioning of Clusters[i..N-1].
7874 // Baseline: Put Clusters[i] into a partition on its own.
7875 MinPartitions[i] = MinPartitions[i + 1] + 1;
7878 // Search for a solution that results in fewer partitions.
7879 // Note: the search is limited by BitWidth, reducing time complexity.
7880 for (int64_t j = std::min(N - 1, i + BitWidth - 1); j > i; --j) {
7881 // Try building a partition from Clusters[i..j].
7884 if (!rangeFitsInWord(Clusters[i].Low->getValue(),
7885 Clusters[j].High->getValue()))
7888 // Check nbr of destinations and cluster types.
7889 // FIXME: This works, but doesn't seem very efficient.
7890 bool RangesOnly = true;
7891 BitVector Dests(FuncInfo.MF->getNumBlockIDs());
7892 for (int64_t k = i; k <= j; k++) {
7893 if (Clusters[k].Kind != CC_Range) {
7897 Dests.set(Clusters[k].MBB->getNumber());
7899 if (!RangesOnly || Dests.count() > 3)
7902 // Check if it's a better partition.
7903 unsigned NumPartitions = 1 + (j == N - 1 ? 0 : MinPartitions[j + 1]);
7904 if (NumPartitions < MinPartitions[i]) {
7905 // Found a better partition.
7906 MinPartitions[i] = NumPartitions;
7912 // Iterate over the partitions, replacing with bit-test clusters in-place.
7913 unsigned DstIndex = 0;
7914 for (unsigned First = 0, Last; First < N; First = Last + 1) {
7915 Last = LastElement[First];
7916 assert(First <= Last);
7917 assert(DstIndex <= First);
7919 CaseCluster BitTestCluster;
7920 if (buildBitTests(Clusters, First, Last, SI, BitTestCluster)) {
7921 Clusters[DstIndex++] = BitTestCluster;
7923 size_t NumClusters = Last - First + 1;
7924 std::memmove(&Clusters[DstIndex], &Clusters[First],
7925 sizeof(Clusters[0]) * NumClusters);
7926 DstIndex += NumClusters;
7929 Clusters.resize(DstIndex);
7932 void SelectionDAGBuilder::lowerWorkItem(SwitchWorkListItem W, Value *Cond,
7933 MachineBasicBlock *SwitchMBB,
7934 MachineBasicBlock *DefaultMBB) {
7935 MachineFunction *CurMF = FuncInfo.MF;
7936 MachineBasicBlock *NextMBB = nullptr;
7937 MachineFunction::iterator BBI = W.MBB;
7938 if (++BBI != FuncInfo.MF->end())
7941 unsigned Size = W.LastCluster - W.FirstCluster + 1;
7943 BranchProbabilityInfo *BPI = FuncInfo.BPI;
7945 if (Size == 2 && W.MBB == SwitchMBB) {
7946 // If any two of the cases has the same destination, and if one value
7947 // is the same as the other, but has one bit unset that the other has set,
7948 // use bit manipulation to do two compares at once. For example:
7949 // "if (X == 6 || X == 4)" -> "if ((X|2) == 6)"
7950 // TODO: This could be extended to merge any 2 cases in switches with 3
7952 // TODO: Handle cases where W.CaseBB != SwitchBB.
7953 CaseCluster &Small = *W.FirstCluster;
7954 CaseCluster &Big = *W.LastCluster;
7956 if (Small.Low == Small.High && Big.Low == Big.High &&
7957 Small.MBB == Big.MBB) {
7958 const APInt &SmallValue = Small.Low->getValue();
7959 const APInt &BigValue = Big.Low->getValue();
7961 // Check that there is only one bit different.
7962 APInt CommonBit = BigValue ^ SmallValue;
7963 if (CommonBit.isPowerOf2()) {
7964 SDValue CondLHS = getValue(Cond);
7965 EVT VT = CondLHS.getValueType();
7966 SDLoc DL = getCurSDLoc();
7968 SDValue Or = DAG.getNode(ISD::OR, DL, VT, CondLHS,
7969 DAG.getConstant(CommonBit, DL, VT));
7970 SDValue Cond = DAG.getSetCC(
7971 DL, MVT::i1, Or, DAG.getConstant(BigValue | SmallValue, DL, VT),
7974 // Update successor info.
7975 // Both Small and Big will jump to Small.BB, so we sum up the weights.
7976 addSuccessorWithWeight(SwitchMBB, Small.MBB, Small.Weight + Big.Weight);
7977 addSuccessorWithWeight(
7978 SwitchMBB, DefaultMBB,
7979 // The default destination is the first successor in IR.
7980 BPI ? BPI->getEdgeWeight(SwitchMBB->getBasicBlock(), (unsigned)0)
7983 // Insert the true branch.
7985 DAG.getNode(ISD::BRCOND, DL, MVT::Other, getControlRoot(), Cond,
7986 DAG.getBasicBlock(Small.MBB));
7987 // Insert the false branch.
7988 BrCond = DAG.getNode(ISD::BR, DL, MVT::Other, BrCond,
7989 DAG.getBasicBlock(DefaultMBB));
7991 DAG.setRoot(BrCond);
7997 if (TM.getOptLevel() != CodeGenOpt::None) {
7998 // Order cases by weight so the most likely case will be checked first.
7999 std::sort(W.FirstCluster, W.LastCluster + 1,
8000 [](const CaseCluster &a, const CaseCluster &b) {
8001 return a.Weight > b.Weight;
8004 // Rearrange the case blocks so that the last one falls through if possible
8005 // without without changing the order of weights.
8006 for (CaseClusterIt I = W.LastCluster; I > W.FirstCluster; ) {
8008 if (I->Weight > W.LastCluster->Weight)
8010 if (I->Kind == CC_Range && I->MBB == NextMBB) {
8011 std::swap(*I, *W.LastCluster);
8017 // Compute total weight.
8018 uint32_t UnhandledWeights = 0;
8019 for (CaseClusterIt I = W.FirstCluster; I <= W.LastCluster; ++I) {
8020 UnhandledWeights += I->Weight;
8021 assert(UnhandledWeights >= I->Weight && "Weight overflow!");
8024 MachineBasicBlock *CurMBB = W.MBB;
8025 for (CaseClusterIt I = W.FirstCluster, E = W.LastCluster; I <= E; ++I) {
8026 MachineBasicBlock *Fallthrough;
8027 if (I == W.LastCluster) {
8028 // For the last cluster, fall through to the default destination.
8029 Fallthrough = DefaultMBB;
8031 Fallthrough = CurMF->CreateMachineBasicBlock(CurMBB->getBasicBlock());
8032 CurMF->insert(BBI, Fallthrough);
8033 // Put Cond in a virtual register to make it available from the new blocks.
8034 ExportFromCurrentBlock(Cond);
8038 case CC_JumpTable: {
8039 // FIXME: Optimize away range check based on pivot comparisons.
8040 JumpTableHeader *JTH = &JTCases[I->JTCasesIndex].first;
8041 JumpTable *JT = &JTCases[I->JTCasesIndex].second;
8043 // The jump block hasn't been inserted yet; insert it here.
8044 MachineBasicBlock *JumpMBB = JT->MBB;
8045 CurMF->insert(BBI, JumpMBB);
8047 // Collect the sum of weights of outgoing edges from JumpMBB, which will
8048 // be the edge weight on CurMBB->JumpMBB.
8049 uint32_t JumpWeight = 0;
8050 for (auto Succ : JumpMBB->successors())
8051 JumpWeight += getEdgeWeight(JumpMBB, Succ);
8052 uint32_t FallthruWeight = getEdgeWeight(CurMBB, Fallthrough);
8054 addSuccessorWithWeight(CurMBB, Fallthrough, FallthruWeight);
8055 addSuccessorWithWeight(CurMBB, JumpMBB, JumpWeight);
8057 // The jump table header will be inserted in our current block, do the
8058 // range check, and fall through to our fallthrough block.
8059 JTH->HeaderBB = CurMBB;
8060 JT->Default = Fallthrough; // FIXME: Move Default to JumpTableHeader.
8062 // If we're in the right place, emit the jump table header right now.
8063 if (CurMBB == SwitchMBB) {
8064 visitJumpTableHeader(*JT, *JTH, SwitchMBB);
8065 JTH->Emitted = true;
8070 // FIXME: Optimize away range check based on pivot comparisons.
8071 BitTestBlock *BTB = &BitTestCases[I->BTCasesIndex];
8073 // The bit test blocks haven't been inserted yet; insert them here.
8074 for (BitTestCase &BTC : BTB->Cases)
8075 CurMF->insert(BBI, BTC.ThisBB);
8077 // Fill in fields of the BitTestBlock.
8078 BTB->Parent = CurMBB;
8079 BTB->Default = Fallthrough;
8081 // If we're in the right place, emit the bit test header header right now.
8082 if (CurMBB ==SwitchMBB) {
8083 visitBitTestHeader(*BTB, SwitchMBB);
8084 BTB->Emitted = true;
8089 const Value *RHS, *LHS, *MHS;
8091 if (I->Low == I->High) {
8092 // Check Cond == I->Low.
8098 // Check I->Low <= Cond <= I->High.
8105 // The false weight is the sum of all unhandled cases.
8106 UnhandledWeights -= I->Weight;
8107 CaseBlock CB(CC, LHS, RHS, MHS, I->MBB, Fallthrough, CurMBB, I->Weight,
8110 if (CurMBB == SwitchMBB)
8111 visitSwitchCase(CB, SwitchMBB);
8113 SwitchCases.push_back(CB);
8118 CurMBB = Fallthrough;
8122 unsigned SelectionDAGBuilder::caseClusterRank(const CaseCluster &CC,
8123 CaseClusterIt First,
8124 CaseClusterIt Last) {
8125 return std::count_if(First, Last + 1, [&](const CaseCluster &X) {
8126 if (X.Weight != CC.Weight)
8127 return X.Weight > CC.Weight;
8129 // Ties are broken by comparing the case value.
8130 return X.Low->getValue().slt(CC.Low->getValue());
8134 void SelectionDAGBuilder::splitWorkItem(SwitchWorkList &WorkList,
8135 const SwitchWorkListItem &W,
8137 MachineBasicBlock *SwitchMBB) {
8138 assert(W.FirstCluster->Low->getValue().slt(W.LastCluster->Low->getValue()) &&
8139 "Clusters not sorted?");
8141 assert(W.LastCluster - W.FirstCluster + 1 >= 2 && "Too small to split!");
8143 // Balance the tree based on branch weights to create a near-optimal (in terms
8144 // of search time given key frequency) binary search tree. See e.g. Kurt
8145 // Mehlhorn "Nearly Optimal Binary Search Trees" (1975).
8146 CaseClusterIt LastLeft = W.FirstCluster;
8147 CaseClusterIt FirstRight = W.LastCluster;
8148 uint32_t LeftWeight = LastLeft->Weight;
8149 uint32_t RightWeight = FirstRight->Weight;
8151 // Move LastLeft and FirstRight towards each other from opposite directions to
8152 // find a partitioning of the clusters which balances the weight on both
8153 // sides. If LeftWeight and RightWeight are equal, alternate which side is
8154 // taken to ensure 0-weight nodes are distributed evenly.
8156 while (LastLeft + 1 < FirstRight) {
8157 if (LeftWeight < RightWeight || (LeftWeight == RightWeight && (I & 1)))
8158 LeftWeight += (++LastLeft)->Weight;
8160 RightWeight += (--FirstRight)->Weight;
8165 // Our binary search tree differs from a typical BST in that ours can have up
8166 // to three values in each leaf. The pivot selection above doesn't take that
8167 // into account, which means the tree might require more nodes and be less
8168 // efficient. We compensate for this here.
8170 unsigned NumLeft = LastLeft - W.FirstCluster + 1;
8171 unsigned NumRight = W.LastCluster - FirstRight + 1;
8173 if (std::min(NumLeft, NumRight) < 3 && std::max(NumLeft, NumRight) > 3) {
8174 // If one side has less than 3 clusters, and the other has more than 3,
8175 // consider taking a cluster from the other side.
8177 if (NumLeft < NumRight) {
8178 // Consider moving the first cluster on the right to the left side.
8179 CaseCluster &CC = *FirstRight;
8180 unsigned RightSideRank = caseClusterRank(CC, FirstRight, W.LastCluster);
8181 unsigned LeftSideRank = caseClusterRank(CC, W.FirstCluster, LastLeft);
8182 if (LeftSideRank <= RightSideRank) {
8183 // Moving the cluster to the left does not demote it.
8189 assert(NumRight < NumLeft);
8190 // Consider moving the last element on the left to the right side.
8191 CaseCluster &CC = *LastLeft;
8192 unsigned LeftSideRank = caseClusterRank(CC, W.FirstCluster, LastLeft);
8193 unsigned RightSideRank = caseClusterRank(CC, FirstRight, W.LastCluster);
8194 if (RightSideRank <= LeftSideRank) {
8195 // Moving the cluster to the right does not demot it.
8205 assert(LastLeft + 1 == FirstRight);
8206 assert(LastLeft >= W.FirstCluster);
8207 assert(FirstRight <= W.LastCluster);
8209 // Use the first element on the right as pivot since we will make less-than
8210 // comparisons against it.
8211 CaseClusterIt PivotCluster = FirstRight;
8212 assert(PivotCluster > W.FirstCluster);
8213 assert(PivotCluster <= W.LastCluster);
8215 CaseClusterIt FirstLeft = W.FirstCluster;
8216 CaseClusterIt LastRight = W.LastCluster;
8218 const ConstantInt *Pivot = PivotCluster->Low;
8220 // New blocks will be inserted immediately after the current one.
8221 MachineFunction::iterator BBI = W.MBB;
8224 // We will branch to the LHS if Value < Pivot. If LHS is a single cluster,
8225 // we can branch to its destination directly if it's squeezed exactly in
8226 // between the known lower bound and Pivot - 1.
8227 MachineBasicBlock *LeftMBB;
8228 if (FirstLeft == LastLeft && FirstLeft->Kind == CC_Range &&
8229 FirstLeft->Low == W.GE &&
8230 (FirstLeft->High->getValue() + 1LL) == Pivot->getValue()) {
8231 LeftMBB = FirstLeft->MBB;
8233 LeftMBB = FuncInfo.MF->CreateMachineBasicBlock(W.MBB->getBasicBlock());
8234 FuncInfo.MF->insert(BBI, LeftMBB);
8235 WorkList.push_back({LeftMBB, FirstLeft, LastLeft, W.GE, Pivot});
8236 // Put Cond in a virtual register to make it available from the new blocks.
8237 ExportFromCurrentBlock(Cond);
8240 // Similarly, we will branch to the RHS if Value >= Pivot. If RHS is a
8241 // single cluster, RHS.Low == Pivot, and we can branch to its destination
8242 // directly if RHS.High equals the current upper bound.
8243 MachineBasicBlock *RightMBB;
8244 if (FirstRight == LastRight && FirstRight->Kind == CC_Range &&
8245 W.LT && (FirstRight->High->getValue() + 1ULL) == W.LT->getValue()) {
8246 RightMBB = FirstRight->MBB;
8248 RightMBB = FuncInfo.MF->CreateMachineBasicBlock(W.MBB->getBasicBlock());
8249 FuncInfo.MF->insert(BBI, RightMBB);
8250 WorkList.push_back({RightMBB, FirstRight, LastRight, Pivot, W.LT});
8251 // Put Cond in a virtual register to make it available from the new blocks.
8252 ExportFromCurrentBlock(Cond);
8255 // Create the CaseBlock record that will be used to lower the branch.
8256 CaseBlock CB(ISD::SETLT, Cond, Pivot, nullptr, LeftMBB, RightMBB, W.MBB,
8257 LeftWeight, RightWeight);
8259 if (W.MBB == SwitchMBB)
8260 visitSwitchCase(CB, SwitchMBB);
8262 SwitchCases.push_back(CB);
8265 void SelectionDAGBuilder::visitSwitch(const SwitchInst &SI) {
8266 // Extract cases from the switch.
8267 BranchProbabilityInfo *BPI = FuncInfo.BPI;
8268 CaseClusterVector Clusters;
8269 Clusters.reserve(SI.getNumCases());
8270 for (auto I : SI.cases()) {
8271 MachineBasicBlock *Succ = FuncInfo.MBBMap[I.getCaseSuccessor()];
8272 const ConstantInt *CaseVal = I.getCaseValue();
8274 BPI ? BPI->getEdgeWeight(SI.getParent(), I.getSuccessorIndex()) : 0;
8275 Clusters.push_back(CaseCluster::range(CaseVal, CaseVal, Succ, Weight));
8278 MachineBasicBlock *DefaultMBB = FuncInfo.MBBMap[SI.getDefaultDest()];
8280 // Cluster adjacent cases with the same destination. We do this at all
8281 // optimization levels because it's cheap to do and will make codegen faster
8282 // if there are many clusters.
8283 sortAndRangeify(Clusters);
8285 if (TM.getOptLevel() != CodeGenOpt::None) {
8286 // Replace an unreachable default with the most popular destination.
8287 // FIXME: Exploit unreachable default more aggressively.
8288 bool UnreachableDefault =
8289 isa<UnreachableInst>(SI.getDefaultDest()->getFirstNonPHIOrDbg());
8290 if (UnreachableDefault && !Clusters.empty()) {
8291 DenseMap<const BasicBlock *, unsigned> Popularity;
8292 unsigned MaxPop = 0;
8293 const BasicBlock *MaxBB = nullptr;
8294 for (auto I : SI.cases()) {
8295 const BasicBlock *BB = I.getCaseSuccessor();
8296 if (++Popularity[BB] > MaxPop) {
8297 MaxPop = Popularity[BB];
8302 assert(MaxPop > 0 && MaxBB);
8303 DefaultMBB = FuncInfo.MBBMap[MaxBB];
8305 // Remove cases that were pointing to the destination that is now the
8307 CaseClusterVector New;
8308 New.reserve(Clusters.size());
8309 for (CaseCluster &CC : Clusters) {
8310 if (CC.MBB != DefaultMBB)
8313 Clusters = std::move(New);
8317 // If there is only the default destination, jump there directly.
8318 MachineBasicBlock *SwitchMBB = FuncInfo.MBB;
8319 if (Clusters.empty()) {
8320 SwitchMBB->addSuccessor(DefaultMBB);
8321 if (DefaultMBB != NextBlock(SwitchMBB)) {
8322 DAG.setRoot(DAG.getNode(ISD::BR, getCurSDLoc(), MVT::Other,
8323 getControlRoot(), DAG.getBasicBlock(DefaultMBB)));
8328 findJumpTables(Clusters, &SI, DefaultMBB);
8329 findBitTestClusters(Clusters, &SI);
8332 dbgs() << "Case clusters: ";
8333 for (const CaseCluster &C : Clusters) {
8334 if (C.Kind == CC_JumpTable) dbgs() << "JT:";
8335 if (C.Kind == CC_BitTests) dbgs() << "BT:";
8337 C.Low->getValue().print(dbgs(), true);
8338 if (C.Low != C.High) {
8340 C.High->getValue().print(dbgs(), true);
8347 assert(!Clusters.empty());
8348 SwitchWorkList WorkList;
8349 CaseClusterIt First = Clusters.begin();
8350 CaseClusterIt Last = Clusters.end() - 1;
8351 WorkList.push_back({SwitchMBB, First, Last, nullptr, nullptr});
8353 while (!WorkList.empty()) {
8354 SwitchWorkListItem W = WorkList.back();
8355 WorkList.pop_back();
8356 unsigned NumClusters = W.LastCluster - W.FirstCluster + 1;
8358 if (NumClusters > 3 && TM.getOptLevel() != CodeGenOpt::None) {
8359 // For optimized builds, lower large range as a balanced binary tree.
8360 splitWorkItem(WorkList, W, SI.getCondition(), SwitchMBB);
8364 lowerWorkItem(W, SI.getCondition(), SwitchMBB, DefaultMBB);