1 //===-- SelectionDAGBuilder.cpp - Selection-DAG building ------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements routines for translating from LLVM IR into SelectionDAG IR.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "isel"
15 #include "SDNodeDbgValue.h"
16 #include "SelectionDAGBuilder.h"
17 #include "llvm/ADT/BitVector.h"
18 #include "llvm/ADT/PostOrderIterator.h"
19 #include "llvm/ADT/SmallSet.h"
20 #include "llvm/Analysis/AliasAnalysis.h"
21 #include "llvm/Analysis/ConstantFolding.h"
22 #include "llvm/Constants.h"
23 #include "llvm/CallingConv.h"
24 #include "llvm/DebugInfo.h"
25 #include "llvm/DerivedTypes.h"
26 #include "llvm/Function.h"
27 #include "llvm/GlobalVariable.h"
28 #include "llvm/InlineAsm.h"
29 #include "llvm/Instructions.h"
30 #include "llvm/Intrinsics.h"
31 #include "llvm/IntrinsicInst.h"
32 #include "llvm/LLVMContext.h"
33 #include "llvm/Module.h"
34 #include "llvm/CodeGen/Analysis.h"
35 #include "llvm/CodeGen/FastISel.h"
36 #include "llvm/CodeGen/FunctionLoweringInfo.h"
37 #include "llvm/CodeGen/GCStrategy.h"
38 #include "llvm/CodeGen/GCMetadata.h"
39 #include "llvm/CodeGen/MachineFunction.h"
40 #include "llvm/CodeGen/MachineFrameInfo.h"
41 #include "llvm/CodeGen/MachineInstrBuilder.h"
42 #include "llvm/CodeGen/MachineJumpTableInfo.h"
43 #include "llvm/CodeGen/MachineModuleInfo.h"
44 #include "llvm/CodeGen/MachineRegisterInfo.h"
45 #include "llvm/CodeGen/SelectionDAG.h"
46 #include "llvm/Target/TargetData.h"
47 #include "llvm/Target/TargetFrameLowering.h"
48 #include "llvm/Target/TargetInstrInfo.h"
49 #include "llvm/Target/TargetIntrinsicInfo.h"
50 #include "llvm/Target/TargetLibraryInfo.h"
51 #include "llvm/Target/TargetLowering.h"
52 #include "llvm/Target/TargetOptions.h"
53 #include "llvm/Support/CommandLine.h"
54 #include "llvm/Support/IntegersSubsetMapping.h"
55 #include "llvm/Support/Debug.h"
56 #include "llvm/Support/ErrorHandling.h"
57 #include "llvm/Support/MathExtras.h"
58 #include "llvm/Support/raw_ostream.h"
62 /// LimitFloatPrecision - Generate low-precision inline sequences for
63 /// some float libcalls (6, 8 or 12 bits).
64 static unsigned LimitFloatPrecision;
66 static cl::opt<unsigned, true>
67 LimitFPPrecision("limit-float-precision",
68 cl::desc("Generate low-precision inline sequences "
69 "for some float libcalls"),
70 cl::location(LimitFloatPrecision),
73 // Limit the width of DAG chains. This is important in general to prevent
74 // prevent DAG-based analysis from blowing up. For example, alias analysis and
75 // load clustering may not complete in reasonable time. It is difficult to
76 // recognize and avoid this situation within each individual analysis, and
77 // future analyses are likely to have the same behavior. Limiting DAG width is
78 // the safe approach, and will be especially important with global DAGs.
80 // MaxParallelChains default is arbitrarily high to avoid affecting
81 // optimization, but could be lowered to improve compile time. Any ld-ld-st-st
82 // sequence over this should have been converted to llvm.memcpy by the
83 // frontend. It easy to induce this behavior with .ll code such as:
84 // %buffer = alloca [4096 x i8]
85 // %data = load [4096 x i8]* %argPtr
86 // store [4096 x i8] %data, [4096 x i8]* %buffer
87 static const unsigned MaxParallelChains = 64;
89 static SDValue getCopyFromPartsVector(SelectionDAG &DAG, DebugLoc DL,
90 const SDValue *Parts, unsigned NumParts,
91 EVT PartVT, EVT ValueVT);
93 /// getCopyFromParts - Create a value that contains the specified legal parts
94 /// combined into the value they represent. If the parts combine to a type
95 /// larger then ValueVT then AssertOp can be used to specify whether the extra
96 /// bits are known to be zero (ISD::AssertZext) or sign extended from ValueVT
97 /// (ISD::AssertSext).
98 static SDValue getCopyFromParts(SelectionDAG &DAG, DebugLoc DL,
100 unsigned NumParts, EVT PartVT, EVT ValueVT,
101 ISD::NodeType AssertOp = ISD::DELETED_NODE) {
102 if (ValueVT.isVector())
103 return getCopyFromPartsVector(DAG, DL, Parts, NumParts, PartVT, ValueVT);
105 assert(NumParts > 0 && "No parts to assemble!");
106 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
107 SDValue Val = Parts[0];
110 // Assemble the value from multiple parts.
111 if (ValueVT.isInteger()) {
112 unsigned PartBits = PartVT.getSizeInBits();
113 unsigned ValueBits = ValueVT.getSizeInBits();
115 // Assemble the power of 2 part.
116 unsigned RoundParts = NumParts & (NumParts - 1) ?
117 1 << Log2_32(NumParts) : NumParts;
118 unsigned RoundBits = PartBits * RoundParts;
119 EVT RoundVT = RoundBits == ValueBits ?
120 ValueVT : EVT::getIntegerVT(*DAG.getContext(), RoundBits);
123 EVT HalfVT = EVT::getIntegerVT(*DAG.getContext(), RoundBits/2);
125 if (RoundParts > 2) {
126 Lo = getCopyFromParts(DAG, DL, Parts, RoundParts / 2,
128 Hi = getCopyFromParts(DAG, DL, Parts + RoundParts / 2,
129 RoundParts / 2, PartVT, HalfVT);
131 Lo = DAG.getNode(ISD::BITCAST, DL, HalfVT, Parts[0]);
132 Hi = DAG.getNode(ISD::BITCAST, DL, HalfVT, Parts[1]);
135 if (TLI.isBigEndian())
138 Val = DAG.getNode(ISD::BUILD_PAIR, DL, RoundVT, Lo, Hi);
140 if (RoundParts < NumParts) {
141 // Assemble the trailing non-power-of-2 part.
142 unsigned OddParts = NumParts - RoundParts;
143 EVT OddVT = EVT::getIntegerVT(*DAG.getContext(), OddParts * PartBits);
144 Hi = getCopyFromParts(DAG, DL,
145 Parts + RoundParts, OddParts, PartVT, OddVT);
147 // Combine the round and odd parts.
149 if (TLI.isBigEndian())
151 EVT TotalVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
152 Hi = DAG.getNode(ISD::ANY_EXTEND, DL, TotalVT, Hi);
153 Hi = DAG.getNode(ISD::SHL, DL, TotalVT, Hi,
154 DAG.getConstant(Lo.getValueType().getSizeInBits(),
155 TLI.getPointerTy()));
156 Lo = DAG.getNode(ISD::ZERO_EXTEND, DL, TotalVT, Lo);
157 Val = DAG.getNode(ISD::OR, DL, TotalVT, Lo, Hi);
159 } else if (PartVT.isFloatingPoint()) {
160 // FP split into multiple FP parts (for ppcf128)
161 assert(ValueVT == EVT(MVT::ppcf128) && PartVT == EVT(MVT::f64) &&
164 Lo = DAG.getNode(ISD::BITCAST, DL, EVT(MVT::f64), Parts[0]);
165 Hi = DAG.getNode(ISD::BITCAST, DL, EVT(MVT::f64), Parts[1]);
166 if (TLI.isBigEndian())
168 Val = DAG.getNode(ISD::BUILD_PAIR, DL, ValueVT, Lo, Hi);
170 // FP split into integer parts (soft fp)
171 assert(ValueVT.isFloatingPoint() && PartVT.isInteger() &&
172 !PartVT.isVector() && "Unexpected split");
173 EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), ValueVT.getSizeInBits());
174 Val = getCopyFromParts(DAG, DL, Parts, NumParts, PartVT, IntVT);
178 // There is now one part, held in Val. Correct it to match ValueVT.
179 PartVT = Val.getValueType();
181 if (PartVT == ValueVT)
184 if (PartVT.isInteger() && ValueVT.isInteger()) {
185 if (ValueVT.bitsLT(PartVT)) {
186 // For a truncate, see if we have any information to
187 // indicate whether the truncated bits will always be
188 // zero or sign-extension.
189 if (AssertOp != ISD::DELETED_NODE)
190 Val = DAG.getNode(AssertOp, DL, PartVT, Val,
191 DAG.getValueType(ValueVT));
192 return DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val);
194 return DAG.getNode(ISD::ANY_EXTEND, DL, ValueVT, Val);
197 if (PartVT.isFloatingPoint() && ValueVT.isFloatingPoint()) {
198 // FP_ROUND's are always exact here.
199 if (ValueVT.bitsLT(Val.getValueType()))
200 return DAG.getNode(ISD::FP_ROUND, DL, ValueVT, Val,
201 DAG.getTargetConstant(1, TLI.getPointerTy()));
203 return DAG.getNode(ISD::FP_EXTEND, DL, ValueVT, Val);
206 if (PartVT.getSizeInBits() == ValueVT.getSizeInBits())
207 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val);
209 llvm_unreachable("Unknown mismatch!");
212 /// getCopyFromParts - Create a value that contains the specified legal parts
213 /// combined into the value they represent. If the parts combine to a type
214 /// larger then ValueVT then AssertOp can be used to specify whether the extra
215 /// bits are known to be zero (ISD::AssertZext) or sign extended from ValueVT
216 /// (ISD::AssertSext).
217 static SDValue getCopyFromPartsVector(SelectionDAG &DAG, DebugLoc DL,
218 const SDValue *Parts, unsigned NumParts,
219 EVT PartVT, EVT ValueVT) {
220 assert(ValueVT.isVector() && "Not a vector value");
221 assert(NumParts > 0 && "No parts to assemble!");
222 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
223 SDValue Val = Parts[0];
225 // Handle a multi-element vector.
227 EVT IntermediateVT, RegisterVT;
228 unsigned NumIntermediates;
230 TLI.getVectorTypeBreakdown(*DAG.getContext(), ValueVT, IntermediateVT,
231 NumIntermediates, RegisterVT);
232 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!");
233 NumParts = NumRegs; // Silence a compiler warning.
234 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!");
235 assert(RegisterVT == Parts[0].getValueType() &&
236 "Part type doesn't match part!");
238 // Assemble the parts into intermediate operands.
239 SmallVector<SDValue, 8> Ops(NumIntermediates);
240 if (NumIntermediates == NumParts) {
241 // If the register was not expanded, truncate or copy the value,
243 for (unsigned i = 0; i != NumParts; ++i)
244 Ops[i] = getCopyFromParts(DAG, DL, &Parts[i], 1,
245 PartVT, IntermediateVT);
246 } else if (NumParts > 0) {
247 // If the intermediate type was expanded, build the intermediate
248 // operands from the parts.
249 assert(NumParts % NumIntermediates == 0 &&
250 "Must expand into a divisible number of parts!");
251 unsigned Factor = NumParts / NumIntermediates;
252 for (unsigned i = 0; i != NumIntermediates; ++i)
253 Ops[i] = getCopyFromParts(DAG, DL, &Parts[i * Factor], Factor,
254 PartVT, IntermediateVT);
257 // Build a vector with BUILD_VECTOR or CONCAT_VECTORS from the
258 // intermediate operands.
259 Val = DAG.getNode(IntermediateVT.isVector() ?
260 ISD::CONCAT_VECTORS : ISD::BUILD_VECTOR, DL,
261 ValueVT, &Ops[0], NumIntermediates);
264 // There is now one part, held in Val. Correct it to match ValueVT.
265 PartVT = Val.getValueType();
267 if (PartVT == ValueVT)
270 if (PartVT.isVector()) {
271 // If the element type of the source/dest vectors are the same, but the
272 // parts vector has more elements than the value vector, then we have a
273 // vector widening case (e.g. <2 x float> -> <4 x float>). Extract the
275 if (PartVT.getVectorElementType() == ValueVT.getVectorElementType()) {
276 assert(PartVT.getVectorNumElements() > ValueVT.getVectorNumElements() &&
277 "Cannot narrow, it would be a lossy transformation");
278 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, ValueVT, Val,
279 DAG.getIntPtrConstant(0));
282 // Vector/Vector bitcast.
283 if (ValueVT.getSizeInBits() == PartVT.getSizeInBits())
284 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val);
286 assert(PartVT.getVectorNumElements() == ValueVT.getVectorNumElements() &&
287 "Cannot handle this kind of promotion");
288 // Promoted vector extract
289 bool Smaller = ValueVT.bitsLE(PartVT);
290 return DAG.getNode((Smaller ? ISD::TRUNCATE : ISD::ANY_EXTEND),
295 // Trivial bitcast if the types are the same size and the destination
296 // vector type is legal.
297 if (PartVT.getSizeInBits() == ValueVT.getSizeInBits() &&
298 TLI.isTypeLegal(ValueVT))
299 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val);
301 // Handle cases such as i8 -> <1 x i1>
302 assert(ValueVT.getVectorNumElements() == 1 &&
303 "Only trivial scalar-to-vector conversions should get here!");
305 if (ValueVT.getVectorNumElements() == 1 &&
306 ValueVT.getVectorElementType() != PartVT) {
307 bool Smaller = ValueVT.bitsLE(PartVT);
308 Val = DAG.getNode((Smaller ? ISD::TRUNCATE : ISD::ANY_EXTEND),
309 DL, ValueVT.getScalarType(), Val);
312 return DAG.getNode(ISD::BUILD_VECTOR, DL, ValueVT, Val);
318 static void getCopyToPartsVector(SelectionDAG &DAG, DebugLoc dl,
319 SDValue Val, SDValue *Parts, unsigned NumParts,
322 /// getCopyToParts - Create a series of nodes that contain the specified value
323 /// split into legal parts. If the parts contain more bits than Val, then, for
324 /// integers, ExtendKind can be used to specify how to generate the extra bits.
325 static void getCopyToParts(SelectionDAG &DAG, DebugLoc DL,
326 SDValue Val, SDValue *Parts, unsigned NumParts,
328 ISD::NodeType ExtendKind = ISD::ANY_EXTEND) {
329 EVT ValueVT = Val.getValueType();
331 // Handle the vector case separately.
332 if (ValueVT.isVector())
333 return getCopyToPartsVector(DAG, DL, Val, Parts, NumParts, PartVT);
335 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
336 unsigned PartBits = PartVT.getSizeInBits();
337 unsigned OrigNumParts = NumParts;
338 assert(TLI.isTypeLegal(PartVT) && "Copying to an illegal type!");
343 assert(!ValueVT.isVector() && "Vector case handled elsewhere");
344 if (PartVT == ValueVT) {
345 assert(NumParts == 1 && "No-op copy with multiple parts!");
350 if (NumParts * PartBits > ValueVT.getSizeInBits()) {
351 // If the parts cover more bits than the value has, promote the value.
352 if (PartVT.isFloatingPoint() && ValueVT.isFloatingPoint()) {
353 assert(NumParts == 1 && "Do not know what to promote to!");
354 Val = DAG.getNode(ISD::FP_EXTEND, DL, PartVT, Val);
356 assert((PartVT.isInteger() || PartVT == MVT::x86mmx) &&
357 ValueVT.isInteger() &&
358 "Unknown mismatch!");
359 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
360 Val = DAG.getNode(ExtendKind, DL, ValueVT, Val);
361 if (PartVT == MVT::x86mmx)
362 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
364 } else if (PartBits == ValueVT.getSizeInBits()) {
365 // Different types of the same size.
366 assert(NumParts == 1 && PartVT != ValueVT);
367 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
368 } else if (NumParts * PartBits < ValueVT.getSizeInBits()) {
369 // If the parts cover less bits than value has, truncate the value.
370 assert((PartVT.isInteger() || PartVT == MVT::x86mmx) &&
371 ValueVT.isInteger() &&
372 "Unknown mismatch!");
373 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
374 Val = DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val);
375 if (PartVT == MVT::x86mmx)
376 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
379 // The value may have changed - recompute ValueVT.
380 ValueVT = Val.getValueType();
381 assert(NumParts * PartBits == ValueVT.getSizeInBits() &&
382 "Failed to tile the value with PartVT!");
385 assert(PartVT == ValueVT && "Type conversion failed!");
390 // Expand the value into multiple parts.
391 if (NumParts & (NumParts - 1)) {
392 // The number of parts is not a power of 2. Split off and copy the tail.
393 assert(PartVT.isInteger() && ValueVT.isInteger() &&
394 "Do not know what to expand to!");
395 unsigned RoundParts = 1 << Log2_32(NumParts);
396 unsigned RoundBits = RoundParts * PartBits;
397 unsigned OddParts = NumParts - RoundParts;
398 SDValue OddVal = DAG.getNode(ISD::SRL, DL, ValueVT, Val,
399 DAG.getIntPtrConstant(RoundBits));
400 getCopyToParts(DAG, DL, OddVal, Parts + RoundParts, OddParts, PartVT);
402 if (TLI.isBigEndian())
403 // The odd parts were reversed by getCopyToParts - unreverse them.
404 std::reverse(Parts + RoundParts, Parts + NumParts);
406 NumParts = RoundParts;
407 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
408 Val = DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val);
411 // The number of parts is a power of 2. Repeatedly bisect the value using
413 Parts[0] = DAG.getNode(ISD::BITCAST, DL,
414 EVT::getIntegerVT(*DAG.getContext(),
415 ValueVT.getSizeInBits()),
418 for (unsigned StepSize = NumParts; StepSize > 1; StepSize /= 2) {
419 for (unsigned i = 0; i < NumParts; i += StepSize) {
420 unsigned ThisBits = StepSize * PartBits / 2;
421 EVT ThisVT = EVT::getIntegerVT(*DAG.getContext(), ThisBits);
422 SDValue &Part0 = Parts[i];
423 SDValue &Part1 = Parts[i+StepSize/2];
425 Part1 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL,
426 ThisVT, Part0, DAG.getIntPtrConstant(1));
427 Part0 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL,
428 ThisVT, Part0, DAG.getIntPtrConstant(0));
430 if (ThisBits == PartBits && ThisVT != PartVT) {
431 Part0 = DAG.getNode(ISD::BITCAST, DL, PartVT, Part0);
432 Part1 = DAG.getNode(ISD::BITCAST, DL, PartVT, Part1);
437 if (TLI.isBigEndian())
438 std::reverse(Parts, Parts + OrigNumParts);
442 /// getCopyToPartsVector - Create a series of nodes that contain the specified
443 /// value split into legal parts.
444 static void getCopyToPartsVector(SelectionDAG &DAG, DebugLoc DL,
445 SDValue Val, SDValue *Parts, unsigned NumParts,
447 EVT ValueVT = Val.getValueType();
448 assert(ValueVT.isVector() && "Not a vector");
449 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
452 if (PartVT == ValueVT) {
454 } else if (PartVT.getSizeInBits() == ValueVT.getSizeInBits()) {
455 // Bitconvert vector->vector case.
456 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
457 } else if (PartVT.isVector() &&
458 PartVT.getVectorElementType() == ValueVT.getVectorElementType() &&
459 PartVT.getVectorNumElements() > ValueVT.getVectorNumElements()) {
460 EVT ElementVT = PartVT.getVectorElementType();
461 // Vector widening case, e.g. <2 x float> -> <4 x float>. Shuffle in
463 SmallVector<SDValue, 16> Ops;
464 for (unsigned i = 0, e = ValueVT.getVectorNumElements(); i != e; ++i)
465 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL,
466 ElementVT, Val, DAG.getIntPtrConstant(i)));
468 for (unsigned i = ValueVT.getVectorNumElements(),
469 e = PartVT.getVectorNumElements(); i != e; ++i)
470 Ops.push_back(DAG.getUNDEF(ElementVT));
472 Val = DAG.getNode(ISD::BUILD_VECTOR, DL, PartVT, &Ops[0], Ops.size());
474 // FIXME: Use CONCAT for 2x -> 4x.
476 //SDValue UndefElts = DAG.getUNDEF(VectorTy);
477 //Val = DAG.getNode(ISD::CONCAT_VECTORS, DL, PartVT, Val, UndefElts);
478 } else if (PartVT.isVector() &&
479 PartVT.getVectorElementType().bitsGE(
480 ValueVT.getVectorElementType()) &&
481 PartVT.getVectorNumElements() == ValueVT.getVectorNumElements()) {
483 // Promoted vector extract
484 bool Smaller = PartVT.bitsLE(ValueVT);
485 Val = DAG.getNode((Smaller ? ISD::TRUNCATE : ISD::ANY_EXTEND),
488 // Vector -> scalar conversion.
489 assert(ValueVT.getVectorNumElements() == 1 &&
490 "Only trivial vector-to-scalar conversions should get here!");
491 Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL,
492 PartVT, Val, DAG.getIntPtrConstant(0));
494 bool Smaller = ValueVT.bitsLE(PartVT);
495 Val = DAG.getNode((Smaller ? ISD::TRUNCATE : ISD::ANY_EXTEND),
503 // Handle a multi-element vector.
504 EVT IntermediateVT, RegisterVT;
505 unsigned NumIntermediates;
506 unsigned NumRegs = TLI.getVectorTypeBreakdown(*DAG.getContext(), ValueVT,
508 NumIntermediates, RegisterVT);
509 unsigned NumElements = ValueVT.getVectorNumElements();
511 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!");
512 NumParts = NumRegs; // Silence a compiler warning.
513 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!");
515 // Split the vector into intermediate operands.
516 SmallVector<SDValue, 8> Ops(NumIntermediates);
517 for (unsigned i = 0; i != NumIntermediates; ++i) {
518 if (IntermediateVT.isVector())
519 Ops[i] = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL,
521 DAG.getIntPtrConstant(i * (NumElements / NumIntermediates)));
523 Ops[i] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL,
524 IntermediateVT, Val, DAG.getIntPtrConstant(i));
527 // Split the intermediate operands into legal parts.
528 if (NumParts == NumIntermediates) {
529 // If the register was not expanded, promote or copy the value,
531 for (unsigned i = 0; i != NumParts; ++i)
532 getCopyToParts(DAG, DL, Ops[i], &Parts[i], 1, PartVT);
533 } else if (NumParts > 0) {
534 // If the intermediate type was expanded, split each the value into
536 assert(NumParts % NumIntermediates == 0 &&
537 "Must expand into a divisible number of parts!");
538 unsigned Factor = NumParts / NumIntermediates;
539 for (unsigned i = 0; i != NumIntermediates; ++i)
540 getCopyToParts(DAG, DL, Ops[i], &Parts[i*Factor], Factor, PartVT);
548 /// RegsForValue - This struct represents the registers (physical or virtual)
549 /// that a particular set of values is assigned, and the type information
550 /// about the value. The most common situation is to represent one value at a
551 /// time, but struct or array values are handled element-wise as multiple
552 /// values. The splitting of aggregates is performed recursively, so that we
553 /// never have aggregate-typed registers. The values at this point do not
554 /// necessarily have legal types, so each value may require one or more
555 /// registers of some legal type.
557 struct RegsForValue {
558 /// ValueVTs - The value types of the values, which may not be legal, and
559 /// may need be promoted or synthesized from one or more registers.
561 SmallVector<EVT, 4> ValueVTs;
563 /// RegVTs - The value types of the registers. This is the same size as
564 /// ValueVTs and it records, for each value, what the type of the assigned
565 /// register or registers are. (Individual values are never synthesized
566 /// from more than one type of register.)
568 /// With virtual registers, the contents of RegVTs is redundant with TLI's
569 /// getRegisterType member function, however when with physical registers
570 /// it is necessary to have a separate record of the types.
572 SmallVector<EVT, 4> RegVTs;
574 /// Regs - This list holds the registers assigned to the values.
575 /// Each legal or promoted value requires one register, and each
576 /// expanded value requires multiple registers.
578 SmallVector<unsigned, 4> Regs;
582 RegsForValue(const SmallVector<unsigned, 4> ®s,
583 EVT regvt, EVT valuevt)
584 : ValueVTs(1, valuevt), RegVTs(1, regvt), Regs(regs) {}
586 RegsForValue(LLVMContext &Context, const TargetLowering &tli,
587 unsigned Reg, Type *Ty) {
588 ComputeValueVTs(tli, Ty, ValueVTs);
590 for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) {
591 EVT ValueVT = ValueVTs[Value];
592 unsigned NumRegs = tli.getNumRegisters(Context, ValueVT);
593 EVT RegisterVT = tli.getRegisterType(Context, ValueVT);
594 for (unsigned i = 0; i != NumRegs; ++i)
595 Regs.push_back(Reg + i);
596 RegVTs.push_back(RegisterVT);
601 /// areValueTypesLegal - Return true if types of all the values are legal.
602 bool areValueTypesLegal(const TargetLowering &TLI) {
603 for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) {
604 EVT RegisterVT = RegVTs[Value];
605 if (!TLI.isTypeLegal(RegisterVT))
611 /// append - Add the specified values to this one.
612 void append(const RegsForValue &RHS) {
613 ValueVTs.append(RHS.ValueVTs.begin(), RHS.ValueVTs.end());
614 RegVTs.append(RHS.RegVTs.begin(), RHS.RegVTs.end());
615 Regs.append(RHS.Regs.begin(), RHS.Regs.end());
618 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from
619 /// this value and returns the result as a ValueVTs value. This uses
620 /// Chain/Flag as the input and updates them for the output Chain/Flag.
621 /// If the Flag pointer is NULL, no flag is used.
622 SDValue getCopyFromRegs(SelectionDAG &DAG, FunctionLoweringInfo &FuncInfo,
624 SDValue &Chain, SDValue *Flag) const;
626 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
627 /// specified value into the registers specified by this object. This uses
628 /// Chain/Flag as the input and updates them for the output Chain/Flag.
629 /// If the Flag pointer is NULL, no flag is used.
630 void getCopyToRegs(SDValue Val, SelectionDAG &DAG, DebugLoc dl,
631 SDValue &Chain, SDValue *Flag) const;
633 /// AddInlineAsmOperands - Add this value to the specified inlineasm node
634 /// operand list. This adds the code marker, matching input operand index
635 /// (if applicable), and includes the number of values added into it.
636 void AddInlineAsmOperands(unsigned Kind,
637 bool HasMatching, unsigned MatchingIdx,
639 std::vector<SDValue> &Ops) const;
643 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from
644 /// this value and returns the result as a ValueVT value. This uses
645 /// Chain/Flag as the input and updates them for the output Chain/Flag.
646 /// If the Flag pointer is NULL, no flag is used.
647 SDValue RegsForValue::getCopyFromRegs(SelectionDAG &DAG,
648 FunctionLoweringInfo &FuncInfo,
650 SDValue &Chain, SDValue *Flag) const {
651 // A Value with type {} or [0 x %t] needs no registers.
652 if (ValueVTs.empty())
655 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
657 // Assemble the legal parts into the final values.
658 SmallVector<SDValue, 4> Values(ValueVTs.size());
659 SmallVector<SDValue, 8> Parts;
660 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) {
661 // Copy the legal parts from the registers.
662 EVT ValueVT = ValueVTs[Value];
663 unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), ValueVT);
664 EVT RegisterVT = RegVTs[Value];
666 Parts.resize(NumRegs);
667 for (unsigned i = 0; i != NumRegs; ++i) {
670 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT);
672 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT, *Flag);
673 *Flag = P.getValue(2);
676 Chain = P.getValue(1);
679 // If the source register was virtual and if we know something about it,
680 // add an assert node.
681 if (!TargetRegisterInfo::isVirtualRegister(Regs[Part+i]) ||
682 !RegisterVT.isInteger() || RegisterVT.isVector())
685 const FunctionLoweringInfo::LiveOutInfo *LOI =
686 FuncInfo.GetLiveOutRegInfo(Regs[Part+i]);
690 unsigned RegSize = RegisterVT.getSizeInBits();
691 unsigned NumSignBits = LOI->NumSignBits;
692 unsigned NumZeroBits = LOI->KnownZero.countLeadingOnes();
694 // FIXME: We capture more information than the dag can represent. For
695 // now, just use the tightest assertzext/assertsext possible.
697 EVT FromVT(MVT::Other);
698 if (NumSignBits == RegSize)
699 isSExt = true, FromVT = MVT::i1; // ASSERT SEXT 1
700 else if (NumZeroBits >= RegSize-1)
701 isSExt = false, FromVT = MVT::i1; // ASSERT ZEXT 1
702 else if (NumSignBits > RegSize-8)
703 isSExt = true, FromVT = MVT::i8; // ASSERT SEXT 8
704 else if (NumZeroBits >= RegSize-8)
705 isSExt = false, FromVT = MVT::i8; // ASSERT ZEXT 8
706 else if (NumSignBits > RegSize-16)
707 isSExt = true, FromVT = MVT::i16; // ASSERT SEXT 16
708 else if (NumZeroBits >= RegSize-16)
709 isSExt = false, FromVT = MVT::i16; // ASSERT ZEXT 16
710 else if (NumSignBits > RegSize-32)
711 isSExt = true, FromVT = MVT::i32; // ASSERT SEXT 32
712 else if (NumZeroBits >= RegSize-32)
713 isSExt = false, FromVT = MVT::i32; // ASSERT ZEXT 32
717 // Add an assertion node.
718 assert(FromVT != MVT::Other);
719 Parts[i] = DAG.getNode(isSExt ? ISD::AssertSext : ISD::AssertZext, dl,
720 RegisterVT, P, DAG.getValueType(FromVT));
723 Values[Value] = getCopyFromParts(DAG, dl, Parts.begin(),
724 NumRegs, RegisterVT, ValueVT);
729 return DAG.getNode(ISD::MERGE_VALUES, dl,
730 DAG.getVTList(&ValueVTs[0], ValueVTs.size()),
731 &Values[0], ValueVTs.size());
734 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
735 /// specified value into the registers specified by this object. This uses
736 /// Chain/Flag as the input and updates them for the output Chain/Flag.
737 /// If the Flag pointer is NULL, no flag is used.
738 void RegsForValue::getCopyToRegs(SDValue Val, SelectionDAG &DAG, DebugLoc dl,
739 SDValue &Chain, SDValue *Flag) const {
740 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
742 // Get the list of the values's legal parts.
743 unsigned NumRegs = Regs.size();
744 SmallVector<SDValue, 8> Parts(NumRegs);
745 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) {
746 EVT ValueVT = ValueVTs[Value];
747 unsigned NumParts = TLI.getNumRegisters(*DAG.getContext(), ValueVT);
748 EVT RegisterVT = RegVTs[Value];
750 getCopyToParts(DAG, dl, Val.getValue(Val.getResNo() + Value),
751 &Parts[Part], NumParts, RegisterVT);
755 // Copy the parts into the registers.
756 SmallVector<SDValue, 8> Chains(NumRegs);
757 for (unsigned i = 0; i != NumRegs; ++i) {
760 Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i]);
762 Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i], *Flag);
763 *Flag = Part.getValue(1);
766 Chains[i] = Part.getValue(0);
769 if (NumRegs == 1 || Flag)
770 // If NumRegs > 1 && Flag is used then the use of the last CopyToReg is
771 // flagged to it. That is the CopyToReg nodes and the user are considered
772 // a single scheduling unit. If we create a TokenFactor and return it as
773 // chain, then the TokenFactor is both a predecessor (operand) of the
774 // user as well as a successor (the TF operands are flagged to the user).
775 // c1, f1 = CopyToReg
776 // c2, f2 = CopyToReg
777 // c3 = TokenFactor c1, c2
780 Chain = Chains[NumRegs-1];
782 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Chains[0], NumRegs);
785 /// AddInlineAsmOperands - Add this value to the specified inlineasm node
786 /// operand list. This adds the code marker and includes the number of
787 /// values added into it.
788 void RegsForValue::AddInlineAsmOperands(unsigned Code, bool HasMatching,
789 unsigned MatchingIdx,
791 std::vector<SDValue> &Ops) const {
792 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
794 unsigned Flag = InlineAsm::getFlagWord(Code, Regs.size());
796 Flag = InlineAsm::getFlagWordForMatchingOp(Flag, MatchingIdx);
797 else if (!Regs.empty() &&
798 TargetRegisterInfo::isVirtualRegister(Regs.front())) {
799 // Put the register class of the virtual registers in the flag word. That
800 // way, later passes can recompute register class constraints for inline
801 // assembly as well as normal instructions.
802 // Don't do this for tied operands that can use the regclass information
804 const MachineRegisterInfo &MRI = DAG.getMachineFunction().getRegInfo();
805 const TargetRegisterClass *RC = MRI.getRegClass(Regs.front());
806 Flag = InlineAsm::getFlagWordForRegClass(Flag, RC->getID());
809 SDValue Res = DAG.getTargetConstant(Flag, MVT::i32);
812 for (unsigned Value = 0, Reg = 0, e = ValueVTs.size(); Value != e; ++Value) {
813 unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), ValueVTs[Value]);
814 EVT RegisterVT = RegVTs[Value];
815 for (unsigned i = 0; i != NumRegs; ++i) {
816 assert(Reg < Regs.size() && "Mismatch in # registers expected");
817 Ops.push_back(DAG.getRegister(Regs[Reg++], RegisterVT));
822 void SelectionDAGBuilder::init(GCFunctionInfo *gfi, AliasAnalysis &aa,
823 const TargetLibraryInfo *li) {
827 TD = DAG.getTarget().getTargetData();
828 Context = DAG.getContext();
829 LPadToCallSiteMap.clear();
832 /// clear - Clear out the current SelectionDAG and the associated
833 /// state and prepare this SelectionDAGBuilder object to be used
834 /// for a new block. This doesn't clear out information about
835 /// additional blocks that are needed to complete switch lowering
836 /// or PHI node updating; that information is cleared out as it is
838 void SelectionDAGBuilder::clear() {
840 UnusedArgNodeMap.clear();
841 PendingLoads.clear();
842 PendingExports.clear();
843 CurDebugLoc = DebugLoc();
847 /// clearDanglingDebugInfo - Clear the dangling debug information
848 /// map. This function is separated from the clear so that debug
849 /// information that is dangling in a basic block can be properly
850 /// resolved in a different basic block. This allows the
851 /// SelectionDAG to resolve dangling debug information attached
853 void SelectionDAGBuilder::clearDanglingDebugInfo() {
854 DanglingDebugInfoMap.clear();
857 /// getRoot - Return the current virtual root of the Selection DAG,
858 /// flushing any PendingLoad items. This must be done before emitting
859 /// a store or any other node that may need to be ordered after any
860 /// prior load instructions.
862 SDValue SelectionDAGBuilder::getRoot() {
863 if (PendingLoads.empty())
864 return DAG.getRoot();
866 if (PendingLoads.size() == 1) {
867 SDValue Root = PendingLoads[0];
869 PendingLoads.clear();
873 // Otherwise, we have to make a token factor node.
874 SDValue Root = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), MVT::Other,
875 &PendingLoads[0], PendingLoads.size());
876 PendingLoads.clear();
881 /// getControlRoot - Similar to getRoot, but instead of flushing all the
882 /// PendingLoad items, flush all the PendingExports items. It is necessary
883 /// to do this before emitting a terminator instruction.
885 SDValue SelectionDAGBuilder::getControlRoot() {
886 SDValue Root = DAG.getRoot();
888 if (PendingExports.empty())
891 // Turn all of the CopyToReg chains into one factored node.
892 if (Root.getOpcode() != ISD::EntryToken) {
893 unsigned i = 0, e = PendingExports.size();
894 for (; i != e; ++i) {
895 assert(PendingExports[i].getNode()->getNumOperands() > 1);
896 if (PendingExports[i].getNode()->getOperand(0) == Root)
897 break; // Don't add the root if we already indirectly depend on it.
901 PendingExports.push_back(Root);
904 Root = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), MVT::Other,
906 PendingExports.size());
907 PendingExports.clear();
912 void SelectionDAGBuilder::AssignOrderingToNode(const SDNode *Node) {
913 if (DAG.GetOrdering(Node) != 0) return; // Already has ordering.
914 DAG.AssignOrdering(Node, SDNodeOrder);
916 for (unsigned I = 0, E = Node->getNumOperands(); I != E; ++I)
917 AssignOrderingToNode(Node->getOperand(I).getNode());
920 void SelectionDAGBuilder::visit(const Instruction &I) {
921 // Set up outgoing PHI node register values before emitting the terminator.
922 if (isa<TerminatorInst>(&I))
923 HandlePHINodesInSuccessorBlocks(I.getParent());
925 CurDebugLoc = I.getDebugLoc();
927 visit(I.getOpcode(), I);
929 if (!isa<TerminatorInst>(&I) && !HasTailCall)
930 CopyToExportRegsIfNeeded(&I);
932 CurDebugLoc = DebugLoc();
935 void SelectionDAGBuilder::visitPHI(const PHINode &) {
936 llvm_unreachable("SelectionDAGBuilder shouldn't visit PHI nodes!");
939 void SelectionDAGBuilder::visit(unsigned Opcode, const User &I) {
940 // Note: this doesn't use InstVisitor, because it has to work with
941 // ConstantExpr's in addition to instructions.
943 default: llvm_unreachable("Unknown instruction type encountered!");
944 // Build the switch statement using the Instruction.def file.
945 #define HANDLE_INST(NUM, OPCODE, CLASS) \
946 case Instruction::OPCODE: visit##OPCODE((const CLASS&)I); break;
947 #include "llvm/Instruction.def"
950 // Assign the ordering to the freshly created DAG nodes.
951 if (NodeMap.count(&I)) {
953 AssignOrderingToNode(getValue(&I).getNode());
957 // resolveDanglingDebugInfo - if we saw an earlier dbg_value referring to V,
958 // generate the debug data structures now that we've seen its definition.
959 void SelectionDAGBuilder::resolveDanglingDebugInfo(const Value *V,
961 DanglingDebugInfo &DDI = DanglingDebugInfoMap[V];
963 const DbgValueInst *DI = DDI.getDI();
964 DebugLoc dl = DDI.getdl();
965 unsigned DbgSDNodeOrder = DDI.getSDNodeOrder();
966 MDNode *Variable = DI->getVariable();
967 uint64_t Offset = DI->getOffset();
970 if (!EmitFuncArgumentDbgValue(V, Variable, Offset, Val)) {
971 SDV = DAG.getDbgValue(Variable, Val.getNode(),
972 Val.getResNo(), Offset, dl, DbgSDNodeOrder);
973 DAG.AddDbgValue(SDV, Val.getNode(), false);
976 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
977 DanglingDebugInfoMap[V] = DanglingDebugInfo();
981 /// getValue - Return an SDValue for the given Value.
982 SDValue SelectionDAGBuilder::getValue(const Value *V) {
983 // If we already have an SDValue for this value, use it. It's important
984 // to do this first, so that we don't create a CopyFromReg if we already
985 // have a regular SDValue.
986 SDValue &N = NodeMap[V];
987 if (N.getNode()) return N;
989 // If there's a virtual register allocated and initialized for this
991 DenseMap<const Value *, unsigned>::iterator It = FuncInfo.ValueMap.find(V);
992 if (It != FuncInfo.ValueMap.end()) {
993 unsigned InReg = It->second;
994 RegsForValue RFV(*DAG.getContext(), TLI, InReg, V->getType());
995 SDValue Chain = DAG.getEntryNode();
996 N = RFV.getCopyFromRegs(DAG, FuncInfo, getCurDebugLoc(), Chain, NULL);
997 resolveDanglingDebugInfo(V, N);
1001 // Otherwise create a new SDValue and remember it.
1002 SDValue Val = getValueImpl(V);
1004 resolveDanglingDebugInfo(V, Val);
1008 /// getNonRegisterValue - Return an SDValue for the given Value, but
1009 /// don't look in FuncInfo.ValueMap for a virtual register.
1010 SDValue SelectionDAGBuilder::getNonRegisterValue(const Value *V) {
1011 // If we already have an SDValue for this value, use it.
1012 SDValue &N = NodeMap[V];
1013 if (N.getNode()) return N;
1015 // Otherwise create a new SDValue and remember it.
1016 SDValue Val = getValueImpl(V);
1018 resolveDanglingDebugInfo(V, Val);
1022 /// getValueImpl - Helper function for getValue and getNonRegisterValue.
1023 /// Create an SDValue for the given value.
1024 SDValue SelectionDAGBuilder::getValueImpl(const Value *V) {
1025 if (const Constant *C = dyn_cast<Constant>(V)) {
1026 EVT VT = TLI.getValueType(V->getType(), true);
1028 if (const ConstantInt *CI = dyn_cast<ConstantInt>(C))
1029 return DAG.getConstant(*CI, VT);
1031 if (const GlobalValue *GV = dyn_cast<GlobalValue>(C))
1032 return DAG.getGlobalAddress(GV, getCurDebugLoc(), VT);
1034 if (isa<ConstantPointerNull>(C))
1035 return DAG.getConstant(0, TLI.getPointerTy());
1037 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(C))
1038 return DAG.getConstantFP(*CFP, VT);
1040 if (isa<UndefValue>(C) && !V->getType()->isAggregateType())
1041 return DAG.getUNDEF(VT);
1043 if (const ConstantExpr *CE = dyn_cast<ConstantExpr>(C)) {
1044 visit(CE->getOpcode(), *CE);
1045 SDValue N1 = NodeMap[V];
1046 assert(N1.getNode() && "visit didn't populate the NodeMap!");
1050 if (isa<ConstantStruct>(C) || isa<ConstantArray>(C)) {
1051 SmallVector<SDValue, 4> Constants;
1052 for (User::const_op_iterator OI = C->op_begin(), OE = C->op_end();
1054 SDNode *Val = getValue(*OI).getNode();
1055 // If the operand is an empty aggregate, there are no values.
1057 // Add each leaf value from the operand to the Constants list
1058 // to form a flattened list of all the values.
1059 for (unsigned i = 0, e = Val->getNumValues(); i != e; ++i)
1060 Constants.push_back(SDValue(Val, i));
1063 return DAG.getMergeValues(&Constants[0], Constants.size(),
1067 if (const ConstantDataSequential *CDS =
1068 dyn_cast<ConstantDataSequential>(C)) {
1069 SmallVector<SDValue, 4> Ops;
1070 for (unsigned i = 0, e = CDS->getNumElements(); i != e; ++i) {
1071 SDNode *Val = getValue(CDS->getElementAsConstant(i)).getNode();
1072 // Add each leaf value from the operand to the Constants list
1073 // to form a flattened list of all the values.
1074 for (unsigned i = 0, e = Val->getNumValues(); i != e; ++i)
1075 Ops.push_back(SDValue(Val, i));
1078 if (isa<ArrayType>(CDS->getType()))
1079 return DAG.getMergeValues(&Ops[0], Ops.size(), getCurDebugLoc());
1080 return NodeMap[V] = DAG.getNode(ISD::BUILD_VECTOR, getCurDebugLoc(),
1081 VT, &Ops[0], Ops.size());
1084 if (C->getType()->isStructTy() || C->getType()->isArrayTy()) {
1085 assert((isa<ConstantAggregateZero>(C) || isa<UndefValue>(C)) &&
1086 "Unknown struct or array constant!");
1088 SmallVector<EVT, 4> ValueVTs;
1089 ComputeValueVTs(TLI, C->getType(), ValueVTs);
1090 unsigned NumElts = ValueVTs.size();
1092 return SDValue(); // empty struct
1093 SmallVector<SDValue, 4> Constants(NumElts);
1094 for (unsigned i = 0; i != NumElts; ++i) {
1095 EVT EltVT = ValueVTs[i];
1096 if (isa<UndefValue>(C))
1097 Constants[i] = DAG.getUNDEF(EltVT);
1098 else if (EltVT.isFloatingPoint())
1099 Constants[i] = DAG.getConstantFP(0, EltVT);
1101 Constants[i] = DAG.getConstant(0, EltVT);
1104 return DAG.getMergeValues(&Constants[0], NumElts,
1108 if (const BlockAddress *BA = dyn_cast<BlockAddress>(C))
1109 return DAG.getBlockAddress(BA, VT);
1111 VectorType *VecTy = cast<VectorType>(V->getType());
1112 unsigned NumElements = VecTy->getNumElements();
1114 // Now that we know the number and type of the elements, get that number of
1115 // elements into the Ops array based on what kind of constant it is.
1116 SmallVector<SDValue, 16> Ops;
1117 if (const ConstantVector *CV = dyn_cast<ConstantVector>(C)) {
1118 for (unsigned i = 0; i != NumElements; ++i)
1119 Ops.push_back(getValue(CV->getOperand(i)));
1121 assert(isa<ConstantAggregateZero>(C) && "Unknown vector constant!");
1122 EVT EltVT = TLI.getValueType(VecTy->getElementType());
1125 if (EltVT.isFloatingPoint())
1126 Op = DAG.getConstantFP(0, EltVT);
1128 Op = DAG.getConstant(0, EltVT);
1129 Ops.assign(NumElements, Op);
1132 // Create a BUILD_VECTOR node.
1133 return NodeMap[V] = DAG.getNode(ISD::BUILD_VECTOR, getCurDebugLoc(),
1134 VT, &Ops[0], Ops.size());
1137 // If this is a static alloca, generate it as the frameindex instead of
1139 if (const AllocaInst *AI = dyn_cast<AllocaInst>(V)) {
1140 DenseMap<const AllocaInst*, int>::iterator SI =
1141 FuncInfo.StaticAllocaMap.find(AI);
1142 if (SI != FuncInfo.StaticAllocaMap.end())
1143 return DAG.getFrameIndex(SI->second, TLI.getPointerTy());
1146 // If this is an instruction which fast-isel has deferred, select it now.
1147 if (const Instruction *Inst = dyn_cast<Instruction>(V)) {
1148 unsigned InReg = FuncInfo.InitializeRegForValue(Inst);
1149 RegsForValue RFV(*DAG.getContext(), TLI, InReg, Inst->getType());
1150 SDValue Chain = DAG.getEntryNode();
1151 return RFV.getCopyFromRegs(DAG, FuncInfo, getCurDebugLoc(), Chain, NULL);
1154 llvm_unreachable("Can't get register for value!");
1157 void SelectionDAGBuilder::visitRet(const ReturnInst &I) {
1158 SDValue Chain = getControlRoot();
1159 SmallVector<ISD::OutputArg, 8> Outs;
1160 SmallVector<SDValue, 8> OutVals;
1162 if (!FuncInfo.CanLowerReturn) {
1163 unsigned DemoteReg = FuncInfo.DemoteRegister;
1164 const Function *F = I.getParent()->getParent();
1166 // Emit a store of the return value through the virtual register.
1167 // Leave Outs empty so that LowerReturn won't try to load return
1168 // registers the usual way.
1169 SmallVector<EVT, 1> PtrValueVTs;
1170 ComputeValueVTs(TLI, PointerType::getUnqual(F->getReturnType()),
1173 SDValue RetPtr = DAG.getRegister(DemoteReg, PtrValueVTs[0]);
1174 SDValue RetOp = getValue(I.getOperand(0));
1176 SmallVector<EVT, 4> ValueVTs;
1177 SmallVector<uint64_t, 4> Offsets;
1178 ComputeValueVTs(TLI, I.getOperand(0)->getType(), ValueVTs, &Offsets);
1179 unsigned NumValues = ValueVTs.size();
1181 SmallVector<SDValue, 4> Chains(NumValues);
1182 for (unsigned i = 0; i != NumValues; ++i) {
1183 SDValue Add = DAG.getNode(ISD::ADD, getCurDebugLoc(),
1184 RetPtr.getValueType(), RetPtr,
1185 DAG.getIntPtrConstant(Offsets[i]));
1187 DAG.getStore(Chain, getCurDebugLoc(),
1188 SDValue(RetOp.getNode(), RetOp.getResNo() + i),
1189 // FIXME: better loc info would be nice.
1190 Add, MachinePointerInfo(), false, false, 0);
1193 Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(),
1194 MVT::Other, &Chains[0], NumValues);
1195 } else if (I.getNumOperands() != 0) {
1196 SmallVector<EVT, 4> ValueVTs;
1197 ComputeValueVTs(TLI, I.getOperand(0)->getType(), ValueVTs);
1198 unsigned NumValues = ValueVTs.size();
1200 SDValue RetOp = getValue(I.getOperand(0));
1201 for (unsigned j = 0, f = NumValues; j != f; ++j) {
1202 EVT VT = ValueVTs[j];
1204 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
1206 const Function *F = I.getParent()->getParent();
1207 if (F->paramHasAttr(0, Attribute::SExt))
1208 ExtendKind = ISD::SIGN_EXTEND;
1209 else if (F->paramHasAttr(0, Attribute::ZExt))
1210 ExtendKind = ISD::ZERO_EXTEND;
1212 if (ExtendKind != ISD::ANY_EXTEND && VT.isInteger())
1213 VT = TLI.getTypeForExtArgOrReturn(*DAG.getContext(), VT, ExtendKind);
1215 unsigned NumParts = TLI.getNumRegisters(*DAG.getContext(), VT);
1216 EVT PartVT = TLI.getRegisterType(*DAG.getContext(), VT);
1217 SmallVector<SDValue, 4> Parts(NumParts);
1218 getCopyToParts(DAG, getCurDebugLoc(),
1219 SDValue(RetOp.getNode(), RetOp.getResNo() + j),
1220 &Parts[0], NumParts, PartVT, ExtendKind);
1222 // 'inreg' on function refers to return value
1223 ISD::ArgFlagsTy Flags = ISD::ArgFlagsTy();
1224 if (F->paramHasAttr(0, Attribute::InReg))
1227 // Propagate extension type if any
1228 if (ExtendKind == ISD::SIGN_EXTEND)
1230 else if (ExtendKind == ISD::ZERO_EXTEND)
1233 for (unsigned i = 0; i < NumParts; ++i) {
1234 Outs.push_back(ISD::OutputArg(Flags, Parts[i].getValueType(),
1236 OutVals.push_back(Parts[i]);
1242 bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg();
1243 CallingConv::ID CallConv =
1244 DAG.getMachineFunction().getFunction()->getCallingConv();
1245 Chain = TLI.LowerReturn(Chain, CallConv, isVarArg,
1246 Outs, OutVals, getCurDebugLoc(), DAG);
1248 // Verify that the target's LowerReturn behaved as expected.
1249 assert(Chain.getNode() && Chain.getValueType() == MVT::Other &&
1250 "LowerReturn didn't return a valid chain!");
1252 // Update the DAG with the new chain value resulting from return lowering.
1256 /// CopyToExportRegsIfNeeded - If the given value has virtual registers
1257 /// created for it, emit nodes to copy the value into the virtual
1259 void SelectionDAGBuilder::CopyToExportRegsIfNeeded(const Value *V) {
1261 if (V->getType()->isEmptyTy())
1264 DenseMap<const Value *, unsigned>::iterator VMI = FuncInfo.ValueMap.find(V);
1265 if (VMI != FuncInfo.ValueMap.end()) {
1266 assert(!V->use_empty() && "Unused value assigned virtual registers!");
1267 CopyValueToVirtualRegister(V, VMI->second);
1271 /// ExportFromCurrentBlock - If this condition isn't known to be exported from
1272 /// the current basic block, add it to ValueMap now so that we'll get a
1274 void SelectionDAGBuilder::ExportFromCurrentBlock(const Value *V) {
1275 // No need to export constants.
1276 if (!isa<Instruction>(V) && !isa<Argument>(V)) return;
1278 // Already exported?
1279 if (FuncInfo.isExportedInst(V)) return;
1281 unsigned Reg = FuncInfo.InitializeRegForValue(V);
1282 CopyValueToVirtualRegister(V, Reg);
1285 bool SelectionDAGBuilder::isExportableFromCurrentBlock(const Value *V,
1286 const BasicBlock *FromBB) {
1287 // The operands of the setcc have to be in this block. We don't know
1288 // how to export them from some other block.
1289 if (const Instruction *VI = dyn_cast<Instruction>(V)) {
1290 // Can export from current BB.
1291 if (VI->getParent() == FromBB)
1294 // Is already exported, noop.
1295 return FuncInfo.isExportedInst(V);
1298 // If this is an argument, we can export it if the BB is the entry block or
1299 // if it is already exported.
1300 if (isa<Argument>(V)) {
1301 if (FromBB == &FromBB->getParent()->getEntryBlock())
1304 // Otherwise, can only export this if it is already exported.
1305 return FuncInfo.isExportedInst(V);
1308 // Otherwise, constants can always be exported.
1312 /// Return branch probability calculated by BranchProbabilityInfo for IR blocks.
1313 uint32_t SelectionDAGBuilder::getEdgeWeight(const MachineBasicBlock *Src,
1314 const MachineBasicBlock *Dst) const {
1315 BranchProbabilityInfo *BPI = FuncInfo.BPI;
1318 const BasicBlock *SrcBB = Src->getBasicBlock();
1319 const BasicBlock *DstBB = Dst->getBasicBlock();
1320 return BPI->getEdgeWeight(SrcBB, DstBB);
1323 void SelectionDAGBuilder::
1324 addSuccessorWithWeight(MachineBasicBlock *Src, MachineBasicBlock *Dst,
1325 uint32_t Weight /* = 0 */) {
1327 Weight = getEdgeWeight(Src, Dst);
1328 Src->addSuccessor(Dst, Weight);
1332 static bool InBlock(const Value *V, const BasicBlock *BB) {
1333 if (const Instruction *I = dyn_cast<Instruction>(V))
1334 return I->getParent() == BB;
1338 /// EmitBranchForMergedCondition - Helper method for FindMergedConditions.
1339 /// This function emits a branch and is used at the leaves of an OR or an
1340 /// AND operator tree.
1343 SelectionDAGBuilder::EmitBranchForMergedCondition(const Value *Cond,
1344 MachineBasicBlock *TBB,
1345 MachineBasicBlock *FBB,
1346 MachineBasicBlock *CurBB,
1347 MachineBasicBlock *SwitchBB) {
1348 const BasicBlock *BB = CurBB->getBasicBlock();
1350 // If the leaf of the tree is a comparison, merge the condition into
1352 if (const CmpInst *BOp = dyn_cast<CmpInst>(Cond)) {
1353 // The operands of the cmp have to be in this block. We don't know
1354 // how to export them from some other block. If this is the first block
1355 // of the sequence, no exporting is needed.
1356 if (CurBB == SwitchBB ||
1357 (isExportableFromCurrentBlock(BOp->getOperand(0), BB) &&
1358 isExportableFromCurrentBlock(BOp->getOperand(1), BB))) {
1359 ISD::CondCode Condition;
1360 if (const ICmpInst *IC = dyn_cast<ICmpInst>(Cond)) {
1361 Condition = getICmpCondCode(IC->getPredicate());
1362 } else if (const FCmpInst *FC = dyn_cast<FCmpInst>(Cond)) {
1363 Condition = getFCmpCondCode(FC->getPredicate());
1364 if (TM.Options.NoNaNsFPMath)
1365 Condition = getFCmpCodeWithoutNaN(Condition);
1367 Condition = ISD::SETEQ; // silence warning.
1368 llvm_unreachable("Unknown compare instruction");
1371 CaseBlock CB(Condition, BOp->getOperand(0),
1372 BOp->getOperand(1), NULL, TBB, FBB, CurBB);
1373 SwitchCases.push_back(CB);
1378 // Create a CaseBlock record representing this branch.
1379 CaseBlock CB(ISD::SETEQ, Cond, ConstantInt::getTrue(*DAG.getContext()),
1380 NULL, TBB, FBB, CurBB);
1381 SwitchCases.push_back(CB);
1384 /// FindMergedConditions - If Cond is an expression like
1385 void SelectionDAGBuilder::FindMergedConditions(const Value *Cond,
1386 MachineBasicBlock *TBB,
1387 MachineBasicBlock *FBB,
1388 MachineBasicBlock *CurBB,
1389 MachineBasicBlock *SwitchBB,
1391 // If this node is not part of the or/and tree, emit it as a branch.
1392 const Instruction *BOp = dyn_cast<Instruction>(Cond);
1393 if (!BOp || !(isa<BinaryOperator>(BOp) || isa<CmpInst>(BOp)) ||
1394 (unsigned)BOp->getOpcode() != Opc || !BOp->hasOneUse() ||
1395 BOp->getParent() != CurBB->getBasicBlock() ||
1396 !InBlock(BOp->getOperand(0), CurBB->getBasicBlock()) ||
1397 !InBlock(BOp->getOperand(1), CurBB->getBasicBlock())) {
1398 EmitBranchForMergedCondition(Cond, TBB, FBB, CurBB, SwitchBB);
1402 // Create TmpBB after CurBB.
1403 MachineFunction::iterator BBI = CurBB;
1404 MachineFunction &MF = DAG.getMachineFunction();
1405 MachineBasicBlock *TmpBB = MF.CreateMachineBasicBlock(CurBB->getBasicBlock());
1406 CurBB->getParent()->insert(++BBI, TmpBB);
1408 if (Opc == Instruction::Or) {
1409 // Codegen X | Y as:
1417 // Emit the LHS condition.
1418 FindMergedConditions(BOp->getOperand(0), TBB, TmpBB, CurBB, SwitchBB, Opc);
1420 // Emit the RHS condition into TmpBB.
1421 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, SwitchBB, Opc);
1423 assert(Opc == Instruction::And && "Unknown merge op!");
1424 // Codegen X & Y as:
1431 // This requires creation of TmpBB after CurBB.
1433 // Emit the LHS condition.
1434 FindMergedConditions(BOp->getOperand(0), TmpBB, FBB, CurBB, SwitchBB, Opc);
1436 // Emit the RHS condition into TmpBB.
1437 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, SwitchBB, Opc);
1441 /// If the set of cases should be emitted as a series of branches, return true.
1442 /// If we should emit this as a bunch of and/or'd together conditions, return
1445 SelectionDAGBuilder::ShouldEmitAsBranches(const std::vector<CaseBlock> &Cases){
1446 if (Cases.size() != 2) return true;
1448 // If this is two comparisons of the same values or'd or and'd together, they
1449 // will get folded into a single comparison, so don't emit two blocks.
1450 if ((Cases[0].CmpLHS == Cases[1].CmpLHS &&
1451 Cases[0].CmpRHS == Cases[1].CmpRHS) ||
1452 (Cases[0].CmpRHS == Cases[1].CmpLHS &&
1453 Cases[0].CmpLHS == Cases[1].CmpRHS)) {
1457 // Handle: (X != null) | (Y != null) --> (X|Y) != 0
1458 // Handle: (X == null) & (Y == null) --> (X|Y) == 0
1459 if (Cases[0].CmpRHS == Cases[1].CmpRHS &&
1460 Cases[0].CC == Cases[1].CC &&
1461 isa<Constant>(Cases[0].CmpRHS) &&
1462 cast<Constant>(Cases[0].CmpRHS)->isNullValue()) {
1463 if (Cases[0].CC == ISD::SETEQ && Cases[0].TrueBB == Cases[1].ThisBB)
1465 if (Cases[0].CC == ISD::SETNE && Cases[0].FalseBB == Cases[1].ThisBB)
1472 void SelectionDAGBuilder::visitBr(const BranchInst &I) {
1473 MachineBasicBlock *BrMBB = FuncInfo.MBB;
1475 // Update machine-CFG edges.
1476 MachineBasicBlock *Succ0MBB = FuncInfo.MBBMap[I.getSuccessor(0)];
1478 // Figure out which block is immediately after the current one.
1479 MachineBasicBlock *NextBlock = 0;
1480 MachineFunction::iterator BBI = BrMBB;
1481 if (++BBI != FuncInfo.MF->end())
1484 if (I.isUnconditional()) {
1485 // Update machine-CFG edges.
1486 BrMBB->addSuccessor(Succ0MBB);
1488 // If this is not a fall-through branch, emit the branch.
1489 if (Succ0MBB != NextBlock)
1490 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(),
1491 MVT::Other, getControlRoot(),
1492 DAG.getBasicBlock(Succ0MBB)));
1497 // If this condition is one of the special cases we handle, do special stuff
1499 const Value *CondVal = I.getCondition();
1500 MachineBasicBlock *Succ1MBB = FuncInfo.MBBMap[I.getSuccessor(1)];
1502 // If this is a series of conditions that are or'd or and'd together, emit
1503 // this as a sequence of branches instead of setcc's with and/or operations.
1504 // As long as jumps are not expensive, this should improve performance.
1505 // For example, instead of something like:
1518 if (const BinaryOperator *BOp = dyn_cast<BinaryOperator>(CondVal)) {
1519 if (!TLI.isJumpExpensive() &&
1521 (BOp->getOpcode() == Instruction::And ||
1522 BOp->getOpcode() == Instruction::Or)) {
1523 FindMergedConditions(BOp, Succ0MBB, Succ1MBB, BrMBB, BrMBB,
1525 // If the compares in later blocks need to use values not currently
1526 // exported from this block, export them now. This block should always
1527 // be the first entry.
1528 assert(SwitchCases[0].ThisBB == BrMBB && "Unexpected lowering!");
1530 // Allow some cases to be rejected.
1531 if (ShouldEmitAsBranches(SwitchCases)) {
1532 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i) {
1533 ExportFromCurrentBlock(SwitchCases[i].CmpLHS);
1534 ExportFromCurrentBlock(SwitchCases[i].CmpRHS);
1537 // Emit the branch for this block.
1538 visitSwitchCase(SwitchCases[0], BrMBB);
1539 SwitchCases.erase(SwitchCases.begin());
1543 // Okay, we decided not to do this, remove any inserted MBB's and clear
1545 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i)
1546 FuncInfo.MF->erase(SwitchCases[i].ThisBB);
1548 SwitchCases.clear();
1552 // Create a CaseBlock record representing this branch.
1553 CaseBlock CB(ISD::SETEQ, CondVal, ConstantInt::getTrue(*DAG.getContext()),
1554 NULL, Succ0MBB, Succ1MBB, BrMBB);
1556 // Use visitSwitchCase to actually insert the fast branch sequence for this
1558 visitSwitchCase(CB, BrMBB);
1561 /// visitSwitchCase - Emits the necessary code to represent a single node in
1562 /// the binary search tree resulting from lowering a switch instruction.
1563 void SelectionDAGBuilder::visitSwitchCase(CaseBlock &CB,
1564 MachineBasicBlock *SwitchBB) {
1566 SDValue CondLHS = getValue(CB.CmpLHS);
1567 DebugLoc dl = getCurDebugLoc();
1569 // Build the setcc now.
1570 if (CB.CmpMHS == NULL) {
1571 // Fold "(X == true)" to X and "(X == false)" to !X to
1572 // handle common cases produced by branch lowering.
1573 if (CB.CmpRHS == ConstantInt::getTrue(*DAG.getContext()) &&
1574 CB.CC == ISD::SETEQ)
1576 else if (CB.CmpRHS == ConstantInt::getFalse(*DAG.getContext()) &&
1577 CB.CC == ISD::SETEQ) {
1578 SDValue True = DAG.getConstant(1, CondLHS.getValueType());
1579 Cond = DAG.getNode(ISD::XOR, dl, CondLHS.getValueType(), CondLHS, True);
1581 Cond = DAG.getSetCC(dl, MVT::i1, CondLHS, getValue(CB.CmpRHS), CB.CC);
1583 assert(CB.CC == ISD::SETCC_INVALID &&
1584 "Condition is undefined for to-the-range belonging check.");
1586 const APInt& Low = cast<ConstantInt>(CB.CmpLHS)->getValue();
1587 const APInt& High = cast<ConstantInt>(CB.CmpRHS)->getValue();
1589 SDValue CmpOp = getValue(CB.CmpMHS);
1590 EVT VT = CmpOp.getValueType();
1592 if (cast<ConstantInt>(CB.CmpLHS)->isMinValue(false)) {
1593 Cond = DAG.getSetCC(dl, MVT::i1, CmpOp, DAG.getConstant(High, VT),
1596 SDValue SUB = DAG.getNode(ISD::SUB, dl,
1597 VT, CmpOp, DAG.getConstant(Low, VT));
1598 Cond = DAG.getSetCC(dl, MVT::i1, SUB,
1599 DAG.getConstant(High-Low, VT), ISD::SETULE);
1603 // Update successor info
1604 addSuccessorWithWeight(SwitchBB, CB.TrueBB, CB.TrueWeight);
1605 // TrueBB and FalseBB are always different unless the incoming IR is
1606 // degenerate. This only happens when running llc on weird IR.
1607 if (CB.TrueBB != CB.FalseBB)
1608 addSuccessorWithWeight(SwitchBB, CB.FalseBB, CB.FalseWeight);
1610 // Set NextBlock to be the MBB immediately after the current one, if any.
1611 // This is used to avoid emitting unnecessary branches to the next block.
1612 MachineBasicBlock *NextBlock = 0;
1613 MachineFunction::iterator BBI = SwitchBB;
1614 if (++BBI != FuncInfo.MF->end())
1617 // If the lhs block is the next block, invert the condition so that we can
1618 // fall through to the lhs instead of the rhs block.
1619 if (CB.TrueBB == NextBlock) {
1620 std::swap(CB.TrueBB, CB.FalseBB);
1621 SDValue True = DAG.getConstant(1, Cond.getValueType());
1622 Cond = DAG.getNode(ISD::XOR, dl, Cond.getValueType(), Cond, True);
1625 SDValue BrCond = DAG.getNode(ISD::BRCOND, dl,
1626 MVT::Other, getControlRoot(), Cond,
1627 DAG.getBasicBlock(CB.TrueBB));
1629 // Insert the false branch. Do this even if it's a fall through branch,
1630 // this makes it easier to do DAG optimizations which require inverting
1631 // the branch condition.
1632 BrCond = DAG.getNode(ISD::BR, dl, MVT::Other, BrCond,
1633 DAG.getBasicBlock(CB.FalseBB));
1635 DAG.setRoot(BrCond);
1638 /// visitJumpTable - Emit JumpTable node in the current MBB
1639 void SelectionDAGBuilder::visitJumpTable(JumpTable &JT) {
1640 // Emit the code for the jump table
1641 assert(JT.Reg != -1U && "Should lower JT Header first!");
1642 EVT PTy = TLI.getPointerTy();
1643 SDValue Index = DAG.getCopyFromReg(getControlRoot(), getCurDebugLoc(),
1645 SDValue Table = DAG.getJumpTable(JT.JTI, PTy);
1646 SDValue BrJumpTable = DAG.getNode(ISD::BR_JT, getCurDebugLoc(),
1647 MVT::Other, Index.getValue(1),
1649 DAG.setRoot(BrJumpTable);
1652 /// visitJumpTableHeader - This function emits necessary code to produce index
1653 /// in the JumpTable from switch case.
1654 void SelectionDAGBuilder::visitJumpTableHeader(JumpTable &JT,
1655 JumpTableHeader &JTH,
1656 MachineBasicBlock *SwitchBB) {
1657 // Subtract the lowest switch case value from the value being switched on and
1658 // conditional branch to default mbb if the result is greater than the
1659 // difference between smallest and largest cases.
1660 SDValue SwitchOp = getValue(JTH.SValue);
1661 EVT VT = SwitchOp.getValueType();
1662 SDValue Sub = DAG.getNode(ISD::SUB, getCurDebugLoc(), VT, SwitchOp,
1663 DAG.getConstant(JTH.First, VT));
1665 // The SDNode we just created, which holds the value being switched on minus
1666 // the smallest case value, needs to be copied to a virtual register so it
1667 // can be used as an index into the jump table in a subsequent basic block.
1668 // This value may be smaller or larger than the target's pointer type, and
1669 // therefore require extension or truncating.
1670 SwitchOp = DAG.getZExtOrTrunc(Sub, getCurDebugLoc(), TLI.getPointerTy());
1672 unsigned JumpTableReg = FuncInfo.CreateReg(TLI.getPointerTy());
1673 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), getCurDebugLoc(),
1674 JumpTableReg, SwitchOp);
1675 JT.Reg = JumpTableReg;
1677 // Emit the range check for the jump table, and branch to the default block
1678 // for the switch statement if the value being switched on exceeds the largest
1679 // case in the switch.
1680 SDValue CMP = DAG.getSetCC(getCurDebugLoc(),
1681 TLI.getSetCCResultType(Sub.getValueType()), Sub,
1682 DAG.getConstant(JTH.Last-JTH.First,VT),
1685 // Set NextBlock to be the MBB immediately after the current one, if any.
1686 // This is used to avoid emitting unnecessary branches to the next block.
1687 MachineBasicBlock *NextBlock = 0;
1688 MachineFunction::iterator BBI = SwitchBB;
1690 if (++BBI != FuncInfo.MF->end())
1693 SDValue BrCond = DAG.getNode(ISD::BRCOND, getCurDebugLoc(),
1694 MVT::Other, CopyTo, CMP,
1695 DAG.getBasicBlock(JT.Default));
1697 if (JT.MBB != NextBlock)
1698 BrCond = DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, BrCond,
1699 DAG.getBasicBlock(JT.MBB));
1701 DAG.setRoot(BrCond);
1704 /// visitBitTestHeader - This function emits necessary code to produce value
1705 /// suitable for "bit tests"
1706 void SelectionDAGBuilder::visitBitTestHeader(BitTestBlock &B,
1707 MachineBasicBlock *SwitchBB) {
1708 // Subtract the minimum value
1709 SDValue SwitchOp = getValue(B.SValue);
1710 EVT VT = SwitchOp.getValueType();
1711 SDValue Sub = DAG.getNode(ISD::SUB, getCurDebugLoc(), VT, SwitchOp,
1712 DAG.getConstant(B.First, VT));
1715 SDValue RangeCmp = DAG.getSetCC(getCurDebugLoc(),
1716 TLI.getSetCCResultType(Sub.getValueType()),
1717 Sub, DAG.getConstant(B.Range, VT),
1720 // Determine the type of the test operands.
1721 bool UsePtrType = false;
1722 if (!TLI.isTypeLegal(VT))
1725 for (unsigned i = 0, e = B.Cases.size(); i != e; ++i)
1726 if (!isUIntN(VT.getSizeInBits(), B.Cases[i].Mask)) {
1727 // Switch table case range are encoded into series of masks.
1728 // Just use pointer type, it's guaranteed to fit.
1734 VT = TLI.getPointerTy();
1735 Sub = DAG.getZExtOrTrunc(Sub, getCurDebugLoc(), VT);
1739 B.Reg = FuncInfo.CreateReg(VT);
1740 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), getCurDebugLoc(),
1743 // Set NextBlock to be the MBB immediately after the current one, if any.
1744 // This is used to avoid emitting unnecessary branches to the next block.
1745 MachineBasicBlock *NextBlock = 0;
1746 MachineFunction::iterator BBI = SwitchBB;
1747 if (++BBI != FuncInfo.MF->end())
1750 MachineBasicBlock* MBB = B.Cases[0].ThisBB;
1752 addSuccessorWithWeight(SwitchBB, B.Default);
1753 addSuccessorWithWeight(SwitchBB, MBB);
1755 SDValue BrRange = DAG.getNode(ISD::BRCOND, getCurDebugLoc(),
1756 MVT::Other, CopyTo, RangeCmp,
1757 DAG.getBasicBlock(B.Default));
1759 if (MBB != NextBlock)
1760 BrRange = DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, CopyTo,
1761 DAG.getBasicBlock(MBB));
1763 DAG.setRoot(BrRange);
1766 /// visitBitTestCase - this function produces one "bit test"
1767 void SelectionDAGBuilder::visitBitTestCase(BitTestBlock &BB,
1768 MachineBasicBlock* NextMBB,
1771 MachineBasicBlock *SwitchBB) {
1773 SDValue ShiftOp = DAG.getCopyFromReg(getControlRoot(), getCurDebugLoc(),
1776 unsigned PopCount = CountPopulation_64(B.Mask);
1777 if (PopCount == 1) {
1778 // Testing for a single bit; just compare the shift count with what it
1779 // would need to be to shift a 1 bit in that position.
1780 Cmp = DAG.getSetCC(getCurDebugLoc(),
1781 TLI.getSetCCResultType(VT),
1783 DAG.getConstant(CountTrailingZeros_64(B.Mask), VT),
1785 } else if (PopCount == BB.Range) {
1786 // There is only one zero bit in the range, test for it directly.
1787 Cmp = DAG.getSetCC(getCurDebugLoc(),
1788 TLI.getSetCCResultType(VT),
1790 DAG.getConstant(CountTrailingOnes_64(B.Mask), VT),
1793 // Make desired shift
1794 SDValue SwitchVal = DAG.getNode(ISD::SHL, getCurDebugLoc(), VT,
1795 DAG.getConstant(1, VT), ShiftOp);
1797 // Emit bit tests and jumps
1798 SDValue AndOp = DAG.getNode(ISD::AND, getCurDebugLoc(),
1799 VT, SwitchVal, DAG.getConstant(B.Mask, VT));
1800 Cmp = DAG.getSetCC(getCurDebugLoc(),
1801 TLI.getSetCCResultType(VT),
1802 AndOp, DAG.getConstant(0, VT),
1806 addSuccessorWithWeight(SwitchBB, B.TargetBB);
1807 addSuccessorWithWeight(SwitchBB, NextMBB);
1809 SDValue BrAnd = DAG.getNode(ISD::BRCOND, getCurDebugLoc(),
1810 MVT::Other, getControlRoot(),
1811 Cmp, DAG.getBasicBlock(B.TargetBB));
1813 // Set NextBlock to be the MBB immediately after the current one, if any.
1814 // This is used to avoid emitting unnecessary branches to the next block.
1815 MachineBasicBlock *NextBlock = 0;
1816 MachineFunction::iterator BBI = SwitchBB;
1817 if (++BBI != FuncInfo.MF->end())
1820 if (NextMBB != NextBlock)
1821 BrAnd = DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, BrAnd,
1822 DAG.getBasicBlock(NextMBB));
1827 void SelectionDAGBuilder::visitInvoke(const InvokeInst &I) {
1828 MachineBasicBlock *InvokeMBB = FuncInfo.MBB;
1830 // Retrieve successors.
1831 MachineBasicBlock *Return = FuncInfo.MBBMap[I.getSuccessor(0)];
1832 MachineBasicBlock *LandingPad = FuncInfo.MBBMap[I.getSuccessor(1)];
1834 const Value *Callee(I.getCalledValue());
1835 const Function *Fn = dyn_cast<Function>(Callee);
1836 if (isa<InlineAsm>(Callee))
1838 else if (Fn && Fn->isIntrinsic()) {
1839 assert(Fn->getIntrinsicID() == Intrinsic::donothing);
1840 // Ignore invokes to @llvm.donothing: jump directly to the next BB.
1842 LowerCallTo(&I, getValue(Callee), false, LandingPad);
1844 // If the value of the invoke is used outside of its defining block, make it
1845 // available as a virtual register.
1846 CopyToExportRegsIfNeeded(&I);
1848 // Update successor info
1849 addSuccessorWithWeight(InvokeMBB, Return);
1850 addSuccessorWithWeight(InvokeMBB, LandingPad);
1852 // Drop into normal successor.
1853 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(),
1854 MVT::Other, getControlRoot(),
1855 DAG.getBasicBlock(Return)));
1858 void SelectionDAGBuilder::visitResume(const ResumeInst &RI) {
1859 llvm_unreachable("SelectionDAGBuilder shouldn't visit resume instructions!");
1862 void SelectionDAGBuilder::visitLandingPad(const LandingPadInst &LP) {
1863 assert(FuncInfo.MBB->isLandingPad() &&
1864 "Call to landingpad not in landing pad!");
1866 MachineBasicBlock *MBB = FuncInfo.MBB;
1867 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
1868 AddLandingPadInfo(LP, MMI, MBB);
1870 // If there aren't registers to copy the values into (e.g., during SjLj
1871 // exceptions), then don't bother to create these DAG nodes.
1872 if (TLI.getExceptionPointerRegister() == 0 &&
1873 TLI.getExceptionSelectorRegister() == 0)
1876 SmallVector<EVT, 2> ValueVTs;
1877 ComputeValueVTs(TLI, LP.getType(), ValueVTs);
1879 // Insert the EXCEPTIONADDR instruction.
1880 assert(FuncInfo.MBB->isLandingPad() &&
1881 "Call to eh.exception not in landing pad!");
1882 SDVTList VTs = DAG.getVTList(TLI.getPointerTy(), MVT::Other);
1884 Ops[0] = DAG.getRoot();
1885 SDValue Op1 = DAG.getNode(ISD::EXCEPTIONADDR, getCurDebugLoc(), VTs, Ops, 1);
1886 SDValue Chain = Op1.getValue(1);
1888 // Insert the EHSELECTION instruction.
1889 VTs = DAG.getVTList(TLI.getPointerTy(), MVT::Other);
1892 SDValue Op2 = DAG.getNode(ISD::EHSELECTION, getCurDebugLoc(), VTs, Ops, 2);
1893 Chain = Op2.getValue(1);
1894 Op2 = DAG.getSExtOrTrunc(Op2, getCurDebugLoc(), MVT::i32);
1898 SDValue Res = DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(),
1899 DAG.getVTList(&ValueVTs[0], ValueVTs.size()),
1902 std::pair<SDValue, SDValue> RetPair = std::make_pair(Res, Chain);
1903 setValue(&LP, RetPair.first);
1904 DAG.setRoot(RetPair.second);
1907 /// handleSmallSwitchCaseRange - Emit a series of specific tests (suitable for
1908 /// small case ranges).
1909 bool SelectionDAGBuilder::handleSmallSwitchRange(CaseRec& CR,
1910 CaseRecVector& WorkList,
1912 MachineBasicBlock *Default,
1913 MachineBasicBlock *SwitchBB) {
1914 // Size is the number of Cases represented by this range.
1915 size_t Size = CR.Range.second - CR.Range.first;
1919 // Get the MachineFunction which holds the current MBB. This is used when
1920 // inserting any additional MBBs necessary to represent the switch.
1921 MachineFunction *CurMF = FuncInfo.MF;
1923 // Figure out which block is immediately after the current one.
1924 MachineBasicBlock *NextBlock = 0;
1925 MachineFunction::iterator BBI = CR.CaseBB;
1927 if (++BBI != FuncInfo.MF->end())
1930 // If any two of the cases has the same destination, and if one value
1931 // is the same as the other, but has one bit unset that the other has set,
1932 // use bit manipulation to do two compares at once. For example:
1933 // "if (X == 6 || X == 4)" -> "if ((X|2) == 6)"
1934 // TODO: This could be extended to merge any 2 cases in switches with 3 cases.
1935 // TODO: Handle cases where CR.CaseBB != SwitchBB.
1936 if (Size == 2 && CR.CaseBB == SwitchBB) {
1937 Case &Small = *CR.Range.first;
1938 Case &Big = *(CR.Range.second-1);
1940 if (Small.Low == Small.High && Big.Low == Big.High && Small.BB == Big.BB) {
1941 const APInt& SmallValue = cast<ConstantInt>(Small.Low)->getValue();
1942 const APInt& BigValue = cast<ConstantInt>(Big.Low)->getValue();
1944 // Check that there is only one bit different.
1945 if (BigValue.countPopulation() == SmallValue.countPopulation() + 1 &&
1946 (SmallValue | BigValue) == BigValue) {
1947 // Isolate the common bit.
1948 APInt CommonBit = BigValue & ~SmallValue;
1949 assert((SmallValue | CommonBit) == BigValue &&
1950 CommonBit.countPopulation() == 1 && "Not a common bit?");
1952 SDValue CondLHS = getValue(SV);
1953 EVT VT = CondLHS.getValueType();
1954 DebugLoc DL = getCurDebugLoc();
1956 SDValue Or = DAG.getNode(ISD::OR, DL, VT, CondLHS,
1957 DAG.getConstant(CommonBit, VT));
1958 SDValue Cond = DAG.getSetCC(DL, MVT::i1,
1959 Or, DAG.getConstant(BigValue, VT),
1962 // Update successor info.
1963 addSuccessorWithWeight(SwitchBB, Small.BB);
1964 addSuccessorWithWeight(SwitchBB, Default);
1966 // Insert the true branch.
1967 SDValue BrCond = DAG.getNode(ISD::BRCOND, DL, MVT::Other,
1968 getControlRoot(), Cond,
1969 DAG.getBasicBlock(Small.BB));
1971 // Insert the false branch.
1972 BrCond = DAG.getNode(ISD::BR, DL, MVT::Other, BrCond,
1973 DAG.getBasicBlock(Default));
1975 DAG.setRoot(BrCond);
1981 // Order cases by weight so the most likely case will be checked first.
1982 BranchProbabilityInfo *BPI = FuncInfo.BPI;
1984 for (CaseItr I = CR.Range.first, IE = CR.Range.second; I != IE; ++I) {
1985 uint32_t IWeight = BPI->getEdgeWeight(SwitchBB->getBasicBlock(),
1986 I->BB->getBasicBlock());
1987 for (CaseItr J = CR.Range.first; J < I; ++J) {
1988 uint32_t JWeight = BPI->getEdgeWeight(SwitchBB->getBasicBlock(),
1989 J->BB->getBasicBlock());
1990 if (IWeight > JWeight)
1995 // Rearrange the case blocks so that the last one falls through if possible.
1996 Case &BackCase = *(CR.Range.second-1);
1998 NextBlock && Default != NextBlock && BackCase.BB != NextBlock) {
1999 // The last case block won't fall through into 'NextBlock' if we emit the
2000 // branches in this order. See if rearranging a case value would help.
2001 // We start at the bottom as it's the case with the least weight.
2002 for (Case *I = &*(CR.Range.second-2), *E = &*CR.Range.first-1; I != E; --I){
2003 if (I->BB == NextBlock) {
2004 std::swap(*I, BackCase);
2010 // Create a CaseBlock record representing a conditional branch to
2011 // the Case's target mbb if the value being switched on SV is equal
2013 MachineBasicBlock *CurBlock = CR.CaseBB;
2014 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++I) {
2015 MachineBasicBlock *FallThrough;
2017 FallThrough = CurMF->CreateMachineBasicBlock(CurBlock->getBasicBlock());
2018 CurMF->insert(BBI, FallThrough);
2020 // Put SV in a virtual register to make it available from the new blocks.
2021 ExportFromCurrentBlock(SV);
2023 // If the last case doesn't match, go to the default block.
2024 FallThrough = Default;
2027 const Value *RHS, *LHS, *MHS;
2029 if (I->High == I->Low) {
2030 // This is just small small case range :) containing exactly 1 case
2032 LHS = SV; RHS = I->High; MHS = NULL;
2034 CC = ISD::SETCC_INVALID;
2035 LHS = I->Low; MHS = SV; RHS = I->High;
2038 uint32_t ExtraWeight = I->ExtraWeight;
2039 CaseBlock CB(CC, LHS, RHS, MHS, /* truebb */ I->BB, /* falsebb */ FallThrough,
2041 /* trueweight */ ExtraWeight / 2, /* falseweight */ ExtraWeight / 2);
2043 // If emitting the first comparison, just call visitSwitchCase to emit the
2044 // code into the current block. Otherwise, push the CaseBlock onto the
2045 // vector to be later processed by SDISel, and insert the node's MBB
2046 // before the next MBB.
2047 if (CurBlock == SwitchBB)
2048 visitSwitchCase(CB, SwitchBB);
2050 SwitchCases.push_back(CB);
2052 CurBlock = FallThrough;
2058 static inline bool areJTsAllowed(const TargetLowering &TLI) {
2059 return TLI.supportJumpTables() &&
2060 (TLI.isOperationLegalOrCustom(ISD::BR_JT, MVT::Other) ||
2061 TLI.isOperationLegalOrCustom(ISD::BRIND, MVT::Other));
2064 static APInt ComputeRange(const APInt &First, const APInt &Last) {
2065 uint32_t BitWidth = std::max(Last.getBitWidth(), First.getBitWidth()) + 1;
2066 APInt LastExt = Last.zext(BitWidth), FirstExt = First.zext(BitWidth);
2067 return (LastExt - FirstExt + 1ULL);
2070 /// handleJTSwitchCase - Emit jumptable for current switch case range
2071 bool SelectionDAGBuilder::handleJTSwitchCase(CaseRec &CR,
2072 CaseRecVector &WorkList,
2074 MachineBasicBlock *Default,
2075 MachineBasicBlock *SwitchBB) {
2076 Case& FrontCase = *CR.Range.first;
2077 Case& BackCase = *(CR.Range.second-1);
2079 const APInt &First = cast<ConstantInt>(FrontCase.Low)->getValue();
2080 const APInt &Last = cast<ConstantInt>(BackCase.High)->getValue();
2082 APInt TSize(First.getBitWidth(), 0);
2083 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++I)
2086 if (!areJTsAllowed(TLI) || TSize.ult(4))
2089 APInt Range = ComputeRange(First, Last);
2090 // The density is TSize / Range. Require at least 40%.
2091 // It should not be possible for IntTSize to saturate for sane code, but make
2092 // sure we handle Range saturation correctly.
2093 uint64_t IntRange = Range.getLimitedValue(UINT64_MAX/10);
2094 uint64_t IntTSize = TSize.getLimitedValue(UINT64_MAX/10);
2095 if (IntTSize * 10 < IntRange * 4)
2098 DEBUG(dbgs() << "Lowering jump table\n"
2099 << "First entry: " << First << ". Last entry: " << Last << '\n'
2100 << "Range: " << Range << ". Size: " << TSize << ".\n\n");
2102 // Get the MachineFunction which holds the current MBB. This is used when
2103 // inserting any additional MBBs necessary to represent the switch.
2104 MachineFunction *CurMF = FuncInfo.MF;
2106 // Figure out which block is immediately after the current one.
2107 MachineFunction::iterator BBI = CR.CaseBB;
2110 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
2112 // Create a new basic block to hold the code for loading the address
2113 // of the jump table, and jumping to it. Update successor information;
2114 // we will either branch to the default case for the switch, or the jump
2116 MachineBasicBlock *JumpTableBB = CurMF->CreateMachineBasicBlock(LLVMBB);
2117 CurMF->insert(BBI, JumpTableBB);
2119 addSuccessorWithWeight(CR.CaseBB, Default);
2120 addSuccessorWithWeight(CR.CaseBB, JumpTableBB);
2122 // Build a vector of destination BBs, corresponding to each target
2123 // of the jump table. If the value of the jump table slot corresponds to
2124 // a case statement, push the case's BB onto the vector, otherwise, push
2126 std::vector<MachineBasicBlock*> DestBBs;
2128 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++TEI) {
2129 const APInt &Low = cast<ConstantInt>(I->Low)->getValue();
2130 const APInt &High = cast<ConstantInt>(I->High)->getValue();
2132 if (Low.ule(TEI) && TEI.ule(High)) {
2133 DestBBs.push_back(I->BB);
2137 DestBBs.push_back(Default);
2141 // Update successor info. Add one edge to each unique successor.
2142 BitVector SuccsHandled(CR.CaseBB->getParent()->getNumBlockIDs());
2143 for (std::vector<MachineBasicBlock*>::iterator I = DestBBs.begin(),
2144 E = DestBBs.end(); I != E; ++I) {
2145 if (!SuccsHandled[(*I)->getNumber()]) {
2146 SuccsHandled[(*I)->getNumber()] = true;
2147 addSuccessorWithWeight(JumpTableBB, *I);
2151 // Create a jump table index for this jump table.
2152 unsigned JTEncoding = TLI.getJumpTableEncoding();
2153 unsigned JTI = CurMF->getOrCreateJumpTableInfo(JTEncoding)
2154 ->createJumpTableIndex(DestBBs);
2156 // Set the jump table information so that we can codegen it as a second
2157 // MachineBasicBlock
2158 JumpTable JT(-1U, JTI, JumpTableBB, Default);
2159 JumpTableHeader JTH(First, Last, SV, CR.CaseBB, (CR.CaseBB == SwitchBB));
2160 if (CR.CaseBB == SwitchBB)
2161 visitJumpTableHeader(JT, JTH, SwitchBB);
2163 JTCases.push_back(JumpTableBlock(JTH, JT));
2167 /// handleBTSplitSwitchCase - emit comparison and split binary search tree into
2169 bool SelectionDAGBuilder::handleBTSplitSwitchCase(CaseRec& CR,
2170 CaseRecVector& WorkList,
2172 MachineBasicBlock *Default,
2173 MachineBasicBlock *SwitchBB) {
2174 // Get the MachineFunction which holds the current MBB. This is used when
2175 // inserting any additional MBBs necessary to represent the switch.
2176 MachineFunction *CurMF = FuncInfo.MF;
2178 // Figure out which block is immediately after the current one.
2179 MachineFunction::iterator BBI = CR.CaseBB;
2182 Case& FrontCase = *CR.Range.first;
2183 Case& BackCase = *(CR.Range.second-1);
2184 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
2186 // Size is the number of Cases represented by this range.
2187 unsigned Size = CR.Range.second - CR.Range.first;
2189 const APInt &First = cast<ConstantInt>(FrontCase.Low)->getValue();
2190 const APInt &Last = cast<ConstantInt>(BackCase.High)->getValue();
2192 CaseItr Pivot = CR.Range.first + Size/2;
2194 // Select optimal pivot, maximizing sum density of LHS and RHS. This will
2195 // (heuristically) allow us to emit JumpTable's later.
2196 APInt TSize(First.getBitWidth(), 0);
2197 for (CaseItr I = CR.Range.first, E = CR.Range.second;
2201 APInt LSize = FrontCase.size();
2202 APInt RSize = TSize-LSize;
2203 DEBUG(dbgs() << "Selecting best pivot: \n"
2204 << "First: " << First << ", Last: " << Last <<'\n'
2205 << "LSize: " << LSize << ", RSize: " << RSize << '\n');
2206 for (CaseItr I = CR.Range.first, J=I+1, E = CR.Range.second;
2208 const APInt &LEnd = cast<ConstantInt>(I->High)->getValue();
2209 const APInt &RBegin = cast<ConstantInt>(J->Low)->getValue();
2210 APInt Range = ComputeRange(LEnd, RBegin);
2211 assert((Range - 2ULL).isNonNegative() &&
2212 "Invalid case distance");
2213 // Use volatile double here to avoid excess precision issues on some hosts,
2214 // e.g. that use 80-bit X87 registers.
2215 volatile double LDensity =
2216 (double)LSize.roundToDouble() /
2217 (LEnd - First + 1ULL).roundToDouble();
2218 volatile double RDensity =
2219 (double)RSize.roundToDouble() /
2220 (Last - RBegin + 1ULL).roundToDouble();
2221 double Metric = Range.logBase2()*(LDensity+RDensity);
2222 // Should always split in some non-trivial place
2223 DEBUG(dbgs() <<"=>Step\n"
2224 << "LEnd: " << LEnd << ", RBegin: " << RBegin << '\n'
2225 << "LDensity: " << LDensity
2226 << ", RDensity: " << RDensity << '\n'
2227 << "Metric: " << Metric << '\n');
2228 if (FMetric < Metric) {
2231 DEBUG(dbgs() << "Current metric set to: " << FMetric << '\n');
2237 if (areJTsAllowed(TLI)) {
2238 // If our case is dense we *really* should handle it earlier!
2239 assert((FMetric > 0) && "Should handle dense range earlier!");
2241 Pivot = CR.Range.first + Size/2;
2244 CaseRange LHSR(CR.Range.first, Pivot);
2245 CaseRange RHSR(Pivot, CR.Range.second);
2246 const Constant *C = Pivot->Low;
2247 MachineBasicBlock *FalseBB = 0, *TrueBB = 0;
2249 // We know that we branch to the LHS if the Value being switched on is
2250 // less than the Pivot value, C. We use this to optimize our binary
2251 // tree a bit, by recognizing that if SV is greater than or equal to the
2252 // LHS's Case Value, and that Case Value is exactly one less than the
2253 // Pivot's Value, then we can branch directly to the LHS's Target,
2254 // rather than creating a leaf node for it.
2255 if ((LHSR.second - LHSR.first) == 1 &&
2256 LHSR.first->High == CR.GE &&
2257 cast<ConstantInt>(C)->getValue() ==
2258 (cast<ConstantInt>(CR.GE)->getValue() + 1LL)) {
2259 TrueBB = LHSR.first->BB;
2261 TrueBB = CurMF->CreateMachineBasicBlock(LLVMBB);
2262 CurMF->insert(BBI, TrueBB);
2263 WorkList.push_back(CaseRec(TrueBB, C, CR.GE, LHSR));
2265 // Put SV in a virtual register to make it available from the new blocks.
2266 ExportFromCurrentBlock(SV);
2269 // Similar to the optimization above, if the Value being switched on is
2270 // known to be less than the Constant CR.LT, and the current Case Value
2271 // is CR.LT - 1, then we can branch directly to the target block for
2272 // the current Case Value, rather than emitting a RHS leaf node for it.
2273 if ((RHSR.second - RHSR.first) == 1 && CR.LT &&
2274 cast<ConstantInt>(RHSR.first->Low)->getValue() ==
2275 (cast<ConstantInt>(CR.LT)->getValue() - 1LL)) {
2276 FalseBB = RHSR.first->BB;
2278 FalseBB = CurMF->CreateMachineBasicBlock(LLVMBB);
2279 CurMF->insert(BBI, FalseBB);
2280 WorkList.push_back(CaseRec(FalseBB,CR.LT,C,RHSR));
2282 // Put SV in a virtual register to make it available from the new blocks.
2283 ExportFromCurrentBlock(SV);
2286 // Create a CaseBlock record representing a conditional branch to
2287 // the LHS node if the value being switched on SV is less than C.
2288 // Otherwise, branch to LHS.
2289 CaseBlock CB(ISD::SETULT, SV, C, NULL, TrueBB, FalseBB, CR.CaseBB);
2291 if (CR.CaseBB == SwitchBB)
2292 visitSwitchCase(CB, SwitchBB);
2294 SwitchCases.push_back(CB);
2299 /// handleBitTestsSwitchCase - if current case range has few destination and
2300 /// range span less, than machine word bitwidth, encode case range into series
2301 /// of masks and emit bit tests with these masks.
2302 bool SelectionDAGBuilder::handleBitTestsSwitchCase(CaseRec& CR,
2303 CaseRecVector& WorkList,
2305 MachineBasicBlock* Default,
2306 MachineBasicBlock *SwitchBB){
2307 EVT PTy = TLI.getPointerTy();
2308 unsigned IntPtrBits = PTy.getSizeInBits();
2310 Case& FrontCase = *CR.Range.first;
2311 Case& BackCase = *(CR.Range.second-1);
2313 // Get the MachineFunction which holds the current MBB. This is used when
2314 // inserting any additional MBBs necessary to represent the switch.
2315 MachineFunction *CurMF = FuncInfo.MF;
2317 // If target does not have legal shift left, do not emit bit tests at all.
2318 if (!TLI.isOperationLegal(ISD::SHL, TLI.getPointerTy()))
2322 for (CaseItr I = CR.Range.first, E = CR.Range.second;
2324 // Single case counts one, case range - two.
2325 numCmps += (I->Low == I->High ? 1 : 2);
2328 // Count unique destinations
2329 SmallSet<MachineBasicBlock*, 4> Dests;
2330 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) {
2331 Dests.insert(I->BB);
2332 if (Dests.size() > 3)
2333 // Don't bother the code below, if there are too much unique destinations
2336 DEBUG(dbgs() << "Total number of unique destinations: "
2337 << Dests.size() << '\n'
2338 << "Total number of comparisons: " << numCmps << '\n');
2340 // Compute span of values.
2341 const APInt& minValue = cast<ConstantInt>(FrontCase.Low)->getValue();
2342 const APInt& maxValue = cast<ConstantInt>(BackCase.High)->getValue();
2343 APInt cmpRange = maxValue - minValue;
2345 DEBUG(dbgs() << "Compare range: " << cmpRange << '\n'
2346 << "Low bound: " << minValue << '\n'
2347 << "High bound: " << maxValue << '\n');
2349 if (cmpRange.uge(IntPtrBits) ||
2350 (!(Dests.size() == 1 && numCmps >= 3) &&
2351 !(Dests.size() == 2 && numCmps >= 5) &&
2352 !(Dests.size() >= 3 && numCmps >= 6)))
2355 DEBUG(dbgs() << "Emitting bit tests\n");
2356 APInt lowBound = APInt::getNullValue(cmpRange.getBitWidth());
2358 // Optimize the case where all the case values fit in a
2359 // word without having to subtract minValue. In this case,
2360 // we can optimize away the subtraction.
2361 if (maxValue.ult(IntPtrBits)) {
2362 cmpRange = maxValue;
2364 lowBound = minValue;
2367 CaseBitsVector CasesBits;
2368 unsigned i, count = 0;
2370 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) {
2371 MachineBasicBlock* Dest = I->BB;
2372 for (i = 0; i < count; ++i)
2373 if (Dest == CasesBits[i].BB)
2377 assert((count < 3) && "Too much destinations to test!");
2378 CasesBits.push_back(CaseBits(0, Dest, 0));
2382 const APInt& lowValue = cast<ConstantInt>(I->Low)->getValue();
2383 const APInt& highValue = cast<ConstantInt>(I->High)->getValue();
2385 uint64_t lo = (lowValue - lowBound).getZExtValue();
2386 uint64_t hi = (highValue - lowBound).getZExtValue();
2388 for (uint64_t j = lo; j <= hi; j++) {
2389 CasesBits[i].Mask |= 1ULL << j;
2390 CasesBits[i].Bits++;
2394 std::sort(CasesBits.begin(), CasesBits.end(), CaseBitsCmp());
2398 // Figure out which block is immediately after the current one.
2399 MachineFunction::iterator BBI = CR.CaseBB;
2402 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
2404 DEBUG(dbgs() << "Cases:\n");
2405 for (unsigned i = 0, e = CasesBits.size(); i!=e; ++i) {
2406 DEBUG(dbgs() << "Mask: " << CasesBits[i].Mask
2407 << ", Bits: " << CasesBits[i].Bits
2408 << ", BB: " << CasesBits[i].BB << '\n');
2410 MachineBasicBlock *CaseBB = CurMF->CreateMachineBasicBlock(LLVMBB);
2411 CurMF->insert(BBI, CaseBB);
2412 BTC.push_back(BitTestCase(CasesBits[i].Mask,
2416 // Put SV in a virtual register to make it available from the new blocks.
2417 ExportFromCurrentBlock(SV);
2420 BitTestBlock BTB(lowBound, cmpRange, SV,
2421 -1U, MVT::Other, (CR.CaseBB == SwitchBB),
2422 CR.CaseBB, Default, BTC);
2424 if (CR.CaseBB == SwitchBB)
2425 visitBitTestHeader(BTB, SwitchBB);
2427 BitTestCases.push_back(BTB);
2432 /// Clusterify - Transform simple list of Cases into list of CaseRange's
2433 size_t SelectionDAGBuilder::Clusterify(CaseVector& Cases,
2434 const SwitchInst& SI) {
2436 /// Use a shorter form of declaration, and also
2437 /// show the we want to use CRSBuilder as Clusterifier.
2438 typedef IntegersSubsetMapping<MachineBasicBlock> Clusterifier;
2440 Clusterifier TheClusterifier;
2442 // Start with "simple" cases
2443 for (SwitchInst::ConstCaseIt i = SI.case_begin(), e = SI.case_end();
2445 const BasicBlock *SuccBB = i.getCaseSuccessor();
2446 MachineBasicBlock *SMBB = FuncInfo.MBBMap[SuccBB];
2448 TheClusterifier.add(i.getCaseValueEx(), SMBB);
2451 TheClusterifier.optimize();
2453 BranchProbabilityInfo *BPI = FuncInfo.BPI;
2455 for (Clusterifier::RangeIterator i = TheClusterifier.begin(),
2456 e = TheClusterifier.end(); i != e; ++i, ++numCmps) {
2457 Clusterifier::Cluster &C = *i;
2460 W = BPI->getEdgeWeight(SI.getParent(), C.second->getBasicBlock());
2463 W *= C.first.Weight;
2464 BPI->setEdgeWeight(SI.getParent(), C.second->getBasicBlock(), W);
2467 // FIXME: Currently work with ConstantInt based numbers.
2468 // Changing it to APInt based is a pretty heavy for this commit.
2469 Cases.push_back(Case(C.first.getLow().toConstantInt(),
2470 C.first.getHigh().toConstantInt(), C.second, W));
2472 if (C.first.getLow() != C.first.getHigh())
2473 // A range counts double, since it requires two compares.
2480 void SelectionDAGBuilder::UpdateSplitBlock(MachineBasicBlock *First,
2481 MachineBasicBlock *Last) {
2483 for (unsigned i = 0, e = JTCases.size(); i != e; ++i)
2484 if (JTCases[i].first.HeaderBB == First)
2485 JTCases[i].first.HeaderBB = Last;
2487 // Update BitTestCases.
2488 for (unsigned i = 0, e = BitTestCases.size(); i != e; ++i)
2489 if (BitTestCases[i].Parent == First)
2490 BitTestCases[i].Parent = Last;
2493 void SelectionDAGBuilder::visitSwitch(const SwitchInst &SI) {
2494 MachineBasicBlock *SwitchMBB = FuncInfo.MBB;
2496 // Figure out which block is immediately after the current one.
2497 MachineBasicBlock *NextBlock = 0;
2498 MachineBasicBlock *Default = FuncInfo.MBBMap[SI.getDefaultDest()];
2500 // If there is only the default destination, branch to it if it is not the
2501 // next basic block. Otherwise, just fall through.
2502 if (!SI.getNumCases()) {
2503 // Update machine-CFG edges.
2505 // If this is not a fall-through branch, emit the branch.
2506 SwitchMBB->addSuccessor(Default);
2507 if (Default != NextBlock)
2508 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(),
2509 MVT::Other, getControlRoot(),
2510 DAG.getBasicBlock(Default)));
2515 // If there are any non-default case statements, create a vector of Cases
2516 // representing each one, and sort the vector so that we can efficiently
2517 // create a binary search tree from them.
2519 size_t numCmps = Clusterify(Cases, SI);
2520 DEBUG(dbgs() << "Clusterify finished. Total clusters: " << Cases.size()
2521 << ". Total compares: " << numCmps << '\n');
2524 // Get the Value to be switched on and default basic blocks, which will be
2525 // inserted into CaseBlock records, representing basic blocks in the binary
2527 const Value *SV = SI.getCondition();
2529 // Push the initial CaseRec onto the worklist
2530 CaseRecVector WorkList;
2531 WorkList.push_back(CaseRec(SwitchMBB,0,0,
2532 CaseRange(Cases.begin(),Cases.end())));
2534 while (!WorkList.empty()) {
2535 // Grab a record representing a case range to process off the worklist
2536 CaseRec CR = WorkList.back();
2537 WorkList.pop_back();
2539 if (handleBitTestsSwitchCase(CR, WorkList, SV, Default, SwitchMBB))
2542 // If the range has few cases (two or less) emit a series of specific
2544 if (handleSmallSwitchRange(CR, WorkList, SV, Default, SwitchMBB))
2547 // If the switch has more than 5 blocks, and at least 40% dense, and the
2548 // target supports indirect branches, then emit a jump table rather than
2549 // lowering the switch to a binary tree of conditional branches.
2550 if (handleJTSwitchCase(CR, WorkList, SV, Default, SwitchMBB))
2553 // Emit binary tree. We need to pick a pivot, and push left and right ranges
2554 // onto the worklist. Leafs are handled via handleSmallSwitchRange() call.
2555 handleBTSplitSwitchCase(CR, WorkList, SV, Default, SwitchMBB);
2559 void SelectionDAGBuilder::visitIndirectBr(const IndirectBrInst &I) {
2560 MachineBasicBlock *IndirectBrMBB = FuncInfo.MBB;
2562 // Update machine-CFG edges with unique successors.
2563 SmallVector<BasicBlock*, 32> succs;
2564 succs.reserve(I.getNumSuccessors());
2565 for (unsigned i = 0, e = I.getNumSuccessors(); i != e; ++i)
2566 succs.push_back(I.getSuccessor(i));
2567 array_pod_sort(succs.begin(), succs.end());
2568 succs.erase(std::unique(succs.begin(), succs.end()), succs.end());
2569 for (unsigned i = 0, e = succs.size(); i != e; ++i) {
2570 MachineBasicBlock *Succ = FuncInfo.MBBMap[succs[i]];
2571 addSuccessorWithWeight(IndirectBrMBB, Succ);
2574 DAG.setRoot(DAG.getNode(ISD::BRIND, getCurDebugLoc(),
2575 MVT::Other, getControlRoot(),
2576 getValue(I.getAddress())));
2579 void SelectionDAGBuilder::visitFSub(const User &I) {
2580 // -0.0 - X --> fneg
2581 Type *Ty = I.getType();
2582 if (isa<Constant>(I.getOperand(0)) &&
2583 I.getOperand(0) == ConstantFP::getZeroValueForNegation(Ty)) {
2584 SDValue Op2 = getValue(I.getOperand(1));
2585 setValue(&I, DAG.getNode(ISD::FNEG, getCurDebugLoc(),
2586 Op2.getValueType(), Op2));
2590 visitBinary(I, ISD::FSUB);
2593 void SelectionDAGBuilder::visitBinary(const User &I, unsigned OpCode) {
2594 SDValue Op1 = getValue(I.getOperand(0));
2595 SDValue Op2 = getValue(I.getOperand(1));
2596 setValue(&I, DAG.getNode(OpCode, getCurDebugLoc(),
2597 Op1.getValueType(), Op1, Op2));
2600 void SelectionDAGBuilder::visitShift(const User &I, unsigned Opcode) {
2601 SDValue Op1 = getValue(I.getOperand(0));
2602 SDValue Op2 = getValue(I.getOperand(1));
2604 MVT ShiftTy = TLI.getShiftAmountTy(Op2.getValueType());
2606 // Coerce the shift amount to the right type if we can.
2607 if (!I.getType()->isVectorTy() && Op2.getValueType() != ShiftTy) {
2608 unsigned ShiftSize = ShiftTy.getSizeInBits();
2609 unsigned Op2Size = Op2.getValueType().getSizeInBits();
2610 DebugLoc DL = getCurDebugLoc();
2612 // If the operand is smaller than the shift count type, promote it.
2613 if (ShiftSize > Op2Size)
2614 Op2 = DAG.getNode(ISD::ZERO_EXTEND, DL, ShiftTy, Op2);
2616 // If the operand is larger than the shift count type but the shift
2617 // count type has enough bits to represent any shift value, truncate
2618 // it now. This is a common case and it exposes the truncate to
2619 // optimization early.
2620 else if (ShiftSize >= Log2_32_Ceil(Op2.getValueType().getSizeInBits()))
2621 Op2 = DAG.getNode(ISD::TRUNCATE, DL, ShiftTy, Op2);
2622 // Otherwise we'll need to temporarily settle for some other convenient
2623 // type. Type legalization will make adjustments once the shiftee is split.
2625 Op2 = DAG.getZExtOrTrunc(Op2, DL, MVT::i32);
2628 setValue(&I, DAG.getNode(Opcode, getCurDebugLoc(),
2629 Op1.getValueType(), Op1, Op2));
2632 void SelectionDAGBuilder::visitSDiv(const User &I) {
2633 SDValue Op1 = getValue(I.getOperand(0));
2634 SDValue Op2 = getValue(I.getOperand(1));
2636 // Turn exact SDivs into multiplications.
2637 // FIXME: This should be in DAGCombiner, but it doesn't have access to the
2639 if (isa<BinaryOperator>(&I) && cast<BinaryOperator>(&I)->isExact() &&
2640 !isa<ConstantSDNode>(Op1) &&
2641 isa<ConstantSDNode>(Op2) && !cast<ConstantSDNode>(Op2)->isNullValue())
2642 setValue(&I, TLI.BuildExactSDIV(Op1, Op2, getCurDebugLoc(), DAG));
2644 setValue(&I, DAG.getNode(ISD::SDIV, getCurDebugLoc(), Op1.getValueType(),
2648 void SelectionDAGBuilder::visitICmp(const User &I) {
2649 ICmpInst::Predicate predicate = ICmpInst::BAD_ICMP_PREDICATE;
2650 if (const ICmpInst *IC = dyn_cast<ICmpInst>(&I))
2651 predicate = IC->getPredicate();
2652 else if (const ConstantExpr *IC = dyn_cast<ConstantExpr>(&I))
2653 predicate = ICmpInst::Predicate(IC->getPredicate());
2654 SDValue Op1 = getValue(I.getOperand(0));
2655 SDValue Op2 = getValue(I.getOperand(1));
2656 ISD::CondCode Opcode = getICmpCondCode(predicate);
2658 EVT DestVT = TLI.getValueType(I.getType());
2659 setValue(&I, DAG.getSetCC(getCurDebugLoc(), DestVT, Op1, Op2, Opcode));
2662 void SelectionDAGBuilder::visitFCmp(const User &I) {
2663 FCmpInst::Predicate predicate = FCmpInst::BAD_FCMP_PREDICATE;
2664 if (const FCmpInst *FC = dyn_cast<FCmpInst>(&I))
2665 predicate = FC->getPredicate();
2666 else if (const ConstantExpr *FC = dyn_cast<ConstantExpr>(&I))
2667 predicate = FCmpInst::Predicate(FC->getPredicate());
2668 SDValue Op1 = getValue(I.getOperand(0));
2669 SDValue Op2 = getValue(I.getOperand(1));
2670 ISD::CondCode Condition = getFCmpCondCode(predicate);
2671 if (TM.Options.NoNaNsFPMath)
2672 Condition = getFCmpCodeWithoutNaN(Condition);
2673 EVT DestVT = TLI.getValueType(I.getType());
2674 setValue(&I, DAG.getSetCC(getCurDebugLoc(), DestVT, Op1, Op2, Condition));
2677 void SelectionDAGBuilder::visitSelect(const User &I) {
2678 SmallVector<EVT, 4> ValueVTs;
2679 ComputeValueVTs(TLI, I.getType(), ValueVTs);
2680 unsigned NumValues = ValueVTs.size();
2681 if (NumValues == 0) return;
2683 SmallVector<SDValue, 4> Values(NumValues);
2684 SDValue Cond = getValue(I.getOperand(0));
2685 SDValue TrueVal = getValue(I.getOperand(1));
2686 SDValue FalseVal = getValue(I.getOperand(2));
2687 ISD::NodeType OpCode = Cond.getValueType().isVector() ?
2688 ISD::VSELECT : ISD::SELECT;
2690 for (unsigned i = 0; i != NumValues; ++i)
2691 Values[i] = DAG.getNode(OpCode, getCurDebugLoc(),
2692 TrueVal.getNode()->getValueType(TrueVal.getResNo()+i),
2694 SDValue(TrueVal.getNode(),
2695 TrueVal.getResNo() + i),
2696 SDValue(FalseVal.getNode(),
2697 FalseVal.getResNo() + i));
2699 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(),
2700 DAG.getVTList(&ValueVTs[0], NumValues),
2701 &Values[0], NumValues));
2704 void SelectionDAGBuilder::visitTrunc(const User &I) {
2705 // TruncInst cannot be a no-op cast because sizeof(src) > sizeof(dest).
2706 SDValue N = getValue(I.getOperand(0));
2707 EVT DestVT = TLI.getValueType(I.getType());
2708 setValue(&I, DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), DestVT, N));
2711 void SelectionDAGBuilder::visitZExt(const User &I) {
2712 // ZExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
2713 // ZExt also can't be a cast to bool for same reason. So, nothing much to do
2714 SDValue N = getValue(I.getOperand(0));
2715 EVT DestVT = TLI.getValueType(I.getType());
2716 setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(), DestVT, N));
2719 void SelectionDAGBuilder::visitSExt(const User &I) {
2720 // SExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
2721 // SExt also can't be a cast to bool for same reason. So, nothing much to do
2722 SDValue N = getValue(I.getOperand(0));
2723 EVT DestVT = TLI.getValueType(I.getType());
2724 setValue(&I, DAG.getNode(ISD::SIGN_EXTEND, getCurDebugLoc(), DestVT, N));
2727 void SelectionDAGBuilder::visitFPTrunc(const User &I) {
2728 // FPTrunc is never a no-op cast, no need to check
2729 SDValue N = getValue(I.getOperand(0));
2730 EVT DestVT = TLI.getValueType(I.getType());
2731 setValue(&I, DAG.getNode(ISD::FP_ROUND, getCurDebugLoc(),
2733 DAG.getTargetConstant(0, TLI.getPointerTy())));
2736 void SelectionDAGBuilder::visitFPExt(const User &I){
2737 // FPExt is never a no-op cast, no need to check
2738 SDValue N = getValue(I.getOperand(0));
2739 EVT DestVT = TLI.getValueType(I.getType());
2740 setValue(&I, DAG.getNode(ISD::FP_EXTEND, getCurDebugLoc(), DestVT, N));
2743 void SelectionDAGBuilder::visitFPToUI(const User &I) {
2744 // FPToUI is never a no-op cast, no need to check
2745 SDValue N = getValue(I.getOperand(0));
2746 EVT DestVT = TLI.getValueType(I.getType());
2747 setValue(&I, DAG.getNode(ISD::FP_TO_UINT, getCurDebugLoc(), DestVT, N));
2750 void SelectionDAGBuilder::visitFPToSI(const User &I) {
2751 // FPToSI is never a no-op cast, no need to check
2752 SDValue N = getValue(I.getOperand(0));
2753 EVT DestVT = TLI.getValueType(I.getType());
2754 setValue(&I, DAG.getNode(ISD::FP_TO_SINT, getCurDebugLoc(), DestVT, N));
2757 void SelectionDAGBuilder::visitUIToFP(const User &I) {
2758 // UIToFP is never a no-op cast, no need to check
2759 SDValue N = getValue(I.getOperand(0));
2760 EVT DestVT = TLI.getValueType(I.getType());
2761 setValue(&I, DAG.getNode(ISD::UINT_TO_FP, getCurDebugLoc(), DestVT, N));
2764 void SelectionDAGBuilder::visitSIToFP(const User &I){
2765 // SIToFP is never a no-op cast, no need to check
2766 SDValue N = getValue(I.getOperand(0));
2767 EVT DestVT = TLI.getValueType(I.getType());
2768 setValue(&I, DAG.getNode(ISD::SINT_TO_FP, getCurDebugLoc(), DestVT, N));
2771 void SelectionDAGBuilder::visitPtrToInt(const User &I) {
2772 // What to do depends on the size of the integer and the size of the pointer.
2773 // We can either truncate, zero extend, or no-op, accordingly.
2774 SDValue N = getValue(I.getOperand(0));
2775 EVT DestVT = TLI.getValueType(I.getType());
2776 setValue(&I, DAG.getZExtOrTrunc(N, getCurDebugLoc(), DestVT));
2779 void SelectionDAGBuilder::visitIntToPtr(const User &I) {
2780 // What to do depends on the size of the integer and the size of the pointer.
2781 // We can either truncate, zero extend, or no-op, accordingly.
2782 SDValue N = getValue(I.getOperand(0));
2783 EVT DestVT = TLI.getValueType(I.getType());
2784 setValue(&I, DAG.getZExtOrTrunc(N, getCurDebugLoc(), DestVT));
2787 void SelectionDAGBuilder::visitBitCast(const User &I) {
2788 SDValue N = getValue(I.getOperand(0));
2789 EVT DestVT = TLI.getValueType(I.getType());
2791 // BitCast assures us that source and destination are the same size so this is
2792 // either a BITCAST or a no-op.
2793 if (DestVT != N.getValueType())
2794 setValue(&I, DAG.getNode(ISD::BITCAST, getCurDebugLoc(),
2795 DestVT, N)); // convert types.
2797 setValue(&I, N); // noop cast.
2800 void SelectionDAGBuilder::visitInsertElement(const User &I) {
2801 SDValue InVec = getValue(I.getOperand(0));
2802 SDValue InVal = getValue(I.getOperand(1));
2803 SDValue InIdx = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(),
2805 getValue(I.getOperand(2)));
2806 setValue(&I, DAG.getNode(ISD::INSERT_VECTOR_ELT, getCurDebugLoc(),
2807 TLI.getValueType(I.getType()),
2808 InVec, InVal, InIdx));
2811 void SelectionDAGBuilder::visitExtractElement(const User &I) {
2812 SDValue InVec = getValue(I.getOperand(0));
2813 SDValue InIdx = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(),
2815 getValue(I.getOperand(1)));
2816 setValue(&I, DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurDebugLoc(),
2817 TLI.getValueType(I.getType()), InVec, InIdx));
2820 // Utility for visitShuffleVector - Return true if every element in Mask,
2821 // beginning from position Pos and ending in Pos+Size, falls within the
2822 // specified sequential range [L, L+Pos). or is undef.
2823 static bool isSequentialInRange(const SmallVectorImpl<int> &Mask,
2824 unsigned Pos, unsigned Size, int Low) {
2825 for (unsigned i = Pos, e = Pos+Size; i != e; ++i, ++Low)
2826 if (Mask[i] >= 0 && Mask[i] != Low)
2831 void SelectionDAGBuilder::visitShuffleVector(const User &I) {
2832 SDValue Src1 = getValue(I.getOperand(0));
2833 SDValue Src2 = getValue(I.getOperand(1));
2835 SmallVector<int, 8> Mask;
2836 ShuffleVectorInst::getShuffleMask(cast<Constant>(I.getOperand(2)), Mask);
2837 unsigned MaskNumElts = Mask.size();
2839 EVT VT = TLI.getValueType(I.getType());
2840 EVT SrcVT = Src1.getValueType();
2841 unsigned SrcNumElts = SrcVT.getVectorNumElements();
2843 if (SrcNumElts == MaskNumElts) {
2844 setValue(&I, DAG.getVectorShuffle(VT, getCurDebugLoc(), Src1, Src2,
2849 // Normalize the shuffle vector since mask and vector length don't match.
2850 if (SrcNumElts < MaskNumElts && MaskNumElts % SrcNumElts == 0) {
2851 // Mask is longer than the source vectors and is a multiple of the source
2852 // vectors. We can use concatenate vector to make the mask and vectors
2854 if (SrcNumElts*2 == MaskNumElts) {
2855 // First check for Src1 in low and Src2 in high
2856 if (isSequentialInRange(Mask, 0, SrcNumElts, 0) &&
2857 isSequentialInRange(Mask, SrcNumElts, SrcNumElts, SrcNumElts)) {
2858 // The shuffle is concatenating two vectors together.
2859 setValue(&I, DAG.getNode(ISD::CONCAT_VECTORS, getCurDebugLoc(),
2863 // Then check for Src2 in low and Src1 in high
2864 if (isSequentialInRange(Mask, 0, SrcNumElts, SrcNumElts) &&
2865 isSequentialInRange(Mask, SrcNumElts, SrcNumElts, 0)) {
2866 // The shuffle is concatenating two vectors together.
2867 setValue(&I, DAG.getNode(ISD::CONCAT_VECTORS, getCurDebugLoc(),
2873 // Pad both vectors with undefs to make them the same length as the mask.
2874 unsigned NumConcat = MaskNumElts / SrcNumElts;
2875 bool Src1U = Src1.getOpcode() == ISD::UNDEF;
2876 bool Src2U = Src2.getOpcode() == ISD::UNDEF;
2877 SDValue UndefVal = DAG.getUNDEF(SrcVT);
2879 SmallVector<SDValue, 8> MOps1(NumConcat, UndefVal);
2880 SmallVector<SDValue, 8> MOps2(NumConcat, UndefVal);
2884 Src1 = Src1U ? DAG.getUNDEF(VT) : DAG.getNode(ISD::CONCAT_VECTORS,
2885 getCurDebugLoc(), VT,
2886 &MOps1[0], NumConcat);
2887 Src2 = Src2U ? DAG.getUNDEF(VT) : DAG.getNode(ISD::CONCAT_VECTORS,
2888 getCurDebugLoc(), VT,
2889 &MOps2[0], NumConcat);
2891 // Readjust mask for new input vector length.
2892 SmallVector<int, 8> MappedOps;
2893 for (unsigned i = 0; i != MaskNumElts; ++i) {
2895 if (Idx >= (int)SrcNumElts)
2896 Idx -= SrcNumElts - MaskNumElts;
2897 MappedOps.push_back(Idx);
2900 setValue(&I, DAG.getVectorShuffle(VT, getCurDebugLoc(), Src1, Src2,
2905 if (SrcNumElts > MaskNumElts) {
2906 // Analyze the access pattern of the vector to see if we can extract
2907 // two subvectors and do the shuffle. The analysis is done by calculating
2908 // the range of elements the mask access on both vectors.
2909 int MinRange[2] = { static_cast<int>(SrcNumElts),
2910 static_cast<int>(SrcNumElts)};
2911 int MaxRange[2] = {-1, -1};
2913 for (unsigned i = 0; i != MaskNumElts; ++i) {
2919 if (Idx >= (int)SrcNumElts) {
2923 if (Idx > MaxRange[Input])
2924 MaxRange[Input] = Idx;
2925 if (Idx < MinRange[Input])
2926 MinRange[Input] = Idx;
2929 // Check if the access is smaller than the vector size and can we find
2930 // a reasonable extract index.
2931 int RangeUse[2] = { -1, -1 }; // 0 = Unused, 1 = Extract, -1 = Can not
2933 int StartIdx[2]; // StartIdx to extract from
2934 for (unsigned Input = 0; Input < 2; ++Input) {
2935 if (MinRange[Input] >= (int)SrcNumElts && MaxRange[Input] < 0) {
2936 RangeUse[Input] = 0; // Unused
2937 StartIdx[Input] = 0;
2941 // Find a good start index that is a multiple of the mask length. Then
2942 // see if the rest of the elements are in range.
2943 StartIdx[Input] = (MinRange[Input]/MaskNumElts)*MaskNumElts;
2944 if (MaxRange[Input] - StartIdx[Input] < (int)MaskNumElts &&
2945 StartIdx[Input] + MaskNumElts <= SrcNumElts)
2946 RangeUse[Input] = 1; // Extract from a multiple of the mask length.
2949 if (RangeUse[0] == 0 && RangeUse[1] == 0) {
2950 setValue(&I, DAG.getUNDEF(VT)); // Vectors are not used.
2953 if (RangeUse[0] >= 0 && RangeUse[1] >= 0) {
2954 // Extract appropriate subvector and generate a vector shuffle
2955 for (unsigned Input = 0; Input < 2; ++Input) {
2956 SDValue &Src = Input == 0 ? Src1 : Src2;
2957 if (RangeUse[Input] == 0)
2958 Src = DAG.getUNDEF(VT);
2960 Src = DAG.getNode(ISD::EXTRACT_SUBVECTOR, getCurDebugLoc(), VT,
2961 Src, DAG.getIntPtrConstant(StartIdx[Input]));
2964 // Calculate new mask.
2965 SmallVector<int, 8> MappedOps;
2966 for (unsigned i = 0; i != MaskNumElts; ++i) {
2969 if (Idx < (int)SrcNumElts)
2972 Idx -= SrcNumElts + StartIdx[1] - MaskNumElts;
2974 MappedOps.push_back(Idx);
2977 setValue(&I, DAG.getVectorShuffle(VT, getCurDebugLoc(), Src1, Src2,
2983 // We can't use either concat vectors or extract subvectors so fall back to
2984 // replacing the shuffle with extract and build vector.
2985 // to insert and build vector.
2986 EVT EltVT = VT.getVectorElementType();
2987 EVT PtrVT = TLI.getPointerTy();
2988 SmallVector<SDValue,8> Ops;
2989 for (unsigned i = 0; i != MaskNumElts; ++i) {
2994 Res = DAG.getUNDEF(EltVT);
2996 SDValue &Src = Idx < (int)SrcNumElts ? Src1 : Src2;
2997 if (Idx >= (int)SrcNumElts) Idx -= SrcNumElts;
2999 Res = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurDebugLoc(),
3000 EltVT, Src, DAG.getConstant(Idx, PtrVT));
3006 setValue(&I, DAG.getNode(ISD::BUILD_VECTOR, getCurDebugLoc(),
3007 VT, &Ops[0], Ops.size()));
3010 void SelectionDAGBuilder::visitInsertValue(const InsertValueInst &I) {
3011 const Value *Op0 = I.getOperand(0);
3012 const Value *Op1 = I.getOperand(1);
3013 Type *AggTy = I.getType();
3014 Type *ValTy = Op1->getType();
3015 bool IntoUndef = isa<UndefValue>(Op0);
3016 bool FromUndef = isa<UndefValue>(Op1);
3018 unsigned LinearIndex = ComputeLinearIndex(AggTy, I.getIndices());
3020 SmallVector<EVT, 4> AggValueVTs;
3021 ComputeValueVTs(TLI, AggTy, AggValueVTs);
3022 SmallVector<EVT, 4> ValValueVTs;
3023 ComputeValueVTs(TLI, ValTy, ValValueVTs);
3025 unsigned NumAggValues = AggValueVTs.size();
3026 unsigned NumValValues = ValValueVTs.size();
3027 SmallVector<SDValue, 4> Values(NumAggValues);
3029 SDValue Agg = getValue(Op0);
3031 // Copy the beginning value(s) from the original aggregate.
3032 for (; i != LinearIndex; ++i)
3033 Values[i] = IntoUndef ? DAG.getUNDEF(AggValueVTs[i]) :
3034 SDValue(Agg.getNode(), Agg.getResNo() + i);
3035 // Copy values from the inserted value(s).
3037 SDValue Val = getValue(Op1);
3038 for (; i != LinearIndex + NumValValues; ++i)
3039 Values[i] = FromUndef ? DAG.getUNDEF(AggValueVTs[i]) :
3040 SDValue(Val.getNode(), Val.getResNo() + i - LinearIndex);
3042 // Copy remaining value(s) from the original aggregate.
3043 for (; i != NumAggValues; ++i)
3044 Values[i] = IntoUndef ? DAG.getUNDEF(AggValueVTs[i]) :
3045 SDValue(Agg.getNode(), Agg.getResNo() + i);
3047 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(),
3048 DAG.getVTList(&AggValueVTs[0], NumAggValues),
3049 &Values[0], NumAggValues));
3052 void SelectionDAGBuilder::visitExtractValue(const ExtractValueInst &I) {
3053 const Value *Op0 = I.getOperand(0);
3054 Type *AggTy = Op0->getType();
3055 Type *ValTy = I.getType();
3056 bool OutOfUndef = isa<UndefValue>(Op0);
3058 unsigned LinearIndex = ComputeLinearIndex(AggTy, I.getIndices());
3060 SmallVector<EVT, 4> ValValueVTs;
3061 ComputeValueVTs(TLI, ValTy, ValValueVTs);
3063 unsigned NumValValues = ValValueVTs.size();
3065 // Ignore a extractvalue that produces an empty object
3066 if (!NumValValues) {
3067 setValue(&I, DAG.getUNDEF(MVT(MVT::Other)));
3071 SmallVector<SDValue, 4> Values(NumValValues);
3073 SDValue Agg = getValue(Op0);
3074 // Copy out the selected value(s).
3075 for (unsigned i = LinearIndex; i != LinearIndex + NumValValues; ++i)
3076 Values[i - LinearIndex] =
3078 DAG.getUNDEF(Agg.getNode()->getValueType(Agg.getResNo() + i)) :
3079 SDValue(Agg.getNode(), Agg.getResNo() + i);
3081 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(),
3082 DAG.getVTList(&ValValueVTs[0], NumValValues),
3083 &Values[0], NumValValues));
3086 void SelectionDAGBuilder::visitGetElementPtr(const User &I) {
3087 SDValue N = getValue(I.getOperand(0));
3088 // Note that the pointer operand may be a vector of pointers. Take the scalar
3089 // element which holds a pointer.
3090 Type *Ty = I.getOperand(0)->getType()->getScalarType();
3092 for (GetElementPtrInst::const_op_iterator OI = I.op_begin()+1, E = I.op_end();
3094 const Value *Idx = *OI;
3095 if (StructType *StTy = dyn_cast<StructType>(Ty)) {
3096 unsigned Field = cast<ConstantInt>(Idx)->getZExtValue();
3099 uint64_t Offset = TD->getStructLayout(StTy)->getElementOffset(Field);
3100 N = DAG.getNode(ISD::ADD, getCurDebugLoc(), N.getValueType(), N,
3101 DAG.getIntPtrConstant(Offset));
3104 Ty = StTy->getElementType(Field);
3106 Ty = cast<SequentialType>(Ty)->getElementType();
3108 // If this is a constant subscript, handle it quickly.
3109 if (const ConstantInt *CI = dyn_cast<ConstantInt>(Idx)) {
3110 if (CI->isZero()) continue;
3112 TD->getTypeAllocSize(Ty)*cast<ConstantInt>(CI)->getSExtValue();
3114 EVT PTy = TLI.getPointerTy();
3115 unsigned PtrBits = PTy.getSizeInBits();
3117 OffsVal = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(),
3119 DAG.getConstant(Offs, MVT::i64));
3121 OffsVal = DAG.getIntPtrConstant(Offs);
3123 N = DAG.getNode(ISD::ADD, getCurDebugLoc(), N.getValueType(), N,
3128 // N = N + Idx * ElementSize;
3129 APInt ElementSize = APInt(TLI.getPointerTy().getSizeInBits(),
3130 TD->getTypeAllocSize(Ty));
3131 SDValue IdxN = getValue(Idx);
3133 // If the index is smaller or larger than intptr_t, truncate or extend
3135 IdxN = DAG.getSExtOrTrunc(IdxN, getCurDebugLoc(), N.getValueType());
3137 // If this is a multiply by a power of two, turn it into a shl
3138 // immediately. This is a very common case.
3139 if (ElementSize != 1) {
3140 if (ElementSize.isPowerOf2()) {
3141 unsigned Amt = ElementSize.logBase2();
3142 IdxN = DAG.getNode(ISD::SHL, getCurDebugLoc(),
3143 N.getValueType(), IdxN,
3144 DAG.getConstant(Amt, IdxN.getValueType()));
3146 SDValue Scale = DAG.getConstant(ElementSize, TLI.getPointerTy());
3147 IdxN = DAG.getNode(ISD::MUL, getCurDebugLoc(),
3148 N.getValueType(), IdxN, Scale);
3152 N = DAG.getNode(ISD::ADD, getCurDebugLoc(),
3153 N.getValueType(), N, IdxN);
3160 void SelectionDAGBuilder::visitAlloca(const AllocaInst &I) {
3161 // If this is a fixed sized alloca in the entry block of the function,
3162 // allocate it statically on the stack.
3163 if (FuncInfo.StaticAllocaMap.count(&I))
3164 return; // getValue will auto-populate this.
3166 Type *Ty = I.getAllocatedType();
3167 uint64_t TySize = TLI.getTargetData()->getTypeAllocSize(Ty);
3169 std::max((unsigned)TLI.getTargetData()->getPrefTypeAlignment(Ty),
3172 SDValue AllocSize = getValue(I.getArraySize());
3174 EVT IntPtr = TLI.getPointerTy();
3175 if (AllocSize.getValueType() != IntPtr)
3176 AllocSize = DAG.getZExtOrTrunc(AllocSize, getCurDebugLoc(), IntPtr);
3178 AllocSize = DAG.getNode(ISD::MUL, getCurDebugLoc(), IntPtr,
3180 DAG.getConstant(TySize, IntPtr));
3182 // Handle alignment. If the requested alignment is less than or equal to
3183 // the stack alignment, ignore it. If the size is greater than or equal to
3184 // the stack alignment, we note this in the DYNAMIC_STACKALLOC node.
3185 unsigned StackAlign = TM.getFrameLowering()->getStackAlignment();
3186 if (Align <= StackAlign)
3189 // Round the size of the allocation up to the stack alignment size
3190 // by add SA-1 to the size.
3191 AllocSize = DAG.getNode(ISD::ADD, getCurDebugLoc(),
3192 AllocSize.getValueType(), AllocSize,
3193 DAG.getIntPtrConstant(StackAlign-1));
3195 // Mask out the low bits for alignment purposes.
3196 AllocSize = DAG.getNode(ISD::AND, getCurDebugLoc(),
3197 AllocSize.getValueType(), AllocSize,
3198 DAG.getIntPtrConstant(~(uint64_t)(StackAlign-1)));
3200 SDValue Ops[] = { getRoot(), AllocSize, DAG.getIntPtrConstant(Align) };
3201 SDVTList VTs = DAG.getVTList(AllocSize.getValueType(), MVT::Other);
3202 SDValue DSA = DAG.getNode(ISD::DYNAMIC_STACKALLOC, getCurDebugLoc(),
3205 DAG.setRoot(DSA.getValue(1));
3207 // Inform the Frame Information that we have just allocated a variable-sized
3209 FuncInfo.MF->getFrameInfo()->CreateVariableSizedObject(Align ? Align : 1);
3212 void SelectionDAGBuilder::visitLoad(const LoadInst &I) {
3214 return visitAtomicLoad(I);
3216 const Value *SV = I.getOperand(0);
3217 SDValue Ptr = getValue(SV);
3219 Type *Ty = I.getType();
3221 bool isVolatile = I.isVolatile();
3222 bool isNonTemporal = I.getMetadata("nontemporal") != 0;
3223 bool isInvariant = I.getMetadata("invariant.load") != 0;
3224 unsigned Alignment = I.getAlignment();
3225 const MDNode *TBAAInfo = I.getMetadata(LLVMContext::MD_tbaa);
3226 const MDNode *Ranges = I.getMetadata(LLVMContext::MD_range);
3228 SmallVector<EVT, 4> ValueVTs;
3229 SmallVector<uint64_t, 4> Offsets;
3230 ComputeValueVTs(TLI, Ty, ValueVTs, &Offsets);
3231 unsigned NumValues = ValueVTs.size();
3236 bool ConstantMemory = false;
3237 if (I.isVolatile() || NumValues > MaxParallelChains)
3238 // Serialize volatile loads with other side effects.
3240 else if (AA->pointsToConstantMemory(
3241 AliasAnalysis::Location(SV, AA->getTypeStoreSize(Ty), TBAAInfo))) {
3242 // Do not serialize (non-volatile) loads of constant memory with anything.
3243 Root = DAG.getEntryNode();
3244 ConstantMemory = true;
3246 // Do not serialize non-volatile loads against each other.
3247 Root = DAG.getRoot();
3250 SmallVector<SDValue, 4> Values(NumValues);
3251 SmallVector<SDValue, 4> Chains(std::min(unsigned(MaxParallelChains),
3253 EVT PtrVT = Ptr.getValueType();
3254 unsigned ChainI = 0;
3255 for (unsigned i = 0; i != NumValues; ++i, ++ChainI) {
3256 // Serializing loads here may result in excessive register pressure, and
3257 // TokenFactor places arbitrary choke points on the scheduler. SD scheduling
3258 // could recover a bit by hoisting nodes upward in the chain by recognizing
3259 // they are side-effect free or do not alias. The optimizer should really
3260 // avoid this case by converting large object/array copies to llvm.memcpy
3261 // (MaxParallelChains should always remain as failsafe).
3262 if (ChainI == MaxParallelChains) {
3263 assert(PendingLoads.empty() && "PendingLoads must be serialized first");
3264 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(),
3265 MVT::Other, &Chains[0], ChainI);
3269 SDValue A = DAG.getNode(ISD::ADD, getCurDebugLoc(),
3271 DAG.getConstant(Offsets[i], PtrVT));
3272 SDValue L = DAG.getLoad(ValueVTs[i], getCurDebugLoc(), Root,
3273 A, MachinePointerInfo(SV, Offsets[i]), isVolatile,
3274 isNonTemporal, isInvariant, Alignment, TBAAInfo,
3278 Chains[ChainI] = L.getValue(1);
3281 if (!ConstantMemory) {
3282 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(),
3283 MVT::Other, &Chains[0], ChainI);
3287 PendingLoads.push_back(Chain);
3290 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(),
3291 DAG.getVTList(&ValueVTs[0], NumValues),
3292 &Values[0], NumValues));
3295 void SelectionDAGBuilder::visitStore(const StoreInst &I) {
3297 return visitAtomicStore(I);
3299 const Value *SrcV = I.getOperand(0);
3300 const Value *PtrV = I.getOperand(1);
3302 SmallVector<EVT, 4> ValueVTs;
3303 SmallVector<uint64_t, 4> Offsets;
3304 ComputeValueVTs(TLI, SrcV->getType(), ValueVTs, &Offsets);
3305 unsigned NumValues = ValueVTs.size();
3309 // Get the lowered operands. Note that we do this after
3310 // checking if NumResults is zero, because with zero results
3311 // the operands won't have values in the map.
3312 SDValue Src = getValue(SrcV);
3313 SDValue Ptr = getValue(PtrV);
3315 SDValue Root = getRoot();
3316 SmallVector<SDValue, 4> Chains(std::min(unsigned(MaxParallelChains),
3318 EVT PtrVT = Ptr.getValueType();
3319 bool isVolatile = I.isVolatile();
3320 bool isNonTemporal = I.getMetadata("nontemporal") != 0;
3321 unsigned Alignment = I.getAlignment();
3322 const MDNode *TBAAInfo = I.getMetadata(LLVMContext::MD_tbaa);
3324 unsigned ChainI = 0;
3325 for (unsigned i = 0; i != NumValues; ++i, ++ChainI) {
3326 // See visitLoad comments.
3327 if (ChainI == MaxParallelChains) {
3328 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(),
3329 MVT::Other, &Chains[0], ChainI);
3333 SDValue Add = DAG.getNode(ISD::ADD, getCurDebugLoc(), PtrVT, Ptr,
3334 DAG.getConstant(Offsets[i], PtrVT));
3335 SDValue St = DAG.getStore(Root, getCurDebugLoc(),
3336 SDValue(Src.getNode(), Src.getResNo() + i),
3337 Add, MachinePointerInfo(PtrV, Offsets[i]),
3338 isVolatile, isNonTemporal, Alignment, TBAAInfo);
3339 Chains[ChainI] = St;
3342 SDValue StoreNode = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(),
3343 MVT::Other, &Chains[0], ChainI);
3345 AssignOrderingToNode(StoreNode.getNode());
3346 DAG.setRoot(StoreNode);
3349 static SDValue InsertFenceForAtomic(SDValue Chain, AtomicOrdering Order,
3350 SynchronizationScope Scope,
3351 bool Before, DebugLoc dl,
3353 const TargetLowering &TLI) {
3354 // Fence, if necessary
3356 if (Order == AcquireRelease || Order == SequentiallyConsistent)
3358 else if (Order == Acquire || Order == Monotonic)
3361 if (Order == AcquireRelease)
3363 else if (Order == Release || Order == Monotonic)
3368 Ops[1] = DAG.getConstant(Order, TLI.getPointerTy());
3369 Ops[2] = DAG.getConstant(Scope, TLI.getPointerTy());
3370 return DAG.getNode(ISD::ATOMIC_FENCE, dl, MVT::Other, Ops, 3);
3373 void SelectionDAGBuilder::visitAtomicCmpXchg(const AtomicCmpXchgInst &I) {
3374 DebugLoc dl = getCurDebugLoc();
3375 AtomicOrdering Order = I.getOrdering();
3376 SynchronizationScope Scope = I.getSynchScope();
3378 SDValue InChain = getRoot();
3380 if (TLI.getInsertFencesForAtomic())
3381 InChain = InsertFenceForAtomic(InChain, Order, Scope, true, dl,
3385 DAG.getAtomic(ISD::ATOMIC_CMP_SWAP, dl,
3386 getValue(I.getCompareOperand()).getValueType().getSimpleVT(),
3388 getValue(I.getPointerOperand()),
3389 getValue(I.getCompareOperand()),
3390 getValue(I.getNewValOperand()),
3391 MachinePointerInfo(I.getPointerOperand()), 0 /* Alignment */,
3392 TLI.getInsertFencesForAtomic() ? Monotonic : Order,
3395 SDValue OutChain = L.getValue(1);
3397 if (TLI.getInsertFencesForAtomic())
3398 OutChain = InsertFenceForAtomic(OutChain, Order, Scope, false, dl,
3402 DAG.setRoot(OutChain);
3405 void SelectionDAGBuilder::visitAtomicRMW(const AtomicRMWInst &I) {
3406 DebugLoc dl = getCurDebugLoc();
3408 switch (I.getOperation()) {
3409 default: llvm_unreachable("Unknown atomicrmw operation");
3410 case AtomicRMWInst::Xchg: NT = ISD::ATOMIC_SWAP; break;
3411 case AtomicRMWInst::Add: NT = ISD::ATOMIC_LOAD_ADD; break;
3412 case AtomicRMWInst::Sub: NT = ISD::ATOMIC_LOAD_SUB; break;
3413 case AtomicRMWInst::And: NT = ISD::ATOMIC_LOAD_AND; break;
3414 case AtomicRMWInst::Nand: NT = ISD::ATOMIC_LOAD_NAND; break;
3415 case AtomicRMWInst::Or: NT = ISD::ATOMIC_LOAD_OR; break;
3416 case AtomicRMWInst::Xor: NT = ISD::ATOMIC_LOAD_XOR; break;
3417 case AtomicRMWInst::Max: NT = ISD::ATOMIC_LOAD_MAX; break;
3418 case AtomicRMWInst::Min: NT = ISD::ATOMIC_LOAD_MIN; break;
3419 case AtomicRMWInst::UMax: NT = ISD::ATOMIC_LOAD_UMAX; break;
3420 case AtomicRMWInst::UMin: NT = ISD::ATOMIC_LOAD_UMIN; break;
3422 AtomicOrdering Order = I.getOrdering();
3423 SynchronizationScope Scope = I.getSynchScope();
3425 SDValue InChain = getRoot();
3427 if (TLI.getInsertFencesForAtomic())
3428 InChain = InsertFenceForAtomic(InChain, Order, Scope, true, dl,
3432 DAG.getAtomic(NT, dl,
3433 getValue(I.getValOperand()).getValueType().getSimpleVT(),
3435 getValue(I.getPointerOperand()),
3436 getValue(I.getValOperand()),
3437 I.getPointerOperand(), 0 /* Alignment */,
3438 TLI.getInsertFencesForAtomic() ? Monotonic : Order,
3441 SDValue OutChain = L.getValue(1);
3443 if (TLI.getInsertFencesForAtomic())
3444 OutChain = InsertFenceForAtomic(OutChain, Order, Scope, false, dl,
3448 DAG.setRoot(OutChain);
3451 void SelectionDAGBuilder::visitFence(const FenceInst &I) {
3452 DebugLoc dl = getCurDebugLoc();
3455 Ops[1] = DAG.getConstant(I.getOrdering(), TLI.getPointerTy());
3456 Ops[2] = DAG.getConstant(I.getSynchScope(), TLI.getPointerTy());
3457 DAG.setRoot(DAG.getNode(ISD::ATOMIC_FENCE, dl, MVT::Other, Ops, 3));
3460 void SelectionDAGBuilder::visitAtomicLoad(const LoadInst &I) {
3461 DebugLoc dl = getCurDebugLoc();
3462 AtomicOrdering Order = I.getOrdering();
3463 SynchronizationScope Scope = I.getSynchScope();
3465 SDValue InChain = getRoot();
3467 EVT VT = TLI.getValueType(I.getType());
3469 if (I.getAlignment() * 8 < VT.getSizeInBits())
3470 report_fatal_error("Cannot generate unaligned atomic load");
3473 DAG.getAtomic(ISD::ATOMIC_LOAD, dl, VT, VT, InChain,
3474 getValue(I.getPointerOperand()),
3475 I.getPointerOperand(), I.getAlignment(),
3476 TLI.getInsertFencesForAtomic() ? Monotonic : Order,
3479 SDValue OutChain = L.getValue(1);
3481 if (TLI.getInsertFencesForAtomic())
3482 OutChain = InsertFenceForAtomic(OutChain, Order, Scope, false, dl,
3486 DAG.setRoot(OutChain);
3489 void SelectionDAGBuilder::visitAtomicStore(const StoreInst &I) {
3490 DebugLoc dl = getCurDebugLoc();
3492 AtomicOrdering Order = I.getOrdering();
3493 SynchronizationScope Scope = I.getSynchScope();
3495 SDValue InChain = getRoot();
3497 EVT VT = TLI.getValueType(I.getValueOperand()->getType());
3499 if (I.getAlignment() * 8 < VT.getSizeInBits())
3500 report_fatal_error("Cannot generate unaligned atomic store");
3502 if (TLI.getInsertFencesForAtomic())
3503 InChain = InsertFenceForAtomic(InChain, Order, Scope, true, dl,
3507 DAG.getAtomic(ISD::ATOMIC_STORE, dl, VT,
3509 getValue(I.getPointerOperand()),
3510 getValue(I.getValueOperand()),
3511 I.getPointerOperand(), I.getAlignment(),
3512 TLI.getInsertFencesForAtomic() ? Monotonic : Order,
3515 if (TLI.getInsertFencesForAtomic())
3516 OutChain = InsertFenceForAtomic(OutChain, Order, Scope, false, dl,
3519 DAG.setRoot(OutChain);
3522 /// visitTargetIntrinsic - Lower a call of a target intrinsic to an INTRINSIC
3524 void SelectionDAGBuilder::visitTargetIntrinsic(const CallInst &I,
3525 unsigned Intrinsic) {
3526 bool HasChain = !I.doesNotAccessMemory();
3527 bool OnlyLoad = HasChain && I.onlyReadsMemory();
3529 // Build the operand list.
3530 SmallVector<SDValue, 8> Ops;
3531 if (HasChain) { // If this intrinsic has side-effects, chainify it.
3533 // We don't need to serialize loads against other loads.
3534 Ops.push_back(DAG.getRoot());
3536 Ops.push_back(getRoot());
3540 // Info is set by getTgtMemInstrinsic
3541 TargetLowering::IntrinsicInfo Info;
3542 bool IsTgtIntrinsic = TLI.getTgtMemIntrinsic(Info, I, Intrinsic);
3544 // Add the intrinsic ID as an integer operand if it's not a target intrinsic.
3545 if (!IsTgtIntrinsic || Info.opc == ISD::INTRINSIC_VOID ||
3546 Info.opc == ISD::INTRINSIC_W_CHAIN)
3547 Ops.push_back(DAG.getTargetConstant(Intrinsic, TLI.getPointerTy()));
3549 // Add all operands of the call to the operand list.
3550 for (unsigned i = 0, e = I.getNumArgOperands(); i != e; ++i) {
3551 SDValue Op = getValue(I.getArgOperand(i));
3555 SmallVector<EVT, 4> ValueVTs;
3556 ComputeValueVTs(TLI, I.getType(), ValueVTs);
3559 ValueVTs.push_back(MVT::Other);
3561 SDVTList VTs = DAG.getVTList(ValueVTs.data(), ValueVTs.size());
3565 if (IsTgtIntrinsic) {
3566 // This is target intrinsic that touches memory
3567 Result = DAG.getMemIntrinsicNode(Info.opc, getCurDebugLoc(),
3568 VTs, &Ops[0], Ops.size(),
3570 MachinePointerInfo(Info.ptrVal, Info.offset),
3571 Info.align, Info.vol,
3572 Info.readMem, Info.writeMem);
3573 } else if (!HasChain) {
3574 Result = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, getCurDebugLoc(),
3575 VTs, &Ops[0], Ops.size());
3576 } else if (!I.getType()->isVoidTy()) {
3577 Result = DAG.getNode(ISD::INTRINSIC_W_CHAIN, getCurDebugLoc(),
3578 VTs, &Ops[0], Ops.size());
3580 Result = DAG.getNode(ISD::INTRINSIC_VOID, getCurDebugLoc(),
3581 VTs, &Ops[0], Ops.size());
3585 SDValue Chain = Result.getValue(Result.getNode()->getNumValues()-1);
3587 PendingLoads.push_back(Chain);
3592 if (!I.getType()->isVoidTy()) {
3593 if (VectorType *PTy = dyn_cast<VectorType>(I.getType())) {
3594 EVT VT = TLI.getValueType(PTy);
3595 Result = DAG.getNode(ISD::BITCAST, getCurDebugLoc(), VT, Result);
3598 setValue(&I, Result);
3600 // Assign order to result here. If the intrinsic does not produce a result,
3601 // it won't be mapped to a SDNode and visit() will not assign it an order
3604 AssignOrderingToNode(Result.getNode());
3608 /// GetSignificand - Get the significand and build it into a floating-point
3609 /// number with exponent of 1:
3611 /// Op = (Op & 0x007fffff) | 0x3f800000;
3613 /// where Op is the hexidecimal representation of floating point value.
3615 GetSignificand(SelectionDAG &DAG, SDValue Op, DebugLoc dl) {
3616 SDValue t1 = DAG.getNode(ISD::AND, dl, MVT::i32, Op,
3617 DAG.getConstant(0x007fffff, MVT::i32));
3618 SDValue t2 = DAG.getNode(ISD::OR, dl, MVT::i32, t1,
3619 DAG.getConstant(0x3f800000, MVT::i32));
3620 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, t2);
3623 /// GetExponent - Get the exponent:
3625 /// (float)(int)(((Op & 0x7f800000) >> 23) - 127);
3627 /// where Op is the hexidecimal representation of floating point value.
3629 GetExponent(SelectionDAG &DAG, SDValue Op, const TargetLowering &TLI,
3631 SDValue t0 = DAG.getNode(ISD::AND, dl, MVT::i32, Op,
3632 DAG.getConstant(0x7f800000, MVT::i32));
3633 SDValue t1 = DAG.getNode(ISD::SRL, dl, MVT::i32, t0,
3634 DAG.getConstant(23, TLI.getPointerTy()));
3635 SDValue t2 = DAG.getNode(ISD::SUB, dl, MVT::i32, t1,
3636 DAG.getConstant(127, MVT::i32));
3637 return DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, t2);
3640 /// getF32Constant - Get 32-bit floating point constant.
3642 getF32Constant(SelectionDAG &DAG, unsigned Flt) {
3643 return DAG.getConstantFP(APFloat(APInt(32, Flt)), MVT::f32);
3646 /// visitExp - Lower an exp intrinsic. Handles the special sequences for
3647 /// limited-precision mode.
3649 SelectionDAGBuilder::visitExp(const CallInst &I) {
3651 DebugLoc dl = getCurDebugLoc();
3653 if (getValue(I.getArgOperand(0)).getValueType() == MVT::f32 &&
3654 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3655 SDValue Op = getValue(I.getArgOperand(0));
3657 // Put the exponent in the right bit position for later addition to the
3660 // #define LOG2OFe 1.4426950f
3661 // IntegerPartOfX = ((int32_t)(X * LOG2OFe));
3662 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, Op,
3663 getF32Constant(DAG, 0x3fb8aa3b));
3664 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, t0);
3666 // FractionalPartOfX = (X * LOG2OFe) - (float)IntegerPartOfX;
3667 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX);
3668 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, t1);
3670 // IntegerPartOfX <<= 23;
3671 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX,
3672 DAG.getConstant(23, TLI.getPointerTy()));
3674 if (LimitFloatPrecision <= 6) {
3675 // For floating-point precision of 6:
3677 // TwoToFractionalPartOfX =
3679 // (0.735607626f + 0.252464424f * x) * x;
3681 // error 0.0144103317, which is 6 bits
3682 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3683 getF32Constant(DAG, 0x3e814304));
3684 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3685 getF32Constant(DAG, 0x3f3c50c8));
3686 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3687 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3688 getF32Constant(DAG, 0x3f7f5e7e));
3689 SDValue TwoToFracPartOfX = DAG.getNode(ISD::BITCAST, dl,MVT::i32, t5);
3691 // Add the exponent into the result in integer domain.
3692 SDValue t6 = DAG.getNode(ISD::ADD, dl, MVT::i32,
3693 TwoToFracPartOfX, IntegerPartOfX);
3695 result = DAG.getNode(ISD::BITCAST, dl, MVT::f32, t6);
3696 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
3697 // For floating-point precision of 12:
3699 // TwoToFractionalPartOfX =
3702 // (0.224338339f + 0.792043434e-1f * x) * x) * x;
3704 // 0.000107046256 error, which is 13 to 14 bits
3705 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3706 getF32Constant(DAG, 0x3da235e3));
3707 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3708 getF32Constant(DAG, 0x3e65b8f3));
3709 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3710 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3711 getF32Constant(DAG, 0x3f324b07));
3712 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3713 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3714 getF32Constant(DAG, 0x3f7ff8fd));
3715 SDValue TwoToFracPartOfX = DAG.getNode(ISD::BITCAST, dl,MVT::i32, t7);
3717 // Add the exponent into the result in integer domain.
3718 SDValue t8 = DAG.getNode(ISD::ADD, dl, MVT::i32,
3719 TwoToFracPartOfX, IntegerPartOfX);
3721 result = DAG.getNode(ISD::BITCAST, dl, MVT::f32, t8);
3722 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
3723 // For floating-point precision of 18:
3725 // TwoToFractionalPartOfX =
3729 // (0.554906021e-1f +
3730 // (0.961591928e-2f +
3731 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x;
3733 // error 2.47208000*10^(-7), which is better than 18 bits
3734 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3735 getF32Constant(DAG, 0x3924b03e));
3736 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3737 getF32Constant(DAG, 0x3ab24b87));
3738 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3739 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3740 getF32Constant(DAG, 0x3c1d8c17));
3741 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3742 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3743 getF32Constant(DAG, 0x3d634a1d));
3744 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3745 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3746 getF32Constant(DAG, 0x3e75fe14));
3747 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3748 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10,
3749 getF32Constant(DAG, 0x3f317234));
3750 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X);
3751 SDValue t13 = DAG.getNode(ISD::FADD, dl, MVT::f32, t12,
3752 getF32Constant(DAG, 0x3f800000));
3753 SDValue TwoToFracPartOfX = DAG.getNode(ISD::BITCAST, dl,
3756 // Add the exponent into the result in integer domain.
3757 SDValue t14 = DAG.getNode(ISD::ADD, dl, MVT::i32,
3758 TwoToFracPartOfX, IntegerPartOfX);
3760 result = DAG.getNode(ISD::BITCAST, dl, MVT::f32, t14);
3763 // No special expansion.
3764 result = DAG.getNode(ISD::FEXP, dl,
3765 getValue(I.getArgOperand(0)).getValueType(),
3766 getValue(I.getArgOperand(0)));
3769 setValue(&I, result);
3772 /// visitLog - Lower a log intrinsic. Handles the special sequences for
3773 /// limited-precision mode.
3775 SelectionDAGBuilder::visitLog(const CallInst &I) {
3777 DebugLoc dl = getCurDebugLoc();
3779 if (getValue(I.getArgOperand(0)).getValueType() == MVT::f32 &&
3780 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3781 SDValue Op = getValue(I.getArgOperand(0));
3782 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op);
3784 // Scale the exponent by log(2) [0.69314718f].
3785 SDValue Exp = GetExponent(DAG, Op1, TLI, dl);
3786 SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp,
3787 getF32Constant(DAG, 0x3f317218));
3789 // Get the significand and build it into a floating-point number with
3791 SDValue X = GetSignificand(DAG, Op1, dl);
3793 if (LimitFloatPrecision <= 6) {
3794 // For floating-point precision of 6:
3798 // (1.4034025f - 0.23903021f * x) * x;
3800 // error 0.0034276066, which is better than 8 bits
3801 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3802 getF32Constant(DAG, 0xbe74c456));
3803 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3804 getF32Constant(DAG, 0x3fb3a2b1));
3805 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3806 SDValue LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3807 getF32Constant(DAG, 0x3f949a29));
3809 result = DAG.getNode(ISD::FADD, dl,
3810 MVT::f32, LogOfExponent, LogOfMantissa);
3811 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
3812 // For floating-point precision of 12:
3818 // (0.44717955f - 0.56570851e-1f * x) * x) * x) * x;
3820 // error 0.000061011436, which is 14 bits
3821 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3822 getF32Constant(DAG, 0xbd67b6d6));
3823 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3824 getF32Constant(DAG, 0x3ee4f4b8));
3825 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3826 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3827 getF32Constant(DAG, 0x3fbc278b));
3828 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3829 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3830 getF32Constant(DAG, 0x40348e95));
3831 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3832 SDValue LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3833 getF32Constant(DAG, 0x3fdef31a));
3835 result = DAG.getNode(ISD::FADD, dl,
3836 MVT::f32, LogOfExponent, LogOfMantissa);
3837 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
3838 // For floating-point precision of 18:
3846 // (0.19073739f - 0.17809712e-1f * x) * x) * x) * x) * x)*x;
3848 // error 0.0000023660568, which is better than 18 bits
3849 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3850 getF32Constant(DAG, 0xbc91e5ac));
3851 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3852 getF32Constant(DAG, 0x3e4350aa));
3853 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3854 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3855 getF32Constant(DAG, 0x3f60d3e3));
3856 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3857 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3858 getF32Constant(DAG, 0x4011cdf0));
3859 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3860 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3861 getF32Constant(DAG, 0x406cfd1c));
3862 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3863 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3864 getF32Constant(DAG, 0x408797cb));
3865 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3866 SDValue LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10,
3867 getF32Constant(DAG, 0x4006dcab));
3869 result = DAG.getNode(ISD::FADD, dl,
3870 MVT::f32, LogOfExponent, LogOfMantissa);
3873 // No special expansion.
3874 result = DAG.getNode(ISD::FLOG, dl,
3875 getValue(I.getArgOperand(0)).getValueType(),
3876 getValue(I.getArgOperand(0)));
3879 setValue(&I, result);
3882 /// visitLog2 - Lower a log2 intrinsic. Handles the special sequences for
3883 /// limited-precision mode.
3885 SelectionDAGBuilder::visitLog2(const CallInst &I) {
3887 DebugLoc dl = getCurDebugLoc();
3889 if (getValue(I.getArgOperand(0)).getValueType() == MVT::f32 &&
3890 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3891 SDValue Op = getValue(I.getArgOperand(0));
3892 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op);
3894 // Get the exponent.
3895 SDValue LogOfExponent = GetExponent(DAG, Op1, TLI, dl);
3897 // Get the significand and build it into a floating-point number with
3899 SDValue X = GetSignificand(DAG, Op1, dl);
3901 // Different possible minimax approximations of significand in
3902 // floating-point for various degrees of accuracy over [1,2].
3903 if (LimitFloatPrecision <= 6) {
3904 // For floating-point precision of 6:
3906 // Log2ofMantissa = -1.6749035f + (2.0246817f - .34484768f * x) * x;
3908 // error 0.0049451742, which is more than 7 bits
3909 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3910 getF32Constant(DAG, 0xbeb08fe0));
3911 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3912 getF32Constant(DAG, 0x40019463));
3913 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3914 SDValue Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3915 getF32Constant(DAG, 0x3fd6633d));
3917 result = DAG.getNode(ISD::FADD, dl,
3918 MVT::f32, LogOfExponent, Log2ofMantissa);
3919 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
3920 // For floating-point precision of 12:
3926 // (.645142248f - 0.816157886e-1f * x) * x) * x) * x;
3928 // error 0.0000876136000, which is better than 13 bits
3929 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3930 getF32Constant(DAG, 0xbda7262e));
3931 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3932 getF32Constant(DAG, 0x3f25280b));
3933 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3934 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3935 getF32Constant(DAG, 0x4007b923));
3936 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3937 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3938 getF32Constant(DAG, 0x40823e2f));
3939 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3940 SDValue Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3941 getF32Constant(DAG, 0x4020d29c));
3943 result = DAG.getNode(ISD::FADD, dl,
3944 MVT::f32, LogOfExponent, Log2ofMantissa);
3945 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
3946 // For floating-point precision of 18:
3955 // 0.25691327e-1f * x) * x) * x) * x) * x) * x;
3957 // error 0.0000018516, which is better than 18 bits
3958 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3959 getF32Constant(DAG, 0xbcd2769e));
3960 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3961 getF32Constant(DAG, 0x3e8ce0b9));
3962 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3963 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3964 getF32Constant(DAG, 0x3fa22ae7));
3965 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3966 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3967 getF32Constant(DAG, 0x40525723));
3968 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3969 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3970 getF32Constant(DAG, 0x40aaf200));
3971 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3972 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3973 getF32Constant(DAG, 0x40c39dad));
3974 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3975 SDValue Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10,
3976 getF32Constant(DAG, 0x4042902c));
3978 result = DAG.getNode(ISD::FADD, dl,
3979 MVT::f32, LogOfExponent, Log2ofMantissa);
3982 // No special expansion.
3983 result = DAG.getNode(ISD::FLOG2, dl,
3984 getValue(I.getArgOperand(0)).getValueType(),
3985 getValue(I.getArgOperand(0)));
3988 setValue(&I, result);
3991 /// visitLog10 - Lower a log10 intrinsic. Handles the special sequences for
3992 /// limited-precision mode.
3994 SelectionDAGBuilder::visitLog10(const CallInst &I) {
3996 DebugLoc dl = getCurDebugLoc();
3998 if (getValue(I.getArgOperand(0)).getValueType() == MVT::f32 &&
3999 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
4000 SDValue Op = getValue(I.getArgOperand(0));
4001 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op);
4003 // Scale the exponent by log10(2) [0.30102999f].
4004 SDValue Exp = GetExponent(DAG, Op1, TLI, dl);
4005 SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp,
4006 getF32Constant(DAG, 0x3e9a209a));
4008 // Get the significand and build it into a floating-point number with
4010 SDValue X = GetSignificand(DAG, Op1, dl);
4012 if (LimitFloatPrecision <= 6) {
4013 // For floating-point precision of 6:
4015 // Log10ofMantissa =
4017 // (0.60948995f - 0.10380950f * x) * x;
4019 // error 0.0014886165, which is 6 bits
4020 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4021 getF32Constant(DAG, 0xbdd49a13));
4022 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
4023 getF32Constant(DAG, 0x3f1c0789));
4024 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
4025 SDValue Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
4026 getF32Constant(DAG, 0x3f011300));
4028 result = DAG.getNode(ISD::FADD, dl,
4029 MVT::f32, LogOfExponent, Log10ofMantissa);
4030 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
4031 // For floating-point precision of 12:
4033 // Log10ofMantissa =
4036 // (-0.31664806f + 0.47637168e-1f * x) * x) * x;
4038 // error 0.00019228036, which is better than 12 bits
4039 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4040 getF32Constant(DAG, 0x3d431f31));
4041 SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0,
4042 getF32Constant(DAG, 0x3ea21fb2));
4043 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
4044 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4045 getF32Constant(DAG, 0x3f6ae232));
4046 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4047 SDValue Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4,
4048 getF32Constant(DAG, 0x3f25f7c3));
4050 result = DAG.getNode(ISD::FADD, dl,
4051 MVT::f32, LogOfExponent, Log10ofMantissa);
4052 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
4053 // For floating-point precision of 18:
4055 // Log10ofMantissa =
4060 // (-0.12539807f + 0.13508273e-1f * x) * x) * x) * x) * x;
4062 // error 0.0000037995730, which is better than 18 bits
4063 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4064 getF32Constant(DAG, 0x3c5d51ce));
4065 SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0,
4066 getF32Constant(DAG, 0x3e00685a));
4067 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
4068 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4069 getF32Constant(DAG, 0x3efb6798));
4070 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4071 SDValue t5 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4,
4072 getF32Constant(DAG, 0x3f88d192));
4073 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4074 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
4075 getF32Constant(DAG, 0x3fc4316c));
4076 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
4077 SDValue Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t8,
4078 getF32Constant(DAG, 0x3f57ce70));
4080 result = DAG.getNode(ISD::FADD, dl,
4081 MVT::f32, LogOfExponent, Log10ofMantissa);
4084 // No special expansion.
4085 result = DAG.getNode(ISD::FLOG10, dl,
4086 getValue(I.getArgOperand(0)).getValueType(),
4087 getValue(I.getArgOperand(0)));
4090 setValue(&I, result);
4093 /// visitExp2 - Lower an exp2 intrinsic. Handles the special sequences for
4094 /// limited-precision mode.
4096 SelectionDAGBuilder::visitExp2(const CallInst &I) {
4098 DebugLoc dl = getCurDebugLoc();
4100 if (getValue(I.getArgOperand(0)).getValueType() == MVT::f32 &&
4101 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
4102 SDValue Op = getValue(I.getArgOperand(0));
4104 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, Op);
4106 // FractionalPartOfX = x - (float)IntegerPartOfX;
4107 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX);
4108 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, Op, t1);
4110 // IntegerPartOfX <<= 23;
4111 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX,
4112 DAG.getConstant(23, TLI.getPointerTy()));
4114 if (LimitFloatPrecision <= 6) {
4115 // For floating-point precision of 6:
4117 // TwoToFractionalPartOfX =
4119 // (0.735607626f + 0.252464424f * x) * x;
4121 // error 0.0144103317, which is 6 bits
4122 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4123 getF32Constant(DAG, 0x3e814304));
4124 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4125 getF32Constant(DAG, 0x3f3c50c8));
4126 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4127 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4128 getF32Constant(DAG, 0x3f7f5e7e));
4129 SDValue t6 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, t5);
4130 SDValue TwoToFractionalPartOfX =
4131 DAG.getNode(ISD::ADD, dl, MVT::i32, t6, IntegerPartOfX);
4133 result = DAG.getNode(ISD::BITCAST, dl,
4134 MVT::f32, TwoToFractionalPartOfX);
4135 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
4136 // For floating-point precision of 12:
4138 // TwoToFractionalPartOfX =
4141 // (0.224338339f + 0.792043434e-1f * x) * x) * x;
4143 // error 0.000107046256, which is 13 to 14 bits
4144 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4145 getF32Constant(DAG, 0x3da235e3));
4146 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4147 getF32Constant(DAG, 0x3e65b8f3));
4148 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4149 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4150 getF32Constant(DAG, 0x3f324b07));
4151 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4152 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
4153 getF32Constant(DAG, 0x3f7ff8fd));
4154 SDValue t8 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, t7);
4155 SDValue TwoToFractionalPartOfX =
4156 DAG.getNode(ISD::ADD, dl, MVT::i32, t8, IntegerPartOfX);
4158 result = DAG.getNode(ISD::BITCAST, dl,
4159 MVT::f32, TwoToFractionalPartOfX);
4160 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
4161 // For floating-point precision of 18:
4163 // TwoToFractionalPartOfX =
4167 // (0.554906021e-1f +
4168 // (0.961591928e-2f +
4169 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x;
4170 // error 2.47208000*10^(-7), which is better than 18 bits
4171 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4172 getF32Constant(DAG, 0x3924b03e));
4173 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4174 getF32Constant(DAG, 0x3ab24b87));
4175 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4176 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4177 getF32Constant(DAG, 0x3c1d8c17));
4178 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4179 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
4180 getF32Constant(DAG, 0x3d634a1d));
4181 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
4182 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
4183 getF32Constant(DAG, 0x3e75fe14));
4184 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
4185 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10,
4186 getF32Constant(DAG, 0x3f317234));
4187 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X);
4188 SDValue t13 = DAG.getNode(ISD::FADD, dl, MVT::f32, t12,
4189 getF32Constant(DAG, 0x3f800000));
4190 SDValue t14 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, t13);
4191 SDValue TwoToFractionalPartOfX =
4192 DAG.getNode(ISD::ADD, dl, MVT::i32, t14, IntegerPartOfX);
4194 result = DAG.getNode(ISD::BITCAST, dl,
4195 MVT::f32, TwoToFractionalPartOfX);
4198 // No special expansion.
4199 result = DAG.getNode(ISD::FEXP2, dl,
4200 getValue(I.getArgOperand(0)).getValueType(),
4201 getValue(I.getArgOperand(0)));
4204 setValue(&I, result);
4207 /// visitPow - Lower a pow intrinsic. Handles the special sequences for
4208 /// limited-precision mode with x == 10.0f.
4210 SelectionDAGBuilder::visitPow(const CallInst &I) {
4212 const Value *Val = I.getArgOperand(0);
4213 DebugLoc dl = getCurDebugLoc();
4214 bool IsExp10 = false;
4216 if (getValue(Val).getValueType() == MVT::f32 &&
4217 getValue(I.getArgOperand(1)).getValueType() == MVT::f32 &&
4218 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
4219 if (Constant *C = const_cast<Constant*>(dyn_cast<Constant>(Val))) {
4220 if (ConstantFP *CFP = dyn_cast<ConstantFP>(C)) {
4222 IsExp10 = CFP->getValueAPF().bitwiseIsEqual(Ten);
4227 if (IsExp10 && LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
4228 SDValue Op = getValue(I.getArgOperand(1));
4230 // Put the exponent in the right bit position for later addition to the
4233 // #define LOG2OF10 3.3219281f
4234 // IntegerPartOfX = (int32_t)(x * LOG2OF10);
4235 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, Op,
4236 getF32Constant(DAG, 0x40549a78));
4237 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, t0);
4239 // FractionalPartOfX = x - (float)IntegerPartOfX;
4240 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX);
4241 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, t1);
4243 // IntegerPartOfX <<= 23;
4244 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX,
4245 DAG.getConstant(23, TLI.getPointerTy()));
4247 if (LimitFloatPrecision <= 6) {
4248 // For floating-point precision of 6:
4250 // twoToFractionalPartOfX =
4252 // (0.735607626f + 0.252464424f * x) * x;
4254 // error 0.0144103317, which is 6 bits
4255 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4256 getF32Constant(DAG, 0x3e814304));
4257 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4258 getF32Constant(DAG, 0x3f3c50c8));
4259 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4260 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4261 getF32Constant(DAG, 0x3f7f5e7e));
4262 SDValue t6 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, t5);
4263 SDValue TwoToFractionalPartOfX =
4264 DAG.getNode(ISD::ADD, dl, MVT::i32, t6, IntegerPartOfX);
4266 result = DAG.getNode(ISD::BITCAST, dl,
4267 MVT::f32, TwoToFractionalPartOfX);
4268 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
4269 // For floating-point precision of 12:
4271 // TwoToFractionalPartOfX =
4274 // (0.224338339f + 0.792043434e-1f * x) * x) * x;
4276 // error 0.000107046256, which is 13 to 14 bits
4277 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4278 getF32Constant(DAG, 0x3da235e3));
4279 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4280 getF32Constant(DAG, 0x3e65b8f3));
4281 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4282 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4283 getF32Constant(DAG, 0x3f324b07));
4284 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4285 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
4286 getF32Constant(DAG, 0x3f7ff8fd));
4287 SDValue t8 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, t7);
4288 SDValue TwoToFractionalPartOfX =
4289 DAG.getNode(ISD::ADD, dl, MVT::i32, t8, IntegerPartOfX);
4291 result = DAG.getNode(ISD::BITCAST, dl,
4292 MVT::f32, TwoToFractionalPartOfX);
4293 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
4294 // For floating-point precision of 18:
4296 // TwoToFractionalPartOfX =
4300 // (0.554906021e-1f +
4301 // (0.961591928e-2f +
4302 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x;
4303 // error 2.47208000*10^(-7), which is better than 18 bits
4304 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4305 getF32Constant(DAG, 0x3924b03e));
4306 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4307 getF32Constant(DAG, 0x3ab24b87));
4308 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4309 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4310 getF32Constant(DAG, 0x3c1d8c17));
4311 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4312 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
4313 getF32Constant(DAG, 0x3d634a1d));
4314 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
4315 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
4316 getF32Constant(DAG, 0x3e75fe14));
4317 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
4318 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10,
4319 getF32Constant(DAG, 0x3f317234));
4320 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X);
4321 SDValue t13 = DAG.getNode(ISD::FADD, dl, MVT::f32, t12,
4322 getF32Constant(DAG, 0x3f800000));
4323 SDValue t14 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, t13);
4324 SDValue TwoToFractionalPartOfX =
4325 DAG.getNode(ISD::ADD, dl, MVT::i32, t14, IntegerPartOfX);
4327 result = DAG.getNode(ISD::BITCAST, dl,
4328 MVT::f32, TwoToFractionalPartOfX);
4331 // No special expansion.
4332 result = DAG.getNode(ISD::FPOW, dl,
4333 getValue(I.getArgOperand(0)).getValueType(),
4334 getValue(I.getArgOperand(0)),
4335 getValue(I.getArgOperand(1)));
4338 setValue(&I, result);
4342 /// ExpandPowI - Expand a llvm.powi intrinsic.
4343 static SDValue ExpandPowI(DebugLoc DL, SDValue LHS, SDValue RHS,
4344 SelectionDAG &DAG) {
4345 // If RHS is a constant, we can expand this out to a multiplication tree,
4346 // otherwise we end up lowering to a call to __powidf2 (for example). When
4347 // optimizing for size, we only want to do this if the expansion would produce
4348 // a small number of multiplies, otherwise we do the full expansion.
4349 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
4350 // Get the exponent as a positive value.
4351 unsigned Val = RHSC->getSExtValue();
4352 if ((int)Val < 0) Val = -Val;
4354 // powi(x, 0) -> 1.0
4356 return DAG.getConstantFP(1.0, LHS.getValueType());
4358 const Function *F = DAG.getMachineFunction().getFunction();
4359 if (!F->hasFnAttr(Attribute::OptimizeForSize) ||
4360 // If optimizing for size, don't insert too many multiplies. This
4361 // inserts up to 5 multiplies.
4362 CountPopulation_32(Val)+Log2_32(Val) < 7) {
4363 // We use the simple binary decomposition method to generate the multiply
4364 // sequence. There are more optimal ways to do this (for example,
4365 // powi(x,15) generates one more multiply than it should), but this has
4366 // the benefit of being both really simple and much better than a libcall.
4367 SDValue Res; // Logically starts equal to 1.0
4368 SDValue CurSquare = LHS;
4372 Res = DAG.getNode(ISD::FMUL, DL,Res.getValueType(), Res, CurSquare);
4374 Res = CurSquare; // 1.0*CurSquare.
4377 CurSquare = DAG.getNode(ISD::FMUL, DL, CurSquare.getValueType(),
4378 CurSquare, CurSquare);
4382 // If the original was negative, invert the result, producing 1/(x*x*x).
4383 if (RHSC->getSExtValue() < 0)
4384 Res = DAG.getNode(ISD::FDIV, DL, LHS.getValueType(),
4385 DAG.getConstantFP(1.0, LHS.getValueType()), Res);
4390 // Otherwise, expand to a libcall.
4391 return DAG.getNode(ISD::FPOWI, DL, LHS.getValueType(), LHS, RHS);
4394 // getTruncatedArgReg - Find underlying register used for an truncated
4396 static unsigned getTruncatedArgReg(const SDValue &N) {
4397 if (N.getOpcode() != ISD::TRUNCATE)
4400 const SDValue &Ext = N.getOperand(0);
4401 if (Ext.getOpcode() == ISD::AssertZext || Ext.getOpcode() == ISD::AssertSext){
4402 const SDValue &CFR = Ext.getOperand(0);
4403 if (CFR.getOpcode() == ISD::CopyFromReg)
4404 return cast<RegisterSDNode>(CFR.getOperand(1))->getReg();
4405 if (CFR.getOpcode() == ISD::TRUNCATE)
4406 return getTruncatedArgReg(CFR);
4411 /// EmitFuncArgumentDbgValue - If the DbgValueInst is a dbg_value of a function
4412 /// argument, create the corresponding DBG_VALUE machine instruction for it now.
4413 /// At the end of instruction selection, they will be inserted to the entry BB.
4415 SelectionDAGBuilder::EmitFuncArgumentDbgValue(const Value *V, MDNode *Variable,
4418 const Argument *Arg = dyn_cast<Argument>(V);
4422 MachineFunction &MF = DAG.getMachineFunction();
4423 const TargetInstrInfo *TII = DAG.getTarget().getInstrInfo();
4424 const TargetRegisterInfo *TRI = DAG.getTarget().getRegisterInfo();
4426 // Ignore inlined function arguments here.
4427 DIVariable DV(Variable);
4428 if (DV.isInlinedFnArgument(MF.getFunction()))
4432 // Some arguments' frame index is recorded during argument lowering.
4433 Offset = FuncInfo.getArgumentFrameIndex(Arg);
4435 Reg = TRI->getFrameRegister(MF);
4437 if (!Reg && N.getNode()) {
4438 if (N.getOpcode() == ISD::CopyFromReg)
4439 Reg = cast<RegisterSDNode>(N.getOperand(1))->getReg();
4441 Reg = getTruncatedArgReg(N);
4442 if (Reg && TargetRegisterInfo::isVirtualRegister(Reg)) {
4443 MachineRegisterInfo &RegInfo = MF.getRegInfo();
4444 unsigned PR = RegInfo.getLiveInPhysReg(Reg);
4451 // Check if ValueMap has reg number.
4452 DenseMap<const Value *, unsigned>::iterator VMI = FuncInfo.ValueMap.find(V);
4453 if (VMI != FuncInfo.ValueMap.end())
4457 if (!Reg && N.getNode()) {
4458 // Check if frame index is available.
4459 if (LoadSDNode *LNode = dyn_cast<LoadSDNode>(N.getNode()))
4460 if (FrameIndexSDNode *FINode =
4461 dyn_cast<FrameIndexSDNode>(LNode->getBasePtr().getNode())) {
4462 Reg = TRI->getFrameRegister(MF);
4463 Offset = FINode->getIndex();
4470 MachineInstrBuilder MIB = BuildMI(MF, getCurDebugLoc(),
4471 TII->get(TargetOpcode::DBG_VALUE))
4472 .addReg(Reg, RegState::Debug).addImm(Offset).addMetadata(Variable);
4473 FuncInfo.ArgDbgValues.push_back(&*MIB);
4477 // VisualStudio defines setjmp as _setjmp
4478 #if defined(_MSC_VER) && defined(setjmp) && \
4479 !defined(setjmp_undefined_for_msvc)
4480 # pragma push_macro("setjmp")
4482 # define setjmp_undefined_for_msvc
4485 /// visitIntrinsicCall - Lower the call to the specified intrinsic function. If
4486 /// we want to emit this as a call to a named external function, return the name
4487 /// otherwise lower it and return null.
4489 SelectionDAGBuilder::visitIntrinsicCall(const CallInst &I, unsigned Intrinsic) {
4490 DebugLoc dl = getCurDebugLoc();
4493 switch (Intrinsic) {
4495 // By default, turn this into a target intrinsic node.
4496 visitTargetIntrinsic(I, Intrinsic);
4498 case Intrinsic::vastart: visitVAStart(I); return 0;
4499 case Intrinsic::vaend: visitVAEnd(I); return 0;
4500 case Intrinsic::vacopy: visitVACopy(I); return 0;
4501 case Intrinsic::returnaddress:
4502 setValue(&I, DAG.getNode(ISD::RETURNADDR, dl, TLI.getPointerTy(),
4503 getValue(I.getArgOperand(0))));
4505 case Intrinsic::frameaddress:
4506 setValue(&I, DAG.getNode(ISD::FRAMEADDR, dl, TLI.getPointerTy(),
4507 getValue(I.getArgOperand(0))));
4509 case Intrinsic::setjmp:
4510 return &"_setjmp"[!TLI.usesUnderscoreSetJmp()];
4511 case Intrinsic::longjmp:
4512 return &"_longjmp"[!TLI.usesUnderscoreLongJmp()];
4513 case Intrinsic::memcpy: {
4514 // Assert for address < 256 since we support only user defined address
4516 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace()
4518 cast<PointerType>(I.getArgOperand(1)->getType())->getAddressSpace()
4520 "Unknown address space");
4521 SDValue Op1 = getValue(I.getArgOperand(0));
4522 SDValue Op2 = getValue(I.getArgOperand(1));
4523 SDValue Op3 = getValue(I.getArgOperand(2));
4524 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue();
4525 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue();
4526 DAG.setRoot(DAG.getMemcpy(getRoot(), dl, Op1, Op2, Op3, Align, isVol, false,
4527 MachinePointerInfo(I.getArgOperand(0)),
4528 MachinePointerInfo(I.getArgOperand(1))));
4531 case Intrinsic::memset: {
4532 // Assert for address < 256 since we support only user defined address
4534 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace()
4536 "Unknown address space");
4537 SDValue Op1 = getValue(I.getArgOperand(0));
4538 SDValue Op2 = getValue(I.getArgOperand(1));
4539 SDValue Op3 = getValue(I.getArgOperand(2));
4540 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue();
4541 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue();
4542 DAG.setRoot(DAG.getMemset(getRoot(), dl, Op1, Op2, Op3, Align, isVol,
4543 MachinePointerInfo(I.getArgOperand(0))));
4546 case Intrinsic::memmove: {
4547 // Assert for address < 256 since we support only user defined address
4549 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace()
4551 cast<PointerType>(I.getArgOperand(1)->getType())->getAddressSpace()
4553 "Unknown address space");
4554 SDValue Op1 = getValue(I.getArgOperand(0));
4555 SDValue Op2 = getValue(I.getArgOperand(1));
4556 SDValue Op3 = getValue(I.getArgOperand(2));
4557 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue();
4558 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue();
4559 DAG.setRoot(DAG.getMemmove(getRoot(), dl, Op1, Op2, Op3, Align, isVol,
4560 MachinePointerInfo(I.getArgOperand(0)),
4561 MachinePointerInfo(I.getArgOperand(1))));
4564 case Intrinsic::dbg_declare: {
4565 const DbgDeclareInst &DI = cast<DbgDeclareInst>(I);
4566 MDNode *Variable = DI.getVariable();
4567 const Value *Address = DI.getAddress();
4568 if (!Address || !DIVariable(Variable).Verify()) {
4569 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
4573 // Build an entry in DbgOrdering. Debug info input nodes get an SDNodeOrder
4574 // but do not always have a corresponding SDNode built. The SDNodeOrder
4575 // absolute, but not relative, values are different depending on whether
4576 // debug info exists.
4579 // Check if address has undef value.
4580 if (isa<UndefValue>(Address) ||
4581 (Address->use_empty() && !isa<Argument>(Address))) {
4582 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
4586 SDValue &N = NodeMap[Address];
4587 if (!N.getNode() && isa<Argument>(Address))
4588 // Check unused arguments map.
4589 N = UnusedArgNodeMap[Address];
4592 if (const BitCastInst *BCI = dyn_cast<BitCastInst>(Address))
4593 Address = BCI->getOperand(0);
4594 // Parameters are handled specially.
4596 (DIVariable(Variable).getTag() == dwarf::DW_TAG_arg_variable ||
4597 isa<Argument>(Address));
4599 const AllocaInst *AI = dyn_cast<AllocaInst>(Address);
4601 if (isParameter && !AI) {
4602 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(N.getNode());
4604 // Byval parameter. We have a frame index at this point.
4605 SDV = DAG.getDbgValue(Variable, FINode->getIndex(),
4606 0, dl, SDNodeOrder);
4608 // Address is an argument, so try to emit its dbg value using
4609 // virtual register info from the FuncInfo.ValueMap.
4610 EmitFuncArgumentDbgValue(Address, Variable, 0, N);
4614 SDV = DAG.getDbgValue(Variable, N.getNode(), N.getResNo(),
4615 0, dl, SDNodeOrder);
4617 // Can't do anything with other non-AI cases yet.
4618 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
4619 DEBUG(dbgs() << "non-AllocaInst issue for Address: \n\t");
4620 DEBUG(Address->dump());
4623 DAG.AddDbgValue(SDV, N.getNode(), isParameter);
4625 // If Address is an argument then try to emit its dbg value using
4626 // virtual register info from the FuncInfo.ValueMap.
4627 if (!EmitFuncArgumentDbgValue(Address, Variable, 0, N)) {
4628 // If variable is pinned by a alloca in dominating bb then
4629 // use StaticAllocaMap.
4630 if (const AllocaInst *AI = dyn_cast<AllocaInst>(Address)) {
4631 if (AI->getParent() != DI.getParent()) {
4632 DenseMap<const AllocaInst*, int>::iterator SI =
4633 FuncInfo.StaticAllocaMap.find(AI);
4634 if (SI != FuncInfo.StaticAllocaMap.end()) {
4635 SDV = DAG.getDbgValue(Variable, SI->second,
4636 0, dl, SDNodeOrder);
4637 DAG.AddDbgValue(SDV, 0, false);
4642 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
4647 case Intrinsic::dbg_value: {
4648 const DbgValueInst &DI = cast<DbgValueInst>(I);
4649 if (!DIVariable(DI.getVariable()).Verify())
4652 MDNode *Variable = DI.getVariable();
4653 uint64_t Offset = DI.getOffset();
4654 const Value *V = DI.getValue();
4658 // Build an entry in DbgOrdering. Debug info input nodes get an SDNodeOrder
4659 // but do not always have a corresponding SDNode built. The SDNodeOrder
4660 // absolute, but not relative, values are different depending on whether
4661 // debug info exists.
4664 if (isa<ConstantInt>(V) || isa<ConstantFP>(V) || isa<UndefValue>(V)) {
4665 SDV = DAG.getDbgValue(Variable, V, Offset, dl, SDNodeOrder);
4666 DAG.AddDbgValue(SDV, 0, false);
4668 // Do not use getValue() in here; we don't want to generate code at
4669 // this point if it hasn't been done yet.
4670 SDValue N = NodeMap[V];
4671 if (!N.getNode() && isa<Argument>(V))
4672 // Check unused arguments map.
4673 N = UnusedArgNodeMap[V];
4675 if (!EmitFuncArgumentDbgValue(V, Variable, Offset, N)) {
4676 SDV = DAG.getDbgValue(Variable, N.getNode(),
4677 N.getResNo(), Offset, dl, SDNodeOrder);
4678 DAG.AddDbgValue(SDV, N.getNode(), false);
4680 } else if (!V->use_empty() ) {
4681 // Do not call getValue(V) yet, as we don't want to generate code.
4682 // Remember it for later.
4683 DanglingDebugInfo DDI(&DI, dl, SDNodeOrder);
4684 DanglingDebugInfoMap[V] = DDI;
4686 // We may expand this to cover more cases. One case where we have no
4687 // data available is an unreferenced parameter.
4688 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
4692 // Build a debug info table entry.
4693 if (const BitCastInst *BCI = dyn_cast<BitCastInst>(V))
4694 V = BCI->getOperand(0);
4695 const AllocaInst *AI = dyn_cast<AllocaInst>(V);
4696 // Don't handle byval struct arguments or VLAs, for example.
4698 DEBUG(dbgs() << "Dropping debug location info for:\n " << DI << "\n");
4699 DEBUG(dbgs() << " Last seen at:\n " << *V << "\n");
4702 DenseMap<const AllocaInst*, int>::iterator SI =
4703 FuncInfo.StaticAllocaMap.find(AI);
4704 if (SI == FuncInfo.StaticAllocaMap.end())
4706 int FI = SI->second;
4708 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
4709 if (!DI.getDebugLoc().isUnknown() && MMI.hasDebugInfo())
4710 MMI.setVariableDbgInfo(Variable, FI, DI.getDebugLoc());
4714 case Intrinsic::eh_typeid_for: {
4715 // Find the type id for the given typeinfo.
4716 GlobalVariable *GV = ExtractTypeInfo(I.getArgOperand(0));
4717 unsigned TypeID = DAG.getMachineFunction().getMMI().getTypeIDFor(GV);
4718 Res = DAG.getConstant(TypeID, MVT::i32);
4723 case Intrinsic::eh_return_i32:
4724 case Intrinsic::eh_return_i64:
4725 DAG.getMachineFunction().getMMI().setCallsEHReturn(true);
4726 DAG.setRoot(DAG.getNode(ISD::EH_RETURN, dl,
4729 getValue(I.getArgOperand(0)),
4730 getValue(I.getArgOperand(1))));
4732 case Intrinsic::eh_unwind_init:
4733 DAG.getMachineFunction().getMMI().setCallsUnwindInit(true);
4735 case Intrinsic::eh_dwarf_cfa: {
4736 SDValue CfaArg = DAG.getSExtOrTrunc(getValue(I.getArgOperand(0)), dl,
4737 TLI.getPointerTy());
4738 SDValue Offset = DAG.getNode(ISD::ADD, dl,
4740 DAG.getNode(ISD::FRAME_TO_ARGS_OFFSET, dl,
4741 TLI.getPointerTy()),
4743 SDValue FA = DAG.getNode(ISD::FRAMEADDR, dl,
4745 DAG.getConstant(0, TLI.getPointerTy()));
4746 setValue(&I, DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(),
4750 case Intrinsic::eh_sjlj_callsite: {
4751 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
4752 ConstantInt *CI = dyn_cast<ConstantInt>(I.getArgOperand(0));
4753 assert(CI && "Non-constant call site value in eh.sjlj.callsite!");
4754 assert(MMI.getCurrentCallSite() == 0 && "Overlapping call sites!");
4756 MMI.setCurrentCallSite(CI->getZExtValue());
4759 case Intrinsic::eh_sjlj_functioncontext: {
4760 // Get and store the index of the function context.
4761 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
4763 cast<AllocaInst>(I.getArgOperand(0)->stripPointerCasts());
4764 int FI = FuncInfo.StaticAllocaMap[FnCtx];
4765 MFI->setFunctionContextIndex(FI);
4768 case Intrinsic::eh_sjlj_setjmp: {
4771 Ops[1] = getValue(I.getArgOperand(0));
4772 SDValue Op = DAG.getNode(ISD::EH_SJLJ_SETJMP, dl,
4773 DAG.getVTList(MVT::i32, MVT::Other),
4775 setValue(&I, Op.getValue(0));
4776 DAG.setRoot(Op.getValue(1));
4779 case Intrinsic::eh_sjlj_longjmp: {
4780 DAG.setRoot(DAG.getNode(ISD::EH_SJLJ_LONGJMP, dl, MVT::Other,
4781 getRoot(), getValue(I.getArgOperand(0))));
4785 case Intrinsic::x86_mmx_pslli_w:
4786 case Intrinsic::x86_mmx_pslli_d:
4787 case Intrinsic::x86_mmx_pslli_q:
4788 case Intrinsic::x86_mmx_psrli_w:
4789 case Intrinsic::x86_mmx_psrli_d:
4790 case Intrinsic::x86_mmx_psrli_q:
4791 case Intrinsic::x86_mmx_psrai_w:
4792 case Intrinsic::x86_mmx_psrai_d: {
4793 SDValue ShAmt = getValue(I.getArgOperand(1));
4794 if (isa<ConstantSDNode>(ShAmt)) {
4795 visitTargetIntrinsic(I, Intrinsic);
4798 unsigned NewIntrinsic = 0;
4799 EVT ShAmtVT = MVT::v2i32;
4800 switch (Intrinsic) {
4801 case Intrinsic::x86_mmx_pslli_w:
4802 NewIntrinsic = Intrinsic::x86_mmx_psll_w;
4804 case Intrinsic::x86_mmx_pslli_d:
4805 NewIntrinsic = Intrinsic::x86_mmx_psll_d;
4807 case Intrinsic::x86_mmx_pslli_q:
4808 NewIntrinsic = Intrinsic::x86_mmx_psll_q;
4810 case Intrinsic::x86_mmx_psrli_w:
4811 NewIntrinsic = Intrinsic::x86_mmx_psrl_w;
4813 case Intrinsic::x86_mmx_psrli_d:
4814 NewIntrinsic = Intrinsic::x86_mmx_psrl_d;
4816 case Intrinsic::x86_mmx_psrli_q:
4817 NewIntrinsic = Intrinsic::x86_mmx_psrl_q;
4819 case Intrinsic::x86_mmx_psrai_w:
4820 NewIntrinsic = Intrinsic::x86_mmx_psra_w;
4822 case Intrinsic::x86_mmx_psrai_d:
4823 NewIntrinsic = Intrinsic::x86_mmx_psra_d;
4825 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
4828 // The vector shift intrinsics with scalars uses 32b shift amounts but
4829 // the sse2/mmx shift instructions reads 64 bits. Set the upper 32 bits
4831 // We must do this early because v2i32 is not a legal type.
4832 DebugLoc dl = getCurDebugLoc();
4835 ShOps[1] = DAG.getConstant(0, MVT::i32);
4836 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, ShAmtVT, &ShOps[0], 2);
4837 EVT DestVT = TLI.getValueType(I.getType());
4838 ShAmt = DAG.getNode(ISD::BITCAST, dl, DestVT, ShAmt);
4839 Res = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT,
4840 DAG.getConstant(NewIntrinsic, MVT::i32),
4841 getValue(I.getArgOperand(0)), ShAmt);
4845 case Intrinsic::x86_avx_vinsertf128_pd_256:
4846 case Intrinsic::x86_avx_vinsertf128_ps_256:
4847 case Intrinsic::x86_avx_vinsertf128_si_256:
4848 case Intrinsic::x86_avx2_vinserti128: {
4849 DebugLoc dl = getCurDebugLoc();
4850 EVT DestVT = TLI.getValueType(I.getType());
4851 EVT ElVT = TLI.getValueType(I.getArgOperand(1)->getType());
4852 uint64_t Idx = (cast<ConstantInt>(I.getArgOperand(2))->getZExtValue() & 1) *
4853 ElVT.getVectorNumElements();
4854 Res = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, DestVT,
4855 getValue(I.getArgOperand(0)),
4856 getValue(I.getArgOperand(1)),
4857 DAG.getConstant(Idx, MVT::i32));
4861 case Intrinsic::convertff:
4862 case Intrinsic::convertfsi:
4863 case Intrinsic::convertfui:
4864 case Intrinsic::convertsif:
4865 case Intrinsic::convertuif:
4866 case Intrinsic::convertss:
4867 case Intrinsic::convertsu:
4868 case Intrinsic::convertus:
4869 case Intrinsic::convertuu: {
4870 ISD::CvtCode Code = ISD::CVT_INVALID;
4871 switch (Intrinsic) {
4872 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
4873 case Intrinsic::convertff: Code = ISD::CVT_FF; break;
4874 case Intrinsic::convertfsi: Code = ISD::CVT_FS; break;
4875 case Intrinsic::convertfui: Code = ISD::CVT_FU; break;
4876 case Intrinsic::convertsif: Code = ISD::CVT_SF; break;
4877 case Intrinsic::convertuif: Code = ISD::CVT_UF; break;
4878 case Intrinsic::convertss: Code = ISD::CVT_SS; break;
4879 case Intrinsic::convertsu: Code = ISD::CVT_SU; break;
4880 case Intrinsic::convertus: Code = ISD::CVT_US; break;
4881 case Intrinsic::convertuu: Code = ISD::CVT_UU; break;
4883 EVT DestVT = TLI.getValueType(I.getType());
4884 const Value *Op1 = I.getArgOperand(0);
4885 Res = DAG.getConvertRndSat(DestVT, getCurDebugLoc(), getValue(Op1),
4886 DAG.getValueType(DestVT),
4887 DAG.getValueType(getValue(Op1).getValueType()),
4888 getValue(I.getArgOperand(1)),
4889 getValue(I.getArgOperand(2)),
4894 case Intrinsic::sqrt:
4895 setValue(&I, DAG.getNode(ISD::FSQRT, dl,
4896 getValue(I.getArgOperand(0)).getValueType(),
4897 getValue(I.getArgOperand(0))));
4899 case Intrinsic::powi:
4900 setValue(&I, ExpandPowI(dl, getValue(I.getArgOperand(0)),
4901 getValue(I.getArgOperand(1)), DAG));
4903 case Intrinsic::sin:
4904 setValue(&I, DAG.getNode(ISD::FSIN, dl,
4905 getValue(I.getArgOperand(0)).getValueType(),
4906 getValue(I.getArgOperand(0))));
4908 case Intrinsic::cos:
4909 setValue(&I, DAG.getNode(ISD::FCOS, dl,
4910 getValue(I.getArgOperand(0)).getValueType(),
4911 getValue(I.getArgOperand(0))));
4913 case Intrinsic::log:
4916 case Intrinsic::log2:
4919 case Intrinsic::log10:
4922 case Intrinsic::exp:
4925 case Intrinsic::exp2:
4928 case Intrinsic::pow:
4931 case Intrinsic::fabs:
4932 setValue(&I, DAG.getNode(ISD::FABS, dl,
4933 getValue(I.getArgOperand(0)).getValueType(),
4934 getValue(I.getArgOperand(0))));
4936 case Intrinsic::floor:
4937 setValue(&I, DAG.getNode(ISD::FFLOOR, dl,
4938 getValue(I.getArgOperand(0)).getValueType(),
4939 getValue(I.getArgOperand(0))));
4941 case Intrinsic::fma:
4942 setValue(&I, DAG.getNode(ISD::FMA, dl,
4943 getValue(I.getArgOperand(0)).getValueType(),
4944 getValue(I.getArgOperand(0)),
4945 getValue(I.getArgOperand(1)),
4946 getValue(I.getArgOperand(2))));
4948 case Intrinsic::fmuladd: {
4949 EVT VT = TLI.getValueType(I.getType());
4950 if (TM.Options.AllowFPOpFusion != FPOpFusion::Strict &&
4951 TLI.isOperationLegal(ISD::FMA, VT) &&
4952 TLI.isFMAFasterThanMulAndAdd(VT)){
4953 setValue(&I, DAG.getNode(ISD::FMA, dl,
4954 getValue(I.getArgOperand(0)).getValueType(),
4955 getValue(I.getArgOperand(0)),
4956 getValue(I.getArgOperand(1)),
4957 getValue(I.getArgOperand(2))));
4959 SDValue Mul = DAG.getNode(ISD::FMUL, dl,
4960 getValue(I.getArgOperand(0)).getValueType(),
4961 getValue(I.getArgOperand(0)),
4962 getValue(I.getArgOperand(1)));
4963 SDValue Add = DAG.getNode(ISD::FADD, dl,
4964 getValue(I.getArgOperand(0)).getValueType(),
4966 getValue(I.getArgOperand(2)));
4971 case Intrinsic::convert_to_fp16:
4972 setValue(&I, DAG.getNode(ISD::FP32_TO_FP16, dl,
4973 MVT::i16, getValue(I.getArgOperand(0))));
4975 case Intrinsic::convert_from_fp16:
4976 setValue(&I, DAG.getNode(ISD::FP16_TO_FP32, dl,
4977 MVT::f32, getValue(I.getArgOperand(0))));
4979 case Intrinsic::pcmarker: {
4980 SDValue Tmp = getValue(I.getArgOperand(0));
4981 DAG.setRoot(DAG.getNode(ISD::PCMARKER, dl, MVT::Other, getRoot(), Tmp));
4984 case Intrinsic::readcyclecounter: {
4985 SDValue Op = getRoot();
4986 Res = DAG.getNode(ISD::READCYCLECOUNTER, dl,
4987 DAG.getVTList(MVT::i64, MVT::Other),
4990 DAG.setRoot(Res.getValue(1));
4993 case Intrinsic::bswap:
4994 setValue(&I, DAG.getNode(ISD::BSWAP, dl,
4995 getValue(I.getArgOperand(0)).getValueType(),
4996 getValue(I.getArgOperand(0))));
4998 case Intrinsic::cttz: {
4999 SDValue Arg = getValue(I.getArgOperand(0));
5000 ConstantInt *CI = cast<ConstantInt>(I.getArgOperand(1));
5001 EVT Ty = Arg.getValueType();
5002 setValue(&I, DAG.getNode(CI->isZero() ? ISD::CTTZ : ISD::CTTZ_ZERO_UNDEF,
5006 case Intrinsic::ctlz: {
5007 SDValue Arg = getValue(I.getArgOperand(0));
5008 ConstantInt *CI = cast<ConstantInt>(I.getArgOperand(1));
5009 EVT Ty = Arg.getValueType();
5010 setValue(&I, DAG.getNode(CI->isZero() ? ISD::CTLZ : ISD::CTLZ_ZERO_UNDEF,
5014 case Intrinsic::ctpop: {
5015 SDValue Arg = getValue(I.getArgOperand(0));
5016 EVT Ty = Arg.getValueType();
5017 setValue(&I, DAG.getNode(ISD::CTPOP, dl, Ty, Arg));
5020 case Intrinsic::stacksave: {
5021 SDValue Op = getRoot();
5022 Res = DAG.getNode(ISD::STACKSAVE, dl,
5023 DAG.getVTList(TLI.getPointerTy(), MVT::Other), &Op, 1);
5025 DAG.setRoot(Res.getValue(1));
5028 case Intrinsic::stackrestore: {
5029 Res = getValue(I.getArgOperand(0));
5030 DAG.setRoot(DAG.getNode(ISD::STACKRESTORE, dl, MVT::Other, getRoot(), Res));
5033 case Intrinsic::stackprotector: {
5034 // Emit code into the DAG to store the stack guard onto the stack.
5035 MachineFunction &MF = DAG.getMachineFunction();
5036 MachineFrameInfo *MFI = MF.getFrameInfo();
5037 EVT PtrTy = TLI.getPointerTy();
5039 SDValue Src = getValue(I.getArgOperand(0)); // The guard's value.
5040 AllocaInst *Slot = cast<AllocaInst>(I.getArgOperand(1));
5042 int FI = FuncInfo.StaticAllocaMap[Slot];
5043 MFI->setStackProtectorIndex(FI);
5045 SDValue FIN = DAG.getFrameIndex(FI, PtrTy);
5047 // Store the stack protector onto the stack.
5048 Res = DAG.getStore(getRoot(), getCurDebugLoc(), Src, FIN,
5049 MachinePointerInfo::getFixedStack(FI),
5055 case Intrinsic::objectsize: {
5056 // If we don't know by now, we're never going to know.
5057 ConstantInt *CI = dyn_cast<ConstantInt>(I.getArgOperand(1));
5059 assert(CI && "Non-constant type in __builtin_object_size?");
5061 SDValue Arg = getValue(I.getCalledValue());
5062 EVT Ty = Arg.getValueType();
5065 Res = DAG.getConstant(-1ULL, Ty);
5067 Res = DAG.getConstant(0, Ty);
5072 case Intrinsic::var_annotation:
5073 // Discard annotate attributes
5076 case Intrinsic::init_trampoline: {
5077 const Function *F = cast<Function>(I.getArgOperand(1)->stripPointerCasts());
5081 Ops[1] = getValue(I.getArgOperand(0));
5082 Ops[2] = getValue(I.getArgOperand(1));
5083 Ops[3] = getValue(I.getArgOperand(2));
5084 Ops[4] = DAG.getSrcValue(I.getArgOperand(0));
5085 Ops[5] = DAG.getSrcValue(F);
5087 Res = DAG.getNode(ISD::INIT_TRAMPOLINE, dl, MVT::Other, Ops, 6);
5092 case Intrinsic::adjust_trampoline: {
5093 setValue(&I, DAG.getNode(ISD::ADJUST_TRAMPOLINE, dl,
5095 getValue(I.getArgOperand(0))));
5098 case Intrinsic::gcroot:
5100 const Value *Alloca = I.getArgOperand(0)->stripPointerCasts();
5101 const Constant *TypeMap = cast<Constant>(I.getArgOperand(1));
5103 FrameIndexSDNode *FI = cast<FrameIndexSDNode>(getValue(Alloca).getNode());
5104 GFI->addStackRoot(FI->getIndex(), TypeMap);
5107 case Intrinsic::gcread:
5108 case Intrinsic::gcwrite:
5109 llvm_unreachable("GC failed to lower gcread/gcwrite intrinsics!");
5110 case Intrinsic::flt_rounds:
5111 setValue(&I, DAG.getNode(ISD::FLT_ROUNDS_, dl, MVT::i32));
5114 case Intrinsic::expect: {
5115 // Just replace __builtin_expect(exp, c) with EXP.
5116 setValue(&I, getValue(I.getArgOperand(0)));
5120 case Intrinsic::trap: {
5121 StringRef TrapFuncName = TM.Options.getTrapFunctionName();
5122 if (TrapFuncName.empty()) {
5123 DAG.setRoot(DAG.getNode(ISD::TRAP, dl,MVT::Other, getRoot()));
5126 TargetLowering::ArgListTy Args;
5128 CallLoweringInfo CLI(getRoot(), I.getType(),
5129 false, false, false, false, 0, CallingConv::C,
5130 /*isTailCall=*/false,
5131 /*doesNotRet=*/false, /*isReturnValueUsed=*/true,
5132 DAG.getExternalSymbol(TrapFuncName.data(), TLI.getPointerTy()),
5133 Args, DAG, getCurDebugLoc());
5134 std::pair<SDValue, SDValue> Result = TLI.LowerCallTo(CLI);
5135 DAG.setRoot(Result.second);
5138 case Intrinsic::debugtrap: {
5139 DAG.setRoot(DAG.getNode(ISD::DEBUGTRAP, dl,MVT::Other, getRoot()));
5142 case Intrinsic::uadd_with_overflow:
5143 case Intrinsic::sadd_with_overflow:
5144 case Intrinsic::usub_with_overflow:
5145 case Intrinsic::ssub_with_overflow:
5146 case Intrinsic::umul_with_overflow:
5147 case Intrinsic::smul_with_overflow: {
5149 switch (Intrinsic) {
5150 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
5151 case Intrinsic::uadd_with_overflow: Op = ISD::UADDO; break;
5152 case Intrinsic::sadd_with_overflow: Op = ISD::SADDO; break;
5153 case Intrinsic::usub_with_overflow: Op = ISD::USUBO; break;
5154 case Intrinsic::ssub_with_overflow: Op = ISD::SSUBO; break;
5155 case Intrinsic::umul_with_overflow: Op = ISD::UMULO; break;
5156 case Intrinsic::smul_with_overflow: Op = ISD::SMULO; break;
5158 SDValue Op1 = getValue(I.getArgOperand(0));
5159 SDValue Op2 = getValue(I.getArgOperand(1));
5161 SDVTList VTs = DAG.getVTList(Op1.getValueType(), MVT::i1);
5162 setValue(&I, DAG.getNode(Op, getCurDebugLoc(), VTs, Op1, Op2));
5165 case Intrinsic::prefetch: {
5167 unsigned rw = cast<ConstantInt>(I.getArgOperand(1))->getZExtValue();
5169 Ops[1] = getValue(I.getArgOperand(0));
5170 Ops[2] = getValue(I.getArgOperand(1));
5171 Ops[3] = getValue(I.getArgOperand(2));
5172 Ops[4] = getValue(I.getArgOperand(3));
5173 DAG.setRoot(DAG.getMemIntrinsicNode(ISD::PREFETCH, dl,
5174 DAG.getVTList(MVT::Other),
5176 EVT::getIntegerVT(*Context, 8),
5177 MachinePointerInfo(I.getArgOperand(0)),
5179 false, /* volatile */
5181 rw==1)); /* write */
5185 case Intrinsic::invariant_start:
5186 case Intrinsic::lifetime_start:
5187 // Discard region information.
5188 setValue(&I, DAG.getUNDEF(TLI.getPointerTy()));
5190 case Intrinsic::invariant_end:
5191 case Intrinsic::lifetime_end:
5192 // Discard region information.
5194 case Intrinsic::donothing:
5200 void SelectionDAGBuilder::LowerCallTo(ImmutableCallSite CS, SDValue Callee,
5202 MachineBasicBlock *LandingPad) {
5203 PointerType *PT = cast<PointerType>(CS.getCalledValue()->getType());
5204 FunctionType *FTy = cast<FunctionType>(PT->getElementType());
5205 Type *RetTy = FTy->getReturnType();
5206 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
5207 MCSymbol *BeginLabel = 0;
5209 TargetLowering::ArgListTy Args;
5210 TargetLowering::ArgListEntry Entry;
5211 Args.reserve(CS.arg_size());
5213 // Check whether the function can return without sret-demotion.
5214 SmallVector<ISD::OutputArg, 4> Outs;
5215 GetReturnInfo(RetTy, CS.getAttributes().getRetAttributes(),
5218 bool CanLowerReturn = TLI.CanLowerReturn(CS.getCallingConv(),
5219 DAG.getMachineFunction(),
5220 FTy->isVarArg(), Outs,
5223 SDValue DemoteStackSlot;
5224 int DemoteStackIdx = -100;
5226 if (!CanLowerReturn) {
5227 uint64_t TySize = TLI.getTargetData()->getTypeAllocSize(
5228 FTy->getReturnType());
5229 unsigned Align = TLI.getTargetData()->getPrefTypeAlignment(
5230 FTy->getReturnType());
5231 MachineFunction &MF = DAG.getMachineFunction();
5232 DemoteStackIdx = MF.getFrameInfo()->CreateStackObject(TySize, Align, false);
5233 Type *StackSlotPtrType = PointerType::getUnqual(FTy->getReturnType());
5235 DemoteStackSlot = DAG.getFrameIndex(DemoteStackIdx, TLI.getPointerTy());
5236 Entry.Node = DemoteStackSlot;
5237 Entry.Ty = StackSlotPtrType;
5238 Entry.isSExt = false;
5239 Entry.isZExt = false;
5240 Entry.isInReg = false;
5241 Entry.isSRet = true;
5242 Entry.isNest = false;
5243 Entry.isByVal = false;
5244 Entry.Alignment = Align;
5245 Args.push_back(Entry);
5246 RetTy = Type::getVoidTy(FTy->getContext());
5249 for (ImmutableCallSite::arg_iterator i = CS.arg_begin(), e = CS.arg_end();
5251 const Value *V = *i;
5254 if (V->getType()->isEmptyTy())
5257 SDValue ArgNode = getValue(V);
5258 Entry.Node = ArgNode; Entry.Ty = V->getType();
5260 unsigned attrInd = i - CS.arg_begin() + 1;
5261 Entry.isSExt = CS.paramHasAttr(attrInd, Attribute::SExt);
5262 Entry.isZExt = CS.paramHasAttr(attrInd, Attribute::ZExt);
5263 Entry.isInReg = CS.paramHasAttr(attrInd, Attribute::InReg);
5264 Entry.isSRet = CS.paramHasAttr(attrInd, Attribute::StructRet);
5265 Entry.isNest = CS.paramHasAttr(attrInd, Attribute::Nest);
5266 Entry.isByVal = CS.paramHasAttr(attrInd, Attribute::ByVal);
5267 Entry.Alignment = CS.getParamAlignment(attrInd);
5268 Args.push_back(Entry);
5272 // Insert a label before the invoke call to mark the try range. This can be
5273 // used to detect deletion of the invoke via the MachineModuleInfo.
5274 BeginLabel = MMI.getContext().CreateTempSymbol();
5276 // For SjLj, keep track of which landing pads go with which invokes
5277 // so as to maintain the ordering of pads in the LSDA.
5278 unsigned CallSiteIndex = MMI.getCurrentCallSite();
5279 if (CallSiteIndex) {
5280 MMI.setCallSiteBeginLabel(BeginLabel, CallSiteIndex);
5281 LPadToCallSiteMap[LandingPad].push_back(CallSiteIndex);
5283 // Now that the call site is handled, stop tracking it.
5284 MMI.setCurrentCallSite(0);
5287 // Both PendingLoads and PendingExports must be flushed here;
5288 // this call might not return.
5290 DAG.setRoot(DAG.getEHLabel(getCurDebugLoc(), getControlRoot(), BeginLabel));
5293 // Check if target-independent constraints permit a tail call here.
5294 // Target-dependent constraints are checked within TLI.LowerCallTo.
5296 !isInTailCallPosition(CS, CS.getAttributes().getRetAttributes(), TLI))
5299 // If there's a possibility that fast-isel has already selected some amount
5300 // of the current basic block, don't emit a tail call.
5301 if (isTailCall && TM.Options.EnableFastISel)
5305 CallLoweringInfo CLI(getRoot(), RetTy, FTy, isTailCall, Callee, Args, DAG,
5306 getCurDebugLoc(), CS);
5307 std::pair<SDValue,SDValue> Result = TLI.LowerCallTo(CLI);
5308 assert((isTailCall || Result.second.getNode()) &&
5309 "Non-null chain expected with non-tail call!");
5310 assert((Result.second.getNode() || !Result.first.getNode()) &&
5311 "Null value expected with tail call!");
5312 if (Result.first.getNode()) {
5313 setValue(CS.getInstruction(), Result.first);
5314 } else if (!CanLowerReturn && Result.second.getNode()) {
5315 // The instruction result is the result of loading from the
5316 // hidden sret parameter.
5317 SmallVector<EVT, 1> PVTs;
5318 Type *PtrRetTy = PointerType::getUnqual(FTy->getReturnType());
5320 ComputeValueVTs(TLI, PtrRetTy, PVTs);
5321 assert(PVTs.size() == 1 && "Pointers should fit in one register");
5322 EVT PtrVT = PVTs[0];
5324 SmallVector<EVT, 4> RetTys;
5325 SmallVector<uint64_t, 4> Offsets;
5326 RetTy = FTy->getReturnType();
5327 ComputeValueVTs(TLI, RetTy, RetTys, &Offsets);
5329 unsigned NumValues = RetTys.size();
5330 SmallVector<SDValue, 4> Values(NumValues);
5331 SmallVector<SDValue, 4> Chains(NumValues);
5333 for (unsigned i = 0; i < NumValues; ++i) {
5334 SDValue Add = DAG.getNode(ISD::ADD, getCurDebugLoc(), PtrVT,
5336 DAG.getConstant(Offsets[i], PtrVT));
5337 SDValue L = DAG.getLoad(RetTys[i], getCurDebugLoc(), Result.second, Add,
5338 MachinePointerInfo::getFixedStack(DemoteStackIdx, Offsets[i]),
5339 false, false, false, 1);
5341 Chains[i] = L.getValue(1);
5344 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(),
5345 MVT::Other, &Chains[0], NumValues);
5346 PendingLoads.push_back(Chain);
5348 setValue(CS.getInstruction(),
5349 DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(),
5350 DAG.getVTList(&RetTys[0], RetTys.size()),
5351 &Values[0], Values.size()));
5354 // Assign order to nodes here. If the call does not produce a result, it won't
5355 // be mapped to a SDNode and visit() will not assign it an order number.
5356 if (!Result.second.getNode()) {
5357 // As a special case, a null chain means that a tail call has been emitted and
5358 // the DAG root is already updated.
5361 AssignOrderingToNode(DAG.getRoot().getNode());
5363 DAG.setRoot(Result.second);
5365 AssignOrderingToNode(Result.second.getNode());
5369 // Insert a label at the end of the invoke call to mark the try range. This
5370 // can be used to detect deletion of the invoke via the MachineModuleInfo.
5371 MCSymbol *EndLabel = MMI.getContext().CreateTempSymbol();
5372 DAG.setRoot(DAG.getEHLabel(getCurDebugLoc(), getRoot(), EndLabel));
5374 // Inform MachineModuleInfo of range.
5375 MMI.addInvoke(LandingPad, BeginLabel, EndLabel);
5379 /// IsOnlyUsedInZeroEqualityComparison - Return true if it only matters that the
5380 /// value is equal or not-equal to zero.
5381 static bool IsOnlyUsedInZeroEqualityComparison(const Value *V) {
5382 for (Value::const_use_iterator UI = V->use_begin(), E = V->use_end();
5384 if (const ICmpInst *IC = dyn_cast<ICmpInst>(*UI))
5385 if (IC->isEquality())
5386 if (const Constant *C = dyn_cast<Constant>(IC->getOperand(1)))
5387 if (C->isNullValue())
5389 // Unknown instruction.
5395 static SDValue getMemCmpLoad(const Value *PtrVal, MVT LoadVT,
5397 SelectionDAGBuilder &Builder) {
5399 // Check to see if this load can be trivially constant folded, e.g. if the
5400 // input is from a string literal.
5401 if (const Constant *LoadInput = dyn_cast<Constant>(PtrVal)) {
5402 // Cast pointer to the type we really want to load.
5403 LoadInput = ConstantExpr::getBitCast(const_cast<Constant *>(LoadInput),
5404 PointerType::getUnqual(LoadTy));
5406 if (const Constant *LoadCst =
5407 ConstantFoldLoadFromConstPtr(const_cast<Constant *>(LoadInput),
5409 return Builder.getValue(LoadCst);
5412 // Otherwise, we have to emit the load. If the pointer is to unfoldable but
5413 // still constant memory, the input chain can be the entry node.
5415 bool ConstantMemory = false;
5417 // Do not serialize (non-volatile) loads of constant memory with anything.
5418 if (Builder.AA->pointsToConstantMemory(PtrVal)) {
5419 Root = Builder.DAG.getEntryNode();
5420 ConstantMemory = true;
5422 // Do not serialize non-volatile loads against each other.
5423 Root = Builder.DAG.getRoot();
5426 SDValue Ptr = Builder.getValue(PtrVal);
5427 SDValue LoadVal = Builder.DAG.getLoad(LoadVT, Builder.getCurDebugLoc(), Root,
5428 Ptr, MachinePointerInfo(PtrVal),
5430 false /*nontemporal*/,
5431 false /*isinvariant*/, 1 /* align=1 */);
5433 if (!ConstantMemory)
5434 Builder.PendingLoads.push_back(LoadVal.getValue(1));
5439 /// visitMemCmpCall - See if we can lower a call to memcmp in an optimized form.
5440 /// If so, return true and lower it, otherwise return false and it will be
5441 /// lowered like a normal call.
5442 bool SelectionDAGBuilder::visitMemCmpCall(const CallInst &I) {
5443 // Verify that the prototype makes sense. int memcmp(void*,void*,size_t)
5444 if (I.getNumArgOperands() != 3)
5447 const Value *LHS = I.getArgOperand(0), *RHS = I.getArgOperand(1);
5448 if (!LHS->getType()->isPointerTy() || !RHS->getType()->isPointerTy() ||
5449 !I.getArgOperand(2)->getType()->isIntegerTy() ||
5450 !I.getType()->isIntegerTy())
5453 const ConstantInt *Size = dyn_cast<ConstantInt>(I.getArgOperand(2));
5455 // memcmp(S1,S2,2) != 0 -> (*(short*)LHS != *(short*)RHS) != 0
5456 // memcmp(S1,S2,4) != 0 -> (*(int*)LHS != *(int*)RHS) != 0
5457 if (Size && IsOnlyUsedInZeroEqualityComparison(&I)) {
5458 bool ActuallyDoIt = true;
5461 switch (Size->getZExtValue()) {
5463 LoadVT = MVT::Other;
5465 ActuallyDoIt = false;
5469 LoadTy = Type::getInt16Ty(Size->getContext());
5473 LoadTy = Type::getInt32Ty(Size->getContext());
5477 LoadTy = Type::getInt64Ty(Size->getContext());
5481 LoadVT = MVT::v4i32;
5482 LoadTy = Type::getInt32Ty(Size->getContext());
5483 LoadTy = VectorType::get(LoadTy, 4);
5488 // This turns into unaligned loads. We only do this if the target natively
5489 // supports the MVT we'll be loading or if it is small enough (<= 4) that
5490 // we'll only produce a small number of byte loads.
5492 // Require that we can find a legal MVT, and only do this if the target
5493 // supports unaligned loads of that type. Expanding into byte loads would
5495 if (ActuallyDoIt && Size->getZExtValue() > 4) {
5496 // TODO: Handle 5 byte compare as 4-byte + 1 byte.
5497 // TODO: Handle 8 byte compare on x86-32 as two 32-bit loads.
5498 if (!TLI.isTypeLegal(LoadVT) ||!TLI.allowsUnalignedMemoryAccesses(LoadVT))
5499 ActuallyDoIt = false;
5503 SDValue LHSVal = getMemCmpLoad(LHS, LoadVT, LoadTy, *this);
5504 SDValue RHSVal = getMemCmpLoad(RHS, LoadVT, LoadTy, *this);
5506 SDValue Res = DAG.getSetCC(getCurDebugLoc(), MVT::i1, LHSVal, RHSVal,
5508 EVT CallVT = TLI.getValueType(I.getType(), true);
5509 setValue(&I, DAG.getZExtOrTrunc(Res, getCurDebugLoc(), CallVT));
5518 /// visitUnaryFloatCall - If a call instruction is a unary floating-point
5519 /// operation (as expected), translate it to an SDNode with the specified opcode
5520 /// and return true.
5521 bool SelectionDAGBuilder::visitUnaryFloatCall(const CallInst &I,
5523 // Sanity check that it really is a unary floating-point call.
5524 if (I.getNumArgOperands() != 1 ||
5525 !I.getArgOperand(0)->getType()->isFloatingPointTy() ||
5526 I.getType() != I.getArgOperand(0)->getType() ||
5527 !I.onlyReadsMemory())
5530 SDValue Tmp = getValue(I.getArgOperand(0));
5531 setValue(&I, DAG.getNode(Opcode, getCurDebugLoc(), Tmp.getValueType(), Tmp));
5535 void SelectionDAGBuilder::visitCall(const CallInst &I) {
5536 // Handle inline assembly differently.
5537 if (isa<InlineAsm>(I.getCalledValue())) {
5542 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
5543 ComputeUsesVAFloatArgument(I, &MMI);
5545 const char *RenameFn = 0;
5546 if (Function *F = I.getCalledFunction()) {
5547 if (F->isDeclaration()) {
5548 if (const TargetIntrinsicInfo *II = TM.getIntrinsicInfo()) {
5549 if (unsigned IID = II->getIntrinsicID(F)) {
5550 RenameFn = visitIntrinsicCall(I, IID);
5555 if (unsigned IID = F->getIntrinsicID()) {
5556 RenameFn = visitIntrinsicCall(I, IID);
5562 // Check for well-known libc/libm calls. If the function is internal, it
5563 // can't be a library call.
5565 if (!F->hasLocalLinkage() && F->hasName() &&
5566 LibInfo->getLibFunc(F->getName(), Func) &&
5567 LibInfo->hasOptimizedCodeGen(Func)) {
5570 case LibFunc::copysign:
5571 case LibFunc::copysignf:
5572 case LibFunc::copysignl:
5573 if (I.getNumArgOperands() == 2 && // Basic sanity checks.
5574 I.getArgOperand(0)->getType()->isFloatingPointTy() &&
5575 I.getType() == I.getArgOperand(0)->getType() &&
5576 I.getType() == I.getArgOperand(1)->getType() &&
5577 I.onlyReadsMemory()) {
5578 SDValue LHS = getValue(I.getArgOperand(0));
5579 SDValue RHS = getValue(I.getArgOperand(1));
5580 setValue(&I, DAG.getNode(ISD::FCOPYSIGN, getCurDebugLoc(),
5581 LHS.getValueType(), LHS, RHS));
5586 case LibFunc::fabsf:
5587 case LibFunc::fabsl:
5588 if (visitUnaryFloatCall(I, ISD::FABS))
5594 if (visitUnaryFloatCall(I, ISD::FSIN))
5600 if (visitUnaryFloatCall(I, ISD::FCOS))
5604 case LibFunc::sqrtf:
5605 case LibFunc::sqrtl:
5606 if (visitUnaryFloatCall(I, ISD::FSQRT))
5609 case LibFunc::floor:
5610 case LibFunc::floorf:
5611 case LibFunc::floorl:
5612 if (visitUnaryFloatCall(I, ISD::FFLOOR))
5615 case LibFunc::nearbyint:
5616 case LibFunc::nearbyintf:
5617 case LibFunc::nearbyintl:
5618 if (visitUnaryFloatCall(I, ISD::FNEARBYINT))
5622 case LibFunc::ceilf:
5623 case LibFunc::ceill:
5624 if (visitUnaryFloatCall(I, ISD::FCEIL))
5628 case LibFunc::rintf:
5629 case LibFunc::rintl:
5630 if (visitUnaryFloatCall(I, ISD::FRINT))
5633 case LibFunc::trunc:
5634 case LibFunc::truncf:
5635 case LibFunc::truncl:
5636 if (visitUnaryFloatCall(I, ISD::FTRUNC))
5640 case LibFunc::log2f:
5641 case LibFunc::log2l:
5642 if (visitUnaryFloatCall(I, ISD::FLOG2))
5646 case LibFunc::exp2f:
5647 case LibFunc::exp2l:
5648 if (visitUnaryFloatCall(I, ISD::FEXP2))
5651 case LibFunc::memcmp:
5652 if (visitMemCmpCall(I))
5661 Callee = getValue(I.getCalledValue());
5663 Callee = DAG.getExternalSymbol(RenameFn, TLI.getPointerTy());
5665 // Check if we can potentially perform a tail call. More detailed checking is
5666 // be done within LowerCallTo, after more information about the call is known.
5667 LowerCallTo(&I, Callee, I.isTailCall());
5672 /// AsmOperandInfo - This contains information for each constraint that we are
5674 class SDISelAsmOperandInfo : public TargetLowering::AsmOperandInfo {
5676 /// CallOperand - If this is the result output operand or a clobber
5677 /// this is null, otherwise it is the incoming operand to the CallInst.
5678 /// This gets modified as the asm is processed.
5679 SDValue CallOperand;
5681 /// AssignedRegs - If this is a register or register class operand, this
5682 /// contains the set of register corresponding to the operand.
5683 RegsForValue AssignedRegs;
5685 explicit SDISelAsmOperandInfo(const TargetLowering::AsmOperandInfo &info)
5686 : TargetLowering::AsmOperandInfo(info), CallOperand(0,0) {
5689 /// getCallOperandValEVT - Return the EVT of the Value* that this operand
5690 /// corresponds to. If there is no Value* for this operand, it returns
5692 EVT getCallOperandValEVT(LLVMContext &Context,
5693 const TargetLowering &TLI,
5694 const TargetData *TD) const {
5695 if (CallOperandVal == 0) return MVT::Other;
5697 if (isa<BasicBlock>(CallOperandVal))
5698 return TLI.getPointerTy();
5700 llvm::Type *OpTy = CallOperandVal->getType();
5702 // FIXME: code duplicated from TargetLowering::ParseConstraints().
5703 // If this is an indirect operand, the operand is a pointer to the
5706 llvm::PointerType *PtrTy = dyn_cast<PointerType>(OpTy);
5708 report_fatal_error("Indirect operand for inline asm not a pointer!");
5709 OpTy = PtrTy->getElementType();
5712 // Look for vector wrapped in a struct. e.g. { <16 x i8> }.
5713 if (StructType *STy = dyn_cast<StructType>(OpTy))
5714 if (STy->getNumElements() == 1)
5715 OpTy = STy->getElementType(0);
5717 // If OpTy is not a single value, it may be a struct/union that we
5718 // can tile with integers.
5719 if (!OpTy->isSingleValueType() && OpTy->isSized()) {
5720 unsigned BitSize = TD->getTypeSizeInBits(OpTy);
5729 OpTy = IntegerType::get(Context, BitSize);
5734 return TLI.getValueType(OpTy, true);
5738 typedef SmallVector<SDISelAsmOperandInfo,16> SDISelAsmOperandInfoVector;
5740 } // end anonymous namespace
5742 /// GetRegistersForValue - Assign registers (virtual or physical) for the
5743 /// specified operand. We prefer to assign virtual registers, to allow the
5744 /// register allocator to handle the assignment process. However, if the asm
5745 /// uses features that we can't model on machineinstrs, we have SDISel do the
5746 /// allocation. This produces generally horrible, but correct, code.
5748 /// OpInfo describes the operand.
5750 static void GetRegistersForValue(SelectionDAG &DAG,
5751 const TargetLowering &TLI,
5753 SDISelAsmOperandInfo &OpInfo) {
5754 LLVMContext &Context = *DAG.getContext();
5756 MachineFunction &MF = DAG.getMachineFunction();
5757 SmallVector<unsigned, 4> Regs;
5759 // If this is a constraint for a single physreg, or a constraint for a
5760 // register class, find it.
5761 std::pair<unsigned, const TargetRegisterClass*> PhysReg =
5762 TLI.getRegForInlineAsmConstraint(OpInfo.ConstraintCode,
5763 OpInfo.ConstraintVT);
5765 unsigned NumRegs = 1;
5766 if (OpInfo.ConstraintVT != MVT::Other) {
5767 // If this is a FP input in an integer register (or visa versa) insert a bit
5768 // cast of the input value. More generally, handle any case where the input
5769 // value disagrees with the register class we plan to stick this in.
5770 if (OpInfo.Type == InlineAsm::isInput &&
5771 PhysReg.second && !PhysReg.second->hasType(OpInfo.ConstraintVT)) {
5772 // Try to convert to the first EVT that the reg class contains. If the
5773 // types are identical size, use a bitcast to convert (e.g. two differing
5775 EVT RegVT = *PhysReg.second->vt_begin();
5776 if (RegVT.getSizeInBits() == OpInfo.ConstraintVT.getSizeInBits()) {
5777 OpInfo.CallOperand = DAG.getNode(ISD::BITCAST, DL,
5778 RegVT, OpInfo.CallOperand);
5779 OpInfo.ConstraintVT = RegVT;
5780 } else if (RegVT.isInteger() && OpInfo.ConstraintVT.isFloatingPoint()) {
5781 // If the input is a FP value and we want it in FP registers, do a
5782 // bitcast to the corresponding integer type. This turns an f64 value
5783 // into i64, which can be passed with two i32 values on a 32-bit
5785 RegVT = EVT::getIntegerVT(Context,
5786 OpInfo.ConstraintVT.getSizeInBits());
5787 OpInfo.CallOperand = DAG.getNode(ISD::BITCAST, DL,
5788 RegVT, OpInfo.CallOperand);
5789 OpInfo.ConstraintVT = RegVT;
5793 NumRegs = TLI.getNumRegisters(Context, OpInfo.ConstraintVT);
5797 EVT ValueVT = OpInfo.ConstraintVT;
5799 // If this is a constraint for a specific physical register, like {r17},
5801 if (unsigned AssignedReg = PhysReg.first) {
5802 const TargetRegisterClass *RC = PhysReg.second;
5803 if (OpInfo.ConstraintVT == MVT::Other)
5804 ValueVT = *RC->vt_begin();
5806 // Get the actual register value type. This is important, because the user
5807 // may have asked for (e.g.) the AX register in i32 type. We need to
5808 // remember that AX is actually i16 to get the right extension.
5809 RegVT = *RC->vt_begin();
5811 // This is a explicit reference to a physical register.
5812 Regs.push_back(AssignedReg);
5814 // If this is an expanded reference, add the rest of the regs to Regs.
5816 TargetRegisterClass::iterator I = RC->begin();
5817 for (; *I != AssignedReg; ++I)
5818 assert(I != RC->end() && "Didn't find reg!");
5820 // Already added the first reg.
5822 for (; NumRegs; --NumRegs, ++I) {
5823 assert(I != RC->end() && "Ran out of registers to allocate!");
5828 OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT);
5832 // Otherwise, if this was a reference to an LLVM register class, create vregs
5833 // for this reference.
5834 if (const TargetRegisterClass *RC = PhysReg.second) {
5835 RegVT = *RC->vt_begin();
5836 if (OpInfo.ConstraintVT == MVT::Other)
5839 // Create the appropriate number of virtual registers.
5840 MachineRegisterInfo &RegInfo = MF.getRegInfo();
5841 for (; NumRegs; --NumRegs)
5842 Regs.push_back(RegInfo.createVirtualRegister(RC));
5844 OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT);
5848 // Otherwise, we couldn't allocate enough registers for this.
5851 /// visitInlineAsm - Handle a call to an InlineAsm object.
5853 void SelectionDAGBuilder::visitInlineAsm(ImmutableCallSite CS) {
5854 const InlineAsm *IA = cast<InlineAsm>(CS.getCalledValue());
5856 /// ConstraintOperands - Information about all of the constraints.
5857 SDISelAsmOperandInfoVector ConstraintOperands;
5859 TargetLowering::AsmOperandInfoVector
5860 TargetConstraints = TLI.ParseConstraints(CS);
5862 bool hasMemory = false;
5864 unsigned ArgNo = 0; // ArgNo - The argument of the CallInst.
5865 unsigned ResNo = 0; // ResNo - The result number of the next output.
5866 for (unsigned i = 0, e = TargetConstraints.size(); i != e; ++i) {
5867 ConstraintOperands.push_back(SDISelAsmOperandInfo(TargetConstraints[i]));
5868 SDISelAsmOperandInfo &OpInfo = ConstraintOperands.back();
5870 EVT OpVT = MVT::Other;
5872 // Compute the value type for each operand.
5873 switch (OpInfo.Type) {
5874 case InlineAsm::isOutput:
5875 // Indirect outputs just consume an argument.
5876 if (OpInfo.isIndirect) {
5877 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++));
5881 // The return value of the call is this value. As such, there is no
5882 // corresponding argument.
5883 assert(!CS.getType()->isVoidTy() && "Bad inline asm!");
5884 if (StructType *STy = dyn_cast<StructType>(CS.getType())) {
5885 OpVT = TLI.getValueType(STy->getElementType(ResNo));
5887 assert(ResNo == 0 && "Asm only has one result!");
5888 OpVT = TLI.getValueType(CS.getType());
5892 case InlineAsm::isInput:
5893 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++));
5895 case InlineAsm::isClobber:
5900 // If this is an input or an indirect output, process the call argument.
5901 // BasicBlocks are labels, currently appearing only in asm's.
5902 if (OpInfo.CallOperandVal) {
5903 if (const BasicBlock *BB = dyn_cast<BasicBlock>(OpInfo.CallOperandVal)) {
5904 OpInfo.CallOperand = DAG.getBasicBlock(FuncInfo.MBBMap[BB]);
5906 OpInfo.CallOperand = getValue(OpInfo.CallOperandVal);
5909 OpVT = OpInfo.getCallOperandValEVT(*DAG.getContext(), TLI, TD);
5912 OpInfo.ConstraintVT = OpVT;
5914 // Indirect operand accesses access memory.
5915 if (OpInfo.isIndirect)
5918 for (unsigned j = 0, ee = OpInfo.Codes.size(); j != ee; ++j) {
5919 TargetLowering::ConstraintType
5920 CType = TLI.getConstraintType(OpInfo.Codes[j]);
5921 if (CType == TargetLowering::C_Memory) {
5929 SDValue Chain, Flag;
5931 // We won't need to flush pending loads if this asm doesn't touch
5932 // memory and is nonvolatile.
5933 if (hasMemory || IA->hasSideEffects())
5936 Chain = DAG.getRoot();
5938 // Second pass over the constraints: compute which constraint option to use
5939 // and assign registers to constraints that want a specific physreg.
5940 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
5941 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
5943 // If this is an output operand with a matching input operand, look up the
5944 // matching input. If their types mismatch, e.g. one is an integer, the
5945 // other is floating point, or their sizes are different, flag it as an
5947 if (OpInfo.hasMatchingInput()) {
5948 SDISelAsmOperandInfo &Input = ConstraintOperands[OpInfo.MatchingInput];
5950 if (OpInfo.ConstraintVT != Input.ConstraintVT) {
5951 std::pair<unsigned, const TargetRegisterClass*> MatchRC =
5952 TLI.getRegForInlineAsmConstraint(OpInfo.ConstraintCode,
5953 OpInfo.ConstraintVT);
5954 std::pair<unsigned, const TargetRegisterClass*> InputRC =
5955 TLI.getRegForInlineAsmConstraint(Input.ConstraintCode,
5956 Input.ConstraintVT);
5957 if ((OpInfo.ConstraintVT.isInteger() !=
5958 Input.ConstraintVT.isInteger()) ||
5959 (MatchRC.second != InputRC.second)) {
5960 report_fatal_error("Unsupported asm: input constraint"
5961 " with a matching output constraint of"
5962 " incompatible type!");
5964 Input.ConstraintVT = OpInfo.ConstraintVT;
5968 // Compute the constraint code and ConstraintType to use.
5969 TLI.ComputeConstraintToUse(OpInfo, OpInfo.CallOperand, &DAG);
5971 // If this is a memory input, and if the operand is not indirect, do what we
5972 // need to to provide an address for the memory input.
5973 if (OpInfo.ConstraintType == TargetLowering::C_Memory &&
5974 !OpInfo.isIndirect) {
5975 assert((OpInfo.isMultipleAlternative ||
5976 (OpInfo.Type == InlineAsm::isInput)) &&
5977 "Can only indirectify direct input operands!");
5979 // Memory operands really want the address of the value. If we don't have
5980 // an indirect input, put it in the constpool if we can, otherwise spill
5981 // it to a stack slot.
5982 // TODO: This isn't quite right. We need to handle these according to
5983 // the addressing mode that the constraint wants. Also, this may take
5984 // an additional register for the computation and we don't want that
5987 // If the operand is a float, integer, or vector constant, spill to a
5988 // constant pool entry to get its address.
5989 const Value *OpVal = OpInfo.CallOperandVal;
5990 if (isa<ConstantFP>(OpVal) || isa<ConstantInt>(OpVal) ||
5991 isa<ConstantVector>(OpVal) || isa<ConstantDataVector>(OpVal)) {
5992 OpInfo.CallOperand = DAG.getConstantPool(cast<Constant>(OpVal),
5993 TLI.getPointerTy());
5995 // Otherwise, create a stack slot and emit a store to it before the
5997 Type *Ty = OpVal->getType();
5998 uint64_t TySize = TLI.getTargetData()->getTypeAllocSize(Ty);
5999 unsigned Align = TLI.getTargetData()->getPrefTypeAlignment(Ty);
6000 MachineFunction &MF = DAG.getMachineFunction();
6001 int SSFI = MF.getFrameInfo()->CreateStackObject(TySize, Align, false);
6002 SDValue StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy());
6003 Chain = DAG.getStore(Chain, getCurDebugLoc(),
6004 OpInfo.CallOperand, StackSlot,
6005 MachinePointerInfo::getFixedStack(SSFI),
6007 OpInfo.CallOperand = StackSlot;
6010 // There is no longer a Value* corresponding to this operand.
6011 OpInfo.CallOperandVal = 0;
6013 // It is now an indirect operand.
6014 OpInfo.isIndirect = true;
6017 // If this constraint is for a specific register, allocate it before
6019 if (OpInfo.ConstraintType == TargetLowering::C_Register)
6020 GetRegistersForValue(DAG, TLI, getCurDebugLoc(), OpInfo);
6023 // Second pass - Loop over all of the operands, assigning virtual or physregs
6024 // to register class operands.
6025 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
6026 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
6028 // C_Register operands have already been allocated, Other/Memory don't need
6030 if (OpInfo.ConstraintType == TargetLowering::C_RegisterClass)
6031 GetRegistersForValue(DAG, TLI, getCurDebugLoc(), OpInfo);
6034 // AsmNodeOperands - The operands for the ISD::INLINEASM node.
6035 std::vector<SDValue> AsmNodeOperands;
6036 AsmNodeOperands.push_back(SDValue()); // reserve space for input chain
6037 AsmNodeOperands.push_back(
6038 DAG.getTargetExternalSymbol(IA->getAsmString().c_str(),
6039 TLI.getPointerTy()));
6041 // If we have a !srcloc metadata node associated with it, we want to attach
6042 // this to the ultimately generated inline asm machineinstr. To do this, we
6043 // pass in the third operand as this (potentially null) inline asm MDNode.
6044 const MDNode *SrcLoc = CS.getInstruction()->getMetadata("srcloc");
6045 AsmNodeOperands.push_back(DAG.getMDNode(SrcLoc));
6047 // Remember the HasSideEffect and AlignStack bits as operand 3.
6048 unsigned ExtraInfo = 0;
6049 if (IA->hasSideEffects())
6050 ExtraInfo |= InlineAsm::Extra_HasSideEffects;
6051 if (IA->isAlignStack())
6052 ExtraInfo |= InlineAsm::Extra_IsAlignStack;
6053 AsmNodeOperands.push_back(DAG.getTargetConstant(ExtraInfo,
6054 TLI.getPointerTy()));
6056 // Loop over all of the inputs, copying the operand values into the
6057 // appropriate registers and processing the output regs.
6058 RegsForValue RetValRegs;
6060 // IndirectStoresToEmit - The set of stores to emit after the inline asm node.
6061 std::vector<std::pair<RegsForValue, Value*> > IndirectStoresToEmit;
6063 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
6064 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
6066 switch (OpInfo.Type) {
6067 case InlineAsm::isOutput: {
6068 if (OpInfo.ConstraintType != TargetLowering::C_RegisterClass &&
6069 OpInfo.ConstraintType != TargetLowering::C_Register) {
6070 // Memory output, or 'other' output (e.g. 'X' constraint).
6071 assert(OpInfo.isIndirect && "Memory output must be indirect operand");
6073 // Add information to the INLINEASM node to know about this output.
6074 unsigned OpFlags = InlineAsm::getFlagWord(InlineAsm::Kind_Mem, 1);
6075 AsmNodeOperands.push_back(DAG.getTargetConstant(OpFlags,
6076 TLI.getPointerTy()));
6077 AsmNodeOperands.push_back(OpInfo.CallOperand);
6081 // Otherwise, this is a register or register class output.
6083 // Copy the output from the appropriate register. Find a register that
6085 if (OpInfo.AssignedRegs.Regs.empty()) {
6086 LLVMContext &Ctx = *DAG.getContext();
6087 Ctx.emitError(CS.getInstruction(),
6088 "couldn't allocate output register for constraint '" +
6089 Twine(OpInfo.ConstraintCode) + "'");
6093 // If this is an indirect operand, store through the pointer after the
6095 if (OpInfo.isIndirect) {
6096 IndirectStoresToEmit.push_back(std::make_pair(OpInfo.AssignedRegs,
6097 OpInfo.CallOperandVal));
6099 // This is the result value of the call.
6100 assert(!CS.getType()->isVoidTy() && "Bad inline asm!");
6101 // Concatenate this output onto the outputs list.
6102 RetValRegs.append(OpInfo.AssignedRegs);
6105 // Add information to the INLINEASM node to know that this register is
6107 OpInfo.AssignedRegs.AddInlineAsmOperands(OpInfo.isEarlyClobber ?
6108 InlineAsm::Kind_RegDefEarlyClobber :
6109 InlineAsm::Kind_RegDef,
6116 case InlineAsm::isInput: {
6117 SDValue InOperandVal = OpInfo.CallOperand;
6119 if (OpInfo.isMatchingInputConstraint()) { // Matching constraint?
6120 // If this is required to match an output register we have already set,
6121 // just use its register.
6122 unsigned OperandNo = OpInfo.getMatchedOperand();
6124 // Scan until we find the definition we already emitted of this operand.
6125 // When we find it, create a RegsForValue operand.
6126 unsigned CurOp = InlineAsm::Op_FirstOperand;
6127 for (; OperandNo; --OperandNo) {
6128 // Advance to the next operand.
6130 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue();
6131 assert((InlineAsm::isRegDefKind(OpFlag) ||
6132 InlineAsm::isRegDefEarlyClobberKind(OpFlag) ||
6133 InlineAsm::isMemKind(OpFlag)) && "Skipped past definitions?");
6134 CurOp += InlineAsm::getNumOperandRegisters(OpFlag)+1;
6138 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue();
6139 if (InlineAsm::isRegDefKind(OpFlag) ||
6140 InlineAsm::isRegDefEarlyClobberKind(OpFlag)) {
6141 // Add (OpFlag&0xffff)>>3 registers to MatchedRegs.
6142 if (OpInfo.isIndirect) {
6143 // This happens on gcc/testsuite/gcc.dg/pr8788-1.c
6144 LLVMContext &Ctx = *DAG.getContext();
6145 Ctx.emitError(CS.getInstruction(), "inline asm not supported yet:"
6146 " don't know how to handle tied "
6147 "indirect register inputs");
6150 RegsForValue MatchedRegs;
6151 MatchedRegs.ValueVTs.push_back(InOperandVal.getValueType());
6152 EVT RegVT = AsmNodeOperands[CurOp+1].getValueType();
6153 MatchedRegs.RegVTs.push_back(RegVT);
6154 MachineRegisterInfo &RegInfo = DAG.getMachineFunction().getRegInfo();
6155 for (unsigned i = 0, e = InlineAsm::getNumOperandRegisters(OpFlag);
6157 MatchedRegs.Regs.push_back
6158 (RegInfo.createVirtualRegister(TLI.getRegClassFor(RegVT)));
6160 // Use the produced MatchedRegs object to
6161 MatchedRegs.getCopyToRegs(InOperandVal, DAG, getCurDebugLoc(),
6163 MatchedRegs.AddInlineAsmOperands(InlineAsm::Kind_RegUse,
6164 true, OpInfo.getMatchedOperand(),
6165 DAG, AsmNodeOperands);
6169 assert(InlineAsm::isMemKind(OpFlag) && "Unknown matching constraint!");
6170 assert(InlineAsm::getNumOperandRegisters(OpFlag) == 1 &&
6171 "Unexpected number of operands");
6172 // Add information to the INLINEASM node to know about this input.
6173 // See InlineAsm.h isUseOperandTiedToDef.
6174 OpFlag = InlineAsm::getFlagWordForMatchingOp(OpFlag,
6175 OpInfo.getMatchedOperand());
6176 AsmNodeOperands.push_back(DAG.getTargetConstant(OpFlag,
6177 TLI.getPointerTy()));
6178 AsmNodeOperands.push_back(AsmNodeOperands[CurOp+1]);
6182 // Treat indirect 'X' constraint as memory.
6183 if (OpInfo.ConstraintType == TargetLowering::C_Other &&
6185 OpInfo.ConstraintType = TargetLowering::C_Memory;
6187 if (OpInfo.ConstraintType == TargetLowering::C_Other) {
6188 std::vector<SDValue> Ops;
6189 TLI.LowerAsmOperandForConstraint(InOperandVal, OpInfo.ConstraintCode,
6192 LLVMContext &Ctx = *DAG.getContext();
6193 Ctx.emitError(CS.getInstruction(),
6194 "invalid operand for inline asm constraint '" +
6195 Twine(OpInfo.ConstraintCode) + "'");
6199 // Add information to the INLINEASM node to know about this input.
6200 unsigned ResOpType =
6201 InlineAsm::getFlagWord(InlineAsm::Kind_Imm, Ops.size());
6202 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
6203 TLI.getPointerTy()));
6204 AsmNodeOperands.insert(AsmNodeOperands.end(), Ops.begin(), Ops.end());
6208 if (OpInfo.ConstraintType == TargetLowering::C_Memory) {
6209 assert(OpInfo.isIndirect && "Operand must be indirect to be a mem!");
6210 assert(InOperandVal.getValueType() == TLI.getPointerTy() &&
6211 "Memory operands expect pointer values");
6213 // Add information to the INLINEASM node to know about this input.
6214 unsigned ResOpType = InlineAsm::getFlagWord(InlineAsm::Kind_Mem, 1);
6215 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
6216 TLI.getPointerTy()));
6217 AsmNodeOperands.push_back(InOperandVal);
6221 assert((OpInfo.ConstraintType == TargetLowering::C_RegisterClass ||
6222 OpInfo.ConstraintType == TargetLowering::C_Register) &&
6223 "Unknown constraint type!");
6225 // TODO: Support this.
6226 if (OpInfo.isIndirect) {
6227 LLVMContext &Ctx = *DAG.getContext();
6228 Ctx.emitError(CS.getInstruction(),
6229 "Don't know how to handle indirect register inputs yet "
6230 "for constraint '" + Twine(OpInfo.ConstraintCode) + "'");
6234 // Copy the input into the appropriate registers.
6235 if (OpInfo.AssignedRegs.Regs.empty()) {
6236 LLVMContext &Ctx = *DAG.getContext();
6237 Ctx.emitError(CS.getInstruction(),
6238 "couldn't allocate input reg for constraint '" +
6239 Twine(OpInfo.ConstraintCode) + "'");
6243 OpInfo.AssignedRegs.getCopyToRegs(InOperandVal, DAG, getCurDebugLoc(),
6246 OpInfo.AssignedRegs.AddInlineAsmOperands(InlineAsm::Kind_RegUse, false, 0,
6247 DAG, AsmNodeOperands);
6250 case InlineAsm::isClobber: {
6251 // Add the clobbered value to the operand list, so that the register
6252 // allocator is aware that the physreg got clobbered.
6253 if (!OpInfo.AssignedRegs.Regs.empty())
6254 OpInfo.AssignedRegs.AddInlineAsmOperands(InlineAsm::Kind_Clobber,
6262 // Finish up input operands. Set the input chain and add the flag last.
6263 AsmNodeOperands[InlineAsm::Op_InputChain] = Chain;
6264 if (Flag.getNode()) AsmNodeOperands.push_back(Flag);
6266 Chain = DAG.getNode(ISD::INLINEASM, getCurDebugLoc(),
6267 DAG.getVTList(MVT::Other, MVT::Glue),
6268 &AsmNodeOperands[0], AsmNodeOperands.size());
6269 Flag = Chain.getValue(1);
6271 // If this asm returns a register value, copy the result from that register
6272 // and set it as the value of the call.
6273 if (!RetValRegs.Regs.empty()) {
6274 SDValue Val = RetValRegs.getCopyFromRegs(DAG, FuncInfo, getCurDebugLoc(),
6277 // FIXME: Why don't we do this for inline asms with MRVs?
6278 if (CS.getType()->isSingleValueType() && CS.getType()->isSized()) {
6279 EVT ResultType = TLI.getValueType(CS.getType());
6281 // If any of the results of the inline asm is a vector, it may have the
6282 // wrong width/num elts. This can happen for register classes that can
6283 // contain multiple different value types. The preg or vreg allocated may
6284 // not have the same VT as was expected. Convert it to the right type
6285 // with bit_convert.
6286 if (ResultType != Val.getValueType() && Val.getValueType().isVector()) {
6287 Val = DAG.getNode(ISD::BITCAST, getCurDebugLoc(),
6290 } else if (ResultType != Val.getValueType() &&
6291 ResultType.isInteger() && Val.getValueType().isInteger()) {
6292 // If a result value was tied to an input value, the computed result may
6293 // have a wider width than the expected result. Extract the relevant
6295 Val = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), ResultType, Val);
6298 assert(ResultType == Val.getValueType() && "Asm result value mismatch!");
6301 setValue(CS.getInstruction(), Val);
6302 // Don't need to use this as a chain in this case.
6303 if (!IA->hasSideEffects() && !hasMemory && IndirectStoresToEmit.empty())
6307 std::vector<std::pair<SDValue, const Value *> > StoresToEmit;
6309 // Process indirect outputs, first output all of the flagged copies out of
6311 for (unsigned i = 0, e = IndirectStoresToEmit.size(); i != e; ++i) {
6312 RegsForValue &OutRegs = IndirectStoresToEmit[i].first;
6313 const Value *Ptr = IndirectStoresToEmit[i].second;
6314 SDValue OutVal = OutRegs.getCopyFromRegs(DAG, FuncInfo, getCurDebugLoc(),
6316 StoresToEmit.push_back(std::make_pair(OutVal, Ptr));
6319 // Emit the non-flagged stores from the physregs.
6320 SmallVector<SDValue, 8> OutChains;
6321 for (unsigned i = 0, e = StoresToEmit.size(); i != e; ++i) {
6322 SDValue Val = DAG.getStore(Chain, getCurDebugLoc(),
6323 StoresToEmit[i].first,
6324 getValue(StoresToEmit[i].second),
6325 MachinePointerInfo(StoresToEmit[i].second),
6327 OutChains.push_back(Val);
6330 if (!OutChains.empty())
6331 Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), MVT::Other,
6332 &OutChains[0], OutChains.size());
6337 void SelectionDAGBuilder::visitVAStart(const CallInst &I) {
6338 DAG.setRoot(DAG.getNode(ISD::VASTART, getCurDebugLoc(),
6339 MVT::Other, getRoot(),
6340 getValue(I.getArgOperand(0)),
6341 DAG.getSrcValue(I.getArgOperand(0))));
6344 void SelectionDAGBuilder::visitVAArg(const VAArgInst &I) {
6345 const TargetData &TD = *TLI.getTargetData();
6346 SDValue V = DAG.getVAArg(TLI.getValueType(I.getType()), getCurDebugLoc(),
6347 getRoot(), getValue(I.getOperand(0)),
6348 DAG.getSrcValue(I.getOperand(0)),
6349 TD.getABITypeAlignment(I.getType()));
6351 DAG.setRoot(V.getValue(1));
6354 void SelectionDAGBuilder::visitVAEnd(const CallInst &I) {
6355 DAG.setRoot(DAG.getNode(ISD::VAEND, getCurDebugLoc(),
6356 MVT::Other, getRoot(),
6357 getValue(I.getArgOperand(0)),
6358 DAG.getSrcValue(I.getArgOperand(0))));
6361 void SelectionDAGBuilder::visitVACopy(const CallInst &I) {
6362 DAG.setRoot(DAG.getNode(ISD::VACOPY, getCurDebugLoc(),
6363 MVT::Other, getRoot(),
6364 getValue(I.getArgOperand(0)),
6365 getValue(I.getArgOperand(1)),
6366 DAG.getSrcValue(I.getArgOperand(0)),
6367 DAG.getSrcValue(I.getArgOperand(1))));
6370 /// TargetLowering::LowerCallTo - This is the default LowerCallTo
6371 /// implementation, which just calls LowerCall.
6372 /// FIXME: When all targets are
6373 /// migrated to using LowerCall, this hook should be integrated into SDISel.
6374 std::pair<SDValue, SDValue>
6375 TargetLowering::LowerCallTo(TargetLowering::CallLoweringInfo &CLI) const {
6376 // Handle all of the outgoing arguments.
6378 CLI.OutVals.clear();
6379 ArgListTy &Args = CLI.Args;
6380 for (unsigned i = 0, e = Args.size(); i != e; ++i) {
6381 SmallVector<EVT, 4> ValueVTs;
6382 ComputeValueVTs(*this, Args[i].Ty, ValueVTs);
6383 for (unsigned Value = 0, NumValues = ValueVTs.size();
6384 Value != NumValues; ++Value) {
6385 EVT VT = ValueVTs[Value];
6386 Type *ArgTy = VT.getTypeForEVT(CLI.RetTy->getContext());
6387 SDValue Op = SDValue(Args[i].Node.getNode(),
6388 Args[i].Node.getResNo() + Value);
6389 ISD::ArgFlagsTy Flags;
6390 unsigned OriginalAlignment =
6391 getTargetData()->getABITypeAlignment(ArgTy);
6397 if (Args[i].isInReg)
6401 if (Args[i].isByVal) {
6403 PointerType *Ty = cast<PointerType>(Args[i].Ty);
6404 Type *ElementTy = Ty->getElementType();
6405 Flags.setByValSize(getTargetData()->getTypeAllocSize(ElementTy));
6406 // For ByVal, alignment should come from FE. BE will guess if this
6407 // info is not there but there are cases it cannot get right.
6408 unsigned FrameAlign;
6409 if (Args[i].Alignment)
6410 FrameAlign = Args[i].Alignment;
6412 FrameAlign = getByValTypeAlignment(ElementTy);
6413 Flags.setByValAlign(FrameAlign);
6417 Flags.setOrigAlign(OriginalAlignment);
6419 EVT PartVT = getRegisterType(CLI.RetTy->getContext(), VT);
6420 unsigned NumParts = getNumRegisters(CLI.RetTy->getContext(), VT);
6421 SmallVector<SDValue, 4> Parts(NumParts);
6422 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
6425 ExtendKind = ISD::SIGN_EXTEND;
6426 else if (Args[i].isZExt)
6427 ExtendKind = ISD::ZERO_EXTEND;
6429 getCopyToParts(CLI.DAG, CLI.DL, Op, &Parts[0], NumParts,
6430 PartVT, ExtendKind);
6432 for (unsigned j = 0; j != NumParts; ++j) {
6433 // if it isn't first piece, alignment must be 1
6434 ISD::OutputArg MyFlags(Flags, Parts[j].getValueType(),
6435 i < CLI.NumFixedArgs);
6436 if (NumParts > 1 && j == 0)
6437 MyFlags.Flags.setSplit();
6439 MyFlags.Flags.setOrigAlign(1);
6441 CLI.Outs.push_back(MyFlags);
6442 CLI.OutVals.push_back(Parts[j]);
6447 // Handle the incoming return values from the call.
6449 SmallVector<EVT, 4> RetTys;
6450 ComputeValueVTs(*this, CLI.RetTy, RetTys);
6451 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
6453 EVT RegisterVT = getRegisterType(CLI.RetTy->getContext(), VT);
6454 unsigned NumRegs = getNumRegisters(CLI.RetTy->getContext(), VT);
6455 for (unsigned i = 0; i != NumRegs; ++i) {
6456 ISD::InputArg MyFlags;
6457 MyFlags.VT = RegisterVT.getSimpleVT();
6458 MyFlags.Used = CLI.IsReturnValueUsed;
6460 MyFlags.Flags.setSExt();
6462 MyFlags.Flags.setZExt();
6464 MyFlags.Flags.setInReg();
6465 CLI.Ins.push_back(MyFlags);
6469 SmallVector<SDValue, 4> InVals;
6470 CLI.Chain = LowerCall(CLI, InVals);
6472 // Verify that the target's LowerCall behaved as expected.
6473 assert(CLI.Chain.getNode() && CLI.Chain.getValueType() == MVT::Other &&
6474 "LowerCall didn't return a valid chain!");
6475 assert((!CLI.IsTailCall || InVals.empty()) &&
6476 "LowerCall emitted a return value for a tail call!");
6477 assert((CLI.IsTailCall || InVals.size() == CLI.Ins.size()) &&
6478 "LowerCall didn't emit the correct number of values!");
6480 // For a tail call, the return value is merely live-out and there aren't
6481 // any nodes in the DAG representing it. Return a special value to
6482 // indicate that a tail call has been emitted and no more Instructions
6483 // should be processed in the current block.
6484 if (CLI.IsTailCall) {
6485 CLI.DAG.setRoot(CLI.Chain);
6486 return std::make_pair(SDValue(), SDValue());
6489 DEBUG(for (unsigned i = 0, e = CLI.Ins.size(); i != e; ++i) {
6490 assert(InVals[i].getNode() &&
6491 "LowerCall emitted a null value!");
6492 assert(EVT(CLI.Ins[i].VT) == InVals[i].getValueType() &&
6493 "LowerCall emitted a value with the wrong type!");
6496 // Collect the legal value parts into potentially illegal values
6497 // that correspond to the original function's return values.
6498 ISD::NodeType AssertOp = ISD::DELETED_NODE;
6500 AssertOp = ISD::AssertSext;
6501 else if (CLI.RetZExt)
6502 AssertOp = ISD::AssertZext;
6503 SmallVector<SDValue, 4> ReturnValues;
6504 unsigned CurReg = 0;
6505 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
6507 EVT RegisterVT = getRegisterType(CLI.RetTy->getContext(), VT);
6508 unsigned NumRegs = getNumRegisters(CLI.RetTy->getContext(), VT);
6510 ReturnValues.push_back(getCopyFromParts(CLI.DAG, CLI.DL, &InVals[CurReg],
6511 NumRegs, RegisterVT, VT,
6516 // For a function returning void, there is no return value. We can't create
6517 // such a node, so we just return a null return value in that case. In
6518 // that case, nothing will actually look at the value.
6519 if (ReturnValues.empty())
6520 return std::make_pair(SDValue(), CLI.Chain);
6522 SDValue Res = CLI.DAG.getNode(ISD::MERGE_VALUES, CLI.DL,
6523 CLI.DAG.getVTList(&RetTys[0], RetTys.size()),
6524 &ReturnValues[0], ReturnValues.size());
6525 return std::make_pair(Res, CLI.Chain);
6528 void TargetLowering::LowerOperationWrapper(SDNode *N,
6529 SmallVectorImpl<SDValue> &Results,
6530 SelectionDAG &DAG) const {
6531 SDValue Res = LowerOperation(SDValue(N, 0), DAG);
6533 Results.push_back(Res);
6536 SDValue TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
6537 llvm_unreachable("LowerOperation not implemented for this target!");
6541 SelectionDAGBuilder::CopyValueToVirtualRegister(const Value *V, unsigned Reg) {
6542 SDValue Op = getNonRegisterValue(V);
6543 assert((Op.getOpcode() != ISD::CopyFromReg ||
6544 cast<RegisterSDNode>(Op.getOperand(1))->getReg() != Reg) &&
6545 "Copy from a reg to the same reg!");
6546 assert(!TargetRegisterInfo::isPhysicalRegister(Reg) && "Is a physreg");
6548 RegsForValue RFV(V->getContext(), TLI, Reg, V->getType());
6549 SDValue Chain = DAG.getEntryNode();
6550 RFV.getCopyToRegs(Op, DAG, getCurDebugLoc(), Chain, 0);
6551 PendingExports.push_back(Chain);
6554 #include "llvm/CodeGen/SelectionDAGISel.h"
6556 /// isOnlyUsedInEntryBlock - If the specified argument is only used in the
6557 /// entry block, return true. This includes arguments used by switches, since
6558 /// the switch may expand into multiple basic blocks.
6559 static bool isOnlyUsedInEntryBlock(const Argument *A, bool FastISel) {
6560 // With FastISel active, we may be splitting blocks, so force creation
6561 // of virtual registers for all non-dead arguments.
6563 return A->use_empty();
6565 const BasicBlock *Entry = A->getParent()->begin();
6566 for (Value::const_use_iterator UI = A->use_begin(), E = A->use_end();
6568 const User *U = *UI;
6569 if (cast<Instruction>(U)->getParent() != Entry || isa<SwitchInst>(U))
6570 return false; // Use not in entry block.
6575 void SelectionDAGISel::LowerArguments(const BasicBlock *LLVMBB) {
6576 // If this is the entry block, emit arguments.
6577 const Function &F = *LLVMBB->getParent();
6578 SelectionDAG &DAG = SDB->DAG;
6579 DebugLoc dl = SDB->getCurDebugLoc();
6580 const TargetData *TD = TLI.getTargetData();
6581 SmallVector<ISD::InputArg, 16> Ins;
6583 // Check whether the function can return without sret-demotion.
6584 SmallVector<ISD::OutputArg, 4> Outs;
6585 GetReturnInfo(F.getReturnType(), F.getAttributes().getRetAttributes(),
6588 if (!FuncInfo->CanLowerReturn) {
6589 // Put in an sret pointer parameter before all the other parameters.
6590 SmallVector<EVT, 1> ValueVTs;
6591 ComputeValueVTs(TLI, PointerType::getUnqual(F.getReturnType()), ValueVTs);
6593 // NOTE: Assuming that a pointer will never break down to more than one VT
6595 ISD::ArgFlagsTy Flags;
6597 EVT RegisterVT = TLI.getRegisterType(*DAG.getContext(), ValueVTs[0]);
6598 ISD::InputArg RetArg(Flags, RegisterVT, true);
6599 Ins.push_back(RetArg);
6602 // Set up the incoming argument description vector.
6604 for (Function::const_arg_iterator I = F.arg_begin(), E = F.arg_end();
6605 I != E; ++I, ++Idx) {
6606 SmallVector<EVT, 4> ValueVTs;
6607 ComputeValueVTs(TLI, I->getType(), ValueVTs);
6608 bool isArgValueUsed = !I->use_empty();
6609 for (unsigned Value = 0, NumValues = ValueVTs.size();
6610 Value != NumValues; ++Value) {
6611 EVT VT = ValueVTs[Value];
6612 Type *ArgTy = VT.getTypeForEVT(*DAG.getContext());
6613 ISD::ArgFlagsTy Flags;
6614 unsigned OriginalAlignment =
6615 TD->getABITypeAlignment(ArgTy);
6617 if (F.paramHasAttr(Idx, Attribute::ZExt))
6619 if (F.paramHasAttr(Idx, Attribute::SExt))
6621 if (F.paramHasAttr(Idx, Attribute::InReg))
6623 if (F.paramHasAttr(Idx, Attribute::StructRet))
6625 if (F.paramHasAttr(Idx, Attribute::ByVal)) {
6627 PointerType *Ty = cast<PointerType>(I->getType());
6628 Type *ElementTy = Ty->getElementType();
6629 Flags.setByValSize(TD->getTypeAllocSize(ElementTy));
6630 // For ByVal, alignment should be passed from FE. BE will guess if
6631 // this info is not there but there are cases it cannot get right.
6632 unsigned FrameAlign;
6633 if (F.getParamAlignment(Idx))
6634 FrameAlign = F.getParamAlignment(Idx);
6636 FrameAlign = TLI.getByValTypeAlignment(ElementTy);
6637 Flags.setByValAlign(FrameAlign);
6639 if (F.paramHasAttr(Idx, Attribute::Nest))
6641 Flags.setOrigAlign(OriginalAlignment);
6643 EVT RegisterVT = TLI.getRegisterType(*CurDAG->getContext(), VT);
6644 unsigned NumRegs = TLI.getNumRegisters(*CurDAG->getContext(), VT);
6645 for (unsigned i = 0; i != NumRegs; ++i) {
6646 ISD::InputArg MyFlags(Flags, RegisterVT, isArgValueUsed);
6647 if (NumRegs > 1 && i == 0)
6648 MyFlags.Flags.setSplit();
6649 // if it isn't first piece, alignment must be 1
6651 MyFlags.Flags.setOrigAlign(1);
6652 Ins.push_back(MyFlags);
6657 // Call the target to set up the argument values.
6658 SmallVector<SDValue, 8> InVals;
6659 SDValue NewRoot = TLI.LowerFormalArguments(DAG.getRoot(), F.getCallingConv(),
6663 // Verify that the target's LowerFormalArguments behaved as expected.
6664 assert(NewRoot.getNode() && NewRoot.getValueType() == MVT::Other &&
6665 "LowerFormalArguments didn't return a valid chain!");
6666 assert(InVals.size() == Ins.size() &&
6667 "LowerFormalArguments didn't emit the correct number of values!");
6669 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
6670 assert(InVals[i].getNode() &&
6671 "LowerFormalArguments emitted a null value!");
6672 assert(EVT(Ins[i].VT) == InVals[i].getValueType() &&
6673 "LowerFormalArguments emitted a value with the wrong type!");
6677 // Update the DAG with the new chain value resulting from argument lowering.
6678 DAG.setRoot(NewRoot);
6680 // Set up the argument values.
6683 if (!FuncInfo->CanLowerReturn) {
6684 // Create a virtual register for the sret pointer, and put in a copy
6685 // from the sret argument into it.
6686 SmallVector<EVT, 1> ValueVTs;
6687 ComputeValueVTs(TLI, PointerType::getUnqual(F.getReturnType()), ValueVTs);
6688 EVT VT = ValueVTs[0];
6689 EVT RegVT = TLI.getRegisterType(*CurDAG->getContext(), VT);
6690 ISD::NodeType AssertOp = ISD::DELETED_NODE;
6691 SDValue ArgValue = getCopyFromParts(DAG, dl, &InVals[0], 1,
6692 RegVT, VT, AssertOp);
6694 MachineFunction& MF = SDB->DAG.getMachineFunction();
6695 MachineRegisterInfo& RegInfo = MF.getRegInfo();
6696 unsigned SRetReg = RegInfo.createVirtualRegister(TLI.getRegClassFor(RegVT));
6697 FuncInfo->DemoteRegister = SRetReg;
6698 NewRoot = SDB->DAG.getCopyToReg(NewRoot, SDB->getCurDebugLoc(),
6700 DAG.setRoot(NewRoot);
6702 // i indexes lowered arguments. Bump it past the hidden sret argument.
6703 // Idx indexes LLVM arguments. Don't touch it.
6707 for (Function::const_arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E;
6709 SmallVector<SDValue, 4> ArgValues;
6710 SmallVector<EVT, 4> ValueVTs;
6711 ComputeValueVTs(TLI, I->getType(), ValueVTs);
6712 unsigned NumValues = ValueVTs.size();
6714 // If this argument is unused then remember its value. It is used to generate
6715 // debugging information.
6716 if (I->use_empty() && NumValues)
6717 SDB->setUnusedArgValue(I, InVals[i]);
6719 for (unsigned Val = 0; Val != NumValues; ++Val) {
6720 EVT VT = ValueVTs[Val];
6721 EVT PartVT = TLI.getRegisterType(*CurDAG->getContext(), VT);
6722 unsigned NumParts = TLI.getNumRegisters(*CurDAG->getContext(), VT);
6724 if (!I->use_empty()) {
6725 ISD::NodeType AssertOp = ISD::DELETED_NODE;
6726 if (F.paramHasAttr(Idx, Attribute::SExt))
6727 AssertOp = ISD::AssertSext;
6728 else if (F.paramHasAttr(Idx, Attribute::ZExt))
6729 AssertOp = ISD::AssertZext;
6731 ArgValues.push_back(getCopyFromParts(DAG, dl, &InVals[i],
6732 NumParts, PartVT, VT,
6739 // We don't need to do anything else for unused arguments.
6740 if (ArgValues.empty())
6743 // Note down frame index.
6744 if (FrameIndexSDNode *FI =
6745 dyn_cast<FrameIndexSDNode>(ArgValues[0].getNode()))
6746 FuncInfo->setArgumentFrameIndex(I, FI->getIndex());
6748 SDValue Res = DAG.getMergeValues(&ArgValues[0], NumValues,
6749 SDB->getCurDebugLoc());
6751 SDB->setValue(I, Res);
6752 if (!TM.Options.EnableFastISel && Res.getOpcode() == ISD::BUILD_PAIR) {
6753 if (LoadSDNode *LNode =
6754 dyn_cast<LoadSDNode>(Res.getOperand(0).getNode()))
6755 if (FrameIndexSDNode *FI =
6756 dyn_cast<FrameIndexSDNode>(LNode->getBasePtr().getNode()))
6757 FuncInfo->setArgumentFrameIndex(I, FI->getIndex());
6760 // If this argument is live outside of the entry block, insert a copy from
6761 // wherever we got it to the vreg that other BB's will reference it as.
6762 if (!TM.Options.EnableFastISel && Res.getOpcode() == ISD::CopyFromReg) {
6763 // If we can, though, try to skip creating an unnecessary vreg.
6764 // FIXME: This isn't very clean... it would be nice to make this more
6765 // general. It's also subtly incompatible with the hacks FastISel
6767 unsigned Reg = cast<RegisterSDNode>(Res.getOperand(1))->getReg();
6768 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
6769 FuncInfo->ValueMap[I] = Reg;
6773 if (!isOnlyUsedInEntryBlock(I, TM.Options.EnableFastISel)) {
6774 FuncInfo->InitializeRegForValue(I);
6775 SDB->CopyToExportRegsIfNeeded(I);
6779 assert(i == InVals.size() && "Argument register count mismatch!");
6781 // Finally, if the target has anything special to do, allow it to do so.
6782 // FIXME: this should insert code into the DAG!
6783 EmitFunctionEntryCode();
6786 /// Handle PHI nodes in successor blocks. Emit code into the SelectionDAG to
6787 /// ensure constants are generated when needed. Remember the virtual registers
6788 /// that need to be added to the Machine PHI nodes as input. We cannot just
6789 /// directly add them, because expansion might result in multiple MBB's for one
6790 /// BB. As such, the start of the BB might correspond to a different MBB than
6794 SelectionDAGBuilder::HandlePHINodesInSuccessorBlocks(const BasicBlock *LLVMBB) {
6795 const TerminatorInst *TI = LLVMBB->getTerminator();
6797 SmallPtrSet<MachineBasicBlock *, 4> SuccsHandled;
6799 // Check successor nodes' PHI nodes that expect a constant to be available
6801 for (unsigned succ = 0, e = TI->getNumSuccessors(); succ != e; ++succ) {
6802 const BasicBlock *SuccBB = TI->getSuccessor(succ);
6803 if (!isa<PHINode>(SuccBB->begin())) continue;
6804 MachineBasicBlock *SuccMBB = FuncInfo.MBBMap[SuccBB];
6806 // If this terminator has multiple identical successors (common for
6807 // switches), only handle each succ once.
6808 if (!SuccsHandled.insert(SuccMBB)) continue;
6810 MachineBasicBlock::iterator MBBI = SuccMBB->begin();
6812 // At this point we know that there is a 1-1 correspondence between LLVM PHI
6813 // nodes and Machine PHI nodes, but the incoming operands have not been
6815 for (BasicBlock::const_iterator I = SuccBB->begin();
6816 const PHINode *PN = dyn_cast<PHINode>(I); ++I) {
6817 // Ignore dead phi's.
6818 if (PN->use_empty()) continue;
6821 if (PN->getType()->isEmptyTy())
6825 const Value *PHIOp = PN->getIncomingValueForBlock(LLVMBB);
6827 if (const Constant *C = dyn_cast<Constant>(PHIOp)) {
6828 unsigned &RegOut = ConstantsOut[C];
6830 RegOut = FuncInfo.CreateRegs(C->getType());
6831 CopyValueToVirtualRegister(C, RegOut);
6835 DenseMap<const Value *, unsigned>::iterator I =
6836 FuncInfo.ValueMap.find(PHIOp);
6837 if (I != FuncInfo.ValueMap.end())
6840 assert(isa<AllocaInst>(PHIOp) &&
6841 FuncInfo.StaticAllocaMap.count(cast<AllocaInst>(PHIOp)) &&
6842 "Didn't codegen value into a register!??");
6843 Reg = FuncInfo.CreateRegs(PHIOp->getType());
6844 CopyValueToVirtualRegister(PHIOp, Reg);
6848 // Remember that this register needs to added to the machine PHI node as
6849 // the input for this MBB.
6850 SmallVector<EVT, 4> ValueVTs;
6851 ComputeValueVTs(TLI, PN->getType(), ValueVTs);
6852 for (unsigned vti = 0, vte = ValueVTs.size(); vti != vte; ++vti) {
6853 EVT VT = ValueVTs[vti];
6854 unsigned NumRegisters = TLI.getNumRegisters(*DAG.getContext(), VT);
6855 for (unsigned i = 0, e = NumRegisters; i != e; ++i)
6856 FuncInfo.PHINodesToUpdate.push_back(std::make_pair(MBBI++, Reg+i));
6857 Reg += NumRegisters;
6861 ConstantsOut.clear();