1 //===-- SelectionDAGBuild.cpp - Selection-DAG building --------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements routines for translating from LLVM IR into SelectionDAG IR.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "isel"
15 #include "SelectionDAGBuild.h"
16 #include "llvm/ADT/BitVector.h"
17 #include "llvm/ADT/SmallSet.h"
18 #include "llvm/Analysis/AliasAnalysis.h"
19 #include "llvm/Constants.h"
20 #include "llvm/Constants.h"
21 #include "llvm/CallingConv.h"
22 #include "llvm/DerivedTypes.h"
23 #include "llvm/Function.h"
24 #include "llvm/GlobalVariable.h"
25 #include "llvm/InlineAsm.h"
26 #include "llvm/Instructions.h"
27 #include "llvm/Intrinsics.h"
28 #include "llvm/IntrinsicInst.h"
29 #include "llvm/Module.h"
30 #include "llvm/CodeGen/FastISel.h"
31 #include "llvm/CodeGen/GCStrategy.h"
32 #include "llvm/CodeGen/GCMetadata.h"
33 #include "llvm/CodeGen/MachineFunction.h"
34 #include "llvm/CodeGen/MachineFrameInfo.h"
35 #include "llvm/CodeGen/MachineInstrBuilder.h"
36 #include "llvm/CodeGen/MachineJumpTableInfo.h"
37 #include "llvm/CodeGen/MachineModuleInfo.h"
38 #include "llvm/CodeGen/MachineRegisterInfo.h"
39 #include "llvm/CodeGen/PseudoSourceValue.h"
40 #include "llvm/CodeGen/SelectionDAG.h"
41 #include "llvm/CodeGen/DwarfWriter.h"
42 #include "llvm/Analysis/DebugInfo.h"
43 #include "llvm/Target/TargetRegisterInfo.h"
44 #include "llvm/Target/TargetData.h"
45 #include "llvm/Target/TargetFrameInfo.h"
46 #include "llvm/Target/TargetInstrInfo.h"
47 #include "llvm/Target/TargetIntrinsicInfo.h"
48 #include "llvm/Target/TargetLowering.h"
49 #include "llvm/Target/TargetOptions.h"
50 #include "llvm/Support/Compiler.h"
51 #include "llvm/Support/CommandLine.h"
52 #include "llvm/Support/Debug.h"
53 #include "llvm/Support/ErrorHandling.h"
54 #include "llvm/Support/MathExtras.h"
55 #include "llvm/Support/raw_ostream.h"
59 /// LimitFloatPrecision - Generate low-precision inline sequences for
60 /// some float libcalls (6, 8 or 12 bits).
61 static unsigned LimitFloatPrecision;
63 static cl::opt<unsigned, true>
64 LimitFPPrecision("limit-float-precision",
65 cl::desc("Generate low-precision inline sequences "
66 "for some float libcalls"),
67 cl::location(LimitFloatPrecision),
70 /// ComputeLinearIndex - Given an LLVM IR aggregate type and a sequence
71 /// of insertvalue or extractvalue indices that identify a member, return
72 /// the linearized index of the start of the member.
74 static unsigned ComputeLinearIndex(const TargetLowering &TLI, const Type *Ty,
75 const unsigned *Indices,
76 const unsigned *IndicesEnd,
77 unsigned CurIndex = 0) {
78 // Base case: We're done.
79 if (Indices && Indices == IndicesEnd)
82 // Given a struct type, recursively traverse the elements.
83 if (const StructType *STy = dyn_cast<StructType>(Ty)) {
84 for (StructType::element_iterator EB = STy->element_begin(),
86 EE = STy->element_end();
88 if (Indices && *Indices == unsigned(EI - EB))
89 return ComputeLinearIndex(TLI, *EI, Indices+1, IndicesEnd, CurIndex);
90 CurIndex = ComputeLinearIndex(TLI, *EI, 0, 0, CurIndex);
94 // Given an array type, recursively traverse the elements.
95 else if (const ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
96 const Type *EltTy = ATy->getElementType();
97 for (unsigned i = 0, e = ATy->getNumElements(); i != e; ++i) {
98 if (Indices && *Indices == i)
99 return ComputeLinearIndex(TLI, EltTy, Indices+1, IndicesEnd, CurIndex);
100 CurIndex = ComputeLinearIndex(TLI, EltTy, 0, 0, CurIndex);
104 // We haven't found the type we're looking for, so keep searching.
108 /// ComputeValueVTs - Given an LLVM IR type, compute a sequence of
109 /// EVTs that represent all the individual underlying
110 /// non-aggregate types that comprise it.
112 /// If Offsets is non-null, it points to a vector to be filled in
113 /// with the in-memory offsets of each of the individual values.
115 static void ComputeValueVTs(const TargetLowering &TLI, const Type *Ty,
116 SmallVectorImpl<EVT> &ValueVTs,
117 SmallVectorImpl<uint64_t> *Offsets = 0,
118 uint64_t StartingOffset = 0) {
119 // Given a struct type, recursively traverse the elements.
120 if (const StructType *STy = dyn_cast<StructType>(Ty)) {
121 const StructLayout *SL = TLI.getTargetData()->getStructLayout(STy);
122 for (StructType::element_iterator EB = STy->element_begin(),
124 EE = STy->element_end();
126 ComputeValueVTs(TLI, *EI, ValueVTs, Offsets,
127 StartingOffset + SL->getElementOffset(EI - EB));
130 // Given an array type, recursively traverse the elements.
131 if (const ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
132 const Type *EltTy = ATy->getElementType();
133 uint64_t EltSize = TLI.getTargetData()->getTypeAllocSize(EltTy);
134 for (unsigned i = 0, e = ATy->getNumElements(); i != e; ++i)
135 ComputeValueVTs(TLI, EltTy, ValueVTs, Offsets,
136 StartingOffset + i * EltSize);
139 // Interpret void as zero return values.
140 if (Ty == Type::getVoidTy(Ty->getContext()))
142 // Base case: we can get an EVT for this LLVM IR type.
143 ValueVTs.push_back(TLI.getValueType(Ty));
145 Offsets->push_back(StartingOffset);
149 /// RegsForValue - This struct represents the registers (physical or virtual)
150 /// that a particular set of values is assigned, and the type information about
151 /// the value. The most common situation is to represent one value at a time,
152 /// but struct or array values are handled element-wise as multiple values.
153 /// The splitting of aggregates is performed recursively, so that we never
154 /// have aggregate-typed registers. The values at this point do not necessarily
155 /// have legal types, so each value may require one or more registers of some
158 struct VISIBILITY_HIDDEN RegsForValue {
159 /// TLI - The TargetLowering object.
161 const TargetLowering *TLI;
163 /// ValueVTs - The value types of the values, which may not be legal, and
164 /// may need be promoted or synthesized from one or more registers.
166 SmallVector<EVT, 4> ValueVTs;
168 /// RegVTs - The value types of the registers. This is the same size as
169 /// ValueVTs and it records, for each value, what the type of the assigned
170 /// register or registers are. (Individual values are never synthesized
171 /// from more than one type of register.)
173 /// With virtual registers, the contents of RegVTs is redundant with TLI's
174 /// getRegisterType member function, however when with physical registers
175 /// it is necessary to have a separate record of the types.
177 SmallVector<EVT, 4> RegVTs;
179 /// Regs - This list holds the registers assigned to the values.
180 /// Each legal or promoted value requires one register, and each
181 /// expanded value requires multiple registers.
183 SmallVector<unsigned, 4> Regs;
185 RegsForValue() : TLI(0) {}
187 RegsForValue(const TargetLowering &tli,
188 const SmallVector<unsigned, 4> ®s,
189 EVT regvt, EVT valuevt)
190 : TLI(&tli), ValueVTs(1, valuevt), RegVTs(1, regvt), Regs(regs) {}
191 RegsForValue(const TargetLowering &tli,
192 const SmallVector<unsigned, 4> ®s,
193 const SmallVector<EVT, 4> ®vts,
194 const SmallVector<EVT, 4> &valuevts)
195 : TLI(&tli), ValueVTs(valuevts), RegVTs(regvts), Regs(regs) {}
196 RegsForValue(LLVMContext &Context, const TargetLowering &tli,
197 unsigned Reg, const Type *Ty) : TLI(&tli) {
198 ComputeValueVTs(tli, Ty, ValueVTs);
200 for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) {
201 EVT ValueVT = ValueVTs[Value];
202 unsigned NumRegs = TLI->getNumRegisters(Context, ValueVT);
203 EVT RegisterVT = TLI->getRegisterType(Context, ValueVT);
204 for (unsigned i = 0; i != NumRegs; ++i)
205 Regs.push_back(Reg + i);
206 RegVTs.push_back(RegisterVT);
211 /// append - Add the specified values to this one.
212 void append(const RegsForValue &RHS) {
214 ValueVTs.append(RHS.ValueVTs.begin(), RHS.ValueVTs.end());
215 RegVTs.append(RHS.RegVTs.begin(), RHS.RegVTs.end());
216 Regs.append(RHS.Regs.begin(), RHS.Regs.end());
220 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from
221 /// this value and returns the result as a ValueVTs value. This uses
222 /// Chain/Flag as the input and updates them for the output Chain/Flag.
223 /// If the Flag pointer is NULL, no flag is used.
224 SDValue getCopyFromRegs(SelectionDAG &DAG, DebugLoc dl,
225 SDValue &Chain, SDValue *Flag) const;
227 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
228 /// specified value into the registers specified by this object. This uses
229 /// Chain/Flag as the input and updates them for the output Chain/Flag.
230 /// If the Flag pointer is NULL, no flag is used.
231 void getCopyToRegs(SDValue Val, SelectionDAG &DAG, DebugLoc dl,
232 SDValue &Chain, SDValue *Flag) const;
234 /// AddInlineAsmOperands - Add this value to the specified inlineasm node
235 /// operand list. This adds the code marker, matching input operand index
236 /// (if applicable), and includes the number of values added into it.
237 void AddInlineAsmOperands(unsigned Code,
238 bool HasMatching, unsigned MatchingIdx,
239 SelectionDAG &DAG, std::vector<SDValue> &Ops) const;
243 /// isUsedOutsideOfDefiningBlock - Return true if this instruction is used by
244 /// PHI nodes or outside of the basic block that defines it, or used by a
245 /// switch or atomic instruction, which may expand to multiple basic blocks.
246 static bool isUsedOutsideOfDefiningBlock(Instruction *I) {
247 if (isa<PHINode>(I)) return true;
248 BasicBlock *BB = I->getParent();
249 for (Value::use_iterator UI = I->use_begin(), E = I->use_end(); UI != E; ++UI)
250 if (cast<Instruction>(*UI)->getParent() != BB || isa<PHINode>(*UI))
255 /// isOnlyUsedInEntryBlock - If the specified argument is only used in the
256 /// entry block, return true. This includes arguments used by switches, since
257 /// the switch may expand into multiple basic blocks.
258 static bool isOnlyUsedInEntryBlock(Argument *A, bool EnableFastISel) {
259 // With FastISel active, we may be splitting blocks, so force creation
260 // of virtual registers for all non-dead arguments.
261 // Don't force virtual registers for byval arguments though, because
262 // fast-isel can't handle those in all cases.
263 if (EnableFastISel && !A->hasByValAttr())
264 return A->use_empty();
266 BasicBlock *Entry = A->getParent()->begin();
267 for (Value::use_iterator UI = A->use_begin(), E = A->use_end(); UI != E; ++UI)
268 if (cast<Instruction>(*UI)->getParent() != Entry || isa<SwitchInst>(*UI))
269 return false; // Use not in entry block.
273 FunctionLoweringInfo::FunctionLoweringInfo(TargetLowering &tli)
277 void FunctionLoweringInfo::set(Function &fn, MachineFunction &mf,
279 bool EnableFastISel) {
282 RegInfo = &MF->getRegInfo();
284 // Create a vreg for each argument register that is not dead and is used
285 // outside of the entry block for the function.
286 for (Function::arg_iterator AI = Fn->arg_begin(), E = Fn->arg_end();
288 if (!isOnlyUsedInEntryBlock(AI, EnableFastISel))
289 InitializeRegForValue(AI);
291 // Initialize the mapping of values to registers. This is only set up for
292 // instruction values that are used outside of the block that defines
294 Function::iterator BB = Fn->begin(), EB = Fn->end();
295 for (BasicBlock::iterator I = BB->begin(), E = BB->end(); I != E; ++I)
296 if (AllocaInst *AI = dyn_cast<AllocaInst>(I))
297 if (ConstantInt *CUI = dyn_cast<ConstantInt>(AI->getArraySize())) {
298 const Type *Ty = AI->getAllocatedType();
299 uint64_t TySize = TLI.getTargetData()->getTypeAllocSize(Ty);
301 std::max((unsigned)TLI.getTargetData()->getPrefTypeAlignment(Ty),
304 TySize *= CUI->getZExtValue(); // Get total allocated size.
305 if (TySize == 0) TySize = 1; // Don't create zero-sized stack objects.
306 StaticAllocaMap[AI] =
307 MF->getFrameInfo()->CreateStackObject(TySize, Align);
310 for (; BB != EB; ++BB)
311 for (BasicBlock::iterator I = BB->begin(), E = BB->end(); I != E; ++I)
312 if (!I->use_empty() && isUsedOutsideOfDefiningBlock(I))
313 if (!isa<AllocaInst>(I) ||
314 !StaticAllocaMap.count(cast<AllocaInst>(I)))
315 InitializeRegForValue(I);
317 // Create an initial MachineBasicBlock for each LLVM BasicBlock in F. This
318 // also creates the initial PHI MachineInstrs, though none of the input
319 // operands are populated.
320 for (BB = Fn->begin(), EB = Fn->end(); BB != EB; ++BB) {
321 MachineBasicBlock *MBB = mf.CreateMachineBasicBlock(BB);
325 // Create Machine PHI nodes for LLVM PHI nodes, lowering them as
329 for (BasicBlock::iterator
330 I = BB->begin(), E = BB->end(); I != E; ++I) {
331 if (CallInst *CI = dyn_cast<CallInst>(I)) {
332 if (Function *F = CI->getCalledFunction()) {
333 switch (F->getIntrinsicID()) {
335 case Intrinsic::dbg_stoppoint: {
336 DbgStopPointInst *SPI = cast<DbgStopPointInst>(I);
337 if (isValidDebugInfoIntrinsic(*SPI, CodeGenOpt::Default))
338 DL = ExtractDebugLocation(*SPI, MF->getDebugLocInfo());
341 case Intrinsic::dbg_func_start: {
342 DbgFuncStartInst *FSI = cast<DbgFuncStartInst>(I);
343 if (isValidDebugInfoIntrinsic(*FSI, CodeGenOpt::Default))
344 DL = ExtractDebugLocation(*FSI, MF->getDebugLocInfo());
351 PN = dyn_cast<PHINode>(I);
352 if (!PN || PN->use_empty()) continue;
354 unsigned PHIReg = ValueMap[PN];
355 assert(PHIReg && "PHI node does not have an assigned virtual register!");
357 SmallVector<EVT, 4> ValueVTs;
358 ComputeValueVTs(TLI, PN->getType(), ValueVTs);
359 for (unsigned vti = 0, vte = ValueVTs.size(); vti != vte; ++vti) {
360 EVT VT = ValueVTs[vti];
361 unsigned NumRegisters = TLI.getNumRegisters(*DAG.getContext(), VT);
362 const TargetInstrInfo *TII = MF->getTarget().getInstrInfo();
363 for (unsigned i = 0; i != NumRegisters; ++i)
364 BuildMI(MBB, DL, TII->get(TargetInstrInfo::PHI), PHIReg + i);
365 PHIReg += NumRegisters;
371 unsigned FunctionLoweringInfo::MakeReg(EVT VT) {
372 return RegInfo->createVirtualRegister(TLI.getRegClassFor(VT));
375 /// CreateRegForValue - Allocate the appropriate number of virtual registers of
376 /// the correctly promoted or expanded types. Assign these registers
377 /// consecutive vreg numbers and return the first assigned number.
379 /// In the case that the given value has struct or array type, this function
380 /// will assign registers for each member or element.
382 unsigned FunctionLoweringInfo::CreateRegForValue(const Value *V) {
383 SmallVector<EVT, 4> ValueVTs;
384 ComputeValueVTs(TLI, V->getType(), ValueVTs);
386 unsigned FirstReg = 0;
387 for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) {
388 EVT ValueVT = ValueVTs[Value];
389 EVT RegisterVT = TLI.getRegisterType(V->getContext(), ValueVT);
391 unsigned NumRegs = TLI.getNumRegisters(V->getContext(), ValueVT);
392 for (unsigned i = 0; i != NumRegs; ++i) {
393 unsigned R = MakeReg(RegisterVT);
394 if (!FirstReg) FirstReg = R;
400 /// getCopyFromParts - Create a value that contains the specified legal parts
401 /// combined into the value they represent. If the parts combine to a type
402 /// larger then ValueVT then AssertOp can be used to specify whether the extra
403 /// bits are known to be zero (ISD::AssertZext) or sign extended from ValueVT
404 /// (ISD::AssertSext).
405 static SDValue getCopyFromParts(SelectionDAG &DAG, DebugLoc dl,
406 const SDValue *Parts,
407 unsigned NumParts, EVT PartVT, EVT ValueVT,
408 ISD::NodeType AssertOp = ISD::DELETED_NODE) {
409 assert(NumParts > 0 && "No parts to assemble!");
410 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
411 SDValue Val = Parts[0];
414 // Assemble the value from multiple parts.
415 if (!ValueVT.isVector() && ValueVT.isInteger()) {
416 unsigned PartBits = PartVT.getSizeInBits();
417 unsigned ValueBits = ValueVT.getSizeInBits();
419 // Assemble the power of 2 part.
420 unsigned RoundParts = NumParts & (NumParts - 1) ?
421 1 << Log2_32(NumParts) : NumParts;
422 unsigned RoundBits = PartBits * RoundParts;
423 EVT RoundVT = RoundBits == ValueBits ?
424 ValueVT : EVT::getIntegerVT(*DAG.getContext(), RoundBits);
427 EVT HalfVT = EVT::getIntegerVT(*DAG.getContext(), RoundBits/2);
429 if (RoundParts > 2) {
430 Lo = getCopyFromParts(DAG, dl, Parts, RoundParts/2, PartVT, HalfVT);
431 Hi = getCopyFromParts(DAG, dl, Parts+RoundParts/2, RoundParts/2,
434 Lo = DAG.getNode(ISD::BIT_CONVERT, dl, HalfVT, Parts[0]);
435 Hi = DAG.getNode(ISD::BIT_CONVERT, dl, HalfVT, Parts[1]);
437 if (TLI.isBigEndian())
439 Val = DAG.getNode(ISD::BUILD_PAIR, dl, RoundVT, Lo, Hi);
441 if (RoundParts < NumParts) {
442 // Assemble the trailing non-power-of-2 part.
443 unsigned OddParts = NumParts - RoundParts;
444 EVT OddVT = EVT::getIntegerVT(*DAG.getContext(), OddParts * PartBits);
445 Hi = getCopyFromParts(DAG, dl,
446 Parts+RoundParts, OddParts, PartVT, OddVT);
448 // Combine the round and odd parts.
450 if (TLI.isBigEndian())
452 EVT TotalVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
453 Hi = DAG.getNode(ISD::ANY_EXTEND, dl, TotalVT, Hi);
454 Hi = DAG.getNode(ISD::SHL, dl, TotalVT, Hi,
455 DAG.getConstant(Lo.getValueType().getSizeInBits(),
456 TLI.getPointerTy()));
457 Lo = DAG.getNode(ISD::ZERO_EXTEND, dl, TotalVT, Lo);
458 Val = DAG.getNode(ISD::OR, dl, TotalVT, Lo, Hi);
460 } else if (ValueVT.isVector()) {
461 // Handle a multi-element vector.
462 EVT IntermediateVT, RegisterVT;
463 unsigned NumIntermediates;
465 TLI.getVectorTypeBreakdown(*DAG.getContext(), ValueVT, IntermediateVT,
466 NumIntermediates, RegisterVT);
467 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!");
468 NumParts = NumRegs; // Silence a compiler warning.
469 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!");
470 assert(RegisterVT == Parts[0].getValueType() &&
471 "Part type doesn't match part!");
473 // Assemble the parts into intermediate operands.
474 SmallVector<SDValue, 8> Ops(NumIntermediates);
475 if (NumIntermediates == NumParts) {
476 // If the register was not expanded, truncate or copy the value,
478 for (unsigned i = 0; i != NumParts; ++i)
479 Ops[i] = getCopyFromParts(DAG, dl, &Parts[i], 1,
480 PartVT, IntermediateVT);
481 } else if (NumParts > 0) {
482 // If the intermediate type was expanded, build the intermediate operands
484 assert(NumParts % NumIntermediates == 0 &&
485 "Must expand into a divisible number of parts!");
486 unsigned Factor = NumParts / NumIntermediates;
487 for (unsigned i = 0; i != NumIntermediates; ++i)
488 Ops[i] = getCopyFromParts(DAG, dl, &Parts[i * Factor], Factor,
489 PartVT, IntermediateVT);
492 // Build a vector with BUILD_VECTOR or CONCAT_VECTORS from the intermediate
494 Val = DAG.getNode(IntermediateVT.isVector() ?
495 ISD::CONCAT_VECTORS : ISD::BUILD_VECTOR, dl,
496 ValueVT, &Ops[0], NumIntermediates);
497 } else if (PartVT.isFloatingPoint()) {
498 // FP split into multiple FP parts (for ppcf128)
499 assert(ValueVT == EVT(MVT::ppcf128) && PartVT == EVT(MVT::f64) &&
502 Lo = DAG.getNode(ISD::BIT_CONVERT, dl, EVT(MVT::f64), Parts[0]);
503 Hi = DAG.getNode(ISD::BIT_CONVERT, dl, EVT(MVT::f64), Parts[1]);
504 if (TLI.isBigEndian())
506 Val = DAG.getNode(ISD::BUILD_PAIR, dl, ValueVT, Lo, Hi);
508 // FP split into integer parts (soft fp)
509 assert(ValueVT.isFloatingPoint() && PartVT.isInteger() &&
510 !PartVT.isVector() && "Unexpected split");
511 EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), ValueVT.getSizeInBits());
512 Val = getCopyFromParts(DAG, dl, Parts, NumParts, PartVT, IntVT);
516 // There is now one part, held in Val. Correct it to match ValueVT.
517 PartVT = Val.getValueType();
519 if (PartVT == ValueVT)
522 if (PartVT.isVector()) {
523 assert(ValueVT.isVector() && "Unknown vector conversion!");
524 return DAG.getNode(ISD::BIT_CONVERT, dl, ValueVT, Val);
527 if (ValueVT.isVector()) {
528 assert(ValueVT.getVectorElementType() == PartVT &&
529 ValueVT.getVectorNumElements() == 1 &&
530 "Only trivial scalar-to-vector conversions should get here!");
531 return DAG.getNode(ISD::BUILD_VECTOR, dl, ValueVT, Val);
534 if (PartVT.isInteger() &&
535 ValueVT.isInteger()) {
536 if (ValueVT.bitsLT(PartVT)) {
537 // For a truncate, see if we have any information to
538 // indicate whether the truncated bits will always be
539 // zero or sign-extension.
540 if (AssertOp != ISD::DELETED_NODE)
541 Val = DAG.getNode(AssertOp, dl, PartVT, Val,
542 DAG.getValueType(ValueVT));
543 return DAG.getNode(ISD::TRUNCATE, dl, ValueVT, Val);
545 return DAG.getNode(ISD::ANY_EXTEND, dl, ValueVT, Val);
549 if (PartVT.isFloatingPoint() && ValueVT.isFloatingPoint()) {
550 if (ValueVT.bitsLT(Val.getValueType()))
551 // FP_ROUND's are always exact here.
552 return DAG.getNode(ISD::FP_ROUND, dl, ValueVT, Val,
553 DAG.getIntPtrConstant(1));
554 return DAG.getNode(ISD::FP_EXTEND, dl, ValueVT, Val);
557 if (PartVT.getSizeInBits() == ValueVT.getSizeInBits())
558 return DAG.getNode(ISD::BIT_CONVERT, dl, ValueVT, Val);
560 llvm_unreachable("Unknown mismatch!");
564 /// getCopyToParts - Create a series of nodes that contain the specified value
565 /// split into legal parts. If the parts contain more bits than Val, then, for
566 /// integers, ExtendKind can be used to specify how to generate the extra bits.
567 static void getCopyToParts(SelectionDAG &DAG, DebugLoc dl, SDValue Val,
568 SDValue *Parts, unsigned NumParts, EVT PartVT,
569 ISD::NodeType ExtendKind = ISD::ANY_EXTEND) {
570 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
571 EVT PtrVT = TLI.getPointerTy();
572 EVT ValueVT = Val.getValueType();
573 unsigned PartBits = PartVT.getSizeInBits();
574 unsigned OrigNumParts = NumParts;
575 assert(TLI.isTypeLegal(PartVT) && "Copying to an illegal type!");
580 if (!ValueVT.isVector()) {
581 if (PartVT == ValueVT) {
582 assert(NumParts == 1 && "No-op copy with multiple parts!");
587 if (NumParts * PartBits > ValueVT.getSizeInBits()) {
588 // If the parts cover more bits than the value has, promote the value.
589 if (PartVT.isFloatingPoint() && ValueVT.isFloatingPoint()) {
590 assert(NumParts == 1 && "Do not know what to promote to!");
591 Val = DAG.getNode(ISD::FP_EXTEND, dl, PartVT, Val);
592 } else if (PartVT.isInteger() && ValueVT.isInteger()) {
593 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
594 Val = DAG.getNode(ExtendKind, dl, ValueVT, Val);
596 llvm_unreachable("Unknown mismatch!");
598 } else if (PartBits == ValueVT.getSizeInBits()) {
599 // Different types of the same size.
600 assert(NumParts == 1 && PartVT != ValueVT);
601 Val = DAG.getNode(ISD::BIT_CONVERT, dl, PartVT, Val);
602 } else if (NumParts * PartBits < ValueVT.getSizeInBits()) {
603 // If the parts cover less bits than value has, truncate the value.
604 if (PartVT.isInteger() && ValueVT.isInteger()) {
605 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
606 Val = DAG.getNode(ISD::TRUNCATE, dl, ValueVT, Val);
608 llvm_unreachable("Unknown mismatch!");
612 // The value may have changed - recompute ValueVT.
613 ValueVT = Val.getValueType();
614 assert(NumParts * PartBits == ValueVT.getSizeInBits() &&
615 "Failed to tile the value with PartVT!");
618 assert(PartVT == ValueVT && "Type conversion failed!");
623 // Expand the value into multiple parts.
624 if (NumParts & (NumParts - 1)) {
625 // The number of parts is not a power of 2. Split off and copy the tail.
626 assert(PartVT.isInteger() && ValueVT.isInteger() &&
627 "Do not know what to expand to!");
628 unsigned RoundParts = 1 << Log2_32(NumParts);
629 unsigned RoundBits = RoundParts * PartBits;
630 unsigned OddParts = NumParts - RoundParts;
631 SDValue OddVal = DAG.getNode(ISD::SRL, dl, ValueVT, Val,
632 DAG.getConstant(RoundBits,
633 TLI.getPointerTy()));
634 getCopyToParts(DAG, dl, OddVal, Parts + RoundParts, OddParts, PartVT);
635 if (TLI.isBigEndian())
636 // The odd parts were reversed by getCopyToParts - unreverse them.
637 std::reverse(Parts + RoundParts, Parts + NumParts);
638 NumParts = RoundParts;
639 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
640 Val = DAG.getNode(ISD::TRUNCATE, dl, ValueVT, Val);
643 // The number of parts is a power of 2. Repeatedly bisect the value using
645 Parts[0] = DAG.getNode(ISD::BIT_CONVERT, dl,
646 EVT::getIntegerVT(*DAG.getContext(), ValueVT.getSizeInBits()),
648 for (unsigned StepSize = NumParts; StepSize > 1; StepSize /= 2) {
649 for (unsigned i = 0; i < NumParts; i += StepSize) {
650 unsigned ThisBits = StepSize * PartBits / 2;
651 EVT ThisVT = EVT::getIntegerVT(*DAG.getContext(), ThisBits);
652 SDValue &Part0 = Parts[i];
653 SDValue &Part1 = Parts[i+StepSize/2];
655 Part1 = DAG.getNode(ISD::EXTRACT_ELEMENT, dl,
657 DAG.getConstant(1, PtrVT));
658 Part0 = DAG.getNode(ISD::EXTRACT_ELEMENT, dl,
660 DAG.getConstant(0, PtrVT));
662 if (ThisBits == PartBits && ThisVT != PartVT) {
663 Part0 = DAG.getNode(ISD::BIT_CONVERT, dl,
665 Part1 = DAG.getNode(ISD::BIT_CONVERT, dl,
671 if (TLI.isBigEndian())
672 std::reverse(Parts, Parts + OrigNumParts);
679 if (PartVT != ValueVT) {
680 if (PartVT.isVector()) {
681 Val = DAG.getNode(ISD::BIT_CONVERT, dl, PartVT, Val);
683 assert(ValueVT.getVectorElementType() == PartVT &&
684 ValueVT.getVectorNumElements() == 1 &&
685 "Only trivial vector-to-scalar conversions should get here!");
686 Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
688 DAG.getConstant(0, PtrVT));
696 // Handle a multi-element vector.
697 EVT IntermediateVT, RegisterVT;
698 unsigned NumIntermediates;
699 unsigned NumRegs = TLI.getVectorTypeBreakdown(*DAG.getContext(), ValueVT,
700 IntermediateVT, NumIntermediates, RegisterVT);
701 unsigned NumElements = ValueVT.getVectorNumElements();
703 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!");
704 NumParts = NumRegs; // Silence a compiler warning.
705 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!");
707 // Split the vector into intermediate operands.
708 SmallVector<SDValue, 8> Ops(NumIntermediates);
709 for (unsigned i = 0; i != NumIntermediates; ++i)
710 if (IntermediateVT.isVector())
711 Ops[i] = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl,
713 DAG.getConstant(i * (NumElements / NumIntermediates),
716 Ops[i] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
718 DAG.getConstant(i, PtrVT));
720 // Split the intermediate operands into legal parts.
721 if (NumParts == NumIntermediates) {
722 // If the register was not expanded, promote or copy the value,
724 for (unsigned i = 0; i != NumParts; ++i)
725 getCopyToParts(DAG, dl, Ops[i], &Parts[i], 1, PartVT);
726 } else if (NumParts > 0) {
727 // If the intermediate type was expanded, split each the value into
729 assert(NumParts % NumIntermediates == 0 &&
730 "Must expand into a divisible number of parts!");
731 unsigned Factor = NumParts / NumIntermediates;
732 for (unsigned i = 0; i != NumIntermediates; ++i)
733 getCopyToParts(DAG, dl, Ops[i], &Parts[i * Factor], Factor, PartVT);
738 void SelectionDAGLowering::init(GCFunctionInfo *gfi, AliasAnalysis &aa) {
741 TD = DAG.getTarget().getTargetData();
744 /// clear - Clear out the curret SelectionDAG and the associated
745 /// state and prepare this SelectionDAGLowering object to be used
746 /// for a new block. This doesn't clear out information about
747 /// additional blocks that are needed to complete switch lowering
748 /// or PHI node updating; that information is cleared out as it is
750 void SelectionDAGLowering::clear() {
752 PendingLoads.clear();
753 PendingExports.clear();
756 CurDebugLoc = DebugLoc::getUnknownLoc();
760 /// getRoot - Return the current virtual root of the Selection DAG,
761 /// flushing any PendingLoad items. This must be done before emitting
762 /// a store or any other node that may need to be ordered after any
763 /// prior load instructions.
765 SDValue SelectionDAGLowering::getRoot() {
766 if (PendingLoads.empty())
767 return DAG.getRoot();
769 if (PendingLoads.size() == 1) {
770 SDValue Root = PendingLoads[0];
772 PendingLoads.clear();
776 // Otherwise, we have to make a token factor node.
777 SDValue Root = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), MVT::Other,
778 &PendingLoads[0], PendingLoads.size());
779 PendingLoads.clear();
784 /// getControlRoot - Similar to getRoot, but instead of flushing all the
785 /// PendingLoad items, flush all the PendingExports items. It is necessary
786 /// to do this before emitting a terminator instruction.
788 SDValue SelectionDAGLowering::getControlRoot() {
789 SDValue Root = DAG.getRoot();
791 if (PendingExports.empty())
794 // Turn all of the CopyToReg chains into one factored node.
795 if (Root.getOpcode() != ISD::EntryToken) {
796 unsigned i = 0, e = PendingExports.size();
797 for (; i != e; ++i) {
798 assert(PendingExports[i].getNode()->getNumOperands() > 1);
799 if (PendingExports[i].getNode()->getOperand(0) == Root)
800 break; // Don't add the root if we already indirectly depend on it.
804 PendingExports.push_back(Root);
807 Root = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), MVT::Other,
809 PendingExports.size());
810 PendingExports.clear();
815 void SelectionDAGLowering::visit(Instruction &I) {
816 visit(I.getOpcode(), I);
819 void SelectionDAGLowering::visit(unsigned Opcode, User &I) {
820 // Note: this doesn't use InstVisitor, because it has to work with
821 // ConstantExpr's in addition to instructions.
823 default: llvm_unreachable("Unknown instruction type encountered!");
824 // Build the switch statement using the Instruction.def file.
825 #define HANDLE_INST(NUM, OPCODE, CLASS) \
826 case Instruction::OPCODE:return visit##OPCODE((CLASS&)I);
827 #include "llvm/Instruction.def"
831 SDValue SelectionDAGLowering::getValue(const Value *V) {
832 SDValue &N = NodeMap[V];
833 if (N.getNode()) return N;
835 if (Constant *C = const_cast<Constant*>(dyn_cast<Constant>(V))) {
836 EVT VT = TLI.getValueType(V->getType(), true);
838 if (ConstantInt *CI = dyn_cast<ConstantInt>(C))
839 return N = DAG.getConstant(*CI, VT);
841 if (GlobalValue *GV = dyn_cast<GlobalValue>(C))
842 return N = DAG.getGlobalAddress(GV, VT);
844 if (isa<ConstantPointerNull>(C))
845 return N = DAG.getConstant(0, TLI.getPointerTy());
847 if (ConstantFP *CFP = dyn_cast<ConstantFP>(C))
848 return N = DAG.getConstantFP(*CFP, VT);
850 if (isa<UndefValue>(C) && !V->getType()->isAggregateType())
851 return N = DAG.getUNDEF(VT);
853 if (ConstantExpr *CE = dyn_cast<ConstantExpr>(C)) {
854 visit(CE->getOpcode(), *CE);
855 SDValue N1 = NodeMap[V];
856 assert(N1.getNode() && "visit didn't populate the ValueMap!");
860 if (isa<ConstantStruct>(C) || isa<ConstantArray>(C)) {
861 SmallVector<SDValue, 4> Constants;
862 for (User::const_op_iterator OI = C->op_begin(), OE = C->op_end();
864 SDNode *Val = getValue(*OI).getNode();
865 // If the operand is an empty aggregate, there are no values.
867 // Add each leaf value from the operand to the Constants list
868 // to form a flattened list of all the values.
869 for (unsigned i = 0, e = Val->getNumValues(); i != e; ++i)
870 Constants.push_back(SDValue(Val, i));
872 return DAG.getMergeValues(&Constants[0], Constants.size(),
876 if (isa<StructType>(C->getType()) || isa<ArrayType>(C->getType())) {
877 assert((isa<ConstantAggregateZero>(C) || isa<UndefValue>(C)) &&
878 "Unknown struct or array constant!");
880 SmallVector<EVT, 4> ValueVTs;
881 ComputeValueVTs(TLI, C->getType(), ValueVTs);
882 unsigned NumElts = ValueVTs.size();
884 return SDValue(); // empty struct
885 SmallVector<SDValue, 4> Constants(NumElts);
886 for (unsigned i = 0; i != NumElts; ++i) {
887 EVT EltVT = ValueVTs[i];
888 if (isa<UndefValue>(C))
889 Constants[i] = DAG.getUNDEF(EltVT);
890 else if (EltVT.isFloatingPoint())
891 Constants[i] = DAG.getConstantFP(0, EltVT);
893 Constants[i] = DAG.getConstant(0, EltVT);
895 return DAG.getMergeValues(&Constants[0], NumElts, getCurDebugLoc());
898 const VectorType *VecTy = cast<VectorType>(V->getType());
899 unsigned NumElements = VecTy->getNumElements();
901 // Now that we know the number and type of the elements, get that number of
902 // elements into the Ops array based on what kind of constant it is.
903 SmallVector<SDValue, 16> Ops;
904 if (ConstantVector *CP = dyn_cast<ConstantVector>(C)) {
905 for (unsigned i = 0; i != NumElements; ++i)
906 Ops.push_back(getValue(CP->getOperand(i)));
908 assert(isa<ConstantAggregateZero>(C) && "Unknown vector constant!");
909 EVT EltVT = TLI.getValueType(VecTy->getElementType());
912 if (EltVT.isFloatingPoint())
913 Op = DAG.getConstantFP(0, EltVT);
915 Op = DAG.getConstant(0, EltVT);
916 Ops.assign(NumElements, Op);
919 // Create a BUILD_VECTOR node.
920 return NodeMap[V] = DAG.getNode(ISD::BUILD_VECTOR, getCurDebugLoc(),
921 VT, &Ops[0], Ops.size());
924 // If this is a static alloca, generate it as the frameindex instead of
926 if (const AllocaInst *AI = dyn_cast<AllocaInst>(V)) {
927 DenseMap<const AllocaInst*, int>::iterator SI =
928 FuncInfo.StaticAllocaMap.find(AI);
929 if (SI != FuncInfo.StaticAllocaMap.end())
930 return DAG.getFrameIndex(SI->second, TLI.getPointerTy());
933 unsigned InReg = FuncInfo.ValueMap[V];
934 assert(InReg && "Value not in map!");
936 RegsForValue RFV(*DAG.getContext(), TLI, InReg, V->getType());
937 SDValue Chain = DAG.getEntryNode();
938 return RFV.getCopyFromRegs(DAG, getCurDebugLoc(), Chain, NULL);
942 void SelectionDAGLowering::visitRet(ReturnInst &I) {
943 SDValue Chain = getControlRoot();
944 SmallVector<ISD::OutputArg, 8> Outs;
945 for (unsigned i = 0, e = I.getNumOperands(); i != e; ++i) {
946 SmallVector<EVT, 4> ValueVTs;
947 ComputeValueVTs(TLI, I.getOperand(i)->getType(), ValueVTs);
948 unsigned NumValues = ValueVTs.size();
949 if (NumValues == 0) continue;
951 SDValue RetOp = getValue(I.getOperand(i));
952 for (unsigned j = 0, f = NumValues; j != f; ++j) {
953 EVT VT = ValueVTs[j];
955 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
957 const Function *F = I.getParent()->getParent();
958 if (F->paramHasAttr(0, Attribute::SExt))
959 ExtendKind = ISD::SIGN_EXTEND;
960 else if (F->paramHasAttr(0, Attribute::ZExt))
961 ExtendKind = ISD::ZERO_EXTEND;
963 // FIXME: C calling convention requires the return type to be promoted to
964 // at least 32-bit. But this is not necessary for non-C calling
965 // conventions. The frontend should mark functions whose return values
966 // require promoting with signext or zeroext attributes.
967 if (ExtendKind != ISD::ANY_EXTEND && VT.isInteger()) {
968 EVT MinVT = TLI.getRegisterType(*DAG.getContext(), MVT::i32);
969 if (VT.bitsLT(MinVT))
973 unsigned NumParts = TLI.getNumRegisters(*DAG.getContext(), VT);
974 EVT PartVT = TLI.getRegisterType(*DAG.getContext(), VT);
975 SmallVector<SDValue, 4> Parts(NumParts);
976 getCopyToParts(DAG, getCurDebugLoc(),
977 SDValue(RetOp.getNode(), RetOp.getResNo() + j),
978 &Parts[0], NumParts, PartVT, ExtendKind);
980 // 'inreg' on function refers to return value
981 ISD::ArgFlagsTy Flags = ISD::ArgFlagsTy();
982 if (F->paramHasAttr(0, Attribute::InReg))
985 // Propagate extension type if any
986 if (F->paramHasAttr(0, Attribute::SExt))
988 else if (F->paramHasAttr(0, Attribute::ZExt))
991 for (unsigned i = 0; i < NumParts; ++i)
992 Outs.push_back(ISD::OutputArg(Flags, Parts[i], /*isfixed=*/true));
996 bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg();
997 CallingConv::ID CallConv =
998 DAG.getMachineFunction().getFunction()->getCallingConv();
999 Chain = TLI.LowerReturn(Chain, CallConv, isVarArg,
1000 Outs, getCurDebugLoc(), DAG);
1002 // Verify that the target's LowerReturn behaved as expected.
1003 assert(Chain.getNode() && Chain.getValueType() == MVT::Other &&
1004 "LowerReturn didn't return a valid chain!");
1006 // Update the DAG with the new chain value resulting from return lowering.
1010 /// CopyToExportRegsIfNeeded - If the given value has virtual registers
1011 /// created for it, emit nodes to copy the value into the virtual
1013 void SelectionDAGLowering::CopyToExportRegsIfNeeded(Value *V) {
1014 if (!V->use_empty()) {
1015 DenseMap<const Value *, unsigned>::iterator VMI = FuncInfo.ValueMap.find(V);
1016 if (VMI != FuncInfo.ValueMap.end())
1017 CopyValueToVirtualRegister(V, VMI->second);
1021 /// ExportFromCurrentBlock - If this condition isn't known to be exported from
1022 /// the current basic block, add it to ValueMap now so that we'll get a
1024 void SelectionDAGLowering::ExportFromCurrentBlock(Value *V) {
1025 // No need to export constants.
1026 if (!isa<Instruction>(V) && !isa<Argument>(V)) return;
1028 // Already exported?
1029 if (FuncInfo.isExportedInst(V)) return;
1031 unsigned Reg = FuncInfo.InitializeRegForValue(V);
1032 CopyValueToVirtualRegister(V, Reg);
1035 bool SelectionDAGLowering::isExportableFromCurrentBlock(Value *V,
1036 const BasicBlock *FromBB) {
1037 // The operands of the setcc have to be in this block. We don't know
1038 // how to export them from some other block.
1039 if (Instruction *VI = dyn_cast<Instruction>(V)) {
1040 // Can export from current BB.
1041 if (VI->getParent() == FromBB)
1044 // Is already exported, noop.
1045 return FuncInfo.isExportedInst(V);
1048 // If this is an argument, we can export it if the BB is the entry block or
1049 // if it is already exported.
1050 if (isa<Argument>(V)) {
1051 if (FromBB == &FromBB->getParent()->getEntryBlock())
1054 // Otherwise, can only export this if it is already exported.
1055 return FuncInfo.isExportedInst(V);
1058 // Otherwise, constants can always be exported.
1062 static bool InBlock(const Value *V, const BasicBlock *BB) {
1063 if (const Instruction *I = dyn_cast<Instruction>(V))
1064 return I->getParent() == BB;
1068 /// getFCmpCondCode - Return the ISD condition code corresponding to
1069 /// the given LLVM IR floating-point condition code. This includes
1070 /// consideration of global floating-point math flags.
1072 static ISD::CondCode getFCmpCondCode(FCmpInst::Predicate Pred) {
1073 ISD::CondCode FPC, FOC;
1075 case FCmpInst::FCMP_FALSE: FOC = FPC = ISD::SETFALSE; break;
1076 case FCmpInst::FCMP_OEQ: FOC = ISD::SETEQ; FPC = ISD::SETOEQ; break;
1077 case FCmpInst::FCMP_OGT: FOC = ISD::SETGT; FPC = ISD::SETOGT; break;
1078 case FCmpInst::FCMP_OGE: FOC = ISD::SETGE; FPC = ISD::SETOGE; break;
1079 case FCmpInst::FCMP_OLT: FOC = ISD::SETLT; FPC = ISD::SETOLT; break;
1080 case FCmpInst::FCMP_OLE: FOC = ISD::SETLE; FPC = ISD::SETOLE; break;
1081 case FCmpInst::FCMP_ONE: FOC = ISD::SETNE; FPC = ISD::SETONE; break;
1082 case FCmpInst::FCMP_ORD: FOC = FPC = ISD::SETO; break;
1083 case FCmpInst::FCMP_UNO: FOC = FPC = ISD::SETUO; break;
1084 case FCmpInst::FCMP_UEQ: FOC = ISD::SETEQ; FPC = ISD::SETUEQ; break;
1085 case FCmpInst::FCMP_UGT: FOC = ISD::SETGT; FPC = ISD::SETUGT; break;
1086 case FCmpInst::FCMP_UGE: FOC = ISD::SETGE; FPC = ISD::SETUGE; break;
1087 case FCmpInst::FCMP_ULT: FOC = ISD::SETLT; FPC = ISD::SETULT; break;
1088 case FCmpInst::FCMP_ULE: FOC = ISD::SETLE; FPC = ISD::SETULE; break;
1089 case FCmpInst::FCMP_UNE: FOC = ISD::SETNE; FPC = ISD::SETUNE; break;
1090 case FCmpInst::FCMP_TRUE: FOC = FPC = ISD::SETTRUE; break;
1092 llvm_unreachable("Invalid FCmp predicate opcode!");
1093 FOC = FPC = ISD::SETFALSE;
1096 if (FiniteOnlyFPMath())
1102 /// getICmpCondCode - Return the ISD condition code corresponding to
1103 /// the given LLVM IR integer condition code.
1105 static ISD::CondCode getICmpCondCode(ICmpInst::Predicate Pred) {
1107 case ICmpInst::ICMP_EQ: return ISD::SETEQ;
1108 case ICmpInst::ICMP_NE: return ISD::SETNE;
1109 case ICmpInst::ICMP_SLE: return ISD::SETLE;
1110 case ICmpInst::ICMP_ULE: return ISD::SETULE;
1111 case ICmpInst::ICMP_SGE: return ISD::SETGE;
1112 case ICmpInst::ICMP_UGE: return ISD::SETUGE;
1113 case ICmpInst::ICMP_SLT: return ISD::SETLT;
1114 case ICmpInst::ICMP_ULT: return ISD::SETULT;
1115 case ICmpInst::ICMP_SGT: return ISD::SETGT;
1116 case ICmpInst::ICMP_UGT: return ISD::SETUGT;
1118 llvm_unreachable("Invalid ICmp predicate opcode!");
1123 /// EmitBranchForMergedCondition - Helper method for FindMergedConditions.
1124 /// This function emits a branch and is used at the leaves of an OR or an
1125 /// AND operator tree.
1128 SelectionDAGLowering::EmitBranchForMergedCondition(Value *Cond,
1129 MachineBasicBlock *TBB,
1130 MachineBasicBlock *FBB,
1131 MachineBasicBlock *CurBB) {
1132 const BasicBlock *BB = CurBB->getBasicBlock();
1134 // If the leaf of the tree is a comparison, merge the condition into
1136 if (CmpInst *BOp = dyn_cast<CmpInst>(Cond)) {
1137 // The operands of the cmp have to be in this block. We don't know
1138 // how to export them from some other block. If this is the first block
1139 // of the sequence, no exporting is needed.
1140 if (CurBB == CurMBB ||
1141 (isExportableFromCurrentBlock(BOp->getOperand(0), BB) &&
1142 isExportableFromCurrentBlock(BOp->getOperand(1), BB))) {
1143 ISD::CondCode Condition;
1144 if (ICmpInst *IC = dyn_cast<ICmpInst>(Cond)) {
1145 Condition = getICmpCondCode(IC->getPredicate());
1146 } else if (FCmpInst *FC = dyn_cast<FCmpInst>(Cond)) {
1147 Condition = getFCmpCondCode(FC->getPredicate());
1149 Condition = ISD::SETEQ; // silence warning.
1150 llvm_unreachable("Unknown compare instruction");
1153 CaseBlock CB(Condition, BOp->getOperand(0),
1154 BOp->getOperand(1), NULL, TBB, FBB, CurBB);
1155 SwitchCases.push_back(CB);
1160 // Create a CaseBlock record representing this branch.
1161 CaseBlock CB(ISD::SETEQ, Cond, ConstantInt::getTrue(*DAG.getContext()),
1162 NULL, TBB, FBB, CurBB);
1163 SwitchCases.push_back(CB);
1166 /// FindMergedConditions - If Cond is an expression like
1167 void SelectionDAGLowering::FindMergedConditions(Value *Cond,
1168 MachineBasicBlock *TBB,
1169 MachineBasicBlock *FBB,
1170 MachineBasicBlock *CurBB,
1172 // If this node is not part of the or/and tree, emit it as a branch.
1173 Instruction *BOp = dyn_cast<Instruction>(Cond);
1174 if (!BOp || !(isa<BinaryOperator>(BOp) || isa<CmpInst>(BOp)) ||
1175 (unsigned)BOp->getOpcode() != Opc || !BOp->hasOneUse() ||
1176 BOp->getParent() != CurBB->getBasicBlock() ||
1177 !InBlock(BOp->getOperand(0), CurBB->getBasicBlock()) ||
1178 !InBlock(BOp->getOperand(1), CurBB->getBasicBlock())) {
1179 EmitBranchForMergedCondition(Cond, TBB, FBB, CurBB);
1183 // Create TmpBB after CurBB.
1184 MachineFunction::iterator BBI = CurBB;
1185 MachineFunction &MF = DAG.getMachineFunction();
1186 MachineBasicBlock *TmpBB = MF.CreateMachineBasicBlock(CurBB->getBasicBlock());
1187 CurBB->getParent()->insert(++BBI, TmpBB);
1189 if (Opc == Instruction::Or) {
1190 // Codegen X | Y as:
1198 // Emit the LHS condition.
1199 FindMergedConditions(BOp->getOperand(0), TBB, TmpBB, CurBB, Opc);
1201 // Emit the RHS condition into TmpBB.
1202 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, Opc);
1204 assert(Opc == Instruction::And && "Unknown merge op!");
1205 // Codegen X & Y as:
1212 // This requires creation of TmpBB after CurBB.
1214 // Emit the LHS condition.
1215 FindMergedConditions(BOp->getOperand(0), TmpBB, FBB, CurBB, Opc);
1217 // Emit the RHS condition into TmpBB.
1218 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, Opc);
1222 /// If the set of cases should be emitted as a series of branches, return true.
1223 /// If we should emit this as a bunch of and/or'd together conditions, return
1226 SelectionDAGLowering::ShouldEmitAsBranches(const std::vector<CaseBlock> &Cases){
1227 if (Cases.size() != 2) return true;
1229 // If this is two comparisons of the same values or'd or and'd together, they
1230 // will get folded into a single comparison, so don't emit two blocks.
1231 if ((Cases[0].CmpLHS == Cases[1].CmpLHS &&
1232 Cases[0].CmpRHS == Cases[1].CmpRHS) ||
1233 (Cases[0].CmpRHS == Cases[1].CmpLHS &&
1234 Cases[0].CmpLHS == Cases[1].CmpRHS)) {
1241 void SelectionDAGLowering::visitBr(BranchInst &I) {
1242 // Update machine-CFG edges.
1243 MachineBasicBlock *Succ0MBB = FuncInfo.MBBMap[I.getSuccessor(0)];
1245 // Figure out which block is immediately after the current one.
1246 MachineBasicBlock *NextBlock = 0;
1247 MachineFunction::iterator BBI = CurMBB;
1248 if (++BBI != FuncInfo.MF->end())
1251 if (I.isUnconditional()) {
1252 // Update machine-CFG edges.
1253 CurMBB->addSuccessor(Succ0MBB);
1255 // If this is not a fall-through branch, emit the branch.
1256 if (Succ0MBB != NextBlock)
1257 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(),
1258 MVT::Other, getControlRoot(),
1259 DAG.getBasicBlock(Succ0MBB)));
1263 // If this condition is one of the special cases we handle, do special stuff
1265 Value *CondVal = I.getCondition();
1266 MachineBasicBlock *Succ1MBB = FuncInfo.MBBMap[I.getSuccessor(1)];
1268 // If this is a series of conditions that are or'd or and'd together, emit
1269 // this as a sequence of branches instead of setcc's with and/or operations.
1270 // For example, instead of something like:
1283 if (BinaryOperator *BOp = dyn_cast<BinaryOperator>(CondVal)) {
1284 if (BOp->hasOneUse() &&
1285 (BOp->getOpcode() == Instruction::And ||
1286 BOp->getOpcode() == Instruction::Or)) {
1287 FindMergedConditions(BOp, Succ0MBB, Succ1MBB, CurMBB, BOp->getOpcode());
1288 // If the compares in later blocks need to use values not currently
1289 // exported from this block, export them now. This block should always
1290 // be the first entry.
1291 assert(SwitchCases[0].ThisBB == CurMBB && "Unexpected lowering!");
1293 // Allow some cases to be rejected.
1294 if (ShouldEmitAsBranches(SwitchCases)) {
1295 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i) {
1296 ExportFromCurrentBlock(SwitchCases[i].CmpLHS);
1297 ExportFromCurrentBlock(SwitchCases[i].CmpRHS);
1300 // Emit the branch for this block.
1301 visitSwitchCase(SwitchCases[0]);
1302 SwitchCases.erase(SwitchCases.begin());
1306 // Okay, we decided not to do this, remove any inserted MBB's and clear
1308 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i)
1309 FuncInfo.MF->erase(SwitchCases[i].ThisBB);
1311 SwitchCases.clear();
1315 // Create a CaseBlock record representing this branch.
1316 CaseBlock CB(ISD::SETEQ, CondVal, ConstantInt::getTrue(*DAG.getContext()),
1317 NULL, Succ0MBB, Succ1MBB, CurMBB);
1318 // Use visitSwitchCase to actually insert the fast branch sequence for this
1320 visitSwitchCase(CB);
1323 /// visitSwitchCase - Emits the necessary code to represent a single node in
1324 /// the binary search tree resulting from lowering a switch instruction.
1325 void SelectionDAGLowering::visitSwitchCase(CaseBlock &CB) {
1327 SDValue CondLHS = getValue(CB.CmpLHS);
1328 DebugLoc dl = getCurDebugLoc();
1330 // Build the setcc now.
1331 if (CB.CmpMHS == NULL) {
1332 // Fold "(X == true)" to X and "(X == false)" to !X to
1333 // handle common cases produced by branch lowering.
1334 if (CB.CmpRHS == ConstantInt::getTrue(*DAG.getContext()) &&
1335 CB.CC == ISD::SETEQ)
1337 else if (CB.CmpRHS == ConstantInt::getFalse(*DAG.getContext()) &&
1338 CB.CC == ISD::SETEQ) {
1339 SDValue True = DAG.getConstant(1, CondLHS.getValueType());
1340 Cond = DAG.getNode(ISD::XOR, dl, CondLHS.getValueType(), CondLHS, True);
1342 Cond = DAG.getSetCC(dl, MVT::i1, CondLHS, getValue(CB.CmpRHS), CB.CC);
1344 assert(CB.CC == ISD::SETLE && "Can handle only LE ranges now");
1346 const APInt& Low = cast<ConstantInt>(CB.CmpLHS)->getValue();
1347 const APInt& High = cast<ConstantInt>(CB.CmpRHS)->getValue();
1349 SDValue CmpOp = getValue(CB.CmpMHS);
1350 EVT VT = CmpOp.getValueType();
1352 if (cast<ConstantInt>(CB.CmpLHS)->isMinValue(true)) {
1353 Cond = DAG.getSetCC(dl, MVT::i1, CmpOp, DAG.getConstant(High, VT),
1356 SDValue SUB = DAG.getNode(ISD::SUB, dl,
1357 VT, CmpOp, DAG.getConstant(Low, VT));
1358 Cond = DAG.getSetCC(dl, MVT::i1, SUB,
1359 DAG.getConstant(High-Low, VT), ISD::SETULE);
1363 // Update successor info
1364 CurMBB->addSuccessor(CB.TrueBB);
1365 CurMBB->addSuccessor(CB.FalseBB);
1367 // Set NextBlock to be the MBB immediately after the current one, if any.
1368 // This is used to avoid emitting unnecessary branches to the next block.
1369 MachineBasicBlock *NextBlock = 0;
1370 MachineFunction::iterator BBI = CurMBB;
1371 if (++BBI != FuncInfo.MF->end())
1374 // If the lhs block is the next block, invert the condition so that we can
1375 // fall through to the lhs instead of the rhs block.
1376 if (CB.TrueBB == NextBlock) {
1377 std::swap(CB.TrueBB, CB.FalseBB);
1378 SDValue True = DAG.getConstant(1, Cond.getValueType());
1379 Cond = DAG.getNode(ISD::XOR, dl, Cond.getValueType(), Cond, True);
1381 SDValue BrCond = DAG.getNode(ISD::BRCOND, dl,
1382 MVT::Other, getControlRoot(), Cond,
1383 DAG.getBasicBlock(CB.TrueBB));
1385 // If the branch was constant folded, fix up the CFG.
1386 if (BrCond.getOpcode() == ISD::BR) {
1387 CurMBB->removeSuccessor(CB.FalseBB);
1388 DAG.setRoot(BrCond);
1390 // Otherwise, go ahead and insert the false branch.
1391 if (BrCond == getControlRoot())
1392 CurMBB->removeSuccessor(CB.TrueBB);
1394 if (CB.FalseBB == NextBlock)
1395 DAG.setRoot(BrCond);
1397 DAG.setRoot(DAG.getNode(ISD::BR, dl, MVT::Other, BrCond,
1398 DAG.getBasicBlock(CB.FalseBB)));
1402 /// visitJumpTable - Emit JumpTable node in the current MBB
1403 void SelectionDAGLowering::visitJumpTable(JumpTable &JT) {
1404 // Emit the code for the jump table
1405 assert(JT.Reg != -1U && "Should lower JT Header first!");
1406 EVT PTy = TLI.getPointerTy();
1407 SDValue Index = DAG.getCopyFromReg(getControlRoot(), getCurDebugLoc(),
1409 SDValue Table = DAG.getJumpTable(JT.JTI, PTy);
1410 DAG.setRoot(DAG.getNode(ISD::BR_JT, getCurDebugLoc(),
1411 MVT::Other, Index.getValue(1),
1415 /// visitJumpTableHeader - This function emits necessary code to produce index
1416 /// in the JumpTable from switch case.
1417 void SelectionDAGLowering::visitJumpTableHeader(JumpTable &JT,
1418 JumpTableHeader &JTH) {
1419 // Subtract the lowest switch case value from the value being switched on and
1420 // conditional branch to default mbb if the result is greater than the
1421 // difference between smallest and largest cases.
1422 SDValue SwitchOp = getValue(JTH.SValue);
1423 EVT VT = SwitchOp.getValueType();
1424 SDValue SUB = DAG.getNode(ISD::SUB, getCurDebugLoc(), VT, SwitchOp,
1425 DAG.getConstant(JTH.First, VT));
1427 // The SDNode we just created, which holds the value being switched on minus
1428 // the the smallest case value, needs to be copied to a virtual register so it
1429 // can be used as an index into the jump table in a subsequent basic block.
1430 // This value may be smaller or larger than the target's pointer type, and
1431 // therefore require extension or truncating.
1432 SwitchOp = DAG.getZExtOrTrunc(SUB, getCurDebugLoc(), TLI.getPointerTy());
1434 unsigned JumpTableReg = FuncInfo.MakeReg(TLI.getPointerTy());
1435 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), getCurDebugLoc(),
1436 JumpTableReg, SwitchOp);
1437 JT.Reg = JumpTableReg;
1439 // Emit the range check for the jump table, and branch to the default block
1440 // for the switch statement if the value being switched on exceeds the largest
1441 // case in the switch.
1442 SDValue CMP = DAG.getSetCC(getCurDebugLoc(),
1443 TLI.getSetCCResultType(SUB.getValueType()), SUB,
1444 DAG.getConstant(JTH.Last-JTH.First,VT),
1447 // Set NextBlock to be the MBB immediately after the current one, if any.
1448 // This is used to avoid emitting unnecessary branches to the next block.
1449 MachineBasicBlock *NextBlock = 0;
1450 MachineFunction::iterator BBI = CurMBB;
1451 if (++BBI != FuncInfo.MF->end())
1454 SDValue BrCond = DAG.getNode(ISD::BRCOND, getCurDebugLoc(),
1455 MVT::Other, CopyTo, CMP,
1456 DAG.getBasicBlock(JT.Default));
1458 if (JT.MBB == NextBlock)
1459 DAG.setRoot(BrCond);
1461 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, BrCond,
1462 DAG.getBasicBlock(JT.MBB)));
1465 /// visitBitTestHeader - This function emits necessary code to produce value
1466 /// suitable for "bit tests"
1467 void SelectionDAGLowering::visitBitTestHeader(BitTestBlock &B) {
1468 // Subtract the minimum value
1469 SDValue SwitchOp = getValue(B.SValue);
1470 EVT VT = SwitchOp.getValueType();
1471 SDValue SUB = DAG.getNode(ISD::SUB, getCurDebugLoc(), VT, SwitchOp,
1472 DAG.getConstant(B.First, VT));
1475 SDValue RangeCmp = DAG.getSetCC(getCurDebugLoc(),
1476 TLI.getSetCCResultType(SUB.getValueType()),
1477 SUB, DAG.getConstant(B.Range, VT),
1480 SDValue ShiftOp = DAG.getZExtOrTrunc(SUB, getCurDebugLoc(), TLI.getPointerTy());
1482 B.Reg = FuncInfo.MakeReg(TLI.getPointerTy());
1483 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), getCurDebugLoc(),
1486 // Set NextBlock to be the MBB immediately after the current one, if any.
1487 // This is used to avoid emitting unnecessary branches to the next block.
1488 MachineBasicBlock *NextBlock = 0;
1489 MachineFunction::iterator BBI = CurMBB;
1490 if (++BBI != FuncInfo.MF->end())
1493 MachineBasicBlock* MBB = B.Cases[0].ThisBB;
1495 CurMBB->addSuccessor(B.Default);
1496 CurMBB->addSuccessor(MBB);
1498 SDValue BrRange = DAG.getNode(ISD::BRCOND, getCurDebugLoc(),
1499 MVT::Other, CopyTo, RangeCmp,
1500 DAG.getBasicBlock(B.Default));
1502 if (MBB == NextBlock)
1503 DAG.setRoot(BrRange);
1505 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, CopyTo,
1506 DAG.getBasicBlock(MBB)));
1509 /// visitBitTestCase - this function produces one "bit test"
1510 void SelectionDAGLowering::visitBitTestCase(MachineBasicBlock* NextMBB,
1513 // Make desired shift
1514 SDValue ShiftOp = DAG.getCopyFromReg(getControlRoot(), getCurDebugLoc(), Reg,
1515 TLI.getPointerTy());
1516 SDValue SwitchVal = DAG.getNode(ISD::SHL, getCurDebugLoc(),
1518 DAG.getConstant(1, TLI.getPointerTy()),
1521 // Emit bit tests and jumps
1522 SDValue AndOp = DAG.getNode(ISD::AND, getCurDebugLoc(),
1523 TLI.getPointerTy(), SwitchVal,
1524 DAG.getConstant(B.Mask, TLI.getPointerTy()));
1525 SDValue AndCmp = DAG.getSetCC(getCurDebugLoc(),
1526 TLI.getSetCCResultType(AndOp.getValueType()),
1527 AndOp, DAG.getConstant(0, TLI.getPointerTy()),
1530 CurMBB->addSuccessor(B.TargetBB);
1531 CurMBB->addSuccessor(NextMBB);
1533 SDValue BrAnd = DAG.getNode(ISD::BRCOND, getCurDebugLoc(),
1534 MVT::Other, getControlRoot(),
1535 AndCmp, DAG.getBasicBlock(B.TargetBB));
1537 // Set NextBlock to be the MBB immediately after the current one, if any.
1538 // This is used to avoid emitting unnecessary branches to the next block.
1539 MachineBasicBlock *NextBlock = 0;
1540 MachineFunction::iterator BBI = CurMBB;
1541 if (++BBI != FuncInfo.MF->end())
1544 if (NextMBB == NextBlock)
1547 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, BrAnd,
1548 DAG.getBasicBlock(NextMBB)));
1551 void SelectionDAGLowering::visitInvoke(InvokeInst &I) {
1552 // Retrieve successors.
1553 MachineBasicBlock *Return = FuncInfo.MBBMap[I.getSuccessor(0)];
1554 MachineBasicBlock *LandingPad = FuncInfo.MBBMap[I.getSuccessor(1)];
1556 const Value *Callee(I.getCalledValue());
1557 if (isa<InlineAsm>(Callee))
1560 LowerCallTo(&I, getValue(Callee), false, LandingPad);
1562 // If the value of the invoke is used outside of its defining block, make it
1563 // available as a virtual register.
1564 CopyToExportRegsIfNeeded(&I);
1566 // Update successor info
1567 CurMBB->addSuccessor(Return);
1568 CurMBB->addSuccessor(LandingPad);
1570 // Drop into normal successor.
1571 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(),
1572 MVT::Other, getControlRoot(),
1573 DAG.getBasicBlock(Return)));
1576 void SelectionDAGLowering::visitUnwind(UnwindInst &I) {
1579 /// handleSmallSwitchCaseRange - Emit a series of specific tests (suitable for
1580 /// small case ranges).
1581 bool SelectionDAGLowering::handleSmallSwitchRange(CaseRec& CR,
1582 CaseRecVector& WorkList,
1584 MachineBasicBlock* Default) {
1585 Case& BackCase = *(CR.Range.second-1);
1587 // Size is the number of Cases represented by this range.
1588 size_t Size = CR.Range.second - CR.Range.first;
1592 // Get the MachineFunction which holds the current MBB. This is used when
1593 // inserting any additional MBBs necessary to represent the switch.
1594 MachineFunction *CurMF = FuncInfo.MF;
1596 // Figure out which block is immediately after the current one.
1597 MachineBasicBlock *NextBlock = 0;
1598 MachineFunction::iterator BBI = CR.CaseBB;
1600 if (++BBI != FuncInfo.MF->end())
1603 // TODO: If any two of the cases has the same destination, and if one value
1604 // is the same as the other, but has one bit unset that the other has set,
1605 // use bit manipulation to do two compares at once. For example:
1606 // "if (X == 6 || X == 4)" -> "if ((X|2) == 6)"
1608 // Rearrange the case blocks so that the last one falls through if possible.
1609 if (NextBlock && Default != NextBlock && BackCase.BB != NextBlock) {
1610 // The last case block won't fall through into 'NextBlock' if we emit the
1611 // branches in this order. See if rearranging a case value would help.
1612 for (CaseItr I = CR.Range.first, E = CR.Range.second-1; I != E; ++I) {
1613 if (I->BB == NextBlock) {
1614 std::swap(*I, BackCase);
1620 // Create a CaseBlock record representing a conditional branch to
1621 // the Case's target mbb if the value being switched on SV is equal
1623 MachineBasicBlock *CurBlock = CR.CaseBB;
1624 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++I) {
1625 MachineBasicBlock *FallThrough;
1627 FallThrough = CurMF->CreateMachineBasicBlock(CurBlock->getBasicBlock());
1628 CurMF->insert(BBI, FallThrough);
1630 // Put SV in a virtual register to make it available from the new blocks.
1631 ExportFromCurrentBlock(SV);
1633 // If the last case doesn't match, go to the default block.
1634 FallThrough = Default;
1637 Value *RHS, *LHS, *MHS;
1639 if (I->High == I->Low) {
1640 // This is just small small case range :) containing exactly 1 case
1642 LHS = SV; RHS = I->High; MHS = NULL;
1645 LHS = I->Low; MHS = SV; RHS = I->High;
1647 CaseBlock CB(CC, LHS, RHS, MHS, I->BB, FallThrough, CurBlock);
1649 // If emitting the first comparison, just call visitSwitchCase to emit the
1650 // code into the current block. Otherwise, push the CaseBlock onto the
1651 // vector to be later processed by SDISel, and insert the node's MBB
1652 // before the next MBB.
1653 if (CurBlock == CurMBB)
1654 visitSwitchCase(CB);
1656 SwitchCases.push_back(CB);
1658 CurBlock = FallThrough;
1664 static inline bool areJTsAllowed(const TargetLowering &TLI) {
1665 return !DisableJumpTables &&
1666 (TLI.isOperationLegalOrCustom(ISD::BR_JT, MVT::Other) ||
1667 TLI.isOperationLegalOrCustom(ISD::BRIND, MVT::Other));
1670 static APInt ComputeRange(const APInt &First, const APInt &Last) {
1671 APInt LastExt(Last), FirstExt(First);
1672 uint32_t BitWidth = std::max(Last.getBitWidth(), First.getBitWidth()) + 1;
1673 LastExt.sext(BitWidth); FirstExt.sext(BitWidth);
1674 return (LastExt - FirstExt + 1ULL);
1677 /// handleJTSwitchCase - Emit jumptable for current switch case range
1678 bool SelectionDAGLowering::handleJTSwitchCase(CaseRec& CR,
1679 CaseRecVector& WorkList,
1681 MachineBasicBlock* Default) {
1682 Case& FrontCase = *CR.Range.first;
1683 Case& BackCase = *(CR.Range.second-1);
1685 const APInt& First = cast<ConstantInt>(FrontCase.Low)->getValue();
1686 const APInt& Last = cast<ConstantInt>(BackCase.High)->getValue();
1689 for (CaseItr I = CR.Range.first, E = CR.Range.second;
1693 if (!areJTsAllowed(TLI) || TSize <= 3)
1696 APInt Range = ComputeRange(First, Last);
1697 double Density = (double)TSize / Range.roundToDouble();
1701 DEBUG(errs() << "Lowering jump table\n"
1702 << "First entry: " << First << ". Last entry: " << Last << '\n'
1703 << "Range: " << Range
1704 << "Size: " << TSize << ". Density: " << Density << "\n\n");
1706 // Get the MachineFunction which holds the current MBB. This is used when
1707 // inserting any additional MBBs necessary to represent the switch.
1708 MachineFunction *CurMF = FuncInfo.MF;
1710 // Figure out which block is immediately after the current one.
1711 MachineFunction::iterator BBI = CR.CaseBB;
1714 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
1716 // Create a new basic block to hold the code for loading the address
1717 // of the jump table, and jumping to it. Update successor information;
1718 // we will either branch to the default case for the switch, or the jump
1720 MachineBasicBlock *JumpTableBB = CurMF->CreateMachineBasicBlock(LLVMBB);
1721 CurMF->insert(BBI, JumpTableBB);
1722 CR.CaseBB->addSuccessor(Default);
1723 CR.CaseBB->addSuccessor(JumpTableBB);
1725 // Build a vector of destination BBs, corresponding to each target
1726 // of the jump table. If the value of the jump table slot corresponds to
1727 // a case statement, push the case's BB onto the vector, otherwise, push
1729 std::vector<MachineBasicBlock*> DestBBs;
1731 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++TEI) {
1732 const APInt& Low = cast<ConstantInt>(I->Low)->getValue();
1733 const APInt& High = cast<ConstantInt>(I->High)->getValue();
1735 if (Low.sle(TEI) && TEI.sle(High)) {
1736 DestBBs.push_back(I->BB);
1740 DestBBs.push_back(Default);
1744 // Update successor info. Add one edge to each unique successor.
1745 BitVector SuccsHandled(CR.CaseBB->getParent()->getNumBlockIDs());
1746 for (std::vector<MachineBasicBlock*>::iterator I = DestBBs.begin(),
1747 E = DestBBs.end(); I != E; ++I) {
1748 if (!SuccsHandled[(*I)->getNumber()]) {
1749 SuccsHandled[(*I)->getNumber()] = true;
1750 JumpTableBB->addSuccessor(*I);
1754 // Create a jump table index for this jump table, or return an existing
1756 unsigned JTI = CurMF->getJumpTableInfo()->getJumpTableIndex(DestBBs);
1758 // Set the jump table information so that we can codegen it as a second
1759 // MachineBasicBlock
1760 JumpTable JT(-1U, JTI, JumpTableBB, Default);
1761 JumpTableHeader JTH(First, Last, SV, CR.CaseBB, (CR.CaseBB == CurMBB));
1762 if (CR.CaseBB == CurMBB)
1763 visitJumpTableHeader(JT, JTH);
1765 JTCases.push_back(JumpTableBlock(JTH, JT));
1770 /// handleBTSplitSwitchCase - emit comparison and split binary search tree into
1772 bool SelectionDAGLowering::handleBTSplitSwitchCase(CaseRec& CR,
1773 CaseRecVector& WorkList,
1775 MachineBasicBlock* Default) {
1776 // Get the MachineFunction which holds the current MBB. This is used when
1777 // inserting any additional MBBs necessary to represent the switch.
1778 MachineFunction *CurMF = FuncInfo.MF;
1780 // Figure out which block is immediately after the current one.
1781 MachineFunction::iterator BBI = CR.CaseBB;
1784 Case& FrontCase = *CR.Range.first;
1785 Case& BackCase = *(CR.Range.second-1);
1786 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
1788 // Size is the number of Cases represented by this range.
1789 unsigned Size = CR.Range.second - CR.Range.first;
1791 const APInt& First = cast<ConstantInt>(FrontCase.Low)->getValue();
1792 const APInt& Last = cast<ConstantInt>(BackCase.High)->getValue();
1794 CaseItr Pivot = CR.Range.first + Size/2;
1796 // Select optimal pivot, maximizing sum density of LHS and RHS. This will
1797 // (heuristically) allow us to emit JumpTable's later.
1799 for (CaseItr I = CR.Range.first, E = CR.Range.second;
1803 size_t LSize = FrontCase.size();
1804 size_t RSize = TSize-LSize;
1805 DEBUG(errs() << "Selecting best pivot: \n"
1806 << "First: " << First << ", Last: " << Last <<'\n'
1807 << "LSize: " << LSize << ", RSize: " << RSize << '\n');
1808 for (CaseItr I = CR.Range.first, J=I+1, E = CR.Range.second;
1810 const APInt& LEnd = cast<ConstantInt>(I->High)->getValue();
1811 const APInt& RBegin = cast<ConstantInt>(J->Low)->getValue();
1812 APInt Range = ComputeRange(LEnd, RBegin);
1813 assert((Range - 2ULL).isNonNegative() &&
1814 "Invalid case distance");
1815 double LDensity = (double)LSize / (LEnd - First + 1ULL).roundToDouble();
1816 double RDensity = (double)RSize / (Last - RBegin + 1ULL).roundToDouble();
1817 double Metric = Range.logBase2()*(LDensity+RDensity);
1818 // Should always split in some non-trivial place
1819 DEBUG(errs() <<"=>Step\n"
1820 << "LEnd: " << LEnd << ", RBegin: " << RBegin << '\n'
1821 << "LDensity: " << LDensity
1822 << ", RDensity: " << RDensity << '\n'
1823 << "Metric: " << Metric << '\n');
1824 if (FMetric < Metric) {
1827 DEBUG(errs() << "Current metric set to: " << FMetric << '\n');
1833 if (areJTsAllowed(TLI)) {
1834 // If our case is dense we *really* should handle it earlier!
1835 assert((FMetric > 0) && "Should handle dense range earlier!");
1837 Pivot = CR.Range.first + Size/2;
1840 CaseRange LHSR(CR.Range.first, Pivot);
1841 CaseRange RHSR(Pivot, CR.Range.second);
1842 Constant *C = Pivot->Low;
1843 MachineBasicBlock *FalseBB = 0, *TrueBB = 0;
1845 // We know that we branch to the LHS if the Value being switched on is
1846 // less than the Pivot value, C. We use this to optimize our binary
1847 // tree a bit, by recognizing that if SV is greater than or equal to the
1848 // LHS's Case Value, and that Case Value is exactly one less than the
1849 // Pivot's Value, then we can branch directly to the LHS's Target,
1850 // rather than creating a leaf node for it.
1851 if ((LHSR.second - LHSR.first) == 1 &&
1852 LHSR.first->High == CR.GE &&
1853 cast<ConstantInt>(C)->getValue() ==
1854 (cast<ConstantInt>(CR.GE)->getValue() + 1LL)) {
1855 TrueBB = LHSR.first->BB;
1857 TrueBB = CurMF->CreateMachineBasicBlock(LLVMBB);
1858 CurMF->insert(BBI, TrueBB);
1859 WorkList.push_back(CaseRec(TrueBB, C, CR.GE, LHSR));
1861 // Put SV in a virtual register to make it available from the new blocks.
1862 ExportFromCurrentBlock(SV);
1865 // Similar to the optimization above, if the Value being switched on is
1866 // known to be less than the Constant CR.LT, and the current Case Value
1867 // is CR.LT - 1, then we can branch directly to the target block for
1868 // the current Case Value, rather than emitting a RHS leaf node for it.
1869 if ((RHSR.second - RHSR.first) == 1 && CR.LT &&
1870 cast<ConstantInt>(RHSR.first->Low)->getValue() ==
1871 (cast<ConstantInt>(CR.LT)->getValue() - 1LL)) {
1872 FalseBB = RHSR.first->BB;
1874 FalseBB = CurMF->CreateMachineBasicBlock(LLVMBB);
1875 CurMF->insert(BBI, FalseBB);
1876 WorkList.push_back(CaseRec(FalseBB,CR.LT,C,RHSR));
1878 // Put SV in a virtual register to make it available from the new blocks.
1879 ExportFromCurrentBlock(SV);
1882 // Create a CaseBlock record representing a conditional branch to
1883 // the LHS node if the value being switched on SV is less than C.
1884 // Otherwise, branch to LHS.
1885 CaseBlock CB(ISD::SETLT, SV, C, NULL, TrueBB, FalseBB, CR.CaseBB);
1887 if (CR.CaseBB == CurMBB)
1888 visitSwitchCase(CB);
1890 SwitchCases.push_back(CB);
1895 /// handleBitTestsSwitchCase - if current case range has few destination and
1896 /// range span less, than machine word bitwidth, encode case range into series
1897 /// of masks and emit bit tests with these masks.
1898 bool SelectionDAGLowering::handleBitTestsSwitchCase(CaseRec& CR,
1899 CaseRecVector& WorkList,
1901 MachineBasicBlock* Default){
1902 EVT PTy = TLI.getPointerTy();
1903 unsigned IntPtrBits = PTy.getSizeInBits();
1905 Case& FrontCase = *CR.Range.first;
1906 Case& BackCase = *(CR.Range.second-1);
1908 // Get the MachineFunction which holds the current MBB. This is used when
1909 // inserting any additional MBBs necessary to represent the switch.
1910 MachineFunction *CurMF = FuncInfo.MF;
1912 // If target does not have legal shift left, do not emit bit tests at all.
1913 if (!TLI.isOperationLegal(ISD::SHL, TLI.getPointerTy()))
1917 for (CaseItr I = CR.Range.first, E = CR.Range.second;
1919 // Single case counts one, case range - two.
1920 numCmps += (I->Low == I->High ? 1 : 2);
1923 // Count unique destinations
1924 SmallSet<MachineBasicBlock*, 4> Dests;
1925 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) {
1926 Dests.insert(I->BB);
1927 if (Dests.size() > 3)
1928 // Don't bother the code below, if there are too much unique destinations
1931 DEBUG(errs() << "Total number of unique destinations: " << Dests.size() << '\n'
1932 << "Total number of comparisons: " << numCmps << '\n');
1934 // Compute span of values.
1935 const APInt& minValue = cast<ConstantInt>(FrontCase.Low)->getValue();
1936 const APInt& maxValue = cast<ConstantInt>(BackCase.High)->getValue();
1937 APInt cmpRange = maxValue - minValue;
1939 DEBUG(errs() << "Compare range: " << cmpRange << '\n'
1940 << "Low bound: " << minValue << '\n'
1941 << "High bound: " << maxValue << '\n');
1943 if (cmpRange.uge(APInt(cmpRange.getBitWidth(), IntPtrBits)) ||
1944 (!(Dests.size() == 1 && numCmps >= 3) &&
1945 !(Dests.size() == 2 && numCmps >= 5) &&
1946 !(Dests.size() >= 3 && numCmps >= 6)))
1949 DEBUG(errs() << "Emitting bit tests\n");
1950 APInt lowBound = APInt::getNullValue(cmpRange.getBitWidth());
1952 // Optimize the case where all the case values fit in a
1953 // word without having to subtract minValue. In this case,
1954 // we can optimize away the subtraction.
1955 if (minValue.isNonNegative() &&
1956 maxValue.slt(APInt(maxValue.getBitWidth(), IntPtrBits))) {
1957 cmpRange = maxValue;
1959 lowBound = minValue;
1962 CaseBitsVector CasesBits;
1963 unsigned i, count = 0;
1965 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) {
1966 MachineBasicBlock* Dest = I->BB;
1967 for (i = 0; i < count; ++i)
1968 if (Dest == CasesBits[i].BB)
1972 assert((count < 3) && "Too much destinations to test!");
1973 CasesBits.push_back(CaseBits(0, Dest, 0));
1977 const APInt& lowValue = cast<ConstantInt>(I->Low)->getValue();
1978 const APInt& highValue = cast<ConstantInt>(I->High)->getValue();
1980 uint64_t lo = (lowValue - lowBound).getZExtValue();
1981 uint64_t hi = (highValue - lowBound).getZExtValue();
1983 for (uint64_t j = lo; j <= hi; j++) {
1984 CasesBits[i].Mask |= 1ULL << j;
1985 CasesBits[i].Bits++;
1989 std::sort(CasesBits.begin(), CasesBits.end(), CaseBitsCmp());
1993 // Figure out which block is immediately after the current one.
1994 MachineFunction::iterator BBI = CR.CaseBB;
1997 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
1999 DEBUG(errs() << "Cases:\n");
2000 for (unsigned i = 0, e = CasesBits.size(); i!=e; ++i) {
2001 DEBUG(errs() << "Mask: " << CasesBits[i].Mask
2002 << ", Bits: " << CasesBits[i].Bits
2003 << ", BB: " << CasesBits[i].BB << '\n');
2005 MachineBasicBlock *CaseBB = CurMF->CreateMachineBasicBlock(LLVMBB);
2006 CurMF->insert(BBI, CaseBB);
2007 BTC.push_back(BitTestCase(CasesBits[i].Mask,
2011 // Put SV in a virtual register to make it available from the new blocks.
2012 ExportFromCurrentBlock(SV);
2015 BitTestBlock BTB(lowBound, cmpRange, SV,
2016 -1U, (CR.CaseBB == CurMBB),
2017 CR.CaseBB, Default, BTC);
2019 if (CR.CaseBB == CurMBB)
2020 visitBitTestHeader(BTB);
2022 BitTestCases.push_back(BTB);
2028 /// Clusterify - Transform simple list of Cases into list of CaseRange's
2029 size_t SelectionDAGLowering::Clusterify(CaseVector& Cases,
2030 const SwitchInst& SI) {
2033 // Start with "simple" cases
2034 for (size_t i = 1; i < SI.getNumSuccessors(); ++i) {
2035 MachineBasicBlock *SMBB = FuncInfo.MBBMap[SI.getSuccessor(i)];
2036 Cases.push_back(Case(SI.getSuccessorValue(i),
2037 SI.getSuccessorValue(i),
2040 std::sort(Cases.begin(), Cases.end(), CaseCmp());
2042 // Merge case into clusters
2043 if (Cases.size() >= 2)
2044 // Must recompute end() each iteration because it may be
2045 // invalidated by erase if we hold on to it
2046 for (CaseItr I = Cases.begin(), J = ++(Cases.begin()); J != Cases.end(); ) {
2047 const APInt& nextValue = cast<ConstantInt>(J->Low)->getValue();
2048 const APInt& currentValue = cast<ConstantInt>(I->High)->getValue();
2049 MachineBasicBlock* nextBB = J->BB;
2050 MachineBasicBlock* currentBB = I->BB;
2052 // If the two neighboring cases go to the same destination, merge them
2053 // into a single case.
2054 if ((nextValue - currentValue == 1) && (currentBB == nextBB)) {
2062 for (CaseItr I=Cases.begin(), E=Cases.end(); I!=E; ++I, ++numCmps) {
2063 if (I->Low != I->High)
2064 // A range counts double, since it requires two compares.
2071 void SelectionDAGLowering::visitSwitch(SwitchInst &SI) {
2072 // Figure out which block is immediately after the current one.
2073 MachineBasicBlock *NextBlock = 0;
2075 MachineBasicBlock *Default = FuncInfo.MBBMap[SI.getDefaultDest()];
2077 // If there is only the default destination, branch to it if it is not the
2078 // next basic block. Otherwise, just fall through.
2079 if (SI.getNumOperands() == 2) {
2080 // Update machine-CFG edges.
2082 // If this is not a fall-through branch, emit the branch.
2083 CurMBB->addSuccessor(Default);
2084 if (Default != NextBlock)
2085 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(),
2086 MVT::Other, getControlRoot(),
2087 DAG.getBasicBlock(Default)));
2091 // If there are any non-default case statements, create a vector of Cases
2092 // representing each one, and sort the vector so that we can efficiently
2093 // create a binary search tree from them.
2095 size_t numCmps = Clusterify(Cases, SI);
2096 DEBUG(errs() << "Clusterify finished. Total clusters: " << Cases.size()
2097 << ". Total compares: " << numCmps << '\n');
2100 // Get the Value to be switched on and default basic blocks, which will be
2101 // inserted into CaseBlock records, representing basic blocks in the binary
2103 Value *SV = SI.getOperand(0);
2105 // Push the initial CaseRec onto the worklist
2106 CaseRecVector WorkList;
2107 WorkList.push_back(CaseRec(CurMBB,0,0,CaseRange(Cases.begin(),Cases.end())));
2109 while (!WorkList.empty()) {
2110 // Grab a record representing a case range to process off the worklist
2111 CaseRec CR = WorkList.back();
2112 WorkList.pop_back();
2114 if (handleBitTestsSwitchCase(CR, WorkList, SV, Default))
2117 // If the range has few cases (two or less) emit a series of specific
2119 if (handleSmallSwitchRange(CR, WorkList, SV, Default))
2122 // If the switch has more than 5 blocks, and at least 40% dense, and the
2123 // target supports indirect branches, then emit a jump table rather than
2124 // lowering the switch to a binary tree of conditional branches.
2125 if (handleJTSwitchCase(CR, WorkList, SV, Default))
2128 // Emit binary tree. We need to pick a pivot, and push left and right ranges
2129 // onto the worklist. Leafs are handled via handleSmallSwitchRange() call.
2130 handleBTSplitSwitchCase(CR, WorkList, SV, Default);
2134 void SelectionDAGLowering::visitIndirectBr(IndirectBrInst &I) {
2135 // Update machine-CFG edges.
2136 for (unsigned i = 0, e = I.getNumSuccessors(); i != e; ++i)
2137 CurMBB->addSuccessor(FuncInfo.MBBMap[I.getSuccessor(i)]);
2139 DAG.setRoot(DAG.getNode(ISD::BRIND, getCurDebugLoc(),
2140 MVT::Other, getControlRoot(),
2141 getValue(I.getAddress())));
2145 void SelectionDAGLowering::visitFSub(User &I) {
2146 // -0.0 - X --> fneg
2147 const Type *Ty = I.getType();
2148 if (isa<VectorType>(Ty)) {
2149 if (ConstantVector *CV = dyn_cast<ConstantVector>(I.getOperand(0))) {
2150 const VectorType *DestTy = cast<VectorType>(I.getType());
2151 const Type *ElTy = DestTy->getElementType();
2152 unsigned VL = DestTy->getNumElements();
2153 std::vector<Constant*> NZ(VL, ConstantFP::getNegativeZero(ElTy));
2154 Constant *CNZ = ConstantVector::get(&NZ[0], NZ.size());
2156 SDValue Op2 = getValue(I.getOperand(1));
2157 setValue(&I, DAG.getNode(ISD::FNEG, getCurDebugLoc(),
2158 Op2.getValueType(), Op2));
2163 if (ConstantFP *CFP = dyn_cast<ConstantFP>(I.getOperand(0)))
2164 if (CFP->isExactlyValue(ConstantFP::getNegativeZero(Ty)->getValueAPF())) {
2165 SDValue Op2 = getValue(I.getOperand(1));
2166 setValue(&I, DAG.getNode(ISD::FNEG, getCurDebugLoc(),
2167 Op2.getValueType(), Op2));
2171 visitBinary(I, ISD::FSUB);
2174 void SelectionDAGLowering::visitBinary(User &I, unsigned OpCode) {
2175 SDValue Op1 = getValue(I.getOperand(0));
2176 SDValue Op2 = getValue(I.getOperand(1));
2178 setValue(&I, DAG.getNode(OpCode, getCurDebugLoc(),
2179 Op1.getValueType(), Op1, Op2));
2182 void SelectionDAGLowering::visitShift(User &I, unsigned Opcode) {
2183 SDValue Op1 = getValue(I.getOperand(0));
2184 SDValue Op2 = getValue(I.getOperand(1));
2185 if (!isa<VectorType>(I.getType()) &&
2186 Op2.getValueType() != TLI.getShiftAmountTy()) {
2187 // If the operand is smaller than the shift count type, promote it.
2188 EVT PTy = TLI.getPointerTy();
2189 EVT STy = TLI.getShiftAmountTy();
2190 if (STy.bitsGT(Op2.getValueType()))
2191 Op2 = DAG.getNode(ISD::ANY_EXTEND, getCurDebugLoc(),
2192 TLI.getShiftAmountTy(), Op2);
2193 // If the operand is larger than the shift count type but the shift
2194 // count type has enough bits to represent any shift value, truncate
2195 // it now. This is a common case and it exposes the truncate to
2196 // optimization early.
2197 else if (STy.getSizeInBits() >=
2198 Log2_32_Ceil(Op2.getValueType().getSizeInBits()))
2199 Op2 = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(),
2200 TLI.getShiftAmountTy(), Op2);
2201 // Otherwise we'll need to temporarily settle for some other
2202 // convenient type; type legalization will make adjustments as
2204 else if (PTy.bitsLT(Op2.getValueType()))
2205 Op2 = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(),
2206 TLI.getPointerTy(), Op2);
2207 else if (PTy.bitsGT(Op2.getValueType()))
2208 Op2 = DAG.getNode(ISD::ANY_EXTEND, getCurDebugLoc(),
2209 TLI.getPointerTy(), Op2);
2212 setValue(&I, DAG.getNode(Opcode, getCurDebugLoc(),
2213 Op1.getValueType(), Op1, Op2));
2216 void SelectionDAGLowering::visitICmp(User &I) {
2217 ICmpInst::Predicate predicate = ICmpInst::BAD_ICMP_PREDICATE;
2218 if (ICmpInst *IC = dyn_cast<ICmpInst>(&I))
2219 predicate = IC->getPredicate();
2220 else if (ConstantExpr *IC = dyn_cast<ConstantExpr>(&I))
2221 predicate = ICmpInst::Predicate(IC->getPredicate());
2222 SDValue Op1 = getValue(I.getOperand(0));
2223 SDValue Op2 = getValue(I.getOperand(1));
2224 ISD::CondCode Opcode = getICmpCondCode(predicate);
2226 EVT DestVT = TLI.getValueType(I.getType());
2227 setValue(&I, DAG.getSetCC(getCurDebugLoc(), DestVT, Op1, Op2, Opcode));
2230 void SelectionDAGLowering::visitFCmp(User &I) {
2231 FCmpInst::Predicate predicate = FCmpInst::BAD_FCMP_PREDICATE;
2232 if (FCmpInst *FC = dyn_cast<FCmpInst>(&I))
2233 predicate = FC->getPredicate();
2234 else if (ConstantExpr *FC = dyn_cast<ConstantExpr>(&I))
2235 predicate = FCmpInst::Predicate(FC->getPredicate());
2236 SDValue Op1 = getValue(I.getOperand(0));
2237 SDValue Op2 = getValue(I.getOperand(1));
2238 ISD::CondCode Condition = getFCmpCondCode(predicate);
2239 EVT DestVT = TLI.getValueType(I.getType());
2240 setValue(&I, DAG.getSetCC(getCurDebugLoc(), DestVT, Op1, Op2, Condition));
2243 void SelectionDAGLowering::visitSelect(User &I) {
2244 SmallVector<EVT, 4> ValueVTs;
2245 ComputeValueVTs(TLI, I.getType(), ValueVTs);
2246 unsigned NumValues = ValueVTs.size();
2247 if (NumValues != 0) {
2248 SmallVector<SDValue, 4> Values(NumValues);
2249 SDValue Cond = getValue(I.getOperand(0));
2250 SDValue TrueVal = getValue(I.getOperand(1));
2251 SDValue FalseVal = getValue(I.getOperand(2));
2253 for (unsigned i = 0; i != NumValues; ++i)
2254 Values[i] = DAG.getNode(ISD::SELECT, getCurDebugLoc(),
2255 TrueVal.getValueType(), Cond,
2256 SDValue(TrueVal.getNode(), TrueVal.getResNo() + i),
2257 SDValue(FalseVal.getNode(), FalseVal.getResNo() + i));
2259 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(),
2260 DAG.getVTList(&ValueVTs[0], NumValues),
2261 &Values[0], NumValues));
2266 void SelectionDAGLowering::visitTrunc(User &I) {
2267 // TruncInst cannot be a no-op cast because sizeof(src) > sizeof(dest).
2268 SDValue N = getValue(I.getOperand(0));
2269 EVT DestVT = TLI.getValueType(I.getType());
2270 setValue(&I, DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), DestVT, N));
2273 void SelectionDAGLowering::visitZExt(User &I) {
2274 // ZExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
2275 // ZExt also can't be a cast to bool for same reason. So, nothing much to do
2276 SDValue N = getValue(I.getOperand(0));
2277 EVT DestVT = TLI.getValueType(I.getType());
2278 setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(), DestVT, N));
2281 void SelectionDAGLowering::visitSExt(User &I) {
2282 // SExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
2283 // SExt also can't be a cast to bool for same reason. So, nothing much to do
2284 SDValue N = getValue(I.getOperand(0));
2285 EVT DestVT = TLI.getValueType(I.getType());
2286 setValue(&I, DAG.getNode(ISD::SIGN_EXTEND, getCurDebugLoc(), DestVT, N));
2289 void SelectionDAGLowering::visitFPTrunc(User &I) {
2290 // FPTrunc is never a no-op cast, no need to check
2291 SDValue N = getValue(I.getOperand(0));
2292 EVT DestVT = TLI.getValueType(I.getType());
2293 setValue(&I, DAG.getNode(ISD::FP_ROUND, getCurDebugLoc(),
2294 DestVT, N, DAG.getIntPtrConstant(0)));
2297 void SelectionDAGLowering::visitFPExt(User &I){
2298 // FPTrunc is never a no-op cast, no need to check
2299 SDValue N = getValue(I.getOperand(0));
2300 EVT DestVT = TLI.getValueType(I.getType());
2301 setValue(&I, DAG.getNode(ISD::FP_EXTEND, getCurDebugLoc(), DestVT, N));
2304 void SelectionDAGLowering::visitFPToUI(User &I) {
2305 // FPToUI is never a no-op cast, no need to check
2306 SDValue N = getValue(I.getOperand(0));
2307 EVT DestVT = TLI.getValueType(I.getType());
2308 setValue(&I, DAG.getNode(ISD::FP_TO_UINT, getCurDebugLoc(), DestVT, N));
2311 void SelectionDAGLowering::visitFPToSI(User &I) {
2312 // FPToSI is never a no-op cast, no need to check
2313 SDValue N = getValue(I.getOperand(0));
2314 EVT DestVT = TLI.getValueType(I.getType());
2315 setValue(&I, DAG.getNode(ISD::FP_TO_SINT, getCurDebugLoc(), DestVT, N));
2318 void SelectionDAGLowering::visitUIToFP(User &I) {
2319 // UIToFP is never a no-op cast, no need to check
2320 SDValue N = getValue(I.getOperand(0));
2321 EVT DestVT = TLI.getValueType(I.getType());
2322 setValue(&I, DAG.getNode(ISD::UINT_TO_FP, getCurDebugLoc(), DestVT, N));
2325 void SelectionDAGLowering::visitSIToFP(User &I){
2326 // SIToFP is never a no-op cast, no need to check
2327 SDValue N = getValue(I.getOperand(0));
2328 EVT DestVT = TLI.getValueType(I.getType());
2329 setValue(&I, DAG.getNode(ISD::SINT_TO_FP, getCurDebugLoc(), DestVT, N));
2332 void SelectionDAGLowering::visitPtrToInt(User &I) {
2333 // What to do depends on the size of the integer and the size of the pointer.
2334 // We can either truncate, zero extend, or no-op, accordingly.
2335 SDValue N = getValue(I.getOperand(0));
2336 EVT SrcVT = N.getValueType();
2337 EVT DestVT = TLI.getValueType(I.getType());
2338 SDValue Result = DAG.getZExtOrTrunc(N, getCurDebugLoc(), DestVT);
2339 setValue(&I, Result);
2342 void SelectionDAGLowering::visitIntToPtr(User &I) {
2343 // What to do depends on the size of the integer and the size of the pointer.
2344 // We can either truncate, zero extend, or no-op, accordingly.
2345 SDValue N = getValue(I.getOperand(0));
2346 EVT SrcVT = N.getValueType();
2347 EVT DestVT = TLI.getValueType(I.getType());
2348 setValue(&I, DAG.getZExtOrTrunc(N, getCurDebugLoc(), DestVT));
2351 void SelectionDAGLowering::visitBitCast(User &I) {
2352 SDValue N = getValue(I.getOperand(0));
2353 EVT DestVT = TLI.getValueType(I.getType());
2355 // BitCast assures us that source and destination are the same size so this
2356 // is either a BIT_CONVERT or a no-op.
2357 if (DestVT != N.getValueType())
2358 setValue(&I, DAG.getNode(ISD::BIT_CONVERT, getCurDebugLoc(),
2359 DestVT, N)); // convert types
2361 setValue(&I, N); // noop cast.
2364 void SelectionDAGLowering::visitInsertElement(User &I) {
2365 SDValue InVec = getValue(I.getOperand(0));
2366 SDValue InVal = getValue(I.getOperand(1));
2367 SDValue InIdx = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(),
2369 getValue(I.getOperand(2)));
2371 setValue(&I, DAG.getNode(ISD::INSERT_VECTOR_ELT, getCurDebugLoc(),
2372 TLI.getValueType(I.getType()),
2373 InVec, InVal, InIdx));
2376 void SelectionDAGLowering::visitExtractElement(User &I) {
2377 SDValue InVec = getValue(I.getOperand(0));
2378 SDValue InIdx = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(),
2380 getValue(I.getOperand(1)));
2381 setValue(&I, DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurDebugLoc(),
2382 TLI.getValueType(I.getType()), InVec, InIdx));
2386 // Utility for visitShuffleVector - Returns true if the mask is mask starting
2387 // from SIndx and increasing to the element length (undefs are allowed).
2388 static bool SequentialMask(SmallVectorImpl<int> &Mask, unsigned SIndx) {
2389 unsigned MaskNumElts = Mask.size();
2390 for (unsigned i = 0; i != MaskNumElts; ++i)
2391 if ((Mask[i] >= 0) && (Mask[i] != (int)(i + SIndx)))
2396 void SelectionDAGLowering::visitShuffleVector(User &I) {
2397 SmallVector<int, 8> Mask;
2398 SDValue Src1 = getValue(I.getOperand(0));
2399 SDValue Src2 = getValue(I.getOperand(1));
2401 // Convert the ConstantVector mask operand into an array of ints, with -1
2402 // representing undef values.
2403 SmallVector<Constant*, 8> MaskElts;
2404 cast<Constant>(I.getOperand(2))->getVectorElements(*DAG.getContext(),
2406 unsigned MaskNumElts = MaskElts.size();
2407 for (unsigned i = 0; i != MaskNumElts; ++i) {
2408 if (isa<UndefValue>(MaskElts[i]))
2411 Mask.push_back(cast<ConstantInt>(MaskElts[i])->getSExtValue());
2414 EVT VT = TLI.getValueType(I.getType());
2415 EVT SrcVT = Src1.getValueType();
2416 unsigned SrcNumElts = SrcVT.getVectorNumElements();
2418 if (SrcNumElts == MaskNumElts) {
2419 setValue(&I, DAG.getVectorShuffle(VT, getCurDebugLoc(), Src1, Src2,
2424 // Normalize the shuffle vector since mask and vector length don't match.
2425 if (SrcNumElts < MaskNumElts && MaskNumElts % SrcNumElts == 0) {
2426 // Mask is longer than the source vectors and is a multiple of the source
2427 // vectors. We can use concatenate vector to make the mask and vectors
2429 if (SrcNumElts*2 == MaskNumElts && SequentialMask(Mask, 0)) {
2430 // The shuffle is concatenating two vectors together.
2431 setValue(&I, DAG.getNode(ISD::CONCAT_VECTORS, getCurDebugLoc(),
2436 // Pad both vectors with undefs to make them the same length as the mask.
2437 unsigned NumConcat = MaskNumElts / SrcNumElts;
2438 bool Src1U = Src1.getOpcode() == ISD::UNDEF;
2439 bool Src2U = Src2.getOpcode() == ISD::UNDEF;
2440 SDValue UndefVal = DAG.getUNDEF(SrcVT);
2442 SmallVector<SDValue, 8> MOps1(NumConcat, UndefVal);
2443 SmallVector<SDValue, 8> MOps2(NumConcat, UndefVal);
2447 Src1 = Src1U ? DAG.getUNDEF(VT) : DAG.getNode(ISD::CONCAT_VECTORS,
2448 getCurDebugLoc(), VT,
2449 &MOps1[0], NumConcat);
2450 Src2 = Src2U ? DAG.getUNDEF(VT) : DAG.getNode(ISD::CONCAT_VECTORS,
2451 getCurDebugLoc(), VT,
2452 &MOps2[0], NumConcat);
2454 // Readjust mask for new input vector length.
2455 SmallVector<int, 8> MappedOps;
2456 for (unsigned i = 0; i != MaskNumElts; ++i) {
2458 if (Idx < (int)SrcNumElts)
2459 MappedOps.push_back(Idx);
2461 MappedOps.push_back(Idx + MaskNumElts - SrcNumElts);
2463 setValue(&I, DAG.getVectorShuffle(VT, getCurDebugLoc(), Src1, Src2,
2468 if (SrcNumElts > MaskNumElts) {
2469 // Analyze the access pattern of the vector to see if we can extract
2470 // two subvectors and do the shuffle. The analysis is done by calculating
2471 // the range of elements the mask access on both vectors.
2472 int MinRange[2] = { SrcNumElts+1, SrcNumElts+1};
2473 int MaxRange[2] = {-1, -1};
2475 for (unsigned i = 0; i != MaskNumElts; ++i) {
2481 if (Idx >= (int)SrcNumElts) {
2485 if (Idx > MaxRange[Input])
2486 MaxRange[Input] = Idx;
2487 if (Idx < MinRange[Input])
2488 MinRange[Input] = Idx;
2491 // Check if the access is smaller than the vector size and can we find
2492 // a reasonable extract index.
2493 int RangeUse[2] = { 2, 2 }; // 0 = Unused, 1 = Extract, 2 = Can not Extract.
2494 int StartIdx[2]; // StartIdx to extract from
2495 for (int Input=0; Input < 2; ++Input) {
2496 if (MinRange[Input] == (int)(SrcNumElts+1) && MaxRange[Input] == -1) {
2497 RangeUse[Input] = 0; // Unused
2498 StartIdx[Input] = 0;
2499 } else if (MaxRange[Input] - MinRange[Input] < (int)MaskNumElts) {
2500 // Fits within range but we should see if we can find a good
2501 // start index that is a multiple of the mask length.
2502 if (MaxRange[Input] < (int)MaskNumElts) {
2503 RangeUse[Input] = 1; // Extract from beginning of the vector
2504 StartIdx[Input] = 0;
2506 StartIdx[Input] = (MinRange[Input]/MaskNumElts)*MaskNumElts;
2507 if (MaxRange[Input] - StartIdx[Input] < (int)MaskNumElts &&
2508 StartIdx[Input] + MaskNumElts < SrcNumElts)
2509 RangeUse[Input] = 1; // Extract from a multiple of the mask length.
2514 if (RangeUse[0] == 0 && RangeUse[1] == 0) {
2515 setValue(&I, DAG.getUNDEF(VT)); // Vectors are not used.
2518 else if (RangeUse[0] < 2 && RangeUse[1] < 2) {
2519 // Extract appropriate subvector and generate a vector shuffle
2520 for (int Input=0; Input < 2; ++Input) {
2521 SDValue& Src = Input == 0 ? Src1 : Src2;
2522 if (RangeUse[Input] == 0) {
2523 Src = DAG.getUNDEF(VT);
2525 Src = DAG.getNode(ISD::EXTRACT_SUBVECTOR, getCurDebugLoc(), VT,
2526 Src, DAG.getIntPtrConstant(StartIdx[Input]));
2529 // Calculate new mask.
2530 SmallVector<int, 8> MappedOps;
2531 for (unsigned i = 0; i != MaskNumElts; ++i) {
2534 MappedOps.push_back(Idx);
2535 else if (Idx < (int)SrcNumElts)
2536 MappedOps.push_back(Idx - StartIdx[0]);
2538 MappedOps.push_back(Idx - SrcNumElts - StartIdx[1] + MaskNumElts);
2540 setValue(&I, DAG.getVectorShuffle(VT, getCurDebugLoc(), Src1, Src2,
2546 // We can't use either concat vectors or extract subvectors so fall back to
2547 // replacing the shuffle with extract and build vector.
2548 // to insert and build vector.
2549 EVT EltVT = VT.getVectorElementType();
2550 EVT PtrVT = TLI.getPointerTy();
2551 SmallVector<SDValue,8> Ops;
2552 for (unsigned i = 0; i != MaskNumElts; ++i) {
2554 Ops.push_back(DAG.getUNDEF(EltVT));
2557 if (Idx < (int)SrcNumElts)
2558 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurDebugLoc(),
2559 EltVT, Src1, DAG.getConstant(Idx, PtrVT)));
2561 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurDebugLoc(),
2563 DAG.getConstant(Idx - SrcNumElts, PtrVT)));
2566 setValue(&I, DAG.getNode(ISD::BUILD_VECTOR, getCurDebugLoc(),
2567 VT, &Ops[0], Ops.size()));
2570 void SelectionDAGLowering::visitInsertValue(InsertValueInst &I) {
2571 const Value *Op0 = I.getOperand(0);
2572 const Value *Op1 = I.getOperand(1);
2573 const Type *AggTy = I.getType();
2574 const Type *ValTy = Op1->getType();
2575 bool IntoUndef = isa<UndefValue>(Op0);
2576 bool FromUndef = isa<UndefValue>(Op1);
2578 unsigned LinearIndex = ComputeLinearIndex(TLI, AggTy,
2579 I.idx_begin(), I.idx_end());
2581 SmallVector<EVT, 4> AggValueVTs;
2582 ComputeValueVTs(TLI, AggTy, AggValueVTs);
2583 SmallVector<EVT, 4> ValValueVTs;
2584 ComputeValueVTs(TLI, ValTy, ValValueVTs);
2586 unsigned NumAggValues = AggValueVTs.size();
2587 unsigned NumValValues = ValValueVTs.size();
2588 SmallVector<SDValue, 4> Values(NumAggValues);
2590 SDValue Agg = getValue(Op0);
2591 SDValue Val = getValue(Op1);
2593 // Copy the beginning value(s) from the original aggregate.
2594 for (; i != LinearIndex; ++i)
2595 Values[i] = IntoUndef ? DAG.getUNDEF(AggValueVTs[i]) :
2596 SDValue(Agg.getNode(), Agg.getResNo() + i);
2597 // Copy values from the inserted value(s).
2598 for (; i != LinearIndex + NumValValues; ++i)
2599 Values[i] = FromUndef ? DAG.getUNDEF(AggValueVTs[i]) :
2600 SDValue(Val.getNode(), Val.getResNo() + i - LinearIndex);
2601 // Copy remaining value(s) from the original aggregate.
2602 for (; i != NumAggValues; ++i)
2603 Values[i] = IntoUndef ? DAG.getUNDEF(AggValueVTs[i]) :
2604 SDValue(Agg.getNode(), Agg.getResNo() + i);
2606 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(),
2607 DAG.getVTList(&AggValueVTs[0], NumAggValues),
2608 &Values[0], NumAggValues));
2611 void SelectionDAGLowering::visitExtractValue(ExtractValueInst &I) {
2612 const Value *Op0 = I.getOperand(0);
2613 const Type *AggTy = Op0->getType();
2614 const Type *ValTy = I.getType();
2615 bool OutOfUndef = isa<UndefValue>(Op0);
2617 unsigned LinearIndex = ComputeLinearIndex(TLI, AggTy,
2618 I.idx_begin(), I.idx_end());
2620 SmallVector<EVT, 4> ValValueVTs;
2621 ComputeValueVTs(TLI, ValTy, ValValueVTs);
2623 unsigned NumValValues = ValValueVTs.size();
2624 SmallVector<SDValue, 4> Values(NumValValues);
2626 SDValue Agg = getValue(Op0);
2627 // Copy out the selected value(s).
2628 for (unsigned i = LinearIndex; i != LinearIndex + NumValValues; ++i)
2629 Values[i - LinearIndex] =
2631 DAG.getUNDEF(Agg.getNode()->getValueType(Agg.getResNo() + i)) :
2632 SDValue(Agg.getNode(), Agg.getResNo() + i);
2634 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(),
2635 DAG.getVTList(&ValValueVTs[0], NumValValues),
2636 &Values[0], NumValValues));
2640 void SelectionDAGLowering::visitGetElementPtr(User &I) {
2641 SDValue N = getValue(I.getOperand(0));
2642 const Type *Ty = I.getOperand(0)->getType();
2644 for (GetElementPtrInst::op_iterator OI = I.op_begin()+1, E = I.op_end();
2647 if (const StructType *StTy = dyn_cast<StructType>(Ty)) {
2648 unsigned Field = cast<ConstantInt>(Idx)->getZExtValue();
2651 uint64_t Offset = TD->getStructLayout(StTy)->getElementOffset(Field);
2652 N = DAG.getNode(ISD::ADD, getCurDebugLoc(), N.getValueType(), N,
2653 DAG.getIntPtrConstant(Offset));
2655 Ty = StTy->getElementType(Field);
2657 Ty = cast<SequentialType>(Ty)->getElementType();
2659 // If this is a constant subscript, handle it quickly.
2660 if (ConstantInt *CI = dyn_cast<ConstantInt>(Idx)) {
2661 if (CI->getZExtValue() == 0) continue;
2663 TD->getTypeAllocSize(Ty)*cast<ConstantInt>(CI)->getSExtValue();
2665 EVT PTy = TLI.getPointerTy();
2666 unsigned PtrBits = PTy.getSizeInBits();
2668 OffsVal = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(),
2670 DAG.getConstant(Offs, MVT::i64));
2672 OffsVal = DAG.getIntPtrConstant(Offs);
2673 N = DAG.getNode(ISD::ADD, getCurDebugLoc(), N.getValueType(), N,
2678 // N = N + Idx * ElementSize;
2679 APInt ElementSize = APInt(TLI.getPointerTy().getSizeInBits(),
2680 TD->getTypeAllocSize(Ty));
2681 SDValue IdxN = getValue(Idx);
2683 // If the index is smaller or larger than intptr_t, truncate or extend
2685 IdxN = DAG.getSExtOrTrunc(IdxN, getCurDebugLoc(), N.getValueType());
2687 // If this is a multiply by a power of two, turn it into a shl
2688 // immediately. This is a very common case.
2689 if (ElementSize != 1) {
2690 if (ElementSize.isPowerOf2()) {
2691 unsigned Amt = ElementSize.logBase2();
2692 IdxN = DAG.getNode(ISD::SHL, getCurDebugLoc(),
2693 N.getValueType(), IdxN,
2694 DAG.getConstant(Amt, TLI.getPointerTy()));
2696 SDValue Scale = DAG.getConstant(ElementSize, TLI.getPointerTy());
2697 IdxN = DAG.getNode(ISD::MUL, getCurDebugLoc(),
2698 N.getValueType(), IdxN, Scale);
2702 N = DAG.getNode(ISD::ADD, getCurDebugLoc(),
2703 N.getValueType(), N, IdxN);
2709 void SelectionDAGLowering::visitAlloca(AllocaInst &I) {
2710 // If this is a fixed sized alloca in the entry block of the function,
2711 // allocate it statically on the stack.
2712 if (FuncInfo.StaticAllocaMap.count(&I))
2713 return; // getValue will auto-populate this.
2715 const Type *Ty = I.getAllocatedType();
2716 uint64_t TySize = TLI.getTargetData()->getTypeAllocSize(Ty);
2718 std::max((unsigned)TLI.getTargetData()->getPrefTypeAlignment(Ty),
2721 SDValue AllocSize = getValue(I.getArraySize());
2723 AllocSize = DAG.getNode(ISD::MUL, getCurDebugLoc(), AllocSize.getValueType(),
2725 DAG.getConstant(TySize, AllocSize.getValueType()));
2729 EVT IntPtr = TLI.getPointerTy();
2730 AllocSize = DAG.getZExtOrTrunc(AllocSize, getCurDebugLoc(), IntPtr);
2732 // Handle alignment. If the requested alignment is less than or equal to
2733 // the stack alignment, ignore it. If the size is greater than or equal to
2734 // the stack alignment, we note this in the DYNAMIC_STACKALLOC node.
2735 unsigned StackAlign =
2736 TLI.getTargetMachine().getFrameInfo()->getStackAlignment();
2737 if (Align <= StackAlign)
2740 // Round the size of the allocation up to the stack alignment size
2741 // by add SA-1 to the size.
2742 AllocSize = DAG.getNode(ISD::ADD, getCurDebugLoc(),
2743 AllocSize.getValueType(), AllocSize,
2744 DAG.getIntPtrConstant(StackAlign-1));
2745 // Mask out the low bits for alignment purposes.
2746 AllocSize = DAG.getNode(ISD::AND, getCurDebugLoc(),
2747 AllocSize.getValueType(), AllocSize,
2748 DAG.getIntPtrConstant(~(uint64_t)(StackAlign-1)));
2750 SDValue Ops[] = { getRoot(), AllocSize, DAG.getIntPtrConstant(Align) };
2751 SDVTList VTs = DAG.getVTList(AllocSize.getValueType(), MVT::Other);
2752 SDValue DSA = DAG.getNode(ISD::DYNAMIC_STACKALLOC, getCurDebugLoc(),
2755 DAG.setRoot(DSA.getValue(1));
2757 // Inform the Frame Information that we have just allocated a variable-sized
2759 FuncInfo.MF->getFrameInfo()->CreateVariableSizedObject();
2762 void SelectionDAGLowering::visitLoad(LoadInst &I) {
2763 const Value *SV = I.getOperand(0);
2764 SDValue Ptr = getValue(SV);
2766 const Type *Ty = I.getType();
2767 bool isVolatile = I.isVolatile();
2768 unsigned Alignment = I.getAlignment();
2770 SmallVector<EVT, 4> ValueVTs;
2771 SmallVector<uint64_t, 4> Offsets;
2772 ComputeValueVTs(TLI, Ty, ValueVTs, &Offsets);
2773 unsigned NumValues = ValueVTs.size();
2778 bool ConstantMemory = false;
2780 // Serialize volatile loads with other side effects.
2782 else if (AA->pointsToConstantMemory(SV)) {
2783 // Do not serialize (non-volatile) loads of constant memory with anything.
2784 Root = DAG.getEntryNode();
2785 ConstantMemory = true;
2787 // Do not serialize non-volatile loads against each other.
2788 Root = DAG.getRoot();
2791 SmallVector<SDValue, 4> Values(NumValues);
2792 SmallVector<SDValue, 4> Chains(NumValues);
2793 EVT PtrVT = Ptr.getValueType();
2794 for (unsigned i = 0; i != NumValues; ++i) {
2795 SDValue L = DAG.getLoad(ValueVTs[i], getCurDebugLoc(), Root,
2796 DAG.getNode(ISD::ADD, getCurDebugLoc(),
2798 DAG.getConstant(Offsets[i], PtrVT)),
2799 SV, Offsets[i], isVolatile, Alignment);
2801 Chains[i] = L.getValue(1);
2804 if (!ConstantMemory) {
2805 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(),
2807 &Chains[0], NumValues);
2811 PendingLoads.push_back(Chain);
2814 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(),
2815 DAG.getVTList(&ValueVTs[0], NumValues),
2816 &Values[0], NumValues));
2820 void SelectionDAGLowering::visitStore(StoreInst &I) {
2821 Value *SrcV = I.getOperand(0);
2822 Value *PtrV = I.getOperand(1);
2824 SmallVector<EVT, 4> ValueVTs;
2825 SmallVector<uint64_t, 4> Offsets;
2826 ComputeValueVTs(TLI, SrcV->getType(), ValueVTs, &Offsets);
2827 unsigned NumValues = ValueVTs.size();
2831 // Get the lowered operands. Note that we do this after
2832 // checking if NumResults is zero, because with zero results
2833 // the operands won't have values in the map.
2834 SDValue Src = getValue(SrcV);
2835 SDValue Ptr = getValue(PtrV);
2837 SDValue Root = getRoot();
2838 SmallVector<SDValue, 4> Chains(NumValues);
2839 EVT PtrVT = Ptr.getValueType();
2840 bool isVolatile = I.isVolatile();
2841 unsigned Alignment = I.getAlignment();
2842 for (unsigned i = 0; i != NumValues; ++i)
2843 Chains[i] = DAG.getStore(Root, getCurDebugLoc(),
2844 SDValue(Src.getNode(), Src.getResNo() + i),
2845 DAG.getNode(ISD::ADD, getCurDebugLoc(),
2847 DAG.getConstant(Offsets[i], PtrVT)),
2848 PtrV, Offsets[i], isVolatile, Alignment);
2850 DAG.setRoot(DAG.getNode(ISD::TokenFactor, getCurDebugLoc(),
2851 MVT::Other, &Chains[0], NumValues));
2854 /// visitTargetIntrinsic - Lower a call of a target intrinsic to an INTRINSIC
2856 void SelectionDAGLowering::visitTargetIntrinsic(CallInst &I,
2857 unsigned Intrinsic) {
2858 bool HasChain = !I.doesNotAccessMemory();
2859 bool OnlyLoad = HasChain && I.onlyReadsMemory();
2861 // Build the operand list.
2862 SmallVector<SDValue, 8> Ops;
2863 if (HasChain) { // If this intrinsic has side-effects, chainify it.
2865 // We don't need to serialize loads against other loads.
2866 Ops.push_back(DAG.getRoot());
2868 Ops.push_back(getRoot());
2872 // Info is set by getTgtMemInstrinsic
2873 TargetLowering::IntrinsicInfo Info;
2874 bool IsTgtIntrinsic = TLI.getTgtMemIntrinsic(Info, I, Intrinsic);
2876 // Add the intrinsic ID as an integer operand if it's not a target intrinsic.
2877 if (!IsTgtIntrinsic)
2878 Ops.push_back(DAG.getConstant(Intrinsic, TLI.getPointerTy()));
2880 // Add all operands of the call to the operand list.
2881 for (unsigned i = 1, e = I.getNumOperands(); i != e; ++i) {
2882 SDValue Op = getValue(I.getOperand(i));
2883 assert(TLI.isTypeLegal(Op.getValueType()) &&
2884 "Intrinsic uses a non-legal type?");
2888 SmallVector<EVT, 4> ValueVTs;
2889 ComputeValueVTs(TLI, I.getType(), ValueVTs);
2891 for (unsigned Val = 0, E = ValueVTs.size(); Val != E; ++Val) {
2892 assert(TLI.isTypeLegal(ValueVTs[Val]) &&
2893 "Intrinsic uses a non-legal type?");
2897 ValueVTs.push_back(MVT::Other);
2899 SDVTList VTs = DAG.getVTList(ValueVTs.data(), ValueVTs.size());
2903 if (IsTgtIntrinsic) {
2904 // This is target intrinsic that touches memory
2905 Result = DAG.getMemIntrinsicNode(Info.opc, getCurDebugLoc(),
2906 VTs, &Ops[0], Ops.size(),
2907 Info.memVT, Info.ptrVal, Info.offset,
2908 Info.align, Info.vol,
2909 Info.readMem, Info.writeMem);
2912 Result = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, getCurDebugLoc(),
2913 VTs, &Ops[0], Ops.size());
2914 else if (I.getType() != Type::getVoidTy(*DAG.getContext()))
2915 Result = DAG.getNode(ISD::INTRINSIC_W_CHAIN, getCurDebugLoc(),
2916 VTs, &Ops[0], Ops.size());
2918 Result = DAG.getNode(ISD::INTRINSIC_VOID, getCurDebugLoc(),
2919 VTs, &Ops[0], Ops.size());
2922 SDValue Chain = Result.getValue(Result.getNode()->getNumValues()-1);
2924 PendingLoads.push_back(Chain);
2928 if (I.getType() != Type::getVoidTy(*DAG.getContext())) {
2929 if (const VectorType *PTy = dyn_cast<VectorType>(I.getType())) {
2930 EVT VT = TLI.getValueType(PTy);
2931 Result = DAG.getNode(ISD::BIT_CONVERT, getCurDebugLoc(), VT, Result);
2933 setValue(&I, Result);
2937 /// ExtractTypeInfo - Returns the type info, possibly bitcast, encoded in V.
2938 static GlobalVariable *ExtractTypeInfo(Value *V) {
2939 V = V->stripPointerCasts();
2940 GlobalVariable *GV = dyn_cast<GlobalVariable>(V);
2941 assert ((GV || isa<ConstantPointerNull>(V)) &&
2942 "TypeInfo must be a global variable or NULL");
2948 /// AddCatchInfo - Extract the personality and type infos from an eh.selector
2949 /// call, and add them to the specified machine basic block.
2950 void AddCatchInfo(CallInst &I, MachineModuleInfo *MMI,
2951 MachineBasicBlock *MBB) {
2952 // Inform the MachineModuleInfo of the personality for this landing pad.
2953 ConstantExpr *CE = cast<ConstantExpr>(I.getOperand(2));
2954 assert(CE->getOpcode() == Instruction::BitCast &&
2955 isa<Function>(CE->getOperand(0)) &&
2956 "Personality should be a function");
2957 MMI->addPersonality(MBB, cast<Function>(CE->getOperand(0)));
2959 // Gather all the type infos for this landing pad and pass them along to
2960 // MachineModuleInfo.
2961 std::vector<GlobalVariable *> TyInfo;
2962 unsigned N = I.getNumOperands();
2964 for (unsigned i = N - 1; i > 2; --i) {
2965 if (ConstantInt *CI = dyn_cast<ConstantInt>(I.getOperand(i))) {
2966 unsigned FilterLength = CI->getZExtValue();
2967 unsigned FirstCatch = i + FilterLength + !FilterLength;
2968 assert (FirstCatch <= N && "Invalid filter length");
2970 if (FirstCatch < N) {
2971 TyInfo.reserve(N - FirstCatch);
2972 for (unsigned j = FirstCatch; j < N; ++j)
2973 TyInfo.push_back(ExtractTypeInfo(I.getOperand(j)));
2974 MMI->addCatchTypeInfo(MBB, TyInfo);
2978 if (!FilterLength) {
2980 MMI->addCleanup(MBB);
2983 TyInfo.reserve(FilterLength - 1);
2984 for (unsigned j = i + 1; j < FirstCatch; ++j)
2985 TyInfo.push_back(ExtractTypeInfo(I.getOperand(j)));
2986 MMI->addFilterTypeInfo(MBB, TyInfo);
2995 TyInfo.reserve(N - 3);
2996 for (unsigned j = 3; j < N; ++j)
2997 TyInfo.push_back(ExtractTypeInfo(I.getOperand(j)));
2998 MMI->addCatchTypeInfo(MBB, TyInfo);
3004 /// GetSignificand - Get the significand and build it into a floating-point
3005 /// number with exponent of 1:
3007 /// Op = (Op & 0x007fffff) | 0x3f800000;
3009 /// where Op is the hexidecimal representation of floating point value.
3011 GetSignificand(SelectionDAG &DAG, SDValue Op, DebugLoc dl) {
3012 SDValue t1 = DAG.getNode(ISD::AND, dl, MVT::i32, Op,
3013 DAG.getConstant(0x007fffff, MVT::i32));
3014 SDValue t2 = DAG.getNode(ISD::OR, dl, MVT::i32, t1,
3015 DAG.getConstant(0x3f800000, MVT::i32));
3016 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, t2);
3019 /// GetExponent - Get the exponent:
3021 /// (float)(int)(((Op & 0x7f800000) >> 23) - 127);
3023 /// where Op is the hexidecimal representation of floating point value.
3025 GetExponent(SelectionDAG &DAG, SDValue Op, const TargetLowering &TLI,
3027 SDValue t0 = DAG.getNode(ISD::AND, dl, MVT::i32, Op,
3028 DAG.getConstant(0x7f800000, MVT::i32));
3029 SDValue t1 = DAG.getNode(ISD::SRL, dl, MVT::i32, t0,
3030 DAG.getConstant(23, TLI.getPointerTy()));
3031 SDValue t2 = DAG.getNode(ISD::SUB, dl, MVT::i32, t1,
3032 DAG.getConstant(127, MVT::i32));
3033 return DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, t2);
3036 /// getF32Constant - Get 32-bit floating point constant.
3038 getF32Constant(SelectionDAG &DAG, unsigned Flt) {
3039 return DAG.getConstantFP(APFloat(APInt(32, Flt)), MVT::f32);
3042 /// Inlined utility function to implement binary input atomic intrinsics for
3043 /// visitIntrinsicCall: I is a call instruction
3044 /// Op is the associated NodeType for I
3046 SelectionDAGLowering::implVisitBinaryAtomic(CallInst& I, ISD::NodeType Op) {
3047 SDValue Root = getRoot();
3049 DAG.getAtomic(Op, getCurDebugLoc(),
3050 getValue(I.getOperand(2)).getValueType().getSimpleVT(),
3052 getValue(I.getOperand(1)),
3053 getValue(I.getOperand(2)),
3056 DAG.setRoot(L.getValue(1));
3060 // implVisitAluOverflow - Lower arithmetic overflow instrinsics.
3062 SelectionDAGLowering::implVisitAluOverflow(CallInst &I, ISD::NodeType Op) {
3063 SDValue Op1 = getValue(I.getOperand(1));
3064 SDValue Op2 = getValue(I.getOperand(2));
3066 SDVTList VTs = DAG.getVTList(Op1.getValueType(), MVT::i1);
3067 SDValue Result = DAG.getNode(Op, getCurDebugLoc(), VTs, Op1, Op2);
3069 setValue(&I, Result);
3073 /// visitExp - Lower an exp intrinsic. Handles the special sequences for
3074 /// limited-precision mode.
3076 SelectionDAGLowering::visitExp(CallInst &I) {
3078 DebugLoc dl = getCurDebugLoc();
3080 if (getValue(I.getOperand(1)).getValueType() == MVT::f32 &&
3081 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3082 SDValue Op = getValue(I.getOperand(1));
3084 // Put the exponent in the right bit position for later addition to the
3087 // #define LOG2OFe 1.4426950f
3088 // IntegerPartOfX = ((int32_t)(X * LOG2OFe));
3089 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, Op,
3090 getF32Constant(DAG, 0x3fb8aa3b));
3091 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, t0);
3093 // FractionalPartOfX = (X * LOG2OFe) - (float)IntegerPartOfX;
3094 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX);
3095 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, t1);
3097 // IntegerPartOfX <<= 23;
3098 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX,
3099 DAG.getConstant(23, TLI.getPointerTy()));
3101 if (LimitFloatPrecision <= 6) {
3102 // For floating-point precision of 6:
3104 // TwoToFractionalPartOfX =
3106 // (0.735607626f + 0.252464424f * x) * x;
3108 // error 0.0144103317, which is 6 bits
3109 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3110 getF32Constant(DAG, 0x3e814304));
3111 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3112 getF32Constant(DAG, 0x3f3c50c8));
3113 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3114 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3115 getF32Constant(DAG, 0x3f7f5e7e));
3116 SDValue TwoToFracPartOfX = DAG.getNode(ISD::BIT_CONVERT, dl,MVT::i32, t5);
3118 // Add the exponent into the result in integer domain.
3119 SDValue t6 = DAG.getNode(ISD::ADD, dl, MVT::i32,
3120 TwoToFracPartOfX, IntegerPartOfX);
3122 result = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, t6);
3123 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
3124 // For floating-point precision of 12:
3126 // TwoToFractionalPartOfX =
3129 // (0.224338339f + 0.792043434e-1f * x) * x) * x;
3131 // 0.000107046256 error, which is 13 to 14 bits
3132 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3133 getF32Constant(DAG, 0x3da235e3));
3134 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3135 getF32Constant(DAG, 0x3e65b8f3));
3136 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3137 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3138 getF32Constant(DAG, 0x3f324b07));
3139 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3140 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3141 getF32Constant(DAG, 0x3f7ff8fd));
3142 SDValue TwoToFracPartOfX = DAG.getNode(ISD::BIT_CONVERT, dl,MVT::i32, t7);
3144 // Add the exponent into the result in integer domain.
3145 SDValue t8 = DAG.getNode(ISD::ADD, dl, MVT::i32,
3146 TwoToFracPartOfX, IntegerPartOfX);
3148 result = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, t8);
3149 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
3150 // For floating-point precision of 18:
3152 // TwoToFractionalPartOfX =
3156 // (0.554906021e-1f +
3157 // (0.961591928e-2f +
3158 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x;
3160 // error 2.47208000*10^(-7), which is better than 18 bits
3161 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3162 getF32Constant(DAG, 0x3924b03e));
3163 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3164 getF32Constant(DAG, 0x3ab24b87));
3165 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3166 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3167 getF32Constant(DAG, 0x3c1d8c17));
3168 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3169 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3170 getF32Constant(DAG, 0x3d634a1d));
3171 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3172 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3173 getF32Constant(DAG, 0x3e75fe14));
3174 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3175 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10,
3176 getF32Constant(DAG, 0x3f317234));
3177 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X);
3178 SDValue t13 = DAG.getNode(ISD::FADD, dl, MVT::f32, t12,
3179 getF32Constant(DAG, 0x3f800000));
3180 SDValue TwoToFracPartOfX = DAG.getNode(ISD::BIT_CONVERT, dl,
3183 // Add the exponent into the result in integer domain.
3184 SDValue t14 = DAG.getNode(ISD::ADD, dl, MVT::i32,
3185 TwoToFracPartOfX, IntegerPartOfX);
3187 result = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, t14);
3190 // No special expansion.
3191 result = DAG.getNode(ISD::FEXP, dl,
3192 getValue(I.getOperand(1)).getValueType(),
3193 getValue(I.getOperand(1)));
3196 setValue(&I, result);
3199 /// visitLog - Lower a log intrinsic. Handles the special sequences for
3200 /// limited-precision mode.
3202 SelectionDAGLowering::visitLog(CallInst &I) {
3204 DebugLoc dl = getCurDebugLoc();
3206 if (getValue(I.getOperand(1)).getValueType() == MVT::f32 &&
3207 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3208 SDValue Op = getValue(I.getOperand(1));
3209 SDValue Op1 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, Op);
3211 // Scale the exponent by log(2) [0.69314718f].
3212 SDValue Exp = GetExponent(DAG, Op1, TLI, dl);
3213 SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp,
3214 getF32Constant(DAG, 0x3f317218));
3216 // Get the significand and build it into a floating-point number with
3218 SDValue X = GetSignificand(DAG, Op1, dl);
3220 if (LimitFloatPrecision <= 6) {
3221 // For floating-point precision of 6:
3225 // (1.4034025f - 0.23903021f * x) * x;
3227 // error 0.0034276066, which is better than 8 bits
3228 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3229 getF32Constant(DAG, 0xbe74c456));
3230 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3231 getF32Constant(DAG, 0x3fb3a2b1));
3232 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3233 SDValue LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3234 getF32Constant(DAG, 0x3f949a29));
3236 result = DAG.getNode(ISD::FADD, dl,
3237 MVT::f32, LogOfExponent, LogOfMantissa);
3238 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
3239 // For floating-point precision of 12:
3245 // (0.44717955f - 0.56570851e-1f * x) * x) * x) * x;
3247 // error 0.000061011436, which is 14 bits
3248 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3249 getF32Constant(DAG, 0xbd67b6d6));
3250 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3251 getF32Constant(DAG, 0x3ee4f4b8));
3252 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3253 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3254 getF32Constant(DAG, 0x3fbc278b));
3255 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3256 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3257 getF32Constant(DAG, 0x40348e95));
3258 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3259 SDValue LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3260 getF32Constant(DAG, 0x3fdef31a));
3262 result = DAG.getNode(ISD::FADD, dl,
3263 MVT::f32, LogOfExponent, LogOfMantissa);
3264 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
3265 // For floating-point precision of 18:
3273 // (0.19073739f - 0.17809712e-1f * x) * x) * x) * x) * x)*x;
3275 // error 0.0000023660568, which is better than 18 bits
3276 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3277 getF32Constant(DAG, 0xbc91e5ac));
3278 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3279 getF32Constant(DAG, 0x3e4350aa));
3280 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3281 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3282 getF32Constant(DAG, 0x3f60d3e3));
3283 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3284 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3285 getF32Constant(DAG, 0x4011cdf0));
3286 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3287 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3288 getF32Constant(DAG, 0x406cfd1c));
3289 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3290 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3291 getF32Constant(DAG, 0x408797cb));
3292 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3293 SDValue LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10,
3294 getF32Constant(DAG, 0x4006dcab));
3296 result = DAG.getNode(ISD::FADD, dl,
3297 MVT::f32, LogOfExponent, LogOfMantissa);
3300 // No special expansion.
3301 result = DAG.getNode(ISD::FLOG, dl,
3302 getValue(I.getOperand(1)).getValueType(),
3303 getValue(I.getOperand(1)));
3306 setValue(&I, result);
3309 /// visitLog2 - Lower a log2 intrinsic. Handles the special sequences for
3310 /// limited-precision mode.
3312 SelectionDAGLowering::visitLog2(CallInst &I) {
3314 DebugLoc dl = getCurDebugLoc();
3316 if (getValue(I.getOperand(1)).getValueType() == MVT::f32 &&
3317 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3318 SDValue Op = getValue(I.getOperand(1));
3319 SDValue Op1 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, Op);
3321 // Get the exponent.
3322 SDValue LogOfExponent = GetExponent(DAG, Op1, TLI, dl);
3324 // Get the significand and build it into a floating-point number with
3326 SDValue X = GetSignificand(DAG, Op1, dl);
3328 // Different possible minimax approximations of significand in
3329 // floating-point for various degrees of accuracy over [1,2].
3330 if (LimitFloatPrecision <= 6) {
3331 // For floating-point precision of 6:
3333 // Log2ofMantissa = -1.6749035f + (2.0246817f - .34484768f * x) * x;
3335 // error 0.0049451742, which is more than 7 bits
3336 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3337 getF32Constant(DAG, 0xbeb08fe0));
3338 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3339 getF32Constant(DAG, 0x40019463));
3340 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3341 SDValue Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3342 getF32Constant(DAG, 0x3fd6633d));
3344 result = DAG.getNode(ISD::FADD, dl,
3345 MVT::f32, LogOfExponent, Log2ofMantissa);
3346 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
3347 // For floating-point precision of 12:
3353 // (.645142248f - 0.816157886e-1f * x) * x) * x) * x;
3355 // error 0.0000876136000, which is better than 13 bits
3356 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3357 getF32Constant(DAG, 0xbda7262e));
3358 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3359 getF32Constant(DAG, 0x3f25280b));
3360 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3361 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3362 getF32Constant(DAG, 0x4007b923));
3363 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3364 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3365 getF32Constant(DAG, 0x40823e2f));
3366 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3367 SDValue Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3368 getF32Constant(DAG, 0x4020d29c));
3370 result = DAG.getNode(ISD::FADD, dl,
3371 MVT::f32, LogOfExponent, Log2ofMantissa);
3372 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
3373 // For floating-point precision of 18:
3382 // 0.25691327e-1f * x) * x) * x) * x) * x) * x;
3384 // error 0.0000018516, which is better than 18 bits
3385 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3386 getF32Constant(DAG, 0xbcd2769e));
3387 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3388 getF32Constant(DAG, 0x3e8ce0b9));
3389 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3390 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3391 getF32Constant(DAG, 0x3fa22ae7));
3392 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3393 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3394 getF32Constant(DAG, 0x40525723));
3395 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3396 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3397 getF32Constant(DAG, 0x40aaf200));
3398 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3399 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3400 getF32Constant(DAG, 0x40c39dad));
3401 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3402 SDValue Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10,
3403 getF32Constant(DAG, 0x4042902c));
3405 result = DAG.getNode(ISD::FADD, dl,
3406 MVT::f32, LogOfExponent, Log2ofMantissa);
3409 // No special expansion.
3410 result = DAG.getNode(ISD::FLOG2, dl,
3411 getValue(I.getOperand(1)).getValueType(),
3412 getValue(I.getOperand(1)));
3415 setValue(&I, result);
3418 /// visitLog10 - Lower a log10 intrinsic. Handles the special sequences for
3419 /// limited-precision mode.
3421 SelectionDAGLowering::visitLog10(CallInst &I) {
3423 DebugLoc dl = getCurDebugLoc();
3425 if (getValue(I.getOperand(1)).getValueType() == MVT::f32 &&
3426 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3427 SDValue Op = getValue(I.getOperand(1));
3428 SDValue Op1 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, Op);
3430 // Scale the exponent by log10(2) [0.30102999f].
3431 SDValue Exp = GetExponent(DAG, Op1, TLI, dl);
3432 SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp,
3433 getF32Constant(DAG, 0x3e9a209a));
3435 // Get the significand and build it into a floating-point number with
3437 SDValue X = GetSignificand(DAG, Op1, dl);
3439 if (LimitFloatPrecision <= 6) {
3440 // For floating-point precision of 6:
3442 // Log10ofMantissa =
3444 // (0.60948995f - 0.10380950f * x) * x;
3446 // error 0.0014886165, which is 6 bits
3447 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3448 getF32Constant(DAG, 0xbdd49a13));
3449 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3450 getF32Constant(DAG, 0x3f1c0789));
3451 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3452 SDValue Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3453 getF32Constant(DAG, 0x3f011300));
3455 result = DAG.getNode(ISD::FADD, dl,
3456 MVT::f32, LogOfExponent, Log10ofMantissa);
3457 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
3458 // For floating-point precision of 12:
3460 // Log10ofMantissa =
3463 // (-0.31664806f + 0.47637168e-1f * x) * x) * x;
3465 // error 0.00019228036, which is better than 12 bits
3466 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3467 getF32Constant(DAG, 0x3d431f31));
3468 SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0,
3469 getF32Constant(DAG, 0x3ea21fb2));
3470 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3471 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3472 getF32Constant(DAG, 0x3f6ae232));
3473 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3474 SDValue Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4,
3475 getF32Constant(DAG, 0x3f25f7c3));
3477 result = DAG.getNode(ISD::FADD, dl,
3478 MVT::f32, LogOfExponent, Log10ofMantissa);
3479 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
3480 // For floating-point precision of 18:
3482 // Log10ofMantissa =
3487 // (-0.12539807f + 0.13508273e-1f * x) * x) * x) * x) * x;
3489 // error 0.0000037995730, which is better than 18 bits
3490 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3491 getF32Constant(DAG, 0x3c5d51ce));
3492 SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0,
3493 getF32Constant(DAG, 0x3e00685a));
3494 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3495 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3496 getF32Constant(DAG, 0x3efb6798));
3497 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3498 SDValue t5 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4,
3499 getF32Constant(DAG, 0x3f88d192));
3500 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3501 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3502 getF32Constant(DAG, 0x3fc4316c));
3503 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3504 SDValue Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t8,
3505 getF32Constant(DAG, 0x3f57ce70));
3507 result = DAG.getNode(ISD::FADD, dl,
3508 MVT::f32, LogOfExponent, Log10ofMantissa);
3511 // No special expansion.
3512 result = DAG.getNode(ISD::FLOG10, dl,
3513 getValue(I.getOperand(1)).getValueType(),
3514 getValue(I.getOperand(1)));
3517 setValue(&I, result);
3520 /// visitExp2 - Lower an exp2 intrinsic. Handles the special sequences for
3521 /// limited-precision mode.
3523 SelectionDAGLowering::visitExp2(CallInst &I) {
3525 DebugLoc dl = getCurDebugLoc();
3527 if (getValue(I.getOperand(1)).getValueType() == MVT::f32 &&
3528 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3529 SDValue Op = getValue(I.getOperand(1));
3531 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, Op);
3533 // FractionalPartOfX = x - (float)IntegerPartOfX;
3534 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX);
3535 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, Op, t1);
3537 // IntegerPartOfX <<= 23;
3538 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX,
3539 DAG.getConstant(23, TLI.getPointerTy()));
3541 if (LimitFloatPrecision <= 6) {
3542 // For floating-point precision of 6:
3544 // TwoToFractionalPartOfX =
3546 // (0.735607626f + 0.252464424f * x) * x;
3548 // error 0.0144103317, which is 6 bits
3549 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3550 getF32Constant(DAG, 0x3e814304));
3551 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3552 getF32Constant(DAG, 0x3f3c50c8));
3553 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3554 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3555 getF32Constant(DAG, 0x3f7f5e7e));
3556 SDValue t6 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, t5);
3557 SDValue TwoToFractionalPartOfX =
3558 DAG.getNode(ISD::ADD, dl, MVT::i32, t6, IntegerPartOfX);
3560 result = DAG.getNode(ISD::BIT_CONVERT, dl,
3561 MVT::f32, TwoToFractionalPartOfX);
3562 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
3563 // For floating-point precision of 12:
3565 // TwoToFractionalPartOfX =
3568 // (0.224338339f + 0.792043434e-1f * x) * x) * x;
3570 // error 0.000107046256, which is 13 to 14 bits
3571 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3572 getF32Constant(DAG, 0x3da235e3));
3573 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3574 getF32Constant(DAG, 0x3e65b8f3));
3575 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3576 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3577 getF32Constant(DAG, 0x3f324b07));
3578 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3579 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3580 getF32Constant(DAG, 0x3f7ff8fd));
3581 SDValue t8 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, t7);
3582 SDValue TwoToFractionalPartOfX =
3583 DAG.getNode(ISD::ADD, dl, MVT::i32, t8, IntegerPartOfX);
3585 result = DAG.getNode(ISD::BIT_CONVERT, dl,
3586 MVT::f32, TwoToFractionalPartOfX);
3587 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
3588 // For floating-point precision of 18:
3590 // TwoToFractionalPartOfX =
3594 // (0.554906021e-1f +
3595 // (0.961591928e-2f +
3596 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x;
3597 // error 2.47208000*10^(-7), which is better than 18 bits
3598 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3599 getF32Constant(DAG, 0x3924b03e));
3600 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3601 getF32Constant(DAG, 0x3ab24b87));
3602 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3603 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3604 getF32Constant(DAG, 0x3c1d8c17));
3605 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3606 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3607 getF32Constant(DAG, 0x3d634a1d));
3608 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3609 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3610 getF32Constant(DAG, 0x3e75fe14));
3611 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3612 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10,
3613 getF32Constant(DAG, 0x3f317234));
3614 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X);
3615 SDValue t13 = DAG.getNode(ISD::FADD, dl, MVT::f32, t12,
3616 getF32Constant(DAG, 0x3f800000));
3617 SDValue t14 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, t13);
3618 SDValue TwoToFractionalPartOfX =
3619 DAG.getNode(ISD::ADD, dl, MVT::i32, t14, IntegerPartOfX);
3621 result = DAG.getNode(ISD::BIT_CONVERT, dl,
3622 MVT::f32, TwoToFractionalPartOfX);
3625 // No special expansion.
3626 result = DAG.getNode(ISD::FEXP2, dl,
3627 getValue(I.getOperand(1)).getValueType(),
3628 getValue(I.getOperand(1)));
3631 setValue(&I, result);
3634 /// visitPow - Lower a pow intrinsic. Handles the special sequences for
3635 /// limited-precision mode with x == 10.0f.
3637 SelectionDAGLowering::visitPow(CallInst &I) {
3639 Value *Val = I.getOperand(1);
3640 DebugLoc dl = getCurDebugLoc();
3641 bool IsExp10 = false;
3643 if (getValue(Val).getValueType() == MVT::f32 &&
3644 getValue(I.getOperand(2)).getValueType() == MVT::f32 &&
3645 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3646 if (Constant *C = const_cast<Constant*>(dyn_cast<Constant>(Val))) {
3647 if (ConstantFP *CFP = dyn_cast<ConstantFP>(C)) {
3649 IsExp10 = CFP->getValueAPF().bitwiseIsEqual(Ten);
3654 if (IsExp10 && LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3655 SDValue Op = getValue(I.getOperand(2));
3657 // Put the exponent in the right bit position for later addition to the
3660 // #define LOG2OF10 3.3219281f
3661 // IntegerPartOfX = (int32_t)(x * LOG2OF10);
3662 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, Op,
3663 getF32Constant(DAG, 0x40549a78));
3664 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, t0);
3666 // FractionalPartOfX = x - (float)IntegerPartOfX;
3667 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX);
3668 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, t1);
3670 // IntegerPartOfX <<= 23;
3671 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX,
3672 DAG.getConstant(23, TLI.getPointerTy()));
3674 if (LimitFloatPrecision <= 6) {
3675 // For floating-point precision of 6:
3677 // twoToFractionalPartOfX =
3679 // (0.735607626f + 0.252464424f * x) * x;
3681 // error 0.0144103317, which is 6 bits
3682 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3683 getF32Constant(DAG, 0x3e814304));
3684 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3685 getF32Constant(DAG, 0x3f3c50c8));
3686 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3687 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3688 getF32Constant(DAG, 0x3f7f5e7e));
3689 SDValue t6 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, t5);
3690 SDValue TwoToFractionalPartOfX =
3691 DAG.getNode(ISD::ADD, dl, MVT::i32, t6, IntegerPartOfX);
3693 result = DAG.getNode(ISD::BIT_CONVERT, dl,
3694 MVT::f32, TwoToFractionalPartOfX);
3695 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
3696 // For floating-point precision of 12:
3698 // TwoToFractionalPartOfX =
3701 // (0.224338339f + 0.792043434e-1f * x) * x) * x;
3703 // error 0.000107046256, which is 13 to 14 bits
3704 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3705 getF32Constant(DAG, 0x3da235e3));
3706 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3707 getF32Constant(DAG, 0x3e65b8f3));
3708 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3709 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3710 getF32Constant(DAG, 0x3f324b07));
3711 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3712 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3713 getF32Constant(DAG, 0x3f7ff8fd));
3714 SDValue t8 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, t7);
3715 SDValue TwoToFractionalPartOfX =
3716 DAG.getNode(ISD::ADD, dl, MVT::i32, t8, IntegerPartOfX);
3718 result = DAG.getNode(ISD::BIT_CONVERT, dl,
3719 MVT::f32, TwoToFractionalPartOfX);
3720 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
3721 // For floating-point precision of 18:
3723 // TwoToFractionalPartOfX =
3727 // (0.554906021e-1f +
3728 // (0.961591928e-2f +
3729 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x;
3730 // error 2.47208000*10^(-7), which is better than 18 bits
3731 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3732 getF32Constant(DAG, 0x3924b03e));
3733 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3734 getF32Constant(DAG, 0x3ab24b87));
3735 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3736 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3737 getF32Constant(DAG, 0x3c1d8c17));
3738 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3739 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3740 getF32Constant(DAG, 0x3d634a1d));
3741 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3742 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3743 getF32Constant(DAG, 0x3e75fe14));
3744 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3745 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10,
3746 getF32Constant(DAG, 0x3f317234));
3747 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X);
3748 SDValue t13 = DAG.getNode(ISD::FADD, dl, MVT::f32, t12,
3749 getF32Constant(DAG, 0x3f800000));
3750 SDValue t14 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, t13);
3751 SDValue TwoToFractionalPartOfX =
3752 DAG.getNode(ISD::ADD, dl, MVT::i32, t14, IntegerPartOfX);
3754 result = DAG.getNode(ISD::BIT_CONVERT, dl,
3755 MVT::f32, TwoToFractionalPartOfX);
3758 // No special expansion.
3759 result = DAG.getNode(ISD::FPOW, dl,
3760 getValue(I.getOperand(1)).getValueType(),
3761 getValue(I.getOperand(1)),
3762 getValue(I.getOperand(2)));
3765 setValue(&I, result);
3768 /// visitIntrinsicCall - Lower the call to the specified intrinsic function. If
3769 /// we want to emit this as a call to a named external function, return the name
3770 /// otherwise lower it and return null.
3772 SelectionDAGLowering::visitIntrinsicCall(CallInst &I, unsigned Intrinsic) {
3773 DebugLoc dl = getCurDebugLoc();
3774 switch (Intrinsic) {
3776 // By default, turn this into a target intrinsic node.
3777 visitTargetIntrinsic(I, Intrinsic);
3779 case Intrinsic::vastart: visitVAStart(I); return 0;
3780 case Intrinsic::vaend: visitVAEnd(I); return 0;
3781 case Intrinsic::vacopy: visitVACopy(I); return 0;
3782 case Intrinsic::returnaddress:
3783 setValue(&I, DAG.getNode(ISD::RETURNADDR, dl, TLI.getPointerTy(),
3784 getValue(I.getOperand(1))));
3786 case Intrinsic::frameaddress:
3787 setValue(&I, DAG.getNode(ISD::FRAMEADDR, dl, TLI.getPointerTy(),
3788 getValue(I.getOperand(1))));
3790 case Intrinsic::setjmp:
3791 return "_setjmp"+!TLI.usesUnderscoreSetJmp();
3793 case Intrinsic::longjmp:
3794 return "_longjmp"+!TLI.usesUnderscoreLongJmp();
3796 case Intrinsic::memcpy: {
3797 SDValue Op1 = getValue(I.getOperand(1));
3798 SDValue Op2 = getValue(I.getOperand(2));
3799 SDValue Op3 = getValue(I.getOperand(3));
3800 unsigned Align = cast<ConstantInt>(I.getOperand(4))->getZExtValue();
3801 DAG.setRoot(DAG.getMemcpy(getRoot(), dl, Op1, Op2, Op3, Align, false,
3802 I.getOperand(1), 0, I.getOperand(2), 0));
3805 case Intrinsic::memset: {
3806 SDValue Op1 = getValue(I.getOperand(1));
3807 SDValue Op2 = getValue(I.getOperand(2));
3808 SDValue Op3 = getValue(I.getOperand(3));
3809 unsigned Align = cast<ConstantInt>(I.getOperand(4))->getZExtValue();
3810 DAG.setRoot(DAG.getMemset(getRoot(), dl, Op1, Op2, Op3, Align,
3811 I.getOperand(1), 0));
3814 case Intrinsic::memmove: {
3815 SDValue Op1 = getValue(I.getOperand(1));
3816 SDValue Op2 = getValue(I.getOperand(2));
3817 SDValue Op3 = getValue(I.getOperand(3));
3818 unsigned Align = cast<ConstantInt>(I.getOperand(4))->getZExtValue();
3820 // If the source and destination are known to not be aliases, we can
3821 // lower memmove as memcpy.
3822 uint64_t Size = -1ULL;
3823 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op3))
3824 Size = C->getZExtValue();
3825 if (AA->alias(I.getOperand(1), Size, I.getOperand(2), Size) ==
3826 AliasAnalysis::NoAlias) {
3827 DAG.setRoot(DAG.getMemcpy(getRoot(), dl, Op1, Op2, Op3, Align, false,
3828 I.getOperand(1), 0, I.getOperand(2), 0));
3832 DAG.setRoot(DAG.getMemmove(getRoot(), dl, Op1, Op2, Op3, Align,
3833 I.getOperand(1), 0, I.getOperand(2), 0));
3836 case Intrinsic::dbg_stoppoint: {
3837 DbgStopPointInst &SPI = cast<DbgStopPointInst>(I);
3838 if (isValidDebugInfoIntrinsic(SPI, CodeGenOpt::Default)) {
3839 MachineFunction &MF = DAG.getMachineFunction();
3840 DebugLoc Loc = ExtractDebugLocation(SPI, MF.getDebugLocInfo());
3841 setCurDebugLoc(Loc);
3843 if (OptLevel == CodeGenOpt::None)
3844 DAG.setRoot(DAG.getDbgStopPoint(Loc, getRoot(),
3851 case Intrinsic::dbg_region_start: {
3852 DwarfWriter *DW = DAG.getDwarfWriter();
3853 DbgRegionStartInst &RSI = cast<DbgRegionStartInst>(I);
3854 if (isValidDebugInfoIntrinsic(RSI, OptLevel) && DW
3855 && DW->ShouldEmitDwarfDebug()) {
3857 DW->RecordRegionStart(RSI.getContext());
3858 DAG.setRoot(DAG.getLabel(ISD::DBG_LABEL, getCurDebugLoc(),
3859 getRoot(), LabelID));
3863 case Intrinsic::dbg_region_end: {
3864 DwarfWriter *DW = DAG.getDwarfWriter();
3865 DbgRegionEndInst &REI = cast<DbgRegionEndInst>(I);
3867 if (!isValidDebugInfoIntrinsic(REI, OptLevel) || !DW
3868 || !DW->ShouldEmitDwarfDebug())
3871 MachineFunction &MF = DAG.getMachineFunction();
3872 DISubprogram Subprogram(REI.getContext());
3874 if (isInlinedFnEnd(REI, MF.getFunction())) {
3875 // This is end of inlined function. Debugging information for inlined
3876 // function is not handled yet (only supported by FastISel).
3877 if (OptLevel == CodeGenOpt::None) {
3878 unsigned ID = DW->RecordInlinedFnEnd(Subprogram);
3880 // Returned ID is 0 if this is unbalanced "end of inlined
3881 // scope". This could happen if optimizer eats dbg intrinsics or
3882 // "beginning of inlined scope" is not recoginized due to missing
3883 // location info. In such cases, do ignore this region.end.
3884 DAG.setRoot(DAG.getLabel(ISD::DBG_LABEL, getCurDebugLoc(),
3891 DW->RecordRegionEnd(REI.getContext());
3892 DAG.setRoot(DAG.getLabel(ISD::DBG_LABEL, getCurDebugLoc(),
3893 getRoot(), LabelID));
3896 case Intrinsic::dbg_func_start: {
3897 DwarfWriter *DW = DAG.getDwarfWriter();
3898 DbgFuncStartInst &FSI = cast<DbgFuncStartInst>(I);
3899 if (!isValidDebugInfoIntrinsic(FSI, CodeGenOpt::None))
3902 MachineFunction &MF = DAG.getMachineFunction();
3903 // This is a beginning of an inlined function.
3904 if (isInlinedFnStart(FSI, MF.getFunction())) {
3905 if (OptLevel != CodeGenOpt::None)
3906 // FIXME: Debugging informaation for inlined function is only
3907 // supported at CodeGenOpt::Node.
3910 DebugLoc PrevLoc = CurDebugLoc;
3911 // If llvm.dbg.func.start is seen in a new block before any
3912 // llvm.dbg.stoppoint intrinsic then the location info is unknown.
3913 // FIXME : Why DebugLoc is reset at the beginning of each block ?
3914 if (PrevLoc.isUnknown())
3917 // Record the source line.
3918 setCurDebugLoc(ExtractDebugLocation(FSI, MF.getDebugLocInfo()));
3920 if (!DW || !DW->ShouldEmitDwarfDebug())
3922 DebugLocTuple PrevLocTpl = MF.getDebugLocTuple(PrevLoc);
3923 DISubprogram SP(FSI.getSubprogram());
3924 DICompileUnit CU(PrevLocTpl.Scope);
3925 unsigned LabelID = DW->RecordInlinedFnStart(SP, CU,
3928 DAG.setRoot(DAG.getLabel(ISD::DBG_LABEL, getCurDebugLoc(),
3929 getRoot(), LabelID));
3933 // This is a beginning of a new function.
3934 MF.setDefaultDebugLoc(ExtractDebugLocation(FSI, MF.getDebugLocInfo()));
3936 if (!DW || !DW->ShouldEmitDwarfDebug())
3938 // llvm.dbg.func_start also defines beginning of function scope.
3939 DW->RecordRegionStart(FSI.getSubprogram());
3942 case Intrinsic::dbg_declare: {
3943 if (OptLevel != CodeGenOpt::None)
3944 // FIXME: Variable debug info is not supported here.
3946 DwarfWriter *DW = DAG.getDwarfWriter();
3949 DbgDeclareInst &DI = cast<DbgDeclareInst>(I);
3950 if (!isValidDebugInfoIntrinsic(DI, CodeGenOpt::None))
3953 MDNode *Variable = DI.getVariable();
3954 Value *Address = DI.getAddress();
3955 if (BitCastInst *BCI = dyn_cast<BitCastInst>(Address))
3956 Address = BCI->getOperand(0);
3957 AllocaInst *AI = dyn_cast<AllocaInst>(Address);
3958 // Don't handle byval struct arguments or VLAs, for example.
3961 DenseMap<const AllocaInst*, int>::iterator SI =
3962 FuncInfo.StaticAllocaMap.find(AI);
3963 if (SI == FuncInfo.StaticAllocaMap.end())
3965 int FI = SI->second;
3966 #ifdef ATTACH_DEBUG_INFO_TO_AN_INSN
3967 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
3969 MMI->setVariableDbgInfo(Variable, FI);
3971 DW->RecordVariable(Variable, FI);
3975 case Intrinsic::eh_exception: {
3976 // Insert the EXCEPTIONADDR instruction.
3977 assert(CurMBB->isLandingPad() &&"Call to eh.exception not in landing pad!");
3978 SDVTList VTs = DAG.getVTList(TLI.getPointerTy(), MVT::Other);
3980 Ops[0] = DAG.getRoot();
3981 SDValue Op = DAG.getNode(ISD::EXCEPTIONADDR, dl, VTs, Ops, 1);
3983 DAG.setRoot(Op.getValue(1));
3987 case Intrinsic::eh_selector: {
3988 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
3990 if (CurMBB->isLandingPad())
3991 AddCatchInfo(I, MMI, CurMBB);
3994 FuncInfo.CatchInfoLost.insert(&I);
3996 // FIXME: Mark exception selector register as live in. Hack for PR1508.
3997 unsigned Reg = TLI.getExceptionSelectorRegister();
3998 if (Reg) CurMBB->addLiveIn(Reg);
4001 // Insert the EHSELECTION instruction.
4002 SDVTList VTs = DAG.getVTList(TLI.getPointerTy(), MVT::Other);
4004 Ops[0] = getValue(I.getOperand(1));
4006 SDValue Op = DAG.getNode(ISD::EHSELECTION, dl, VTs, Ops, 2);
4008 DAG.setRoot(Op.getValue(1));
4010 setValue(&I, DAG.getSExtOrTrunc(Op, dl, MVT::i32));
4014 case Intrinsic::eh_typeid_for: {
4015 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
4018 // Find the type id for the given typeinfo.
4019 GlobalVariable *GV = ExtractTypeInfo(I.getOperand(1));
4021 unsigned TypeID = MMI->getTypeIDFor(GV);
4022 setValue(&I, DAG.getConstant(TypeID, MVT::i32));
4024 // Return something different to eh_selector.
4025 setValue(&I, DAG.getConstant(1, MVT::i32));
4031 case Intrinsic::eh_return_i32:
4032 case Intrinsic::eh_return_i64:
4033 if (MachineModuleInfo *MMI = DAG.getMachineModuleInfo()) {
4034 MMI->setCallsEHReturn(true);
4035 DAG.setRoot(DAG.getNode(ISD::EH_RETURN, dl,
4038 getValue(I.getOperand(1)),
4039 getValue(I.getOperand(2))));
4041 setValue(&I, DAG.getConstant(0, TLI.getPointerTy()));
4045 case Intrinsic::eh_unwind_init:
4046 if (MachineModuleInfo *MMI = DAG.getMachineModuleInfo()) {
4047 MMI->setCallsUnwindInit(true);
4052 case Intrinsic::eh_dwarf_cfa: {
4053 EVT VT = getValue(I.getOperand(1)).getValueType();
4054 SDValue CfaArg = DAG.getSExtOrTrunc(getValue(I.getOperand(1)), dl,
4055 TLI.getPointerTy());
4057 SDValue Offset = DAG.getNode(ISD::ADD, dl,
4059 DAG.getNode(ISD::FRAME_TO_ARGS_OFFSET, dl,
4060 TLI.getPointerTy()),
4062 setValue(&I, DAG.getNode(ISD::ADD, dl,
4064 DAG.getNode(ISD::FRAMEADDR, dl,
4067 TLI.getPointerTy())),
4071 case Intrinsic::convertff:
4072 case Intrinsic::convertfsi:
4073 case Intrinsic::convertfui:
4074 case Intrinsic::convertsif:
4075 case Intrinsic::convertuif:
4076 case Intrinsic::convertss:
4077 case Intrinsic::convertsu:
4078 case Intrinsic::convertus:
4079 case Intrinsic::convertuu: {
4080 ISD::CvtCode Code = ISD::CVT_INVALID;
4081 switch (Intrinsic) {
4082 case Intrinsic::convertff: Code = ISD::CVT_FF; break;
4083 case Intrinsic::convertfsi: Code = ISD::CVT_FS; break;
4084 case Intrinsic::convertfui: Code = ISD::CVT_FU; break;
4085 case Intrinsic::convertsif: Code = ISD::CVT_SF; break;
4086 case Intrinsic::convertuif: Code = ISD::CVT_UF; break;
4087 case Intrinsic::convertss: Code = ISD::CVT_SS; break;
4088 case Intrinsic::convertsu: Code = ISD::CVT_SU; break;
4089 case Intrinsic::convertus: Code = ISD::CVT_US; break;
4090 case Intrinsic::convertuu: Code = ISD::CVT_UU; break;
4092 EVT DestVT = TLI.getValueType(I.getType());
4093 Value* Op1 = I.getOperand(1);
4094 setValue(&I, DAG.getConvertRndSat(DestVT, getCurDebugLoc(), getValue(Op1),
4095 DAG.getValueType(DestVT),
4096 DAG.getValueType(getValue(Op1).getValueType()),
4097 getValue(I.getOperand(2)),
4098 getValue(I.getOperand(3)),
4103 case Intrinsic::sqrt:
4104 setValue(&I, DAG.getNode(ISD::FSQRT, dl,
4105 getValue(I.getOperand(1)).getValueType(),
4106 getValue(I.getOperand(1))));
4108 case Intrinsic::powi:
4109 setValue(&I, DAG.getNode(ISD::FPOWI, dl,
4110 getValue(I.getOperand(1)).getValueType(),
4111 getValue(I.getOperand(1)),
4112 getValue(I.getOperand(2))));
4114 case Intrinsic::sin:
4115 setValue(&I, DAG.getNode(ISD::FSIN, dl,
4116 getValue(I.getOperand(1)).getValueType(),
4117 getValue(I.getOperand(1))));
4119 case Intrinsic::cos:
4120 setValue(&I, DAG.getNode(ISD::FCOS, dl,
4121 getValue(I.getOperand(1)).getValueType(),
4122 getValue(I.getOperand(1))));
4124 case Intrinsic::log:
4127 case Intrinsic::log2:
4130 case Intrinsic::log10:
4133 case Intrinsic::exp:
4136 case Intrinsic::exp2:
4139 case Intrinsic::pow:
4142 case Intrinsic::pcmarker: {
4143 SDValue Tmp = getValue(I.getOperand(1));
4144 DAG.setRoot(DAG.getNode(ISD::PCMARKER, dl, MVT::Other, getRoot(), Tmp));
4147 case Intrinsic::readcyclecounter: {
4148 SDValue Op = getRoot();
4149 SDValue Tmp = DAG.getNode(ISD::READCYCLECOUNTER, dl,
4150 DAG.getVTList(MVT::i64, MVT::Other),
4153 DAG.setRoot(Tmp.getValue(1));
4156 case Intrinsic::bswap:
4157 setValue(&I, DAG.getNode(ISD::BSWAP, dl,
4158 getValue(I.getOperand(1)).getValueType(),
4159 getValue(I.getOperand(1))));
4161 case Intrinsic::cttz: {
4162 SDValue Arg = getValue(I.getOperand(1));
4163 EVT Ty = Arg.getValueType();
4164 SDValue result = DAG.getNode(ISD::CTTZ, dl, Ty, Arg);
4165 setValue(&I, result);
4168 case Intrinsic::ctlz: {
4169 SDValue Arg = getValue(I.getOperand(1));
4170 EVT Ty = Arg.getValueType();
4171 SDValue result = DAG.getNode(ISD::CTLZ, dl, Ty, Arg);
4172 setValue(&I, result);
4175 case Intrinsic::ctpop: {
4176 SDValue Arg = getValue(I.getOperand(1));
4177 EVT Ty = Arg.getValueType();
4178 SDValue result = DAG.getNode(ISD::CTPOP, dl, Ty, Arg);
4179 setValue(&I, result);
4182 case Intrinsic::stacksave: {
4183 SDValue Op = getRoot();
4184 SDValue Tmp = DAG.getNode(ISD::STACKSAVE, dl,
4185 DAG.getVTList(TLI.getPointerTy(), MVT::Other), &Op, 1);
4187 DAG.setRoot(Tmp.getValue(1));
4190 case Intrinsic::stackrestore: {
4191 SDValue Tmp = getValue(I.getOperand(1));
4192 DAG.setRoot(DAG.getNode(ISD::STACKRESTORE, dl, MVT::Other, getRoot(), Tmp));
4195 case Intrinsic::stackprotector: {
4196 // Emit code into the DAG to store the stack guard onto the stack.
4197 MachineFunction &MF = DAG.getMachineFunction();
4198 MachineFrameInfo *MFI = MF.getFrameInfo();
4199 EVT PtrTy = TLI.getPointerTy();
4201 SDValue Src = getValue(I.getOperand(1)); // The guard's value.
4202 AllocaInst *Slot = cast<AllocaInst>(I.getOperand(2));
4204 int FI = FuncInfo.StaticAllocaMap[Slot];
4205 MFI->setStackProtectorIndex(FI);
4207 SDValue FIN = DAG.getFrameIndex(FI, PtrTy);
4209 // Store the stack protector onto the stack.
4210 SDValue Result = DAG.getStore(getRoot(), getCurDebugLoc(), Src, FIN,
4211 PseudoSourceValue::getFixedStack(FI),
4213 setValue(&I, Result);
4214 DAG.setRoot(Result);
4217 case Intrinsic::objectsize: {
4218 // If we don't know by now, we're never going to know.
4219 ConstantInt *CI = dyn_cast<ConstantInt>(I.getOperand(2));
4221 assert(CI && "Non-constant type in __builtin_object_size?");
4223 SDValue Arg = getValue(I.getOperand(0));
4224 EVT Ty = Arg.getValueType();
4226 if (CI->getZExtValue() < 2)
4227 setValue(&I, DAG.getConstant(-1, Ty));
4229 setValue(&I, DAG.getConstant(0, Ty));
4232 case Intrinsic::var_annotation:
4233 // Discard annotate attributes
4236 case Intrinsic::init_trampoline: {
4237 const Function *F = cast<Function>(I.getOperand(2)->stripPointerCasts());
4241 Ops[1] = getValue(I.getOperand(1));
4242 Ops[2] = getValue(I.getOperand(2));
4243 Ops[3] = getValue(I.getOperand(3));
4244 Ops[4] = DAG.getSrcValue(I.getOperand(1));
4245 Ops[5] = DAG.getSrcValue(F);
4247 SDValue Tmp = DAG.getNode(ISD::TRAMPOLINE, dl,
4248 DAG.getVTList(TLI.getPointerTy(), MVT::Other),
4252 DAG.setRoot(Tmp.getValue(1));
4256 case Intrinsic::gcroot:
4258 Value *Alloca = I.getOperand(1);
4259 Constant *TypeMap = cast<Constant>(I.getOperand(2));
4261 FrameIndexSDNode *FI = cast<FrameIndexSDNode>(getValue(Alloca).getNode());
4262 GFI->addStackRoot(FI->getIndex(), TypeMap);
4266 case Intrinsic::gcread:
4267 case Intrinsic::gcwrite:
4268 llvm_unreachable("GC failed to lower gcread/gcwrite intrinsics!");
4271 case Intrinsic::flt_rounds: {
4272 setValue(&I, DAG.getNode(ISD::FLT_ROUNDS_, dl, MVT::i32));
4276 case Intrinsic::trap: {
4277 DAG.setRoot(DAG.getNode(ISD::TRAP, dl,MVT::Other, getRoot()));
4281 case Intrinsic::uadd_with_overflow:
4282 return implVisitAluOverflow(I, ISD::UADDO);
4283 case Intrinsic::sadd_with_overflow:
4284 return implVisitAluOverflow(I, ISD::SADDO);
4285 case Intrinsic::usub_with_overflow:
4286 return implVisitAluOverflow(I, ISD::USUBO);
4287 case Intrinsic::ssub_with_overflow:
4288 return implVisitAluOverflow(I, ISD::SSUBO);
4289 case Intrinsic::umul_with_overflow:
4290 return implVisitAluOverflow(I, ISD::UMULO);
4291 case Intrinsic::smul_with_overflow:
4292 return implVisitAluOverflow(I, ISD::SMULO);
4294 case Intrinsic::prefetch: {
4297 Ops[1] = getValue(I.getOperand(1));
4298 Ops[2] = getValue(I.getOperand(2));
4299 Ops[3] = getValue(I.getOperand(3));
4300 DAG.setRoot(DAG.getNode(ISD::PREFETCH, dl, MVT::Other, &Ops[0], 4));
4304 case Intrinsic::memory_barrier: {
4307 for (int x = 1; x < 6; ++x)
4308 Ops[x] = getValue(I.getOperand(x));
4310 DAG.setRoot(DAG.getNode(ISD::MEMBARRIER, dl, MVT::Other, &Ops[0], 6));
4313 case Intrinsic::atomic_cmp_swap: {
4314 SDValue Root = getRoot();
4316 DAG.getAtomic(ISD::ATOMIC_CMP_SWAP, getCurDebugLoc(),
4317 getValue(I.getOperand(2)).getValueType().getSimpleVT(),
4319 getValue(I.getOperand(1)),
4320 getValue(I.getOperand(2)),
4321 getValue(I.getOperand(3)),
4324 DAG.setRoot(L.getValue(1));
4327 case Intrinsic::atomic_load_add:
4328 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_ADD);
4329 case Intrinsic::atomic_load_sub:
4330 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_SUB);
4331 case Intrinsic::atomic_load_or:
4332 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_OR);
4333 case Intrinsic::atomic_load_xor:
4334 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_XOR);
4335 case Intrinsic::atomic_load_and:
4336 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_AND);
4337 case Intrinsic::atomic_load_nand:
4338 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_NAND);
4339 case Intrinsic::atomic_load_max:
4340 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_MAX);
4341 case Intrinsic::atomic_load_min:
4342 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_MIN);
4343 case Intrinsic::atomic_load_umin:
4344 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_UMIN);
4345 case Intrinsic::atomic_load_umax:
4346 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_UMAX);
4347 case Intrinsic::atomic_swap:
4348 return implVisitBinaryAtomic(I, ISD::ATOMIC_SWAP);
4352 /// Test if the given instruction is in a position to be optimized
4353 /// with a tail-call. This roughly means that it's in a block with
4354 /// a return and there's nothing that needs to be scheduled
4355 /// between it and the return.
4357 /// This function only tests target-independent requirements.
4358 /// For target-dependent requirements, a target should override
4359 /// TargetLowering::IsEligibleForTailCallOptimization.
4362 isInTailCallPosition(const Instruction *I, Attributes RetAttr,
4363 const TargetLowering &TLI) {
4364 const BasicBlock *ExitBB = I->getParent();
4365 const TerminatorInst *Term = ExitBB->getTerminator();
4366 const ReturnInst *Ret = dyn_cast<ReturnInst>(Term);
4367 const Function *F = ExitBB->getParent();
4369 // The block must end in a return statement or an unreachable.
4370 if (!Ret && !isa<UnreachableInst>(Term)) return false;
4372 // If I will have a chain, make sure no other instruction that will have a
4373 // chain interposes between I and the return.
4374 if (I->mayHaveSideEffects() || I->mayReadFromMemory() ||
4375 !I->isSafeToSpeculativelyExecute())
4376 for (BasicBlock::const_iterator BBI = prior(prior(ExitBB->end())); ;
4380 if (BBI->mayHaveSideEffects() || BBI->mayReadFromMemory() ||
4381 !BBI->isSafeToSpeculativelyExecute())
4385 // If the block ends with a void return or unreachable, it doesn't matter
4386 // what the call's return type is.
4387 if (!Ret || Ret->getNumOperands() == 0) return true;
4389 // Conservatively require the attributes of the call to match those of
4391 if (F->getAttributes().getRetAttributes() != RetAttr)
4394 // Otherwise, make sure the unmodified return value of I is the return value.
4395 for (const Instruction *U = dyn_cast<Instruction>(Ret->getOperand(0)); ;
4396 U = dyn_cast<Instruction>(U->getOperand(0))) {
4399 if (!U->hasOneUse())
4403 // Check for a truly no-op truncate.
4404 if (isa<TruncInst>(U) &&
4405 TLI.isTruncateFree(U->getOperand(0)->getType(), U->getType()))
4407 // Check for a truly no-op bitcast.
4408 if (isa<BitCastInst>(U) &&
4409 (U->getOperand(0)->getType() == U->getType() ||
4410 (isa<PointerType>(U->getOperand(0)->getType()) &&
4411 isa<PointerType>(U->getType()))))
4413 // Otherwise it's not a true no-op.
4420 void SelectionDAGLowering::LowerCallTo(CallSite CS, SDValue Callee,
4422 MachineBasicBlock *LandingPad) {
4423 const PointerType *PT = cast<PointerType>(CS.getCalledValue()->getType());
4424 const FunctionType *FTy = cast<FunctionType>(PT->getElementType());
4425 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
4426 unsigned BeginLabel = 0, EndLabel = 0;
4428 TargetLowering::ArgListTy Args;
4429 TargetLowering::ArgListEntry Entry;
4430 Args.reserve(CS.arg_size());
4432 for (CallSite::arg_iterator i = CS.arg_begin(), e = CS.arg_end();
4434 SDValue ArgNode = getValue(*i);
4435 Entry.Node = ArgNode; Entry.Ty = (*i)->getType();
4437 unsigned attrInd = i - CS.arg_begin() + 1;
4438 Entry.isSExt = CS.paramHasAttr(attrInd, Attribute::SExt);
4439 Entry.isZExt = CS.paramHasAttr(attrInd, Attribute::ZExt);
4440 Entry.isInReg = CS.paramHasAttr(attrInd, Attribute::InReg);
4441 Entry.isSRet = CS.paramHasAttr(attrInd, Attribute::StructRet);
4442 Entry.isNest = CS.paramHasAttr(attrInd, Attribute::Nest);
4443 Entry.isByVal = CS.paramHasAttr(attrInd, Attribute::ByVal);
4444 Entry.Alignment = CS.getParamAlignment(attrInd);
4445 Args.push_back(Entry);
4448 if (LandingPad && MMI) {
4449 // Insert a label before the invoke call to mark the try range. This can be
4450 // used to detect deletion of the invoke via the MachineModuleInfo.
4451 BeginLabel = MMI->NextLabelID();
4453 // Both PendingLoads and PendingExports must be flushed here;
4454 // this call might not return.
4456 DAG.setRoot(DAG.getLabel(ISD::EH_LABEL, getCurDebugLoc(),
4457 getControlRoot(), BeginLabel));
4460 // Check if target-independent constraints permit a tail call here.
4461 // Target-dependent constraints are checked within TLI.LowerCallTo.
4463 !isInTailCallPosition(CS.getInstruction(),
4464 CS.getAttributes().getRetAttributes(),
4468 std::pair<SDValue,SDValue> Result =
4469 TLI.LowerCallTo(getRoot(), CS.getType(),
4470 CS.paramHasAttr(0, Attribute::SExt),
4471 CS.paramHasAttr(0, Attribute::ZExt), FTy->isVarArg(),
4472 CS.paramHasAttr(0, Attribute::InReg), FTy->getNumParams(),
4473 CS.getCallingConv(),
4475 !CS.getInstruction()->use_empty(),
4476 Callee, Args, DAG, getCurDebugLoc());
4477 assert((isTailCall || Result.second.getNode()) &&
4478 "Non-null chain expected with non-tail call!");
4479 assert((Result.second.getNode() || !Result.first.getNode()) &&
4480 "Null value expected with tail call!");
4481 if (Result.first.getNode())
4482 setValue(CS.getInstruction(), Result.first);
4483 // As a special case, a null chain means that a tail call has
4484 // been emitted and the DAG root is already updated.
4485 if (Result.second.getNode())
4486 DAG.setRoot(Result.second);
4490 if (LandingPad && MMI) {
4491 // Insert a label at the end of the invoke call to mark the try range. This
4492 // can be used to detect deletion of the invoke via the MachineModuleInfo.
4493 EndLabel = MMI->NextLabelID();
4494 DAG.setRoot(DAG.getLabel(ISD::EH_LABEL, getCurDebugLoc(),
4495 getRoot(), EndLabel));
4497 // Inform MachineModuleInfo of range.
4498 MMI->addInvoke(LandingPad, BeginLabel, EndLabel);
4503 void SelectionDAGLowering::visitCall(CallInst &I) {
4504 const char *RenameFn = 0;
4505 if (Function *F = I.getCalledFunction()) {
4506 if (F->isDeclaration()) {
4507 const TargetIntrinsicInfo *II = TLI.getTargetMachine().getIntrinsicInfo();
4509 if (unsigned IID = II->getIntrinsicID(F)) {
4510 RenameFn = visitIntrinsicCall(I, IID);
4515 if (unsigned IID = F->getIntrinsicID()) {
4516 RenameFn = visitIntrinsicCall(I, IID);
4522 // Check for well-known libc/libm calls. If the function is internal, it
4523 // can't be a library call.
4524 if (!F->hasLocalLinkage() && F->hasName()) {
4525 StringRef Name = F->getName();
4526 if (Name == "copysign" || Name == "copysignf") {
4527 if (I.getNumOperands() == 3 && // Basic sanity checks.
4528 I.getOperand(1)->getType()->isFloatingPoint() &&
4529 I.getType() == I.getOperand(1)->getType() &&
4530 I.getType() == I.getOperand(2)->getType()) {
4531 SDValue LHS = getValue(I.getOperand(1));
4532 SDValue RHS = getValue(I.getOperand(2));
4533 setValue(&I, DAG.getNode(ISD::FCOPYSIGN, getCurDebugLoc(),
4534 LHS.getValueType(), LHS, RHS));
4537 } else if (Name == "fabs" || Name == "fabsf" || Name == "fabsl") {
4538 if (I.getNumOperands() == 2 && // Basic sanity checks.
4539 I.getOperand(1)->getType()->isFloatingPoint() &&
4540 I.getType() == I.getOperand(1)->getType()) {
4541 SDValue Tmp = getValue(I.getOperand(1));
4542 setValue(&I, DAG.getNode(ISD::FABS, getCurDebugLoc(),
4543 Tmp.getValueType(), Tmp));
4546 } else if (Name == "sin" || Name == "sinf" || Name == "sinl") {
4547 if (I.getNumOperands() == 2 && // Basic sanity checks.
4548 I.getOperand(1)->getType()->isFloatingPoint() &&
4549 I.getType() == I.getOperand(1)->getType() &&
4550 I.onlyReadsMemory()) {
4551 SDValue Tmp = getValue(I.getOperand(1));
4552 setValue(&I, DAG.getNode(ISD::FSIN, getCurDebugLoc(),
4553 Tmp.getValueType(), Tmp));
4556 } else if (Name == "cos" || Name == "cosf" || Name == "cosl") {
4557 if (I.getNumOperands() == 2 && // Basic sanity checks.
4558 I.getOperand(1)->getType()->isFloatingPoint() &&
4559 I.getType() == I.getOperand(1)->getType() &&
4560 I.onlyReadsMemory()) {
4561 SDValue Tmp = getValue(I.getOperand(1));
4562 setValue(&I, DAG.getNode(ISD::FCOS, getCurDebugLoc(),
4563 Tmp.getValueType(), Tmp));
4566 } else if (Name == "sqrt" || Name == "sqrtf" || Name == "sqrtl") {
4567 if (I.getNumOperands() == 2 && // Basic sanity checks.
4568 I.getOperand(1)->getType()->isFloatingPoint() &&
4569 I.getType() == I.getOperand(1)->getType() &&
4570 I.onlyReadsMemory()) {
4571 SDValue Tmp = getValue(I.getOperand(1));
4572 setValue(&I, DAG.getNode(ISD::FSQRT, getCurDebugLoc(),
4573 Tmp.getValueType(), Tmp));
4578 } else if (isa<InlineAsm>(I.getOperand(0))) {
4585 Callee = getValue(I.getOperand(0));
4587 Callee = DAG.getExternalSymbol(RenameFn, TLI.getPointerTy());
4589 // Check if we can potentially perform a tail call. More detailed
4590 // checking is be done within LowerCallTo, after more information
4591 // about the call is known.
4592 bool isTailCall = PerformTailCallOpt && I.isTailCall();
4594 LowerCallTo(&I, Callee, isTailCall);
4598 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from
4599 /// this value and returns the result as a ValueVT value. This uses
4600 /// Chain/Flag as the input and updates them for the output Chain/Flag.
4601 /// If the Flag pointer is NULL, no flag is used.
4602 SDValue RegsForValue::getCopyFromRegs(SelectionDAG &DAG, DebugLoc dl,
4604 SDValue *Flag) const {
4605 // Assemble the legal parts into the final values.
4606 SmallVector<SDValue, 4> Values(ValueVTs.size());
4607 SmallVector<SDValue, 8> Parts;
4608 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) {
4609 // Copy the legal parts from the registers.
4610 EVT ValueVT = ValueVTs[Value];
4611 unsigned NumRegs = TLI->getNumRegisters(*DAG.getContext(), ValueVT);
4612 EVT RegisterVT = RegVTs[Value];
4614 Parts.resize(NumRegs);
4615 for (unsigned i = 0; i != NumRegs; ++i) {
4618 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT);
4620 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT, *Flag);
4621 *Flag = P.getValue(2);
4623 Chain = P.getValue(1);
4625 // If the source register was virtual and if we know something about it,
4626 // add an assert node.
4627 if (TargetRegisterInfo::isVirtualRegister(Regs[Part+i]) &&
4628 RegisterVT.isInteger() && !RegisterVT.isVector()) {
4629 unsigned SlotNo = Regs[Part+i]-TargetRegisterInfo::FirstVirtualRegister;
4630 FunctionLoweringInfo &FLI = DAG.getFunctionLoweringInfo();
4631 if (FLI.LiveOutRegInfo.size() > SlotNo) {
4632 FunctionLoweringInfo::LiveOutInfo &LOI = FLI.LiveOutRegInfo[SlotNo];
4634 unsigned RegSize = RegisterVT.getSizeInBits();
4635 unsigned NumSignBits = LOI.NumSignBits;
4636 unsigned NumZeroBits = LOI.KnownZero.countLeadingOnes();
4638 // FIXME: We capture more information than the dag can represent. For
4639 // now, just use the tightest assertzext/assertsext possible.
4641 EVT FromVT(MVT::Other);
4642 if (NumSignBits == RegSize)
4643 isSExt = true, FromVT = MVT::i1; // ASSERT SEXT 1
4644 else if (NumZeroBits >= RegSize-1)
4645 isSExt = false, FromVT = MVT::i1; // ASSERT ZEXT 1
4646 else if (NumSignBits > RegSize-8)
4647 isSExt = true, FromVT = MVT::i8; // ASSERT SEXT 8
4648 else if (NumZeroBits >= RegSize-8)
4649 isSExt = false, FromVT = MVT::i8; // ASSERT ZEXT 8
4650 else if (NumSignBits > RegSize-16)
4651 isSExt = true, FromVT = MVT::i16; // ASSERT SEXT 16
4652 else if (NumZeroBits >= RegSize-16)
4653 isSExt = false, FromVT = MVT::i16; // ASSERT ZEXT 16
4654 else if (NumSignBits > RegSize-32)
4655 isSExt = true, FromVT = MVT::i32; // ASSERT SEXT 32
4656 else if (NumZeroBits >= RegSize-32)
4657 isSExt = false, FromVT = MVT::i32; // ASSERT ZEXT 32
4659 if (FromVT != MVT::Other) {
4660 P = DAG.getNode(isSExt ? ISD::AssertSext : ISD::AssertZext, dl,
4661 RegisterVT, P, DAG.getValueType(FromVT));
4670 Values[Value] = getCopyFromParts(DAG, dl, Parts.begin(),
4671 NumRegs, RegisterVT, ValueVT);
4676 return DAG.getNode(ISD::MERGE_VALUES, dl,
4677 DAG.getVTList(&ValueVTs[0], ValueVTs.size()),
4678 &Values[0], ValueVTs.size());
4681 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
4682 /// specified value into the registers specified by this object. This uses
4683 /// Chain/Flag as the input and updates them for the output Chain/Flag.
4684 /// If the Flag pointer is NULL, no flag is used.
4685 void RegsForValue::getCopyToRegs(SDValue Val, SelectionDAG &DAG, DebugLoc dl,
4686 SDValue &Chain, SDValue *Flag) const {
4687 // Get the list of the values's legal parts.
4688 unsigned NumRegs = Regs.size();
4689 SmallVector<SDValue, 8> Parts(NumRegs);
4690 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) {
4691 EVT ValueVT = ValueVTs[Value];
4692 unsigned NumParts = TLI->getNumRegisters(*DAG.getContext(), ValueVT);
4693 EVT RegisterVT = RegVTs[Value];
4695 getCopyToParts(DAG, dl, Val.getValue(Val.getResNo() + Value),
4696 &Parts[Part], NumParts, RegisterVT);
4700 // Copy the parts into the registers.
4701 SmallVector<SDValue, 8> Chains(NumRegs);
4702 for (unsigned i = 0; i != NumRegs; ++i) {
4705 Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i]);
4707 Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i], *Flag);
4708 *Flag = Part.getValue(1);
4710 Chains[i] = Part.getValue(0);
4713 if (NumRegs == 1 || Flag)
4714 // If NumRegs > 1 && Flag is used then the use of the last CopyToReg is
4715 // flagged to it. That is the CopyToReg nodes and the user are considered
4716 // a single scheduling unit. If we create a TokenFactor and return it as
4717 // chain, then the TokenFactor is both a predecessor (operand) of the
4718 // user as well as a successor (the TF operands are flagged to the user).
4719 // c1, f1 = CopyToReg
4720 // c2, f2 = CopyToReg
4721 // c3 = TokenFactor c1, c2
4724 Chain = Chains[NumRegs-1];
4726 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Chains[0], NumRegs);
4729 /// AddInlineAsmOperands - Add this value to the specified inlineasm node
4730 /// operand list. This adds the code marker and includes the number of
4731 /// values added into it.
4732 void RegsForValue::AddInlineAsmOperands(unsigned Code,
4733 bool HasMatching,unsigned MatchingIdx,
4735 std::vector<SDValue> &Ops) const {
4736 EVT IntPtrTy = DAG.getTargetLoweringInfo().getPointerTy();
4737 assert(Regs.size() < (1 << 13) && "Too many inline asm outputs!");
4738 unsigned Flag = Code | (Regs.size() << 3);
4740 Flag |= 0x80000000 | (MatchingIdx << 16);
4741 Ops.push_back(DAG.getTargetConstant(Flag, IntPtrTy));
4742 for (unsigned Value = 0, Reg = 0, e = ValueVTs.size(); Value != e; ++Value) {
4743 unsigned NumRegs = TLI->getNumRegisters(*DAG.getContext(), ValueVTs[Value]);
4744 EVT RegisterVT = RegVTs[Value];
4745 for (unsigned i = 0; i != NumRegs; ++i) {
4746 assert(Reg < Regs.size() && "Mismatch in # registers expected");
4747 Ops.push_back(DAG.getRegister(Regs[Reg++], RegisterVT));
4752 /// isAllocatableRegister - If the specified register is safe to allocate,
4753 /// i.e. it isn't a stack pointer or some other special register, return the
4754 /// register class for the register. Otherwise, return null.
4755 static const TargetRegisterClass *
4756 isAllocatableRegister(unsigned Reg, MachineFunction &MF,
4757 const TargetLowering &TLI,
4758 const TargetRegisterInfo *TRI) {
4759 EVT FoundVT = MVT::Other;
4760 const TargetRegisterClass *FoundRC = 0;
4761 for (TargetRegisterInfo::regclass_iterator RCI = TRI->regclass_begin(),
4762 E = TRI->regclass_end(); RCI != E; ++RCI) {
4763 EVT ThisVT = MVT::Other;
4765 const TargetRegisterClass *RC = *RCI;
4766 // If none of the the value types for this register class are valid, we
4767 // can't use it. For example, 64-bit reg classes on 32-bit targets.
4768 for (TargetRegisterClass::vt_iterator I = RC->vt_begin(), E = RC->vt_end();
4770 if (TLI.isTypeLegal(*I)) {
4771 // If we have already found this register in a different register class,
4772 // choose the one with the largest VT specified. For example, on
4773 // PowerPC, we favor f64 register classes over f32.
4774 if (FoundVT == MVT::Other || FoundVT.bitsLT(*I)) {
4781 if (ThisVT == MVT::Other) continue;
4783 // NOTE: This isn't ideal. In particular, this might allocate the
4784 // frame pointer in functions that need it (due to them not being taken
4785 // out of allocation, because a variable sized allocation hasn't been seen
4786 // yet). This is a slight code pessimization, but should still work.
4787 for (TargetRegisterClass::iterator I = RC->allocation_order_begin(MF),
4788 E = RC->allocation_order_end(MF); I != E; ++I)
4790 // We found a matching register class. Keep looking at others in case
4791 // we find one with larger registers that this physreg is also in.
4802 /// AsmOperandInfo - This contains information for each constraint that we are
4804 class VISIBILITY_HIDDEN SDISelAsmOperandInfo :
4805 public TargetLowering::AsmOperandInfo {
4807 /// CallOperand - If this is the result output operand or a clobber
4808 /// this is null, otherwise it is the incoming operand to the CallInst.
4809 /// This gets modified as the asm is processed.
4810 SDValue CallOperand;
4812 /// AssignedRegs - If this is a register or register class operand, this
4813 /// contains the set of register corresponding to the operand.
4814 RegsForValue AssignedRegs;
4816 explicit SDISelAsmOperandInfo(const InlineAsm::ConstraintInfo &info)
4817 : TargetLowering::AsmOperandInfo(info), CallOperand(0,0) {
4820 /// MarkAllocatedRegs - Once AssignedRegs is set, mark the assigned registers
4821 /// busy in OutputRegs/InputRegs.
4822 void MarkAllocatedRegs(bool isOutReg, bool isInReg,
4823 std::set<unsigned> &OutputRegs,
4824 std::set<unsigned> &InputRegs,
4825 const TargetRegisterInfo &TRI) const {
4827 for (unsigned i = 0, e = AssignedRegs.Regs.size(); i != e; ++i)
4828 MarkRegAndAliases(AssignedRegs.Regs[i], OutputRegs, TRI);
4831 for (unsigned i = 0, e = AssignedRegs.Regs.size(); i != e; ++i)
4832 MarkRegAndAliases(AssignedRegs.Regs[i], InputRegs, TRI);
4836 /// getCallOperandValEVT - Return the EVT of the Value* that this operand
4837 /// corresponds to. If there is no Value* for this operand, it returns
4839 EVT getCallOperandValEVT(LLVMContext &Context,
4840 const TargetLowering &TLI,
4841 const TargetData *TD) const {
4842 if (CallOperandVal == 0) return MVT::Other;
4844 if (isa<BasicBlock>(CallOperandVal))
4845 return TLI.getPointerTy();
4847 const llvm::Type *OpTy = CallOperandVal->getType();
4849 // If this is an indirect operand, the operand is a pointer to the
4852 OpTy = cast<PointerType>(OpTy)->getElementType();
4854 // If OpTy is not a single value, it may be a struct/union that we
4855 // can tile with integers.
4856 if (!OpTy->isSingleValueType() && OpTy->isSized()) {
4857 unsigned BitSize = TD->getTypeSizeInBits(OpTy);
4866 OpTy = IntegerType::get(Context, BitSize);
4871 return TLI.getValueType(OpTy, true);
4875 /// MarkRegAndAliases - Mark the specified register and all aliases in the
4877 static void MarkRegAndAliases(unsigned Reg, std::set<unsigned> &Regs,
4878 const TargetRegisterInfo &TRI) {
4879 assert(TargetRegisterInfo::isPhysicalRegister(Reg) && "Isn't a physreg");
4881 if (const unsigned *Aliases = TRI.getAliasSet(Reg))
4882 for (; *Aliases; ++Aliases)
4883 Regs.insert(*Aliases);
4886 } // end llvm namespace.
4889 /// GetRegistersForValue - Assign registers (virtual or physical) for the
4890 /// specified operand. We prefer to assign virtual registers, to allow the
4891 /// register allocator handle the assignment process. However, if the asm uses
4892 /// features that we can't model on machineinstrs, we have SDISel do the
4893 /// allocation. This produces generally horrible, but correct, code.
4895 /// OpInfo describes the operand.
4896 /// Input and OutputRegs are the set of already allocated physical registers.
4898 void SelectionDAGLowering::
4899 GetRegistersForValue(SDISelAsmOperandInfo &OpInfo,
4900 std::set<unsigned> &OutputRegs,
4901 std::set<unsigned> &InputRegs) {
4902 LLVMContext &Context = FuncInfo.Fn->getContext();
4904 // Compute whether this value requires an input register, an output register,
4906 bool isOutReg = false;
4907 bool isInReg = false;
4908 switch (OpInfo.Type) {
4909 case InlineAsm::isOutput:
4912 // If there is an input constraint that matches this, we need to reserve
4913 // the input register so no other inputs allocate to it.
4914 isInReg = OpInfo.hasMatchingInput();
4916 case InlineAsm::isInput:
4920 case InlineAsm::isClobber:
4927 MachineFunction &MF = DAG.getMachineFunction();
4928 SmallVector<unsigned, 4> Regs;
4930 // If this is a constraint for a single physreg, or a constraint for a
4931 // register class, find it.
4932 std::pair<unsigned, const TargetRegisterClass*> PhysReg =
4933 TLI.getRegForInlineAsmConstraint(OpInfo.ConstraintCode,
4934 OpInfo.ConstraintVT);
4936 unsigned NumRegs = 1;
4937 if (OpInfo.ConstraintVT != MVT::Other) {
4938 // If this is a FP input in an integer register (or visa versa) insert a bit
4939 // cast of the input value. More generally, handle any case where the input
4940 // value disagrees with the register class we plan to stick this in.
4941 if (OpInfo.Type == InlineAsm::isInput &&
4942 PhysReg.second && !PhysReg.second->hasType(OpInfo.ConstraintVT)) {
4943 // Try to convert to the first EVT that the reg class contains. If the
4944 // types are identical size, use a bitcast to convert (e.g. two differing
4946 EVT RegVT = *PhysReg.second->vt_begin();
4947 if (RegVT.getSizeInBits() == OpInfo.ConstraintVT.getSizeInBits()) {
4948 OpInfo.CallOperand = DAG.getNode(ISD::BIT_CONVERT, getCurDebugLoc(),
4949 RegVT, OpInfo.CallOperand);
4950 OpInfo.ConstraintVT = RegVT;
4951 } else if (RegVT.isInteger() && OpInfo.ConstraintVT.isFloatingPoint()) {
4952 // If the input is a FP value and we want it in FP registers, do a
4953 // bitcast to the corresponding integer type. This turns an f64 value
4954 // into i64, which can be passed with two i32 values on a 32-bit
4956 RegVT = EVT::getIntegerVT(Context,
4957 OpInfo.ConstraintVT.getSizeInBits());
4958 OpInfo.CallOperand = DAG.getNode(ISD::BIT_CONVERT, getCurDebugLoc(),
4959 RegVT, OpInfo.CallOperand);
4960 OpInfo.ConstraintVT = RegVT;
4964 NumRegs = TLI.getNumRegisters(Context, OpInfo.ConstraintVT);
4968 EVT ValueVT = OpInfo.ConstraintVT;
4970 // If this is a constraint for a specific physical register, like {r17},
4972 if (unsigned AssignedReg = PhysReg.first) {
4973 const TargetRegisterClass *RC = PhysReg.second;
4974 if (OpInfo.ConstraintVT == MVT::Other)
4975 ValueVT = *RC->vt_begin();
4977 // Get the actual register value type. This is important, because the user
4978 // may have asked for (e.g.) the AX register in i32 type. We need to
4979 // remember that AX is actually i16 to get the right extension.
4980 RegVT = *RC->vt_begin();
4982 // This is a explicit reference to a physical register.
4983 Regs.push_back(AssignedReg);
4985 // If this is an expanded reference, add the rest of the regs to Regs.
4987 TargetRegisterClass::iterator I = RC->begin();
4988 for (; *I != AssignedReg; ++I)
4989 assert(I != RC->end() && "Didn't find reg!");
4991 // Already added the first reg.
4993 for (; NumRegs; --NumRegs, ++I) {
4994 assert(I != RC->end() && "Ran out of registers to allocate!");
4998 OpInfo.AssignedRegs = RegsForValue(TLI, Regs, RegVT, ValueVT);
4999 const TargetRegisterInfo *TRI = DAG.getTarget().getRegisterInfo();
5000 OpInfo.MarkAllocatedRegs(isOutReg, isInReg, OutputRegs, InputRegs, *TRI);
5004 // Otherwise, if this was a reference to an LLVM register class, create vregs
5005 // for this reference.
5006 if (const TargetRegisterClass *RC = PhysReg.second) {
5007 RegVT = *RC->vt_begin();
5008 if (OpInfo.ConstraintVT == MVT::Other)
5011 // Create the appropriate number of virtual registers.
5012 MachineRegisterInfo &RegInfo = MF.getRegInfo();
5013 for (; NumRegs; --NumRegs)
5014 Regs.push_back(RegInfo.createVirtualRegister(RC));
5016 OpInfo.AssignedRegs = RegsForValue(TLI, Regs, RegVT, ValueVT);
5020 // This is a reference to a register class that doesn't directly correspond
5021 // to an LLVM register class. Allocate NumRegs consecutive, available,
5022 // registers from the class.
5023 std::vector<unsigned> RegClassRegs
5024 = TLI.getRegClassForInlineAsmConstraint(OpInfo.ConstraintCode,
5025 OpInfo.ConstraintVT);
5027 const TargetRegisterInfo *TRI = DAG.getTarget().getRegisterInfo();
5028 unsigned NumAllocated = 0;
5029 for (unsigned i = 0, e = RegClassRegs.size(); i != e; ++i) {
5030 unsigned Reg = RegClassRegs[i];
5031 // See if this register is available.
5032 if ((isOutReg && OutputRegs.count(Reg)) || // Already used.
5033 (isInReg && InputRegs.count(Reg))) { // Already used.
5034 // Make sure we find consecutive registers.
5039 // Check to see if this register is allocatable (i.e. don't give out the
5041 const TargetRegisterClass *RC = isAllocatableRegister(Reg, MF, TLI, TRI);
5042 if (!RC) { // Couldn't allocate this register.
5043 // Reset NumAllocated to make sure we return consecutive registers.
5048 // Okay, this register is good, we can use it.
5051 // If we allocated enough consecutive registers, succeed.
5052 if (NumAllocated == NumRegs) {
5053 unsigned RegStart = (i-NumAllocated)+1;
5054 unsigned RegEnd = i+1;
5055 // Mark all of the allocated registers used.
5056 for (unsigned i = RegStart; i != RegEnd; ++i)
5057 Regs.push_back(RegClassRegs[i]);
5059 OpInfo.AssignedRegs = RegsForValue(TLI, Regs, *RC->vt_begin(),
5060 OpInfo.ConstraintVT);
5061 OpInfo.MarkAllocatedRegs(isOutReg, isInReg, OutputRegs, InputRegs, *TRI);
5066 // Otherwise, we couldn't allocate enough registers for this.
5069 /// hasInlineAsmMemConstraint - Return true if the inline asm instruction being
5070 /// processed uses a memory 'm' constraint.
5072 hasInlineAsmMemConstraint(std::vector<InlineAsm::ConstraintInfo> &CInfos,
5073 const TargetLowering &TLI) {
5074 for (unsigned i = 0, e = CInfos.size(); i != e; ++i) {
5075 InlineAsm::ConstraintInfo &CI = CInfos[i];
5076 for (unsigned j = 0, ee = CI.Codes.size(); j != ee; ++j) {
5077 TargetLowering::ConstraintType CType = TLI.getConstraintType(CI.Codes[j]);
5078 if (CType == TargetLowering::C_Memory)
5082 // Indirect operand accesses access memory.
5090 /// visitInlineAsm - Handle a call to an InlineAsm object.
5092 void SelectionDAGLowering::visitInlineAsm(CallSite CS) {
5093 InlineAsm *IA = cast<InlineAsm>(CS.getCalledValue());
5095 /// ConstraintOperands - Information about all of the constraints.
5096 std::vector<SDISelAsmOperandInfo> ConstraintOperands;
5098 std::set<unsigned> OutputRegs, InputRegs;
5100 // Do a prepass over the constraints, canonicalizing them, and building up the
5101 // ConstraintOperands list.
5102 std::vector<InlineAsm::ConstraintInfo>
5103 ConstraintInfos = IA->ParseConstraints();
5105 bool hasMemory = hasInlineAsmMemConstraint(ConstraintInfos, TLI);
5107 SDValue Chain, Flag;
5109 // We won't need to flush pending loads if this asm doesn't touch
5110 // memory and is nonvolatile.
5111 if (hasMemory || IA->hasSideEffects())
5114 Chain = DAG.getRoot();
5116 unsigned ArgNo = 0; // ArgNo - The argument of the CallInst.
5117 unsigned ResNo = 0; // ResNo - The result number of the next output.
5118 for (unsigned i = 0, e = ConstraintInfos.size(); i != e; ++i) {
5119 ConstraintOperands.push_back(SDISelAsmOperandInfo(ConstraintInfos[i]));
5120 SDISelAsmOperandInfo &OpInfo = ConstraintOperands.back();
5122 EVT OpVT = MVT::Other;
5124 // Compute the value type for each operand.
5125 switch (OpInfo.Type) {
5126 case InlineAsm::isOutput:
5127 // Indirect outputs just consume an argument.
5128 if (OpInfo.isIndirect) {
5129 OpInfo.CallOperandVal = CS.getArgument(ArgNo++);
5133 // The return value of the call is this value. As such, there is no
5134 // corresponding argument.
5135 assert(CS.getType() != Type::getVoidTy(*DAG.getContext()) &&
5137 if (const StructType *STy = dyn_cast<StructType>(CS.getType())) {
5138 OpVT = TLI.getValueType(STy->getElementType(ResNo));
5140 assert(ResNo == 0 && "Asm only has one result!");
5141 OpVT = TLI.getValueType(CS.getType());
5145 case InlineAsm::isInput:
5146 OpInfo.CallOperandVal = CS.getArgument(ArgNo++);
5148 case InlineAsm::isClobber:
5153 // If this is an input or an indirect output, process the call argument.
5154 // BasicBlocks are labels, currently appearing only in asm's.
5155 if (OpInfo.CallOperandVal) {
5156 // Strip bitcasts, if any. This mostly comes up for functions.
5157 OpInfo.CallOperandVal = OpInfo.CallOperandVal->stripPointerCasts();
5159 if (BasicBlock *BB = dyn_cast<BasicBlock>(OpInfo.CallOperandVal)) {
5160 OpInfo.CallOperand = DAG.getBasicBlock(FuncInfo.MBBMap[BB]);
5162 OpInfo.CallOperand = getValue(OpInfo.CallOperandVal);
5165 OpVT = OpInfo.getCallOperandValEVT(*DAG.getContext(), TLI, TD);
5168 OpInfo.ConstraintVT = OpVT;
5171 // Second pass over the constraints: compute which constraint option to use
5172 // and assign registers to constraints that want a specific physreg.
5173 for (unsigned i = 0, e = ConstraintInfos.size(); i != e; ++i) {
5174 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
5176 // If this is an output operand with a matching input operand, look up the
5177 // matching input. If their types mismatch, e.g. one is an integer, the
5178 // other is floating point, or their sizes are different, flag it as an
5180 if (OpInfo.hasMatchingInput()) {
5181 SDISelAsmOperandInfo &Input = ConstraintOperands[OpInfo.MatchingInput];
5182 if (OpInfo.ConstraintVT != Input.ConstraintVT) {
5183 if ((OpInfo.ConstraintVT.isInteger() !=
5184 Input.ConstraintVT.isInteger()) ||
5185 (OpInfo.ConstraintVT.getSizeInBits() !=
5186 Input.ConstraintVT.getSizeInBits())) {
5187 llvm_report_error("Unsupported asm: input constraint"
5188 " with a matching output constraint of incompatible"
5191 Input.ConstraintVT = OpInfo.ConstraintVT;
5195 // Compute the constraint code and ConstraintType to use.
5196 TLI.ComputeConstraintToUse(OpInfo, OpInfo.CallOperand, hasMemory, &DAG);
5198 // If this is a memory input, and if the operand is not indirect, do what we
5199 // need to to provide an address for the memory input.
5200 if (OpInfo.ConstraintType == TargetLowering::C_Memory &&
5201 !OpInfo.isIndirect) {
5202 assert(OpInfo.Type == InlineAsm::isInput &&
5203 "Can only indirectify direct input operands!");
5205 // Memory operands really want the address of the value. If we don't have
5206 // an indirect input, put it in the constpool if we can, otherwise spill
5207 // it to a stack slot.
5209 // If the operand is a float, integer, or vector constant, spill to a
5210 // constant pool entry to get its address.
5211 Value *OpVal = OpInfo.CallOperandVal;
5212 if (isa<ConstantFP>(OpVal) || isa<ConstantInt>(OpVal) ||
5213 isa<ConstantVector>(OpVal)) {
5214 OpInfo.CallOperand = DAG.getConstantPool(cast<Constant>(OpVal),
5215 TLI.getPointerTy());
5217 // Otherwise, create a stack slot and emit a store to it before the
5219 const Type *Ty = OpVal->getType();
5220 uint64_t TySize = TLI.getTargetData()->getTypeAllocSize(Ty);
5221 unsigned Align = TLI.getTargetData()->getPrefTypeAlignment(Ty);
5222 MachineFunction &MF = DAG.getMachineFunction();
5223 int SSFI = MF.getFrameInfo()->CreateStackObject(TySize, Align);
5224 SDValue StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy());
5225 Chain = DAG.getStore(Chain, getCurDebugLoc(),
5226 OpInfo.CallOperand, StackSlot, NULL, 0);
5227 OpInfo.CallOperand = StackSlot;
5230 // There is no longer a Value* corresponding to this operand.
5231 OpInfo.CallOperandVal = 0;
5232 // It is now an indirect operand.
5233 OpInfo.isIndirect = true;
5236 // If this constraint is for a specific register, allocate it before
5238 if (OpInfo.ConstraintType == TargetLowering::C_Register)
5239 GetRegistersForValue(OpInfo, OutputRegs, InputRegs);
5241 ConstraintInfos.clear();
5244 // Second pass - Loop over all of the operands, assigning virtual or physregs
5245 // to register class operands.
5246 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
5247 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
5249 // C_Register operands have already been allocated, Other/Memory don't need
5251 if (OpInfo.ConstraintType == TargetLowering::C_RegisterClass)
5252 GetRegistersForValue(OpInfo, OutputRegs, InputRegs);
5255 // AsmNodeOperands - The operands for the ISD::INLINEASM node.
5256 std::vector<SDValue> AsmNodeOperands;
5257 AsmNodeOperands.push_back(SDValue()); // reserve space for input chain
5258 AsmNodeOperands.push_back(
5259 DAG.getTargetExternalSymbol(IA->getAsmString().c_str(), MVT::Other));
5262 // Loop over all of the inputs, copying the operand values into the
5263 // appropriate registers and processing the output regs.
5264 RegsForValue RetValRegs;
5266 // IndirectStoresToEmit - The set of stores to emit after the inline asm node.
5267 std::vector<std::pair<RegsForValue, Value*> > IndirectStoresToEmit;
5269 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
5270 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
5272 switch (OpInfo.Type) {
5273 case InlineAsm::isOutput: {
5274 if (OpInfo.ConstraintType != TargetLowering::C_RegisterClass &&
5275 OpInfo.ConstraintType != TargetLowering::C_Register) {
5276 // Memory output, or 'other' output (e.g. 'X' constraint).
5277 assert(OpInfo.isIndirect && "Memory output must be indirect operand");
5279 // Add information to the INLINEASM node to know about this output.
5280 unsigned ResOpType = 4/*MEM*/ | (1<<3);
5281 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
5282 TLI.getPointerTy()));
5283 AsmNodeOperands.push_back(OpInfo.CallOperand);
5287 // Otherwise, this is a register or register class output.
5289 // Copy the output from the appropriate register. Find a register that
5291 if (OpInfo.AssignedRegs.Regs.empty()) {
5292 llvm_report_error("Couldn't allocate output reg for"
5293 " constraint '" + OpInfo.ConstraintCode + "'!");
5296 // If this is an indirect operand, store through the pointer after the
5298 if (OpInfo.isIndirect) {
5299 IndirectStoresToEmit.push_back(std::make_pair(OpInfo.AssignedRegs,
5300 OpInfo.CallOperandVal));
5302 // This is the result value of the call.
5303 assert(CS.getType() != Type::getVoidTy(*DAG.getContext()) &&
5305 // Concatenate this output onto the outputs list.
5306 RetValRegs.append(OpInfo.AssignedRegs);
5309 // Add information to the INLINEASM node to know that this register is
5311 OpInfo.AssignedRegs.AddInlineAsmOperands(OpInfo.isEarlyClobber ?
5312 6 /* EARLYCLOBBER REGDEF */ :
5316 DAG, AsmNodeOperands);
5319 case InlineAsm::isInput: {
5320 SDValue InOperandVal = OpInfo.CallOperand;
5322 if (OpInfo.isMatchingInputConstraint()) { // Matching constraint?
5323 // If this is required to match an output register we have already set,
5324 // just use its register.
5325 unsigned OperandNo = OpInfo.getMatchedOperand();
5327 // Scan until we find the definition we already emitted of this operand.
5328 // When we find it, create a RegsForValue operand.
5329 unsigned CurOp = 2; // The first operand.
5330 for (; OperandNo; --OperandNo) {
5331 // Advance to the next operand.
5333 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue();
5334 assert(((OpFlag & 7) == 2 /*REGDEF*/ ||
5335 (OpFlag & 7) == 6 /*EARLYCLOBBER REGDEF*/ ||
5336 (OpFlag & 7) == 4 /*MEM*/) &&
5337 "Skipped past definitions?");
5338 CurOp += InlineAsm::getNumOperandRegisters(OpFlag)+1;
5342 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue();
5343 if ((OpFlag & 7) == 2 /*REGDEF*/
5344 || (OpFlag & 7) == 6 /* EARLYCLOBBER REGDEF */) {
5345 // Add (OpFlag&0xffff)>>3 registers to MatchedRegs.
5346 if (OpInfo.isIndirect) {
5347 llvm_report_error("Don't know how to handle tied indirect "
5348 "register inputs yet!");
5350 RegsForValue MatchedRegs;
5351 MatchedRegs.TLI = &TLI;
5352 MatchedRegs.ValueVTs.push_back(InOperandVal.getValueType());
5353 EVT RegVT = AsmNodeOperands[CurOp+1].getValueType();
5354 MatchedRegs.RegVTs.push_back(RegVT);
5355 MachineRegisterInfo &RegInfo = DAG.getMachineFunction().getRegInfo();
5356 for (unsigned i = 0, e = InlineAsm::getNumOperandRegisters(OpFlag);
5359 push_back(RegInfo.createVirtualRegister(TLI.getRegClassFor(RegVT)));
5361 // Use the produced MatchedRegs object to
5362 MatchedRegs.getCopyToRegs(InOperandVal, DAG, getCurDebugLoc(),
5364 MatchedRegs.AddInlineAsmOperands(1 /*REGUSE*/,
5365 true, OpInfo.getMatchedOperand(),
5366 DAG, AsmNodeOperands);
5369 assert(((OpFlag & 7) == 4) && "Unknown matching constraint!");
5370 assert((InlineAsm::getNumOperandRegisters(OpFlag)) == 1 &&
5371 "Unexpected number of operands");
5372 // Add information to the INLINEASM node to know about this input.
5373 // See InlineAsm.h isUseOperandTiedToDef.
5374 OpFlag |= 0x80000000 | (OpInfo.getMatchedOperand() << 16);
5375 AsmNodeOperands.push_back(DAG.getTargetConstant(OpFlag,
5376 TLI.getPointerTy()));
5377 AsmNodeOperands.push_back(AsmNodeOperands[CurOp+1]);
5382 if (OpInfo.ConstraintType == TargetLowering::C_Other) {
5383 assert(!OpInfo.isIndirect &&
5384 "Don't know how to handle indirect other inputs yet!");
5386 std::vector<SDValue> Ops;
5387 TLI.LowerAsmOperandForConstraint(InOperandVal, OpInfo.ConstraintCode[0],
5388 hasMemory, Ops, DAG);
5390 llvm_report_error("Invalid operand for inline asm"
5391 " constraint '" + OpInfo.ConstraintCode + "'!");
5394 // Add information to the INLINEASM node to know about this input.
5395 unsigned ResOpType = 3 /*IMM*/ | (Ops.size() << 3);
5396 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
5397 TLI.getPointerTy()));
5398 AsmNodeOperands.insert(AsmNodeOperands.end(), Ops.begin(), Ops.end());
5400 } else if (OpInfo.ConstraintType == TargetLowering::C_Memory) {
5401 assert(OpInfo.isIndirect && "Operand must be indirect to be a mem!");
5402 assert(InOperandVal.getValueType() == TLI.getPointerTy() &&
5403 "Memory operands expect pointer values");
5405 // Add information to the INLINEASM node to know about this input.
5406 unsigned ResOpType = 4/*MEM*/ | (1<<3);
5407 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
5408 TLI.getPointerTy()));
5409 AsmNodeOperands.push_back(InOperandVal);
5413 assert((OpInfo.ConstraintType == TargetLowering::C_RegisterClass ||
5414 OpInfo.ConstraintType == TargetLowering::C_Register) &&
5415 "Unknown constraint type!");
5416 assert(!OpInfo.isIndirect &&
5417 "Don't know how to handle indirect register inputs yet!");
5419 // Copy the input into the appropriate registers.
5420 if (OpInfo.AssignedRegs.Regs.empty()) {
5421 llvm_report_error("Couldn't allocate input reg for"
5422 " constraint '"+ OpInfo.ConstraintCode +"'!");
5425 OpInfo.AssignedRegs.getCopyToRegs(InOperandVal, DAG, getCurDebugLoc(),
5428 OpInfo.AssignedRegs.AddInlineAsmOperands(1/*REGUSE*/, false, 0,
5429 DAG, AsmNodeOperands);
5432 case InlineAsm::isClobber: {
5433 // Add the clobbered value to the operand list, so that the register
5434 // allocator is aware that the physreg got clobbered.
5435 if (!OpInfo.AssignedRegs.Regs.empty())
5436 OpInfo.AssignedRegs.AddInlineAsmOperands(6 /* EARLYCLOBBER REGDEF */,
5437 false, 0, DAG,AsmNodeOperands);
5443 // Finish up input operands.
5444 AsmNodeOperands[0] = Chain;
5445 if (Flag.getNode()) AsmNodeOperands.push_back(Flag);
5447 Chain = DAG.getNode(ISD::INLINEASM, getCurDebugLoc(),
5448 DAG.getVTList(MVT::Other, MVT::Flag),
5449 &AsmNodeOperands[0], AsmNodeOperands.size());
5450 Flag = Chain.getValue(1);
5452 // If this asm returns a register value, copy the result from that register
5453 // and set it as the value of the call.
5454 if (!RetValRegs.Regs.empty()) {
5455 SDValue Val = RetValRegs.getCopyFromRegs(DAG, getCurDebugLoc(),
5458 // FIXME: Why don't we do this for inline asms with MRVs?
5459 if (CS.getType()->isSingleValueType() && CS.getType()->isSized()) {
5460 EVT ResultType = TLI.getValueType(CS.getType());
5462 // If any of the results of the inline asm is a vector, it may have the
5463 // wrong width/num elts. This can happen for register classes that can
5464 // contain multiple different value types. The preg or vreg allocated may
5465 // not have the same VT as was expected. Convert it to the right type
5466 // with bit_convert.
5467 if (ResultType != Val.getValueType() && Val.getValueType().isVector()) {
5468 Val = DAG.getNode(ISD::BIT_CONVERT, getCurDebugLoc(),
5471 } else if (ResultType != Val.getValueType() &&
5472 ResultType.isInteger() && Val.getValueType().isInteger()) {
5473 // If a result value was tied to an input value, the computed result may
5474 // have a wider width than the expected result. Extract the relevant
5476 Val = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), ResultType, Val);
5479 assert(ResultType == Val.getValueType() && "Asm result value mismatch!");
5482 setValue(CS.getInstruction(), Val);
5483 // Don't need to use this as a chain in this case.
5484 if (!IA->hasSideEffects() && !hasMemory && IndirectStoresToEmit.empty())
5488 std::vector<std::pair<SDValue, Value*> > StoresToEmit;
5490 // Process indirect outputs, first output all of the flagged copies out of
5492 for (unsigned i = 0, e = IndirectStoresToEmit.size(); i != e; ++i) {
5493 RegsForValue &OutRegs = IndirectStoresToEmit[i].first;
5494 Value *Ptr = IndirectStoresToEmit[i].second;
5495 SDValue OutVal = OutRegs.getCopyFromRegs(DAG, getCurDebugLoc(),
5497 StoresToEmit.push_back(std::make_pair(OutVal, Ptr));
5501 // Emit the non-flagged stores from the physregs.
5502 SmallVector<SDValue, 8> OutChains;
5503 for (unsigned i = 0, e = StoresToEmit.size(); i != e; ++i)
5504 OutChains.push_back(DAG.getStore(Chain, getCurDebugLoc(),
5505 StoresToEmit[i].first,
5506 getValue(StoresToEmit[i].second),
5507 StoresToEmit[i].second, 0));
5508 if (!OutChains.empty())
5509 Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), MVT::Other,
5510 &OutChains[0], OutChains.size());
5514 void SelectionDAGLowering::visitVAStart(CallInst &I) {
5515 DAG.setRoot(DAG.getNode(ISD::VASTART, getCurDebugLoc(),
5516 MVT::Other, getRoot(),
5517 getValue(I.getOperand(1)),
5518 DAG.getSrcValue(I.getOperand(1))));
5521 void SelectionDAGLowering::visitVAArg(VAArgInst &I) {
5522 SDValue V = DAG.getVAArg(TLI.getValueType(I.getType()), getCurDebugLoc(),
5523 getRoot(), getValue(I.getOperand(0)),
5524 DAG.getSrcValue(I.getOperand(0)));
5526 DAG.setRoot(V.getValue(1));
5529 void SelectionDAGLowering::visitVAEnd(CallInst &I) {
5530 DAG.setRoot(DAG.getNode(ISD::VAEND, getCurDebugLoc(),
5531 MVT::Other, getRoot(),
5532 getValue(I.getOperand(1)),
5533 DAG.getSrcValue(I.getOperand(1))));
5536 void SelectionDAGLowering::visitVACopy(CallInst &I) {
5537 DAG.setRoot(DAG.getNode(ISD::VACOPY, getCurDebugLoc(),
5538 MVT::Other, getRoot(),
5539 getValue(I.getOperand(1)),
5540 getValue(I.getOperand(2)),
5541 DAG.getSrcValue(I.getOperand(1)),
5542 DAG.getSrcValue(I.getOperand(2))));
5545 /// TargetLowering::LowerCallTo - This is the default LowerCallTo
5546 /// implementation, which just calls LowerCall.
5547 /// FIXME: When all targets are
5548 /// migrated to using LowerCall, this hook should be integrated into SDISel.
5549 std::pair<SDValue, SDValue>
5550 TargetLowering::LowerCallTo(SDValue Chain, const Type *RetTy,
5551 bool RetSExt, bool RetZExt, bool isVarArg,
5552 bool isInreg, unsigned NumFixedArgs,
5553 CallingConv::ID CallConv, bool isTailCall,
5554 bool isReturnValueUsed,
5556 ArgListTy &Args, SelectionDAG &DAG, DebugLoc dl) {
5558 assert((!isTailCall || PerformTailCallOpt) &&
5559 "isTailCall set when tail-call optimizations are disabled!");
5561 // Handle all of the outgoing arguments.
5562 SmallVector<ISD::OutputArg, 32> Outs;
5563 for (unsigned i = 0, e = Args.size(); i != e; ++i) {
5564 SmallVector<EVT, 4> ValueVTs;
5565 ComputeValueVTs(*this, Args[i].Ty, ValueVTs);
5566 for (unsigned Value = 0, NumValues = ValueVTs.size();
5567 Value != NumValues; ++Value) {
5568 EVT VT = ValueVTs[Value];
5569 const Type *ArgTy = VT.getTypeForEVT(RetTy->getContext());
5570 SDValue Op = SDValue(Args[i].Node.getNode(),
5571 Args[i].Node.getResNo() + Value);
5572 ISD::ArgFlagsTy Flags;
5573 unsigned OriginalAlignment =
5574 getTargetData()->getABITypeAlignment(ArgTy);
5580 if (Args[i].isInReg)
5584 if (Args[i].isByVal) {
5586 const PointerType *Ty = cast<PointerType>(Args[i].Ty);
5587 const Type *ElementTy = Ty->getElementType();
5588 unsigned FrameAlign = getByValTypeAlignment(ElementTy);
5589 unsigned FrameSize = getTargetData()->getTypeAllocSize(ElementTy);
5590 // For ByVal, alignment should come from FE. BE will guess if this
5591 // info is not there but there are cases it cannot get right.
5592 if (Args[i].Alignment)
5593 FrameAlign = Args[i].Alignment;
5594 Flags.setByValAlign(FrameAlign);
5595 Flags.setByValSize(FrameSize);
5599 Flags.setOrigAlign(OriginalAlignment);
5601 EVT PartVT = getRegisterType(RetTy->getContext(), VT);
5602 unsigned NumParts = getNumRegisters(RetTy->getContext(), VT);
5603 SmallVector<SDValue, 4> Parts(NumParts);
5604 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
5607 ExtendKind = ISD::SIGN_EXTEND;
5608 else if (Args[i].isZExt)
5609 ExtendKind = ISD::ZERO_EXTEND;
5611 getCopyToParts(DAG, dl, Op, &Parts[0], NumParts, PartVT, ExtendKind);
5613 for (unsigned j = 0; j != NumParts; ++j) {
5614 // if it isn't first piece, alignment must be 1
5615 ISD::OutputArg MyFlags(Flags, Parts[j], i < NumFixedArgs);
5616 if (NumParts > 1 && j == 0)
5617 MyFlags.Flags.setSplit();
5619 MyFlags.Flags.setOrigAlign(1);
5621 Outs.push_back(MyFlags);
5626 // Handle the incoming return values from the call.
5627 SmallVector<ISD::InputArg, 32> Ins;
5628 SmallVector<EVT, 4> RetTys;
5629 ComputeValueVTs(*this, RetTy, RetTys);
5630 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
5632 EVT RegisterVT = getRegisterType(RetTy->getContext(), VT);
5633 unsigned NumRegs = getNumRegisters(RetTy->getContext(), VT);
5634 for (unsigned i = 0; i != NumRegs; ++i) {
5635 ISD::InputArg MyFlags;
5636 MyFlags.VT = RegisterVT;
5637 MyFlags.Used = isReturnValueUsed;
5639 MyFlags.Flags.setSExt();
5641 MyFlags.Flags.setZExt();
5643 MyFlags.Flags.setInReg();
5644 Ins.push_back(MyFlags);
5648 // Check if target-dependent constraints permit a tail call here.
5649 // Target-independent constraints should be checked by the caller.
5651 !IsEligibleForTailCallOptimization(Callee, CallConv, isVarArg, Ins, DAG))
5654 SmallVector<SDValue, 4> InVals;
5655 Chain = LowerCall(Chain, Callee, CallConv, isVarArg, isTailCall,
5656 Outs, Ins, dl, DAG, InVals);
5658 // Verify that the target's LowerCall behaved as expected.
5659 assert(Chain.getNode() && Chain.getValueType() == MVT::Other &&
5660 "LowerCall didn't return a valid chain!");
5661 assert((!isTailCall || InVals.empty()) &&
5662 "LowerCall emitted a return value for a tail call!");
5663 assert((isTailCall || InVals.size() == Ins.size()) &&
5664 "LowerCall didn't emit the correct number of values!");
5665 DEBUG(for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
5666 assert(InVals[i].getNode() &&
5667 "LowerCall emitted a null value!");
5668 assert(Ins[i].VT == InVals[i].getValueType() &&
5669 "LowerCall emitted a value with the wrong type!");
5672 // For a tail call, the return value is merely live-out and there aren't
5673 // any nodes in the DAG representing it. Return a special value to
5674 // indicate that a tail call has been emitted and no more Instructions
5675 // should be processed in the current block.
5678 return std::make_pair(SDValue(), SDValue());
5681 // Collect the legal value parts into potentially illegal values
5682 // that correspond to the original function's return values.
5683 ISD::NodeType AssertOp = ISD::DELETED_NODE;
5685 AssertOp = ISD::AssertSext;
5687 AssertOp = ISD::AssertZext;
5688 SmallVector<SDValue, 4> ReturnValues;
5689 unsigned CurReg = 0;
5690 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
5692 EVT RegisterVT = getRegisterType(RetTy->getContext(), VT);
5693 unsigned NumRegs = getNumRegisters(RetTy->getContext(), VT);
5695 SDValue ReturnValue =
5696 getCopyFromParts(DAG, dl, &InVals[CurReg], NumRegs, RegisterVT, VT,
5698 ReturnValues.push_back(ReturnValue);
5702 // For a function returning void, there is no return value. We can't create
5703 // such a node, so we just return a null return value in that case. In
5704 // that case, nothing will actualy look at the value.
5705 if (ReturnValues.empty())
5706 return std::make_pair(SDValue(), Chain);
5708 SDValue Res = DAG.getNode(ISD::MERGE_VALUES, dl,
5709 DAG.getVTList(&RetTys[0], RetTys.size()),
5710 &ReturnValues[0], ReturnValues.size());
5712 return std::make_pair(Res, Chain);
5715 void TargetLowering::LowerOperationWrapper(SDNode *N,
5716 SmallVectorImpl<SDValue> &Results,
5717 SelectionDAG &DAG) {
5718 SDValue Res = LowerOperation(SDValue(N, 0), DAG);
5720 Results.push_back(Res);
5723 SDValue TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) {
5724 llvm_unreachable("LowerOperation not implemented for this target!");
5729 void SelectionDAGLowering::CopyValueToVirtualRegister(Value *V, unsigned Reg) {
5730 SDValue Op = getValue(V);
5731 assert((Op.getOpcode() != ISD::CopyFromReg ||
5732 cast<RegisterSDNode>(Op.getOperand(1))->getReg() != Reg) &&
5733 "Copy from a reg to the same reg!");
5734 assert(!TargetRegisterInfo::isPhysicalRegister(Reg) && "Is a physreg");
5736 RegsForValue RFV(V->getContext(), TLI, Reg, V->getType());
5737 SDValue Chain = DAG.getEntryNode();
5738 RFV.getCopyToRegs(Op, DAG, getCurDebugLoc(), Chain, 0);
5739 PendingExports.push_back(Chain);
5742 #include "llvm/CodeGen/SelectionDAGISel.h"
5744 void SelectionDAGISel::
5745 LowerArguments(BasicBlock *LLVMBB) {
5746 // If this is the entry block, emit arguments.
5747 Function &F = *LLVMBB->getParent();
5748 SelectionDAG &DAG = SDL->DAG;
5749 SDValue OldRoot = DAG.getRoot();
5750 DebugLoc dl = SDL->getCurDebugLoc();
5751 const TargetData *TD = TLI.getTargetData();
5753 // Set up the incoming argument description vector.
5754 SmallVector<ISD::InputArg, 16> Ins;
5756 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end();
5757 I != E; ++I, ++Idx) {
5758 SmallVector<EVT, 4> ValueVTs;
5759 ComputeValueVTs(TLI, I->getType(), ValueVTs);
5760 bool isArgValueUsed = !I->use_empty();
5761 for (unsigned Value = 0, NumValues = ValueVTs.size();
5762 Value != NumValues; ++Value) {
5763 EVT VT = ValueVTs[Value];
5764 const Type *ArgTy = VT.getTypeForEVT(*DAG.getContext());
5765 ISD::ArgFlagsTy Flags;
5766 unsigned OriginalAlignment =
5767 TD->getABITypeAlignment(ArgTy);
5769 if (F.paramHasAttr(Idx, Attribute::ZExt))
5771 if (F.paramHasAttr(Idx, Attribute::SExt))
5773 if (F.paramHasAttr(Idx, Attribute::InReg))
5775 if (F.paramHasAttr(Idx, Attribute::StructRet))
5777 if (F.paramHasAttr(Idx, Attribute::ByVal)) {
5779 const PointerType *Ty = cast<PointerType>(I->getType());
5780 const Type *ElementTy = Ty->getElementType();
5781 unsigned FrameAlign = TLI.getByValTypeAlignment(ElementTy);
5782 unsigned FrameSize = TD->getTypeAllocSize(ElementTy);
5783 // For ByVal, alignment should be passed from FE. BE will guess if
5784 // this info is not there but there are cases it cannot get right.
5785 if (F.getParamAlignment(Idx))
5786 FrameAlign = F.getParamAlignment(Idx);
5787 Flags.setByValAlign(FrameAlign);
5788 Flags.setByValSize(FrameSize);
5790 if (F.paramHasAttr(Idx, Attribute::Nest))
5792 Flags.setOrigAlign(OriginalAlignment);
5794 EVT RegisterVT = TLI.getRegisterType(*CurDAG->getContext(), VT);
5795 unsigned NumRegs = TLI.getNumRegisters(*CurDAG->getContext(), VT);
5796 for (unsigned i = 0; i != NumRegs; ++i) {
5797 ISD::InputArg MyFlags(Flags, RegisterVT, isArgValueUsed);
5798 if (NumRegs > 1 && i == 0)
5799 MyFlags.Flags.setSplit();
5800 // if it isn't first piece, alignment must be 1
5802 MyFlags.Flags.setOrigAlign(1);
5803 Ins.push_back(MyFlags);
5808 // Call the target to set up the argument values.
5809 SmallVector<SDValue, 8> InVals;
5810 SDValue NewRoot = TLI.LowerFormalArguments(DAG.getRoot(), F.getCallingConv(),
5814 // Verify that the target's LowerFormalArguments behaved as expected.
5815 assert(NewRoot.getNode() && NewRoot.getValueType() == MVT::Other &&
5816 "LowerFormalArguments didn't return a valid chain!");
5817 assert(InVals.size() == Ins.size() &&
5818 "LowerFormalArguments didn't emit the correct number of values!");
5819 DEBUG(for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
5820 assert(InVals[i].getNode() &&
5821 "LowerFormalArguments emitted a null value!");
5822 assert(Ins[i].VT == InVals[i].getValueType() &&
5823 "LowerFormalArguments emitted a value with the wrong type!");
5826 // Update the DAG with the new chain value resulting from argument lowering.
5827 DAG.setRoot(NewRoot);
5829 // Set up the argument values.
5832 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E;
5834 SmallVector<SDValue, 4> ArgValues;
5835 SmallVector<EVT, 4> ValueVTs;
5836 ComputeValueVTs(TLI, I->getType(), ValueVTs);
5837 unsigned NumValues = ValueVTs.size();
5838 for (unsigned Value = 0; Value != NumValues; ++Value) {
5839 EVT VT = ValueVTs[Value];
5840 EVT PartVT = TLI.getRegisterType(*CurDAG->getContext(), VT);
5841 unsigned NumParts = TLI.getNumRegisters(*CurDAG->getContext(), VT);
5843 if (!I->use_empty()) {
5844 ISD::NodeType AssertOp = ISD::DELETED_NODE;
5845 if (F.paramHasAttr(Idx, Attribute::SExt))
5846 AssertOp = ISD::AssertSext;
5847 else if (F.paramHasAttr(Idx, Attribute::ZExt))
5848 AssertOp = ISD::AssertZext;
5850 ArgValues.push_back(getCopyFromParts(DAG, dl, &InVals[i], NumParts,
5851 PartVT, VT, AssertOp));
5855 if (!I->use_empty()) {
5856 SDL->setValue(I, DAG.getMergeValues(&ArgValues[0], NumValues,
5857 SDL->getCurDebugLoc()));
5858 // If this argument is live outside of the entry block, insert a copy from
5859 // whereever we got it to the vreg that other BB's will reference it as.
5860 SDL->CopyToExportRegsIfNeeded(I);
5863 assert(i == InVals.size() && "Argument register count mismatch!");
5865 // Finally, if the target has anything special to do, allow it to do so.
5866 // FIXME: this should insert code into the DAG!
5867 EmitFunctionEntryCode(F, SDL->DAG.getMachineFunction());
5870 /// Handle PHI nodes in successor blocks. Emit code into the SelectionDAG to
5871 /// ensure constants are generated when needed. Remember the virtual registers
5872 /// that need to be added to the Machine PHI nodes as input. We cannot just
5873 /// directly add them, because expansion might result in multiple MBB's for one
5874 /// BB. As such, the start of the BB might correspond to a different MBB than
5878 SelectionDAGISel::HandlePHINodesInSuccessorBlocks(BasicBlock *LLVMBB) {
5879 TerminatorInst *TI = LLVMBB->getTerminator();
5881 SmallPtrSet<MachineBasicBlock *, 4> SuccsHandled;
5883 // Check successor nodes' PHI nodes that expect a constant to be available
5885 for (unsigned succ = 0, e = TI->getNumSuccessors(); succ != e; ++succ) {
5886 BasicBlock *SuccBB = TI->getSuccessor(succ);
5887 if (!isa<PHINode>(SuccBB->begin())) continue;
5888 MachineBasicBlock *SuccMBB = FuncInfo->MBBMap[SuccBB];
5890 // If this terminator has multiple identical successors (common for
5891 // switches), only handle each succ once.
5892 if (!SuccsHandled.insert(SuccMBB)) continue;
5894 MachineBasicBlock::iterator MBBI = SuccMBB->begin();
5897 // At this point we know that there is a 1-1 correspondence between LLVM PHI
5898 // nodes and Machine PHI nodes, but the incoming operands have not been
5900 for (BasicBlock::iterator I = SuccBB->begin();
5901 (PN = dyn_cast<PHINode>(I)); ++I) {
5902 // Ignore dead phi's.
5903 if (PN->use_empty()) continue;
5906 Value *PHIOp = PN->getIncomingValueForBlock(LLVMBB);
5908 if (Constant *C = dyn_cast<Constant>(PHIOp)) {
5909 unsigned &RegOut = SDL->ConstantsOut[C];
5911 RegOut = FuncInfo->CreateRegForValue(C);
5912 SDL->CopyValueToVirtualRegister(C, RegOut);
5916 Reg = FuncInfo->ValueMap[PHIOp];
5918 assert(isa<AllocaInst>(PHIOp) &&
5919 FuncInfo->StaticAllocaMap.count(cast<AllocaInst>(PHIOp)) &&
5920 "Didn't codegen value into a register!??");
5921 Reg = FuncInfo->CreateRegForValue(PHIOp);
5922 SDL->CopyValueToVirtualRegister(PHIOp, Reg);
5926 // Remember that this register needs to added to the machine PHI node as
5927 // the input for this MBB.
5928 SmallVector<EVT, 4> ValueVTs;
5929 ComputeValueVTs(TLI, PN->getType(), ValueVTs);
5930 for (unsigned vti = 0, vte = ValueVTs.size(); vti != vte; ++vti) {
5931 EVT VT = ValueVTs[vti];
5932 unsigned NumRegisters = TLI.getNumRegisters(*CurDAG->getContext(), VT);
5933 for (unsigned i = 0, e = NumRegisters; i != e; ++i)
5934 SDL->PHINodesToUpdate.push_back(std::make_pair(MBBI++, Reg+i));
5935 Reg += NumRegisters;
5939 SDL->ConstantsOut.clear();
5942 /// This is the Fast-ISel version of HandlePHINodesInSuccessorBlocks. It only
5943 /// supports legal types, and it emits MachineInstrs directly instead of
5944 /// creating SelectionDAG nodes.
5947 SelectionDAGISel::HandlePHINodesInSuccessorBlocksFast(BasicBlock *LLVMBB,
5949 TerminatorInst *TI = LLVMBB->getTerminator();
5951 SmallPtrSet<MachineBasicBlock *, 4> SuccsHandled;
5952 unsigned OrigNumPHINodesToUpdate = SDL->PHINodesToUpdate.size();
5954 // Check successor nodes' PHI nodes that expect a constant to be available
5956 for (unsigned succ = 0, e = TI->getNumSuccessors(); succ != e; ++succ) {
5957 BasicBlock *SuccBB = TI->getSuccessor(succ);
5958 if (!isa<PHINode>(SuccBB->begin())) continue;
5959 MachineBasicBlock *SuccMBB = FuncInfo->MBBMap[SuccBB];
5961 // If this terminator has multiple identical successors (common for
5962 // switches), only handle each succ once.
5963 if (!SuccsHandled.insert(SuccMBB)) continue;
5965 MachineBasicBlock::iterator MBBI = SuccMBB->begin();
5968 // At this point we know that there is a 1-1 correspondence between LLVM PHI
5969 // nodes and Machine PHI nodes, but the incoming operands have not been
5971 for (BasicBlock::iterator I = SuccBB->begin();
5972 (PN = dyn_cast<PHINode>(I)); ++I) {
5973 // Ignore dead phi's.
5974 if (PN->use_empty()) continue;
5976 // Only handle legal types. Two interesting things to note here. First,
5977 // by bailing out early, we may leave behind some dead instructions,
5978 // since SelectionDAG's HandlePHINodesInSuccessorBlocks will insert its
5979 // own moves. Second, this check is necessary becuase FastISel doesn't
5980 // use CreateRegForValue to create registers, so it always creates
5981 // exactly one register for each non-void instruction.
5982 EVT VT = TLI.getValueType(PN->getType(), /*AllowUnknown=*/true);
5983 if (VT == MVT::Other || !TLI.isTypeLegal(VT)) {
5986 VT = TLI.getTypeToTransformTo(*CurDAG->getContext(), VT);
5988 SDL->PHINodesToUpdate.resize(OrigNumPHINodesToUpdate);
5993 Value *PHIOp = PN->getIncomingValueForBlock(LLVMBB);
5995 unsigned Reg = F->getRegForValue(PHIOp);
5997 SDL->PHINodesToUpdate.resize(OrigNumPHINodesToUpdate);
6000 SDL->PHINodesToUpdate.push_back(std::make_pair(MBBI++, Reg));