1 //===-- SelectionDAGBuild.cpp - Selection-DAG building --------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements routines for translating from LLVM IR into SelectionDAG IR.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "isel"
15 #include "SelectionDAGBuild.h"
16 #include "llvm/ADT/BitVector.h"
17 #include "llvm/ADT/SmallSet.h"
18 #include "llvm/Analysis/AliasAnalysis.h"
19 #include "llvm/Constants.h"
20 #include "llvm/CallingConv.h"
21 #include "llvm/DerivedTypes.h"
22 #include "llvm/Function.h"
23 #include "llvm/GlobalVariable.h"
24 #include "llvm/InlineAsm.h"
25 #include "llvm/Instructions.h"
26 #include "llvm/Intrinsics.h"
27 #include "llvm/IntrinsicInst.h"
28 #include "llvm/Module.h"
29 #include "llvm/CodeGen/FastISel.h"
30 #include "llvm/CodeGen/GCStrategy.h"
31 #include "llvm/CodeGen/GCMetadata.h"
32 #include "llvm/CodeGen/MachineFunction.h"
33 #include "llvm/CodeGen/MachineFrameInfo.h"
34 #include "llvm/CodeGen/MachineInstrBuilder.h"
35 #include "llvm/CodeGen/MachineJumpTableInfo.h"
36 #include "llvm/CodeGen/MachineModuleInfo.h"
37 #include "llvm/CodeGen/MachineRegisterInfo.h"
38 #include "llvm/CodeGen/PseudoSourceValue.h"
39 #include "llvm/CodeGen/SelectionDAG.h"
40 #include "llvm/CodeGen/DwarfWriter.h"
41 #include "llvm/Analysis/DebugInfo.h"
42 #include "llvm/Target/TargetRegisterInfo.h"
43 #include "llvm/Target/TargetData.h"
44 #include "llvm/Target/TargetFrameInfo.h"
45 #include "llvm/Target/TargetInstrInfo.h"
46 #include "llvm/Target/TargetIntrinsicInfo.h"
47 #include "llvm/Target/TargetLowering.h"
48 #include "llvm/Target/TargetOptions.h"
49 #include "llvm/Support/Compiler.h"
50 #include "llvm/Support/CommandLine.h"
51 #include "llvm/Support/Debug.h"
52 #include "llvm/Support/ErrorHandling.h"
53 #include "llvm/Support/MathExtras.h"
54 #include "llvm/Support/raw_ostream.h"
58 /// LimitFloatPrecision - Generate low-precision inline sequences for
59 /// some float libcalls (6, 8 or 12 bits).
60 static unsigned LimitFloatPrecision;
62 static cl::opt<unsigned, true>
63 LimitFPPrecision("limit-float-precision",
64 cl::desc("Generate low-precision inline sequences "
65 "for some float libcalls"),
66 cl::location(LimitFloatPrecision),
69 /// ComputeLinearIndex - Given an LLVM IR aggregate type and a sequence
70 /// of insertvalue or extractvalue indices that identify a member, return
71 /// the linearized index of the start of the member.
73 static unsigned ComputeLinearIndex(const TargetLowering &TLI, const Type *Ty,
74 const unsigned *Indices,
75 const unsigned *IndicesEnd,
76 unsigned CurIndex = 0) {
77 // Base case: We're done.
78 if (Indices && Indices == IndicesEnd)
81 // Given a struct type, recursively traverse the elements.
82 if (const StructType *STy = dyn_cast<StructType>(Ty)) {
83 for (StructType::element_iterator EB = STy->element_begin(),
85 EE = STy->element_end();
87 if (Indices && *Indices == unsigned(EI - EB))
88 return ComputeLinearIndex(TLI, *EI, Indices+1, IndicesEnd, CurIndex);
89 CurIndex = ComputeLinearIndex(TLI, *EI, 0, 0, CurIndex);
93 // Given an array type, recursively traverse the elements.
94 else if (const ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
95 const Type *EltTy = ATy->getElementType();
96 for (unsigned i = 0, e = ATy->getNumElements(); i != e; ++i) {
97 if (Indices && *Indices == i)
98 return ComputeLinearIndex(TLI, EltTy, Indices+1, IndicesEnd, CurIndex);
99 CurIndex = ComputeLinearIndex(TLI, EltTy, 0, 0, CurIndex);
103 // We haven't found the type we're looking for, so keep searching.
107 /// ComputeValueVTs - Given an LLVM IR type, compute a sequence of
108 /// MVTs that represent all the individual underlying
109 /// non-aggregate types that comprise it.
111 /// If Offsets is non-null, it points to a vector to be filled in
112 /// with the in-memory offsets of each of the individual values.
114 static void ComputeValueVTs(const TargetLowering &TLI, const Type *Ty,
115 SmallVectorImpl<MVT> &ValueVTs,
116 SmallVectorImpl<uint64_t> *Offsets = 0,
117 uint64_t StartingOffset = 0) {
118 // Given a struct type, recursively traverse the elements.
119 if (const StructType *STy = dyn_cast<StructType>(Ty)) {
120 const StructLayout *SL = TLI.getTargetData()->getStructLayout(STy);
121 for (StructType::element_iterator EB = STy->element_begin(),
123 EE = STy->element_end();
125 ComputeValueVTs(TLI, *EI, ValueVTs, Offsets,
126 StartingOffset + SL->getElementOffset(EI - EB));
129 // Given an array type, recursively traverse the elements.
130 if (const ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
131 const Type *EltTy = ATy->getElementType();
132 uint64_t EltSize = TLI.getTargetData()->getTypeAllocSize(EltTy);
133 for (unsigned i = 0, e = ATy->getNumElements(); i != e; ++i)
134 ComputeValueVTs(TLI, EltTy, ValueVTs, Offsets,
135 StartingOffset + i * EltSize);
138 // Interpret void as zero return values.
139 if (Ty == Type::VoidTy)
141 // Base case: we can get an MVT for this LLVM IR type.
142 ValueVTs.push_back(TLI.getValueType(Ty));
144 Offsets->push_back(StartingOffset);
148 /// RegsForValue - This struct represents the registers (physical or virtual)
149 /// that a particular set of values is assigned, and the type information about
150 /// the value. The most common situation is to represent one value at a time,
151 /// but struct or array values are handled element-wise as multiple values.
152 /// The splitting of aggregates is performed recursively, so that we never
153 /// have aggregate-typed registers. The values at this point do not necessarily
154 /// have legal types, so each value may require one or more registers of some
157 struct VISIBILITY_HIDDEN RegsForValue {
158 /// TLI - The TargetLowering object.
160 const TargetLowering *TLI;
162 /// ValueVTs - The value types of the values, which may not be legal, and
163 /// may need be promoted or synthesized from one or more registers.
165 SmallVector<MVT, 4> ValueVTs;
167 /// RegVTs - The value types of the registers. This is the same size as
168 /// ValueVTs and it records, for each value, what the type of the assigned
169 /// register or registers are. (Individual values are never synthesized
170 /// from more than one type of register.)
172 /// With virtual registers, the contents of RegVTs is redundant with TLI's
173 /// getRegisterType member function, however when with physical registers
174 /// it is necessary to have a separate record of the types.
176 SmallVector<MVT, 4> RegVTs;
178 /// Regs - This list holds the registers assigned to the values.
179 /// Each legal or promoted value requires one register, and each
180 /// expanded value requires multiple registers.
182 SmallVector<unsigned, 4> Regs;
184 RegsForValue() : TLI(0) {}
186 RegsForValue(const TargetLowering &tli,
187 const SmallVector<unsigned, 4> ®s,
188 MVT regvt, MVT valuevt)
189 : TLI(&tli), ValueVTs(1, valuevt), RegVTs(1, regvt), Regs(regs) {}
190 RegsForValue(const TargetLowering &tli,
191 const SmallVector<unsigned, 4> ®s,
192 const SmallVector<MVT, 4> ®vts,
193 const SmallVector<MVT, 4> &valuevts)
194 : TLI(&tli), ValueVTs(valuevts), RegVTs(regvts), Regs(regs) {}
195 RegsForValue(const TargetLowering &tli,
196 unsigned Reg, const Type *Ty) : TLI(&tli) {
197 ComputeValueVTs(tli, Ty, ValueVTs);
199 for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) {
200 MVT ValueVT = ValueVTs[Value];
201 unsigned NumRegs = TLI->getNumRegisters(ValueVT);
202 MVT RegisterVT = TLI->getRegisterType(ValueVT);
203 for (unsigned i = 0; i != NumRegs; ++i)
204 Regs.push_back(Reg + i);
205 RegVTs.push_back(RegisterVT);
210 /// append - Add the specified values to this one.
211 void append(const RegsForValue &RHS) {
213 ValueVTs.append(RHS.ValueVTs.begin(), RHS.ValueVTs.end());
214 RegVTs.append(RHS.RegVTs.begin(), RHS.RegVTs.end());
215 Regs.append(RHS.Regs.begin(), RHS.Regs.end());
219 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from
220 /// this value and returns the result as a ValueVTs value. This uses
221 /// Chain/Flag as the input and updates them for the output Chain/Flag.
222 /// If the Flag pointer is NULL, no flag is used.
223 SDValue getCopyFromRegs(SelectionDAG &DAG, DebugLoc dl,
224 SDValue &Chain, SDValue *Flag) const;
226 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
227 /// specified value into the registers specified by this object. This uses
228 /// Chain/Flag as the input and updates them for the output Chain/Flag.
229 /// If the Flag pointer is NULL, no flag is used.
230 void getCopyToRegs(SDValue Val, SelectionDAG &DAG, DebugLoc dl,
231 SDValue &Chain, SDValue *Flag) const;
233 /// AddInlineAsmOperands - Add this value to the specified inlineasm node
234 /// operand list. This adds the code marker, matching input operand index
235 /// (if applicable), and includes the number of values added into it.
236 void AddInlineAsmOperands(unsigned Code,
237 bool HasMatching, unsigned MatchingIdx,
238 SelectionDAG &DAG, std::vector<SDValue> &Ops) const;
242 /// isUsedOutsideOfDefiningBlock - Return true if this instruction is used by
243 /// PHI nodes or outside of the basic block that defines it, or used by a
244 /// switch or atomic instruction, which may expand to multiple basic blocks.
245 static bool isUsedOutsideOfDefiningBlock(Instruction *I) {
246 if (isa<PHINode>(I)) return true;
247 BasicBlock *BB = I->getParent();
248 for (Value::use_iterator UI = I->use_begin(), E = I->use_end(); UI != E; ++UI)
249 if (cast<Instruction>(*UI)->getParent() != BB || isa<PHINode>(*UI))
254 /// isOnlyUsedInEntryBlock - If the specified argument is only used in the
255 /// entry block, return true. This includes arguments used by switches, since
256 /// the switch may expand into multiple basic blocks.
257 static bool isOnlyUsedInEntryBlock(Argument *A, bool EnableFastISel) {
258 // With FastISel active, we may be splitting blocks, so force creation
259 // of virtual registers for all non-dead arguments.
260 // Don't force virtual registers for byval arguments though, because
261 // fast-isel can't handle those in all cases.
262 if (EnableFastISel && !A->hasByValAttr())
263 return A->use_empty();
265 BasicBlock *Entry = A->getParent()->begin();
266 for (Value::use_iterator UI = A->use_begin(), E = A->use_end(); UI != E; ++UI)
267 if (cast<Instruction>(*UI)->getParent() != Entry || isa<SwitchInst>(*UI))
268 return false; // Use not in entry block.
272 FunctionLoweringInfo::FunctionLoweringInfo(TargetLowering &tli)
276 void FunctionLoweringInfo::set(Function &fn, MachineFunction &mf,
278 bool EnableFastISel) {
281 RegInfo = &MF->getRegInfo();
283 // Create a vreg for each argument register that is not dead and is used
284 // outside of the entry block for the function.
285 for (Function::arg_iterator AI = Fn->arg_begin(), E = Fn->arg_end();
287 if (!isOnlyUsedInEntryBlock(AI, EnableFastISel))
288 InitializeRegForValue(AI);
290 // Initialize the mapping of values to registers. This is only set up for
291 // instruction values that are used outside of the block that defines
293 Function::iterator BB = Fn->begin(), EB = Fn->end();
294 for (BasicBlock::iterator I = BB->begin(), E = BB->end(); I != E; ++I)
295 if (AllocaInst *AI = dyn_cast<AllocaInst>(I))
296 if (ConstantInt *CUI = dyn_cast<ConstantInt>(AI->getArraySize())) {
297 const Type *Ty = AI->getAllocatedType();
298 uint64_t TySize = TLI.getTargetData()->getTypeAllocSize(Ty);
300 std::max((unsigned)TLI.getTargetData()->getPrefTypeAlignment(Ty),
303 TySize *= CUI->getZExtValue(); // Get total allocated size.
304 if (TySize == 0) TySize = 1; // Don't create zero-sized stack objects.
305 StaticAllocaMap[AI] =
306 MF->getFrameInfo()->CreateStackObject(TySize, Align);
309 for (; BB != EB; ++BB)
310 for (BasicBlock::iterator I = BB->begin(), E = BB->end(); I != E; ++I)
311 if (!I->use_empty() && isUsedOutsideOfDefiningBlock(I))
312 if (!isa<AllocaInst>(I) ||
313 !StaticAllocaMap.count(cast<AllocaInst>(I)))
314 InitializeRegForValue(I);
316 // Create an initial MachineBasicBlock for each LLVM BasicBlock in F. This
317 // also creates the initial PHI MachineInstrs, though none of the input
318 // operands are populated.
319 for (BB = Fn->begin(), EB = Fn->end(); BB != EB; ++BB) {
320 MachineBasicBlock *MBB = mf.CreateMachineBasicBlock(BB);
324 // Create Machine PHI nodes for LLVM PHI nodes, lowering them as
328 for (BasicBlock::iterator
329 I = BB->begin(), E = BB->end(); I != E; ++I) {
330 if (CallInst *CI = dyn_cast<CallInst>(I)) {
331 if (Function *F = CI->getCalledFunction()) {
332 switch (F->getIntrinsicID()) {
334 case Intrinsic::dbg_stoppoint: {
335 DbgStopPointInst *SPI = cast<DbgStopPointInst>(I);
336 if (isValidDebugInfoIntrinsic(*SPI, CodeGenOpt::Default))
337 DL = ExtractDebugLocation(*SPI, MF->getDebugLocInfo());
340 case Intrinsic::dbg_func_start: {
341 DbgFuncStartInst *FSI = cast<DbgFuncStartInst>(I);
342 if (isValidDebugInfoIntrinsic(*FSI, CodeGenOpt::Default))
343 DL = ExtractDebugLocation(*FSI, MF->getDebugLocInfo());
350 PN = dyn_cast<PHINode>(I);
351 if (!PN || PN->use_empty()) continue;
353 unsigned PHIReg = ValueMap[PN];
354 assert(PHIReg && "PHI node does not have an assigned virtual register!");
356 SmallVector<MVT, 4> ValueVTs;
357 ComputeValueVTs(TLI, PN->getType(), ValueVTs);
358 for (unsigned vti = 0, vte = ValueVTs.size(); vti != vte; ++vti) {
359 MVT VT = ValueVTs[vti];
360 unsigned NumRegisters = TLI.getNumRegisters(VT);
361 const TargetInstrInfo *TII = MF->getTarget().getInstrInfo();
362 for (unsigned i = 0; i != NumRegisters; ++i)
363 BuildMI(MBB, DL, TII->get(TargetInstrInfo::PHI), PHIReg + i);
364 PHIReg += NumRegisters;
370 unsigned FunctionLoweringInfo::MakeReg(MVT VT) {
371 return RegInfo->createVirtualRegister(TLI.getRegClassFor(VT));
374 /// CreateRegForValue - Allocate the appropriate number of virtual registers of
375 /// the correctly promoted or expanded types. Assign these registers
376 /// consecutive vreg numbers and return the first assigned number.
378 /// In the case that the given value has struct or array type, this function
379 /// will assign registers for each member or element.
381 unsigned FunctionLoweringInfo::CreateRegForValue(const Value *V) {
382 SmallVector<MVT, 4> ValueVTs;
383 ComputeValueVTs(TLI, V->getType(), ValueVTs);
385 unsigned FirstReg = 0;
386 for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) {
387 MVT ValueVT = ValueVTs[Value];
388 MVT RegisterVT = TLI.getRegisterType(ValueVT);
390 unsigned NumRegs = TLI.getNumRegisters(ValueVT);
391 for (unsigned i = 0; i != NumRegs; ++i) {
392 unsigned R = MakeReg(RegisterVT);
393 if (!FirstReg) FirstReg = R;
399 /// getCopyFromParts - Create a value that contains the specified legal parts
400 /// combined into the value they represent. If the parts combine to a type
401 /// larger then ValueVT then AssertOp can be used to specify whether the extra
402 /// bits are known to be zero (ISD::AssertZext) or sign extended from ValueVT
403 /// (ISD::AssertSext).
404 static SDValue getCopyFromParts(SelectionDAG &DAG, DebugLoc dl,
405 const SDValue *Parts,
406 unsigned NumParts, MVT PartVT, MVT ValueVT,
407 ISD::NodeType AssertOp = ISD::DELETED_NODE) {
408 assert(NumParts > 0 && "No parts to assemble!");
409 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
410 SDValue Val = Parts[0];
413 // Assemble the value from multiple parts.
414 if (!ValueVT.isVector() && ValueVT.isInteger()) {
415 unsigned PartBits = PartVT.getSizeInBits();
416 unsigned ValueBits = ValueVT.getSizeInBits();
418 // Assemble the power of 2 part.
419 unsigned RoundParts = NumParts & (NumParts - 1) ?
420 1 << Log2_32(NumParts) : NumParts;
421 unsigned RoundBits = PartBits * RoundParts;
422 MVT RoundVT = RoundBits == ValueBits ?
423 ValueVT : MVT::getIntegerVT(RoundBits);
426 MVT HalfVT = MVT::getIntegerVT(RoundBits/2);
428 if (RoundParts > 2) {
429 Lo = getCopyFromParts(DAG, dl, Parts, RoundParts/2, PartVT, HalfVT);
430 Hi = getCopyFromParts(DAG, dl, Parts+RoundParts/2, RoundParts/2,
433 Lo = DAG.getNode(ISD::BIT_CONVERT, dl, HalfVT, Parts[0]);
434 Hi = DAG.getNode(ISD::BIT_CONVERT, dl, HalfVT, Parts[1]);
436 if (TLI.isBigEndian())
438 Val = DAG.getNode(ISD::BUILD_PAIR, dl, RoundVT, Lo, Hi);
440 if (RoundParts < NumParts) {
441 // Assemble the trailing non-power-of-2 part.
442 unsigned OddParts = NumParts - RoundParts;
443 MVT OddVT = MVT::getIntegerVT(OddParts * PartBits);
444 Hi = getCopyFromParts(DAG, dl,
445 Parts+RoundParts, OddParts, PartVT, OddVT);
447 // Combine the round and odd parts.
449 if (TLI.isBigEndian())
451 MVT TotalVT = MVT::getIntegerVT(NumParts * PartBits);
452 Hi = DAG.getNode(ISD::ANY_EXTEND, dl, TotalVT, Hi);
453 Hi = DAG.getNode(ISD::SHL, dl, TotalVT, Hi,
454 DAG.getConstant(Lo.getValueType().getSizeInBits(),
455 TLI.getPointerTy()));
456 Lo = DAG.getNode(ISD::ZERO_EXTEND, dl, TotalVT, Lo);
457 Val = DAG.getNode(ISD::OR, dl, TotalVT, Lo, Hi);
459 } else if (ValueVT.isVector()) {
460 // Handle a multi-element vector.
461 MVT IntermediateVT, RegisterVT;
462 unsigned NumIntermediates;
464 TLI.getVectorTypeBreakdown(ValueVT, IntermediateVT, NumIntermediates,
466 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!");
467 NumParts = NumRegs; // Silence a compiler warning.
468 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!");
469 assert(RegisterVT == Parts[0].getValueType() &&
470 "Part type doesn't match part!");
472 // Assemble the parts into intermediate operands.
473 SmallVector<SDValue, 8> Ops(NumIntermediates);
474 if (NumIntermediates == NumParts) {
475 // If the register was not expanded, truncate or copy the value,
477 for (unsigned i = 0; i != NumParts; ++i)
478 Ops[i] = getCopyFromParts(DAG, dl, &Parts[i], 1,
479 PartVT, IntermediateVT);
480 } else if (NumParts > 0) {
481 // If the intermediate type was expanded, build the intermediate operands
483 assert(NumParts % NumIntermediates == 0 &&
484 "Must expand into a divisible number of parts!");
485 unsigned Factor = NumParts / NumIntermediates;
486 for (unsigned i = 0; i != NumIntermediates; ++i)
487 Ops[i] = getCopyFromParts(DAG, dl, &Parts[i * Factor], Factor,
488 PartVT, IntermediateVT);
491 // Build a vector with BUILD_VECTOR or CONCAT_VECTORS from the intermediate
493 Val = DAG.getNode(IntermediateVT.isVector() ?
494 ISD::CONCAT_VECTORS : ISD::BUILD_VECTOR, dl,
495 ValueVT, &Ops[0], NumIntermediates);
496 } else if (PartVT.isFloatingPoint()) {
497 // FP split into multiple FP parts (for ppcf128)
498 assert(ValueVT == MVT(MVT::ppcf128) && PartVT == MVT(MVT::f64) &&
501 Lo = DAG.getNode(ISD::BIT_CONVERT, dl, MVT(MVT::f64), Parts[0]);
502 Hi = DAG.getNode(ISD::BIT_CONVERT, dl, MVT(MVT::f64), Parts[1]);
503 if (TLI.isBigEndian())
505 Val = DAG.getNode(ISD::BUILD_PAIR, dl, ValueVT, Lo, Hi);
507 // FP split into integer parts (soft fp)
508 assert(ValueVT.isFloatingPoint() && PartVT.isInteger() &&
509 !PartVT.isVector() && "Unexpected split");
510 MVT IntVT = MVT::getIntegerVT(ValueVT.getSizeInBits());
511 Val = getCopyFromParts(DAG, dl, Parts, NumParts, PartVT, IntVT);
515 // There is now one part, held in Val. Correct it to match ValueVT.
516 PartVT = Val.getValueType();
518 if (PartVT == ValueVT)
521 if (PartVT.isVector()) {
522 assert(ValueVT.isVector() && "Unknown vector conversion!");
523 return DAG.getNode(ISD::BIT_CONVERT, dl, ValueVT, Val);
526 if (ValueVT.isVector()) {
527 assert(ValueVT.getVectorElementType() == PartVT &&
528 ValueVT.getVectorNumElements() == 1 &&
529 "Only trivial scalar-to-vector conversions should get here!");
530 return DAG.getNode(ISD::BUILD_VECTOR, dl, ValueVT, Val);
533 if (PartVT.isInteger() &&
534 ValueVT.isInteger()) {
535 if (ValueVT.bitsLT(PartVT)) {
536 // For a truncate, see if we have any information to
537 // indicate whether the truncated bits will always be
538 // zero or sign-extension.
539 if (AssertOp != ISD::DELETED_NODE)
540 Val = DAG.getNode(AssertOp, dl, PartVT, Val,
541 DAG.getValueType(ValueVT));
542 return DAG.getNode(ISD::TRUNCATE, dl, ValueVT, Val);
544 return DAG.getNode(ISD::ANY_EXTEND, dl, ValueVT, Val);
548 if (PartVT.isFloatingPoint() && ValueVT.isFloatingPoint()) {
549 if (ValueVT.bitsLT(Val.getValueType()))
550 // FP_ROUND's are always exact here.
551 return DAG.getNode(ISD::FP_ROUND, dl, ValueVT, Val,
552 DAG.getIntPtrConstant(1));
553 return DAG.getNode(ISD::FP_EXTEND, dl, ValueVT, Val);
556 if (PartVT.getSizeInBits() == ValueVT.getSizeInBits())
557 return DAG.getNode(ISD::BIT_CONVERT, dl, ValueVT, Val);
559 llvm_unreachable("Unknown mismatch!");
563 /// getCopyToParts - Create a series of nodes that contain the specified value
564 /// split into legal parts. If the parts contain more bits than Val, then, for
565 /// integers, ExtendKind can be used to specify how to generate the extra bits.
566 static void getCopyToParts(SelectionDAG &DAG, DebugLoc dl, SDValue Val,
567 SDValue *Parts, unsigned NumParts, MVT PartVT,
568 ISD::NodeType ExtendKind = ISD::ANY_EXTEND) {
569 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
570 MVT PtrVT = TLI.getPointerTy();
571 MVT ValueVT = Val.getValueType();
572 unsigned PartBits = PartVT.getSizeInBits();
573 unsigned OrigNumParts = NumParts;
574 assert(TLI.isTypeLegal(PartVT) && "Copying to an illegal type!");
579 if (!ValueVT.isVector()) {
580 if (PartVT == ValueVT) {
581 assert(NumParts == 1 && "No-op copy with multiple parts!");
586 if (NumParts * PartBits > ValueVT.getSizeInBits()) {
587 // If the parts cover more bits than the value has, promote the value.
588 if (PartVT.isFloatingPoint() && ValueVT.isFloatingPoint()) {
589 assert(NumParts == 1 && "Do not know what to promote to!");
590 Val = DAG.getNode(ISD::FP_EXTEND, dl, PartVT, Val);
591 } else if (PartVT.isInteger() && ValueVT.isInteger()) {
592 ValueVT = MVT::getIntegerVT(NumParts * PartBits);
593 Val = DAG.getNode(ExtendKind, dl, ValueVT, Val);
595 llvm_unreachable("Unknown mismatch!");
597 } else if (PartBits == ValueVT.getSizeInBits()) {
598 // Different types of the same size.
599 assert(NumParts == 1 && PartVT != ValueVT);
600 Val = DAG.getNode(ISD::BIT_CONVERT, dl, PartVT, Val);
601 } else if (NumParts * PartBits < ValueVT.getSizeInBits()) {
602 // If the parts cover less bits than value has, truncate the value.
603 if (PartVT.isInteger() && ValueVT.isInteger()) {
604 ValueVT = MVT::getIntegerVT(NumParts * PartBits);
605 Val = DAG.getNode(ISD::TRUNCATE, dl, ValueVT, Val);
607 llvm_unreachable("Unknown mismatch!");
611 // The value may have changed - recompute ValueVT.
612 ValueVT = Val.getValueType();
613 assert(NumParts * PartBits == ValueVT.getSizeInBits() &&
614 "Failed to tile the value with PartVT!");
617 assert(PartVT == ValueVT && "Type conversion failed!");
622 // Expand the value into multiple parts.
623 if (NumParts & (NumParts - 1)) {
624 // The number of parts is not a power of 2. Split off and copy the tail.
625 assert(PartVT.isInteger() && ValueVT.isInteger() &&
626 "Do not know what to expand to!");
627 unsigned RoundParts = 1 << Log2_32(NumParts);
628 unsigned RoundBits = RoundParts * PartBits;
629 unsigned OddParts = NumParts - RoundParts;
630 SDValue OddVal = DAG.getNode(ISD::SRL, dl, ValueVT, Val,
631 DAG.getConstant(RoundBits,
632 TLI.getPointerTy()));
633 getCopyToParts(DAG, dl, OddVal, Parts + RoundParts, OddParts, PartVT);
634 if (TLI.isBigEndian())
635 // The odd parts were reversed by getCopyToParts - unreverse them.
636 std::reverse(Parts + RoundParts, Parts + NumParts);
637 NumParts = RoundParts;
638 ValueVT = MVT::getIntegerVT(NumParts * PartBits);
639 Val = DAG.getNode(ISD::TRUNCATE, dl, ValueVT, Val);
642 // The number of parts is a power of 2. Repeatedly bisect the value using
644 Parts[0] = DAG.getNode(ISD::BIT_CONVERT, dl,
645 MVT::getIntegerVT(ValueVT.getSizeInBits()),
647 for (unsigned StepSize = NumParts; StepSize > 1; StepSize /= 2) {
648 for (unsigned i = 0; i < NumParts; i += StepSize) {
649 unsigned ThisBits = StepSize * PartBits / 2;
650 MVT ThisVT = MVT::getIntegerVT (ThisBits);
651 SDValue &Part0 = Parts[i];
652 SDValue &Part1 = Parts[i+StepSize/2];
654 Part1 = DAG.getNode(ISD::EXTRACT_ELEMENT, dl,
656 DAG.getConstant(1, PtrVT));
657 Part0 = DAG.getNode(ISD::EXTRACT_ELEMENT, dl,
659 DAG.getConstant(0, PtrVT));
661 if (ThisBits == PartBits && ThisVT != PartVT) {
662 Part0 = DAG.getNode(ISD::BIT_CONVERT, dl,
664 Part1 = DAG.getNode(ISD::BIT_CONVERT, dl,
670 if (TLI.isBigEndian())
671 std::reverse(Parts, Parts + OrigNumParts);
678 if (PartVT != ValueVT) {
679 if (PartVT.isVector()) {
680 Val = DAG.getNode(ISD::BIT_CONVERT, dl, PartVT, Val);
682 assert(ValueVT.getVectorElementType() == PartVT &&
683 ValueVT.getVectorNumElements() == 1 &&
684 "Only trivial vector-to-scalar conversions should get here!");
685 Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
687 DAG.getConstant(0, PtrVT));
695 // Handle a multi-element vector.
696 MVT IntermediateVT, RegisterVT;
697 unsigned NumIntermediates;
698 unsigned NumRegs = TLI
699 .getVectorTypeBreakdown(ValueVT, IntermediateVT, NumIntermediates,
701 unsigned NumElements = ValueVT.getVectorNumElements();
703 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!");
704 NumParts = NumRegs; // Silence a compiler warning.
705 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!");
707 // Split the vector into intermediate operands.
708 SmallVector<SDValue, 8> Ops(NumIntermediates);
709 for (unsigned i = 0; i != NumIntermediates; ++i)
710 if (IntermediateVT.isVector())
711 Ops[i] = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl,
713 DAG.getConstant(i * (NumElements / NumIntermediates),
716 Ops[i] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
718 DAG.getConstant(i, PtrVT));
720 // Split the intermediate operands into legal parts.
721 if (NumParts == NumIntermediates) {
722 // If the register was not expanded, promote or copy the value,
724 for (unsigned i = 0; i != NumParts; ++i)
725 getCopyToParts(DAG, dl, Ops[i], &Parts[i], 1, PartVT);
726 } else if (NumParts > 0) {
727 // If the intermediate type was expanded, split each the value into
729 assert(NumParts % NumIntermediates == 0 &&
730 "Must expand into a divisible number of parts!");
731 unsigned Factor = NumParts / NumIntermediates;
732 for (unsigned i = 0; i != NumIntermediates; ++i)
733 getCopyToParts(DAG, dl, Ops[i], &Parts[i * Factor], Factor, PartVT);
738 void SelectionDAGLowering::init(GCFunctionInfo *gfi, AliasAnalysis &aa) {
741 TD = DAG.getTarget().getTargetData();
744 /// clear - Clear out the curret SelectionDAG and the associated
745 /// state and prepare this SelectionDAGLowering object to be used
746 /// for a new block. This doesn't clear out information about
747 /// additional blocks that are needed to complete switch lowering
748 /// or PHI node updating; that information is cleared out as it is
750 void SelectionDAGLowering::clear() {
752 PendingLoads.clear();
753 PendingExports.clear();
755 CurDebugLoc = DebugLoc::getUnknownLoc();
758 /// getRoot - Return the current virtual root of the Selection DAG,
759 /// flushing any PendingLoad items. This must be done before emitting
760 /// a store or any other node that may need to be ordered after any
761 /// prior load instructions.
763 SDValue SelectionDAGLowering::getRoot() {
764 if (PendingLoads.empty())
765 return DAG.getRoot();
767 if (PendingLoads.size() == 1) {
768 SDValue Root = PendingLoads[0];
770 PendingLoads.clear();
774 // Otherwise, we have to make a token factor node.
775 SDValue Root = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), MVT::Other,
776 &PendingLoads[0], PendingLoads.size());
777 PendingLoads.clear();
782 /// getControlRoot - Similar to getRoot, but instead of flushing all the
783 /// PendingLoad items, flush all the PendingExports items. It is necessary
784 /// to do this before emitting a terminator instruction.
786 SDValue SelectionDAGLowering::getControlRoot() {
787 SDValue Root = DAG.getRoot();
789 if (PendingExports.empty())
792 // Turn all of the CopyToReg chains into one factored node.
793 if (Root.getOpcode() != ISD::EntryToken) {
794 unsigned i = 0, e = PendingExports.size();
795 for (; i != e; ++i) {
796 assert(PendingExports[i].getNode()->getNumOperands() > 1);
797 if (PendingExports[i].getNode()->getOperand(0) == Root)
798 break; // Don't add the root if we already indirectly depend on it.
802 PendingExports.push_back(Root);
805 Root = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), MVT::Other,
807 PendingExports.size());
808 PendingExports.clear();
813 void SelectionDAGLowering::visit(Instruction &I) {
814 visit(I.getOpcode(), I);
817 void SelectionDAGLowering::visit(unsigned Opcode, User &I) {
818 // Note: this doesn't use InstVisitor, because it has to work with
819 // ConstantExpr's in addition to instructions.
821 default: llvm_unreachable("Unknown instruction type encountered!");
822 // Build the switch statement using the Instruction.def file.
823 #define HANDLE_INST(NUM, OPCODE, CLASS) \
824 case Instruction::OPCODE:return visit##OPCODE((CLASS&)I);
825 #include "llvm/Instruction.def"
829 SDValue SelectionDAGLowering::getValue(const Value *V) {
830 SDValue &N = NodeMap[V];
831 if (N.getNode()) return N;
833 if (Constant *C = const_cast<Constant*>(dyn_cast<Constant>(V))) {
834 MVT VT = TLI.getValueType(V->getType(), true);
836 if (ConstantInt *CI = dyn_cast<ConstantInt>(C))
837 return N = DAG.getConstant(*CI, VT);
839 if (GlobalValue *GV = dyn_cast<GlobalValue>(C))
840 return N = DAG.getGlobalAddress(GV, VT);
842 if (isa<ConstantPointerNull>(C))
843 return N = DAG.getConstant(0, TLI.getPointerTy());
845 if (ConstantFP *CFP = dyn_cast<ConstantFP>(C))
846 return N = DAG.getConstantFP(*CFP, VT);
848 if (isa<UndefValue>(C) && !V->getType()->isAggregateType())
849 return N = DAG.getUNDEF(VT);
851 if (ConstantExpr *CE = dyn_cast<ConstantExpr>(C)) {
852 visit(CE->getOpcode(), *CE);
853 SDValue N1 = NodeMap[V];
854 assert(N1.getNode() && "visit didn't populate the ValueMap!");
858 if (isa<ConstantStruct>(C) || isa<ConstantArray>(C)) {
859 SmallVector<SDValue, 4> Constants;
860 for (User::const_op_iterator OI = C->op_begin(), OE = C->op_end();
862 SDNode *Val = getValue(*OI).getNode();
863 for (unsigned i = 0, e = Val->getNumValues(); i != e; ++i)
864 Constants.push_back(SDValue(Val, i));
866 return DAG.getMergeValues(&Constants[0], Constants.size(),
870 if (isa<StructType>(C->getType()) || isa<ArrayType>(C->getType())) {
871 assert((isa<ConstantAggregateZero>(C) || isa<UndefValue>(C)) &&
872 "Unknown struct or array constant!");
874 SmallVector<MVT, 4> ValueVTs;
875 ComputeValueVTs(TLI, C->getType(), ValueVTs);
876 unsigned NumElts = ValueVTs.size();
878 return SDValue(); // empty struct
879 SmallVector<SDValue, 4> Constants(NumElts);
880 for (unsigned i = 0; i != NumElts; ++i) {
881 MVT EltVT = ValueVTs[i];
882 if (isa<UndefValue>(C))
883 Constants[i] = DAG.getUNDEF(EltVT);
884 else if (EltVT.isFloatingPoint())
885 Constants[i] = DAG.getConstantFP(0, EltVT);
887 Constants[i] = DAG.getConstant(0, EltVT);
889 return DAG.getMergeValues(&Constants[0], NumElts, getCurDebugLoc());
892 const VectorType *VecTy = cast<VectorType>(V->getType());
893 unsigned NumElements = VecTy->getNumElements();
895 // Now that we know the number and type of the elements, get that number of
896 // elements into the Ops array based on what kind of constant it is.
897 SmallVector<SDValue, 16> Ops;
898 if (ConstantVector *CP = dyn_cast<ConstantVector>(C)) {
899 for (unsigned i = 0; i != NumElements; ++i)
900 Ops.push_back(getValue(CP->getOperand(i)));
902 assert(isa<ConstantAggregateZero>(C) && "Unknown vector constant!");
903 MVT EltVT = TLI.getValueType(VecTy->getElementType());
906 if (EltVT.isFloatingPoint())
907 Op = DAG.getConstantFP(0, EltVT);
909 Op = DAG.getConstant(0, EltVT);
910 Ops.assign(NumElements, Op);
913 // Create a BUILD_VECTOR node.
914 return NodeMap[V] = DAG.getNode(ISD::BUILD_VECTOR, getCurDebugLoc(),
915 VT, &Ops[0], Ops.size());
918 // If this is a static alloca, generate it as the frameindex instead of
920 if (const AllocaInst *AI = dyn_cast<AllocaInst>(V)) {
921 DenseMap<const AllocaInst*, int>::iterator SI =
922 FuncInfo.StaticAllocaMap.find(AI);
923 if (SI != FuncInfo.StaticAllocaMap.end())
924 return DAG.getFrameIndex(SI->second, TLI.getPointerTy());
927 unsigned InReg = FuncInfo.ValueMap[V];
928 assert(InReg && "Value not in map!");
930 RegsForValue RFV(TLI, InReg, V->getType());
931 SDValue Chain = DAG.getEntryNode();
932 return RFV.getCopyFromRegs(DAG, getCurDebugLoc(), Chain, NULL);
936 void SelectionDAGLowering::visitRet(ReturnInst &I) {
937 if (I.getNumOperands() == 0) {
938 DAG.setRoot(DAG.getNode(ISD::RET, getCurDebugLoc(),
939 MVT::Other, getControlRoot()));
943 SmallVector<SDValue, 8> NewValues;
944 NewValues.push_back(getControlRoot());
945 for (unsigned i = 0, e = I.getNumOperands(); i != e; ++i) {
946 SmallVector<MVT, 4> ValueVTs;
947 ComputeValueVTs(TLI, I.getOperand(i)->getType(), ValueVTs);
948 unsigned NumValues = ValueVTs.size();
949 if (NumValues == 0) continue;
951 SDValue RetOp = getValue(I.getOperand(i));
952 for (unsigned j = 0, f = NumValues; j != f; ++j) {
953 MVT VT = ValueVTs[j];
955 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
957 const Function *F = I.getParent()->getParent();
958 if (F->paramHasAttr(0, Attribute::SExt))
959 ExtendKind = ISD::SIGN_EXTEND;
960 else if (F->paramHasAttr(0, Attribute::ZExt))
961 ExtendKind = ISD::ZERO_EXTEND;
963 // FIXME: C calling convention requires the return type to be promoted to
964 // at least 32-bit. But this is not necessary for non-C calling
965 // conventions. The frontend should mark functions whose return values
966 // require promoting with signext or zeroext attributes.
967 if (ExtendKind != ISD::ANY_EXTEND && VT.isInteger()) {
968 MVT MinVT = TLI.getRegisterType(MVT::i32);
969 if (VT.bitsLT(MinVT))
973 unsigned NumParts = TLI.getNumRegisters(VT);
974 MVT PartVT = TLI.getRegisterType(VT);
975 SmallVector<SDValue, 4> Parts(NumParts);
976 getCopyToParts(DAG, getCurDebugLoc(),
977 SDValue(RetOp.getNode(), RetOp.getResNo() + j),
978 &Parts[0], NumParts, PartVT, ExtendKind);
980 // 'inreg' on function refers to return value
981 ISD::ArgFlagsTy Flags = ISD::ArgFlagsTy();
982 if (F->paramHasAttr(0, Attribute::InReg))
985 // Propagate extension type if any
986 if (F->paramHasAttr(0, Attribute::SExt))
988 else if (F->paramHasAttr(0, Attribute::ZExt))
991 for (unsigned i = 0; i < NumParts; ++i) {
992 NewValues.push_back(Parts[i]);
993 NewValues.push_back(DAG.getArgFlags(Flags));
997 DAG.setRoot(DAG.getNode(ISD::RET, getCurDebugLoc(), MVT::Other,
998 &NewValues[0], NewValues.size()));
1001 /// CopyToExportRegsIfNeeded - If the given value has virtual registers
1002 /// created for it, emit nodes to copy the value into the virtual
1004 void SelectionDAGLowering::CopyToExportRegsIfNeeded(Value *V) {
1005 if (!V->use_empty()) {
1006 DenseMap<const Value *, unsigned>::iterator VMI = FuncInfo.ValueMap.find(V);
1007 if (VMI != FuncInfo.ValueMap.end())
1008 CopyValueToVirtualRegister(V, VMI->second);
1012 /// ExportFromCurrentBlock - If this condition isn't known to be exported from
1013 /// the current basic block, add it to ValueMap now so that we'll get a
1015 void SelectionDAGLowering::ExportFromCurrentBlock(Value *V) {
1016 // No need to export constants.
1017 if (!isa<Instruction>(V) && !isa<Argument>(V)) return;
1019 // Already exported?
1020 if (FuncInfo.isExportedInst(V)) return;
1022 unsigned Reg = FuncInfo.InitializeRegForValue(V);
1023 CopyValueToVirtualRegister(V, Reg);
1026 bool SelectionDAGLowering::isExportableFromCurrentBlock(Value *V,
1027 const BasicBlock *FromBB) {
1028 // The operands of the setcc have to be in this block. We don't know
1029 // how to export them from some other block.
1030 if (Instruction *VI = dyn_cast<Instruction>(V)) {
1031 // Can export from current BB.
1032 if (VI->getParent() == FromBB)
1035 // Is already exported, noop.
1036 return FuncInfo.isExportedInst(V);
1039 // If this is an argument, we can export it if the BB is the entry block or
1040 // if it is already exported.
1041 if (isa<Argument>(V)) {
1042 if (FromBB == &FromBB->getParent()->getEntryBlock())
1045 // Otherwise, can only export this if it is already exported.
1046 return FuncInfo.isExportedInst(V);
1049 // Otherwise, constants can always be exported.
1053 static bool InBlock(const Value *V, const BasicBlock *BB) {
1054 if (const Instruction *I = dyn_cast<Instruction>(V))
1055 return I->getParent() == BB;
1059 /// getFCmpCondCode - Return the ISD condition code corresponding to
1060 /// the given LLVM IR floating-point condition code. This includes
1061 /// consideration of global floating-point math flags.
1063 static ISD::CondCode getFCmpCondCode(FCmpInst::Predicate Pred) {
1064 ISD::CondCode FPC, FOC;
1066 case FCmpInst::FCMP_FALSE: FOC = FPC = ISD::SETFALSE; break;
1067 case FCmpInst::FCMP_OEQ: FOC = ISD::SETEQ; FPC = ISD::SETOEQ; break;
1068 case FCmpInst::FCMP_OGT: FOC = ISD::SETGT; FPC = ISD::SETOGT; break;
1069 case FCmpInst::FCMP_OGE: FOC = ISD::SETGE; FPC = ISD::SETOGE; break;
1070 case FCmpInst::FCMP_OLT: FOC = ISD::SETLT; FPC = ISD::SETOLT; break;
1071 case FCmpInst::FCMP_OLE: FOC = ISD::SETLE; FPC = ISD::SETOLE; break;
1072 case FCmpInst::FCMP_ONE: FOC = ISD::SETNE; FPC = ISD::SETONE; break;
1073 case FCmpInst::FCMP_ORD: FOC = FPC = ISD::SETO; break;
1074 case FCmpInst::FCMP_UNO: FOC = FPC = ISD::SETUO; break;
1075 case FCmpInst::FCMP_UEQ: FOC = ISD::SETEQ; FPC = ISD::SETUEQ; break;
1076 case FCmpInst::FCMP_UGT: FOC = ISD::SETGT; FPC = ISD::SETUGT; break;
1077 case FCmpInst::FCMP_UGE: FOC = ISD::SETGE; FPC = ISD::SETUGE; break;
1078 case FCmpInst::FCMP_ULT: FOC = ISD::SETLT; FPC = ISD::SETULT; break;
1079 case FCmpInst::FCMP_ULE: FOC = ISD::SETLE; FPC = ISD::SETULE; break;
1080 case FCmpInst::FCMP_UNE: FOC = ISD::SETNE; FPC = ISD::SETUNE; break;
1081 case FCmpInst::FCMP_TRUE: FOC = FPC = ISD::SETTRUE; break;
1083 llvm_unreachable("Invalid FCmp predicate opcode!");
1084 FOC = FPC = ISD::SETFALSE;
1087 if (FiniteOnlyFPMath())
1093 /// getICmpCondCode - Return the ISD condition code corresponding to
1094 /// the given LLVM IR integer condition code.
1096 static ISD::CondCode getICmpCondCode(ICmpInst::Predicate Pred) {
1098 case ICmpInst::ICMP_EQ: return ISD::SETEQ;
1099 case ICmpInst::ICMP_NE: return ISD::SETNE;
1100 case ICmpInst::ICMP_SLE: return ISD::SETLE;
1101 case ICmpInst::ICMP_ULE: return ISD::SETULE;
1102 case ICmpInst::ICMP_SGE: return ISD::SETGE;
1103 case ICmpInst::ICMP_UGE: return ISD::SETUGE;
1104 case ICmpInst::ICMP_SLT: return ISD::SETLT;
1105 case ICmpInst::ICMP_ULT: return ISD::SETULT;
1106 case ICmpInst::ICMP_SGT: return ISD::SETGT;
1107 case ICmpInst::ICMP_UGT: return ISD::SETUGT;
1109 llvm_unreachable("Invalid ICmp predicate opcode!");
1114 /// EmitBranchForMergedCondition - Helper method for FindMergedConditions.
1115 /// This function emits a branch and is used at the leaves of an OR or an
1116 /// AND operator tree.
1119 SelectionDAGLowering::EmitBranchForMergedCondition(Value *Cond,
1120 MachineBasicBlock *TBB,
1121 MachineBasicBlock *FBB,
1122 MachineBasicBlock *CurBB) {
1123 const BasicBlock *BB = CurBB->getBasicBlock();
1125 // If the leaf of the tree is a comparison, merge the condition into
1127 if (CmpInst *BOp = dyn_cast<CmpInst>(Cond)) {
1128 // The operands of the cmp have to be in this block. We don't know
1129 // how to export them from some other block. If this is the first block
1130 // of the sequence, no exporting is needed.
1131 if (CurBB == CurMBB ||
1132 (isExportableFromCurrentBlock(BOp->getOperand(0), BB) &&
1133 isExportableFromCurrentBlock(BOp->getOperand(1), BB))) {
1134 ISD::CondCode Condition;
1135 if (ICmpInst *IC = dyn_cast<ICmpInst>(Cond)) {
1136 Condition = getICmpCondCode(IC->getPredicate());
1137 } else if (FCmpInst *FC = dyn_cast<FCmpInst>(Cond)) {
1138 Condition = getFCmpCondCode(FC->getPredicate());
1140 Condition = ISD::SETEQ; // silence warning.
1141 llvm_unreachable("Unknown compare instruction");
1144 CaseBlock CB(Condition, BOp->getOperand(0),
1145 BOp->getOperand(1), NULL, TBB, FBB, CurBB);
1146 SwitchCases.push_back(CB);
1151 // Create a CaseBlock record representing this branch.
1152 CaseBlock CB(ISD::SETEQ, Cond, DAG.getContext()->getConstantIntTrue(),
1153 NULL, TBB, FBB, CurBB);
1154 SwitchCases.push_back(CB);
1157 /// FindMergedConditions - If Cond is an expression like
1158 void SelectionDAGLowering::FindMergedConditions(Value *Cond,
1159 MachineBasicBlock *TBB,
1160 MachineBasicBlock *FBB,
1161 MachineBasicBlock *CurBB,
1163 // If this node is not part of the or/and tree, emit it as a branch.
1164 Instruction *BOp = dyn_cast<Instruction>(Cond);
1165 if (!BOp || !(isa<BinaryOperator>(BOp) || isa<CmpInst>(BOp)) ||
1166 (unsigned)BOp->getOpcode() != Opc || !BOp->hasOneUse() ||
1167 BOp->getParent() != CurBB->getBasicBlock() ||
1168 !InBlock(BOp->getOperand(0), CurBB->getBasicBlock()) ||
1169 !InBlock(BOp->getOperand(1), CurBB->getBasicBlock())) {
1170 EmitBranchForMergedCondition(Cond, TBB, FBB, CurBB);
1174 // Create TmpBB after CurBB.
1175 MachineFunction::iterator BBI = CurBB;
1176 MachineFunction &MF = DAG.getMachineFunction();
1177 MachineBasicBlock *TmpBB = MF.CreateMachineBasicBlock(CurBB->getBasicBlock());
1178 CurBB->getParent()->insert(++BBI, TmpBB);
1180 if (Opc == Instruction::Or) {
1181 // Codegen X | Y as:
1189 // Emit the LHS condition.
1190 FindMergedConditions(BOp->getOperand(0), TBB, TmpBB, CurBB, Opc);
1192 // Emit the RHS condition into TmpBB.
1193 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, Opc);
1195 assert(Opc == Instruction::And && "Unknown merge op!");
1196 // Codegen X & Y as:
1203 // This requires creation of TmpBB after CurBB.
1205 // Emit the LHS condition.
1206 FindMergedConditions(BOp->getOperand(0), TmpBB, FBB, CurBB, Opc);
1208 // Emit the RHS condition into TmpBB.
1209 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, Opc);
1213 /// If the set of cases should be emitted as a series of branches, return true.
1214 /// If we should emit this as a bunch of and/or'd together conditions, return
1217 SelectionDAGLowering::ShouldEmitAsBranches(const std::vector<CaseBlock> &Cases){
1218 if (Cases.size() != 2) return true;
1220 // If this is two comparisons of the same values or'd or and'd together, they
1221 // will get folded into a single comparison, so don't emit two blocks.
1222 if ((Cases[0].CmpLHS == Cases[1].CmpLHS &&
1223 Cases[0].CmpRHS == Cases[1].CmpRHS) ||
1224 (Cases[0].CmpRHS == Cases[1].CmpLHS &&
1225 Cases[0].CmpLHS == Cases[1].CmpRHS)) {
1232 void SelectionDAGLowering::visitBr(BranchInst &I) {
1233 // Update machine-CFG edges.
1234 MachineBasicBlock *Succ0MBB = FuncInfo.MBBMap[I.getSuccessor(0)];
1236 // Figure out which block is immediately after the current one.
1237 MachineBasicBlock *NextBlock = 0;
1238 MachineFunction::iterator BBI = CurMBB;
1239 if (++BBI != CurMBB->getParent()->end())
1242 if (I.isUnconditional()) {
1243 // Update machine-CFG edges.
1244 CurMBB->addSuccessor(Succ0MBB);
1246 // If this is not a fall-through branch, emit the branch.
1247 if (Succ0MBB != NextBlock)
1248 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(),
1249 MVT::Other, getControlRoot(),
1250 DAG.getBasicBlock(Succ0MBB)));
1254 // If this condition is one of the special cases we handle, do special stuff
1256 Value *CondVal = I.getCondition();
1257 MachineBasicBlock *Succ1MBB = FuncInfo.MBBMap[I.getSuccessor(1)];
1259 // If this is a series of conditions that are or'd or and'd together, emit
1260 // this as a sequence of branches instead of setcc's with and/or operations.
1261 // For example, instead of something like:
1274 if (BinaryOperator *BOp = dyn_cast<BinaryOperator>(CondVal)) {
1275 if (BOp->hasOneUse() &&
1276 (BOp->getOpcode() == Instruction::And ||
1277 BOp->getOpcode() == Instruction::Or)) {
1278 FindMergedConditions(BOp, Succ0MBB, Succ1MBB, CurMBB, BOp->getOpcode());
1279 // If the compares in later blocks need to use values not currently
1280 // exported from this block, export them now. This block should always
1281 // be the first entry.
1282 assert(SwitchCases[0].ThisBB == CurMBB && "Unexpected lowering!");
1284 // Allow some cases to be rejected.
1285 if (ShouldEmitAsBranches(SwitchCases)) {
1286 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i) {
1287 ExportFromCurrentBlock(SwitchCases[i].CmpLHS);
1288 ExportFromCurrentBlock(SwitchCases[i].CmpRHS);
1291 // Emit the branch for this block.
1292 visitSwitchCase(SwitchCases[0]);
1293 SwitchCases.erase(SwitchCases.begin());
1297 // Okay, we decided not to do this, remove any inserted MBB's and clear
1299 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i)
1300 CurMBB->getParent()->erase(SwitchCases[i].ThisBB);
1302 SwitchCases.clear();
1306 // Create a CaseBlock record representing this branch.
1307 CaseBlock CB(ISD::SETEQ, CondVal, DAG.getContext()->getConstantIntTrue(),
1308 NULL, Succ0MBB, Succ1MBB, CurMBB);
1309 // Use visitSwitchCase to actually insert the fast branch sequence for this
1311 visitSwitchCase(CB);
1314 /// visitSwitchCase - Emits the necessary code to represent a single node in
1315 /// the binary search tree resulting from lowering a switch instruction.
1316 void SelectionDAGLowering::visitSwitchCase(CaseBlock &CB) {
1318 SDValue CondLHS = getValue(CB.CmpLHS);
1319 DebugLoc dl = getCurDebugLoc();
1321 // Build the setcc now.
1322 if (CB.CmpMHS == NULL) {
1323 // Fold "(X == true)" to X and "(X == false)" to !X to
1324 // handle common cases produced by branch lowering.
1325 if (CB.CmpRHS == DAG.getContext()->getConstantIntTrue() &&
1326 CB.CC == ISD::SETEQ)
1328 else if (CB.CmpRHS == DAG.getContext()->getConstantIntFalse() &&
1329 CB.CC == ISD::SETEQ) {
1330 SDValue True = DAG.getConstant(1, CondLHS.getValueType());
1331 Cond = DAG.getNode(ISD::XOR, dl, CondLHS.getValueType(), CondLHS, True);
1333 Cond = DAG.getSetCC(dl, MVT::i1, CondLHS, getValue(CB.CmpRHS), CB.CC);
1335 assert(CB.CC == ISD::SETLE && "Can handle only LE ranges now");
1337 const APInt& Low = cast<ConstantInt>(CB.CmpLHS)->getValue();
1338 const APInt& High = cast<ConstantInt>(CB.CmpRHS)->getValue();
1340 SDValue CmpOp = getValue(CB.CmpMHS);
1341 MVT VT = CmpOp.getValueType();
1343 if (cast<ConstantInt>(CB.CmpLHS)->isMinValue(true)) {
1344 Cond = DAG.getSetCC(dl, MVT::i1, CmpOp, DAG.getConstant(High, VT),
1347 SDValue SUB = DAG.getNode(ISD::SUB, dl,
1348 VT, CmpOp, DAG.getConstant(Low, VT));
1349 Cond = DAG.getSetCC(dl, MVT::i1, SUB,
1350 DAG.getConstant(High-Low, VT), ISD::SETULE);
1354 // Update successor info
1355 CurMBB->addSuccessor(CB.TrueBB);
1356 CurMBB->addSuccessor(CB.FalseBB);
1358 // Set NextBlock to be the MBB immediately after the current one, if any.
1359 // This is used to avoid emitting unnecessary branches to the next block.
1360 MachineBasicBlock *NextBlock = 0;
1361 MachineFunction::iterator BBI = CurMBB;
1362 if (++BBI != CurMBB->getParent()->end())
1365 // If the lhs block is the next block, invert the condition so that we can
1366 // fall through to the lhs instead of the rhs block.
1367 if (CB.TrueBB == NextBlock) {
1368 std::swap(CB.TrueBB, CB.FalseBB);
1369 SDValue True = DAG.getConstant(1, Cond.getValueType());
1370 Cond = DAG.getNode(ISD::XOR, dl, Cond.getValueType(), Cond, True);
1372 SDValue BrCond = DAG.getNode(ISD::BRCOND, dl,
1373 MVT::Other, getControlRoot(), Cond,
1374 DAG.getBasicBlock(CB.TrueBB));
1376 // If the branch was constant folded, fix up the CFG.
1377 if (BrCond.getOpcode() == ISD::BR) {
1378 CurMBB->removeSuccessor(CB.FalseBB);
1379 DAG.setRoot(BrCond);
1381 // Otherwise, go ahead and insert the false branch.
1382 if (BrCond == getControlRoot())
1383 CurMBB->removeSuccessor(CB.TrueBB);
1385 if (CB.FalseBB == NextBlock)
1386 DAG.setRoot(BrCond);
1388 DAG.setRoot(DAG.getNode(ISD::BR, dl, MVT::Other, BrCond,
1389 DAG.getBasicBlock(CB.FalseBB)));
1393 /// visitJumpTable - Emit JumpTable node in the current MBB
1394 void SelectionDAGLowering::visitJumpTable(JumpTable &JT) {
1395 // Emit the code for the jump table
1396 assert(JT.Reg != -1U && "Should lower JT Header first!");
1397 MVT PTy = TLI.getPointerTy();
1398 SDValue Index = DAG.getCopyFromReg(getControlRoot(), getCurDebugLoc(),
1400 SDValue Table = DAG.getJumpTable(JT.JTI, PTy);
1401 DAG.setRoot(DAG.getNode(ISD::BR_JT, getCurDebugLoc(),
1402 MVT::Other, Index.getValue(1),
1406 /// visitJumpTableHeader - This function emits necessary code to produce index
1407 /// in the JumpTable from switch case.
1408 void SelectionDAGLowering::visitJumpTableHeader(JumpTable &JT,
1409 JumpTableHeader &JTH) {
1410 // Subtract the lowest switch case value from the value being switched on and
1411 // conditional branch to default mbb if the result is greater than the
1412 // difference between smallest and largest cases.
1413 SDValue SwitchOp = getValue(JTH.SValue);
1414 MVT VT = SwitchOp.getValueType();
1415 SDValue SUB = DAG.getNode(ISD::SUB, getCurDebugLoc(), VT, SwitchOp,
1416 DAG.getConstant(JTH.First, VT));
1418 // The SDNode we just created, which holds the value being switched on minus
1419 // the the smallest case value, needs to be copied to a virtual register so it
1420 // can be used as an index into the jump table in a subsequent basic block.
1421 // This value may be smaller or larger than the target's pointer type, and
1422 // therefore require extension or truncating.
1423 if (VT.bitsGT(TLI.getPointerTy()))
1424 SwitchOp = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(),
1425 TLI.getPointerTy(), SUB);
1427 SwitchOp = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(),
1428 TLI.getPointerTy(), SUB);
1430 unsigned JumpTableReg = FuncInfo.MakeReg(TLI.getPointerTy());
1431 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), getCurDebugLoc(),
1432 JumpTableReg, SwitchOp);
1433 JT.Reg = JumpTableReg;
1435 // Emit the range check for the jump table, and branch to the default block
1436 // for the switch statement if the value being switched on exceeds the largest
1437 // case in the switch.
1438 SDValue CMP = DAG.getSetCC(getCurDebugLoc(),
1439 TLI.getSetCCResultType(SUB.getValueType()), SUB,
1440 DAG.getConstant(JTH.Last-JTH.First,VT),
1443 // Set NextBlock to be the MBB immediately after the current one, if any.
1444 // This is used to avoid emitting unnecessary branches to the next block.
1445 MachineBasicBlock *NextBlock = 0;
1446 MachineFunction::iterator BBI = CurMBB;
1447 if (++BBI != CurMBB->getParent()->end())
1450 SDValue BrCond = DAG.getNode(ISD::BRCOND, getCurDebugLoc(),
1451 MVT::Other, CopyTo, CMP,
1452 DAG.getBasicBlock(JT.Default));
1454 if (JT.MBB == NextBlock)
1455 DAG.setRoot(BrCond);
1457 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, BrCond,
1458 DAG.getBasicBlock(JT.MBB)));
1461 /// visitBitTestHeader - This function emits necessary code to produce value
1462 /// suitable for "bit tests"
1463 void SelectionDAGLowering::visitBitTestHeader(BitTestBlock &B) {
1464 // Subtract the minimum value
1465 SDValue SwitchOp = getValue(B.SValue);
1466 MVT VT = SwitchOp.getValueType();
1467 SDValue SUB = DAG.getNode(ISD::SUB, getCurDebugLoc(), VT, SwitchOp,
1468 DAG.getConstant(B.First, VT));
1471 SDValue RangeCmp = DAG.getSetCC(getCurDebugLoc(),
1472 TLI.getSetCCResultType(SUB.getValueType()),
1473 SUB, DAG.getConstant(B.Range, VT),
1477 if (VT.bitsGT(TLI.getPointerTy()))
1478 ShiftOp = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(),
1479 TLI.getPointerTy(), SUB);
1481 ShiftOp = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(),
1482 TLI.getPointerTy(), SUB);
1484 B.Reg = FuncInfo.MakeReg(TLI.getPointerTy());
1485 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), getCurDebugLoc(),
1488 // Set NextBlock to be the MBB immediately after the current one, if any.
1489 // This is used to avoid emitting unnecessary branches to the next block.
1490 MachineBasicBlock *NextBlock = 0;
1491 MachineFunction::iterator BBI = CurMBB;
1492 if (++BBI != CurMBB->getParent()->end())
1495 MachineBasicBlock* MBB = B.Cases[0].ThisBB;
1497 CurMBB->addSuccessor(B.Default);
1498 CurMBB->addSuccessor(MBB);
1500 SDValue BrRange = DAG.getNode(ISD::BRCOND, getCurDebugLoc(),
1501 MVT::Other, CopyTo, RangeCmp,
1502 DAG.getBasicBlock(B.Default));
1504 if (MBB == NextBlock)
1505 DAG.setRoot(BrRange);
1507 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, CopyTo,
1508 DAG.getBasicBlock(MBB)));
1511 /// visitBitTestCase - this function produces one "bit test"
1512 void SelectionDAGLowering::visitBitTestCase(MachineBasicBlock* NextMBB,
1515 // Make desired shift
1516 SDValue ShiftOp = DAG.getCopyFromReg(getControlRoot(), getCurDebugLoc(), Reg,
1517 TLI.getPointerTy());
1518 SDValue SwitchVal = DAG.getNode(ISD::SHL, getCurDebugLoc(),
1520 DAG.getConstant(1, TLI.getPointerTy()),
1523 // Emit bit tests and jumps
1524 SDValue AndOp = DAG.getNode(ISD::AND, getCurDebugLoc(),
1525 TLI.getPointerTy(), SwitchVal,
1526 DAG.getConstant(B.Mask, TLI.getPointerTy()));
1527 SDValue AndCmp = DAG.getSetCC(getCurDebugLoc(),
1528 TLI.getSetCCResultType(AndOp.getValueType()),
1529 AndOp, DAG.getConstant(0, TLI.getPointerTy()),
1532 CurMBB->addSuccessor(B.TargetBB);
1533 CurMBB->addSuccessor(NextMBB);
1535 SDValue BrAnd = DAG.getNode(ISD::BRCOND, getCurDebugLoc(),
1536 MVT::Other, getControlRoot(),
1537 AndCmp, DAG.getBasicBlock(B.TargetBB));
1539 // Set NextBlock to be the MBB immediately after the current one, if any.
1540 // This is used to avoid emitting unnecessary branches to the next block.
1541 MachineBasicBlock *NextBlock = 0;
1542 MachineFunction::iterator BBI = CurMBB;
1543 if (++BBI != CurMBB->getParent()->end())
1546 if (NextMBB == NextBlock)
1549 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, BrAnd,
1550 DAG.getBasicBlock(NextMBB)));
1553 void SelectionDAGLowering::visitInvoke(InvokeInst &I) {
1554 // Retrieve successors.
1555 MachineBasicBlock *Return = FuncInfo.MBBMap[I.getSuccessor(0)];
1556 MachineBasicBlock *LandingPad = FuncInfo.MBBMap[I.getSuccessor(1)];
1558 const Value *Callee(I.getCalledValue());
1559 if (isa<InlineAsm>(Callee))
1562 LowerCallTo(&I, getValue(Callee), false, LandingPad);
1564 // If the value of the invoke is used outside of its defining block, make it
1565 // available as a virtual register.
1566 CopyToExportRegsIfNeeded(&I);
1568 // Update successor info
1569 CurMBB->addSuccessor(Return);
1570 CurMBB->addSuccessor(LandingPad);
1572 // Drop into normal successor.
1573 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(),
1574 MVT::Other, getControlRoot(),
1575 DAG.getBasicBlock(Return)));
1578 void SelectionDAGLowering::visitUnwind(UnwindInst &I) {
1581 /// handleSmallSwitchCaseRange - Emit a series of specific tests (suitable for
1582 /// small case ranges).
1583 bool SelectionDAGLowering::handleSmallSwitchRange(CaseRec& CR,
1584 CaseRecVector& WorkList,
1586 MachineBasicBlock* Default) {
1587 Case& BackCase = *(CR.Range.second-1);
1589 // Size is the number of Cases represented by this range.
1590 size_t Size = CR.Range.second - CR.Range.first;
1594 // Get the MachineFunction which holds the current MBB. This is used when
1595 // inserting any additional MBBs necessary to represent the switch.
1596 MachineFunction *CurMF = CurMBB->getParent();
1598 // Figure out which block is immediately after the current one.
1599 MachineBasicBlock *NextBlock = 0;
1600 MachineFunction::iterator BBI = CR.CaseBB;
1602 if (++BBI != CurMBB->getParent()->end())
1605 // TODO: If any two of the cases has the same destination, and if one value
1606 // is the same as the other, but has one bit unset that the other has set,
1607 // use bit manipulation to do two compares at once. For example:
1608 // "if (X == 6 || X == 4)" -> "if ((X|2) == 6)"
1610 // Rearrange the case blocks so that the last one falls through if possible.
1611 if (NextBlock && Default != NextBlock && BackCase.BB != NextBlock) {
1612 // The last case block won't fall through into 'NextBlock' if we emit the
1613 // branches in this order. See if rearranging a case value would help.
1614 for (CaseItr I = CR.Range.first, E = CR.Range.second-1; I != E; ++I) {
1615 if (I->BB == NextBlock) {
1616 std::swap(*I, BackCase);
1622 // Create a CaseBlock record representing a conditional branch to
1623 // the Case's target mbb if the value being switched on SV is equal
1625 MachineBasicBlock *CurBlock = CR.CaseBB;
1626 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++I) {
1627 MachineBasicBlock *FallThrough;
1629 FallThrough = CurMF->CreateMachineBasicBlock(CurBlock->getBasicBlock());
1630 CurMF->insert(BBI, FallThrough);
1632 // Put SV in a virtual register to make it available from the new blocks.
1633 ExportFromCurrentBlock(SV);
1635 // If the last case doesn't match, go to the default block.
1636 FallThrough = Default;
1639 Value *RHS, *LHS, *MHS;
1641 if (I->High == I->Low) {
1642 // This is just small small case range :) containing exactly 1 case
1644 LHS = SV; RHS = I->High; MHS = NULL;
1647 LHS = I->Low; MHS = SV; RHS = I->High;
1649 CaseBlock CB(CC, LHS, RHS, MHS, I->BB, FallThrough, CurBlock);
1651 // If emitting the first comparison, just call visitSwitchCase to emit the
1652 // code into the current block. Otherwise, push the CaseBlock onto the
1653 // vector to be later processed by SDISel, and insert the node's MBB
1654 // before the next MBB.
1655 if (CurBlock == CurMBB)
1656 visitSwitchCase(CB);
1658 SwitchCases.push_back(CB);
1660 CurBlock = FallThrough;
1666 static inline bool areJTsAllowed(const TargetLowering &TLI) {
1667 return !DisableJumpTables &&
1668 (TLI.isOperationLegalOrCustom(ISD::BR_JT, MVT::Other) ||
1669 TLI.isOperationLegalOrCustom(ISD::BRIND, MVT::Other));
1672 static APInt ComputeRange(const APInt &First, const APInt &Last) {
1673 APInt LastExt(Last), FirstExt(First);
1674 uint32_t BitWidth = std::max(Last.getBitWidth(), First.getBitWidth()) + 1;
1675 LastExt.sext(BitWidth); FirstExt.sext(BitWidth);
1676 return (LastExt - FirstExt + 1ULL);
1679 /// handleJTSwitchCase - Emit jumptable for current switch case range
1680 bool SelectionDAGLowering::handleJTSwitchCase(CaseRec& CR,
1681 CaseRecVector& WorkList,
1683 MachineBasicBlock* Default) {
1684 Case& FrontCase = *CR.Range.first;
1685 Case& BackCase = *(CR.Range.second-1);
1687 const APInt& First = cast<ConstantInt>(FrontCase.Low)->getValue();
1688 const APInt& Last = cast<ConstantInt>(BackCase.High)->getValue();
1691 for (CaseItr I = CR.Range.first, E = CR.Range.second;
1695 if (!areJTsAllowed(TLI) || TSize <= 3)
1698 APInt Range = ComputeRange(First, Last);
1699 double Density = (double)TSize / Range.roundToDouble();
1703 DEBUG(errs() << "Lowering jump table\n"
1704 << "First entry: " << First << ". Last entry: " << Last << '\n'
1705 << "Range: " << Range
1706 << "Size: " << TSize << ". Density: " << Density << "\n\n");
1708 // Get the MachineFunction which holds the current MBB. This is used when
1709 // inserting any additional MBBs necessary to represent the switch.
1710 MachineFunction *CurMF = CurMBB->getParent();
1712 // Figure out which block is immediately after the current one.
1713 MachineBasicBlock *NextBlock = 0;
1714 MachineFunction::iterator BBI = CR.CaseBB;
1716 if (++BBI != CurMBB->getParent()->end())
1719 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
1721 // Create a new basic block to hold the code for loading the address
1722 // of the jump table, and jumping to it. Update successor information;
1723 // we will either branch to the default case for the switch, or the jump
1725 MachineBasicBlock *JumpTableBB = CurMF->CreateMachineBasicBlock(LLVMBB);
1726 CurMF->insert(BBI, JumpTableBB);
1727 CR.CaseBB->addSuccessor(Default);
1728 CR.CaseBB->addSuccessor(JumpTableBB);
1730 // Build a vector of destination BBs, corresponding to each target
1731 // of the jump table. If the value of the jump table slot corresponds to
1732 // a case statement, push the case's BB onto the vector, otherwise, push
1734 std::vector<MachineBasicBlock*> DestBBs;
1736 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++TEI) {
1737 const APInt& Low = cast<ConstantInt>(I->Low)->getValue();
1738 const APInt& High = cast<ConstantInt>(I->High)->getValue();
1740 if (Low.sle(TEI) && TEI.sle(High)) {
1741 DestBBs.push_back(I->BB);
1745 DestBBs.push_back(Default);
1749 // Update successor info. Add one edge to each unique successor.
1750 BitVector SuccsHandled(CR.CaseBB->getParent()->getNumBlockIDs());
1751 for (std::vector<MachineBasicBlock*>::iterator I = DestBBs.begin(),
1752 E = DestBBs.end(); I != E; ++I) {
1753 if (!SuccsHandled[(*I)->getNumber()]) {
1754 SuccsHandled[(*I)->getNumber()] = true;
1755 JumpTableBB->addSuccessor(*I);
1759 // Create a jump table index for this jump table, or return an existing
1761 unsigned JTI = CurMF->getJumpTableInfo()->getJumpTableIndex(DestBBs);
1763 // Set the jump table information so that we can codegen it as a second
1764 // MachineBasicBlock
1765 JumpTable JT(-1U, JTI, JumpTableBB, Default);
1766 JumpTableHeader JTH(First, Last, SV, CR.CaseBB, (CR.CaseBB == CurMBB));
1767 if (CR.CaseBB == CurMBB)
1768 visitJumpTableHeader(JT, JTH);
1770 JTCases.push_back(JumpTableBlock(JTH, JT));
1775 /// handleBTSplitSwitchCase - emit comparison and split binary search tree into
1777 bool SelectionDAGLowering::handleBTSplitSwitchCase(CaseRec& CR,
1778 CaseRecVector& WorkList,
1780 MachineBasicBlock* Default) {
1781 // Get the MachineFunction which holds the current MBB. This is used when
1782 // inserting any additional MBBs necessary to represent the switch.
1783 MachineFunction *CurMF = CurMBB->getParent();
1785 // Figure out which block is immediately after the current one.
1786 MachineBasicBlock *NextBlock = 0;
1787 MachineFunction::iterator BBI = CR.CaseBB;
1789 if (++BBI != CurMBB->getParent()->end())
1792 Case& FrontCase = *CR.Range.first;
1793 Case& BackCase = *(CR.Range.second-1);
1794 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
1796 // Size is the number of Cases represented by this range.
1797 unsigned Size = CR.Range.second - CR.Range.first;
1799 const APInt& First = cast<ConstantInt>(FrontCase.Low)->getValue();
1800 const APInt& Last = cast<ConstantInt>(BackCase.High)->getValue();
1802 CaseItr Pivot = CR.Range.first + Size/2;
1804 // Select optimal pivot, maximizing sum density of LHS and RHS. This will
1805 // (heuristically) allow us to emit JumpTable's later.
1807 for (CaseItr I = CR.Range.first, E = CR.Range.second;
1811 size_t LSize = FrontCase.size();
1812 size_t RSize = TSize-LSize;
1813 DEBUG(errs() << "Selecting best pivot: \n"
1814 << "First: " << First << ", Last: " << Last <<'\n'
1815 << "LSize: " << LSize << ", RSize: " << RSize << '\n');
1816 for (CaseItr I = CR.Range.first, J=I+1, E = CR.Range.second;
1818 const APInt& LEnd = cast<ConstantInt>(I->High)->getValue();
1819 const APInt& RBegin = cast<ConstantInt>(J->Low)->getValue();
1820 APInt Range = ComputeRange(LEnd, RBegin);
1821 assert((Range - 2ULL).isNonNegative() &&
1822 "Invalid case distance");
1823 double LDensity = (double)LSize / (LEnd - First + 1ULL).roundToDouble();
1824 double RDensity = (double)RSize / (Last - RBegin + 1ULL).roundToDouble();
1825 double Metric = Range.logBase2()*(LDensity+RDensity);
1826 // Should always split in some non-trivial place
1827 DEBUG(errs() <<"=>Step\n"
1828 << "LEnd: " << LEnd << ", RBegin: " << RBegin << '\n'
1829 << "LDensity: " << LDensity
1830 << ", RDensity: " << RDensity << '\n'
1831 << "Metric: " << Metric << '\n');
1832 if (FMetric < Metric) {
1835 DEBUG(errs() << "Current metric set to: " << FMetric << '\n');
1841 if (areJTsAllowed(TLI)) {
1842 // If our case is dense we *really* should handle it earlier!
1843 assert((FMetric > 0) && "Should handle dense range earlier!");
1845 Pivot = CR.Range.first + Size/2;
1848 CaseRange LHSR(CR.Range.first, Pivot);
1849 CaseRange RHSR(Pivot, CR.Range.second);
1850 Constant *C = Pivot->Low;
1851 MachineBasicBlock *FalseBB = 0, *TrueBB = 0;
1853 // We know that we branch to the LHS if the Value being switched on is
1854 // less than the Pivot value, C. We use this to optimize our binary
1855 // tree a bit, by recognizing that if SV is greater than or equal to the
1856 // LHS's Case Value, and that Case Value is exactly one less than the
1857 // Pivot's Value, then we can branch directly to the LHS's Target,
1858 // rather than creating a leaf node for it.
1859 if ((LHSR.second - LHSR.first) == 1 &&
1860 LHSR.first->High == CR.GE &&
1861 cast<ConstantInt>(C)->getValue() ==
1862 (cast<ConstantInt>(CR.GE)->getValue() + 1LL)) {
1863 TrueBB = LHSR.first->BB;
1865 TrueBB = CurMF->CreateMachineBasicBlock(LLVMBB);
1866 CurMF->insert(BBI, TrueBB);
1867 WorkList.push_back(CaseRec(TrueBB, C, CR.GE, LHSR));
1869 // Put SV in a virtual register to make it available from the new blocks.
1870 ExportFromCurrentBlock(SV);
1873 // Similar to the optimization above, if the Value being switched on is
1874 // known to be less than the Constant CR.LT, and the current Case Value
1875 // is CR.LT - 1, then we can branch directly to the target block for
1876 // the current Case Value, rather than emitting a RHS leaf node for it.
1877 if ((RHSR.second - RHSR.first) == 1 && CR.LT &&
1878 cast<ConstantInt>(RHSR.first->Low)->getValue() ==
1879 (cast<ConstantInt>(CR.LT)->getValue() - 1LL)) {
1880 FalseBB = RHSR.first->BB;
1882 FalseBB = CurMF->CreateMachineBasicBlock(LLVMBB);
1883 CurMF->insert(BBI, FalseBB);
1884 WorkList.push_back(CaseRec(FalseBB,CR.LT,C,RHSR));
1886 // Put SV in a virtual register to make it available from the new blocks.
1887 ExportFromCurrentBlock(SV);
1890 // Create a CaseBlock record representing a conditional branch to
1891 // the LHS node if the value being switched on SV is less than C.
1892 // Otherwise, branch to LHS.
1893 CaseBlock CB(ISD::SETLT, SV, C, NULL, TrueBB, FalseBB, CR.CaseBB);
1895 if (CR.CaseBB == CurMBB)
1896 visitSwitchCase(CB);
1898 SwitchCases.push_back(CB);
1903 /// handleBitTestsSwitchCase - if current case range has few destination and
1904 /// range span less, than machine word bitwidth, encode case range into series
1905 /// of masks and emit bit tests with these masks.
1906 bool SelectionDAGLowering::handleBitTestsSwitchCase(CaseRec& CR,
1907 CaseRecVector& WorkList,
1909 MachineBasicBlock* Default){
1910 unsigned IntPtrBits = TLI.getPointerTy().getSizeInBits();
1912 Case& FrontCase = *CR.Range.first;
1913 Case& BackCase = *(CR.Range.second-1);
1915 // Get the MachineFunction which holds the current MBB. This is used when
1916 // inserting any additional MBBs necessary to represent the switch.
1917 MachineFunction *CurMF = CurMBB->getParent();
1919 // If target does not have legal shift left, do not emit bit tests at all.
1920 if (!TLI.isOperationLegal(ISD::SHL, TLI.getPointerTy()))
1924 for (CaseItr I = CR.Range.first, E = CR.Range.second;
1926 // Single case counts one, case range - two.
1927 numCmps += (I->Low == I->High ? 1 : 2);
1930 // Count unique destinations
1931 SmallSet<MachineBasicBlock*, 4> Dests;
1932 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) {
1933 Dests.insert(I->BB);
1934 if (Dests.size() > 3)
1935 // Don't bother the code below, if there are too much unique destinations
1938 DEBUG(errs() << "Total number of unique destinations: " << Dests.size() << '\n'
1939 << "Total number of comparisons: " << numCmps << '\n');
1941 // Compute span of values.
1942 const APInt& minValue = cast<ConstantInt>(FrontCase.Low)->getValue();
1943 const APInt& maxValue = cast<ConstantInt>(BackCase.High)->getValue();
1944 APInt cmpRange = maxValue - minValue;
1946 DEBUG(errs() << "Compare range: " << cmpRange << '\n'
1947 << "Low bound: " << minValue << '\n'
1948 << "High bound: " << maxValue << '\n');
1950 if (cmpRange.uge(APInt(cmpRange.getBitWidth(), IntPtrBits)) ||
1951 (!(Dests.size() == 1 && numCmps >= 3) &&
1952 !(Dests.size() == 2 && numCmps >= 5) &&
1953 !(Dests.size() >= 3 && numCmps >= 6)))
1956 DEBUG(errs() << "Emitting bit tests\n");
1957 APInt lowBound = APInt::getNullValue(cmpRange.getBitWidth());
1959 // Optimize the case where all the case values fit in a
1960 // word without having to subtract minValue. In this case,
1961 // we can optimize away the subtraction.
1962 if (minValue.isNonNegative() &&
1963 maxValue.slt(APInt(maxValue.getBitWidth(), IntPtrBits))) {
1964 cmpRange = maxValue;
1966 lowBound = minValue;
1969 CaseBitsVector CasesBits;
1970 unsigned i, count = 0;
1972 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) {
1973 MachineBasicBlock* Dest = I->BB;
1974 for (i = 0; i < count; ++i)
1975 if (Dest == CasesBits[i].BB)
1979 assert((count < 3) && "Too much destinations to test!");
1980 CasesBits.push_back(CaseBits(0, Dest, 0));
1984 const APInt& lowValue = cast<ConstantInt>(I->Low)->getValue();
1985 const APInt& highValue = cast<ConstantInt>(I->High)->getValue();
1987 uint64_t lo = (lowValue - lowBound).getZExtValue();
1988 uint64_t hi = (highValue - lowBound).getZExtValue();
1990 for (uint64_t j = lo; j <= hi; j++) {
1991 CasesBits[i].Mask |= 1ULL << j;
1992 CasesBits[i].Bits++;
1996 std::sort(CasesBits.begin(), CasesBits.end(), CaseBitsCmp());
2000 // Figure out which block is immediately after the current one.
2001 MachineFunction::iterator BBI = CR.CaseBB;
2004 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
2006 DEBUG(errs() << "Cases:\n");
2007 for (unsigned i = 0, e = CasesBits.size(); i!=e; ++i) {
2008 DEBUG(errs() << "Mask: " << CasesBits[i].Mask
2009 << ", Bits: " << CasesBits[i].Bits
2010 << ", BB: " << CasesBits[i].BB << '\n');
2012 MachineBasicBlock *CaseBB = CurMF->CreateMachineBasicBlock(LLVMBB);
2013 CurMF->insert(BBI, CaseBB);
2014 BTC.push_back(BitTestCase(CasesBits[i].Mask,
2018 // Put SV in a virtual register to make it available from the new blocks.
2019 ExportFromCurrentBlock(SV);
2022 BitTestBlock BTB(lowBound, cmpRange, SV,
2023 -1U, (CR.CaseBB == CurMBB),
2024 CR.CaseBB, Default, BTC);
2026 if (CR.CaseBB == CurMBB)
2027 visitBitTestHeader(BTB);
2029 BitTestCases.push_back(BTB);
2035 /// Clusterify - Transform simple list of Cases into list of CaseRange's
2036 size_t SelectionDAGLowering::Clusterify(CaseVector& Cases,
2037 const SwitchInst& SI) {
2040 // Start with "simple" cases
2041 for (size_t i = 1; i < SI.getNumSuccessors(); ++i) {
2042 MachineBasicBlock *SMBB = FuncInfo.MBBMap[SI.getSuccessor(i)];
2043 Cases.push_back(Case(SI.getSuccessorValue(i),
2044 SI.getSuccessorValue(i),
2047 std::sort(Cases.begin(), Cases.end(), CaseCmp());
2049 // Merge case into clusters
2050 if (Cases.size() >= 2)
2051 // Must recompute end() each iteration because it may be
2052 // invalidated by erase if we hold on to it
2053 for (CaseItr I = Cases.begin(), J = ++(Cases.begin()); J != Cases.end(); ) {
2054 const APInt& nextValue = cast<ConstantInt>(J->Low)->getValue();
2055 const APInt& currentValue = cast<ConstantInt>(I->High)->getValue();
2056 MachineBasicBlock* nextBB = J->BB;
2057 MachineBasicBlock* currentBB = I->BB;
2059 // If the two neighboring cases go to the same destination, merge them
2060 // into a single case.
2061 if ((nextValue - currentValue == 1) && (currentBB == nextBB)) {
2069 for (CaseItr I=Cases.begin(), E=Cases.end(); I!=E; ++I, ++numCmps) {
2070 if (I->Low != I->High)
2071 // A range counts double, since it requires two compares.
2078 void SelectionDAGLowering::visitSwitch(SwitchInst &SI) {
2079 // Figure out which block is immediately after the current one.
2080 MachineBasicBlock *NextBlock = 0;
2081 MachineFunction::iterator BBI = CurMBB;
2083 MachineBasicBlock *Default = FuncInfo.MBBMap[SI.getDefaultDest()];
2085 // If there is only the default destination, branch to it if it is not the
2086 // next basic block. Otherwise, just fall through.
2087 if (SI.getNumOperands() == 2) {
2088 // Update machine-CFG edges.
2090 // If this is not a fall-through branch, emit the branch.
2091 CurMBB->addSuccessor(Default);
2092 if (Default != NextBlock)
2093 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(),
2094 MVT::Other, getControlRoot(),
2095 DAG.getBasicBlock(Default)));
2099 // If there are any non-default case statements, create a vector of Cases
2100 // representing each one, and sort the vector so that we can efficiently
2101 // create a binary search tree from them.
2103 size_t numCmps = Clusterify(Cases, SI);
2104 DEBUG(errs() << "Clusterify finished. Total clusters: " << Cases.size()
2105 << ". Total compares: " << numCmps << '\n');
2108 // Get the Value to be switched on and default basic blocks, which will be
2109 // inserted into CaseBlock records, representing basic blocks in the binary
2111 Value *SV = SI.getOperand(0);
2113 // Push the initial CaseRec onto the worklist
2114 CaseRecVector WorkList;
2115 WorkList.push_back(CaseRec(CurMBB,0,0,CaseRange(Cases.begin(),Cases.end())));
2117 while (!WorkList.empty()) {
2118 // Grab a record representing a case range to process off the worklist
2119 CaseRec CR = WorkList.back();
2120 WorkList.pop_back();
2122 if (handleBitTestsSwitchCase(CR, WorkList, SV, Default))
2125 // If the range has few cases (two or less) emit a series of specific
2127 if (handleSmallSwitchRange(CR, WorkList, SV, Default))
2130 // If the switch has more than 5 blocks, and at least 40% dense, and the
2131 // target supports indirect branches, then emit a jump table rather than
2132 // lowering the switch to a binary tree of conditional branches.
2133 if (handleJTSwitchCase(CR, WorkList, SV, Default))
2136 // Emit binary tree. We need to pick a pivot, and push left and right ranges
2137 // onto the worklist. Leafs are handled via handleSmallSwitchRange() call.
2138 handleBTSplitSwitchCase(CR, WorkList, SV, Default);
2143 void SelectionDAGLowering::visitFSub(User &I) {
2144 // -0.0 - X --> fneg
2145 const Type *Ty = I.getType();
2146 if (isa<VectorType>(Ty)) {
2147 if (ConstantVector *CV = dyn_cast<ConstantVector>(I.getOperand(0))) {
2148 const VectorType *DestTy = cast<VectorType>(I.getType());
2149 const Type *ElTy = DestTy->getElementType();
2150 unsigned VL = DestTy->getNumElements();
2151 std::vector<Constant*> NZ(VL,
2152 DAG.getContext()->getConstantFPNegativeZero(ElTy));
2153 Constant *CNZ = DAG.getContext()->getConstantVector(&NZ[0], NZ.size());
2155 SDValue Op2 = getValue(I.getOperand(1));
2156 setValue(&I, DAG.getNode(ISD::FNEG, getCurDebugLoc(),
2157 Op2.getValueType(), Op2));
2162 if (ConstantFP *CFP = dyn_cast<ConstantFP>(I.getOperand(0)))
2163 if (CFP->isExactlyValue(
2164 DAG.getContext()->getConstantFPNegativeZero(Ty)->getValueAPF())) {
2165 SDValue Op2 = getValue(I.getOperand(1));
2166 setValue(&I, DAG.getNode(ISD::FNEG, getCurDebugLoc(),
2167 Op2.getValueType(), Op2));
2171 visitBinary(I, ISD::FSUB);
2174 void SelectionDAGLowering::visitBinary(User &I, unsigned OpCode) {
2175 SDValue Op1 = getValue(I.getOperand(0));
2176 SDValue Op2 = getValue(I.getOperand(1));
2178 setValue(&I, DAG.getNode(OpCode, getCurDebugLoc(),
2179 Op1.getValueType(), Op1, Op2));
2182 void SelectionDAGLowering::visitShift(User &I, unsigned Opcode) {
2183 SDValue Op1 = getValue(I.getOperand(0));
2184 SDValue Op2 = getValue(I.getOperand(1));
2185 if (!isa<VectorType>(I.getType()) &&
2186 Op2.getValueType() != TLI.getShiftAmountTy()) {
2187 // If the operand is smaller than the shift count type, promote it.
2188 if (TLI.getShiftAmountTy().bitsGT(Op2.getValueType()))
2189 Op2 = DAG.getNode(ISD::ANY_EXTEND, getCurDebugLoc(),
2190 TLI.getShiftAmountTy(), Op2);
2191 // If the operand is larger than the shift count type but the shift
2192 // count type has enough bits to represent any shift value, truncate
2193 // it now. This is a common case and it exposes the truncate to
2194 // optimization early.
2195 else if (TLI.getShiftAmountTy().getSizeInBits() >=
2196 Log2_32_Ceil(Op2.getValueType().getSizeInBits()))
2197 Op2 = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(),
2198 TLI.getShiftAmountTy(), Op2);
2199 // Otherwise we'll need to temporarily settle for some other
2200 // convenient type; type legalization will make adjustments as
2202 else if (TLI.getPointerTy().bitsLT(Op2.getValueType()))
2203 Op2 = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(),
2204 TLI.getPointerTy(), Op2);
2205 else if (TLI.getPointerTy().bitsGT(Op2.getValueType()))
2206 Op2 = DAG.getNode(ISD::ANY_EXTEND, getCurDebugLoc(),
2207 TLI.getPointerTy(), Op2);
2210 setValue(&I, DAG.getNode(Opcode, getCurDebugLoc(),
2211 Op1.getValueType(), Op1, Op2));
2214 void SelectionDAGLowering::visitICmp(User &I) {
2215 ICmpInst::Predicate predicate = ICmpInst::BAD_ICMP_PREDICATE;
2216 if (ICmpInst *IC = dyn_cast<ICmpInst>(&I))
2217 predicate = IC->getPredicate();
2218 else if (ConstantExpr *IC = dyn_cast<ConstantExpr>(&I))
2219 predicate = ICmpInst::Predicate(IC->getPredicate());
2220 SDValue Op1 = getValue(I.getOperand(0));
2221 SDValue Op2 = getValue(I.getOperand(1));
2222 ISD::CondCode Opcode = getICmpCondCode(predicate);
2224 MVT DestVT = TLI.getValueType(I.getType());
2225 setValue(&I, DAG.getSetCC(getCurDebugLoc(), DestVT, Op1, Op2, Opcode));
2228 void SelectionDAGLowering::visitFCmp(User &I) {
2229 FCmpInst::Predicate predicate = FCmpInst::BAD_FCMP_PREDICATE;
2230 if (FCmpInst *FC = dyn_cast<FCmpInst>(&I))
2231 predicate = FC->getPredicate();
2232 else if (ConstantExpr *FC = dyn_cast<ConstantExpr>(&I))
2233 predicate = FCmpInst::Predicate(FC->getPredicate());
2234 SDValue Op1 = getValue(I.getOperand(0));
2235 SDValue Op2 = getValue(I.getOperand(1));
2236 ISD::CondCode Condition = getFCmpCondCode(predicate);
2237 MVT DestVT = TLI.getValueType(I.getType());
2238 setValue(&I, DAG.getSetCC(getCurDebugLoc(), DestVT, Op1, Op2, Condition));
2241 void SelectionDAGLowering::visitSelect(User &I) {
2242 SmallVector<MVT, 4> ValueVTs;
2243 ComputeValueVTs(TLI, I.getType(), ValueVTs);
2244 unsigned NumValues = ValueVTs.size();
2245 if (NumValues != 0) {
2246 SmallVector<SDValue, 4> Values(NumValues);
2247 SDValue Cond = getValue(I.getOperand(0));
2248 SDValue TrueVal = getValue(I.getOperand(1));
2249 SDValue FalseVal = getValue(I.getOperand(2));
2251 for (unsigned i = 0; i != NumValues; ++i)
2252 Values[i] = DAG.getNode(ISD::SELECT, getCurDebugLoc(),
2253 TrueVal.getValueType(), Cond,
2254 SDValue(TrueVal.getNode(), TrueVal.getResNo() + i),
2255 SDValue(FalseVal.getNode(), FalseVal.getResNo() + i));
2257 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(),
2258 DAG.getVTList(&ValueVTs[0], NumValues),
2259 &Values[0], NumValues));
2264 void SelectionDAGLowering::visitTrunc(User &I) {
2265 // TruncInst cannot be a no-op cast because sizeof(src) > sizeof(dest).
2266 SDValue N = getValue(I.getOperand(0));
2267 MVT DestVT = TLI.getValueType(I.getType());
2268 setValue(&I, DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), DestVT, N));
2271 void SelectionDAGLowering::visitZExt(User &I) {
2272 // ZExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
2273 // ZExt also can't be a cast to bool for same reason. So, nothing much to do
2274 SDValue N = getValue(I.getOperand(0));
2275 MVT DestVT = TLI.getValueType(I.getType());
2276 setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(), DestVT, N));
2279 void SelectionDAGLowering::visitSExt(User &I) {
2280 // SExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
2281 // SExt also can't be a cast to bool for same reason. So, nothing much to do
2282 SDValue N = getValue(I.getOperand(0));
2283 MVT DestVT = TLI.getValueType(I.getType());
2284 setValue(&I, DAG.getNode(ISD::SIGN_EXTEND, getCurDebugLoc(), DestVT, N));
2287 void SelectionDAGLowering::visitFPTrunc(User &I) {
2288 // FPTrunc is never a no-op cast, no need to check
2289 SDValue N = getValue(I.getOperand(0));
2290 MVT DestVT = TLI.getValueType(I.getType());
2291 setValue(&I, DAG.getNode(ISD::FP_ROUND, getCurDebugLoc(),
2292 DestVT, N, DAG.getIntPtrConstant(0)));
2295 void SelectionDAGLowering::visitFPExt(User &I){
2296 // FPTrunc is never a no-op cast, no need to check
2297 SDValue N = getValue(I.getOperand(0));
2298 MVT DestVT = TLI.getValueType(I.getType());
2299 setValue(&I, DAG.getNode(ISD::FP_EXTEND, getCurDebugLoc(), DestVT, N));
2302 void SelectionDAGLowering::visitFPToUI(User &I) {
2303 // FPToUI is never a no-op cast, no need to check
2304 SDValue N = getValue(I.getOperand(0));
2305 MVT DestVT = TLI.getValueType(I.getType());
2306 setValue(&I, DAG.getNode(ISD::FP_TO_UINT, getCurDebugLoc(), DestVT, N));
2309 void SelectionDAGLowering::visitFPToSI(User &I) {
2310 // FPToSI is never a no-op cast, no need to check
2311 SDValue N = getValue(I.getOperand(0));
2312 MVT DestVT = TLI.getValueType(I.getType());
2313 setValue(&I, DAG.getNode(ISD::FP_TO_SINT, getCurDebugLoc(), DestVT, N));
2316 void SelectionDAGLowering::visitUIToFP(User &I) {
2317 // UIToFP is never a no-op cast, no need to check
2318 SDValue N = getValue(I.getOperand(0));
2319 MVT DestVT = TLI.getValueType(I.getType());
2320 setValue(&I, DAG.getNode(ISD::UINT_TO_FP, getCurDebugLoc(), DestVT, N));
2323 void SelectionDAGLowering::visitSIToFP(User &I){
2324 // SIToFP is never a no-op cast, no need to check
2325 SDValue N = getValue(I.getOperand(0));
2326 MVT DestVT = TLI.getValueType(I.getType());
2327 setValue(&I, DAG.getNode(ISD::SINT_TO_FP, getCurDebugLoc(), DestVT, N));
2330 void SelectionDAGLowering::visitPtrToInt(User &I) {
2331 // What to do depends on the size of the integer and the size of the pointer.
2332 // We can either truncate, zero extend, or no-op, accordingly.
2333 SDValue N = getValue(I.getOperand(0));
2334 MVT SrcVT = N.getValueType();
2335 MVT DestVT = TLI.getValueType(I.getType());
2337 if (DestVT.bitsLT(SrcVT))
2338 Result = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), DestVT, N);
2340 // Note: ZERO_EXTEND can handle cases where the sizes are equal too
2341 Result = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(), DestVT, N);
2342 setValue(&I, Result);
2345 void SelectionDAGLowering::visitIntToPtr(User &I) {
2346 // What to do depends on the size of the integer and the size of the pointer.
2347 // We can either truncate, zero extend, or no-op, accordingly.
2348 SDValue N = getValue(I.getOperand(0));
2349 MVT SrcVT = N.getValueType();
2350 MVT DestVT = TLI.getValueType(I.getType());
2351 if (DestVT.bitsLT(SrcVT))
2352 setValue(&I, DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), DestVT, N));
2354 // Note: ZERO_EXTEND can handle cases where the sizes are equal too
2355 setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(),
2359 void SelectionDAGLowering::visitBitCast(User &I) {
2360 SDValue N = getValue(I.getOperand(0));
2361 MVT DestVT = TLI.getValueType(I.getType());
2363 // BitCast assures us that source and destination are the same size so this
2364 // is either a BIT_CONVERT or a no-op.
2365 if (DestVT != N.getValueType())
2366 setValue(&I, DAG.getNode(ISD::BIT_CONVERT, getCurDebugLoc(),
2367 DestVT, N)); // convert types
2369 setValue(&I, N); // noop cast.
2372 void SelectionDAGLowering::visitInsertElement(User &I) {
2373 SDValue InVec = getValue(I.getOperand(0));
2374 SDValue InVal = getValue(I.getOperand(1));
2375 SDValue InIdx = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(),
2377 getValue(I.getOperand(2)));
2379 setValue(&I, DAG.getNode(ISD::INSERT_VECTOR_ELT, getCurDebugLoc(),
2380 TLI.getValueType(I.getType()),
2381 InVec, InVal, InIdx));
2384 void SelectionDAGLowering::visitExtractElement(User &I) {
2385 SDValue InVec = getValue(I.getOperand(0));
2386 SDValue InIdx = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(),
2388 getValue(I.getOperand(1)));
2389 setValue(&I, DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurDebugLoc(),
2390 TLI.getValueType(I.getType()), InVec, InIdx));
2394 // Utility for visitShuffleVector - Returns true if the mask is mask starting
2395 // from SIndx and increasing to the element length (undefs are allowed).
2396 static bool SequentialMask(SmallVectorImpl<int> &Mask, unsigned SIndx) {
2397 unsigned MaskNumElts = Mask.size();
2398 for (unsigned i = 0; i != MaskNumElts; ++i)
2399 if ((Mask[i] >= 0) && (Mask[i] != (int)(i + SIndx)))
2404 void SelectionDAGLowering::visitShuffleVector(User &I) {
2405 SmallVector<int, 8> Mask;
2406 SDValue Src1 = getValue(I.getOperand(0));
2407 SDValue Src2 = getValue(I.getOperand(1));
2409 // Convert the ConstantVector mask operand into an array of ints, with -1
2410 // representing undef values.
2411 SmallVector<Constant*, 8> MaskElts;
2412 cast<Constant>(I.getOperand(2))->getVectorElements(*DAG.getContext(),
2414 unsigned MaskNumElts = MaskElts.size();
2415 for (unsigned i = 0; i != MaskNumElts; ++i) {
2416 if (isa<UndefValue>(MaskElts[i]))
2419 Mask.push_back(cast<ConstantInt>(MaskElts[i])->getSExtValue());
2422 MVT VT = TLI.getValueType(I.getType());
2423 MVT SrcVT = Src1.getValueType();
2424 unsigned SrcNumElts = SrcVT.getVectorNumElements();
2426 if (SrcNumElts == MaskNumElts) {
2427 setValue(&I, DAG.getVectorShuffle(VT, getCurDebugLoc(), Src1, Src2,
2432 // Normalize the shuffle vector since mask and vector length don't match.
2433 if (SrcNumElts < MaskNumElts && MaskNumElts % SrcNumElts == 0) {
2434 // Mask is longer than the source vectors and is a multiple of the source
2435 // vectors. We can use concatenate vector to make the mask and vectors
2437 if (SrcNumElts*2 == MaskNumElts && SequentialMask(Mask, 0)) {
2438 // The shuffle is concatenating two vectors together.
2439 setValue(&I, DAG.getNode(ISD::CONCAT_VECTORS, getCurDebugLoc(),
2444 // Pad both vectors with undefs to make them the same length as the mask.
2445 unsigned NumConcat = MaskNumElts / SrcNumElts;
2446 bool Src1U = Src1.getOpcode() == ISD::UNDEF;
2447 bool Src2U = Src2.getOpcode() == ISD::UNDEF;
2448 SDValue UndefVal = DAG.getUNDEF(SrcVT);
2450 SmallVector<SDValue, 8> MOps1(NumConcat, UndefVal);
2451 SmallVector<SDValue, 8> MOps2(NumConcat, UndefVal);
2455 Src1 = Src1U ? DAG.getUNDEF(VT) : DAG.getNode(ISD::CONCAT_VECTORS,
2456 getCurDebugLoc(), VT,
2457 &MOps1[0], NumConcat);
2458 Src2 = Src2U ? DAG.getUNDEF(VT) : DAG.getNode(ISD::CONCAT_VECTORS,
2459 getCurDebugLoc(), VT,
2460 &MOps2[0], NumConcat);
2462 // Readjust mask for new input vector length.
2463 SmallVector<int, 8> MappedOps;
2464 for (unsigned i = 0; i != MaskNumElts; ++i) {
2466 if (Idx < (int)SrcNumElts)
2467 MappedOps.push_back(Idx);
2469 MappedOps.push_back(Idx + MaskNumElts - SrcNumElts);
2471 setValue(&I, DAG.getVectorShuffle(VT, getCurDebugLoc(), Src1, Src2,
2476 if (SrcNumElts > MaskNumElts) {
2477 // Analyze the access pattern of the vector to see if we can extract
2478 // two subvectors and do the shuffle. The analysis is done by calculating
2479 // the range of elements the mask access on both vectors.
2480 int MinRange[2] = { SrcNumElts+1, SrcNumElts+1};
2481 int MaxRange[2] = {-1, -1};
2483 for (unsigned i = 0; i != MaskNumElts; ++i) {
2489 if (Idx >= (int)SrcNumElts) {
2493 if (Idx > MaxRange[Input])
2494 MaxRange[Input] = Idx;
2495 if (Idx < MinRange[Input])
2496 MinRange[Input] = Idx;
2499 // Check if the access is smaller than the vector size and can we find
2500 // a reasonable extract index.
2501 int RangeUse[2] = { 2, 2 }; // 0 = Unused, 1 = Extract, 2 = Can not Extract.
2502 int StartIdx[2]; // StartIdx to extract from
2503 for (int Input=0; Input < 2; ++Input) {
2504 if (MinRange[Input] == (int)(SrcNumElts+1) && MaxRange[Input] == -1) {
2505 RangeUse[Input] = 0; // Unused
2506 StartIdx[Input] = 0;
2507 } else if (MaxRange[Input] - MinRange[Input] < (int)MaskNumElts) {
2508 // Fits within range but we should see if we can find a good
2509 // start index that is a multiple of the mask length.
2510 if (MaxRange[Input] < (int)MaskNumElts) {
2511 RangeUse[Input] = 1; // Extract from beginning of the vector
2512 StartIdx[Input] = 0;
2514 StartIdx[Input] = (MinRange[Input]/MaskNumElts)*MaskNumElts;
2515 if (MaxRange[Input] - StartIdx[Input] < (int)MaskNumElts &&
2516 StartIdx[Input] + MaskNumElts < SrcNumElts)
2517 RangeUse[Input] = 1; // Extract from a multiple of the mask length.
2522 if (RangeUse[0] == 0 && RangeUse[0] == 0) {
2523 setValue(&I, DAG.getUNDEF(VT)); // Vectors are not used.
2526 else if (RangeUse[0] < 2 && RangeUse[1] < 2) {
2527 // Extract appropriate subvector and generate a vector shuffle
2528 for (int Input=0; Input < 2; ++Input) {
2529 SDValue& Src = Input == 0 ? Src1 : Src2;
2530 if (RangeUse[Input] == 0) {
2531 Src = DAG.getUNDEF(VT);
2533 Src = DAG.getNode(ISD::EXTRACT_SUBVECTOR, getCurDebugLoc(), VT,
2534 Src, DAG.getIntPtrConstant(StartIdx[Input]));
2537 // Calculate new mask.
2538 SmallVector<int, 8> MappedOps;
2539 for (unsigned i = 0; i != MaskNumElts; ++i) {
2542 MappedOps.push_back(Idx);
2543 else if (Idx < (int)SrcNumElts)
2544 MappedOps.push_back(Idx - StartIdx[0]);
2546 MappedOps.push_back(Idx - SrcNumElts - StartIdx[1] + MaskNumElts);
2548 setValue(&I, DAG.getVectorShuffle(VT, getCurDebugLoc(), Src1, Src2,
2554 // We can't use either concat vectors or extract subvectors so fall back to
2555 // replacing the shuffle with extract and build vector.
2556 // to insert and build vector.
2557 MVT EltVT = VT.getVectorElementType();
2558 MVT PtrVT = TLI.getPointerTy();
2559 SmallVector<SDValue,8> Ops;
2560 for (unsigned i = 0; i != MaskNumElts; ++i) {
2562 Ops.push_back(DAG.getUNDEF(EltVT));
2565 if (Idx < (int)SrcNumElts)
2566 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurDebugLoc(),
2567 EltVT, Src1, DAG.getConstant(Idx, PtrVT)));
2569 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurDebugLoc(),
2571 DAG.getConstant(Idx - SrcNumElts, PtrVT)));
2574 setValue(&I, DAG.getNode(ISD::BUILD_VECTOR, getCurDebugLoc(),
2575 VT, &Ops[0], Ops.size()));
2578 void SelectionDAGLowering::visitInsertValue(InsertValueInst &I) {
2579 const Value *Op0 = I.getOperand(0);
2580 const Value *Op1 = I.getOperand(1);
2581 const Type *AggTy = I.getType();
2582 const Type *ValTy = Op1->getType();
2583 bool IntoUndef = isa<UndefValue>(Op0);
2584 bool FromUndef = isa<UndefValue>(Op1);
2586 unsigned LinearIndex = ComputeLinearIndex(TLI, AggTy,
2587 I.idx_begin(), I.idx_end());
2589 SmallVector<MVT, 4> AggValueVTs;
2590 ComputeValueVTs(TLI, AggTy, AggValueVTs);
2591 SmallVector<MVT, 4> ValValueVTs;
2592 ComputeValueVTs(TLI, ValTy, ValValueVTs);
2594 unsigned NumAggValues = AggValueVTs.size();
2595 unsigned NumValValues = ValValueVTs.size();
2596 SmallVector<SDValue, 4> Values(NumAggValues);
2598 SDValue Agg = getValue(Op0);
2599 SDValue Val = getValue(Op1);
2601 // Copy the beginning value(s) from the original aggregate.
2602 for (; i != LinearIndex; ++i)
2603 Values[i] = IntoUndef ? DAG.getUNDEF(AggValueVTs[i]) :
2604 SDValue(Agg.getNode(), Agg.getResNo() + i);
2605 // Copy values from the inserted value(s).
2606 for (; i != LinearIndex + NumValValues; ++i)
2607 Values[i] = FromUndef ? DAG.getUNDEF(AggValueVTs[i]) :
2608 SDValue(Val.getNode(), Val.getResNo() + i - LinearIndex);
2609 // Copy remaining value(s) from the original aggregate.
2610 for (; i != NumAggValues; ++i)
2611 Values[i] = IntoUndef ? DAG.getUNDEF(AggValueVTs[i]) :
2612 SDValue(Agg.getNode(), Agg.getResNo() + i);
2614 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(),
2615 DAG.getVTList(&AggValueVTs[0], NumAggValues),
2616 &Values[0], NumAggValues));
2619 void SelectionDAGLowering::visitExtractValue(ExtractValueInst &I) {
2620 const Value *Op0 = I.getOperand(0);
2621 const Type *AggTy = Op0->getType();
2622 const Type *ValTy = I.getType();
2623 bool OutOfUndef = isa<UndefValue>(Op0);
2625 unsigned LinearIndex = ComputeLinearIndex(TLI, AggTy,
2626 I.idx_begin(), I.idx_end());
2628 SmallVector<MVT, 4> ValValueVTs;
2629 ComputeValueVTs(TLI, ValTy, ValValueVTs);
2631 unsigned NumValValues = ValValueVTs.size();
2632 SmallVector<SDValue, 4> Values(NumValValues);
2634 SDValue Agg = getValue(Op0);
2635 // Copy out the selected value(s).
2636 for (unsigned i = LinearIndex; i != LinearIndex + NumValValues; ++i)
2637 Values[i - LinearIndex] =
2639 DAG.getUNDEF(Agg.getNode()->getValueType(Agg.getResNo() + i)) :
2640 SDValue(Agg.getNode(), Agg.getResNo() + i);
2642 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(),
2643 DAG.getVTList(&ValValueVTs[0], NumValValues),
2644 &Values[0], NumValValues));
2648 void SelectionDAGLowering::visitGetElementPtr(User &I) {
2649 SDValue N = getValue(I.getOperand(0));
2650 const Type *Ty = I.getOperand(0)->getType();
2652 for (GetElementPtrInst::op_iterator OI = I.op_begin()+1, E = I.op_end();
2655 if (const StructType *StTy = dyn_cast<StructType>(Ty)) {
2656 unsigned Field = cast<ConstantInt>(Idx)->getZExtValue();
2659 uint64_t Offset = TD->getStructLayout(StTy)->getElementOffset(Field);
2660 N = DAG.getNode(ISD::ADD, getCurDebugLoc(), N.getValueType(), N,
2661 DAG.getIntPtrConstant(Offset));
2663 Ty = StTy->getElementType(Field);
2665 Ty = cast<SequentialType>(Ty)->getElementType();
2667 // If this is a constant subscript, handle it quickly.
2668 if (ConstantInt *CI = dyn_cast<ConstantInt>(Idx)) {
2669 if (CI->getZExtValue() == 0) continue;
2671 TD->getTypeAllocSize(Ty)*cast<ConstantInt>(CI)->getSExtValue();
2673 unsigned PtrBits = TLI.getPointerTy().getSizeInBits();
2675 OffsVal = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(),
2677 DAG.getConstant(Offs, MVT::i64));
2679 OffsVal = DAG.getIntPtrConstant(Offs);
2680 N = DAG.getNode(ISD::ADD, getCurDebugLoc(), N.getValueType(), N,
2685 // N = N + Idx * ElementSize;
2686 uint64_t ElementSize = TD->getTypeAllocSize(Ty);
2687 SDValue IdxN = getValue(Idx);
2689 // If the index is smaller or larger than intptr_t, truncate or extend
2691 if (IdxN.getValueType().bitsLT(N.getValueType()))
2692 IdxN = DAG.getNode(ISD::SIGN_EXTEND, getCurDebugLoc(),
2693 N.getValueType(), IdxN);
2694 else if (IdxN.getValueType().bitsGT(N.getValueType()))
2695 IdxN = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(),
2696 N.getValueType(), IdxN);
2698 // If this is a multiply by a power of two, turn it into a shl
2699 // immediately. This is a very common case.
2700 if (ElementSize != 1) {
2701 if (isPowerOf2_64(ElementSize)) {
2702 unsigned Amt = Log2_64(ElementSize);
2703 IdxN = DAG.getNode(ISD::SHL, getCurDebugLoc(),
2704 N.getValueType(), IdxN,
2705 DAG.getConstant(Amt, TLI.getPointerTy()));
2707 SDValue Scale = DAG.getIntPtrConstant(ElementSize);
2708 IdxN = DAG.getNode(ISD::MUL, getCurDebugLoc(),
2709 N.getValueType(), IdxN, Scale);
2713 N = DAG.getNode(ISD::ADD, getCurDebugLoc(),
2714 N.getValueType(), N, IdxN);
2720 void SelectionDAGLowering::visitAlloca(AllocaInst &I) {
2721 // If this is a fixed sized alloca in the entry block of the function,
2722 // allocate it statically on the stack.
2723 if (FuncInfo.StaticAllocaMap.count(&I))
2724 return; // getValue will auto-populate this.
2726 const Type *Ty = I.getAllocatedType();
2727 uint64_t TySize = TLI.getTargetData()->getTypeAllocSize(Ty);
2729 std::max((unsigned)TLI.getTargetData()->getPrefTypeAlignment(Ty),
2732 SDValue AllocSize = getValue(I.getArraySize());
2734 AllocSize = DAG.getNode(ISD::MUL, getCurDebugLoc(), AllocSize.getValueType(),
2736 DAG.getConstant(TySize, AllocSize.getValueType()));
2740 MVT IntPtr = TLI.getPointerTy();
2741 if (IntPtr.bitsLT(AllocSize.getValueType()))
2742 AllocSize = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(),
2744 else if (IntPtr.bitsGT(AllocSize.getValueType()))
2745 AllocSize = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(),
2748 // Handle alignment. If the requested alignment is less than or equal to
2749 // the stack alignment, ignore it. If the size is greater than or equal to
2750 // the stack alignment, we note this in the DYNAMIC_STACKALLOC node.
2751 unsigned StackAlign =
2752 TLI.getTargetMachine().getFrameInfo()->getStackAlignment();
2753 if (Align <= StackAlign)
2756 // Round the size of the allocation up to the stack alignment size
2757 // by add SA-1 to the size.
2758 AllocSize = DAG.getNode(ISD::ADD, getCurDebugLoc(),
2759 AllocSize.getValueType(), AllocSize,
2760 DAG.getIntPtrConstant(StackAlign-1));
2761 // Mask out the low bits for alignment purposes.
2762 AllocSize = DAG.getNode(ISD::AND, getCurDebugLoc(),
2763 AllocSize.getValueType(), AllocSize,
2764 DAG.getIntPtrConstant(~(uint64_t)(StackAlign-1)));
2766 SDValue Ops[] = { getRoot(), AllocSize, DAG.getIntPtrConstant(Align) };
2767 SDVTList VTs = DAG.getVTList(AllocSize.getValueType(), MVT::Other);
2768 SDValue DSA = DAG.getNode(ISD::DYNAMIC_STACKALLOC, getCurDebugLoc(),
2771 DAG.setRoot(DSA.getValue(1));
2773 // Inform the Frame Information that we have just allocated a variable-sized
2775 CurMBB->getParent()->getFrameInfo()->CreateVariableSizedObject();
2778 void SelectionDAGLowering::visitLoad(LoadInst &I) {
2779 const Value *SV = I.getOperand(0);
2780 SDValue Ptr = getValue(SV);
2782 const Type *Ty = I.getType();
2783 bool isVolatile = I.isVolatile();
2784 unsigned Alignment = I.getAlignment();
2786 SmallVector<MVT, 4> ValueVTs;
2787 SmallVector<uint64_t, 4> Offsets;
2788 ComputeValueVTs(TLI, Ty, ValueVTs, &Offsets);
2789 unsigned NumValues = ValueVTs.size();
2794 bool ConstantMemory = false;
2796 // Serialize volatile loads with other side effects.
2798 else if (AA->pointsToConstantMemory(SV)) {
2799 // Do not serialize (non-volatile) loads of constant memory with anything.
2800 Root = DAG.getEntryNode();
2801 ConstantMemory = true;
2803 // Do not serialize non-volatile loads against each other.
2804 Root = DAG.getRoot();
2807 SmallVector<SDValue, 4> Values(NumValues);
2808 SmallVector<SDValue, 4> Chains(NumValues);
2809 MVT PtrVT = Ptr.getValueType();
2810 for (unsigned i = 0; i != NumValues; ++i) {
2811 SDValue L = DAG.getLoad(ValueVTs[i], getCurDebugLoc(), Root,
2812 DAG.getNode(ISD::ADD, getCurDebugLoc(),
2814 DAG.getConstant(Offsets[i], PtrVT)),
2816 isVolatile, Alignment);
2818 Chains[i] = L.getValue(1);
2821 if (!ConstantMemory) {
2822 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(),
2824 &Chains[0], NumValues);
2828 PendingLoads.push_back(Chain);
2831 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(),
2832 DAG.getVTList(&ValueVTs[0], NumValues),
2833 &Values[0], NumValues));
2837 void SelectionDAGLowering::visitStore(StoreInst &I) {
2838 Value *SrcV = I.getOperand(0);
2839 Value *PtrV = I.getOperand(1);
2841 SmallVector<MVT, 4> ValueVTs;
2842 SmallVector<uint64_t, 4> Offsets;
2843 ComputeValueVTs(TLI, SrcV->getType(), ValueVTs, &Offsets);
2844 unsigned NumValues = ValueVTs.size();
2848 // Get the lowered operands. Note that we do this after
2849 // checking if NumResults is zero, because with zero results
2850 // the operands won't have values in the map.
2851 SDValue Src = getValue(SrcV);
2852 SDValue Ptr = getValue(PtrV);
2854 SDValue Root = getRoot();
2855 SmallVector<SDValue, 4> Chains(NumValues);
2856 MVT PtrVT = Ptr.getValueType();
2857 bool isVolatile = I.isVolatile();
2858 unsigned Alignment = I.getAlignment();
2859 for (unsigned i = 0; i != NumValues; ++i)
2860 Chains[i] = DAG.getStore(Root, getCurDebugLoc(),
2861 SDValue(Src.getNode(), Src.getResNo() + i),
2862 DAG.getNode(ISD::ADD, getCurDebugLoc(),
2864 DAG.getConstant(Offsets[i], PtrVT)),
2866 isVolatile, Alignment);
2868 DAG.setRoot(DAG.getNode(ISD::TokenFactor, getCurDebugLoc(),
2869 MVT::Other, &Chains[0], NumValues));
2872 /// visitTargetIntrinsic - Lower a call of a target intrinsic to an INTRINSIC
2874 void SelectionDAGLowering::visitTargetIntrinsic(CallInst &I,
2875 unsigned Intrinsic) {
2876 bool HasChain = !I.doesNotAccessMemory();
2877 bool OnlyLoad = HasChain && I.onlyReadsMemory();
2879 // Build the operand list.
2880 SmallVector<SDValue, 8> Ops;
2881 if (HasChain) { // If this intrinsic has side-effects, chainify it.
2883 // We don't need to serialize loads against other loads.
2884 Ops.push_back(DAG.getRoot());
2886 Ops.push_back(getRoot());
2890 // Info is set by getTgtMemInstrinsic
2891 TargetLowering::IntrinsicInfo Info;
2892 bool IsTgtIntrinsic = TLI.getTgtMemIntrinsic(Info, I, Intrinsic);
2894 // Add the intrinsic ID as an integer operand if it's not a target intrinsic.
2895 if (!IsTgtIntrinsic)
2896 Ops.push_back(DAG.getConstant(Intrinsic, TLI.getPointerTy()));
2898 // Add all operands of the call to the operand list.
2899 for (unsigned i = 1, e = I.getNumOperands(); i != e; ++i) {
2900 SDValue Op = getValue(I.getOperand(i));
2901 assert(TLI.isTypeLegal(Op.getValueType()) &&
2902 "Intrinsic uses a non-legal type?");
2906 std::vector<MVT> VTArray;
2907 if (I.getType() != Type::VoidTy) {
2908 MVT VT = TLI.getValueType(I.getType());
2909 if (VT.isVector()) {
2910 const VectorType *DestTy = cast<VectorType>(I.getType());
2911 MVT EltVT = TLI.getValueType(DestTy->getElementType());
2913 VT = MVT::getVectorVT(EltVT, DestTy->getNumElements());
2914 assert(VT != MVT::Other && "Intrinsic uses a non-legal type?");
2917 assert(TLI.isTypeLegal(VT) && "Intrinsic uses a non-legal type?");
2918 VTArray.push_back(VT);
2921 VTArray.push_back(MVT::Other);
2923 SDVTList VTs = DAG.getVTList(&VTArray[0], VTArray.size());
2927 if (IsTgtIntrinsic) {
2928 // This is target intrinsic that touches memory
2929 Result = DAG.getMemIntrinsicNode(Info.opc, getCurDebugLoc(),
2930 VTs, &Ops[0], Ops.size(),
2931 Info.memVT, Info.ptrVal, Info.offset,
2932 Info.align, Info.vol,
2933 Info.readMem, Info.writeMem);
2936 Result = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, getCurDebugLoc(),
2937 VTs, &Ops[0], Ops.size());
2938 else if (I.getType() != Type::VoidTy)
2939 Result = DAG.getNode(ISD::INTRINSIC_W_CHAIN, getCurDebugLoc(),
2940 VTs, &Ops[0], Ops.size());
2942 Result = DAG.getNode(ISD::INTRINSIC_VOID, getCurDebugLoc(),
2943 VTs, &Ops[0], Ops.size());
2946 SDValue Chain = Result.getValue(Result.getNode()->getNumValues()-1);
2948 PendingLoads.push_back(Chain);
2952 if (I.getType() != Type::VoidTy) {
2953 if (const VectorType *PTy = dyn_cast<VectorType>(I.getType())) {
2954 MVT VT = TLI.getValueType(PTy);
2955 Result = DAG.getNode(ISD::BIT_CONVERT, getCurDebugLoc(), VT, Result);
2957 setValue(&I, Result);
2961 /// ExtractTypeInfo - Returns the type info, possibly bitcast, encoded in V.
2962 static GlobalVariable *ExtractTypeInfo(Value *V) {
2963 V = V->stripPointerCasts();
2964 GlobalVariable *GV = dyn_cast<GlobalVariable>(V);
2965 assert ((GV || isa<ConstantPointerNull>(V)) &&
2966 "TypeInfo must be a global variable or NULL");
2972 /// AddCatchInfo - Extract the personality and type infos from an eh.selector
2973 /// call, and add them to the specified machine basic block.
2974 void AddCatchInfo(CallInst &I, MachineModuleInfo *MMI,
2975 MachineBasicBlock *MBB) {
2976 // Inform the MachineModuleInfo of the personality for this landing pad.
2977 ConstantExpr *CE = cast<ConstantExpr>(I.getOperand(2));
2978 assert(CE->getOpcode() == Instruction::BitCast &&
2979 isa<Function>(CE->getOperand(0)) &&
2980 "Personality should be a function");
2981 MMI->addPersonality(MBB, cast<Function>(CE->getOperand(0)));
2983 // Gather all the type infos for this landing pad and pass them along to
2984 // MachineModuleInfo.
2985 std::vector<GlobalVariable *> TyInfo;
2986 unsigned N = I.getNumOperands();
2988 for (unsigned i = N - 1; i > 2; --i) {
2989 if (ConstantInt *CI = dyn_cast<ConstantInt>(I.getOperand(i))) {
2990 unsigned FilterLength = CI->getZExtValue();
2991 unsigned FirstCatch = i + FilterLength + !FilterLength;
2992 assert (FirstCatch <= N && "Invalid filter length");
2994 if (FirstCatch < N) {
2995 TyInfo.reserve(N - FirstCatch);
2996 for (unsigned j = FirstCatch; j < N; ++j)
2997 TyInfo.push_back(ExtractTypeInfo(I.getOperand(j)));
2998 MMI->addCatchTypeInfo(MBB, TyInfo);
3002 if (!FilterLength) {
3004 MMI->addCleanup(MBB);
3007 TyInfo.reserve(FilterLength - 1);
3008 for (unsigned j = i + 1; j < FirstCatch; ++j)
3009 TyInfo.push_back(ExtractTypeInfo(I.getOperand(j)));
3010 MMI->addFilterTypeInfo(MBB, TyInfo);
3019 TyInfo.reserve(N - 3);
3020 for (unsigned j = 3; j < N; ++j)
3021 TyInfo.push_back(ExtractTypeInfo(I.getOperand(j)));
3022 MMI->addCatchTypeInfo(MBB, TyInfo);
3028 /// GetSignificand - Get the significand and build it into a floating-point
3029 /// number with exponent of 1:
3031 /// Op = (Op & 0x007fffff) | 0x3f800000;
3033 /// where Op is the hexidecimal representation of floating point value.
3035 GetSignificand(SelectionDAG &DAG, SDValue Op, DebugLoc dl) {
3036 SDValue t1 = DAG.getNode(ISD::AND, dl, MVT::i32, Op,
3037 DAG.getConstant(0x007fffff, MVT::i32));
3038 SDValue t2 = DAG.getNode(ISD::OR, dl, MVT::i32, t1,
3039 DAG.getConstant(0x3f800000, MVT::i32));
3040 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, t2);
3043 /// GetExponent - Get the exponent:
3045 /// (float)(int)(((Op & 0x7f800000) >> 23) - 127);
3047 /// where Op is the hexidecimal representation of floating point value.
3049 GetExponent(SelectionDAG &DAG, SDValue Op, const TargetLowering &TLI,
3051 SDValue t0 = DAG.getNode(ISD::AND, dl, MVT::i32, Op,
3052 DAG.getConstant(0x7f800000, MVT::i32));
3053 SDValue t1 = DAG.getNode(ISD::SRL, dl, MVT::i32, t0,
3054 DAG.getConstant(23, TLI.getPointerTy()));
3055 SDValue t2 = DAG.getNode(ISD::SUB, dl, MVT::i32, t1,
3056 DAG.getConstant(127, MVT::i32));
3057 return DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, t2);
3060 /// getF32Constant - Get 32-bit floating point constant.
3062 getF32Constant(SelectionDAG &DAG, unsigned Flt) {
3063 return DAG.getConstantFP(APFloat(APInt(32, Flt)), MVT::f32);
3066 /// Inlined utility function to implement binary input atomic intrinsics for
3067 /// visitIntrinsicCall: I is a call instruction
3068 /// Op is the associated NodeType for I
3070 SelectionDAGLowering::implVisitBinaryAtomic(CallInst& I, ISD::NodeType Op) {
3071 SDValue Root = getRoot();
3073 DAG.getAtomic(Op, getCurDebugLoc(),
3074 getValue(I.getOperand(2)).getValueType().getSimpleVT(),
3076 getValue(I.getOperand(1)),
3077 getValue(I.getOperand(2)),
3080 DAG.setRoot(L.getValue(1));
3084 // implVisitAluOverflow - Lower arithmetic overflow instrinsics.
3086 SelectionDAGLowering::implVisitAluOverflow(CallInst &I, ISD::NodeType Op) {
3087 SDValue Op1 = getValue(I.getOperand(1));
3088 SDValue Op2 = getValue(I.getOperand(2));
3090 SDVTList VTs = DAG.getVTList(Op1.getValueType(), MVT::i1);
3091 SDValue Result = DAG.getNode(Op, getCurDebugLoc(), VTs, Op1, Op2);
3093 setValue(&I, Result);
3097 /// visitExp - Lower an exp intrinsic. Handles the special sequences for
3098 /// limited-precision mode.
3100 SelectionDAGLowering::visitExp(CallInst &I) {
3102 DebugLoc dl = getCurDebugLoc();
3104 if (getValue(I.getOperand(1)).getValueType() == MVT::f32 &&
3105 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3106 SDValue Op = getValue(I.getOperand(1));
3108 // Put the exponent in the right bit position for later addition to the
3111 // #define LOG2OFe 1.4426950f
3112 // IntegerPartOfX = ((int32_t)(X * LOG2OFe));
3113 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, Op,
3114 getF32Constant(DAG, 0x3fb8aa3b));
3115 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, t0);
3117 // FractionalPartOfX = (X * LOG2OFe) - (float)IntegerPartOfX;
3118 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX);
3119 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, t1);
3121 // IntegerPartOfX <<= 23;
3122 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX,
3123 DAG.getConstant(23, TLI.getPointerTy()));
3125 if (LimitFloatPrecision <= 6) {
3126 // For floating-point precision of 6:
3128 // TwoToFractionalPartOfX =
3130 // (0.735607626f + 0.252464424f * x) * x;
3132 // error 0.0144103317, which is 6 bits
3133 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3134 getF32Constant(DAG, 0x3e814304));
3135 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3136 getF32Constant(DAG, 0x3f3c50c8));
3137 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3138 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3139 getF32Constant(DAG, 0x3f7f5e7e));
3140 SDValue TwoToFracPartOfX = DAG.getNode(ISD::BIT_CONVERT, dl,MVT::i32, t5);
3142 // Add the exponent into the result in integer domain.
3143 SDValue t6 = DAG.getNode(ISD::ADD, dl, MVT::i32,
3144 TwoToFracPartOfX, IntegerPartOfX);
3146 result = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, t6);
3147 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
3148 // For floating-point precision of 12:
3150 // TwoToFractionalPartOfX =
3153 // (0.224338339f + 0.792043434e-1f * x) * x) * x;
3155 // 0.000107046256 error, which is 13 to 14 bits
3156 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3157 getF32Constant(DAG, 0x3da235e3));
3158 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3159 getF32Constant(DAG, 0x3e65b8f3));
3160 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3161 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3162 getF32Constant(DAG, 0x3f324b07));
3163 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3164 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3165 getF32Constant(DAG, 0x3f7ff8fd));
3166 SDValue TwoToFracPartOfX = DAG.getNode(ISD::BIT_CONVERT, dl,MVT::i32, t7);
3168 // Add the exponent into the result in integer domain.
3169 SDValue t8 = DAG.getNode(ISD::ADD, dl, MVT::i32,
3170 TwoToFracPartOfX, IntegerPartOfX);
3172 result = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, t8);
3173 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
3174 // For floating-point precision of 18:
3176 // TwoToFractionalPartOfX =
3180 // (0.554906021e-1f +
3181 // (0.961591928e-2f +
3182 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x;
3184 // error 2.47208000*10^(-7), which is better than 18 bits
3185 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3186 getF32Constant(DAG, 0x3924b03e));
3187 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3188 getF32Constant(DAG, 0x3ab24b87));
3189 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3190 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3191 getF32Constant(DAG, 0x3c1d8c17));
3192 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3193 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3194 getF32Constant(DAG, 0x3d634a1d));
3195 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3196 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3197 getF32Constant(DAG, 0x3e75fe14));
3198 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3199 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10,
3200 getF32Constant(DAG, 0x3f317234));
3201 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X);
3202 SDValue t13 = DAG.getNode(ISD::FADD, dl, MVT::f32, t12,
3203 getF32Constant(DAG, 0x3f800000));
3204 SDValue TwoToFracPartOfX = DAG.getNode(ISD::BIT_CONVERT, dl,
3207 // Add the exponent into the result in integer domain.
3208 SDValue t14 = DAG.getNode(ISD::ADD, dl, MVT::i32,
3209 TwoToFracPartOfX, IntegerPartOfX);
3211 result = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, t14);
3214 // No special expansion.
3215 result = DAG.getNode(ISD::FEXP, dl,
3216 getValue(I.getOperand(1)).getValueType(),
3217 getValue(I.getOperand(1)));
3220 setValue(&I, result);
3223 /// visitLog - Lower a log intrinsic. Handles the special sequences for
3224 /// limited-precision mode.
3226 SelectionDAGLowering::visitLog(CallInst &I) {
3228 DebugLoc dl = getCurDebugLoc();
3230 if (getValue(I.getOperand(1)).getValueType() == MVT::f32 &&
3231 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3232 SDValue Op = getValue(I.getOperand(1));
3233 SDValue Op1 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, Op);
3235 // Scale the exponent by log(2) [0.69314718f].
3236 SDValue Exp = GetExponent(DAG, Op1, TLI, dl);
3237 SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp,
3238 getF32Constant(DAG, 0x3f317218));
3240 // Get the significand and build it into a floating-point number with
3242 SDValue X = GetSignificand(DAG, Op1, dl);
3244 if (LimitFloatPrecision <= 6) {
3245 // For floating-point precision of 6:
3249 // (1.4034025f - 0.23903021f * x) * x;
3251 // error 0.0034276066, which is better than 8 bits
3252 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3253 getF32Constant(DAG, 0xbe74c456));
3254 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3255 getF32Constant(DAG, 0x3fb3a2b1));
3256 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3257 SDValue LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3258 getF32Constant(DAG, 0x3f949a29));
3260 result = DAG.getNode(ISD::FADD, dl,
3261 MVT::f32, LogOfExponent, LogOfMantissa);
3262 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
3263 // For floating-point precision of 12:
3269 // (0.44717955f - 0.56570851e-1f * x) * x) * x) * x;
3271 // error 0.000061011436, which is 14 bits
3272 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3273 getF32Constant(DAG, 0xbd67b6d6));
3274 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3275 getF32Constant(DAG, 0x3ee4f4b8));
3276 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3277 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3278 getF32Constant(DAG, 0x3fbc278b));
3279 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3280 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3281 getF32Constant(DAG, 0x40348e95));
3282 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3283 SDValue LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3284 getF32Constant(DAG, 0x3fdef31a));
3286 result = DAG.getNode(ISD::FADD, dl,
3287 MVT::f32, LogOfExponent, LogOfMantissa);
3288 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
3289 // For floating-point precision of 18:
3297 // (0.19073739f - 0.17809712e-1f * x) * x) * x) * x) * x)*x;
3299 // error 0.0000023660568, which is better than 18 bits
3300 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3301 getF32Constant(DAG, 0xbc91e5ac));
3302 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3303 getF32Constant(DAG, 0x3e4350aa));
3304 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3305 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3306 getF32Constant(DAG, 0x3f60d3e3));
3307 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3308 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3309 getF32Constant(DAG, 0x4011cdf0));
3310 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3311 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3312 getF32Constant(DAG, 0x406cfd1c));
3313 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3314 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3315 getF32Constant(DAG, 0x408797cb));
3316 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3317 SDValue LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10,
3318 getF32Constant(DAG, 0x4006dcab));
3320 result = DAG.getNode(ISD::FADD, dl,
3321 MVT::f32, LogOfExponent, LogOfMantissa);
3324 // No special expansion.
3325 result = DAG.getNode(ISD::FLOG, dl,
3326 getValue(I.getOperand(1)).getValueType(),
3327 getValue(I.getOperand(1)));
3330 setValue(&I, result);
3333 /// visitLog2 - Lower a log2 intrinsic. Handles the special sequences for
3334 /// limited-precision mode.
3336 SelectionDAGLowering::visitLog2(CallInst &I) {
3338 DebugLoc dl = getCurDebugLoc();
3340 if (getValue(I.getOperand(1)).getValueType() == MVT::f32 &&
3341 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3342 SDValue Op = getValue(I.getOperand(1));
3343 SDValue Op1 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, Op);
3345 // Get the exponent.
3346 SDValue LogOfExponent = GetExponent(DAG, Op1, TLI, dl);
3348 // Get the significand and build it into a floating-point number with
3350 SDValue X = GetSignificand(DAG, Op1, dl);
3352 // Different possible minimax approximations of significand in
3353 // floating-point for various degrees of accuracy over [1,2].
3354 if (LimitFloatPrecision <= 6) {
3355 // For floating-point precision of 6:
3357 // Log2ofMantissa = -1.6749035f + (2.0246817f - .34484768f * x) * x;
3359 // error 0.0049451742, which is more than 7 bits
3360 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3361 getF32Constant(DAG, 0xbeb08fe0));
3362 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3363 getF32Constant(DAG, 0x40019463));
3364 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3365 SDValue Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3366 getF32Constant(DAG, 0x3fd6633d));
3368 result = DAG.getNode(ISD::FADD, dl,
3369 MVT::f32, LogOfExponent, Log2ofMantissa);
3370 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
3371 // For floating-point precision of 12:
3377 // (.645142248f - 0.816157886e-1f * x) * x) * x) * x;
3379 // error 0.0000876136000, which is better than 13 bits
3380 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3381 getF32Constant(DAG, 0xbda7262e));
3382 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3383 getF32Constant(DAG, 0x3f25280b));
3384 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3385 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3386 getF32Constant(DAG, 0x4007b923));
3387 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3388 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3389 getF32Constant(DAG, 0x40823e2f));
3390 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3391 SDValue Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3392 getF32Constant(DAG, 0x4020d29c));
3394 result = DAG.getNode(ISD::FADD, dl,
3395 MVT::f32, LogOfExponent, Log2ofMantissa);
3396 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
3397 // For floating-point precision of 18:
3406 // 0.25691327e-1f * x) * x) * x) * x) * x) * x;
3408 // error 0.0000018516, which is better than 18 bits
3409 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3410 getF32Constant(DAG, 0xbcd2769e));
3411 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3412 getF32Constant(DAG, 0x3e8ce0b9));
3413 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3414 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3415 getF32Constant(DAG, 0x3fa22ae7));
3416 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3417 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3418 getF32Constant(DAG, 0x40525723));
3419 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3420 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3421 getF32Constant(DAG, 0x40aaf200));
3422 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3423 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3424 getF32Constant(DAG, 0x40c39dad));
3425 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3426 SDValue Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10,
3427 getF32Constant(DAG, 0x4042902c));
3429 result = DAG.getNode(ISD::FADD, dl,
3430 MVT::f32, LogOfExponent, Log2ofMantissa);
3433 // No special expansion.
3434 result = DAG.getNode(ISD::FLOG2, dl,
3435 getValue(I.getOperand(1)).getValueType(),
3436 getValue(I.getOperand(1)));
3439 setValue(&I, result);
3442 /// visitLog10 - Lower a log10 intrinsic. Handles the special sequences for
3443 /// limited-precision mode.
3445 SelectionDAGLowering::visitLog10(CallInst &I) {
3447 DebugLoc dl = getCurDebugLoc();
3449 if (getValue(I.getOperand(1)).getValueType() == MVT::f32 &&
3450 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3451 SDValue Op = getValue(I.getOperand(1));
3452 SDValue Op1 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, Op);
3454 // Scale the exponent by log10(2) [0.30102999f].
3455 SDValue Exp = GetExponent(DAG, Op1, TLI, dl);
3456 SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp,
3457 getF32Constant(DAG, 0x3e9a209a));
3459 // Get the significand and build it into a floating-point number with
3461 SDValue X = GetSignificand(DAG, Op1, dl);
3463 if (LimitFloatPrecision <= 6) {
3464 // For floating-point precision of 6:
3466 // Log10ofMantissa =
3468 // (0.60948995f - 0.10380950f * x) * x;
3470 // error 0.0014886165, which is 6 bits
3471 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3472 getF32Constant(DAG, 0xbdd49a13));
3473 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3474 getF32Constant(DAG, 0x3f1c0789));
3475 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3476 SDValue Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3477 getF32Constant(DAG, 0x3f011300));
3479 result = DAG.getNode(ISD::FADD, dl,
3480 MVT::f32, LogOfExponent, Log10ofMantissa);
3481 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
3482 // For floating-point precision of 12:
3484 // Log10ofMantissa =
3487 // (-0.31664806f + 0.47637168e-1f * x) * x) * x;
3489 // error 0.00019228036, which is better than 12 bits
3490 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3491 getF32Constant(DAG, 0x3d431f31));
3492 SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0,
3493 getF32Constant(DAG, 0x3ea21fb2));
3494 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3495 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3496 getF32Constant(DAG, 0x3f6ae232));
3497 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3498 SDValue Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4,
3499 getF32Constant(DAG, 0x3f25f7c3));
3501 result = DAG.getNode(ISD::FADD, dl,
3502 MVT::f32, LogOfExponent, Log10ofMantissa);
3503 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
3504 // For floating-point precision of 18:
3506 // Log10ofMantissa =
3511 // (-0.12539807f + 0.13508273e-1f * x) * x) * x) * x) * x;
3513 // error 0.0000037995730, which is better than 18 bits
3514 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3515 getF32Constant(DAG, 0x3c5d51ce));
3516 SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0,
3517 getF32Constant(DAG, 0x3e00685a));
3518 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3519 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3520 getF32Constant(DAG, 0x3efb6798));
3521 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3522 SDValue t5 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4,
3523 getF32Constant(DAG, 0x3f88d192));
3524 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3525 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3526 getF32Constant(DAG, 0x3fc4316c));
3527 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3528 SDValue Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t8,
3529 getF32Constant(DAG, 0x3f57ce70));
3531 result = DAG.getNode(ISD::FADD, dl,
3532 MVT::f32, LogOfExponent, Log10ofMantissa);
3535 // No special expansion.
3536 result = DAG.getNode(ISD::FLOG10, dl,
3537 getValue(I.getOperand(1)).getValueType(),
3538 getValue(I.getOperand(1)));
3541 setValue(&I, result);
3544 /// visitExp2 - Lower an exp2 intrinsic. Handles the special sequences for
3545 /// limited-precision mode.
3547 SelectionDAGLowering::visitExp2(CallInst &I) {
3549 DebugLoc dl = getCurDebugLoc();
3551 if (getValue(I.getOperand(1)).getValueType() == MVT::f32 &&
3552 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3553 SDValue Op = getValue(I.getOperand(1));
3555 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, Op);
3557 // FractionalPartOfX = x - (float)IntegerPartOfX;
3558 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX);
3559 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, Op, t1);
3561 // IntegerPartOfX <<= 23;
3562 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX,
3563 DAG.getConstant(23, TLI.getPointerTy()));
3565 if (LimitFloatPrecision <= 6) {
3566 // For floating-point precision of 6:
3568 // TwoToFractionalPartOfX =
3570 // (0.735607626f + 0.252464424f * x) * x;
3572 // error 0.0144103317, which is 6 bits
3573 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3574 getF32Constant(DAG, 0x3e814304));
3575 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3576 getF32Constant(DAG, 0x3f3c50c8));
3577 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3578 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3579 getF32Constant(DAG, 0x3f7f5e7e));
3580 SDValue t6 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, t5);
3581 SDValue TwoToFractionalPartOfX =
3582 DAG.getNode(ISD::ADD, dl, MVT::i32, t6, IntegerPartOfX);
3584 result = DAG.getNode(ISD::BIT_CONVERT, dl,
3585 MVT::f32, TwoToFractionalPartOfX);
3586 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
3587 // For floating-point precision of 12:
3589 // TwoToFractionalPartOfX =
3592 // (0.224338339f + 0.792043434e-1f * x) * x) * x;
3594 // error 0.000107046256, which is 13 to 14 bits
3595 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3596 getF32Constant(DAG, 0x3da235e3));
3597 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3598 getF32Constant(DAG, 0x3e65b8f3));
3599 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3600 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3601 getF32Constant(DAG, 0x3f324b07));
3602 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3603 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3604 getF32Constant(DAG, 0x3f7ff8fd));
3605 SDValue t8 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, t7);
3606 SDValue TwoToFractionalPartOfX =
3607 DAG.getNode(ISD::ADD, dl, MVT::i32, t8, IntegerPartOfX);
3609 result = DAG.getNode(ISD::BIT_CONVERT, dl,
3610 MVT::f32, TwoToFractionalPartOfX);
3611 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
3612 // For floating-point precision of 18:
3614 // TwoToFractionalPartOfX =
3618 // (0.554906021e-1f +
3619 // (0.961591928e-2f +
3620 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x;
3621 // error 2.47208000*10^(-7), which is better than 18 bits
3622 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3623 getF32Constant(DAG, 0x3924b03e));
3624 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3625 getF32Constant(DAG, 0x3ab24b87));
3626 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3627 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3628 getF32Constant(DAG, 0x3c1d8c17));
3629 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3630 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3631 getF32Constant(DAG, 0x3d634a1d));
3632 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3633 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3634 getF32Constant(DAG, 0x3e75fe14));
3635 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3636 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10,
3637 getF32Constant(DAG, 0x3f317234));
3638 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X);
3639 SDValue t13 = DAG.getNode(ISD::FADD, dl, MVT::f32, t12,
3640 getF32Constant(DAG, 0x3f800000));
3641 SDValue t14 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, t13);
3642 SDValue TwoToFractionalPartOfX =
3643 DAG.getNode(ISD::ADD, dl, MVT::i32, t14, IntegerPartOfX);
3645 result = DAG.getNode(ISD::BIT_CONVERT, dl,
3646 MVT::f32, TwoToFractionalPartOfX);
3649 // No special expansion.
3650 result = DAG.getNode(ISD::FEXP2, dl,
3651 getValue(I.getOperand(1)).getValueType(),
3652 getValue(I.getOperand(1)));
3655 setValue(&I, result);
3658 /// visitPow - Lower a pow intrinsic. Handles the special sequences for
3659 /// limited-precision mode with x == 10.0f.
3661 SelectionDAGLowering::visitPow(CallInst &I) {
3663 Value *Val = I.getOperand(1);
3664 DebugLoc dl = getCurDebugLoc();
3665 bool IsExp10 = false;
3667 if (getValue(Val).getValueType() == MVT::f32 &&
3668 getValue(I.getOperand(2)).getValueType() == MVT::f32 &&
3669 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3670 if (Constant *C = const_cast<Constant*>(dyn_cast<Constant>(Val))) {
3671 if (ConstantFP *CFP = dyn_cast<ConstantFP>(C)) {
3673 IsExp10 = CFP->getValueAPF().bitwiseIsEqual(Ten);
3678 if (IsExp10 && LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3679 SDValue Op = getValue(I.getOperand(2));
3681 // Put the exponent in the right bit position for later addition to the
3684 // #define LOG2OF10 3.3219281f
3685 // IntegerPartOfX = (int32_t)(x * LOG2OF10);
3686 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, Op,
3687 getF32Constant(DAG, 0x40549a78));
3688 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, t0);
3690 // FractionalPartOfX = x - (float)IntegerPartOfX;
3691 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX);
3692 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, t1);
3694 // IntegerPartOfX <<= 23;
3695 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX,
3696 DAG.getConstant(23, TLI.getPointerTy()));
3698 if (LimitFloatPrecision <= 6) {
3699 // For floating-point precision of 6:
3701 // twoToFractionalPartOfX =
3703 // (0.735607626f + 0.252464424f * x) * x;
3705 // error 0.0144103317, which is 6 bits
3706 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3707 getF32Constant(DAG, 0x3e814304));
3708 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3709 getF32Constant(DAG, 0x3f3c50c8));
3710 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3711 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3712 getF32Constant(DAG, 0x3f7f5e7e));
3713 SDValue t6 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, t5);
3714 SDValue TwoToFractionalPartOfX =
3715 DAG.getNode(ISD::ADD, dl, MVT::i32, t6, IntegerPartOfX);
3717 result = DAG.getNode(ISD::BIT_CONVERT, dl,
3718 MVT::f32, TwoToFractionalPartOfX);
3719 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
3720 // For floating-point precision of 12:
3722 // TwoToFractionalPartOfX =
3725 // (0.224338339f + 0.792043434e-1f * x) * x) * x;
3727 // error 0.000107046256, which is 13 to 14 bits
3728 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3729 getF32Constant(DAG, 0x3da235e3));
3730 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3731 getF32Constant(DAG, 0x3e65b8f3));
3732 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3733 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3734 getF32Constant(DAG, 0x3f324b07));
3735 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3736 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3737 getF32Constant(DAG, 0x3f7ff8fd));
3738 SDValue t8 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, t7);
3739 SDValue TwoToFractionalPartOfX =
3740 DAG.getNode(ISD::ADD, dl, MVT::i32, t8, IntegerPartOfX);
3742 result = DAG.getNode(ISD::BIT_CONVERT, dl,
3743 MVT::f32, TwoToFractionalPartOfX);
3744 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
3745 // For floating-point precision of 18:
3747 // TwoToFractionalPartOfX =
3751 // (0.554906021e-1f +
3752 // (0.961591928e-2f +
3753 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x;
3754 // error 2.47208000*10^(-7), which is better than 18 bits
3755 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3756 getF32Constant(DAG, 0x3924b03e));
3757 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3758 getF32Constant(DAG, 0x3ab24b87));
3759 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3760 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3761 getF32Constant(DAG, 0x3c1d8c17));
3762 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3763 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3764 getF32Constant(DAG, 0x3d634a1d));
3765 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3766 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3767 getF32Constant(DAG, 0x3e75fe14));
3768 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3769 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10,
3770 getF32Constant(DAG, 0x3f317234));
3771 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X);
3772 SDValue t13 = DAG.getNode(ISD::FADD, dl, MVT::f32, t12,
3773 getF32Constant(DAG, 0x3f800000));
3774 SDValue t14 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, t13);
3775 SDValue TwoToFractionalPartOfX =
3776 DAG.getNode(ISD::ADD, dl, MVT::i32, t14, IntegerPartOfX);
3778 result = DAG.getNode(ISD::BIT_CONVERT, dl,
3779 MVT::f32, TwoToFractionalPartOfX);
3782 // No special expansion.
3783 result = DAG.getNode(ISD::FPOW, dl,
3784 getValue(I.getOperand(1)).getValueType(),
3785 getValue(I.getOperand(1)),
3786 getValue(I.getOperand(2)));
3789 setValue(&I, result);
3792 /// visitIntrinsicCall - Lower the call to the specified intrinsic function. If
3793 /// we want to emit this as a call to a named external function, return the name
3794 /// otherwise lower it and return null.
3796 SelectionDAGLowering::visitIntrinsicCall(CallInst &I, unsigned Intrinsic) {
3797 DebugLoc dl = getCurDebugLoc();
3798 switch (Intrinsic) {
3800 // By default, turn this into a target intrinsic node.
3801 visitTargetIntrinsic(I, Intrinsic);
3803 case Intrinsic::vastart: visitVAStart(I); return 0;
3804 case Intrinsic::vaend: visitVAEnd(I); return 0;
3805 case Intrinsic::vacopy: visitVACopy(I); return 0;
3806 case Intrinsic::returnaddress:
3807 setValue(&I, DAG.getNode(ISD::RETURNADDR, dl, TLI.getPointerTy(),
3808 getValue(I.getOperand(1))));
3810 case Intrinsic::frameaddress:
3811 setValue(&I, DAG.getNode(ISD::FRAMEADDR, dl, TLI.getPointerTy(),
3812 getValue(I.getOperand(1))));
3814 case Intrinsic::setjmp:
3815 return "_setjmp"+!TLI.usesUnderscoreSetJmp();
3817 case Intrinsic::longjmp:
3818 return "_longjmp"+!TLI.usesUnderscoreLongJmp();
3820 case Intrinsic::memcpy: {
3821 SDValue Op1 = getValue(I.getOperand(1));
3822 SDValue Op2 = getValue(I.getOperand(2));
3823 SDValue Op3 = getValue(I.getOperand(3));
3824 unsigned Align = cast<ConstantInt>(I.getOperand(4))->getZExtValue();
3825 DAG.setRoot(DAG.getMemcpy(getRoot(), dl, Op1, Op2, Op3, Align, false,
3826 I.getOperand(1), 0, I.getOperand(2), 0));
3829 case Intrinsic::memset: {
3830 SDValue Op1 = getValue(I.getOperand(1));
3831 SDValue Op2 = getValue(I.getOperand(2));
3832 SDValue Op3 = getValue(I.getOperand(3));
3833 unsigned Align = cast<ConstantInt>(I.getOperand(4))->getZExtValue();
3834 DAG.setRoot(DAG.getMemset(getRoot(), dl, Op1, Op2, Op3, Align,
3835 I.getOperand(1), 0));
3838 case Intrinsic::memmove: {
3839 SDValue Op1 = getValue(I.getOperand(1));
3840 SDValue Op2 = getValue(I.getOperand(2));
3841 SDValue Op3 = getValue(I.getOperand(3));
3842 unsigned Align = cast<ConstantInt>(I.getOperand(4))->getZExtValue();
3844 // If the source and destination are known to not be aliases, we can
3845 // lower memmove as memcpy.
3846 uint64_t Size = -1ULL;
3847 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op3))
3848 Size = C->getZExtValue();
3849 if (AA->alias(I.getOperand(1), Size, I.getOperand(2), Size) ==
3850 AliasAnalysis::NoAlias) {
3851 DAG.setRoot(DAG.getMemcpy(getRoot(), dl, Op1, Op2, Op3, Align, false,
3852 I.getOperand(1), 0, I.getOperand(2), 0));
3856 DAG.setRoot(DAG.getMemmove(getRoot(), dl, Op1, Op2, Op3, Align,
3857 I.getOperand(1), 0, I.getOperand(2), 0));
3860 case Intrinsic::dbg_stoppoint: {
3861 DbgStopPointInst &SPI = cast<DbgStopPointInst>(I);
3862 if (isValidDebugInfoIntrinsic(SPI, CodeGenOpt::Default)) {
3863 MachineFunction &MF = DAG.getMachineFunction();
3864 DebugLoc Loc = ExtractDebugLocation(SPI, MF.getDebugLocInfo());
3865 setCurDebugLoc(Loc);
3867 if (OptLevel == CodeGenOpt::None)
3868 DAG.setRoot(DAG.getDbgStopPoint(Loc, getRoot(),
3875 case Intrinsic::dbg_region_start: {
3876 DwarfWriter *DW = DAG.getDwarfWriter();
3877 DbgRegionStartInst &RSI = cast<DbgRegionStartInst>(I);
3878 if (isValidDebugInfoIntrinsic(RSI, OptLevel) && DW
3879 && DW->ShouldEmitDwarfDebug()) {
3881 DW->RecordRegionStart(cast<GlobalVariable>(RSI.getContext()));
3882 DAG.setRoot(DAG.getLabel(ISD::DBG_LABEL, getCurDebugLoc(),
3883 getRoot(), LabelID));
3887 case Intrinsic::dbg_region_end: {
3888 DwarfWriter *DW = DAG.getDwarfWriter();
3889 DbgRegionEndInst &REI = cast<DbgRegionEndInst>(I);
3891 if (!isValidDebugInfoIntrinsic(REI, OptLevel) || !DW
3892 || !DW->ShouldEmitDwarfDebug())
3895 MachineFunction &MF = DAG.getMachineFunction();
3896 DISubprogram Subprogram(cast<GlobalVariable>(REI.getContext()));
3898 if (isInlinedFnEnd(REI, MF.getFunction())) {
3899 // This is end of inlined function. Debugging information for inlined
3900 // function is not handled yet (only supported by FastISel).
3901 if (OptLevel == CodeGenOpt::None) {
3902 unsigned ID = DW->RecordInlinedFnEnd(Subprogram);
3904 // Returned ID is 0 if this is unbalanced "end of inlined
3905 // scope". This could happen if optimizer eats dbg intrinsics or
3906 // "beginning of inlined scope" is not recoginized due to missing
3907 // location info. In such cases, do ignore this region.end.
3908 DAG.setRoot(DAG.getLabel(ISD::DBG_LABEL, getCurDebugLoc(),
3915 DW->RecordRegionEnd(cast<GlobalVariable>(REI.getContext()));
3916 DAG.setRoot(DAG.getLabel(ISD::DBG_LABEL, getCurDebugLoc(),
3917 getRoot(), LabelID));
3920 case Intrinsic::dbg_func_start: {
3921 DwarfWriter *DW = DAG.getDwarfWriter();
3922 DbgFuncStartInst &FSI = cast<DbgFuncStartInst>(I);
3923 if (!isValidDebugInfoIntrinsic(FSI, CodeGenOpt::None))
3926 MachineFunction &MF = DAG.getMachineFunction();
3927 // This is a beginning of an inlined function.
3928 if (isInlinedFnStart(FSI, MF.getFunction())) {
3929 if (OptLevel != CodeGenOpt::None)
3930 // FIXME: Debugging informaation for inlined function is only
3931 // supported at CodeGenOpt::Node.
3934 DebugLoc PrevLoc = CurDebugLoc;
3935 // If llvm.dbg.func.start is seen in a new block before any
3936 // llvm.dbg.stoppoint intrinsic then the location info is unknown.
3937 // FIXME : Why DebugLoc is reset at the beginning of each block ?
3938 if (PrevLoc.isUnknown())
3941 // Record the source line.
3942 setCurDebugLoc(ExtractDebugLocation(FSI, MF.getDebugLocInfo()));
3944 if (!DW || !DW->ShouldEmitDwarfDebug())
3946 DebugLocTuple PrevLocTpl = MF.getDebugLocTuple(PrevLoc);
3947 DISubprogram SP(cast<GlobalVariable>(FSI.getSubprogram()));
3948 DICompileUnit CU(PrevLocTpl.CompileUnit);
3949 unsigned LabelID = DW->RecordInlinedFnStart(SP, CU,
3952 DAG.setRoot(DAG.getLabel(ISD::DBG_LABEL, getCurDebugLoc(),
3953 getRoot(), LabelID));
3957 // This is a beginning of a new function.
3958 MF.setDefaultDebugLoc(ExtractDebugLocation(FSI, MF.getDebugLocInfo()));
3960 if (!DW || !DW->ShouldEmitDwarfDebug())
3962 // llvm.dbg.func_start also defines beginning of function scope.
3963 DW->RecordRegionStart(cast<GlobalVariable>(FSI.getSubprogram()));
3966 case Intrinsic::dbg_declare: {
3967 if (OptLevel != CodeGenOpt::None)
3968 // FIXME: Variable debug info is not supported here.
3971 DbgDeclareInst &DI = cast<DbgDeclareInst>(I);
3972 if (!isValidDebugInfoIntrinsic(DI, CodeGenOpt::None))
3975 Value *Variable = DI.getVariable();
3976 DAG.setRoot(DAG.getNode(ISD::DECLARE, dl, MVT::Other, getRoot(),
3977 getValue(DI.getAddress()), getValue(Variable)));
3980 case Intrinsic::eh_exception: {
3981 // Insert the EXCEPTIONADDR instruction.
3982 assert(CurMBB->isLandingPad() &&"Call to eh.exception not in landing pad!");
3983 SDVTList VTs = DAG.getVTList(TLI.getPointerTy(), MVT::Other);
3985 Ops[0] = DAG.getRoot();
3986 SDValue Op = DAG.getNode(ISD::EXCEPTIONADDR, dl, VTs, Ops, 1);
3988 DAG.setRoot(Op.getValue(1));
3992 case Intrinsic::eh_selector_i32:
3993 case Intrinsic::eh_selector_i64: {
3994 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
3995 MVT VT = (Intrinsic == Intrinsic::eh_selector_i32 ?
3996 MVT::i32 : MVT::i64);
3999 if (CurMBB->isLandingPad())
4000 AddCatchInfo(I, MMI, CurMBB);
4003 FuncInfo.CatchInfoLost.insert(&I);
4005 // FIXME: Mark exception selector register as live in. Hack for PR1508.
4006 unsigned Reg = TLI.getExceptionSelectorRegister();
4007 if (Reg) CurMBB->addLiveIn(Reg);
4010 // Insert the EHSELECTION instruction.
4011 SDVTList VTs = DAG.getVTList(VT, MVT::Other);
4013 Ops[0] = getValue(I.getOperand(1));
4015 SDValue Op = DAG.getNode(ISD::EHSELECTION, dl, VTs, Ops, 2);
4017 DAG.setRoot(Op.getValue(1));
4019 setValue(&I, DAG.getConstant(0, VT));
4025 case Intrinsic::eh_typeid_for_i32:
4026 case Intrinsic::eh_typeid_for_i64: {
4027 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
4028 MVT VT = (Intrinsic == Intrinsic::eh_typeid_for_i32 ?
4029 MVT::i32 : MVT::i64);
4032 // Find the type id for the given typeinfo.
4033 GlobalVariable *GV = ExtractTypeInfo(I.getOperand(1));
4035 unsigned TypeID = MMI->getTypeIDFor(GV);
4036 setValue(&I, DAG.getConstant(TypeID, VT));
4038 // Return something different to eh_selector.
4039 setValue(&I, DAG.getConstant(1, VT));
4045 case Intrinsic::eh_return_i32:
4046 case Intrinsic::eh_return_i64:
4047 if (MachineModuleInfo *MMI = DAG.getMachineModuleInfo()) {
4048 MMI->setCallsEHReturn(true);
4049 DAG.setRoot(DAG.getNode(ISD::EH_RETURN, dl,
4052 getValue(I.getOperand(1)),
4053 getValue(I.getOperand(2))));
4055 setValue(&I, DAG.getConstant(0, TLI.getPointerTy()));
4059 case Intrinsic::eh_unwind_init:
4060 if (MachineModuleInfo *MMI = DAG.getMachineModuleInfo()) {
4061 MMI->setCallsUnwindInit(true);
4066 case Intrinsic::eh_dwarf_cfa: {
4067 MVT VT = getValue(I.getOperand(1)).getValueType();
4069 if (VT.bitsGT(TLI.getPointerTy()))
4070 CfaArg = DAG.getNode(ISD::TRUNCATE, dl,
4071 TLI.getPointerTy(), getValue(I.getOperand(1)));
4073 CfaArg = DAG.getNode(ISD::SIGN_EXTEND, dl,
4074 TLI.getPointerTy(), getValue(I.getOperand(1)));
4076 SDValue Offset = DAG.getNode(ISD::ADD, dl,
4078 DAG.getNode(ISD::FRAME_TO_ARGS_OFFSET, dl,
4079 TLI.getPointerTy()),
4081 setValue(&I, DAG.getNode(ISD::ADD, dl,
4083 DAG.getNode(ISD::FRAMEADDR, dl,
4086 TLI.getPointerTy())),
4091 case Intrinsic::convertff:
4092 case Intrinsic::convertfsi:
4093 case Intrinsic::convertfui:
4094 case Intrinsic::convertsif:
4095 case Intrinsic::convertuif:
4096 case Intrinsic::convertss:
4097 case Intrinsic::convertsu:
4098 case Intrinsic::convertus:
4099 case Intrinsic::convertuu: {
4100 ISD::CvtCode Code = ISD::CVT_INVALID;
4101 switch (Intrinsic) {
4102 case Intrinsic::convertff: Code = ISD::CVT_FF; break;
4103 case Intrinsic::convertfsi: Code = ISD::CVT_FS; break;
4104 case Intrinsic::convertfui: Code = ISD::CVT_FU; break;
4105 case Intrinsic::convertsif: Code = ISD::CVT_SF; break;
4106 case Intrinsic::convertuif: Code = ISD::CVT_UF; break;
4107 case Intrinsic::convertss: Code = ISD::CVT_SS; break;
4108 case Intrinsic::convertsu: Code = ISD::CVT_SU; break;
4109 case Intrinsic::convertus: Code = ISD::CVT_US; break;
4110 case Intrinsic::convertuu: Code = ISD::CVT_UU; break;
4112 MVT DestVT = TLI.getValueType(I.getType());
4113 Value* Op1 = I.getOperand(1);
4114 setValue(&I, DAG.getConvertRndSat(DestVT, getCurDebugLoc(), getValue(Op1),
4115 DAG.getValueType(DestVT),
4116 DAG.getValueType(getValue(Op1).getValueType()),
4117 getValue(I.getOperand(2)),
4118 getValue(I.getOperand(3)),
4123 case Intrinsic::sqrt:
4124 setValue(&I, DAG.getNode(ISD::FSQRT, dl,
4125 getValue(I.getOperand(1)).getValueType(),
4126 getValue(I.getOperand(1))));
4128 case Intrinsic::powi:
4129 setValue(&I, DAG.getNode(ISD::FPOWI, dl,
4130 getValue(I.getOperand(1)).getValueType(),
4131 getValue(I.getOperand(1)),
4132 getValue(I.getOperand(2))));
4134 case Intrinsic::sin:
4135 setValue(&I, DAG.getNode(ISD::FSIN, dl,
4136 getValue(I.getOperand(1)).getValueType(),
4137 getValue(I.getOperand(1))));
4139 case Intrinsic::cos:
4140 setValue(&I, DAG.getNode(ISD::FCOS, dl,
4141 getValue(I.getOperand(1)).getValueType(),
4142 getValue(I.getOperand(1))));
4144 case Intrinsic::log:
4147 case Intrinsic::log2:
4150 case Intrinsic::log10:
4153 case Intrinsic::exp:
4156 case Intrinsic::exp2:
4159 case Intrinsic::pow:
4162 case Intrinsic::pcmarker: {
4163 SDValue Tmp = getValue(I.getOperand(1));
4164 DAG.setRoot(DAG.getNode(ISD::PCMARKER, dl, MVT::Other, getRoot(), Tmp));
4167 case Intrinsic::readcyclecounter: {
4168 SDValue Op = getRoot();
4169 SDValue Tmp = DAG.getNode(ISD::READCYCLECOUNTER, dl,
4170 DAG.getVTList(MVT::i64, MVT::Other),
4173 DAG.setRoot(Tmp.getValue(1));
4176 case Intrinsic::bswap:
4177 setValue(&I, DAG.getNode(ISD::BSWAP, dl,
4178 getValue(I.getOperand(1)).getValueType(),
4179 getValue(I.getOperand(1))));
4181 case Intrinsic::cttz: {
4182 SDValue Arg = getValue(I.getOperand(1));
4183 MVT Ty = Arg.getValueType();
4184 SDValue result = DAG.getNode(ISD::CTTZ, dl, Ty, Arg);
4185 setValue(&I, result);
4188 case Intrinsic::ctlz: {
4189 SDValue Arg = getValue(I.getOperand(1));
4190 MVT Ty = Arg.getValueType();
4191 SDValue result = DAG.getNode(ISD::CTLZ, dl, Ty, Arg);
4192 setValue(&I, result);
4195 case Intrinsic::ctpop: {
4196 SDValue Arg = getValue(I.getOperand(1));
4197 MVT Ty = Arg.getValueType();
4198 SDValue result = DAG.getNode(ISD::CTPOP, dl, Ty, Arg);
4199 setValue(&I, result);
4202 case Intrinsic::stacksave: {
4203 SDValue Op = getRoot();
4204 SDValue Tmp = DAG.getNode(ISD::STACKSAVE, dl,
4205 DAG.getVTList(TLI.getPointerTy(), MVT::Other), &Op, 1);
4207 DAG.setRoot(Tmp.getValue(1));
4210 case Intrinsic::stackrestore: {
4211 SDValue Tmp = getValue(I.getOperand(1));
4212 DAG.setRoot(DAG.getNode(ISD::STACKRESTORE, dl, MVT::Other, getRoot(), Tmp));
4215 case Intrinsic::stackprotector: {
4216 // Emit code into the DAG to store the stack guard onto the stack.
4217 MachineFunction &MF = DAG.getMachineFunction();
4218 MachineFrameInfo *MFI = MF.getFrameInfo();
4219 MVT PtrTy = TLI.getPointerTy();
4221 SDValue Src = getValue(I.getOperand(1)); // The guard's value.
4222 AllocaInst *Slot = cast<AllocaInst>(I.getOperand(2));
4224 int FI = FuncInfo.StaticAllocaMap[Slot];
4225 MFI->setStackProtectorIndex(FI);
4227 SDValue FIN = DAG.getFrameIndex(FI, PtrTy);
4229 // Store the stack protector onto the stack.
4230 SDValue Result = DAG.getStore(getRoot(), getCurDebugLoc(), Src, FIN,
4231 PseudoSourceValue::getFixedStack(FI),
4233 setValue(&I, Result);
4234 DAG.setRoot(Result);
4237 case Intrinsic::var_annotation:
4238 // Discard annotate attributes
4241 case Intrinsic::init_trampoline: {
4242 const Function *F = cast<Function>(I.getOperand(2)->stripPointerCasts());
4246 Ops[1] = getValue(I.getOperand(1));
4247 Ops[2] = getValue(I.getOperand(2));
4248 Ops[3] = getValue(I.getOperand(3));
4249 Ops[4] = DAG.getSrcValue(I.getOperand(1));
4250 Ops[5] = DAG.getSrcValue(F);
4252 SDValue Tmp = DAG.getNode(ISD::TRAMPOLINE, dl,
4253 DAG.getVTList(TLI.getPointerTy(), MVT::Other),
4257 DAG.setRoot(Tmp.getValue(1));
4261 case Intrinsic::gcroot:
4263 Value *Alloca = I.getOperand(1);
4264 Constant *TypeMap = cast<Constant>(I.getOperand(2));
4266 FrameIndexSDNode *FI = cast<FrameIndexSDNode>(getValue(Alloca).getNode());
4267 GFI->addStackRoot(FI->getIndex(), TypeMap);
4271 case Intrinsic::gcread:
4272 case Intrinsic::gcwrite:
4273 llvm_unreachable("GC failed to lower gcread/gcwrite intrinsics!");
4276 case Intrinsic::flt_rounds: {
4277 setValue(&I, DAG.getNode(ISD::FLT_ROUNDS_, dl, MVT::i32));
4281 case Intrinsic::trap: {
4282 DAG.setRoot(DAG.getNode(ISD::TRAP, dl,MVT::Other, getRoot()));
4286 case Intrinsic::uadd_with_overflow:
4287 return implVisitAluOverflow(I, ISD::UADDO);
4288 case Intrinsic::sadd_with_overflow:
4289 return implVisitAluOverflow(I, ISD::SADDO);
4290 case Intrinsic::usub_with_overflow:
4291 return implVisitAluOverflow(I, ISD::USUBO);
4292 case Intrinsic::ssub_with_overflow:
4293 return implVisitAluOverflow(I, ISD::SSUBO);
4294 case Intrinsic::umul_with_overflow:
4295 return implVisitAluOverflow(I, ISD::UMULO);
4296 case Intrinsic::smul_with_overflow:
4297 return implVisitAluOverflow(I, ISD::SMULO);
4299 case Intrinsic::prefetch: {
4302 Ops[1] = getValue(I.getOperand(1));
4303 Ops[2] = getValue(I.getOperand(2));
4304 Ops[3] = getValue(I.getOperand(3));
4305 DAG.setRoot(DAG.getNode(ISD::PREFETCH, dl, MVT::Other, &Ops[0], 4));
4309 case Intrinsic::memory_barrier: {
4312 for (int x = 1; x < 6; ++x)
4313 Ops[x] = getValue(I.getOperand(x));
4315 DAG.setRoot(DAG.getNode(ISD::MEMBARRIER, dl, MVT::Other, &Ops[0], 6));
4318 case Intrinsic::atomic_cmp_swap: {
4319 SDValue Root = getRoot();
4321 DAG.getAtomic(ISD::ATOMIC_CMP_SWAP, getCurDebugLoc(),
4322 getValue(I.getOperand(2)).getValueType().getSimpleVT(),
4324 getValue(I.getOperand(1)),
4325 getValue(I.getOperand(2)),
4326 getValue(I.getOperand(3)),
4329 DAG.setRoot(L.getValue(1));
4332 case Intrinsic::atomic_load_add:
4333 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_ADD);
4334 case Intrinsic::atomic_load_sub:
4335 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_SUB);
4336 case Intrinsic::atomic_load_or:
4337 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_OR);
4338 case Intrinsic::atomic_load_xor:
4339 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_XOR);
4340 case Intrinsic::atomic_load_and:
4341 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_AND);
4342 case Intrinsic::atomic_load_nand:
4343 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_NAND);
4344 case Intrinsic::atomic_load_max:
4345 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_MAX);
4346 case Intrinsic::atomic_load_min:
4347 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_MIN);
4348 case Intrinsic::atomic_load_umin:
4349 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_UMIN);
4350 case Intrinsic::atomic_load_umax:
4351 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_UMAX);
4352 case Intrinsic::atomic_swap:
4353 return implVisitBinaryAtomic(I, ISD::ATOMIC_SWAP);
4358 void SelectionDAGLowering::LowerCallTo(CallSite CS, SDValue Callee,
4360 MachineBasicBlock *LandingPad) {
4361 const PointerType *PT = cast<PointerType>(CS.getCalledValue()->getType());
4362 const FunctionType *FTy = cast<FunctionType>(PT->getElementType());
4363 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
4364 unsigned BeginLabel = 0, EndLabel = 0;
4366 TargetLowering::ArgListTy Args;
4367 TargetLowering::ArgListEntry Entry;
4368 Args.reserve(CS.arg_size());
4369 for (CallSite::arg_iterator i = CS.arg_begin(), e = CS.arg_end();
4371 SDValue ArgNode = getValue(*i);
4372 Entry.Node = ArgNode; Entry.Ty = (*i)->getType();
4374 unsigned attrInd = i - CS.arg_begin() + 1;
4375 Entry.isSExt = CS.paramHasAttr(attrInd, Attribute::SExt);
4376 Entry.isZExt = CS.paramHasAttr(attrInd, Attribute::ZExt);
4377 Entry.isInReg = CS.paramHasAttr(attrInd, Attribute::InReg);
4378 Entry.isSRet = CS.paramHasAttr(attrInd, Attribute::StructRet);
4379 Entry.isNest = CS.paramHasAttr(attrInd, Attribute::Nest);
4380 Entry.isByVal = CS.paramHasAttr(attrInd, Attribute::ByVal);
4381 Entry.Alignment = CS.getParamAlignment(attrInd);
4382 Args.push_back(Entry);
4385 if (LandingPad && MMI) {
4386 // Insert a label before the invoke call to mark the try range. This can be
4387 // used to detect deletion of the invoke via the MachineModuleInfo.
4388 BeginLabel = MMI->NextLabelID();
4389 // Both PendingLoads and PendingExports must be flushed here;
4390 // this call might not return.
4392 DAG.setRoot(DAG.getLabel(ISD::EH_LABEL, getCurDebugLoc(),
4393 getControlRoot(), BeginLabel));
4396 std::pair<SDValue,SDValue> Result =
4397 TLI.LowerCallTo(getRoot(), CS.getType(),
4398 CS.paramHasAttr(0, Attribute::SExt),
4399 CS.paramHasAttr(0, Attribute::ZExt), FTy->isVarArg(),
4400 CS.paramHasAttr(0, Attribute::InReg), FTy->getNumParams(),
4401 CS.getCallingConv(),
4402 IsTailCall && PerformTailCallOpt,
4403 Callee, Args, DAG, getCurDebugLoc());
4404 if (CS.getType() != Type::VoidTy)
4405 setValue(CS.getInstruction(), Result.first);
4406 DAG.setRoot(Result.second);
4408 if (LandingPad && MMI) {
4409 // Insert a label at the end of the invoke call to mark the try range. This
4410 // can be used to detect deletion of the invoke via the MachineModuleInfo.
4411 EndLabel = MMI->NextLabelID();
4412 DAG.setRoot(DAG.getLabel(ISD::EH_LABEL, getCurDebugLoc(),
4413 getRoot(), EndLabel));
4415 // Inform MachineModuleInfo of range.
4416 MMI->addInvoke(LandingPad, BeginLabel, EndLabel);
4421 void SelectionDAGLowering::visitCall(CallInst &I) {
4422 const char *RenameFn = 0;
4423 if (Function *F = I.getCalledFunction()) {
4424 if (F->isDeclaration()) {
4425 const TargetIntrinsicInfo *II = TLI.getTargetMachine().getIntrinsicInfo();
4427 if (unsigned IID = II->getIntrinsicID(F)) {
4428 RenameFn = visitIntrinsicCall(I, IID);
4433 if (unsigned IID = F->getIntrinsicID()) {
4434 RenameFn = visitIntrinsicCall(I, IID);
4440 // Check for well-known libc/libm calls. If the function is internal, it
4441 // can't be a library call.
4442 unsigned NameLen = F->getNameLen();
4443 if (!F->hasLocalLinkage() && NameLen) {
4444 const char *NameStr = F->getNameStart();
4445 if (NameStr[0] == 'c' &&
4446 ((NameLen == 8 && !strcmp(NameStr, "copysign")) ||
4447 (NameLen == 9 && !strcmp(NameStr, "copysignf")))) {
4448 if (I.getNumOperands() == 3 && // Basic sanity checks.
4449 I.getOperand(1)->getType()->isFloatingPoint() &&
4450 I.getType() == I.getOperand(1)->getType() &&
4451 I.getType() == I.getOperand(2)->getType()) {
4452 SDValue LHS = getValue(I.getOperand(1));
4453 SDValue RHS = getValue(I.getOperand(2));
4454 setValue(&I, DAG.getNode(ISD::FCOPYSIGN, getCurDebugLoc(),
4455 LHS.getValueType(), LHS, RHS));
4458 } else if (NameStr[0] == 'f' &&
4459 ((NameLen == 4 && !strcmp(NameStr, "fabs")) ||
4460 (NameLen == 5 && !strcmp(NameStr, "fabsf")) ||
4461 (NameLen == 5 && !strcmp(NameStr, "fabsl")))) {
4462 if (I.getNumOperands() == 2 && // Basic sanity checks.
4463 I.getOperand(1)->getType()->isFloatingPoint() &&
4464 I.getType() == I.getOperand(1)->getType()) {
4465 SDValue Tmp = getValue(I.getOperand(1));
4466 setValue(&I, DAG.getNode(ISD::FABS, getCurDebugLoc(),
4467 Tmp.getValueType(), Tmp));
4470 } else if (NameStr[0] == 's' &&
4471 ((NameLen == 3 && !strcmp(NameStr, "sin")) ||
4472 (NameLen == 4 && !strcmp(NameStr, "sinf")) ||
4473 (NameLen == 4 && !strcmp(NameStr, "sinl")))) {
4474 if (I.getNumOperands() == 2 && // Basic sanity checks.
4475 I.getOperand(1)->getType()->isFloatingPoint() &&
4476 I.getType() == I.getOperand(1)->getType()) {
4477 SDValue Tmp = getValue(I.getOperand(1));
4478 setValue(&I, DAG.getNode(ISD::FSIN, getCurDebugLoc(),
4479 Tmp.getValueType(), Tmp));
4482 } else if (NameStr[0] == 'c' &&
4483 ((NameLen == 3 && !strcmp(NameStr, "cos")) ||
4484 (NameLen == 4 && !strcmp(NameStr, "cosf")) ||
4485 (NameLen == 4 && !strcmp(NameStr, "cosl")))) {
4486 if (I.getNumOperands() == 2 && // Basic sanity checks.
4487 I.getOperand(1)->getType()->isFloatingPoint() &&
4488 I.getType() == I.getOperand(1)->getType()) {
4489 SDValue Tmp = getValue(I.getOperand(1));
4490 setValue(&I, DAG.getNode(ISD::FCOS, getCurDebugLoc(),
4491 Tmp.getValueType(), Tmp));
4496 } else if (isa<InlineAsm>(I.getOperand(0))) {
4503 Callee = getValue(I.getOperand(0));
4505 Callee = DAG.getExternalSymbol(RenameFn, TLI.getPointerTy());
4507 LowerCallTo(&I, Callee, I.isTailCall());
4511 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from
4512 /// this value and returns the result as a ValueVT value. This uses
4513 /// Chain/Flag as the input and updates them for the output Chain/Flag.
4514 /// If the Flag pointer is NULL, no flag is used.
4515 SDValue RegsForValue::getCopyFromRegs(SelectionDAG &DAG, DebugLoc dl,
4517 SDValue *Flag) const {
4518 // Assemble the legal parts into the final values.
4519 SmallVector<SDValue, 4> Values(ValueVTs.size());
4520 SmallVector<SDValue, 8> Parts;
4521 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) {
4522 // Copy the legal parts from the registers.
4523 MVT ValueVT = ValueVTs[Value];
4524 unsigned NumRegs = TLI->getNumRegisters(ValueVT);
4525 MVT RegisterVT = RegVTs[Value];
4527 Parts.resize(NumRegs);
4528 for (unsigned i = 0; i != NumRegs; ++i) {
4531 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT);
4533 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT, *Flag);
4534 *Flag = P.getValue(2);
4536 Chain = P.getValue(1);
4538 // If the source register was virtual and if we know something about it,
4539 // add an assert node.
4540 if (TargetRegisterInfo::isVirtualRegister(Regs[Part+i]) &&
4541 RegisterVT.isInteger() && !RegisterVT.isVector()) {
4542 unsigned SlotNo = Regs[Part+i]-TargetRegisterInfo::FirstVirtualRegister;
4543 FunctionLoweringInfo &FLI = DAG.getFunctionLoweringInfo();
4544 if (FLI.LiveOutRegInfo.size() > SlotNo) {
4545 FunctionLoweringInfo::LiveOutInfo &LOI = FLI.LiveOutRegInfo[SlotNo];
4547 unsigned RegSize = RegisterVT.getSizeInBits();
4548 unsigned NumSignBits = LOI.NumSignBits;
4549 unsigned NumZeroBits = LOI.KnownZero.countLeadingOnes();
4551 // FIXME: We capture more information than the dag can represent. For
4552 // now, just use the tightest assertzext/assertsext possible.
4554 MVT FromVT(MVT::Other);
4555 if (NumSignBits == RegSize)
4556 isSExt = true, FromVT = MVT::i1; // ASSERT SEXT 1
4557 else if (NumZeroBits >= RegSize-1)
4558 isSExt = false, FromVT = MVT::i1; // ASSERT ZEXT 1
4559 else if (NumSignBits > RegSize-8)
4560 isSExt = true, FromVT = MVT::i8; // ASSERT SEXT 8
4561 else if (NumZeroBits >= RegSize-8)
4562 isSExt = false, FromVT = MVT::i8; // ASSERT ZEXT 8
4563 else if (NumSignBits > RegSize-16)
4564 isSExt = true, FromVT = MVT::i16; // ASSERT SEXT 16
4565 else if (NumZeroBits >= RegSize-16)
4566 isSExt = false, FromVT = MVT::i16; // ASSERT ZEXT 16
4567 else if (NumSignBits > RegSize-32)
4568 isSExt = true, FromVT = MVT::i32; // ASSERT SEXT 32
4569 else if (NumZeroBits >= RegSize-32)
4570 isSExt = false, FromVT = MVT::i32; // ASSERT ZEXT 32
4572 if (FromVT != MVT::Other) {
4573 P = DAG.getNode(isSExt ? ISD::AssertSext : ISD::AssertZext, dl,
4574 RegisterVT, P, DAG.getValueType(FromVT));
4583 Values[Value] = getCopyFromParts(DAG, dl, Parts.begin(),
4584 NumRegs, RegisterVT, ValueVT);
4589 return DAG.getNode(ISD::MERGE_VALUES, dl,
4590 DAG.getVTList(&ValueVTs[0], ValueVTs.size()),
4591 &Values[0], ValueVTs.size());
4594 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
4595 /// specified value into the registers specified by this object. This uses
4596 /// Chain/Flag as the input and updates them for the output Chain/Flag.
4597 /// If the Flag pointer is NULL, no flag is used.
4598 void RegsForValue::getCopyToRegs(SDValue Val, SelectionDAG &DAG, DebugLoc dl,
4599 SDValue &Chain, SDValue *Flag) const {
4600 // Get the list of the values's legal parts.
4601 unsigned NumRegs = Regs.size();
4602 SmallVector<SDValue, 8> Parts(NumRegs);
4603 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) {
4604 MVT ValueVT = ValueVTs[Value];
4605 unsigned NumParts = TLI->getNumRegisters(ValueVT);
4606 MVT RegisterVT = RegVTs[Value];
4608 getCopyToParts(DAG, dl, Val.getValue(Val.getResNo() + Value),
4609 &Parts[Part], NumParts, RegisterVT);
4613 // Copy the parts into the registers.
4614 SmallVector<SDValue, 8> Chains(NumRegs);
4615 for (unsigned i = 0; i != NumRegs; ++i) {
4618 Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i]);
4620 Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i], *Flag);
4621 *Flag = Part.getValue(1);
4623 Chains[i] = Part.getValue(0);
4626 if (NumRegs == 1 || Flag)
4627 // If NumRegs > 1 && Flag is used then the use of the last CopyToReg is
4628 // flagged to it. That is the CopyToReg nodes and the user are considered
4629 // a single scheduling unit. If we create a TokenFactor and return it as
4630 // chain, then the TokenFactor is both a predecessor (operand) of the
4631 // user as well as a successor (the TF operands are flagged to the user).
4632 // c1, f1 = CopyToReg
4633 // c2, f2 = CopyToReg
4634 // c3 = TokenFactor c1, c2
4637 Chain = Chains[NumRegs-1];
4639 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Chains[0], NumRegs);
4642 /// AddInlineAsmOperands - Add this value to the specified inlineasm node
4643 /// operand list. This adds the code marker and includes the number of
4644 /// values added into it.
4645 void RegsForValue::AddInlineAsmOperands(unsigned Code,
4646 bool HasMatching,unsigned MatchingIdx,
4648 std::vector<SDValue> &Ops) const {
4649 MVT IntPtrTy = DAG.getTargetLoweringInfo().getPointerTy();
4650 assert(Regs.size() < (1 << 13) && "Too many inline asm outputs!");
4651 unsigned Flag = Code | (Regs.size() << 3);
4653 Flag |= 0x80000000 | (MatchingIdx << 16);
4654 Ops.push_back(DAG.getTargetConstant(Flag, IntPtrTy));
4655 for (unsigned Value = 0, Reg = 0, e = ValueVTs.size(); Value != e; ++Value) {
4656 unsigned NumRegs = TLI->getNumRegisters(ValueVTs[Value]);
4657 MVT RegisterVT = RegVTs[Value];
4658 for (unsigned i = 0; i != NumRegs; ++i) {
4659 assert(Reg < Regs.size() && "Mismatch in # registers expected");
4660 Ops.push_back(DAG.getRegister(Regs[Reg++], RegisterVT));
4665 /// isAllocatableRegister - If the specified register is safe to allocate,
4666 /// i.e. it isn't a stack pointer or some other special register, return the
4667 /// register class for the register. Otherwise, return null.
4668 static const TargetRegisterClass *
4669 isAllocatableRegister(unsigned Reg, MachineFunction &MF,
4670 const TargetLowering &TLI,
4671 const TargetRegisterInfo *TRI) {
4672 MVT FoundVT = MVT::Other;
4673 const TargetRegisterClass *FoundRC = 0;
4674 for (TargetRegisterInfo::regclass_iterator RCI = TRI->regclass_begin(),
4675 E = TRI->regclass_end(); RCI != E; ++RCI) {
4676 MVT ThisVT = MVT::Other;
4678 const TargetRegisterClass *RC = *RCI;
4679 // If none of the the value types for this register class are valid, we
4680 // can't use it. For example, 64-bit reg classes on 32-bit targets.
4681 for (TargetRegisterClass::vt_iterator I = RC->vt_begin(), E = RC->vt_end();
4683 if (TLI.isTypeLegal(*I)) {
4684 // If we have already found this register in a different register class,
4685 // choose the one with the largest VT specified. For example, on
4686 // PowerPC, we favor f64 register classes over f32.
4687 if (FoundVT == MVT::Other || FoundVT.bitsLT(*I)) {
4694 if (ThisVT == MVT::Other) continue;
4696 // NOTE: This isn't ideal. In particular, this might allocate the
4697 // frame pointer in functions that need it (due to them not being taken
4698 // out of allocation, because a variable sized allocation hasn't been seen
4699 // yet). This is a slight code pessimization, but should still work.
4700 for (TargetRegisterClass::iterator I = RC->allocation_order_begin(MF),
4701 E = RC->allocation_order_end(MF); I != E; ++I)
4703 // We found a matching register class. Keep looking at others in case
4704 // we find one with larger registers that this physreg is also in.
4715 /// AsmOperandInfo - This contains information for each constraint that we are
4717 class VISIBILITY_HIDDEN SDISelAsmOperandInfo :
4718 public TargetLowering::AsmOperandInfo {
4720 /// CallOperand - If this is the result output operand or a clobber
4721 /// this is null, otherwise it is the incoming operand to the CallInst.
4722 /// This gets modified as the asm is processed.
4723 SDValue CallOperand;
4725 /// AssignedRegs - If this is a register or register class operand, this
4726 /// contains the set of register corresponding to the operand.
4727 RegsForValue AssignedRegs;
4729 explicit SDISelAsmOperandInfo(const InlineAsm::ConstraintInfo &info)
4730 : TargetLowering::AsmOperandInfo(info), CallOperand(0,0) {
4733 /// MarkAllocatedRegs - Once AssignedRegs is set, mark the assigned registers
4734 /// busy in OutputRegs/InputRegs.
4735 void MarkAllocatedRegs(bool isOutReg, bool isInReg,
4736 std::set<unsigned> &OutputRegs,
4737 std::set<unsigned> &InputRegs,
4738 const TargetRegisterInfo &TRI) const {
4740 for (unsigned i = 0, e = AssignedRegs.Regs.size(); i != e; ++i)
4741 MarkRegAndAliases(AssignedRegs.Regs[i], OutputRegs, TRI);
4744 for (unsigned i = 0, e = AssignedRegs.Regs.size(); i != e; ++i)
4745 MarkRegAndAliases(AssignedRegs.Regs[i], InputRegs, TRI);
4749 /// getCallOperandValMVT - Return the MVT of the Value* that this operand
4750 /// corresponds to. If there is no Value* for this operand, it returns
4752 MVT getCallOperandValMVT(const TargetLowering &TLI,
4753 const TargetData *TD) const {
4754 if (CallOperandVal == 0) return MVT::Other;
4756 if (isa<BasicBlock>(CallOperandVal))
4757 return TLI.getPointerTy();
4759 const llvm::Type *OpTy = CallOperandVal->getType();
4761 // If this is an indirect operand, the operand is a pointer to the
4764 OpTy = cast<PointerType>(OpTy)->getElementType();
4766 // If OpTy is not a single value, it may be a struct/union that we
4767 // can tile with integers.
4768 if (!OpTy->isSingleValueType() && OpTy->isSized()) {
4769 unsigned BitSize = TD->getTypeSizeInBits(OpTy);
4778 OpTy = IntegerType::get(BitSize);
4783 return TLI.getValueType(OpTy, true);
4787 /// MarkRegAndAliases - Mark the specified register and all aliases in the
4789 static void MarkRegAndAliases(unsigned Reg, std::set<unsigned> &Regs,
4790 const TargetRegisterInfo &TRI) {
4791 assert(TargetRegisterInfo::isPhysicalRegister(Reg) && "Isn't a physreg");
4793 if (const unsigned *Aliases = TRI.getAliasSet(Reg))
4794 for (; *Aliases; ++Aliases)
4795 Regs.insert(*Aliases);
4798 } // end llvm namespace.
4801 /// GetRegistersForValue - Assign registers (virtual or physical) for the
4802 /// specified operand. We prefer to assign virtual registers, to allow the
4803 /// register allocator handle the assignment process. However, if the asm uses
4804 /// features that we can't model on machineinstrs, we have SDISel do the
4805 /// allocation. This produces generally horrible, but correct, code.
4807 /// OpInfo describes the operand.
4808 /// Input and OutputRegs are the set of already allocated physical registers.
4810 void SelectionDAGLowering::
4811 GetRegistersForValue(SDISelAsmOperandInfo &OpInfo,
4812 std::set<unsigned> &OutputRegs,
4813 std::set<unsigned> &InputRegs) {
4814 // Compute whether this value requires an input register, an output register,
4816 bool isOutReg = false;
4817 bool isInReg = false;
4818 switch (OpInfo.Type) {
4819 case InlineAsm::isOutput:
4822 // If there is an input constraint that matches this, we need to reserve
4823 // the input register so no other inputs allocate to it.
4824 isInReg = OpInfo.hasMatchingInput();
4826 case InlineAsm::isInput:
4830 case InlineAsm::isClobber:
4837 MachineFunction &MF = DAG.getMachineFunction();
4838 SmallVector<unsigned, 4> Regs;
4840 // If this is a constraint for a single physreg, or a constraint for a
4841 // register class, find it.
4842 std::pair<unsigned, const TargetRegisterClass*> PhysReg =
4843 TLI.getRegForInlineAsmConstraint(OpInfo.ConstraintCode,
4844 OpInfo.ConstraintVT);
4846 unsigned NumRegs = 1;
4847 if (OpInfo.ConstraintVT != MVT::Other) {
4848 // If this is a FP input in an integer register (or visa versa) insert a bit
4849 // cast of the input value. More generally, handle any case where the input
4850 // value disagrees with the register class we plan to stick this in.
4851 if (OpInfo.Type == InlineAsm::isInput &&
4852 PhysReg.second && !PhysReg.second->hasType(OpInfo.ConstraintVT)) {
4853 // Try to convert to the first MVT that the reg class contains. If the
4854 // types are identical size, use a bitcast to convert (e.g. two differing
4856 MVT RegVT = *PhysReg.second->vt_begin();
4857 if (RegVT.getSizeInBits() == OpInfo.ConstraintVT.getSizeInBits()) {
4858 OpInfo.CallOperand = DAG.getNode(ISD::BIT_CONVERT, getCurDebugLoc(),
4859 RegVT, OpInfo.CallOperand);
4860 OpInfo.ConstraintVT = RegVT;
4861 } else if (RegVT.isInteger() && OpInfo.ConstraintVT.isFloatingPoint()) {
4862 // If the input is a FP value and we want it in FP registers, do a
4863 // bitcast to the corresponding integer type. This turns an f64 value
4864 // into i64, which can be passed with two i32 values on a 32-bit
4866 RegVT = MVT::getIntegerVT(OpInfo.ConstraintVT.getSizeInBits());
4867 OpInfo.CallOperand = DAG.getNode(ISD::BIT_CONVERT, getCurDebugLoc(),
4868 RegVT, OpInfo.CallOperand);
4869 OpInfo.ConstraintVT = RegVT;
4873 NumRegs = TLI.getNumRegisters(OpInfo.ConstraintVT);
4877 MVT ValueVT = OpInfo.ConstraintVT;
4879 // If this is a constraint for a specific physical register, like {r17},
4881 if (unsigned AssignedReg = PhysReg.first) {
4882 const TargetRegisterClass *RC = PhysReg.second;
4883 if (OpInfo.ConstraintVT == MVT::Other)
4884 ValueVT = *RC->vt_begin();
4886 // Get the actual register value type. This is important, because the user
4887 // may have asked for (e.g.) the AX register in i32 type. We need to
4888 // remember that AX is actually i16 to get the right extension.
4889 RegVT = *RC->vt_begin();
4891 // This is a explicit reference to a physical register.
4892 Regs.push_back(AssignedReg);
4894 // If this is an expanded reference, add the rest of the regs to Regs.
4896 TargetRegisterClass::iterator I = RC->begin();
4897 for (; *I != AssignedReg; ++I)
4898 assert(I != RC->end() && "Didn't find reg!");
4900 // Already added the first reg.
4902 for (; NumRegs; --NumRegs, ++I) {
4903 assert(I != RC->end() && "Ran out of registers to allocate!");
4907 OpInfo.AssignedRegs = RegsForValue(TLI, Regs, RegVT, ValueVT);
4908 const TargetRegisterInfo *TRI = DAG.getTarget().getRegisterInfo();
4909 OpInfo.MarkAllocatedRegs(isOutReg, isInReg, OutputRegs, InputRegs, *TRI);
4913 // Otherwise, if this was a reference to an LLVM register class, create vregs
4914 // for this reference.
4915 if (const TargetRegisterClass *RC = PhysReg.second) {
4916 RegVT = *RC->vt_begin();
4917 if (OpInfo.ConstraintVT == MVT::Other)
4920 // Create the appropriate number of virtual registers.
4921 MachineRegisterInfo &RegInfo = MF.getRegInfo();
4922 for (; NumRegs; --NumRegs)
4923 Regs.push_back(RegInfo.createVirtualRegister(RC));
4925 OpInfo.AssignedRegs = RegsForValue(TLI, Regs, RegVT, ValueVT);
4929 // This is a reference to a register class that doesn't directly correspond
4930 // to an LLVM register class. Allocate NumRegs consecutive, available,
4931 // registers from the class.
4932 std::vector<unsigned> RegClassRegs
4933 = TLI.getRegClassForInlineAsmConstraint(OpInfo.ConstraintCode,
4934 OpInfo.ConstraintVT);
4936 const TargetRegisterInfo *TRI = DAG.getTarget().getRegisterInfo();
4937 unsigned NumAllocated = 0;
4938 for (unsigned i = 0, e = RegClassRegs.size(); i != e; ++i) {
4939 unsigned Reg = RegClassRegs[i];
4940 // See if this register is available.
4941 if ((isOutReg && OutputRegs.count(Reg)) || // Already used.
4942 (isInReg && InputRegs.count(Reg))) { // Already used.
4943 // Make sure we find consecutive registers.
4948 // Check to see if this register is allocatable (i.e. don't give out the
4950 const TargetRegisterClass *RC = isAllocatableRegister(Reg, MF, TLI, TRI);
4951 if (!RC) { // Couldn't allocate this register.
4952 // Reset NumAllocated to make sure we return consecutive registers.
4957 // Okay, this register is good, we can use it.
4960 // If we allocated enough consecutive registers, succeed.
4961 if (NumAllocated == NumRegs) {
4962 unsigned RegStart = (i-NumAllocated)+1;
4963 unsigned RegEnd = i+1;
4964 // Mark all of the allocated registers used.
4965 for (unsigned i = RegStart; i != RegEnd; ++i)
4966 Regs.push_back(RegClassRegs[i]);
4968 OpInfo.AssignedRegs = RegsForValue(TLI, Regs, *RC->vt_begin(),
4969 OpInfo.ConstraintVT);
4970 OpInfo.MarkAllocatedRegs(isOutReg, isInReg, OutputRegs, InputRegs, *TRI);
4975 // Otherwise, we couldn't allocate enough registers for this.
4978 /// hasInlineAsmMemConstraint - Return true if the inline asm instruction being
4979 /// processed uses a memory 'm' constraint.
4981 hasInlineAsmMemConstraint(std::vector<InlineAsm::ConstraintInfo> &CInfos,
4982 const TargetLowering &TLI) {
4983 for (unsigned i = 0, e = CInfos.size(); i != e; ++i) {
4984 InlineAsm::ConstraintInfo &CI = CInfos[i];
4985 for (unsigned j = 0, ee = CI.Codes.size(); j != ee; ++j) {
4986 TargetLowering::ConstraintType CType = TLI.getConstraintType(CI.Codes[j]);
4987 if (CType == TargetLowering::C_Memory)
4991 // Indirect operand accesses access memory.
4999 /// visitInlineAsm - Handle a call to an InlineAsm object.
5001 void SelectionDAGLowering::visitInlineAsm(CallSite CS) {
5002 InlineAsm *IA = cast<InlineAsm>(CS.getCalledValue());
5004 /// ConstraintOperands - Information about all of the constraints.
5005 std::vector<SDISelAsmOperandInfo> ConstraintOperands;
5007 std::set<unsigned> OutputRegs, InputRegs;
5009 // Do a prepass over the constraints, canonicalizing them, and building up the
5010 // ConstraintOperands list.
5011 std::vector<InlineAsm::ConstraintInfo>
5012 ConstraintInfos = IA->ParseConstraints();
5014 bool hasMemory = hasInlineAsmMemConstraint(ConstraintInfos, TLI);
5016 SDValue Chain, Flag;
5018 // We won't need to flush pending loads if this asm doesn't touch
5019 // memory and is nonvolatile.
5020 if (hasMemory || IA->hasSideEffects())
5023 Chain = DAG.getRoot();
5025 unsigned ArgNo = 0; // ArgNo - The argument of the CallInst.
5026 unsigned ResNo = 0; // ResNo - The result number of the next output.
5027 for (unsigned i = 0, e = ConstraintInfos.size(); i != e; ++i) {
5028 ConstraintOperands.push_back(SDISelAsmOperandInfo(ConstraintInfos[i]));
5029 SDISelAsmOperandInfo &OpInfo = ConstraintOperands.back();
5031 MVT OpVT = MVT::Other;
5033 // Compute the value type for each operand.
5034 switch (OpInfo.Type) {
5035 case InlineAsm::isOutput:
5036 // Indirect outputs just consume an argument.
5037 if (OpInfo.isIndirect) {
5038 OpInfo.CallOperandVal = CS.getArgument(ArgNo++);
5042 // The return value of the call is this value. As such, there is no
5043 // corresponding argument.
5044 assert(CS.getType() != Type::VoidTy && "Bad inline asm!");
5045 if (const StructType *STy = dyn_cast<StructType>(CS.getType())) {
5046 OpVT = TLI.getValueType(STy->getElementType(ResNo));
5048 assert(ResNo == 0 && "Asm only has one result!");
5049 OpVT = TLI.getValueType(CS.getType());
5053 case InlineAsm::isInput:
5054 OpInfo.CallOperandVal = CS.getArgument(ArgNo++);
5056 case InlineAsm::isClobber:
5061 // If this is an input or an indirect output, process the call argument.
5062 // BasicBlocks are labels, currently appearing only in asm's.
5063 if (OpInfo.CallOperandVal) {
5064 // Strip bitcasts, if any. This mostly comes up for functions.
5065 ConstantExpr* CE = NULL;
5066 while ((CE = dyn_cast<ConstantExpr>(OpInfo.CallOperandVal)) &&
5067 CE->getOpcode()==Instruction::BitCast)
5068 OpInfo.CallOperandVal = CE->getOperand(0);
5069 if (BasicBlock *BB = dyn_cast<BasicBlock>(OpInfo.CallOperandVal)) {
5070 OpInfo.CallOperand = DAG.getBasicBlock(FuncInfo.MBBMap[BB]);
5072 OpInfo.CallOperand = getValue(OpInfo.CallOperandVal);
5075 OpVT = OpInfo.getCallOperandValMVT(TLI, TD);
5078 OpInfo.ConstraintVT = OpVT;
5081 // Second pass over the constraints: compute which constraint option to use
5082 // and assign registers to constraints that want a specific physreg.
5083 for (unsigned i = 0, e = ConstraintInfos.size(); i != e; ++i) {
5084 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
5086 // If this is an output operand with a matching input operand, look up the
5087 // matching input. If their types mismatch, e.g. one is an integer, the
5088 // other is floating point, or their sizes are different, flag it as an
5090 if (OpInfo.hasMatchingInput()) {
5091 SDISelAsmOperandInfo &Input = ConstraintOperands[OpInfo.MatchingInput];
5092 if (OpInfo.ConstraintVT != Input.ConstraintVT) {
5093 if ((OpInfo.ConstraintVT.isInteger() !=
5094 Input.ConstraintVT.isInteger()) ||
5095 (OpInfo.ConstraintVT.getSizeInBits() !=
5096 Input.ConstraintVT.getSizeInBits())) {
5097 llvm_report_error("llvm: error: Unsupported asm: input constraint"
5098 " with a matching output constraint of incompatible"
5101 Input.ConstraintVT = OpInfo.ConstraintVT;
5105 // Compute the constraint code and ConstraintType to use.
5106 TLI.ComputeConstraintToUse(OpInfo, OpInfo.CallOperand, hasMemory, &DAG);
5108 // If this is a memory input, and if the operand is not indirect, do what we
5109 // need to to provide an address for the memory input.
5110 if (OpInfo.ConstraintType == TargetLowering::C_Memory &&
5111 !OpInfo.isIndirect) {
5112 assert(OpInfo.Type == InlineAsm::isInput &&
5113 "Can only indirectify direct input operands!");
5115 // Memory operands really want the address of the value. If we don't have
5116 // an indirect input, put it in the constpool if we can, otherwise spill
5117 // it to a stack slot.
5119 // If the operand is a float, integer, or vector constant, spill to a
5120 // constant pool entry to get its address.
5121 Value *OpVal = OpInfo.CallOperandVal;
5122 if (isa<ConstantFP>(OpVal) || isa<ConstantInt>(OpVal) ||
5123 isa<ConstantVector>(OpVal)) {
5124 OpInfo.CallOperand = DAG.getConstantPool(cast<Constant>(OpVal),
5125 TLI.getPointerTy());
5127 // Otherwise, create a stack slot and emit a store to it before the
5129 const Type *Ty = OpVal->getType();
5130 uint64_t TySize = TLI.getTargetData()->getTypeAllocSize(Ty);
5131 unsigned Align = TLI.getTargetData()->getPrefTypeAlignment(Ty);
5132 MachineFunction &MF = DAG.getMachineFunction();
5133 int SSFI = MF.getFrameInfo()->CreateStackObject(TySize, Align);
5134 SDValue StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy());
5135 Chain = DAG.getStore(Chain, getCurDebugLoc(),
5136 OpInfo.CallOperand, StackSlot, NULL, 0);
5137 OpInfo.CallOperand = StackSlot;
5140 // There is no longer a Value* corresponding to this operand.
5141 OpInfo.CallOperandVal = 0;
5142 // It is now an indirect operand.
5143 OpInfo.isIndirect = true;
5146 // If this constraint is for a specific register, allocate it before
5148 if (OpInfo.ConstraintType == TargetLowering::C_Register)
5149 GetRegistersForValue(OpInfo, OutputRegs, InputRegs);
5151 ConstraintInfos.clear();
5154 // Second pass - Loop over all of the operands, assigning virtual or physregs
5155 // to register class operands.
5156 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
5157 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
5159 // C_Register operands have already been allocated, Other/Memory don't need
5161 if (OpInfo.ConstraintType == TargetLowering::C_RegisterClass)
5162 GetRegistersForValue(OpInfo, OutputRegs, InputRegs);
5165 // AsmNodeOperands - The operands for the ISD::INLINEASM node.
5166 std::vector<SDValue> AsmNodeOperands;
5167 AsmNodeOperands.push_back(SDValue()); // reserve space for input chain
5168 AsmNodeOperands.push_back(
5169 DAG.getTargetExternalSymbol(IA->getAsmString().c_str(), MVT::Other));
5172 // Loop over all of the inputs, copying the operand values into the
5173 // appropriate registers and processing the output regs.
5174 RegsForValue RetValRegs;
5176 // IndirectStoresToEmit - The set of stores to emit after the inline asm node.
5177 std::vector<std::pair<RegsForValue, Value*> > IndirectStoresToEmit;
5179 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
5180 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
5182 switch (OpInfo.Type) {
5183 case InlineAsm::isOutput: {
5184 if (OpInfo.ConstraintType != TargetLowering::C_RegisterClass &&
5185 OpInfo.ConstraintType != TargetLowering::C_Register) {
5186 // Memory output, or 'other' output (e.g. 'X' constraint).
5187 assert(OpInfo.isIndirect && "Memory output must be indirect operand");
5189 // Add information to the INLINEASM node to know about this output.
5190 unsigned ResOpType = 4/*MEM*/ | (1<<3);
5191 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
5192 TLI.getPointerTy()));
5193 AsmNodeOperands.push_back(OpInfo.CallOperand);
5197 // Otherwise, this is a register or register class output.
5199 // Copy the output from the appropriate register. Find a register that
5201 if (OpInfo.AssignedRegs.Regs.empty()) {
5202 llvm_report_error("llvm: error: Couldn't allocate output reg for"
5203 " constraint '" + OpInfo.ConstraintCode + "'!");
5206 // If this is an indirect operand, store through the pointer after the
5208 if (OpInfo.isIndirect) {
5209 IndirectStoresToEmit.push_back(std::make_pair(OpInfo.AssignedRegs,
5210 OpInfo.CallOperandVal));
5212 // This is the result value of the call.
5213 assert(CS.getType() != Type::VoidTy && "Bad inline asm!");
5214 // Concatenate this output onto the outputs list.
5215 RetValRegs.append(OpInfo.AssignedRegs);
5218 // Add information to the INLINEASM node to know that this register is
5220 OpInfo.AssignedRegs.AddInlineAsmOperands(OpInfo.isEarlyClobber ?
5221 6 /* EARLYCLOBBER REGDEF */ :
5225 DAG, AsmNodeOperands);
5228 case InlineAsm::isInput: {
5229 SDValue InOperandVal = OpInfo.CallOperand;
5231 if (OpInfo.isMatchingInputConstraint()) { // Matching constraint?
5232 // If this is required to match an output register we have already set,
5233 // just use its register.
5234 unsigned OperandNo = OpInfo.getMatchedOperand();
5236 // Scan until we find the definition we already emitted of this operand.
5237 // When we find it, create a RegsForValue operand.
5238 unsigned CurOp = 2; // The first operand.
5239 for (; OperandNo; --OperandNo) {
5240 // Advance to the next operand.
5242 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue();
5243 assert(((OpFlag & 7) == 2 /*REGDEF*/ ||
5244 (OpFlag & 7) == 6 /*EARLYCLOBBER REGDEF*/ ||
5245 (OpFlag & 7) == 4 /*MEM*/) &&
5246 "Skipped past definitions?");
5247 CurOp += InlineAsm::getNumOperandRegisters(OpFlag)+1;
5251 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue();
5252 if ((OpFlag & 7) == 2 /*REGDEF*/
5253 || (OpFlag & 7) == 6 /* EARLYCLOBBER REGDEF */) {
5254 // Add (OpFlag&0xffff)>>3 registers to MatchedRegs.
5255 if (OpInfo.isIndirect) {
5256 llvm_report_error("llvm: error: "
5257 "Don't know how to handle tied indirect "
5258 "register inputs yet!");
5260 RegsForValue MatchedRegs;
5261 MatchedRegs.TLI = &TLI;
5262 MatchedRegs.ValueVTs.push_back(InOperandVal.getValueType());
5263 MVT RegVT = AsmNodeOperands[CurOp+1].getValueType();
5264 MatchedRegs.RegVTs.push_back(RegVT);
5265 MachineRegisterInfo &RegInfo = DAG.getMachineFunction().getRegInfo();
5266 for (unsigned i = 0, e = InlineAsm::getNumOperandRegisters(OpFlag);
5269 push_back(RegInfo.createVirtualRegister(TLI.getRegClassFor(RegVT)));
5271 // Use the produced MatchedRegs object to
5272 MatchedRegs.getCopyToRegs(InOperandVal, DAG, getCurDebugLoc(),
5274 MatchedRegs.AddInlineAsmOperands(1 /*REGUSE*/,
5275 true, OpInfo.getMatchedOperand(),
5276 DAG, AsmNodeOperands);
5279 assert(((OpFlag & 7) == 4) && "Unknown matching constraint!");
5280 assert((InlineAsm::getNumOperandRegisters(OpFlag)) == 1 &&
5281 "Unexpected number of operands");
5282 // Add information to the INLINEASM node to know about this input.
5283 // See InlineAsm.h isUseOperandTiedToDef.
5284 OpFlag |= 0x80000000 | (OpInfo.getMatchedOperand() << 16);
5285 AsmNodeOperands.push_back(DAG.getTargetConstant(OpFlag,
5286 TLI.getPointerTy()));
5287 AsmNodeOperands.push_back(AsmNodeOperands[CurOp+1]);
5292 if (OpInfo.ConstraintType == TargetLowering::C_Other) {
5293 assert(!OpInfo.isIndirect &&
5294 "Don't know how to handle indirect other inputs yet!");
5296 std::vector<SDValue> Ops;
5297 TLI.LowerAsmOperandForConstraint(InOperandVal, OpInfo.ConstraintCode[0],
5298 hasMemory, Ops, DAG);
5300 llvm_report_error("llvm: error: Invalid operand for inline asm"
5301 " constraint '" + OpInfo.ConstraintCode + "'!");
5304 // Add information to the INLINEASM node to know about this input.
5305 unsigned ResOpType = 3 /*IMM*/ | (Ops.size() << 3);
5306 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
5307 TLI.getPointerTy()));
5308 AsmNodeOperands.insert(AsmNodeOperands.end(), Ops.begin(), Ops.end());
5310 } else if (OpInfo.ConstraintType == TargetLowering::C_Memory) {
5311 assert(OpInfo.isIndirect && "Operand must be indirect to be a mem!");
5312 assert(InOperandVal.getValueType() == TLI.getPointerTy() &&
5313 "Memory operands expect pointer values");
5315 // Add information to the INLINEASM node to know about this input.
5316 unsigned ResOpType = 4/*MEM*/ | (1<<3);
5317 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
5318 TLI.getPointerTy()));
5319 AsmNodeOperands.push_back(InOperandVal);
5323 assert((OpInfo.ConstraintType == TargetLowering::C_RegisterClass ||
5324 OpInfo.ConstraintType == TargetLowering::C_Register) &&
5325 "Unknown constraint type!");
5326 assert(!OpInfo.isIndirect &&
5327 "Don't know how to handle indirect register inputs yet!");
5329 // Copy the input into the appropriate registers.
5330 if (OpInfo.AssignedRegs.Regs.empty()) {
5331 llvm_report_error("llvm: error: Couldn't allocate input reg for"
5332 " constraint '"+ OpInfo.ConstraintCode +"'!");
5335 OpInfo.AssignedRegs.getCopyToRegs(InOperandVal, DAG, getCurDebugLoc(),
5338 OpInfo.AssignedRegs.AddInlineAsmOperands(1/*REGUSE*/, false, 0,
5339 DAG, AsmNodeOperands);
5342 case InlineAsm::isClobber: {
5343 // Add the clobbered value to the operand list, so that the register
5344 // allocator is aware that the physreg got clobbered.
5345 if (!OpInfo.AssignedRegs.Regs.empty())
5346 OpInfo.AssignedRegs.AddInlineAsmOperands(6 /* EARLYCLOBBER REGDEF */,
5347 false, 0, DAG,AsmNodeOperands);
5353 // Finish up input operands.
5354 AsmNodeOperands[0] = Chain;
5355 if (Flag.getNode()) AsmNodeOperands.push_back(Flag);
5357 Chain = DAG.getNode(ISD::INLINEASM, getCurDebugLoc(),
5358 DAG.getVTList(MVT::Other, MVT::Flag),
5359 &AsmNodeOperands[0], AsmNodeOperands.size());
5360 Flag = Chain.getValue(1);
5362 // If this asm returns a register value, copy the result from that register
5363 // and set it as the value of the call.
5364 if (!RetValRegs.Regs.empty()) {
5365 SDValue Val = RetValRegs.getCopyFromRegs(DAG, getCurDebugLoc(),
5368 // FIXME: Why don't we do this for inline asms with MRVs?
5369 if (CS.getType()->isSingleValueType() && CS.getType()->isSized()) {
5370 MVT ResultType = TLI.getValueType(CS.getType());
5372 // If any of the results of the inline asm is a vector, it may have the
5373 // wrong width/num elts. This can happen for register classes that can
5374 // contain multiple different value types. The preg or vreg allocated may
5375 // not have the same VT as was expected. Convert it to the right type
5376 // with bit_convert.
5377 if (ResultType != Val.getValueType() && Val.getValueType().isVector()) {
5378 Val = DAG.getNode(ISD::BIT_CONVERT, getCurDebugLoc(),
5381 } else if (ResultType != Val.getValueType() &&
5382 ResultType.isInteger() && Val.getValueType().isInteger()) {
5383 // If a result value was tied to an input value, the computed result may
5384 // have a wider width than the expected result. Extract the relevant
5386 Val = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), ResultType, Val);
5389 assert(ResultType == Val.getValueType() && "Asm result value mismatch!");
5392 setValue(CS.getInstruction(), Val);
5393 // Don't need to use this as a chain in this case.
5394 if (!IA->hasSideEffects() && !hasMemory && IndirectStoresToEmit.empty())
5398 std::vector<std::pair<SDValue, Value*> > StoresToEmit;
5400 // Process indirect outputs, first output all of the flagged copies out of
5402 for (unsigned i = 0, e = IndirectStoresToEmit.size(); i != e; ++i) {
5403 RegsForValue &OutRegs = IndirectStoresToEmit[i].first;
5404 Value *Ptr = IndirectStoresToEmit[i].second;
5405 SDValue OutVal = OutRegs.getCopyFromRegs(DAG, getCurDebugLoc(),
5407 StoresToEmit.push_back(std::make_pair(OutVal, Ptr));
5411 // Emit the non-flagged stores from the physregs.
5412 SmallVector<SDValue, 8> OutChains;
5413 for (unsigned i = 0, e = StoresToEmit.size(); i != e; ++i)
5414 OutChains.push_back(DAG.getStore(Chain, getCurDebugLoc(),
5415 StoresToEmit[i].first,
5416 getValue(StoresToEmit[i].second),
5417 StoresToEmit[i].second, 0));
5418 if (!OutChains.empty())
5419 Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), MVT::Other,
5420 &OutChains[0], OutChains.size());
5425 void SelectionDAGLowering::visitMalloc(MallocInst &I) {
5426 SDValue Src = getValue(I.getOperand(0));
5428 // Scale up by the type size in the original i32 type width. Various
5429 // mid-level optimizers may make assumptions about demanded bits etc from the
5430 // i32-ness of the optimizer: we do not want to promote to i64 and then
5431 // multiply on 64-bit targets.
5432 // FIXME: Malloc inst should go away: PR715.
5433 uint64_t ElementSize = TD->getTypeAllocSize(I.getType()->getElementType());
5434 if (ElementSize != 1)
5435 Src = DAG.getNode(ISD::MUL, getCurDebugLoc(), Src.getValueType(),
5436 Src, DAG.getConstant(ElementSize, Src.getValueType()));
5438 MVT IntPtr = TLI.getPointerTy();
5440 if (IntPtr.bitsLT(Src.getValueType()))
5441 Src = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), IntPtr, Src);
5442 else if (IntPtr.bitsGT(Src.getValueType()))
5443 Src = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(), IntPtr, Src);
5445 TargetLowering::ArgListTy Args;
5446 TargetLowering::ArgListEntry Entry;
5448 Entry.Ty = TLI.getTargetData()->getIntPtrType();
5449 Args.push_back(Entry);
5451 std::pair<SDValue,SDValue> Result =
5452 TLI.LowerCallTo(getRoot(), I.getType(), false, false, false, false,
5453 0, CallingConv::C, PerformTailCallOpt,
5454 DAG.getExternalSymbol("malloc", IntPtr),
5455 Args, DAG, getCurDebugLoc());
5456 setValue(&I, Result.first); // Pointers always fit in registers
5457 DAG.setRoot(Result.second);
5460 void SelectionDAGLowering::visitFree(FreeInst &I) {
5461 TargetLowering::ArgListTy Args;
5462 TargetLowering::ArgListEntry Entry;
5463 Entry.Node = getValue(I.getOperand(0));
5464 Entry.Ty = TLI.getTargetData()->getIntPtrType();
5465 Args.push_back(Entry);
5466 MVT IntPtr = TLI.getPointerTy();
5467 std::pair<SDValue,SDValue> Result =
5468 TLI.LowerCallTo(getRoot(), Type::VoidTy, false, false, false, false,
5469 0, CallingConv::C, PerformTailCallOpt,
5470 DAG.getExternalSymbol("free", IntPtr), Args, DAG,
5472 DAG.setRoot(Result.second);
5475 void SelectionDAGLowering::visitVAStart(CallInst &I) {
5476 DAG.setRoot(DAG.getNode(ISD::VASTART, getCurDebugLoc(),
5477 MVT::Other, getRoot(),
5478 getValue(I.getOperand(1)),
5479 DAG.getSrcValue(I.getOperand(1))));
5482 void SelectionDAGLowering::visitVAArg(VAArgInst &I) {
5483 SDValue V = DAG.getVAArg(TLI.getValueType(I.getType()), getCurDebugLoc(),
5484 getRoot(), getValue(I.getOperand(0)),
5485 DAG.getSrcValue(I.getOperand(0)));
5487 DAG.setRoot(V.getValue(1));
5490 void SelectionDAGLowering::visitVAEnd(CallInst &I) {
5491 DAG.setRoot(DAG.getNode(ISD::VAEND, getCurDebugLoc(),
5492 MVT::Other, getRoot(),
5493 getValue(I.getOperand(1)),
5494 DAG.getSrcValue(I.getOperand(1))));
5497 void SelectionDAGLowering::visitVACopy(CallInst &I) {
5498 DAG.setRoot(DAG.getNode(ISD::VACOPY, getCurDebugLoc(),
5499 MVT::Other, getRoot(),
5500 getValue(I.getOperand(1)),
5501 getValue(I.getOperand(2)),
5502 DAG.getSrcValue(I.getOperand(1)),
5503 DAG.getSrcValue(I.getOperand(2))));
5506 /// TargetLowering::LowerArguments - This is the default LowerArguments
5507 /// implementation, which just inserts a FORMAL_ARGUMENTS node. FIXME: When all
5508 /// targets are migrated to using FORMAL_ARGUMENTS, this hook should be
5509 /// integrated into SDISel.
5510 void TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG,
5511 SmallVectorImpl<SDValue> &ArgValues,
5513 // Add CC# and isVararg as operands to the FORMAL_ARGUMENTS node.
5514 SmallVector<SDValue, 3+16> Ops;
5515 Ops.push_back(DAG.getRoot());
5516 Ops.push_back(DAG.getConstant(F.getCallingConv(), getPointerTy()));
5517 Ops.push_back(DAG.getConstant(F.isVarArg(), getPointerTy()));
5519 // Add one result value for each formal argument.
5520 SmallVector<MVT, 16> RetVals;
5522 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end();
5524 SmallVector<MVT, 4> ValueVTs;
5525 ComputeValueVTs(*this, I->getType(), ValueVTs);
5526 for (unsigned Value = 0, NumValues = ValueVTs.size();
5527 Value != NumValues; ++Value) {
5528 MVT VT = ValueVTs[Value];
5529 const Type *ArgTy = VT.getTypeForMVT(*DAG.getContext());
5530 ISD::ArgFlagsTy Flags;
5531 unsigned OriginalAlignment =
5532 getTargetData()->getABITypeAlignment(ArgTy);
5534 if (F.paramHasAttr(j, Attribute::ZExt))
5536 if (F.paramHasAttr(j, Attribute::SExt))
5538 if (F.paramHasAttr(j, Attribute::InReg))
5540 if (F.paramHasAttr(j, Attribute::StructRet))
5542 if (F.paramHasAttr(j, Attribute::ByVal)) {
5544 const PointerType *Ty = cast<PointerType>(I->getType());
5545 const Type *ElementTy = Ty->getElementType();
5546 unsigned FrameAlign = getByValTypeAlignment(ElementTy);
5547 unsigned FrameSize = getTargetData()->getTypeAllocSize(ElementTy);
5548 // For ByVal, alignment should be passed from FE. BE will guess if
5549 // this info is not there but there are cases it cannot get right.
5550 if (F.getParamAlignment(j))
5551 FrameAlign = F.getParamAlignment(j);
5552 Flags.setByValAlign(FrameAlign);
5553 Flags.setByValSize(FrameSize);
5555 if (F.paramHasAttr(j, Attribute::Nest))
5557 Flags.setOrigAlign(OriginalAlignment);
5559 MVT RegisterVT = getRegisterType(VT);
5560 unsigned NumRegs = getNumRegisters(VT);
5561 for (unsigned i = 0; i != NumRegs; ++i) {
5562 RetVals.push_back(RegisterVT);
5563 ISD::ArgFlagsTy MyFlags = Flags;
5564 if (NumRegs > 1 && i == 0)
5566 // if it isn't first piece, alignment must be 1
5568 MyFlags.setOrigAlign(1);
5569 Ops.push_back(DAG.getArgFlags(MyFlags));
5574 RetVals.push_back(MVT::Other);
5577 SDNode *Result = DAG.getNode(ISD::FORMAL_ARGUMENTS, dl,
5578 DAG.getVTList(&RetVals[0], RetVals.size()),
5579 &Ops[0], Ops.size()).getNode();
5581 // Prelower FORMAL_ARGUMENTS. This isn't required for functionality, but
5582 // allows exposing the loads that may be part of the argument access to the
5583 // first DAGCombiner pass.
5584 SDValue TmpRes = LowerOperation(SDValue(Result, 0), DAG);
5586 // The number of results should match up, except that the lowered one may have
5587 // an extra flag result.
5588 assert((Result->getNumValues() == TmpRes.getNode()->getNumValues() ||
5589 (Result->getNumValues()+1 == TmpRes.getNode()->getNumValues() &&
5590 TmpRes.getValue(Result->getNumValues()).getValueType() == MVT::Flag))
5591 && "Lowering produced unexpected number of results!");
5593 // The FORMAL_ARGUMENTS node itself is likely no longer needed.
5594 if (Result != TmpRes.getNode() && Result->use_empty()) {
5595 HandleSDNode Dummy(DAG.getRoot());
5596 DAG.RemoveDeadNode(Result);
5599 Result = TmpRes.getNode();
5601 unsigned NumArgRegs = Result->getNumValues() - 1;
5602 DAG.setRoot(SDValue(Result, NumArgRegs));
5604 // Set up the return result vector.
5607 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E;
5609 SmallVector<MVT, 4> ValueVTs;
5610 ComputeValueVTs(*this, I->getType(), ValueVTs);
5611 for (unsigned Value = 0, NumValues = ValueVTs.size();
5612 Value != NumValues; ++Value) {
5613 MVT VT = ValueVTs[Value];
5614 MVT PartVT = getRegisterType(VT);
5616 unsigned NumParts = getNumRegisters(VT);
5617 SmallVector<SDValue, 4> Parts(NumParts);
5618 for (unsigned j = 0; j != NumParts; ++j)
5619 Parts[j] = SDValue(Result, i++);
5621 ISD::NodeType AssertOp = ISD::DELETED_NODE;
5622 if (F.paramHasAttr(Idx, Attribute::SExt))
5623 AssertOp = ISD::AssertSext;
5624 else if (F.paramHasAttr(Idx, Attribute::ZExt))
5625 AssertOp = ISD::AssertZext;
5627 ArgValues.push_back(getCopyFromParts(DAG, dl, &Parts[0], NumParts,
5628 PartVT, VT, AssertOp));
5631 assert(i == NumArgRegs && "Argument register count mismatch!");
5635 /// TargetLowering::LowerCallTo - This is the default LowerCallTo
5636 /// implementation, which just inserts an ISD::CALL node, which is later custom
5637 /// lowered by the target to something concrete. FIXME: When all targets are
5638 /// migrated to using ISD::CALL, this hook should be integrated into SDISel.
5639 std::pair<SDValue, SDValue>
5640 TargetLowering::LowerCallTo(SDValue Chain, const Type *RetTy,
5641 bool RetSExt, bool RetZExt, bool isVarArg,
5642 bool isInreg, unsigned NumFixedArgs,
5643 unsigned CallingConv, bool isTailCall,
5645 ArgListTy &Args, SelectionDAG &DAG, DebugLoc dl) {
5646 assert((!isTailCall || PerformTailCallOpt) &&
5647 "isTailCall set when tail-call optimizations are disabled!");
5649 SmallVector<SDValue, 32> Ops;
5650 Ops.push_back(Chain); // Op#0 - Chain
5651 Ops.push_back(Callee);
5653 // Handle all of the outgoing arguments.
5654 for (unsigned i = 0, e = Args.size(); i != e; ++i) {
5655 SmallVector<MVT, 4> ValueVTs;
5656 ComputeValueVTs(*this, Args[i].Ty, ValueVTs);
5657 for (unsigned Value = 0, NumValues = ValueVTs.size();
5658 Value != NumValues; ++Value) {
5659 MVT VT = ValueVTs[Value];
5660 const Type *ArgTy = VT.getTypeForMVT(*DAG.getContext());
5661 SDValue Op = SDValue(Args[i].Node.getNode(),
5662 Args[i].Node.getResNo() + Value);
5663 ISD::ArgFlagsTy Flags;
5664 unsigned OriginalAlignment =
5665 getTargetData()->getABITypeAlignment(ArgTy);
5671 if (Args[i].isInReg)
5675 if (Args[i].isByVal) {
5677 const PointerType *Ty = cast<PointerType>(Args[i].Ty);
5678 const Type *ElementTy = Ty->getElementType();
5679 unsigned FrameAlign = getByValTypeAlignment(ElementTy);
5680 unsigned FrameSize = getTargetData()->getTypeAllocSize(ElementTy);
5681 // For ByVal, alignment should come from FE. BE will guess if this
5682 // info is not there but there are cases it cannot get right.
5683 if (Args[i].Alignment)
5684 FrameAlign = Args[i].Alignment;
5685 Flags.setByValAlign(FrameAlign);
5686 Flags.setByValSize(FrameSize);
5690 Flags.setOrigAlign(OriginalAlignment);
5692 MVT PartVT = getRegisterType(VT);
5693 unsigned NumParts = getNumRegisters(VT);
5694 SmallVector<SDValue, 4> Parts(NumParts);
5695 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
5698 ExtendKind = ISD::SIGN_EXTEND;
5699 else if (Args[i].isZExt)
5700 ExtendKind = ISD::ZERO_EXTEND;
5702 getCopyToParts(DAG, dl, Op, &Parts[0], NumParts, PartVT, ExtendKind);
5704 for (unsigned i = 0; i != NumParts; ++i) {
5705 // if it isn't first piece, alignment must be 1
5706 ISD::ArgFlagsTy MyFlags = Flags;
5707 if (NumParts > 1 && i == 0)
5710 MyFlags.setOrigAlign(1);
5712 Ops.push_back(Parts[i]);
5713 Ops.push_back(DAG.getArgFlags(MyFlags));
5718 // Figure out the result value types. We start by making a list of
5719 // the potentially illegal return value types.
5720 SmallVector<MVT, 4> LoweredRetTys;
5721 SmallVector<MVT, 4> RetTys;
5722 ComputeValueVTs(*this, RetTy, RetTys);
5724 // Then we translate that to a list of legal types.
5725 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
5727 MVT RegisterVT = getRegisterType(VT);
5728 unsigned NumRegs = getNumRegisters(VT);
5729 for (unsigned i = 0; i != NumRegs; ++i)
5730 LoweredRetTys.push_back(RegisterVT);
5733 LoweredRetTys.push_back(MVT::Other); // Always has a chain.
5735 // Create the CALL node.
5736 SDValue Res = DAG.getCall(CallingConv, dl,
5737 isVarArg, isTailCall, isInreg,
5738 DAG.getVTList(&LoweredRetTys[0],
5739 LoweredRetTys.size()),
5740 &Ops[0], Ops.size(), NumFixedArgs
5742 Chain = Res.getValue(LoweredRetTys.size() - 1);
5744 // Gather up the call result into a single value.
5745 if (RetTy != Type::VoidTy && !RetTys.empty()) {
5746 ISD::NodeType AssertOp = ISD::DELETED_NODE;
5749 AssertOp = ISD::AssertSext;
5751 AssertOp = ISD::AssertZext;
5753 SmallVector<SDValue, 4> ReturnValues;
5755 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
5757 MVT RegisterVT = getRegisterType(VT);
5758 unsigned NumRegs = getNumRegisters(VT);
5759 unsigned RegNoEnd = NumRegs + RegNo;
5760 SmallVector<SDValue, 4> Results;
5761 for (; RegNo != RegNoEnd; ++RegNo)
5762 Results.push_back(Res.getValue(RegNo));
5763 SDValue ReturnValue =
5764 getCopyFromParts(DAG, dl, &Results[0], NumRegs, RegisterVT, VT,
5766 ReturnValues.push_back(ReturnValue);
5768 Res = DAG.getNode(ISD::MERGE_VALUES, dl,
5769 DAG.getVTList(&RetTys[0], RetTys.size()),
5770 &ReturnValues[0], ReturnValues.size());
5773 return std::make_pair(Res, Chain);
5776 void TargetLowering::LowerOperationWrapper(SDNode *N,
5777 SmallVectorImpl<SDValue> &Results,
5778 SelectionDAG &DAG) {
5779 SDValue Res = LowerOperation(SDValue(N, 0), DAG);
5781 Results.push_back(Res);
5784 SDValue TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) {
5785 llvm_unreachable("LowerOperation not implemented for this target!");
5790 void SelectionDAGLowering::CopyValueToVirtualRegister(Value *V, unsigned Reg) {
5791 SDValue Op = getValue(V);
5792 assert((Op.getOpcode() != ISD::CopyFromReg ||
5793 cast<RegisterSDNode>(Op.getOperand(1))->getReg() != Reg) &&
5794 "Copy from a reg to the same reg!");
5795 assert(!TargetRegisterInfo::isPhysicalRegister(Reg) && "Is a physreg");
5797 RegsForValue RFV(TLI, Reg, V->getType());
5798 SDValue Chain = DAG.getEntryNode();
5799 RFV.getCopyToRegs(Op, DAG, getCurDebugLoc(), Chain, 0);
5800 PendingExports.push_back(Chain);
5803 #include "llvm/CodeGen/SelectionDAGISel.h"
5805 void SelectionDAGISel::
5806 LowerArguments(BasicBlock *LLVMBB) {
5807 // If this is the entry block, emit arguments.
5808 Function &F = *LLVMBB->getParent();
5809 SDValue OldRoot = SDL->DAG.getRoot();
5810 SmallVector<SDValue, 16> Args;
5811 TLI.LowerArguments(F, SDL->DAG, Args, SDL->getCurDebugLoc());
5814 for (Function::arg_iterator AI = F.arg_begin(), E = F.arg_end();
5816 SmallVector<MVT, 4> ValueVTs;
5817 ComputeValueVTs(TLI, AI->getType(), ValueVTs);
5818 unsigned NumValues = ValueVTs.size();
5819 if (!AI->use_empty()) {
5820 SDL->setValue(AI, SDL->DAG.getMergeValues(&Args[a], NumValues,
5821 SDL->getCurDebugLoc()));
5822 // If this argument is live outside of the entry block, insert a copy from
5823 // whereever we got it to the vreg that other BB's will reference it as.
5824 SDL->CopyToExportRegsIfNeeded(AI);
5829 // Finally, if the target has anything special to do, allow it to do so.
5830 // FIXME: this should insert code into the DAG!
5831 EmitFunctionEntryCode(F, SDL->DAG.getMachineFunction());
5834 /// Handle PHI nodes in successor blocks. Emit code into the SelectionDAG to
5835 /// ensure constants are generated when needed. Remember the virtual registers
5836 /// that need to be added to the Machine PHI nodes as input. We cannot just
5837 /// directly add them, because expansion might result in multiple MBB's for one
5838 /// BB. As such, the start of the BB might correspond to a different MBB than
5842 SelectionDAGISel::HandlePHINodesInSuccessorBlocks(BasicBlock *LLVMBB) {
5843 TerminatorInst *TI = LLVMBB->getTerminator();
5845 SmallPtrSet<MachineBasicBlock *, 4> SuccsHandled;
5847 // Check successor nodes' PHI nodes that expect a constant to be available
5849 for (unsigned succ = 0, e = TI->getNumSuccessors(); succ != e; ++succ) {
5850 BasicBlock *SuccBB = TI->getSuccessor(succ);
5851 if (!isa<PHINode>(SuccBB->begin())) continue;
5852 MachineBasicBlock *SuccMBB = FuncInfo->MBBMap[SuccBB];
5854 // If this terminator has multiple identical successors (common for
5855 // switches), only handle each succ once.
5856 if (!SuccsHandled.insert(SuccMBB)) continue;
5858 MachineBasicBlock::iterator MBBI = SuccMBB->begin();
5861 // At this point we know that there is a 1-1 correspondence between LLVM PHI
5862 // nodes and Machine PHI nodes, but the incoming operands have not been
5864 for (BasicBlock::iterator I = SuccBB->begin();
5865 (PN = dyn_cast<PHINode>(I)); ++I) {
5866 // Ignore dead phi's.
5867 if (PN->use_empty()) continue;
5870 Value *PHIOp = PN->getIncomingValueForBlock(LLVMBB);
5872 if (Constant *C = dyn_cast<Constant>(PHIOp)) {
5873 unsigned &RegOut = SDL->ConstantsOut[C];
5875 RegOut = FuncInfo->CreateRegForValue(C);
5876 SDL->CopyValueToVirtualRegister(C, RegOut);
5880 Reg = FuncInfo->ValueMap[PHIOp];
5882 assert(isa<AllocaInst>(PHIOp) &&
5883 FuncInfo->StaticAllocaMap.count(cast<AllocaInst>(PHIOp)) &&
5884 "Didn't codegen value into a register!??");
5885 Reg = FuncInfo->CreateRegForValue(PHIOp);
5886 SDL->CopyValueToVirtualRegister(PHIOp, Reg);
5890 // Remember that this register needs to added to the machine PHI node as
5891 // the input for this MBB.
5892 SmallVector<MVT, 4> ValueVTs;
5893 ComputeValueVTs(TLI, PN->getType(), ValueVTs);
5894 for (unsigned vti = 0, vte = ValueVTs.size(); vti != vte; ++vti) {
5895 MVT VT = ValueVTs[vti];
5896 unsigned NumRegisters = TLI.getNumRegisters(VT);
5897 for (unsigned i = 0, e = NumRegisters; i != e; ++i)
5898 SDL->PHINodesToUpdate.push_back(std::make_pair(MBBI++, Reg+i));
5899 Reg += NumRegisters;
5903 SDL->ConstantsOut.clear();
5906 /// This is the Fast-ISel version of HandlePHINodesInSuccessorBlocks. It only
5907 /// supports legal types, and it emits MachineInstrs directly instead of
5908 /// creating SelectionDAG nodes.
5911 SelectionDAGISel::HandlePHINodesInSuccessorBlocksFast(BasicBlock *LLVMBB,
5913 TerminatorInst *TI = LLVMBB->getTerminator();
5915 SmallPtrSet<MachineBasicBlock *, 4> SuccsHandled;
5916 unsigned OrigNumPHINodesToUpdate = SDL->PHINodesToUpdate.size();
5918 // Check successor nodes' PHI nodes that expect a constant to be available
5920 for (unsigned succ = 0, e = TI->getNumSuccessors(); succ != e; ++succ) {
5921 BasicBlock *SuccBB = TI->getSuccessor(succ);
5922 if (!isa<PHINode>(SuccBB->begin())) continue;
5923 MachineBasicBlock *SuccMBB = FuncInfo->MBBMap[SuccBB];
5925 // If this terminator has multiple identical successors (common for
5926 // switches), only handle each succ once.
5927 if (!SuccsHandled.insert(SuccMBB)) continue;
5929 MachineBasicBlock::iterator MBBI = SuccMBB->begin();
5932 // At this point we know that there is a 1-1 correspondence between LLVM PHI
5933 // nodes and Machine PHI nodes, but the incoming operands have not been
5935 for (BasicBlock::iterator I = SuccBB->begin();
5936 (PN = dyn_cast<PHINode>(I)); ++I) {
5937 // Ignore dead phi's.
5938 if (PN->use_empty()) continue;
5940 // Only handle legal types. Two interesting things to note here. First,
5941 // by bailing out early, we may leave behind some dead instructions,
5942 // since SelectionDAG's HandlePHINodesInSuccessorBlocks will insert its
5943 // own moves. Second, this check is necessary becuase FastISel doesn't
5944 // use CreateRegForValue to create registers, so it always creates
5945 // exactly one register for each non-void instruction.
5946 MVT VT = TLI.getValueType(PN->getType(), /*AllowUnknown=*/true);
5947 if (VT == MVT::Other || !TLI.isTypeLegal(VT)) {
5950 VT = TLI.getTypeToTransformTo(VT);
5952 SDL->PHINodesToUpdate.resize(OrigNumPHINodesToUpdate);
5957 Value *PHIOp = PN->getIncomingValueForBlock(LLVMBB);
5959 unsigned Reg = F->getRegForValue(PHIOp);
5961 SDL->PHINodesToUpdate.resize(OrigNumPHINodesToUpdate);
5964 SDL->PHINodesToUpdate.push_back(std::make_pair(MBBI++, Reg));