1 //===---- ScheduleDAGEmit.cpp - Emit routines for the ScheduleDAG class ---===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements the Emit routines for the ScheduleDAG class, which creates
11 // MachineInstrs according to the computed schedule.
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "pre-RA-sched"
16 #include "ScheduleDAGSDNodes.h"
17 #include "llvm/CodeGen/MachineConstantPool.h"
18 #include "llvm/CodeGen/MachineFunction.h"
19 #include "llvm/CodeGen/MachineInstrBuilder.h"
20 #include "llvm/CodeGen/MachineRegisterInfo.h"
21 #include "llvm/Target/TargetData.h"
22 #include "llvm/Target/TargetMachine.h"
23 #include "llvm/Target/TargetInstrInfo.h"
24 #include "llvm/Target/TargetLowering.h"
25 #include "llvm/ADT/Statistic.h"
26 #include "llvm/Support/CommandLine.h"
27 #include "llvm/Support/Debug.h"
28 #include "llvm/Support/MathExtras.h"
31 /// EmitCopyFromReg - Generate machine code for an CopyFromReg node or an
32 /// implicit physical register output.
33 void ScheduleDAGSDNodes::
34 EmitCopyFromReg(SDNode *Node, unsigned ResNo, bool IsClone, bool IsCloned,
35 unsigned SrcReg, DenseMap<SDValue, unsigned> &VRBaseMap) {
37 if (TargetRegisterInfo::isVirtualRegister(SrcReg)) {
38 // Just use the input register directly!
39 SDValue Op(Node, ResNo);
42 bool isNew = VRBaseMap.insert(std::make_pair(Op, SrcReg)).second;
43 isNew = isNew; // Silence compiler warning.
44 assert(isNew && "Node emitted out of order - early");
48 // If the node is only used by a CopyToReg and the dest reg is a vreg, use
49 // the CopyToReg'd destination register instead of creating a new vreg.
51 const TargetRegisterClass *UseRC = NULL;
52 if (!IsClone && !IsCloned)
53 for (SDNode::use_iterator UI = Node->use_begin(), E = Node->use_end();
57 if (User->getOpcode() == ISD::CopyToReg &&
58 User->getOperand(2).getNode() == Node &&
59 User->getOperand(2).getResNo() == ResNo) {
60 unsigned DestReg = cast<RegisterSDNode>(User->getOperand(1))->getReg();
61 if (TargetRegisterInfo::isVirtualRegister(DestReg)) {
64 } else if (DestReg != SrcReg)
67 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) {
68 SDValue Op = User->getOperand(i);
69 if (Op.getNode() != Node || Op.getResNo() != ResNo)
71 MVT VT = Node->getValueType(Op.getResNo());
72 if (VT == MVT::Other || VT == MVT::Flag)
75 if (User->isMachineOpcode()) {
76 const TargetInstrDesc &II = TII->get(User->getMachineOpcode());
77 const TargetRegisterClass *RC =
78 getInstrOperandRegClass(TRI, II, i+II.getNumDefs());
82 if (UseRC->hasSuperClass(RC))
85 assert((UseRC == RC || RC->hasSuperClass(UseRC)) &&
86 "Multiple uses expecting different register classes!");
96 MVT VT = Node->getValueType(ResNo);
97 const TargetRegisterClass *SrcRC = 0, *DstRC = 0;
98 SrcRC = TRI->getPhysicalRegisterRegClass(SrcReg, VT);
100 // Figure out the register class to create for the destreg.
102 DstRC = MRI.getRegClass(VRBase);
104 assert(UseRC->hasType(VT) && "Incompatible phys register def and uses!");
107 DstRC = TLI->getRegClassFor(VT);
110 // If all uses are reading from the src physical register and copying the
111 // register is either impossible or very expensive, then don't create a copy.
112 if (MatchReg && SrcRC->getCopyCost() < 0) {
115 // Create the reg, emit the copy.
116 VRBase = MRI.createVirtualRegister(DstRC);
117 bool Emitted = TII->copyRegToReg(*BB, InsertPos, VRBase, SrcReg,
120 assert(Emitted && "Unable to issue a copy instruction!\n");
124 SDValue Op(Node, ResNo);
127 bool isNew = VRBaseMap.insert(std::make_pair(Op, VRBase)).second;
128 isNew = isNew; // Silence compiler warning.
129 assert(isNew && "Node emitted out of order - early");
132 /// getDstOfCopyToRegUse - If the only use of the specified result number of
133 /// node is a CopyToReg, return its destination register. Return 0 otherwise.
134 unsigned ScheduleDAGSDNodes::getDstOfOnlyCopyToRegUse(SDNode *Node,
135 unsigned ResNo) const {
136 if (!Node->hasOneUse())
139 SDNode *User = *Node->use_begin();
140 if (User->getOpcode() == ISD::CopyToReg &&
141 User->getOperand(2).getNode() == Node &&
142 User->getOperand(2).getResNo() == ResNo) {
143 unsigned Reg = cast<RegisterSDNode>(User->getOperand(1))->getReg();
144 if (TargetRegisterInfo::isVirtualRegister(Reg))
150 void ScheduleDAGSDNodes::CreateVirtualRegisters(SDNode *Node, MachineInstr *MI,
151 const TargetInstrDesc &II,
152 bool IsClone, bool IsCloned,
153 DenseMap<SDValue, unsigned> &VRBaseMap) {
154 assert(Node->getMachineOpcode() != TargetInstrInfo::IMPLICIT_DEF &&
155 "IMPLICIT_DEF should have been handled as a special case elsewhere!");
157 for (unsigned i = 0; i < II.getNumDefs(); ++i) {
158 // If the specific node value is only used by a CopyToReg and the dest reg
159 // is a vreg in the same register class, use the CopyToReg'd destination
160 // register instead of creating a new vreg.
162 const TargetRegisterClass *RC = getInstrOperandRegClass(TRI, II, i);
163 if (II.OpInfo[i].isOptionalDef()) {
164 // Optional def must be a physical register.
165 unsigned NumResults = CountResults(Node);
166 VRBase = cast<RegisterSDNode>(Node->getOperand(i-NumResults))->getReg();
167 assert(TargetRegisterInfo::isPhysicalRegister(VRBase));
168 MI->addOperand(MachineOperand::CreateReg(VRBase, true));
171 if (!VRBase && !IsClone && !IsCloned)
172 for (SDNode::use_iterator UI = Node->use_begin(), E = Node->use_end();
175 if (User->getOpcode() == ISD::CopyToReg &&
176 User->getOperand(2).getNode() == Node &&
177 User->getOperand(2).getResNo() == i) {
178 unsigned Reg = cast<RegisterSDNode>(User->getOperand(1))->getReg();
179 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
180 const TargetRegisterClass *RegRC = MRI.getRegClass(Reg);
183 MI->addOperand(MachineOperand::CreateReg(Reg, true));
190 // Create the result registers for this node and add the result regs to
191 // the machine instruction.
193 assert(RC && "Isn't a register operand!");
194 VRBase = MRI.createVirtualRegister(RC);
195 MI->addOperand(MachineOperand::CreateReg(VRBase, true));
201 bool isNew = VRBaseMap.insert(std::make_pair(Op, VRBase)).second;
202 isNew = isNew; // Silence compiler warning.
203 assert(isNew && "Node emitted out of order - early");
207 /// getVR - Return the virtual register corresponding to the specified result
208 /// of the specified node.
209 unsigned ScheduleDAGSDNodes::getVR(SDValue Op,
210 DenseMap<SDValue, unsigned> &VRBaseMap) {
211 if (Op.isMachineOpcode() &&
212 Op.getMachineOpcode() == TargetInstrInfo::IMPLICIT_DEF) {
213 // Add an IMPLICIT_DEF instruction before every use.
214 unsigned VReg = getDstOfOnlyCopyToRegUse(Op.getNode(), Op.getResNo());
215 // IMPLICIT_DEF can produce any type of result so its TargetInstrDesc
216 // does not include operand register class info.
218 const TargetRegisterClass *RC = TLI->getRegClassFor(Op.getValueType());
219 VReg = MRI.createVirtualRegister(RC);
221 BuildMI(BB, Op.getDebugLoc(), TII->get(TargetInstrInfo::IMPLICIT_DEF),VReg);
225 DenseMap<SDValue, unsigned>::iterator I = VRBaseMap.find(Op);
226 assert(I != VRBaseMap.end() && "Node emitted out of order - late");
231 /// AddRegisterOperand - Add the specified register as an operand to the
232 /// specified machine instr. Insert register copies if the register is
233 /// not in the required register class.
235 ScheduleDAGSDNodes::AddRegisterOperand(MachineInstr *MI, SDValue Op,
237 const TargetInstrDesc *II,
238 DenseMap<SDValue, unsigned> &VRBaseMap) {
239 assert(Op.getValueType() != MVT::Other &&
240 Op.getValueType() != MVT::Flag &&
241 "Chain and flag operands should occur at end of operand list!");
242 // Get/emit the operand.
243 unsigned VReg = getVR(Op, VRBaseMap);
244 assert(TargetRegisterInfo::isVirtualRegister(VReg) && "Not a vreg?");
246 const TargetInstrDesc &TID = MI->getDesc();
247 bool isOptDef = IIOpNum < TID.getNumOperands() &&
248 TID.OpInfo[IIOpNum].isOptionalDef();
250 // If the instruction requires a register in a different class, create
251 // a new virtual register and copy the value into it.
253 const TargetRegisterClass *SrcRC =
254 MRI.getRegClass(VReg);
255 const TargetRegisterClass *DstRC =
256 getInstrOperandRegClass(TRI, *II, IIOpNum);
257 assert((DstRC || (TID.isVariadic() && IIOpNum >= TID.getNumOperands())) &&
258 "Don't have operand info for this instruction!");
259 if (DstRC && SrcRC != DstRC && !SrcRC->hasSuperClass(DstRC)) {
260 unsigned NewVReg = MRI.createVirtualRegister(DstRC);
261 bool Emitted = TII->copyRegToReg(*BB, InsertPos, NewVReg, VReg,
263 assert(Emitted && "Unable to issue a copy instruction!\n");
269 MI->addOperand(MachineOperand::CreateReg(VReg, isOptDef));
272 /// AddOperand - Add the specified operand to the specified machine instr. II
273 /// specifies the instruction information for the node, and IIOpNum is the
274 /// operand number (in the II) that we are adding. IIOpNum and II are used for
276 void ScheduleDAGSDNodes::AddOperand(MachineInstr *MI, SDValue Op,
278 const TargetInstrDesc *II,
279 DenseMap<SDValue, unsigned> &VRBaseMap) {
280 if (Op.isMachineOpcode()) {
281 AddRegisterOperand(MI, Op, IIOpNum, II, VRBaseMap);
282 } else if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
283 MI->addOperand(MachineOperand::CreateImm(C->getZExtValue()));
284 } else if (ConstantFPSDNode *F = dyn_cast<ConstantFPSDNode>(Op)) {
285 const ConstantFP *CFP = F->getConstantFPValue();
286 MI->addOperand(MachineOperand::CreateFPImm(CFP));
287 } else if (RegisterSDNode *R = dyn_cast<RegisterSDNode>(Op)) {
288 MI->addOperand(MachineOperand::CreateReg(R->getReg(), false));
289 } else if (GlobalAddressSDNode *TGA = dyn_cast<GlobalAddressSDNode>(Op)) {
290 MI->addOperand(MachineOperand::CreateGA(TGA->getGlobal(), TGA->getOffset(),
291 TGA->getTargetFlags()));
292 } else if (BasicBlockSDNode *BBNode = dyn_cast<BasicBlockSDNode>(Op)) {
293 MI->addOperand(MachineOperand::CreateMBB(BBNode->getBasicBlock()));
294 } else if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(Op)) {
295 MI->addOperand(MachineOperand::CreateFI(FI->getIndex()));
296 } else if (JumpTableSDNode *JT = dyn_cast<JumpTableSDNode>(Op)) {
297 MI->addOperand(MachineOperand::CreateJTI(JT->getIndex(),
298 JT->getTargetFlags()));
299 } else if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Op)) {
300 int Offset = CP->getOffset();
301 unsigned Align = CP->getAlignment();
302 const Type *Type = CP->getType();
303 // MachineConstantPool wants an explicit alignment.
305 Align = TM.getTargetData()->getPrefTypeAlignment(Type);
307 // Alignment of vector types. FIXME!
308 Align = TM.getTargetData()->getTypeAllocSize(Type);
313 if (CP->isMachineConstantPoolEntry())
314 Idx = ConstPool->getConstantPoolIndex(CP->getMachineCPVal(), Align);
316 Idx = ConstPool->getConstantPoolIndex(CP->getConstVal(), Align);
317 MI->addOperand(MachineOperand::CreateCPI(Idx, Offset,
318 CP->getTargetFlags()));
319 } else if (ExternalSymbolSDNode *ES = dyn_cast<ExternalSymbolSDNode>(Op)) {
320 MI->addOperand(MachineOperand::CreateES(ES->getSymbol(), 0,
321 ES->getTargetFlags()));
323 assert(Op.getValueType() != MVT::Other &&
324 Op.getValueType() != MVT::Flag &&
325 "Chain and flag operands should occur at end of operand list!");
326 AddRegisterOperand(MI, Op, IIOpNum, II, VRBaseMap);
330 /// getSuperRegisterRegClass - Returns the register class of a superreg A whose
331 /// "SubIdx"'th sub-register class is the specified register class and whose
332 /// type matches the specified type.
333 static const TargetRegisterClass*
334 getSuperRegisterRegClass(const TargetRegisterClass *TRC,
335 unsigned SubIdx, MVT VT) {
336 // Pick the register class of the superegister for this type
337 for (TargetRegisterInfo::regclass_iterator I = TRC->superregclasses_begin(),
338 E = TRC->superregclasses_end(); I != E; ++I)
339 if ((*I)->hasType(VT) && (*I)->getSubRegisterRegClass(SubIdx) == TRC)
341 assert(false && "Couldn't find the register class");
345 /// EmitSubregNode - Generate machine code for subreg nodes.
347 void ScheduleDAGSDNodes::EmitSubregNode(SDNode *Node,
348 DenseMap<SDValue, unsigned> &VRBaseMap){
350 unsigned Opc = Node->getMachineOpcode();
352 // If the node is only used by a CopyToReg and the dest reg is a vreg, use
353 // the CopyToReg'd destination register instead of creating a new vreg.
354 for (SDNode::use_iterator UI = Node->use_begin(), E = Node->use_end();
357 if (User->getOpcode() == ISD::CopyToReg &&
358 User->getOperand(2).getNode() == Node) {
359 unsigned DestReg = cast<RegisterSDNode>(User->getOperand(1))->getReg();
360 if (TargetRegisterInfo::isVirtualRegister(DestReg)) {
367 if (Opc == TargetInstrInfo::EXTRACT_SUBREG) {
368 unsigned SubIdx = cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue();
370 // Create the extract_subreg machine instruction.
371 MachineInstr *MI = BuildMI(MF, Node->getDebugLoc(),
372 TII->get(TargetInstrInfo::EXTRACT_SUBREG));
374 // Figure out the register class to create for the destreg.
375 unsigned VReg = getVR(Node->getOperand(0), VRBaseMap);
376 const TargetRegisterClass *TRC = MRI.getRegClass(VReg);
377 const TargetRegisterClass *SRC = TRC->getSubRegisterRegClass(SubIdx);
378 assert(SRC && "Invalid subregister index in EXTRACT_SUBREG");
380 // Figure out the register class to create for the destreg.
381 // Note that if we're going to directly use an existing register,
382 // it must be precisely the required class, and not a subclass
384 if (VRBase == 0 || SRC != MRI.getRegClass(VRBase)) {
386 assert(SRC && "Couldn't find source register class");
387 VRBase = MRI.createVirtualRegister(SRC);
390 // Add def, source, and subreg index
391 MI->addOperand(MachineOperand::CreateReg(VRBase, true));
392 AddOperand(MI, Node->getOperand(0), 0, 0, VRBaseMap);
393 MI->addOperand(MachineOperand::CreateImm(SubIdx));
394 BB->insert(InsertPos, MI);
395 } else if (Opc == TargetInstrInfo::INSERT_SUBREG ||
396 Opc == TargetInstrInfo::SUBREG_TO_REG) {
397 SDValue N0 = Node->getOperand(0);
398 SDValue N1 = Node->getOperand(1);
399 SDValue N2 = Node->getOperand(2);
400 unsigned SubReg = getVR(N1, VRBaseMap);
401 unsigned SubIdx = cast<ConstantSDNode>(N2)->getZExtValue();
402 const TargetRegisterClass *TRC = MRI.getRegClass(SubReg);
403 const TargetRegisterClass *SRC =
404 getSuperRegisterRegClass(TRC, SubIdx,
405 Node->getValueType(0));
407 // Figure out the register class to create for the destreg.
408 // Note that if we're going to directly use an existing register,
409 // it must be precisely the required class, and not a subclass
411 if (VRBase == 0 || SRC != MRI.getRegClass(VRBase)) {
413 assert(SRC && "Couldn't find source register class");
414 VRBase = MRI.createVirtualRegister(SRC);
417 // Create the insert_subreg or subreg_to_reg machine instruction.
418 MachineInstr *MI = BuildMI(MF, Node->getDebugLoc(), TII->get(Opc));
419 MI->addOperand(MachineOperand::CreateReg(VRBase, true));
421 // If creating a subreg_to_reg, then the first input operand
422 // is an implicit value immediate, otherwise it's a register
423 if (Opc == TargetInstrInfo::SUBREG_TO_REG) {
424 const ConstantSDNode *SD = cast<ConstantSDNode>(N0);
425 MI->addOperand(MachineOperand::CreateImm(SD->getZExtValue()));
427 AddOperand(MI, N0, 0, 0, VRBaseMap);
428 // Add the subregster being inserted
429 AddOperand(MI, N1, 0, 0, VRBaseMap);
430 MI->addOperand(MachineOperand::CreateImm(SubIdx));
431 BB->insert(InsertPos, MI);
433 assert(0 && "Node is not insert_subreg, extract_subreg, or subreg_to_reg");
436 bool isNew = VRBaseMap.insert(std::make_pair(Op, VRBase)).second;
437 isNew = isNew; // Silence compiler warning.
438 assert(isNew && "Node emitted out of order - early");
441 /// EmitCopyToRegClassNode - Generate machine code for COPY_TO_REGCLASS nodes.
442 /// COPY_TO_REGCLASS is just a normal copy, except that the destination
443 /// register is constrained to be in a particular register class.
446 ScheduleDAGSDNodes::EmitCopyToRegClassNode(SDNode *Node,
447 DenseMap<SDValue, unsigned> &VRBaseMap) {
448 unsigned VReg = getVR(Node->getOperand(0), VRBaseMap);
449 const TargetRegisterClass *SrcRC = MRI.getRegClass(VReg);
451 unsigned DstRCIdx = cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue();
452 const TargetRegisterClass *DstRC = TRI->getRegClass(DstRCIdx);
454 // Create the new VReg in the destination class and emit a copy.
455 unsigned NewVReg = MRI.createVirtualRegister(DstRC);
456 bool Emitted = TII->copyRegToReg(*BB, InsertPos, NewVReg, VReg,
459 "Unable to issue a copy instruction for a COPY_TO_REGCLASS node!\n");
463 bool isNew = VRBaseMap.insert(std::make_pair(Op, NewVReg)).second;
464 isNew = isNew; // Silence compiler warning.
465 assert(isNew && "Node emitted out of order - early");
468 /// EmitNode - Generate machine code for an node and needed dependencies.
470 void ScheduleDAGSDNodes::EmitNode(SDNode *Node, bool IsClone, bool IsCloned,
471 DenseMap<SDValue, unsigned> &VRBaseMap) {
472 // If machine instruction
473 if (Node->isMachineOpcode()) {
474 unsigned Opc = Node->getMachineOpcode();
476 // Handle subreg insert/extract specially
477 if (Opc == TargetInstrInfo::EXTRACT_SUBREG ||
478 Opc == TargetInstrInfo::INSERT_SUBREG ||
479 Opc == TargetInstrInfo::SUBREG_TO_REG) {
480 EmitSubregNode(Node, VRBaseMap);
484 // Handle COPY_TO_REGCLASS specially.
485 if (Opc == TargetInstrInfo::COPY_TO_REGCLASS) {
486 EmitCopyToRegClassNode(Node, VRBaseMap);
490 if (Opc == TargetInstrInfo::IMPLICIT_DEF)
491 // We want a unique VR for each IMPLICIT_DEF use.
494 const TargetInstrDesc &II = TII->get(Opc);
495 unsigned NumResults = CountResults(Node);
496 unsigned NodeOperands = CountOperands(Node);
497 unsigned MemOperandsEnd = ComputeMemOperandsEnd(Node);
498 bool HasPhysRegOuts = (NumResults > II.getNumDefs()) &&
499 II.getImplicitDefs() != 0;
501 unsigned NumMIOperands = NodeOperands + NumResults;
502 assert((II.getNumOperands() == NumMIOperands ||
503 HasPhysRegOuts || II.isVariadic()) &&
504 "#operands for dag node doesn't match .td file!");
507 // Create the new machine instruction.
508 MachineInstr *MI = BuildMI(MF, Node->getDebugLoc(), II);
510 // Add result register values for things that are defined by this
513 CreateVirtualRegisters(Node, MI, II, IsClone, IsCloned, VRBaseMap);
515 // Emit all of the actual operands of this instruction, adding them to the
516 // instruction as appropriate.
517 bool HasOptPRefs = II.getNumDefs() > NumResults;
518 assert((!HasOptPRefs || !HasPhysRegOuts) &&
519 "Unable to cope with optional defs and phys regs defs!");
520 unsigned NumSkip = HasOptPRefs ? II.getNumDefs() - NumResults : 0;
521 for (unsigned i = NumSkip; i != NodeOperands; ++i)
522 AddOperand(MI, Node->getOperand(i), i-NumSkip+II.getNumDefs(), &II,
525 // Emit all of the memory operands of this instruction
526 for (unsigned i = NodeOperands; i != MemOperandsEnd; ++i)
527 AddMemOperand(MI,cast<MemOperandSDNode>(Node->getOperand(i+NumSkip))->MO);
529 if (II.usesCustomDAGSchedInsertionHook()) {
530 // Insert this instruction into the basic block using a target
531 // specific inserter which may returns a new basic block.
532 BB = TLI->EmitInstrWithCustomInserter(MI, BB);
533 InsertPos = BB->end();
535 BB->insert(InsertPos, MI);
538 // Additional results must be an physical register def.
539 if (HasPhysRegOuts) {
540 for (unsigned i = II.getNumDefs(); i < NumResults; ++i) {
541 unsigned Reg = II.getImplicitDefs()[i - II.getNumDefs()];
542 if (Node->hasAnyUseOfValue(i))
543 EmitCopyFromReg(Node, i, IsClone, IsCloned, Reg, VRBaseMap);
549 switch (Node->getOpcode()) {
554 assert(0 && "This target-independent node should have been selected!");
556 case ISD::EntryToken:
557 assert(0 && "EntryToken should have been excluded from the schedule!");
559 case ISD::TokenFactor: // fall thru
561 case ISD::CopyToReg: {
563 SDValue SrcVal = Node->getOperand(2);
564 if (RegisterSDNode *R = dyn_cast<RegisterSDNode>(SrcVal))
565 SrcReg = R->getReg();
567 SrcReg = getVR(SrcVal, VRBaseMap);
569 unsigned DestReg = cast<RegisterSDNode>(Node->getOperand(1))->getReg();
570 if (SrcReg == DestReg) // Coalesced away the copy? Ignore.
573 const TargetRegisterClass *SrcTRC = 0, *DstTRC = 0;
574 // Get the register classes of the src/dst.
575 if (TargetRegisterInfo::isVirtualRegister(SrcReg))
576 SrcTRC = MRI.getRegClass(SrcReg);
578 SrcTRC = TRI->getPhysicalRegisterRegClass(SrcReg,SrcVal.getValueType());
580 if (TargetRegisterInfo::isVirtualRegister(DestReg))
581 DstTRC = MRI.getRegClass(DestReg);
583 DstTRC = TRI->getPhysicalRegisterRegClass(DestReg,
584 Node->getOperand(1).getValueType());
586 bool Emitted = TII->copyRegToReg(*BB, InsertPos, DestReg, SrcReg,
588 assert(Emitted && "Unable to issue a copy instruction!\n");
592 case ISD::CopyFromReg: {
593 unsigned SrcReg = cast<RegisterSDNode>(Node->getOperand(1))->getReg();
594 EmitCopyFromReg(Node, 0, IsClone, IsCloned, SrcReg, VRBaseMap);
597 case ISD::INLINEASM: {
598 unsigned NumOps = Node->getNumOperands();
599 if (Node->getOperand(NumOps-1).getValueType() == MVT::Flag)
600 --NumOps; // Ignore the flag operand.
602 // Create the inline asm machine instruction.
603 MachineInstr *MI = BuildMI(MF, Node->getDebugLoc(),
604 TII->get(TargetInstrInfo::INLINEASM));
606 // Add the asm string as an external symbol operand.
608 cast<ExternalSymbolSDNode>(Node->getOperand(1))->getSymbol();
609 MI->addOperand(MachineOperand::CreateES(AsmStr));
611 // Add all of the operand registers to the instruction.
612 for (unsigned i = 2; i != NumOps;) {
614 cast<ConstantSDNode>(Node->getOperand(i))->getZExtValue();
615 unsigned NumVals = InlineAsm::getNumOperandRegisters(Flags);
617 MI->addOperand(MachineOperand::CreateImm(Flags));
618 ++i; // Skip the ID value.
621 default: assert(0 && "Bad flags!");
622 case 2: // Def of register.
623 for (; NumVals; --NumVals, ++i) {
624 unsigned Reg = cast<RegisterSDNode>(Node->getOperand(i))->getReg();
625 MI->addOperand(MachineOperand::CreateReg(Reg, true));
628 case 6: // Def of earlyclobber register.
629 for (; NumVals; --NumVals, ++i) {
630 unsigned Reg = cast<RegisterSDNode>(Node->getOperand(i))->getReg();
631 MI->addOperand(MachineOperand::CreateReg(Reg, true, false, false,
632 false, false, true));
635 case 1: // Use of register.
636 case 3: // Immediate.
637 case 4: // Addressing mode.
638 // The addressing mode has been selected, just add all of the
639 // operands to the machine instruction.
640 for (; NumVals; --NumVals, ++i)
641 AddOperand(MI, Node->getOperand(i), 0, 0, VRBaseMap);
645 BB->insert(InsertPos, MI);
651 /// EmitSchedule - Emit the machine code in scheduled order.
652 MachineBasicBlock *ScheduleDAGSDNodes::EmitSchedule() {
653 DenseMap<SDValue, unsigned> VRBaseMap;
654 DenseMap<SUnit*, unsigned> CopyVRBaseMap;
655 for (unsigned i = 0, e = Sequence.size(); i != e; i++) {
656 SUnit *SU = Sequence[i];
658 // Null SUnit* is a noop.
663 // For pre-regalloc scheduling, create instructions corresponding to the
664 // SDNode and any flagged SDNodes and append them to the block.
665 if (!SU->getNode()) {
667 EmitPhysRegCopy(SU, CopyVRBaseMap);
671 SmallVector<SDNode *, 4> FlaggedNodes;
672 for (SDNode *N = SU->getNode()->getFlaggedNode(); N;
673 N = N->getFlaggedNode())
674 FlaggedNodes.push_back(N);
675 while (!FlaggedNodes.empty()) {
676 EmitNode(FlaggedNodes.back(), SU->OrigNode != SU, SU->isCloned,VRBaseMap);
677 FlaggedNodes.pop_back();
679 EmitNode(SU->getNode(), SU->OrigNode != SU, SU->isCloned, VRBaseMap);