1 //===-- ScheduleDAG.cpp - Implement a trivial DAG scheduler ---------------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by James M. Laskey and is distributed under the
6 // University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements a simple two pass scheduler. The first pass attempts to push
11 // backward any lengthy instructions and critical paths. The second pass packs
12 // instructions into semi-optimal time slots.
14 //===----------------------------------------------------------------------===//
16 #define DEBUG_TYPE "sched"
17 #include "llvm/CodeGen/MachineConstantPool.h"
18 #include "llvm/CodeGen/MachineFunction.h"
19 #include "llvm/CodeGen/SelectionDAGISel.h"
20 #include "llvm/CodeGen/SelectionDAG.h"
21 #include "llvm/CodeGen/SSARegMap.h"
22 #include "llvm/Target/TargetMachine.h"
23 #include "llvm/Target/TargetInstrInfo.h"
24 #include "llvm/Target/TargetInstrItineraries.h"
25 #include "llvm/Target/TargetLowering.h"
26 #include "llvm/Support/CommandLine.h"
27 #include "llvm/Support/Debug.h"
33 // Style of scheduling to use.
34 enum ScheduleChoices {
37 simpleNoItinScheduling
41 cl::opt<ScheduleChoices> ScheduleStyle("sched",
42 cl::desc("Choose scheduling style"),
43 cl::init(noScheduling),
45 clEnumValN(noScheduling, "none",
46 "Trivial emission with no analysis"),
47 clEnumValN(simpleScheduling, "simple",
48 "Minimize critical path and maximize processor utilization"),
49 clEnumValN(simpleNoItinScheduling, "simple-noitin",
50 "Same as simple except using generic latency"),
56 ViewDAGs("view-sched-dags", cl::Hidden,
57 cl::desc("Pop up a window to show sched dags as they are processed"));
59 static const bool ViewDAGs = 0;
63 //===----------------------------------------------------------------------===//
65 /// BitsIterator - Provides iteration through individual bits in a bit vector.
70 T Bits; // Bits left to iterate through
74 BitsIterator(T Initial) : Bits(Initial) {}
76 /// Next - Returns the next bit set or zero if exhausted.
78 // Get the rightmost bit set
79 T Result = Bits & -Bits;
82 // Return single bit or zero
87 //===----------------------------------------------------------------------===//
90 //===----------------------------------------------------------------------===//
92 /// ResourceTally - Manages the use of resources over time intervals. Each
93 /// item (slot) in the tally vector represents the resources used at a given
94 /// moment. A bit set to 1 indicates that a resource is in use, otherwise
95 /// available. An assumption is made that the tally is large enough to schedule
96 /// all current instructions (asserts otherwise.)
101 std::vector<T> Tally; // Resources used per slot
102 typedef typename std::vector<T>::iterator Iter;
105 /// SlotsAvailable - Returns true if all units are available.
107 bool SlotsAvailable(Iter Begin, unsigned N, unsigned ResourceSet,
108 unsigned &Resource) {
109 assert(N && "Must check availability with N != 0");
110 // Determine end of interval
111 Iter End = Begin + N;
112 assert(End <= Tally.end() && "Tally is not large enough for schedule");
114 // Iterate thru each resource
115 BitsIterator<T> Resources(ResourceSet & ~*Begin);
116 while (unsigned Res = Resources.Next()) {
117 // Check if resource is available for next N slots
121 if (*Interval & Res) break;
122 } while (Interval != Begin);
124 // If available for N
125 if (Interval == Begin) {
137 /// RetrySlot - Finds a good candidate slot to retry search.
138 Iter RetrySlot(Iter Begin, unsigned N, unsigned ResourceSet) {
139 assert(N && "Must check availability with N != 0");
140 // Determine end of interval
141 Iter End = Begin + N;
142 assert(End <= Tally.end() && "Tally is not large enough for schedule");
144 while (Begin != End--) {
145 // Clear units in use
146 ResourceSet &= ~*End;
147 // If no units left then we should go no further
148 if (!ResourceSet) return End + 1;
150 // Made it all the way through
154 /// FindAndReserveStages - Return true if the stages can be completed. If
156 bool FindAndReserveStages(Iter Begin,
157 InstrStage *Stage, InstrStage *StageEnd) {
158 // If at last stage then we're done
159 if (Stage == StageEnd) return true;
160 // Get number of cycles for current stage
161 unsigned N = Stage->Cycles;
162 // Check to see if N slots are available, if not fail
164 if (!SlotsAvailable(Begin, N, Stage->Units, Resource)) return false;
165 // Check to see if remaining stages are available, if not fail
166 if (!FindAndReserveStages(Begin + N, Stage + 1, StageEnd)) return false;
168 Reserve(Begin, N, Resource);
173 /// Reserve - Mark busy (set) the specified N slots.
174 void Reserve(Iter Begin, unsigned N, unsigned Resource) {
175 // Determine end of interval
176 Iter End = Begin + N;
177 assert(End <= Tally.end() && "Tally is not large enough for schedule");
179 // Set resource bit in each slot
180 for (; Begin < End; Begin++)
184 /// FindSlots - Starting from Begin, locate consecutive slots where all stages
185 /// can be completed. Returns the address of first slot.
186 Iter FindSlots(Iter Begin, InstrStage *StageBegin, InstrStage *StageEnd) {
190 // Try all possible slots forward
192 // Try at cursor, if successful return position.
193 if (FindAndReserveStages(Cursor, StageBegin, StageEnd)) return Cursor;
194 // Locate a better position
195 Cursor = RetrySlot(Cursor + 1, StageBegin->Cycles, StageBegin->Units);
200 /// Initialize - Resize and zero the tally to the specified number of time
202 inline void Initialize(unsigned N) {
203 Tally.assign(N, 0); // Initialize tally to all zeros.
206 // FindAndReserve - Locate an ideal slot for the specified stages and mark
208 unsigned FindAndReserve(unsigned Slot, InstrStage *StageBegin,
209 InstrStage *StageEnd) {
211 Iter Begin = Tally.begin() + Slot;
213 Iter Where = FindSlots(Begin, StageBegin, StageEnd);
214 // Distance is slot number
215 unsigned Final = Where - Tally.begin();
220 //===----------------------------------------------------------------------===//
224 typedef NodeInfo *NodeInfoPtr;
225 typedef std::vector<NodeInfoPtr> NIVector;
226 typedef std::vector<NodeInfoPtr>::iterator NIIterator;
228 //===----------------------------------------------------------------------===//
230 /// Node group - This struct is used to manage flagged node groups.
234 NIVector Members; // Group member nodes
235 NodeInfo *Dominator; // Node with highest latency
236 unsigned Latency; // Total latency of the group
237 int Pending; // Number of visits pending before
242 NodeGroup() : Dominator(NULL), Pending(0) {}
245 inline void setDominator(NodeInfo *D) { Dominator = D; }
246 inline NodeInfo *getDominator() { return Dominator; }
247 inline void setLatency(unsigned L) { Latency = L; }
248 inline unsigned getLatency() { return Latency; }
249 inline int getPending() const { return Pending; }
250 inline void setPending(int P) { Pending = P; }
251 inline int addPending(int I) { return Pending += I; }
254 inline bool group_empty() { return Members.empty(); }
255 inline NIIterator group_begin() { return Members.begin(); }
256 inline NIIterator group_end() { return Members.end(); }
257 inline void group_push_back(const NodeInfoPtr &NI) { Members.push_back(NI); }
258 inline NIIterator group_insert(NIIterator Pos, const NodeInfoPtr &NI) {
259 return Members.insert(Pos, NI);
261 inline void group_insert(NIIterator Pos, NIIterator First, NIIterator Last) {
262 Members.insert(Pos, First, Last);
265 static void Add(NodeInfo *D, NodeInfo *U);
266 static unsigned CountInternalUses(NodeInfo *D, NodeInfo *U);
268 //===----------------------------------------------------------------------===//
271 //===----------------------------------------------------------------------===//
273 /// NodeInfo - This struct tracks information used to schedule the a node.
277 int Pending; // Number of visits pending before
280 SDNode *Node; // DAG node
281 InstrStage *StageBegin; // First stage in itinerary
282 InstrStage *StageEnd; // Last+1 stage in itinerary
283 unsigned Latency; // Total cycles to complete instruction
284 bool IsCall : 1; // Is function call
285 bool IsLoad : 1; // Is memory load
286 bool IsStore : 1; // Is memory store
287 unsigned Slot; // Node's time slot
288 NodeGroup *Group; // Grouping information
289 unsigned VRBase; // Virtual register base
291 unsigned Preorder; // Index before scheduling
295 NodeInfo(SDNode *N = NULL)
311 inline bool isInGroup() const {
312 assert(!Group || !Group->group_empty() && "Group with no members");
313 return Group != NULL;
315 inline bool isGroupDominator() const {
316 return isInGroup() && Group->getDominator() == this;
318 inline int getPending() const {
319 return Group ? Group->getPending() : Pending;
321 inline void setPending(int P) {
322 if (Group) Group->setPending(P);
325 inline int addPending(int I) {
326 if (Group) return Group->addPending(I);
327 else return Pending += I;
330 //===----------------------------------------------------------------------===//
333 //===----------------------------------------------------------------------===//
335 /// NodeGroupIterator - Iterates over all the nodes indicated by the node info.
336 /// If the node is in a group then iterate over the members of the group,
337 /// otherwise just the node info.
339 class NodeGroupIterator {
341 NodeInfo *NI; // Node info
342 NIIterator NGI; // Node group iterator
343 NIIterator NGE; // Node group iterator end
347 NodeGroupIterator(NodeInfo *N) : NI(N) {
348 // If the node is in a group then set up the group iterator. Otherwise
349 // the group iterators will trip first time out.
350 if (N->isInGroup()) {
352 NodeGroup *Group = NI->Group;
353 NGI = Group->group_begin();
354 NGE = Group->group_end();
355 // Prevent this node from being used (will be in members list
360 /// next - Return the next node info, otherwise NULL.
364 if (NGI != NGE) return *NGI++;
365 // Use node as the result (may be NULL)
366 NodeInfo *Result = NI;
369 // Return node or NULL
373 //===----------------------------------------------------------------------===//
376 //===----------------------------------------------------------------------===//
378 /// NodeGroupOpIterator - Iterates over all the operands of a node. If the node
379 /// is a member of a group, this iterates over all the operands of all the
380 /// members of the group.
382 class NodeGroupOpIterator {
384 NodeInfo *NI; // Node containing operands
385 NodeGroupIterator GI; // Node group iterator
386 SDNode::op_iterator OI; // Operand iterator
387 SDNode::op_iterator OE; // Operand iterator end
389 /// CheckNode - Test if node has more operands. If not get the next node
390 /// skipping over nodes that have no operands.
392 // Only if operands are exhausted first
394 // Get next node info
395 NodeInfo *NI = GI.next();
396 // Exit if nodes are exhausted
399 SDNode *Node = NI->Node;
400 // Set up the operand iterators
401 OI = Node->op_begin();
408 NodeGroupOpIterator(NodeInfo *N)
409 : NI(N), GI(N), OI(SDNode::op_iterator()), OE(SDNode::op_iterator()) {}
411 /// isEnd - Returns true when not more operands are available.
413 inline bool isEnd() { CheckNode(); return OI == OE; }
415 /// next - Returns the next available operand.
417 inline SDOperand next() {
418 assert(OI != OE && "Not checking for end of NodeGroupOpIterator correctly");
422 //===----------------------------------------------------------------------===//
425 //===----------------------------------------------------------------------===//
427 /// SimpleSched - Simple two pass scheduler.
431 MachineBasicBlock *BB; // Current basic block
432 SelectionDAG &DAG; // DAG of the current basic block
433 const TargetMachine &TM; // Target processor
434 const TargetInstrInfo &TII; // Target instruction information
435 const MRegisterInfo &MRI; // Target processor register information
436 SSARegMap *RegMap; // Virtual/real register map
437 MachineConstantPool *ConstPool; // Target constant pool
438 unsigned NodeCount; // Number of nodes in DAG
439 bool HasGroups; // True if there are any groups
440 NodeInfo *Info; // Info for nodes being scheduled
441 std::map<SDNode *, NodeInfo *> Map; // Map nodes to info
442 NIVector Ordering; // Emit ordering of nodes
443 ResourceTally<unsigned> Tally; // Resource usage tally
444 unsigned NSlots; // Total latency
445 static const unsigned NotFound = ~0U; // Search marker
450 SimpleSched(SelectionDAG &D, MachineBasicBlock *bb)
451 : BB(bb), DAG(D), TM(D.getTarget()), TII(*TM.getInstrInfo()),
452 MRI(*TM.getRegisterInfo()), RegMap(BB->getParent()->getSSARegMap()),
453 ConstPool(BB->getParent()->getConstantPool()),
454 NodeCount(0), HasGroups(false), Info(NULL), Map(), Tally(), NSlots(0) {
455 assert(&TII && "Target doesn't provide instr info?");
456 assert(&MRI && "Target doesn't provide register info?");
459 // Run - perform scheduling.
460 MachineBasicBlock *Run() {
466 /// getNI - Returns the node info for the specified node.
468 inline NodeInfo *getNI(SDNode *Node) { return Map[Node]; }
470 /// getVR - Returns the virtual register number of the node.
472 inline unsigned getVR(SDOperand Op) {
473 NodeInfo *NI = getNI(Op.Val);
474 assert(NI->VRBase != 0 && "Node emitted out of order - late");
475 return NI->VRBase + Op.ResNo;
478 static bool isFlagDefiner(SDNode *A);
479 static bool isFlagUser(SDNode *A);
480 static bool isDefiner(NodeInfo *A, NodeInfo *B);
481 static bool isPassiveNode(SDNode *Node);
482 void IncludeNode(NodeInfo *NI);
485 void IdentifyGroups();
486 void GatherSchedulingInfo();
487 void FakeGroupDominators();
488 void PrepareNodeInfo();
489 bool isStrongDependency(NodeInfo *A, NodeInfo *B);
490 bool isWeakDependency(NodeInfo *A, NodeInfo *B);
491 void ScheduleBackward();
492 void ScheduleForward();
494 void EmitNode(NodeInfo *NI);
495 static unsigned CountResults(SDNode *Node);
496 static unsigned CountOperands(SDNode *Node);
497 unsigned CreateVirtualRegisters(MachineInstr *MI,
499 const TargetInstrDescriptor &II);
501 void printChanges(unsigned Index);
502 void printSI(std::ostream &O, NodeInfo *NI) const;
503 void print(std::ostream &O) const;
504 inline void dump(const char *tag) const { std::cerr << tag; dump(); }
509 //===----------------------------------------------------------------------===//
510 /// Special case itineraries.
513 CallLatency = 40, // To push calls back in time
515 RSInteger = 0xC0000000, // Two integer units
516 RSFloat = 0x30000000, // Two float units
517 RSLoadStore = 0x0C000000, // Two load store units
518 RSBranch = 0x02000000 // One branch unit
520 static InstrStage CallStage = { CallLatency, RSBranch };
521 static InstrStage LoadStage = { 5, RSLoadStore };
522 static InstrStage StoreStage = { 2, RSLoadStore };
523 static InstrStage IntStage = { 2, RSInteger };
524 static InstrStage FloatStage = { 3, RSFloat };
525 //===----------------------------------------------------------------------===//
528 //===----------------------------------------------------------------------===//
532 //===----------------------------------------------------------------------===//
535 //===----------------------------------------------------------------------===//
536 /// Add - Adds a definer and user pair to a node group.
538 void NodeGroup::Add(NodeInfo *D, NodeInfo *U) {
539 // Get current groups
540 NodeGroup *DGroup = D->Group;
541 NodeGroup *UGroup = U->Group;
542 // If both are members of groups
543 if (DGroup && UGroup) {
544 // There may have been another edge connecting
545 if (DGroup == UGroup) return;
546 // Add the pending users count
547 DGroup->addPending(UGroup->getPending());
548 // For each member of the users group
549 NodeGroupIterator UNGI(U);
550 while (NodeInfo *UNI = UNGI.next() ) {
553 // For each member of the definers group
554 NodeGroupIterator DNGI(D);
555 while (NodeInfo *DNI = DNGI.next() ) {
556 // Remove internal edges
557 DGroup->addPending(-CountInternalUses(DNI, UNI));
560 // Merge the two lists
561 DGroup->group_insert(DGroup->group_end(),
562 UGroup->group_begin(), UGroup->group_end());
564 // Make user member of definers group
566 // Add users uses to definers group pending
567 DGroup->addPending(U->Node->use_size());
568 // For each member of the definers group
569 NodeGroupIterator DNGI(D);
570 while (NodeInfo *DNI = DNGI.next() ) {
571 // Remove internal edges
572 DGroup->addPending(-CountInternalUses(DNI, U));
574 DGroup->group_push_back(U);
576 // Make definer member of users group
578 // Add definers uses to users group pending
579 UGroup->addPending(D->Node->use_size());
580 // For each member of the users group
581 NodeGroupIterator UNGI(U);
582 while (NodeInfo *UNI = UNGI.next() ) {
583 // Remove internal edges
584 UGroup->addPending(-CountInternalUses(D, UNI));
586 UGroup->group_insert(UGroup->group_begin(), D);
588 D->Group = U->Group = DGroup = new NodeGroup();
589 DGroup->addPending(D->Node->use_size() + U->Node->use_size() -
590 CountInternalUses(D, U));
591 DGroup->group_push_back(D);
592 DGroup->group_push_back(U);
596 /// CountInternalUses - Returns the number of edges between the two nodes.
598 unsigned NodeGroup::CountInternalUses(NodeInfo *D, NodeInfo *U) {
600 for (unsigned M = U->Node->getNumOperands(); 0 < M--;) {
601 SDOperand Op = U->Node->getOperand(M);
602 if (Op.Val == D->Node) N++;
607 //===----------------------------------------------------------------------===//
610 //===----------------------------------------------------------------------===//
611 /// isFlagDefiner - Returns true if the node defines a flag result.
612 bool SimpleSched::isFlagDefiner(SDNode *A) {
613 unsigned N = A->getNumValues();
614 return N && A->getValueType(N - 1) == MVT::Flag;
617 /// isFlagUser - Returns true if the node uses a flag result.
619 bool SimpleSched::isFlagUser(SDNode *A) {
620 unsigned N = A->getNumOperands();
621 return N && A->getOperand(N - 1).getValueType() == MVT::Flag;
624 /// isDefiner - Return true if node A is a definer for B.
626 bool SimpleSched::isDefiner(NodeInfo *A, NodeInfo *B) {
627 // While there are A nodes
628 NodeGroupIterator NII(A);
629 while (NodeInfo *NI = NII.next()) {
631 SDNode *Node = NI->Node;
632 // While there operands in nodes of B
633 NodeGroupOpIterator NGOI(B);
634 while (!NGOI.isEnd()) {
635 SDOperand Op = NGOI.next();
636 // If node from A defines a node in B
637 if (Node == Op.Val) return true;
643 /// isPassiveNode - Return true if the node is a non-scheduled leaf.
645 bool SimpleSched::isPassiveNode(SDNode *Node) {
646 if (isa<ConstantSDNode>(Node)) return true;
647 if (isa<RegisterSDNode>(Node)) return true;
648 if (isa<GlobalAddressSDNode>(Node)) return true;
649 if (isa<BasicBlockSDNode>(Node)) return true;
650 if (isa<FrameIndexSDNode>(Node)) return true;
651 if (isa<ConstantPoolSDNode>(Node)) return true;
652 if (isa<ExternalSymbolSDNode>(Node)) return true;
656 /// IncludeNode - Add node to NodeInfo vector.
658 void SimpleSched::IncludeNode(NodeInfo *NI) {
660 SDNode *Node = NI->Node;
662 if (Node->getOpcode() == ISD::EntryToken) return;
663 // Check current count for node
664 int Count = NI->getPending();
665 // If the node is already in list
666 if (Count < 0) return;
667 // Decrement count to indicate a visit
669 // If count has gone to zero then add node to list
672 if (NI->isInGroup()) {
673 Ordering.push_back(NI->Group->getDominator());
675 Ordering.push_back(NI);
677 // indicate node has been added
680 // Mark as visited with new count
681 NI->setPending(Count);
684 /// VisitAll - Visit each node breadth-wise to produce an initial ordering.
685 /// Note that the ordering in the Nodes vector is reversed.
686 void SimpleSched::VisitAll() {
687 // Add first element to list
688 NodeInfo *NI = getNI(DAG.getRoot().Val);
689 if (NI->isInGroup()) {
690 Ordering.push_back(NI->Group->getDominator());
692 Ordering.push_back(NI);
695 // Iterate through all nodes that have been added
696 for (unsigned i = 0; i < Ordering.size(); i++) { // note: size() varies
697 // Visit all operands
698 NodeGroupOpIterator NGI(Ordering[i]);
699 while (!NGI.isEnd()) {
701 SDOperand Op = NGI.next();
703 SDNode *Node = Op.Val;
704 // Ignore passive nodes
705 if (isPassiveNode(Node)) continue;
707 IncludeNode(getNI(Node));
711 // Add entry node last (IncludeNode filters entry nodes)
712 if (DAG.getEntryNode().Val != DAG.getRoot().Val)
713 Ordering.push_back(getNI(DAG.getEntryNode().Val));
716 std::reverse(Ordering.begin(), Ordering.end());
719 /// IdentifyGroups - Put flagged nodes into groups.
721 void SimpleSched::IdentifyGroups() {
722 for (unsigned i = 0, N = NodeCount; i < N; i++) {
723 NodeInfo* NI = &Info[i];
724 SDNode *Node = NI->Node;
726 // For each operand (in reverse to only look at flags)
727 for (unsigned N = Node->getNumOperands(); 0 < N--;) {
729 SDOperand Op = Node->getOperand(N);
730 // No more flags to walk
731 if (Op.getValueType() != MVT::Flag) break;
733 NodeGroup::Add(getNI(Op.Val), NI);
734 // Let evryone else know
740 /// GatherSchedulingInfo - Get latency and resource information about each node.
742 void SimpleSched::GatherSchedulingInfo() {
743 // Get instruction itineraries for the target
744 const InstrItineraryData InstrItins = TM.getInstrItineraryData();
747 for (unsigned i = 0, N = NodeCount; i < N; i++) {
749 NodeInfo* NI = &Info[i];
750 SDNode *Node = NI->Node;
752 // If there are itineraries and it is a machine instruction
753 if (InstrItins.isEmpty() || ScheduleStyle == simpleNoItinScheduling) {
755 if (Node->isTargetOpcode()) {
756 // Get return type to guess which processing unit
757 MVT::ValueType VT = Node->getValueType(0);
758 // Get machine opcode
759 MachineOpCode TOpc = Node->getTargetOpcode();
760 NI->IsCall = TII.isCall(TOpc);
761 NI->IsLoad = TII.isLoad(TOpc);
762 NI->IsStore = TII.isStore(TOpc);
764 if (TII.isLoad(TOpc)) NI->StageBegin = &LoadStage;
765 else if (TII.isStore(TOpc)) NI->StageBegin = &StoreStage;
766 else if (MVT::isInteger(VT)) NI->StageBegin = &IntStage;
767 else if (MVT::isFloatingPoint(VT)) NI->StageBegin = &FloatStage;
768 if (NI->StageBegin) NI->StageEnd = NI->StageBegin + 1;
770 } else if (Node->isTargetOpcode()) {
771 // get machine opcode
772 MachineOpCode TOpc = Node->getTargetOpcode();
773 // Check to see if it is a call
774 NI->IsCall = TII.isCall(TOpc);
775 // Get itinerary stages for instruction
776 unsigned II = TII.getSchedClass(TOpc);
777 NI->StageBegin = InstrItins.begin(II);
778 NI->StageEnd = InstrItins.end(II);
781 // One slot for the instruction itself
784 // Add long latency for a call to push it back in time
785 if (NI->IsCall) NI->Latency += CallLatency;
787 // Sum up all the latencies
788 for (InstrStage *Stage = NI->StageBegin, *E = NI->StageEnd;
789 Stage != E; Stage++) {
790 NI->Latency += Stage->Cycles;
793 // Sum up all the latencies for max tally size
794 NSlots += NI->Latency;
797 // Unify metrics if in a group
799 for (unsigned i = 0, N = NodeCount; i < N; i++) {
800 NodeInfo* NI = &Info[i];
802 if (NI->isInGroup()) {
803 NodeGroup *Group = NI->Group;
805 if (!Group->getDominator()) {
806 NIIterator NGI = Group->group_begin(), NGE = Group->group_end();
807 NodeInfo *Dominator = *NGI;
808 unsigned Latency = 0;
810 for (NGI++; NGI != NGE; NGI++) {
811 NodeInfo* NGNI = *NGI;
812 Latency += NGNI->Latency;
813 if (Dominator->Latency < NGNI->Latency) Dominator = NGNI;
816 Dominator->Latency = Latency;
817 Group->setDominator(Dominator);
824 /// FakeGroupDominators - Set dominators for non-scheduling.
826 void SimpleSched::FakeGroupDominators() {
827 for (unsigned i = 0, N = NodeCount; i < N; i++) {
828 NodeInfo* NI = &Info[i];
830 if (NI->isInGroup()) {
831 NodeGroup *Group = NI->Group;
833 if (!Group->getDominator()) {
834 Group->setDominator(NI);
840 /// PrepareNodeInfo - Set up the basic minimum node info for scheduling.
842 void SimpleSched::PrepareNodeInfo() {
843 // Allocate node information
844 Info = new NodeInfo[NodeCount];
847 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(),
848 E = DAG.allnodes_end(); I != E; ++I, ++i) {
849 // Fast reference to node schedule info
850 NodeInfo* NI = &Info[i];
855 // Set pending visit count
856 NI->setPending(I->use_size());
860 /// isStrongDependency - Return true if node A has results used by node B.
861 /// I.E., B must wait for latency of A.
862 bool SimpleSched::isStrongDependency(NodeInfo *A, NodeInfo *B) {
863 // If A defines for B then it's a strong dependency
864 return isDefiner(A, B) || (A->IsStore && B->IsLoad);
867 /// isWeakDependency Return true if node A produces a result that will
868 /// conflict with operands of B. It is assumed that we have called
869 /// isStrongDependency prior.
870 bool SimpleSched::isWeakDependency(NodeInfo *A, NodeInfo *B) {
871 // TODO check for conflicting real registers and aliases
872 #if 0 // FIXME - Since we are in SSA form and not checking register aliasing
873 return A->Node->getOpcode() == ISD::EntryToken || isStrongDependency(B, A);
875 return A->Node->getOpcode() == ISD::EntryToken;
879 /// ScheduleBackward - Schedule instructions so that any long latency
880 /// instructions and the critical path get pushed back in time. Time is run in
881 /// reverse to allow code reuse of the Tally and eliminate the overhead of
882 /// biasing every slot indices against NSlots.
883 void SimpleSched::ScheduleBackward() {
884 // Size and clear the resource tally
885 Tally.Initialize(NSlots);
886 // Get number of nodes to schedule
887 unsigned N = Ordering.size();
889 // For each node being scheduled
890 for (unsigned i = N; 0 < i--;) {
891 NodeInfo *NI = Ordering[i];
893 unsigned Slot = NotFound;
895 // Compare against those previously scheduled nodes
898 // Get following instruction
899 NodeInfo *Other = Ordering[j];
901 // Check dependency against previously inserted nodes
902 if (isStrongDependency(NI, Other)) {
903 Slot = Other->Slot + Other->Latency;
905 } else if (isWeakDependency(NI, Other)) {
911 // If independent of others (or first entry)
912 if (Slot == NotFound) Slot = 0;
914 #if 0 // FIXME - measure later
915 // Find a slot where the needed resources are available
916 if (NI->StageBegin != NI->StageEnd)
917 Slot = Tally.FindAndReserve(Slot, NI->StageBegin, NI->StageEnd);
923 // Insert sort based on slot
926 // Get following instruction
927 NodeInfo *Other = Ordering[j];
928 // Should we look further (remember slots are in reverse time)
929 if (Slot >= Other->Slot) break;
930 // Shuffle other into ordering
931 Ordering[j - 1] = Other;
933 // Insert node in proper slot
934 if (j != i + 1) Ordering[j - 1] = NI;
938 /// ScheduleForward - Schedule instructions to maximize packing.
940 void SimpleSched::ScheduleForward() {
941 // Size and clear the resource tally
942 Tally.Initialize(NSlots);
943 // Get number of nodes to schedule
944 unsigned N = Ordering.size();
946 // For each node being scheduled
947 for (unsigned i = 0; i < N; i++) {
948 NodeInfo *NI = Ordering[i];
950 unsigned Slot = NotFound;
952 // Compare against those previously scheduled nodes
955 // Get following instruction
956 NodeInfo *Other = Ordering[j];
958 // Check dependency against previously inserted nodes
959 if (isStrongDependency(Other, NI)) {
960 Slot = Other->Slot + Other->Latency;
962 } else if (Other->IsCall || isWeakDependency(Other, NI)) {
968 // If independent of others (or first entry)
969 if (Slot == NotFound) Slot = 0;
971 // Find a slot where the needed resources are available
972 if (NI->StageBegin != NI->StageEnd)
973 Slot = Tally.FindAndReserve(Slot, NI->StageBegin, NI->StageEnd);
978 // Insert sort based on slot
981 // Get prior instruction
982 NodeInfo *Other = Ordering[j];
983 // Should we look further
984 if (Slot >= Other->Slot) break;
985 // Shuffle other into ordering
986 Ordering[j + 1] = Other;
988 // Insert node in proper slot
989 if (j != i) Ordering[j + 1] = NI;
993 /// EmitAll - Emit all nodes in schedule sorted order.
995 void SimpleSched::EmitAll() {
996 // For each node in the ordering
997 for (unsigned i = 0, N = Ordering.size(); i < N; i++) {
998 // Get the scheduling info
999 NodeInfo *NI = Ordering[i];
1000 if (NI->isInGroup()) {
1001 NodeGroupIterator NGI(Ordering[i]);
1002 while (NodeInfo *NI = NGI.next()) EmitNode(NI);
1009 /// CountResults - The results of target nodes have register or immediate
1010 /// operands first, then an optional chain, and optional flag operands (which do
1011 /// not go into the machine instrs.)
1012 unsigned SimpleSched::CountResults(SDNode *Node) {
1013 unsigned N = Node->getNumValues();
1014 while (N && Node->getValueType(N - 1) == MVT::Flag)
1016 if (N && Node->getValueType(N - 1) == MVT::Other)
1017 --N; // Skip over chain result.
1021 /// CountOperands The inputs to target nodes have any actual inputs first,
1022 /// followed by an optional chain operand, then flag operands. Compute the
1023 /// number of actual operands that will go into the machine instr.
1024 unsigned SimpleSched::CountOperands(SDNode *Node) {
1025 unsigned N = Node->getNumOperands();
1026 while (N && Node->getOperand(N - 1).getValueType() == MVT::Flag)
1028 if (N && Node->getOperand(N - 1).getValueType() == MVT::Other)
1029 --N; // Ignore chain if it exists.
1033 /// CreateVirtualRegisters - Add result register values for things that are
1034 /// defined by this instruction.
1035 unsigned SimpleSched::CreateVirtualRegisters(MachineInstr *MI,
1036 unsigned NumResults,
1037 const TargetInstrDescriptor &II) {
1038 // Create the result registers for this node and add the result regs to
1039 // the machine instruction.
1040 const TargetOperandInfo *OpInfo = II.OpInfo;
1041 unsigned ResultReg = RegMap->createVirtualRegister(OpInfo[0].RegClass);
1042 MI->addRegOperand(ResultReg, MachineOperand::Def);
1043 for (unsigned i = 1; i != NumResults; ++i) {
1044 assert(OpInfo[i].RegClass && "Isn't a register operand!");
1045 MI->addRegOperand(RegMap->createVirtualRegister(OpInfo[i].RegClass),
1046 MachineOperand::Def);
1051 /// EmitNode - Generate machine code for an node and needed dependencies.
1053 void SimpleSched::EmitNode(NodeInfo *NI) {
1054 unsigned VRBase = 0; // First virtual register for node
1055 SDNode *Node = NI->Node;
1057 // If machine instruction
1058 if (Node->isTargetOpcode()) {
1059 unsigned Opc = Node->getTargetOpcode();
1060 const TargetInstrDescriptor &II = TII.get(Opc);
1062 unsigned NumResults = CountResults(Node);
1063 unsigned NodeOperands = CountOperands(Node);
1064 unsigned NumMIOperands = NodeOperands + NumResults;
1066 assert((unsigned(II.numOperands) == NumMIOperands || II.numOperands == -1)&&
1067 "#operands for dag node doesn't match .td file!");
1070 // Create the new machine instruction.
1071 MachineInstr *MI = new MachineInstr(Opc, NumMIOperands, true, true);
1073 // Add result register values for things that are defined by this
1076 // If the node is only used by a CopyToReg and the dest reg is a vreg, use
1077 // the CopyToReg'd destination register instead of creating a new vreg.
1078 if (NumResults == 1) {
1079 for (SDNode::use_iterator UI = Node->use_begin(), E = Node->use_end();
1082 if (Use->getOpcode() == ISD::CopyToReg &&
1083 Use->getOperand(2).Val == Node) {
1084 unsigned Reg = cast<RegisterSDNode>(Use->getOperand(1))->getReg();
1085 if (MRegisterInfo::isVirtualRegister(Reg)) {
1087 MI->addRegOperand(Reg, MachineOperand::Def);
1094 // Otherwise, create new virtual registers.
1095 if (NumResults && VRBase == 0)
1096 VRBase = CreateVirtualRegisters(MI, NumResults, II);
1098 // Emit all of the actual operands of this instruction, adding them to the
1099 // instruction as appropriate.
1100 for (unsigned i = 0; i != NodeOperands; ++i) {
1101 if (Node->getOperand(i).isTargetOpcode()) {
1102 // Note that this case is redundant with the final else block, but we
1103 // include it because it is the most common and it makes the logic
1105 assert(Node->getOperand(i).getValueType() != MVT::Other &&
1106 Node->getOperand(i).getValueType() != MVT::Flag &&
1107 "Chain and flag operands should occur at end of operand list!");
1109 // Get/emit the operand.
1110 unsigned VReg = getVR(Node->getOperand(i));
1111 MI->addRegOperand(VReg, MachineOperand::Use);
1113 // Verify that it is right.
1114 assert(MRegisterInfo::isVirtualRegister(VReg) && "Not a vreg?");
1115 assert(II.OpInfo[i+NumResults].RegClass &&
1116 "Don't have operand info for this instruction!");
1117 assert(RegMap->getRegClass(VReg) == II.OpInfo[i+NumResults].RegClass &&
1118 "Register class of operand and regclass of use don't agree!");
1119 } else if (ConstantSDNode *C =
1120 dyn_cast<ConstantSDNode>(Node->getOperand(i))) {
1121 MI->addZeroExtImm64Operand(C->getValue());
1122 } else if (RegisterSDNode*R =
1123 dyn_cast<RegisterSDNode>(Node->getOperand(i))) {
1124 MI->addRegOperand(R->getReg(), MachineOperand::Use);
1125 } else if (GlobalAddressSDNode *TGA =
1126 dyn_cast<GlobalAddressSDNode>(Node->getOperand(i))) {
1127 MI->addGlobalAddressOperand(TGA->getGlobal(), false, TGA->getOffset());
1128 } else if (BasicBlockSDNode *BB =
1129 dyn_cast<BasicBlockSDNode>(Node->getOperand(i))) {
1130 MI->addMachineBasicBlockOperand(BB->getBasicBlock());
1131 } else if (FrameIndexSDNode *FI =
1132 dyn_cast<FrameIndexSDNode>(Node->getOperand(i))) {
1133 MI->addFrameIndexOperand(FI->getIndex());
1134 } else if (ConstantPoolSDNode *CP =
1135 dyn_cast<ConstantPoolSDNode>(Node->getOperand(i))) {
1136 unsigned Idx = ConstPool->getConstantPoolIndex(CP->get());
1137 MI->addConstantPoolIndexOperand(Idx);
1138 } else if (ExternalSymbolSDNode *ES =
1139 dyn_cast<ExternalSymbolSDNode>(Node->getOperand(i))) {
1140 MI->addExternalSymbolOperand(ES->getSymbol(), false);
1142 assert(Node->getOperand(i).getValueType() != MVT::Other &&
1143 Node->getOperand(i).getValueType() != MVT::Flag &&
1144 "Chain and flag operands should occur at end of operand list!");
1145 unsigned VReg = getVR(Node->getOperand(i));
1146 MI->addRegOperand(VReg, MachineOperand::Use);
1148 // Verify that it is right.
1149 assert(MRegisterInfo::isVirtualRegister(VReg) && "Not a vreg?");
1150 assert(II.OpInfo[i+NumResults].RegClass &&
1151 "Don't have operand info for this instruction!");
1152 assert(RegMap->getRegClass(VReg) == II.OpInfo[i+NumResults].RegClass &&
1153 "Register class of operand and regclass of use don't agree!");
1157 // Now that we have emitted all operands, emit this instruction itself.
1158 if ((II.Flags & M_USES_CUSTOM_DAG_SCHED_INSERTION) == 0) {
1159 BB->insert(BB->end(), MI);
1161 // Insert this instruction into the end of the basic block, potentially
1162 // taking some custom action.
1163 BB = DAG.getTargetLoweringInfo().InsertAtEndOfBasicBlock(MI, BB);
1166 switch (Node->getOpcode()) {
1169 assert(0 && "This target-independent node should have been selected!");
1170 case ISD::EntryToken: // fall thru
1171 case ISD::TokenFactor:
1173 case ISD::CopyToReg: {
1174 unsigned InReg = getVR(Node->getOperand(2));
1175 unsigned DestReg = cast<RegisterSDNode>(Node->getOperand(1))->getReg();
1176 if (InReg != DestReg) // Coallesced away the copy?
1177 MRI.copyRegToReg(*BB, BB->end(), DestReg, InReg,
1178 RegMap->getRegClass(InReg));
1181 case ISD::CopyFromReg: {
1182 unsigned SrcReg = cast<RegisterSDNode>(Node->getOperand(1))->getReg();
1183 if (MRegisterInfo::isVirtualRegister(SrcReg)) {
1184 VRBase = SrcReg; // Just use the input register directly!
1188 // If the node is only used by a CopyToReg and the dest reg is a vreg, use
1189 // the CopyToReg'd destination register instead of creating a new vreg.
1190 for (SDNode::use_iterator UI = Node->use_begin(), E = Node->use_end();
1193 if (Use->getOpcode() == ISD::CopyToReg &&
1194 Use->getOperand(2).Val == Node) {
1195 unsigned DestReg = cast<RegisterSDNode>(Use->getOperand(1))->getReg();
1196 if (MRegisterInfo::isVirtualRegister(DestReg)) {
1203 // Figure out the register class to create for the destreg.
1204 const TargetRegisterClass *TRC = 0;
1206 TRC = RegMap->getRegClass(VRBase);
1209 // Pick the register class of the right type that contains this physreg.
1210 for (MRegisterInfo::regclass_iterator I = MRI.regclass_begin(),
1211 E = MRI.regclass_end(); I != E; ++I)
1212 if ((*I)->hasType(Node->getValueType(0)) &&
1213 (*I)->contains(SrcReg)) {
1217 assert(TRC && "Couldn't find register class for reg copy!");
1219 // Create the reg, emit the copy.
1220 VRBase = RegMap->createVirtualRegister(TRC);
1222 MRI.copyRegToReg(*BB, BB->end(), VRBase, SrcReg, TRC);
1228 assert(NI->VRBase == 0 && "Node emitted out of order - early");
1229 NI->VRBase = VRBase;
1232 /// Schedule - Order nodes according to selected style.
1234 void SimpleSched::Schedule() {
1236 NodeCount = std::distance(DAG.allnodes_begin(), DAG.allnodes_end());
1237 // Test to see if scheduling should occur
1238 bool ShouldSchedule = NodeCount > 3 && ScheduleStyle != noScheduling;
1239 // Set up minimum info for scheduling
1241 // Construct node groups for flagged nodes
1244 // Don't waste time if is only entry and return
1245 if (ShouldSchedule) {
1246 // Get latency and resource requirements
1247 GatherSchedulingInfo();
1248 } else if (HasGroups) {
1249 // Make sure all the groups have dominators
1250 FakeGroupDominators();
1253 // Breadth first walk of DAG
1257 static unsigned Count = 0;
1259 for (unsigned i = 0, N = Ordering.size(); i < N; i++) {
1260 NodeInfo *NI = Ordering[i];
1265 // Don't waste time if is only entry and return
1266 if (ShouldSchedule) {
1267 // Push back long instructions and critical path
1270 // Pack instructions to maximize resource utilization
1274 DEBUG(printChanges(Count));
1276 // Emit in scheduled order
1280 /// printChanges - Hilight changes in order caused by scheduling.
1282 void SimpleSched::printChanges(unsigned Index) {
1284 // Get the ordered node count
1285 unsigned N = Ordering.size();
1286 // Determine if any changes
1288 for (; i < N; i++) {
1289 NodeInfo *NI = Ordering[i];
1290 if (NI->Preorder != i) break;
1294 std::cerr << Index << ". New Ordering\n";
1296 for (i = 0; i < N; i++) {
1297 NodeInfo *NI = Ordering[i];
1298 std::cerr << " " << NI->Preorder << ". ";
1299 printSI(std::cerr, NI);
1301 if (NI->isGroupDominator()) {
1302 NodeGroup *Group = NI->Group;
1303 for (NIIterator NII = Group->group_begin(), E = Group->group_end();
1306 printSI(std::cerr, *NII);
1312 std::cerr << Index << ". No Changes\n";
1317 /// printSI - Print schedule info.
1319 void SimpleSched::printSI(std::ostream &O, NodeInfo *NI) const {
1321 SDNode *Node = NI->Node;
1323 << std::hex << Node << std::dec
1324 << ", Lat=" << NI->Latency
1325 << ", Slot=" << NI->Slot
1326 << ", ARITY=(" << Node->getNumOperands() << ","
1327 << Node->getNumValues() << ")"
1328 << " " << Node->getOperationName(&DAG);
1329 if (isFlagDefiner(Node)) O << "<#";
1330 if (isFlagUser(Node)) O << ">#";
1334 /// print - Print ordering to specified output stream.
1336 void SimpleSched::print(std::ostream &O) const {
1338 using namespace std;
1340 for (unsigned i = 0, N = Ordering.size(); i < N; i++) {
1341 NodeInfo *NI = Ordering[i];
1344 if (NI->isGroupDominator()) {
1345 NodeGroup *Group = NI->Group;
1346 for (NIIterator NII = Group->group_begin(), E = Group->group_end();
1357 /// dump - Print ordering to std::cerr.
1359 void SimpleSched::dump() const {
1362 //===----------------------------------------------------------------------===//
1365 //===----------------------------------------------------------------------===//
1366 /// ScheduleAndEmitDAG - Pick a safe ordering and emit instructions for each
1367 /// target node in the graph.
1368 void SelectionDAGISel::ScheduleAndEmitDAG(SelectionDAG &SD) {
1369 if (ViewDAGs) SD.viewGraph();
1370 BB = SimpleSched(SD, BB).Run();