1 //===---- ScheduleDAG.cpp - Implement the ScheduleDAG class ---------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements a simple two pass scheduler. The first pass attempts to push
11 // backward any lengthy instructions and critical paths. The second pass packs
12 // instructions into semi-optimal time slots.
14 //===----------------------------------------------------------------------===//
16 #define DEBUG_TYPE "pre-RA-sched"
17 #include "llvm/Constants.h"
18 #include "llvm/Type.h"
19 #include "llvm/CodeGen/ScheduleDAG.h"
20 #include "llvm/CodeGen/MachineConstantPool.h"
21 #include "llvm/CodeGen/MachineFunction.h"
22 #include "llvm/CodeGen/MachineInstrBuilder.h"
23 #include "llvm/CodeGen/MachineRegisterInfo.h"
24 #include "llvm/Target/TargetData.h"
25 #include "llvm/Target/TargetMachine.h"
26 #include "llvm/Target/TargetInstrInfo.h"
27 #include "llvm/Target/TargetLowering.h"
28 #include "llvm/ADT/Statistic.h"
29 #include "llvm/Support/CommandLine.h"
30 #include "llvm/Support/Debug.h"
31 #include "llvm/Support/MathExtras.h"
34 STATISTIC(NumCommutes, "Number of instructions commuted");
38 SchedLiveInCopies("schedule-livein-copies",
39 cl::desc("Schedule copies of livein registers"),
43 ScheduleDAG::ScheduleDAG(SelectionDAG &dag, MachineBasicBlock *bb,
44 const TargetMachine &tm)
45 : DAG(dag), BB(bb), TM(tm), MRI(BB->getParent()->getRegInfo()) {
46 TII = TM.getInstrInfo();
47 MF = &DAG.getMachineFunction();
48 TRI = TM.getRegisterInfo();
49 TLI = &DAG.getTargetLoweringInfo();
50 ConstPool = BB->getParent()->getConstantPool();
53 /// CheckForPhysRegDependency - Check if the dependency between def and use of
54 /// a specified operand is a physical register dependency. If so, returns the
55 /// register and the cost of copying the register.
56 static void CheckForPhysRegDependency(SDNode *Def, SDNode *Use, unsigned Op,
57 const TargetRegisterInfo *TRI,
58 const TargetInstrInfo *TII,
59 unsigned &PhysReg, int &Cost) {
60 if (Op != 2 || Use->getOpcode() != ISD::CopyToReg)
63 unsigned Reg = cast<RegisterSDNode>(Use->getOperand(1))->getReg();
64 if (TargetRegisterInfo::isVirtualRegister(Reg))
67 unsigned ResNo = Use->getOperand(2).ResNo;
68 if (Def->isTargetOpcode()) {
69 const TargetInstrDesc &II = TII->get(Def->getTargetOpcode());
70 if (ResNo >= II.getNumDefs() &&
71 II.ImplicitDefs[ResNo - II.getNumDefs()] == Reg) {
73 const TargetRegisterClass *RC =
74 TRI->getPhysicalRegisterRegClass(Reg, Def->getValueType(ResNo));
75 Cost = RC->getCopyCost();
80 SUnit *ScheduleDAG::Clone(SUnit *Old) {
81 SUnit *SU = NewSUnit(Old->Node);
82 SU->FlaggedNodes = Old->FlaggedNodes;
83 SU->InstanceNo = SUnitMap[Old->Node].size();
84 SU->Latency = Old->Latency;
85 SU->isTwoAddress = Old->isTwoAddress;
86 SU->isCommutable = Old->isCommutable;
87 SU->hasPhysRegDefs = Old->hasPhysRegDefs;
88 SUnitMap[Old->Node].push_back(SU);
93 /// BuildSchedUnits - Build SUnits from the selection dag that we are input.
94 /// This SUnit graph is similar to the SelectionDAG, but represents flagged
95 /// together nodes with a single SUnit.
96 void ScheduleDAG::BuildSchedUnits() {
97 // Reserve entries in the vector for each of the SUnits we are creating. This
98 // ensure that reallocation of the vector won't happen, so SUnit*'s won't get
100 SUnits.reserve(std::distance(DAG.allnodes_begin(), DAG.allnodes_end()));
102 for (SelectionDAG::allnodes_iterator NI = DAG.allnodes_begin(),
103 E = DAG.allnodes_end(); NI != E; ++NI) {
104 if (isPassiveNode(NI)) // Leaf node, e.g. a TargetImmediate.
107 // If this node has already been processed, stop now.
108 if (SUnitMap[NI].size()) continue;
110 SUnit *NodeSUnit = NewSUnit(NI);
112 // See if anything is flagged to this node, if so, add them to flagged
113 // nodes. Nodes can have at most one flag input and one flag output. Flags
114 // are required the be the last operand and result of a node.
116 // Scan up, adding flagged preds to FlaggedNodes.
118 if (N->getNumOperands() &&
119 N->getOperand(N->getNumOperands()-1).getValueType() == MVT::Flag) {
121 N = N->getOperand(N->getNumOperands()-1).Val;
122 NodeSUnit->FlaggedNodes.push_back(N);
123 SUnitMap[N].push_back(NodeSUnit);
124 } while (N->getNumOperands() &&
125 N->getOperand(N->getNumOperands()-1).getValueType()== MVT::Flag);
126 std::reverse(NodeSUnit->FlaggedNodes.begin(),
127 NodeSUnit->FlaggedNodes.end());
130 // Scan down, adding this node and any flagged succs to FlaggedNodes if they
131 // have a user of the flag operand.
133 while (N->getValueType(N->getNumValues()-1) == MVT::Flag) {
134 SDOperand FlagVal(N, N->getNumValues()-1);
136 // There are either zero or one users of the Flag result.
137 bool HasFlagUse = false;
138 for (SDNode::use_iterator UI = N->use_begin(), E = N->use_end();
140 if (FlagVal.isOperandOf(*UI)) {
142 NodeSUnit->FlaggedNodes.push_back(N);
143 SUnitMap[N].push_back(NodeSUnit);
147 if (!HasFlagUse) break;
150 // Now all flagged nodes are in FlaggedNodes and N is the bottom-most node.
153 SUnitMap[N].push_back(NodeSUnit);
155 ComputeLatency(NodeSUnit);
158 // Pass 2: add the preds, succs, etc.
159 for (unsigned su = 0, e = SUnits.size(); su != e; ++su) {
160 SUnit *SU = &SUnits[su];
161 SDNode *MainNode = SU->Node;
163 if (MainNode->isTargetOpcode()) {
164 unsigned Opc = MainNode->getTargetOpcode();
165 const TargetInstrDesc &TID = TII->get(Opc);
166 for (unsigned i = 0; i != TID.getNumOperands(); ++i) {
167 if (TID.getOperandConstraint(i, TOI::TIED_TO) != -1) {
168 SU->isTwoAddress = true;
172 if (TID.isCommutable())
173 SU->isCommutable = true;
176 // Find all predecessors and successors of the group.
177 // Temporarily add N to make code simpler.
178 SU->FlaggedNodes.push_back(MainNode);
180 for (unsigned n = 0, e = SU->FlaggedNodes.size(); n != e; ++n) {
181 SDNode *N = SU->FlaggedNodes[n];
182 if (N->isTargetOpcode() &&
183 TII->get(N->getTargetOpcode()).getImplicitDefs() &&
184 CountResults(N) > TII->get(N->getTargetOpcode()).getNumDefs())
185 SU->hasPhysRegDefs = true;
187 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
188 SDNode *OpN = N->getOperand(i).Val;
189 if (isPassiveNode(OpN)) continue; // Not scheduled.
190 SUnit *OpSU = SUnitMap[OpN].front();
191 assert(OpSU && "Node has no SUnit!");
192 if (OpSU == SU) continue; // In the same group.
194 MVT::ValueType OpVT = N->getOperand(i).getValueType();
195 assert(OpVT != MVT::Flag && "Flagged nodes should be in same sunit!");
196 bool isChain = OpVT == MVT::Other;
198 unsigned PhysReg = 0;
200 // Determine if this is a physical register dependency.
201 CheckForPhysRegDependency(OpN, N, i, TRI, TII, PhysReg, Cost);
202 SU->addPred(OpSU, isChain, false, PhysReg, Cost);
206 // Remove MainNode from FlaggedNodes again.
207 SU->FlaggedNodes.pop_back();
213 void ScheduleDAG::ComputeLatency(SUnit *SU) {
214 const InstrItineraryData &InstrItins = TM.getInstrItineraryData();
216 // Compute the latency for the node. We use the sum of the latencies for
217 // all nodes flagged together into this SUnit.
218 if (InstrItins.isEmpty()) {
219 // No latency information.
223 if (SU->Node->isTargetOpcode()) {
224 unsigned SchedClass =
225 TII->get(SU->Node->getTargetOpcode()).getSchedClass();
226 const InstrStage *S = InstrItins.begin(SchedClass);
227 const InstrStage *E = InstrItins.end(SchedClass);
229 SU->Latency += S->Cycles;
231 for (unsigned i = 0, e = SU->FlaggedNodes.size(); i != e; ++i) {
232 SDNode *FNode = SU->FlaggedNodes[i];
233 if (FNode->isTargetOpcode()) {
234 unsigned SchedClass =TII->get(FNode->getTargetOpcode()).getSchedClass();
235 const InstrStage *S = InstrItins.begin(SchedClass);
236 const InstrStage *E = InstrItins.end(SchedClass);
238 SU->Latency += S->Cycles;
244 /// CalculateDepths - compute depths using algorithms for the longest
246 void ScheduleDAG::CalculateDepths() {
247 unsigned DAGSize = SUnits.size();
248 std::vector<unsigned> InDegree(DAGSize);
249 std::vector<SUnit*> WorkList;
250 WorkList.reserve(DAGSize);
252 // Initialize the data structures
253 for (unsigned i = 0, e = DAGSize; i != e; ++i) {
254 SUnit *SU = &SUnits[i];
255 int NodeNum = SU->NodeNum;
256 unsigned Degree = SU->Preds.size();
257 InDegree[NodeNum] = Degree;
260 // Is it a node without dependencies?
262 assert(SU->Preds.empty() && "SUnit should have no predecessors");
263 // Collect leaf nodes
264 WorkList.push_back(SU);
268 // Process nodes in the topological order
269 while (!WorkList.empty()) {
270 SUnit *SU = WorkList.back();
272 unsigned &SUDepth = SU->Depth;
274 // Use dynamic programming:
275 // When current node is being processed, all of its dependencies
276 // are already processed.
277 // So, just iterate over all predecessors and take the longest path
278 for (SUnit::const_pred_iterator I = SU->Preds.begin(), E = SU->Preds.end();
280 unsigned PredDepth = I->Dep->Depth;
281 if (PredDepth+1 > SUDepth) {
282 SUDepth = PredDepth + 1;
286 // Update InDegrees of all nodes depending on current SUnit
287 for (SUnit::const_succ_iterator I = SU->Succs.begin(), E = SU->Succs.end();
290 if (!--InDegree[SU->NodeNum])
291 // If all dependencies of the node are processed already,
292 // then the longest path for the node can be computed now
293 WorkList.push_back(SU);
298 /// CalculateHeights - compute heights using algorithms for the longest
300 void ScheduleDAG::CalculateHeights() {
301 unsigned DAGSize = SUnits.size();
302 std::vector<unsigned> InDegree(DAGSize);
303 std::vector<SUnit*> WorkList;
304 WorkList.reserve(DAGSize);
306 // Initialize the data structures
307 for (unsigned i = 0, e = DAGSize; i != e; ++i) {
308 SUnit *SU = &SUnits[i];
309 int NodeNum = SU->NodeNum;
310 unsigned Degree = SU->Succs.size();
311 InDegree[NodeNum] = Degree;
314 // Is it a node without dependencies?
316 assert(SU->Succs.empty() && "Something wrong");
317 assert(WorkList.empty() && "Should be empty");
318 // Collect leaf nodes
319 WorkList.push_back(SU);
323 // Process nodes in the topological order
324 while (!WorkList.empty()) {
325 SUnit *SU = WorkList.back();
327 unsigned &SUHeight = SU->Height;
329 // Use dynamic programming:
330 // When current node is being processed, all of its dependencies
331 // are already processed.
332 // So, just iterate over all successors and take the longest path
333 for (SUnit::const_succ_iterator I = SU->Succs.begin(), E = SU->Succs.end();
335 unsigned SuccHeight = I->Dep->Height;
336 if (SuccHeight+1 > SUHeight) {
337 SUHeight = SuccHeight + 1;
341 // Update InDegrees of all nodes depending on current SUnit
342 for (SUnit::const_pred_iterator I = SU->Preds.begin(), E = SU->Preds.end();
345 if (!--InDegree[SU->NodeNum])
346 // If all dependencies of the node are processed already,
347 // then the longest path for the node can be computed now
348 WorkList.push_back(SU);
353 /// CountResults - The results of target nodes have register or immediate
354 /// operands first, then an optional chain, and optional flag operands (which do
355 /// not go into the resulting MachineInstr).
356 unsigned ScheduleDAG::CountResults(SDNode *Node) {
357 unsigned N = Node->getNumValues();
358 while (N && Node->getValueType(N - 1) == MVT::Flag)
360 if (N && Node->getValueType(N - 1) == MVT::Other)
361 --N; // Skip over chain result.
365 /// CountOperands - The inputs to target nodes have any actual inputs first,
366 /// followed by special operands that describe memory references, then an
367 /// optional chain operand, then flag operands. Compute the number of
368 /// actual operands that will go into the resulting MachineInstr.
369 unsigned ScheduleDAG::CountOperands(SDNode *Node) {
370 unsigned N = ComputeMemOperandsEnd(Node);
371 while (N && isa<MemOperandSDNode>(Node->getOperand(N - 1).Val))
372 --N; // Ignore MemOperand nodes
376 /// ComputeMemOperandsEnd - Find the index one past the last MemOperandSDNode
378 unsigned ScheduleDAG::ComputeMemOperandsEnd(SDNode *Node) {
379 unsigned N = Node->getNumOperands();
380 while (N && Node->getOperand(N - 1).getValueType() == MVT::Flag)
382 if (N && Node->getOperand(N - 1).getValueType() == MVT::Other)
383 --N; // Ignore chain if it exists.
387 static const TargetRegisterClass *getInstrOperandRegClass(
388 const TargetRegisterInfo *TRI,
389 const TargetInstrInfo *TII,
390 const TargetInstrDesc &II,
392 if (Op >= II.getNumOperands()) {
393 assert(II.isVariadic() && "Invalid operand # of instruction");
396 if (II.OpInfo[Op].isLookupPtrRegClass())
397 return TII->getPointerRegClass();
398 return TRI->getRegClass(II.OpInfo[Op].RegClass);
401 void ScheduleDAG::EmitCopyFromReg(SDNode *Node, unsigned ResNo,
402 unsigned InstanceNo, unsigned SrcReg,
403 DenseMap<SDOperand, unsigned> &VRBaseMap) {
405 if (TargetRegisterInfo::isVirtualRegister(SrcReg)) {
406 // Just use the input register directly!
408 VRBaseMap.erase(SDOperand(Node, ResNo));
409 bool isNew = VRBaseMap.insert(std::make_pair(SDOperand(Node,ResNo),SrcReg));
410 assert(isNew && "Node emitted out of order - early");
414 // If the node is only used by a CopyToReg and the dest reg is a vreg, use
415 // the CopyToReg'd destination register instead of creating a new vreg.
416 bool MatchReg = true;
417 for (SDNode::use_iterator UI = Node->use_begin(), E = Node->use_end();
421 if (Use->getOpcode() == ISD::CopyToReg &&
422 Use->getOperand(2).Val == Node &&
423 Use->getOperand(2).ResNo == ResNo) {
424 unsigned DestReg = cast<RegisterSDNode>(Use->getOperand(1))->getReg();
425 if (TargetRegisterInfo::isVirtualRegister(DestReg)) {
428 } else if (DestReg != SrcReg)
431 for (unsigned i = 0, e = Use->getNumOperands(); i != e; ++i) {
432 SDOperand Op = Use->getOperand(i);
433 if (Op.Val != Node || Op.ResNo != ResNo)
435 MVT::ValueType VT = Node->getValueType(Op.ResNo);
436 if (VT != MVT::Other && VT != MVT::Flag)
445 const TargetRegisterClass *SrcRC = 0, *DstRC = 0;
446 SrcRC = TRI->getPhysicalRegisterRegClass(SrcReg, Node->getValueType(ResNo));
448 // Figure out the register class to create for the destreg.
450 DstRC = MRI.getRegClass(VRBase);
452 DstRC = TLI->getRegClassFor(Node->getValueType(ResNo));
455 // If all uses are reading from the src physical register and copying the
456 // register is either impossible or very expensive, then don't create a copy.
457 if (MatchReg && SrcRC->getCopyCost() < 0) {
460 // Create the reg, emit the copy.
461 VRBase = MRI.createVirtualRegister(DstRC);
462 TII->copyRegToReg(*BB, BB->end(), VRBase, SrcReg, DstRC, SrcRC);
466 VRBaseMap.erase(SDOperand(Node, ResNo));
467 bool isNew = VRBaseMap.insert(std::make_pair(SDOperand(Node,ResNo), VRBase));
468 assert(isNew && "Node emitted out of order - early");
471 /// getDstOfCopyToRegUse - If the only use of the specified result number of
472 /// node is a CopyToReg, return its destination register. Return 0 otherwise.
473 unsigned ScheduleDAG::getDstOfOnlyCopyToRegUse(SDNode *Node,
474 unsigned ResNo) const {
475 if (!Node->hasOneUse())
478 SDNode *Use = *Node->use_begin();
479 if (Use->getOpcode() == ISD::CopyToReg &&
480 Use->getOperand(2).Val == Node &&
481 Use->getOperand(2).ResNo == ResNo) {
482 unsigned Reg = cast<RegisterSDNode>(Use->getOperand(1))->getReg();
483 if (TargetRegisterInfo::isVirtualRegister(Reg))
489 void ScheduleDAG::CreateVirtualRegisters(SDNode *Node, MachineInstr *MI,
490 const TargetInstrDesc &II,
491 DenseMap<SDOperand, unsigned> &VRBaseMap) {
492 assert(Node->getTargetOpcode() != TargetInstrInfo::IMPLICIT_DEF &&
493 "IMPLICIT_DEF should have been handled as a special case elsewhere!");
495 for (unsigned i = 0; i < II.getNumDefs(); ++i) {
496 // If the specific node value is only used by a CopyToReg and the dest reg
497 // is a vreg, use the CopyToReg'd destination register instead of creating
500 for (SDNode::use_iterator UI = Node->use_begin(), E = Node->use_end();
503 if (Use->getOpcode() == ISD::CopyToReg &&
504 Use->getOperand(2).Val == Node &&
505 Use->getOperand(2).ResNo == i) {
506 unsigned Reg = cast<RegisterSDNode>(Use->getOperand(1))->getReg();
507 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
509 MI->addOperand(MachineOperand::CreateReg(Reg, true));
515 // Create the result registers for this node and add the result regs to
516 // the machine instruction.
518 const TargetRegisterClass *RC = getInstrOperandRegClass(TRI, TII, II, i);
519 assert(RC && "Isn't a register operand!");
520 VRBase = MRI.createVirtualRegister(RC);
521 MI->addOperand(MachineOperand::CreateReg(VRBase, true));
524 bool isNew = VRBaseMap.insert(std::make_pair(SDOperand(Node,i), VRBase));
525 assert(isNew && "Node emitted out of order - early");
529 /// getVR - Return the virtual register corresponding to the specified result
530 /// of the specified node.
531 unsigned ScheduleDAG::getVR(SDOperand Op,
532 DenseMap<SDOperand, unsigned> &VRBaseMap) {
533 if (Op.isTargetOpcode() &&
534 Op.getTargetOpcode() == TargetInstrInfo::IMPLICIT_DEF) {
535 // Add an IMPLICIT_DEF instruction before every use.
536 unsigned VReg = getDstOfOnlyCopyToRegUse(Op.Val, Op.ResNo);
537 // IMPLICIT_DEF can produce any type of result so its TargetInstrDesc
538 // does not include operand register class info.
540 const TargetRegisterClass *RC = TLI->getRegClassFor(Op.getValueType());
541 VReg = MRI.createVirtualRegister(RC);
543 BuildMI(BB, TII->get(TargetInstrInfo::IMPLICIT_DEF), VReg);
547 DenseMap<SDOperand, unsigned>::iterator I = VRBaseMap.find(Op);
548 assert(I != VRBaseMap.end() && "Node emitted out of order - late");
553 /// AddOperand - Add the specified operand to the specified machine instr. II
554 /// specifies the instruction information for the node, and IIOpNum is the
555 /// operand number (in the II) that we are adding. IIOpNum and II are used for
557 void ScheduleDAG::AddOperand(MachineInstr *MI, SDOperand Op,
559 const TargetInstrDesc *II,
560 DenseMap<SDOperand, unsigned> &VRBaseMap) {
561 if (Op.isTargetOpcode()) {
562 // Note that this case is redundant with the final else block, but we
563 // include it because it is the most common and it makes the logic
565 assert(Op.getValueType() != MVT::Other &&
566 Op.getValueType() != MVT::Flag &&
567 "Chain and flag operands should occur at end of operand list!");
568 // Get/emit the operand.
569 unsigned VReg = getVR(Op, VRBaseMap);
570 const TargetInstrDesc &TID = MI->getDesc();
571 bool isOptDef = IIOpNum < TID.getNumOperands() &&
572 TID.OpInfo[IIOpNum].isOptionalDef();
573 MI->addOperand(MachineOperand::CreateReg(VReg, isOptDef));
575 // Verify that it is right.
576 assert(TargetRegisterInfo::isVirtualRegister(VReg) && "Not a vreg?");
579 // There may be no register class for this operand if it is a variadic
580 // argument (RC will be NULL in this case). In this case, we just assume
581 // the regclass is ok.
582 const TargetRegisterClass *RC =
583 getInstrOperandRegClass(TRI, TII, *II, IIOpNum);
584 assert((RC || II->isVariadic()) && "Expected reg class info!");
585 const TargetRegisterClass *VRC = MRI.getRegClass(VReg);
586 if (RC && VRC != RC) {
587 cerr << "Register class of operand and regclass of use don't agree!\n";
588 cerr << "Operand = " << IIOpNum << "\n";
589 cerr << "Op->Val = "; Op.Val->dump(&DAG); cerr << "\n";
590 cerr << "MI = "; MI->print(cerr);
591 cerr << "VReg = " << VReg << "\n";
592 cerr << "VReg RegClass size = " << VRC->getSize()
593 << ", align = " << VRC->getAlignment() << "\n";
594 cerr << "Expected RegClass size = " << RC->getSize()
595 << ", align = " << RC->getAlignment() << "\n";
596 cerr << "Fatal error, aborting.\n";
601 } else if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
602 MI->addOperand(MachineOperand::CreateImm(C->getValue()));
603 } else if (ConstantFPSDNode *F = dyn_cast<ConstantFPSDNode>(Op)) {
604 const Type *FType = MVT::getTypeForValueType(Op.getValueType());
605 ConstantFP *CFP = ConstantFP::get(FType, F->getValueAPF());
606 MI->addOperand(MachineOperand::CreateFPImm(CFP));
607 } else if (RegisterSDNode *R = dyn_cast<RegisterSDNode>(Op)) {
608 MI->addOperand(MachineOperand::CreateReg(R->getReg(), false));
609 } else if (GlobalAddressSDNode *TGA = dyn_cast<GlobalAddressSDNode>(Op)) {
610 MI->addOperand(MachineOperand::CreateGA(TGA->getGlobal(),TGA->getOffset()));
611 } else if (BasicBlockSDNode *BB = dyn_cast<BasicBlockSDNode>(Op)) {
612 MI->addOperand(MachineOperand::CreateMBB(BB->getBasicBlock()));
613 } else if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(Op)) {
614 MI->addOperand(MachineOperand::CreateFI(FI->getIndex()));
615 } else if (JumpTableSDNode *JT = dyn_cast<JumpTableSDNode>(Op)) {
616 MI->addOperand(MachineOperand::CreateJTI(JT->getIndex()));
617 } else if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Op)) {
618 int Offset = CP->getOffset();
619 unsigned Align = CP->getAlignment();
620 const Type *Type = CP->getType();
621 // MachineConstantPool wants an explicit alignment.
623 Align = TM.getTargetData()->getPreferredTypeAlignmentShift(Type);
625 // Alignment of vector types. FIXME!
626 Align = TM.getTargetData()->getABITypeSize(Type);
627 Align = Log2_64(Align);
632 if (CP->isMachineConstantPoolEntry())
633 Idx = ConstPool->getConstantPoolIndex(CP->getMachineCPVal(), Align);
635 Idx = ConstPool->getConstantPoolIndex(CP->getConstVal(), Align);
636 MI->addOperand(MachineOperand::CreateCPI(Idx, Offset));
637 } else if (ExternalSymbolSDNode *ES = dyn_cast<ExternalSymbolSDNode>(Op)) {
638 MI->addOperand(MachineOperand::CreateES(ES->getSymbol()));
640 assert(Op.getValueType() != MVT::Other &&
641 Op.getValueType() != MVT::Flag &&
642 "Chain and flag operands should occur at end of operand list!");
643 unsigned VReg = getVR(Op, VRBaseMap);
644 MI->addOperand(MachineOperand::CreateReg(VReg, false));
646 // Verify that it is right. Note that the reg class of the physreg and the
647 // vreg don't necessarily need to match, but the target copy insertion has
648 // to be able to handle it. This handles things like copies from ST(0) to
649 // an FP vreg on x86.
650 assert(TargetRegisterInfo::isVirtualRegister(VReg) && "Not a vreg?");
651 if (II && !II->isVariadic()) {
652 assert(getInstrOperandRegClass(TRI, TII, *II, IIOpNum) &&
653 "Don't have operand info for this instruction!");
659 void ScheduleDAG::AddMemOperand(MachineInstr *MI, const MemOperand &MO) {
660 MI->addMemOperand(MO);
663 // Returns the Register Class of a subregister
664 static const TargetRegisterClass *getSubRegisterRegClass(
665 const TargetRegisterClass *TRC,
667 // Pick the register class of the subregister
668 TargetRegisterInfo::regclass_iterator I =
669 TRC->subregclasses_begin() + SubIdx-1;
670 assert(I < TRC->subregclasses_end() &&
671 "Invalid subregister index for register class");
675 static const TargetRegisterClass *getSuperregRegisterClass(
676 const TargetRegisterClass *TRC,
679 // Pick the register class of the superegister for this type
680 for (TargetRegisterInfo::regclass_iterator I = TRC->superregclasses_begin(),
681 E = TRC->superregclasses_end(); I != E; ++I)
682 if ((*I)->hasType(VT) && getSubRegisterRegClass(*I, SubIdx) == TRC)
684 assert(false && "Couldn't find the register class");
688 /// EmitSubregNode - Generate machine code for subreg nodes.
690 void ScheduleDAG::EmitSubregNode(SDNode *Node,
691 DenseMap<SDOperand, unsigned> &VRBaseMap) {
693 unsigned Opc = Node->getTargetOpcode();
695 // If the node is only used by a CopyToReg and the dest reg is a vreg, use
696 // the CopyToReg'd destination register instead of creating a new vreg.
697 for (SDNode::use_iterator UI = Node->use_begin(), E = Node->use_end();
700 if (Use->getOpcode() == ISD::CopyToReg &&
701 Use->getOperand(2).Val == Node) {
702 unsigned DestReg = cast<RegisterSDNode>(Use->getOperand(1))->getReg();
703 if (TargetRegisterInfo::isVirtualRegister(DestReg)) {
710 if (Opc == TargetInstrInfo::EXTRACT_SUBREG) {
711 unsigned SubIdx = cast<ConstantSDNode>(Node->getOperand(1))->getValue();
713 // Create the extract_subreg machine instruction.
714 MachineInstr *MI = BuildMI(TII->get(TargetInstrInfo::EXTRACT_SUBREG));
716 // Figure out the register class to create for the destreg.
717 unsigned VReg = getVR(Node->getOperand(0), VRBaseMap);
718 const TargetRegisterClass *TRC = MRI.getRegClass(VReg);
719 const TargetRegisterClass *SRC = getSubRegisterRegClass(TRC, SubIdx);
722 // Grab the destination register
723 const TargetRegisterClass *DRC = MRI.getRegClass(VRBase);
724 assert(SRC && DRC && SRC == DRC &&
725 "Source subregister and destination must have the same class");
728 assert(SRC && "Couldn't find source register class");
729 VRBase = MRI.createVirtualRegister(SRC);
732 // Add def, source, and subreg index
733 MI->addOperand(MachineOperand::CreateReg(VRBase, true));
734 AddOperand(MI, Node->getOperand(0), 0, 0, VRBaseMap);
735 MI->addOperand(MachineOperand::CreateImm(SubIdx));
737 } else if (Opc == TargetInstrInfo::INSERT_SUBREG ||
738 Opc == TargetInstrInfo::SUBREG_TO_REG) {
739 SDOperand N0 = Node->getOperand(0);
740 SDOperand N1 = Node->getOperand(1);
741 SDOperand N2 = Node->getOperand(2);
742 unsigned SubReg = getVR(N1, VRBaseMap);
743 unsigned SubIdx = cast<ConstantSDNode>(N2)->getValue();
746 // Figure out the register class to create for the destreg.
747 const TargetRegisterClass *TRC = 0;
749 TRC = MRI.getRegClass(VRBase);
751 TRC = getSuperregRegisterClass(MRI.getRegClass(SubReg), SubIdx,
752 Node->getValueType(0));
753 assert(TRC && "Couldn't determine register class for insert_subreg");
754 VRBase = MRI.createVirtualRegister(TRC); // Create the reg
757 // Create the insert_subreg or subreg_to_reg machine instruction.
758 MachineInstr *MI = BuildMI(TII->get(Opc));
759 MI->addOperand(MachineOperand::CreateReg(VRBase, true));
761 // If creating a subreg_to_reg, then the first input operand
762 // is an implicit value immediate, otherwise it's a register
763 if (Opc == TargetInstrInfo::SUBREG_TO_REG) {
764 const ConstantSDNode *SD = cast<ConstantSDNode>(N0);
765 MI->addOperand(MachineOperand::CreateImm(SD->getValue()));
767 AddOperand(MI, N0, 0, 0, VRBaseMap);
768 // Add the subregster being inserted
769 AddOperand(MI, N1, 0, 0, VRBaseMap);
770 MI->addOperand(MachineOperand::CreateImm(SubIdx));
773 assert(0 && "Node is not insert_subreg, extract_subreg, or subreg_to_reg");
775 bool isNew = VRBaseMap.insert(std::make_pair(SDOperand(Node,0), VRBase));
776 assert(isNew && "Node emitted out of order - early");
779 /// EmitNode - Generate machine code for an node and needed dependencies.
781 void ScheduleDAG::EmitNode(SDNode *Node, unsigned InstanceNo,
782 DenseMap<SDOperand, unsigned> &VRBaseMap) {
783 // If machine instruction
784 if (Node->isTargetOpcode()) {
785 unsigned Opc = Node->getTargetOpcode();
787 // Handle subreg insert/extract specially
788 if (Opc == TargetInstrInfo::EXTRACT_SUBREG ||
789 Opc == TargetInstrInfo::INSERT_SUBREG ||
790 Opc == TargetInstrInfo::SUBREG_TO_REG) {
791 EmitSubregNode(Node, VRBaseMap);
795 if (Opc == TargetInstrInfo::IMPLICIT_DEF)
796 // We want a unique VR for each IMPLICIT_DEF use.
799 const TargetInstrDesc &II = TII->get(Opc);
800 unsigned NumResults = CountResults(Node);
801 unsigned NodeOperands = CountOperands(Node);
802 unsigned MemOperandsEnd = ComputeMemOperandsEnd(Node);
803 unsigned NumMIOperands = NodeOperands + NumResults;
804 bool HasPhysRegOuts = (NumResults > II.getNumDefs()) &&
805 II.getImplicitDefs() != 0;
807 assert((II.getNumOperands() == NumMIOperands ||
808 HasPhysRegOuts || II.isVariadic()) &&
809 "#operands for dag node doesn't match .td file!");
812 // Create the new machine instruction.
813 MachineInstr *MI = BuildMI(II);
815 // Add result register values for things that are defined by this
818 CreateVirtualRegisters(Node, MI, II, VRBaseMap);
820 // Emit all of the actual operands of this instruction, adding them to the
821 // instruction as appropriate.
822 for (unsigned i = 0; i != NodeOperands; ++i)
823 AddOperand(MI, Node->getOperand(i), i+II.getNumDefs(), &II, VRBaseMap);
825 // Emit all of the memory operands of this instruction
826 for (unsigned i = NodeOperands; i != MemOperandsEnd; ++i)
827 AddMemOperand(MI, cast<MemOperandSDNode>(Node->getOperand(i))->MO);
829 // Commute node if it has been determined to be profitable.
830 if (CommuteSet.count(Node)) {
831 MachineInstr *NewMI = TII->commuteInstruction(MI);
833 DOUT << "Sched: COMMUTING FAILED!\n";
835 DOUT << "Sched: COMMUTED TO: " << *NewMI;
844 if (II.usesCustomDAGSchedInsertionHook())
845 // Insert this instruction into the basic block using a target
846 // specific inserter which may returns a new basic block.
847 BB = TLI->EmitInstrWithCustomInserter(MI, BB);
851 // Additional results must be an physical register def.
852 if (HasPhysRegOuts) {
853 for (unsigned i = II.getNumDefs(); i < NumResults; ++i) {
854 unsigned Reg = II.getImplicitDefs()[i - II.getNumDefs()];
855 if (Node->hasAnyUseOfValue(i))
856 EmitCopyFromReg(Node, i, InstanceNo, Reg, VRBaseMap);
860 switch (Node->getOpcode()) {
865 assert(0 && "This target-independent node should have been selected!");
866 case ISD::EntryToken: // fall thru
867 case ISD::TokenFactor:
872 case ISD::CopyToReg: {
874 SDOperand SrcVal = Node->getOperand(2);
875 if (RegisterSDNode *R = dyn_cast<RegisterSDNode>(SrcVal))
876 SrcReg = R->getReg();
878 SrcReg = getVR(SrcVal, VRBaseMap);
880 unsigned DestReg = cast<RegisterSDNode>(Node->getOperand(1))->getReg();
881 if (SrcReg == DestReg) // Coalesced away the copy? Ignore.
884 const TargetRegisterClass *SrcTRC = 0, *DstTRC = 0;
885 // Get the register classes of the src/dst.
886 if (TargetRegisterInfo::isVirtualRegister(SrcReg))
887 SrcTRC = MRI.getRegClass(SrcReg);
889 SrcTRC = TRI->getPhysicalRegisterRegClass(SrcReg,SrcVal.getValueType());
891 if (TargetRegisterInfo::isVirtualRegister(DestReg))
892 DstTRC = MRI.getRegClass(DestReg);
894 DstTRC = TRI->getPhysicalRegisterRegClass(DestReg,
895 Node->getOperand(1).getValueType());
896 TII->copyRegToReg(*BB, BB->end(), DestReg, SrcReg, DstTRC, SrcTRC);
899 case ISD::CopyFromReg: {
900 unsigned SrcReg = cast<RegisterSDNode>(Node->getOperand(1))->getReg();
901 EmitCopyFromReg(Node, 0, InstanceNo, SrcReg, VRBaseMap);
904 case ISD::INLINEASM: {
905 unsigned NumOps = Node->getNumOperands();
906 if (Node->getOperand(NumOps-1).getValueType() == MVT::Flag)
907 --NumOps; // Ignore the flag operand.
909 // Create the inline asm machine instruction.
910 MachineInstr *MI = BuildMI(TII->get(TargetInstrInfo::INLINEASM));
912 // Add the asm string as an external symbol operand.
914 cast<ExternalSymbolSDNode>(Node->getOperand(1))->getSymbol();
915 MI->addOperand(MachineOperand::CreateES(AsmStr));
917 // Add all of the operand registers to the instruction.
918 for (unsigned i = 2; i != NumOps;) {
919 unsigned Flags = cast<ConstantSDNode>(Node->getOperand(i))->getValue();
920 unsigned NumVals = Flags >> 3;
922 MI->addOperand(MachineOperand::CreateImm(Flags));
923 ++i; // Skip the ID value.
926 default: assert(0 && "Bad flags!");
927 case 1: // Use of register.
928 for (; NumVals; --NumVals, ++i) {
929 unsigned Reg = cast<RegisterSDNode>(Node->getOperand(i))->getReg();
930 MI->addOperand(MachineOperand::CreateReg(Reg, false));
933 case 2: // Def of register.
934 for (; NumVals; --NumVals, ++i) {
935 unsigned Reg = cast<RegisterSDNode>(Node->getOperand(i))->getReg();
936 MI->addOperand(MachineOperand::CreateReg(Reg, true));
939 case 3: { // Immediate.
940 for (; NumVals; --NumVals, ++i) {
941 if (ConstantSDNode *CS =
942 dyn_cast<ConstantSDNode>(Node->getOperand(i))) {
943 MI->addOperand(MachineOperand::CreateImm(CS->getValue()));
944 } else if (GlobalAddressSDNode *GA =
945 dyn_cast<GlobalAddressSDNode>(Node->getOperand(i))) {
946 MI->addOperand(MachineOperand::CreateGA(GA->getGlobal(),
949 BasicBlockSDNode *BB =cast<BasicBlockSDNode>(Node->getOperand(i));
950 MI->addOperand(MachineOperand::CreateMBB(BB->getBasicBlock()));
955 case 4: // Addressing mode.
956 // The addressing mode has been selected, just add all of the
957 // operands to the machine instruction.
958 for (; NumVals; --NumVals, ++i)
959 AddOperand(MI, Node->getOperand(i), 0, 0, VRBaseMap);
970 void ScheduleDAG::EmitNoop() {
971 TII->insertNoop(*BB, BB->end());
974 void ScheduleDAG::EmitCrossRCCopy(SUnit *SU,
975 DenseMap<SUnit*, unsigned> &VRBaseMap) {
976 for (SUnit::const_pred_iterator I = SU->Preds.begin(), E = SU->Preds.end();
978 if (I->isCtrl) continue; // ignore chain preds
980 // Copy to physical register.
981 DenseMap<SUnit*, unsigned>::iterator VRI = VRBaseMap.find(I->Dep);
982 assert(VRI != VRBaseMap.end() && "Node emitted out of order - late");
983 // Find the destination physical register.
985 for (SUnit::const_succ_iterator II = SU->Succs.begin(),
986 EE = SU->Succs.end(); II != EE; ++II) {
992 assert(I->Reg && "Unknown physical register!");
993 TII->copyRegToReg(*BB, BB->end(), Reg, VRI->second,
994 SU->CopyDstRC, SU->CopySrcRC);
996 // Copy from physical register.
997 assert(I->Reg && "Unknown physical register!");
998 unsigned VRBase = MRI.createVirtualRegister(SU->CopyDstRC);
999 bool isNew = VRBaseMap.insert(std::make_pair(SU, VRBase));
1000 assert(isNew && "Node emitted out of order - early");
1001 TII->copyRegToReg(*BB, BB->end(), VRBase, I->Reg,
1002 SU->CopyDstRC, SU->CopySrcRC);
1008 /// EmitLiveInCopy - Emit a copy for a live in physical register. If the
1009 /// physical register has only a single copy use, then coalesced the copy
1011 void ScheduleDAG::EmitLiveInCopy(MachineBasicBlock *MBB,
1012 MachineBasicBlock::iterator &InsertPos,
1013 unsigned VirtReg, unsigned PhysReg,
1014 const TargetRegisterClass *RC,
1015 DenseMap<MachineInstr*, unsigned> &CopyRegMap){
1016 unsigned NumUses = 0;
1017 MachineInstr *UseMI = NULL;
1018 for (MachineRegisterInfo::use_iterator UI = MRI.use_begin(VirtReg),
1019 UE = MRI.use_end(); UI != UE; ++UI) {
1025 // If the number of uses is not one, or the use is not a move instruction,
1026 // don't coalesce. Also, only coalesce away a virtual register to virtual
1028 bool Coalesced = false;
1029 unsigned SrcReg, DstReg;
1031 TII->isMoveInstr(*UseMI, SrcReg, DstReg) &&
1032 TargetRegisterInfo::isVirtualRegister(DstReg)) {
1037 // Now find an ideal location to insert the copy.
1038 MachineBasicBlock::iterator Pos = InsertPos;
1039 while (Pos != MBB->begin()) {
1040 MachineInstr *PrevMI = prior(Pos);
1041 DenseMap<MachineInstr*, unsigned>::iterator RI = CopyRegMap.find(PrevMI);
1042 // copyRegToReg might emit multiple instructions to do a copy.
1043 unsigned CopyDstReg = (RI == CopyRegMap.end()) ? 0 : RI->second;
1044 if (CopyDstReg && !TRI->regsOverlap(CopyDstReg, PhysReg))
1045 // This is what the BB looks like right now:
1050 // We want to insert "r1025 = mov r1". Inserting this copy below the
1051 // move to r1024 makes it impossible for that move to be coalesced.
1058 break; // Woot! Found a good location.
1062 TII->copyRegToReg(*MBB, Pos, VirtReg, PhysReg, RC, RC);
1063 CopyRegMap.insert(std::make_pair(prior(Pos), VirtReg));
1065 if (&*InsertPos == UseMI) ++InsertPos;
1070 /// EmitLiveInCopies - If this is the first basic block in the function,
1071 /// and if it has live ins that need to be copied into vregs, emit the
1072 /// copies into the top of the block.
1073 void ScheduleDAG::EmitLiveInCopies(MachineBasicBlock *MBB) {
1074 DenseMap<MachineInstr*, unsigned> CopyRegMap;
1075 MachineBasicBlock::iterator InsertPos = MBB->begin();
1076 for (MachineRegisterInfo::livein_iterator LI = MRI.livein_begin(),
1077 E = MRI.livein_end(); LI != E; ++LI)
1079 const TargetRegisterClass *RC = MRI.getRegClass(LI->second);
1080 EmitLiveInCopy(MBB, InsertPos, LI->second, LI->first, RC, CopyRegMap);
1084 /// EmitSchedule - Emit the machine code in scheduled order.
1085 void ScheduleDAG::EmitSchedule() {
1086 bool isEntryBB = &MF->front() == BB;
1088 if (isEntryBB && !SchedLiveInCopies) {
1089 // If this is the first basic block in the function, and if it has live ins
1090 // that need to be copied into vregs, emit the copies into the top of the
1091 // block before emitting the code for the block.
1092 for (MachineRegisterInfo::livein_iterator LI = MRI.livein_begin(),
1093 E = MRI.livein_end(); LI != E; ++LI)
1095 const TargetRegisterClass *RC = MRI.getRegClass(LI->second);
1096 TII->copyRegToReg(*MF->begin(), MF->begin()->end(), LI->second,
1101 // Finally, emit the code for all of the scheduled instructions.
1102 DenseMap<SDOperand, unsigned> VRBaseMap;
1103 DenseMap<SUnit*, unsigned> CopyVRBaseMap;
1104 for (unsigned i = 0, e = Sequence.size(); i != e; i++) {
1105 SUnit *SU = Sequence[i];
1107 // Null SUnit* is a noop.
1111 for (unsigned j = 0, ee = SU->FlaggedNodes.size(); j != ee; ++j)
1112 EmitNode(SU->FlaggedNodes[j], SU->InstanceNo, VRBaseMap);
1114 EmitCrossRCCopy(SU, CopyVRBaseMap);
1116 EmitNode(SU->Node, SU->InstanceNo, VRBaseMap);
1119 if (isEntryBB && SchedLiveInCopies)
1120 EmitLiveInCopies(MF->begin());
1123 /// dump - dump the schedule.
1124 void ScheduleDAG::dumpSchedule() const {
1125 for (unsigned i = 0, e = Sequence.size(); i != e; i++) {
1126 if (SUnit *SU = Sequence[i])
1129 cerr << "**** NOOP ****\n";
1134 /// Run - perform scheduling.
1136 MachineBasicBlock *ScheduleDAG::Run() {
1141 /// SUnit - Scheduling unit. It's an wrapper around either a single SDNode or
1142 /// a group of nodes flagged together.
1143 void SUnit::dump(const SelectionDAG *G) const {
1144 cerr << "SU(" << NodeNum << "): ";
1148 cerr << "CROSS RC COPY ";
1150 if (FlaggedNodes.size() != 0) {
1151 for (unsigned i = 0, e = FlaggedNodes.size(); i != e; i++) {
1153 FlaggedNodes[i]->dump(G);
1159 void SUnit::dumpAll(const SelectionDAG *G) const {
1162 cerr << " # preds left : " << NumPredsLeft << "\n";
1163 cerr << " # succs left : " << NumSuccsLeft << "\n";
1164 cerr << " Latency : " << Latency << "\n";
1165 cerr << " Depth : " << Depth << "\n";
1166 cerr << " Height : " << Height << "\n";
1168 if (Preds.size() != 0) {
1169 cerr << " Predecessors:\n";
1170 for (SUnit::const_succ_iterator I = Preds.begin(), E = Preds.end();
1176 cerr << I->Dep << " - SU(" << I->Dep->NodeNum << ")";
1182 if (Succs.size() != 0) {
1183 cerr << " Successors:\n";
1184 for (SUnit::const_succ_iterator I = Succs.begin(), E = Succs.end();
1190 cerr << I->Dep << " - SU(" << I->Dep->NodeNum << ")";