1 //===------- LegalizeVectorTypes.cpp - Legalization of vector types -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file performs vector type splitting and scalarization for LegalizeTypes.
11 // Scalarization is the act of changing a computation in an illegal one-element
12 // vector type to be a computation in its scalar element type. For example,
13 // implementing <1 x f32> arithmetic in a scalar f32 register. This is needed
14 // as a base case when scalarizing vector arithmetic like <4 x f32>, which
15 // eventually decomposes to scalars if the target doesn't support v4f32 or v2f32
17 // Splitting is the act of changing a computation in an invalid vector type to
18 // be a computation in two vectors of half the size. For example, implementing
19 // <128 x f32> operations in terms of two <64 x f32> operations.
21 //===----------------------------------------------------------------------===//
23 #include "LegalizeTypes.h"
24 #include "llvm/IR/DataLayout.h"
25 #include "llvm/Support/ErrorHandling.h"
26 #include "llvm/Support/raw_ostream.h"
29 #define DEBUG_TYPE "legalize-types"
31 //===----------------------------------------------------------------------===//
32 // Result Vector Scalarization: <1 x ty> -> ty.
33 //===----------------------------------------------------------------------===//
35 void DAGTypeLegalizer::ScalarizeVectorResult(SDNode *N, unsigned ResNo) {
36 DEBUG(dbgs() << "Scalarize node result " << ResNo << ": ";
39 SDValue R = SDValue();
41 switch (N->getOpcode()) {
44 dbgs() << "ScalarizeVectorResult #" << ResNo << ": ";
48 report_fatal_error("Do not know how to scalarize the result of this "
51 case ISD::MERGE_VALUES: R = ScalarizeVecRes_MERGE_VALUES(N, ResNo);break;
52 case ISD::BITCAST: R = ScalarizeVecRes_BITCAST(N); break;
53 case ISD::BUILD_VECTOR: R = ScalarizeVecRes_BUILD_VECTOR(N); break;
54 case ISD::CONVERT_RNDSAT: R = ScalarizeVecRes_CONVERT_RNDSAT(N); break;
55 case ISD::EXTRACT_SUBVECTOR: R = ScalarizeVecRes_EXTRACT_SUBVECTOR(N); break;
56 case ISD::FP_ROUND: R = ScalarizeVecRes_FP_ROUND(N); break;
57 case ISD::FP_ROUND_INREG: R = ScalarizeVecRes_InregOp(N); break;
58 case ISD::FPOWI: R = ScalarizeVecRes_FPOWI(N); break;
59 case ISD::INSERT_VECTOR_ELT: R = ScalarizeVecRes_INSERT_VECTOR_ELT(N); break;
60 case ISD::LOAD: R = ScalarizeVecRes_LOAD(cast<LoadSDNode>(N));break;
61 case ISD::SCALAR_TO_VECTOR: R = ScalarizeVecRes_SCALAR_TO_VECTOR(N); break;
62 case ISD::SIGN_EXTEND_INREG: R = ScalarizeVecRes_InregOp(N); break;
63 case ISD::VSELECT: R = ScalarizeVecRes_VSELECT(N); break;
64 case ISD::SELECT: R = ScalarizeVecRes_SELECT(N); break;
65 case ISD::SELECT_CC: R = ScalarizeVecRes_SELECT_CC(N); break;
66 case ISD::SETCC: R = ScalarizeVecRes_SETCC(N); break;
67 case ISD::UNDEF: R = ScalarizeVecRes_UNDEF(N); break;
68 case ISD::VECTOR_SHUFFLE: R = ScalarizeVecRes_VECTOR_SHUFFLE(N); break;
72 case ISD::CTLZ_ZERO_UNDEF:
75 case ISD::CTTZ_ZERO_UNDEF:
95 case ISD::SIGN_EXTEND:
99 case ISD::ZERO_EXTEND:
100 R = ScalarizeVecRes_UnaryOp(N);
126 R = ScalarizeVecRes_BinOp(N);
129 R = ScalarizeVecRes_TernaryOp(N);
133 // If R is null, the sub-method took care of registering the result.
135 SetScalarizedVector(SDValue(N, ResNo), R);
138 SDValue DAGTypeLegalizer::ScalarizeVecRes_BinOp(SDNode *N) {
139 SDValue LHS = GetScalarizedVector(N->getOperand(0));
140 SDValue RHS = GetScalarizedVector(N->getOperand(1));
141 return DAG.getNode(N->getOpcode(), SDLoc(N),
142 LHS.getValueType(), LHS, RHS);
145 SDValue DAGTypeLegalizer::ScalarizeVecRes_TernaryOp(SDNode *N) {
146 SDValue Op0 = GetScalarizedVector(N->getOperand(0));
147 SDValue Op1 = GetScalarizedVector(N->getOperand(1));
148 SDValue Op2 = GetScalarizedVector(N->getOperand(2));
149 return DAG.getNode(N->getOpcode(), SDLoc(N),
150 Op0.getValueType(), Op0, Op1, Op2);
153 SDValue DAGTypeLegalizer::ScalarizeVecRes_MERGE_VALUES(SDNode *N,
155 SDValue Op = DisintegrateMERGE_VALUES(N, ResNo);
156 return GetScalarizedVector(Op);
159 SDValue DAGTypeLegalizer::ScalarizeVecRes_BITCAST(SDNode *N) {
160 EVT NewVT = N->getValueType(0).getVectorElementType();
161 return DAG.getNode(ISD::BITCAST, SDLoc(N),
162 NewVT, N->getOperand(0));
165 SDValue DAGTypeLegalizer::ScalarizeVecRes_BUILD_VECTOR(SDNode *N) {
166 EVT EltVT = N->getValueType(0).getVectorElementType();
167 SDValue InOp = N->getOperand(0);
168 // The BUILD_VECTOR operands may be of wider element types and
169 // we may need to truncate them back to the requested return type.
170 if (EltVT.isInteger())
171 return DAG.getNode(ISD::TRUNCATE, SDLoc(N), EltVT, InOp);
175 SDValue DAGTypeLegalizer::ScalarizeVecRes_CONVERT_RNDSAT(SDNode *N) {
176 EVT NewVT = N->getValueType(0).getVectorElementType();
177 SDValue Op0 = GetScalarizedVector(N->getOperand(0));
178 return DAG.getConvertRndSat(NewVT, SDLoc(N),
179 Op0, DAG.getValueType(NewVT),
180 DAG.getValueType(Op0.getValueType()),
183 cast<CvtRndSatSDNode>(N)->getCvtCode());
186 SDValue DAGTypeLegalizer::ScalarizeVecRes_EXTRACT_SUBVECTOR(SDNode *N) {
187 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SDLoc(N),
188 N->getValueType(0).getVectorElementType(),
189 N->getOperand(0), N->getOperand(1));
192 SDValue DAGTypeLegalizer::ScalarizeVecRes_FP_ROUND(SDNode *N) {
193 EVT NewVT = N->getValueType(0).getVectorElementType();
194 SDValue Op = GetScalarizedVector(N->getOperand(0));
195 return DAG.getNode(ISD::FP_ROUND, SDLoc(N),
196 NewVT, Op, N->getOperand(1));
199 SDValue DAGTypeLegalizer::ScalarizeVecRes_FPOWI(SDNode *N) {
200 SDValue Op = GetScalarizedVector(N->getOperand(0));
201 return DAG.getNode(ISD::FPOWI, SDLoc(N),
202 Op.getValueType(), Op, N->getOperand(1));
205 SDValue DAGTypeLegalizer::ScalarizeVecRes_INSERT_VECTOR_ELT(SDNode *N) {
206 // The value to insert may have a wider type than the vector element type,
207 // so be sure to truncate it to the element type if necessary.
208 SDValue Op = N->getOperand(1);
209 EVT EltVT = N->getValueType(0).getVectorElementType();
210 if (Op.getValueType() != EltVT)
211 // FIXME: Can this happen for floating point types?
212 Op = DAG.getNode(ISD::TRUNCATE, SDLoc(N), EltVT, Op);
216 SDValue DAGTypeLegalizer::ScalarizeVecRes_LOAD(LoadSDNode *N) {
217 assert(N->isUnindexed() && "Indexed vector load?");
219 SDValue Result = DAG.getLoad(ISD::UNINDEXED,
220 N->getExtensionType(),
221 N->getValueType(0).getVectorElementType(),
223 N->getChain(), N->getBasePtr(),
224 DAG.getUNDEF(N->getBasePtr().getValueType()),
226 N->getMemoryVT().getVectorElementType(),
227 N->isVolatile(), N->isNonTemporal(),
228 N->isInvariant(), N->getOriginalAlignment(),
231 // Legalized the chain result - switch anything that used the old chain to
233 ReplaceValueWith(SDValue(N, 1), Result.getValue(1));
237 SDValue DAGTypeLegalizer::ScalarizeVecRes_UnaryOp(SDNode *N) {
238 // Get the dest type - it doesn't always match the input type, e.g. int_to_fp.
239 EVT DestVT = N->getValueType(0).getVectorElementType();
240 SDValue Op = N->getOperand(0);
241 EVT OpVT = Op.getValueType();
243 // The result needs scalarizing, but it's not a given that the source does.
244 // This is a workaround for targets where it's impossible to scalarize the
245 // result of a conversion, because the source type is legal.
246 // For instance, this happens on AArch64: v1i1 is illegal but v1i{8,16,32}
247 // are widened to v8i8, v4i16, and v2i32, which is legal, because v1i64 is
248 // legal and was not scalarized.
249 // See the similar logic in ScalarizeVecRes_VSETCC
250 if (getTypeAction(OpVT) == TargetLowering::TypeScalarizeVector) {
251 Op = GetScalarizedVector(Op);
253 EVT VT = OpVT.getVectorElementType();
254 Op = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, VT, Op,
255 DAG.getConstant(0, TLI.getVectorIdxTy()));
257 return DAG.getNode(N->getOpcode(), SDLoc(N), DestVT, Op);
260 SDValue DAGTypeLegalizer::ScalarizeVecRes_InregOp(SDNode *N) {
261 EVT EltVT = N->getValueType(0).getVectorElementType();
262 EVT ExtVT = cast<VTSDNode>(N->getOperand(1))->getVT().getVectorElementType();
263 SDValue LHS = GetScalarizedVector(N->getOperand(0));
264 return DAG.getNode(N->getOpcode(), SDLoc(N), EltVT,
265 LHS, DAG.getValueType(ExtVT));
268 SDValue DAGTypeLegalizer::ScalarizeVecRes_SCALAR_TO_VECTOR(SDNode *N) {
269 // If the operand is wider than the vector element type then it is implicitly
270 // truncated. Make that explicit here.
271 EVT EltVT = N->getValueType(0).getVectorElementType();
272 SDValue InOp = N->getOperand(0);
273 if (InOp.getValueType() != EltVT)
274 return DAG.getNode(ISD::TRUNCATE, SDLoc(N), EltVT, InOp);
278 SDValue DAGTypeLegalizer::ScalarizeVecRes_VSELECT(SDNode *N) {
279 SDValue Cond = GetScalarizedVector(N->getOperand(0));
280 SDValue LHS = GetScalarizedVector(N->getOperand(1));
281 TargetLowering::BooleanContent ScalarBool =
282 TLI.getBooleanContents(false, false);
283 TargetLowering::BooleanContent VecBool = TLI.getBooleanContents(true, false);
285 // If integer and float booleans have different contents then we can't
286 // reliably optimize in all cases. There is a full explanation for this in
287 // DAGCombiner::visitSELECT() where the same issue affects folding
288 // (select C, 0, 1) to (xor C, 1).
289 if (TLI.getBooleanContents(false, false) !=
290 TLI.getBooleanContents(false, true)) {
291 // At least try the common case where the boolean is generated by a
293 if (Cond->getOpcode() == ISD::SETCC) {
294 EVT OpVT = Cond->getOperand(0)->getValueType(0);
295 ScalarBool = TLI.getBooleanContents(OpVT.getScalarType());
296 VecBool = TLI.getBooleanContents(OpVT);
298 ScalarBool = TargetLowering::UndefinedBooleanContent;
301 if (ScalarBool != VecBool) {
302 EVT CondVT = Cond.getValueType();
303 switch (ScalarBool) {
304 case TargetLowering::UndefinedBooleanContent:
306 case TargetLowering::ZeroOrOneBooleanContent:
307 assert(VecBool == TargetLowering::UndefinedBooleanContent ||
308 VecBool == TargetLowering::ZeroOrNegativeOneBooleanContent);
309 // Vector read from all ones, scalar expects a single 1 so mask.
310 Cond = DAG.getNode(ISD::AND, SDLoc(N), CondVT,
311 Cond, DAG.getConstant(1, CondVT));
313 case TargetLowering::ZeroOrNegativeOneBooleanContent:
314 assert(VecBool == TargetLowering::UndefinedBooleanContent ||
315 VecBool == TargetLowering::ZeroOrOneBooleanContent);
316 // Vector reads from a one, scalar from all ones so sign extend.
317 Cond = DAG.getNode(ISD::SIGN_EXTEND_INREG, SDLoc(N), CondVT,
318 Cond, DAG.getValueType(MVT::i1));
323 return DAG.getSelect(SDLoc(N),
324 LHS.getValueType(), Cond, LHS,
325 GetScalarizedVector(N->getOperand(2)));
328 SDValue DAGTypeLegalizer::ScalarizeVecRes_SELECT(SDNode *N) {
329 SDValue LHS = GetScalarizedVector(N->getOperand(1));
330 return DAG.getSelect(SDLoc(N),
331 LHS.getValueType(), N->getOperand(0), LHS,
332 GetScalarizedVector(N->getOperand(2)));
335 SDValue DAGTypeLegalizer::ScalarizeVecRes_SELECT_CC(SDNode *N) {
336 SDValue LHS = GetScalarizedVector(N->getOperand(2));
337 return DAG.getNode(ISD::SELECT_CC, SDLoc(N), LHS.getValueType(),
338 N->getOperand(0), N->getOperand(1),
339 LHS, GetScalarizedVector(N->getOperand(3)),
343 SDValue DAGTypeLegalizer::ScalarizeVecRes_SETCC(SDNode *N) {
344 assert(N->getValueType(0).isVector() ==
345 N->getOperand(0).getValueType().isVector() &&
346 "Scalar/Vector type mismatch");
348 if (N->getValueType(0).isVector()) return ScalarizeVecRes_VSETCC(N);
350 SDValue LHS = GetScalarizedVector(N->getOperand(0));
351 SDValue RHS = GetScalarizedVector(N->getOperand(1));
354 // Turn it into a scalar SETCC.
355 return DAG.getNode(ISD::SETCC, DL, MVT::i1, LHS, RHS, N->getOperand(2));
358 SDValue DAGTypeLegalizer::ScalarizeVecRes_UNDEF(SDNode *N) {
359 return DAG.getUNDEF(N->getValueType(0).getVectorElementType());
362 SDValue DAGTypeLegalizer::ScalarizeVecRes_VECTOR_SHUFFLE(SDNode *N) {
363 // Figure out if the scalar is the LHS or RHS and return it.
364 SDValue Arg = N->getOperand(2).getOperand(0);
365 if (Arg.getOpcode() == ISD::UNDEF)
366 return DAG.getUNDEF(N->getValueType(0).getVectorElementType());
367 unsigned Op = !cast<ConstantSDNode>(Arg)->isNullValue();
368 return GetScalarizedVector(N->getOperand(Op));
371 SDValue DAGTypeLegalizer::ScalarizeVecRes_VSETCC(SDNode *N) {
372 assert(N->getValueType(0).isVector() &&
373 N->getOperand(0).getValueType().isVector() &&
374 "Operand types must be vectors");
375 SDValue LHS = N->getOperand(0);
376 SDValue RHS = N->getOperand(1);
377 EVT OpVT = LHS.getValueType();
378 EVT NVT = N->getValueType(0).getVectorElementType();
381 // The result needs scalarizing, but it's not a given that the source does.
382 if (getTypeAction(OpVT) == TargetLowering::TypeScalarizeVector) {
383 LHS = GetScalarizedVector(LHS);
384 RHS = GetScalarizedVector(RHS);
386 EVT VT = OpVT.getVectorElementType();
387 LHS = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, VT, LHS,
388 DAG.getConstant(0, TLI.getVectorIdxTy()));
389 RHS = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, VT, RHS,
390 DAG.getConstant(0, TLI.getVectorIdxTy()));
393 // Turn it into a scalar SETCC.
394 SDValue Res = DAG.getNode(ISD::SETCC, DL, MVT::i1, LHS, RHS,
396 // Vectors may have a different boolean contents to scalars. Promote the
397 // value appropriately.
398 ISD::NodeType ExtendCode =
399 TargetLowering::getExtendForContent(TLI.getBooleanContents(OpVT));
400 return DAG.getNode(ExtendCode, DL, NVT, Res);
404 //===----------------------------------------------------------------------===//
405 // Operand Vector Scalarization <1 x ty> -> ty.
406 //===----------------------------------------------------------------------===//
408 bool DAGTypeLegalizer::ScalarizeVectorOperand(SDNode *N, unsigned OpNo) {
409 DEBUG(dbgs() << "Scalarize node operand " << OpNo << ": ";
412 SDValue Res = SDValue();
414 if (!Res.getNode()) {
415 switch (N->getOpcode()) {
418 dbgs() << "ScalarizeVectorOperand Op #" << OpNo << ": ";
422 llvm_unreachable("Do not know how to scalarize this operator's operand!");
424 Res = ScalarizeVecOp_BITCAST(N);
426 case ISD::ANY_EXTEND:
427 case ISD::ZERO_EXTEND:
428 case ISD::SIGN_EXTEND:
430 case ISD::FP_TO_SINT:
431 case ISD::FP_TO_UINT:
432 case ISD::SINT_TO_FP:
433 case ISD::UINT_TO_FP:
434 Res = ScalarizeVecOp_UnaryOp(N);
436 case ISD::CONCAT_VECTORS:
437 Res = ScalarizeVecOp_CONCAT_VECTORS(N);
439 case ISD::EXTRACT_VECTOR_ELT:
440 Res = ScalarizeVecOp_EXTRACT_VECTOR_ELT(N);
443 Res = ScalarizeVecOp_VSELECT(N);
446 Res = ScalarizeVecOp_STORE(cast<StoreSDNode>(N), OpNo);
449 Res = ScalarizeVecOp_FP_ROUND(N, OpNo);
454 // If the result is null, the sub-method took care of registering results etc.
455 if (!Res.getNode()) return false;
457 // If the result is N, the sub-method updated N in place. Tell the legalizer
459 if (Res.getNode() == N)
462 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 &&
463 "Invalid operand expansion");
465 ReplaceValueWith(SDValue(N, 0), Res);
469 /// ScalarizeVecOp_BITCAST - If the value to convert is a vector that needs
470 /// to be scalarized, it must be <1 x ty>. Convert the element instead.
471 SDValue DAGTypeLegalizer::ScalarizeVecOp_BITCAST(SDNode *N) {
472 SDValue Elt = GetScalarizedVector(N->getOperand(0));
473 return DAG.getNode(ISD::BITCAST, SDLoc(N),
474 N->getValueType(0), Elt);
477 /// ScalarizeVecOp_UnaryOp - If the input is a vector that needs to be
478 /// scalarized, it must be <1 x ty>. Do the operation on the element instead.
479 SDValue DAGTypeLegalizer::ScalarizeVecOp_UnaryOp(SDNode *N) {
480 assert(N->getValueType(0).getVectorNumElements() == 1 &&
481 "Unexpected vector type!");
482 SDValue Elt = GetScalarizedVector(N->getOperand(0));
483 SDValue Op = DAG.getNode(N->getOpcode(), SDLoc(N),
484 N->getValueType(0).getScalarType(), Elt);
485 // Revectorize the result so the types line up with what the uses of this
486 // expression expect.
487 return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(N), N->getValueType(0), Op);
490 /// ScalarizeVecOp_CONCAT_VECTORS - The vectors to concatenate have length one -
491 /// use a BUILD_VECTOR instead.
492 SDValue DAGTypeLegalizer::ScalarizeVecOp_CONCAT_VECTORS(SDNode *N) {
493 SmallVector<SDValue, 8> Ops(N->getNumOperands());
494 for (unsigned i = 0, e = N->getNumOperands(); i < e; ++i)
495 Ops[i] = GetScalarizedVector(N->getOperand(i));
496 return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(N), N->getValueType(0), Ops);
499 /// ScalarizeVecOp_EXTRACT_VECTOR_ELT - If the input is a vector that needs to
500 /// be scalarized, it must be <1 x ty>, so just return the element, ignoring the
502 SDValue DAGTypeLegalizer::ScalarizeVecOp_EXTRACT_VECTOR_ELT(SDNode *N) {
503 SDValue Res = GetScalarizedVector(N->getOperand(0));
504 if (Res.getValueType() != N->getValueType(0))
505 Res = DAG.getNode(ISD::ANY_EXTEND, SDLoc(N), N->getValueType(0),
511 /// ScalarizeVecOp_VSELECT - If the input condition is a vector that needs to be
512 /// scalarized, it must be <1 x i1>, so just convert to a normal ISD::SELECT
513 /// (still with vector output type since that was acceptable if we got here).
514 SDValue DAGTypeLegalizer::ScalarizeVecOp_VSELECT(SDNode *N) {
515 SDValue ScalarCond = GetScalarizedVector(N->getOperand(0));
516 EVT VT = N->getValueType(0);
518 return DAG.getNode(ISD::SELECT, SDLoc(N), VT, ScalarCond, N->getOperand(1),
522 /// ScalarizeVecOp_STORE - If the value to store is a vector that needs to be
523 /// scalarized, it must be <1 x ty>. Just store the element.
524 SDValue DAGTypeLegalizer::ScalarizeVecOp_STORE(StoreSDNode *N, unsigned OpNo){
525 assert(N->isUnindexed() && "Indexed store of one-element vector?");
526 assert(OpNo == 1 && "Do not know how to scalarize this operand!");
529 if (N->isTruncatingStore())
530 return DAG.getTruncStore(N->getChain(), dl,
531 GetScalarizedVector(N->getOperand(1)),
532 N->getBasePtr(), N->getPointerInfo(),
533 N->getMemoryVT().getVectorElementType(),
534 N->isVolatile(), N->isNonTemporal(),
535 N->getAlignment(), N->getAAInfo());
537 return DAG.getStore(N->getChain(), dl, GetScalarizedVector(N->getOperand(1)),
538 N->getBasePtr(), N->getPointerInfo(),
539 N->isVolatile(), N->isNonTemporal(),
540 N->getOriginalAlignment(), N->getAAInfo());
543 /// ScalarizeVecOp_FP_ROUND - If the value to round is a vector that needs
544 /// to be scalarized, it must be <1 x ty>. Convert the element instead.
545 SDValue DAGTypeLegalizer::ScalarizeVecOp_FP_ROUND(SDNode *N, unsigned OpNo) {
546 SDValue Elt = GetScalarizedVector(N->getOperand(0));
547 SDValue Res = DAG.getNode(ISD::FP_ROUND, SDLoc(N),
548 N->getValueType(0).getVectorElementType(), Elt,
550 return DAG.getNode(ISD::SCALAR_TO_VECTOR, SDLoc(N), N->getValueType(0), Res);
553 //===----------------------------------------------------------------------===//
554 // Result Vector Splitting
555 //===----------------------------------------------------------------------===//
557 /// SplitVectorResult - This method is called when the specified result of the
558 /// specified node is found to need vector splitting. At this point, the node
559 /// may also have invalid operands or may have other results that need
560 /// legalization, we just know that (at least) one result needs vector
562 void DAGTypeLegalizer::SplitVectorResult(SDNode *N, unsigned ResNo) {
563 DEBUG(dbgs() << "Split node result: ";
568 // See if the target wants to custom expand this node.
569 if (CustomLowerNode(N, N->getValueType(ResNo), true))
572 switch (N->getOpcode()) {
575 dbgs() << "SplitVectorResult #" << ResNo << ": ";
579 report_fatal_error("Do not know how to split the result of this "
582 case ISD::MERGE_VALUES: SplitRes_MERGE_VALUES(N, ResNo, Lo, Hi); break;
584 case ISD::SELECT: SplitRes_SELECT(N, Lo, Hi); break;
585 case ISD::SELECT_CC: SplitRes_SELECT_CC(N, Lo, Hi); break;
586 case ISD::UNDEF: SplitRes_UNDEF(N, Lo, Hi); break;
587 case ISD::BITCAST: SplitVecRes_BITCAST(N, Lo, Hi); break;
588 case ISD::BUILD_VECTOR: SplitVecRes_BUILD_VECTOR(N, Lo, Hi); break;
589 case ISD::CONCAT_VECTORS: SplitVecRes_CONCAT_VECTORS(N, Lo, Hi); break;
590 case ISD::EXTRACT_SUBVECTOR: SplitVecRes_EXTRACT_SUBVECTOR(N, Lo, Hi); break;
591 case ISD::INSERT_SUBVECTOR: SplitVecRes_INSERT_SUBVECTOR(N, Lo, Hi); break;
592 case ISD::FP_ROUND_INREG: SplitVecRes_InregOp(N, Lo, Hi); break;
593 case ISD::FPOWI: SplitVecRes_FPOWI(N, Lo, Hi); break;
594 case ISD::INSERT_VECTOR_ELT: SplitVecRes_INSERT_VECTOR_ELT(N, Lo, Hi); break;
595 case ISD::SCALAR_TO_VECTOR: SplitVecRes_SCALAR_TO_VECTOR(N, Lo, Hi); break;
596 case ISD::SIGN_EXTEND_INREG: SplitVecRes_InregOp(N, Lo, Hi); break;
598 SplitVecRes_LOAD(cast<LoadSDNode>(N), Lo, Hi);
601 SplitVecRes_MLOAD(cast<MaskedLoadSDNode>(N), Lo, Hi);
604 SplitVecRes_SETCC(N, Lo, Hi);
606 case ISD::VECTOR_SHUFFLE:
607 SplitVecRes_VECTOR_SHUFFLE(cast<ShuffleVectorSDNode>(N), Lo, Hi);
611 case ISD::CONVERT_RNDSAT:
614 case ISD::CTLZ_ZERO_UNDEF:
615 case ISD::CTTZ_ZERO_UNDEF:
626 case ISD::FNEARBYINT:
630 case ISD::FP_TO_SINT:
631 case ISD::FP_TO_UINT:
637 case ISD::SINT_TO_FP:
639 case ISD::UINT_TO_FP:
640 SplitVecRes_UnaryOp(N, Lo, Hi);
643 case ISD::ANY_EXTEND:
644 case ISD::SIGN_EXTEND:
645 case ISD::ZERO_EXTEND:
646 SplitVecRes_ExtendOp(N, Lo, Hi);
671 SplitVecRes_BinOp(N, Lo, Hi);
674 SplitVecRes_TernaryOp(N, Lo, Hi);
678 // If Lo/Hi is null, the sub-method took care of registering results etc.
680 SetSplitVector(SDValue(N, ResNo), Lo, Hi);
683 void DAGTypeLegalizer::SplitVecRes_BinOp(SDNode *N, SDValue &Lo,
685 SDValue LHSLo, LHSHi;
686 GetSplitVector(N->getOperand(0), LHSLo, LHSHi);
687 SDValue RHSLo, RHSHi;
688 GetSplitVector(N->getOperand(1), RHSLo, RHSHi);
691 Lo = DAG.getNode(N->getOpcode(), dl, LHSLo.getValueType(), LHSLo, RHSLo);
692 Hi = DAG.getNode(N->getOpcode(), dl, LHSHi.getValueType(), LHSHi, RHSHi);
695 void DAGTypeLegalizer::SplitVecRes_TernaryOp(SDNode *N, SDValue &Lo,
697 SDValue Op0Lo, Op0Hi;
698 GetSplitVector(N->getOperand(0), Op0Lo, Op0Hi);
699 SDValue Op1Lo, Op1Hi;
700 GetSplitVector(N->getOperand(1), Op1Lo, Op1Hi);
701 SDValue Op2Lo, Op2Hi;
702 GetSplitVector(N->getOperand(2), Op2Lo, Op2Hi);
705 Lo = DAG.getNode(N->getOpcode(), dl, Op0Lo.getValueType(),
706 Op0Lo, Op1Lo, Op2Lo);
707 Hi = DAG.getNode(N->getOpcode(), dl, Op0Hi.getValueType(),
708 Op0Hi, Op1Hi, Op2Hi);
711 void DAGTypeLegalizer::SplitVecRes_BITCAST(SDNode *N, SDValue &Lo,
713 // We know the result is a vector. The input may be either a vector or a
716 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(N->getValueType(0));
719 SDValue InOp = N->getOperand(0);
720 EVT InVT = InOp.getValueType();
722 // Handle some special cases efficiently.
723 switch (getTypeAction(InVT)) {
724 case TargetLowering::TypeLegal:
725 case TargetLowering::TypePromoteInteger:
726 case TargetLowering::TypeSoftenFloat:
727 case TargetLowering::TypeScalarizeVector:
728 case TargetLowering::TypeWidenVector:
730 case TargetLowering::TypeExpandInteger:
731 case TargetLowering::TypeExpandFloat:
732 // A scalar to vector conversion, where the scalar needs expansion.
733 // If the vector is being split in two then we can just convert the
736 GetExpandedOp(InOp, Lo, Hi);
737 if (TLI.isBigEndian())
739 Lo = DAG.getNode(ISD::BITCAST, dl, LoVT, Lo);
740 Hi = DAG.getNode(ISD::BITCAST, dl, HiVT, Hi);
744 case TargetLowering::TypeSplitVector:
745 // If the input is a vector that needs to be split, convert each split
746 // piece of the input now.
747 GetSplitVector(InOp, Lo, Hi);
748 Lo = DAG.getNode(ISD::BITCAST, dl, LoVT, Lo);
749 Hi = DAG.getNode(ISD::BITCAST, dl, HiVT, Hi);
753 // In the general case, convert the input to an integer and split it by hand.
754 EVT LoIntVT = EVT::getIntegerVT(*DAG.getContext(), LoVT.getSizeInBits());
755 EVT HiIntVT = EVT::getIntegerVT(*DAG.getContext(), HiVT.getSizeInBits());
756 if (TLI.isBigEndian())
757 std::swap(LoIntVT, HiIntVT);
759 SplitInteger(BitConvertToInteger(InOp), LoIntVT, HiIntVT, Lo, Hi);
761 if (TLI.isBigEndian())
763 Lo = DAG.getNode(ISD::BITCAST, dl, LoVT, Lo);
764 Hi = DAG.getNode(ISD::BITCAST, dl, HiVT, Hi);
767 void DAGTypeLegalizer::SplitVecRes_BUILD_VECTOR(SDNode *N, SDValue &Lo,
771 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(N->getValueType(0));
772 unsigned LoNumElts = LoVT.getVectorNumElements();
773 SmallVector<SDValue, 8> LoOps(N->op_begin(), N->op_begin()+LoNumElts);
774 Lo = DAG.getNode(ISD::BUILD_VECTOR, dl, LoVT, LoOps);
776 SmallVector<SDValue, 8> HiOps(N->op_begin()+LoNumElts, N->op_end());
777 Hi = DAG.getNode(ISD::BUILD_VECTOR, dl, HiVT, HiOps);
780 void DAGTypeLegalizer::SplitVecRes_CONCAT_VECTORS(SDNode *N, SDValue &Lo,
782 assert(!(N->getNumOperands() & 1) && "Unsupported CONCAT_VECTORS");
784 unsigned NumSubvectors = N->getNumOperands() / 2;
785 if (NumSubvectors == 1) {
786 Lo = N->getOperand(0);
787 Hi = N->getOperand(1);
792 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(N->getValueType(0));
794 SmallVector<SDValue, 8> LoOps(N->op_begin(), N->op_begin()+NumSubvectors);
795 Lo = DAG.getNode(ISD::CONCAT_VECTORS, dl, LoVT, LoOps);
797 SmallVector<SDValue, 8> HiOps(N->op_begin()+NumSubvectors, N->op_end());
798 Hi = DAG.getNode(ISD::CONCAT_VECTORS, dl, HiVT, HiOps);
801 void DAGTypeLegalizer::SplitVecRes_EXTRACT_SUBVECTOR(SDNode *N, SDValue &Lo,
803 SDValue Vec = N->getOperand(0);
804 SDValue Idx = N->getOperand(1);
808 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(N->getValueType(0));
810 Lo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, LoVT, Vec, Idx);
811 uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
812 Hi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, HiVT, Vec,
813 DAG.getConstant(IdxVal + LoVT.getVectorNumElements(),
814 TLI.getVectorIdxTy()));
817 void DAGTypeLegalizer::SplitVecRes_INSERT_SUBVECTOR(SDNode *N, SDValue &Lo,
819 SDValue Vec = N->getOperand(0);
820 SDValue SubVec = N->getOperand(1);
821 SDValue Idx = N->getOperand(2);
823 GetSplitVector(Vec, Lo, Hi);
825 // Spill the vector to the stack.
826 EVT VecVT = Vec.getValueType();
827 EVT SubVecVT = VecVT.getVectorElementType();
828 SDValue StackPtr = DAG.CreateStackTemporary(VecVT);
829 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Vec, StackPtr,
830 MachinePointerInfo(), false, false, 0);
832 // Store the new subvector into the specified index.
833 SDValue SubVecPtr = GetVectorElementPointer(StackPtr, SubVecVT, Idx);
834 Type *VecType = VecVT.getTypeForEVT(*DAG.getContext());
835 unsigned Alignment = TLI.getDataLayout()->getPrefTypeAlignment(VecType);
836 Store = DAG.getStore(Store, dl, SubVec, SubVecPtr, MachinePointerInfo(),
839 // Load the Lo part from the stack slot.
840 Lo = DAG.getLoad(Lo.getValueType(), dl, Store, StackPtr, MachinePointerInfo(),
841 false, false, false, 0);
843 // Increment the pointer to the other part.
844 unsigned IncrementSize = Lo.getValueType().getSizeInBits() / 8;
846 DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr,
847 DAG.getConstant(IncrementSize, StackPtr.getValueType()));
849 // Load the Hi part from the stack slot.
850 Hi = DAG.getLoad(Hi.getValueType(), dl, Store, StackPtr, MachinePointerInfo(),
851 false, false, false, MinAlign(Alignment, IncrementSize));
854 void DAGTypeLegalizer::SplitVecRes_FPOWI(SDNode *N, SDValue &Lo,
857 GetSplitVector(N->getOperand(0), Lo, Hi);
858 Lo = DAG.getNode(ISD::FPOWI, dl, Lo.getValueType(), Lo, N->getOperand(1));
859 Hi = DAG.getNode(ISD::FPOWI, dl, Hi.getValueType(), Hi, N->getOperand(1));
862 void DAGTypeLegalizer::SplitVecRes_InregOp(SDNode *N, SDValue &Lo,
864 SDValue LHSLo, LHSHi;
865 GetSplitVector(N->getOperand(0), LHSLo, LHSHi);
869 std::tie(LoVT, HiVT) =
870 DAG.GetSplitDestVTs(cast<VTSDNode>(N->getOperand(1))->getVT());
872 Lo = DAG.getNode(N->getOpcode(), dl, LHSLo.getValueType(), LHSLo,
873 DAG.getValueType(LoVT));
874 Hi = DAG.getNode(N->getOpcode(), dl, LHSHi.getValueType(), LHSHi,
875 DAG.getValueType(HiVT));
878 void DAGTypeLegalizer::SplitVecRes_INSERT_VECTOR_ELT(SDNode *N, SDValue &Lo,
880 SDValue Vec = N->getOperand(0);
881 SDValue Elt = N->getOperand(1);
882 SDValue Idx = N->getOperand(2);
884 GetSplitVector(Vec, Lo, Hi);
886 if (ConstantSDNode *CIdx = dyn_cast<ConstantSDNode>(Idx)) {
887 unsigned IdxVal = CIdx->getZExtValue();
888 unsigned LoNumElts = Lo.getValueType().getVectorNumElements();
889 if (IdxVal < LoNumElts)
890 Lo = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
891 Lo.getValueType(), Lo, Elt, Idx);
893 Hi = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, Hi.getValueType(), Hi, Elt,
894 DAG.getConstant(IdxVal - LoNumElts,
895 TLI.getVectorIdxTy()));
899 // See if the target wants to custom expand this node.
900 if (CustomLowerNode(N, N->getValueType(0), true))
903 // Spill the vector to the stack.
904 EVT VecVT = Vec.getValueType();
905 EVT EltVT = VecVT.getVectorElementType();
906 SDValue StackPtr = DAG.CreateStackTemporary(VecVT);
907 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Vec, StackPtr,
908 MachinePointerInfo(), false, false, 0);
910 // Store the new element. This may be larger than the vector element type,
911 // so use a truncating store.
912 SDValue EltPtr = GetVectorElementPointer(StackPtr, EltVT, Idx);
913 Type *VecType = VecVT.getTypeForEVT(*DAG.getContext());
915 TLI.getDataLayout()->getPrefTypeAlignment(VecType);
916 Store = DAG.getTruncStore(Store, dl, Elt, EltPtr, MachinePointerInfo(), EltVT,
919 // Load the Lo part from the stack slot.
920 Lo = DAG.getLoad(Lo.getValueType(), dl, Store, StackPtr, MachinePointerInfo(),
921 false, false, false, 0);
923 // Increment the pointer to the other part.
924 unsigned IncrementSize = Lo.getValueType().getSizeInBits() / 8;
925 StackPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr,
926 DAG.getConstant(IncrementSize, StackPtr.getValueType()));
928 // Load the Hi part from the stack slot.
929 Hi = DAG.getLoad(Hi.getValueType(), dl, Store, StackPtr, MachinePointerInfo(),
930 false, false, false, MinAlign(Alignment, IncrementSize));
933 void DAGTypeLegalizer::SplitVecRes_SCALAR_TO_VECTOR(SDNode *N, SDValue &Lo,
937 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(N->getValueType(0));
938 Lo = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LoVT, N->getOperand(0));
939 Hi = DAG.getUNDEF(HiVT);
942 void DAGTypeLegalizer::SplitVecRes_LOAD(LoadSDNode *LD, SDValue &Lo,
944 assert(ISD::isUNINDEXEDLoad(LD) && "Indexed load during type legalization!");
947 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(LD->getValueType(0));
949 ISD::LoadExtType ExtType = LD->getExtensionType();
950 SDValue Ch = LD->getChain();
951 SDValue Ptr = LD->getBasePtr();
952 SDValue Offset = DAG.getUNDEF(Ptr.getValueType());
953 EVT MemoryVT = LD->getMemoryVT();
954 unsigned Alignment = LD->getOriginalAlignment();
955 bool isVolatile = LD->isVolatile();
956 bool isNonTemporal = LD->isNonTemporal();
957 bool isInvariant = LD->isInvariant();
958 AAMDNodes AAInfo = LD->getAAInfo();
960 EVT LoMemVT, HiMemVT;
961 std::tie(LoMemVT, HiMemVT) = DAG.GetSplitDestVTs(MemoryVT);
963 Lo = DAG.getLoad(ISD::UNINDEXED, ExtType, LoVT, dl, Ch, Ptr, Offset,
964 LD->getPointerInfo(), LoMemVT, isVolatile, isNonTemporal,
965 isInvariant, Alignment, AAInfo);
967 unsigned IncrementSize = LoMemVT.getSizeInBits()/8;
968 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
969 DAG.getConstant(IncrementSize, Ptr.getValueType()));
970 Hi = DAG.getLoad(ISD::UNINDEXED, ExtType, HiVT, dl, Ch, Ptr, Offset,
971 LD->getPointerInfo().getWithOffset(IncrementSize),
972 HiMemVT, isVolatile, isNonTemporal, isInvariant, Alignment,
975 // Build a factor node to remember that this load is independent of the
977 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
980 // Legalized the chain result - switch anything that used the old chain to
982 ReplaceValueWith(SDValue(LD, 1), Ch);
985 void DAGTypeLegalizer::SplitVecRes_MLOAD(MaskedLoadSDNode *MLD,
986 SDValue &Lo, SDValue &Hi) {
989 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(MLD->getValueType(0));
991 SDValue Ch = MLD->getChain();
992 SDValue Ptr = MLD->getBasePtr();
993 SDValue Mask = MLD->getMask();
994 unsigned Alignment = MLD->getOriginalAlignment();
995 ISD::LoadExtType ExtType = MLD->getExtensionType();
997 // if Alignment is equal to the vector size,
998 // take the half of it for the second part
999 unsigned SecondHalfAlignment =
1000 (Alignment == MLD->getValueType(0).getSizeInBits()/8) ?
1001 Alignment/2 : Alignment;
1003 SDValue MaskLo, MaskHi;
1004 std::tie(MaskLo, MaskHi) = DAG.SplitVector(Mask, dl);
1006 EVT MemoryVT = MLD->getMemoryVT();
1007 EVT LoMemVT, HiMemVT;
1008 std::tie(LoMemVT, HiMemVT) = DAG.GetSplitDestVTs(MemoryVT);
1010 SDValue Src0 = MLD->getSrc0();
1011 SDValue Src0Lo, Src0Hi;
1012 std::tie(Src0Lo, Src0Hi) = DAG.SplitVector(Src0, dl);
1014 MachineMemOperand *MMO = DAG.getMachineFunction().
1015 getMachineMemOperand(MLD->getPointerInfo(),
1016 MachineMemOperand::MOLoad, LoMemVT.getStoreSize(),
1017 Alignment, MLD->getAAInfo(), MLD->getRanges());
1019 Lo = DAG.getMaskedLoad(LoVT, dl, Ch, Ptr, MaskLo, Src0Lo, LoMemVT, MMO,
1022 unsigned IncrementSize = LoMemVT.getSizeInBits()/8;
1023 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
1024 DAG.getConstant(IncrementSize, Ptr.getValueType()));
1026 MMO = DAG.getMachineFunction().
1027 getMachineMemOperand(MLD->getPointerInfo(),
1028 MachineMemOperand::MOLoad, HiMemVT.getStoreSize(),
1029 SecondHalfAlignment, MLD->getAAInfo(), MLD->getRanges());
1031 Hi = DAG.getMaskedLoad(HiVT, dl, Ch, Ptr, MaskHi, Src0Hi, HiMemVT, MMO,
1035 // Build a factor node to remember that this load is independent of the
1037 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
1040 // Legalized the chain result - switch anything that used the old chain to
1042 ReplaceValueWith(SDValue(MLD, 1), Ch);
1046 void DAGTypeLegalizer::SplitVecRes_SETCC(SDNode *N, SDValue &Lo, SDValue &Hi) {
1047 assert(N->getValueType(0).isVector() &&
1048 N->getOperand(0).getValueType().isVector() &&
1049 "Operand types must be vectors");
1053 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(N->getValueType(0));
1056 SDValue LL, LH, RL, RH;
1057 std::tie(LL, LH) = DAG.SplitVectorOperand(N, 0);
1058 std::tie(RL, RH) = DAG.SplitVectorOperand(N, 1);
1060 Lo = DAG.getNode(N->getOpcode(), DL, LoVT, LL, RL, N->getOperand(2));
1061 Hi = DAG.getNode(N->getOpcode(), DL, HiVT, LH, RH, N->getOperand(2));
1064 void DAGTypeLegalizer::SplitVecRes_UnaryOp(SDNode *N, SDValue &Lo,
1066 // Get the dest types - they may not match the input types, e.g. int_to_fp.
1069 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(N->getValueType(0));
1071 // If the input also splits, handle it directly for a compile time speedup.
1072 // Otherwise split it by hand.
1073 EVT InVT = N->getOperand(0).getValueType();
1074 if (getTypeAction(InVT) == TargetLowering::TypeSplitVector)
1075 GetSplitVector(N->getOperand(0), Lo, Hi);
1077 std::tie(Lo, Hi) = DAG.SplitVectorOperand(N, 0);
1079 if (N->getOpcode() == ISD::FP_ROUND) {
1080 Lo = DAG.getNode(N->getOpcode(), dl, LoVT, Lo, N->getOperand(1));
1081 Hi = DAG.getNode(N->getOpcode(), dl, HiVT, Hi, N->getOperand(1));
1082 } else if (N->getOpcode() == ISD::CONVERT_RNDSAT) {
1083 SDValue DTyOpLo = DAG.getValueType(LoVT);
1084 SDValue DTyOpHi = DAG.getValueType(HiVT);
1085 SDValue STyOpLo = DAG.getValueType(Lo.getValueType());
1086 SDValue STyOpHi = DAG.getValueType(Hi.getValueType());
1087 SDValue RndOp = N->getOperand(3);
1088 SDValue SatOp = N->getOperand(4);
1089 ISD::CvtCode CvtCode = cast<CvtRndSatSDNode>(N)->getCvtCode();
1090 Lo = DAG.getConvertRndSat(LoVT, dl, Lo, DTyOpLo, STyOpLo, RndOp, SatOp,
1092 Hi = DAG.getConvertRndSat(HiVT, dl, Hi, DTyOpHi, STyOpHi, RndOp, SatOp,
1095 Lo = DAG.getNode(N->getOpcode(), dl, LoVT, Lo);
1096 Hi = DAG.getNode(N->getOpcode(), dl, HiVT, Hi);
1100 void DAGTypeLegalizer::SplitVecRes_ExtendOp(SDNode *N, SDValue &Lo,
1103 EVT SrcVT = N->getOperand(0).getValueType();
1104 EVT DestVT = N->getValueType(0);
1106 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(DestVT);
1108 // We can do better than a generic split operation if the extend is doing
1109 // more than just doubling the width of the elements and the following are
1111 // - The number of vector elements is even,
1112 // - the source type is legal,
1113 // - the type of a split source is illegal,
1114 // - the type of an extended (by doubling element size) source is legal, and
1115 // - the type of that extended source when split is legal.
1117 // This won't necessarily completely legalize the operation, but it will
1118 // more effectively move in the right direction and prevent falling down
1119 // to scalarization in many cases due to the input vector being split too
1121 unsigned NumElements = SrcVT.getVectorNumElements();
1122 if ((NumElements & 1) == 0 &&
1123 SrcVT.getSizeInBits() * 2 < DestVT.getSizeInBits()) {
1124 LLVMContext &Ctx = *DAG.getContext();
1125 EVT NewSrcVT = EVT::getVectorVT(
1126 Ctx, EVT::getIntegerVT(
1127 Ctx, SrcVT.getVectorElementType().getSizeInBits() * 2),
1130 EVT::getVectorVT(Ctx, SrcVT.getVectorElementType(), NumElements / 2);
1131 EVT SplitLoVT, SplitHiVT;
1132 std::tie(SplitLoVT, SplitHiVT) = DAG.GetSplitDestVTs(NewSrcVT);
1133 if (TLI.isTypeLegal(SrcVT) && !TLI.isTypeLegal(SplitSrcVT) &&
1134 TLI.isTypeLegal(NewSrcVT) && TLI.isTypeLegal(SplitLoVT)) {
1135 DEBUG(dbgs() << "Split vector extend via incremental extend:";
1136 N->dump(&DAG); dbgs() << "\n");
1137 // Extend the source vector by one step.
1139 DAG.getNode(N->getOpcode(), dl, NewSrcVT, N->getOperand(0));
1140 // Get the low and high halves of the new, extended one step, vector.
1141 std::tie(Lo, Hi) = DAG.SplitVector(NewSrc, dl);
1142 // Extend those vector halves the rest of the way.
1143 Lo = DAG.getNode(N->getOpcode(), dl, LoVT, Lo);
1144 Hi = DAG.getNode(N->getOpcode(), dl, HiVT, Hi);
1148 // Fall back to the generic unary operator splitting otherwise.
1149 SplitVecRes_UnaryOp(N, Lo, Hi);
1152 void DAGTypeLegalizer::SplitVecRes_VECTOR_SHUFFLE(ShuffleVectorSDNode *N,
1153 SDValue &Lo, SDValue &Hi) {
1154 // The low and high parts of the original input give four input vectors.
1157 GetSplitVector(N->getOperand(0), Inputs[0], Inputs[1]);
1158 GetSplitVector(N->getOperand(1), Inputs[2], Inputs[3]);
1159 EVT NewVT = Inputs[0].getValueType();
1160 unsigned NewElts = NewVT.getVectorNumElements();
1162 // If Lo or Hi uses elements from at most two of the four input vectors, then
1163 // express it as a vector shuffle of those two inputs. Otherwise extract the
1164 // input elements by hand and construct the Lo/Hi output using a BUILD_VECTOR.
1165 SmallVector<int, 16> Ops;
1166 for (unsigned High = 0; High < 2; ++High) {
1167 SDValue &Output = High ? Hi : Lo;
1169 // Build a shuffle mask for the output, discovering on the fly which
1170 // input vectors to use as shuffle operands (recorded in InputUsed).
1171 // If building a suitable shuffle vector proves too hard, then bail
1172 // out with useBuildVector set.
1173 unsigned InputUsed[2] = { -1U, -1U }; // Not yet discovered.
1174 unsigned FirstMaskIdx = High * NewElts;
1175 bool useBuildVector = false;
1176 for (unsigned MaskOffset = 0; MaskOffset < NewElts; ++MaskOffset) {
1177 // The mask element. This indexes into the input.
1178 int Idx = N->getMaskElt(FirstMaskIdx + MaskOffset);
1180 // The input vector this mask element indexes into.
1181 unsigned Input = (unsigned)Idx / NewElts;
1183 if (Input >= array_lengthof(Inputs)) {
1184 // The mask element does not index into any input vector.
1189 // Turn the index into an offset from the start of the input vector.
1190 Idx -= Input * NewElts;
1192 // Find or create a shuffle vector operand to hold this input.
1194 for (OpNo = 0; OpNo < array_lengthof(InputUsed); ++OpNo) {
1195 if (InputUsed[OpNo] == Input) {
1196 // This input vector is already an operand.
1198 } else if (InputUsed[OpNo] == -1U) {
1199 // Create a new operand for this input vector.
1200 InputUsed[OpNo] = Input;
1205 if (OpNo >= array_lengthof(InputUsed)) {
1206 // More than two input vectors used! Give up on trying to create a
1207 // shuffle vector. Insert all elements into a BUILD_VECTOR instead.
1208 useBuildVector = true;
1212 // Add the mask index for the new shuffle vector.
1213 Ops.push_back(Idx + OpNo * NewElts);
1216 if (useBuildVector) {
1217 EVT EltVT = NewVT.getVectorElementType();
1218 SmallVector<SDValue, 16> SVOps;
1220 // Extract the input elements by hand.
1221 for (unsigned MaskOffset = 0; MaskOffset < NewElts; ++MaskOffset) {
1222 // The mask element. This indexes into the input.
1223 int Idx = N->getMaskElt(FirstMaskIdx + MaskOffset);
1225 // The input vector this mask element indexes into.
1226 unsigned Input = (unsigned)Idx / NewElts;
1228 if (Input >= array_lengthof(Inputs)) {
1229 // The mask element is "undef" or indexes off the end of the input.
1230 SVOps.push_back(DAG.getUNDEF(EltVT));
1234 // Turn the index into an offset from the start of the input vector.
1235 Idx -= Input * NewElts;
1237 // Extract the vector element by hand.
1238 SVOps.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT,
1239 Inputs[Input], DAG.getConstant(Idx,
1240 TLI.getVectorIdxTy())));
1243 // Construct the Lo/Hi output using a BUILD_VECTOR.
1244 Output = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, SVOps);
1245 } else if (InputUsed[0] == -1U) {
1246 // No input vectors were used! The result is undefined.
1247 Output = DAG.getUNDEF(NewVT);
1249 SDValue Op0 = Inputs[InputUsed[0]];
1250 // If only one input was used, use an undefined vector for the other.
1251 SDValue Op1 = InputUsed[1] == -1U ?
1252 DAG.getUNDEF(NewVT) : Inputs[InputUsed[1]];
1253 // At least one input vector was used. Create a new shuffle vector.
1254 Output = DAG.getVectorShuffle(NewVT, dl, Op0, Op1, &Ops[0]);
1262 //===----------------------------------------------------------------------===//
1263 // Operand Vector Splitting
1264 //===----------------------------------------------------------------------===//
1266 /// SplitVectorOperand - This method is called when the specified operand of the
1267 /// specified node is found to need vector splitting. At this point, all of the
1268 /// result types of the node are known to be legal, but other operands of the
1269 /// node may need legalization as well as the specified one.
1270 bool DAGTypeLegalizer::SplitVectorOperand(SDNode *N, unsigned OpNo) {
1271 DEBUG(dbgs() << "Split node operand: ";
1274 SDValue Res = SDValue();
1276 // See if the target wants to custom split this node.
1277 if (CustomLowerNode(N, N->getOperand(OpNo).getValueType(), false))
1280 if (!Res.getNode()) {
1281 switch (N->getOpcode()) {
1284 dbgs() << "SplitVectorOperand Op #" << OpNo << ": ";
1288 report_fatal_error("Do not know how to split this operator's "
1291 case ISD::SETCC: Res = SplitVecOp_VSETCC(N); break;
1292 case ISD::BITCAST: Res = SplitVecOp_BITCAST(N); break;
1293 case ISD::EXTRACT_SUBVECTOR: Res = SplitVecOp_EXTRACT_SUBVECTOR(N); break;
1294 case ISD::EXTRACT_VECTOR_ELT:Res = SplitVecOp_EXTRACT_VECTOR_ELT(N); break;
1295 case ISD::CONCAT_VECTORS: Res = SplitVecOp_CONCAT_VECTORS(N); break;
1297 Res = SplitVecOp_TruncateHelper(N, ISD::TRUNCATE);
1299 case ISD::FP_ROUND: Res = SplitVecOp_FP_ROUND(N); break;
1301 Res = SplitVecOp_STORE(cast<StoreSDNode>(N), OpNo);
1304 Res = SplitVecOp_MSTORE(cast<MaskedStoreSDNode>(N), OpNo);
1307 Res = SplitVecOp_VSELECT(N, OpNo);
1309 case ISD::FP_TO_SINT:
1310 case ISD::FP_TO_UINT:
1311 if (N->getValueType(0).bitsLT(N->getOperand(0)->getValueType(0)))
1312 Res = SplitVecOp_TruncateHelper(N, ISD::TRUNCATE);
1314 Res = SplitVecOp_UnaryOp(N);
1316 case ISD::SINT_TO_FP:
1317 case ISD::UINT_TO_FP:
1318 if (N->getValueType(0).bitsLT(N->getOperand(0)->getValueType(0)))
1319 Res = SplitVecOp_TruncateHelper(N, ISD::FTRUNC);
1321 Res = SplitVecOp_UnaryOp(N);
1326 case ISD::FP_EXTEND:
1327 case ISD::SIGN_EXTEND:
1328 case ISD::ZERO_EXTEND:
1329 case ISD::ANY_EXTEND:
1330 Res = SplitVecOp_UnaryOp(N);
1333 Res = SplitVecOp_TruncateHelper(N, ISD::FTRUNC);
1338 // If the result is null, the sub-method took care of registering results etc.
1339 if (!Res.getNode()) return false;
1341 // If the result is N, the sub-method updated N in place. Tell the legalizer
1343 if (Res.getNode() == N)
1346 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 &&
1347 "Invalid operand expansion");
1349 ReplaceValueWith(SDValue(N, 0), Res);
1353 SDValue DAGTypeLegalizer::SplitVecOp_VSELECT(SDNode *N, unsigned OpNo) {
1354 // The only possibility for an illegal operand is the mask, since result type
1355 // legalization would have handled this node already otherwise.
1356 assert(OpNo == 0 && "Illegal operand must be mask");
1358 SDValue Mask = N->getOperand(0);
1359 SDValue Src0 = N->getOperand(1);
1360 SDValue Src1 = N->getOperand(2);
1361 EVT Src0VT = Src0.getValueType();
1363 assert(Mask.getValueType().isVector() && "VSELECT without a vector mask?");
1366 GetSplitVector(N->getOperand(0), Lo, Hi);
1367 assert(Lo.getValueType() == Hi.getValueType() &&
1368 "Lo and Hi have differing types");
1371 std::tie(LoOpVT, HiOpVT) = DAG.GetSplitDestVTs(Src0VT);
1372 assert(LoOpVT == HiOpVT && "Asymmetric vector split?");
1374 SDValue LoOp0, HiOp0, LoOp1, HiOp1, LoMask, HiMask;
1375 std::tie(LoOp0, HiOp0) = DAG.SplitVector(Src0, DL);
1376 std::tie(LoOp1, HiOp1) = DAG.SplitVector(Src1, DL);
1377 std::tie(LoMask, HiMask) = DAG.SplitVector(Mask, DL);
1380 DAG.getNode(ISD::VSELECT, DL, LoOpVT, LoMask, LoOp0, LoOp1);
1382 DAG.getNode(ISD::VSELECT, DL, HiOpVT, HiMask, HiOp0, HiOp1);
1384 return DAG.getNode(ISD::CONCAT_VECTORS, DL, Src0VT, LoSelect, HiSelect);
1387 SDValue DAGTypeLegalizer::SplitVecOp_UnaryOp(SDNode *N) {
1388 // The result has a legal vector type, but the input needs splitting.
1389 EVT ResVT = N->getValueType(0);
1392 GetSplitVector(N->getOperand(0), Lo, Hi);
1393 EVT InVT = Lo.getValueType();
1395 EVT OutVT = EVT::getVectorVT(*DAG.getContext(), ResVT.getVectorElementType(),
1396 InVT.getVectorNumElements());
1398 Lo = DAG.getNode(N->getOpcode(), dl, OutVT, Lo);
1399 Hi = DAG.getNode(N->getOpcode(), dl, OutVT, Hi);
1401 return DAG.getNode(ISD::CONCAT_VECTORS, dl, ResVT, Lo, Hi);
1404 SDValue DAGTypeLegalizer::SplitVecOp_BITCAST(SDNode *N) {
1405 // For example, i64 = BITCAST v4i16 on alpha. Typically the vector will
1406 // end up being split all the way down to individual components. Convert the
1407 // split pieces into integers and reassemble.
1409 GetSplitVector(N->getOperand(0), Lo, Hi);
1410 Lo = BitConvertToInteger(Lo);
1411 Hi = BitConvertToInteger(Hi);
1413 if (TLI.isBigEndian())
1416 return DAG.getNode(ISD::BITCAST, SDLoc(N), N->getValueType(0),
1417 JoinIntegers(Lo, Hi));
1420 SDValue DAGTypeLegalizer::SplitVecOp_EXTRACT_SUBVECTOR(SDNode *N) {
1421 // We know that the extracted result type is legal.
1422 EVT SubVT = N->getValueType(0);
1423 SDValue Idx = N->getOperand(1);
1426 GetSplitVector(N->getOperand(0), Lo, Hi);
1428 uint64_t LoElts = Lo.getValueType().getVectorNumElements();
1429 uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
1431 if (IdxVal < LoElts) {
1432 assert(IdxVal + SubVT.getVectorNumElements() <= LoElts &&
1433 "Extracted subvector crosses vector split!");
1434 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, Lo, Idx);
1436 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, Hi,
1437 DAG.getConstant(IdxVal - LoElts, Idx.getValueType()));
1441 SDValue DAGTypeLegalizer::SplitVecOp_EXTRACT_VECTOR_ELT(SDNode *N) {
1442 SDValue Vec = N->getOperand(0);
1443 SDValue Idx = N->getOperand(1);
1444 EVT VecVT = Vec.getValueType();
1446 if (isa<ConstantSDNode>(Idx)) {
1447 uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
1448 assert(IdxVal < VecVT.getVectorNumElements() && "Invalid vector index!");
1451 GetSplitVector(Vec, Lo, Hi);
1453 uint64_t LoElts = Lo.getValueType().getVectorNumElements();
1455 if (IdxVal < LoElts)
1456 return SDValue(DAG.UpdateNodeOperands(N, Lo, Idx), 0);
1457 return SDValue(DAG.UpdateNodeOperands(N, Hi,
1458 DAG.getConstant(IdxVal - LoElts,
1459 Idx.getValueType())), 0);
1462 // See if the target wants to custom expand this node.
1463 if (CustomLowerNode(N, N->getValueType(0), true))
1466 // Store the vector to the stack.
1467 EVT EltVT = VecVT.getVectorElementType();
1469 SDValue StackPtr = DAG.CreateStackTemporary(VecVT);
1470 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Vec, StackPtr,
1471 MachinePointerInfo(), false, false, 0);
1473 // Load back the required element.
1474 StackPtr = GetVectorElementPointer(StackPtr, EltVT, Idx);
1475 return DAG.getExtLoad(ISD::EXTLOAD, dl, N->getValueType(0), Store, StackPtr,
1476 MachinePointerInfo(), EltVT, false, false, false, 0);
1479 SDValue DAGTypeLegalizer::SplitVecOp_MSTORE(MaskedStoreSDNode *N,
1481 SDValue Ch = N->getChain();
1482 SDValue Ptr = N->getBasePtr();
1483 SDValue Mask = N->getMask();
1484 SDValue Data = N->getValue();
1485 EVT MemoryVT = N->getMemoryVT();
1486 unsigned Alignment = N->getOriginalAlignment();
1489 EVT LoMemVT, HiMemVT;
1490 std::tie(LoMemVT, HiMemVT) = DAG.GetSplitDestVTs(MemoryVT);
1492 SDValue DataLo, DataHi;
1493 GetSplitVector(Data, DataLo, DataHi);
1494 SDValue MaskLo, MaskHi;
1495 GetSplitVector(Mask, MaskLo, MaskHi);
1497 // if Alignment is equal to the vector size,
1498 // take the half of it for the second part
1499 unsigned SecondHalfAlignment =
1500 (Alignment == Data->getValueType(0).getSizeInBits()/8) ?
1501 Alignment/2 : Alignment;
1504 MachineMemOperand *MMO = DAG.getMachineFunction().
1505 getMachineMemOperand(N->getPointerInfo(),
1506 MachineMemOperand::MOStore, LoMemVT.getStoreSize(),
1507 Alignment, N->getAAInfo(), N->getRanges());
1509 Lo = DAG.getMaskedStore(Ch, DL, DataLo, Ptr, MaskLo, LoMemVT, MMO,
1510 N->isTruncatingStore());
1512 unsigned IncrementSize = LoMemVT.getSizeInBits()/8;
1513 Ptr = DAG.getNode(ISD::ADD, DL, Ptr.getValueType(), Ptr,
1514 DAG.getConstant(IncrementSize, Ptr.getValueType()));
1516 MMO = DAG.getMachineFunction().
1517 getMachineMemOperand(N->getPointerInfo(),
1518 MachineMemOperand::MOStore, HiMemVT.getStoreSize(),
1519 SecondHalfAlignment, N->getAAInfo(), N->getRanges());
1521 Hi = DAG.getMaskedStore(Ch, DL, DataHi, Ptr, MaskHi, HiMemVT, MMO,
1522 N->isTruncatingStore());
1525 // Build a factor node to remember that this store is independent of the
1527 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Lo, Hi);
1531 SDValue DAGTypeLegalizer::SplitVecOp_STORE(StoreSDNode *N, unsigned OpNo) {
1532 assert(N->isUnindexed() && "Indexed store of vector?");
1533 assert(OpNo == 1 && "Can only split the stored value");
1536 bool isTruncating = N->isTruncatingStore();
1537 SDValue Ch = N->getChain();
1538 SDValue Ptr = N->getBasePtr();
1539 EVT MemoryVT = N->getMemoryVT();
1540 unsigned Alignment = N->getOriginalAlignment();
1541 bool isVol = N->isVolatile();
1542 bool isNT = N->isNonTemporal();
1543 AAMDNodes AAInfo = N->getAAInfo();
1545 GetSplitVector(N->getOperand(1), Lo, Hi);
1547 EVT LoMemVT, HiMemVT;
1548 std::tie(LoMemVT, HiMemVT) = DAG.GetSplitDestVTs(MemoryVT);
1550 unsigned IncrementSize = LoMemVT.getSizeInBits()/8;
1553 Lo = DAG.getTruncStore(Ch, DL, Lo, Ptr, N->getPointerInfo(),
1554 LoMemVT, isVol, isNT, Alignment, AAInfo);
1556 Lo = DAG.getStore(Ch, DL, Lo, Ptr, N->getPointerInfo(),
1557 isVol, isNT, Alignment, AAInfo);
1559 // Increment the pointer to the other half.
1560 Ptr = DAG.getNode(ISD::ADD, DL, Ptr.getValueType(), Ptr,
1561 DAG.getConstant(IncrementSize, Ptr.getValueType()));
1564 Hi = DAG.getTruncStore(Ch, DL, Hi, Ptr,
1565 N->getPointerInfo().getWithOffset(IncrementSize),
1566 HiMemVT, isVol, isNT, Alignment, AAInfo);
1568 Hi = DAG.getStore(Ch, DL, Hi, Ptr,
1569 N->getPointerInfo().getWithOffset(IncrementSize),
1570 isVol, isNT, Alignment, AAInfo);
1572 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Lo, Hi);
1575 SDValue DAGTypeLegalizer::SplitVecOp_CONCAT_VECTORS(SDNode *N) {
1578 // The input operands all must have the same type, and we know the result
1579 // type is valid. Convert this to a buildvector which extracts all the
1581 // TODO: If the input elements are power-two vectors, we could convert this to
1582 // a new CONCAT_VECTORS node with elements that are half-wide.
1583 SmallVector<SDValue, 32> Elts;
1584 EVT EltVT = N->getValueType(0).getVectorElementType();
1585 for (unsigned op = 0, e = N->getNumOperands(); op != e; ++op) {
1586 SDValue Op = N->getOperand(op);
1587 for (unsigned i = 0, e = Op.getValueType().getVectorNumElements();
1589 Elts.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, EltVT,
1590 Op, DAG.getConstant(i, TLI.getVectorIdxTy())));
1595 return DAG.getNode(ISD::BUILD_VECTOR, DL, N->getValueType(0), Elts);
1598 SDValue DAGTypeLegalizer::SplitVecOp_TruncateHelper(SDNode *N,
1599 unsigned TruncateOp) {
1600 // The result type is legal, but the input type is illegal. If splitting
1601 // ends up with the result type of each half still being legal, just
1602 // do that. If, however, that would result in an illegal result type,
1603 // we can try to get more clever with power-two vectors. Specifically,
1604 // split the input type, but also widen the result element size, then
1605 // concatenate the halves and truncate again. For example, consider a target
1606 // where v8i8 is legal and v8i32 is not (ARM, which doesn't have 256-bit
1607 // vectors). To perform a "%res = v8i8 trunc v8i32 %in" we do:
1608 // %inlo = v4i32 extract_subvector %in, 0
1609 // %inhi = v4i32 extract_subvector %in, 4
1610 // %lo16 = v4i16 trunc v4i32 %inlo
1611 // %hi16 = v4i16 trunc v4i32 %inhi
1612 // %in16 = v8i16 concat_vectors v4i16 %lo16, v4i16 %hi16
1613 // %res = v8i8 trunc v8i16 %in16
1615 // Without this transform, the original truncate would end up being
1616 // scalarized, which is pretty much always a last resort.
1617 SDValue InVec = N->getOperand(0);
1618 EVT InVT = InVec->getValueType(0);
1619 EVT OutVT = N->getValueType(0);
1620 unsigned NumElements = OutVT.getVectorNumElements();
1621 // Widening should have already made sure this is a power-two vector
1622 // if we're trying to split it at all. assert() that's true, just in case.
1623 assert(!(NumElements & 1) && "Splitting vector, but not in half!");
1625 unsigned InElementSize = InVT.getVectorElementType().getSizeInBits();
1626 unsigned OutElementSize = OutVT.getVectorElementType().getSizeInBits();
1628 // If the input elements are only 1/2 the width of the result elements,
1629 // just use the normal splitting. Our trick only work if there's room
1630 // to split more than once.
1631 if (InElementSize <= OutElementSize * 2)
1632 return SplitVecOp_UnaryOp(N);
1635 // Extract the halves of the input via extract_subvector.
1636 SDValue InLoVec, InHiVec;
1637 std::tie(InLoVec, InHiVec) = DAG.SplitVector(InVec, DL);
1638 // Truncate them to 1/2 the element size.
1639 EVT HalfElementVT = EVT::getIntegerVT(*DAG.getContext(), InElementSize/2);
1640 EVT HalfVT = EVT::getVectorVT(*DAG.getContext(), HalfElementVT,
1642 SDValue HalfLo = DAG.getNode(N->getOpcode(), DL, HalfVT, InLoVec);
1643 SDValue HalfHi = DAG.getNode(N->getOpcode(), DL, HalfVT, InHiVec);
1644 // Concatenate them to get the full intermediate truncation result.
1645 EVT InterVT = EVT::getVectorVT(*DAG.getContext(), HalfElementVT, NumElements);
1646 SDValue InterVec = DAG.getNode(ISD::CONCAT_VECTORS, DL, InterVT, HalfLo,
1648 // Now finish up by truncating all the way down to the original result
1649 // type. This should normally be something that ends up being legal directly,
1650 // but in theory if a target has very wide vectors and an annoyingly
1651 // restricted set of legal types, this split can chain to build things up.
1652 return DAG.getNode(TruncateOp, DL, OutVT, InterVec);
1655 SDValue DAGTypeLegalizer::SplitVecOp_VSETCC(SDNode *N) {
1656 assert(N->getValueType(0).isVector() &&
1657 N->getOperand(0).getValueType().isVector() &&
1658 "Operand types must be vectors");
1659 // The result has a legal vector type, but the input needs splitting.
1660 SDValue Lo0, Hi0, Lo1, Hi1, LoRes, HiRes;
1662 GetSplitVector(N->getOperand(0), Lo0, Hi0);
1663 GetSplitVector(N->getOperand(1), Lo1, Hi1);
1664 unsigned PartElements = Lo0.getValueType().getVectorNumElements();
1665 EVT PartResVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1, PartElements);
1666 EVT WideResVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1, 2*PartElements);
1668 LoRes = DAG.getNode(ISD::SETCC, DL, PartResVT, Lo0, Lo1, N->getOperand(2));
1669 HiRes = DAG.getNode(ISD::SETCC, DL, PartResVT, Hi0, Hi1, N->getOperand(2));
1670 SDValue Con = DAG.getNode(ISD::CONCAT_VECTORS, DL, WideResVT, LoRes, HiRes);
1671 return PromoteTargetBoolean(Con, N->getValueType(0));
1675 SDValue DAGTypeLegalizer::SplitVecOp_FP_ROUND(SDNode *N) {
1676 // The result has a legal vector type, but the input needs splitting.
1677 EVT ResVT = N->getValueType(0);
1680 GetSplitVector(N->getOperand(0), Lo, Hi);
1681 EVT InVT = Lo.getValueType();
1683 EVT OutVT = EVT::getVectorVT(*DAG.getContext(), ResVT.getVectorElementType(),
1684 InVT.getVectorNumElements());
1686 Lo = DAG.getNode(ISD::FP_ROUND, DL, OutVT, Lo, N->getOperand(1));
1687 Hi = DAG.getNode(ISD::FP_ROUND, DL, OutVT, Hi, N->getOperand(1));
1689 return DAG.getNode(ISD::CONCAT_VECTORS, DL, ResVT, Lo, Hi);
1694 //===----------------------------------------------------------------------===//
1695 // Result Vector Widening
1696 //===----------------------------------------------------------------------===//
1698 void DAGTypeLegalizer::WidenVectorResult(SDNode *N, unsigned ResNo) {
1699 DEBUG(dbgs() << "Widen node result " << ResNo << ": ";
1703 // See if the target wants to custom widen this node.
1704 if (CustomWidenLowerNode(N, N->getValueType(ResNo)))
1707 SDValue Res = SDValue();
1708 switch (N->getOpcode()) {
1711 dbgs() << "WidenVectorResult #" << ResNo << ": ";
1715 llvm_unreachable("Do not know how to widen the result of this operator!");
1717 case ISD::MERGE_VALUES: Res = WidenVecRes_MERGE_VALUES(N, ResNo); break;
1718 case ISD::BITCAST: Res = WidenVecRes_BITCAST(N); break;
1719 case ISD::BUILD_VECTOR: Res = WidenVecRes_BUILD_VECTOR(N); break;
1720 case ISD::CONCAT_VECTORS: Res = WidenVecRes_CONCAT_VECTORS(N); break;
1721 case ISD::CONVERT_RNDSAT: Res = WidenVecRes_CONVERT_RNDSAT(N); break;
1722 case ISD::EXTRACT_SUBVECTOR: Res = WidenVecRes_EXTRACT_SUBVECTOR(N); break;
1723 case ISD::FP_ROUND_INREG: Res = WidenVecRes_InregOp(N); break;
1724 case ISD::INSERT_VECTOR_ELT: Res = WidenVecRes_INSERT_VECTOR_ELT(N); break;
1725 case ISD::LOAD: Res = WidenVecRes_LOAD(N); break;
1726 case ISD::SCALAR_TO_VECTOR: Res = WidenVecRes_SCALAR_TO_VECTOR(N); break;
1727 case ISD::SIGN_EXTEND_INREG: Res = WidenVecRes_InregOp(N); break;
1729 case ISD::SELECT: Res = WidenVecRes_SELECT(N); break;
1730 case ISD::SELECT_CC: Res = WidenVecRes_SELECT_CC(N); break;
1731 case ISD::SETCC: Res = WidenVecRes_SETCC(N); break;
1732 case ISD::UNDEF: Res = WidenVecRes_UNDEF(N); break;
1733 case ISD::VECTOR_SHUFFLE:
1734 Res = WidenVecRes_VECTOR_SHUFFLE(cast<ShuffleVectorSDNode>(N));
1737 Res = WidenVecRes_MLOAD(cast<MaskedLoadSDNode>(N));
1750 Res = WidenVecRes_Binary(N);
1754 case ISD::FCOPYSIGN:
1764 Res = WidenVecRes_BinaryCanTrap(N);
1768 Res = WidenVecRes_POWI(N);
1774 Res = WidenVecRes_Shift(N);
1777 case ISD::ANY_EXTEND:
1778 case ISD::FP_EXTEND:
1780 case ISD::FP_TO_SINT:
1781 case ISD::FP_TO_UINT:
1782 case ISD::SIGN_EXTEND:
1783 case ISD::SINT_TO_FP:
1785 case ISD::UINT_TO_FP:
1786 case ISD::ZERO_EXTEND:
1787 Res = WidenVecRes_Convert(N);
1803 case ISD::FNEARBYINT:
1810 Res = WidenVecRes_Unary(N);
1813 Res = WidenVecRes_Ternary(N);
1817 // If Res is null, the sub-method took care of registering the result.
1819 SetWidenedVector(SDValue(N, ResNo), Res);
1822 SDValue DAGTypeLegalizer::WidenVecRes_Ternary(SDNode *N) {
1823 // Ternary op widening.
1825 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1826 SDValue InOp1 = GetWidenedVector(N->getOperand(0));
1827 SDValue InOp2 = GetWidenedVector(N->getOperand(1));
1828 SDValue InOp3 = GetWidenedVector(N->getOperand(2));
1829 return DAG.getNode(N->getOpcode(), dl, WidenVT, InOp1, InOp2, InOp3);
1832 SDValue DAGTypeLegalizer::WidenVecRes_Binary(SDNode *N) {
1833 // Binary op widening.
1835 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1836 SDValue InOp1 = GetWidenedVector(N->getOperand(0));
1837 SDValue InOp2 = GetWidenedVector(N->getOperand(1));
1838 return DAG.getNode(N->getOpcode(), dl, WidenVT, InOp1, InOp2);
1841 SDValue DAGTypeLegalizer::WidenVecRes_BinaryCanTrap(SDNode *N) {
1842 // Binary op widening for operations that can trap.
1843 unsigned Opcode = N->getOpcode();
1845 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1846 EVT WidenEltVT = WidenVT.getVectorElementType();
1848 unsigned NumElts = VT.getVectorNumElements();
1849 while (!TLI.isTypeLegal(VT) && NumElts != 1) {
1850 NumElts = NumElts / 2;
1851 VT = EVT::getVectorVT(*DAG.getContext(), WidenEltVT, NumElts);
1854 if (NumElts != 1 && !TLI.canOpTrap(N->getOpcode(), VT)) {
1855 // Operation doesn't trap so just widen as normal.
1856 SDValue InOp1 = GetWidenedVector(N->getOperand(0));
1857 SDValue InOp2 = GetWidenedVector(N->getOperand(1));
1858 return DAG.getNode(N->getOpcode(), dl, WidenVT, InOp1, InOp2);
1861 // No legal vector version so unroll the vector operation and then widen.
1863 return DAG.UnrollVectorOp(N, WidenVT.getVectorNumElements());
1865 // Since the operation can trap, apply operation on the original vector.
1867 SDValue InOp1 = GetWidenedVector(N->getOperand(0));
1868 SDValue InOp2 = GetWidenedVector(N->getOperand(1));
1869 unsigned CurNumElts = N->getValueType(0).getVectorNumElements();
1871 SmallVector<SDValue, 16> ConcatOps(CurNumElts);
1872 unsigned ConcatEnd = 0; // Current ConcatOps index.
1873 int Idx = 0; // Current Idx into input vectors.
1875 // NumElts := greatest legal vector size (at most WidenVT)
1876 // while (orig. vector has unhandled elements) {
1877 // take munches of size NumElts from the beginning and add to ConcatOps
1878 // NumElts := next smaller supported vector size or 1
1880 while (CurNumElts != 0) {
1881 while (CurNumElts >= NumElts) {
1882 SDValue EOp1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, InOp1,
1883 DAG.getConstant(Idx, TLI.getVectorIdxTy()));
1884 SDValue EOp2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, InOp2,
1885 DAG.getConstant(Idx, TLI.getVectorIdxTy()));
1886 ConcatOps[ConcatEnd++] = DAG.getNode(Opcode, dl, VT, EOp1, EOp2);
1888 CurNumElts -= NumElts;
1891 NumElts = NumElts / 2;
1892 VT = EVT::getVectorVT(*DAG.getContext(), WidenEltVT, NumElts);
1893 } while (!TLI.isTypeLegal(VT) && NumElts != 1);
1896 for (unsigned i = 0; i != CurNumElts; ++i, ++Idx) {
1897 SDValue EOp1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, WidenEltVT,
1898 InOp1, DAG.getConstant(Idx,
1899 TLI.getVectorIdxTy()));
1900 SDValue EOp2 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, WidenEltVT,
1901 InOp2, DAG.getConstant(Idx,
1902 TLI.getVectorIdxTy()));
1903 ConcatOps[ConcatEnd++] = DAG.getNode(Opcode, dl, WidenEltVT,
1910 // Check to see if we have a single operation with the widen type.
1911 if (ConcatEnd == 1) {
1912 VT = ConcatOps[0].getValueType();
1914 return ConcatOps[0];
1917 // while (Some element of ConcatOps is not of type MaxVT) {
1918 // From the end of ConcatOps, collect elements of the same type and put
1919 // them into an op of the next larger supported type
1921 while (ConcatOps[ConcatEnd-1].getValueType() != MaxVT) {
1922 Idx = ConcatEnd - 1;
1923 VT = ConcatOps[Idx--].getValueType();
1924 while (Idx >= 0 && ConcatOps[Idx].getValueType() == VT)
1927 int NextSize = VT.isVector() ? VT.getVectorNumElements() : 1;
1931 NextVT = EVT::getVectorVT(*DAG.getContext(), WidenEltVT, NextSize);
1932 } while (!TLI.isTypeLegal(NextVT));
1934 if (!VT.isVector()) {
1935 // Scalar type, create an INSERT_VECTOR_ELEMENT of type NextVT
1936 SDValue VecOp = DAG.getUNDEF(NextVT);
1937 unsigned NumToInsert = ConcatEnd - Idx - 1;
1938 for (unsigned i = 0, OpIdx = Idx+1; i < NumToInsert; i++, OpIdx++) {
1939 VecOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, NextVT, VecOp,
1940 ConcatOps[OpIdx], DAG.getConstant(i,
1941 TLI.getVectorIdxTy()));
1943 ConcatOps[Idx+1] = VecOp;
1944 ConcatEnd = Idx + 2;
1946 // Vector type, create a CONCAT_VECTORS of type NextVT
1947 SDValue undefVec = DAG.getUNDEF(VT);
1948 unsigned OpsToConcat = NextSize/VT.getVectorNumElements();
1949 SmallVector<SDValue, 16> SubConcatOps(OpsToConcat);
1950 unsigned RealVals = ConcatEnd - Idx - 1;
1951 unsigned SubConcatEnd = 0;
1952 unsigned SubConcatIdx = Idx + 1;
1953 while (SubConcatEnd < RealVals)
1954 SubConcatOps[SubConcatEnd++] = ConcatOps[++Idx];
1955 while (SubConcatEnd < OpsToConcat)
1956 SubConcatOps[SubConcatEnd++] = undefVec;
1957 ConcatOps[SubConcatIdx] = DAG.getNode(ISD::CONCAT_VECTORS, dl,
1958 NextVT, SubConcatOps);
1959 ConcatEnd = SubConcatIdx + 1;
1963 // Check to see if we have a single operation with the widen type.
1964 if (ConcatEnd == 1) {
1965 VT = ConcatOps[0].getValueType();
1967 return ConcatOps[0];
1970 // add undefs of size MaxVT until ConcatOps grows to length of WidenVT
1971 unsigned NumOps = WidenVT.getVectorNumElements()/MaxVT.getVectorNumElements();
1972 if (NumOps != ConcatEnd ) {
1973 SDValue UndefVal = DAG.getUNDEF(MaxVT);
1974 for (unsigned j = ConcatEnd; j < NumOps; ++j)
1975 ConcatOps[j] = UndefVal;
1977 return DAG.getNode(ISD::CONCAT_VECTORS, dl, WidenVT,
1978 makeArrayRef(ConcatOps.data(), NumOps));
1981 SDValue DAGTypeLegalizer::WidenVecRes_Convert(SDNode *N) {
1982 SDValue InOp = N->getOperand(0);
1985 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1986 unsigned WidenNumElts = WidenVT.getVectorNumElements();
1988 EVT InVT = InOp.getValueType();
1989 EVT InEltVT = InVT.getVectorElementType();
1990 EVT InWidenVT = EVT::getVectorVT(*DAG.getContext(), InEltVT, WidenNumElts);
1992 unsigned Opcode = N->getOpcode();
1993 unsigned InVTNumElts = InVT.getVectorNumElements();
1995 if (getTypeAction(InVT) == TargetLowering::TypeWidenVector) {
1996 InOp = GetWidenedVector(N->getOperand(0));
1997 InVT = InOp.getValueType();
1998 InVTNumElts = InVT.getVectorNumElements();
1999 if (InVTNumElts == WidenNumElts) {
2000 if (N->getNumOperands() == 1)
2001 return DAG.getNode(Opcode, DL, WidenVT, InOp);
2002 return DAG.getNode(Opcode, DL, WidenVT, InOp, N->getOperand(1));
2006 if (TLI.isTypeLegal(InWidenVT)) {
2007 // Because the result and the input are different vector types, widening
2008 // the result could create a legal type but widening the input might make
2009 // it an illegal type that might lead to repeatedly splitting the input
2010 // and then widening it. To avoid this, we widen the input only if
2011 // it results in a legal type.
2012 if (WidenNumElts % InVTNumElts == 0) {
2013 // Widen the input and call convert on the widened input vector.
2014 unsigned NumConcat = WidenNumElts/InVTNumElts;
2015 SmallVector<SDValue, 16> Ops(NumConcat);
2017 SDValue UndefVal = DAG.getUNDEF(InVT);
2018 for (unsigned i = 1; i != NumConcat; ++i)
2020 SDValue InVec = DAG.getNode(ISD::CONCAT_VECTORS, DL, InWidenVT, Ops);
2021 if (N->getNumOperands() == 1)
2022 return DAG.getNode(Opcode, DL, WidenVT, InVec);
2023 return DAG.getNode(Opcode, DL, WidenVT, InVec, N->getOperand(1));
2026 if (InVTNumElts % WidenNumElts == 0) {
2027 SDValue InVal = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, InWidenVT,
2028 InOp, DAG.getConstant(0,
2029 TLI.getVectorIdxTy()));
2030 // Extract the input and convert the shorten input vector.
2031 if (N->getNumOperands() == 1)
2032 return DAG.getNode(Opcode, DL, WidenVT, InVal);
2033 return DAG.getNode(Opcode, DL, WidenVT, InVal, N->getOperand(1));
2037 // Otherwise unroll into some nasty scalar code and rebuild the vector.
2038 SmallVector<SDValue, 16> Ops(WidenNumElts);
2039 EVT EltVT = WidenVT.getVectorElementType();
2040 unsigned MinElts = std::min(InVTNumElts, WidenNumElts);
2042 for (i=0; i < MinElts; ++i) {
2043 SDValue Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, InEltVT, InOp,
2044 DAG.getConstant(i, TLI.getVectorIdxTy()));
2045 if (N->getNumOperands() == 1)
2046 Ops[i] = DAG.getNode(Opcode, DL, EltVT, Val);
2048 Ops[i] = DAG.getNode(Opcode, DL, EltVT, Val, N->getOperand(1));
2051 SDValue UndefVal = DAG.getUNDEF(EltVT);
2052 for (; i < WidenNumElts; ++i)
2055 return DAG.getNode(ISD::BUILD_VECTOR, DL, WidenVT, Ops);
2058 SDValue DAGTypeLegalizer::WidenVecRes_POWI(SDNode *N) {
2059 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2060 SDValue InOp = GetWidenedVector(N->getOperand(0));
2061 SDValue ShOp = N->getOperand(1);
2062 return DAG.getNode(N->getOpcode(), SDLoc(N), WidenVT, InOp, ShOp);
2065 SDValue DAGTypeLegalizer::WidenVecRes_Shift(SDNode *N) {
2066 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2067 SDValue InOp = GetWidenedVector(N->getOperand(0));
2068 SDValue ShOp = N->getOperand(1);
2070 EVT ShVT = ShOp.getValueType();
2071 if (getTypeAction(ShVT) == TargetLowering::TypeWidenVector) {
2072 ShOp = GetWidenedVector(ShOp);
2073 ShVT = ShOp.getValueType();
2075 EVT ShWidenVT = EVT::getVectorVT(*DAG.getContext(),
2076 ShVT.getVectorElementType(),
2077 WidenVT.getVectorNumElements());
2078 if (ShVT != ShWidenVT)
2079 ShOp = ModifyToType(ShOp, ShWidenVT);
2081 return DAG.getNode(N->getOpcode(), SDLoc(N), WidenVT, InOp, ShOp);
2084 SDValue DAGTypeLegalizer::WidenVecRes_Unary(SDNode *N) {
2085 // Unary op widening.
2086 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2087 SDValue InOp = GetWidenedVector(N->getOperand(0));
2088 return DAG.getNode(N->getOpcode(), SDLoc(N), WidenVT, InOp);
2091 SDValue DAGTypeLegalizer::WidenVecRes_InregOp(SDNode *N) {
2092 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2093 EVT ExtVT = EVT::getVectorVT(*DAG.getContext(),
2094 cast<VTSDNode>(N->getOperand(1))->getVT()
2095 .getVectorElementType(),
2096 WidenVT.getVectorNumElements());
2097 SDValue WidenLHS = GetWidenedVector(N->getOperand(0));
2098 return DAG.getNode(N->getOpcode(), SDLoc(N),
2099 WidenVT, WidenLHS, DAG.getValueType(ExtVT));
2102 SDValue DAGTypeLegalizer::WidenVecRes_MERGE_VALUES(SDNode *N, unsigned ResNo) {
2103 SDValue WidenVec = DisintegrateMERGE_VALUES(N, ResNo);
2104 return GetWidenedVector(WidenVec);
2107 SDValue DAGTypeLegalizer::WidenVecRes_BITCAST(SDNode *N) {
2108 SDValue InOp = N->getOperand(0);
2109 EVT InVT = InOp.getValueType();
2110 EVT VT = N->getValueType(0);
2111 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
2114 switch (getTypeAction(InVT)) {
2115 case TargetLowering::TypeLegal:
2117 case TargetLowering::TypePromoteInteger:
2118 // If the incoming type is a vector that is being promoted, then
2119 // we know that the elements are arranged differently and that we
2120 // must perform the conversion using a stack slot.
2121 if (InVT.isVector())
2124 // If the InOp is promoted to the same size, convert it. Otherwise,
2125 // fall out of the switch and widen the promoted input.
2126 InOp = GetPromotedInteger(InOp);
2127 InVT = InOp.getValueType();
2128 if (WidenVT.bitsEq(InVT))
2129 return DAG.getNode(ISD::BITCAST, dl, WidenVT, InOp);
2131 case TargetLowering::TypeSoftenFloat:
2132 case TargetLowering::TypeExpandInteger:
2133 case TargetLowering::TypeExpandFloat:
2134 case TargetLowering::TypeScalarizeVector:
2135 case TargetLowering::TypeSplitVector:
2137 case TargetLowering::TypeWidenVector:
2138 // If the InOp is widened to the same size, convert it. Otherwise, fall
2139 // out of the switch and widen the widened input.
2140 InOp = GetWidenedVector(InOp);
2141 InVT = InOp.getValueType();
2142 if (WidenVT.bitsEq(InVT))
2143 // The input widens to the same size. Convert to the widen value.
2144 return DAG.getNode(ISD::BITCAST, dl, WidenVT, InOp);
2148 unsigned WidenSize = WidenVT.getSizeInBits();
2149 unsigned InSize = InVT.getSizeInBits();
2150 // x86mmx is not an acceptable vector element type, so don't try.
2151 if (WidenSize % InSize == 0 && InVT != MVT::x86mmx) {
2152 // Determine new input vector type. The new input vector type will use
2153 // the same element type (if its a vector) or use the input type as a
2154 // vector. It is the same size as the type to widen to.
2156 unsigned NewNumElts = WidenSize / InSize;
2157 if (InVT.isVector()) {
2158 EVT InEltVT = InVT.getVectorElementType();
2159 NewInVT = EVT::getVectorVT(*DAG.getContext(), InEltVT,
2160 WidenSize / InEltVT.getSizeInBits());
2162 NewInVT = EVT::getVectorVT(*DAG.getContext(), InVT, NewNumElts);
2165 if (TLI.isTypeLegal(NewInVT)) {
2166 // Because the result and the input are different vector types, widening
2167 // the result could create a legal type but widening the input might make
2168 // it an illegal type that might lead to repeatedly splitting the input
2169 // and then widening it. To avoid this, we widen the input only if
2170 // it results in a legal type.
2171 SmallVector<SDValue, 16> Ops(NewNumElts);
2172 SDValue UndefVal = DAG.getUNDEF(InVT);
2174 for (unsigned i = 1; i < NewNumElts; ++i)
2178 if (InVT.isVector())
2179 NewVec = DAG.getNode(ISD::CONCAT_VECTORS, dl, NewInVT, Ops);
2181 NewVec = DAG.getNode(ISD::BUILD_VECTOR, dl, NewInVT, Ops);
2182 return DAG.getNode(ISD::BITCAST, dl, WidenVT, NewVec);
2186 return CreateStackStoreLoad(InOp, WidenVT);
2189 SDValue DAGTypeLegalizer::WidenVecRes_BUILD_VECTOR(SDNode *N) {
2191 // Build a vector with undefined for the new nodes.
2192 EVT VT = N->getValueType(0);
2194 // Integer BUILD_VECTOR operands may be larger than the node's vector element
2195 // type. The UNDEFs need to have the same type as the existing operands.
2196 EVT EltVT = N->getOperand(0).getValueType();
2197 unsigned NumElts = VT.getVectorNumElements();
2199 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
2200 unsigned WidenNumElts = WidenVT.getVectorNumElements();
2202 SmallVector<SDValue, 16> NewOps(N->op_begin(), N->op_end());
2203 assert(WidenNumElts >= NumElts && "Shrinking vector instead of widening!");
2204 NewOps.append(WidenNumElts - NumElts, DAG.getUNDEF(EltVT));
2206 return DAG.getNode(ISD::BUILD_VECTOR, dl, WidenVT, NewOps);
2209 SDValue DAGTypeLegalizer::WidenVecRes_CONCAT_VECTORS(SDNode *N) {
2210 EVT InVT = N->getOperand(0).getValueType();
2211 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2213 unsigned WidenNumElts = WidenVT.getVectorNumElements();
2214 unsigned NumInElts = InVT.getVectorNumElements();
2215 unsigned NumOperands = N->getNumOperands();
2217 bool InputWidened = false; // Indicates we need to widen the input.
2218 if (getTypeAction(InVT) != TargetLowering::TypeWidenVector) {
2219 if (WidenVT.getVectorNumElements() % InVT.getVectorNumElements() == 0) {
2220 // Add undef vectors to widen to correct length.
2221 unsigned NumConcat = WidenVT.getVectorNumElements() /
2222 InVT.getVectorNumElements();
2223 SDValue UndefVal = DAG.getUNDEF(InVT);
2224 SmallVector<SDValue, 16> Ops(NumConcat);
2225 for (unsigned i=0; i < NumOperands; ++i)
2226 Ops[i] = N->getOperand(i);
2227 for (unsigned i = NumOperands; i != NumConcat; ++i)
2229 return DAG.getNode(ISD::CONCAT_VECTORS, dl, WidenVT, Ops);
2232 InputWidened = true;
2233 if (WidenVT == TLI.getTypeToTransformTo(*DAG.getContext(), InVT)) {
2234 // The inputs and the result are widen to the same value.
2236 for (i=1; i < NumOperands; ++i)
2237 if (N->getOperand(i).getOpcode() != ISD::UNDEF)
2240 if (i == NumOperands)
2241 // Everything but the first operand is an UNDEF so just return the
2242 // widened first operand.
2243 return GetWidenedVector(N->getOperand(0));
2245 if (NumOperands == 2) {
2246 // Replace concat of two operands with a shuffle.
2247 SmallVector<int, 16> MaskOps(WidenNumElts, -1);
2248 for (unsigned i = 0; i < NumInElts; ++i) {
2250 MaskOps[i + NumInElts] = i + WidenNumElts;
2252 return DAG.getVectorShuffle(WidenVT, dl,
2253 GetWidenedVector(N->getOperand(0)),
2254 GetWidenedVector(N->getOperand(1)),
2260 // Fall back to use extracts and build vector.
2261 EVT EltVT = WidenVT.getVectorElementType();
2262 SmallVector<SDValue, 16> Ops(WidenNumElts);
2264 for (unsigned i=0; i < NumOperands; ++i) {
2265 SDValue InOp = N->getOperand(i);
2267 InOp = GetWidenedVector(InOp);
2268 for (unsigned j=0; j < NumInElts; ++j)
2269 Ops[Idx++] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, InOp,
2270 DAG.getConstant(j, TLI.getVectorIdxTy()));
2272 SDValue UndefVal = DAG.getUNDEF(EltVT);
2273 for (; Idx < WidenNumElts; ++Idx)
2274 Ops[Idx] = UndefVal;
2275 return DAG.getNode(ISD::BUILD_VECTOR, dl, WidenVT, Ops);
2278 SDValue DAGTypeLegalizer::WidenVecRes_CONVERT_RNDSAT(SDNode *N) {
2280 SDValue InOp = N->getOperand(0);
2281 SDValue RndOp = N->getOperand(3);
2282 SDValue SatOp = N->getOperand(4);
2284 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2285 unsigned WidenNumElts = WidenVT.getVectorNumElements();
2287 EVT InVT = InOp.getValueType();
2288 EVT InEltVT = InVT.getVectorElementType();
2289 EVT InWidenVT = EVT::getVectorVT(*DAG.getContext(), InEltVT, WidenNumElts);
2291 SDValue DTyOp = DAG.getValueType(WidenVT);
2292 SDValue STyOp = DAG.getValueType(InWidenVT);
2293 ISD::CvtCode CvtCode = cast<CvtRndSatSDNode>(N)->getCvtCode();
2295 unsigned InVTNumElts = InVT.getVectorNumElements();
2296 if (getTypeAction(InVT) == TargetLowering::TypeWidenVector) {
2297 InOp = GetWidenedVector(InOp);
2298 InVT = InOp.getValueType();
2299 InVTNumElts = InVT.getVectorNumElements();
2300 if (InVTNumElts == WidenNumElts)
2301 return DAG.getConvertRndSat(WidenVT, dl, InOp, DTyOp, STyOp, RndOp,
2305 if (TLI.isTypeLegal(InWidenVT)) {
2306 // Because the result and the input are different vector types, widening
2307 // the result could create a legal type but widening the input might make
2308 // it an illegal type that might lead to repeatedly splitting the input
2309 // and then widening it. To avoid this, we widen the input only if
2310 // it results in a legal type.
2311 if (WidenNumElts % InVTNumElts == 0) {
2312 // Widen the input and call convert on the widened input vector.
2313 unsigned NumConcat = WidenNumElts/InVTNumElts;
2314 SmallVector<SDValue, 16> Ops(NumConcat);
2316 SDValue UndefVal = DAG.getUNDEF(InVT);
2317 for (unsigned i = 1; i != NumConcat; ++i)
2320 InOp = DAG.getNode(ISD::CONCAT_VECTORS, dl, InWidenVT, Ops);
2321 return DAG.getConvertRndSat(WidenVT, dl, InOp, DTyOp, STyOp, RndOp,
2325 if (InVTNumElts % WidenNumElts == 0) {
2326 // Extract the input and convert the shorten input vector.
2327 InOp = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, InWidenVT, InOp,
2328 DAG.getConstant(0, TLI.getVectorIdxTy()));
2329 return DAG.getConvertRndSat(WidenVT, dl, InOp, DTyOp, STyOp, RndOp,
2334 // Otherwise unroll into some nasty scalar code and rebuild the vector.
2335 SmallVector<SDValue, 16> Ops(WidenNumElts);
2336 EVT EltVT = WidenVT.getVectorElementType();
2337 DTyOp = DAG.getValueType(EltVT);
2338 STyOp = DAG.getValueType(InEltVT);
2340 unsigned MinElts = std::min(InVTNumElts, WidenNumElts);
2342 for (i=0; i < MinElts; ++i) {
2343 SDValue ExtVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, InEltVT, InOp,
2344 DAG.getConstant(i, TLI.getVectorIdxTy()));
2345 Ops[i] = DAG.getConvertRndSat(WidenVT, dl, ExtVal, DTyOp, STyOp, RndOp,
2349 SDValue UndefVal = DAG.getUNDEF(EltVT);
2350 for (; i < WidenNumElts; ++i)
2353 return DAG.getNode(ISD::BUILD_VECTOR, dl, WidenVT, Ops);
2356 SDValue DAGTypeLegalizer::WidenVecRes_EXTRACT_SUBVECTOR(SDNode *N) {
2357 EVT VT = N->getValueType(0);
2358 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
2359 unsigned WidenNumElts = WidenVT.getVectorNumElements();
2360 SDValue InOp = N->getOperand(0);
2361 SDValue Idx = N->getOperand(1);
2364 if (getTypeAction(InOp.getValueType()) == TargetLowering::TypeWidenVector)
2365 InOp = GetWidenedVector(InOp);
2367 EVT InVT = InOp.getValueType();
2369 // Check if we can just return the input vector after widening.
2370 uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
2371 if (IdxVal == 0 && InVT == WidenVT)
2374 // Check if we can extract from the vector.
2375 unsigned InNumElts = InVT.getVectorNumElements();
2376 if (IdxVal % WidenNumElts == 0 && IdxVal + WidenNumElts < InNumElts)
2377 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, WidenVT, InOp, Idx);
2379 // We could try widening the input to the right length but for now, extract
2380 // the original elements, fill the rest with undefs and build a vector.
2381 SmallVector<SDValue, 16> Ops(WidenNumElts);
2382 EVT EltVT = VT.getVectorElementType();
2383 unsigned NumElts = VT.getVectorNumElements();
2385 for (i=0; i < NumElts; ++i)
2386 Ops[i] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, InOp,
2387 DAG.getConstant(IdxVal+i, TLI.getVectorIdxTy()));
2389 SDValue UndefVal = DAG.getUNDEF(EltVT);
2390 for (; i < WidenNumElts; ++i)
2392 return DAG.getNode(ISD::BUILD_VECTOR, dl, WidenVT, Ops);
2395 SDValue DAGTypeLegalizer::WidenVecRes_INSERT_VECTOR_ELT(SDNode *N) {
2396 SDValue InOp = GetWidenedVector(N->getOperand(0));
2397 return DAG.getNode(ISD::INSERT_VECTOR_ELT, SDLoc(N),
2398 InOp.getValueType(), InOp,
2399 N->getOperand(1), N->getOperand(2));
2402 SDValue DAGTypeLegalizer::WidenVecRes_LOAD(SDNode *N) {
2403 LoadSDNode *LD = cast<LoadSDNode>(N);
2404 ISD::LoadExtType ExtType = LD->getExtensionType();
2407 SmallVector<SDValue, 16> LdChain; // Chain for the series of load
2408 if (ExtType != ISD::NON_EXTLOAD)
2409 Result = GenWidenVectorExtLoads(LdChain, LD, ExtType);
2411 Result = GenWidenVectorLoads(LdChain, LD);
2413 // If we generate a single load, we can use that for the chain. Otherwise,
2414 // build a factor node to remember the multiple loads are independent and
2417 if (LdChain.size() == 1)
2418 NewChain = LdChain[0];
2420 NewChain = DAG.getNode(ISD::TokenFactor, SDLoc(LD), MVT::Other, LdChain);
2422 // Modified the chain - switch anything that used the old chain to use
2424 ReplaceValueWith(SDValue(N, 1), NewChain);
2429 SDValue DAGTypeLegalizer::WidenVecRes_MLOAD(MaskedLoadSDNode *N) {
2431 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(),N->getValueType(0));
2432 SDValue Mask = N->getMask();
2433 EVT MaskVT = Mask.getValueType();
2434 SDValue Src0 = GetWidenedVector(N->getSrc0());
2435 ISD::LoadExtType ExtType = N->getExtensionType();
2438 if (getTypeAction(MaskVT) == TargetLowering::TypeWidenVector)
2439 Mask = GetWidenedVector(Mask);
2441 EVT BoolVT = getSetCCResultType(WidenVT);
2443 // We can't use ModifyToType() because we should fill the mask with
2445 unsigned WidenNumElts = BoolVT.getVectorNumElements();
2446 unsigned MaskNumElts = MaskVT.getVectorNumElements();
2448 unsigned NumConcat = WidenNumElts / MaskNumElts;
2449 SmallVector<SDValue, 16> Ops(NumConcat);
2450 SDValue ZeroVal = DAG.getConstant(0, MaskVT);
2452 for (unsigned i = 1; i != NumConcat; ++i)
2455 Mask = DAG.getNode(ISD::CONCAT_VECTORS, dl, BoolVT, Ops);
2458 SDValue Res = DAG.getMaskedLoad(WidenVT, dl, N->getChain(), N->getBasePtr(),
2459 Mask, Src0, N->getMemoryVT(),
2460 N->getMemOperand(), ExtType);
2461 // Legalized the chain result - switch anything that used the old chain to
2463 ReplaceValueWith(SDValue(N, 1), Res.getValue(1));
2467 SDValue DAGTypeLegalizer::WidenVecRes_SCALAR_TO_VECTOR(SDNode *N) {
2468 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2469 return DAG.getNode(ISD::SCALAR_TO_VECTOR, SDLoc(N),
2470 WidenVT, N->getOperand(0));
2473 SDValue DAGTypeLegalizer::WidenVecRes_SELECT(SDNode *N) {
2474 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2475 unsigned WidenNumElts = WidenVT.getVectorNumElements();
2477 SDValue Cond1 = N->getOperand(0);
2478 EVT CondVT = Cond1.getValueType();
2479 if (CondVT.isVector()) {
2480 EVT CondEltVT = CondVT.getVectorElementType();
2481 EVT CondWidenVT = EVT::getVectorVT(*DAG.getContext(),
2482 CondEltVT, WidenNumElts);
2483 if (getTypeAction(CondVT) == TargetLowering::TypeWidenVector)
2484 Cond1 = GetWidenedVector(Cond1);
2486 // If we have to split the condition there is no point in widening the
2487 // select. This would result in an cycle of widening the select ->
2488 // widening the condition operand -> splitting the condition operand ->
2489 // splitting the select -> widening the select. Instead split this select
2490 // further and widen the resulting type.
2491 if (getTypeAction(CondVT) == TargetLowering::TypeSplitVector) {
2492 SDValue SplitSelect = SplitVecOp_VSELECT(N, 0);
2493 SDValue Res = ModifyToType(SplitSelect, WidenVT);
2497 if (Cond1.getValueType() != CondWidenVT)
2498 Cond1 = ModifyToType(Cond1, CondWidenVT);
2501 SDValue InOp1 = GetWidenedVector(N->getOperand(1));
2502 SDValue InOp2 = GetWidenedVector(N->getOperand(2));
2503 assert(InOp1.getValueType() == WidenVT && InOp2.getValueType() == WidenVT);
2504 return DAG.getNode(N->getOpcode(), SDLoc(N),
2505 WidenVT, Cond1, InOp1, InOp2);
2508 SDValue DAGTypeLegalizer::WidenVecRes_SELECT_CC(SDNode *N) {
2509 SDValue InOp1 = GetWidenedVector(N->getOperand(2));
2510 SDValue InOp2 = GetWidenedVector(N->getOperand(3));
2511 return DAG.getNode(ISD::SELECT_CC, SDLoc(N),
2512 InOp1.getValueType(), N->getOperand(0),
2513 N->getOperand(1), InOp1, InOp2, N->getOperand(4));
2516 SDValue DAGTypeLegalizer::WidenVecRes_SETCC(SDNode *N) {
2517 assert(N->getValueType(0).isVector() ==
2518 N->getOperand(0).getValueType().isVector() &&
2519 "Scalar/Vector type mismatch");
2520 if (N->getValueType(0).isVector()) return WidenVecRes_VSETCC(N);
2522 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2523 SDValue InOp1 = GetWidenedVector(N->getOperand(0));
2524 SDValue InOp2 = GetWidenedVector(N->getOperand(1));
2525 return DAG.getNode(ISD::SETCC, SDLoc(N), WidenVT,
2526 InOp1, InOp2, N->getOperand(2));
2529 SDValue DAGTypeLegalizer::WidenVecRes_UNDEF(SDNode *N) {
2530 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2531 return DAG.getUNDEF(WidenVT);
2534 SDValue DAGTypeLegalizer::WidenVecRes_VECTOR_SHUFFLE(ShuffleVectorSDNode *N) {
2535 EVT VT = N->getValueType(0);
2538 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
2539 unsigned NumElts = VT.getVectorNumElements();
2540 unsigned WidenNumElts = WidenVT.getVectorNumElements();
2542 SDValue InOp1 = GetWidenedVector(N->getOperand(0));
2543 SDValue InOp2 = GetWidenedVector(N->getOperand(1));
2545 // Adjust mask based on new input vector length.
2546 SmallVector<int, 16> NewMask;
2547 for (unsigned i = 0; i != NumElts; ++i) {
2548 int Idx = N->getMaskElt(i);
2549 if (Idx < (int)NumElts)
2550 NewMask.push_back(Idx);
2552 NewMask.push_back(Idx - NumElts + WidenNumElts);
2554 for (unsigned i = NumElts; i != WidenNumElts; ++i)
2555 NewMask.push_back(-1);
2556 return DAG.getVectorShuffle(WidenVT, dl, InOp1, InOp2, &NewMask[0]);
2559 SDValue DAGTypeLegalizer::WidenVecRes_VSETCC(SDNode *N) {
2560 assert(N->getValueType(0).isVector() &&
2561 N->getOperand(0).getValueType().isVector() &&
2562 "Operands must be vectors");
2563 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2564 unsigned WidenNumElts = WidenVT.getVectorNumElements();
2566 SDValue InOp1 = N->getOperand(0);
2567 EVT InVT = InOp1.getValueType();
2568 assert(InVT.isVector() && "can not widen non-vector type");
2569 EVT WidenInVT = EVT::getVectorVT(*DAG.getContext(),
2570 InVT.getVectorElementType(), WidenNumElts);
2572 // The input and output types often differ here, and it could be that while
2573 // we'd prefer to widen the result type, the input operands have been split.
2574 // In this case, we also need to split the result of this node as well.
2575 if (getTypeAction(InVT) == TargetLowering::TypeSplitVector) {
2576 SDValue SplitVSetCC = SplitVecOp_VSETCC(N);
2577 SDValue Res = ModifyToType(SplitVSetCC, WidenVT);
2581 InOp1 = GetWidenedVector(InOp1);
2582 SDValue InOp2 = GetWidenedVector(N->getOperand(1));
2584 // Assume that the input and output will be widen appropriately. If not,
2585 // we will have to unroll it at some point.
2586 assert(InOp1.getValueType() == WidenInVT &&
2587 InOp2.getValueType() == WidenInVT &&
2588 "Input not widened to expected type!");
2590 return DAG.getNode(ISD::SETCC, SDLoc(N),
2591 WidenVT, InOp1, InOp2, N->getOperand(2));
2595 //===----------------------------------------------------------------------===//
2596 // Widen Vector Operand
2597 //===----------------------------------------------------------------------===//
2598 bool DAGTypeLegalizer::WidenVectorOperand(SDNode *N, unsigned OpNo) {
2599 DEBUG(dbgs() << "Widen node operand " << OpNo << ": ";
2602 SDValue Res = SDValue();
2604 // See if the target wants to custom widen this node.
2605 if (CustomLowerNode(N, N->getOperand(OpNo).getValueType(), false))
2608 switch (N->getOpcode()) {
2611 dbgs() << "WidenVectorOperand op #" << OpNo << ": ";
2615 llvm_unreachable("Do not know how to widen this operator's operand!");
2617 case ISD::BITCAST: Res = WidenVecOp_BITCAST(N); break;
2618 case ISD::CONCAT_VECTORS: Res = WidenVecOp_CONCAT_VECTORS(N); break;
2619 case ISD::EXTRACT_SUBVECTOR: Res = WidenVecOp_EXTRACT_SUBVECTOR(N); break;
2620 case ISD::EXTRACT_VECTOR_ELT: Res = WidenVecOp_EXTRACT_VECTOR_ELT(N); break;
2621 case ISD::STORE: Res = WidenVecOp_STORE(N); break;
2622 case ISD::MSTORE: Res = WidenVecOp_MSTORE(N, OpNo); break;
2623 case ISD::SETCC: Res = WidenVecOp_SETCC(N); break;
2625 case ISD::ANY_EXTEND:
2626 case ISD::SIGN_EXTEND:
2627 case ISD::ZERO_EXTEND:
2628 Res = WidenVecOp_EXTEND(N);
2631 case ISD::FP_EXTEND:
2632 case ISD::FP_TO_SINT:
2633 case ISD::FP_TO_UINT:
2634 case ISD::SINT_TO_FP:
2635 case ISD::UINT_TO_FP:
2637 Res = WidenVecOp_Convert(N);
2641 // If Res is null, the sub-method took care of registering the result.
2642 if (!Res.getNode()) return false;
2644 // If the result is N, the sub-method updated N in place. Tell the legalizer
2646 if (Res.getNode() == N)
2650 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 &&
2651 "Invalid operand expansion");
2653 ReplaceValueWith(SDValue(N, 0), Res);
2657 SDValue DAGTypeLegalizer::WidenVecOp_EXTEND(SDNode *N) {
2659 EVT VT = N->getValueType(0);
2661 SDValue InOp = N->getOperand(0);
2662 // If some legalization strategy other than widening is used on the operand,
2663 // we can't safely assume that just extending the low lanes is the correct
2665 if (getTypeAction(InOp.getValueType()) != TargetLowering::TypeWidenVector)
2666 return WidenVecOp_Convert(N);
2667 InOp = GetWidenedVector(InOp);
2668 assert(VT.getVectorNumElements() <
2669 InOp.getValueType().getVectorNumElements() &&
2670 "Input wasn't widened!");
2672 // We may need to further widen the operand until it has the same total
2673 // vector size as the result.
2674 EVT InVT = InOp.getValueType();
2675 if (InVT.getSizeInBits() != VT.getSizeInBits()) {
2676 EVT InEltVT = InVT.getVectorElementType();
2677 for (int i = MVT::FIRST_VECTOR_VALUETYPE, e = MVT::LAST_VECTOR_VALUETYPE; i < e; ++i) {
2678 EVT FixedVT = (MVT::SimpleValueType)i;
2679 EVT FixedEltVT = FixedVT.getVectorElementType();
2680 if (TLI.isTypeLegal(FixedVT) &&
2681 FixedVT.getSizeInBits() == VT.getSizeInBits() &&
2682 FixedEltVT == InEltVT) {
2683 assert(FixedVT.getVectorNumElements() >= VT.getVectorNumElements() &&
2684 "Not enough elements in the fixed type for the operand!");
2685 assert(FixedVT.getVectorNumElements() != InVT.getVectorNumElements() &&
2686 "We can't have the same type as we started with!");
2687 if (FixedVT.getVectorNumElements() > InVT.getVectorNumElements())
2688 InOp = DAG.getNode(ISD::INSERT_SUBVECTOR, DL, FixedVT,
2689 DAG.getUNDEF(FixedVT), InOp,
2690 DAG.getConstant(0, TLI.getVectorIdxTy()));
2692 InOp = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, FixedVT, InOp,
2693 DAG.getConstant(0, TLI.getVectorIdxTy()));
2697 InVT = InOp.getValueType();
2698 if (InVT.getSizeInBits() != VT.getSizeInBits())
2699 // We couldn't find a legal vector type that was a widening of the input
2700 // and could be extended in-register to the result type, so we have to
2702 return WidenVecOp_Convert(N);
2705 // Use special DAG nodes to represent the operation of extending the
2707 switch (N->getOpcode()) {
2709 llvm_unreachable("Extend legalization on on extend operation!");
2710 case ISD::ANY_EXTEND:
2711 return DAG.getAnyExtendVectorInReg(InOp, DL, VT);
2712 case ISD::SIGN_EXTEND:
2713 return DAG.getSignExtendVectorInReg(InOp, DL, VT);
2714 case ISD::ZERO_EXTEND:
2715 return DAG.getZeroExtendVectorInReg(InOp, DL, VT);
2719 SDValue DAGTypeLegalizer::WidenVecOp_Convert(SDNode *N) {
2720 // Since the result is legal and the input is illegal, it is unlikely
2721 // that we can fix the input to a legal type so unroll the convert
2722 // into some scalar code and create a nasty build vector.
2723 EVT VT = N->getValueType(0);
2724 EVT EltVT = VT.getVectorElementType();
2726 unsigned NumElts = VT.getVectorNumElements();
2727 SDValue InOp = N->getOperand(0);
2728 if (getTypeAction(InOp.getValueType()) == TargetLowering::TypeWidenVector)
2729 InOp = GetWidenedVector(InOp);
2730 EVT InVT = InOp.getValueType();
2731 EVT InEltVT = InVT.getVectorElementType();
2733 unsigned Opcode = N->getOpcode();
2734 SmallVector<SDValue, 16> Ops(NumElts);
2735 for (unsigned i=0; i < NumElts; ++i)
2736 Ops[i] = DAG.getNode(Opcode, dl, EltVT,
2737 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, InEltVT, InOp,
2738 DAG.getConstant(i, TLI.getVectorIdxTy())));
2740 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
2743 SDValue DAGTypeLegalizer::WidenVecOp_BITCAST(SDNode *N) {
2744 EVT VT = N->getValueType(0);
2745 SDValue InOp = GetWidenedVector(N->getOperand(0));
2746 EVT InWidenVT = InOp.getValueType();
2749 // Check if we can convert between two legal vector types and extract.
2750 unsigned InWidenSize = InWidenVT.getSizeInBits();
2751 unsigned Size = VT.getSizeInBits();
2752 // x86mmx is not an acceptable vector element type, so don't try.
2753 if (InWidenSize % Size == 0 && !VT.isVector() && VT != MVT::x86mmx) {
2754 unsigned NewNumElts = InWidenSize / Size;
2755 EVT NewVT = EVT::getVectorVT(*DAG.getContext(), VT, NewNumElts);
2756 if (TLI.isTypeLegal(NewVT)) {
2757 SDValue BitOp = DAG.getNode(ISD::BITCAST, dl, NewVT, InOp);
2758 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, BitOp,
2759 DAG.getConstant(0, TLI.getVectorIdxTy()));
2763 return CreateStackStoreLoad(InOp, VT);
2766 SDValue DAGTypeLegalizer::WidenVecOp_CONCAT_VECTORS(SDNode *N) {
2767 // If the input vector is not legal, it is likely that we will not find a
2768 // legal vector of the same size. Replace the concatenate vector with a
2769 // nasty build vector.
2770 EVT VT = N->getValueType(0);
2771 EVT EltVT = VT.getVectorElementType();
2773 unsigned NumElts = VT.getVectorNumElements();
2774 SmallVector<SDValue, 16> Ops(NumElts);
2776 EVT InVT = N->getOperand(0).getValueType();
2777 unsigned NumInElts = InVT.getVectorNumElements();
2780 unsigned NumOperands = N->getNumOperands();
2781 for (unsigned i=0; i < NumOperands; ++i) {
2782 SDValue InOp = N->getOperand(i);
2783 if (getTypeAction(InOp.getValueType()) == TargetLowering::TypeWidenVector)
2784 InOp = GetWidenedVector(InOp);
2785 for (unsigned j=0; j < NumInElts; ++j)
2786 Ops[Idx++] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, InOp,
2787 DAG.getConstant(j, TLI.getVectorIdxTy()));
2789 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
2792 SDValue DAGTypeLegalizer::WidenVecOp_EXTRACT_SUBVECTOR(SDNode *N) {
2793 SDValue InOp = GetWidenedVector(N->getOperand(0));
2794 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, SDLoc(N),
2795 N->getValueType(0), InOp, N->getOperand(1));
2798 SDValue DAGTypeLegalizer::WidenVecOp_EXTRACT_VECTOR_ELT(SDNode *N) {
2799 SDValue InOp = GetWidenedVector(N->getOperand(0));
2800 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SDLoc(N),
2801 N->getValueType(0), InOp, N->getOperand(1));
2804 SDValue DAGTypeLegalizer::WidenVecOp_STORE(SDNode *N) {
2805 // We have to widen the value but we want only to store the original
2807 StoreSDNode *ST = cast<StoreSDNode>(N);
2809 SmallVector<SDValue, 16> StChain;
2810 if (ST->isTruncatingStore())
2811 GenWidenVectorTruncStores(StChain, ST);
2813 GenWidenVectorStores(StChain, ST);
2815 if (StChain.size() == 1)
2818 return DAG.getNode(ISD::TokenFactor, SDLoc(ST), MVT::Other, StChain);
2821 SDValue DAGTypeLegalizer::WidenVecOp_MSTORE(SDNode *N, unsigned OpNo) {
2822 MaskedStoreSDNode *MST = cast<MaskedStoreSDNode>(N);
2823 SDValue Mask = MST->getMask();
2824 EVT MaskVT = Mask.getValueType();
2825 SDValue StVal = MST->getValue();
2827 SDValue WideVal = GetWidenedVector(StVal);
2830 if (OpNo == 2 || getTypeAction(MaskVT) == TargetLowering::TypeWidenVector)
2831 Mask = GetWidenedVector(Mask);
2833 // The mask should be widened as well
2834 EVT BoolVT = getSetCCResultType(WideVal.getValueType());
2835 // We can't use ModifyToType() because we should fill the mask with
2837 unsigned WidenNumElts = BoolVT.getVectorNumElements();
2838 unsigned MaskNumElts = MaskVT.getVectorNumElements();
2840 unsigned NumConcat = WidenNumElts / MaskNumElts;
2841 SmallVector<SDValue, 16> Ops(NumConcat);
2842 SDValue ZeroVal = DAG.getConstant(0, MaskVT);
2844 for (unsigned i = 1; i != NumConcat; ++i)
2847 Mask = DAG.getNode(ISD::CONCAT_VECTORS, dl, BoolVT, Ops);
2849 assert(Mask.getValueType().getVectorNumElements() ==
2850 WideVal.getValueType().getVectorNumElements() &&
2851 "Mask and data vectors should have the same number of elements");
2852 return DAG.getMaskedStore(MST->getChain(), dl, WideVal, MST->getBasePtr(),
2853 Mask, MST->getMemoryVT(), MST->getMemOperand(),
2857 SDValue DAGTypeLegalizer::WidenVecOp_SETCC(SDNode *N) {
2858 SDValue InOp0 = GetWidenedVector(N->getOperand(0));
2859 SDValue InOp1 = GetWidenedVector(N->getOperand(1));
2862 // WARNING: In this code we widen the compare instruction with garbage.
2863 // This garbage may contain denormal floats which may be slow. Is this a real
2864 // concern ? Should we zero the unused lanes if this is a float compare ?
2866 // Get a new SETCC node to compare the newly widened operands.
2867 // Only some of the compared elements are legal.
2868 EVT SVT = TLI.getSetCCResultType(*DAG.getContext(), InOp0.getValueType());
2869 SDValue WideSETCC = DAG.getNode(ISD::SETCC, SDLoc(N),
2870 SVT, InOp0, InOp1, N->getOperand(2));
2872 // Extract the needed results from the result vector.
2873 EVT ResVT = EVT::getVectorVT(*DAG.getContext(),
2874 SVT.getVectorElementType(),
2875 N->getValueType(0).getVectorNumElements());
2876 SDValue CC = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl,
2877 ResVT, WideSETCC, DAG.getConstant(0,
2878 TLI.getVectorIdxTy()));
2880 return PromoteTargetBoolean(CC, N->getValueType(0));
2884 //===----------------------------------------------------------------------===//
2885 // Vector Widening Utilities
2886 //===----------------------------------------------------------------------===//
2888 // Utility function to find the type to chop up a widen vector for load/store
2889 // TLI: Target lowering used to determine legal types.
2890 // Width: Width left need to load/store.
2891 // WidenVT: The widen vector type to load to/store from
2892 // Align: If 0, don't allow use of a wider type
2893 // WidenEx: If Align is not 0, the amount additional we can load/store from.
2895 static EVT FindMemType(SelectionDAG& DAG, const TargetLowering &TLI,
2896 unsigned Width, EVT WidenVT,
2897 unsigned Align = 0, unsigned WidenEx = 0) {
2898 EVT WidenEltVT = WidenVT.getVectorElementType();
2899 unsigned WidenWidth = WidenVT.getSizeInBits();
2900 unsigned WidenEltWidth = WidenEltVT.getSizeInBits();
2901 unsigned AlignInBits = Align*8;
2903 // If we have one element to load/store, return it.
2904 EVT RetVT = WidenEltVT;
2905 if (Width == WidenEltWidth)
2908 // See if there is larger legal integer than the element type to load/store
2910 for (VT = (unsigned)MVT::LAST_INTEGER_VALUETYPE;
2911 VT >= (unsigned)MVT::FIRST_INTEGER_VALUETYPE; --VT) {
2912 EVT MemVT((MVT::SimpleValueType) VT);
2913 unsigned MemVTWidth = MemVT.getSizeInBits();
2914 if (MemVT.getSizeInBits() <= WidenEltWidth)
2916 if (TLI.isTypeLegal(MemVT) && (WidenWidth % MemVTWidth) == 0 &&
2917 isPowerOf2_32(WidenWidth / MemVTWidth) &&
2918 (MemVTWidth <= Width ||
2919 (Align!=0 && MemVTWidth<=AlignInBits && MemVTWidth<=Width+WidenEx))) {
2925 // See if there is a larger vector type to load/store that has the same vector
2926 // element type and is evenly divisible with the WidenVT.
2927 for (VT = (unsigned)MVT::LAST_VECTOR_VALUETYPE;
2928 VT >= (unsigned)MVT::FIRST_VECTOR_VALUETYPE; --VT) {
2929 EVT MemVT = (MVT::SimpleValueType) VT;
2930 unsigned MemVTWidth = MemVT.getSizeInBits();
2931 if (TLI.isTypeLegal(MemVT) && WidenEltVT == MemVT.getVectorElementType() &&
2932 (WidenWidth % MemVTWidth) == 0 &&
2933 isPowerOf2_32(WidenWidth / MemVTWidth) &&
2934 (MemVTWidth <= Width ||
2935 (Align!=0 && MemVTWidth<=AlignInBits && MemVTWidth<=Width+WidenEx))) {
2936 if (RetVT.getSizeInBits() < MemVTWidth || MemVT == WidenVT)
2944 // Builds a vector type from scalar loads
2945 // VecTy: Resulting Vector type
2946 // LDOps: Load operators to build a vector type
2947 // [Start,End) the list of loads to use.
2948 static SDValue BuildVectorFromScalar(SelectionDAG& DAG, EVT VecTy,
2949 SmallVectorImpl<SDValue> &LdOps,
2950 unsigned Start, unsigned End) {
2951 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2952 SDLoc dl(LdOps[Start]);
2953 EVT LdTy = LdOps[Start].getValueType();
2954 unsigned Width = VecTy.getSizeInBits();
2955 unsigned NumElts = Width / LdTy.getSizeInBits();
2956 EVT NewVecVT = EVT::getVectorVT(*DAG.getContext(), LdTy, NumElts);
2959 SDValue VecOp = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, NewVecVT,LdOps[Start]);
2961 for (unsigned i = Start + 1; i != End; ++i) {
2962 EVT NewLdTy = LdOps[i].getValueType();
2963 if (NewLdTy != LdTy) {
2964 NumElts = Width / NewLdTy.getSizeInBits();
2965 NewVecVT = EVT::getVectorVT(*DAG.getContext(), NewLdTy, NumElts);
2966 VecOp = DAG.getNode(ISD::BITCAST, dl, NewVecVT, VecOp);
2967 // Readjust position and vector position based on new load type
2968 Idx = Idx * LdTy.getSizeInBits() / NewLdTy.getSizeInBits();
2971 VecOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, NewVecVT, VecOp, LdOps[i],
2972 DAG.getConstant(Idx++, TLI.getVectorIdxTy()));
2974 return DAG.getNode(ISD::BITCAST, dl, VecTy, VecOp);
2977 SDValue DAGTypeLegalizer::GenWidenVectorLoads(SmallVectorImpl<SDValue> &LdChain,
2979 // The strategy assumes that we can efficiently load powers of two widths.
2980 // The routines chops the vector into the largest vector loads with the same
2981 // element type or scalar loads and then recombines it to the widen vector
2983 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(),LD->getValueType(0));
2984 unsigned WidenWidth = WidenVT.getSizeInBits();
2985 EVT LdVT = LD->getMemoryVT();
2987 assert(LdVT.isVector() && WidenVT.isVector());
2988 assert(LdVT.getVectorElementType() == WidenVT.getVectorElementType());
2991 SDValue Chain = LD->getChain();
2992 SDValue BasePtr = LD->getBasePtr();
2993 unsigned Align = LD->getAlignment();
2994 bool isVolatile = LD->isVolatile();
2995 bool isNonTemporal = LD->isNonTemporal();
2996 bool isInvariant = LD->isInvariant();
2997 AAMDNodes AAInfo = LD->getAAInfo();
2999 int LdWidth = LdVT.getSizeInBits();
3000 int WidthDiff = WidenWidth - LdWidth; // Difference
3001 unsigned LdAlign = (isVolatile) ? 0 : Align; // Allow wider loads
3003 // Find the vector type that can load from.
3004 EVT NewVT = FindMemType(DAG, TLI, LdWidth, WidenVT, LdAlign, WidthDiff);
3005 int NewVTWidth = NewVT.getSizeInBits();
3006 SDValue LdOp = DAG.getLoad(NewVT, dl, Chain, BasePtr, LD->getPointerInfo(),
3007 isVolatile, isNonTemporal, isInvariant, Align,
3009 LdChain.push_back(LdOp.getValue(1));
3011 // Check if we can load the element with one instruction
3012 if (LdWidth <= NewVTWidth) {
3013 if (!NewVT.isVector()) {
3014 unsigned NumElts = WidenWidth / NewVTWidth;
3015 EVT NewVecVT = EVT::getVectorVT(*DAG.getContext(), NewVT, NumElts);
3016 SDValue VecOp = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, NewVecVT, LdOp);
3017 return DAG.getNode(ISD::BITCAST, dl, WidenVT, VecOp);
3019 if (NewVT == WidenVT)
3022 assert(WidenWidth % NewVTWidth == 0);
3023 unsigned NumConcat = WidenWidth / NewVTWidth;
3024 SmallVector<SDValue, 16> ConcatOps(NumConcat);
3025 SDValue UndefVal = DAG.getUNDEF(NewVT);
3026 ConcatOps[0] = LdOp;
3027 for (unsigned i = 1; i != NumConcat; ++i)
3028 ConcatOps[i] = UndefVal;
3029 return DAG.getNode(ISD::CONCAT_VECTORS, dl, WidenVT, ConcatOps);
3032 // Load vector by using multiple loads from largest vector to scalar
3033 SmallVector<SDValue, 16> LdOps;
3034 LdOps.push_back(LdOp);
3036 LdWidth -= NewVTWidth;
3037 unsigned Offset = 0;
3039 while (LdWidth > 0) {
3040 unsigned Increment = NewVTWidth / 8;
3041 Offset += Increment;
3042 BasePtr = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(), BasePtr,
3043 DAG.getConstant(Increment, BasePtr.getValueType()));
3046 if (LdWidth < NewVTWidth) {
3047 // Our current type we are using is too large, find a better size
3048 NewVT = FindMemType(DAG, TLI, LdWidth, WidenVT, LdAlign, WidthDiff);
3049 NewVTWidth = NewVT.getSizeInBits();
3050 L = DAG.getLoad(NewVT, dl, Chain, BasePtr,
3051 LD->getPointerInfo().getWithOffset(Offset), isVolatile,
3052 isNonTemporal, isInvariant, MinAlign(Align, Increment),
3054 LdChain.push_back(L.getValue(1));
3055 if (L->getValueType(0).isVector()) {
3056 SmallVector<SDValue, 16> Loads;
3058 unsigned size = L->getValueSizeInBits(0);
3059 while (size < LdOp->getValueSizeInBits(0)) {
3060 Loads.push_back(DAG.getUNDEF(L->getValueType(0)));
3061 size += L->getValueSizeInBits(0);
3063 L = DAG.getNode(ISD::CONCAT_VECTORS, dl, LdOp->getValueType(0), Loads);
3066 L = DAG.getLoad(NewVT, dl, Chain, BasePtr,
3067 LD->getPointerInfo().getWithOffset(Offset), isVolatile,
3068 isNonTemporal, isInvariant, MinAlign(Align, Increment),
3070 LdChain.push_back(L.getValue(1));
3076 LdWidth -= NewVTWidth;
3079 // Build the vector from the loads operations
3080 unsigned End = LdOps.size();
3081 if (!LdOps[0].getValueType().isVector())
3082 // All the loads are scalar loads.
3083 return BuildVectorFromScalar(DAG, WidenVT, LdOps, 0, End);
3085 // If the load contains vectors, build the vector using concat vector.
3086 // All of the vectors used to loads are power of 2 and the scalars load
3087 // can be combined to make a power of 2 vector.
3088 SmallVector<SDValue, 16> ConcatOps(End);
3091 EVT LdTy = LdOps[i].getValueType();
3092 // First combine the scalar loads to a vector
3093 if (!LdTy.isVector()) {
3094 for (--i; i >= 0; --i) {
3095 LdTy = LdOps[i].getValueType();
3096 if (LdTy.isVector())
3099 ConcatOps[--Idx] = BuildVectorFromScalar(DAG, LdTy, LdOps, i+1, End);
3101 ConcatOps[--Idx] = LdOps[i];
3102 for (--i; i >= 0; --i) {
3103 EVT NewLdTy = LdOps[i].getValueType();
3104 if (NewLdTy != LdTy) {
3105 // Create a larger vector
3106 ConcatOps[End-1] = DAG.getNode(ISD::CONCAT_VECTORS, dl, NewLdTy,
3107 makeArrayRef(&ConcatOps[Idx], End - Idx));
3111 ConcatOps[--Idx] = LdOps[i];
3114 if (WidenWidth == LdTy.getSizeInBits()*(End - Idx))
3115 return DAG.getNode(ISD::CONCAT_VECTORS, dl, WidenVT,
3116 makeArrayRef(&ConcatOps[Idx], End - Idx));
3118 // We need to fill the rest with undefs to build the vector
3119 unsigned NumOps = WidenWidth / LdTy.getSizeInBits();
3120 SmallVector<SDValue, 16> WidenOps(NumOps);
3121 SDValue UndefVal = DAG.getUNDEF(LdTy);
3124 for (; i != End-Idx; ++i)
3125 WidenOps[i] = ConcatOps[Idx+i];
3126 for (; i != NumOps; ++i)
3127 WidenOps[i] = UndefVal;
3129 return DAG.getNode(ISD::CONCAT_VECTORS, dl, WidenVT, WidenOps);
3133 DAGTypeLegalizer::GenWidenVectorExtLoads(SmallVectorImpl<SDValue> &LdChain,
3135 ISD::LoadExtType ExtType) {
3136 // For extension loads, it may not be more efficient to chop up the vector
3137 // and then extended it. Instead, we unroll the load and build a new vector.
3138 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(),LD->getValueType(0));
3139 EVT LdVT = LD->getMemoryVT();
3141 assert(LdVT.isVector() && WidenVT.isVector());
3144 SDValue Chain = LD->getChain();
3145 SDValue BasePtr = LD->getBasePtr();
3146 unsigned Align = LD->getAlignment();
3147 bool isVolatile = LD->isVolatile();
3148 bool isNonTemporal = LD->isNonTemporal();
3149 bool isInvariant = LD->isInvariant();
3150 AAMDNodes AAInfo = LD->getAAInfo();
3152 EVT EltVT = WidenVT.getVectorElementType();
3153 EVT LdEltVT = LdVT.getVectorElementType();
3154 unsigned NumElts = LdVT.getVectorNumElements();
3156 // Load each element and widen
3157 unsigned WidenNumElts = WidenVT.getVectorNumElements();
3158 SmallVector<SDValue, 16> Ops(WidenNumElts);
3159 unsigned Increment = LdEltVT.getSizeInBits() / 8;
3160 Ops[0] = DAG.getExtLoad(ExtType, dl, EltVT, Chain, BasePtr,
3161 LD->getPointerInfo(),
3162 LdEltVT, isVolatile, isNonTemporal, isInvariant,
3164 LdChain.push_back(Ops[0].getValue(1));
3165 unsigned i = 0, Offset = Increment;
3166 for (i=1; i < NumElts; ++i, Offset += Increment) {
3167 SDValue NewBasePtr = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(),
3169 DAG.getConstant(Offset,
3170 BasePtr.getValueType()));
3171 Ops[i] = DAG.getExtLoad(ExtType, dl, EltVT, Chain, NewBasePtr,
3172 LD->getPointerInfo().getWithOffset(Offset), LdEltVT,
3173 isVolatile, isNonTemporal, isInvariant, Align,
3175 LdChain.push_back(Ops[i].getValue(1));
3178 // Fill the rest with undefs
3179 SDValue UndefVal = DAG.getUNDEF(EltVT);
3180 for (; i != WidenNumElts; ++i)
3183 return DAG.getNode(ISD::BUILD_VECTOR, dl, WidenVT, Ops);
3187 void DAGTypeLegalizer::GenWidenVectorStores(SmallVectorImpl<SDValue> &StChain,
3189 // The strategy assumes that we can efficiently store powers of two widths.
3190 // The routines chops the vector into the largest vector stores with the same
3191 // element type or scalar stores.
3192 SDValue Chain = ST->getChain();
3193 SDValue BasePtr = ST->getBasePtr();
3194 unsigned Align = ST->getAlignment();
3195 bool isVolatile = ST->isVolatile();
3196 bool isNonTemporal = ST->isNonTemporal();
3197 AAMDNodes AAInfo = ST->getAAInfo();
3198 SDValue ValOp = GetWidenedVector(ST->getValue());
3201 EVT StVT = ST->getMemoryVT();
3202 unsigned StWidth = StVT.getSizeInBits();
3203 EVT ValVT = ValOp.getValueType();
3204 unsigned ValWidth = ValVT.getSizeInBits();
3205 EVT ValEltVT = ValVT.getVectorElementType();
3206 unsigned ValEltWidth = ValEltVT.getSizeInBits();
3207 assert(StVT.getVectorElementType() == ValEltVT);
3209 int Idx = 0; // current index to store
3210 unsigned Offset = 0; // offset from base to store
3211 while (StWidth != 0) {
3212 // Find the largest vector type we can store with
3213 EVT NewVT = FindMemType(DAG, TLI, StWidth, ValVT);
3214 unsigned NewVTWidth = NewVT.getSizeInBits();
3215 unsigned Increment = NewVTWidth / 8;
3216 if (NewVT.isVector()) {
3217 unsigned NumVTElts = NewVT.getVectorNumElements();
3219 SDValue EOp = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, NewVT, ValOp,
3220 DAG.getConstant(Idx, TLI.getVectorIdxTy()));
3221 StChain.push_back(DAG.getStore(Chain, dl, EOp, BasePtr,
3222 ST->getPointerInfo().getWithOffset(Offset),
3223 isVolatile, isNonTemporal,
3224 MinAlign(Align, Offset), AAInfo));
3225 StWidth -= NewVTWidth;
3226 Offset += Increment;
3228 BasePtr = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(), BasePtr,
3229 DAG.getConstant(Increment, BasePtr.getValueType()));
3230 } while (StWidth != 0 && StWidth >= NewVTWidth);
3232 // Cast the vector to the scalar type we can store
3233 unsigned NumElts = ValWidth / NewVTWidth;
3234 EVT NewVecVT = EVT::getVectorVT(*DAG.getContext(), NewVT, NumElts);
3235 SDValue VecOp = DAG.getNode(ISD::BITCAST, dl, NewVecVT, ValOp);
3236 // Readjust index position based on new vector type
3237 Idx = Idx * ValEltWidth / NewVTWidth;
3239 SDValue EOp = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, NewVT, VecOp,
3240 DAG.getConstant(Idx++, TLI.getVectorIdxTy()));
3241 StChain.push_back(DAG.getStore(Chain, dl, EOp, BasePtr,
3242 ST->getPointerInfo().getWithOffset(Offset),
3243 isVolatile, isNonTemporal,
3244 MinAlign(Align, Offset), AAInfo));
3245 StWidth -= NewVTWidth;
3246 Offset += Increment;
3247 BasePtr = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(), BasePtr,
3248 DAG.getConstant(Increment, BasePtr.getValueType()));
3249 } while (StWidth != 0 && StWidth >= NewVTWidth);
3250 // Restore index back to be relative to the original widen element type
3251 Idx = Idx * NewVTWidth / ValEltWidth;
3257 DAGTypeLegalizer::GenWidenVectorTruncStores(SmallVectorImpl<SDValue> &StChain,
3259 // For extension loads, it may not be more efficient to truncate the vector
3260 // and then store it. Instead, we extract each element and then store it.
3261 SDValue Chain = ST->getChain();
3262 SDValue BasePtr = ST->getBasePtr();
3263 unsigned Align = ST->getAlignment();
3264 bool isVolatile = ST->isVolatile();
3265 bool isNonTemporal = ST->isNonTemporal();
3266 AAMDNodes AAInfo = ST->getAAInfo();
3267 SDValue ValOp = GetWidenedVector(ST->getValue());
3270 EVT StVT = ST->getMemoryVT();
3271 EVT ValVT = ValOp.getValueType();
3273 // It must be true that we the widen vector type is bigger than where
3274 // we need to store.
3275 assert(StVT.isVector() && ValOp.getValueType().isVector());
3276 assert(StVT.bitsLT(ValOp.getValueType()));
3278 // For truncating stores, we can not play the tricks of chopping legal
3279 // vector types and bit cast it to the right type. Instead, we unroll
3281 EVT StEltVT = StVT.getVectorElementType();
3282 EVT ValEltVT = ValVT.getVectorElementType();
3283 unsigned Increment = ValEltVT.getSizeInBits() / 8;
3284 unsigned NumElts = StVT.getVectorNumElements();
3285 SDValue EOp = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ValEltVT, ValOp,
3286 DAG.getConstant(0, TLI.getVectorIdxTy()));
3287 StChain.push_back(DAG.getTruncStore(Chain, dl, EOp, BasePtr,
3288 ST->getPointerInfo(), StEltVT,
3289 isVolatile, isNonTemporal, Align,
3291 unsigned Offset = Increment;
3292 for (unsigned i=1; i < NumElts; ++i, Offset += Increment) {
3293 SDValue NewBasePtr = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(),
3294 BasePtr, DAG.getConstant(Offset,
3295 BasePtr.getValueType()));
3296 SDValue EOp = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ValEltVT, ValOp,
3297 DAG.getConstant(0, TLI.getVectorIdxTy()));
3298 StChain.push_back(DAG.getTruncStore(Chain, dl, EOp, NewBasePtr,
3299 ST->getPointerInfo().getWithOffset(Offset),
3300 StEltVT, isVolatile, isNonTemporal,
3301 MinAlign(Align, Offset), AAInfo));
3305 /// Modifies a vector input (widen or narrows) to a vector of NVT. The
3306 /// input vector must have the same element type as NVT.
3307 SDValue DAGTypeLegalizer::ModifyToType(SDValue InOp, EVT NVT) {
3308 // Note that InOp might have been widened so it might already have
3309 // the right width or it might need be narrowed.
3310 EVT InVT = InOp.getValueType();
3311 assert(InVT.getVectorElementType() == NVT.getVectorElementType() &&
3312 "input and widen element type must match");
3315 // Check if InOp already has the right width.
3319 unsigned InNumElts = InVT.getVectorNumElements();
3320 unsigned WidenNumElts = NVT.getVectorNumElements();
3321 if (WidenNumElts > InNumElts && WidenNumElts % InNumElts == 0) {
3322 unsigned NumConcat = WidenNumElts / InNumElts;
3323 SmallVector<SDValue, 16> Ops(NumConcat);
3324 SDValue UndefVal = DAG.getUNDEF(InVT);
3326 for (unsigned i = 1; i != NumConcat; ++i)
3329 return DAG.getNode(ISD::CONCAT_VECTORS, dl, NVT, Ops);
3332 if (WidenNumElts < InNumElts && InNumElts % WidenNumElts)
3333 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, NVT, InOp,
3334 DAG.getConstant(0, TLI.getVectorIdxTy()));
3336 // Fall back to extract and build.
3337 SmallVector<SDValue, 16> Ops(WidenNumElts);
3338 EVT EltVT = NVT.getVectorElementType();
3339 unsigned MinNumElts = std::min(WidenNumElts, InNumElts);
3341 for (Idx = 0; Idx < MinNumElts; ++Idx)
3342 Ops[Idx] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, InOp,
3343 DAG.getConstant(Idx, TLI.getVectorIdxTy()));
3345 SDValue UndefVal = DAG.getUNDEF(EltVT);
3346 for ( ; Idx < WidenNumElts; ++Idx)
3347 Ops[Idx] = UndefVal;
3348 return DAG.getNode(ISD::BUILD_VECTOR, dl, NVT, Ops);