1 //===------- LegalizeVectorTypes.cpp - Legalization of vector types -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file performs vector type splitting and scalarization for LegalizeTypes.
11 // Scalarization is the act of changing a computation in an illegal one-element
12 // vector type to be a computation in its scalar element type. For example,
13 // implementing <1 x f32> arithmetic in a scalar f32 register. This is needed
14 // as a base case when scalarizing vector arithmetic like <4 x f32>, which
15 // eventually decomposes to scalars if the target doesn't support v4f32 or v2f32
17 // Splitting is the act of changing a computation in an invalid vector type to
18 // be a computation in two vectors of half the size. For example, implementing
19 // <128 x f32> operations in terms of two <64 x f32> operations.
21 //===----------------------------------------------------------------------===//
23 #include "LegalizeTypes.h"
24 #include "llvm/IR/DataLayout.h"
25 #include "llvm/Support/ErrorHandling.h"
26 #include "llvm/Support/raw_ostream.h"
29 #define DEBUG_TYPE "legalize-types"
31 //===----------------------------------------------------------------------===//
32 // Result Vector Scalarization: <1 x ty> -> ty.
33 //===----------------------------------------------------------------------===//
35 void DAGTypeLegalizer::ScalarizeVectorResult(SDNode *N, unsigned ResNo) {
36 DEBUG(dbgs() << "Scalarize node result " << ResNo << ": ";
39 SDValue R = SDValue();
41 switch (N->getOpcode()) {
44 dbgs() << "ScalarizeVectorResult #" << ResNo << ": ";
48 report_fatal_error("Do not know how to scalarize the result of this "
51 case ISD::MERGE_VALUES: R = ScalarizeVecRes_MERGE_VALUES(N, ResNo);break;
52 case ISD::BITCAST: R = ScalarizeVecRes_BITCAST(N); break;
53 case ISD::BUILD_VECTOR: R = ScalarizeVecRes_BUILD_VECTOR(N); break;
54 case ISD::CONVERT_RNDSAT: R = ScalarizeVecRes_CONVERT_RNDSAT(N); break;
55 case ISD::EXTRACT_SUBVECTOR: R = ScalarizeVecRes_EXTRACT_SUBVECTOR(N); break;
56 case ISD::FP_ROUND: R = ScalarizeVecRes_FP_ROUND(N); break;
57 case ISD::FP_ROUND_INREG: R = ScalarizeVecRes_InregOp(N); break;
58 case ISD::FPOWI: R = ScalarizeVecRes_FPOWI(N); break;
59 case ISD::INSERT_VECTOR_ELT: R = ScalarizeVecRes_INSERT_VECTOR_ELT(N); break;
60 case ISD::LOAD: R = ScalarizeVecRes_LOAD(cast<LoadSDNode>(N));break;
61 case ISD::SCALAR_TO_VECTOR: R = ScalarizeVecRes_SCALAR_TO_VECTOR(N); break;
62 case ISD::SIGN_EXTEND_INREG: R = ScalarizeVecRes_InregOp(N); break;
63 case ISD::VSELECT: R = ScalarizeVecRes_VSELECT(N); break;
64 case ISD::SELECT: R = ScalarizeVecRes_SELECT(N); break;
65 case ISD::SELECT_CC: R = ScalarizeVecRes_SELECT_CC(N); break;
66 case ISD::SETCC: R = ScalarizeVecRes_SETCC(N); break;
67 case ISD::UNDEF: R = ScalarizeVecRes_UNDEF(N); break;
68 case ISD::VECTOR_SHUFFLE: R = ScalarizeVecRes_VECTOR_SHUFFLE(N); break;
72 case ISD::CTLZ_ZERO_UNDEF:
75 case ISD::CTTZ_ZERO_UNDEF:
95 case ISD::SIGN_EXTEND:
99 case ISD::ZERO_EXTEND:
100 R = ScalarizeVecRes_UnaryOp(N);
128 R = ScalarizeVecRes_BinOp(N);
131 R = ScalarizeVecRes_TernaryOp(N);
135 // If R is null, the sub-method took care of registering the result.
137 SetScalarizedVector(SDValue(N, ResNo), R);
140 SDValue DAGTypeLegalizer::ScalarizeVecRes_BinOp(SDNode *N) {
141 SDValue LHS = GetScalarizedVector(N->getOperand(0));
142 SDValue RHS = GetScalarizedVector(N->getOperand(1));
143 return DAG.getNode(N->getOpcode(), SDLoc(N),
144 LHS.getValueType(), LHS, RHS, N->getFlags());
147 SDValue DAGTypeLegalizer::ScalarizeVecRes_TernaryOp(SDNode *N) {
148 SDValue Op0 = GetScalarizedVector(N->getOperand(0));
149 SDValue Op1 = GetScalarizedVector(N->getOperand(1));
150 SDValue Op2 = GetScalarizedVector(N->getOperand(2));
151 return DAG.getNode(N->getOpcode(), SDLoc(N),
152 Op0.getValueType(), Op0, Op1, Op2);
155 SDValue DAGTypeLegalizer::ScalarizeVecRes_MERGE_VALUES(SDNode *N,
157 SDValue Op = DisintegrateMERGE_VALUES(N, ResNo);
158 return GetScalarizedVector(Op);
161 SDValue DAGTypeLegalizer::ScalarizeVecRes_BITCAST(SDNode *N) {
162 EVT NewVT = N->getValueType(0).getVectorElementType();
163 return DAG.getNode(ISD::BITCAST, SDLoc(N),
164 NewVT, N->getOperand(0));
167 SDValue DAGTypeLegalizer::ScalarizeVecRes_BUILD_VECTOR(SDNode *N) {
168 EVT EltVT = N->getValueType(0).getVectorElementType();
169 SDValue InOp = N->getOperand(0);
170 // The BUILD_VECTOR operands may be of wider element types and
171 // we may need to truncate them back to the requested return type.
172 if (EltVT.isInteger())
173 return DAG.getNode(ISD::TRUNCATE, SDLoc(N), EltVT, InOp);
177 SDValue DAGTypeLegalizer::ScalarizeVecRes_CONVERT_RNDSAT(SDNode *N) {
178 EVT NewVT = N->getValueType(0).getVectorElementType();
179 SDValue Op0 = GetScalarizedVector(N->getOperand(0));
180 return DAG.getConvertRndSat(NewVT, SDLoc(N),
181 Op0, DAG.getValueType(NewVT),
182 DAG.getValueType(Op0.getValueType()),
185 cast<CvtRndSatSDNode>(N)->getCvtCode());
188 SDValue DAGTypeLegalizer::ScalarizeVecRes_EXTRACT_SUBVECTOR(SDNode *N) {
189 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SDLoc(N),
190 N->getValueType(0).getVectorElementType(),
191 N->getOperand(0), N->getOperand(1));
194 SDValue DAGTypeLegalizer::ScalarizeVecRes_FP_ROUND(SDNode *N) {
195 EVT NewVT = N->getValueType(0).getVectorElementType();
196 SDValue Op = GetScalarizedVector(N->getOperand(0));
197 return DAG.getNode(ISD::FP_ROUND, SDLoc(N),
198 NewVT, Op, N->getOperand(1));
201 SDValue DAGTypeLegalizer::ScalarizeVecRes_FPOWI(SDNode *N) {
202 SDValue Op = GetScalarizedVector(N->getOperand(0));
203 return DAG.getNode(ISD::FPOWI, SDLoc(N),
204 Op.getValueType(), Op, N->getOperand(1));
207 SDValue DAGTypeLegalizer::ScalarizeVecRes_INSERT_VECTOR_ELT(SDNode *N) {
208 // The value to insert may have a wider type than the vector element type,
209 // so be sure to truncate it to the element type if necessary.
210 SDValue Op = N->getOperand(1);
211 EVT EltVT = N->getValueType(0).getVectorElementType();
212 if (Op.getValueType() != EltVT)
213 // FIXME: Can this happen for floating point types?
214 Op = DAG.getNode(ISD::TRUNCATE, SDLoc(N), EltVT, Op);
218 SDValue DAGTypeLegalizer::ScalarizeVecRes_LOAD(LoadSDNode *N) {
219 assert(N->isUnindexed() && "Indexed vector load?");
221 SDValue Result = DAG.getLoad(ISD::UNINDEXED,
222 N->getExtensionType(),
223 N->getValueType(0).getVectorElementType(),
225 N->getChain(), N->getBasePtr(),
226 DAG.getUNDEF(N->getBasePtr().getValueType()),
228 N->getMemoryVT().getVectorElementType(),
229 N->isVolatile(), N->isNonTemporal(),
230 N->isInvariant(), N->getOriginalAlignment(),
233 // Legalized the chain result - switch anything that used the old chain to
235 ReplaceValueWith(SDValue(N, 1), Result.getValue(1));
239 SDValue DAGTypeLegalizer::ScalarizeVecRes_UnaryOp(SDNode *N) {
240 // Get the dest type - it doesn't always match the input type, e.g. int_to_fp.
241 EVT DestVT = N->getValueType(0).getVectorElementType();
242 SDValue Op = N->getOperand(0);
243 EVT OpVT = Op.getValueType();
245 // The result needs scalarizing, but it's not a given that the source does.
246 // This is a workaround for targets where it's impossible to scalarize the
247 // result of a conversion, because the source type is legal.
248 // For instance, this happens on AArch64: v1i1 is illegal but v1i{8,16,32}
249 // are widened to v8i8, v4i16, and v2i32, which is legal, because v1i64 is
250 // legal and was not scalarized.
251 // See the similar logic in ScalarizeVecRes_VSETCC
252 if (getTypeAction(OpVT) == TargetLowering::TypeScalarizeVector) {
253 Op = GetScalarizedVector(Op);
255 EVT VT = OpVT.getVectorElementType();
257 ISD::EXTRACT_VECTOR_ELT, DL, VT, Op,
258 DAG.getConstant(0, DL, TLI.getVectorIdxTy(DAG.getDataLayout())));
260 return DAG.getNode(N->getOpcode(), SDLoc(N), DestVT, Op);
263 SDValue DAGTypeLegalizer::ScalarizeVecRes_InregOp(SDNode *N) {
264 EVT EltVT = N->getValueType(0).getVectorElementType();
265 EVT ExtVT = cast<VTSDNode>(N->getOperand(1))->getVT().getVectorElementType();
266 SDValue LHS = GetScalarizedVector(N->getOperand(0));
267 return DAG.getNode(N->getOpcode(), SDLoc(N), EltVT,
268 LHS, DAG.getValueType(ExtVT));
271 SDValue DAGTypeLegalizer::ScalarizeVecRes_SCALAR_TO_VECTOR(SDNode *N) {
272 // If the operand is wider than the vector element type then it is implicitly
273 // truncated. Make that explicit here.
274 EVT EltVT = N->getValueType(0).getVectorElementType();
275 SDValue InOp = N->getOperand(0);
276 if (InOp.getValueType() != EltVT)
277 return DAG.getNode(ISD::TRUNCATE, SDLoc(N), EltVT, InOp);
281 SDValue DAGTypeLegalizer::ScalarizeVecRes_VSELECT(SDNode *N) {
282 SDValue Cond = GetScalarizedVector(N->getOperand(0));
283 SDValue LHS = GetScalarizedVector(N->getOperand(1));
284 TargetLowering::BooleanContent ScalarBool =
285 TLI.getBooleanContents(false, false);
286 TargetLowering::BooleanContent VecBool = TLI.getBooleanContents(true, false);
288 // If integer and float booleans have different contents then we can't
289 // reliably optimize in all cases. There is a full explanation for this in
290 // DAGCombiner::visitSELECT() where the same issue affects folding
291 // (select C, 0, 1) to (xor C, 1).
292 if (TLI.getBooleanContents(false, false) !=
293 TLI.getBooleanContents(false, true)) {
294 // At least try the common case where the boolean is generated by a
296 if (Cond->getOpcode() == ISD::SETCC) {
297 EVT OpVT = Cond->getOperand(0)->getValueType(0);
298 ScalarBool = TLI.getBooleanContents(OpVT.getScalarType());
299 VecBool = TLI.getBooleanContents(OpVT);
301 ScalarBool = TargetLowering::UndefinedBooleanContent;
304 if (ScalarBool != VecBool) {
305 EVT CondVT = Cond.getValueType();
306 switch (ScalarBool) {
307 case TargetLowering::UndefinedBooleanContent:
309 case TargetLowering::ZeroOrOneBooleanContent:
310 assert(VecBool == TargetLowering::UndefinedBooleanContent ||
311 VecBool == TargetLowering::ZeroOrNegativeOneBooleanContent);
312 // Vector read from all ones, scalar expects a single 1 so mask.
313 Cond = DAG.getNode(ISD::AND, SDLoc(N), CondVT,
314 Cond, DAG.getConstant(1, SDLoc(N), CondVT));
316 case TargetLowering::ZeroOrNegativeOneBooleanContent:
317 assert(VecBool == TargetLowering::UndefinedBooleanContent ||
318 VecBool == TargetLowering::ZeroOrOneBooleanContent);
319 // Vector reads from a one, scalar from all ones so sign extend.
320 Cond = DAG.getNode(ISD::SIGN_EXTEND_INREG, SDLoc(N), CondVT,
321 Cond, DAG.getValueType(MVT::i1));
326 return DAG.getSelect(SDLoc(N),
327 LHS.getValueType(), Cond, LHS,
328 GetScalarizedVector(N->getOperand(2)));
331 SDValue DAGTypeLegalizer::ScalarizeVecRes_SELECT(SDNode *N) {
332 SDValue LHS = GetScalarizedVector(N->getOperand(1));
333 return DAG.getSelect(SDLoc(N),
334 LHS.getValueType(), N->getOperand(0), LHS,
335 GetScalarizedVector(N->getOperand(2)));
338 SDValue DAGTypeLegalizer::ScalarizeVecRes_SELECT_CC(SDNode *N) {
339 SDValue LHS = GetScalarizedVector(N->getOperand(2));
340 return DAG.getNode(ISD::SELECT_CC, SDLoc(N), LHS.getValueType(),
341 N->getOperand(0), N->getOperand(1),
342 LHS, GetScalarizedVector(N->getOperand(3)),
346 SDValue DAGTypeLegalizer::ScalarizeVecRes_SETCC(SDNode *N) {
347 assert(N->getValueType(0).isVector() ==
348 N->getOperand(0).getValueType().isVector() &&
349 "Scalar/Vector type mismatch");
351 if (N->getValueType(0).isVector()) return ScalarizeVecRes_VSETCC(N);
353 SDValue LHS = GetScalarizedVector(N->getOperand(0));
354 SDValue RHS = GetScalarizedVector(N->getOperand(1));
357 // Turn it into a scalar SETCC.
358 return DAG.getNode(ISD::SETCC, DL, MVT::i1, LHS, RHS, N->getOperand(2));
361 SDValue DAGTypeLegalizer::ScalarizeVecRes_UNDEF(SDNode *N) {
362 return DAG.getUNDEF(N->getValueType(0).getVectorElementType());
365 SDValue DAGTypeLegalizer::ScalarizeVecRes_VECTOR_SHUFFLE(SDNode *N) {
366 // Figure out if the scalar is the LHS or RHS and return it.
367 SDValue Arg = N->getOperand(2).getOperand(0);
368 if (Arg.getOpcode() == ISD::UNDEF)
369 return DAG.getUNDEF(N->getValueType(0).getVectorElementType());
370 unsigned Op = !cast<ConstantSDNode>(Arg)->isNullValue();
371 return GetScalarizedVector(N->getOperand(Op));
374 SDValue DAGTypeLegalizer::ScalarizeVecRes_VSETCC(SDNode *N) {
375 assert(N->getValueType(0).isVector() &&
376 N->getOperand(0).getValueType().isVector() &&
377 "Operand types must be vectors");
378 SDValue LHS = N->getOperand(0);
379 SDValue RHS = N->getOperand(1);
380 EVT OpVT = LHS.getValueType();
381 EVT NVT = N->getValueType(0).getVectorElementType();
384 // The result needs scalarizing, but it's not a given that the source does.
385 if (getTypeAction(OpVT) == TargetLowering::TypeScalarizeVector) {
386 LHS = GetScalarizedVector(LHS);
387 RHS = GetScalarizedVector(RHS);
389 EVT VT = OpVT.getVectorElementType();
391 ISD::EXTRACT_VECTOR_ELT, DL, VT, LHS,
392 DAG.getConstant(0, DL, TLI.getVectorIdxTy(DAG.getDataLayout())));
394 ISD::EXTRACT_VECTOR_ELT, DL, VT, RHS,
395 DAG.getConstant(0, DL, TLI.getVectorIdxTy(DAG.getDataLayout())));
398 // Turn it into a scalar SETCC.
399 SDValue Res = DAG.getNode(ISD::SETCC, DL, MVT::i1, LHS, RHS,
401 // Vectors may have a different boolean contents to scalars. Promote the
402 // value appropriately.
403 ISD::NodeType ExtendCode =
404 TargetLowering::getExtendForContent(TLI.getBooleanContents(OpVT));
405 return DAG.getNode(ExtendCode, DL, NVT, Res);
409 //===----------------------------------------------------------------------===//
410 // Operand Vector Scalarization <1 x ty> -> ty.
411 //===----------------------------------------------------------------------===//
413 bool DAGTypeLegalizer::ScalarizeVectorOperand(SDNode *N, unsigned OpNo) {
414 DEBUG(dbgs() << "Scalarize node operand " << OpNo << ": ";
417 SDValue Res = SDValue();
419 if (!Res.getNode()) {
420 switch (N->getOpcode()) {
423 dbgs() << "ScalarizeVectorOperand Op #" << OpNo << ": ";
427 llvm_unreachable("Do not know how to scalarize this operator's operand!");
429 Res = ScalarizeVecOp_BITCAST(N);
431 case ISD::ANY_EXTEND:
432 case ISD::ZERO_EXTEND:
433 case ISD::SIGN_EXTEND:
435 case ISD::FP_TO_SINT:
436 case ISD::FP_TO_UINT:
437 case ISD::SINT_TO_FP:
438 case ISD::UINT_TO_FP:
439 Res = ScalarizeVecOp_UnaryOp(N);
441 case ISD::CONCAT_VECTORS:
442 Res = ScalarizeVecOp_CONCAT_VECTORS(N);
444 case ISD::EXTRACT_VECTOR_ELT:
445 Res = ScalarizeVecOp_EXTRACT_VECTOR_ELT(N);
448 Res = ScalarizeVecOp_VSELECT(N);
451 Res = ScalarizeVecOp_STORE(cast<StoreSDNode>(N), OpNo);
454 Res = ScalarizeVecOp_FP_ROUND(N, OpNo);
459 // If the result is null, the sub-method took care of registering results etc.
460 if (!Res.getNode()) return false;
462 // If the result is N, the sub-method updated N in place. Tell the legalizer
464 if (Res.getNode() == N)
467 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 &&
468 "Invalid operand expansion");
470 ReplaceValueWith(SDValue(N, 0), Res);
474 /// ScalarizeVecOp_BITCAST - If the value to convert is a vector that needs
475 /// to be scalarized, it must be <1 x ty>. Convert the element instead.
476 SDValue DAGTypeLegalizer::ScalarizeVecOp_BITCAST(SDNode *N) {
477 SDValue Elt = GetScalarizedVector(N->getOperand(0));
478 return DAG.getNode(ISD::BITCAST, SDLoc(N),
479 N->getValueType(0), Elt);
482 /// ScalarizeVecOp_UnaryOp - If the input is a vector that needs to be
483 /// scalarized, it must be <1 x ty>. Do the operation on the element instead.
484 SDValue DAGTypeLegalizer::ScalarizeVecOp_UnaryOp(SDNode *N) {
485 assert(N->getValueType(0).getVectorNumElements() == 1 &&
486 "Unexpected vector type!");
487 SDValue Elt = GetScalarizedVector(N->getOperand(0));
488 SDValue Op = DAG.getNode(N->getOpcode(), SDLoc(N),
489 N->getValueType(0).getScalarType(), Elt);
490 // Revectorize the result so the types line up with what the uses of this
491 // expression expect.
492 return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(N), N->getValueType(0), Op);
495 /// ScalarizeVecOp_CONCAT_VECTORS - The vectors to concatenate have length one -
496 /// use a BUILD_VECTOR instead.
497 SDValue DAGTypeLegalizer::ScalarizeVecOp_CONCAT_VECTORS(SDNode *N) {
498 SmallVector<SDValue, 8> Ops(N->getNumOperands());
499 for (unsigned i = 0, e = N->getNumOperands(); i < e; ++i)
500 Ops[i] = GetScalarizedVector(N->getOperand(i));
501 return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(N), N->getValueType(0), Ops);
504 /// ScalarizeVecOp_EXTRACT_VECTOR_ELT - If the input is a vector that needs to
505 /// be scalarized, it must be <1 x ty>, so just return the element, ignoring the
507 SDValue DAGTypeLegalizer::ScalarizeVecOp_EXTRACT_VECTOR_ELT(SDNode *N) {
508 SDValue Res = GetScalarizedVector(N->getOperand(0));
509 if (Res.getValueType() != N->getValueType(0))
510 Res = DAG.getNode(ISD::ANY_EXTEND, SDLoc(N), N->getValueType(0),
516 /// ScalarizeVecOp_VSELECT - If the input condition is a vector that needs to be
517 /// scalarized, it must be <1 x i1>, so just convert to a normal ISD::SELECT
518 /// (still with vector output type since that was acceptable if we got here).
519 SDValue DAGTypeLegalizer::ScalarizeVecOp_VSELECT(SDNode *N) {
520 SDValue ScalarCond = GetScalarizedVector(N->getOperand(0));
521 EVT VT = N->getValueType(0);
523 return DAG.getNode(ISD::SELECT, SDLoc(N), VT, ScalarCond, N->getOperand(1),
527 /// ScalarizeVecOp_STORE - If the value to store is a vector that needs to be
528 /// scalarized, it must be <1 x ty>. Just store the element.
529 SDValue DAGTypeLegalizer::ScalarizeVecOp_STORE(StoreSDNode *N, unsigned OpNo){
530 assert(N->isUnindexed() && "Indexed store of one-element vector?");
531 assert(OpNo == 1 && "Do not know how to scalarize this operand!");
534 if (N->isTruncatingStore())
535 return DAG.getTruncStore(N->getChain(), dl,
536 GetScalarizedVector(N->getOperand(1)),
537 N->getBasePtr(), N->getPointerInfo(),
538 N->getMemoryVT().getVectorElementType(),
539 N->isVolatile(), N->isNonTemporal(),
540 N->getAlignment(), N->getAAInfo());
542 return DAG.getStore(N->getChain(), dl, GetScalarizedVector(N->getOperand(1)),
543 N->getBasePtr(), N->getPointerInfo(),
544 N->isVolatile(), N->isNonTemporal(),
545 N->getOriginalAlignment(), N->getAAInfo());
548 /// ScalarizeVecOp_FP_ROUND - If the value to round is a vector that needs
549 /// to be scalarized, it must be <1 x ty>. Convert the element instead.
550 SDValue DAGTypeLegalizer::ScalarizeVecOp_FP_ROUND(SDNode *N, unsigned OpNo) {
551 SDValue Elt = GetScalarizedVector(N->getOperand(0));
552 SDValue Res = DAG.getNode(ISD::FP_ROUND, SDLoc(N),
553 N->getValueType(0).getVectorElementType(), Elt,
555 return DAG.getNode(ISD::SCALAR_TO_VECTOR, SDLoc(N), N->getValueType(0), Res);
558 //===----------------------------------------------------------------------===//
559 // Result Vector Splitting
560 //===----------------------------------------------------------------------===//
562 /// SplitVectorResult - This method is called when the specified result of the
563 /// specified node is found to need vector splitting. At this point, the node
564 /// may also have invalid operands or may have other results that need
565 /// legalization, we just know that (at least) one result needs vector
567 void DAGTypeLegalizer::SplitVectorResult(SDNode *N, unsigned ResNo) {
568 DEBUG(dbgs() << "Split node result: ";
573 // See if the target wants to custom expand this node.
574 if (CustomLowerNode(N, N->getValueType(ResNo), true))
577 switch (N->getOpcode()) {
580 dbgs() << "SplitVectorResult #" << ResNo << ": ";
584 report_fatal_error("Do not know how to split the result of this "
587 case ISD::MERGE_VALUES: SplitRes_MERGE_VALUES(N, ResNo, Lo, Hi); break;
589 case ISD::SELECT: SplitRes_SELECT(N, Lo, Hi); break;
590 case ISD::SELECT_CC: SplitRes_SELECT_CC(N, Lo, Hi); break;
591 case ISD::UNDEF: SplitRes_UNDEF(N, Lo, Hi); break;
592 case ISD::BITCAST: SplitVecRes_BITCAST(N, Lo, Hi); break;
593 case ISD::BUILD_VECTOR: SplitVecRes_BUILD_VECTOR(N, Lo, Hi); break;
594 case ISD::CONCAT_VECTORS: SplitVecRes_CONCAT_VECTORS(N, Lo, Hi); break;
595 case ISD::EXTRACT_SUBVECTOR: SplitVecRes_EXTRACT_SUBVECTOR(N, Lo, Hi); break;
596 case ISD::INSERT_SUBVECTOR: SplitVecRes_INSERT_SUBVECTOR(N, Lo, Hi); break;
597 case ISD::FP_ROUND_INREG: SplitVecRes_InregOp(N, Lo, Hi); break;
598 case ISD::FPOWI: SplitVecRes_FPOWI(N, Lo, Hi); break;
599 case ISD::FCOPYSIGN: SplitVecRes_FCOPYSIGN(N, Lo, Hi); break;
600 case ISD::INSERT_VECTOR_ELT: SplitVecRes_INSERT_VECTOR_ELT(N, Lo, Hi); break;
601 case ISD::SCALAR_TO_VECTOR: SplitVecRes_SCALAR_TO_VECTOR(N, Lo, Hi); break;
602 case ISD::SIGN_EXTEND_INREG: SplitVecRes_InregOp(N, Lo, Hi); break;
604 SplitVecRes_LOAD(cast<LoadSDNode>(N), Lo, Hi);
607 SplitVecRes_MLOAD(cast<MaskedLoadSDNode>(N), Lo, Hi);
610 SplitVecRes_MGATHER(cast<MaskedGatherSDNode>(N), Lo, Hi);
613 SplitVecRes_SETCC(N, Lo, Hi);
615 case ISD::VECTOR_SHUFFLE:
616 SplitVecRes_VECTOR_SHUFFLE(cast<ShuffleVectorSDNode>(N), Lo, Hi);
620 case ISD::CONVERT_RNDSAT:
623 case ISD::CTLZ_ZERO_UNDEF:
624 case ISD::CTTZ_ZERO_UNDEF:
635 case ISD::FNEARBYINT:
639 case ISD::FP_TO_SINT:
640 case ISD::FP_TO_UINT:
646 case ISD::SINT_TO_FP:
648 case ISD::UINT_TO_FP:
649 SplitVecRes_UnaryOp(N, Lo, Hi);
652 case ISD::ANY_EXTEND:
653 case ISD::SIGN_EXTEND:
654 case ISD::ZERO_EXTEND:
655 SplitVecRes_ExtendOp(N, Lo, Hi);
687 SplitVecRes_BinOp(N, Lo, Hi);
690 SplitVecRes_TernaryOp(N, Lo, Hi);
694 // If Lo/Hi is null, the sub-method took care of registering results etc.
696 SetSplitVector(SDValue(N, ResNo), Lo, Hi);
699 void DAGTypeLegalizer::SplitVecRes_BinOp(SDNode *N, SDValue &Lo,
701 SDValue LHSLo, LHSHi;
702 GetSplitVector(N->getOperand(0), LHSLo, LHSHi);
703 SDValue RHSLo, RHSHi;
704 GetSplitVector(N->getOperand(1), RHSLo, RHSHi);
707 const SDNodeFlags *Flags = N->getFlags();
708 unsigned Opcode = N->getOpcode();
709 Lo = DAG.getNode(Opcode, dl, LHSLo.getValueType(), LHSLo, RHSLo, Flags);
710 Hi = DAG.getNode(Opcode, dl, LHSHi.getValueType(), LHSHi, RHSHi, Flags);
713 void DAGTypeLegalizer::SplitVecRes_TernaryOp(SDNode *N, SDValue &Lo,
715 SDValue Op0Lo, Op0Hi;
716 GetSplitVector(N->getOperand(0), Op0Lo, Op0Hi);
717 SDValue Op1Lo, Op1Hi;
718 GetSplitVector(N->getOperand(1), Op1Lo, Op1Hi);
719 SDValue Op2Lo, Op2Hi;
720 GetSplitVector(N->getOperand(2), Op2Lo, Op2Hi);
723 Lo = DAG.getNode(N->getOpcode(), dl, Op0Lo.getValueType(),
724 Op0Lo, Op1Lo, Op2Lo);
725 Hi = DAG.getNode(N->getOpcode(), dl, Op0Hi.getValueType(),
726 Op0Hi, Op1Hi, Op2Hi);
729 void DAGTypeLegalizer::SplitVecRes_BITCAST(SDNode *N, SDValue &Lo,
731 // We know the result is a vector. The input may be either a vector or a
734 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(N->getValueType(0));
737 SDValue InOp = N->getOperand(0);
738 EVT InVT = InOp.getValueType();
740 // Handle some special cases efficiently.
741 switch (getTypeAction(InVT)) {
742 case TargetLowering::TypeLegal:
743 case TargetLowering::TypePromoteInteger:
744 case TargetLowering::TypePromoteFloat:
745 case TargetLowering::TypeSoftenFloat:
746 case TargetLowering::TypeScalarizeVector:
747 case TargetLowering::TypeWidenVector:
749 case TargetLowering::TypeExpandInteger:
750 case TargetLowering::TypeExpandFloat:
751 // A scalar to vector conversion, where the scalar needs expansion.
752 // If the vector is being split in two then we can just convert the
755 GetExpandedOp(InOp, Lo, Hi);
756 if (DAG.getDataLayout().isBigEndian())
758 Lo = DAG.getNode(ISD::BITCAST, dl, LoVT, Lo);
759 Hi = DAG.getNode(ISD::BITCAST, dl, HiVT, Hi);
763 case TargetLowering::TypeSplitVector:
764 // If the input is a vector that needs to be split, convert each split
765 // piece of the input now.
766 GetSplitVector(InOp, Lo, Hi);
767 Lo = DAG.getNode(ISD::BITCAST, dl, LoVT, Lo);
768 Hi = DAG.getNode(ISD::BITCAST, dl, HiVT, Hi);
772 // In the general case, convert the input to an integer and split it by hand.
773 EVT LoIntVT = EVT::getIntegerVT(*DAG.getContext(), LoVT.getSizeInBits());
774 EVT HiIntVT = EVT::getIntegerVT(*DAG.getContext(), HiVT.getSizeInBits());
775 if (DAG.getDataLayout().isBigEndian())
776 std::swap(LoIntVT, HiIntVT);
778 SplitInteger(BitConvertToInteger(InOp), LoIntVT, HiIntVT, Lo, Hi);
780 if (DAG.getDataLayout().isBigEndian())
782 Lo = DAG.getNode(ISD::BITCAST, dl, LoVT, Lo);
783 Hi = DAG.getNode(ISD::BITCAST, dl, HiVT, Hi);
786 void DAGTypeLegalizer::SplitVecRes_BUILD_VECTOR(SDNode *N, SDValue &Lo,
790 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(N->getValueType(0));
791 unsigned LoNumElts = LoVT.getVectorNumElements();
792 SmallVector<SDValue, 8> LoOps(N->op_begin(), N->op_begin()+LoNumElts);
793 Lo = DAG.getNode(ISD::BUILD_VECTOR, dl, LoVT, LoOps);
795 SmallVector<SDValue, 8> HiOps(N->op_begin()+LoNumElts, N->op_end());
796 Hi = DAG.getNode(ISD::BUILD_VECTOR, dl, HiVT, HiOps);
799 void DAGTypeLegalizer::SplitVecRes_CONCAT_VECTORS(SDNode *N, SDValue &Lo,
801 assert(!(N->getNumOperands() & 1) && "Unsupported CONCAT_VECTORS");
803 unsigned NumSubvectors = N->getNumOperands() / 2;
804 if (NumSubvectors == 1) {
805 Lo = N->getOperand(0);
806 Hi = N->getOperand(1);
811 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(N->getValueType(0));
813 SmallVector<SDValue, 8> LoOps(N->op_begin(), N->op_begin()+NumSubvectors);
814 Lo = DAG.getNode(ISD::CONCAT_VECTORS, dl, LoVT, LoOps);
816 SmallVector<SDValue, 8> HiOps(N->op_begin()+NumSubvectors, N->op_end());
817 Hi = DAG.getNode(ISD::CONCAT_VECTORS, dl, HiVT, HiOps);
820 void DAGTypeLegalizer::SplitVecRes_EXTRACT_SUBVECTOR(SDNode *N, SDValue &Lo,
822 SDValue Vec = N->getOperand(0);
823 SDValue Idx = N->getOperand(1);
827 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(N->getValueType(0));
829 Lo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, LoVT, Vec, Idx);
830 uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
831 Hi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, HiVT, Vec,
832 DAG.getConstant(IdxVal + LoVT.getVectorNumElements(), dl,
833 TLI.getVectorIdxTy(DAG.getDataLayout())));
836 void DAGTypeLegalizer::SplitVecRes_INSERT_SUBVECTOR(SDNode *N, SDValue &Lo,
838 SDValue Vec = N->getOperand(0);
839 SDValue SubVec = N->getOperand(1);
840 SDValue Idx = N->getOperand(2);
842 GetSplitVector(Vec, Lo, Hi);
844 // Spill the vector to the stack.
845 EVT VecVT = Vec.getValueType();
846 EVT SubVecVT = VecVT.getVectorElementType();
847 SDValue StackPtr = DAG.CreateStackTemporary(VecVT);
848 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Vec, StackPtr,
849 MachinePointerInfo(), false, false, 0);
851 // Store the new subvector into the specified index.
852 SDValue SubVecPtr = GetVectorElementPointer(StackPtr, SubVecVT, Idx);
853 Type *VecType = VecVT.getTypeForEVT(*DAG.getContext());
854 unsigned Alignment = DAG.getDataLayout().getPrefTypeAlignment(VecType);
855 Store = DAG.getStore(Store, dl, SubVec, SubVecPtr, MachinePointerInfo(),
858 // Load the Lo part from the stack slot.
859 Lo = DAG.getLoad(Lo.getValueType(), dl, Store, StackPtr, MachinePointerInfo(),
860 false, false, false, 0);
862 // Increment the pointer to the other part.
863 unsigned IncrementSize = Lo.getValueType().getSizeInBits() / 8;
865 DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr,
866 DAG.getConstant(IncrementSize, dl, StackPtr.getValueType()));
868 // Load the Hi part from the stack slot.
869 Hi = DAG.getLoad(Hi.getValueType(), dl, Store, StackPtr, MachinePointerInfo(),
870 false, false, false, MinAlign(Alignment, IncrementSize));
873 void DAGTypeLegalizer::SplitVecRes_FPOWI(SDNode *N, SDValue &Lo,
876 GetSplitVector(N->getOperand(0), Lo, Hi);
877 Lo = DAG.getNode(ISD::FPOWI, dl, Lo.getValueType(), Lo, N->getOperand(1));
878 Hi = DAG.getNode(ISD::FPOWI, dl, Hi.getValueType(), Hi, N->getOperand(1));
881 void DAGTypeLegalizer::SplitVecRes_FCOPYSIGN(SDNode *N, SDValue &Lo,
883 SDValue LHSLo, LHSHi;
884 GetSplitVector(N->getOperand(0), LHSLo, LHSHi);
887 SDValue RHSLo, RHSHi;
888 SDValue RHS = N->getOperand(1);
889 EVT RHSVT = RHS.getValueType();
890 if (getTypeAction(RHSVT) == TargetLowering::TypeSplitVector)
891 GetSplitVector(RHS, RHSLo, RHSHi);
893 std::tie(RHSLo, RHSHi) = DAG.SplitVector(RHS, SDLoc(RHS));
896 Lo = DAG.getNode(ISD::FCOPYSIGN, DL, LHSLo.getValueType(), LHSLo, RHSLo);
897 Hi = DAG.getNode(ISD::FCOPYSIGN, DL, LHSHi.getValueType(), LHSHi, RHSHi);
900 void DAGTypeLegalizer::SplitVecRes_InregOp(SDNode *N, SDValue &Lo,
902 SDValue LHSLo, LHSHi;
903 GetSplitVector(N->getOperand(0), LHSLo, LHSHi);
907 std::tie(LoVT, HiVT) =
908 DAG.GetSplitDestVTs(cast<VTSDNode>(N->getOperand(1))->getVT());
910 Lo = DAG.getNode(N->getOpcode(), dl, LHSLo.getValueType(), LHSLo,
911 DAG.getValueType(LoVT));
912 Hi = DAG.getNode(N->getOpcode(), dl, LHSHi.getValueType(), LHSHi,
913 DAG.getValueType(HiVT));
916 void DAGTypeLegalizer::SplitVecRes_INSERT_VECTOR_ELT(SDNode *N, SDValue &Lo,
918 SDValue Vec = N->getOperand(0);
919 SDValue Elt = N->getOperand(1);
920 SDValue Idx = N->getOperand(2);
922 GetSplitVector(Vec, Lo, Hi);
924 if (ConstantSDNode *CIdx = dyn_cast<ConstantSDNode>(Idx)) {
925 unsigned IdxVal = CIdx->getZExtValue();
926 unsigned LoNumElts = Lo.getValueType().getVectorNumElements();
927 if (IdxVal < LoNumElts)
928 Lo = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
929 Lo.getValueType(), Lo, Elt, Idx);
932 DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, Hi.getValueType(), Hi, Elt,
933 DAG.getConstant(IdxVal - LoNumElts, dl,
934 TLI.getVectorIdxTy(DAG.getDataLayout())));
938 // See if the target wants to custom expand this node.
939 if (CustomLowerNode(N, N->getValueType(0), true))
942 // Spill the vector to the stack.
943 EVT VecVT = Vec.getValueType();
944 EVT EltVT = VecVT.getVectorElementType();
945 SDValue StackPtr = DAG.CreateStackTemporary(VecVT);
946 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Vec, StackPtr,
947 MachinePointerInfo(), false, false, 0);
949 // Store the new element. This may be larger than the vector element type,
950 // so use a truncating store.
951 SDValue EltPtr = GetVectorElementPointer(StackPtr, EltVT, Idx);
952 Type *VecType = VecVT.getTypeForEVT(*DAG.getContext());
953 unsigned Alignment = DAG.getDataLayout().getPrefTypeAlignment(VecType);
954 Store = DAG.getTruncStore(Store, dl, Elt, EltPtr, MachinePointerInfo(), EltVT,
957 // Load the Lo part from the stack slot.
958 Lo = DAG.getLoad(Lo.getValueType(), dl, Store, StackPtr, MachinePointerInfo(),
959 false, false, false, 0);
961 // Increment the pointer to the other part.
962 unsigned IncrementSize = Lo.getValueType().getSizeInBits() / 8;
963 StackPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr,
964 DAG.getConstant(IncrementSize, dl,
965 StackPtr.getValueType()));
967 // Load the Hi part from the stack slot.
968 Hi = DAG.getLoad(Hi.getValueType(), dl, Store, StackPtr, MachinePointerInfo(),
969 false, false, false, MinAlign(Alignment, IncrementSize));
972 void DAGTypeLegalizer::SplitVecRes_SCALAR_TO_VECTOR(SDNode *N, SDValue &Lo,
976 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(N->getValueType(0));
977 Lo = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LoVT, N->getOperand(0));
978 Hi = DAG.getUNDEF(HiVT);
981 void DAGTypeLegalizer::SplitVecRes_LOAD(LoadSDNode *LD, SDValue &Lo,
983 assert(ISD::isUNINDEXEDLoad(LD) && "Indexed load during type legalization!");
986 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(LD->getValueType(0));
988 ISD::LoadExtType ExtType = LD->getExtensionType();
989 SDValue Ch = LD->getChain();
990 SDValue Ptr = LD->getBasePtr();
991 SDValue Offset = DAG.getUNDEF(Ptr.getValueType());
992 EVT MemoryVT = LD->getMemoryVT();
993 unsigned Alignment = LD->getOriginalAlignment();
994 bool isVolatile = LD->isVolatile();
995 bool isNonTemporal = LD->isNonTemporal();
996 bool isInvariant = LD->isInvariant();
997 AAMDNodes AAInfo = LD->getAAInfo();
999 EVT LoMemVT, HiMemVT;
1000 std::tie(LoMemVT, HiMemVT) = DAG.GetSplitDestVTs(MemoryVT);
1002 Lo = DAG.getLoad(ISD::UNINDEXED, ExtType, LoVT, dl, Ch, Ptr, Offset,
1003 LD->getPointerInfo(), LoMemVT, isVolatile, isNonTemporal,
1004 isInvariant, Alignment, AAInfo);
1006 unsigned IncrementSize = LoMemVT.getSizeInBits()/8;
1007 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
1008 DAG.getConstant(IncrementSize, dl, Ptr.getValueType()));
1009 Hi = DAG.getLoad(ISD::UNINDEXED, ExtType, HiVT, dl, Ch, Ptr, Offset,
1010 LD->getPointerInfo().getWithOffset(IncrementSize),
1011 HiMemVT, isVolatile, isNonTemporal, isInvariant, Alignment,
1014 // Build a factor node to remember that this load is independent of the
1016 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
1019 // Legalized the chain result - switch anything that used the old chain to
1021 ReplaceValueWith(SDValue(LD, 1), Ch);
1024 void DAGTypeLegalizer::SplitVecRes_MLOAD(MaskedLoadSDNode *MLD,
1025 SDValue &Lo, SDValue &Hi) {
1028 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(MLD->getValueType(0));
1030 SDValue Ch = MLD->getChain();
1031 SDValue Ptr = MLD->getBasePtr();
1032 SDValue Mask = MLD->getMask();
1033 unsigned Alignment = MLD->getOriginalAlignment();
1034 ISD::LoadExtType ExtType = MLD->getExtensionType();
1036 // if Alignment is equal to the vector size,
1037 // take the half of it for the second part
1038 unsigned SecondHalfAlignment =
1039 (Alignment == MLD->getValueType(0).getSizeInBits()/8) ?
1040 Alignment/2 : Alignment;
1042 SDValue MaskLo, MaskHi;
1043 std::tie(MaskLo, MaskHi) = DAG.SplitVector(Mask, dl);
1045 EVT MemoryVT = MLD->getMemoryVT();
1046 EVT LoMemVT, HiMemVT;
1047 std::tie(LoMemVT, HiMemVT) = DAG.GetSplitDestVTs(MemoryVT);
1049 SDValue Src0 = MLD->getSrc0();
1050 SDValue Src0Lo, Src0Hi;
1051 std::tie(Src0Lo, Src0Hi) = DAG.SplitVector(Src0, dl);
1053 MachineMemOperand *MMO = DAG.getMachineFunction().
1054 getMachineMemOperand(MLD->getPointerInfo(),
1055 MachineMemOperand::MOLoad, LoMemVT.getStoreSize(),
1056 Alignment, MLD->getAAInfo(), MLD->getRanges());
1058 Lo = DAG.getMaskedLoad(LoVT, dl, Ch, Ptr, MaskLo, Src0Lo, LoMemVT, MMO,
1061 unsigned IncrementSize = LoMemVT.getSizeInBits()/8;
1062 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
1063 DAG.getConstant(IncrementSize, dl, Ptr.getValueType()));
1065 MMO = DAG.getMachineFunction().
1066 getMachineMemOperand(MLD->getPointerInfo(),
1067 MachineMemOperand::MOLoad, HiMemVT.getStoreSize(),
1068 SecondHalfAlignment, MLD->getAAInfo(), MLD->getRanges());
1070 Hi = DAG.getMaskedLoad(HiVT, dl, Ch, Ptr, MaskHi, Src0Hi, HiMemVT, MMO,
1074 // Build a factor node to remember that this load is independent of the
1076 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
1079 // Legalized the chain result - switch anything that used the old chain to
1081 ReplaceValueWith(SDValue(MLD, 1), Ch);
1085 void DAGTypeLegalizer::SplitVecRes_MGATHER(MaskedGatherSDNode *MGT,
1086 SDValue &Lo, SDValue &Hi) {
1089 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(MGT->getValueType(0));
1091 SDValue Ch = MGT->getChain();
1092 SDValue Ptr = MGT->getBasePtr();
1093 SDValue Mask = MGT->getMask();
1094 unsigned Alignment = MGT->getOriginalAlignment();
1096 SDValue MaskLo, MaskHi;
1097 std::tie(MaskLo, MaskHi) = DAG.SplitVector(Mask, dl);
1099 EVT MemoryVT = MGT->getMemoryVT();
1100 EVT LoMemVT, HiMemVT;
1101 std::tie(LoMemVT, HiMemVT) = DAG.GetSplitDestVTs(MemoryVT);
1103 SDValue Src0Lo, Src0Hi;
1104 std::tie(Src0Lo, Src0Hi) = DAG.SplitVector(MGT->getValue(), dl);
1106 SDValue IndexHi, IndexLo;
1107 std::tie(IndexLo, IndexHi) = DAG.SplitVector(MGT->getIndex(), dl);
1109 MachineMemOperand *MMO = DAG.getMachineFunction().
1110 getMachineMemOperand(MGT->getPointerInfo(),
1111 MachineMemOperand::MOLoad, LoMemVT.getStoreSize(),
1112 Alignment, MGT->getAAInfo(), MGT->getRanges());
1114 SDValue OpsLo[] = {Ch, Src0Lo, MaskLo, Ptr, IndexLo};
1115 Lo = DAG.getMaskedGather(DAG.getVTList(LoVT, MVT::Other), LoVT, dl, OpsLo,
1118 SDValue OpsHi[] = {Ch, Src0Hi, MaskHi, Ptr, IndexHi};
1119 Hi = DAG.getMaskedGather(DAG.getVTList(HiVT, MVT::Other), HiVT, dl, OpsHi,
1122 // Build a factor node to remember that this load is independent of the
1124 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
1127 // Legalized the chain result - switch anything that used the old chain to
1129 ReplaceValueWith(SDValue(MGT, 1), Ch);
1133 void DAGTypeLegalizer::SplitVecRes_SETCC(SDNode *N, SDValue &Lo, SDValue &Hi) {
1134 assert(N->getValueType(0).isVector() &&
1135 N->getOperand(0).getValueType().isVector() &&
1136 "Operand types must be vectors");
1140 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(N->getValueType(0));
1143 SDValue LL, LH, RL, RH;
1144 std::tie(LL, LH) = DAG.SplitVectorOperand(N, 0);
1145 std::tie(RL, RH) = DAG.SplitVectorOperand(N, 1);
1147 Lo = DAG.getNode(N->getOpcode(), DL, LoVT, LL, RL, N->getOperand(2));
1148 Hi = DAG.getNode(N->getOpcode(), DL, HiVT, LH, RH, N->getOperand(2));
1151 void DAGTypeLegalizer::SplitVecRes_UnaryOp(SDNode *N, SDValue &Lo,
1153 // Get the dest types - they may not match the input types, e.g. int_to_fp.
1156 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(N->getValueType(0));
1158 // If the input also splits, handle it directly for a compile time speedup.
1159 // Otherwise split it by hand.
1160 EVT InVT = N->getOperand(0).getValueType();
1161 if (getTypeAction(InVT) == TargetLowering::TypeSplitVector)
1162 GetSplitVector(N->getOperand(0), Lo, Hi);
1164 std::tie(Lo, Hi) = DAG.SplitVectorOperand(N, 0);
1166 if (N->getOpcode() == ISD::FP_ROUND) {
1167 Lo = DAG.getNode(N->getOpcode(), dl, LoVT, Lo, N->getOperand(1));
1168 Hi = DAG.getNode(N->getOpcode(), dl, HiVT, Hi, N->getOperand(1));
1169 } else if (N->getOpcode() == ISD::CONVERT_RNDSAT) {
1170 SDValue DTyOpLo = DAG.getValueType(LoVT);
1171 SDValue DTyOpHi = DAG.getValueType(HiVT);
1172 SDValue STyOpLo = DAG.getValueType(Lo.getValueType());
1173 SDValue STyOpHi = DAG.getValueType(Hi.getValueType());
1174 SDValue RndOp = N->getOperand(3);
1175 SDValue SatOp = N->getOperand(4);
1176 ISD::CvtCode CvtCode = cast<CvtRndSatSDNode>(N)->getCvtCode();
1177 Lo = DAG.getConvertRndSat(LoVT, dl, Lo, DTyOpLo, STyOpLo, RndOp, SatOp,
1179 Hi = DAG.getConvertRndSat(HiVT, dl, Hi, DTyOpHi, STyOpHi, RndOp, SatOp,
1182 Lo = DAG.getNode(N->getOpcode(), dl, LoVT, Lo);
1183 Hi = DAG.getNode(N->getOpcode(), dl, HiVT, Hi);
1187 void DAGTypeLegalizer::SplitVecRes_ExtendOp(SDNode *N, SDValue &Lo,
1190 EVT SrcVT = N->getOperand(0).getValueType();
1191 EVT DestVT = N->getValueType(0);
1193 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(DestVT);
1195 // We can do better than a generic split operation if the extend is doing
1196 // more than just doubling the width of the elements and the following are
1198 // - The number of vector elements is even,
1199 // - the source type is legal,
1200 // - the type of a split source is illegal,
1201 // - the type of an extended (by doubling element size) source is legal, and
1202 // - the type of that extended source when split is legal.
1204 // This won't necessarily completely legalize the operation, but it will
1205 // more effectively move in the right direction and prevent falling down
1206 // to scalarization in many cases due to the input vector being split too
1208 unsigned NumElements = SrcVT.getVectorNumElements();
1209 if ((NumElements & 1) == 0 &&
1210 SrcVT.getSizeInBits() * 2 < DestVT.getSizeInBits()) {
1211 LLVMContext &Ctx = *DAG.getContext();
1212 EVT NewSrcVT = EVT::getVectorVT(
1213 Ctx, EVT::getIntegerVT(
1214 Ctx, SrcVT.getVectorElementType().getSizeInBits() * 2),
1217 EVT::getVectorVT(Ctx, SrcVT.getVectorElementType(), NumElements / 2);
1218 EVT SplitLoVT, SplitHiVT;
1219 std::tie(SplitLoVT, SplitHiVT) = DAG.GetSplitDestVTs(NewSrcVT);
1220 if (TLI.isTypeLegal(SrcVT) && !TLI.isTypeLegal(SplitSrcVT) &&
1221 TLI.isTypeLegal(NewSrcVT) && TLI.isTypeLegal(SplitLoVT)) {
1222 DEBUG(dbgs() << "Split vector extend via incremental extend:";
1223 N->dump(&DAG); dbgs() << "\n");
1224 // Extend the source vector by one step.
1226 DAG.getNode(N->getOpcode(), dl, NewSrcVT, N->getOperand(0));
1227 // Get the low and high halves of the new, extended one step, vector.
1228 std::tie(Lo, Hi) = DAG.SplitVector(NewSrc, dl);
1229 // Extend those vector halves the rest of the way.
1230 Lo = DAG.getNode(N->getOpcode(), dl, LoVT, Lo);
1231 Hi = DAG.getNode(N->getOpcode(), dl, HiVT, Hi);
1235 // Fall back to the generic unary operator splitting otherwise.
1236 SplitVecRes_UnaryOp(N, Lo, Hi);
1239 void DAGTypeLegalizer::SplitVecRes_VECTOR_SHUFFLE(ShuffleVectorSDNode *N,
1240 SDValue &Lo, SDValue &Hi) {
1241 // The low and high parts of the original input give four input vectors.
1244 GetSplitVector(N->getOperand(0), Inputs[0], Inputs[1]);
1245 GetSplitVector(N->getOperand(1), Inputs[2], Inputs[3]);
1246 EVT NewVT = Inputs[0].getValueType();
1247 unsigned NewElts = NewVT.getVectorNumElements();
1249 // If Lo or Hi uses elements from at most two of the four input vectors, then
1250 // express it as a vector shuffle of those two inputs. Otherwise extract the
1251 // input elements by hand and construct the Lo/Hi output using a BUILD_VECTOR.
1252 SmallVector<int, 16> Ops;
1253 for (unsigned High = 0; High < 2; ++High) {
1254 SDValue &Output = High ? Hi : Lo;
1256 // Build a shuffle mask for the output, discovering on the fly which
1257 // input vectors to use as shuffle operands (recorded in InputUsed).
1258 // If building a suitable shuffle vector proves too hard, then bail
1259 // out with useBuildVector set.
1260 unsigned InputUsed[2] = { -1U, -1U }; // Not yet discovered.
1261 unsigned FirstMaskIdx = High * NewElts;
1262 bool useBuildVector = false;
1263 for (unsigned MaskOffset = 0; MaskOffset < NewElts; ++MaskOffset) {
1264 // The mask element. This indexes into the input.
1265 int Idx = N->getMaskElt(FirstMaskIdx + MaskOffset);
1267 // The input vector this mask element indexes into.
1268 unsigned Input = (unsigned)Idx / NewElts;
1270 if (Input >= array_lengthof(Inputs)) {
1271 // The mask element does not index into any input vector.
1276 // Turn the index into an offset from the start of the input vector.
1277 Idx -= Input * NewElts;
1279 // Find or create a shuffle vector operand to hold this input.
1281 for (OpNo = 0; OpNo < array_lengthof(InputUsed); ++OpNo) {
1282 if (InputUsed[OpNo] == Input) {
1283 // This input vector is already an operand.
1285 } else if (InputUsed[OpNo] == -1U) {
1286 // Create a new operand for this input vector.
1287 InputUsed[OpNo] = Input;
1292 if (OpNo >= array_lengthof(InputUsed)) {
1293 // More than two input vectors used! Give up on trying to create a
1294 // shuffle vector. Insert all elements into a BUILD_VECTOR instead.
1295 useBuildVector = true;
1299 // Add the mask index for the new shuffle vector.
1300 Ops.push_back(Idx + OpNo * NewElts);
1303 if (useBuildVector) {
1304 EVT EltVT = NewVT.getVectorElementType();
1305 SmallVector<SDValue, 16> SVOps;
1307 // Extract the input elements by hand.
1308 for (unsigned MaskOffset = 0; MaskOffset < NewElts; ++MaskOffset) {
1309 // The mask element. This indexes into the input.
1310 int Idx = N->getMaskElt(FirstMaskIdx + MaskOffset);
1312 // The input vector this mask element indexes into.
1313 unsigned Input = (unsigned)Idx / NewElts;
1315 if (Input >= array_lengthof(Inputs)) {
1316 // The mask element is "undef" or indexes off the end of the input.
1317 SVOps.push_back(DAG.getUNDEF(EltVT));
1321 // Turn the index into an offset from the start of the input vector.
1322 Idx -= Input * NewElts;
1324 // Extract the vector element by hand.
1325 SVOps.push_back(DAG.getNode(
1326 ISD::EXTRACT_VECTOR_ELT, dl, EltVT, Inputs[Input],
1327 DAG.getConstant(Idx, dl, TLI.getVectorIdxTy(DAG.getDataLayout()))));
1330 // Construct the Lo/Hi output using a BUILD_VECTOR.
1331 Output = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, SVOps);
1332 } else if (InputUsed[0] == -1U) {
1333 // No input vectors were used! The result is undefined.
1334 Output = DAG.getUNDEF(NewVT);
1336 SDValue Op0 = Inputs[InputUsed[0]];
1337 // If only one input was used, use an undefined vector for the other.
1338 SDValue Op1 = InputUsed[1] == -1U ?
1339 DAG.getUNDEF(NewVT) : Inputs[InputUsed[1]];
1340 // At least one input vector was used. Create a new shuffle vector.
1341 Output = DAG.getVectorShuffle(NewVT, dl, Op0, Op1, &Ops[0]);
1349 //===----------------------------------------------------------------------===//
1350 // Operand Vector Splitting
1351 //===----------------------------------------------------------------------===//
1353 /// SplitVectorOperand - This method is called when the specified operand of the
1354 /// specified node is found to need vector splitting. At this point, all of the
1355 /// result types of the node are known to be legal, but other operands of the
1356 /// node may need legalization as well as the specified one.
1357 bool DAGTypeLegalizer::SplitVectorOperand(SDNode *N, unsigned OpNo) {
1358 DEBUG(dbgs() << "Split node operand: ";
1361 SDValue Res = SDValue();
1363 // See if the target wants to custom split this node.
1364 if (CustomLowerNode(N, N->getOperand(OpNo).getValueType(), false))
1367 if (!Res.getNode()) {
1368 switch (N->getOpcode()) {
1371 dbgs() << "SplitVectorOperand Op #" << OpNo << ": ";
1375 report_fatal_error("Do not know how to split this operator's "
1378 case ISD::SETCC: Res = SplitVecOp_VSETCC(N); break;
1379 case ISD::BITCAST: Res = SplitVecOp_BITCAST(N); break;
1380 case ISD::EXTRACT_SUBVECTOR: Res = SplitVecOp_EXTRACT_SUBVECTOR(N); break;
1381 case ISD::EXTRACT_VECTOR_ELT:Res = SplitVecOp_EXTRACT_VECTOR_ELT(N); break;
1382 case ISD::CONCAT_VECTORS: Res = SplitVecOp_CONCAT_VECTORS(N); break;
1384 Res = SplitVecOp_TruncateHelper(N);
1386 case ISD::FP_ROUND: Res = SplitVecOp_FP_ROUND(N); break;
1387 case ISD::FCOPYSIGN: Res = SplitVecOp_FCOPYSIGN(N); break;
1389 Res = SplitVecOp_STORE(cast<StoreSDNode>(N), OpNo);
1392 Res = SplitVecOp_MSTORE(cast<MaskedStoreSDNode>(N), OpNo);
1395 Res = SplitVecOp_MSCATTER(cast<MaskedScatterSDNode>(N), OpNo);
1398 Res = SplitVecOp_MGATHER(cast<MaskedGatherSDNode>(N), OpNo);
1401 Res = SplitVecOp_VSELECT(N, OpNo);
1403 case ISD::FP_TO_SINT:
1404 case ISD::FP_TO_UINT:
1405 if (N->getValueType(0).bitsLT(N->getOperand(0)->getValueType(0)))
1406 Res = SplitVecOp_TruncateHelper(N);
1408 Res = SplitVecOp_UnaryOp(N);
1410 case ISD::SINT_TO_FP:
1411 case ISD::UINT_TO_FP:
1412 if (N->getValueType(0).bitsLT(N->getOperand(0)->getValueType(0)))
1413 Res = SplitVecOp_TruncateHelper(N);
1415 Res = SplitVecOp_UnaryOp(N);
1420 case ISD::FP_EXTEND:
1421 case ISD::SIGN_EXTEND:
1422 case ISD::ZERO_EXTEND:
1423 case ISD::ANY_EXTEND:
1425 Res = SplitVecOp_UnaryOp(N);
1430 // If the result is null, the sub-method took care of registering results etc.
1431 if (!Res.getNode()) return false;
1433 // If the result is N, the sub-method updated N in place. Tell the legalizer
1435 if (Res.getNode() == N)
1438 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 &&
1439 "Invalid operand expansion");
1441 ReplaceValueWith(SDValue(N, 0), Res);
1445 SDValue DAGTypeLegalizer::SplitVecOp_VSELECT(SDNode *N, unsigned OpNo) {
1446 // The only possibility for an illegal operand is the mask, since result type
1447 // legalization would have handled this node already otherwise.
1448 assert(OpNo == 0 && "Illegal operand must be mask");
1450 SDValue Mask = N->getOperand(0);
1451 SDValue Src0 = N->getOperand(1);
1452 SDValue Src1 = N->getOperand(2);
1453 EVT Src0VT = Src0.getValueType();
1455 assert(Mask.getValueType().isVector() && "VSELECT without a vector mask?");
1458 GetSplitVector(N->getOperand(0), Lo, Hi);
1459 assert(Lo.getValueType() == Hi.getValueType() &&
1460 "Lo and Hi have differing types");
1463 std::tie(LoOpVT, HiOpVT) = DAG.GetSplitDestVTs(Src0VT);
1464 assert(LoOpVT == HiOpVT && "Asymmetric vector split?");
1466 SDValue LoOp0, HiOp0, LoOp1, HiOp1, LoMask, HiMask;
1467 std::tie(LoOp0, HiOp0) = DAG.SplitVector(Src0, DL);
1468 std::tie(LoOp1, HiOp1) = DAG.SplitVector(Src1, DL);
1469 std::tie(LoMask, HiMask) = DAG.SplitVector(Mask, DL);
1472 DAG.getNode(ISD::VSELECT, DL, LoOpVT, LoMask, LoOp0, LoOp1);
1474 DAG.getNode(ISD::VSELECT, DL, HiOpVT, HiMask, HiOp0, HiOp1);
1476 return DAG.getNode(ISD::CONCAT_VECTORS, DL, Src0VT, LoSelect, HiSelect);
1479 SDValue DAGTypeLegalizer::SplitVecOp_UnaryOp(SDNode *N) {
1480 // The result has a legal vector type, but the input needs splitting.
1481 EVT ResVT = N->getValueType(0);
1484 GetSplitVector(N->getOperand(0), Lo, Hi);
1485 EVT InVT = Lo.getValueType();
1487 EVT OutVT = EVT::getVectorVT(*DAG.getContext(), ResVT.getVectorElementType(),
1488 InVT.getVectorNumElements());
1490 Lo = DAG.getNode(N->getOpcode(), dl, OutVT, Lo);
1491 Hi = DAG.getNode(N->getOpcode(), dl, OutVT, Hi);
1493 return DAG.getNode(ISD::CONCAT_VECTORS, dl, ResVT, Lo, Hi);
1496 SDValue DAGTypeLegalizer::SplitVecOp_BITCAST(SDNode *N) {
1497 // For example, i64 = BITCAST v4i16 on alpha. Typically the vector will
1498 // end up being split all the way down to individual components. Convert the
1499 // split pieces into integers and reassemble.
1501 GetSplitVector(N->getOperand(0), Lo, Hi);
1502 Lo = BitConvertToInteger(Lo);
1503 Hi = BitConvertToInteger(Hi);
1505 if (DAG.getDataLayout().isBigEndian())
1508 return DAG.getNode(ISD::BITCAST, SDLoc(N), N->getValueType(0),
1509 JoinIntegers(Lo, Hi));
1512 SDValue DAGTypeLegalizer::SplitVecOp_EXTRACT_SUBVECTOR(SDNode *N) {
1513 // We know that the extracted result type is legal.
1514 EVT SubVT = N->getValueType(0);
1515 SDValue Idx = N->getOperand(1);
1518 GetSplitVector(N->getOperand(0), Lo, Hi);
1520 uint64_t LoElts = Lo.getValueType().getVectorNumElements();
1521 uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
1523 if (IdxVal < LoElts) {
1524 assert(IdxVal + SubVT.getVectorNumElements() <= LoElts &&
1525 "Extracted subvector crosses vector split!");
1526 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, Lo, Idx);
1528 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, Hi,
1529 DAG.getConstant(IdxVal - LoElts, dl,
1530 Idx.getValueType()));
1534 SDValue DAGTypeLegalizer::SplitVecOp_EXTRACT_VECTOR_ELT(SDNode *N) {
1535 SDValue Vec = N->getOperand(0);
1536 SDValue Idx = N->getOperand(1);
1537 EVT VecVT = Vec.getValueType();
1539 if (isa<ConstantSDNode>(Idx)) {
1540 uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
1541 assert(IdxVal < VecVT.getVectorNumElements() && "Invalid vector index!");
1544 GetSplitVector(Vec, Lo, Hi);
1546 uint64_t LoElts = Lo.getValueType().getVectorNumElements();
1548 if (IdxVal < LoElts)
1549 return SDValue(DAG.UpdateNodeOperands(N, Lo, Idx), 0);
1550 return SDValue(DAG.UpdateNodeOperands(N, Hi,
1551 DAG.getConstant(IdxVal - LoElts, SDLoc(N),
1552 Idx.getValueType())), 0);
1555 // See if the target wants to custom expand this node.
1556 if (CustomLowerNode(N, N->getValueType(0), true))
1559 // Make the vector elements byte-addressable if they aren't already.
1561 EVT EltVT = VecVT.getVectorElementType();
1562 if (EltVT.getSizeInBits() < 8) {
1563 SmallVector<SDValue, 4> ElementOps;
1564 for (unsigned i = 0; i < VecVT.getVectorNumElements(); ++i) {
1565 ElementOps.push_back(DAG.getAnyExtOrTrunc(
1566 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, Vec,
1567 DAG.getConstant(i, dl, MVT::i8)),
1572 VecVT = EVT::getVectorVT(*DAG.getContext(), EltVT,
1573 VecVT.getVectorNumElements());
1574 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, VecVT, ElementOps);
1577 // Store the vector to the stack.
1578 SDValue StackPtr = DAG.CreateStackTemporary(VecVT);
1579 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Vec, StackPtr,
1580 MachinePointerInfo(), false, false, 0);
1582 // Load back the required element.
1583 StackPtr = GetVectorElementPointer(StackPtr, EltVT, Idx);
1584 return DAG.getExtLoad(ISD::EXTLOAD, dl, N->getValueType(0), Store, StackPtr,
1585 MachinePointerInfo(), EltVT, false, false, false, 0);
1588 SDValue DAGTypeLegalizer::SplitVecOp_MGATHER(MaskedGatherSDNode *MGT,
1592 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(MGT->getValueType(0));
1594 SDValue Ch = MGT->getChain();
1595 SDValue Ptr = MGT->getBasePtr();
1596 SDValue Index = MGT->getIndex();
1597 SDValue Mask = MGT->getMask();
1598 unsigned Alignment = MGT->getOriginalAlignment();
1600 SDValue MaskLo, MaskHi;
1601 std::tie(MaskLo, MaskHi) = DAG.SplitVector(Mask, dl);
1603 EVT MemoryVT = MGT->getMemoryVT();
1604 EVT LoMemVT, HiMemVT;
1605 std::tie(LoMemVT, HiMemVT) = DAG.GetSplitDestVTs(MemoryVT);
1607 SDValue Src0Lo, Src0Hi;
1608 std::tie(Src0Lo, Src0Hi) = DAG.SplitVector(MGT->getValue(), dl);
1610 SDValue IndexHi, IndexLo;
1611 if (Index.getNode())
1612 std::tie(IndexLo, IndexHi) = DAG.SplitVector(Index, dl);
1614 IndexLo = IndexHi = Index;
1616 MachineMemOperand *MMO = DAG.getMachineFunction().
1617 getMachineMemOperand(MGT->getPointerInfo(),
1618 MachineMemOperand::MOLoad, LoMemVT.getStoreSize(),
1619 Alignment, MGT->getAAInfo(), MGT->getRanges());
1621 SDValue OpsLo[] = {Ch, Src0Lo, MaskLo, Ptr, IndexLo};
1622 SDValue Lo = DAG.getMaskedGather(DAG.getVTList(LoVT, MVT::Other), LoVT, dl,
1625 MMO = DAG.getMachineFunction().
1626 getMachineMemOperand(MGT->getPointerInfo(),
1627 MachineMemOperand::MOLoad, HiMemVT.getStoreSize(),
1628 Alignment, MGT->getAAInfo(),
1631 SDValue OpsHi[] = {Ch, Src0Hi, MaskHi, Ptr, IndexHi};
1632 SDValue Hi = DAG.getMaskedGather(DAG.getVTList(HiVT, MVT::Other), HiVT, dl,
1635 // Build a factor node to remember that this load is independent of the
1637 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
1640 // Legalized the chain result - switch anything that used the old chain to
1642 ReplaceValueWith(SDValue(MGT, 1), Ch);
1644 SDValue Res = DAG.getNode(ISD::CONCAT_VECTORS, dl, MGT->getValueType(0), Lo,
1646 ReplaceValueWith(SDValue(MGT, 0), Res);
1650 SDValue DAGTypeLegalizer::SplitVecOp_MSTORE(MaskedStoreSDNode *N,
1652 SDValue Ch = N->getChain();
1653 SDValue Ptr = N->getBasePtr();
1654 SDValue Mask = N->getMask();
1655 SDValue Data = N->getValue();
1656 EVT MemoryVT = N->getMemoryVT();
1657 unsigned Alignment = N->getOriginalAlignment();
1660 EVT LoMemVT, HiMemVT;
1661 std::tie(LoMemVT, HiMemVT) = DAG.GetSplitDestVTs(MemoryVT);
1663 SDValue DataLo, DataHi;
1664 GetSplitVector(Data, DataLo, DataHi);
1665 SDValue MaskLo, MaskHi;
1666 GetSplitVector(Mask, MaskLo, MaskHi);
1668 // if Alignment is equal to the vector size,
1669 // take the half of it for the second part
1670 unsigned SecondHalfAlignment =
1671 (Alignment == Data->getValueType(0).getSizeInBits()/8) ?
1672 Alignment/2 : Alignment;
1675 MachineMemOperand *MMO = DAG.getMachineFunction().
1676 getMachineMemOperand(N->getPointerInfo(),
1677 MachineMemOperand::MOStore, LoMemVT.getStoreSize(),
1678 Alignment, N->getAAInfo(), N->getRanges());
1680 Lo = DAG.getMaskedStore(Ch, DL, DataLo, Ptr, MaskLo, LoMemVT, MMO,
1681 N->isTruncatingStore());
1683 unsigned IncrementSize = LoMemVT.getSizeInBits()/8;
1684 Ptr = DAG.getNode(ISD::ADD, DL, Ptr.getValueType(), Ptr,
1685 DAG.getConstant(IncrementSize, DL, Ptr.getValueType()));
1687 MMO = DAG.getMachineFunction().
1688 getMachineMemOperand(N->getPointerInfo(),
1689 MachineMemOperand::MOStore, HiMemVT.getStoreSize(),
1690 SecondHalfAlignment, N->getAAInfo(), N->getRanges());
1692 Hi = DAG.getMaskedStore(Ch, DL, DataHi, Ptr, MaskHi, HiMemVT, MMO,
1693 N->isTruncatingStore());
1695 // Build a factor node to remember that this store is independent of the
1697 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Lo, Hi);
1700 SDValue DAGTypeLegalizer::SplitVecOp_MSCATTER(MaskedScatterSDNode *N,
1702 SDValue Ch = N->getChain();
1703 SDValue Ptr = N->getBasePtr();
1704 SDValue Mask = N->getMask();
1705 SDValue Index = N->getIndex();
1706 SDValue Data = N->getValue();
1707 EVT MemoryVT = N->getMemoryVT();
1708 unsigned Alignment = N->getOriginalAlignment();
1711 EVT LoMemVT, HiMemVT;
1712 std::tie(LoMemVT, HiMemVT) = DAG.GetSplitDestVTs(MemoryVT);
1714 SDValue DataLo, DataHi;
1715 GetSplitVector(Data, DataLo, DataHi);
1716 SDValue MaskLo, MaskHi;
1717 GetSplitVector(Mask, MaskLo, MaskHi);
1719 SDValue PtrLo, PtrHi;
1720 if (Ptr.getValueType().isVector()) // gather form vector of pointers
1721 std::tie(PtrLo, PtrHi) = DAG.SplitVector(Ptr, DL);
1723 PtrLo = PtrHi = Ptr;
1725 SDValue IndexHi, IndexLo;
1726 if (Index.getNode())
1727 std::tie(IndexLo, IndexHi) = DAG.SplitVector(Index, DL);
1729 IndexLo = IndexHi = Index;
1732 MachineMemOperand *MMO = DAG.getMachineFunction().
1733 getMachineMemOperand(N->getPointerInfo(),
1734 MachineMemOperand::MOStore, LoMemVT.getStoreSize(),
1735 Alignment, N->getAAInfo(), N->getRanges());
1737 SDValue OpsLo[] = {Ch, DataLo, MaskLo, PtrLo, IndexLo};
1738 Lo = DAG.getMaskedScatter(DAG.getVTList(MVT::Other), DataLo.getValueType(),
1741 MMO = DAG.getMachineFunction().
1742 getMachineMemOperand(N->getPointerInfo(),
1743 MachineMemOperand::MOStore, HiMemVT.getStoreSize(),
1744 Alignment, N->getAAInfo(), N->getRanges());
1746 SDValue OpsHi[] = {Ch, DataHi, MaskHi, PtrHi, IndexHi};
1747 Hi = DAG.getMaskedScatter(DAG.getVTList(MVT::Other), DataHi.getValueType(),
1750 // Build a factor node to remember that this store is independent of the
1752 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Lo, Hi);
1755 SDValue DAGTypeLegalizer::SplitVecOp_STORE(StoreSDNode *N, unsigned OpNo) {
1756 assert(N->isUnindexed() && "Indexed store of vector?");
1757 assert(OpNo == 1 && "Can only split the stored value");
1760 bool isTruncating = N->isTruncatingStore();
1761 SDValue Ch = N->getChain();
1762 SDValue Ptr = N->getBasePtr();
1763 EVT MemoryVT = N->getMemoryVT();
1764 unsigned Alignment = N->getOriginalAlignment();
1765 bool isVol = N->isVolatile();
1766 bool isNT = N->isNonTemporal();
1767 AAMDNodes AAInfo = N->getAAInfo();
1769 GetSplitVector(N->getOperand(1), Lo, Hi);
1771 EVT LoMemVT, HiMemVT;
1772 std::tie(LoMemVT, HiMemVT) = DAG.GetSplitDestVTs(MemoryVT);
1774 unsigned IncrementSize = LoMemVT.getSizeInBits()/8;
1777 Lo = DAG.getTruncStore(Ch, DL, Lo, Ptr, N->getPointerInfo(),
1778 LoMemVT, isVol, isNT, Alignment, AAInfo);
1780 Lo = DAG.getStore(Ch, DL, Lo, Ptr, N->getPointerInfo(),
1781 isVol, isNT, Alignment, AAInfo);
1783 // Increment the pointer to the other half.
1784 Ptr = DAG.getNode(ISD::ADD, DL, Ptr.getValueType(), Ptr,
1785 DAG.getConstant(IncrementSize, DL, Ptr.getValueType()));
1788 Hi = DAG.getTruncStore(Ch, DL, Hi, Ptr,
1789 N->getPointerInfo().getWithOffset(IncrementSize),
1790 HiMemVT, isVol, isNT, Alignment, AAInfo);
1792 Hi = DAG.getStore(Ch, DL, Hi, Ptr,
1793 N->getPointerInfo().getWithOffset(IncrementSize),
1794 isVol, isNT, Alignment, AAInfo);
1796 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Lo, Hi);
1799 SDValue DAGTypeLegalizer::SplitVecOp_CONCAT_VECTORS(SDNode *N) {
1802 // The input operands all must have the same type, and we know the result
1803 // type is valid. Convert this to a buildvector which extracts all the
1805 // TODO: If the input elements are power-two vectors, we could convert this to
1806 // a new CONCAT_VECTORS node with elements that are half-wide.
1807 SmallVector<SDValue, 32> Elts;
1808 EVT EltVT = N->getValueType(0).getVectorElementType();
1809 for (const SDValue &Op : N->op_values()) {
1810 for (unsigned i = 0, e = Op.getValueType().getVectorNumElements();
1812 Elts.push_back(DAG.getNode(
1813 ISD::EXTRACT_VECTOR_ELT, DL, EltVT, Op,
1814 DAG.getConstant(i, DL, TLI.getVectorIdxTy(DAG.getDataLayout()))));
1818 return DAG.getNode(ISD::BUILD_VECTOR, DL, N->getValueType(0), Elts);
1821 SDValue DAGTypeLegalizer::SplitVecOp_TruncateHelper(SDNode *N) {
1822 // The result type is legal, but the input type is illegal. If splitting
1823 // ends up with the result type of each half still being legal, just
1824 // do that. If, however, that would result in an illegal result type,
1825 // we can try to get more clever with power-two vectors. Specifically,
1826 // split the input type, but also widen the result element size, then
1827 // concatenate the halves and truncate again. For example, consider a target
1828 // where v8i8 is legal and v8i32 is not (ARM, which doesn't have 256-bit
1829 // vectors). To perform a "%res = v8i8 trunc v8i32 %in" we do:
1830 // %inlo = v4i32 extract_subvector %in, 0
1831 // %inhi = v4i32 extract_subvector %in, 4
1832 // %lo16 = v4i16 trunc v4i32 %inlo
1833 // %hi16 = v4i16 trunc v4i32 %inhi
1834 // %in16 = v8i16 concat_vectors v4i16 %lo16, v4i16 %hi16
1835 // %res = v8i8 trunc v8i16 %in16
1837 // Without this transform, the original truncate would end up being
1838 // scalarized, which is pretty much always a last resort.
1839 SDValue InVec = N->getOperand(0);
1840 EVT InVT = InVec->getValueType(0);
1841 EVT OutVT = N->getValueType(0);
1842 unsigned NumElements = OutVT.getVectorNumElements();
1843 bool IsFloat = OutVT.isFloatingPoint();
1845 // Widening should have already made sure this is a power-two vector
1846 // if we're trying to split it at all. assert() that's true, just in case.
1847 assert(!(NumElements & 1) && "Splitting vector, but not in half!");
1849 unsigned InElementSize = InVT.getVectorElementType().getSizeInBits();
1850 unsigned OutElementSize = OutVT.getVectorElementType().getSizeInBits();
1852 // If the input elements are only 1/2 the width of the result elements,
1853 // just use the normal splitting. Our trick only work if there's room
1854 // to split more than once.
1855 if (InElementSize <= OutElementSize * 2)
1856 return SplitVecOp_UnaryOp(N);
1859 // Extract the halves of the input via extract_subvector.
1860 SDValue InLoVec, InHiVec;
1861 std::tie(InLoVec, InHiVec) = DAG.SplitVector(InVec, DL);
1862 // Truncate them to 1/2 the element size.
1863 EVT HalfElementVT = IsFloat ?
1864 EVT::getFloatingPointVT(InElementSize/2) :
1865 EVT::getIntegerVT(*DAG.getContext(), InElementSize/2);
1866 EVT HalfVT = EVT::getVectorVT(*DAG.getContext(), HalfElementVT,
1868 SDValue HalfLo = DAG.getNode(N->getOpcode(), DL, HalfVT, InLoVec);
1869 SDValue HalfHi = DAG.getNode(N->getOpcode(), DL, HalfVT, InHiVec);
1870 // Concatenate them to get the full intermediate truncation result.
1871 EVT InterVT = EVT::getVectorVT(*DAG.getContext(), HalfElementVT, NumElements);
1872 SDValue InterVec = DAG.getNode(ISD::CONCAT_VECTORS, DL, InterVT, HalfLo,
1874 // Now finish up by truncating all the way down to the original result
1875 // type. This should normally be something that ends up being legal directly,
1876 // but in theory if a target has very wide vectors and an annoyingly
1877 // restricted set of legal types, this split can chain to build things up.
1879 ? DAG.getNode(ISD::FP_ROUND, DL, OutVT, InterVec,
1880 DAG.getTargetConstant(
1881 0, DL, TLI.getPointerTy(DAG.getDataLayout())))
1882 : DAG.getNode(ISD::TRUNCATE, DL, OutVT, InterVec);
1885 SDValue DAGTypeLegalizer::SplitVecOp_VSETCC(SDNode *N) {
1886 assert(N->getValueType(0).isVector() &&
1887 N->getOperand(0).getValueType().isVector() &&
1888 "Operand types must be vectors");
1889 // The result has a legal vector type, but the input needs splitting.
1890 SDValue Lo0, Hi0, Lo1, Hi1, LoRes, HiRes;
1892 GetSplitVector(N->getOperand(0), Lo0, Hi0);
1893 GetSplitVector(N->getOperand(1), Lo1, Hi1);
1894 unsigned PartElements = Lo0.getValueType().getVectorNumElements();
1895 EVT PartResVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1, PartElements);
1896 EVT WideResVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1, 2*PartElements);
1898 LoRes = DAG.getNode(ISD::SETCC, DL, PartResVT, Lo0, Lo1, N->getOperand(2));
1899 HiRes = DAG.getNode(ISD::SETCC, DL, PartResVT, Hi0, Hi1, N->getOperand(2));
1900 SDValue Con = DAG.getNode(ISD::CONCAT_VECTORS, DL, WideResVT, LoRes, HiRes);
1901 return PromoteTargetBoolean(Con, N->getValueType(0));
1905 SDValue DAGTypeLegalizer::SplitVecOp_FP_ROUND(SDNode *N) {
1906 // The result has a legal vector type, but the input needs splitting.
1907 EVT ResVT = N->getValueType(0);
1910 GetSplitVector(N->getOperand(0), Lo, Hi);
1911 EVT InVT = Lo.getValueType();
1913 EVT OutVT = EVT::getVectorVT(*DAG.getContext(), ResVT.getVectorElementType(),
1914 InVT.getVectorNumElements());
1916 Lo = DAG.getNode(ISD::FP_ROUND, DL, OutVT, Lo, N->getOperand(1));
1917 Hi = DAG.getNode(ISD::FP_ROUND, DL, OutVT, Hi, N->getOperand(1));
1919 return DAG.getNode(ISD::CONCAT_VECTORS, DL, ResVT, Lo, Hi);
1922 SDValue DAGTypeLegalizer::SplitVecOp_FCOPYSIGN(SDNode *N) {
1923 // The result (and the first input) has a legal vector type, but the second
1924 // input needs splitting.
1925 return DAG.UnrollVectorOp(N, N->getValueType(0).getVectorNumElements());
1929 //===----------------------------------------------------------------------===//
1930 // Result Vector Widening
1931 //===----------------------------------------------------------------------===//
1933 void DAGTypeLegalizer::WidenVectorResult(SDNode *N, unsigned ResNo) {
1934 DEBUG(dbgs() << "Widen node result " << ResNo << ": ";
1938 // See if the target wants to custom widen this node.
1939 if (CustomWidenLowerNode(N, N->getValueType(ResNo)))
1942 SDValue Res = SDValue();
1943 switch (N->getOpcode()) {
1946 dbgs() << "WidenVectorResult #" << ResNo << ": ";
1950 llvm_unreachable("Do not know how to widen the result of this operator!");
1952 case ISD::MERGE_VALUES: Res = WidenVecRes_MERGE_VALUES(N, ResNo); break;
1953 case ISD::BITCAST: Res = WidenVecRes_BITCAST(N); break;
1954 case ISD::BUILD_VECTOR: Res = WidenVecRes_BUILD_VECTOR(N); break;
1955 case ISD::CONCAT_VECTORS: Res = WidenVecRes_CONCAT_VECTORS(N); break;
1956 case ISD::CONVERT_RNDSAT: Res = WidenVecRes_CONVERT_RNDSAT(N); break;
1957 case ISD::EXTRACT_SUBVECTOR: Res = WidenVecRes_EXTRACT_SUBVECTOR(N); break;
1958 case ISD::FP_ROUND_INREG: Res = WidenVecRes_InregOp(N); break;
1959 case ISD::INSERT_VECTOR_ELT: Res = WidenVecRes_INSERT_VECTOR_ELT(N); break;
1960 case ISD::LOAD: Res = WidenVecRes_LOAD(N); break;
1961 case ISD::SCALAR_TO_VECTOR: Res = WidenVecRes_SCALAR_TO_VECTOR(N); break;
1962 case ISD::SIGN_EXTEND_INREG: Res = WidenVecRes_InregOp(N); break;
1964 case ISD::SELECT: Res = WidenVecRes_SELECT(N); break;
1965 case ISD::SELECT_CC: Res = WidenVecRes_SELECT_CC(N); break;
1966 case ISD::SETCC: Res = WidenVecRes_SETCC(N); break;
1967 case ISD::UNDEF: Res = WidenVecRes_UNDEF(N); break;
1968 case ISD::VECTOR_SHUFFLE:
1969 Res = WidenVecRes_VECTOR_SHUFFLE(cast<ShuffleVectorSDNode>(N));
1972 Res = WidenVecRes_MLOAD(cast<MaskedLoadSDNode>(N));
1987 Res = WidenVecRes_Binary(N);
2000 Res = WidenVecRes_BinaryCanTrap(N);
2003 case ISD::FCOPYSIGN:
2004 Res = WidenVecRes_FCOPYSIGN(N);
2008 Res = WidenVecRes_POWI(N);
2014 Res = WidenVecRes_Shift(N);
2017 case ISD::ANY_EXTEND:
2018 case ISD::FP_EXTEND:
2020 case ISD::FP_TO_SINT:
2021 case ISD::FP_TO_UINT:
2022 case ISD::SIGN_EXTEND:
2023 case ISD::SINT_TO_FP:
2025 case ISD::UINT_TO_FP:
2026 case ISD::ZERO_EXTEND:
2027 Res = WidenVecRes_Convert(N);
2043 case ISD::FNEARBYINT:
2050 Res = WidenVecRes_Unary(N);
2053 Res = WidenVecRes_Ternary(N);
2057 // If Res is null, the sub-method took care of registering the result.
2059 SetWidenedVector(SDValue(N, ResNo), Res);
2062 SDValue DAGTypeLegalizer::WidenVecRes_Ternary(SDNode *N) {
2063 // Ternary op widening.
2065 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2066 SDValue InOp1 = GetWidenedVector(N->getOperand(0));
2067 SDValue InOp2 = GetWidenedVector(N->getOperand(1));
2068 SDValue InOp3 = GetWidenedVector(N->getOperand(2));
2069 return DAG.getNode(N->getOpcode(), dl, WidenVT, InOp1, InOp2, InOp3);
2072 SDValue DAGTypeLegalizer::WidenVecRes_Binary(SDNode *N) {
2073 // Binary op widening.
2075 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2076 SDValue InOp1 = GetWidenedVector(N->getOperand(0));
2077 SDValue InOp2 = GetWidenedVector(N->getOperand(1));
2078 return DAG.getNode(N->getOpcode(), dl, WidenVT, InOp1, InOp2, N->getFlags());
2081 SDValue DAGTypeLegalizer::WidenVecRes_BinaryCanTrap(SDNode *N) {
2082 // Binary op widening for operations that can trap.
2083 unsigned Opcode = N->getOpcode();
2085 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2086 EVT WidenEltVT = WidenVT.getVectorElementType();
2088 unsigned NumElts = VT.getVectorNumElements();
2089 const SDNodeFlags *Flags = N->getFlags();
2090 while (!TLI.isTypeLegal(VT) && NumElts != 1) {
2091 NumElts = NumElts / 2;
2092 VT = EVT::getVectorVT(*DAG.getContext(), WidenEltVT, NumElts);
2095 if (NumElts != 1 && !TLI.canOpTrap(N->getOpcode(), VT)) {
2096 // Operation doesn't trap so just widen as normal.
2097 SDValue InOp1 = GetWidenedVector(N->getOperand(0));
2098 SDValue InOp2 = GetWidenedVector(N->getOperand(1));
2099 return DAG.getNode(N->getOpcode(), dl, WidenVT, InOp1, InOp2, Flags);
2102 // No legal vector version so unroll the vector operation and then widen.
2104 return DAG.UnrollVectorOp(N, WidenVT.getVectorNumElements());
2106 // Since the operation can trap, apply operation on the original vector.
2108 SDValue InOp1 = GetWidenedVector(N->getOperand(0));
2109 SDValue InOp2 = GetWidenedVector(N->getOperand(1));
2110 unsigned CurNumElts = N->getValueType(0).getVectorNumElements();
2112 SmallVector<SDValue, 16> ConcatOps(CurNumElts);
2113 unsigned ConcatEnd = 0; // Current ConcatOps index.
2114 int Idx = 0; // Current Idx into input vectors.
2116 // NumElts := greatest legal vector size (at most WidenVT)
2117 // while (orig. vector has unhandled elements) {
2118 // take munches of size NumElts from the beginning and add to ConcatOps
2119 // NumElts := next smaller supported vector size or 1
2121 while (CurNumElts != 0) {
2122 while (CurNumElts >= NumElts) {
2123 SDValue EOp1 = DAG.getNode(
2124 ISD::EXTRACT_SUBVECTOR, dl, VT, InOp1,
2125 DAG.getConstant(Idx, dl, TLI.getVectorIdxTy(DAG.getDataLayout())));
2126 SDValue EOp2 = DAG.getNode(
2127 ISD::EXTRACT_SUBVECTOR, dl, VT, InOp2,
2128 DAG.getConstant(Idx, dl, TLI.getVectorIdxTy(DAG.getDataLayout())));
2129 ConcatOps[ConcatEnd++] = DAG.getNode(Opcode, dl, VT, EOp1, EOp2, Flags);
2131 CurNumElts -= NumElts;
2134 NumElts = NumElts / 2;
2135 VT = EVT::getVectorVT(*DAG.getContext(), WidenEltVT, NumElts);
2136 } while (!TLI.isTypeLegal(VT) && NumElts != 1);
2139 for (unsigned i = 0; i != CurNumElts; ++i, ++Idx) {
2140 SDValue EOp1 = DAG.getNode(
2141 ISD::EXTRACT_VECTOR_ELT, dl, WidenEltVT, InOp1,
2142 DAG.getConstant(Idx, dl, TLI.getVectorIdxTy(DAG.getDataLayout())));
2143 SDValue EOp2 = DAG.getNode(
2144 ISD::EXTRACT_VECTOR_ELT, dl, WidenEltVT, InOp2,
2145 DAG.getConstant(Idx, dl, TLI.getVectorIdxTy(DAG.getDataLayout())));
2146 ConcatOps[ConcatEnd++] = DAG.getNode(Opcode, dl, WidenEltVT,
2153 // Check to see if we have a single operation with the widen type.
2154 if (ConcatEnd == 1) {
2155 VT = ConcatOps[0].getValueType();
2157 return ConcatOps[0];
2160 // while (Some element of ConcatOps is not of type MaxVT) {
2161 // From the end of ConcatOps, collect elements of the same type and put
2162 // them into an op of the next larger supported type
2164 while (ConcatOps[ConcatEnd-1].getValueType() != MaxVT) {
2165 Idx = ConcatEnd - 1;
2166 VT = ConcatOps[Idx--].getValueType();
2167 while (Idx >= 0 && ConcatOps[Idx].getValueType() == VT)
2170 int NextSize = VT.isVector() ? VT.getVectorNumElements() : 1;
2174 NextVT = EVT::getVectorVT(*DAG.getContext(), WidenEltVT, NextSize);
2175 } while (!TLI.isTypeLegal(NextVT));
2177 if (!VT.isVector()) {
2178 // Scalar type, create an INSERT_VECTOR_ELEMENT of type NextVT
2179 SDValue VecOp = DAG.getUNDEF(NextVT);
2180 unsigned NumToInsert = ConcatEnd - Idx - 1;
2181 for (unsigned i = 0, OpIdx = Idx+1; i < NumToInsert; i++, OpIdx++) {
2182 VecOp = DAG.getNode(
2183 ISD::INSERT_VECTOR_ELT, dl, NextVT, VecOp, ConcatOps[OpIdx],
2184 DAG.getConstant(i, dl, TLI.getVectorIdxTy(DAG.getDataLayout())));
2186 ConcatOps[Idx+1] = VecOp;
2187 ConcatEnd = Idx + 2;
2189 // Vector type, create a CONCAT_VECTORS of type NextVT
2190 SDValue undefVec = DAG.getUNDEF(VT);
2191 unsigned OpsToConcat = NextSize/VT.getVectorNumElements();
2192 SmallVector<SDValue, 16> SubConcatOps(OpsToConcat);
2193 unsigned RealVals = ConcatEnd - Idx - 1;
2194 unsigned SubConcatEnd = 0;
2195 unsigned SubConcatIdx = Idx + 1;
2196 while (SubConcatEnd < RealVals)
2197 SubConcatOps[SubConcatEnd++] = ConcatOps[++Idx];
2198 while (SubConcatEnd < OpsToConcat)
2199 SubConcatOps[SubConcatEnd++] = undefVec;
2200 ConcatOps[SubConcatIdx] = DAG.getNode(ISD::CONCAT_VECTORS, dl,
2201 NextVT, SubConcatOps);
2202 ConcatEnd = SubConcatIdx + 1;
2206 // Check to see if we have a single operation with the widen type.
2207 if (ConcatEnd == 1) {
2208 VT = ConcatOps[0].getValueType();
2210 return ConcatOps[0];
2213 // add undefs of size MaxVT until ConcatOps grows to length of WidenVT
2214 unsigned NumOps = WidenVT.getVectorNumElements()/MaxVT.getVectorNumElements();
2215 if (NumOps != ConcatEnd ) {
2216 SDValue UndefVal = DAG.getUNDEF(MaxVT);
2217 for (unsigned j = ConcatEnd; j < NumOps; ++j)
2218 ConcatOps[j] = UndefVal;
2220 return DAG.getNode(ISD::CONCAT_VECTORS, dl, WidenVT,
2221 makeArrayRef(ConcatOps.data(), NumOps));
2224 SDValue DAGTypeLegalizer::WidenVecRes_Convert(SDNode *N) {
2225 SDValue InOp = N->getOperand(0);
2228 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2229 unsigned WidenNumElts = WidenVT.getVectorNumElements();
2231 EVT InVT = InOp.getValueType();
2232 EVT InEltVT = InVT.getVectorElementType();
2233 EVT InWidenVT = EVT::getVectorVT(*DAG.getContext(), InEltVT, WidenNumElts);
2235 unsigned Opcode = N->getOpcode();
2236 unsigned InVTNumElts = InVT.getVectorNumElements();
2237 const SDNodeFlags *Flags = N->getFlags();
2238 if (getTypeAction(InVT) == TargetLowering::TypeWidenVector) {
2239 InOp = GetWidenedVector(N->getOperand(0));
2240 InVT = InOp.getValueType();
2241 InVTNumElts = InVT.getVectorNumElements();
2242 if (InVTNumElts == WidenNumElts) {
2243 if (N->getNumOperands() == 1)
2244 return DAG.getNode(Opcode, DL, WidenVT, InOp);
2245 return DAG.getNode(Opcode, DL, WidenVT, InOp, N->getOperand(1), Flags);
2249 if (TLI.isTypeLegal(InWidenVT)) {
2250 // Because the result and the input are different vector types, widening
2251 // the result could create a legal type but widening the input might make
2252 // it an illegal type that might lead to repeatedly splitting the input
2253 // and then widening it. To avoid this, we widen the input only if
2254 // it results in a legal type.
2255 if (WidenNumElts % InVTNumElts == 0) {
2256 // Widen the input and call convert on the widened input vector.
2257 unsigned NumConcat = WidenNumElts/InVTNumElts;
2258 SmallVector<SDValue, 16> Ops(NumConcat);
2260 SDValue UndefVal = DAG.getUNDEF(InVT);
2261 for (unsigned i = 1; i != NumConcat; ++i)
2263 SDValue InVec = DAG.getNode(ISD::CONCAT_VECTORS, DL, InWidenVT, Ops);
2264 if (N->getNumOperands() == 1)
2265 return DAG.getNode(Opcode, DL, WidenVT, InVec);
2266 return DAG.getNode(Opcode, DL, WidenVT, InVec, N->getOperand(1), Flags);
2269 if (InVTNumElts % WidenNumElts == 0) {
2270 SDValue InVal = DAG.getNode(
2271 ISD::EXTRACT_SUBVECTOR, DL, InWidenVT, InOp,
2272 DAG.getConstant(0, DL, TLI.getVectorIdxTy(DAG.getDataLayout())));
2273 // Extract the input and convert the shorten input vector.
2274 if (N->getNumOperands() == 1)
2275 return DAG.getNode(Opcode, DL, WidenVT, InVal);
2276 return DAG.getNode(Opcode, DL, WidenVT, InVal, N->getOperand(1), Flags);
2280 // Otherwise unroll into some nasty scalar code and rebuild the vector.
2281 SmallVector<SDValue, 16> Ops(WidenNumElts);
2282 EVT EltVT = WidenVT.getVectorElementType();
2283 unsigned MinElts = std::min(InVTNumElts, WidenNumElts);
2285 for (i=0; i < MinElts; ++i) {
2286 SDValue Val = DAG.getNode(
2287 ISD::EXTRACT_VECTOR_ELT, DL, InEltVT, InOp,
2288 DAG.getConstant(i, DL, TLI.getVectorIdxTy(DAG.getDataLayout())));
2289 if (N->getNumOperands() == 1)
2290 Ops[i] = DAG.getNode(Opcode, DL, EltVT, Val);
2292 Ops[i] = DAG.getNode(Opcode, DL, EltVT, Val, N->getOperand(1), Flags);
2295 SDValue UndefVal = DAG.getUNDEF(EltVT);
2296 for (; i < WidenNumElts; ++i)
2299 return DAG.getNode(ISD::BUILD_VECTOR, DL, WidenVT, Ops);
2302 SDValue DAGTypeLegalizer::WidenVecRes_FCOPYSIGN(SDNode *N) {
2303 // If this is an FCOPYSIGN with same input types, we can treat it as a
2304 // normal (can trap) binary op.
2305 if (N->getOperand(0).getValueType() == N->getOperand(1).getValueType())
2306 return WidenVecRes_BinaryCanTrap(N);
2308 // If the types are different, fall back to unrolling.
2309 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2310 return DAG.UnrollVectorOp(N, WidenVT.getVectorNumElements());
2313 SDValue DAGTypeLegalizer::WidenVecRes_POWI(SDNode *N) {
2314 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2315 SDValue InOp = GetWidenedVector(N->getOperand(0));
2316 SDValue ShOp = N->getOperand(1);
2317 return DAG.getNode(N->getOpcode(), SDLoc(N), WidenVT, InOp, ShOp);
2320 SDValue DAGTypeLegalizer::WidenVecRes_Shift(SDNode *N) {
2321 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2322 SDValue InOp = GetWidenedVector(N->getOperand(0));
2323 SDValue ShOp = N->getOperand(1);
2325 EVT ShVT = ShOp.getValueType();
2326 if (getTypeAction(ShVT) == TargetLowering::TypeWidenVector) {
2327 ShOp = GetWidenedVector(ShOp);
2328 ShVT = ShOp.getValueType();
2330 EVT ShWidenVT = EVT::getVectorVT(*DAG.getContext(),
2331 ShVT.getVectorElementType(),
2332 WidenVT.getVectorNumElements());
2333 if (ShVT != ShWidenVT)
2334 ShOp = ModifyToType(ShOp, ShWidenVT);
2336 return DAG.getNode(N->getOpcode(), SDLoc(N), WidenVT, InOp, ShOp);
2339 SDValue DAGTypeLegalizer::WidenVecRes_Unary(SDNode *N) {
2340 // Unary op widening.
2341 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2342 SDValue InOp = GetWidenedVector(N->getOperand(0));
2343 return DAG.getNode(N->getOpcode(), SDLoc(N), WidenVT, InOp);
2346 SDValue DAGTypeLegalizer::WidenVecRes_InregOp(SDNode *N) {
2347 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2348 EVT ExtVT = EVT::getVectorVT(*DAG.getContext(),
2349 cast<VTSDNode>(N->getOperand(1))->getVT()
2350 .getVectorElementType(),
2351 WidenVT.getVectorNumElements());
2352 SDValue WidenLHS = GetWidenedVector(N->getOperand(0));
2353 return DAG.getNode(N->getOpcode(), SDLoc(N),
2354 WidenVT, WidenLHS, DAG.getValueType(ExtVT));
2357 SDValue DAGTypeLegalizer::WidenVecRes_MERGE_VALUES(SDNode *N, unsigned ResNo) {
2358 SDValue WidenVec = DisintegrateMERGE_VALUES(N, ResNo);
2359 return GetWidenedVector(WidenVec);
2362 SDValue DAGTypeLegalizer::WidenVecRes_BITCAST(SDNode *N) {
2363 SDValue InOp = N->getOperand(0);
2364 EVT InVT = InOp.getValueType();
2365 EVT VT = N->getValueType(0);
2366 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
2369 switch (getTypeAction(InVT)) {
2370 case TargetLowering::TypeLegal:
2372 case TargetLowering::TypePromoteInteger:
2373 // If the incoming type is a vector that is being promoted, then
2374 // we know that the elements are arranged differently and that we
2375 // must perform the conversion using a stack slot.
2376 if (InVT.isVector())
2379 // If the InOp is promoted to the same size, convert it. Otherwise,
2380 // fall out of the switch and widen the promoted input.
2381 InOp = GetPromotedInteger(InOp);
2382 InVT = InOp.getValueType();
2383 if (WidenVT.bitsEq(InVT))
2384 return DAG.getNode(ISD::BITCAST, dl, WidenVT, InOp);
2386 case TargetLowering::TypeSoftenFloat:
2387 case TargetLowering::TypePromoteFloat:
2388 case TargetLowering::TypeExpandInteger:
2389 case TargetLowering::TypeExpandFloat:
2390 case TargetLowering::TypeScalarizeVector:
2391 case TargetLowering::TypeSplitVector:
2393 case TargetLowering::TypeWidenVector:
2394 // If the InOp is widened to the same size, convert it. Otherwise, fall
2395 // out of the switch and widen the widened input.
2396 InOp = GetWidenedVector(InOp);
2397 InVT = InOp.getValueType();
2398 if (WidenVT.bitsEq(InVT))
2399 // The input widens to the same size. Convert to the widen value.
2400 return DAG.getNode(ISD::BITCAST, dl, WidenVT, InOp);
2404 unsigned WidenSize = WidenVT.getSizeInBits();
2405 unsigned InSize = InVT.getSizeInBits();
2406 // x86mmx is not an acceptable vector element type, so don't try.
2407 if (WidenSize % InSize == 0 && InVT != MVT::x86mmx) {
2408 // Determine new input vector type. The new input vector type will use
2409 // the same element type (if its a vector) or use the input type as a
2410 // vector. It is the same size as the type to widen to.
2412 unsigned NewNumElts = WidenSize / InSize;
2413 if (InVT.isVector()) {
2414 EVT InEltVT = InVT.getVectorElementType();
2415 NewInVT = EVT::getVectorVT(*DAG.getContext(), InEltVT,
2416 WidenSize / InEltVT.getSizeInBits());
2418 NewInVT = EVT::getVectorVT(*DAG.getContext(), InVT, NewNumElts);
2421 if (TLI.isTypeLegal(NewInVT)) {
2422 // Because the result and the input are different vector types, widening
2423 // the result could create a legal type but widening the input might make
2424 // it an illegal type that might lead to repeatedly splitting the input
2425 // and then widening it. To avoid this, we widen the input only if
2426 // it results in a legal type.
2427 SmallVector<SDValue, 16> Ops(NewNumElts);
2428 SDValue UndefVal = DAG.getUNDEF(InVT);
2430 for (unsigned i = 1; i < NewNumElts; ++i)
2434 if (InVT.isVector())
2435 NewVec = DAG.getNode(ISD::CONCAT_VECTORS, dl, NewInVT, Ops);
2437 NewVec = DAG.getNode(ISD::BUILD_VECTOR, dl, NewInVT, Ops);
2438 return DAG.getNode(ISD::BITCAST, dl, WidenVT, NewVec);
2442 return CreateStackStoreLoad(InOp, WidenVT);
2445 SDValue DAGTypeLegalizer::WidenVecRes_BUILD_VECTOR(SDNode *N) {
2447 // Build a vector with undefined for the new nodes.
2448 EVT VT = N->getValueType(0);
2450 // Integer BUILD_VECTOR operands may be larger than the node's vector element
2451 // type. The UNDEFs need to have the same type as the existing operands.
2452 EVT EltVT = N->getOperand(0).getValueType();
2453 unsigned NumElts = VT.getVectorNumElements();
2455 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
2456 unsigned WidenNumElts = WidenVT.getVectorNumElements();
2458 SmallVector<SDValue, 16> NewOps(N->op_begin(), N->op_end());
2459 assert(WidenNumElts >= NumElts && "Shrinking vector instead of widening!");
2460 NewOps.append(WidenNumElts - NumElts, DAG.getUNDEF(EltVT));
2462 return DAG.getNode(ISD::BUILD_VECTOR, dl, WidenVT, NewOps);
2465 SDValue DAGTypeLegalizer::WidenVecRes_CONCAT_VECTORS(SDNode *N) {
2466 EVT InVT = N->getOperand(0).getValueType();
2467 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2469 unsigned WidenNumElts = WidenVT.getVectorNumElements();
2470 unsigned NumInElts = InVT.getVectorNumElements();
2471 unsigned NumOperands = N->getNumOperands();
2473 bool InputWidened = false; // Indicates we need to widen the input.
2474 if (getTypeAction(InVT) != TargetLowering::TypeWidenVector) {
2475 if (WidenVT.getVectorNumElements() % InVT.getVectorNumElements() == 0) {
2476 // Add undef vectors to widen to correct length.
2477 unsigned NumConcat = WidenVT.getVectorNumElements() /
2478 InVT.getVectorNumElements();
2479 SDValue UndefVal = DAG.getUNDEF(InVT);
2480 SmallVector<SDValue, 16> Ops(NumConcat);
2481 for (unsigned i=0; i < NumOperands; ++i)
2482 Ops[i] = N->getOperand(i);
2483 for (unsigned i = NumOperands; i != NumConcat; ++i)
2485 return DAG.getNode(ISD::CONCAT_VECTORS, dl, WidenVT, Ops);
2488 InputWidened = true;
2489 if (WidenVT == TLI.getTypeToTransformTo(*DAG.getContext(), InVT)) {
2490 // The inputs and the result are widen to the same value.
2492 for (i=1; i < NumOperands; ++i)
2493 if (N->getOperand(i).getOpcode() != ISD::UNDEF)
2496 if (i == NumOperands)
2497 // Everything but the first operand is an UNDEF so just return the
2498 // widened first operand.
2499 return GetWidenedVector(N->getOperand(0));
2501 if (NumOperands == 2) {
2502 // Replace concat of two operands with a shuffle.
2503 SmallVector<int, 16> MaskOps(WidenNumElts, -1);
2504 for (unsigned i = 0; i < NumInElts; ++i) {
2506 MaskOps[i + NumInElts] = i + WidenNumElts;
2508 return DAG.getVectorShuffle(WidenVT, dl,
2509 GetWidenedVector(N->getOperand(0)),
2510 GetWidenedVector(N->getOperand(1)),
2516 // Fall back to use extracts and build vector.
2517 EVT EltVT = WidenVT.getVectorElementType();
2518 SmallVector<SDValue, 16> Ops(WidenNumElts);
2520 for (unsigned i=0; i < NumOperands; ++i) {
2521 SDValue InOp = N->getOperand(i);
2523 InOp = GetWidenedVector(InOp);
2524 for (unsigned j=0; j < NumInElts; ++j)
2525 Ops[Idx++] = DAG.getNode(
2526 ISD::EXTRACT_VECTOR_ELT, dl, EltVT, InOp,
2527 DAG.getConstant(j, dl, TLI.getVectorIdxTy(DAG.getDataLayout())));
2529 SDValue UndefVal = DAG.getUNDEF(EltVT);
2530 for (; Idx < WidenNumElts; ++Idx)
2531 Ops[Idx] = UndefVal;
2532 return DAG.getNode(ISD::BUILD_VECTOR, dl, WidenVT, Ops);
2535 SDValue DAGTypeLegalizer::WidenVecRes_CONVERT_RNDSAT(SDNode *N) {
2537 SDValue InOp = N->getOperand(0);
2538 SDValue RndOp = N->getOperand(3);
2539 SDValue SatOp = N->getOperand(4);
2541 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2542 unsigned WidenNumElts = WidenVT.getVectorNumElements();
2544 EVT InVT = InOp.getValueType();
2545 EVT InEltVT = InVT.getVectorElementType();
2546 EVT InWidenVT = EVT::getVectorVT(*DAG.getContext(), InEltVT, WidenNumElts);
2548 SDValue DTyOp = DAG.getValueType(WidenVT);
2549 SDValue STyOp = DAG.getValueType(InWidenVT);
2550 ISD::CvtCode CvtCode = cast<CvtRndSatSDNode>(N)->getCvtCode();
2552 unsigned InVTNumElts = InVT.getVectorNumElements();
2553 if (getTypeAction(InVT) == TargetLowering::TypeWidenVector) {
2554 InOp = GetWidenedVector(InOp);
2555 InVT = InOp.getValueType();
2556 InVTNumElts = InVT.getVectorNumElements();
2557 if (InVTNumElts == WidenNumElts)
2558 return DAG.getConvertRndSat(WidenVT, dl, InOp, DTyOp, STyOp, RndOp,
2562 if (TLI.isTypeLegal(InWidenVT)) {
2563 // Because the result and the input are different vector types, widening
2564 // the result could create a legal type but widening the input might make
2565 // it an illegal type that might lead to repeatedly splitting the input
2566 // and then widening it. To avoid this, we widen the input only if
2567 // it results in a legal type.
2568 if (WidenNumElts % InVTNumElts == 0) {
2569 // Widen the input and call convert on the widened input vector.
2570 unsigned NumConcat = WidenNumElts/InVTNumElts;
2571 SmallVector<SDValue, 16> Ops(NumConcat);
2573 SDValue UndefVal = DAG.getUNDEF(InVT);
2574 for (unsigned i = 1; i != NumConcat; ++i)
2577 InOp = DAG.getNode(ISD::CONCAT_VECTORS, dl, InWidenVT, Ops);
2578 return DAG.getConvertRndSat(WidenVT, dl, InOp, DTyOp, STyOp, RndOp,
2582 if (InVTNumElts % WidenNumElts == 0) {
2583 // Extract the input and convert the shorten input vector.
2585 ISD::EXTRACT_SUBVECTOR, dl, InWidenVT, InOp,
2586 DAG.getConstant(0, dl, TLI.getVectorIdxTy(DAG.getDataLayout())));
2587 return DAG.getConvertRndSat(WidenVT, dl, InOp, DTyOp, STyOp, RndOp,
2592 // Otherwise unroll into some nasty scalar code and rebuild the vector.
2593 SmallVector<SDValue, 16> Ops(WidenNumElts);
2594 EVT EltVT = WidenVT.getVectorElementType();
2595 DTyOp = DAG.getValueType(EltVT);
2596 STyOp = DAG.getValueType(InEltVT);
2598 unsigned MinElts = std::min(InVTNumElts, WidenNumElts);
2600 for (i=0; i < MinElts; ++i) {
2601 SDValue ExtVal = DAG.getNode(
2602 ISD::EXTRACT_VECTOR_ELT, dl, InEltVT, InOp,
2603 DAG.getConstant(i, dl, TLI.getVectorIdxTy(DAG.getDataLayout())));
2604 Ops[i] = DAG.getConvertRndSat(WidenVT, dl, ExtVal, DTyOp, STyOp, RndOp,
2608 SDValue UndefVal = DAG.getUNDEF(EltVT);
2609 for (; i < WidenNumElts; ++i)
2612 return DAG.getNode(ISD::BUILD_VECTOR, dl, WidenVT, Ops);
2615 SDValue DAGTypeLegalizer::WidenVecRes_EXTRACT_SUBVECTOR(SDNode *N) {
2616 EVT VT = N->getValueType(0);
2617 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
2618 unsigned WidenNumElts = WidenVT.getVectorNumElements();
2619 SDValue InOp = N->getOperand(0);
2620 SDValue Idx = N->getOperand(1);
2623 if (getTypeAction(InOp.getValueType()) == TargetLowering::TypeWidenVector)
2624 InOp = GetWidenedVector(InOp);
2626 EVT InVT = InOp.getValueType();
2628 // Check if we can just return the input vector after widening.
2629 uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
2630 if (IdxVal == 0 && InVT == WidenVT)
2633 // Check if we can extract from the vector.
2634 unsigned InNumElts = InVT.getVectorNumElements();
2635 if (IdxVal % WidenNumElts == 0 && IdxVal + WidenNumElts < InNumElts)
2636 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, WidenVT, InOp, Idx);
2638 // We could try widening the input to the right length but for now, extract
2639 // the original elements, fill the rest with undefs and build a vector.
2640 SmallVector<SDValue, 16> Ops(WidenNumElts);
2641 EVT EltVT = VT.getVectorElementType();
2642 unsigned NumElts = VT.getVectorNumElements();
2644 for (i=0; i < NumElts; ++i)
2646 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, InOp,
2647 DAG.getConstant(IdxVal + i, dl,
2648 TLI.getVectorIdxTy(DAG.getDataLayout())));
2650 SDValue UndefVal = DAG.getUNDEF(EltVT);
2651 for (; i < WidenNumElts; ++i)
2653 return DAG.getNode(ISD::BUILD_VECTOR, dl, WidenVT, Ops);
2656 SDValue DAGTypeLegalizer::WidenVecRes_INSERT_VECTOR_ELT(SDNode *N) {
2657 SDValue InOp = GetWidenedVector(N->getOperand(0));
2658 return DAG.getNode(ISD::INSERT_VECTOR_ELT, SDLoc(N),
2659 InOp.getValueType(), InOp,
2660 N->getOperand(1), N->getOperand(2));
2663 SDValue DAGTypeLegalizer::WidenVecRes_LOAD(SDNode *N) {
2664 LoadSDNode *LD = cast<LoadSDNode>(N);
2665 ISD::LoadExtType ExtType = LD->getExtensionType();
2668 SmallVector<SDValue, 16> LdChain; // Chain for the series of load
2669 if (ExtType != ISD::NON_EXTLOAD)
2670 Result = GenWidenVectorExtLoads(LdChain, LD, ExtType);
2672 Result = GenWidenVectorLoads(LdChain, LD);
2674 // If we generate a single load, we can use that for the chain. Otherwise,
2675 // build a factor node to remember the multiple loads are independent and
2678 if (LdChain.size() == 1)
2679 NewChain = LdChain[0];
2681 NewChain = DAG.getNode(ISD::TokenFactor, SDLoc(LD), MVT::Other, LdChain);
2683 // Modified the chain - switch anything that used the old chain to use
2685 ReplaceValueWith(SDValue(N, 1), NewChain);
2690 SDValue DAGTypeLegalizer::WidenVecRes_MLOAD(MaskedLoadSDNode *N) {
2692 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(),N->getValueType(0));
2693 SDValue Mask = N->getMask();
2694 EVT MaskVT = Mask.getValueType();
2695 SDValue Src0 = GetWidenedVector(N->getSrc0());
2696 ISD::LoadExtType ExtType = N->getExtensionType();
2699 if (getTypeAction(MaskVT) == TargetLowering::TypeWidenVector)
2700 Mask = GetWidenedVector(Mask);
2702 EVT BoolVT = getSetCCResultType(WidenVT);
2704 // We can't use ModifyToType() because we should fill the mask with
2706 unsigned WidenNumElts = BoolVT.getVectorNumElements();
2707 unsigned MaskNumElts = MaskVT.getVectorNumElements();
2709 unsigned NumConcat = WidenNumElts / MaskNumElts;
2710 SmallVector<SDValue, 16> Ops(NumConcat);
2711 SDValue ZeroVal = DAG.getConstant(0, dl, MaskVT);
2713 for (unsigned i = 1; i != NumConcat; ++i)
2716 Mask = DAG.getNode(ISD::CONCAT_VECTORS, dl, BoolVT, Ops);
2719 SDValue Res = DAG.getMaskedLoad(WidenVT, dl, N->getChain(), N->getBasePtr(),
2720 Mask, Src0, N->getMemoryVT(),
2721 N->getMemOperand(), ExtType);
2722 // Legalized the chain result - switch anything that used the old chain to
2724 ReplaceValueWith(SDValue(N, 1), Res.getValue(1));
2728 SDValue DAGTypeLegalizer::WidenVecRes_SCALAR_TO_VECTOR(SDNode *N) {
2729 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2730 return DAG.getNode(ISD::SCALAR_TO_VECTOR, SDLoc(N),
2731 WidenVT, N->getOperand(0));
2734 SDValue DAGTypeLegalizer::WidenVecRes_SELECT(SDNode *N) {
2735 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2736 unsigned WidenNumElts = WidenVT.getVectorNumElements();
2738 SDValue Cond1 = N->getOperand(0);
2739 EVT CondVT = Cond1.getValueType();
2740 if (CondVT.isVector()) {
2741 EVT CondEltVT = CondVT.getVectorElementType();
2742 EVT CondWidenVT = EVT::getVectorVT(*DAG.getContext(),
2743 CondEltVT, WidenNumElts);
2744 if (getTypeAction(CondVT) == TargetLowering::TypeWidenVector)
2745 Cond1 = GetWidenedVector(Cond1);
2747 // If we have to split the condition there is no point in widening the
2748 // select. This would result in an cycle of widening the select ->
2749 // widening the condition operand -> splitting the condition operand ->
2750 // splitting the select -> widening the select. Instead split this select
2751 // further and widen the resulting type.
2752 if (getTypeAction(CondVT) == TargetLowering::TypeSplitVector) {
2753 SDValue SplitSelect = SplitVecOp_VSELECT(N, 0);
2754 SDValue Res = ModifyToType(SplitSelect, WidenVT);
2758 if (Cond1.getValueType() != CondWidenVT)
2759 Cond1 = ModifyToType(Cond1, CondWidenVT);
2762 SDValue InOp1 = GetWidenedVector(N->getOperand(1));
2763 SDValue InOp2 = GetWidenedVector(N->getOperand(2));
2764 assert(InOp1.getValueType() == WidenVT && InOp2.getValueType() == WidenVT);
2765 return DAG.getNode(N->getOpcode(), SDLoc(N),
2766 WidenVT, Cond1, InOp1, InOp2);
2769 SDValue DAGTypeLegalizer::WidenVecRes_SELECT_CC(SDNode *N) {
2770 SDValue InOp1 = GetWidenedVector(N->getOperand(2));
2771 SDValue InOp2 = GetWidenedVector(N->getOperand(3));
2772 return DAG.getNode(ISD::SELECT_CC, SDLoc(N),
2773 InOp1.getValueType(), N->getOperand(0),
2774 N->getOperand(1), InOp1, InOp2, N->getOperand(4));
2777 SDValue DAGTypeLegalizer::WidenVecRes_SETCC(SDNode *N) {
2778 assert(N->getValueType(0).isVector() ==
2779 N->getOperand(0).getValueType().isVector() &&
2780 "Scalar/Vector type mismatch");
2781 if (N->getValueType(0).isVector()) return WidenVecRes_VSETCC(N);
2783 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2784 SDValue InOp1 = GetWidenedVector(N->getOperand(0));
2785 SDValue InOp2 = GetWidenedVector(N->getOperand(1));
2786 return DAG.getNode(ISD::SETCC, SDLoc(N), WidenVT,
2787 InOp1, InOp2, N->getOperand(2));
2790 SDValue DAGTypeLegalizer::WidenVecRes_UNDEF(SDNode *N) {
2791 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2792 return DAG.getUNDEF(WidenVT);
2795 SDValue DAGTypeLegalizer::WidenVecRes_VECTOR_SHUFFLE(ShuffleVectorSDNode *N) {
2796 EVT VT = N->getValueType(0);
2799 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
2800 unsigned NumElts = VT.getVectorNumElements();
2801 unsigned WidenNumElts = WidenVT.getVectorNumElements();
2803 SDValue InOp1 = GetWidenedVector(N->getOperand(0));
2804 SDValue InOp2 = GetWidenedVector(N->getOperand(1));
2806 // Adjust mask based on new input vector length.
2807 SmallVector<int, 16> NewMask;
2808 for (unsigned i = 0; i != NumElts; ++i) {
2809 int Idx = N->getMaskElt(i);
2810 if (Idx < (int)NumElts)
2811 NewMask.push_back(Idx);
2813 NewMask.push_back(Idx - NumElts + WidenNumElts);
2815 for (unsigned i = NumElts; i != WidenNumElts; ++i)
2816 NewMask.push_back(-1);
2817 return DAG.getVectorShuffle(WidenVT, dl, InOp1, InOp2, &NewMask[0]);
2820 SDValue DAGTypeLegalizer::WidenVecRes_VSETCC(SDNode *N) {
2821 assert(N->getValueType(0).isVector() &&
2822 N->getOperand(0).getValueType().isVector() &&
2823 "Operands must be vectors");
2824 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2825 unsigned WidenNumElts = WidenVT.getVectorNumElements();
2827 SDValue InOp1 = N->getOperand(0);
2828 EVT InVT = InOp1.getValueType();
2829 assert(InVT.isVector() && "can not widen non-vector type");
2830 EVT WidenInVT = EVT::getVectorVT(*DAG.getContext(),
2831 InVT.getVectorElementType(), WidenNumElts);
2833 // The input and output types often differ here, and it could be that while
2834 // we'd prefer to widen the result type, the input operands have been split.
2835 // In this case, we also need to split the result of this node as well.
2836 if (getTypeAction(InVT) == TargetLowering::TypeSplitVector) {
2837 SDValue SplitVSetCC = SplitVecOp_VSETCC(N);
2838 SDValue Res = ModifyToType(SplitVSetCC, WidenVT);
2842 InOp1 = GetWidenedVector(InOp1);
2843 SDValue InOp2 = GetWidenedVector(N->getOperand(1));
2845 // Assume that the input and output will be widen appropriately. If not,
2846 // we will have to unroll it at some point.
2847 assert(InOp1.getValueType() == WidenInVT &&
2848 InOp2.getValueType() == WidenInVT &&
2849 "Input not widened to expected type!");
2851 return DAG.getNode(ISD::SETCC, SDLoc(N),
2852 WidenVT, InOp1, InOp2, N->getOperand(2));
2856 //===----------------------------------------------------------------------===//
2857 // Widen Vector Operand
2858 //===----------------------------------------------------------------------===//
2859 bool DAGTypeLegalizer::WidenVectorOperand(SDNode *N, unsigned OpNo) {
2860 DEBUG(dbgs() << "Widen node operand " << OpNo << ": ";
2863 SDValue Res = SDValue();
2865 // See if the target wants to custom widen this node.
2866 if (CustomLowerNode(N, N->getOperand(OpNo).getValueType(), false))
2869 switch (N->getOpcode()) {
2872 dbgs() << "WidenVectorOperand op #" << OpNo << ": ";
2876 llvm_unreachable("Do not know how to widen this operator's operand!");
2878 case ISD::BITCAST: Res = WidenVecOp_BITCAST(N); break;
2879 case ISD::CONCAT_VECTORS: Res = WidenVecOp_CONCAT_VECTORS(N); break;
2880 case ISD::EXTRACT_SUBVECTOR: Res = WidenVecOp_EXTRACT_SUBVECTOR(N); break;
2881 case ISD::EXTRACT_VECTOR_ELT: Res = WidenVecOp_EXTRACT_VECTOR_ELT(N); break;
2882 case ISD::STORE: Res = WidenVecOp_STORE(N); break;
2883 case ISD::MSTORE: Res = WidenVecOp_MSTORE(N, OpNo); break;
2884 case ISD::SETCC: Res = WidenVecOp_SETCC(N); break;
2885 case ISD::FCOPYSIGN: Res = WidenVecOp_FCOPYSIGN(N); break;
2887 case ISD::ANY_EXTEND:
2888 case ISD::SIGN_EXTEND:
2889 case ISD::ZERO_EXTEND:
2890 Res = WidenVecOp_EXTEND(N);
2893 case ISD::FP_EXTEND:
2894 case ISD::FP_TO_SINT:
2895 case ISD::FP_TO_UINT:
2896 case ISD::SINT_TO_FP:
2897 case ISD::UINT_TO_FP:
2899 Res = WidenVecOp_Convert(N);
2903 // If Res is null, the sub-method took care of registering the result.
2904 if (!Res.getNode()) return false;
2906 // If the result is N, the sub-method updated N in place. Tell the legalizer
2908 if (Res.getNode() == N)
2912 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 &&
2913 "Invalid operand expansion");
2915 ReplaceValueWith(SDValue(N, 0), Res);
2919 SDValue DAGTypeLegalizer::WidenVecOp_EXTEND(SDNode *N) {
2921 EVT VT = N->getValueType(0);
2923 SDValue InOp = N->getOperand(0);
2924 // If some legalization strategy other than widening is used on the operand,
2925 // we can't safely assume that just extending the low lanes is the correct
2927 if (getTypeAction(InOp.getValueType()) != TargetLowering::TypeWidenVector)
2928 return WidenVecOp_Convert(N);
2929 InOp = GetWidenedVector(InOp);
2930 assert(VT.getVectorNumElements() <
2931 InOp.getValueType().getVectorNumElements() &&
2932 "Input wasn't widened!");
2934 // We may need to further widen the operand until it has the same total
2935 // vector size as the result.
2936 EVT InVT = InOp.getValueType();
2937 if (InVT.getSizeInBits() != VT.getSizeInBits()) {
2938 EVT InEltVT = InVT.getVectorElementType();
2939 for (int i = MVT::FIRST_VECTOR_VALUETYPE, e = MVT::LAST_VECTOR_VALUETYPE; i < e; ++i) {
2940 EVT FixedVT = (MVT::SimpleValueType)i;
2941 EVT FixedEltVT = FixedVT.getVectorElementType();
2942 if (TLI.isTypeLegal(FixedVT) &&
2943 FixedVT.getSizeInBits() == VT.getSizeInBits() &&
2944 FixedEltVT == InEltVT) {
2945 assert(FixedVT.getVectorNumElements() >= VT.getVectorNumElements() &&
2946 "Not enough elements in the fixed type for the operand!");
2947 assert(FixedVT.getVectorNumElements() != InVT.getVectorNumElements() &&
2948 "We can't have the same type as we started with!");
2949 if (FixedVT.getVectorNumElements() > InVT.getVectorNumElements())
2951 ISD::INSERT_SUBVECTOR, DL, FixedVT, DAG.getUNDEF(FixedVT), InOp,
2952 DAG.getConstant(0, DL, TLI.getVectorIdxTy(DAG.getDataLayout())));
2955 ISD::EXTRACT_SUBVECTOR, DL, FixedVT, InOp,
2956 DAG.getConstant(0, DL, TLI.getVectorIdxTy(DAG.getDataLayout())));
2960 InVT = InOp.getValueType();
2961 if (InVT.getSizeInBits() != VT.getSizeInBits())
2962 // We couldn't find a legal vector type that was a widening of the input
2963 // and could be extended in-register to the result type, so we have to
2965 return WidenVecOp_Convert(N);
2968 // Use special DAG nodes to represent the operation of extending the
2970 switch (N->getOpcode()) {
2972 llvm_unreachable("Extend legalization on on extend operation!");
2973 case ISD::ANY_EXTEND:
2974 return DAG.getAnyExtendVectorInReg(InOp, DL, VT);
2975 case ISD::SIGN_EXTEND:
2976 return DAG.getSignExtendVectorInReg(InOp, DL, VT);
2977 case ISD::ZERO_EXTEND:
2978 return DAG.getZeroExtendVectorInReg(InOp, DL, VT);
2982 SDValue DAGTypeLegalizer::WidenVecOp_FCOPYSIGN(SDNode *N) {
2983 // The result (and first input) is legal, but the second input is illegal.
2984 // We can't do much to fix that, so just unroll and let the extracts off of
2985 // the second input be widened as needed later.
2986 return DAG.UnrollVectorOp(N);
2989 SDValue DAGTypeLegalizer::WidenVecOp_Convert(SDNode *N) {
2990 // Since the result is legal and the input is illegal, it is unlikely
2991 // that we can fix the input to a legal type so unroll the convert
2992 // into some scalar code and create a nasty build vector.
2993 EVT VT = N->getValueType(0);
2994 EVT EltVT = VT.getVectorElementType();
2996 unsigned NumElts = VT.getVectorNumElements();
2997 SDValue InOp = N->getOperand(0);
2998 if (getTypeAction(InOp.getValueType()) == TargetLowering::TypeWidenVector)
2999 InOp = GetWidenedVector(InOp);
3000 EVT InVT = InOp.getValueType();
3001 EVT InEltVT = InVT.getVectorElementType();
3003 unsigned Opcode = N->getOpcode();
3004 SmallVector<SDValue, 16> Ops(NumElts);
3005 for (unsigned i=0; i < NumElts; ++i)
3006 Ops[i] = DAG.getNode(
3009 ISD::EXTRACT_VECTOR_ELT, dl, InEltVT, InOp,
3010 DAG.getConstant(i, dl, TLI.getVectorIdxTy(DAG.getDataLayout()))));
3012 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
3015 SDValue DAGTypeLegalizer::WidenVecOp_BITCAST(SDNode *N) {
3016 EVT VT = N->getValueType(0);
3017 SDValue InOp = GetWidenedVector(N->getOperand(0));
3018 EVT InWidenVT = InOp.getValueType();
3021 // Check if we can convert between two legal vector types and extract.
3022 unsigned InWidenSize = InWidenVT.getSizeInBits();
3023 unsigned Size = VT.getSizeInBits();
3024 // x86mmx is not an acceptable vector element type, so don't try.
3025 if (InWidenSize % Size == 0 && !VT.isVector() && VT != MVT::x86mmx) {
3026 unsigned NewNumElts = InWidenSize / Size;
3027 EVT NewVT = EVT::getVectorVT(*DAG.getContext(), VT, NewNumElts);
3028 if (TLI.isTypeLegal(NewVT)) {
3029 SDValue BitOp = DAG.getNode(ISD::BITCAST, dl, NewVT, InOp);
3031 ISD::EXTRACT_VECTOR_ELT, dl, VT, BitOp,
3032 DAG.getConstant(0, dl, TLI.getVectorIdxTy(DAG.getDataLayout())));
3036 return CreateStackStoreLoad(InOp, VT);
3039 SDValue DAGTypeLegalizer::WidenVecOp_CONCAT_VECTORS(SDNode *N) {
3040 // If the input vector is not legal, it is likely that we will not find a
3041 // legal vector of the same size. Replace the concatenate vector with a
3042 // nasty build vector.
3043 EVT VT = N->getValueType(0);
3044 EVT EltVT = VT.getVectorElementType();
3046 unsigned NumElts = VT.getVectorNumElements();
3047 SmallVector<SDValue, 16> Ops(NumElts);
3049 EVT InVT = N->getOperand(0).getValueType();
3050 unsigned NumInElts = InVT.getVectorNumElements();
3053 unsigned NumOperands = N->getNumOperands();
3054 for (unsigned i=0; i < NumOperands; ++i) {
3055 SDValue InOp = N->getOperand(i);
3056 if (getTypeAction(InOp.getValueType()) == TargetLowering::TypeWidenVector)
3057 InOp = GetWidenedVector(InOp);
3058 for (unsigned j=0; j < NumInElts; ++j)
3059 Ops[Idx++] = DAG.getNode(
3060 ISD::EXTRACT_VECTOR_ELT, dl, EltVT, InOp,
3061 DAG.getConstant(j, dl, TLI.getVectorIdxTy(DAG.getDataLayout())));
3063 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
3066 SDValue DAGTypeLegalizer::WidenVecOp_EXTRACT_SUBVECTOR(SDNode *N) {
3067 SDValue InOp = GetWidenedVector(N->getOperand(0));
3068 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, SDLoc(N),
3069 N->getValueType(0), InOp, N->getOperand(1));
3072 SDValue DAGTypeLegalizer::WidenVecOp_EXTRACT_VECTOR_ELT(SDNode *N) {
3073 SDValue InOp = GetWidenedVector(N->getOperand(0));
3074 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SDLoc(N),
3075 N->getValueType(0), InOp, N->getOperand(1));
3078 SDValue DAGTypeLegalizer::WidenVecOp_STORE(SDNode *N) {
3079 // We have to widen the value but we want only to store the original
3081 StoreSDNode *ST = cast<StoreSDNode>(N);
3083 SmallVector<SDValue, 16> StChain;
3084 if (ST->isTruncatingStore())
3085 GenWidenVectorTruncStores(StChain, ST);
3087 GenWidenVectorStores(StChain, ST);
3089 if (StChain.size() == 1)
3092 return DAG.getNode(ISD::TokenFactor, SDLoc(ST), MVT::Other, StChain);
3095 SDValue DAGTypeLegalizer::WidenVecOp_MSTORE(SDNode *N, unsigned OpNo) {
3096 MaskedStoreSDNode *MST = cast<MaskedStoreSDNode>(N);
3097 SDValue Mask = MST->getMask();
3098 EVT MaskVT = Mask.getValueType();
3099 SDValue StVal = MST->getValue();
3101 SDValue WideVal = GetWidenedVector(StVal);
3104 if (OpNo == 2 || getTypeAction(MaskVT) == TargetLowering::TypeWidenVector)
3105 Mask = GetWidenedVector(Mask);
3107 // The mask should be widened as well
3108 EVT BoolVT = getSetCCResultType(WideVal.getValueType());
3109 // We can't use ModifyToType() because we should fill the mask with
3111 unsigned WidenNumElts = BoolVT.getVectorNumElements();
3112 unsigned MaskNumElts = MaskVT.getVectorNumElements();
3114 unsigned NumConcat = WidenNumElts / MaskNumElts;
3115 SmallVector<SDValue, 16> Ops(NumConcat);
3116 SDValue ZeroVal = DAG.getConstant(0, dl, MaskVT);
3118 for (unsigned i = 1; i != NumConcat; ++i)
3121 Mask = DAG.getNode(ISD::CONCAT_VECTORS, dl, BoolVT, Ops);
3123 assert(Mask.getValueType().getVectorNumElements() ==
3124 WideVal.getValueType().getVectorNumElements() &&
3125 "Mask and data vectors should have the same number of elements");
3126 return DAG.getMaskedStore(MST->getChain(), dl, WideVal, MST->getBasePtr(),
3127 Mask, MST->getMemoryVT(), MST->getMemOperand(),
3131 SDValue DAGTypeLegalizer::WidenVecOp_SETCC(SDNode *N) {
3132 SDValue InOp0 = GetWidenedVector(N->getOperand(0));
3133 SDValue InOp1 = GetWidenedVector(N->getOperand(1));
3136 // WARNING: In this code we widen the compare instruction with garbage.
3137 // This garbage may contain denormal floats which may be slow. Is this a real
3138 // concern ? Should we zero the unused lanes if this is a float compare ?
3140 // Get a new SETCC node to compare the newly widened operands.
3141 // Only some of the compared elements are legal.
3142 EVT SVT = TLI.getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(),
3143 InOp0.getValueType());
3144 SDValue WideSETCC = DAG.getNode(ISD::SETCC, SDLoc(N),
3145 SVT, InOp0, InOp1, N->getOperand(2));
3147 // Extract the needed results from the result vector.
3148 EVT ResVT = EVT::getVectorVT(*DAG.getContext(),
3149 SVT.getVectorElementType(),
3150 N->getValueType(0).getVectorNumElements());
3151 SDValue CC = DAG.getNode(
3152 ISD::EXTRACT_SUBVECTOR, dl, ResVT, WideSETCC,
3153 DAG.getConstant(0, dl, TLI.getVectorIdxTy(DAG.getDataLayout())));
3155 return PromoteTargetBoolean(CC, N->getValueType(0));
3159 //===----------------------------------------------------------------------===//
3160 // Vector Widening Utilities
3161 //===----------------------------------------------------------------------===//
3163 // Utility function to find the type to chop up a widen vector for load/store
3164 // TLI: Target lowering used to determine legal types.
3165 // Width: Width left need to load/store.
3166 // WidenVT: The widen vector type to load to/store from
3167 // Align: If 0, don't allow use of a wider type
3168 // WidenEx: If Align is not 0, the amount additional we can load/store from.
3170 static EVT FindMemType(SelectionDAG& DAG, const TargetLowering &TLI,
3171 unsigned Width, EVT WidenVT,
3172 unsigned Align = 0, unsigned WidenEx = 0) {
3173 EVT WidenEltVT = WidenVT.getVectorElementType();
3174 unsigned WidenWidth = WidenVT.getSizeInBits();
3175 unsigned WidenEltWidth = WidenEltVT.getSizeInBits();
3176 unsigned AlignInBits = Align*8;
3178 // If we have one element to load/store, return it.
3179 EVT RetVT = WidenEltVT;
3180 if (Width == WidenEltWidth)
3183 // See if there is larger legal integer than the element type to load/store
3185 for (VT = (unsigned)MVT::LAST_INTEGER_VALUETYPE;
3186 VT >= (unsigned)MVT::FIRST_INTEGER_VALUETYPE; --VT) {
3187 EVT MemVT((MVT::SimpleValueType) VT);
3188 unsigned MemVTWidth = MemVT.getSizeInBits();
3189 if (MemVT.getSizeInBits() <= WidenEltWidth)
3191 auto Action = TLI.getTypeAction(*DAG.getContext(), MemVT);
3192 if ((Action == TargetLowering::TypeLegal ||
3193 Action == TargetLowering::TypePromoteInteger) &&
3194 (WidenWidth % MemVTWidth) == 0 &&
3195 isPowerOf2_32(WidenWidth / MemVTWidth) &&
3196 (MemVTWidth <= Width ||
3197 (Align!=0 && MemVTWidth<=AlignInBits && MemVTWidth<=Width+WidenEx))) {
3203 // See if there is a larger vector type to load/store that has the same vector
3204 // element type and is evenly divisible with the WidenVT.
3205 for (VT = (unsigned)MVT::LAST_VECTOR_VALUETYPE;
3206 VT >= (unsigned)MVT::FIRST_VECTOR_VALUETYPE; --VT) {
3207 EVT MemVT = (MVT::SimpleValueType) VT;
3208 unsigned MemVTWidth = MemVT.getSizeInBits();
3209 if (TLI.isTypeLegal(MemVT) && WidenEltVT == MemVT.getVectorElementType() &&
3210 (WidenWidth % MemVTWidth) == 0 &&
3211 isPowerOf2_32(WidenWidth / MemVTWidth) &&
3212 (MemVTWidth <= Width ||
3213 (Align!=0 && MemVTWidth<=AlignInBits && MemVTWidth<=Width+WidenEx))) {
3214 if (RetVT.getSizeInBits() < MemVTWidth || MemVT == WidenVT)
3222 // Builds a vector type from scalar loads
3223 // VecTy: Resulting Vector type
3224 // LDOps: Load operators to build a vector type
3225 // [Start,End) the list of loads to use.
3226 static SDValue BuildVectorFromScalar(SelectionDAG& DAG, EVT VecTy,
3227 SmallVectorImpl<SDValue> &LdOps,
3228 unsigned Start, unsigned End) {
3229 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3230 SDLoc dl(LdOps[Start]);
3231 EVT LdTy = LdOps[Start].getValueType();
3232 unsigned Width = VecTy.getSizeInBits();
3233 unsigned NumElts = Width / LdTy.getSizeInBits();
3234 EVT NewVecVT = EVT::getVectorVT(*DAG.getContext(), LdTy, NumElts);
3237 SDValue VecOp = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, NewVecVT,LdOps[Start]);
3239 for (unsigned i = Start + 1; i != End; ++i) {
3240 EVT NewLdTy = LdOps[i].getValueType();
3241 if (NewLdTy != LdTy) {
3242 NumElts = Width / NewLdTy.getSizeInBits();
3243 NewVecVT = EVT::getVectorVT(*DAG.getContext(), NewLdTy, NumElts);
3244 VecOp = DAG.getNode(ISD::BITCAST, dl, NewVecVT, VecOp);
3245 // Readjust position and vector position based on new load type
3246 Idx = Idx * LdTy.getSizeInBits() / NewLdTy.getSizeInBits();
3249 VecOp = DAG.getNode(
3250 ISD::INSERT_VECTOR_ELT, dl, NewVecVT, VecOp, LdOps[i],
3251 DAG.getConstant(Idx++, dl, TLI.getVectorIdxTy(DAG.getDataLayout())));
3253 return DAG.getNode(ISD::BITCAST, dl, VecTy, VecOp);
3256 SDValue DAGTypeLegalizer::GenWidenVectorLoads(SmallVectorImpl<SDValue> &LdChain,
3258 // The strategy assumes that we can efficiently load powers of two widths.
3259 // The routines chops the vector into the largest vector loads with the same
3260 // element type or scalar loads and then recombines it to the widen vector
3262 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(),LD->getValueType(0));
3263 unsigned WidenWidth = WidenVT.getSizeInBits();
3264 EVT LdVT = LD->getMemoryVT();
3266 assert(LdVT.isVector() && WidenVT.isVector());
3267 assert(LdVT.getVectorElementType() == WidenVT.getVectorElementType());
3270 SDValue Chain = LD->getChain();
3271 SDValue BasePtr = LD->getBasePtr();
3272 unsigned Align = LD->getAlignment();
3273 bool isVolatile = LD->isVolatile();
3274 bool isNonTemporal = LD->isNonTemporal();
3275 bool isInvariant = LD->isInvariant();
3276 AAMDNodes AAInfo = LD->getAAInfo();
3278 int LdWidth = LdVT.getSizeInBits();
3279 int WidthDiff = WidenWidth - LdWidth; // Difference
3280 unsigned LdAlign = (isVolatile) ? 0 : Align; // Allow wider loads
3282 // Find the vector type that can load from.
3283 EVT NewVT = FindMemType(DAG, TLI, LdWidth, WidenVT, LdAlign, WidthDiff);
3284 int NewVTWidth = NewVT.getSizeInBits();
3285 SDValue LdOp = DAG.getLoad(NewVT, dl, Chain, BasePtr, LD->getPointerInfo(),
3286 isVolatile, isNonTemporal, isInvariant, Align,
3288 LdChain.push_back(LdOp.getValue(1));
3290 // Check if we can load the element with one instruction
3291 if (LdWidth <= NewVTWidth) {
3292 if (!NewVT.isVector()) {
3293 unsigned NumElts = WidenWidth / NewVTWidth;
3294 EVT NewVecVT = EVT::getVectorVT(*DAG.getContext(), NewVT, NumElts);
3295 SDValue VecOp = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, NewVecVT, LdOp);
3296 return DAG.getNode(ISD::BITCAST, dl, WidenVT, VecOp);
3298 if (NewVT == WidenVT)
3301 assert(WidenWidth % NewVTWidth == 0);
3302 unsigned NumConcat = WidenWidth / NewVTWidth;
3303 SmallVector<SDValue, 16> ConcatOps(NumConcat);
3304 SDValue UndefVal = DAG.getUNDEF(NewVT);
3305 ConcatOps[0] = LdOp;
3306 for (unsigned i = 1; i != NumConcat; ++i)
3307 ConcatOps[i] = UndefVal;
3308 return DAG.getNode(ISD::CONCAT_VECTORS, dl, WidenVT, ConcatOps);
3311 // Load vector by using multiple loads from largest vector to scalar
3312 SmallVector<SDValue, 16> LdOps;
3313 LdOps.push_back(LdOp);
3315 LdWidth -= NewVTWidth;
3316 unsigned Offset = 0;
3318 while (LdWidth > 0) {
3319 unsigned Increment = NewVTWidth / 8;
3320 Offset += Increment;
3321 BasePtr = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(), BasePtr,
3322 DAG.getConstant(Increment, dl, BasePtr.getValueType()));
3325 if (LdWidth < NewVTWidth) {
3326 // Our current type we are using is too large, find a better size
3327 NewVT = FindMemType(DAG, TLI, LdWidth, WidenVT, LdAlign, WidthDiff);
3328 NewVTWidth = NewVT.getSizeInBits();
3329 L = DAG.getLoad(NewVT, dl, Chain, BasePtr,
3330 LD->getPointerInfo().getWithOffset(Offset), isVolatile,
3331 isNonTemporal, isInvariant, MinAlign(Align, Increment),
3333 LdChain.push_back(L.getValue(1));
3334 if (L->getValueType(0).isVector()) {
3335 SmallVector<SDValue, 16> Loads;
3337 unsigned size = L->getValueSizeInBits(0);
3338 while (size < LdOp->getValueSizeInBits(0)) {
3339 Loads.push_back(DAG.getUNDEF(L->getValueType(0)));
3340 size += L->getValueSizeInBits(0);
3342 L = DAG.getNode(ISD::CONCAT_VECTORS, dl, LdOp->getValueType(0), Loads);
3345 L = DAG.getLoad(NewVT, dl, Chain, BasePtr,
3346 LD->getPointerInfo().getWithOffset(Offset), isVolatile,
3347 isNonTemporal, isInvariant, MinAlign(Align, Increment),
3349 LdChain.push_back(L.getValue(1));
3355 LdWidth -= NewVTWidth;
3358 // Build the vector from the loads operations
3359 unsigned End = LdOps.size();
3360 if (!LdOps[0].getValueType().isVector())
3361 // All the loads are scalar loads.
3362 return BuildVectorFromScalar(DAG, WidenVT, LdOps, 0, End);
3364 // If the load contains vectors, build the vector using concat vector.
3365 // All of the vectors used to loads are power of 2 and the scalars load
3366 // can be combined to make a power of 2 vector.
3367 SmallVector<SDValue, 16> ConcatOps(End);
3370 EVT LdTy = LdOps[i].getValueType();
3371 // First combine the scalar loads to a vector
3372 if (!LdTy.isVector()) {
3373 for (--i; i >= 0; --i) {
3374 LdTy = LdOps[i].getValueType();
3375 if (LdTy.isVector())
3378 ConcatOps[--Idx] = BuildVectorFromScalar(DAG, LdTy, LdOps, i+1, End);
3380 ConcatOps[--Idx] = LdOps[i];
3381 for (--i; i >= 0; --i) {
3382 EVT NewLdTy = LdOps[i].getValueType();
3383 if (NewLdTy != LdTy) {
3384 // Create a larger vector
3385 ConcatOps[End-1] = DAG.getNode(ISD::CONCAT_VECTORS, dl, NewLdTy,
3386 makeArrayRef(&ConcatOps[Idx], End - Idx));
3390 ConcatOps[--Idx] = LdOps[i];
3393 if (WidenWidth == LdTy.getSizeInBits()*(End - Idx))
3394 return DAG.getNode(ISD::CONCAT_VECTORS, dl, WidenVT,
3395 makeArrayRef(&ConcatOps[Idx], End - Idx));
3397 // We need to fill the rest with undefs to build the vector
3398 unsigned NumOps = WidenWidth / LdTy.getSizeInBits();
3399 SmallVector<SDValue, 16> WidenOps(NumOps);
3400 SDValue UndefVal = DAG.getUNDEF(LdTy);
3403 for (; i != End-Idx; ++i)
3404 WidenOps[i] = ConcatOps[Idx+i];
3405 for (; i != NumOps; ++i)
3406 WidenOps[i] = UndefVal;
3408 return DAG.getNode(ISD::CONCAT_VECTORS, dl, WidenVT, WidenOps);
3412 DAGTypeLegalizer::GenWidenVectorExtLoads(SmallVectorImpl<SDValue> &LdChain,
3414 ISD::LoadExtType ExtType) {
3415 // For extension loads, it may not be more efficient to chop up the vector
3416 // and then extended it. Instead, we unroll the load and build a new vector.
3417 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(),LD->getValueType(0));
3418 EVT LdVT = LD->getMemoryVT();
3420 assert(LdVT.isVector() && WidenVT.isVector());
3423 SDValue Chain = LD->getChain();
3424 SDValue BasePtr = LD->getBasePtr();
3425 unsigned Align = LD->getAlignment();
3426 bool isVolatile = LD->isVolatile();
3427 bool isNonTemporal = LD->isNonTemporal();
3428 bool isInvariant = LD->isInvariant();
3429 AAMDNodes AAInfo = LD->getAAInfo();
3431 EVT EltVT = WidenVT.getVectorElementType();
3432 EVT LdEltVT = LdVT.getVectorElementType();
3433 unsigned NumElts = LdVT.getVectorNumElements();
3435 // Load each element and widen
3436 unsigned WidenNumElts = WidenVT.getVectorNumElements();
3437 SmallVector<SDValue, 16> Ops(WidenNumElts);
3438 unsigned Increment = LdEltVT.getSizeInBits() / 8;
3439 Ops[0] = DAG.getExtLoad(ExtType, dl, EltVT, Chain, BasePtr,
3440 LD->getPointerInfo(),
3441 LdEltVT, isVolatile, isNonTemporal, isInvariant,
3443 LdChain.push_back(Ops[0].getValue(1));
3444 unsigned i = 0, Offset = Increment;
3445 for (i=1; i < NumElts; ++i, Offset += Increment) {
3446 SDValue NewBasePtr = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(),
3448 DAG.getConstant(Offset, dl,
3449 BasePtr.getValueType()));
3450 Ops[i] = DAG.getExtLoad(ExtType, dl, EltVT, Chain, NewBasePtr,
3451 LD->getPointerInfo().getWithOffset(Offset), LdEltVT,
3452 isVolatile, isNonTemporal, isInvariant, Align,
3454 LdChain.push_back(Ops[i].getValue(1));
3457 // Fill the rest with undefs
3458 SDValue UndefVal = DAG.getUNDEF(EltVT);
3459 for (; i != WidenNumElts; ++i)
3462 return DAG.getNode(ISD::BUILD_VECTOR, dl, WidenVT, Ops);
3466 void DAGTypeLegalizer::GenWidenVectorStores(SmallVectorImpl<SDValue> &StChain,
3468 // The strategy assumes that we can efficiently store powers of two widths.
3469 // The routines chops the vector into the largest vector stores with the same
3470 // element type or scalar stores.
3471 SDValue Chain = ST->getChain();
3472 SDValue BasePtr = ST->getBasePtr();
3473 unsigned Align = ST->getAlignment();
3474 bool isVolatile = ST->isVolatile();
3475 bool isNonTemporal = ST->isNonTemporal();
3476 AAMDNodes AAInfo = ST->getAAInfo();
3477 SDValue ValOp = GetWidenedVector(ST->getValue());
3480 EVT StVT = ST->getMemoryVT();
3481 unsigned StWidth = StVT.getSizeInBits();
3482 EVT ValVT = ValOp.getValueType();
3483 unsigned ValWidth = ValVT.getSizeInBits();
3484 EVT ValEltVT = ValVT.getVectorElementType();
3485 unsigned ValEltWidth = ValEltVT.getSizeInBits();
3486 assert(StVT.getVectorElementType() == ValEltVT);
3488 int Idx = 0; // current index to store
3489 unsigned Offset = 0; // offset from base to store
3490 while (StWidth != 0) {
3491 // Find the largest vector type we can store with
3492 EVT NewVT = FindMemType(DAG, TLI, StWidth, ValVT);
3493 unsigned NewVTWidth = NewVT.getSizeInBits();
3494 unsigned Increment = NewVTWidth / 8;
3495 if (NewVT.isVector()) {
3496 unsigned NumVTElts = NewVT.getVectorNumElements();
3498 SDValue EOp = DAG.getNode(
3499 ISD::EXTRACT_SUBVECTOR, dl, NewVT, ValOp,
3500 DAG.getConstant(Idx, dl, TLI.getVectorIdxTy(DAG.getDataLayout())));
3501 StChain.push_back(DAG.getStore(Chain, dl, EOp, BasePtr,
3502 ST->getPointerInfo().getWithOffset(Offset),
3503 isVolatile, isNonTemporal,
3504 MinAlign(Align, Offset), AAInfo));
3505 StWidth -= NewVTWidth;
3506 Offset += Increment;
3508 BasePtr = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(), BasePtr,
3509 DAG.getConstant(Increment, dl,
3510 BasePtr.getValueType()));
3511 } while (StWidth != 0 && StWidth >= NewVTWidth);
3513 // Cast the vector to the scalar type we can store
3514 unsigned NumElts = ValWidth / NewVTWidth;
3515 EVT NewVecVT = EVT::getVectorVT(*DAG.getContext(), NewVT, NumElts);
3516 SDValue VecOp = DAG.getNode(ISD::BITCAST, dl, NewVecVT, ValOp);
3517 // Readjust index position based on new vector type
3518 Idx = Idx * ValEltWidth / NewVTWidth;
3520 SDValue EOp = DAG.getNode(
3521 ISD::EXTRACT_VECTOR_ELT, dl, NewVT, VecOp,
3522 DAG.getConstant(Idx++, dl,
3523 TLI.getVectorIdxTy(DAG.getDataLayout())));
3524 StChain.push_back(DAG.getStore(Chain, dl, EOp, BasePtr,
3525 ST->getPointerInfo().getWithOffset(Offset),
3526 isVolatile, isNonTemporal,
3527 MinAlign(Align, Offset), AAInfo));
3528 StWidth -= NewVTWidth;
3529 Offset += Increment;
3530 BasePtr = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(), BasePtr,
3531 DAG.getConstant(Increment, dl,
3532 BasePtr.getValueType()));
3533 } while (StWidth != 0 && StWidth >= NewVTWidth);
3534 // Restore index back to be relative to the original widen element type
3535 Idx = Idx * NewVTWidth / ValEltWidth;
3541 DAGTypeLegalizer::GenWidenVectorTruncStores(SmallVectorImpl<SDValue> &StChain,
3543 // For extension loads, it may not be more efficient to truncate the vector
3544 // and then store it. Instead, we extract each element and then store it.
3545 SDValue Chain = ST->getChain();
3546 SDValue BasePtr = ST->getBasePtr();
3547 unsigned Align = ST->getAlignment();
3548 bool isVolatile = ST->isVolatile();
3549 bool isNonTemporal = ST->isNonTemporal();
3550 AAMDNodes AAInfo = ST->getAAInfo();
3551 SDValue ValOp = GetWidenedVector(ST->getValue());
3554 EVT StVT = ST->getMemoryVT();
3555 EVT ValVT = ValOp.getValueType();
3557 // It must be true that we the widen vector type is bigger than where
3558 // we need to store.
3559 assert(StVT.isVector() && ValOp.getValueType().isVector());
3560 assert(StVT.bitsLT(ValOp.getValueType()));
3562 // For truncating stores, we can not play the tricks of chopping legal
3563 // vector types and bit cast it to the right type. Instead, we unroll
3565 EVT StEltVT = StVT.getVectorElementType();
3566 EVT ValEltVT = ValVT.getVectorElementType();
3567 unsigned Increment = ValEltVT.getSizeInBits() / 8;
3568 unsigned NumElts = StVT.getVectorNumElements();
3569 SDValue EOp = DAG.getNode(
3570 ISD::EXTRACT_VECTOR_ELT, dl, ValEltVT, ValOp,
3571 DAG.getConstant(0, dl, TLI.getVectorIdxTy(DAG.getDataLayout())));
3572 StChain.push_back(DAG.getTruncStore(Chain, dl, EOp, BasePtr,
3573 ST->getPointerInfo(), StEltVT,
3574 isVolatile, isNonTemporal, Align,
3576 unsigned Offset = Increment;
3577 for (unsigned i=1; i < NumElts; ++i, Offset += Increment) {
3578 SDValue NewBasePtr = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(),
3580 DAG.getConstant(Offset, dl,
3581 BasePtr.getValueType()));
3582 SDValue EOp = DAG.getNode(
3583 ISD::EXTRACT_VECTOR_ELT, dl, ValEltVT, ValOp,
3584 DAG.getConstant(0, dl, TLI.getVectorIdxTy(DAG.getDataLayout())));
3585 StChain.push_back(DAG.getTruncStore(Chain, dl, EOp, NewBasePtr,
3586 ST->getPointerInfo().getWithOffset(Offset),
3587 StEltVT, isVolatile, isNonTemporal,
3588 MinAlign(Align, Offset), AAInfo));
3592 /// Modifies a vector input (widen or narrows) to a vector of NVT. The
3593 /// input vector must have the same element type as NVT.
3594 SDValue DAGTypeLegalizer::ModifyToType(SDValue InOp, EVT NVT) {
3595 // Note that InOp might have been widened so it might already have
3596 // the right width or it might need be narrowed.
3597 EVT InVT = InOp.getValueType();
3598 assert(InVT.getVectorElementType() == NVT.getVectorElementType() &&
3599 "input and widen element type must match");
3602 // Check if InOp already has the right width.
3606 unsigned InNumElts = InVT.getVectorNumElements();
3607 unsigned WidenNumElts = NVT.getVectorNumElements();
3608 if (WidenNumElts > InNumElts && WidenNumElts % InNumElts == 0) {
3609 unsigned NumConcat = WidenNumElts / InNumElts;
3610 SmallVector<SDValue, 16> Ops(NumConcat);
3611 SDValue UndefVal = DAG.getUNDEF(InVT);
3613 for (unsigned i = 1; i != NumConcat; ++i)
3616 return DAG.getNode(ISD::CONCAT_VECTORS, dl, NVT, Ops);
3619 if (WidenNumElts < InNumElts && InNumElts % WidenNumElts)
3621 ISD::EXTRACT_SUBVECTOR, dl, NVT, InOp,
3622 DAG.getConstant(0, dl, TLI.getVectorIdxTy(DAG.getDataLayout())));
3624 // Fall back to extract and build.
3625 SmallVector<SDValue, 16> Ops(WidenNumElts);
3626 EVT EltVT = NVT.getVectorElementType();
3627 unsigned MinNumElts = std::min(WidenNumElts, InNumElts);
3629 for (Idx = 0; Idx < MinNumElts; ++Idx)
3630 Ops[Idx] = DAG.getNode(
3631 ISD::EXTRACT_VECTOR_ELT, dl, EltVT, InOp,
3632 DAG.getConstant(Idx, dl, TLI.getVectorIdxTy(DAG.getDataLayout())));
3634 SDValue UndefVal = DAG.getUNDEF(EltVT);
3635 for ( ; Idx < WidenNumElts; ++Idx)
3636 Ops[Idx] = UndefVal;
3637 return DAG.getNode(ISD::BUILD_VECTOR, dl, NVT, Ops);