1 //===------- LegalizeVectorTypes.cpp - Legalization of vector types -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file performs vector type splitting and scalarization for LegalizeTypes.
11 // Scalarization is the act of changing a computation in an illegal one-element
12 // vector type to be a computation in its scalar element type. For example,
13 // implementing <1 x f32> arithmetic in a scalar f32 register. This is needed
14 // as a base case when scalarizing vector arithmetic like <4 x f32>, which
15 // eventually decomposes to scalars if the target doesn't support v4f32 or v2f32
17 // Splitting is the act of changing a computation in an invalid vector type to
18 // be a computation in two vectors of half the size. For example, implementing
19 // <128 x f32> operations in terms of two <64 x f32> operations.
21 //===----------------------------------------------------------------------===//
23 #include "LegalizeTypes.h"
24 #include "llvm/CodeGen/PseudoSourceValue.h"
25 #include "llvm/Target/TargetData.h"
26 #include "llvm/Support/ErrorHandling.h"
29 //===----------------------------------------------------------------------===//
30 // Result Vector Scalarization: <1 x ty> -> ty.
31 //===----------------------------------------------------------------------===//
33 void DAGTypeLegalizer::ScalarizeVectorResult(SDNode *N, unsigned ResNo) {
34 DEBUG(cerr << "Scalarize node result " << ResNo << ": "; N->dump(&DAG);
36 SDValue R = SDValue();
38 switch (N->getOpcode()) {
41 cerr << "ScalarizeVectorResult #" << ResNo << ": ";
42 N->dump(&DAG); cerr << "\n";
44 LLVM_UNREACHABLE("Do not know how to scalarize the result of this operator!");
46 case ISD::BIT_CONVERT: R = ScalarizeVecRes_BIT_CONVERT(N); break;
47 case ISD::BUILD_VECTOR: R = N->getOperand(0); break;
48 case ISD::CONVERT_RNDSAT: R = ScalarizeVecRes_CONVERT_RNDSAT(N); break;
49 case ISD::EXTRACT_SUBVECTOR: R = ScalarizeVecRes_EXTRACT_SUBVECTOR(N); break;
50 case ISD::FPOWI: R = ScalarizeVecRes_FPOWI(N); break;
51 case ISD::INSERT_VECTOR_ELT: R = ScalarizeVecRes_INSERT_VECTOR_ELT(N); break;
52 case ISD::LOAD: R = ScalarizeVecRes_LOAD(cast<LoadSDNode>(N));break;
53 case ISD::SCALAR_TO_VECTOR: R = ScalarizeVecRes_SCALAR_TO_VECTOR(N); break;
54 case ISD::SELECT: R = ScalarizeVecRes_SELECT(N); break;
55 case ISD::SELECT_CC: R = ScalarizeVecRes_SELECT_CC(N); break;
56 case ISD::SETCC: R = ScalarizeVecRes_SETCC(N); break;
57 case ISD::UNDEF: R = ScalarizeVecRes_UNDEF(N); break;
58 case ISD::VECTOR_SHUFFLE: R = ScalarizeVecRes_VECTOR_SHUFFLE(N); break;
59 case ISD::VSETCC: R = ScalarizeVecRes_VSETCC(N); break;
79 case ISD::SIGN_EXTEND:
80 case ISD::ZERO_EXTEND:
82 R = ScalarizeVecRes_UnaryOp(N);
104 R = ScalarizeVecRes_BinOp(N);
108 // If R is null, the sub-method took care of registering the result.
110 SetScalarizedVector(SDValue(N, ResNo), R);
113 SDValue DAGTypeLegalizer::ScalarizeVecRes_BinOp(SDNode *N) {
114 SDValue LHS = GetScalarizedVector(N->getOperand(0));
115 SDValue RHS = GetScalarizedVector(N->getOperand(1));
116 return DAG.getNode(N->getOpcode(), N->getDebugLoc(),
117 LHS.getValueType(), LHS, RHS);
120 SDValue DAGTypeLegalizer::ScalarizeVecRes_BIT_CONVERT(SDNode *N) {
121 MVT NewVT = N->getValueType(0).getVectorElementType();
122 return DAG.getNode(ISD::BIT_CONVERT, N->getDebugLoc(),
123 NewVT, N->getOperand(0));
126 SDValue DAGTypeLegalizer::ScalarizeVecRes_CONVERT_RNDSAT(SDNode *N) {
127 MVT NewVT = N->getValueType(0).getVectorElementType();
128 SDValue Op0 = GetScalarizedVector(N->getOperand(0));
129 return DAG.getConvertRndSat(NewVT, N->getDebugLoc(),
130 Op0, DAG.getValueType(NewVT),
131 DAG.getValueType(Op0.getValueType()),
134 cast<CvtRndSatSDNode>(N)->getCvtCode());
137 SDValue DAGTypeLegalizer::ScalarizeVecRes_EXTRACT_SUBVECTOR(SDNode *N) {
138 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, N->getDebugLoc(),
139 N->getValueType(0).getVectorElementType(),
140 N->getOperand(0), N->getOperand(1));
143 SDValue DAGTypeLegalizer::ScalarizeVecRes_FPOWI(SDNode *N) {
144 SDValue Op = GetScalarizedVector(N->getOperand(0));
145 return DAG.getNode(ISD::FPOWI, N->getDebugLoc(),
146 Op.getValueType(), Op, N->getOperand(1));
149 SDValue DAGTypeLegalizer::ScalarizeVecRes_INSERT_VECTOR_ELT(SDNode *N) {
150 // The value to insert may have a wider type than the vector element type,
151 // so be sure to truncate it to the element type if necessary.
152 SDValue Op = N->getOperand(1);
153 MVT EltVT = N->getValueType(0).getVectorElementType();
154 if (Op.getValueType() != EltVT)
155 // FIXME: Can this happen for floating point types?
156 Op = DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), EltVT, Op);
160 SDValue DAGTypeLegalizer::ScalarizeVecRes_LOAD(LoadSDNode *N) {
161 assert(N->isUnindexed() && "Indexed vector load?");
163 SDValue Result = DAG.getLoad(ISD::UNINDEXED, N->getDebugLoc(),
164 N->getExtensionType(),
165 N->getValueType(0).getVectorElementType(),
166 N->getChain(), N->getBasePtr(),
167 DAG.getUNDEF(N->getBasePtr().getValueType()),
168 N->getSrcValue(), N->getSrcValueOffset(),
169 N->getMemoryVT().getVectorElementType(),
170 N->isVolatile(), N->getAlignment());
172 // Legalized the chain result - switch anything that used the old chain to
174 ReplaceValueWith(SDValue(N, 1), Result.getValue(1));
178 SDValue DAGTypeLegalizer::ScalarizeVecRes_UnaryOp(SDNode *N) {
179 // Get the dest type - it doesn't always match the input type, e.g. int_to_fp.
180 MVT DestVT = N->getValueType(0).getVectorElementType();
181 SDValue Op = GetScalarizedVector(N->getOperand(0));
182 return DAG.getNode(N->getOpcode(), N->getDebugLoc(), DestVT, Op);
185 SDValue DAGTypeLegalizer::ScalarizeVecRes_SCALAR_TO_VECTOR(SDNode *N) {
186 // If the operand is wider than the vector element type then it is implicitly
187 // truncated. Make that explicit here.
188 MVT EltVT = N->getValueType(0).getVectorElementType();
189 SDValue InOp = N->getOperand(0);
190 if (InOp.getValueType() != EltVT)
191 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), EltVT, InOp);
195 SDValue DAGTypeLegalizer::ScalarizeVecRes_SELECT(SDNode *N) {
196 SDValue LHS = GetScalarizedVector(N->getOperand(1));
197 return DAG.getNode(ISD::SELECT, N->getDebugLoc(),
198 LHS.getValueType(), N->getOperand(0), LHS,
199 GetScalarizedVector(N->getOperand(2)));
202 SDValue DAGTypeLegalizer::ScalarizeVecRes_SELECT_CC(SDNode *N) {
203 SDValue LHS = GetScalarizedVector(N->getOperand(2));
204 return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(), LHS.getValueType(),
205 N->getOperand(0), N->getOperand(1),
206 LHS, GetScalarizedVector(N->getOperand(3)),
210 SDValue DAGTypeLegalizer::ScalarizeVecRes_SETCC(SDNode *N) {
211 SDValue LHS = GetScalarizedVector(N->getOperand(0));
212 SDValue RHS = GetScalarizedVector(N->getOperand(1));
213 DebugLoc DL = N->getDebugLoc();
215 // Turn it into a scalar SETCC.
216 return DAG.getNode(ISD::SETCC, DL, MVT::i1, LHS, RHS, N->getOperand(2));
219 SDValue DAGTypeLegalizer::ScalarizeVecRes_UNDEF(SDNode *N) {
220 return DAG.getUNDEF(N->getValueType(0).getVectorElementType());
223 SDValue DAGTypeLegalizer::ScalarizeVecRes_VECTOR_SHUFFLE(SDNode *N) {
224 // Figure out if the scalar is the LHS or RHS and return it.
225 SDValue Arg = N->getOperand(2).getOperand(0);
226 if (Arg.getOpcode() == ISD::UNDEF)
227 return DAG.getUNDEF(N->getValueType(0).getVectorElementType());
228 unsigned Op = !cast<ConstantSDNode>(Arg)->isNullValue();
229 return GetScalarizedVector(N->getOperand(Op));
232 SDValue DAGTypeLegalizer::ScalarizeVecRes_VSETCC(SDNode *N) {
233 SDValue LHS = GetScalarizedVector(N->getOperand(0));
234 SDValue RHS = GetScalarizedVector(N->getOperand(1));
235 MVT NVT = N->getValueType(0).getVectorElementType();
236 MVT SVT = TLI.getSetCCResultType(LHS.getValueType());
237 DebugLoc DL = N->getDebugLoc();
239 // Turn it into a scalar SETCC.
240 SDValue Res = DAG.getNode(ISD::SETCC, DL, SVT, LHS, RHS, N->getOperand(2));
242 // VSETCC always returns a sign-extended value, while SETCC may not. The
243 // SETCC result type may not match the vector element type. Correct these.
244 if (NVT.bitsLE(SVT)) {
245 // The SETCC result type is bigger than the vector element type.
246 // Ensure the SETCC result is sign-extended.
247 if (TLI.getBooleanContents() !=
248 TargetLowering::ZeroOrNegativeOneBooleanContent)
249 Res = DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, SVT, Res,
250 DAG.getValueType(MVT::i1));
251 // Truncate to the final type.
252 return DAG.getNode(ISD::TRUNCATE, DL, NVT, Res);
255 // The SETCC result type is smaller than the vector element type.
256 // If the SetCC result is not sign-extended, chop it down to MVT::i1.
257 if (TLI.getBooleanContents() !=
258 TargetLowering::ZeroOrNegativeOneBooleanContent)
259 Res = DAG.getNode(ISD::TRUNCATE, DL, MVT::i1, Res);
260 // Sign extend to the final type.
261 return DAG.getNode(ISD::SIGN_EXTEND, DL, NVT, Res);
265 //===----------------------------------------------------------------------===//
266 // Operand Vector Scalarization <1 x ty> -> ty.
267 //===----------------------------------------------------------------------===//
269 bool DAGTypeLegalizer::ScalarizeVectorOperand(SDNode *N, unsigned OpNo) {
270 DEBUG(cerr << "Scalarize node operand " << OpNo << ": "; N->dump(&DAG);
272 SDValue Res = SDValue();
274 if (Res.getNode() == 0) {
275 switch (N->getOpcode()) {
278 cerr << "ScalarizeVectorOperand Op #" << OpNo << ": ";
279 N->dump(&DAG); cerr << "\n";
281 assert(0 && "Do not know how to scalarize this operator's operand!");
282 case ISD::BIT_CONVERT:
283 Res = ScalarizeVecOp_BIT_CONVERT(N);
285 case ISD::CONCAT_VECTORS:
286 Res = ScalarizeVecOp_CONCAT_VECTORS(N);
288 case ISD::EXTRACT_VECTOR_ELT:
289 Res = ScalarizeVecOp_EXTRACT_VECTOR_ELT(N);
292 Res = ScalarizeVecOp_STORE(cast<StoreSDNode>(N), OpNo);
297 // If the result is null, the sub-method took care of registering results etc.
298 if (!Res.getNode()) return false;
300 // If the result is N, the sub-method updated N in place. Tell the legalizer
302 if (Res.getNode() == N)
305 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 &&
306 "Invalid operand expansion");
308 ReplaceValueWith(SDValue(N, 0), Res);
312 /// ScalarizeVecOp_BIT_CONVERT - If the value to convert is a vector that needs
313 /// to be scalarized, it must be <1 x ty>. Convert the element instead.
314 SDValue DAGTypeLegalizer::ScalarizeVecOp_BIT_CONVERT(SDNode *N) {
315 SDValue Elt = GetScalarizedVector(N->getOperand(0));
316 return DAG.getNode(ISD::BIT_CONVERT, N->getDebugLoc(),
317 N->getValueType(0), Elt);
320 /// ScalarizeVecOp_CONCAT_VECTORS - The vectors to concatenate have length one -
321 /// use a BUILD_VECTOR instead.
322 SDValue DAGTypeLegalizer::ScalarizeVecOp_CONCAT_VECTORS(SDNode *N) {
323 SmallVector<SDValue, 8> Ops(N->getNumOperands());
324 for (unsigned i = 0, e = N->getNumOperands(); i < e; ++i)
325 Ops[i] = GetScalarizedVector(N->getOperand(i));
326 return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), N->getValueType(0),
327 &Ops[0], Ops.size());
330 /// ScalarizeVecOp_EXTRACT_VECTOR_ELT - If the input is a vector that needs to
331 /// be scalarized, it must be <1 x ty>, so just return the element, ignoring the
333 SDValue DAGTypeLegalizer::ScalarizeVecOp_EXTRACT_VECTOR_ELT(SDNode *N) {
334 SDValue Res = GetScalarizedVector(N->getOperand(0));
335 if (Res.getValueType() != N->getValueType(0))
336 Res = DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), N->getValueType(0),
341 /// ScalarizeVecOp_STORE - If the value to store is a vector that needs to be
342 /// scalarized, it must be <1 x ty>. Just store the element.
343 SDValue DAGTypeLegalizer::ScalarizeVecOp_STORE(StoreSDNode *N, unsigned OpNo){
344 assert(N->isUnindexed() && "Indexed store of one-element vector?");
345 assert(OpNo == 1 && "Do not know how to scalarize this operand!");
346 DebugLoc dl = N->getDebugLoc();
348 if (N->isTruncatingStore())
349 return DAG.getTruncStore(N->getChain(), dl,
350 GetScalarizedVector(N->getOperand(1)),
352 N->getSrcValue(), N->getSrcValueOffset(),
353 N->getMemoryVT().getVectorElementType(),
354 N->isVolatile(), N->getAlignment());
356 return DAG.getStore(N->getChain(), dl, GetScalarizedVector(N->getOperand(1)),
357 N->getBasePtr(), N->getSrcValue(), N->getSrcValueOffset(),
358 N->isVolatile(), N->getAlignment());
362 //===----------------------------------------------------------------------===//
363 // Result Vector Splitting
364 //===----------------------------------------------------------------------===//
366 /// SplitVectorResult - This method is called when the specified result of the
367 /// specified node is found to need vector splitting. At this point, the node
368 /// may also have invalid operands or may have other results that need
369 /// legalization, we just know that (at least) one result needs vector
371 void DAGTypeLegalizer::SplitVectorResult(SDNode *N, unsigned ResNo) {
372 DEBUG(cerr << "Split node result: "; N->dump(&DAG); cerr << "\n");
375 switch (N->getOpcode()) {
378 cerr << "SplitVectorResult #" << ResNo << ": ";
379 N->dump(&DAG); cerr << "\n";
381 LLVM_UNREACHABLE("Do not know how to split the result of this operator!");
383 case ISD::MERGE_VALUES: SplitRes_MERGE_VALUES(N, Lo, Hi); break;
384 case ISD::SELECT: SplitRes_SELECT(N, Lo, Hi); break;
385 case ISD::SELECT_CC: SplitRes_SELECT_CC(N, Lo, Hi); break;
386 case ISD::UNDEF: SplitRes_UNDEF(N, Lo, Hi); break;
388 case ISD::BIT_CONVERT: SplitVecRes_BIT_CONVERT(N, Lo, Hi); break;
389 case ISD::BUILD_VECTOR: SplitVecRes_BUILD_VECTOR(N, Lo, Hi); break;
390 case ISD::CONCAT_VECTORS: SplitVecRes_CONCAT_VECTORS(N, Lo, Hi); break;
391 case ISD::CONVERT_RNDSAT: SplitVecRes_CONVERT_RNDSAT(N, Lo, Hi); break;
392 case ISD::EXTRACT_SUBVECTOR: SplitVecRes_EXTRACT_SUBVECTOR(N, Lo, Hi); break;
393 case ISD::FPOWI: SplitVecRes_FPOWI(N, Lo, Hi); break;
394 case ISD::INSERT_VECTOR_ELT: SplitVecRes_INSERT_VECTOR_ELT(N, Lo, Hi); break;
395 case ISD::SCALAR_TO_VECTOR: SplitVecRes_SCALAR_TO_VECTOR(N, Lo, Hi); break;
397 SplitVecRes_LOAD(cast<LoadSDNode>(N), Lo, Hi);
401 SplitVecRes_SETCC(N, Lo, Hi);
403 case ISD::VECTOR_SHUFFLE:
404 SplitVecRes_VECTOR_SHUFFLE(cast<ShuffleVectorSDNode>(N), Lo, Hi);
419 case ISD::FNEARBYINT:
420 case ISD::FP_TO_SINT:
421 case ISD::FP_TO_UINT:
422 case ISD::SINT_TO_FP:
423 case ISD::UINT_TO_FP:
425 case ISD::SIGN_EXTEND:
426 case ISD::ZERO_EXTEND:
427 case ISD::ANY_EXTEND:
428 SplitVecRes_UnaryOp(N, Lo, Hi);
450 SplitVecRes_BinOp(N, Lo, Hi);
454 // If Lo/Hi is null, the sub-method took care of registering results etc.
456 SetSplitVector(SDValue(N, ResNo), Lo, Hi);
459 void DAGTypeLegalizer::SplitVecRes_BinOp(SDNode *N, SDValue &Lo,
461 SDValue LHSLo, LHSHi;
462 GetSplitVector(N->getOperand(0), LHSLo, LHSHi);
463 SDValue RHSLo, RHSHi;
464 GetSplitVector(N->getOperand(1), RHSLo, RHSHi);
465 DebugLoc dl = N->getDebugLoc();
467 Lo = DAG.getNode(N->getOpcode(), dl, LHSLo.getValueType(), LHSLo, RHSLo);
468 Hi = DAG.getNode(N->getOpcode(), dl, LHSHi.getValueType(), LHSHi, RHSHi);
471 void DAGTypeLegalizer::SplitVecRes_BIT_CONVERT(SDNode *N, SDValue &Lo,
473 // We know the result is a vector. The input may be either a vector or a
476 GetSplitDestVTs(N->getValueType(0), LoVT, HiVT);
477 DebugLoc dl = N->getDebugLoc();
479 SDValue InOp = N->getOperand(0);
480 MVT InVT = InOp.getValueType();
482 // Handle some special cases efficiently.
483 switch (getTypeAction(InVT)) {
485 assert(false && "Unknown type action!");
489 case ScalarizeVector:
493 // A scalar to vector conversion, where the scalar needs expansion.
494 // If the vector is being split in two then we can just convert the
497 GetExpandedOp(InOp, Lo, Hi);
498 if (TLI.isBigEndian())
500 Lo = DAG.getNode(ISD::BIT_CONVERT, dl, LoVT, Lo);
501 Hi = DAG.getNode(ISD::BIT_CONVERT, dl, HiVT, Hi);
506 // If the input is a vector that needs to be split, convert each split
507 // piece of the input now.
508 GetSplitVector(InOp, Lo, Hi);
509 Lo = DAG.getNode(ISD::BIT_CONVERT, dl, LoVT, Lo);
510 Hi = DAG.getNode(ISD::BIT_CONVERT, dl, HiVT, Hi);
514 // In the general case, convert the input to an integer and split it by hand.
515 MVT LoIntVT = MVT::getIntegerVT(LoVT.getSizeInBits());
516 MVT HiIntVT = MVT::getIntegerVT(HiVT.getSizeInBits());
517 if (TLI.isBigEndian())
518 std::swap(LoIntVT, HiIntVT);
520 SplitInteger(BitConvertToInteger(InOp), LoIntVT, HiIntVT, Lo, Hi);
522 if (TLI.isBigEndian())
524 Lo = DAG.getNode(ISD::BIT_CONVERT, dl, LoVT, Lo);
525 Hi = DAG.getNode(ISD::BIT_CONVERT, dl, HiVT, Hi);
528 void DAGTypeLegalizer::SplitVecRes_BUILD_VECTOR(SDNode *N, SDValue &Lo,
531 DebugLoc dl = N->getDebugLoc();
532 GetSplitDestVTs(N->getValueType(0), LoVT, HiVT);
533 unsigned LoNumElts = LoVT.getVectorNumElements();
534 SmallVector<SDValue, 8> LoOps(N->op_begin(), N->op_begin()+LoNumElts);
535 Lo = DAG.getNode(ISD::BUILD_VECTOR, dl, LoVT, &LoOps[0], LoOps.size());
537 SmallVector<SDValue, 8> HiOps(N->op_begin()+LoNumElts, N->op_end());
538 Hi = DAG.getNode(ISD::BUILD_VECTOR, dl, HiVT, &HiOps[0], HiOps.size());
541 void DAGTypeLegalizer::SplitVecRes_CONCAT_VECTORS(SDNode *N, SDValue &Lo,
543 assert(!(N->getNumOperands() & 1) && "Unsupported CONCAT_VECTORS");
544 DebugLoc dl = N->getDebugLoc();
545 unsigned NumSubvectors = N->getNumOperands() / 2;
546 if (NumSubvectors == 1) {
547 Lo = N->getOperand(0);
548 Hi = N->getOperand(1);
553 GetSplitDestVTs(N->getValueType(0), LoVT, HiVT);
555 SmallVector<SDValue, 8> LoOps(N->op_begin(), N->op_begin()+NumSubvectors);
556 Lo = DAG.getNode(ISD::CONCAT_VECTORS, dl, LoVT, &LoOps[0], LoOps.size());
558 SmallVector<SDValue, 8> HiOps(N->op_begin()+NumSubvectors, N->op_end());
559 Hi = DAG.getNode(ISD::CONCAT_VECTORS, dl, HiVT, &HiOps[0], HiOps.size());
562 void DAGTypeLegalizer::SplitVecRes_CONVERT_RNDSAT(SDNode *N, SDValue &Lo,
565 DebugLoc dl = N->getDebugLoc();
566 GetSplitDestVTs(N->getValueType(0), LoVT, HiVT);
568 SDValue DTyOpLo = DAG.getValueType(LoVT);
569 SDValue DTyOpHi = DAG.getValueType(HiVT);
571 SDValue RndOp = N->getOperand(3);
572 SDValue SatOp = N->getOperand(4);
573 ISD::CvtCode CvtCode = cast<CvtRndSatSDNode>(N)->getCvtCode();
577 MVT InVT = N->getOperand(0).getValueType();
578 switch (getTypeAction(InVT)) {
579 default: assert(0 && "Unexpected type action!");
581 MVT InNVT = MVT::getVectorVT(InVT.getVectorElementType(),
582 LoVT.getVectorNumElements());
583 VLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, InNVT, N->getOperand(0),
584 DAG.getIntPtrConstant(0));
585 VHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, InNVT, N->getOperand(0),
586 DAG.getIntPtrConstant(InNVT.getVectorNumElements()));
590 GetSplitVector(N->getOperand(0), VLo, VHi);
593 // If the result needs to be split and the input needs to be widened,
594 // the two types must have different lengths. Use the widened result
595 // and extract from it to do the split.
596 SDValue InOp = GetWidenedVector(N->getOperand(0));
597 MVT InNVT = MVT::getVectorVT(InVT.getVectorElementType(),
598 LoVT.getVectorNumElements());
599 VLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, InNVT, InOp,
600 DAG.getIntPtrConstant(0));
601 VHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, InNVT, InOp,
602 DAG.getIntPtrConstant(InNVT.getVectorNumElements()));
607 SDValue STyOpLo = DAG.getValueType(VLo.getValueType());
608 SDValue STyOpHi = DAG.getValueType(VHi.getValueType());
610 Lo = DAG.getConvertRndSat(LoVT, dl, VLo, DTyOpLo, STyOpLo, RndOp, SatOp,
612 Hi = DAG.getConvertRndSat(HiVT, dl, VHi, DTyOpHi, STyOpHi, RndOp, SatOp,
616 void DAGTypeLegalizer::SplitVecRes_EXTRACT_SUBVECTOR(SDNode *N, SDValue &Lo,
618 SDValue Vec = N->getOperand(0);
619 SDValue Idx = N->getOperand(1);
620 MVT IdxVT = Idx.getValueType();
621 DebugLoc dl = N->getDebugLoc();
624 GetSplitDestVTs(N->getValueType(0), LoVT, HiVT);
626 Lo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, LoVT, Vec, Idx);
627 Idx = DAG.getNode(ISD::ADD, dl, IdxVT, Idx,
628 DAG.getConstant(LoVT.getVectorNumElements(), IdxVT));
629 Hi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, HiVT, Vec, Idx);
632 void DAGTypeLegalizer::SplitVecRes_FPOWI(SDNode *N, SDValue &Lo,
634 DebugLoc dl = N->getDebugLoc();
635 GetSplitVector(N->getOperand(0), Lo, Hi);
636 Lo = DAG.getNode(ISD::FPOWI, dl, Lo.getValueType(), Lo, N->getOperand(1));
637 Hi = DAG.getNode(ISD::FPOWI, dl, Hi.getValueType(), Hi, N->getOperand(1));
640 void DAGTypeLegalizer::SplitVecRes_INSERT_VECTOR_ELT(SDNode *N, SDValue &Lo,
642 SDValue Vec = N->getOperand(0);
643 SDValue Elt = N->getOperand(1);
644 SDValue Idx = N->getOperand(2);
645 DebugLoc dl = N->getDebugLoc();
646 GetSplitVector(Vec, Lo, Hi);
648 if (ConstantSDNode *CIdx = dyn_cast<ConstantSDNode>(Idx)) {
649 unsigned IdxVal = CIdx->getZExtValue();
650 unsigned LoNumElts = Lo.getValueType().getVectorNumElements();
651 if (IdxVal < LoNumElts)
652 Lo = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
653 Lo.getValueType(), Lo, Elt, Idx);
655 Hi = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, Hi.getValueType(), Hi, Elt,
656 DAG.getIntPtrConstant(IdxVal - LoNumElts));
660 // Spill the vector to the stack.
661 MVT VecVT = Vec.getValueType();
662 MVT EltVT = VecVT.getVectorElementType();
663 SDValue StackPtr = DAG.CreateStackTemporary(VecVT);
664 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Vec, StackPtr, NULL, 0);
666 // Store the new element. This may be larger than the vector element type,
667 // so use a truncating store.
668 SDValue EltPtr = GetVectorElementPointer(StackPtr, EltVT, Idx);
670 TLI.getTargetData()->getPrefTypeAlignment(VecVT.getTypeForMVT(
672 Store = DAG.getTruncStore(Store, dl, Elt, EltPtr, NULL, 0, EltVT);
674 // Load the Lo part from the stack slot.
675 Lo = DAG.getLoad(Lo.getValueType(), dl, Store, StackPtr, NULL, 0);
677 // Increment the pointer to the other part.
678 unsigned IncrementSize = Lo.getValueType().getSizeInBits() / 8;
679 StackPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr,
680 DAG.getIntPtrConstant(IncrementSize));
682 // Load the Hi part from the stack slot.
683 Hi = DAG.getLoad(Hi.getValueType(), dl, Store, StackPtr, NULL, 0, false,
684 MinAlign(Alignment, IncrementSize));
687 void DAGTypeLegalizer::SplitVecRes_SCALAR_TO_VECTOR(SDNode *N, SDValue &Lo,
690 DebugLoc dl = N->getDebugLoc();
691 GetSplitDestVTs(N->getValueType(0), LoVT, HiVT);
692 Lo = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LoVT, N->getOperand(0));
693 Hi = DAG.getUNDEF(HiVT);
696 void DAGTypeLegalizer::SplitVecRes_LOAD(LoadSDNode *LD, SDValue &Lo,
698 assert(ISD::isUNINDEXEDLoad(LD) && "Indexed load during type legalization!");
700 DebugLoc dl = LD->getDebugLoc();
701 GetSplitDestVTs(LD->getValueType(0), LoVT, HiVT);
703 ISD::LoadExtType ExtType = LD->getExtensionType();
704 SDValue Ch = LD->getChain();
705 SDValue Ptr = LD->getBasePtr();
706 SDValue Offset = DAG.getUNDEF(Ptr.getValueType());
707 const Value *SV = LD->getSrcValue();
708 int SVOffset = LD->getSrcValueOffset();
709 MVT MemoryVT = LD->getMemoryVT();
710 unsigned Alignment = LD->getAlignment();
711 bool isVolatile = LD->isVolatile();
713 MVT LoMemVT, HiMemVT;
714 GetSplitDestVTs(MemoryVT, LoMemVT, HiMemVT);
716 Lo = DAG.getLoad(ISD::UNINDEXED, dl, ExtType, LoVT, Ch, Ptr, Offset,
717 SV, SVOffset, LoMemVT, isVolatile, Alignment);
719 unsigned IncrementSize = LoMemVT.getSizeInBits()/8;
720 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
721 DAG.getIntPtrConstant(IncrementSize));
722 SVOffset += IncrementSize;
723 Alignment = MinAlign(Alignment, IncrementSize);
724 Hi = DAG.getLoad(ISD::UNINDEXED, dl, ExtType, HiVT, Ch, Ptr, Offset,
725 SV, SVOffset, HiMemVT, isVolatile, Alignment);
727 // Build a factor node to remember that this load is independent of the
729 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
732 // Legalized the chain result - switch anything that used the old chain to
734 ReplaceValueWith(SDValue(LD, 1), Ch);
737 void DAGTypeLegalizer::SplitVecRes_SETCC(SDNode *N, SDValue &Lo, SDValue &Hi) {
739 DebugLoc DL = N->getDebugLoc();
740 GetSplitDestVTs(N->getValueType(0), LoVT, HiVT);
743 MVT InVT = N->getOperand(0).getValueType();
744 SDValue LL, LH, RL, RH;
745 MVT InNVT = MVT::getVectorVT(InVT.getVectorElementType(),
746 LoVT.getVectorNumElements());
747 LL = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, InNVT, N->getOperand(0),
748 DAG.getIntPtrConstant(0));
749 LH = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, InNVT, N->getOperand(0),
750 DAG.getIntPtrConstant(InNVT.getVectorNumElements()));
752 RL = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, InNVT, N->getOperand(1),
753 DAG.getIntPtrConstant(0));
754 RH = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, InNVT, N->getOperand(1),
755 DAG.getIntPtrConstant(InNVT.getVectorNumElements()));
757 Lo = DAG.getNode(N->getOpcode(), DL, LoVT, LL, RL, N->getOperand(2));
758 Hi = DAG.getNode(N->getOpcode(), DL, HiVT, LH, RH, N->getOperand(2));
761 void DAGTypeLegalizer::SplitVecRes_UnaryOp(SDNode *N, SDValue &Lo,
763 // Get the dest types - they may not match the input types, e.g. int_to_fp.
765 DebugLoc dl = N->getDebugLoc();
766 GetSplitDestVTs(N->getValueType(0), LoVT, HiVT);
769 MVT InVT = N->getOperand(0).getValueType();
770 switch (getTypeAction(InVT)) {
771 default: assert(0 && "Unexpected type action!");
773 MVT InNVT = MVT::getVectorVT(InVT.getVectorElementType(),
774 LoVT.getVectorNumElements());
775 Lo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, InNVT, N->getOperand(0),
776 DAG.getIntPtrConstant(0));
777 Hi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, InNVT, N->getOperand(0),
778 DAG.getIntPtrConstant(InNVT.getVectorNumElements()));
782 GetSplitVector(N->getOperand(0), Lo, Hi);
785 // If the result needs to be split and the input needs to be widened,
786 // the two types must have different lengths. Use the widened result
787 // and extract from it to do the split.
788 SDValue InOp = GetWidenedVector(N->getOperand(0));
789 MVT InNVT = MVT::getVectorVT(InVT.getVectorElementType(),
790 LoVT.getVectorNumElements());
791 Lo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, InNVT, InOp,
792 DAG.getIntPtrConstant(0));
793 Hi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, InNVT, InOp,
794 DAG.getIntPtrConstant(InNVT.getVectorNumElements()));
799 Lo = DAG.getNode(N->getOpcode(), dl, LoVT, Lo);
800 Hi = DAG.getNode(N->getOpcode(), dl, HiVT, Hi);
803 void DAGTypeLegalizer::SplitVecRes_VECTOR_SHUFFLE(ShuffleVectorSDNode *N,
804 SDValue &Lo, SDValue &Hi) {
805 // The low and high parts of the original input give four input vectors.
807 DebugLoc dl = N->getDebugLoc();
808 GetSplitVector(N->getOperand(0), Inputs[0], Inputs[1]);
809 GetSplitVector(N->getOperand(1), Inputs[2], Inputs[3]);
810 MVT NewVT = Inputs[0].getValueType();
811 unsigned NewElts = NewVT.getVectorNumElements();
813 // If Lo or Hi uses elements from at most two of the four input vectors, then
814 // express it as a vector shuffle of those two inputs. Otherwise extract the
815 // input elements by hand and construct the Lo/Hi output using a BUILD_VECTOR.
816 SmallVector<int, 16> Ops;
817 for (unsigned High = 0; High < 2; ++High) {
818 SDValue &Output = High ? Hi : Lo;
820 // Build a shuffle mask for the output, discovering on the fly which
821 // input vectors to use as shuffle operands (recorded in InputUsed).
822 // If building a suitable shuffle vector proves too hard, then bail
823 // out with useBuildVector set.
824 unsigned InputUsed[2] = { -1U, -1U }; // Not yet discovered.
825 unsigned FirstMaskIdx = High * NewElts;
826 bool useBuildVector = false;
827 for (unsigned MaskOffset = 0; MaskOffset < NewElts; ++MaskOffset) {
828 // The mask element. This indexes into the input.
829 int Idx = N->getMaskElt(FirstMaskIdx + MaskOffset);
831 // The input vector this mask element indexes into.
832 unsigned Input = (unsigned)Idx / NewElts;
834 if (Input >= array_lengthof(Inputs)) {
835 // The mask element does not index into any input vector.
840 // Turn the index into an offset from the start of the input vector.
841 Idx -= Input * NewElts;
843 // Find or create a shuffle vector operand to hold this input.
845 for (OpNo = 0; OpNo < array_lengthof(InputUsed); ++OpNo) {
846 if (InputUsed[OpNo] == Input) {
847 // This input vector is already an operand.
849 } else if (InputUsed[OpNo] == -1U) {
850 // Create a new operand for this input vector.
851 InputUsed[OpNo] = Input;
856 if (OpNo >= array_lengthof(InputUsed)) {
857 // More than two input vectors used! Give up on trying to create a
858 // shuffle vector. Insert all elements into a BUILD_VECTOR instead.
859 useBuildVector = true;
863 // Add the mask index for the new shuffle vector.
864 Ops.push_back(Idx + OpNo * NewElts);
867 if (useBuildVector) {
868 MVT EltVT = NewVT.getVectorElementType();
869 SmallVector<SDValue, 16> SVOps;
871 // Extract the input elements by hand.
872 for (unsigned MaskOffset = 0; MaskOffset < NewElts; ++MaskOffset) {
873 // The mask element. This indexes into the input.
874 int Idx = N->getMaskElt(FirstMaskIdx + MaskOffset);
876 // The input vector this mask element indexes into.
877 unsigned Input = (unsigned)Idx / NewElts;
879 if (Input >= array_lengthof(Inputs)) {
880 // The mask element is "undef" or indexes off the end of the input.
881 SVOps.push_back(DAG.getUNDEF(EltVT));
885 // Turn the index into an offset from the start of the input vector.
886 Idx -= Input * NewElts;
888 // Extract the vector element by hand.
889 SVOps.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT,
890 Inputs[Input], DAG.getIntPtrConstant(Idx)));
893 // Construct the Lo/Hi output using a BUILD_VECTOR.
894 Output = DAG.getNode(ISD::BUILD_VECTOR,dl,NewVT, &SVOps[0], SVOps.size());
895 } else if (InputUsed[0] == -1U) {
896 // No input vectors were used! The result is undefined.
897 Output = DAG.getUNDEF(NewVT);
899 SDValue Op0 = Inputs[InputUsed[0]];
900 // If only one input was used, use an undefined vector for the other.
901 SDValue Op1 = InputUsed[1] == -1U ?
902 DAG.getUNDEF(NewVT) : Inputs[InputUsed[1]];
903 // At least one input vector was used. Create a new shuffle vector.
904 Output = DAG.getVectorShuffle(NewVT, dl, Op0, Op1, &Ops[0]);
912 //===----------------------------------------------------------------------===//
913 // Operand Vector Splitting
914 //===----------------------------------------------------------------------===//
916 /// SplitVectorOperand - This method is called when the specified operand of the
917 /// specified node is found to need vector splitting. At this point, all of the
918 /// result types of the node are known to be legal, but other operands of the
919 /// node may need legalization as well as the specified one.
920 bool DAGTypeLegalizer::SplitVectorOperand(SDNode *N, unsigned OpNo) {
921 DEBUG(cerr << "Split node operand: "; N->dump(&DAG); cerr << "\n");
922 SDValue Res = SDValue();
924 if (Res.getNode() == 0) {
925 switch (N->getOpcode()) {
928 cerr << "SplitVectorOperand Op #" << OpNo << ": ";
929 N->dump(&DAG); cerr << "\n";
931 LLVM_UNREACHABLE("Do not know how to split this operator's operand!");
933 case ISD::BIT_CONVERT: Res = SplitVecOp_BIT_CONVERT(N); break;
934 case ISD::EXTRACT_SUBVECTOR: Res = SplitVecOp_EXTRACT_SUBVECTOR(N); break;
935 case ISD::EXTRACT_VECTOR_ELT:Res = SplitVecOp_EXTRACT_VECTOR_ELT(N); break;
937 Res = SplitVecOp_STORE(cast<StoreSDNode>(N), OpNo);
943 case ISD::FP_TO_SINT:
944 case ISD::FP_TO_UINT:
945 case ISD::SINT_TO_FP:
946 case ISD::UINT_TO_FP:
948 case ISD::SIGN_EXTEND:
949 case ISD::ZERO_EXTEND:
950 case ISD::ANY_EXTEND:
951 Res = SplitVecOp_UnaryOp(N);
956 // If the result is null, the sub-method took care of registering results etc.
957 if (!Res.getNode()) return false;
959 // If the result is N, the sub-method updated N in place. Tell the legalizer
961 if (Res.getNode() == N)
964 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 &&
965 "Invalid operand expansion");
967 ReplaceValueWith(SDValue(N, 0), Res);
971 SDValue DAGTypeLegalizer::SplitVecOp_UnaryOp(SDNode *N) {
972 // The result has a legal vector type, but the input needs splitting.
973 MVT ResVT = N->getValueType(0);
975 DebugLoc dl = N->getDebugLoc();
976 GetSplitVector(N->getOperand(0), Lo, Hi);
977 MVT InVT = Lo.getValueType();
979 MVT OutVT = MVT::getVectorVT(ResVT.getVectorElementType(),
980 InVT.getVectorNumElements());
982 Lo = DAG.getNode(N->getOpcode(), dl, OutVT, Lo);
983 Hi = DAG.getNode(N->getOpcode(), dl, OutVT, Hi);
985 return DAG.getNode(ISD::CONCAT_VECTORS, dl, ResVT, Lo, Hi);
988 SDValue DAGTypeLegalizer::SplitVecOp_BIT_CONVERT(SDNode *N) {
989 // For example, i64 = BIT_CONVERT v4i16 on alpha. Typically the vector will
990 // end up being split all the way down to individual components. Convert the
991 // split pieces into integers and reassemble.
993 GetSplitVector(N->getOperand(0), Lo, Hi);
994 Lo = BitConvertToInteger(Lo);
995 Hi = BitConvertToInteger(Hi);
997 if (TLI.isBigEndian())
1000 return DAG.getNode(ISD::BIT_CONVERT, N->getDebugLoc(), N->getValueType(0),
1001 JoinIntegers(Lo, Hi));
1004 SDValue DAGTypeLegalizer::SplitVecOp_EXTRACT_SUBVECTOR(SDNode *N) {
1005 // We know that the extracted result type is legal. For now, assume the index
1007 MVT SubVT = N->getValueType(0);
1008 SDValue Idx = N->getOperand(1);
1009 DebugLoc dl = N->getDebugLoc();
1011 GetSplitVector(N->getOperand(0), Lo, Hi);
1013 uint64_t LoElts = Lo.getValueType().getVectorNumElements();
1014 uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
1016 if (IdxVal < LoElts) {
1017 assert(IdxVal + SubVT.getVectorNumElements() <= LoElts &&
1018 "Extracted subvector crosses vector split!");
1019 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, Lo, Idx);
1021 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, Hi,
1022 DAG.getConstant(IdxVal - LoElts, Idx.getValueType()));
1026 SDValue DAGTypeLegalizer::SplitVecOp_EXTRACT_VECTOR_ELT(SDNode *N) {
1027 SDValue Vec = N->getOperand(0);
1028 SDValue Idx = N->getOperand(1);
1029 MVT VecVT = Vec.getValueType();
1031 if (isa<ConstantSDNode>(Idx)) {
1032 uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
1033 assert(IdxVal < VecVT.getVectorNumElements() && "Invalid vector index!");
1036 GetSplitVector(Vec, Lo, Hi);
1038 uint64_t LoElts = Lo.getValueType().getVectorNumElements();
1040 if (IdxVal < LoElts)
1041 return DAG.UpdateNodeOperands(SDValue(N, 0), Lo, Idx);
1042 return DAG.UpdateNodeOperands(SDValue(N, 0), Hi,
1043 DAG.getConstant(IdxVal - LoElts,
1044 Idx.getValueType()));
1047 // Store the vector to the stack.
1048 MVT EltVT = VecVT.getVectorElementType();
1049 DebugLoc dl = N->getDebugLoc();
1050 SDValue StackPtr = DAG.CreateStackTemporary(VecVT);
1051 int SPFI = cast<FrameIndexSDNode>(StackPtr.getNode())->getIndex();
1052 const Value *SV = PseudoSourceValue::getFixedStack(SPFI);
1053 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Vec, StackPtr, SV, 0);
1055 // Load back the required element.
1056 StackPtr = GetVectorElementPointer(StackPtr, EltVT, Idx);
1057 return DAG.getExtLoad(ISD::EXTLOAD, dl, N->getValueType(0), Store, StackPtr,
1061 SDValue DAGTypeLegalizer::SplitVecOp_STORE(StoreSDNode *N, unsigned OpNo) {
1062 assert(N->isUnindexed() && "Indexed store of vector?");
1063 assert(OpNo == 1 && "Can only split the stored value");
1064 DebugLoc dl = N->getDebugLoc();
1066 bool isTruncating = N->isTruncatingStore();
1067 SDValue Ch = N->getChain();
1068 SDValue Ptr = N->getBasePtr();
1069 int SVOffset = N->getSrcValueOffset();
1070 MVT MemoryVT = N->getMemoryVT();
1071 unsigned Alignment = N->getAlignment();
1072 bool isVol = N->isVolatile();
1074 GetSplitVector(N->getOperand(1), Lo, Hi);
1076 MVT LoMemVT, HiMemVT;
1077 GetSplitDestVTs(MemoryVT, LoMemVT, HiMemVT);
1079 unsigned IncrementSize = LoMemVT.getSizeInBits()/8;
1082 Lo = DAG.getTruncStore(Ch, dl, Lo, Ptr, N->getSrcValue(), SVOffset,
1083 LoMemVT, isVol, Alignment);
1085 Lo = DAG.getStore(Ch, dl, Lo, Ptr, N->getSrcValue(), SVOffset,
1088 // Increment the pointer to the other half.
1089 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
1090 DAG.getIntPtrConstant(IncrementSize));
1093 Hi = DAG.getTruncStore(Ch, dl, Hi, Ptr,
1094 N->getSrcValue(), SVOffset+IncrementSize,
1096 isVol, MinAlign(Alignment, IncrementSize));
1098 Hi = DAG.getStore(Ch, dl, Hi, Ptr, N->getSrcValue(), SVOffset+IncrementSize,
1099 isVol, MinAlign(Alignment, IncrementSize));
1101 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi);
1105 //===----------------------------------------------------------------------===//
1106 // Result Vector Widening
1107 //===----------------------------------------------------------------------===//
1109 void DAGTypeLegalizer::WidenVectorResult(SDNode *N, unsigned ResNo) {
1110 DEBUG(cerr << "Widen node result " << ResNo << ": "; N->dump(&DAG);
1112 SDValue Res = SDValue();
1114 switch (N->getOpcode()) {
1117 cerr << "WidenVectorResult #" << ResNo << ": ";
1118 N->dump(&DAG); cerr << "\n";
1120 LLVM_UNREACHABLE("Do not know how to widen the result of this operator!");
1122 case ISD::BIT_CONVERT: Res = WidenVecRes_BIT_CONVERT(N); break;
1123 case ISD::BUILD_VECTOR: Res = WidenVecRes_BUILD_VECTOR(N); break;
1124 case ISD::CONCAT_VECTORS: Res = WidenVecRes_CONCAT_VECTORS(N); break;
1125 case ISD::CONVERT_RNDSAT: Res = WidenVecRes_CONVERT_RNDSAT(N); break;
1126 case ISD::EXTRACT_SUBVECTOR: Res = WidenVecRes_EXTRACT_SUBVECTOR(N); break;
1127 case ISD::INSERT_VECTOR_ELT: Res = WidenVecRes_INSERT_VECTOR_ELT(N); break;
1128 case ISD::LOAD: Res = WidenVecRes_LOAD(N); break;
1129 case ISD::SCALAR_TO_VECTOR: Res = WidenVecRes_SCALAR_TO_VECTOR(N); break;
1130 case ISD::SELECT: Res = WidenVecRes_SELECT(N); break;
1131 case ISD::SELECT_CC: Res = WidenVecRes_SELECT_CC(N); break;
1132 case ISD::UNDEF: Res = WidenVecRes_UNDEF(N); break;
1133 case ISD::VECTOR_SHUFFLE:
1134 Res = WidenVecRes_VECTOR_SHUFFLE(cast<ShuffleVectorSDNode>(N));
1137 Res = WidenVecRes_VSETCC(N);
1144 case ISD::FCOPYSIGN:
1161 Res = WidenVecRes_Binary(N);
1167 Res = WidenVecRes_Shift(N);
1171 case ISD::FP_TO_SINT:
1172 case ISD::FP_TO_UINT:
1173 case ISD::SINT_TO_FP:
1174 case ISD::UINT_TO_FP:
1176 case ISD::SIGN_EXTEND:
1177 case ISD::ZERO_EXTEND:
1178 case ISD::ANY_EXTEND:
1179 Res = WidenVecRes_Convert(N);
1190 Res = WidenVecRes_Unary(N);
1194 // If Res is null, the sub-method took care of registering the result.
1196 SetWidenedVector(SDValue(N, ResNo), Res);
1199 SDValue DAGTypeLegalizer::WidenVecRes_Binary(SDNode *N) {
1200 // Binary op widening.
1201 MVT WidenVT = TLI.getTypeToTransformTo(N->getValueType(0));
1202 SDValue InOp1 = GetWidenedVector(N->getOperand(0));
1203 SDValue InOp2 = GetWidenedVector(N->getOperand(1));
1204 return DAG.getNode(N->getOpcode(), N->getDebugLoc(), WidenVT, InOp1, InOp2);
1207 SDValue DAGTypeLegalizer::WidenVecRes_Convert(SDNode *N) {
1208 SDValue InOp = N->getOperand(0);
1209 DebugLoc dl = N->getDebugLoc();
1211 MVT WidenVT = TLI.getTypeToTransformTo(N->getValueType(0));
1212 unsigned WidenNumElts = WidenVT.getVectorNumElements();
1214 MVT InVT = InOp.getValueType();
1215 MVT InEltVT = InVT.getVectorElementType();
1216 MVT InWidenVT = MVT::getVectorVT(InEltVT, WidenNumElts);
1218 unsigned Opcode = N->getOpcode();
1219 unsigned InVTNumElts = InVT.getVectorNumElements();
1221 if (getTypeAction(InVT) == WidenVector) {
1222 InOp = GetWidenedVector(N->getOperand(0));
1223 InVT = InOp.getValueType();
1224 InVTNumElts = InVT.getVectorNumElements();
1225 if (InVTNumElts == WidenNumElts)
1226 return DAG.getNode(Opcode, dl, WidenVT, InOp);
1229 if (TLI.isTypeLegal(InWidenVT)) {
1230 // Because the result and the input are different vector types, widening
1231 // the result could create a legal type but widening the input might make
1232 // it an illegal type that might lead to repeatedly splitting the input
1233 // and then widening it. To avoid this, we widen the input only if
1234 // it results in a legal type.
1235 if (WidenNumElts % InVTNumElts == 0) {
1236 // Widen the input and call convert on the widened input vector.
1237 unsigned NumConcat = WidenNumElts/InVTNumElts;
1238 SmallVector<SDValue, 16> Ops(NumConcat);
1240 SDValue UndefVal = DAG.getUNDEF(InVT);
1241 for (unsigned i = 1; i != NumConcat; ++i)
1243 return DAG.getNode(Opcode, dl, WidenVT,
1244 DAG.getNode(ISD::CONCAT_VECTORS, dl, InWidenVT,
1245 &Ops[0], NumConcat));
1248 if (InVTNumElts % WidenNumElts == 0) {
1249 // Extract the input and convert the shorten input vector.
1250 return DAG.getNode(Opcode, dl, WidenVT,
1251 DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, InWidenVT,
1252 InOp, DAG.getIntPtrConstant(0)));
1256 // Otherwise unroll into some nasty scalar code and rebuild the vector.
1257 SmallVector<SDValue, 16> Ops(WidenNumElts);
1258 MVT EltVT = WidenVT.getVectorElementType();
1259 unsigned MinElts = std::min(InVTNumElts, WidenNumElts);
1261 for (i=0; i < MinElts; ++i)
1262 Ops[i] = DAG.getNode(Opcode, dl, EltVT,
1263 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, InEltVT, InOp,
1264 DAG.getIntPtrConstant(i)));
1266 SDValue UndefVal = DAG.getUNDEF(EltVT);
1267 for (; i < WidenNumElts; ++i)
1270 return DAG.getNode(ISD::BUILD_VECTOR, dl, WidenVT, &Ops[0], WidenNumElts);
1273 SDValue DAGTypeLegalizer::WidenVecRes_Shift(SDNode *N) {
1274 MVT WidenVT = TLI.getTypeToTransformTo(N->getValueType(0));
1275 SDValue InOp = GetWidenedVector(N->getOperand(0));
1276 SDValue ShOp = N->getOperand(1);
1278 MVT ShVT = ShOp.getValueType();
1279 if (getTypeAction(ShVT) == WidenVector) {
1280 ShOp = GetWidenedVector(ShOp);
1281 ShVT = ShOp.getValueType();
1283 MVT ShWidenVT = MVT::getVectorVT(ShVT.getVectorElementType(),
1284 WidenVT.getVectorNumElements());
1285 if (ShVT != ShWidenVT)
1286 ShOp = ModifyToType(ShOp, ShWidenVT);
1288 return DAG.getNode(N->getOpcode(), N->getDebugLoc(), WidenVT, InOp, ShOp);
1291 SDValue DAGTypeLegalizer::WidenVecRes_Unary(SDNode *N) {
1292 // Unary op widening.
1293 MVT WidenVT = TLI.getTypeToTransformTo(N->getValueType(0));
1294 SDValue InOp = GetWidenedVector(N->getOperand(0));
1295 return DAG.getNode(N->getOpcode(), N->getDebugLoc(), WidenVT, InOp);
1298 SDValue DAGTypeLegalizer::WidenVecRes_BIT_CONVERT(SDNode *N) {
1299 SDValue InOp = N->getOperand(0);
1300 MVT InVT = InOp.getValueType();
1301 MVT VT = N->getValueType(0);
1302 MVT WidenVT = TLI.getTypeToTransformTo(VT);
1303 DebugLoc dl = N->getDebugLoc();
1305 switch (getTypeAction(InVT)) {
1307 assert(false && "Unknown type action!");
1311 case PromoteInteger:
1312 // If the InOp is promoted to the same size, convert it. Otherwise,
1313 // fall out of the switch and widen the promoted input.
1314 InOp = GetPromotedInteger(InOp);
1315 InVT = InOp.getValueType();
1316 if (WidenVT.bitsEq(InVT))
1317 return DAG.getNode(ISD::BIT_CONVERT, dl, WidenVT, InOp);
1322 case ScalarizeVector:
1326 // If the InOp is widened to the same size, convert it. Otherwise, fall
1327 // out of the switch and widen the widened input.
1328 InOp = GetWidenedVector(InOp);
1329 InVT = InOp.getValueType();
1330 if (WidenVT.bitsEq(InVT))
1331 // The input widens to the same size. Convert to the widen value.
1332 return DAG.getNode(ISD::BIT_CONVERT, dl, WidenVT, InOp);
1336 unsigned WidenSize = WidenVT.getSizeInBits();
1337 unsigned InSize = InVT.getSizeInBits();
1338 if (WidenSize % InSize == 0) {
1339 // Determine new input vector type. The new input vector type will use
1340 // the same element type (if its a vector) or use the input type as a
1341 // vector. It is the same size as the type to widen to.
1343 unsigned NewNumElts = WidenSize / InSize;
1344 if (InVT.isVector()) {
1345 MVT InEltVT = InVT.getVectorElementType();
1346 NewInVT= MVT::getVectorVT(InEltVT, WidenSize / InEltVT.getSizeInBits());
1348 NewInVT = MVT::getVectorVT(InVT, NewNumElts);
1351 if (TLI.isTypeLegal(NewInVT)) {
1352 // Because the result and the input are different vector types, widening
1353 // the result could create a legal type but widening the input might make
1354 // it an illegal type that might lead to repeatedly splitting the input
1355 // and then widening it. To avoid this, we widen the input only if
1356 // it results in a legal type.
1357 SmallVector<SDValue, 16> Ops(NewNumElts);
1358 SDValue UndefVal = DAG.getUNDEF(InVT);
1360 for (unsigned i = 1; i < NewNumElts; ++i)
1364 if (InVT.isVector())
1365 NewVec = DAG.getNode(ISD::CONCAT_VECTORS, dl,
1366 NewInVT, &Ops[0], NewNumElts);
1368 NewVec = DAG.getNode(ISD::BUILD_VECTOR, dl,
1369 NewInVT, &Ops[0], NewNumElts);
1370 return DAG.getNode(ISD::BIT_CONVERT, dl, WidenVT, NewVec);
1374 return CreateStackStoreLoad(InOp, WidenVT);
1377 SDValue DAGTypeLegalizer::WidenVecRes_BUILD_VECTOR(SDNode *N) {
1378 DebugLoc dl = N->getDebugLoc();
1379 // Build a vector with undefined for the new nodes.
1380 MVT VT = N->getValueType(0);
1381 MVT EltVT = VT.getVectorElementType();
1382 unsigned NumElts = VT.getVectorNumElements();
1384 MVT WidenVT = TLI.getTypeToTransformTo(VT);
1385 unsigned WidenNumElts = WidenVT.getVectorNumElements();
1387 SmallVector<SDValue, 16> NewOps(N->op_begin(), N->op_end());
1388 NewOps.reserve(WidenNumElts);
1389 for (unsigned i = NumElts; i < WidenNumElts; ++i)
1390 NewOps.push_back(DAG.getUNDEF(EltVT));
1392 return DAG.getNode(ISD::BUILD_VECTOR, dl, WidenVT, &NewOps[0], NewOps.size());
1395 SDValue DAGTypeLegalizer::WidenVecRes_CONCAT_VECTORS(SDNode *N) {
1396 MVT InVT = N->getOperand(0).getValueType();
1397 MVT WidenVT = TLI.getTypeToTransformTo(N->getValueType(0));
1398 DebugLoc dl = N->getDebugLoc();
1399 unsigned WidenNumElts = WidenVT.getVectorNumElements();
1400 unsigned NumOperands = N->getNumOperands();
1402 bool InputWidened = false; // Indicates we need to widen the input.
1403 if (getTypeAction(InVT) != WidenVector) {
1404 if (WidenVT.getVectorNumElements() % InVT.getVectorNumElements() == 0) {
1405 // Add undef vectors to widen to correct length.
1406 unsigned NumConcat = WidenVT.getVectorNumElements() /
1407 InVT.getVectorNumElements();
1408 SDValue UndefVal = DAG.getUNDEF(InVT);
1409 SmallVector<SDValue, 16> Ops(NumConcat);
1410 for (unsigned i=0; i < NumOperands; ++i)
1411 Ops[i] = N->getOperand(i);
1412 for (unsigned i = NumOperands; i != NumConcat; ++i)
1414 return DAG.getNode(ISD::CONCAT_VECTORS, dl, WidenVT, &Ops[0], NumConcat);
1417 InputWidened = true;
1418 if (WidenVT == TLI.getTypeToTransformTo(InVT)) {
1419 // The inputs and the result are widen to the same value.
1421 for (i=1; i < NumOperands; ++i)
1422 if (N->getOperand(i).getOpcode() != ISD::UNDEF)
1425 if (i > NumOperands)
1426 // Everything but the first operand is an UNDEF so just return the
1427 // widened first operand.
1428 return GetWidenedVector(N->getOperand(0));
1430 if (NumOperands == 2) {
1431 // Replace concat of two operands with a shuffle.
1432 SmallVector<int, 16> MaskOps(WidenNumElts);
1433 for (unsigned i=0; i < WidenNumElts/2; ++i) {
1435 MaskOps[i+WidenNumElts/2] = i+WidenNumElts;
1437 return DAG.getVectorShuffle(WidenVT, dl,
1438 GetWidenedVector(N->getOperand(0)),
1439 GetWidenedVector(N->getOperand(1)),
1445 // Fall back to use extracts and build vector.
1446 MVT EltVT = WidenVT.getVectorElementType();
1447 unsigned NumInElts = InVT.getVectorNumElements();
1448 SmallVector<SDValue, 16> Ops(WidenNumElts);
1450 for (unsigned i=0; i < NumOperands; ++i) {
1451 SDValue InOp = N->getOperand(i);
1453 InOp = GetWidenedVector(InOp);
1454 for (unsigned j=0; j < NumInElts; ++j)
1455 Ops[Idx++] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, InOp,
1456 DAG.getIntPtrConstant(j));
1458 SDValue UndefVal = DAG.getUNDEF(EltVT);
1459 for (; Idx < WidenNumElts; ++Idx)
1460 Ops[Idx] = UndefVal;
1461 return DAG.getNode(ISD::BUILD_VECTOR, dl, WidenVT, &Ops[0], WidenNumElts);
1464 SDValue DAGTypeLegalizer::WidenVecRes_CONVERT_RNDSAT(SDNode *N) {
1465 DebugLoc dl = N->getDebugLoc();
1466 SDValue InOp = N->getOperand(0);
1467 SDValue RndOp = N->getOperand(3);
1468 SDValue SatOp = N->getOperand(4);
1470 MVT WidenVT = TLI.getTypeToTransformTo(N->getValueType(0));
1471 unsigned WidenNumElts = WidenVT.getVectorNumElements();
1473 MVT InVT = InOp.getValueType();
1474 MVT InEltVT = InVT.getVectorElementType();
1475 MVT InWidenVT = MVT::getVectorVT(InEltVT, WidenNumElts);
1477 SDValue DTyOp = DAG.getValueType(WidenVT);
1478 SDValue STyOp = DAG.getValueType(InWidenVT);
1479 ISD::CvtCode CvtCode = cast<CvtRndSatSDNode>(N)->getCvtCode();
1481 unsigned InVTNumElts = InVT.getVectorNumElements();
1482 if (getTypeAction(InVT) == WidenVector) {
1483 InOp = GetWidenedVector(InOp);
1484 InVT = InOp.getValueType();
1485 InVTNumElts = InVT.getVectorNumElements();
1486 if (InVTNumElts == WidenNumElts)
1487 return DAG.getConvertRndSat(WidenVT, dl, InOp, DTyOp, STyOp, RndOp,
1491 if (TLI.isTypeLegal(InWidenVT)) {
1492 // Because the result and the input are different vector types, widening
1493 // the result could create a legal type but widening the input might make
1494 // it an illegal type that might lead to repeatedly splitting the input
1495 // and then widening it. To avoid this, we widen the input only if
1496 // it results in a legal type.
1497 if (WidenNumElts % InVTNumElts == 0) {
1498 // Widen the input and call convert on the widened input vector.
1499 unsigned NumConcat = WidenNumElts/InVTNumElts;
1500 SmallVector<SDValue, 16> Ops(NumConcat);
1502 SDValue UndefVal = DAG.getUNDEF(InVT);
1503 for (unsigned i = 1; i != NumConcat; ++i) {
1506 InOp = DAG.getNode(ISD::CONCAT_VECTORS, dl, InWidenVT, &Ops[0],NumConcat);
1507 return DAG.getConvertRndSat(WidenVT, dl, InOp, DTyOp, STyOp, RndOp,
1511 if (InVTNumElts % WidenNumElts == 0) {
1512 // Extract the input and convert the shorten input vector.
1513 InOp = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, InWidenVT, InOp,
1514 DAG.getIntPtrConstant(0));
1515 return DAG.getConvertRndSat(WidenVT, dl, InOp, DTyOp, STyOp, RndOp,
1520 // Otherwise unroll into some nasty scalar code and rebuild the vector.
1521 SmallVector<SDValue, 16> Ops(WidenNumElts);
1522 MVT EltVT = WidenVT.getVectorElementType();
1523 DTyOp = DAG.getValueType(EltVT);
1524 STyOp = DAG.getValueType(InEltVT);
1526 unsigned MinElts = std::min(InVTNumElts, WidenNumElts);
1528 for (i=0; i < MinElts; ++i) {
1529 SDValue ExtVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, InEltVT, InOp,
1530 DAG.getIntPtrConstant(i));
1531 Ops[i] = DAG.getConvertRndSat(WidenVT, dl, ExtVal, DTyOp, STyOp, RndOp,
1535 SDValue UndefVal = DAG.getUNDEF(EltVT);
1536 for (; i < WidenNumElts; ++i)
1539 return DAG.getNode(ISD::BUILD_VECTOR, dl, WidenVT, &Ops[0], WidenNumElts);
1542 SDValue DAGTypeLegalizer::WidenVecRes_EXTRACT_SUBVECTOR(SDNode *N) {
1543 MVT VT = N->getValueType(0);
1544 MVT WidenVT = TLI.getTypeToTransformTo(VT);
1545 unsigned WidenNumElts = WidenVT.getVectorNumElements();
1546 SDValue InOp = N->getOperand(0);
1547 SDValue Idx = N->getOperand(1);
1548 DebugLoc dl = N->getDebugLoc();
1550 if (getTypeAction(InOp.getValueType()) == WidenVector)
1551 InOp = GetWidenedVector(InOp);
1553 MVT InVT = InOp.getValueType();
1555 ConstantSDNode *CIdx = dyn_cast<ConstantSDNode>(Idx);
1557 unsigned IdxVal = CIdx->getZExtValue();
1558 // Check if we can just return the input vector after widening.
1559 if (IdxVal == 0 && InVT == WidenVT)
1562 // Check if we can extract from the vector.
1563 unsigned InNumElts = InVT.getVectorNumElements();
1564 if (IdxVal % WidenNumElts == 0 && IdxVal + WidenNumElts < InNumElts)
1565 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, WidenVT, InOp, Idx);
1568 // We could try widening the input to the right length but for now, extract
1569 // the original elements, fill the rest with undefs and build a vector.
1570 SmallVector<SDValue, 16> Ops(WidenNumElts);
1571 MVT EltVT = VT.getVectorElementType();
1572 MVT IdxVT = Idx.getValueType();
1573 unsigned NumElts = VT.getVectorNumElements();
1576 unsigned IdxVal = CIdx->getZExtValue();
1577 for (i=0; i < NumElts; ++i)
1578 Ops[i] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, InOp,
1579 DAG.getConstant(IdxVal+i, IdxVT));
1581 Ops[0] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, InOp, Idx);
1582 for (i=1; i < NumElts; ++i) {
1583 SDValue NewIdx = DAG.getNode(ISD::ADD, dl, Idx.getValueType(), Idx,
1584 DAG.getConstant(i, IdxVT));
1585 Ops[i] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, InOp, NewIdx);
1589 SDValue UndefVal = DAG.getUNDEF(EltVT);
1590 for (; i < WidenNumElts; ++i)
1592 return DAG.getNode(ISD::BUILD_VECTOR, dl, WidenVT, &Ops[0], WidenNumElts);
1595 SDValue DAGTypeLegalizer::WidenVecRes_INSERT_VECTOR_ELT(SDNode *N) {
1596 SDValue InOp = GetWidenedVector(N->getOperand(0));
1597 return DAG.getNode(ISD::INSERT_VECTOR_ELT, N->getDebugLoc(),
1598 InOp.getValueType(), InOp,
1599 N->getOperand(1), N->getOperand(2));
1602 SDValue DAGTypeLegalizer::WidenVecRes_LOAD(SDNode *N) {
1603 LoadSDNode *LD = cast<LoadSDNode>(N);
1604 MVT WidenVT = TLI.getTypeToTransformTo(LD->getValueType(0));
1605 MVT LdVT = LD->getMemoryVT();
1606 DebugLoc dl = N->getDebugLoc();
1607 assert(LdVT.isVector() && WidenVT.isVector());
1610 SDValue Chain = LD->getChain();
1611 SDValue BasePtr = LD->getBasePtr();
1612 int SVOffset = LD->getSrcValueOffset();
1613 unsigned Align = LD->getAlignment();
1614 bool isVolatile = LD->isVolatile();
1615 const Value *SV = LD->getSrcValue();
1616 ISD::LoadExtType ExtType = LD->getExtensionType();
1619 SmallVector<SDValue, 16> LdChain; // Chain for the series of load
1620 if (ExtType != ISD::NON_EXTLOAD) {
1621 // For extension loads, we can not play the tricks of chopping legal
1622 // vector types and bit cast it to the right type. Instead, we unroll
1623 // the load and build a vector.
1624 MVT EltVT = WidenVT.getVectorElementType();
1625 MVT LdEltVT = LdVT.getVectorElementType();
1626 unsigned NumElts = LdVT.getVectorNumElements();
1628 // Load each element and widen
1629 unsigned WidenNumElts = WidenVT.getVectorNumElements();
1630 SmallVector<SDValue, 16> Ops(WidenNumElts);
1631 unsigned Increment = LdEltVT.getSizeInBits() / 8;
1632 Ops[0] = DAG.getExtLoad(ExtType, dl, EltVT, Chain, BasePtr, SV, SVOffset,
1633 LdEltVT, isVolatile, Align);
1634 LdChain.push_back(Ops[0].getValue(1));
1635 unsigned i = 0, Offset = Increment;
1636 for (i=1; i < NumElts; ++i, Offset += Increment) {
1637 SDValue NewBasePtr = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(),
1638 BasePtr, DAG.getIntPtrConstant(Offset));
1639 Ops[i] = DAG.getExtLoad(ExtType, dl, EltVT, Chain, NewBasePtr, SV,
1640 SVOffset + Offset, LdEltVT, isVolatile, Align);
1641 LdChain.push_back(Ops[i].getValue(1));
1644 // Fill the rest with undefs
1645 SDValue UndefVal = DAG.getUNDEF(EltVT);
1646 for (; i != WidenNumElts; ++i)
1649 Result = DAG.getNode(ISD::BUILD_VECTOR, dl, WidenVT, &Ops[0], Ops.size());
1651 assert(LdVT.getVectorElementType() == WidenVT.getVectorElementType());
1652 unsigned int LdWidth = LdVT.getSizeInBits();
1653 Result = GenWidenVectorLoads(LdChain, Chain, BasePtr, SV, SVOffset,
1654 Align, isVolatile, LdWidth, WidenVT, dl);
1657 // If we generate a single load, we can use that for the chain. Otherwise,
1658 // build a factor node to remember the multiple loads are independent and
1661 if (LdChain.size() == 1)
1662 NewChain = LdChain[0];
1664 NewChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &LdChain[0],
1667 // Modified the chain - switch anything that used the old chain to use
1669 ReplaceValueWith(SDValue(N, 1), Chain);
1674 SDValue DAGTypeLegalizer::WidenVecRes_SCALAR_TO_VECTOR(SDNode *N) {
1675 MVT WidenVT = TLI.getTypeToTransformTo(N->getValueType(0));
1676 return DAG.getNode(ISD::SCALAR_TO_VECTOR, N->getDebugLoc(),
1677 WidenVT, N->getOperand(0));
1680 SDValue DAGTypeLegalizer::WidenVecRes_SELECT(SDNode *N) {
1681 MVT WidenVT = TLI.getTypeToTransformTo(N->getValueType(0));
1682 unsigned WidenNumElts = WidenVT.getVectorNumElements();
1684 SDValue Cond1 = N->getOperand(0);
1685 MVT CondVT = Cond1.getValueType();
1686 if (CondVT.isVector()) {
1687 MVT CondEltVT = CondVT.getVectorElementType();
1688 MVT CondWidenVT = MVT::getVectorVT(CondEltVT, WidenNumElts);
1689 if (getTypeAction(CondVT) == WidenVector)
1690 Cond1 = GetWidenedVector(Cond1);
1692 if (Cond1.getValueType() != CondWidenVT)
1693 Cond1 = ModifyToType(Cond1, CondWidenVT);
1696 SDValue InOp1 = GetWidenedVector(N->getOperand(1));
1697 SDValue InOp2 = GetWidenedVector(N->getOperand(2));
1698 assert(InOp1.getValueType() == WidenVT && InOp2.getValueType() == WidenVT);
1699 return DAG.getNode(ISD::SELECT, N->getDebugLoc(),
1700 WidenVT, Cond1, InOp1, InOp2);
1703 SDValue DAGTypeLegalizer::WidenVecRes_SELECT_CC(SDNode *N) {
1704 SDValue InOp1 = GetWidenedVector(N->getOperand(2));
1705 SDValue InOp2 = GetWidenedVector(N->getOperand(3));
1706 return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(),
1707 InOp1.getValueType(), N->getOperand(0),
1708 N->getOperand(1), InOp1, InOp2, N->getOperand(4));
1711 SDValue DAGTypeLegalizer::WidenVecRes_UNDEF(SDNode *N) {
1712 MVT WidenVT = TLI.getTypeToTransformTo(N->getValueType(0));
1713 return DAG.getUNDEF(WidenVT);
1716 SDValue DAGTypeLegalizer::WidenVecRes_VECTOR_SHUFFLE(ShuffleVectorSDNode *N) {
1717 MVT VT = N->getValueType(0);
1718 DebugLoc dl = N->getDebugLoc();
1720 MVT WidenVT = TLI.getTypeToTransformTo(VT);
1721 unsigned NumElts = VT.getVectorNumElements();
1722 unsigned WidenNumElts = WidenVT.getVectorNumElements();
1724 SDValue InOp1 = GetWidenedVector(N->getOperand(0));
1725 SDValue InOp2 = GetWidenedVector(N->getOperand(1));
1727 // Adjust mask based on new input vector length.
1728 SmallVector<int, 16> NewMask;
1729 for (unsigned i = 0; i != NumElts; ++i) {
1730 int Idx = N->getMaskElt(i);
1731 if (Idx < (int)NumElts)
1732 NewMask.push_back(Idx);
1734 NewMask.push_back(Idx - NumElts + WidenNumElts);
1736 for (unsigned i = NumElts; i != WidenNumElts; ++i)
1737 NewMask.push_back(-1);
1738 return DAG.getVectorShuffle(WidenVT, dl, InOp1, InOp2, &NewMask[0]);
1741 SDValue DAGTypeLegalizer::WidenVecRes_VSETCC(SDNode *N) {
1742 MVT WidenVT = TLI.getTypeToTransformTo(N->getValueType(0));
1743 unsigned WidenNumElts = WidenVT.getVectorNumElements();
1745 SDValue InOp1 = N->getOperand(0);
1746 MVT InVT = InOp1.getValueType();
1747 assert(InVT.isVector() && "can not widen non vector type");
1748 MVT WidenInVT = MVT::getVectorVT(InVT.getVectorElementType(), WidenNumElts);
1749 InOp1 = GetWidenedVector(InOp1);
1750 SDValue InOp2 = GetWidenedVector(N->getOperand(1));
1752 // Assume that the input and output will be widen appropriately. If not,
1753 // we will have to unroll it at some point.
1754 assert(InOp1.getValueType() == WidenInVT &&
1755 InOp2.getValueType() == WidenInVT &&
1756 "Input not widened to expected type!");
1757 return DAG.getNode(ISD::VSETCC, N->getDebugLoc(),
1758 WidenVT, InOp1, InOp2, N->getOperand(2));
1762 //===----------------------------------------------------------------------===//
1763 // Widen Vector Operand
1764 //===----------------------------------------------------------------------===//
1765 bool DAGTypeLegalizer::WidenVectorOperand(SDNode *N, unsigned ResNo) {
1766 DEBUG(cerr << "Widen node operand " << ResNo << ": "; N->dump(&DAG);
1768 SDValue Res = SDValue();
1770 switch (N->getOpcode()) {
1773 cerr << "WidenVectorOperand op #" << ResNo << ": ";
1774 N->dump(&DAG); cerr << "\n";
1776 LLVM_UNREACHABLE("Do not know how to widen this operator's operand!");
1778 case ISD::BIT_CONVERT: Res = WidenVecOp_BIT_CONVERT(N); break;
1779 case ISD::CONCAT_VECTORS: Res = WidenVecOp_CONCAT_VECTORS(N); break;
1780 case ISD::EXTRACT_VECTOR_ELT: Res = WidenVecOp_EXTRACT_VECTOR_ELT(N); break;
1781 case ISD::STORE: Res = WidenVecOp_STORE(N); break;
1784 case ISD::FP_TO_SINT:
1785 case ISD::FP_TO_UINT:
1786 case ISD::SINT_TO_FP:
1787 case ISD::UINT_TO_FP:
1789 case ISD::SIGN_EXTEND:
1790 case ISD::ZERO_EXTEND:
1791 case ISD::ANY_EXTEND:
1792 Res = WidenVecOp_Convert(N);
1796 // If Res is null, the sub-method took care of registering the result.
1797 if (!Res.getNode()) return false;
1799 // If the result is N, the sub-method updated N in place. Tell the legalizer
1801 if (Res.getNode() == N)
1805 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 &&
1806 "Invalid operand expansion");
1808 ReplaceValueWith(SDValue(N, 0), Res);
1812 SDValue DAGTypeLegalizer::WidenVecOp_Convert(SDNode *N) {
1813 // Since the result is legal and the input is illegal, it is unlikely
1814 // that we can fix the input to a legal type so unroll the convert
1815 // into some scalar code and create a nasty build vector.
1816 MVT VT = N->getValueType(0);
1817 MVT EltVT = VT.getVectorElementType();
1818 DebugLoc dl = N->getDebugLoc();
1819 unsigned NumElts = VT.getVectorNumElements();
1820 SDValue InOp = N->getOperand(0);
1821 if (getTypeAction(InOp.getValueType()) == WidenVector)
1822 InOp = GetWidenedVector(InOp);
1823 MVT InVT = InOp.getValueType();
1824 MVT InEltVT = InVT.getVectorElementType();
1826 unsigned Opcode = N->getOpcode();
1827 SmallVector<SDValue, 16> Ops(NumElts);
1828 for (unsigned i=0; i < NumElts; ++i)
1829 Ops[i] = DAG.getNode(Opcode, dl, EltVT,
1830 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, InEltVT, InOp,
1831 DAG.getIntPtrConstant(i)));
1833 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &Ops[0], NumElts);
1836 SDValue DAGTypeLegalizer::WidenVecOp_BIT_CONVERT(SDNode *N) {
1837 MVT VT = N->getValueType(0);
1838 SDValue InOp = GetWidenedVector(N->getOperand(0));
1839 MVT InWidenVT = InOp.getValueType();
1840 DebugLoc dl = N->getDebugLoc();
1842 // Check if we can convert between two legal vector types and extract.
1843 unsigned InWidenSize = InWidenVT.getSizeInBits();
1844 unsigned Size = VT.getSizeInBits();
1845 if (InWidenSize % Size == 0 && !VT.isVector()) {
1846 unsigned NewNumElts = InWidenSize / Size;
1847 MVT NewVT = MVT::getVectorVT(VT, NewNumElts);
1848 if (TLI.isTypeLegal(NewVT)) {
1849 SDValue BitOp = DAG.getNode(ISD::BIT_CONVERT, dl, NewVT, InOp);
1850 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, BitOp,
1851 DAG.getIntPtrConstant(0));
1855 return CreateStackStoreLoad(InOp, VT);
1858 SDValue DAGTypeLegalizer::WidenVecOp_CONCAT_VECTORS(SDNode *N) {
1859 // If the input vector is not legal, it is likely that we will not find a
1860 // legal vector of the same size. Replace the concatenate vector with a
1861 // nasty build vector.
1862 MVT VT = N->getValueType(0);
1863 MVT EltVT = VT.getVectorElementType();
1864 DebugLoc dl = N->getDebugLoc();
1865 unsigned NumElts = VT.getVectorNumElements();
1866 SmallVector<SDValue, 16> Ops(NumElts);
1868 MVT InVT = N->getOperand(0).getValueType();
1869 unsigned NumInElts = InVT.getVectorNumElements();
1872 unsigned NumOperands = N->getNumOperands();
1873 for (unsigned i=0; i < NumOperands; ++i) {
1874 SDValue InOp = N->getOperand(i);
1875 if (getTypeAction(InOp.getValueType()) == WidenVector)
1876 InOp = GetWidenedVector(InOp);
1877 for (unsigned j=0; j < NumInElts; ++j)
1878 Ops[Idx++] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, InOp,
1879 DAG.getIntPtrConstant(j));
1881 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &Ops[0], NumElts);
1884 SDValue DAGTypeLegalizer::WidenVecOp_EXTRACT_VECTOR_ELT(SDNode *N) {
1885 SDValue InOp = GetWidenedVector(N->getOperand(0));
1886 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, N->getDebugLoc(),
1887 N->getValueType(0), InOp, N->getOperand(1));
1890 SDValue DAGTypeLegalizer::WidenVecOp_STORE(SDNode *N) {
1891 // We have to widen the value but we want only to store the original
1893 StoreSDNode *ST = cast<StoreSDNode>(N);
1894 SDValue Chain = ST->getChain();
1895 SDValue BasePtr = ST->getBasePtr();
1896 const Value *SV = ST->getSrcValue();
1897 int SVOffset = ST->getSrcValueOffset();
1898 unsigned Align = ST->getAlignment();
1899 bool isVolatile = ST->isVolatile();
1900 SDValue ValOp = GetWidenedVector(ST->getValue());
1901 DebugLoc dl = N->getDebugLoc();
1903 MVT StVT = ST->getMemoryVT();
1904 MVT ValVT = ValOp.getValueType();
1905 // It must be true that we the widen vector type is bigger than where
1906 // we need to store.
1907 assert(StVT.isVector() && ValOp.getValueType().isVector());
1908 assert(StVT.bitsLT(ValOp.getValueType()));
1910 SmallVector<SDValue, 16> StChain;
1911 if (ST->isTruncatingStore()) {
1912 // For truncating stores, we can not play the tricks of chopping legal
1913 // vector types and bit cast it to the right type. Instead, we unroll
1915 MVT StEltVT = StVT.getVectorElementType();
1916 MVT ValEltVT = ValVT.getVectorElementType();
1917 unsigned Increment = ValEltVT.getSizeInBits() / 8;
1918 unsigned NumElts = StVT.getVectorNumElements();
1919 SDValue EOp = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ValEltVT, ValOp,
1920 DAG.getIntPtrConstant(0));
1921 StChain.push_back(DAG.getTruncStore(Chain, dl, EOp, BasePtr, SV,
1923 isVolatile, Align));
1924 unsigned Offset = Increment;
1925 for (unsigned i=1; i < NumElts; ++i, Offset += Increment) {
1926 SDValue NewBasePtr = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(),
1927 BasePtr, DAG.getIntPtrConstant(Offset));
1928 SDValue EOp = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ValEltVT, ValOp,
1929 DAG.getIntPtrConstant(0));
1930 StChain.push_back(DAG.getTruncStore(Chain, dl, EOp, NewBasePtr, SV,
1931 SVOffset + Offset, StEltVT,
1932 isVolatile, MinAlign(Align, Offset)));
1936 assert(StVT.getVectorElementType() == ValVT.getVectorElementType());
1938 GenWidenVectorStores(StChain, Chain, BasePtr, SV, SVOffset,
1939 Align, isVolatile, ValOp, StVT.getSizeInBits(), dl);
1941 if (StChain.size() == 1)
1944 return DAG.getNode(ISD::TokenFactor, dl,
1945 MVT::Other,&StChain[0],StChain.size());
1948 //===----------------------------------------------------------------------===//
1949 // Vector Widening Utilities
1950 //===----------------------------------------------------------------------===//
1953 // Utility function to find a vector type and its associated element
1954 // type from a preferred width and whose vector type must be the same size
1956 // TLI: Target lowering used to determine legal types.
1957 // Width: Preferred width to store.
1958 // VecVT: Vector value type whose size we must match.
1959 // Returns NewVecVT and NewEltVT - the vector type and its associated
1961 static void FindAssocWidenVecType(const TargetLowering &TLI, unsigned Width,
1963 MVT& NewEltVT, MVT& NewVecVT) {
1964 unsigned EltWidth = Width + 1;
1965 if (TLI.isTypeLegal(VecVT)) {
1966 // We start with the preferred with, making it a power of 2 and find a
1967 // legal vector type of that width. If not, we reduce it by another of 2.
1968 // For incoming type is legal, this process will end as a vector of the
1969 // smallest loadable type should always be legal.
1971 assert(EltWidth > 0);
1972 EltWidth = 1 << Log2_32(EltWidth - 1);
1973 NewEltVT = MVT::getIntegerVT(EltWidth);
1974 unsigned NumElts = VecVT.getSizeInBits() / EltWidth;
1975 NewVecVT = MVT::getVectorVT(NewEltVT, NumElts);
1976 } while (!TLI.isTypeLegal(NewVecVT) ||
1977 VecVT.getSizeInBits() != NewVecVT.getSizeInBits());
1979 // The incoming vector type is illegal and is the result of widening
1980 // a vector to a power of 2. In this case, we will use the preferred
1981 // with as long as it is a multiple of the incoming vector length.
1982 // The legalization process will eventually make this into a legal type
1983 // and remove the illegal bit converts (which would turn to stack converts
1984 // if they are allow to exist).
1986 assert(EltWidth > 0);
1987 EltWidth = 1 << Log2_32(EltWidth - 1);
1988 NewEltVT = MVT::getIntegerVT(EltWidth);
1989 unsigned NumElts = VecVT.getSizeInBits() / EltWidth;
1990 NewVecVT = MVT::getVectorVT(NewEltVT, NumElts);
1991 } while (!TLI.isTypeLegal(NewEltVT) ||
1992 VecVT.getSizeInBits() != NewVecVT.getSizeInBits());
1996 SDValue DAGTypeLegalizer::GenWidenVectorLoads(SmallVector<SDValue, 16>& LdChain,
2006 // The strategy assumes that we can efficiently load powers of two widths.
2007 // The routines chops the vector into the largest power of 2 load and
2008 // can be inserted into a legal vector and then cast the result into the
2009 // vector type we want. This avoids unnecessary stack converts.
2011 // TODO: If the Ldwidth is legal, alignment is the same as the LdWidth, and
2012 // the load is nonvolatile, we an use a wider load for the value.
2014 // Find the vector type that can load from.
2015 MVT NewEltVT, NewVecVT;
2016 unsigned NewEltVTWidth;
2017 FindAssocWidenVecType(TLI, LdWidth, ResType, NewEltVT, NewVecVT);
2018 NewEltVTWidth = NewEltVT.getSizeInBits();
2020 SDValue LdOp = DAG.getLoad(NewEltVT, dl, Chain, BasePtr, SV, SVOffset,
2021 isVolatile, Alignment);
2022 SDValue VecOp = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, NewVecVT, LdOp);
2023 LdChain.push_back(LdOp.getValue(1));
2025 // Check if we can load the element with one instruction
2026 if (LdWidth == NewEltVTWidth) {
2027 return DAG.getNode(ISD::BIT_CONVERT, dl, ResType, VecOp);
2031 LdWidth -= NewEltVTWidth;
2032 unsigned Offset = 0;
2034 while (LdWidth > 0) {
2035 unsigned Increment = NewEltVTWidth / 8;
2036 Offset += Increment;
2037 BasePtr = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(), BasePtr,
2038 DAG.getIntPtrConstant(Increment));
2040 if (LdWidth < NewEltVTWidth) {
2041 // Our current type we are using is too large, use a smaller size by
2042 // using a smaller power of 2
2043 unsigned oNewEltVTWidth = NewEltVTWidth;
2044 FindAssocWidenVecType(TLI, LdWidth, ResType, NewEltVT, NewVecVT);
2045 NewEltVTWidth = NewEltVT.getSizeInBits();
2046 // Readjust position and vector position based on new load type
2047 Idx = Idx * (oNewEltVTWidth/NewEltVTWidth);
2048 VecOp = DAG.getNode(ISD::BIT_CONVERT, dl, NewVecVT, VecOp);
2051 SDValue LdOp = DAG.getLoad(NewEltVT, dl, Chain, BasePtr, SV,
2052 SVOffset+Offset, isVolatile,
2053 MinAlign(Alignment, Offset));
2054 LdChain.push_back(LdOp.getValue(1));
2055 VecOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, NewVecVT, VecOp, LdOp,
2056 DAG.getIntPtrConstant(Idx++));
2058 LdWidth -= NewEltVTWidth;
2061 return DAG.getNode(ISD::BIT_CONVERT, dl, ResType, VecOp);
2064 void DAGTypeLegalizer::GenWidenVectorStores(SmallVector<SDValue, 16>& StChain,
2074 // Breaks the stores into a series of power of 2 width stores. For any
2075 // width, we convert the vector to the vector of element size that we
2076 // want to store. This avoids requiring a stack convert.
2078 // Find a width of the element type we can store with
2079 MVT WidenVT = ValOp.getValueType();
2080 MVT NewEltVT, NewVecVT;
2082 FindAssocWidenVecType(TLI, StWidth, WidenVT, NewEltVT, NewVecVT);
2083 unsigned NewEltVTWidth = NewEltVT.getSizeInBits();
2085 SDValue VecOp = DAG.getNode(ISD::BIT_CONVERT, dl, NewVecVT, ValOp);
2086 SDValue EOp = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, NewEltVT, VecOp,
2087 DAG.getIntPtrConstant(0));
2088 SDValue StOp = DAG.getStore(Chain, dl, EOp, BasePtr, SV, SVOffset,
2089 isVolatile, Alignment);
2090 StChain.push_back(StOp);
2092 // Check if we are done
2093 if (StWidth == NewEltVTWidth) {
2098 StWidth -= NewEltVTWidth;
2099 unsigned Offset = 0;
2101 while (StWidth > 0) {
2102 unsigned Increment = NewEltVTWidth / 8;
2103 Offset += Increment;
2104 BasePtr = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(), BasePtr,
2105 DAG.getIntPtrConstant(Increment));
2107 if (StWidth < NewEltVTWidth) {
2108 // Our current type we are using is too large, use a smaller size by
2109 // using a smaller power of 2
2110 unsigned oNewEltVTWidth = NewEltVTWidth;
2111 FindAssocWidenVecType(TLI, StWidth, WidenVT, NewEltVT, NewVecVT);
2112 NewEltVTWidth = NewEltVT.getSizeInBits();
2113 // Readjust position and vector position based on new load type
2114 Idx = Idx * (oNewEltVTWidth/NewEltVTWidth);
2115 VecOp = DAG.getNode(ISD::BIT_CONVERT, dl, NewVecVT, VecOp);
2118 EOp = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, NewEltVT, VecOp,
2119 DAG.getIntPtrConstant(Idx++));
2120 StChain.push_back(DAG.getStore(Chain, dl, EOp, BasePtr, SV,
2121 SVOffset + Offset, isVolatile,
2122 MinAlign(Alignment, Offset)));
2123 StWidth -= NewEltVTWidth;
2127 /// Modifies a vector input (widen or narrows) to a vector of NVT. The
2128 /// input vector must have the same element type as NVT.
2129 SDValue DAGTypeLegalizer::ModifyToType(SDValue InOp, MVT NVT) {
2130 // Note that InOp might have been widened so it might already have
2131 // the right width or it might need be narrowed.
2132 MVT InVT = InOp.getValueType();
2133 assert(InVT.getVectorElementType() == NVT.getVectorElementType() &&
2134 "input and widen element type must match");
2135 DebugLoc dl = InOp.getDebugLoc();
2137 // Check if InOp already has the right width.
2141 unsigned InNumElts = InVT.getVectorNumElements();
2142 unsigned WidenNumElts = NVT.getVectorNumElements();
2143 if (WidenNumElts > InNumElts && WidenNumElts % InNumElts == 0) {
2144 unsigned NumConcat = WidenNumElts / InNumElts;
2145 SmallVector<SDValue, 16> Ops(NumConcat);
2146 SDValue UndefVal = DAG.getUNDEF(InVT);
2148 for (unsigned i = 1; i != NumConcat; ++i)
2151 return DAG.getNode(ISD::CONCAT_VECTORS, dl, NVT, &Ops[0], NumConcat);
2154 if (WidenNumElts < InNumElts && InNumElts % WidenNumElts)
2155 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, NVT, InOp,
2156 DAG.getIntPtrConstant(0));
2158 // Fall back to extract and build.
2159 SmallVector<SDValue, 16> Ops(WidenNumElts);
2160 MVT EltVT = NVT.getVectorElementType();
2161 unsigned MinNumElts = std::min(WidenNumElts, InNumElts);
2163 for (Idx = 0; Idx < MinNumElts; ++Idx)
2164 Ops[Idx] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, InOp,
2165 DAG.getIntPtrConstant(Idx));
2167 SDValue UndefVal = DAG.getUNDEF(EltVT);
2168 for ( ; Idx < WidenNumElts; ++Idx)
2169 Ops[Idx] = UndefVal;
2170 return DAG.getNode(ISD::BUILD_VECTOR, dl, NVT, &Ops[0], WidenNumElts);