1 //===------- LegalizeVectorTypes.cpp - Legalization of vector types -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file performs vector type splitting and scalarization for LegalizeTypes.
11 // Scalarization is the act of changing a computation in an illegal one-element
12 // vector type to be a computation in its scalar element type. For example,
13 // implementing <1 x f32> arithmetic in a scalar f32 register. This is needed
14 // as a base case when scalarizing vector arithmetic like <4 x f32>, which
15 // eventually decomposes to scalars if the target doesn't support v4f32 or v2f32
17 // Splitting is the act of changing a computation in an invalid vector type to
18 // be a computation in two vectors of half the size. For example, implementing
19 // <128 x f32> operations in terms of two <64 x f32> operations.
21 //===----------------------------------------------------------------------===//
23 #include "LegalizeTypes.h"
24 #include "llvm/CodeGen/PseudoSourceValue.h"
25 #include "llvm/Target/TargetData.h"
26 #include "llvm/Support/ErrorHandling.h"
27 #include "llvm/Support/raw_ostream.h"
30 //===----------------------------------------------------------------------===//
31 // Result Vector Scalarization: <1 x ty> -> ty.
32 //===----------------------------------------------------------------------===//
34 void DAGTypeLegalizer::ScalarizeVectorResult(SDNode *N, unsigned ResNo) {
35 DEBUG(dbgs() << "Scalarize node result " << ResNo << ": ";
38 SDValue R = SDValue();
40 switch (N->getOpcode()) {
43 dbgs() << "ScalarizeVectorResult #" << ResNo << ": ";
47 llvm_unreachable("Do not know how to scalarize the result of this operator!");
49 case ISD::BITCAST: R = ScalarizeVecRes_BITCAST(N); break;
50 case ISD::BUILD_VECTOR: R = N->getOperand(0); break;
51 case ISD::CONVERT_RNDSAT: R = ScalarizeVecRes_CONVERT_RNDSAT(N); break;
52 case ISD::EXTRACT_SUBVECTOR: R = ScalarizeVecRes_EXTRACT_SUBVECTOR(N); break;
53 case ISD::FP_ROUND: R = ScalarizeVecRes_FP_ROUND(N); break;
54 case ISD::FP_ROUND_INREG: R = ScalarizeVecRes_InregOp(N); break;
55 case ISD::FPOWI: R = ScalarizeVecRes_FPOWI(N); break;
56 case ISD::INSERT_VECTOR_ELT: R = ScalarizeVecRes_INSERT_VECTOR_ELT(N); break;
57 case ISD::LOAD: R = ScalarizeVecRes_LOAD(cast<LoadSDNode>(N));break;
58 case ISD::SCALAR_TO_VECTOR: R = ScalarizeVecRes_SCALAR_TO_VECTOR(N); break;
59 case ISD::SIGN_EXTEND_INREG: R = ScalarizeVecRes_InregOp(N); break;
60 case ISD::SELECT: R = ScalarizeVecRes_SELECT(N); break;
61 case ISD::SELECT_CC: R = ScalarizeVecRes_SELECT_CC(N); break;
62 case ISD::SETCC: R = ScalarizeVecRes_SETCC(N); break;
63 case ISD::UNDEF: R = ScalarizeVecRes_UNDEF(N); break;
64 case ISD::VECTOR_SHUFFLE: R = ScalarizeVecRes_VECTOR_SHUFFLE(N); break;
65 case ISD::VSETCC: R = ScalarizeVecRes_VSETCC(N); break;
89 case ISD::SIGN_EXTEND:
93 case ISD::ZERO_EXTEND:
94 R = ScalarizeVecRes_UnaryOp(N);
116 R = ScalarizeVecRes_BinOp(N);
120 // If R is null, the sub-method took care of registering the result.
122 SetScalarizedVector(SDValue(N, ResNo), R);
125 SDValue DAGTypeLegalizer::ScalarizeVecRes_BinOp(SDNode *N) {
126 SDValue LHS = GetScalarizedVector(N->getOperand(0));
127 SDValue RHS = GetScalarizedVector(N->getOperand(1));
128 return DAG.getNode(N->getOpcode(), N->getDebugLoc(),
129 LHS.getValueType(), LHS, RHS);
132 SDValue DAGTypeLegalizer::ScalarizeVecRes_BITCAST(SDNode *N) {
133 EVT NewVT = N->getValueType(0).getVectorElementType();
134 return DAG.getNode(ISD::BITCAST, N->getDebugLoc(),
135 NewVT, N->getOperand(0));
138 SDValue DAGTypeLegalizer::ScalarizeVecRes_CONVERT_RNDSAT(SDNode *N) {
139 EVT NewVT = N->getValueType(0).getVectorElementType();
140 SDValue Op0 = GetScalarizedVector(N->getOperand(0));
141 return DAG.getConvertRndSat(NewVT, N->getDebugLoc(),
142 Op0, DAG.getValueType(NewVT),
143 DAG.getValueType(Op0.getValueType()),
146 cast<CvtRndSatSDNode>(N)->getCvtCode());
149 SDValue DAGTypeLegalizer::ScalarizeVecRes_EXTRACT_SUBVECTOR(SDNode *N) {
150 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, N->getDebugLoc(),
151 N->getValueType(0).getVectorElementType(),
152 N->getOperand(0), N->getOperand(1));
155 SDValue DAGTypeLegalizer::ScalarizeVecRes_FP_ROUND(SDNode *N) {
156 EVT NewVT = N->getValueType(0).getVectorElementType();
157 SDValue Op = GetScalarizedVector(N->getOperand(0));
158 return DAG.getNode(ISD::FP_ROUND, N->getDebugLoc(),
159 NewVT, Op, N->getOperand(1));
162 SDValue DAGTypeLegalizer::ScalarizeVecRes_FPOWI(SDNode *N) {
163 SDValue Op = GetScalarizedVector(N->getOperand(0));
164 return DAG.getNode(ISD::FPOWI, N->getDebugLoc(),
165 Op.getValueType(), Op, N->getOperand(1));
168 SDValue DAGTypeLegalizer::ScalarizeVecRes_INSERT_VECTOR_ELT(SDNode *N) {
169 // The value to insert may have a wider type than the vector element type,
170 // so be sure to truncate it to the element type if necessary.
171 SDValue Op = N->getOperand(1);
172 EVT EltVT = N->getValueType(0).getVectorElementType();
173 if (Op.getValueType() != EltVT)
174 // FIXME: Can this happen for floating point types?
175 Op = DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), EltVT, Op);
179 SDValue DAGTypeLegalizer::ScalarizeVecRes_LOAD(LoadSDNode *N) {
180 assert(N->isUnindexed() && "Indexed vector load?");
182 SDValue Result = DAG.getLoad(ISD::UNINDEXED,
183 N->getExtensionType(),
184 N->getValueType(0).getVectorElementType(),
186 N->getChain(), N->getBasePtr(),
187 DAG.getUNDEF(N->getBasePtr().getValueType()),
189 N->getMemoryVT().getVectorElementType(),
190 N->isVolatile(), N->isNonTemporal(),
191 N->getOriginalAlignment());
193 // Legalized the chain result - switch anything that used the old chain to
195 ReplaceValueWith(SDValue(N, 1), Result.getValue(1));
199 SDValue DAGTypeLegalizer::ScalarizeVecRes_UnaryOp(SDNode *N) {
200 // Get the dest type - it doesn't always match the input type, e.g. int_to_fp.
201 EVT DestVT = N->getValueType(0).getVectorElementType();
202 SDValue Op = GetScalarizedVector(N->getOperand(0));
203 return DAG.getNode(N->getOpcode(), N->getDebugLoc(), DestVT, Op);
206 SDValue DAGTypeLegalizer::ScalarizeVecRes_InregOp(SDNode *N) {
207 EVT EltVT = N->getValueType(0).getVectorElementType();
208 EVT ExtVT = cast<VTSDNode>(N->getOperand(1))->getVT().getVectorElementType();
209 SDValue LHS = GetScalarizedVector(N->getOperand(0));
210 return DAG.getNode(N->getOpcode(), N->getDebugLoc(), EltVT,
211 LHS, DAG.getValueType(ExtVT));
214 SDValue DAGTypeLegalizer::ScalarizeVecRes_SCALAR_TO_VECTOR(SDNode *N) {
215 // If the operand is wider than the vector element type then it is implicitly
216 // truncated. Make that explicit here.
217 EVT EltVT = N->getValueType(0).getVectorElementType();
218 SDValue InOp = N->getOperand(0);
219 if (InOp.getValueType() != EltVT)
220 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), EltVT, InOp);
224 SDValue DAGTypeLegalizer::ScalarizeVecRes_SELECT(SDNode *N) {
225 SDValue LHS = GetScalarizedVector(N->getOperand(1));
226 return DAG.getNode(ISD::SELECT, N->getDebugLoc(),
227 LHS.getValueType(), N->getOperand(0), LHS,
228 GetScalarizedVector(N->getOperand(2)));
231 SDValue DAGTypeLegalizer::ScalarizeVecRes_SELECT_CC(SDNode *N) {
232 SDValue LHS = GetScalarizedVector(N->getOperand(2));
233 return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(), LHS.getValueType(),
234 N->getOperand(0), N->getOperand(1),
235 LHS, GetScalarizedVector(N->getOperand(3)),
239 SDValue DAGTypeLegalizer::ScalarizeVecRes_SETCC(SDNode *N) {
240 SDValue LHS = GetScalarizedVector(N->getOperand(0));
241 SDValue RHS = GetScalarizedVector(N->getOperand(1));
242 DebugLoc DL = N->getDebugLoc();
244 // Turn it into a scalar SETCC.
245 return DAG.getNode(ISD::SETCC, DL, MVT::i1, LHS, RHS, N->getOperand(2));
248 SDValue DAGTypeLegalizer::ScalarizeVecRes_UNDEF(SDNode *N) {
249 return DAG.getUNDEF(N->getValueType(0).getVectorElementType());
252 SDValue DAGTypeLegalizer::ScalarizeVecRes_VECTOR_SHUFFLE(SDNode *N) {
253 // Figure out if the scalar is the LHS or RHS and return it.
254 SDValue Arg = N->getOperand(2).getOperand(0);
255 if (Arg.getOpcode() == ISD::UNDEF)
256 return DAG.getUNDEF(N->getValueType(0).getVectorElementType());
257 unsigned Op = !cast<ConstantSDNode>(Arg)->isNullValue();
258 return GetScalarizedVector(N->getOperand(Op));
261 SDValue DAGTypeLegalizer::ScalarizeVecRes_VSETCC(SDNode *N) {
262 SDValue LHS = GetScalarizedVector(N->getOperand(0));
263 SDValue RHS = GetScalarizedVector(N->getOperand(1));
264 EVT NVT = N->getValueType(0).getVectorElementType();
265 EVT SVT = TLI.getSetCCResultType(LHS.getValueType());
266 DebugLoc DL = N->getDebugLoc();
268 // Turn it into a scalar SETCC.
269 SDValue Res = DAG.getNode(ISD::SETCC, DL, SVT, LHS, RHS, N->getOperand(2));
271 // VSETCC always returns a sign-extended value, while SETCC may not. The
272 // SETCC result type may not match the vector element type. Correct these.
273 if (NVT.bitsLE(SVT)) {
274 // The SETCC result type is bigger than the vector element type.
275 // Ensure the SETCC result is sign-extended.
276 if (TLI.getBooleanContents() !=
277 TargetLowering::ZeroOrNegativeOneBooleanContent)
278 Res = DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, SVT, Res,
279 DAG.getValueType(MVT::i1));
280 // Truncate to the final type.
281 return DAG.getNode(ISD::TRUNCATE, DL, NVT, Res);
284 // The SETCC result type is smaller than the vector element type.
285 // If the SetCC result is not sign-extended, chop it down to MVT::i1.
286 if (TLI.getBooleanContents() !=
287 TargetLowering::ZeroOrNegativeOneBooleanContent)
288 Res = DAG.getNode(ISD::TRUNCATE, DL, MVT::i1, Res);
289 // Sign extend to the final type.
290 return DAG.getNode(ISD::SIGN_EXTEND, DL, NVT, Res);
294 //===----------------------------------------------------------------------===//
295 // Operand Vector Scalarization <1 x ty> -> ty.
296 //===----------------------------------------------------------------------===//
298 bool DAGTypeLegalizer::ScalarizeVectorOperand(SDNode *N, unsigned OpNo) {
299 DEBUG(dbgs() << "Scalarize node operand " << OpNo << ": ";
302 SDValue Res = SDValue();
304 if (Res.getNode() == 0) {
305 switch (N->getOpcode()) {
308 dbgs() << "ScalarizeVectorOperand Op #" << OpNo << ": ";
312 llvm_unreachable("Do not know how to scalarize this operator's operand!");
314 Res = ScalarizeVecOp_BITCAST(N);
316 case ISD::CONCAT_VECTORS:
317 Res = ScalarizeVecOp_CONCAT_VECTORS(N);
319 case ISD::EXTRACT_VECTOR_ELT:
320 Res = ScalarizeVecOp_EXTRACT_VECTOR_ELT(N);
323 Res = ScalarizeVecOp_STORE(cast<StoreSDNode>(N), OpNo);
328 // If the result is null, the sub-method took care of registering results etc.
329 if (!Res.getNode()) return false;
331 // If the result is N, the sub-method updated N in place. Tell the legalizer
333 if (Res.getNode() == N)
336 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 &&
337 "Invalid operand expansion");
339 ReplaceValueWith(SDValue(N, 0), Res);
343 /// ScalarizeVecOp_BITCAST - If the value to convert is a vector that needs
344 /// to be scalarized, it must be <1 x ty>. Convert the element instead.
345 SDValue DAGTypeLegalizer::ScalarizeVecOp_BITCAST(SDNode *N) {
346 SDValue Elt = GetScalarizedVector(N->getOperand(0));
347 return DAG.getNode(ISD::BITCAST, N->getDebugLoc(),
348 N->getValueType(0), Elt);
351 /// ScalarizeVecOp_CONCAT_VECTORS - The vectors to concatenate have length one -
352 /// use a BUILD_VECTOR instead.
353 SDValue DAGTypeLegalizer::ScalarizeVecOp_CONCAT_VECTORS(SDNode *N) {
354 SmallVector<SDValue, 8> Ops(N->getNumOperands());
355 for (unsigned i = 0, e = N->getNumOperands(); i < e; ++i)
356 Ops[i] = GetScalarizedVector(N->getOperand(i));
357 return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), N->getValueType(0),
358 &Ops[0], Ops.size());
361 /// ScalarizeVecOp_EXTRACT_VECTOR_ELT - If the input is a vector that needs to
362 /// be scalarized, it must be <1 x ty>, so just return the element, ignoring the
364 SDValue DAGTypeLegalizer::ScalarizeVecOp_EXTRACT_VECTOR_ELT(SDNode *N) {
365 SDValue Res = GetScalarizedVector(N->getOperand(0));
366 if (Res.getValueType() != N->getValueType(0))
367 Res = DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), N->getValueType(0),
372 /// ScalarizeVecOp_STORE - If the value to store is a vector that needs to be
373 /// scalarized, it must be <1 x ty>. Just store the element.
374 SDValue DAGTypeLegalizer::ScalarizeVecOp_STORE(StoreSDNode *N, unsigned OpNo){
375 assert(N->isUnindexed() && "Indexed store of one-element vector?");
376 assert(OpNo == 1 && "Do not know how to scalarize this operand!");
377 DebugLoc dl = N->getDebugLoc();
379 if (N->isTruncatingStore())
380 return DAG.getTruncStore(N->getChain(), dl,
381 GetScalarizedVector(N->getOperand(1)),
382 N->getBasePtr(), N->getPointerInfo(),
383 N->getMemoryVT().getVectorElementType(),
384 N->isVolatile(), N->isNonTemporal(),
387 return DAG.getStore(N->getChain(), dl, GetScalarizedVector(N->getOperand(1)),
388 N->getBasePtr(), N->getPointerInfo(),
389 N->isVolatile(), N->isNonTemporal(),
390 N->getOriginalAlignment());
394 //===----------------------------------------------------------------------===//
395 // Result Vector Splitting
396 //===----------------------------------------------------------------------===//
398 /// SplitVectorResult - This method is called when the specified result of the
399 /// specified node is found to need vector splitting. At this point, the node
400 /// may also have invalid operands or may have other results that need
401 /// legalization, we just know that (at least) one result needs vector
403 void DAGTypeLegalizer::SplitVectorResult(SDNode *N, unsigned ResNo) {
404 DEBUG(dbgs() << "Split node result: ";
409 switch (N->getOpcode()) {
412 dbgs() << "SplitVectorResult #" << ResNo << ": ";
416 llvm_unreachable("Do not know how to split the result of this operator!");
418 case ISD::MERGE_VALUES: SplitRes_MERGE_VALUES(N, Lo, Hi); break;
419 case ISD::SELECT: SplitRes_SELECT(N, Lo, Hi); break;
420 case ISD::SELECT_CC: SplitRes_SELECT_CC(N, Lo, Hi); break;
421 case ISD::UNDEF: SplitRes_UNDEF(N, Lo, Hi); break;
422 case ISD::BITCAST: SplitVecRes_BITCAST(N, Lo, Hi); break;
423 case ISD::BUILD_VECTOR: SplitVecRes_BUILD_VECTOR(N, Lo, Hi); break;
424 case ISD::CONCAT_VECTORS: SplitVecRes_CONCAT_VECTORS(N, Lo, Hi); break;
425 case ISD::EXTRACT_SUBVECTOR: SplitVecRes_EXTRACT_SUBVECTOR(N, Lo, Hi); break;
426 case ISD::FP_ROUND_INREG: SplitVecRes_InregOp(N, Lo, Hi); break;
427 case ISD::FPOWI: SplitVecRes_FPOWI(N, Lo, Hi); break;
428 case ISD::INSERT_VECTOR_ELT: SplitVecRes_INSERT_VECTOR_ELT(N, Lo, Hi); break;
429 case ISD::SCALAR_TO_VECTOR: SplitVecRes_SCALAR_TO_VECTOR(N, Lo, Hi); break;
430 case ISD::SIGN_EXTEND_INREG: SplitVecRes_InregOp(N, Lo, Hi); break;
432 SplitVecRes_LOAD(cast<LoadSDNode>(N), Lo, Hi);
436 SplitVecRes_SETCC(N, Lo, Hi);
438 case ISD::VECTOR_SHUFFLE:
439 SplitVecRes_VECTOR_SHUFFLE(cast<ShuffleVectorSDNode>(N), Lo, Hi);
442 case ISD::ANY_EXTEND:
443 case ISD::CONVERT_RNDSAT:
456 case ISD::FNEARBYINT:
460 case ISD::FP_TO_SINT:
461 case ISD::FP_TO_UINT:
466 case ISD::SIGN_EXTEND:
467 case ISD::SINT_TO_FP:
469 case ISD::UINT_TO_FP:
470 case ISD::ZERO_EXTEND:
471 SplitVecRes_UnaryOp(N, Lo, Hi);
493 SplitVecRes_BinOp(N, Lo, Hi);
497 // If Lo/Hi is null, the sub-method took care of registering results etc.
499 SetSplitVector(SDValue(N, ResNo), Lo, Hi);
502 void DAGTypeLegalizer::SplitVecRes_BinOp(SDNode *N, SDValue &Lo,
504 SDValue LHSLo, LHSHi;
505 GetSplitVector(N->getOperand(0), LHSLo, LHSHi);
506 SDValue RHSLo, RHSHi;
507 GetSplitVector(N->getOperand(1), RHSLo, RHSHi);
508 DebugLoc dl = N->getDebugLoc();
510 Lo = DAG.getNode(N->getOpcode(), dl, LHSLo.getValueType(), LHSLo, RHSLo);
511 Hi = DAG.getNode(N->getOpcode(), dl, LHSHi.getValueType(), LHSHi, RHSHi);
514 void DAGTypeLegalizer::SplitVecRes_BITCAST(SDNode *N, SDValue &Lo,
516 // We know the result is a vector. The input may be either a vector or a
519 GetSplitDestVTs(N->getValueType(0), LoVT, HiVT);
520 DebugLoc dl = N->getDebugLoc();
522 SDValue InOp = N->getOperand(0);
523 EVT InVT = InOp.getValueType();
525 // Handle some special cases efficiently.
526 switch (getTypeAction(InVT)) {
528 assert(false && "Unknown type action!");
529 case TargetLowering::TypeLegal:
530 case TargetLowering::TypePromoteInteger:
531 case TargetLowering::TypeSoftenFloat:
532 case TargetLowering::TypeScalarizeVector:
534 case TargetLowering::TypeExpandInteger:
535 case TargetLowering::TypeExpandFloat:
536 // A scalar to vector conversion, where the scalar needs expansion.
537 // If the vector is being split in two then we can just convert the
540 GetExpandedOp(InOp, Lo, Hi);
541 if (TLI.isBigEndian())
543 Lo = DAG.getNode(ISD::BITCAST, dl, LoVT, Lo);
544 Hi = DAG.getNode(ISD::BITCAST, dl, HiVT, Hi);
548 case TargetLowering::TypeSplitVector:
549 // If the input is a vector that needs to be split, convert each split
550 // piece of the input now.
551 GetSplitVector(InOp, Lo, Hi);
552 Lo = DAG.getNode(ISD::BITCAST, dl, LoVT, Lo);
553 Hi = DAG.getNode(ISD::BITCAST, dl, HiVT, Hi);
557 // In the general case, convert the input to an integer and split it by hand.
558 EVT LoIntVT = EVT::getIntegerVT(*DAG.getContext(), LoVT.getSizeInBits());
559 EVT HiIntVT = EVT::getIntegerVT(*DAG.getContext(), HiVT.getSizeInBits());
560 if (TLI.isBigEndian())
561 std::swap(LoIntVT, HiIntVT);
563 SplitInteger(BitConvertToInteger(InOp), LoIntVT, HiIntVT, Lo, Hi);
565 if (TLI.isBigEndian())
567 Lo = DAG.getNode(ISD::BITCAST, dl, LoVT, Lo);
568 Hi = DAG.getNode(ISD::BITCAST, dl, HiVT, Hi);
571 void DAGTypeLegalizer::SplitVecRes_BUILD_VECTOR(SDNode *N, SDValue &Lo,
574 DebugLoc dl = N->getDebugLoc();
575 GetSplitDestVTs(N->getValueType(0), LoVT, HiVT);
576 unsigned LoNumElts = LoVT.getVectorNumElements();
577 SmallVector<SDValue, 8> LoOps(N->op_begin(), N->op_begin()+LoNumElts);
578 Lo = DAG.getNode(ISD::BUILD_VECTOR, dl, LoVT, &LoOps[0], LoOps.size());
580 SmallVector<SDValue, 8> HiOps(N->op_begin()+LoNumElts, N->op_end());
581 Hi = DAG.getNode(ISD::BUILD_VECTOR, dl, HiVT, &HiOps[0], HiOps.size());
584 void DAGTypeLegalizer::SplitVecRes_CONCAT_VECTORS(SDNode *N, SDValue &Lo,
586 assert(!(N->getNumOperands() & 1) && "Unsupported CONCAT_VECTORS");
587 DebugLoc dl = N->getDebugLoc();
588 unsigned NumSubvectors = N->getNumOperands() / 2;
589 if (NumSubvectors == 1) {
590 Lo = N->getOperand(0);
591 Hi = N->getOperand(1);
596 GetSplitDestVTs(N->getValueType(0), LoVT, HiVT);
598 SmallVector<SDValue, 8> LoOps(N->op_begin(), N->op_begin()+NumSubvectors);
599 Lo = DAG.getNode(ISD::CONCAT_VECTORS, dl, LoVT, &LoOps[0], LoOps.size());
601 SmallVector<SDValue, 8> HiOps(N->op_begin()+NumSubvectors, N->op_end());
602 Hi = DAG.getNode(ISD::CONCAT_VECTORS, dl, HiVT, &HiOps[0], HiOps.size());
605 void DAGTypeLegalizer::SplitVecRes_EXTRACT_SUBVECTOR(SDNode *N, SDValue &Lo,
607 SDValue Vec = N->getOperand(0);
608 SDValue Idx = N->getOperand(1);
609 DebugLoc dl = N->getDebugLoc();
612 GetSplitDestVTs(N->getValueType(0), LoVT, HiVT);
614 Lo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, LoVT, Vec, Idx);
615 uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
616 Hi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, HiVT, Vec,
617 DAG.getIntPtrConstant(IdxVal + LoVT.getVectorNumElements()));
620 void DAGTypeLegalizer::SplitVecRes_FPOWI(SDNode *N, SDValue &Lo,
622 DebugLoc dl = N->getDebugLoc();
623 GetSplitVector(N->getOperand(0), Lo, Hi);
624 Lo = DAG.getNode(ISD::FPOWI, dl, Lo.getValueType(), Lo, N->getOperand(1));
625 Hi = DAG.getNode(ISD::FPOWI, dl, Hi.getValueType(), Hi, N->getOperand(1));
628 void DAGTypeLegalizer::SplitVecRes_InregOp(SDNode *N, SDValue &Lo,
630 SDValue LHSLo, LHSHi;
631 GetSplitVector(N->getOperand(0), LHSLo, LHSHi);
632 DebugLoc dl = N->getDebugLoc();
635 GetSplitDestVTs(cast<VTSDNode>(N->getOperand(1))->getVT(), LoVT, HiVT);
637 Lo = DAG.getNode(N->getOpcode(), dl, LHSLo.getValueType(), LHSLo,
638 DAG.getValueType(LoVT));
639 Hi = DAG.getNode(N->getOpcode(), dl, LHSHi.getValueType(), LHSHi,
640 DAG.getValueType(HiVT));
643 void DAGTypeLegalizer::SplitVecRes_INSERT_VECTOR_ELT(SDNode *N, SDValue &Lo,
645 SDValue Vec = N->getOperand(0);
646 SDValue Elt = N->getOperand(1);
647 SDValue Idx = N->getOperand(2);
648 DebugLoc dl = N->getDebugLoc();
649 GetSplitVector(Vec, Lo, Hi);
651 if (ConstantSDNode *CIdx = dyn_cast<ConstantSDNode>(Idx)) {
652 unsigned IdxVal = CIdx->getZExtValue();
653 unsigned LoNumElts = Lo.getValueType().getVectorNumElements();
654 if (IdxVal < LoNumElts)
655 Lo = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
656 Lo.getValueType(), Lo, Elt, Idx);
658 Hi = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, Hi.getValueType(), Hi, Elt,
659 DAG.getIntPtrConstant(IdxVal - LoNumElts));
663 // Spill the vector to the stack.
664 EVT VecVT = Vec.getValueType();
665 EVT EltVT = VecVT.getVectorElementType();
666 SDValue StackPtr = DAG.CreateStackTemporary(VecVT);
667 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Vec, StackPtr,
668 MachinePointerInfo(), false, false, 0);
670 // Store the new element. This may be larger than the vector element type,
671 // so use a truncating store.
672 SDValue EltPtr = GetVectorElementPointer(StackPtr, EltVT, Idx);
673 Type *VecType = VecVT.getTypeForEVT(*DAG.getContext());
675 TLI.getTargetData()->getPrefTypeAlignment(VecType);
676 Store = DAG.getTruncStore(Store, dl, Elt, EltPtr, MachinePointerInfo(), EltVT,
679 // Load the Lo part from the stack slot.
680 Lo = DAG.getLoad(Lo.getValueType(), dl, Store, StackPtr, MachinePointerInfo(),
683 // Increment the pointer to the other part.
684 unsigned IncrementSize = Lo.getValueType().getSizeInBits() / 8;
685 StackPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr,
686 DAG.getIntPtrConstant(IncrementSize));
688 // Load the Hi part from the stack slot.
689 Hi = DAG.getLoad(Hi.getValueType(), dl, Store, StackPtr, MachinePointerInfo(),
690 false, false, MinAlign(Alignment, IncrementSize));
693 void DAGTypeLegalizer::SplitVecRes_SCALAR_TO_VECTOR(SDNode *N, SDValue &Lo,
696 DebugLoc dl = N->getDebugLoc();
697 GetSplitDestVTs(N->getValueType(0), LoVT, HiVT);
698 Lo = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LoVT, N->getOperand(0));
699 Hi = DAG.getUNDEF(HiVT);
702 void DAGTypeLegalizer::SplitVecRes_LOAD(LoadSDNode *LD, SDValue &Lo,
704 assert(ISD::isUNINDEXEDLoad(LD) && "Indexed load during type legalization!");
706 DebugLoc dl = LD->getDebugLoc();
707 GetSplitDestVTs(LD->getValueType(0), LoVT, HiVT);
709 ISD::LoadExtType ExtType = LD->getExtensionType();
710 SDValue Ch = LD->getChain();
711 SDValue Ptr = LD->getBasePtr();
712 SDValue Offset = DAG.getUNDEF(Ptr.getValueType());
713 EVT MemoryVT = LD->getMemoryVT();
714 unsigned Alignment = LD->getOriginalAlignment();
715 bool isVolatile = LD->isVolatile();
716 bool isNonTemporal = LD->isNonTemporal();
718 EVT LoMemVT, HiMemVT;
719 GetSplitDestVTs(MemoryVT, LoMemVT, HiMemVT);
721 Lo = DAG.getLoad(ISD::UNINDEXED, ExtType, LoVT, dl, Ch, Ptr, Offset,
722 LD->getPointerInfo(), LoMemVT, isVolatile, isNonTemporal,
725 unsigned IncrementSize = LoMemVT.getSizeInBits()/8;
726 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
727 DAG.getIntPtrConstant(IncrementSize));
728 Hi = DAG.getLoad(ISD::UNINDEXED, ExtType, HiVT, dl, Ch, Ptr, Offset,
729 LD->getPointerInfo().getWithOffset(IncrementSize),
730 HiMemVT, isVolatile, isNonTemporal, Alignment);
732 // Build a factor node to remember that this load is independent of the
734 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
737 // Legalized the chain result - switch anything that used the old chain to
739 ReplaceValueWith(SDValue(LD, 1), Ch);
742 void DAGTypeLegalizer::SplitVecRes_SETCC(SDNode *N, SDValue &Lo, SDValue &Hi) {
744 DebugLoc DL = N->getDebugLoc();
745 GetSplitDestVTs(N->getValueType(0), LoVT, HiVT);
748 EVT InVT = N->getOperand(0).getValueType();
749 SDValue LL, LH, RL, RH;
750 EVT InNVT = EVT::getVectorVT(*DAG.getContext(), InVT.getVectorElementType(),
751 LoVT.getVectorNumElements());
752 LL = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, InNVT, N->getOperand(0),
753 DAG.getIntPtrConstant(0));
754 LH = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, InNVT, N->getOperand(0),
755 DAG.getIntPtrConstant(InNVT.getVectorNumElements()));
757 RL = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, InNVT, N->getOperand(1),
758 DAG.getIntPtrConstant(0));
759 RH = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, InNVT, N->getOperand(1),
760 DAG.getIntPtrConstant(InNVT.getVectorNumElements()));
762 Lo = DAG.getNode(N->getOpcode(), DL, LoVT, LL, RL, N->getOperand(2));
763 Hi = DAG.getNode(N->getOpcode(), DL, HiVT, LH, RH, N->getOperand(2));
766 void DAGTypeLegalizer::SplitVecRes_UnaryOp(SDNode *N, SDValue &Lo,
768 // Get the dest types - they may not match the input types, e.g. int_to_fp.
770 DebugLoc dl = N->getDebugLoc();
771 GetSplitDestVTs(N->getValueType(0), LoVT, HiVT);
774 EVT InVT = N->getOperand(0).getValueType();
775 switch (getTypeAction(InVT)) {
776 default: llvm_unreachable("Unexpected type action!");
777 case TargetLowering::TypeLegal: {
778 EVT InNVT = EVT::getVectorVT(*DAG.getContext(), InVT.getVectorElementType(),
779 LoVT.getVectorNumElements());
780 Lo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, InNVT, N->getOperand(0),
781 DAG.getIntPtrConstant(0));
782 Hi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, InNVT, N->getOperand(0),
783 DAG.getIntPtrConstant(InNVT.getVectorNumElements()));
786 case TargetLowering::TypePromoteInteger: {
787 SDValue InOp = GetPromotedInteger(N->getOperand(0));
788 EVT InNVT = EVT::getVectorVT(*DAG.getContext(),
789 InOp.getValueType().getVectorElementType(),
790 LoVT.getVectorNumElements());
791 Lo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, InNVT, InOp,
792 DAG.getIntPtrConstant(0));
793 Hi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, InNVT, InOp,
794 DAG.getIntPtrConstant(InNVT.getVectorNumElements()));
797 case TargetLowering::TypeSplitVector:
798 GetSplitVector(N->getOperand(0), Lo, Hi);
800 case TargetLowering::TypeWidenVector: {
801 // If the result needs to be split and the input needs to be widened,
802 // the two types must have different lengths. Use the widened result
803 // and extract from it to do the split.
804 SDValue InOp = GetWidenedVector(N->getOperand(0));
805 EVT InNVT = EVT::getVectorVT(*DAG.getContext(), InVT.getVectorElementType(),
806 LoVT.getVectorNumElements());
807 Lo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, InNVT, InOp,
808 DAG.getIntPtrConstant(0));
809 Hi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, InNVT, InOp,
810 DAG.getIntPtrConstant(InNVT.getVectorNumElements()));
815 if (N->getOpcode() == ISD::FP_ROUND) {
816 Lo = DAG.getNode(N->getOpcode(), dl, LoVT, Lo, N->getOperand(1));
817 Hi = DAG.getNode(N->getOpcode(), dl, HiVT, Hi, N->getOperand(1));
818 } else if (N->getOpcode() == ISD::CONVERT_RNDSAT) {
819 SDValue DTyOpLo = DAG.getValueType(LoVT);
820 SDValue DTyOpHi = DAG.getValueType(HiVT);
821 SDValue STyOpLo = DAG.getValueType(Lo.getValueType());
822 SDValue STyOpHi = DAG.getValueType(Hi.getValueType());
823 SDValue RndOp = N->getOperand(3);
824 SDValue SatOp = N->getOperand(4);
825 ISD::CvtCode CvtCode = cast<CvtRndSatSDNode>(N)->getCvtCode();
826 Lo = DAG.getConvertRndSat(LoVT, dl, Lo, DTyOpLo, STyOpLo, RndOp, SatOp,
828 Hi = DAG.getConvertRndSat(HiVT, dl, Hi, DTyOpHi, STyOpHi, RndOp, SatOp,
831 Lo = DAG.getNode(N->getOpcode(), dl, LoVT, Lo);
832 Hi = DAG.getNode(N->getOpcode(), dl, HiVT, Hi);
836 void DAGTypeLegalizer::SplitVecRes_VECTOR_SHUFFLE(ShuffleVectorSDNode *N,
837 SDValue &Lo, SDValue &Hi) {
838 // The low and high parts of the original input give four input vectors.
840 DebugLoc dl = N->getDebugLoc();
841 GetSplitVector(N->getOperand(0), Inputs[0], Inputs[1]);
842 GetSplitVector(N->getOperand(1), Inputs[2], Inputs[3]);
843 EVT NewVT = Inputs[0].getValueType();
844 unsigned NewElts = NewVT.getVectorNumElements();
846 // If Lo or Hi uses elements from at most two of the four input vectors, then
847 // express it as a vector shuffle of those two inputs. Otherwise extract the
848 // input elements by hand and construct the Lo/Hi output using a BUILD_VECTOR.
849 SmallVector<int, 16> Ops;
850 for (unsigned High = 0; High < 2; ++High) {
851 SDValue &Output = High ? Hi : Lo;
853 // Build a shuffle mask for the output, discovering on the fly which
854 // input vectors to use as shuffle operands (recorded in InputUsed).
855 // If building a suitable shuffle vector proves too hard, then bail
856 // out with useBuildVector set.
857 unsigned InputUsed[2] = { -1U, -1U }; // Not yet discovered.
858 unsigned FirstMaskIdx = High * NewElts;
859 bool useBuildVector = false;
860 for (unsigned MaskOffset = 0; MaskOffset < NewElts; ++MaskOffset) {
861 // The mask element. This indexes into the input.
862 int Idx = N->getMaskElt(FirstMaskIdx + MaskOffset);
864 // The input vector this mask element indexes into.
865 unsigned Input = (unsigned)Idx / NewElts;
867 if (Input >= array_lengthof(Inputs)) {
868 // The mask element does not index into any input vector.
873 // Turn the index into an offset from the start of the input vector.
874 Idx -= Input * NewElts;
876 // Find or create a shuffle vector operand to hold this input.
878 for (OpNo = 0; OpNo < array_lengthof(InputUsed); ++OpNo) {
879 if (InputUsed[OpNo] == Input) {
880 // This input vector is already an operand.
882 } else if (InputUsed[OpNo] == -1U) {
883 // Create a new operand for this input vector.
884 InputUsed[OpNo] = Input;
889 if (OpNo >= array_lengthof(InputUsed)) {
890 // More than two input vectors used! Give up on trying to create a
891 // shuffle vector. Insert all elements into a BUILD_VECTOR instead.
892 useBuildVector = true;
896 // Add the mask index for the new shuffle vector.
897 Ops.push_back(Idx + OpNo * NewElts);
900 if (useBuildVector) {
901 EVT EltVT = NewVT.getVectorElementType();
902 SmallVector<SDValue, 16> SVOps;
904 // Extract the input elements by hand.
905 for (unsigned MaskOffset = 0; MaskOffset < NewElts; ++MaskOffset) {
906 // The mask element. This indexes into the input.
907 int Idx = N->getMaskElt(FirstMaskIdx + MaskOffset);
909 // The input vector this mask element indexes into.
910 unsigned Input = (unsigned)Idx / NewElts;
912 if (Input >= array_lengthof(Inputs)) {
913 // The mask element is "undef" or indexes off the end of the input.
914 SVOps.push_back(DAG.getUNDEF(EltVT));
918 // Turn the index into an offset from the start of the input vector.
919 Idx -= Input * NewElts;
921 // Extract the vector element by hand.
922 SVOps.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT,
923 Inputs[Input], DAG.getIntPtrConstant(Idx)));
926 // Construct the Lo/Hi output using a BUILD_VECTOR.
927 Output = DAG.getNode(ISD::BUILD_VECTOR,dl,NewVT, &SVOps[0], SVOps.size());
928 } else if (InputUsed[0] == -1U) {
929 // No input vectors were used! The result is undefined.
930 Output = DAG.getUNDEF(NewVT);
932 SDValue Op0 = Inputs[InputUsed[0]];
933 // If only one input was used, use an undefined vector for the other.
934 SDValue Op1 = InputUsed[1] == -1U ?
935 DAG.getUNDEF(NewVT) : Inputs[InputUsed[1]];
936 // At least one input vector was used. Create a new shuffle vector.
937 Output = DAG.getVectorShuffle(NewVT, dl, Op0, Op1, &Ops[0]);
945 //===----------------------------------------------------------------------===//
946 // Operand Vector Splitting
947 //===----------------------------------------------------------------------===//
949 /// SplitVectorOperand - This method is called when the specified operand of the
950 /// specified node is found to need vector splitting. At this point, all of the
951 /// result types of the node are known to be legal, but other operands of the
952 /// node may need legalization as well as the specified one.
953 bool DAGTypeLegalizer::SplitVectorOperand(SDNode *N, unsigned OpNo) {
954 DEBUG(dbgs() << "Split node operand: ";
957 SDValue Res = SDValue();
959 if (Res.getNode() == 0) {
960 switch (N->getOpcode()) {
963 dbgs() << "SplitVectorOperand Op #" << OpNo << ": ";
967 llvm_unreachable("Do not know how to split this operator's operand!");
969 case ISD::BITCAST: Res = SplitVecOp_BITCAST(N); break;
970 case ISD::EXTRACT_SUBVECTOR: Res = SplitVecOp_EXTRACT_SUBVECTOR(N); break;
971 case ISD::EXTRACT_VECTOR_ELT:Res = SplitVecOp_EXTRACT_VECTOR_ELT(N); break;
972 case ISD::CONCAT_VECTORS: Res = SplitVecOp_CONCAT_VECTORS(N); break;
973 case ISD::FP_ROUND: Res = SplitVecOp_FP_ROUND(N); break;
975 Res = SplitVecOp_STORE(cast<StoreSDNode>(N), OpNo);
982 case ISD::FP_TO_SINT:
983 case ISD::FP_TO_UINT:
984 case ISD::SINT_TO_FP:
985 case ISD::UINT_TO_FP:
988 case ISD::SIGN_EXTEND:
989 case ISD::ZERO_EXTEND:
990 case ISD::ANY_EXTEND:
991 Res = SplitVecOp_UnaryOp(N);
996 // If the result is null, the sub-method took care of registering results etc.
997 if (!Res.getNode()) return false;
999 // If the result is N, the sub-method updated N in place. Tell the legalizer
1001 if (Res.getNode() == N)
1004 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 &&
1005 "Invalid operand expansion");
1007 ReplaceValueWith(SDValue(N, 0), Res);
1011 SDValue DAGTypeLegalizer::SplitVecOp_UnaryOp(SDNode *N) {
1012 // The result has a legal vector type, but the input needs splitting.
1013 EVT ResVT = N->getValueType(0);
1015 DebugLoc dl = N->getDebugLoc();
1016 GetSplitVector(N->getOperand(0), Lo, Hi);
1017 EVT InVT = Lo.getValueType();
1019 EVT OutVT = EVT::getVectorVT(*DAG.getContext(), ResVT.getVectorElementType(),
1020 InVT.getVectorNumElements());
1022 Lo = DAG.getNode(N->getOpcode(), dl, OutVT, Lo);
1023 Hi = DAG.getNode(N->getOpcode(), dl, OutVT, Hi);
1025 return DAG.getNode(ISD::CONCAT_VECTORS, dl, ResVT, Lo, Hi);
1028 SDValue DAGTypeLegalizer::SplitVecOp_BITCAST(SDNode *N) {
1029 // For example, i64 = BITCAST v4i16 on alpha. Typically the vector will
1030 // end up being split all the way down to individual components. Convert the
1031 // split pieces into integers and reassemble.
1033 GetSplitVector(N->getOperand(0), Lo, Hi);
1034 Lo = BitConvertToInteger(Lo);
1035 Hi = BitConvertToInteger(Hi);
1037 if (TLI.isBigEndian())
1040 return DAG.getNode(ISD::BITCAST, N->getDebugLoc(), N->getValueType(0),
1041 JoinIntegers(Lo, Hi));
1044 SDValue DAGTypeLegalizer::SplitVecOp_EXTRACT_SUBVECTOR(SDNode *N) {
1045 // We know that the extracted result type is legal.
1046 EVT SubVT = N->getValueType(0);
1047 SDValue Idx = N->getOperand(1);
1048 DebugLoc dl = N->getDebugLoc();
1050 GetSplitVector(N->getOperand(0), Lo, Hi);
1052 uint64_t LoElts = Lo.getValueType().getVectorNumElements();
1053 uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
1055 if (IdxVal < LoElts) {
1056 assert(IdxVal + SubVT.getVectorNumElements() <= LoElts &&
1057 "Extracted subvector crosses vector split!");
1058 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, Lo, Idx);
1060 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, Hi,
1061 DAG.getConstant(IdxVal - LoElts, Idx.getValueType()));
1065 SDValue DAGTypeLegalizer::SplitVecOp_EXTRACT_VECTOR_ELT(SDNode *N) {
1066 SDValue Vec = N->getOperand(0);
1067 SDValue Idx = N->getOperand(1);
1068 EVT VecVT = Vec.getValueType();
1070 if (isa<ConstantSDNode>(Idx)) {
1071 uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
1072 assert(IdxVal < VecVT.getVectorNumElements() && "Invalid vector index!");
1075 GetSplitVector(Vec, Lo, Hi);
1077 uint64_t LoElts = Lo.getValueType().getVectorNumElements();
1079 if (IdxVal < LoElts)
1080 return SDValue(DAG.UpdateNodeOperands(N, Lo, Idx), 0);
1081 return SDValue(DAG.UpdateNodeOperands(N, Hi,
1082 DAG.getConstant(IdxVal - LoElts,
1083 Idx.getValueType())), 0);
1086 // Store the vector to the stack.
1087 EVT EltVT = VecVT.getVectorElementType();
1088 DebugLoc dl = N->getDebugLoc();
1089 SDValue StackPtr = DAG.CreateStackTemporary(VecVT);
1090 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Vec, StackPtr,
1091 MachinePointerInfo(), false, false, 0);
1093 // Load back the required element.
1094 StackPtr = GetVectorElementPointer(StackPtr, EltVT, Idx);
1095 return DAG.getExtLoad(ISD::EXTLOAD, dl, N->getValueType(0), Store, StackPtr,
1096 MachinePointerInfo(), EltVT, false, false, 0);
1099 SDValue DAGTypeLegalizer::SplitVecOp_STORE(StoreSDNode *N, unsigned OpNo) {
1100 assert(N->isUnindexed() && "Indexed store of vector?");
1101 assert(OpNo == 1 && "Can only split the stored value");
1102 DebugLoc DL = N->getDebugLoc();
1104 bool isTruncating = N->isTruncatingStore();
1105 SDValue Ch = N->getChain();
1106 SDValue Ptr = N->getBasePtr();
1107 EVT MemoryVT = N->getMemoryVT();
1108 unsigned Alignment = N->getOriginalAlignment();
1109 bool isVol = N->isVolatile();
1110 bool isNT = N->isNonTemporal();
1112 GetSplitVector(N->getOperand(1), Lo, Hi);
1114 EVT LoMemVT, HiMemVT;
1115 GetSplitDestVTs(MemoryVT, LoMemVT, HiMemVT);
1117 unsigned IncrementSize = LoMemVT.getSizeInBits()/8;
1120 Lo = DAG.getTruncStore(Ch, DL, Lo, Ptr, N->getPointerInfo(),
1121 LoMemVT, isVol, isNT, Alignment);
1123 Lo = DAG.getStore(Ch, DL, Lo, Ptr, N->getPointerInfo(),
1124 isVol, isNT, Alignment);
1126 // Increment the pointer to the other half.
1127 Ptr = DAG.getNode(ISD::ADD, DL, Ptr.getValueType(), Ptr,
1128 DAG.getIntPtrConstant(IncrementSize));
1131 Hi = DAG.getTruncStore(Ch, DL, Hi, Ptr,
1132 N->getPointerInfo().getWithOffset(IncrementSize),
1133 HiMemVT, isVol, isNT, Alignment);
1135 Hi = DAG.getStore(Ch, DL, Hi, Ptr,
1136 N->getPointerInfo().getWithOffset(IncrementSize),
1137 isVol, isNT, Alignment);
1139 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Lo, Hi);
1142 SDValue DAGTypeLegalizer::SplitVecOp_CONCAT_VECTORS(SDNode *N) {
1143 DebugLoc DL = N->getDebugLoc();
1145 // The input operands all must have the same type, and we know the result the
1146 // result type is valid. Convert this to a buildvector which extracts all the
1148 // TODO: If the input elements are power-two vectors, we could convert this to
1149 // a new CONCAT_VECTORS node with elements that are half-wide.
1150 SmallVector<SDValue, 32> Elts;
1151 EVT EltVT = N->getValueType(0).getVectorElementType();
1152 for (unsigned op = 0, e = N->getNumOperands(); op != e; ++op) {
1153 SDValue Op = N->getOperand(op);
1154 for (unsigned i = 0, e = Op.getValueType().getVectorNumElements();
1156 Elts.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, EltVT,
1157 Op, DAG.getIntPtrConstant(i)));
1162 return DAG.getNode(ISD::BUILD_VECTOR, DL, N->getValueType(0),
1163 &Elts[0], Elts.size());
1166 SDValue DAGTypeLegalizer::SplitVecOp_FP_ROUND(SDNode *N) {
1167 // The result has a legal vector type, but the input needs splitting.
1168 EVT ResVT = N->getValueType(0);
1170 DebugLoc DL = N->getDebugLoc();
1171 GetSplitVector(N->getOperand(0), Lo, Hi);
1172 EVT InVT = Lo.getValueType();
1174 EVT OutVT = EVT::getVectorVT(*DAG.getContext(), ResVT.getVectorElementType(),
1175 InVT.getVectorNumElements());
1177 Lo = DAG.getNode(ISD::FP_ROUND, DL, OutVT, Lo, N->getOperand(1));
1178 Hi = DAG.getNode(ISD::FP_ROUND, DL, OutVT, Hi, N->getOperand(1));
1180 return DAG.getNode(ISD::CONCAT_VECTORS, DL, ResVT, Lo, Hi);
1185 //===----------------------------------------------------------------------===//
1186 // Result Vector Widening
1187 //===----------------------------------------------------------------------===//
1189 void DAGTypeLegalizer::WidenVectorResult(SDNode *N, unsigned ResNo) {
1190 DEBUG(dbgs() << "Widen node result " << ResNo << ": ";
1194 // See if the target wants to custom widen this node.
1195 if (CustomWidenLowerNode(N, N->getValueType(ResNo)))
1198 SDValue Res = SDValue();
1199 switch (N->getOpcode()) {
1202 dbgs() << "WidenVectorResult #" << ResNo << ": ";
1206 llvm_unreachable("Do not know how to widen the result of this operator!");
1208 case ISD::BITCAST: Res = WidenVecRes_BITCAST(N); break;
1209 case ISD::BUILD_VECTOR: Res = WidenVecRes_BUILD_VECTOR(N); break;
1210 case ISD::CONCAT_VECTORS: Res = WidenVecRes_CONCAT_VECTORS(N); break;
1211 case ISD::CONVERT_RNDSAT: Res = WidenVecRes_CONVERT_RNDSAT(N); break;
1212 case ISD::EXTRACT_SUBVECTOR: Res = WidenVecRes_EXTRACT_SUBVECTOR(N); break;
1213 case ISD::FP_ROUND_INREG: Res = WidenVecRes_InregOp(N); break;
1214 case ISD::INSERT_VECTOR_ELT: Res = WidenVecRes_INSERT_VECTOR_ELT(N); break;
1215 case ISD::LOAD: Res = WidenVecRes_LOAD(N); break;
1216 case ISD::SCALAR_TO_VECTOR: Res = WidenVecRes_SCALAR_TO_VECTOR(N); break;
1217 case ISD::SIGN_EXTEND_INREG: Res = WidenVecRes_InregOp(N); break;
1218 case ISD::SELECT: Res = WidenVecRes_SELECT(N); break;
1219 case ISD::SELECT_CC: Res = WidenVecRes_SELECT_CC(N); break;
1220 case ISD::SETCC: Res = WidenVecRes_SETCC(N); break;
1221 case ISD::UNDEF: Res = WidenVecRes_UNDEF(N); break;
1222 case ISD::VECTOR_SHUFFLE:
1223 Res = WidenVecRes_VECTOR_SHUFFLE(cast<ShuffleVectorSDNode>(N));
1226 Res = WidenVecRes_VSETCC(N);
1233 case ISD::FCOPYSIGN:
1249 Res = WidenVecRes_Binary(N);
1253 Res = WidenVecRes_POWI(N);
1259 Res = WidenVecRes_Shift(N);
1262 case ISD::ANY_EXTEND:
1263 case ISD::FP_EXTEND:
1265 case ISD::FP_TO_SINT:
1266 case ISD::FP_TO_UINT:
1267 case ISD::SIGN_EXTEND:
1268 case ISD::SINT_TO_FP:
1270 case ISD::UINT_TO_FP:
1271 case ISD::ZERO_EXTEND:
1272 Res = WidenVecRes_Convert(N);
1287 case ISD::FNEARBYINT:
1293 Res = WidenVecRes_Unary(N);
1297 // If Res is null, the sub-method took care of registering the result.
1299 SetWidenedVector(SDValue(N, ResNo), Res);
1302 SDValue DAGTypeLegalizer::WidenVecRes_Binary(SDNode *N) {
1303 // Binary op widening.
1304 unsigned Opcode = N->getOpcode();
1305 DebugLoc dl = N->getDebugLoc();
1306 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1307 EVT WidenEltVT = WidenVT.getVectorElementType();
1309 unsigned NumElts = VT.getVectorNumElements();
1310 while (!TLI.isTypeLegal(VT) && NumElts != 1) {
1311 NumElts = NumElts / 2;
1312 VT = EVT::getVectorVT(*DAG.getContext(), WidenEltVT, NumElts);
1315 if (NumElts != 1 && !TLI.canOpTrap(N->getOpcode(), VT)) {
1316 // Operation doesn't trap so just widen as normal.
1317 SDValue InOp1 = GetWidenedVector(N->getOperand(0));
1318 SDValue InOp2 = GetWidenedVector(N->getOperand(1));
1319 return DAG.getNode(N->getOpcode(), dl, WidenVT, InOp1, InOp2);
1322 // No legal vector version so unroll the vector operation and then widen.
1324 return DAG.UnrollVectorOp(N, WidenVT.getVectorNumElements());
1326 // Since the operation can trap, apply operation on the original vector.
1328 SDValue InOp1 = GetWidenedVector(N->getOperand(0));
1329 SDValue InOp2 = GetWidenedVector(N->getOperand(1));
1330 unsigned CurNumElts = N->getValueType(0).getVectorNumElements();
1332 SmallVector<SDValue, 16> ConcatOps(CurNumElts);
1333 unsigned ConcatEnd = 0; // Current ConcatOps index.
1334 int Idx = 0; // Current Idx into input vectors.
1336 // NumElts := greatest legal vector size (at most WidenVT)
1337 // while (orig. vector has unhandled elements) {
1338 // take munches of size NumElts from the beginning and add to ConcatOps
1339 // NumElts := next smaller supported vector size or 1
1341 while (CurNumElts != 0) {
1342 while (CurNumElts >= NumElts) {
1343 SDValue EOp1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, InOp1,
1344 DAG.getIntPtrConstant(Idx));
1345 SDValue EOp2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, InOp2,
1346 DAG.getIntPtrConstant(Idx));
1347 ConcatOps[ConcatEnd++] = DAG.getNode(Opcode, dl, VT, EOp1, EOp2);
1349 CurNumElts -= NumElts;
1352 NumElts = NumElts / 2;
1353 VT = EVT::getVectorVT(*DAG.getContext(), WidenEltVT, NumElts);
1354 } while (!TLI.isTypeLegal(VT) && NumElts != 1);
1357 for (unsigned i = 0; i != CurNumElts; ++i, ++Idx) {
1358 SDValue EOp1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, WidenEltVT,
1359 InOp1, DAG.getIntPtrConstant(Idx));
1360 SDValue EOp2 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, WidenEltVT,
1361 InOp2, DAG.getIntPtrConstant(Idx));
1362 ConcatOps[ConcatEnd++] = DAG.getNode(Opcode, dl, WidenEltVT,
1369 // Check to see if we have a single operation with the widen type.
1370 if (ConcatEnd == 1) {
1371 VT = ConcatOps[0].getValueType();
1373 return ConcatOps[0];
1376 // while (Some element of ConcatOps is not of type MaxVT) {
1377 // From the end of ConcatOps, collect elements of the same type and put
1378 // them into an op of the next larger supported type
1380 while (ConcatOps[ConcatEnd-1].getValueType() != MaxVT) {
1381 Idx = ConcatEnd - 1;
1382 VT = ConcatOps[Idx--].getValueType();
1383 while (Idx >= 0 && ConcatOps[Idx].getValueType() == VT)
1386 int NextSize = VT.isVector() ? VT.getVectorNumElements() : 1;
1390 NextVT = EVT::getVectorVT(*DAG.getContext(), WidenEltVT, NextSize);
1391 } while (!TLI.isTypeLegal(NextVT));
1393 if (!VT.isVector()) {
1394 // Scalar type, create an INSERT_VECTOR_ELEMENT of type NextVT
1395 SDValue VecOp = DAG.getUNDEF(NextVT);
1396 unsigned NumToInsert = ConcatEnd - Idx - 1;
1397 for (unsigned i = 0, OpIdx = Idx+1; i < NumToInsert; i++, OpIdx++) {
1398 VecOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, NextVT, VecOp,
1399 ConcatOps[OpIdx], DAG.getIntPtrConstant(i));
1401 ConcatOps[Idx+1] = VecOp;
1402 ConcatEnd = Idx + 2;
1404 // Vector type, create a CONCAT_VECTORS of type NextVT
1405 SDValue undefVec = DAG.getUNDEF(VT);
1406 unsigned OpsToConcat = NextSize/VT.getVectorNumElements();
1407 SmallVector<SDValue, 16> SubConcatOps(OpsToConcat);
1408 unsigned RealVals = ConcatEnd - Idx - 1;
1409 unsigned SubConcatEnd = 0;
1410 unsigned SubConcatIdx = Idx + 1;
1411 while (SubConcatEnd < RealVals)
1412 SubConcatOps[SubConcatEnd++] = ConcatOps[++Idx];
1413 while (SubConcatEnd < OpsToConcat)
1414 SubConcatOps[SubConcatEnd++] = undefVec;
1415 ConcatOps[SubConcatIdx] = DAG.getNode(ISD::CONCAT_VECTORS, dl,
1416 NextVT, &SubConcatOps[0],
1418 ConcatEnd = SubConcatIdx + 1;
1422 // Check to see if we have a single operation with the widen type.
1423 if (ConcatEnd == 1) {
1424 VT = ConcatOps[0].getValueType();
1426 return ConcatOps[0];
1429 // add undefs of size MaxVT until ConcatOps grows to length of WidenVT
1430 unsigned NumOps = WidenVT.getVectorNumElements()/MaxVT.getVectorNumElements();
1431 if (NumOps != ConcatEnd ) {
1432 SDValue UndefVal = DAG.getUNDEF(MaxVT);
1433 for (unsigned j = ConcatEnd; j < NumOps; ++j)
1434 ConcatOps[j] = UndefVal;
1436 return DAG.getNode(ISD::CONCAT_VECTORS, dl, WidenVT, &ConcatOps[0], NumOps);
1439 SDValue DAGTypeLegalizer::WidenVecRes_Convert(SDNode *N) {
1440 SDValue InOp = N->getOperand(0);
1441 DebugLoc DL = N->getDebugLoc();
1443 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1444 unsigned WidenNumElts = WidenVT.getVectorNumElements();
1446 EVT InVT = InOp.getValueType();
1447 EVT InEltVT = InVT.getVectorElementType();
1448 EVT InWidenVT = EVT::getVectorVT(*DAG.getContext(), InEltVT, WidenNumElts);
1450 unsigned Opcode = N->getOpcode();
1451 unsigned InVTNumElts = InVT.getVectorNumElements();
1453 if (getTypeAction(InVT) == TargetLowering::TypeWidenVector) {
1454 InOp = GetWidenedVector(N->getOperand(0));
1455 InVT = InOp.getValueType();
1456 InVTNumElts = InVT.getVectorNumElements();
1457 if (InVTNumElts == WidenNumElts) {
1458 if (N->getNumOperands() == 1)
1459 return DAG.getNode(Opcode, DL, WidenVT, InOp);
1460 return DAG.getNode(Opcode, DL, WidenVT, InOp, N->getOperand(1));
1464 if (TLI.isTypeLegal(InWidenVT)) {
1465 // Because the result and the input are different vector types, widening
1466 // the result could create a legal type but widening the input might make
1467 // it an illegal type that might lead to repeatedly splitting the input
1468 // and then widening it. To avoid this, we widen the input only if
1469 // it results in a legal type.
1470 if (WidenNumElts % InVTNumElts == 0) {
1471 // Widen the input and call convert on the widened input vector.
1472 unsigned NumConcat = WidenNumElts/InVTNumElts;
1473 SmallVector<SDValue, 16> Ops(NumConcat);
1475 SDValue UndefVal = DAG.getUNDEF(InVT);
1476 for (unsigned i = 1; i != NumConcat; ++i)
1478 SDValue InVec = DAG.getNode(ISD::CONCAT_VECTORS, DL, InWidenVT,
1479 &Ops[0], NumConcat);
1480 if (N->getNumOperands() == 1)
1481 return DAG.getNode(Opcode, DL, WidenVT, InVec);
1482 return DAG.getNode(Opcode, DL, WidenVT, InVec, N->getOperand(1));
1485 if (InVTNumElts % WidenNumElts == 0) {
1486 SDValue InVal = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, InWidenVT,
1487 InOp, DAG.getIntPtrConstant(0));
1488 // Extract the input and convert the shorten input vector.
1489 if (N->getNumOperands() == 1)
1490 return DAG.getNode(Opcode, DL, WidenVT, InVal);
1491 return DAG.getNode(Opcode, DL, WidenVT, InVal, N->getOperand(1));
1495 // Otherwise unroll into some nasty scalar code and rebuild the vector.
1496 SmallVector<SDValue, 16> Ops(WidenNumElts);
1497 EVT EltVT = WidenVT.getVectorElementType();
1498 unsigned MinElts = std::min(InVTNumElts, WidenNumElts);
1500 for (i=0; i < MinElts; ++i) {
1501 SDValue Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, InEltVT, InOp,
1502 DAG.getIntPtrConstant(i));
1503 if (N->getNumOperands() == 1)
1504 Ops[i] = DAG.getNode(Opcode, DL, EltVT, Val);
1506 Ops[i] = DAG.getNode(Opcode, DL, EltVT, Val, N->getOperand(1));
1509 SDValue UndefVal = DAG.getUNDEF(EltVT);
1510 for (; i < WidenNumElts; ++i)
1513 return DAG.getNode(ISD::BUILD_VECTOR, DL, WidenVT, &Ops[0], WidenNumElts);
1516 SDValue DAGTypeLegalizer::WidenVecRes_POWI(SDNode *N) {
1517 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1518 SDValue InOp = GetWidenedVector(N->getOperand(0));
1519 SDValue ShOp = N->getOperand(1);
1520 return DAG.getNode(N->getOpcode(), N->getDebugLoc(), WidenVT, InOp, ShOp);
1523 SDValue DAGTypeLegalizer::WidenVecRes_Shift(SDNode *N) {
1524 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1525 SDValue InOp = GetWidenedVector(N->getOperand(0));
1526 SDValue ShOp = N->getOperand(1);
1528 EVT ShVT = ShOp.getValueType();
1529 if (getTypeAction(ShVT) == TargetLowering::TypeWidenVector) {
1530 ShOp = GetWidenedVector(ShOp);
1531 ShVT = ShOp.getValueType();
1533 EVT ShWidenVT = EVT::getVectorVT(*DAG.getContext(),
1534 ShVT.getVectorElementType(),
1535 WidenVT.getVectorNumElements());
1536 if (ShVT != ShWidenVT)
1537 ShOp = ModifyToType(ShOp, ShWidenVT);
1539 return DAG.getNode(N->getOpcode(), N->getDebugLoc(), WidenVT, InOp, ShOp);
1542 SDValue DAGTypeLegalizer::WidenVecRes_Unary(SDNode *N) {
1543 // Unary op widening.
1544 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1545 SDValue InOp = GetWidenedVector(N->getOperand(0));
1546 return DAG.getNode(N->getOpcode(), N->getDebugLoc(), WidenVT, InOp);
1549 SDValue DAGTypeLegalizer::WidenVecRes_InregOp(SDNode *N) {
1550 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1551 EVT ExtVT = EVT::getVectorVT(*DAG.getContext(),
1552 cast<VTSDNode>(N->getOperand(1))->getVT()
1553 .getVectorElementType(),
1554 WidenVT.getVectorNumElements());
1555 SDValue WidenLHS = GetWidenedVector(N->getOperand(0));
1556 return DAG.getNode(N->getOpcode(), N->getDebugLoc(),
1557 WidenVT, WidenLHS, DAG.getValueType(ExtVT));
1560 SDValue DAGTypeLegalizer::WidenVecRes_BITCAST(SDNode *N) {
1561 SDValue InOp = N->getOperand(0);
1562 EVT InVT = InOp.getValueType();
1563 EVT VT = N->getValueType(0);
1564 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
1565 DebugLoc dl = N->getDebugLoc();
1567 switch (getTypeAction(InVT)) {
1569 assert(false && "Unknown type action!");
1571 case TargetLowering::TypeLegal:
1573 case TargetLowering::TypePromoteInteger:
1574 // If the InOp is promoted to the same size, convert it. Otherwise,
1575 // fall out of the switch and widen the promoted input.
1576 InOp = GetPromotedInteger(InOp);
1577 InVT = InOp.getValueType();
1578 if (WidenVT.bitsEq(InVT))
1579 return DAG.getNode(ISD::BITCAST, dl, WidenVT, InOp);
1581 case TargetLowering::TypeSoftenFloat:
1582 case TargetLowering::TypeExpandInteger:
1583 case TargetLowering::TypeExpandFloat:
1584 case TargetLowering::TypeScalarizeVector:
1585 case TargetLowering::TypeSplitVector:
1587 case TargetLowering::TypeWidenVector:
1588 // If the InOp is widened to the same size, convert it. Otherwise, fall
1589 // out of the switch and widen the widened input.
1590 InOp = GetWidenedVector(InOp);
1591 InVT = InOp.getValueType();
1592 if (WidenVT.bitsEq(InVT))
1593 // The input widens to the same size. Convert to the widen value.
1594 return DAG.getNode(ISD::BITCAST, dl, WidenVT, InOp);
1598 unsigned WidenSize = WidenVT.getSizeInBits();
1599 unsigned InSize = InVT.getSizeInBits();
1600 // x86mmx is not an acceptable vector element type, so don't try.
1601 if (WidenSize % InSize == 0 && InVT != MVT::x86mmx) {
1602 // Determine new input vector type. The new input vector type will use
1603 // the same element type (if its a vector) or use the input type as a
1604 // vector. It is the same size as the type to widen to.
1606 unsigned NewNumElts = WidenSize / InSize;
1607 if (InVT.isVector()) {
1608 EVT InEltVT = InVT.getVectorElementType();
1609 NewInVT = EVT::getVectorVT(*DAG.getContext(), InEltVT,
1610 WidenSize / InEltVT.getSizeInBits());
1612 NewInVT = EVT::getVectorVT(*DAG.getContext(), InVT, NewNumElts);
1615 if (TLI.isTypeLegal(NewInVT)) {
1616 // Because the result and the input are different vector types, widening
1617 // the result could create a legal type but widening the input might make
1618 // it an illegal type that might lead to repeatedly splitting the input
1619 // and then widening it. To avoid this, we widen the input only if
1620 // it results in a legal type.
1621 SmallVector<SDValue, 16> Ops(NewNumElts);
1622 SDValue UndefVal = DAG.getUNDEF(InVT);
1624 for (unsigned i = 1; i < NewNumElts; ++i)
1628 if (InVT.isVector())
1629 NewVec = DAG.getNode(ISD::CONCAT_VECTORS, dl,
1630 NewInVT, &Ops[0], NewNumElts);
1632 NewVec = DAG.getNode(ISD::BUILD_VECTOR, dl,
1633 NewInVT, &Ops[0], NewNumElts);
1634 return DAG.getNode(ISD::BITCAST, dl, WidenVT, NewVec);
1638 return CreateStackStoreLoad(InOp, WidenVT);
1641 SDValue DAGTypeLegalizer::WidenVecRes_BUILD_VECTOR(SDNode *N) {
1642 DebugLoc dl = N->getDebugLoc();
1643 // Build a vector with undefined for the new nodes.
1644 EVT VT = N->getValueType(0);
1645 EVT EltVT = VT.getVectorElementType();
1646 unsigned NumElts = VT.getVectorNumElements();
1648 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
1649 unsigned WidenNumElts = WidenVT.getVectorNumElements();
1651 SmallVector<SDValue, 16> NewOps(N->op_begin(), N->op_end());
1652 NewOps.reserve(WidenNumElts);
1653 for (unsigned i = NumElts; i < WidenNumElts; ++i)
1654 NewOps.push_back(DAG.getUNDEF(EltVT));
1656 return DAG.getNode(ISD::BUILD_VECTOR, dl, WidenVT, &NewOps[0], NewOps.size());
1659 SDValue DAGTypeLegalizer::WidenVecRes_CONCAT_VECTORS(SDNode *N) {
1660 EVT InVT = N->getOperand(0).getValueType();
1661 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1662 DebugLoc dl = N->getDebugLoc();
1663 unsigned WidenNumElts = WidenVT.getVectorNumElements();
1664 unsigned NumInElts = InVT.getVectorNumElements();
1665 unsigned NumOperands = N->getNumOperands();
1667 bool InputWidened = false; // Indicates we need to widen the input.
1668 if (getTypeAction(InVT) != TargetLowering::TypeWidenVector) {
1669 if (WidenVT.getVectorNumElements() % InVT.getVectorNumElements() == 0) {
1670 // Add undef vectors to widen to correct length.
1671 unsigned NumConcat = WidenVT.getVectorNumElements() /
1672 InVT.getVectorNumElements();
1673 SDValue UndefVal = DAG.getUNDEF(InVT);
1674 SmallVector<SDValue, 16> Ops(NumConcat);
1675 for (unsigned i=0; i < NumOperands; ++i)
1676 Ops[i] = N->getOperand(i);
1677 for (unsigned i = NumOperands; i != NumConcat; ++i)
1679 return DAG.getNode(ISD::CONCAT_VECTORS, dl, WidenVT, &Ops[0], NumConcat);
1682 InputWidened = true;
1683 if (WidenVT == TLI.getTypeToTransformTo(*DAG.getContext(), InVT)) {
1684 // The inputs and the result are widen to the same value.
1686 for (i=1; i < NumOperands; ++i)
1687 if (N->getOperand(i).getOpcode() != ISD::UNDEF)
1690 if (i == NumOperands)
1691 // Everything but the first operand is an UNDEF so just return the
1692 // widened first operand.
1693 return GetWidenedVector(N->getOperand(0));
1695 if (NumOperands == 2) {
1696 // Replace concat of two operands with a shuffle.
1697 SmallVector<int, 16> MaskOps(WidenNumElts, -1);
1698 for (unsigned i = 0; i < NumInElts; ++i) {
1700 MaskOps[i + NumInElts] = i + WidenNumElts;
1702 return DAG.getVectorShuffle(WidenVT, dl,
1703 GetWidenedVector(N->getOperand(0)),
1704 GetWidenedVector(N->getOperand(1)),
1710 // Fall back to use extracts and build vector.
1711 EVT EltVT = WidenVT.getVectorElementType();
1712 SmallVector<SDValue, 16> Ops(WidenNumElts);
1714 for (unsigned i=0; i < NumOperands; ++i) {
1715 SDValue InOp = N->getOperand(i);
1717 InOp = GetWidenedVector(InOp);
1718 for (unsigned j=0; j < NumInElts; ++j)
1719 Ops[Idx++] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, InOp,
1720 DAG.getIntPtrConstant(j));
1722 SDValue UndefVal = DAG.getUNDEF(EltVT);
1723 for (; Idx < WidenNumElts; ++Idx)
1724 Ops[Idx] = UndefVal;
1725 return DAG.getNode(ISD::BUILD_VECTOR, dl, WidenVT, &Ops[0], WidenNumElts);
1728 SDValue DAGTypeLegalizer::WidenVecRes_CONVERT_RNDSAT(SDNode *N) {
1729 DebugLoc dl = N->getDebugLoc();
1730 SDValue InOp = N->getOperand(0);
1731 SDValue RndOp = N->getOperand(3);
1732 SDValue SatOp = N->getOperand(4);
1734 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1735 unsigned WidenNumElts = WidenVT.getVectorNumElements();
1737 EVT InVT = InOp.getValueType();
1738 EVT InEltVT = InVT.getVectorElementType();
1739 EVT InWidenVT = EVT::getVectorVT(*DAG.getContext(), InEltVT, WidenNumElts);
1741 SDValue DTyOp = DAG.getValueType(WidenVT);
1742 SDValue STyOp = DAG.getValueType(InWidenVT);
1743 ISD::CvtCode CvtCode = cast<CvtRndSatSDNode>(N)->getCvtCode();
1745 unsigned InVTNumElts = InVT.getVectorNumElements();
1746 if (getTypeAction(InVT) == TargetLowering::TypeWidenVector) {
1747 InOp = GetWidenedVector(InOp);
1748 InVT = InOp.getValueType();
1749 InVTNumElts = InVT.getVectorNumElements();
1750 if (InVTNumElts == WidenNumElts)
1751 return DAG.getConvertRndSat(WidenVT, dl, InOp, DTyOp, STyOp, RndOp,
1755 if (TLI.isTypeLegal(InWidenVT)) {
1756 // Because the result and the input are different vector types, widening
1757 // the result could create a legal type but widening the input might make
1758 // it an illegal type that might lead to repeatedly splitting the input
1759 // and then widening it. To avoid this, we widen the input only if
1760 // it results in a legal type.
1761 if (WidenNumElts % InVTNumElts == 0) {
1762 // Widen the input and call convert on the widened input vector.
1763 unsigned NumConcat = WidenNumElts/InVTNumElts;
1764 SmallVector<SDValue, 16> Ops(NumConcat);
1766 SDValue UndefVal = DAG.getUNDEF(InVT);
1767 for (unsigned i = 1; i != NumConcat; ++i)
1770 InOp = DAG.getNode(ISD::CONCAT_VECTORS, dl, InWidenVT, &Ops[0],NumConcat);
1771 return DAG.getConvertRndSat(WidenVT, dl, InOp, DTyOp, STyOp, RndOp,
1775 if (InVTNumElts % WidenNumElts == 0) {
1776 // Extract the input and convert the shorten input vector.
1777 InOp = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, InWidenVT, InOp,
1778 DAG.getIntPtrConstant(0));
1779 return DAG.getConvertRndSat(WidenVT, dl, InOp, DTyOp, STyOp, RndOp,
1784 // Otherwise unroll into some nasty scalar code and rebuild the vector.
1785 SmallVector<SDValue, 16> Ops(WidenNumElts);
1786 EVT EltVT = WidenVT.getVectorElementType();
1787 DTyOp = DAG.getValueType(EltVT);
1788 STyOp = DAG.getValueType(InEltVT);
1790 unsigned MinElts = std::min(InVTNumElts, WidenNumElts);
1792 for (i=0; i < MinElts; ++i) {
1793 SDValue ExtVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, InEltVT, InOp,
1794 DAG.getIntPtrConstant(i));
1795 Ops[i] = DAG.getConvertRndSat(WidenVT, dl, ExtVal, DTyOp, STyOp, RndOp,
1799 SDValue UndefVal = DAG.getUNDEF(EltVT);
1800 for (; i < WidenNumElts; ++i)
1803 return DAG.getNode(ISD::BUILD_VECTOR, dl, WidenVT, &Ops[0], WidenNumElts);
1806 SDValue DAGTypeLegalizer::WidenVecRes_EXTRACT_SUBVECTOR(SDNode *N) {
1807 EVT VT = N->getValueType(0);
1808 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
1809 unsigned WidenNumElts = WidenVT.getVectorNumElements();
1810 SDValue InOp = N->getOperand(0);
1811 SDValue Idx = N->getOperand(1);
1812 DebugLoc dl = N->getDebugLoc();
1814 if (getTypeAction(InOp.getValueType()) == TargetLowering::TypeWidenVector)
1815 InOp = GetWidenedVector(InOp);
1817 EVT InVT = InOp.getValueType();
1819 // Check if we can just return the input vector after widening.
1820 uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
1821 if (IdxVal == 0 && InVT == WidenVT)
1824 // Check if we can extract from the vector.
1825 unsigned InNumElts = InVT.getVectorNumElements();
1826 if (IdxVal % WidenNumElts == 0 && IdxVal + WidenNumElts < InNumElts)
1827 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, WidenVT, InOp, Idx);
1829 // We could try widening the input to the right length but for now, extract
1830 // the original elements, fill the rest with undefs and build a vector.
1831 SmallVector<SDValue, 16> Ops(WidenNumElts);
1832 EVT EltVT = VT.getVectorElementType();
1833 unsigned NumElts = VT.getVectorNumElements();
1835 for (i=0; i < NumElts; ++i)
1836 Ops[i] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, InOp,
1837 DAG.getIntPtrConstant(IdxVal+i));
1839 SDValue UndefVal = DAG.getUNDEF(EltVT);
1840 for (; i < WidenNumElts; ++i)
1842 return DAG.getNode(ISD::BUILD_VECTOR, dl, WidenVT, &Ops[0], WidenNumElts);
1845 SDValue DAGTypeLegalizer::WidenVecRes_INSERT_VECTOR_ELT(SDNode *N) {
1846 SDValue InOp = GetWidenedVector(N->getOperand(0));
1847 return DAG.getNode(ISD::INSERT_VECTOR_ELT, N->getDebugLoc(),
1848 InOp.getValueType(), InOp,
1849 N->getOperand(1), N->getOperand(2));
1852 SDValue DAGTypeLegalizer::WidenVecRes_LOAD(SDNode *N) {
1853 LoadSDNode *LD = cast<LoadSDNode>(N);
1854 ISD::LoadExtType ExtType = LD->getExtensionType();
1857 SmallVector<SDValue, 16> LdChain; // Chain for the series of load
1858 if (ExtType != ISD::NON_EXTLOAD)
1859 Result = GenWidenVectorExtLoads(LdChain, LD, ExtType);
1861 Result = GenWidenVectorLoads(LdChain, LD);
1863 // If we generate a single load, we can use that for the chain. Otherwise,
1864 // build a factor node to remember the multiple loads are independent and
1867 if (LdChain.size() == 1)
1868 NewChain = LdChain[0];
1870 NewChain = DAG.getNode(ISD::TokenFactor, LD->getDebugLoc(), MVT::Other,
1871 &LdChain[0], LdChain.size());
1873 // Modified the chain - switch anything that used the old chain to use
1875 ReplaceValueWith(SDValue(N, 1), NewChain);
1880 SDValue DAGTypeLegalizer::WidenVecRes_SCALAR_TO_VECTOR(SDNode *N) {
1881 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1882 return DAG.getNode(ISD::SCALAR_TO_VECTOR, N->getDebugLoc(),
1883 WidenVT, N->getOperand(0));
1886 SDValue DAGTypeLegalizer::WidenVecRes_SELECT(SDNode *N) {
1887 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1888 unsigned WidenNumElts = WidenVT.getVectorNumElements();
1890 SDValue Cond1 = N->getOperand(0);
1891 EVT CondVT = Cond1.getValueType();
1892 if (CondVT.isVector()) {
1893 EVT CondEltVT = CondVT.getVectorElementType();
1894 EVT CondWidenVT = EVT::getVectorVT(*DAG.getContext(),
1895 CondEltVT, WidenNumElts);
1896 if (getTypeAction(CondVT) == TargetLowering::TypeWidenVector)
1897 Cond1 = GetWidenedVector(Cond1);
1899 if (Cond1.getValueType() != CondWidenVT)
1900 Cond1 = ModifyToType(Cond1, CondWidenVT);
1903 SDValue InOp1 = GetWidenedVector(N->getOperand(1));
1904 SDValue InOp2 = GetWidenedVector(N->getOperand(2));
1905 assert(InOp1.getValueType() == WidenVT && InOp2.getValueType() == WidenVT);
1906 return DAG.getNode(ISD::SELECT, N->getDebugLoc(),
1907 WidenVT, Cond1, InOp1, InOp2);
1910 SDValue DAGTypeLegalizer::WidenVecRes_SELECT_CC(SDNode *N) {
1911 SDValue InOp1 = GetWidenedVector(N->getOperand(2));
1912 SDValue InOp2 = GetWidenedVector(N->getOperand(3));
1913 return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(),
1914 InOp1.getValueType(), N->getOperand(0),
1915 N->getOperand(1), InOp1, InOp2, N->getOperand(4));
1918 SDValue DAGTypeLegalizer::WidenVecRes_SETCC(SDNode *N) {
1919 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1920 SDValue InOp1 = GetWidenedVector(N->getOperand(0));
1921 SDValue InOp2 = GetWidenedVector(N->getOperand(1));
1922 return DAG.getNode(ISD::SETCC, N->getDebugLoc(), WidenVT,
1923 InOp1, InOp2, N->getOperand(2));
1926 SDValue DAGTypeLegalizer::WidenVecRes_UNDEF(SDNode *N) {
1927 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1928 return DAG.getUNDEF(WidenVT);
1931 SDValue DAGTypeLegalizer::WidenVecRes_VECTOR_SHUFFLE(ShuffleVectorSDNode *N) {
1932 EVT VT = N->getValueType(0);
1933 DebugLoc dl = N->getDebugLoc();
1935 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
1936 unsigned NumElts = VT.getVectorNumElements();
1937 unsigned WidenNumElts = WidenVT.getVectorNumElements();
1939 SDValue InOp1 = GetWidenedVector(N->getOperand(0));
1940 SDValue InOp2 = GetWidenedVector(N->getOperand(1));
1942 // Adjust mask based on new input vector length.
1943 SmallVector<int, 16> NewMask;
1944 for (unsigned i = 0; i != NumElts; ++i) {
1945 int Idx = N->getMaskElt(i);
1946 if (Idx < (int)NumElts)
1947 NewMask.push_back(Idx);
1949 NewMask.push_back(Idx - NumElts + WidenNumElts);
1951 for (unsigned i = NumElts; i != WidenNumElts; ++i)
1952 NewMask.push_back(-1);
1953 return DAG.getVectorShuffle(WidenVT, dl, InOp1, InOp2, &NewMask[0]);
1956 SDValue DAGTypeLegalizer::WidenVecRes_VSETCC(SDNode *N) {
1957 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1958 unsigned WidenNumElts = WidenVT.getVectorNumElements();
1960 SDValue InOp1 = N->getOperand(0);
1961 EVT InVT = InOp1.getValueType();
1962 assert(InVT.isVector() && "can not widen non vector type");
1963 EVT WidenInVT = EVT::getVectorVT(*DAG.getContext(),
1964 InVT.getVectorElementType(), WidenNumElts);
1965 InOp1 = GetWidenedVector(InOp1);
1966 SDValue InOp2 = GetWidenedVector(N->getOperand(1));
1968 // Assume that the input and output will be widen appropriately. If not,
1969 // we will have to unroll it at some point.
1970 assert(InOp1.getValueType() == WidenInVT &&
1971 InOp2.getValueType() == WidenInVT &&
1972 "Input not widened to expected type!");
1973 return DAG.getNode(ISD::VSETCC, N->getDebugLoc(),
1974 WidenVT, InOp1, InOp2, N->getOperand(2));
1978 //===----------------------------------------------------------------------===//
1979 // Widen Vector Operand
1980 //===----------------------------------------------------------------------===//
1981 bool DAGTypeLegalizer::WidenVectorOperand(SDNode *N, unsigned ResNo) {
1982 DEBUG(dbgs() << "Widen node operand " << ResNo << ": ";
1985 SDValue Res = SDValue();
1987 switch (N->getOpcode()) {
1990 dbgs() << "WidenVectorOperand op #" << ResNo << ": ";
1994 llvm_unreachable("Do not know how to widen this operator's operand!");
1996 case ISD::BITCAST: Res = WidenVecOp_BITCAST(N); break;
1997 case ISD::CONCAT_VECTORS: Res = WidenVecOp_CONCAT_VECTORS(N); break;
1998 case ISD::EXTRACT_SUBVECTOR: Res = WidenVecOp_EXTRACT_SUBVECTOR(N); break;
1999 case ISD::EXTRACT_VECTOR_ELT: Res = WidenVecOp_EXTRACT_VECTOR_ELT(N); break;
2000 case ISD::STORE: Res = WidenVecOp_STORE(N); break;
2002 case ISD::FP_EXTEND:
2003 case ISD::FP_TO_SINT:
2004 case ISD::FP_TO_UINT:
2005 case ISD::SINT_TO_FP:
2006 case ISD::UINT_TO_FP:
2008 case ISD::SIGN_EXTEND:
2009 case ISD::ZERO_EXTEND:
2010 case ISD::ANY_EXTEND:
2011 Res = WidenVecOp_Convert(N);
2015 // If Res is null, the sub-method took care of registering the result.
2016 if (!Res.getNode()) return false;
2018 // If the result is N, the sub-method updated N in place. Tell the legalizer
2020 if (Res.getNode() == N)
2024 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 &&
2025 "Invalid operand expansion");
2027 ReplaceValueWith(SDValue(N, 0), Res);
2031 SDValue DAGTypeLegalizer::WidenVecOp_Convert(SDNode *N) {
2032 // Since the result is legal and the input is illegal, it is unlikely
2033 // that we can fix the input to a legal type so unroll the convert
2034 // into some scalar code and create a nasty build vector.
2035 EVT VT = N->getValueType(0);
2036 EVT EltVT = VT.getVectorElementType();
2037 DebugLoc dl = N->getDebugLoc();
2038 unsigned NumElts = VT.getVectorNumElements();
2039 SDValue InOp = N->getOperand(0);
2040 if (getTypeAction(InOp.getValueType()) == TargetLowering::TypeWidenVector)
2041 InOp = GetWidenedVector(InOp);
2042 EVT InVT = InOp.getValueType();
2043 EVT InEltVT = InVT.getVectorElementType();
2045 unsigned Opcode = N->getOpcode();
2046 SmallVector<SDValue, 16> Ops(NumElts);
2047 for (unsigned i=0; i < NumElts; ++i)
2048 Ops[i] = DAG.getNode(Opcode, dl, EltVT,
2049 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, InEltVT, InOp,
2050 DAG.getIntPtrConstant(i)));
2052 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &Ops[0], NumElts);
2055 SDValue DAGTypeLegalizer::WidenVecOp_BITCAST(SDNode *N) {
2056 EVT VT = N->getValueType(0);
2057 SDValue InOp = GetWidenedVector(N->getOperand(0));
2058 EVT InWidenVT = InOp.getValueType();
2059 DebugLoc dl = N->getDebugLoc();
2061 // Check if we can convert between two legal vector types and extract.
2062 unsigned InWidenSize = InWidenVT.getSizeInBits();
2063 unsigned Size = VT.getSizeInBits();
2064 // x86mmx is not an acceptable vector element type, so don't try.
2065 if (InWidenSize % Size == 0 && !VT.isVector() && VT != MVT::x86mmx) {
2066 unsigned NewNumElts = InWidenSize / Size;
2067 EVT NewVT = EVT::getVectorVT(*DAG.getContext(), VT, NewNumElts);
2068 if (TLI.isTypeLegal(NewVT)) {
2069 SDValue BitOp = DAG.getNode(ISD::BITCAST, dl, NewVT, InOp);
2070 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, BitOp,
2071 DAG.getIntPtrConstant(0));
2075 return CreateStackStoreLoad(InOp, VT);
2078 SDValue DAGTypeLegalizer::WidenVecOp_CONCAT_VECTORS(SDNode *N) {
2079 // If the input vector is not legal, it is likely that we will not find a
2080 // legal vector of the same size. Replace the concatenate vector with a
2081 // nasty build vector.
2082 EVT VT = N->getValueType(0);
2083 EVT EltVT = VT.getVectorElementType();
2084 DebugLoc dl = N->getDebugLoc();
2085 unsigned NumElts = VT.getVectorNumElements();
2086 SmallVector<SDValue, 16> Ops(NumElts);
2088 EVT InVT = N->getOperand(0).getValueType();
2089 unsigned NumInElts = InVT.getVectorNumElements();
2092 unsigned NumOperands = N->getNumOperands();
2093 for (unsigned i=0; i < NumOperands; ++i) {
2094 SDValue InOp = N->getOperand(i);
2095 if (getTypeAction(InOp.getValueType()) == TargetLowering::TypeWidenVector)
2096 InOp = GetWidenedVector(InOp);
2097 for (unsigned j=0; j < NumInElts; ++j)
2098 Ops[Idx++] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, InOp,
2099 DAG.getIntPtrConstant(j));
2101 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &Ops[0], NumElts);
2104 SDValue DAGTypeLegalizer::WidenVecOp_EXTRACT_SUBVECTOR(SDNode *N) {
2105 SDValue InOp = GetWidenedVector(N->getOperand(0));
2106 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, N->getDebugLoc(),
2107 N->getValueType(0), InOp, N->getOperand(1));
2110 SDValue DAGTypeLegalizer::WidenVecOp_EXTRACT_VECTOR_ELT(SDNode *N) {
2111 SDValue InOp = GetWidenedVector(N->getOperand(0));
2112 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, N->getDebugLoc(),
2113 N->getValueType(0), InOp, N->getOperand(1));
2116 SDValue DAGTypeLegalizer::WidenVecOp_STORE(SDNode *N) {
2117 // We have to widen the value but we want only to store the original
2119 StoreSDNode *ST = cast<StoreSDNode>(N);
2121 SmallVector<SDValue, 16> StChain;
2122 if (ST->isTruncatingStore())
2123 GenWidenVectorTruncStores(StChain, ST);
2125 GenWidenVectorStores(StChain, ST);
2127 if (StChain.size() == 1)
2130 return DAG.getNode(ISD::TokenFactor, ST->getDebugLoc(),
2131 MVT::Other,&StChain[0],StChain.size());
2134 //===----------------------------------------------------------------------===//
2135 // Vector Widening Utilities
2136 //===----------------------------------------------------------------------===//
2138 // Utility function to find the type to chop up a widen vector for load/store
2139 // TLI: Target lowering used to determine legal types.
2140 // Width: Width left need to load/store.
2141 // WidenVT: The widen vector type to load to/store from
2142 // Align: If 0, don't allow use of a wider type
2143 // WidenEx: If Align is not 0, the amount additional we can load/store from.
2145 static EVT FindMemType(SelectionDAG& DAG, const TargetLowering &TLI,
2146 unsigned Width, EVT WidenVT,
2147 unsigned Align = 0, unsigned WidenEx = 0) {
2148 EVT WidenEltVT = WidenVT.getVectorElementType();
2149 unsigned WidenWidth = WidenVT.getSizeInBits();
2150 unsigned WidenEltWidth = WidenEltVT.getSizeInBits();
2151 unsigned AlignInBits = Align*8;
2153 // If we have one element to load/store, return it.
2154 EVT RetVT = WidenEltVT;
2155 if (Width == WidenEltWidth)
2158 // See if there is larger legal integer than the element type to load/store
2160 for (VT = (unsigned)MVT::LAST_INTEGER_VALUETYPE;
2161 VT >= (unsigned)MVT::FIRST_INTEGER_VALUETYPE; --VT) {
2162 EVT MemVT((MVT::SimpleValueType) VT);
2163 unsigned MemVTWidth = MemVT.getSizeInBits();
2164 if (MemVT.getSizeInBits() <= WidenEltWidth)
2166 if (TLI.isTypeLegal(MemVT) && (WidenWidth % MemVTWidth) == 0 &&
2167 isPowerOf2_32(WidenWidth / MemVTWidth) &&
2168 (MemVTWidth <= Width ||
2169 (Align!=0 && MemVTWidth<=AlignInBits && MemVTWidth<=Width+WidenEx))) {
2175 // See if there is a larger vector type to load/store that has the same vector
2176 // element type and is evenly divisible with the WidenVT.
2177 for (VT = (unsigned)MVT::LAST_VECTOR_VALUETYPE;
2178 VT >= (unsigned)MVT::FIRST_VECTOR_VALUETYPE; --VT) {
2179 EVT MemVT = (MVT::SimpleValueType) VT;
2180 unsigned MemVTWidth = MemVT.getSizeInBits();
2181 if (TLI.isTypeLegal(MemVT) && WidenEltVT == MemVT.getVectorElementType() &&
2182 (WidenWidth % MemVTWidth) == 0 &&
2183 isPowerOf2_32(WidenWidth / MemVTWidth) &&
2184 (MemVTWidth <= Width ||
2185 (Align!=0 && MemVTWidth<=AlignInBits && MemVTWidth<=Width+WidenEx))) {
2186 if (RetVT.getSizeInBits() < MemVTWidth || MemVT == WidenVT)
2194 // Builds a vector type from scalar loads
2195 // VecTy: Resulting Vector type
2196 // LDOps: Load operators to build a vector type
2197 // [Start,End) the list of loads to use.
2198 static SDValue BuildVectorFromScalar(SelectionDAG& DAG, EVT VecTy,
2199 SmallVector<SDValue, 16>& LdOps,
2200 unsigned Start, unsigned End) {
2201 DebugLoc dl = LdOps[Start].getDebugLoc();
2202 EVT LdTy = LdOps[Start].getValueType();
2203 unsigned Width = VecTy.getSizeInBits();
2204 unsigned NumElts = Width / LdTy.getSizeInBits();
2205 EVT NewVecVT = EVT::getVectorVT(*DAG.getContext(), LdTy, NumElts);
2208 SDValue VecOp = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, NewVecVT,LdOps[Start]);
2210 for (unsigned i = Start + 1; i != End; ++i) {
2211 EVT NewLdTy = LdOps[i].getValueType();
2212 if (NewLdTy != LdTy) {
2213 NumElts = Width / NewLdTy.getSizeInBits();
2214 NewVecVT = EVT::getVectorVT(*DAG.getContext(), NewLdTy, NumElts);
2215 VecOp = DAG.getNode(ISD::BITCAST, dl, NewVecVT, VecOp);
2216 // Readjust position and vector position based on new load type
2217 Idx = Idx * LdTy.getSizeInBits() / NewLdTy.getSizeInBits();
2220 VecOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, NewVecVT, VecOp, LdOps[i],
2221 DAG.getIntPtrConstant(Idx++));
2223 return DAG.getNode(ISD::BITCAST, dl, VecTy, VecOp);
2226 SDValue DAGTypeLegalizer::GenWidenVectorLoads(SmallVector<SDValue, 16> &LdChain,
2228 // The strategy assumes that we can efficiently load powers of two widths.
2229 // The routines chops the vector into the largest vector loads with the same
2230 // element type or scalar loads and then recombines it to the widen vector
2232 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(),LD->getValueType(0));
2233 unsigned WidenWidth = WidenVT.getSizeInBits();
2234 EVT LdVT = LD->getMemoryVT();
2235 DebugLoc dl = LD->getDebugLoc();
2236 assert(LdVT.isVector() && WidenVT.isVector());
2237 assert(LdVT.getVectorElementType() == WidenVT.getVectorElementType());
2240 SDValue Chain = LD->getChain();
2241 SDValue BasePtr = LD->getBasePtr();
2242 unsigned Align = LD->getAlignment();
2243 bool isVolatile = LD->isVolatile();
2244 bool isNonTemporal = LD->isNonTemporal();
2246 int LdWidth = LdVT.getSizeInBits();
2247 int WidthDiff = WidenWidth - LdWidth; // Difference
2248 unsigned LdAlign = (isVolatile) ? 0 : Align; // Allow wider loads
2250 // Find the vector type that can load from.
2251 EVT NewVT = FindMemType(DAG, TLI, LdWidth, WidenVT, LdAlign, WidthDiff);
2252 int NewVTWidth = NewVT.getSizeInBits();
2253 SDValue LdOp = DAG.getLoad(NewVT, dl, Chain, BasePtr, LD->getPointerInfo(),
2254 isVolatile, isNonTemporal, Align);
2255 LdChain.push_back(LdOp.getValue(1));
2257 // Check if we can load the element with one instruction
2258 if (LdWidth <= NewVTWidth) {
2259 if (!NewVT.isVector()) {
2260 unsigned NumElts = WidenWidth / NewVTWidth;
2261 EVT NewVecVT = EVT::getVectorVT(*DAG.getContext(), NewVT, NumElts);
2262 SDValue VecOp = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, NewVecVT, LdOp);
2263 return DAG.getNode(ISD::BITCAST, dl, WidenVT, VecOp);
2265 if (NewVT == WidenVT)
2268 assert(WidenWidth % NewVTWidth == 0);
2269 unsigned NumConcat = WidenWidth / NewVTWidth;
2270 SmallVector<SDValue, 16> ConcatOps(NumConcat);
2271 SDValue UndefVal = DAG.getUNDEF(NewVT);
2272 ConcatOps[0] = LdOp;
2273 for (unsigned i = 1; i != NumConcat; ++i)
2274 ConcatOps[i] = UndefVal;
2275 return DAG.getNode(ISD::CONCAT_VECTORS, dl, WidenVT, &ConcatOps[0],
2279 // Load vector by using multiple loads from largest vector to scalar
2280 SmallVector<SDValue, 16> LdOps;
2281 LdOps.push_back(LdOp);
2283 LdWidth -= NewVTWidth;
2284 unsigned Offset = 0;
2286 while (LdWidth > 0) {
2287 unsigned Increment = NewVTWidth / 8;
2288 Offset += Increment;
2289 BasePtr = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(), BasePtr,
2290 DAG.getIntPtrConstant(Increment));
2292 if (LdWidth < NewVTWidth) {
2293 // Our current type we are using is too large, find a better size
2294 NewVT = FindMemType(DAG, TLI, LdWidth, WidenVT, LdAlign, WidthDiff);
2295 NewVTWidth = NewVT.getSizeInBits();
2298 SDValue LdOp = DAG.getLoad(NewVT, dl, Chain, BasePtr,
2299 LD->getPointerInfo().getWithOffset(Offset),
2301 isNonTemporal, MinAlign(Align, Increment));
2302 LdChain.push_back(LdOp.getValue(1));
2303 LdOps.push_back(LdOp);
2305 LdWidth -= NewVTWidth;
2308 // Build the vector from the loads operations
2309 unsigned End = LdOps.size();
2310 if (!LdOps[0].getValueType().isVector())
2311 // All the loads are scalar loads.
2312 return BuildVectorFromScalar(DAG, WidenVT, LdOps, 0, End);
2314 // If the load contains vectors, build the vector using concat vector.
2315 // All of the vectors used to loads are power of 2 and the scalars load
2316 // can be combined to make a power of 2 vector.
2317 SmallVector<SDValue, 16> ConcatOps(End);
2320 EVT LdTy = LdOps[i].getValueType();
2321 // First combine the scalar loads to a vector
2322 if (!LdTy.isVector()) {
2323 for (--i; i >= 0; --i) {
2324 LdTy = LdOps[i].getValueType();
2325 if (LdTy.isVector())
2328 ConcatOps[--Idx] = BuildVectorFromScalar(DAG, LdTy, LdOps, i+1, End);
2330 ConcatOps[--Idx] = LdOps[i];
2331 for (--i; i >= 0; --i) {
2332 EVT NewLdTy = LdOps[i].getValueType();
2333 if (NewLdTy != LdTy) {
2334 // Create a larger vector
2335 ConcatOps[End-1] = DAG.getNode(ISD::CONCAT_VECTORS, dl, NewLdTy,
2336 &ConcatOps[Idx], End - Idx);
2340 ConcatOps[--Idx] = LdOps[i];
2343 if (WidenWidth == LdTy.getSizeInBits()*(End - Idx))
2344 return DAG.getNode(ISD::CONCAT_VECTORS, dl, WidenVT,
2345 &ConcatOps[Idx], End - Idx);
2347 // We need to fill the rest with undefs to build the vector
2348 unsigned NumOps = WidenWidth / LdTy.getSizeInBits();
2349 SmallVector<SDValue, 16> WidenOps(NumOps);
2350 SDValue UndefVal = DAG.getUNDEF(LdTy);
2353 for (; i != End-Idx; ++i)
2354 WidenOps[i] = ConcatOps[Idx+i];
2355 for (; i != NumOps; ++i)
2356 WidenOps[i] = UndefVal;
2358 return DAG.getNode(ISD::CONCAT_VECTORS, dl, WidenVT, &WidenOps[0],NumOps);
2362 DAGTypeLegalizer::GenWidenVectorExtLoads(SmallVector<SDValue, 16>& LdChain,
2364 ISD::LoadExtType ExtType) {
2365 // For extension loads, it may not be more efficient to chop up the vector
2366 // and then extended it. Instead, we unroll the load and build a new vector.
2367 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(),LD->getValueType(0));
2368 EVT LdVT = LD->getMemoryVT();
2369 DebugLoc dl = LD->getDebugLoc();
2370 assert(LdVT.isVector() && WidenVT.isVector());
2373 SDValue Chain = LD->getChain();
2374 SDValue BasePtr = LD->getBasePtr();
2375 unsigned Align = LD->getAlignment();
2376 bool isVolatile = LD->isVolatile();
2377 bool isNonTemporal = LD->isNonTemporal();
2379 EVT EltVT = WidenVT.getVectorElementType();
2380 EVT LdEltVT = LdVT.getVectorElementType();
2381 unsigned NumElts = LdVT.getVectorNumElements();
2383 // Load each element and widen
2384 unsigned WidenNumElts = WidenVT.getVectorNumElements();
2385 SmallVector<SDValue, 16> Ops(WidenNumElts);
2386 unsigned Increment = LdEltVT.getSizeInBits() / 8;
2387 Ops[0] = DAG.getExtLoad(ExtType, dl, EltVT, Chain, BasePtr,
2388 LD->getPointerInfo(),
2389 LdEltVT, isVolatile, isNonTemporal, Align);
2390 LdChain.push_back(Ops[0].getValue(1));
2391 unsigned i = 0, Offset = Increment;
2392 for (i=1; i < NumElts; ++i, Offset += Increment) {
2393 SDValue NewBasePtr = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(),
2394 BasePtr, DAG.getIntPtrConstant(Offset));
2395 Ops[i] = DAG.getExtLoad(ExtType, dl, EltVT, Chain, NewBasePtr,
2396 LD->getPointerInfo().getWithOffset(Offset), LdEltVT,
2397 isVolatile, isNonTemporal, Align);
2398 LdChain.push_back(Ops[i].getValue(1));
2401 // Fill the rest with undefs
2402 SDValue UndefVal = DAG.getUNDEF(EltVT);
2403 for (; i != WidenNumElts; ++i)
2406 return DAG.getNode(ISD::BUILD_VECTOR, dl, WidenVT, &Ops[0], Ops.size());
2410 void DAGTypeLegalizer::GenWidenVectorStores(SmallVector<SDValue, 16>& StChain,
2412 // The strategy assumes that we can efficiently store powers of two widths.
2413 // The routines chops the vector into the largest vector stores with the same
2414 // element type or scalar stores.
2415 SDValue Chain = ST->getChain();
2416 SDValue BasePtr = ST->getBasePtr();
2417 unsigned Align = ST->getAlignment();
2418 bool isVolatile = ST->isVolatile();
2419 bool isNonTemporal = ST->isNonTemporal();
2420 SDValue ValOp = GetWidenedVector(ST->getValue());
2421 DebugLoc dl = ST->getDebugLoc();
2423 EVT StVT = ST->getMemoryVT();
2424 unsigned StWidth = StVT.getSizeInBits();
2425 EVT ValVT = ValOp.getValueType();
2426 unsigned ValWidth = ValVT.getSizeInBits();
2427 EVT ValEltVT = ValVT.getVectorElementType();
2428 unsigned ValEltWidth = ValEltVT.getSizeInBits();
2429 assert(StVT.getVectorElementType() == ValEltVT);
2431 int Idx = 0; // current index to store
2432 unsigned Offset = 0; // offset from base to store
2433 while (StWidth != 0) {
2434 // Find the largest vector type we can store with
2435 EVT NewVT = FindMemType(DAG, TLI, StWidth, ValVT);
2436 unsigned NewVTWidth = NewVT.getSizeInBits();
2437 unsigned Increment = NewVTWidth / 8;
2438 if (NewVT.isVector()) {
2439 unsigned NumVTElts = NewVT.getVectorNumElements();
2441 SDValue EOp = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, NewVT, ValOp,
2442 DAG.getIntPtrConstant(Idx));
2443 StChain.push_back(DAG.getStore(Chain, dl, EOp, BasePtr,
2444 ST->getPointerInfo().getWithOffset(Offset),
2445 isVolatile, isNonTemporal,
2446 MinAlign(Align, Offset)));
2447 StWidth -= NewVTWidth;
2448 Offset += Increment;
2450 BasePtr = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(), BasePtr,
2451 DAG.getIntPtrConstant(Increment));
2452 } while (StWidth != 0 && StWidth >= NewVTWidth);
2454 // Cast the vector to the scalar type we can store
2455 unsigned NumElts = ValWidth / NewVTWidth;
2456 EVT NewVecVT = EVT::getVectorVT(*DAG.getContext(), NewVT, NumElts);
2457 SDValue VecOp = DAG.getNode(ISD::BITCAST, dl, NewVecVT, ValOp);
2458 // Readjust index position based on new vector type
2459 Idx = Idx * ValEltWidth / NewVTWidth;
2461 SDValue EOp = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, NewVT, VecOp,
2462 DAG.getIntPtrConstant(Idx++));
2463 StChain.push_back(DAG.getStore(Chain, dl, EOp, BasePtr,
2464 ST->getPointerInfo().getWithOffset(Offset),
2465 isVolatile, isNonTemporal,
2466 MinAlign(Align, Offset)));
2467 StWidth -= NewVTWidth;
2468 Offset += Increment;
2469 BasePtr = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(), BasePtr,
2470 DAG.getIntPtrConstant(Increment));
2471 } while (StWidth != 0 && StWidth >= NewVTWidth);
2472 // Restore index back to be relative to the original widen element type
2473 Idx = Idx * NewVTWidth / ValEltWidth;
2479 DAGTypeLegalizer::GenWidenVectorTruncStores(SmallVector<SDValue, 16>& StChain,
2481 // For extension loads, it may not be more efficient to truncate the vector
2482 // and then store it. Instead, we extract each element and then store it.
2483 SDValue Chain = ST->getChain();
2484 SDValue BasePtr = ST->getBasePtr();
2485 unsigned Align = ST->getAlignment();
2486 bool isVolatile = ST->isVolatile();
2487 bool isNonTemporal = ST->isNonTemporal();
2488 SDValue ValOp = GetWidenedVector(ST->getValue());
2489 DebugLoc dl = ST->getDebugLoc();
2491 EVT StVT = ST->getMemoryVT();
2492 EVT ValVT = ValOp.getValueType();
2494 // It must be true that we the widen vector type is bigger than where
2495 // we need to store.
2496 assert(StVT.isVector() && ValOp.getValueType().isVector());
2497 assert(StVT.bitsLT(ValOp.getValueType()));
2499 // For truncating stores, we can not play the tricks of chopping legal
2500 // vector types and bit cast it to the right type. Instead, we unroll
2502 EVT StEltVT = StVT.getVectorElementType();
2503 EVT ValEltVT = ValVT.getVectorElementType();
2504 unsigned Increment = ValEltVT.getSizeInBits() / 8;
2505 unsigned NumElts = StVT.getVectorNumElements();
2506 SDValue EOp = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ValEltVT, ValOp,
2507 DAG.getIntPtrConstant(0));
2508 StChain.push_back(DAG.getTruncStore(Chain, dl, EOp, BasePtr,
2509 ST->getPointerInfo(), StEltVT,
2510 isVolatile, isNonTemporal, Align));
2511 unsigned Offset = Increment;
2512 for (unsigned i=1; i < NumElts; ++i, Offset += Increment) {
2513 SDValue NewBasePtr = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(),
2514 BasePtr, DAG.getIntPtrConstant(Offset));
2515 SDValue EOp = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ValEltVT, ValOp,
2516 DAG.getIntPtrConstant(0));
2517 StChain.push_back(DAG.getTruncStore(Chain, dl, EOp, NewBasePtr,
2518 ST->getPointerInfo().getWithOffset(Offset),
2519 StEltVT, isVolatile, isNonTemporal,
2520 MinAlign(Align, Offset)));
2524 /// Modifies a vector input (widen or narrows) to a vector of NVT. The
2525 /// input vector must have the same element type as NVT.
2526 SDValue DAGTypeLegalizer::ModifyToType(SDValue InOp, EVT NVT) {
2527 // Note that InOp might have been widened so it might already have
2528 // the right width or it might need be narrowed.
2529 EVT InVT = InOp.getValueType();
2530 assert(InVT.getVectorElementType() == NVT.getVectorElementType() &&
2531 "input and widen element type must match");
2532 DebugLoc dl = InOp.getDebugLoc();
2534 // Check if InOp already has the right width.
2538 unsigned InNumElts = InVT.getVectorNumElements();
2539 unsigned WidenNumElts = NVT.getVectorNumElements();
2540 if (WidenNumElts > InNumElts && WidenNumElts % InNumElts == 0) {
2541 unsigned NumConcat = WidenNumElts / InNumElts;
2542 SmallVector<SDValue, 16> Ops(NumConcat);
2543 SDValue UndefVal = DAG.getUNDEF(InVT);
2545 for (unsigned i = 1; i != NumConcat; ++i)
2548 return DAG.getNode(ISD::CONCAT_VECTORS, dl, NVT, &Ops[0], NumConcat);
2551 if (WidenNumElts < InNumElts && InNumElts % WidenNumElts)
2552 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, NVT, InOp,
2553 DAG.getIntPtrConstant(0));
2555 // Fall back to extract and build.
2556 SmallVector<SDValue, 16> Ops(WidenNumElts);
2557 EVT EltVT = NVT.getVectorElementType();
2558 unsigned MinNumElts = std::min(WidenNumElts, InNumElts);
2560 for (Idx = 0; Idx < MinNumElts; ++Idx)
2561 Ops[Idx] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, InOp,
2562 DAG.getIntPtrConstant(Idx));
2564 SDValue UndefVal = DAG.getUNDEF(EltVT);
2565 for ( ; Idx < WidenNumElts; ++Idx)
2566 Ops[Idx] = UndefVal;
2567 return DAG.getNode(ISD::BUILD_VECTOR, dl, NVT, &Ops[0], WidenNumElts);