1 //===------- LegalizeVectorTypes.cpp - Legalization of vector types -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file performs vector type splitting and scalarization for LegalizeTypes.
11 // Scalarization is the act of changing a computation in an illegal one-element
12 // vector type to be a computation in its scalar element type. For example,
13 // implementing <1 x f32> arithmetic in a scalar f32 register. This is needed
14 // as a base case when scalarizing vector arithmetic like <4 x f32>, which
15 // eventually decomposes to scalars if the target doesn't support v4f32 or v2f32
17 // Splitting is the act of changing a computation in an invalid vector type to
18 // be a computation in multiple vectors of a smaller type. For example,
19 // implementing <128 x f32> operations in terms of two <64 x f32> operations.
21 //===----------------------------------------------------------------------===//
23 #include "LegalizeTypes.h"
24 #include "llvm/CodeGen/PseudoSourceValue.h"
25 #include "llvm/Target/TargetData.h"
28 //===----------------------------------------------------------------------===//
29 // Result Vector Scalarization: <1 x ty> -> ty.
30 //===----------------------------------------------------------------------===//
32 void DAGTypeLegalizer::ScalarizeVectorResult(SDNode *N, unsigned ResNo) {
33 DEBUG(cerr << "Scalarize node result " << ResNo << ": "; N->dump(&DAG);
35 SDValue R = SDValue();
37 switch (N->getOpcode()) {
40 cerr << "ScalarizeVectorResult #" << ResNo << ": ";
41 N->dump(&DAG); cerr << "\n";
43 assert(0 && "Do not know how to scalarize the result of this operator!");
46 case ISD::BIT_CONVERT: R = ScalarizeVecRes_BIT_CONVERT(N); break;
47 case ISD::BUILD_VECTOR: R = N->getOperand(0); break;
48 case ISD::CONVERT_RNDSAT: R = ScalarizeVecRes_CONVERT_RNDSAT(N); break;
49 case ISD::EXTRACT_SUBVECTOR: R = ScalarizeVecRes_EXTRACT_SUBVECTOR(N); break;
50 case ISD::FPOWI: R = ScalarizeVecRes_FPOWI(N); break;
51 case ISD::INSERT_VECTOR_ELT: R = ScalarizeVecRes_INSERT_VECTOR_ELT(N); break;
52 case ISD::LOAD: R = ScalarizeVecRes_LOAD(cast<LoadSDNode>(N));break;
53 case ISD::SCALAR_TO_VECTOR: R = ScalarizeVecRes_SCALAR_TO_VECTOR(N); break;
54 case ISD::SELECT: R = ScalarizeVecRes_SELECT(N); break;
55 case ISD::SELECT_CC: R = ScalarizeVecRes_SELECT_CC(N); break;
56 case ISD::UNDEF: R = ScalarizeVecRes_UNDEF(N); break;
57 case ISD::VECTOR_SHUFFLE: R = ScalarizeVecRes_VECTOR_SHUFFLE(N); break;
58 case ISD::VSETCC: R = ScalarizeVecRes_VSETCC(N); break;
78 case ISD::SIGN_EXTEND:
79 case ISD::ZERO_EXTEND:
81 R = ScalarizeVecRes_UnaryOp(N);
100 R = ScalarizeVecRes_BinOp(N);
106 R = ScalarizeVecRes_ShiftOp(N);
110 // If R is null, the sub-method took care of registering the result.
112 SetScalarizedVector(SDValue(N, ResNo), R);
115 SDValue DAGTypeLegalizer::ScalarizeVecRes_BinOp(SDNode *N) {
116 SDValue LHS = GetScalarizedVector(N->getOperand(0));
117 SDValue RHS = GetScalarizedVector(N->getOperand(1));
118 return DAG.getNode(N->getOpcode(), N->getDebugLoc(),
119 LHS.getValueType(), LHS, RHS);
122 SDValue DAGTypeLegalizer::ScalarizeVecRes_ShiftOp(SDNode *N) {
123 SDValue LHS = GetScalarizedVector(N->getOperand(0));
124 SDValue ShiftAmt = GetScalarizedVector(N->getOperand(1));
125 return DAG.getNode(N->getOpcode(), N->getDebugLoc(),
126 LHS.getValueType(), LHS, ShiftAmt);
129 SDValue DAGTypeLegalizer::ScalarizeVecRes_BIT_CONVERT(SDNode *N) {
130 MVT NewVT = N->getValueType(0).getVectorElementType();
131 return DAG.getNode(ISD::BIT_CONVERT, N->getDebugLoc(),
132 NewVT, N->getOperand(0));
135 SDValue DAGTypeLegalizer::ScalarizeVecRes_CONVERT_RNDSAT(SDNode *N) {
136 MVT NewVT = N->getValueType(0).getVectorElementType();
137 SDValue Op0 = GetScalarizedVector(N->getOperand(0));
138 return DAG.getConvertRndSat(NewVT, N->getDebugLoc(),
139 Op0, DAG.getValueType(NewVT),
140 DAG.getValueType(Op0.getValueType()),
143 cast<CvtRndSatSDNode>(N)->getCvtCode());
146 SDValue DAGTypeLegalizer::ScalarizeVecRes_EXTRACT_SUBVECTOR(SDNode *N) {
147 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, N->getDebugLoc(),
148 N->getValueType(0).getVectorElementType(),
149 N->getOperand(0), N->getOperand(1));
152 SDValue DAGTypeLegalizer::ScalarizeVecRes_FPOWI(SDNode *N) {
153 SDValue Op = GetScalarizedVector(N->getOperand(0));
154 return DAG.getNode(ISD::FPOWI, N->getDebugLoc(),
155 Op.getValueType(), Op, N->getOperand(1));
158 SDValue DAGTypeLegalizer::ScalarizeVecRes_INSERT_VECTOR_ELT(SDNode *N) {
159 // The value to insert may have a wider type than the vector element type,
160 // so be sure to truncate it to the element type if necessary.
161 SDValue Op = N->getOperand(1);
162 MVT EltVT = N->getValueType(0).getVectorElementType();
163 if (Op.getValueType() != EltVT)
164 // FIXME: Can this happen for floating point types?
165 Op = DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), EltVT, Op);
169 SDValue DAGTypeLegalizer::ScalarizeVecRes_LOAD(LoadSDNode *N) {
170 assert(N->isUnindexed() && "Indexed vector load?");
172 SDValue Result = DAG.getLoad(ISD::UNINDEXED, N->getDebugLoc(),
173 N->getExtensionType(),
174 N->getValueType(0).getVectorElementType(),
175 N->getChain(), N->getBasePtr(),
176 DAG.getUNDEF(N->getBasePtr().getValueType()),
177 N->getSrcValue(), N->getSrcValueOffset(),
178 N->getMemoryVT().getVectorElementType(),
179 N->isVolatile(), N->getAlignment());
181 // Legalized the chain result - switch anything that used the old chain to
183 ReplaceValueWith(SDValue(N, 1), Result.getValue(1));
187 SDValue DAGTypeLegalizer::ScalarizeVecRes_UnaryOp(SDNode *N) {
188 // Get the dest type - it doesn't always match the input type, e.g. int_to_fp.
189 MVT DestVT = N->getValueType(0).getVectorElementType();
190 SDValue Op = GetScalarizedVector(N->getOperand(0));
191 return DAG.getNode(N->getOpcode(), N->getDebugLoc(), DestVT, Op);
194 SDValue DAGTypeLegalizer::ScalarizeVecRes_SCALAR_TO_VECTOR(SDNode *N) {
195 // If the operand is wider than the vector element type then it is implicitly
196 // truncated. Make that explicit here.
197 MVT EltVT = N->getValueType(0).getVectorElementType();
198 SDValue InOp = N->getOperand(0);
199 if (InOp.getValueType() != EltVT)
200 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), EltVT, InOp);
204 SDValue DAGTypeLegalizer::ScalarizeVecRes_SELECT(SDNode *N) {
205 SDValue LHS = GetScalarizedVector(N->getOperand(1));
206 return DAG.getNode(ISD::SELECT, N->getDebugLoc(),
207 LHS.getValueType(), N->getOperand(0), LHS,
208 GetScalarizedVector(N->getOperand(2)));
211 SDValue DAGTypeLegalizer::ScalarizeVecRes_SELECT_CC(SDNode *N) {
212 SDValue LHS = GetScalarizedVector(N->getOperand(2));
213 return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(), LHS.getValueType(),
214 N->getOperand(0), N->getOperand(1),
215 LHS, GetScalarizedVector(N->getOperand(3)),
219 SDValue DAGTypeLegalizer::ScalarizeVecRes_UNDEF(SDNode *N) {
220 return DAG.getUNDEF(N->getValueType(0).getVectorElementType());
223 SDValue DAGTypeLegalizer::ScalarizeVecRes_VECTOR_SHUFFLE(SDNode *N) {
224 // Figure out if the scalar is the LHS or RHS and return it.
225 SDValue Arg = N->getOperand(2).getOperand(0);
226 if (Arg.getOpcode() == ISD::UNDEF)
227 return DAG.getUNDEF(N->getValueType(0).getVectorElementType());
228 unsigned Op = !cast<ConstantSDNode>(Arg)->isNullValue();
229 return GetScalarizedVector(N->getOperand(Op));
232 SDValue DAGTypeLegalizer::ScalarizeVecRes_VSETCC(SDNode *N) {
233 SDValue LHS = GetScalarizedVector(N->getOperand(0));
234 SDValue RHS = GetScalarizedVector(N->getOperand(1));
235 MVT NVT = N->getValueType(0).getVectorElementType();
236 MVT SVT = TLI.getSetCCResultType(LHS.getValueType());
237 DebugLoc dl = N->getDebugLoc();
239 // Turn it into a scalar SETCC.
240 SDValue Res = DAG.getNode(ISD::SETCC, dl, SVT, LHS, RHS, N->getOperand(2));
242 // VSETCC always returns a sign-extended value, while SETCC may not. The
243 // SETCC result type may not match the vector element type. Correct these.
244 if (NVT.bitsLE(SVT)) {
245 // The SETCC result type is bigger than the vector element type.
246 // Ensure the SETCC result is sign-extended.
247 if (TLI.getBooleanContents() !=
248 TargetLowering::ZeroOrNegativeOneBooleanContent)
249 Res = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, SVT, Res,
250 DAG.getValueType(MVT::i1));
251 // Truncate to the final type.
252 return DAG.getNode(ISD::TRUNCATE, dl, NVT, Res);
254 // The SETCC result type is smaller than the vector element type.
255 // If the SetCC result is not sign-extended, chop it down to MVT::i1.
256 if (TLI.getBooleanContents() !=
257 TargetLowering::ZeroOrNegativeOneBooleanContent)
258 Res = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, Res);
259 // Sign extend to the final type.
260 return DAG.getNode(ISD::SIGN_EXTEND, dl, NVT, Res);
265 //===----------------------------------------------------------------------===//
266 // Operand Vector Scalarization <1 x ty> -> ty.
267 //===----------------------------------------------------------------------===//
269 bool DAGTypeLegalizer::ScalarizeVectorOperand(SDNode *N, unsigned OpNo) {
270 DEBUG(cerr << "Scalarize node operand " << OpNo << ": "; N->dump(&DAG);
272 SDValue Res = SDValue();
274 if (Res.getNode() == 0) {
275 switch (N->getOpcode()) {
278 cerr << "ScalarizeVectorOperand Op #" << OpNo << ": ";
279 N->dump(&DAG); cerr << "\n";
281 assert(0 && "Do not know how to scalarize this operator's operand!");
284 case ISD::BIT_CONVERT:
285 Res = ScalarizeVecOp_BIT_CONVERT(N); break;
287 case ISD::CONCAT_VECTORS:
288 Res = ScalarizeVecOp_CONCAT_VECTORS(N); break;
290 case ISD::EXTRACT_VECTOR_ELT:
291 Res = ScalarizeVecOp_EXTRACT_VECTOR_ELT(N); break;
294 Res = ScalarizeVecOp_STORE(cast<StoreSDNode>(N), OpNo); break;
298 // If the result is null, the sub-method took care of registering results etc.
299 if (!Res.getNode()) return false;
301 // If the result is N, the sub-method updated N in place. Tell the legalizer
303 if (Res.getNode() == N)
306 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 &&
307 "Invalid operand expansion");
309 ReplaceValueWith(SDValue(N, 0), Res);
313 /// ScalarizeVecOp_BIT_CONVERT - If the value to convert is a vector that needs
314 /// to be scalarized, it must be <1 x ty>. Convert the element instead.
315 SDValue DAGTypeLegalizer::ScalarizeVecOp_BIT_CONVERT(SDNode *N) {
316 SDValue Elt = GetScalarizedVector(N->getOperand(0));
317 return DAG.getNode(ISD::BIT_CONVERT, N->getDebugLoc(),
318 N->getValueType(0), Elt);
321 /// ScalarizeVecOp_CONCAT_VECTORS - The vectors to concatenate have length one -
322 /// use a BUILD_VECTOR instead.
323 SDValue DAGTypeLegalizer::ScalarizeVecOp_CONCAT_VECTORS(SDNode *N) {
324 SmallVector<SDValue, 8> Ops(N->getNumOperands());
325 for (unsigned i = 0, e = N->getNumOperands(); i < e; ++i)
326 Ops[i] = GetScalarizedVector(N->getOperand(i));
327 return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), N->getValueType(0),
328 &Ops[0], Ops.size());
331 /// ScalarizeVecOp_EXTRACT_VECTOR_ELT - If the input is a vector that needs to
332 /// be scalarized, it must be <1 x ty>, so just return the element, ignoring the
334 SDValue DAGTypeLegalizer::ScalarizeVecOp_EXTRACT_VECTOR_ELT(SDNode *N) {
335 return GetScalarizedVector(N->getOperand(0));
338 /// ScalarizeVecOp_STORE - If the value to store is a vector that needs to be
339 /// scalarized, it must be <1 x ty>. Just store the element.
340 SDValue DAGTypeLegalizer::ScalarizeVecOp_STORE(StoreSDNode *N, unsigned OpNo){
341 assert(N->isUnindexed() && "Indexed store of one-element vector?");
342 assert(OpNo == 1 && "Do not know how to scalarize this operand!");
343 DebugLoc dl = N->getDebugLoc();
345 if (N->isTruncatingStore())
346 return DAG.getTruncStore(N->getChain(), dl,
347 GetScalarizedVector(N->getOperand(1)),
349 N->getSrcValue(), N->getSrcValueOffset(),
350 N->getMemoryVT().getVectorElementType(),
351 N->isVolatile(), N->getAlignment());
353 return DAG.getStore(N->getChain(), dl, GetScalarizedVector(N->getOperand(1)),
354 N->getBasePtr(), N->getSrcValue(), N->getSrcValueOffset(),
355 N->isVolatile(), N->getAlignment());
359 //===----------------------------------------------------------------------===//
360 // Result Vector Splitting
361 //===----------------------------------------------------------------------===//
363 /// SplitVectorResult - This method is called when the specified result of the
364 /// specified node is found to need vector splitting. At this point, the node
365 /// may also have invalid operands or may have other results that need
366 /// legalization, we just know that (at least) one result needs vector
368 void DAGTypeLegalizer::SplitVectorResult(SDNode *N, unsigned ResNo) {
369 DEBUG(cerr << "Split node result: "; N->dump(&DAG); cerr << "\n");
372 switch (N->getOpcode()) {
375 cerr << "SplitVectorResult #" << ResNo << ": ";
376 N->dump(&DAG); cerr << "\n";
378 assert(0 && "Do not know how to split the result of this operator!");
381 case ISD::MERGE_VALUES: SplitRes_MERGE_VALUES(N, Lo, Hi); break;
382 case ISD::SELECT: SplitRes_SELECT(N, Lo, Hi); break;
383 case ISD::SELECT_CC: SplitRes_SELECT_CC(N, Lo, Hi); break;
384 case ISD::UNDEF: SplitRes_UNDEF(N, Lo, Hi); break;
386 case ISD::BIT_CONVERT: SplitVecRes_BIT_CONVERT(N, Lo, Hi); break;
387 case ISD::BUILD_VECTOR: SplitVecRes_BUILD_VECTOR(N, Lo, Hi); break;
388 case ISD::CONCAT_VECTORS: SplitVecRes_CONCAT_VECTORS(N, Lo, Hi); break;
389 case ISD::CONVERT_RNDSAT: SplitVecRes_CONVERT_RNDSAT(N, Lo, Hi); break;
390 case ISD::EXTRACT_SUBVECTOR: SplitVecRes_EXTRACT_SUBVECTOR(N, Lo, Hi); break;
391 case ISD::FPOWI: SplitVecRes_FPOWI(N, Lo, Hi); break;
392 case ISD::INSERT_VECTOR_ELT: SplitVecRes_INSERT_VECTOR_ELT(N, Lo, Hi); break;
393 case ISD::SCALAR_TO_VECTOR: SplitVecRes_SCALAR_TO_VECTOR(N, Lo, Hi); break;
394 case ISD::LOAD: SplitVecRes_LOAD(cast<LoadSDNode>(N), Lo, Hi);break;
395 case ISD::VECTOR_SHUFFLE:
396 SplitVecRes_VECTOR_SHUFFLE(cast<ShuffleVectorSDNode>(N), Lo, Hi); break;
397 case ISD::VSETCC: SplitVecRes_VSETCC(N, Lo, Hi); break;
411 case ISD::FNEARBYINT:
412 case ISD::FP_TO_SINT:
413 case ISD::FP_TO_UINT:
414 case ISD::SINT_TO_FP:
415 case ISD::UINT_TO_FP:
417 case ISD::SIGN_EXTEND:
418 case ISD::ZERO_EXTEND:
419 case ISD::ANY_EXTEND:
420 SplitVecRes_UnaryOp(N, Lo, Hi);
442 SplitVecRes_BinOp(N, Lo, Hi);
446 // If Lo/Hi is null, the sub-method took care of registering results etc.
448 SetSplitVector(SDValue(N, ResNo), Lo, Hi);
451 void DAGTypeLegalizer::SplitVecRes_BinOp(SDNode *N, SDValue &Lo,
453 SDValue LHSLo, LHSHi;
454 GetSplitVector(N->getOperand(0), LHSLo, LHSHi);
455 SDValue RHSLo, RHSHi;
456 GetSplitVector(N->getOperand(1), RHSLo, RHSHi);
457 DebugLoc dl = N->getDebugLoc();
459 Lo = DAG.getNode(N->getOpcode(), dl, LHSLo.getValueType(), LHSLo, RHSLo);
460 Hi = DAG.getNode(N->getOpcode(), dl, LHSHi.getValueType(), LHSHi, RHSHi);
463 void DAGTypeLegalizer::SplitVecRes_BIT_CONVERT(SDNode *N, SDValue &Lo,
465 // We know the result is a vector. The input may be either a vector or a
468 GetSplitDestVTs(N->getValueType(0), LoVT, HiVT);
469 DebugLoc dl = N->getDebugLoc();
471 SDValue InOp = N->getOperand(0);
472 MVT InVT = InOp.getValueType();
474 // Handle some special cases efficiently.
475 switch (getTypeAction(InVT)) {
477 assert(false && "Unknown type action!");
481 case ScalarizeVector:
485 // A scalar to vector conversion, where the scalar needs expansion.
486 // If the vector is being split in two then we can just convert the
489 GetExpandedOp(InOp, Lo, Hi);
490 if (TLI.isBigEndian())
492 Lo = DAG.getNode(ISD::BIT_CONVERT, dl, LoVT, Lo);
493 Hi = DAG.getNode(ISD::BIT_CONVERT, dl, HiVT, Hi);
498 // If the input is a vector that needs to be split, convert each split
499 // piece of the input now.
500 GetSplitVector(InOp, Lo, Hi);
501 Lo = DAG.getNode(ISD::BIT_CONVERT, dl, LoVT, Lo);
502 Hi = DAG.getNode(ISD::BIT_CONVERT, dl, HiVT, Hi);
506 // In the general case, convert the input to an integer and split it by hand.
507 MVT LoIntVT = MVT::getIntegerVT(LoVT.getSizeInBits());
508 MVT HiIntVT = MVT::getIntegerVT(HiVT.getSizeInBits());
509 if (TLI.isBigEndian())
510 std::swap(LoIntVT, HiIntVT);
512 SplitInteger(BitConvertToInteger(InOp), LoIntVT, HiIntVT, Lo, Hi);
514 if (TLI.isBigEndian())
516 Lo = DAG.getNode(ISD::BIT_CONVERT, dl, LoVT, Lo);
517 Hi = DAG.getNode(ISD::BIT_CONVERT, dl, HiVT, Hi);
520 void DAGTypeLegalizer::SplitVecRes_BUILD_VECTOR(SDNode *N, SDValue &Lo,
523 DebugLoc dl = N->getDebugLoc();
524 GetSplitDestVTs(N->getValueType(0), LoVT, HiVT);
525 unsigned LoNumElts = LoVT.getVectorNumElements();
526 SmallVector<SDValue, 8> LoOps(N->op_begin(), N->op_begin()+LoNumElts);
527 Lo = DAG.getNode(ISD::BUILD_VECTOR, dl, LoVT, &LoOps[0], LoOps.size());
529 SmallVector<SDValue, 8> HiOps(N->op_begin()+LoNumElts, N->op_end());
530 Hi = DAG.getNode(ISD::BUILD_VECTOR, dl, HiVT, &HiOps[0], HiOps.size());
533 void DAGTypeLegalizer::SplitVecRes_CONCAT_VECTORS(SDNode *N, SDValue &Lo,
535 assert(!(N->getNumOperands() & 1) && "Unsupported CONCAT_VECTORS");
536 DebugLoc dl = N->getDebugLoc();
537 unsigned NumSubvectors = N->getNumOperands() / 2;
538 if (NumSubvectors == 1) {
539 Lo = N->getOperand(0);
540 Hi = N->getOperand(1);
545 GetSplitDestVTs(N->getValueType(0), LoVT, HiVT);
547 SmallVector<SDValue, 8> LoOps(N->op_begin(), N->op_begin()+NumSubvectors);
548 Lo = DAG.getNode(ISD::CONCAT_VECTORS, dl, LoVT, &LoOps[0], LoOps.size());
550 SmallVector<SDValue, 8> HiOps(N->op_begin()+NumSubvectors, N->op_end());
551 Hi = DAG.getNode(ISD::CONCAT_VECTORS, dl, HiVT, &HiOps[0], HiOps.size());
554 void DAGTypeLegalizer::SplitVecRes_CONVERT_RNDSAT(SDNode *N, SDValue &Lo,
557 DebugLoc dl = N->getDebugLoc();
558 GetSplitDestVTs(N->getValueType(0), LoVT, HiVT);
560 SDValue DTyOpLo = DAG.getValueType(LoVT);
561 SDValue DTyOpHi = DAG.getValueType(HiVT);
563 SDValue RndOp = N->getOperand(3);
564 SDValue SatOp = N->getOperand(4);
565 ISD::CvtCode CvtCode = cast<CvtRndSatSDNode>(N)->getCvtCode();
569 MVT InVT = N->getOperand(0).getValueType();
570 switch (getTypeAction(InVT)) {
571 default: assert(0 && "Unexpected type action!");
573 assert(LoVT == HiVT && "Legal non-power-of-two vector type?");
574 MVT InNVT = MVT::getVectorVT(InVT.getVectorElementType(),
575 LoVT.getVectorNumElements());
576 VLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, InNVT, N->getOperand(0),
577 DAG.getIntPtrConstant(0));
578 VHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, InNVT, N->getOperand(0),
579 DAG.getIntPtrConstant(InNVT.getVectorNumElements()));
583 GetSplitVector(N->getOperand(0), VLo, VHi);
586 // If the result needs to be split and the input needs to be widened,
587 // the two types must have different lengths. Use the widened result
588 // and extract from it to do the split.
589 assert(LoVT == HiVT && "Legal non-power-of-two vector type?");
590 SDValue InOp = GetWidenedVector(N->getOperand(0));
591 MVT InNVT = MVT::getVectorVT(InVT.getVectorElementType(),
592 LoVT.getVectorNumElements());
593 VLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, InNVT, InOp,
594 DAG.getIntPtrConstant(0));
595 VHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, InNVT, InOp,
596 DAG.getIntPtrConstant(InNVT.getVectorNumElements()));
601 SDValue STyOpLo = DAG.getValueType(VLo.getValueType());
602 SDValue STyOpHi = DAG.getValueType(VHi.getValueType());
604 Lo = DAG.getConvertRndSat(LoVT, dl, VLo, DTyOpLo, STyOpLo, RndOp, SatOp,
606 Hi = DAG.getConvertRndSat(HiVT, dl, VHi, DTyOpHi, STyOpHi, RndOp, SatOp,
610 void DAGTypeLegalizer::SplitVecRes_EXTRACT_SUBVECTOR(SDNode *N, SDValue &Lo,
612 SDValue Vec = N->getOperand(0);
613 SDValue Idx = N->getOperand(1);
614 MVT IdxVT = Idx.getValueType();
615 DebugLoc dl = N->getDebugLoc();
618 GetSplitDestVTs(N->getValueType(0), LoVT, HiVT);
619 // The indices are not guaranteed to be a multiple of the new vector
620 // size unless the original vector type was split in two.
621 assert(LoVT == HiVT && "Non power-of-two vectors not supported!");
623 Lo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, LoVT, Vec, Idx);
624 Idx = DAG.getNode(ISD::ADD, dl, IdxVT, Idx,
625 DAG.getConstant(LoVT.getVectorNumElements(), IdxVT));
626 Hi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, HiVT, Vec, Idx);
629 void DAGTypeLegalizer::SplitVecRes_FPOWI(SDNode *N, SDValue &Lo,
631 DebugLoc dl = N->getDebugLoc();
632 GetSplitVector(N->getOperand(0), Lo, Hi);
633 Lo = DAG.getNode(ISD::FPOWI, dl, Lo.getValueType(), Lo, N->getOperand(1));
634 Hi = DAG.getNode(ISD::FPOWI, dl, Hi.getValueType(), Hi, N->getOperand(1));
637 void DAGTypeLegalizer::SplitVecRes_INSERT_VECTOR_ELT(SDNode *N, SDValue &Lo,
639 SDValue Vec = N->getOperand(0);
640 SDValue Elt = N->getOperand(1);
641 SDValue Idx = N->getOperand(2);
642 DebugLoc dl = N->getDebugLoc();
643 GetSplitVector(Vec, Lo, Hi);
645 if (ConstantSDNode *CIdx = dyn_cast<ConstantSDNode>(Idx)) {
646 unsigned IdxVal = CIdx->getZExtValue();
647 unsigned LoNumElts = Lo.getValueType().getVectorNumElements();
648 if (IdxVal < LoNumElts)
649 Lo = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
650 Lo.getValueType(), Lo, Elt, Idx);
652 Hi = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, Hi.getValueType(), Hi, Elt,
653 DAG.getIntPtrConstant(IdxVal - LoNumElts));
657 // Spill the vector to the stack.
658 MVT VecVT = Vec.getValueType();
659 MVT EltVT = VecVT.getVectorElementType();
660 SDValue StackPtr = DAG.CreateStackTemporary(VecVT);
661 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Vec, StackPtr, NULL, 0);
663 // Store the new element. This may be larger than the vector element type,
664 // so use a truncating store.
665 SDValue EltPtr = GetVectorElementPointer(StackPtr, EltVT, Idx);
667 TLI.getTargetData()->getPrefTypeAlignment(VecVT.getTypeForMVT());
668 Store = DAG.getTruncStore(Store, dl, Elt, EltPtr, NULL, 0, EltVT);
670 // Load the Lo part from the stack slot.
671 Lo = DAG.getLoad(Lo.getValueType(), dl, Store, StackPtr, NULL, 0);
673 // Increment the pointer to the other part.
674 unsigned IncrementSize = Lo.getValueType().getSizeInBits() / 8;
675 StackPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr,
676 DAG.getIntPtrConstant(IncrementSize));
678 // Load the Hi part from the stack slot.
679 Hi = DAG.getLoad(Hi.getValueType(), dl, Store, StackPtr, NULL, 0, false,
680 MinAlign(Alignment, IncrementSize));
683 void DAGTypeLegalizer::SplitVecRes_SCALAR_TO_VECTOR(SDNode *N, SDValue &Lo,
686 DebugLoc dl = N->getDebugLoc();
687 GetSplitDestVTs(N->getValueType(0), LoVT, HiVT);
688 Lo = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LoVT, N->getOperand(0));
689 Hi = DAG.getUNDEF(HiVT);
692 void DAGTypeLegalizer::SplitVecRes_LOAD(LoadSDNode *LD, SDValue &Lo,
694 assert(ISD::isUNINDEXEDLoad(LD) && "Indexed load during type legalization!");
696 DebugLoc dl = LD->getDebugLoc();
697 GetSplitDestVTs(LD->getValueType(0), LoVT, HiVT);
699 ISD::LoadExtType ExtType = LD->getExtensionType();
700 SDValue Ch = LD->getChain();
701 SDValue Ptr = LD->getBasePtr();
702 SDValue Offset = DAG.getUNDEF(Ptr.getValueType());
703 const Value *SV = LD->getSrcValue();
704 int SVOffset = LD->getSrcValueOffset();
705 MVT MemoryVT = LD->getMemoryVT();
706 unsigned Alignment = LD->getAlignment();
707 bool isVolatile = LD->isVolatile();
709 MVT LoMemVT, HiMemVT;
710 GetSplitDestVTs(MemoryVT, LoMemVT, HiMemVT);
712 Lo = DAG.getLoad(ISD::UNINDEXED, dl, ExtType, LoVT, Ch, Ptr, Offset,
713 SV, SVOffset, LoMemVT, isVolatile, Alignment);
715 unsigned IncrementSize = LoMemVT.getSizeInBits()/8;
716 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
717 DAG.getIntPtrConstant(IncrementSize));
718 SVOffset += IncrementSize;
719 Alignment = MinAlign(Alignment, IncrementSize);
720 Hi = DAG.getLoad(ISD::UNINDEXED, dl, ExtType, HiVT, Ch, Ptr, Offset,
721 SV, SVOffset, HiMemVT, isVolatile, Alignment);
723 // Build a factor node to remember that this load is independent of the
725 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
728 // Legalized the chain result - switch anything that used the old chain to
730 ReplaceValueWith(SDValue(LD, 1), Ch);
733 void DAGTypeLegalizer::SplitVecRes_UnaryOp(SDNode *N, SDValue &Lo,
735 // Get the dest types - they may not match the input types, e.g. int_to_fp.
737 DebugLoc dl = N->getDebugLoc();
738 GetSplitDestVTs(N->getValueType(0), LoVT, HiVT);
741 MVT InVT = N->getOperand(0).getValueType();
742 switch (getTypeAction(InVT)) {
743 default: assert(0 && "Unexpected type action!");
745 assert(LoVT == HiVT && "Legal non-power-of-two vector type?");
746 MVT InNVT = MVT::getVectorVT(InVT.getVectorElementType(),
747 LoVT.getVectorNumElements());
748 Lo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, InNVT, N->getOperand(0),
749 DAG.getIntPtrConstant(0));
750 Hi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, InNVT, N->getOperand(0),
751 DAG.getIntPtrConstant(InNVT.getVectorNumElements()));
755 GetSplitVector(N->getOperand(0), Lo, Hi);
758 // If the result needs to be split and the input needs to be widened,
759 // the two types must have different lengths. Use the widened result
760 // and extract from it to do the split.
761 assert(LoVT == HiVT && "Legal non-power-of-two vector type?");
762 SDValue InOp = GetWidenedVector(N->getOperand(0));
763 MVT InNVT = MVT::getVectorVT(InVT.getVectorElementType(),
764 LoVT.getVectorNumElements());
765 Lo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, InNVT, InOp,
766 DAG.getIntPtrConstant(0));
767 Hi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, InNVT, InOp,
768 DAG.getIntPtrConstant(InNVT.getVectorNumElements()));
773 Lo = DAG.getNode(N->getOpcode(), dl, LoVT, Lo);
774 Hi = DAG.getNode(N->getOpcode(), dl, HiVT, Hi);
777 void DAGTypeLegalizer::SplitVecRes_VECTOR_SHUFFLE(ShuffleVectorSDNode *N,
778 SDValue &Lo, SDValue &Hi) {
779 // The low and high parts of the original input give four input vectors.
781 DebugLoc dl = N->getDebugLoc();
782 GetSplitVector(N->getOperand(0), Inputs[0], Inputs[1]);
783 GetSplitVector(N->getOperand(1), Inputs[2], Inputs[3]);
784 MVT NewVT = Inputs[0].getValueType();
785 unsigned NewElts = NewVT.getVectorNumElements();
786 assert(NewVT == Inputs[1].getValueType() &&
787 "Non power-of-two vectors not supported!");
789 // If Lo or Hi uses elements from at most two of the four input vectors, then
790 // express it as a vector shuffle of those two inputs. Otherwise extract the
791 // input elements by hand and construct the Lo/Hi output using a BUILD_VECTOR.
792 SmallVector<int, 16> Ops;
793 for (unsigned High = 0; High < 2; ++High) {
794 SDValue &Output = High ? Hi : Lo;
796 // Build a shuffle mask for the output, discovering on the fly which
797 // input vectors to use as shuffle operands (recorded in InputUsed).
798 // If building a suitable shuffle vector proves too hard, then bail
799 // out with useBuildVector set.
800 unsigned InputUsed[2] = { -1U, -1U }; // Not yet discovered.
801 unsigned FirstMaskIdx = High * NewElts;
802 bool useBuildVector = false;
803 for (unsigned MaskOffset = 0; MaskOffset < NewElts; ++MaskOffset) {
804 // The mask element. This indexes into the input.
805 int Idx = N->getMaskElt(FirstMaskIdx + MaskOffset);
807 // The input vector this mask element indexes into.
808 unsigned Input = (unsigned)Idx / NewElts;
810 if (Input >= array_lengthof(Inputs)) {
811 // The mask element does not index into any input vector.
816 // Turn the index into an offset from the start of the input vector.
817 Idx -= Input * NewElts;
819 // Find or create a shuffle vector operand to hold this input.
821 for (OpNo = 0; OpNo < array_lengthof(InputUsed); ++OpNo) {
822 if (InputUsed[OpNo] == Input) {
823 // This input vector is already an operand.
825 } else if (InputUsed[OpNo] == -1U) {
826 // Create a new operand for this input vector.
827 InputUsed[OpNo] = Input;
832 if (OpNo >= array_lengthof(InputUsed)) {
833 // More than two input vectors used! Give up on trying to create a
834 // shuffle vector. Insert all elements into a BUILD_VECTOR instead.
835 useBuildVector = true;
839 // Add the mask index for the new shuffle vector.
840 Ops.push_back(Idx + OpNo * NewElts);
843 if (useBuildVector) {
844 MVT EltVT = NewVT.getVectorElementType();
845 SmallVector<SDValue, 16> SVOps;
847 // Extract the input elements by hand.
848 for (unsigned MaskOffset = 0; MaskOffset < NewElts; ++MaskOffset) {
849 // The mask element. This indexes into the input.
850 int Idx = N->getMaskElt(FirstMaskIdx + MaskOffset);
852 // The input vector this mask element indexes into.
853 unsigned Input = (unsigned)Idx / NewElts;
855 if (Input >= array_lengthof(Inputs)) {
856 // The mask element is "undef" or indexes off the end of the input.
857 SVOps.push_back(DAG.getUNDEF(EltVT));
861 // Turn the index into an offset from the start of the input vector.
862 Idx -= Input * NewElts;
864 // Extract the vector element by hand.
865 SVOps.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT,
866 Inputs[Input], DAG.getIntPtrConstant(Idx)));
869 // Construct the Lo/Hi output using a BUILD_VECTOR.
870 Output = DAG.getNode(ISD::BUILD_VECTOR,dl,NewVT, &SVOps[0], SVOps.size());
871 } else if (InputUsed[0] == -1U) {
872 // No input vectors were used! The result is undefined.
873 Output = DAG.getUNDEF(NewVT);
875 SDValue Op0 = Inputs[InputUsed[0]];
876 // If only one input was used, use an undefined vector for the other.
877 SDValue Op1 = InputUsed[1] == -1U ?
878 DAG.getUNDEF(NewVT) : Inputs[InputUsed[1]];
879 // At least one input vector was used. Create a new shuffle vector.
880 Output = DAG.getVectorShuffle(NewVT, dl, Op0, Op1, &Ops[0]);
887 void DAGTypeLegalizer::SplitVecRes_VSETCC(SDNode *N, SDValue &Lo,
890 DebugLoc dl = N->getDebugLoc();
891 GetSplitDestVTs(N->getValueType(0), LoVT, HiVT);
893 SDValue LL, LH, RL, RH;
894 GetSplitVector(N->getOperand(0), LL, LH);
895 GetSplitVector(N->getOperand(1), RL, RH);
897 Lo = DAG.getNode(ISD::VSETCC, dl, LoVT, LL, RL, N->getOperand(2));
898 Hi = DAG.getNode(ISD::VSETCC, dl, HiVT, LH, RH, N->getOperand(2));
902 //===----------------------------------------------------------------------===//
903 // Operand Vector Splitting
904 //===----------------------------------------------------------------------===//
906 /// SplitVectorOperand - This method is called when the specified operand of the
907 /// specified node is found to need vector splitting. At this point, all of the
908 /// result types of the node are known to be legal, but other operands of the
909 /// node may need legalization as well as the specified one.
910 bool DAGTypeLegalizer::SplitVectorOperand(SDNode *N, unsigned OpNo) {
911 DEBUG(cerr << "Split node operand: "; N->dump(&DAG); cerr << "\n");
912 SDValue Res = SDValue();
914 if (Res.getNode() == 0) {
915 switch (N->getOpcode()) {
918 cerr << "SplitVectorOperand Op #" << OpNo << ": ";
919 N->dump(&DAG); cerr << "\n";
921 assert(0 && "Do not know how to split this operator's operand!");
924 case ISD::BIT_CONVERT: Res = SplitVecOp_BIT_CONVERT(N); break;
925 case ISD::EXTRACT_SUBVECTOR: Res = SplitVecOp_EXTRACT_SUBVECTOR(N); break;
926 case ISD::EXTRACT_VECTOR_ELT:Res = SplitVecOp_EXTRACT_VECTOR_ELT(N); break;
928 Res = SplitVecOp_STORE(cast<StoreSDNode>(N), OpNo);
934 case ISD::FP_TO_SINT:
935 case ISD::FP_TO_UINT:
936 case ISD::SINT_TO_FP:
937 case ISD::UINT_TO_FP:
939 case ISD::SIGN_EXTEND:
940 case ISD::ZERO_EXTEND:
941 case ISD::ANY_EXTEND:
942 Res = SplitVecOp_UnaryOp(N);
947 // If the result is null, the sub-method took care of registering results etc.
948 if (!Res.getNode()) return false;
950 // If the result is N, the sub-method updated N in place. Tell the legalizer
952 if (Res.getNode() == N)
955 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 &&
956 "Invalid operand expansion");
958 ReplaceValueWith(SDValue(N, 0), Res);
962 SDValue DAGTypeLegalizer::SplitVecOp_UnaryOp(SDNode *N) {
963 // The result has a legal vector type, but the input needs splitting.
964 MVT ResVT = N->getValueType(0);
966 DebugLoc dl = N->getDebugLoc();
967 GetSplitVector(N->getOperand(0), Lo, Hi);
968 assert(Lo.getValueType() == Hi.getValueType() &&
969 "Returns legal non-power-of-two vector type?");
970 MVT InVT = Lo.getValueType();
972 MVT OutVT = MVT::getVectorVT(ResVT.getVectorElementType(),
973 InVT.getVectorNumElements());
975 Lo = DAG.getNode(N->getOpcode(), dl, OutVT, Lo);
976 Hi = DAG.getNode(N->getOpcode(), dl, OutVT, Hi);
978 return DAG.getNode(ISD::CONCAT_VECTORS, dl, ResVT, Lo, Hi);
981 SDValue DAGTypeLegalizer::SplitVecOp_BIT_CONVERT(SDNode *N) {
982 // For example, i64 = BIT_CONVERT v4i16 on alpha. Typically the vector will
983 // end up being split all the way down to individual components. Convert the
984 // split pieces into integers and reassemble.
986 GetSplitVector(N->getOperand(0), Lo, Hi);
987 Lo = BitConvertToInteger(Lo);
988 Hi = BitConvertToInteger(Hi);
990 if (TLI.isBigEndian())
993 return DAG.getNode(ISD::BIT_CONVERT, N->getDebugLoc(), N->getValueType(0),
994 JoinIntegers(Lo, Hi));
997 SDValue DAGTypeLegalizer::SplitVecOp_EXTRACT_SUBVECTOR(SDNode *N) {
998 // We know that the extracted result type is legal. For now, assume the index
1000 MVT SubVT = N->getValueType(0);
1001 SDValue Idx = N->getOperand(1);
1002 DebugLoc dl = N->getDebugLoc();
1004 GetSplitVector(N->getOperand(0), Lo, Hi);
1006 uint64_t LoElts = Lo.getValueType().getVectorNumElements();
1007 uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
1009 if (IdxVal < LoElts) {
1010 assert(IdxVal + SubVT.getVectorNumElements() <= LoElts &&
1011 "Extracted subvector crosses vector split!");
1012 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, Lo, Idx);
1014 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, Hi,
1015 DAG.getConstant(IdxVal - LoElts, Idx.getValueType()));
1019 SDValue DAGTypeLegalizer::SplitVecOp_EXTRACT_VECTOR_ELT(SDNode *N) {
1020 SDValue Vec = N->getOperand(0);
1021 SDValue Idx = N->getOperand(1);
1022 MVT VecVT = Vec.getValueType();
1024 if (isa<ConstantSDNode>(Idx)) {
1025 uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
1026 assert(IdxVal < VecVT.getVectorNumElements() && "Invalid vector index!");
1029 GetSplitVector(Vec, Lo, Hi);
1031 uint64_t LoElts = Lo.getValueType().getVectorNumElements();
1033 if (IdxVal < LoElts)
1034 return DAG.UpdateNodeOperands(SDValue(N, 0), Lo, Idx);
1036 return DAG.UpdateNodeOperands(SDValue(N, 0), Hi,
1037 DAG.getConstant(IdxVal - LoElts,
1038 Idx.getValueType()));
1041 // Store the vector to the stack.
1042 MVT EltVT = VecVT.getVectorElementType();
1043 DebugLoc dl = N->getDebugLoc();
1044 SDValue StackPtr = DAG.CreateStackTemporary(VecVT);
1045 int SPFI = cast<FrameIndexSDNode>(StackPtr.getNode())->getIndex();
1046 const Value *SV = PseudoSourceValue::getFixedStack(SPFI);
1047 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Vec, StackPtr, SV, 0);
1049 // Load back the required element.
1050 StackPtr = GetVectorElementPointer(StackPtr, EltVT, Idx);
1051 return DAG.getLoad(EltVT, dl, Store, StackPtr, SV, 0);
1054 SDValue DAGTypeLegalizer::SplitVecOp_STORE(StoreSDNode *N, unsigned OpNo) {
1055 assert(N->isUnindexed() && "Indexed store of vector?");
1056 assert(OpNo == 1 && "Can only split the stored value");
1057 DebugLoc dl = N->getDebugLoc();
1059 bool isTruncating = N->isTruncatingStore();
1060 SDValue Ch = N->getChain();
1061 SDValue Ptr = N->getBasePtr();
1062 int SVOffset = N->getSrcValueOffset();
1063 MVT MemoryVT = N->getMemoryVT();
1064 unsigned Alignment = N->getAlignment();
1065 bool isVol = N->isVolatile();
1067 GetSplitVector(N->getOperand(1), Lo, Hi);
1069 MVT LoMemVT, HiMemVT;
1070 GetSplitDestVTs(MemoryVT, LoMemVT, HiMemVT);
1072 unsigned IncrementSize = LoMemVT.getSizeInBits()/8;
1075 Lo = DAG.getTruncStore(Ch, dl, Lo, Ptr, N->getSrcValue(), SVOffset,
1076 LoMemVT, isVol, Alignment);
1078 Lo = DAG.getStore(Ch, dl, Lo, Ptr, N->getSrcValue(), SVOffset,
1081 // Increment the pointer to the other half.
1082 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
1083 DAG.getIntPtrConstant(IncrementSize));
1086 Hi = DAG.getTruncStore(Ch, dl, Hi, Ptr,
1087 N->getSrcValue(), SVOffset+IncrementSize,
1089 isVol, MinAlign(Alignment, IncrementSize));
1091 Hi = DAG.getStore(Ch, dl, Hi, Ptr, N->getSrcValue(), SVOffset+IncrementSize,
1092 isVol, MinAlign(Alignment, IncrementSize));
1094 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi);
1098 //===----------------------------------------------------------------------===//
1099 // Result Vector Widening
1100 //===----------------------------------------------------------------------===//
1102 void DAGTypeLegalizer::WidenVectorResult(SDNode *N, unsigned ResNo) {
1103 DEBUG(cerr << "Widen node result " << ResNo << ": "; N->dump(&DAG);
1105 SDValue Res = SDValue();
1107 switch (N->getOpcode()) {
1110 cerr << "WidenVectorResult #" << ResNo << ": ";
1111 N->dump(&DAG); cerr << "\n";
1113 assert(0 && "Do not know how to widen the result of this operator!");
1116 case ISD::BIT_CONVERT: Res = WidenVecRes_BIT_CONVERT(N); break;
1117 case ISD::BUILD_VECTOR: Res = WidenVecRes_BUILD_VECTOR(N); break;
1118 case ISD::CONCAT_VECTORS: Res = WidenVecRes_CONCAT_VECTORS(N); break;
1119 case ISD::CONVERT_RNDSAT: Res = WidenVecRes_CONVERT_RNDSAT(N); break;
1120 case ISD::EXTRACT_SUBVECTOR: Res = WidenVecRes_EXTRACT_SUBVECTOR(N); break;
1121 case ISD::INSERT_VECTOR_ELT: Res = WidenVecRes_INSERT_VECTOR_ELT(N); break;
1122 case ISD::LOAD: Res = WidenVecRes_LOAD(N); break;
1123 case ISD::SCALAR_TO_VECTOR: Res = WidenVecRes_SCALAR_TO_VECTOR(N); break;
1124 case ISD::SELECT: Res = WidenVecRes_SELECT(N); break;
1125 case ISD::SELECT_CC: Res = WidenVecRes_SELECT_CC(N); break;
1126 case ISD::UNDEF: Res = WidenVecRes_UNDEF(N); break;
1127 case ISD::VECTOR_SHUFFLE:
1128 Res = WidenVecRes_VECTOR_SHUFFLE(cast<ShuffleVectorSDNode>(N)); break;
1129 case ISD::VSETCC: Res = WidenVecRes_VSETCC(N); break;
1135 case ISD::FCOPYSIGN:
1152 Res = WidenVecRes_Binary(N);
1158 Res = WidenVecRes_Shift(N);
1162 case ISD::FP_TO_SINT:
1163 case ISD::FP_TO_UINT:
1164 case ISD::SINT_TO_FP:
1165 case ISD::UINT_TO_FP:
1167 case ISD::SIGN_EXTEND:
1168 case ISD::ZERO_EXTEND:
1169 case ISD::ANY_EXTEND:
1170 Res = WidenVecRes_Convert(N);
1181 Res = WidenVecRes_Unary(N);
1185 // If Res is null, the sub-method took care of registering the result.
1187 SetWidenedVector(SDValue(N, ResNo), Res);
1190 SDValue DAGTypeLegalizer::WidenVecRes_Binary(SDNode *N) {
1191 // Binary op widening.
1192 MVT WidenVT = TLI.getTypeToTransformTo(N->getValueType(0));
1193 SDValue InOp1 = GetWidenedVector(N->getOperand(0));
1194 SDValue InOp2 = GetWidenedVector(N->getOperand(1));
1195 return DAG.getNode(N->getOpcode(), N->getDebugLoc(), WidenVT, InOp1, InOp2);
1198 SDValue DAGTypeLegalizer::WidenVecRes_Convert(SDNode *N) {
1199 SDValue InOp = N->getOperand(0);
1200 DebugLoc dl = N->getDebugLoc();
1202 MVT WidenVT = TLI.getTypeToTransformTo(N->getValueType(0));
1203 unsigned WidenNumElts = WidenVT.getVectorNumElements();
1205 MVT InVT = InOp.getValueType();
1206 MVT InEltVT = InVT.getVectorElementType();
1207 MVT InWidenVT = MVT::getVectorVT(InEltVT, WidenNumElts);
1209 unsigned Opcode = N->getOpcode();
1210 unsigned InVTNumElts = InVT.getVectorNumElements();
1212 if (getTypeAction(InVT) == WidenVector) {
1213 InOp = GetWidenedVector(N->getOperand(0));
1214 InVT = InOp.getValueType();
1215 InVTNumElts = InVT.getVectorNumElements();
1216 if (InVTNumElts == WidenNumElts)
1217 return DAG.getNode(Opcode, dl, WidenVT, InOp);
1220 if (TLI.isTypeLegal(InWidenVT)) {
1221 // Because the result and the input are different vector types, widening
1222 // the result could create a legal type but widening the input might make
1223 // it an illegal type that might lead to repeatedly splitting the input
1224 // and then widening it. To avoid this, we widen the input only if
1225 // it results in a legal type.
1226 if (WidenNumElts % InVTNumElts == 0) {
1227 // Widen the input and call convert on the widened input vector.
1228 unsigned NumConcat = WidenNumElts/InVTNumElts;
1229 SmallVector<SDValue, 16> Ops(NumConcat);
1231 SDValue UndefVal = DAG.getUNDEF(InVT);
1232 for (unsigned i = 1; i != NumConcat; ++i)
1234 return DAG.getNode(Opcode, dl, WidenVT,
1235 DAG.getNode(ISD::CONCAT_VECTORS, dl, InWidenVT,
1236 &Ops[0], NumConcat));
1239 if (InVTNumElts % WidenNumElts == 0) {
1240 // Extract the input and convert the shorten input vector.
1241 return DAG.getNode(Opcode, dl, WidenVT,
1242 DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, InWidenVT,
1243 InOp, DAG.getIntPtrConstant(0)));
1247 // Otherwise unroll into some nasty scalar code and rebuild the vector.
1248 SmallVector<SDValue, 16> Ops(WidenNumElts);
1249 MVT EltVT = WidenVT.getVectorElementType();
1250 unsigned MinElts = std::min(InVTNumElts, WidenNumElts);
1252 for (i=0; i < MinElts; ++i)
1253 Ops[i] = DAG.getNode(Opcode, dl, EltVT,
1254 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, InEltVT, InOp,
1255 DAG.getIntPtrConstant(i)));
1257 SDValue UndefVal = DAG.getUNDEF(EltVT);
1258 for (; i < WidenNumElts; ++i)
1261 return DAG.getNode(ISD::BUILD_VECTOR, dl, WidenVT, &Ops[0], WidenNumElts);
1264 SDValue DAGTypeLegalizer::WidenVecRes_Shift(SDNode *N) {
1265 MVT WidenVT = TLI.getTypeToTransformTo(N->getValueType(0));
1266 SDValue InOp = GetWidenedVector(N->getOperand(0));
1267 SDValue ShOp = N->getOperand(1);
1269 MVT ShVT = ShOp.getValueType();
1270 if (getTypeAction(ShVT) == WidenVector) {
1271 ShOp = GetWidenedVector(ShOp);
1272 ShVT = ShOp.getValueType();
1274 MVT ShWidenVT = MVT::getVectorVT(ShVT.getVectorElementType(),
1275 WidenVT.getVectorNumElements());
1276 if (ShVT != ShWidenVT)
1277 ShOp = ModifyToType(ShOp, ShWidenVT);
1279 return DAG.getNode(N->getOpcode(), N->getDebugLoc(), WidenVT, InOp, ShOp);
1282 SDValue DAGTypeLegalizer::WidenVecRes_Unary(SDNode *N) {
1283 // Unary op widening.
1284 MVT WidenVT = TLI.getTypeToTransformTo(N->getValueType(0));
1285 SDValue InOp = GetWidenedVector(N->getOperand(0));
1286 return DAG.getNode(N->getOpcode(), N->getDebugLoc(), WidenVT, InOp);
1289 SDValue DAGTypeLegalizer::WidenVecRes_BIT_CONVERT(SDNode *N) {
1290 SDValue InOp = N->getOperand(0);
1291 MVT InVT = InOp.getValueType();
1292 MVT VT = N->getValueType(0);
1293 MVT WidenVT = TLI.getTypeToTransformTo(VT);
1294 DebugLoc dl = N->getDebugLoc();
1296 switch (getTypeAction(InVT)) {
1298 assert(false && "Unknown type action!");
1302 case PromoteInteger:
1303 // If the InOp is promoted to the same size, convert it. Otherwise,
1304 // fall out of the switch and widen the promoted input.
1305 InOp = GetPromotedInteger(InOp);
1306 InVT = InOp.getValueType();
1307 if (WidenVT.bitsEq(InVT))
1308 return DAG.getNode(ISD::BIT_CONVERT, dl, WidenVT, InOp);
1313 case ScalarizeVector:
1317 // If the InOp is widened to the same size, convert it. Otherwise, fall
1318 // out of the switch and widen the widened input.
1319 InOp = GetWidenedVector(InOp);
1320 InVT = InOp.getValueType();
1321 if (WidenVT.bitsEq(InVT))
1322 // The input widens to the same size. Convert to the widen value.
1323 return DAG.getNode(ISD::BIT_CONVERT, dl, WidenVT, InOp);
1327 unsigned WidenSize = WidenVT.getSizeInBits();
1328 unsigned InSize = InVT.getSizeInBits();
1329 if (WidenSize % InSize == 0) {
1330 // Determine new input vector type. The new input vector type will use
1331 // the same element type (if its a vector) or use the input type as a
1332 // vector. It is the same size as the type to widen to.
1334 unsigned NewNumElts = WidenSize / InSize;
1335 if (InVT.isVector()) {
1336 MVT InEltVT = InVT.getVectorElementType();
1337 NewInVT= MVT::getVectorVT(InEltVT, WidenSize / InEltVT.getSizeInBits());
1339 NewInVT = MVT::getVectorVT(InVT, NewNumElts);
1342 if (TLI.isTypeLegal(NewInVT)) {
1343 // Because the result and the input are different vector types, widening
1344 // the result could create a legal type but widening the input might make
1345 // it an illegal type that might lead to repeatedly splitting the input
1346 // and then widening it. To avoid this, we widen the input only if
1347 // it results in a legal type.
1348 SmallVector<SDValue, 16> Ops(NewNumElts);
1349 SDValue UndefVal = DAG.getUNDEF(InVT);
1351 for (unsigned i = 1; i < NewNumElts; ++i)
1355 if (InVT.isVector())
1356 NewVec = DAG.getNode(ISD::CONCAT_VECTORS, dl,
1357 NewInVT, &Ops[0], NewNumElts);
1359 NewVec = DAG.getNode(ISD::BUILD_VECTOR, dl,
1360 NewInVT, &Ops[0], NewNumElts);
1361 return DAG.getNode(ISD::BIT_CONVERT, dl, WidenVT, NewVec);
1365 // This should occur rarely. Lower the bit-convert to a store/load
1366 // from the stack. Create the stack frame object. Make sure it is aligned
1367 // for both the source and destination types.
1368 SDValue FIPtr = DAG.CreateStackTemporary(InVT, WidenVT);
1369 int FI = cast<FrameIndexSDNode>(FIPtr.getNode())->getIndex();
1370 const Value *SV = PseudoSourceValue::getFixedStack(FI);
1372 // Emit a store to the stack slot.
1373 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, InOp, FIPtr, SV, 0);
1375 // Result is a load from the stack slot.
1376 return DAG.getLoad(WidenVT, dl, Store, FIPtr, SV, 0);
1379 SDValue DAGTypeLegalizer::WidenVecRes_BUILD_VECTOR(SDNode *N) {
1380 DebugLoc dl = N->getDebugLoc();
1381 // Build a vector with undefined for the new nodes.
1382 MVT VT = N->getValueType(0);
1383 MVT EltVT = VT.getVectorElementType();
1384 unsigned NumElts = VT.getVectorNumElements();
1386 MVT WidenVT = TLI.getTypeToTransformTo(VT);
1387 unsigned WidenNumElts = WidenVT.getVectorNumElements();
1389 SmallVector<SDValue, 16> NewOps(N->op_begin(), N->op_end());
1390 NewOps.reserve(WidenNumElts);
1391 for (unsigned i = NumElts; i < WidenNumElts; ++i)
1392 NewOps.push_back(DAG.getUNDEF(EltVT));
1394 return DAG.getNode(ISD::BUILD_VECTOR, dl, WidenVT, &NewOps[0], NewOps.size());
1397 SDValue DAGTypeLegalizer::WidenVecRes_CONCAT_VECTORS(SDNode *N) {
1398 MVT InVT = N->getOperand(0).getValueType();
1399 MVT WidenVT = TLI.getTypeToTransformTo(N->getValueType(0));
1400 DebugLoc dl = N->getDebugLoc();
1401 unsigned WidenNumElts = WidenVT.getVectorNumElements();
1402 unsigned NumOperands = N->getNumOperands();
1404 bool InputWidened = false; // Indicates we need to widen the input.
1405 if (getTypeAction(InVT) != WidenVector) {
1406 if (WidenVT.getVectorNumElements() % InVT.getVectorNumElements() == 0) {
1407 // Add undef vectors to widen to correct length.
1408 unsigned NumConcat = WidenVT.getVectorNumElements() /
1409 InVT.getVectorNumElements();
1410 SDValue UndefVal = DAG.getUNDEF(InVT);
1411 SmallVector<SDValue, 16> Ops(NumConcat);
1412 for (unsigned i=0; i < NumOperands; ++i)
1413 Ops[i] = N->getOperand(i);
1414 for (unsigned i = NumOperands; i != NumConcat; ++i)
1416 return DAG.getNode(ISD::CONCAT_VECTORS, dl, WidenVT, &Ops[0], NumConcat);
1419 InputWidened = true;
1420 if (WidenVT == TLI.getTypeToTransformTo(InVT)) {
1421 // The inputs and the result are widen to the same value.
1423 for (i=1; i < NumOperands; ++i)
1424 if (N->getOperand(i).getOpcode() != ISD::UNDEF)
1427 if (i > NumOperands)
1428 // Everything but the first operand is an UNDEF so just return the
1429 // widened first operand.
1430 return GetWidenedVector(N->getOperand(0));
1432 if (NumOperands == 2) {
1433 // Replace concat of two operands with a shuffle.
1434 SmallVector<int, 16> MaskOps(WidenNumElts);
1435 for (unsigned i=0; i < WidenNumElts/2; ++i) {
1437 MaskOps[i+WidenNumElts/2] = i+WidenNumElts;
1439 return DAG.getVectorShuffle(WidenVT, dl,
1440 GetWidenedVector(N->getOperand(0)),
1441 GetWidenedVector(N->getOperand(1)),
1447 // Fall back to use extracts and build vector.
1448 MVT EltVT = WidenVT.getVectorElementType();
1449 unsigned NumInElts = InVT.getVectorNumElements();
1450 SmallVector<SDValue, 16> Ops(WidenNumElts);
1452 for (unsigned i=0; i < NumOperands; ++i) {
1453 SDValue InOp = N->getOperand(i);
1455 InOp = GetWidenedVector(InOp);
1456 for (unsigned j=0; j < NumInElts; ++j)
1457 Ops[Idx++] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, InOp,
1458 DAG.getIntPtrConstant(j));
1460 SDValue UndefVal = DAG.getUNDEF(EltVT);
1461 for (; Idx < WidenNumElts; ++Idx)
1462 Ops[Idx] = UndefVal;
1463 return DAG.getNode(ISD::BUILD_VECTOR, dl, WidenVT, &Ops[0], WidenNumElts);
1466 SDValue DAGTypeLegalizer::WidenVecRes_CONVERT_RNDSAT(SDNode *N) {
1467 DebugLoc dl = N->getDebugLoc();
1468 SDValue InOp = N->getOperand(0);
1469 SDValue RndOp = N->getOperand(3);
1470 SDValue SatOp = N->getOperand(4);
1472 MVT WidenVT = TLI.getTypeToTransformTo(N->getValueType(0));
1473 unsigned WidenNumElts = WidenVT.getVectorNumElements();
1475 MVT InVT = InOp.getValueType();
1476 MVT InEltVT = InVT.getVectorElementType();
1477 MVT InWidenVT = MVT::getVectorVT(InEltVT, WidenNumElts);
1479 SDValue DTyOp = DAG.getValueType(WidenVT);
1480 SDValue STyOp = DAG.getValueType(InWidenVT);
1481 ISD::CvtCode CvtCode = cast<CvtRndSatSDNode>(N)->getCvtCode();
1483 unsigned InVTNumElts = InVT.getVectorNumElements();
1484 if (getTypeAction(InVT) == WidenVector) {
1485 InOp = GetWidenedVector(InOp);
1486 InVT = InOp.getValueType();
1487 InVTNumElts = InVT.getVectorNumElements();
1488 if (InVTNumElts == WidenNumElts)
1489 return DAG.getConvertRndSat(WidenVT, dl, InOp, DTyOp, STyOp, RndOp,
1493 if (TLI.isTypeLegal(InWidenVT)) {
1494 // Because the result and the input are different vector types, widening
1495 // the result could create a legal type but widening the input might make
1496 // it an illegal type that might lead to repeatedly splitting the input
1497 // and then widening it. To avoid this, we widen the input only if
1498 // it results in a legal type.
1499 if (WidenNumElts % InVTNumElts == 0) {
1500 // Widen the input and call convert on the widened input vector.
1501 unsigned NumConcat = WidenNumElts/InVTNumElts;
1502 SmallVector<SDValue, 16> Ops(NumConcat);
1504 SDValue UndefVal = DAG.getUNDEF(InVT);
1505 for (unsigned i = 1; i != NumConcat; ++i) {
1508 InOp = DAG.getNode(ISD::CONCAT_VECTORS, dl, InWidenVT, &Ops[0],NumConcat);
1509 return DAG.getConvertRndSat(WidenVT, dl, InOp, DTyOp, STyOp, RndOp,
1513 if (InVTNumElts % WidenNumElts == 0) {
1514 // Extract the input and convert the shorten input vector.
1515 InOp = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, InWidenVT, InOp,
1516 DAG.getIntPtrConstant(0));
1517 return DAG.getConvertRndSat(WidenVT, dl, InOp, DTyOp, STyOp, RndOp,
1522 // Otherwise unroll into some nasty scalar code and rebuild the vector.
1523 SmallVector<SDValue, 16> Ops(WidenNumElts);
1524 MVT EltVT = WidenVT.getVectorElementType();
1525 DTyOp = DAG.getValueType(EltVT);
1526 STyOp = DAG.getValueType(InEltVT);
1528 unsigned MinElts = std::min(InVTNumElts, WidenNumElts);
1530 for (i=0; i < MinElts; ++i) {
1531 SDValue ExtVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, InEltVT, InOp,
1532 DAG.getIntPtrConstant(i));
1533 Ops[i] = DAG.getConvertRndSat(WidenVT, dl, ExtVal, DTyOp, STyOp, RndOp,
1537 SDValue UndefVal = DAG.getUNDEF(EltVT);
1538 for (; i < WidenNumElts; ++i)
1541 return DAG.getNode(ISD::BUILD_VECTOR, dl, WidenVT, &Ops[0], WidenNumElts);
1544 SDValue DAGTypeLegalizer::WidenVecRes_EXTRACT_SUBVECTOR(SDNode *N) {
1545 MVT VT = N->getValueType(0);
1546 MVT WidenVT = TLI.getTypeToTransformTo(VT);
1547 unsigned WidenNumElts = WidenVT.getVectorNumElements();
1548 SDValue InOp = N->getOperand(0);
1549 SDValue Idx = N->getOperand(1);
1550 DebugLoc dl = N->getDebugLoc();
1552 if (getTypeAction(InOp.getValueType()) == WidenVector)
1553 InOp = GetWidenedVector(InOp);
1555 MVT InVT = InOp.getValueType();
1557 ConstantSDNode *CIdx = dyn_cast<ConstantSDNode>(Idx);
1559 unsigned IdxVal = CIdx->getZExtValue();
1560 // Check if we can just return the input vector after widening.
1561 if (IdxVal == 0 && InVT == WidenVT)
1564 // Check if we can extract from the vector.
1565 unsigned InNumElts = InVT.getVectorNumElements();
1566 if (IdxVal % WidenNumElts == 0 && IdxVal + WidenNumElts < InNumElts)
1567 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, WidenVT, InOp, Idx);
1570 // We could try widening the input to the right length but for now, extract
1571 // the original elements, fill the rest with undefs and build a vector.
1572 SmallVector<SDValue, 16> Ops(WidenNumElts);
1573 MVT EltVT = VT.getVectorElementType();
1574 MVT IdxVT = Idx.getValueType();
1575 unsigned NumElts = VT.getVectorNumElements();
1578 unsigned IdxVal = CIdx->getZExtValue();
1579 for (i=0; i < NumElts; ++i)
1580 Ops[i] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, InOp,
1581 DAG.getConstant(IdxVal+i, IdxVT));
1583 Ops[0] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, InOp, Idx);
1584 for (i=1; i < NumElts; ++i) {
1585 SDValue NewIdx = DAG.getNode(ISD::ADD, dl, Idx.getValueType(), Idx,
1586 DAG.getConstant(i, IdxVT));
1587 Ops[i] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, InOp, NewIdx);
1591 SDValue UndefVal = DAG.getUNDEF(EltVT);
1592 for (; i < WidenNumElts; ++i)
1594 return DAG.getNode(ISD::BUILD_VECTOR, dl, WidenVT, &Ops[0], WidenNumElts);
1597 SDValue DAGTypeLegalizer::WidenVecRes_INSERT_VECTOR_ELT(SDNode *N) {
1598 SDValue InOp = GetWidenedVector(N->getOperand(0));
1599 return DAG.getNode(ISD::INSERT_VECTOR_ELT, N->getDebugLoc(),
1600 InOp.getValueType(), InOp,
1601 N->getOperand(1), N->getOperand(2));
1604 SDValue DAGTypeLegalizer::WidenVecRes_LOAD(SDNode *N) {
1605 LoadSDNode *LD = cast<LoadSDNode>(N);
1606 MVT WidenVT = TLI.getTypeToTransformTo(LD->getValueType(0));
1607 MVT LdVT = LD->getMemoryVT();
1608 DebugLoc dl = N->getDebugLoc();
1609 assert(LdVT.isVector() && WidenVT.isVector());
1612 SDValue Chain = LD->getChain();
1613 SDValue BasePtr = LD->getBasePtr();
1614 int SVOffset = LD->getSrcValueOffset();
1615 unsigned Align = LD->getAlignment();
1616 bool isVolatile = LD->isVolatile();
1617 const Value *SV = LD->getSrcValue();
1618 ISD::LoadExtType ExtType = LD->getExtensionType();
1621 SmallVector<SDValue, 16> LdChain; // Chain for the series of load
1622 if (ExtType != ISD::NON_EXTLOAD) {
1623 // For extension loads, we can not play the tricks of chopping legal
1624 // vector types and bit cast it to the right type. Instead, we unroll
1625 // the load and build a vector.
1626 MVT EltVT = WidenVT.getVectorElementType();
1627 MVT LdEltVT = LdVT.getVectorElementType();
1628 unsigned NumElts = LdVT.getVectorNumElements();
1630 // Load each element and widen
1631 unsigned WidenNumElts = WidenVT.getVectorNumElements();
1632 SmallVector<SDValue, 16> Ops(WidenNumElts);
1633 unsigned Increment = LdEltVT.getSizeInBits() / 8;
1634 Ops[0] = DAG.getExtLoad(ExtType, dl, EltVT, Chain, BasePtr, SV, SVOffset,
1635 LdEltVT, isVolatile, Align);
1636 LdChain.push_back(Ops[0].getValue(1));
1637 unsigned i = 0, Offset = Increment;
1638 for (i=1; i < NumElts; ++i, Offset += Increment) {
1639 SDValue NewBasePtr = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(),
1640 BasePtr, DAG.getIntPtrConstant(Offset));
1641 Ops[i] = DAG.getExtLoad(ExtType, dl, EltVT, Chain, NewBasePtr, SV,
1642 SVOffset + Offset, LdEltVT, isVolatile, Align);
1643 LdChain.push_back(Ops[i].getValue(1));
1646 // Fill the rest with undefs
1647 SDValue UndefVal = DAG.getUNDEF(EltVT);
1648 for (; i != WidenNumElts; ++i)
1651 Result = DAG.getNode(ISD::BUILD_VECTOR, dl, WidenVT, &Ops[0], Ops.size());
1653 assert(LdVT.getVectorElementType() == WidenVT.getVectorElementType());
1654 unsigned int LdWidth = LdVT.getSizeInBits();
1655 Result = GenWidenVectorLoads(LdChain, Chain, BasePtr, SV, SVOffset,
1656 Align, isVolatile, LdWidth, WidenVT, dl);
1659 // If we generate a single load, we can use that for the chain. Otherwise,
1660 // build a factor node to remember the multiple loads are independent and
1663 if (LdChain.size() == 1)
1664 NewChain = LdChain[0];
1666 NewChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &LdChain[0],
1669 // Modified the chain - switch anything that used the old chain to use
1671 ReplaceValueWith(SDValue(N, 1), Chain);
1676 SDValue DAGTypeLegalizer::WidenVecRes_SCALAR_TO_VECTOR(SDNode *N) {
1677 MVT WidenVT = TLI.getTypeToTransformTo(N->getValueType(0));
1678 return DAG.getNode(ISD::SCALAR_TO_VECTOR, N->getDebugLoc(),
1679 WidenVT, N->getOperand(0));
1682 SDValue DAGTypeLegalizer::WidenVecRes_SELECT(SDNode *N) {
1683 MVT WidenVT = TLI.getTypeToTransformTo(N->getValueType(0));
1684 unsigned WidenNumElts = WidenVT.getVectorNumElements();
1686 SDValue Cond1 = N->getOperand(0);
1687 MVT CondVT = Cond1.getValueType();
1688 if (CondVT.isVector()) {
1689 MVT CondEltVT = CondVT.getVectorElementType();
1690 MVT CondWidenVT = MVT::getVectorVT(CondEltVT, WidenNumElts);
1691 if (getTypeAction(CondVT) == WidenVector)
1692 Cond1 = GetWidenedVector(Cond1);
1694 if (Cond1.getValueType() != CondWidenVT)
1695 Cond1 = ModifyToType(Cond1, CondWidenVT);
1698 SDValue InOp1 = GetWidenedVector(N->getOperand(1));
1699 SDValue InOp2 = GetWidenedVector(N->getOperand(2));
1700 assert(InOp1.getValueType() == WidenVT && InOp2.getValueType() == WidenVT);
1701 return DAG.getNode(ISD::SELECT, N->getDebugLoc(),
1702 WidenVT, Cond1, InOp1, InOp2);
1705 SDValue DAGTypeLegalizer::WidenVecRes_SELECT_CC(SDNode *N) {
1706 SDValue InOp1 = GetWidenedVector(N->getOperand(2));
1707 SDValue InOp2 = GetWidenedVector(N->getOperand(3));
1708 return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(),
1709 InOp1.getValueType(), N->getOperand(0),
1710 N->getOperand(1), InOp1, InOp2, N->getOperand(4));
1713 SDValue DAGTypeLegalizer::WidenVecRes_UNDEF(SDNode *N) {
1714 MVT WidenVT = TLI.getTypeToTransformTo(N->getValueType(0));
1715 return DAG.getUNDEF(WidenVT);
1718 SDValue DAGTypeLegalizer::WidenVecRes_VECTOR_SHUFFLE(ShuffleVectorSDNode *N) {
1719 MVT VT = N->getValueType(0);
1720 DebugLoc dl = N->getDebugLoc();
1722 MVT WidenVT = TLI.getTypeToTransformTo(VT);
1723 unsigned NumElts = VT.getVectorNumElements();
1724 unsigned WidenNumElts = WidenVT.getVectorNumElements();
1726 SDValue InOp1 = GetWidenedVector(N->getOperand(0));
1727 SDValue InOp2 = GetWidenedVector(N->getOperand(1));
1729 // Adjust mask based on new input vector length.
1730 SmallVector<int, 16> NewMask;
1731 for (unsigned i = 0; i != NumElts; ++i) {
1732 int Idx = N->getMaskElt(i);
1733 if (Idx < (int)NumElts)
1734 NewMask.push_back(Idx);
1736 NewMask.push_back(Idx - NumElts + WidenNumElts);
1738 for (unsigned i = NumElts; i != WidenNumElts; ++i)
1739 NewMask.push_back(-1);
1740 return DAG.getVectorShuffle(WidenVT, dl, InOp1, InOp2, &NewMask[0]);
1743 SDValue DAGTypeLegalizer::WidenVecRes_VSETCC(SDNode *N) {
1744 MVT WidenVT = TLI.getTypeToTransformTo(N->getValueType(0));
1745 unsigned WidenNumElts = WidenVT.getVectorNumElements();
1747 SDValue InOp1 = N->getOperand(0);
1748 MVT InVT = InOp1.getValueType();
1749 assert(InVT.isVector() && "can not widen non vector type");
1750 MVT WidenInVT = MVT::getVectorVT(InVT.getVectorElementType(), WidenNumElts);
1751 InOp1 = GetWidenedVector(InOp1);
1752 SDValue InOp2 = GetWidenedVector(N->getOperand(1));
1754 // Assume that the input and output will be widen appropriately. If not,
1755 // we will have to unroll it at some point.
1756 assert(InOp1.getValueType() == WidenInVT &&
1757 InOp2.getValueType() == WidenInVT &&
1758 "Input not widened to expected type!");
1759 return DAG.getNode(ISD::VSETCC, N->getDebugLoc(),
1760 WidenVT, InOp1, InOp2, N->getOperand(2));
1764 //===----------------------------------------------------------------------===//
1765 // Widen Vector Operand
1766 //===----------------------------------------------------------------------===//
1767 bool DAGTypeLegalizer::WidenVectorOperand(SDNode *N, unsigned ResNo) {
1768 DEBUG(cerr << "Widen node operand " << ResNo << ": "; N->dump(&DAG);
1770 SDValue Res = SDValue();
1772 switch (N->getOpcode()) {
1775 cerr << "WidenVectorOperand op #" << ResNo << ": ";
1776 N->dump(&DAG); cerr << "\n";
1778 assert(0 && "Do not know how to widen this operator's operand!");
1781 case ISD::BIT_CONVERT: Res = WidenVecOp_BIT_CONVERT(N); break;
1782 case ISD::CONCAT_VECTORS: Res = WidenVecOp_CONCAT_VECTORS(N); break;
1783 case ISD::EXTRACT_VECTOR_ELT: Res = WidenVecOp_EXTRACT_VECTOR_ELT(N); break;
1784 case ISD::STORE: Res = WidenVecOp_STORE(N); break;
1787 case ISD::FP_TO_SINT:
1788 case ISD::FP_TO_UINT:
1789 case ISD::SINT_TO_FP:
1790 case ISD::UINT_TO_FP:
1792 case ISD::SIGN_EXTEND:
1793 case ISD::ZERO_EXTEND:
1794 case ISD::ANY_EXTEND:
1795 Res = WidenVecOp_Convert(N);
1799 // If Res is null, the sub-method took care of registering the result.
1800 if (!Res.getNode()) return false;
1802 // If the result is N, the sub-method updated N in place. Tell the legalizer
1804 if (Res.getNode() == N)
1808 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 &&
1809 "Invalid operand expansion");
1811 ReplaceValueWith(SDValue(N, 0), Res);
1815 SDValue DAGTypeLegalizer::WidenVecOp_Convert(SDNode *N) {
1816 // Since the result is legal and the input is illegal, it is unlikely
1817 // that we can fix the input to a legal type so unroll the convert
1818 // into some scalar code and create a nasty build vector.
1819 MVT VT = N->getValueType(0);
1820 MVT EltVT = VT.getVectorElementType();
1821 DebugLoc dl = N->getDebugLoc();
1822 unsigned NumElts = VT.getVectorNumElements();
1823 SDValue InOp = N->getOperand(0);
1824 if (getTypeAction(InOp.getValueType()) == WidenVector)
1825 InOp = GetWidenedVector(InOp);
1826 MVT InVT = InOp.getValueType();
1827 MVT InEltVT = InVT.getVectorElementType();
1829 unsigned Opcode = N->getOpcode();
1830 SmallVector<SDValue, 16> Ops(NumElts);
1831 for (unsigned i=0; i < NumElts; ++i)
1832 Ops[i] = DAG.getNode(Opcode, dl, EltVT,
1833 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, InEltVT, InOp,
1834 DAG.getIntPtrConstant(i)));
1836 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &Ops[0], NumElts);
1839 SDValue DAGTypeLegalizer::WidenVecOp_BIT_CONVERT(SDNode *N) {
1840 MVT VT = N->getValueType(0);
1841 SDValue InOp = GetWidenedVector(N->getOperand(0));
1842 MVT InWidenVT = InOp.getValueType();
1843 DebugLoc dl = N->getDebugLoc();
1845 // Check if we can convert between two legal vector types and extract.
1846 unsigned InWidenSize = InWidenVT.getSizeInBits();
1847 unsigned Size = VT.getSizeInBits();
1848 if (InWidenSize % Size == 0 && !VT.isVector()) {
1849 unsigned NewNumElts = InWidenSize / Size;
1850 MVT NewVT = MVT::getVectorVT(VT, NewNumElts);
1851 if (TLI.isTypeLegal(NewVT)) {
1852 SDValue BitOp = DAG.getNode(ISD::BIT_CONVERT, dl, NewVT, InOp);
1853 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, BitOp,
1854 DAG.getIntPtrConstant(0));
1858 // Lower the bit-convert to a store/load from the stack. Create the stack
1859 // frame object. Make sure it is aligned for both the source and destination
1861 SDValue FIPtr = DAG.CreateStackTemporary(InWidenVT, VT);
1862 int FI = cast<FrameIndexSDNode>(FIPtr.getNode())->getIndex();
1863 const Value *SV = PseudoSourceValue::getFixedStack(FI);
1865 // Emit a store to the stack slot.
1866 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, InOp, FIPtr, SV, 0);
1868 // Result is a load from the stack slot.
1869 return DAG.getLoad(VT, dl, Store, FIPtr, SV, 0);
1872 SDValue DAGTypeLegalizer::WidenVecOp_CONCAT_VECTORS(SDNode *N) {
1873 // If the input vector is not legal, it is likely that we will not find a
1874 // legal vector of the same size. Replace the concatenate vector with a
1875 // nasty build vector.
1876 MVT VT = N->getValueType(0);
1877 MVT EltVT = VT.getVectorElementType();
1878 DebugLoc dl = N->getDebugLoc();
1879 unsigned NumElts = VT.getVectorNumElements();
1880 SmallVector<SDValue, 16> Ops(NumElts);
1882 MVT InVT = N->getOperand(0).getValueType();
1883 unsigned NumInElts = InVT.getVectorNumElements();
1886 unsigned NumOperands = N->getNumOperands();
1887 for (unsigned i=0; i < NumOperands; ++i) {
1888 SDValue InOp = N->getOperand(i);
1889 if (getTypeAction(InOp.getValueType()) == WidenVector)
1890 InOp = GetWidenedVector(InOp);
1891 for (unsigned j=0; j < NumInElts; ++j)
1892 Ops[Idx++] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, InOp,
1893 DAG.getIntPtrConstant(j));
1895 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &Ops[0], NumElts);
1898 SDValue DAGTypeLegalizer::WidenVecOp_EXTRACT_VECTOR_ELT(SDNode *N) {
1899 SDValue InOp = GetWidenedVector(N->getOperand(0));
1900 MVT EltVT = InOp.getValueType().getVectorElementType();
1901 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, N->getDebugLoc(),
1902 EltVT, InOp, N->getOperand(1));
1905 SDValue DAGTypeLegalizer::WidenVecOp_STORE(SDNode *N) {
1906 // We have to widen the value but we want only to store the original
1908 StoreSDNode *ST = cast<StoreSDNode>(N);
1909 SDValue Chain = ST->getChain();
1910 SDValue BasePtr = ST->getBasePtr();
1911 const Value *SV = ST->getSrcValue();
1912 int SVOffset = ST->getSrcValueOffset();
1913 unsigned Align = ST->getAlignment();
1914 bool isVolatile = ST->isVolatile();
1915 SDValue ValOp = GetWidenedVector(ST->getValue());
1916 DebugLoc dl = N->getDebugLoc();
1918 MVT StVT = ST->getMemoryVT();
1919 MVT ValVT = ValOp.getValueType();
1920 // It must be true that we the widen vector type is bigger than where
1921 // we need to store.
1922 assert(StVT.isVector() && ValOp.getValueType().isVector());
1923 assert(StVT.bitsLT(ValOp.getValueType()));
1925 SmallVector<SDValue, 16> StChain;
1926 if (ST->isTruncatingStore()) {
1927 // For truncating stores, we can not play the tricks of chopping legal
1928 // vector types and bit cast it to the right type. Instead, we unroll
1930 MVT StEltVT = StVT.getVectorElementType();
1931 MVT ValEltVT = ValVT.getVectorElementType();
1932 unsigned Increment = ValEltVT.getSizeInBits() / 8;
1933 unsigned NumElts = StVT.getVectorNumElements();
1934 SDValue EOp = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ValEltVT, ValOp,
1935 DAG.getIntPtrConstant(0));
1936 StChain.push_back(DAG.getTruncStore(Chain, dl, EOp, BasePtr, SV,
1938 isVolatile, Align));
1939 unsigned Offset = Increment;
1940 for (unsigned i=1; i < NumElts; ++i, Offset += Increment) {
1941 SDValue NewBasePtr = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(),
1942 BasePtr, DAG.getIntPtrConstant(Offset));
1943 SDValue EOp = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ValEltVT, ValOp,
1944 DAG.getIntPtrConstant(0));
1945 StChain.push_back(DAG.getTruncStore(Chain, dl, EOp, NewBasePtr, SV,
1946 SVOffset + Offset, StEltVT,
1947 isVolatile, MinAlign(Align, Offset)));
1951 assert(StVT.getVectorElementType() == ValVT.getVectorElementType());
1953 GenWidenVectorStores(StChain, Chain, BasePtr, SV, SVOffset,
1954 Align, isVolatile, ValOp, StVT.getSizeInBits(), dl);
1956 if (StChain.size() == 1)
1959 return DAG.getNode(ISD::TokenFactor, dl,
1960 MVT::Other,&StChain[0],StChain.size());
1963 //===----------------------------------------------------------------------===//
1964 // Vector Widening Utilities
1965 //===----------------------------------------------------------------------===//
1968 // Utility function to find a vector type and its associated element
1969 // type from a preferred width and whose vector type must be the same size
1971 // TLI: Target lowering used to determine legal types.
1972 // Width: Preferred width to store.
1973 // VecVT: Vector value type whose size we must match.
1974 // Returns NewVecVT and NewEltVT - the vector type and its associated
1976 static void FindAssocWidenVecType(const TargetLowering &TLI, unsigned Width,
1978 MVT& NewEltVT, MVT& NewVecVT) {
1979 unsigned EltWidth = Width + 1;
1980 if (TLI.isTypeLegal(VecVT)) {
1981 // We start with the preferred with, making it a power of 2 and find a
1982 // legal vector type of that width. If not, we reduce it by another of 2.
1983 // For incoming type is legal, this process will end as a vector of the
1984 // smallest loadable type should always be legal.
1986 assert(EltWidth > 0);
1987 EltWidth = 1 << Log2_32(EltWidth - 1);
1988 NewEltVT = MVT::getIntegerVT(EltWidth);
1989 unsigned NumElts = VecVT.getSizeInBits() / EltWidth;
1990 NewVecVT = MVT::getVectorVT(NewEltVT, NumElts);
1991 } while (!TLI.isTypeLegal(NewVecVT) ||
1992 VecVT.getSizeInBits() != NewVecVT.getSizeInBits());
1994 // The incoming vector type is illegal and is the result of widening
1995 // a vector to a power of 2. In this case, we will use the preferred
1996 // with as long as it is a multiple of the incoming vector length.
1997 // The legalization process will eventually make this into a legal type
1998 // and remove the illegal bit converts (which would turn to stack converts
1999 // if they are allow to exist).
2001 assert(EltWidth > 0);
2002 EltWidth = 1 << Log2_32(EltWidth - 1);
2003 NewEltVT = MVT::getIntegerVT(EltWidth);
2004 unsigned NumElts = VecVT.getSizeInBits() / EltWidth;
2005 NewVecVT = MVT::getVectorVT(NewEltVT, NumElts);
2006 } while (!TLI.isTypeLegal(NewEltVT) ||
2007 VecVT.getSizeInBits() != NewVecVT.getSizeInBits());
2011 SDValue DAGTypeLegalizer::GenWidenVectorLoads(SmallVector<SDValue, 16>& LdChain,
2021 // The strategy assumes that we can efficiently load powers of two widths.
2022 // The routines chops the vector into the largest power of 2 load and
2023 // can be inserted into a legal vector and then cast the result into the
2024 // vector type we want. This avoids unnecessary stack converts.
2026 // TODO: If the Ldwidth is legal, alignment is the same as the LdWidth, and
2027 // the load is nonvolatile, we an use a wider load for the value.
2029 // Find the vector type that can load from.
2030 MVT NewEltVT, NewVecVT;
2031 unsigned NewEltVTWidth;
2032 FindAssocWidenVecType(TLI, LdWidth, ResType, NewEltVT, NewVecVT);
2033 NewEltVTWidth = NewEltVT.getSizeInBits();
2035 SDValue LdOp = DAG.getLoad(NewEltVT, dl, Chain, BasePtr, SV, SVOffset,
2036 isVolatile, Alignment);
2037 SDValue VecOp = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, NewVecVT, LdOp);
2038 LdChain.push_back(LdOp.getValue(1));
2040 // Check if we can load the element with one instruction
2041 if (LdWidth == NewEltVTWidth) {
2042 return DAG.getNode(ISD::BIT_CONVERT, dl, ResType, VecOp);
2046 LdWidth -= NewEltVTWidth;
2047 unsigned Offset = 0;
2049 while (LdWidth > 0) {
2050 unsigned Increment = NewEltVTWidth / 8;
2051 Offset += Increment;
2052 BasePtr = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(), BasePtr,
2053 DAG.getIntPtrConstant(Increment));
2055 if (LdWidth < NewEltVTWidth) {
2056 // Our current type we are using is too large, use a smaller size by
2057 // using a smaller power of 2
2058 unsigned oNewEltVTWidth = NewEltVTWidth;
2059 FindAssocWidenVecType(TLI, LdWidth, ResType, NewEltVT, NewVecVT);
2060 NewEltVTWidth = NewEltVT.getSizeInBits();
2061 // Readjust position and vector position based on new load type
2062 Idx = Idx * (oNewEltVTWidth/NewEltVTWidth);
2063 VecOp = DAG.getNode(ISD::BIT_CONVERT, dl, NewVecVT, VecOp);
2066 SDValue LdOp = DAG.getLoad(NewEltVT, dl, Chain, BasePtr, SV,
2067 SVOffset+Offset, isVolatile,
2068 MinAlign(Alignment, Offset));
2069 LdChain.push_back(LdOp.getValue(1));
2070 VecOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, NewVecVT, VecOp, LdOp,
2071 DAG.getIntPtrConstant(Idx++));
2073 LdWidth -= NewEltVTWidth;
2076 return DAG.getNode(ISD::BIT_CONVERT, dl, ResType, VecOp);
2079 void DAGTypeLegalizer::GenWidenVectorStores(SmallVector<SDValue, 16>& StChain,
2089 // Breaks the stores into a series of power of 2 width stores. For any
2090 // width, we convert the vector to the vector of element size that we
2091 // want to store. This avoids requiring a stack convert.
2093 // Find a width of the element type we can store with
2094 MVT WidenVT = ValOp.getValueType();
2095 MVT NewEltVT, NewVecVT;
2097 FindAssocWidenVecType(TLI, StWidth, WidenVT, NewEltVT, NewVecVT);
2098 unsigned NewEltVTWidth = NewEltVT.getSizeInBits();
2100 SDValue VecOp = DAG.getNode(ISD::BIT_CONVERT, dl, NewVecVT, ValOp);
2101 SDValue EOp = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, NewEltVT, VecOp,
2102 DAG.getIntPtrConstant(0));
2103 SDValue StOp = DAG.getStore(Chain, dl, EOp, BasePtr, SV, SVOffset,
2104 isVolatile, Alignment);
2105 StChain.push_back(StOp);
2107 // Check if we are done
2108 if (StWidth == NewEltVTWidth) {
2113 StWidth -= NewEltVTWidth;
2114 unsigned Offset = 0;
2116 while (StWidth > 0) {
2117 unsigned Increment = NewEltVTWidth / 8;
2118 Offset += Increment;
2119 BasePtr = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(), BasePtr,
2120 DAG.getIntPtrConstant(Increment));
2122 if (StWidth < NewEltVTWidth) {
2123 // Our current type we are using is too large, use a smaller size by
2124 // using a smaller power of 2
2125 unsigned oNewEltVTWidth = NewEltVTWidth;
2126 FindAssocWidenVecType(TLI, StWidth, WidenVT, NewEltVT, NewVecVT);
2127 NewEltVTWidth = NewEltVT.getSizeInBits();
2128 // Readjust position and vector position based on new load type
2129 Idx = Idx * (oNewEltVTWidth/NewEltVTWidth);
2130 VecOp = DAG.getNode(ISD::BIT_CONVERT, dl, NewVecVT, VecOp);
2133 EOp = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, NewEltVT, VecOp,
2134 DAG.getIntPtrConstant(Idx++));
2135 StChain.push_back(DAG.getStore(Chain, dl, EOp, BasePtr, SV,
2136 SVOffset + Offset, isVolatile,
2137 MinAlign(Alignment, Offset)));
2138 StWidth -= NewEltVTWidth;
2142 /// Modifies a vector input (widen or narrows) to a vector of NVT. The
2143 /// input vector must have the same element type as NVT.
2144 SDValue DAGTypeLegalizer::ModifyToType(SDValue InOp, MVT NVT) {
2145 // Note that InOp might have been widened so it might already have
2146 // the right width or it might need be narrowed.
2147 MVT InVT = InOp.getValueType();
2148 assert(InVT.getVectorElementType() == NVT.getVectorElementType() &&
2149 "input and widen element type must match");
2150 DebugLoc dl = InOp.getDebugLoc();
2152 // Check if InOp already has the right width.
2156 unsigned InNumElts = InVT.getVectorNumElements();
2157 unsigned WidenNumElts = NVT.getVectorNumElements();
2158 if (WidenNumElts > InNumElts && WidenNumElts % InNumElts == 0) {
2159 unsigned NumConcat = WidenNumElts / InNumElts;
2160 SmallVector<SDValue, 16> Ops(NumConcat);
2161 SDValue UndefVal = DAG.getUNDEF(InVT);
2163 for (unsigned i = 1; i != NumConcat; ++i)
2166 return DAG.getNode(ISD::CONCAT_VECTORS, dl, NVT, &Ops[0], NumConcat);
2169 if (WidenNumElts < InNumElts && InNumElts % WidenNumElts)
2170 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, NVT, InOp,
2171 DAG.getIntPtrConstant(0));
2173 // Fall back to extract and build.
2174 SmallVector<SDValue, 16> Ops(WidenNumElts);
2175 MVT EltVT = NVT.getVectorElementType();
2176 unsigned MinNumElts = std::min(WidenNumElts, InNumElts);
2178 for (Idx = 0; Idx < MinNumElts; ++Idx)
2179 Ops[Idx] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, InOp,
2180 DAG.getIntPtrConstant(Idx));
2182 SDValue UndefVal = DAG.getUNDEF(EltVT);
2183 for ( ; Idx < WidenNumElts; ++Idx)
2184 Ops[Idx] = UndefVal;
2185 return DAG.getNode(ISD::BUILD_VECTOR, dl, NVT, &Ops[0], WidenNumElts);