1 //===------- LegalizeVectorTypes.cpp - Legalization of vector types -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file performs vector type splitting and scalarization for LegalizeTypes.
11 // Scalarization is the act of changing a computation in an illegal one-element
12 // vector type to be a computation in its scalar element type. For example,
13 // implementing <1 x f32> arithmetic in a scalar f32 register. This is needed
14 // as a base case when scalarizing vector arithmetic like <4 x f32>, which
15 // eventually decomposes to scalars if the target doesn't support v4f32 or v2f32
17 // Splitting is the act of changing a computation in an invalid vector type to
18 // be a computation in multiple vectors of a smaller type. For example,
19 // implementing <128 x f32> operations in terms of two <64 x f32> operations.
21 //===----------------------------------------------------------------------===//
23 #include "LegalizeTypes.h"
26 //===----------------------------------------------------------------------===//
27 // Result Vector Scalarization: <1 x ty> -> ty.
28 //===----------------------------------------------------------------------===//
30 void DAGTypeLegalizer::ScalarizeVectorResult(SDNode *N, unsigned ResNo) {
31 DEBUG(cerr << "Scalarize node result " << ResNo << ": "; N->dump(&DAG);
33 SDValue R = SDValue();
35 switch (N->getOpcode()) {
38 cerr << "ScalarizeVectorResult #" << ResNo << ": ";
39 N->dump(&DAG); cerr << "\n";
41 assert(0 && "Do not know how to scalarize the result of this operator!");
44 case ISD::BIT_CONVERT: R = ScalarizeVecRes_BIT_CONVERT(N); break;
45 case ISD::BUILD_VECTOR: R = N->getOperand(0); break;
46 case ISD::CONVERT_RNDSAT: R = ScalarizeVecRes_CONVERT_RNDSAT(N); break;
47 case ISD::EXTRACT_SUBVECTOR: R = ScalarizeVecRes_EXTRACT_SUBVECTOR(N); break;
48 case ISD::FPOWI: R = ScalarizeVecRes_FPOWI(N); break;
49 case ISD::INSERT_VECTOR_ELT: R = ScalarizeVecRes_INSERT_VECTOR_ELT(N); break;
50 case ISD::LOAD: R = ScalarizeVecRes_LOAD(cast<LoadSDNode>(N));break;
51 case ISD::SELECT: R = ScalarizeVecRes_SELECT(N); break;
52 case ISD::SELECT_CC: R = ScalarizeVecRes_SELECT_CC(N); break;
53 case ISD::UNDEF: R = ScalarizeVecRes_UNDEF(N); break;
54 case ISD::VECTOR_SHUFFLE: R = ScalarizeVecRes_VECTOR_SHUFFLE(N); break;
55 case ISD::VSETCC: R = ScalarizeVecRes_VSETCC(N); break;
74 case ISD::UINT_TO_FP: R = ScalarizeVecRes_UnaryOp(N); break;
91 case ISD::XOR: R = ScalarizeVecRes_BinOp(N); break;
94 // If R is null, the sub-method took care of registering the result.
96 SetScalarizedVector(SDValue(N, ResNo), R);
99 SDValue DAGTypeLegalizer::ScalarizeVecRes_BinOp(SDNode *N) {
100 SDValue LHS = GetScalarizedVector(N->getOperand(0));
101 SDValue RHS = GetScalarizedVector(N->getOperand(1));
102 return DAG.getNode(N->getOpcode(), LHS.getValueType(), LHS, RHS);
105 SDValue DAGTypeLegalizer::ScalarizeVecRes_BIT_CONVERT(SDNode *N) {
106 MVT NewVT = N->getValueType(0).getVectorElementType();
107 return DAG.getNode(ISD::BIT_CONVERT, NewVT, N->getOperand(0));
110 SDValue DAGTypeLegalizer::ScalarizeVecRes_CONVERT_RNDSAT(SDNode *N) {
111 MVT NewVT = N->getValueType(0).getVectorElementType();
112 SDValue Op0 = GetScalarizedVector(N->getOperand(0));
113 return DAG.getConvertRndSat(NewVT, Op0, DAG.getValueType(NewVT),
114 DAG.getValueType(Op0.getValueType()),
117 cast<CvtRndSatSDNode>(N)->getCvtCode());
120 SDValue DAGTypeLegalizer::ScalarizeVecRes_EXTRACT_SUBVECTOR(SDNode *N) {
121 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT,
122 N->getValueType(0).getVectorElementType(),
123 N->getOperand(0), N->getOperand(1));
126 SDValue DAGTypeLegalizer::ScalarizeVecRes_FPOWI(SDNode *N) {
127 SDValue Op = GetScalarizedVector(N->getOperand(0));
128 return DAG.getNode(ISD::FPOWI, Op.getValueType(), Op, N->getOperand(1));
131 SDValue DAGTypeLegalizer::ScalarizeVecRes_INSERT_VECTOR_ELT(SDNode *N) {
132 // The value to insert may have a wider type than the vector element type,
133 // so be sure to truncate it to the element type if necessary.
134 SDValue Op = N->getOperand(1);
135 MVT EltVT = N->getValueType(0).getVectorElementType();
136 if (Op.getValueType() != EltVT)
137 // FIXME: Can this happen for floating point types?
138 Op = DAG.getNode(ISD::TRUNCATE, EltVT, Op);
142 SDValue DAGTypeLegalizer::ScalarizeVecRes_LOAD(LoadSDNode *N) {
143 assert(N->isUnindexed() && "Indexed vector load?");
145 SDValue Result = DAG.getLoad(ISD::UNINDEXED, N->getExtensionType(),
146 N->getValueType(0).getVectorElementType(),
147 N->getChain(), N->getBasePtr(),
148 DAG.getNode(ISD::UNDEF,
149 N->getBasePtr().getValueType()),
150 N->getSrcValue(), N->getSrcValueOffset(),
151 N->getMemoryVT().getVectorElementType(),
152 N->isVolatile(), N->getAlignment());
154 // Legalized the chain result - switch anything that used the old chain to
156 ReplaceValueWith(SDValue(N, 1), Result.getValue(1));
160 SDValue DAGTypeLegalizer::ScalarizeVecRes_UnaryOp(SDNode *N) {
161 // Get the dest type - it doesn't always match the input type, e.g. int_to_fp.
162 MVT DestVT = N->getValueType(0).getVectorElementType();
163 SDValue Op = GetScalarizedVector(N->getOperand(0));
164 return DAG.getNode(N->getOpcode(), DestVT, Op);
167 SDValue DAGTypeLegalizer::ScalarizeVecRes_UNDEF(SDNode *N) {
168 return DAG.getNode(ISD::UNDEF, N->getValueType(0).getVectorElementType());
171 SDValue DAGTypeLegalizer::ScalarizeVecRes_SELECT(SDNode *N) {
172 SDValue LHS = GetScalarizedVector(N->getOperand(1));
173 return DAG.getNode(ISD::SELECT, LHS.getValueType(), N->getOperand(0), LHS,
174 GetScalarizedVector(N->getOperand(2)));
177 SDValue DAGTypeLegalizer::ScalarizeVecRes_SELECT_CC(SDNode *N) {
178 SDValue LHS = GetScalarizedVector(N->getOperand(2));
179 return DAG.getNode(ISD::SELECT_CC, LHS.getValueType(),
180 N->getOperand(0), N->getOperand(1),
181 LHS, GetScalarizedVector(N->getOperand(3)),
185 SDValue DAGTypeLegalizer::ScalarizeVecRes_VECTOR_SHUFFLE(SDNode *N) {
186 // Figure out if the scalar is the LHS or RHS and return it.
187 SDValue Arg = N->getOperand(2).getOperand(0);
188 if (Arg.getOpcode() == ISD::UNDEF)
189 return DAG.getNode(ISD::UNDEF, N->getValueType(0).getVectorElementType());
190 unsigned Op = !cast<ConstantSDNode>(Arg)->isNullValue();
191 return GetScalarizedVector(N->getOperand(Op));
194 SDValue DAGTypeLegalizer::ScalarizeVecRes_VSETCC(SDNode *N) {
195 SDValue LHS = GetScalarizedVector(N->getOperand(0));
196 SDValue RHS = GetScalarizedVector(N->getOperand(1));
197 MVT NVT = N->getValueType(0).getVectorElementType();
198 MVT SVT = TLI.getSetCCResultType(LHS);
200 // Turn it into a scalar SETCC.
201 SDValue Res = DAG.getNode(ISD::SETCC, SVT, LHS, RHS, N->getOperand(2));
203 // VSETCC always returns a sign-extended value, while SETCC may not. The
204 // SETCC result type may not match the vector element type. Correct these.
205 if (NVT.bitsLE(SVT)) {
206 // The SETCC result type is bigger than the vector element type.
207 // Ensure the SETCC result is sign-extended.
208 if (TLI.getSetCCResultContents() !=
209 TargetLowering::ZeroOrNegativeOneSetCCResult)
210 Res = DAG.getNode(ISD::SIGN_EXTEND_INREG, SVT, Res,
211 DAG.getValueType(MVT::i1));
212 // Truncate to the final type.
213 return DAG.getNode(ISD::TRUNCATE, NVT, Res);
215 // The SETCC result type is smaller than the vector element type.
216 // If the SetCC result is not sign-extended, chop it down to MVT::i1.
217 if (TLI.getSetCCResultContents() !=
218 TargetLowering::ZeroOrNegativeOneSetCCResult)
219 Res = DAG.getNode(ISD::TRUNCATE, MVT::i1, Res);
220 // Sign extend to the final type.
221 return DAG.getNode(ISD::SIGN_EXTEND, NVT, Res);
226 //===----------------------------------------------------------------------===//
227 // Operand Vector Scalarization <1 x ty> -> ty.
228 //===----------------------------------------------------------------------===//
230 bool DAGTypeLegalizer::ScalarizeVectorOperand(SDNode *N, unsigned OpNo) {
231 DEBUG(cerr << "Scalarize node operand " << OpNo << ": "; N->dump(&DAG);
233 SDValue Res = SDValue();
235 if (Res.getNode() == 0) {
236 switch (N->getOpcode()) {
239 cerr << "ScalarizeVectorOperand Op #" << OpNo << ": ";
240 N->dump(&DAG); cerr << "\n";
242 assert(0 && "Do not know how to scalarize this operator's operand!");
245 case ISD::BIT_CONVERT:
246 Res = ScalarizeVecOp_BIT_CONVERT(N); break;
248 case ISD::CONCAT_VECTORS:
249 Res = ScalarizeVecOp_CONCAT_VECTORS(N); break;
251 case ISD::EXTRACT_VECTOR_ELT:
252 Res = ScalarizeVecOp_EXTRACT_VECTOR_ELT(N); break;
255 Res = ScalarizeVecOp_STORE(cast<StoreSDNode>(N), OpNo); break;
259 // If the result is null, the sub-method took care of registering results etc.
260 if (!Res.getNode()) return false;
262 // If the result is N, the sub-method updated N in place. Check to see if any
263 // operands are new, and if so, mark them.
264 if (Res.getNode() == N) {
265 // Mark N as new and remark N and its operands. This allows us to correctly
266 // revisit N if it needs another step of promotion and allows us to visit
267 // any new operands to N.
272 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 &&
273 "Invalid operand expansion");
275 ReplaceValueWith(SDValue(N, 0), Res);
279 /// ScalarizeVecOp_BIT_CONVERT - If the value to convert is a vector that needs
280 /// to be scalarized, it must be <1 x ty>. Convert the element instead.
281 SDValue DAGTypeLegalizer::ScalarizeVecOp_BIT_CONVERT(SDNode *N) {
282 SDValue Elt = GetScalarizedVector(N->getOperand(0));
283 return DAG.getNode(ISD::BIT_CONVERT, N->getValueType(0), Elt);
286 /// ScalarizeVecOp_CONCAT_VECTORS - The vectors to concatenate have length one -
287 /// use a BUILD_VECTOR instead.
288 SDValue DAGTypeLegalizer::ScalarizeVecOp_CONCAT_VECTORS(SDNode *N) {
289 SmallVector<SDValue, 8> Ops(N->getNumOperands());
290 for (unsigned i = 0, e = N->getNumOperands(); i < e; ++i)
291 Ops[i] = GetScalarizedVector(N->getOperand(i));
292 return DAG.getNode(ISD::BUILD_VECTOR, N->getValueType(0),
293 &Ops[0], Ops.size());
296 /// ScalarizeVecOp_EXTRACT_VECTOR_ELT - If the input is a vector that needs to
297 /// be scalarized, it must be <1 x ty>, so just return the element, ignoring the
299 SDValue DAGTypeLegalizer::ScalarizeVecOp_EXTRACT_VECTOR_ELT(SDNode *N) {
300 return GetScalarizedVector(N->getOperand(0));
303 /// ScalarizeVecOp_STORE - If the value to store is a vector that needs to be
304 /// scalarized, it must be <1 x ty>. Just store the element.
305 SDValue DAGTypeLegalizer::ScalarizeVecOp_STORE(StoreSDNode *N, unsigned OpNo){
306 assert(N->isUnindexed() && "Indexed store of one-element vector?");
307 assert(OpNo == 1 && "Do not know how to scalarize this operand!");
309 if (N->isTruncatingStore())
310 return DAG.getTruncStore(N->getChain(),
311 GetScalarizedVector(N->getOperand(1)),
313 N->getSrcValue(), N->getSrcValueOffset(),
314 N->getMemoryVT().getVectorElementType(),
315 N->isVolatile(), N->getAlignment());
317 return DAG.getStore(N->getChain(), GetScalarizedVector(N->getOperand(1)),
318 N->getBasePtr(), N->getSrcValue(), N->getSrcValueOffset(),
319 N->isVolatile(), N->getAlignment());
323 //===----------------------------------------------------------------------===//
324 // Result Vector Splitting
325 //===----------------------------------------------------------------------===//
327 /// SplitVectorResult - This method is called when the specified result of the
328 /// specified node is found to need vector splitting. At this point, the node
329 /// may also have invalid operands or may have other results that need
330 /// legalization, we just know that (at least) one result needs vector
332 void DAGTypeLegalizer::SplitVectorResult(SDNode *N, unsigned ResNo) {
333 DEBUG(cerr << "Split node result: "; N->dump(&DAG); cerr << "\n");
336 switch (N->getOpcode()) {
339 cerr << "SplitVectorResult #" << ResNo << ": ";
340 N->dump(&DAG); cerr << "\n";
342 assert(0 && "Do not know how to split the result of this operator!");
345 case ISD::MERGE_VALUES: SplitRes_MERGE_VALUES(N, Lo, Hi); break;
346 case ISD::SELECT: SplitRes_SELECT(N, Lo, Hi); break;
347 case ISD::SELECT_CC: SplitRes_SELECT_CC(N, Lo, Hi); break;
348 case ISD::UNDEF: SplitRes_UNDEF(N, Lo, Hi); break;
350 case ISD::BIT_CONVERT: SplitVecRes_BIT_CONVERT(N, Lo, Hi); break;
351 case ISD::BUILD_VECTOR: SplitVecRes_BUILD_VECTOR(N, Lo, Hi); break;
352 case ISD::CONCAT_VECTORS: SplitVecRes_CONCAT_VECTORS(N, Lo, Hi); break;
353 case ISD::CONVERT_RNDSAT: SplitVecRes_CONVERT_RNDSAT(N, Lo, Hi); break;
354 case ISD::EXTRACT_SUBVECTOR: SplitVecRes_EXTRACT_SUBVECTOR(N, Lo, Hi); break;
355 case ISD::FPOWI: SplitVecRes_FPOWI(N, Lo, Hi); break;
356 case ISD::INSERT_VECTOR_ELT: SplitVecRes_INSERT_VECTOR_ELT(N, Lo, Hi); break;
357 case ISD::LOAD: SplitVecRes_LOAD(cast<LoadSDNode>(N), Lo, Hi);break;
358 case ISD::VECTOR_SHUFFLE: SplitVecRes_VECTOR_SHUFFLE(N, Lo, Hi); break;
359 case ISD::VSETCC: SplitVecRes_VSETCC(N, Lo, Hi); break;
373 case ISD::FNEARBYINT:
374 case ISD::FP_TO_SINT:
375 case ISD::FP_TO_UINT:
376 case ISD::SINT_TO_FP:
378 case ISD::UINT_TO_FP: SplitVecRes_UnaryOp(N, Lo, Hi); break;
395 case ISD::FREM: SplitVecRes_BinOp(N, Lo, Hi); break;
398 // If Lo/Hi is null, the sub-method took care of registering results etc.
400 SetSplitVector(SDValue(N, ResNo), Lo, Hi);
403 void DAGTypeLegalizer::SplitVecRes_BinOp(SDNode *N, SDValue &Lo,
405 SDValue LHSLo, LHSHi;
406 GetSplitVector(N->getOperand(0), LHSLo, LHSHi);
407 SDValue RHSLo, RHSHi;
408 GetSplitVector(N->getOperand(1), RHSLo, RHSHi);
410 Lo = DAG.getNode(N->getOpcode(), LHSLo.getValueType(), LHSLo, RHSLo);
411 Hi = DAG.getNode(N->getOpcode(), LHSHi.getValueType(), LHSHi, RHSHi);
414 void DAGTypeLegalizer::SplitVecRes_BIT_CONVERT(SDNode *N, SDValue &Lo,
416 // We know the result is a vector. The input may be either a vector or a
419 GetSplitDestVTs(N->getValueType(0), LoVT, HiVT);
421 SDValue InOp = N->getOperand(0);
422 MVT InVT = InOp.getValueType();
424 // Handle some special cases efficiently.
425 switch (getTypeAction(InVT)) {
427 assert(false && "Unknown type action!");
431 case ScalarizeVector:
435 // A scalar to vector conversion, where the scalar needs expansion.
436 // If the vector is being split in two then we can just convert the
439 GetExpandedOp(InOp, Lo, Hi);
440 if (TLI.isBigEndian())
442 Lo = DAG.getNode(ISD::BIT_CONVERT, LoVT, Lo);
443 Hi = DAG.getNode(ISD::BIT_CONVERT, HiVT, Hi);
448 // If the input is a vector that needs to be split, convert each split
449 // piece of the input now.
450 GetSplitVector(InOp, Lo, Hi);
451 Lo = DAG.getNode(ISD::BIT_CONVERT, LoVT, Lo);
452 Hi = DAG.getNode(ISD::BIT_CONVERT, HiVT, Hi);
456 // In the general case, convert the input to an integer and split it by hand.
457 MVT LoIntVT = MVT::getIntegerVT(LoVT.getSizeInBits());
458 MVT HiIntVT = MVT::getIntegerVT(HiVT.getSizeInBits());
459 if (TLI.isBigEndian())
460 std::swap(LoIntVT, HiIntVT);
462 SplitInteger(BitConvertToInteger(InOp), LoIntVT, HiIntVT, Lo, Hi);
464 if (TLI.isBigEndian())
466 Lo = DAG.getNode(ISD::BIT_CONVERT, LoVT, Lo);
467 Hi = DAG.getNode(ISD::BIT_CONVERT, HiVT, Hi);
470 void DAGTypeLegalizer::SplitVecRes_BUILD_VECTOR(SDNode *N, SDValue &Lo,
473 GetSplitDestVTs(N->getValueType(0), LoVT, HiVT);
474 unsigned LoNumElts = LoVT.getVectorNumElements();
475 SmallVector<SDValue, 8> LoOps(N->op_begin(), N->op_begin()+LoNumElts);
476 Lo = DAG.getNode(ISD::BUILD_VECTOR, LoVT, &LoOps[0], LoOps.size());
478 SmallVector<SDValue, 8> HiOps(N->op_begin()+LoNumElts, N->op_end());
479 Hi = DAG.getNode(ISD::BUILD_VECTOR, HiVT, &HiOps[0], HiOps.size());
482 void DAGTypeLegalizer::SplitVecRes_CONCAT_VECTORS(SDNode *N, SDValue &Lo,
484 assert(!(N->getNumOperands() & 1) && "Unsupported CONCAT_VECTORS");
485 unsigned NumSubvectors = N->getNumOperands() / 2;
486 if (NumSubvectors == 1) {
487 Lo = N->getOperand(0);
488 Hi = N->getOperand(1);
493 GetSplitDestVTs(N->getValueType(0), LoVT, HiVT);
495 SmallVector<SDValue, 8> LoOps(N->op_begin(), N->op_begin()+NumSubvectors);
496 Lo = DAG.getNode(ISD::CONCAT_VECTORS, LoVT, &LoOps[0], LoOps.size());
498 SmallVector<SDValue, 8> HiOps(N->op_begin()+NumSubvectors, N->op_end());
499 Hi = DAG.getNode(ISD::CONCAT_VECTORS, HiVT, &HiOps[0], HiOps.size());
502 void DAGTypeLegalizer::SplitVecRes_CONVERT_RNDSAT(SDNode *N, SDValue &Lo,
505 GetSplitDestVTs(N->getValueType(0), LoVT, HiVT);
507 GetSplitVector(N->getOperand(0), VLo, VHi);
508 SDValue DTyOpLo = DAG.getValueType(LoVT);
509 SDValue DTyOpHi = DAG.getValueType(HiVT);
510 SDValue STyOpLo = DAG.getValueType(VLo.getValueType());
511 SDValue STyOpHi = DAG.getValueType(VHi.getValueType());
513 SDValue RndOp = N->getOperand(3);
514 SDValue SatOp = N->getOperand(4);
515 ISD::CvtCode CvtCode = cast<CvtRndSatSDNode>(N)->getCvtCode();
517 Lo = DAG.getConvertRndSat(LoVT, VLo, DTyOpLo, STyOpLo, RndOp, SatOp, CvtCode);
518 Hi = DAG.getConvertRndSat(HiVT, VHi, DTyOpHi, STyOpHi, RndOp, SatOp, CvtCode);
521 void DAGTypeLegalizer::SplitVecRes_EXTRACT_SUBVECTOR(SDNode *N, SDValue &Lo,
523 SDValue Vec = N->getOperand(0);
524 SDValue Idx = N->getOperand(1);
525 MVT IdxVT = Idx.getValueType();
528 GetSplitDestVTs(N->getValueType(0), LoVT, HiVT);
529 // The indices are not guaranteed to be a multiple of the new vector
530 // size unless the original vector type was split in two.
531 assert(LoVT == HiVT && "Non power-of-two vectors not supported!");
533 Lo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, LoVT, Vec, Idx);
534 Idx = DAG.getNode(ISD::ADD, IdxVT, Idx,
535 DAG.getConstant(LoVT.getVectorNumElements(), IdxVT));
536 Hi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, HiVT, Vec, Idx);
539 void DAGTypeLegalizer::SplitVecRes_FPOWI(SDNode *N, SDValue &Lo,
541 GetSplitVector(N->getOperand(0), Lo, Hi);
542 Lo = DAG.getNode(ISD::FPOWI, Lo.getValueType(), Lo, N->getOperand(1));
543 Hi = DAG.getNode(ISD::FPOWI, Hi.getValueType(), Hi, N->getOperand(1));
546 void DAGTypeLegalizer::SplitVecRes_INSERT_VECTOR_ELT(SDNode *N, SDValue &Lo,
548 SDValue Vec = N->getOperand(0);
549 SDValue Elt = N->getOperand(1);
550 SDValue Idx = N->getOperand(2);
551 GetSplitVector(Vec, Lo, Hi);
553 if (ConstantSDNode *CIdx = dyn_cast<ConstantSDNode>(Idx)) {
554 unsigned IdxVal = CIdx->getZExtValue();
555 unsigned LoNumElts = Lo.getValueType().getVectorNumElements();
556 if (IdxVal < LoNumElts)
557 Lo = DAG.getNode(ISD::INSERT_VECTOR_ELT, Lo.getValueType(), Lo, Elt, Idx);
559 Hi = DAG.getNode(ISD::INSERT_VECTOR_ELT, Hi.getValueType(), Hi, Elt,
560 DAG.getIntPtrConstant(IdxVal - LoNumElts));
564 // Spill the vector to the stack.
565 MVT VecVT = Vec.getValueType();
566 MVT EltVT = VecVT.getVectorElementType();
567 SDValue StackPtr = DAG.CreateStackTemporary(VecVT);
568 SDValue Store = DAG.getStore(DAG.getEntryNode(), Vec, StackPtr, NULL, 0);
570 // Store the new element. This may be larger than the vector element type,
571 // so use a truncating store.
572 SDValue EltPtr = GetVectorElementPointer(StackPtr, EltVT, Idx);
573 Store = DAG.getTruncStore(Store, Elt, EltPtr, NULL, 0, EltVT);
575 // Reload the vector from the stack.
576 SDValue Load = DAG.getLoad(VecVT, Store, StackPtr, NULL, 0);
579 SplitVecRes_LOAD(cast<LoadSDNode>(Load.getNode()), Lo, Hi);
582 void DAGTypeLegalizer::SplitVecRes_LOAD(LoadSDNode *LD, SDValue &Lo,
584 assert(ISD::isUNINDEXEDLoad(LD) && "Indexed load during type legalization!");
586 GetSplitDestVTs(LD->getValueType(0), LoVT, HiVT);
588 ISD::LoadExtType ExtType = LD->getExtensionType();
589 SDValue Ch = LD->getChain();
590 SDValue Ptr = LD->getBasePtr();
591 SDValue Offset = DAG.getNode(ISD::UNDEF, Ptr.getValueType());
592 const Value *SV = LD->getSrcValue();
593 int SVOffset = LD->getSrcValueOffset();
594 MVT MemoryVT = LD->getMemoryVT();
595 unsigned Alignment = LD->getAlignment();
596 bool isVolatile = LD->isVolatile();
598 MVT LoMemVT, HiMemVT;
599 GetSplitDestVTs(MemoryVT, LoMemVT, HiMemVT);
601 Lo = DAG.getLoad(ISD::UNINDEXED, ExtType, LoVT, Ch, Ptr, Offset,
602 SV, SVOffset, LoMemVT, isVolatile, Alignment);
604 unsigned IncrementSize = LoMemVT.getSizeInBits()/8;
605 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
606 DAG.getIntPtrConstant(IncrementSize));
607 SVOffset += IncrementSize;
608 Alignment = MinAlign(Alignment, IncrementSize);
609 Hi = DAG.getLoad(ISD::UNINDEXED, ExtType, HiVT, Ch, Ptr, Offset,
610 SV, SVOffset, HiMemVT, isVolatile, Alignment);
612 // Build a factor node to remember that this load is independent of the
614 Ch = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
617 // Legalized the chain result - switch anything that used the old chain to
619 ReplaceValueWith(SDValue(LD, 1), Ch);
622 void DAGTypeLegalizer::SplitVecRes_UnaryOp(SDNode *N, SDValue &Lo,
624 // Get the dest types - they may not match the input types, e.g. int_to_fp.
626 GetSplitDestVTs(N->getValueType(0), LoVT, HiVT);
629 MVT InVT = N->getOperand(0).getValueType();
630 switch (getTypeAction(InVT)) {
631 default: assert(0 && "Unexpected type action!");
633 assert(LoVT == HiVT && "Legal non-power-of-two vector type?");
634 MVT InNVT = MVT::getVectorVT(InVT.getVectorElementType(),
635 LoVT.getVectorNumElements());
636 Lo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, InNVT, N->getOperand(0),
637 DAG.getIntPtrConstant(0));
638 Hi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, InNVT, N->getOperand(0),
639 DAG.getIntPtrConstant(InNVT.getVectorNumElements()));
643 GetSplitVector(N->getOperand(0), Lo, Hi);
647 Lo = DAG.getNode(N->getOpcode(), LoVT, Lo);
648 Hi = DAG.getNode(N->getOpcode(), HiVT, Hi);
651 void DAGTypeLegalizer::SplitVecRes_VECTOR_SHUFFLE(SDNode *N, SDValue &Lo,
653 // The low and high parts of the original input give four input vectors.
655 GetSplitVector(N->getOperand(0), Inputs[0], Inputs[1]);
656 GetSplitVector(N->getOperand(1), Inputs[2], Inputs[3]);
657 MVT NewVT = Inputs[0].getValueType();
658 unsigned NewElts = NewVT.getVectorNumElements();
659 assert(NewVT == Inputs[1].getValueType() &&
660 "Non power-of-two vectors not supported!");
662 // If Lo or Hi uses elements from at most two of the four input vectors, then
663 // express it as a vector shuffle of those two inputs. Otherwise extract the
664 // input elements by hand and construct the Lo/Hi output using a BUILD_VECTOR.
665 SDValue Mask = N->getOperand(2);
666 MVT IdxVT = Mask.getValueType().getVectorElementType();
667 SmallVector<SDValue, 16> Ops;
668 Ops.reserve(NewElts);
669 for (unsigned High = 0; High < 2; ++High) {
670 SDValue &Output = High ? Hi : Lo;
672 // Build a shuffle mask for the output, discovering on the fly which
673 // input vectors to use as shuffle operands (recorded in InputUsed).
674 // If building a suitable shuffle vector proves too hard, then bail
675 // out with useBuildVector set.
676 unsigned InputUsed[2] = { -1U, -1U }; // Not yet discovered.
677 unsigned FirstMaskIdx = High * NewElts;
678 bool useBuildVector = false;
679 for (unsigned MaskOffset = 0; MaskOffset < NewElts; ++MaskOffset) {
680 SDValue Arg = Mask.getOperand(FirstMaskIdx + MaskOffset);
682 // The mask element. This indexes into the input.
683 unsigned Idx = Arg.getOpcode() == ISD::UNDEF ?
684 -1U : cast<ConstantSDNode>(Arg)->getZExtValue();
686 // The input vector this mask element indexes into.
687 unsigned Input = Idx / NewElts;
689 if (Input >= array_lengthof(Inputs)) {
690 // The mask element does not index into any input vector.
691 Ops.push_back(DAG.getNode(ISD::UNDEF, IdxVT));
695 // Turn the index into an offset from the start of the input vector.
696 Idx -= Input * NewElts;
698 // Find or create a shuffle vector operand to hold this input.
700 for (OpNo = 0; OpNo < array_lengthof(InputUsed); ++OpNo) {
701 if (InputUsed[OpNo] == Input) {
702 // This input vector is already an operand.
704 } else if (InputUsed[OpNo] == -1U) {
705 // Create a new operand for this input vector.
706 InputUsed[OpNo] = Input;
711 if (OpNo >= array_lengthof(InputUsed)) {
712 // More than two input vectors used! Give up on trying to create a
713 // shuffle vector. Insert all elements into a BUILD_VECTOR instead.
714 useBuildVector = true;
718 // Add the mask index for the new shuffle vector.
719 Ops.push_back(DAG.getConstant(Idx + OpNo * NewElts, IdxVT));
722 if (useBuildVector) {
723 MVT EltVT = NewVT.getVectorElementType();
726 // Extract the input elements by hand.
727 for (unsigned MaskOffset = 0; MaskOffset < NewElts; ++MaskOffset) {
728 SDValue Arg = Mask.getOperand(FirstMaskIdx + MaskOffset);
730 // The mask element. This indexes into the input.
731 unsigned Idx = Arg.getOpcode() == ISD::UNDEF ?
732 -1U : cast<ConstantSDNode>(Arg)->getZExtValue();
734 // The input vector this mask element indexes into.
735 unsigned Input = Idx / NewElts;
737 if (Input >= array_lengthof(Inputs)) {
738 // The mask element is "undef" or indexes off the end of the input.
739 Ops.push_back(DAG.getNode(ISD::UNDEF, EltVT));
743 // Turn the index into an offset from the start of the input vector.
744 Idx -= Input * NewElts;
746 // Extract the vector element by hand.
747 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT,
748 Inputs[Input], DAG.getIntPtrConstant(Idx)));
751 // Construct the Lo/Hi output using a BUILD_VECTOR.
752 Output = DAG.getNode(ISD::BUILD_VECTOR, NewVT, &Ops[0], Ops.size());
753 } else if (InputUsed[0] == -1U) {
754 // No input vectors were used! The result is undefined.
755 Output = DAG.getNode(ISD::UNDEF, NewVT);
757 // At least one input vector was used. Create a new shuffle vector.
758 SDValue NewMask = DAG.getNode(ISD::BUILD_VECTOR,
759 MVT::getVectorVT(IdxVT, Ops.size()),
760 &Ops[0], Ops.size());
761 SDValue Op0 = Inputs[InputUsed[0]];
762 // If only one input was used, use an undefined vector for the other.
763 SDValue Op1 = InputUsed[1] == -1U ?
764 DAG.getNode(ISD::UNDEF, NewVT) : Inputs[InputUsed[1]];
765 Output = DAG.getNode(ISD::VECTOR_SHUFFLE, NewVT, Op0, Op1, NewMask);
772 void DAGTypeLegalizer::SplitVecRes_VSETCC(SDNode *N, SDValue &Lo,
775 GetSplitDestVTs(N->getValueType(0), LoVT, HiVT);
777 SDValue LL, LH, RL, RH;
778 GetSplitVector(N->getOperand(0), LL, LH);
779 GetSplitVector(N->getOperand(1), RL, RH);
781 Lo = DAG.getNode(ISD::VSETCC, LoVT, LL, RL, N->getOperand(2));
782 Hi = DAG.getNode(ISD::VSETCC, HiVT, LH, RH, N->getOperand(2));
786 //===----------------------------------------------------------------------===//
787 // Operand Vector Splitting
788 //===----------------------------------------------------------------------===//
790 /// SplitVectorOperand - This method is called when the specified operand of the
791 /// specified node is found to need vector splitting. At this point, all of the
792 /// result types of the node are known to be legal, but other operands of the
793 /// node may need legalization as well as the specified one.
794 bool DAGTypeLegalizer::SplitVectorOperand(SDNode *N, unsigned OpNo) {
795 DEBUG(cerr << "Split node operand: "; N->dump(&DAG); cerr << "\n");
796 SDValue Res = SDValue();
798 if (Res.getNode() == 0) {
799 switch (N->getOpcode()) {
802 cerr << "SplitVectorOperand Op #" << OpNo << ": ";
803 N->dump(&DAG); cerr << "\n";
805 assert(0 && "Do not know how to split this operator's operand!");
808 case ISD::BIT_CONVERT: Res = SplitVecOp_BIT_CONVERT(N); break;
809 case ISD::EXTRACT_SUBVECTOR: Res = SplitVecOp_EXTRACT_SUBVECTOR(N); break;
810 case ISD::EXTRACT_VECTOR_ELT:Res = SplitVecOp_EXTRACT_VECTOR_ELT(N); break;
811 case ISD::STORE: Res = SplitVecOp_STORE(cast<StoreSDNode>(N),
813 case ISD::VECTOR_SHUFFLE: Res = SplitVecOp_VECTOR_SHUFFLE(N, OpNo);break;
818 case ISD::FP_TO_SINT:
819 case ISD::FP_TO_UINT:
820 case ISD::SINT_TO_FP:
822 case ISD::UINT_TO_FP: Res = SplitVecOp_UnaryOp(N); break;
826 // If the result is null, the sub-method took care of registering results etc.
827 if (!Res.getNode()) return false;
829 // If the result is N, the sub-method updated N in place. Check to see if any
830 // operands are new, and if so, mark them.
831 if (Res.getNode() == N) {
832 // Mark N as new and remark N and its operands. This allows us to correctly
833 // revisit N if it needs another step of promotion and allows us to visit
834 // any new operands to N.
839 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 &&
840 "Invalid operand expansion");
842 ReplaceValueWith(SDValue(N, 0), Res);
846 SDValue DAGTypeLegalizer::SplitVecOp_UnaryOp(SDNode *N) {
847 // The result has a legal vector type, but the input needs splitting.
848 MVT ResVT = N->getValueType(0);
850 GetSplitVector(N->getOperand(0), Lo, Hi);
851 assert(Lo.getValueType() == Hi.getValueType() &&
852 "Returns legal non-power-of-two vector type?");
853 MVT InVT = Lo.getValueType();
855 MVT OutVT = MVT::getVectorVT(ResVT.getVectorElementType(),
856 InVT.getVectorNumElements());
858 Lo = DAG.getNode(N->getOpcode(), OutVT, Lo);
859 Hi = DAG.getNode(N->getOpcode(), OutVT, Hi);
861 return DAG.getNode(ISD::CONCAT_VECTORS, ResVT, Lo, Hi);
864 SDValue DAGTypeLegalizer::SplitVecOp_BIT_CONVERT(SDNode *N) {
865 // For example, i64 = BIT_CONVERT v4i16 on alpha. Typically the vector will
866 // end up being split all the way down to individual components. Convert the
867 // split pieces into integers and reassemble.
869 GetSplitVector(N->getOperand(0), Lo, Hi);
870 Lo = BitConvertToInteger(Lo);
871 Hi = BitConvertToInteger(Hi);
873 if (TLI.isBigEndian())
876 return DAG.getNode(ISD::BIT_CONVERT, N->getValueType(0),
877 JoinIntegers(Lo, Hi));
880 SDValue DAGTypeLegalizer::SplitVecOp_EXTRACT_SUBVECTOR(SDNode *N) {
881 // We know that the extracted result type is legal. For now, assume the index
883 MVT SubVT = N->getValueType(0);
884 SDValue Idx = N->getOperand(1);
886 GetSplitVector(N->getOperand(0), Lo, Hi);
888 uint64_t LoElts = Lo.getValueType().getVectorNumElements();
889 uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
891 if (IdxVal < LoElts) {
892 assert(IdxVal + SubVT.getVectorNumElements() <= LoElts &&
893 "Extracted subvector crosses vector split!");
894 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, SubVT, Lo, Idx);
896 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, SubVT, Hi,
897 DAG.getConstant(IdxVal - LoElts, Idx.getValueType()));
901 SDValue DAGTypeLegalizer::SplitVecOp_EXTRACT_VECTOR_ELT(SDNode *N) {
902 SDValue Vec = N->getOperand(0);
903 SDValue Idx = N->getOperand(1);
904 MVT VecVT = Vec.getValueType();
906 if (isa<ConstantSDNode>(Idx)) {
907 uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
908 assert(IdxVal < VecVT.getVectorNumElements() && "Invalid vector index!");
911 GetSplitVector(Vec, Lo, Hi);
913 uint64_t LoElts = Lo.getValueType().getVectorNumElements();
916 return DAG.UpdateNodeOperands(SDValue(N, 0), Lo, Idx);
918 return DAG.UpdateNodeOperands(SDValue(N, 0), Hi,
919 DAG.getConstant(IdxVal - LoElts,
920 Idx.getValueType()));
923 // Store the vector to the stack.
924 MVT EltVT = VecVT.getVectorElementType();
925 SDValue StackPtr = DAG.CreateStackTemporary(VecVT);
926 SDValue Store = DAG.getStore(DAG.getEntryNode(), Vec, StackPtr, NULL, 0);
928 // Load back the required element.
929 StackPtr = GetVectorElementPointer(StackPtr, EltVT, Idx);
930 return DAG.getLoad(EltVT, Store, StackPtr, NULL, 0);
933 SDValue DAGTypeLegalizer::SplitVecOp_STORE(StoreSDNode *N, unsigned OpNo) {
934 assert(N->isUnindexed() && "Indexed store of vector?");
935 assert(OpNo == 1 && "Can only split the stored value");
937 bool isTruncating = N->isTruncatingStore();
938 SDValue Ch = N->getChain();
939 SDValue Ptr = N->getBasePtr();
940 int SVOffset = N->getSrcValueOffset();
941 MVT MemoryVT = N->getMemoryVT();
942 unsigned Alignment = N->getAlignment();
943 bool isVol = N->isVolatile();
945 GetSplitVector(N->getOperand(1), Lo, Hi);
947 MVT LoMemVT, HiMemVT;
948 GetSplitDestVTs(MemoryVT, LoMemVT, HiMemVT);
950 unsigned IncrementSize = LoMemVT.getSizeInBits()/8;
953 Lo = DAG.getTruncStore(Ch, Lo, Ptr, N->getSrcValue(), SVOffset,
954 LoMemVT, isVol, Alignment);
956 Lo = DAG.getStore(Ch, Lo, Ptr, N->getSrcValue(), SVOffset,
959 // Increment the pointer to the other half.
960 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
961 DAG.getIntPtrConstant(IncrementSize));
964 Hi = DAG.getTruncStore(Ch, Hi, Ptr,
965 N->getSrcValue(), SVOffset+IncrementSize,
967 isVol, MinAlign(Alignment, IncrementSize));
969 Hi = DAG.getStore(Ch, Hi, Ptr, N->getSrcValue(), SVOffset+IncrementSize,
970 isVol, MinAlign(Alignment, IncrementSize));
972 return DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi);
975 SDValue DAGTypeLegalizer::SplitVecOp_VECTOR_SHUFFLE(SDNode *N, unsigned OpNo) {
976 assert(OpNo == 2 && "Shuffle source type differs from result type?");
977 SDValue Mask = N->getOperand(2);
978 unsigned MaskLength = Mask.getValueType().getVectorNumElements();
979 unsigned LargestMaskEntryPlusOne = 2 * MaskLength;
980 unsigned MinimumBitWidth = Log2_32_Ceil(LargestMaskEntryPlusOne);
982 // Look for a legal vector type to place the mask values in.
983 // Note that there may not be *any* legal vector-of-integer
984 // type for which the element type is legal!
985 for (MVT::SimpleValueType EltVT = MVT::FIRST_INTEGER_VALUETYPE;
986 EltVT <= MVT::LAST_INTEGER_VALUETYPE;
987 // Integer values types are consecutively numbered. Exploit this.
988 EltVT = MVT::SimpleValueType(EltVT + 1)) {
990 // Is the element type big enough to hold the values?
991 if (MVT(EltVT).getSizeInBits() < MinimumBitWidth)
995 // Is the vector type legal?
996 MVT VecVT = MVT::getVectorVT(EltVT, MaskLength);
997 if (!isTypeLegal(VecVT))
1001 // If the element type is not legal, find a larger legal type to use for
1002 // the BUILD_VECTOR operands. This is an ugly hack, but seems to work!
1003 // FIXME: The real solution is to change VECTOR_SHUFFLE into a variadic
1004 // node where the shuffle mask is a list of integer operands, #2 .. #2+n.
1005 for (MVT::SimpleValueType OpVT = EltVT; OpVT <= MVT::LAST_INTEGER_VALUETYPE;
1006 // Integer values types are consecutively numbered. Exploit this.
1007 OpVT = MVT::SimpleValueType(OpVT + 1)) {
1008 if (!isTypeLegal(OpVT))
1011 // Success! Rebuild the vector using the legal types.
1012 SmallVector<SDValue, 16> Ops(MaskLength);
1013 for (unsigned i = 0; i < MaskLength; ++i) {
1014 SDValue Arg = Mask.getOperand(i);
1015 if (Arg.getOpcode() == ISD::UNDEF) {
1016 Ops[i] = DAG.getNode(ISD::UNDEF, OpVT);
1018 uint64_t Idx = cast<ConstantSDNode>(Arg)->getZExtValue();
1019 Ops[i] = DAG.getConstant(Idx, OpVT);
1022 return DAG.UpdateNodeOperands(SDValue(N,0),
1023 N->getOperand(0), N->getOperand(1),
1024 DAG.getNode(ISD::BUILD_VECTOR,
1025 VecVT, &Ops[0], Ops.size()));
1028 // Continuing is pointless - failure is certain.
1031 assert(false && "Failed to find an appropriate mask type!");
1032 return SDValue(N, 0);