1 //===------- LegalizeVectorTypes.cpp - Legalization of vector types -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file performs vector type splitting and scalarization for LegalizeTypes.
11 // Scalarization is the act of changing a computation in an illegal one-element
12 // vector type to be a computation in its scalar element type. For example,
13 // implementing <1 x f32> arithmetic in a scalar f32 register. This is needed
14 // as a base case when scalarizing vector arithmetic like <4 x f32>, which
15 // eventually decomposes to scalars if the target doesn't support v4f32 or v2f32
17 // Splitting is the act of changing a computation in an invalid vector type to
18 // be a computation in two vectors of half the size. For example, implementing
19 // <128 x f32> operations in terms of two <64 x f32> operations.
21 //===----------------------------------------------------------------------===//
23 #include "LegalizeTypes.h"
24 #include "llvm/IR/DataLayout.h"
25 #include "llvm/Support/ErrorHandling.h"
26 #include "llvm/Support/raw_ostream.h"
29 #define DEBUG_TYPE "legalize-types"
31 //===----------------------------------------------------------------------===//
32 // Result Vector Scalarization: <1 x ty> -> ty.
33 //===----------------------------------------------------------------------===//
35 void DAGTypeLegalizer::ScalarizeVectorResult(SDNode *N, unsigned ResNo) {
36 DEBUG(dbgs() << "Scalarize node result " << ResNo << ": ";
39 SDValue R = SDValue();
41 switch (N->getOpcode()) {
44 dbgs() << "ScalarizeVectorResult #" << ResNo << ": ";
48 report_fatal_error("Do not know how to scalarize the result of this "
51 case ISD::MERGE_VALUES: R = ScalarizeVecRes_MERGE_VALUES(N, ResNo);break;
52 case ISD::BITCAST: R = ScalarizeVecRes_BITCAST(N); break;
53 case ISD::BUILD_VECTOR: R = ScalarizeVecRes_BUILD_VECTOR(N); break;
54 case ISD::CONVERT_RNDSAT: R = ScalarizeVecRes_CONVERT_RNDSAT(N); break;
55 case ISD::EXTRACT_SUBVECTOR: R = ScalarizeVecRes_EXTRACT_SUBVECTOR(N); break;
56 case ISD::FP_ROUND: R = ScalarizeVecRes_FP_ROUND(N); break;
57 case ISD::FP_ROUND_INREG: R = ScalarizeVecRes_InregOp(N); break;
58 case ISD::FPOWI: R = ScalarizeVecRes_FPOWI(N); break;
59 case ISD::INSERT_VECTOR_ELT: R = ScalarizeVecRes_INSERT_VECTOR_ELT(N); break;
60 case ISD::LOAD: R = ScalarizeVecRes_LOAD(cast<LoadSDNode>(N));break;
61 case ISD::SCALAR_TO_VECTOR: R = ScalarizeVecRes_SCALAR_TO_VECTOR(N); break;
62 case ISD::SIGN_EXTEND_INREG: R = ScalarizeVecRes_InregOp(N); break;
63 case ISD::VSELECT: R = ScalarizeVecRes_VSELECT(N); break;
64 case ISD::SELECT: R = ScalarizeVecRes_SELECT(N); break;
65 case ISD::SELECT_CC: R = ScalarizeVecRes_SELECT_CC(N); break;
66 case ISD::SETCC: R = ScalarizeVecRes_SETCC(N); break;
67 case ISD::UNDEF: R = ScalarizeVecRes_UNDEF(N); break;
68 case ISD::VECTOR_SHUFFLE: R = ScalarizeVecRes_VECTOR_SHUFFLE(N); break;
72 case ISD::CTLZ_ZERO_UNDEF:
75 case ISD::CTTZ_ZERO_UNDEF:
95 case ISD::SIGN_EXTEND:
99 case ISD::ZERO_EXTEND:
100 R = ScalarizeVecRes_UnaryOp(N);
128 R = ScalarizeVecRes_BinOp(N);
131 R = ScalarizeVecRes_TernaryOp(N);
135 // If R is null, the sub-method took care of registering the result.
137 SetScalarizedVector(SDValue(N, ResNo), R);
140 SDValue DAGTypeLegalizer::ScalarizeVecRes_BinOp(SDNode *N) {
141 SDValue LHS = GetScalarizedVector(N->getOperand(0));
142 SDValue RHS = GetScalarizedVector(N->getOperand(1));
143 return DAG.getNode(N->getOpcode(), SDLoc(N),
144 LHS.getValueType(), LHS, RHS);
147 SDValue DAGTypeLegalizer::ScalarizeVecRes_TernaryOp(SDNode *N) {
148 SDValue Op0 = GetScalarizedVector(N->getOperand(0));
149 SDValue Op1 = GetScalarizedVector(N->getOperand(1));
150 SDValue Op2 = GetScalarizedVector(N->getOperand(2));
151 return DAG.getNode(N->getOpcode(), SDLoc(N),
152 Op0.getValueType(), Op0, Op1, Op2);
155 SDValue DAGTypeLegalizer::ScalarizeVecRes_MERGE_VALUES(SDNode *N,
157 SDValue Op = DisintegrateMERGE_VALUES(N, ResNo);
158 return GetScalarizedVector(Op);
161 SDValue DAGTypeLegalizer::ScalarizeVecRes_BITCAST(SDNode *N) {
162 EVT NewVT = N->getValueType(0).getVectorElementType();
163 return DAG.getNode(ISD::BITCAST, SDLoc(N),
164 NewVT, N->getOperand(0));
167 SDValue DAGTypeLegalizer::ScalarizeVecRes_BUILD_VECTOR(SDNode *N) {
168 EVT EltVT = N->getValueType(0).getVectorElementType();
169 SDValue InOp = N->getOperand(0);
170 // The BUILD_VECTOR operands may be of wider element types and
171 // we may need to truncate them back to the requested return type.
172 if (EltVT.isInteger())
173 return DAG.getNode(ISD::TRUNCATE, SDLoc(N), EltVT, InOp);
177 SDValue DAGTypeLegalizer::ScalarizeVecRes_CONVERT_RNDSAT(SDNode *N) {
178 EVT NewVT = N->getValueType(0).getVectorElementType();
179 SDValue Op0 = GetScalarizedVector(N->getOperand(0));
180 return DAG.getConvertRndSat(NewVT, SDLoc(N),
181 Op0, DAG.getValueType(NewVT),
182 DAG.getValueType(Op0.getValueType()),
185 cast<CvtRndSatSDNode>(N)->getCvtCode());
188 SDValue DAGTypeLegalizer::ScalarizeVecRes_EXTRACT_SUBVECTOR(SDNode *N) {
189 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SDLoc(N),
190 N->getValueType(0).getVectorElementType(),
191 N->getOperand(0), N->getOperand(1));
194 SDValue DAGTypeLegalizer::ScalarizeVecRes_FP_ROUND(SDNode *N) {
195 EVT NewVT = N->getValueType(0).getVectorElementType();
196 SDValue Op = GetScalarizedVector(N->getOperand(0));
197 return DAG.getNode(ISD::FP_ROUND, SDLoc(N),
198 NewVT, Op, N->getOperand(1));
201 SDValue DAGTypeLegalizer::ScalarizeVecRes_FPOWI(SDNode *N) {
202 SDValue Op = GetScalarizedVector(N->getOperand(0));
203 return DAG.getNode(ISD::FPOWI, SDLoc(N),
204 Op.getValueType(), Op, N->getOperand(1));
207 SDValue DAGTypeLegalizer::ScalarizeVecRes_INSERT_VECTOR_ELT(SDNode *N) {
208 // The value to insert may have a wider type than the vector element type,
209 // so be sure to truncate it to the element type if necessary.
210 SDValue Op = N->getOperand(1);
211 EVT EltVT = N->getValueType(0).getVectorElementType();
212 if (Op.getValueType() != EltVT)
213 // FIXME: Can this happen for floating point types?
214 Op = DAG.getNode(ISD::TRUNCATE, SDLoc(N), EltVT, Op);
218 SDValue DAGTypeLegalizer::ScalarizeVecRes_LOAD(LoadSDNode *N) {
219 assert(N->isUnindexed() && "Indexed vector load?");
221 SDValue Result = DAG.getLoad(ISD::UNINDEXED,
222 N->getExtensionType(),
223 N->getValueType(0).getVectorElementType(),
225 N->getChain(), N->getBasePtr(),
226 DAG.getUNDEF(N->getBasePtr().getValueType()),
228 N->getMemoryVT().getVectorElementType(),
229 N->isVolatile(), N->isNonTemporal(),
230 N->isInvariant(), N->getOriginalAlignment(),
233 // Legalized the chain result - switch anything that used the old chain to
235 ReplaceValueWith(SDValue(N, 1), Result.getValue(1));
239 SDValue DAGTypeLegalizer::ScalarizeVecRes_UnaryOp(SDNode *N) {
240 // Get the dest type - it doesn't always match the input type, e.g. int_to_fp.
241 EVT DestVT = N->getValueType(0).getVectorElementType();
242 SDValue Op = N->getOperand(0);
243 EVT OpVT = Op.getValueType();
245 // The result needs scalarizing, but it's not a given that the source does.
246 // This is a workaround for targets where it's impossible to scalarize the
247 // result of a conversion, because the source type is legal.
248 // For instance, this happens on AArch64: v1i1 is illegal but v1i{8,16,32}
249 // are widened to v8i8, v4i16, and v2i32, which is legal, because v1i64 is
250 // legal and was not scalarized.
251 // See the similar logic in ScalarizeVecRes_VSETCC
252 if (getTypeAction(OpVT) == TargetLowering::TypeScalarizeVector) {
253 Op = GetScalarizedVector(Op);
255 EVT VT = OpVT.getVectorElementType();
257 ISD::EXTRACT_VECTOR_ELT, DL, VT, Op,
258 DAG.getConstant(0, DL, TLI.getVectorIdxTy(DAG.getDataLayout())));
260 return DAG.getNode(N->getOpcode(), SDLoc(N), DestVT, Op);
263 SDValue DAGTypeLegalizer::ScalarizeVecRes_InregOp(SDNode *N) {
264 EVT EltVT = N->getValueType(0).getVectorElementType();
265 EVT ExtVT = cast<VTSDNode>(N->getOperand(1))->getVT().getVectorElementType();
266 SDValue LHS = GetScalarizedVector(N->getOperand(0));
267 return DAG.getNode(N->getOpcode(), SDLoc(N), EltVT,
268 LHS, DAG.getValueType(ExtVT));
271 SDValue DAGTypeLegalizer::ScalarizeVecRes_SCALAR_TO_VECTOR(SDNode *N) {
272 // If the operand is wider than the vector element type then it is implicitly
273 // truncated. Make that explicit here.
274 EVT EltVT = N->getValueType(0).getVectorElementType();
275 SDValue InOp = N->getOperand(0);
276 if (InOp.getValueType() != EltVT)
277 return DAG.getNode(ISD::TRUNCATE, SDLoc(N), EltVT, InOp);
281 SDValue DAGTypeLegalizer::ScalarizeVecRes_VSELECT(SDNode *N) {
282 SDValue Cond = GetScalarizedVector(N->getOperand(0));
283 SDValue LHS = GetScalarizedVector(N->getOperand(1));
284 TargetLowering::BooleanContent ScalarBool =
285 TLI.getBooleanContents(false, false);
286 TargetLowering::BooleanContent VecBool = TLI.getBooleanContents(true, false);
288 // If integer and float booleans have different contents then we can't
289 // reliably optimize in all cases. There is a full explanation for this in
290 // DAGCombiner::visitSELECT() where the same issue affects folding
291 // (select C, 0, 1) to (xor C, 1).
292 if (TLI.getBooleanContents(false, false) !=
293 TLI.getBooleanContents(false, true)) {
294 // At least try the common case where the boolean is generated by a
296 if (Cond->getOpcode() == ISD::SETCC) {
297 EVT OpVT = Cond->getOperand(0)->getValueType(0);
298 ScalarBool = TLI.getBooleanContents(OpVT.getScalarType());
299 VecBool = TLI.getBooleanContents(OpVT);
301 ScalarBool = TargetLowering::UndefinedBooleanContent;
304 if (ScalarBool != VecBool) {
305 EVT CondVT = Cond.getValueType();
306 switch (ScalarBool) {
307 case TargetLowering::UndefinedBooleanContent:
309 case TargetLowering::ZeroOrOneBooleanContent:
310 assert(VecBool == TargetLowering::UndefinedBooleanContent ||
311 VecBool == TargetLowering::ZeroOrNegativeOneBooleanContent);
312 // Vector read from all ones, scalar expects a single 1 so mask.
313 Cond = DAG.getNode(ISD::AND, SDLoc(N), CondVT,
314 Cond, DAG.getConstant(1, SDLoc(N), CondVT));
316 case TargetLowering::ZeroOrNegativeOneBooleanContent:
317 assert(VecBool == TargetLowering::UndefinedBooleanContent ||
318 VecBool == TargetLowering::ZeroOrOneBooleanContent);
319 // Vector reads from a one, scalar from all ones so sign extend.
320 Cond = DAG.getNode(ISD::SIGN_EXTEND_INREG, SDLoc(N), CondVT,
321 Cond, DAG.getValueType(MVT::i1));
326 return DAG.getSelect(SDLoc(N),
327 LHS.getValueType(), Cond, LHS,
328 GetScalarizedVector(N->getOperand(2)));
331 SDValue DAGTypeLegalizer::ScalarizeVecRes_SELECT(SDNode *N) {
332 SDValue LHS = GetScalarizedVector(N->getOperand(1));
333 return DAG.getSelect(SDLoc(N),
334 LHS.getValueType(), N->getOperand(0), LHS,
335 GetScalarizedVector(N->getOperand(2)));
338 SDValue DAGTypeLegalizer::ScalarizeVecRes_SELECT_CC(SDNode *N) {
339 SDValue LHS = GetScalarizedVector(N->getOperand(2));
340 return DAG.getNode(ISD::SELECT_CC, SDLoc(N), LHS.getValueType(),
341 N->getOperand(0), N->getOperand(1),
342 LHS, GetScalarizedVector(N->getOperand(3)),
346 SDValue DAGTypeLegalizer::ScalarizeVecRes_SETCC(SDNode *N) {
347 assert(N->getValueType(0).isVector() ==
348 N->getOperand(0).getValueType().isVector() &&
349 "Scalar/Vector type mismatch");
351 if (N->getValueType(0).isVector()) return ScalarizeVecRes_VSETCC(N);
353 SDValue LHS = GetScalarizedVector(N->getOperand(0));
354 SDValue RHS = GetScalarizedVector(N->getOperand(1));
357 // Turn it into a scalar SETCC.
358 return DAG.getNode(ISD::SETCC, DL, MVT::i1, LHS, RHS, N->getOperand(2));
361 SDValue DAGTypeLegalizer::ScalarizeVecRes_UNDEF(SDNode *N) {
362 return DAG.getUNDEF(N->getValueType(0).getVectorElementType());
365 SDValue DAGTypeLegalizer::ScalarizeVecRes_VECTOR_SHUFFLE(SDNode *N) {
366 // Figure out if the scalar is the LHS or RHS and return it.
367 SDValue Arg = N->getOperand(2).getOperand(0);
368 if (Arg.getOpcode() == ISD::UNDEF)
369 return DAG.getUNDEF(N->getValueType(0).getVectorElementType());
370 unsigned Op = !cast<ConstantSDNode>(Arg)->isNullValue();
371 return GetScalarizedVector(N->getOperand(Op));
374 SDValue DAGTypeLegalizer::ScalarizeVecRes_VSETCC(SDNode *N) {
375 assert(N->getValueType(0).isVector() &&
376 N->getOperand(0).getValueType().isVector() &&
377 "Operand types must be vectors");
378 SDValue LHS = N->getOperand(0);
379 SDValue RHS = N->getOperand(1);
380 EVT OpVT = LHS.getValueType();
381 EVT NVT = N->getValueType(0).getVectorElementType();
384 // The result needs scalarizing, but it's not a given that the source does.
385 if (getTypeAction(OpVT) == TargetLowering::TypeScalarizeVector) {
386 LHS = GetScalarizedVector(LHS);
387 RHS = GetScalarizedVector(RHS);
389 EVT VT = OpVT.getVectorElementType();
391 ISD::EXTRACT_VECTOR_ELT, DL, VT, LHS,
392 DAG.getConstant(0, DL, TLI.getVectorIdxTy(DAG.getDataLayout())));
394 ISD::EXTRACT_VECTOR_ELT, DL, VT, RHS,
395 DAG.getConstant(0, DL, TLI.getVectorIdxTy(DAG.getDataLayout())));
398 // Turn it into a scalar SETCC.
399 SDValue Res = DAG.getNode(ISD::SETCC, DL, MVT::i1, LHS, RHS,
401 // Vectors may have a different boolean contents to scalars. Promote the
402 // value appropriately.
403 ISD::NodeType ExtendCode =
404 TargetLowering::getExtendForContent(TLI.getBooleanContents(OpVT));
405 return DAG.getNode(ExtendCode, DL, NVT, Res);
409 //===----------------------------------------------------------------------===//
410 // Operand Vector Scalarization <1 x ty> -> ty.
411 //===----------------------------------------------------------------------===//
413 bool DAGTypeLegalizer::ScalarizeVectorOperand(SDNode *N, unsigned OpNo) {
414 DEBUG(dbgs() << "Scalarize node operand " << OpNo << ": ";
417 SDValue Res = SDValue();
419 if (!Res.getNode()) {
420 switch (N->getOpcode()) {
423 dbgs() << "ScalarizeVectorOperand Op #" << OpNo << ": ";
427 llvm_unreachable("Do not know how to scalarize this operator's operand!");
429 Res = ScalarizeVecOp_BITCAST(N);
431 case ISD::ANY_EXTEND:
432 case ISD::ZERO_EXTEND:
433 case ISD::SIGN_EXTEND:
435 case ISD::FP_TO_SINT:
436 case ISD::FP_TO_UINT:
437 case ISD::SINT_TO_FP:
438 case ISD::UINT_TO_FP:
439 Res = ScalarizeVecOp_UnaryOp(N);
441 case ISD::CONCAT_VECTORS:
442 Res = ScalarizeVecOp_CONCAT_VECTORS(N);
444 case ISD::EXTRACT_VECTOR_ELT:
445 Res = ScalarizeVecOp_EXTRACT_VECTOR_ELT(N);
448 Res = ScalarizeVecOp_VSELECT(N);
451 Res = ScalarizeVecOp_STORE(cast<StoreSDNode>(N), OpNo);
454 Res = ScalarizeVecOp_FP_ROUND(N, OpNo);
459 // If the result is null, the sub-method took care of registering results etc.
460 if (!Res.getNode()) return false;
462 // If the result is N, the sub-method updated N in place. Tell the legalizer
464 if (Res.getNode() == N)
467 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 &&
468 "Invalid operand expansion");
470 ReplaceValueWith(SDValue(N, 0), Res);
474 /// ScalarizeVecOp_BITCAST - If the value to convert is a vector that needs
475 /// to be scalarized, it must be <1 x ty>. Convert the element instead.
476 SDValue DAGTypeLegalizer::ScalarizeVecOp_BITCAST(SDNode *N) {
477 SDValue Elt = GetScalarizedVector(N->getOperand(0));
478 return DAG.getNode(ISD::BITCAST, SDLoc(N),
479 N->getValueType(0), Elt);
482 /// ScalarizeVecOp_UnaryOp - If the input is a vector that needs to be
483 /// scalarized, it must be <1 x ty>. Do the operation on the element instead.
484 SDValue DAGTypeLegalizer::ScalarizeVecOp_UnaryOp(SDNode *N) {
485 assert(N->getValueType(0).getVectorNumElements() == 1 &&
486 "Unexpected vector type!");
487 SDValue Elt = GetScalarizedVector(N->getOperand(0));
488 SDValue Op = DAG.getNode(N->getOpcode(), SDLoc(N),
489 N->getValueType(0).getScalarType(), Elt);
490 // Revectorize the result so the types line up with what the uses of this
491 // expression expect.
492 return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(N), N->getValueType(0), Op);
495 /// ScalarizeVecOp_CONCAT_VECTORS - The vectors to concatenate have length one -
496 /// use a BUILD_VECTOR instead.
497 SDValue DAGTypeLegalizer::ScalarizeVecOp_CONCAT_VECTORS(SDNode *N) {
498 SmallVector<SDValue, 8> Ops(N->getNumOperands());
499 for (unsigned i = 0, e = N->getNumOperands(); i < e; ++i)
500 Ops[i] = GetScalarizedVector(N->getOperand(i));
501 return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(N), N->getValueType(0), Ops);
504 /// ScalarizeVecOp_EXTRACT_VECTOR_ELT - If the input is a vector that needs to
505 /// be scalarized, it must be <1 x ty>, so just return the element, ignoring the
507 SDValue DAGTypeLegalizer::ScalarizeVecOp_EXTRACT_VECTOR_ELT(SDNode *N) {
508 SDValue Res = GetScalarizedVector(N->getOperand(0));
509 if (Res.getValueType() != N->getValueType(0))
510 Res = DAG.getNode(ISD::ANY_EXTEND, SDLoc(N), N->getValueType(0),
516 /// ScalarizeVecOp_VSELECT - If the input condition is a vector that needs to be
517 /// scalarized, it must be <1 x i1>, so just convert to a normal ISD::SELECT
518 /// (still with vector output type since that was acceptable if we got here).
519 SDValue DAGTypeLegalizer::ScalarizeVecOp_VSELECT(SDNode *N) {
520 SDValue ScalarCond = GetScalarizedVector(N->getOperand(0));
521 EVT VT = N->getValueType(0);
523 return DAG.getNode(ISD::SELECT, SDLoc(N), VT, ScalarCond, N->getOperand(1),
527 /// ScalarizeVecOp_STORE - If the value to store is a vector that needs to be
528 /// scalarized, it must be <1 x ty>. Just store the element.
529 SDValue DAGTypeLegalizer::ScalarizeVecOp_STORE(StoreSDNode *N, unsigned OpNo){
530 assert(N->isUnindexed() && "Indexed store of one-element vector?");
531 assert(OpNo == 1 && "Do not know how to scalarize this operand!");
534 if (N->isTruncatingStore())
535 return DAG.getTruncStore(N->getChain(), dl,
536 GetScalarizedVector(N->getOperand(1)),
537 N->getBasePtr(), N->getPointerInfo(),
538 N->getMemoryVT().getVectorElementType(),
539 N->isVolatile(), N->isNonTemporal(),
540 N->getAlignment(), N->getAAInfo());
542 return DAG.getStore(N->getChain(), dl, GetScalarizedVector(N->getOperand(1)),
543 N->getBasePtr(), N->getPointerInfo(),
544 N->isVolatile(), N->isNonTemporal(),
545 N->getOriginalAlignment(), N->getAAInfo());
548 /// ScalarizeVecOp_FP_ROUND - If the value to round is a vector that needs
549 /// to be scalarized, it must be <1 x ty>. Convert the element instead.
550 SDValue DAGTypeLegalizer::ScalarizeVecOp_FP_ROUND(SDNode *N, unsigned OpNo) {
551 SDValue Elt = GetScalarizedVector(N->getOperand(0));
552 SDValue Res = DAG.getNode(ISD::FP_ROUND, SDLoc(N),
553 N->getValueType(0).getVectorElementType(), Elt,
555 return DAG.getNode(ISD::SCALAR_TO_VECTOR, SDLoc(N), N->getValueType(0), Res);
558 //===----------------------------------------------------------------------===//
559 // Result Vector Splitting
560 //===----------------------------------------------------------------------===//
562 /// SplitVectorResult - This method is called when the specified result of the
563 /// specified node is found to need vector splitting. At this point, the node
564 /// may also have invalid operands or may have other results that need
565 /// legalization, we just know that (at least) one result needs vector
567 void DAGTypeLegalizer::SplitVectorResult(SDNode *N, unsigned ResNo) {
568 DEBUG(dbgs() << "Split node result: ";
573 // See if the target wants to custom expand this node.
574 if (CustomLowerNode(N, N->getValueType(ResNo), true))
577 switch (N->getOpcode()) {
580 dbgs() << "SplitVectorResult #" << ResNo << ": ";
584 report_fatal_error("Do not know how to split the result of this "
587 case ISD::MERGE_VALUES: SplitRes_MERGE_VALUES(N, ResNo, Lo, Hi); break;
589 case ISD::SELECT: SplitRes_SELECT(N, Lo, Hi); break;
590 case ISD::SELECT_CC: SplitRes_SELECT_CC(N, Lo, Hi); break;
591 case ISD::UNDEF: SplitRes_UNDEF(N, Lo, Hi); break;
592 case ISD::BITCAST: SplitVecRes_BITCAST(N, Lo, Hi); break;
593 case ISD::BUILD_VECTOR: SplitVecRes_BUILD_VECTOR(N, Lo, Hi); break;
594 case ISD::CONCAT_VECTORS: SplitVecRes_CONCAT_VECTORS(N, Lo, Hi); break;
595 case ISD::EXTRACT_SUBVECTOR: SplitVecRes_EXTRACT_SUBVECTOR(N, Lo, Hi); break;
596 case ISD::INSERT_SUBVECTOR: SplitVecRes_INSERT_SUBVECTOR(N, Lo, Hi); break;
597 case ISD::FP_ROUND_INREG: SplitVecRes_InregOp(N, Lo, Hi); break;
598 case ISD::FPOWI: SplitVecRes_FPOWI(N, Lo, Hi); break;
599 case ISD::FCOPYSIGN: SplitVecRes_FCOPYSIGN(N, Lo, Hi); break;
600 case ISD::INSERT_VECTOR_ELT: SplitVecRes_INSERT_VECTOR_ELT(N, Lo, Hi); break;
601 case ISD::SCALAR_TO_VECTOR: SplitVecRes_SCALAR_TO_VECTOR(N, Lo, Hi); break;
602 case ISD::SIGN_EXTEND_INREG: SplitVecRes_InregOp(N, Lo, Hi); break;
604 SplitVecRes_LOAD(cast<LoadSDNode>(N), Lo, Hi);
607 SplitVecRes_MLOAD(cast<MaskedLoadSDNode>(N), Lo, Hi);
610 SplitVecRes_MGATHER(cast<MaskedGatherSDNode>(N), Lo, Hi);
613 SplitVecRes_SETCC(N, Lo, Hi);
615 case ISD::VECTOR_SHUFFLE:
616 SplitVecRes_VECTOR_SHUFFLE(cast<ShuffleVectorSDNode>(N), Lo, Hi);
620 case ISD::CONVERT_RNDSAT:
623 case ISD::CTLZ_ZERO_UNDEF:
624 case ISD::CTTZ_ZERO_UNDEF:
635 case ISD::FNEARBYINT:
639 case ISD::FP_TO_SINT:
640 case ISD::FP_TO_UINT:
646 case ISD::SINT_TO_FP:
648 case ISD::UINT_TO_FP:
649 SplitVecRes_UnaryOp(N, Lo, Hi);
652 case ISD::ANY_EXTEND:
653 case ISD::SIGN_EXTEND:
654 case ISD::ZERO_EXTEND:
655 SplitVecRes_ExtendOp(N, Lo, Hi);
687 SplitVecRes_BinOp(N, Lo, Hi);
690 SplitVecRes_TernaryOp(N, Lo, Hi);
694 // If Lo/Hi is null, the sub-method took care of registering results etc.
696 SetSplitVector(SDValue(N, ResNo), Lo, Hi);
699 void DAGTypeLegalizer::SplitVecRes_BinOp(SDNode *N, SDValue &Lo,
701 SDValue LHSLo, LHSHi;
702 GetSplitVector(N->getOperand(0), LHSLo, LHSHi);
703 SDValue RHSLo, RHSHi;
704 GetSplitVector(N->getOperand(1), RHSLo, RHSHi);
707 Lo = DAG.getNode(N->getOpcode(), dl, LHSLo.getValueType(), LHSLo, RHSLo);
708 Hi = DAG.getNode(N->getOpcode(), dl, LHSHi.getValueType(), LHSHi, RHSHi);
711 void DAGTypeLegalizer::SplitVecRes_TernaryOp(SDNode *N, SDValue &Lo,
713 SDValue Op0Lo, Op0Hi;
714 GetSplitVector(N->getOperand(0), Op0Lo, Op0Hi);
715 SDValue Op1Lo, Op1Hi;
716 GetSplitVector(N->getOperand(1), Op1Lo, Op1Hi);
717 SDValue Op2Lo, Op2Hi;
718 GetSplitVector(N->getOperand(2), Op2Lo, Op2Hi);
721 Lo = DAG.getNode(N->getOpcode(), dl, Op0Lo.getValueType(),
722 Op0Lo, Op1Lo, Op2Lo);
723 Hi = DAG.getNode(N->getOpcode(), dl, Op0Hi.getValueType(),
724 Op0Hi, Op1Hi, Op2Hi);
727 void DAGTypeLegalizer::SplitVecRes_BITCAST(SDNode *N, SDValue &Lo,
729 // We know the result is a vector. The input may be either a vector or a
732 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(N->getValueType(0));
735 SDValue InOp = N->getOperand(0);
736 EVT InVT = InOp.getValueType();
738 // Handle some special cases efficiently.
739 switch (getTypeAction(InVT)) {
740 case TargetLowering::TypeLegal:
741 case TargetLowering::TypePromoteInteger:
742 case TargetLowering::TypePromoteFloat:
743 case TargetLowering::TypeSoftenFloat:
744 case TargetLowering::TypeScalarizeVector:
745 case TargetLowering::TypeWidenVector:
747 case TargetLowering::TypeExpandInteger:
748 case TargetLowering::TypeExpandFloat:
749 // A scalar to vector conversion, where the scalar needs expansion.
750 // If the vector is being split in two then we can just convert the
753 GetExpandedOp(InOp, Lo, Hi);
754 if (DAG.getDataLayout().isBigEndian())
756 Lo = DAG.getNode(ISD::BITCAST, dl, LoVT, Lo);
757 Hi = DAG.getNode(ISD::BITCAST, dl, HiVT, Hi);
761 case TargetLowering::TypeSplitVector:
762 // If the input is a vector that needs to be split, convert each split
763 // piece of the input now.
764 GetSplitVector(InOp, Lo, Hi);
765 Lo = DAG.getNode(ISD::BITCAST, dl, LoVT, Lo);
766 Hi = DAG.getNode(ISD::BITCAST, dl, HiVT, Hi);
770 // In the general case, convert the input to an integer and split it by hand.
771 EVT LoIntVT = EVT::getIntegerVT(*DAG.getContext(), LoVT.getSizeInBits());
772 EVT HiIntVT = EVT::getIntegerVT(*DAG.getContext(), HiVT.getSizeInBits());
773 if (DAG.getDataLayout().isBigEndian())
774 std::swap(LoIntVT, HiIntVT);
776 SplitInteger(BitConvertToInteger(InOp), LoIntVT, HiIntVT, Lo, Hi);
778 if (DAG.getDataLayout().isBigEndian())
780 Lo = DAG.getNode(ISD::BITCAST, dl, LoVT, Lo);
781 Hi = DAG.getNode(ISD::BITCAST, dl, HiVT, Hi);
784 void DAGTypeLegalizer::SplitVecRes_BUILD_VECTOR(SDNode *N, SDValue &Lo,
788 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(N->getValueType(0));
789 unsigned LoNumElts = LoVT.getVectorNumElements();
790 SmallVector<SDValue, 8> LoOps(N->op_begin(), N->op_begin()+LoNumElts);
791 Lo = DAG.getNode(ISD::BUILD_VECTOR, dl, LoVT, LoOps);
793 SmallVector<SDValue, 8> HiOps(N->op_begin()+LoNumElts, N->op_end());
794 Hi = DAG.getNode(ISD::BUILD_VECTOR, dl, HiVT, HiOps);
797 void DAGTypeLegalizer::SplitVecRes_CONCAT_VECTORS(SDNode *N, SDValue &Lo,
799 assert(!(N->getNumOperands() & 1) && "Unsupported CONCAT_VECTORS");
801 unsigned NumSubvectors = N->getNumOperands() / 2;
802 if (NumSubvectors == 1) {
803 Lo = N->getOperand(0);
804 Hi = N->getOperand(1);
809 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(N->getValueType(0));
811 SmallVector<SDValue, 8> LoOps(N->op_begin(), N->op_begin()+NumSubvectors);
812 Lo = DAG.getNode(ISD::CONCAT_VECTORS, dl, LoVT, LoOps);
814 SmallVector<SDValue, 8> HiOps(N->op_begin()+NumSubvectors, N->op_end());
815 Hi = DAG.getNode(ISD::CONCAT_VECTORS, dl, HiVT, HiOps);
818 void DAGTypeLegalizer::SplitVecRes_EXTRACT_SUBVECTOR(SDNode *N, SDValue &Lo,
820 SDValue Vec = N->getOperand(0);
821 SDValue Idx = N->getOperand(1);
825 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(N->getValueType(0));
827 Lo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, LoVT, Vec, Idx);
828 uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
829 Hi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, HiVT, Vec,
830 DAG.getConstant(IdxVal + LoVT.getVectorNumElements(), dl,
831 TLI.getVectorIdxTy(DAG.getDataLayout())));
834 void DAGTypeLegalizer::SplitVecRes_INSERT_SUBVECTOR(SDNode *N, SDValue &Lo,
836 SDValue Vec = N->getOperand(0);
837 SDValue SubVec = N->getOperand(1);
838 SDValue Idx = N->getOperand(2);
840 GetSplitVector(Vec, Lo, Hi);
842 // Spill the vector to the stack.
843 EVT VecVT = Vec.getValueType();
844 EVT SubVecVT = VecVT.getVectorElementType();
845 SDValue StackPtr = DAG.CreateStackTemporary(VecVT);
846 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Vec, StackPtr,
847 MachinePointerInfo(), false, false, 0);
849 // Store the new subvector into the specified index.
850 SDValue SubVecPtr = GetVectorElementPointer(StackPtr, SubVecVT, Idx);
851 Type *VecType = VecVT.getTypeForEVT(*DAG.getContext());
852 unsigned Alignment = DAG.getDataLayout().getPrefTypeAlignment(VecType);
853 Store = DAG.getStore(Store, dl, SubVec, SubVecPtr, MachinePointerInfo(),
856 // Load the Lo part from the stack slot.
857 Lo = DAG.getLoad(Lo.getValueType(), dl, Store, StackPtr, MachinePointerInfo(),
858 false, false, false, 0);
860 // Increment the pointer to the other part.
861 unsigned IncrementSize = Lo.getValueType().getSizeInBits() / 8;
863 DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr,
864 DAG.getConstant(IncrementSize, dl, StackPtr.getValueType()));
866 // Load the Hi part from the stack slot.
867 Hi = DAG.getLoad(Hi.getValueType(), dl, Store, StackPtr, MachinePointerInfo(),
868 false, false, false, MinAlign(Alignment, IncrementSize));
871 void DAGTypeLegalizer::SplitVecRes_FPOWI(SDNode *N, SDValue &Lo,
874 GetSplitVector(N->getOperand(0), Lo, Hi);
875 Lo = DAG.getNode(ISD::FPOWI, dl, Lo.getValueType(), Lo, N->getOperand(1));
876 Hi = DAG.getNode(ISD::FPOWI, dl, Hi.getValueType(), Hi, N->getOperand(1));
879 void DAGTypeLegalizer::SplitVecRes_FCOPYSIGN(SDNode *N, SDValue &Lo,
881 SDValue LHSLo, LHSHi;
882 GetSplitVector(N->getOperand(0), LHSLo, LHSHi);
885 SDValue RHSLo, RHSHi;
886 SDValue RHS = N->getOperand(1);
887 EVT RHSVT = RHS.getValueType();
888 if (getTypeAction(RHSVT) == TargetLowering::TypeSplitVector)
889 GetSplitVector(RHS, RHSLo, RHSHi);
891 std::tie(RHSLo, RHSHi) = DAG.SplitVector(RHS, SDLoc(RHS));
894 Lo = DAG.getNode(ISD::FCOPYSIGN, DL, LHSLo.getValueType(), LHSLo, RHSLo);
895 Hi = DAG.getNode(ISD::FCOPYSIGN, DL, LHSHi.getValueType(), LHSHi, RHSHi);
898 void DAGTypeLegalizer::SplitVecRes_InregOp(SDNode *N, SDValue &Lo,
900 SDValue LHSLo, LHSHi;
901 GetSplitVector(N->getOperand(0), LHSLo, LHSHi);
905 std::tie(LoVT, HiVT) =
906 DAG.GetSplitDestVTs(cast<VTSDNode>(N->getOperand(1))->getVT());
908 Lo = DAG.getNode(N->getOpcode(), dl, LHSLo.getValueType(), LHSLo,
909 DAG.getValueType(LoVT));
910 Hi = DAG.getNode(N->getOpcode(), dl, LHSHi.getValueType(), LHSHi,
911 DAG.getValueType(HiVT));
914 void DAGTypeLegalizer::SplitVecRes_INSERT_VECTOR_ELT(SDNode *N, SDValue &Lo,
916 SDValue Vec = N->getOperand(0);
917 SDValue Elt = N->getOperand(1);
918 SDValue Idx = N->getOperand(2);
920 GetSplitVector(Vec, Lo, Hi);
922 if (ConstantSDNode *CIdx = dyn_cast<ConstantSDNode>(Idx)) {
923 unsigned IdxVal = CIdx->getZExtValue();
924 unsigned LoNumElts = Lo.getValueType().getVectorNumElements();
925 if (IdxVal < LoNumElts)
926 Lo = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
927 Lo.getValueType(), Lo, Elt, Idx);
930 DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, Hi.getValueType(), Hi, Elt,
931 DAG.getConstant(IdxVal - LoNumElts, dl,
932 TLI.getVectorIdxTy(DAG.getDataLayout())));
936 // See if the target wants to custom expand this node.
937 if (CustomLowerNode(N, N->getValueType(0), true))
940 // Spill the vector to the stack.
941 EVT VecVT = Vec.getValueType();
942 EVT EltVT = VecVT.getVectorElementType();
943 SDValue StackPtr = DAG.CreateStackTemporary(VecVT);
944 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Vec, StackPtr,
945 MachinePointerInfo(), false, false, 0);
947 // Store the new element. This may be larger than the vector element type,
948 // so use a truncating store.
949 SDValue EltPtr = GetVectorElementPointer(StackPtr, EltVT, Idx);
950 Type *VecType = VecVT.getTypeForEVT(*DAG.getContext());
951 unsigned Alignment = DAG.getDataLayout().getPrefTypeAlignment(VecType);
952 Store = DAG.getTruncStore(Store, dl, Elt, EltPtr, MachinePointerInfo(), EltVT,
955 // Load the Lo part from the stack slot.
956 Lo = DAG.getLoad(Lo.getValueType(), dl, Store, StackPtr, MachinePointerInfo(),
957 false, false, false, 0);
959 // Increment the pointer to the other part.
960 unsigned IncrementSize = Lo.getValueType().getSizeInBits() / 8;
961 StackPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr,
962 DAG.getConstant(IncrementSize, dl,
963 StackPtr.getValueType()));
965 // Load the Hi part from the stack slot.
966 Hi = DAG.getLoad(Hi.getValueType(), dl, Store, StackPtr, MachinePointerInfo(),
967 false, false, false, MinAlign(Alignment, IncrementSize));
970 void DAGTypeLegalizer::SplitVecRes_SCALAR_TO_VECTOR(SDNode *N, SDValue &Lo,
974 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(N->getValueType(0));
975 Lo = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LoVT, N->getOperand(0));
976 Hi = DAG.getUNDEF(HiVT);
979 void DAGTypeLegalizer::SplitVecRes_LOAD(LoadSDNode *LD, SDValue &Lo,
981 assert(ISD::isUNINDEXEDLoad(LD) && "Indexed load during type legalization!");
984 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(LD->getValueType(0));
986 ISD::LoadExtType ExtType = LD->getExtensionType();
987 SDValue Ch = LD->getChain();
988 SDValue Ptr = LD->getBasePtr();
989 SDValue Offset = DAG.getUNDEF(Ptr.getValueType());
990 EVT MemoryVT = LD->getMemoryVT();
991 unsigned Alignment = LD->getOriginalAlignment();
992 bool isVolatile = LD->isVolatile();
993 bool isNonTemporal = LD->isNonTemporal();
994 bool isInvariant = LD->isInvariant();
995 AAMDNodes AAInfo = LD->getAAInfo();
997 EVT LoMemVT, HiMemVT;
998 std::tie(LoMemVT, HiMemVT) = DAG.GetSplitDestVTs(MemoryVT);
1000 Lo = DAG.getLoad(ISD::UNINDEXED, ExtType, LoVT, dl, Ch, Ptr, Offset,
1001 LD->getPointerInfo(), LoMemVT, isVolatile, isNonTemporal,
1002 isInvariant, Alignment, AAInfo);
1004 unsigned IncrementSize = LoMemVT.getSizeInBits()/8;
1005 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
1006 DAG.getConstant(IncrementSize, dl, Ptr.getValueType()));
1007 Hi = DAG.getLoad(ISD::UNINDEXED, ExtType, HiVT, dl, Ch, Ptr, Offset,
1008 LD->getPointerInfo().getWithOffset(IncrementSize),
1009 HiMemVT, isVolatile, isNonTemporal, isInvariant, Alignment,
1012 // Build a factor node to remember that this load is independent of the
1014 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
1017 // Legalized the chain result - switch anything that used the old chain to
1019 ReplaceValueWith(SDValue(LD, 1), Ch);
1022 void DAGTypeLegalizer::SplitVecRes_MLOAD(MaskedLoadSDNode *MLD,
1023 SDValue &Lo, SDValue &Hi) {
1026 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(MLD->getValueType(0));
1028 SDValue Ch = MLD->getChain();
1029 SDValue Ptr = MLD->getBasePtr();
1030 SDValue Mask = MLD->getMask();
1031 unsigned Alignment = MLD->getOriginalAlignment();
1032 ISD::LoadExtType ExtType = MLD->getExtensionType();
1034 // if Alignment is equal to the vector size,
1035 // take the half of it for the second part
1036 unsigned SecondHalfAlignment =
1037 (Alignment == MLD->getValueType(0).getSizeInBits()/8) ?
1038 Alignment/2 : Alignment;
1040 SDValue MaskLo, MaskHi;
1041 std::tie(MaskLo, MaskHi) = DAG.SplitVector(Mask, dl);
1043 EVT MemoryVT = MLD->getMemoryVT();
1044 EVT LoMemVT, HiMemVT;
1045 std::tie(LoMemVT, HiMemVT) = DAG.GetSplitDestVTs(MemoryVT);
1047 SDValue Src0 = MLD->getSrc0();
1048 SDValue Src0Lo, Src0Hi;
1049 std::tie(Src0Lo, Src0Hi) = DAG.SplitVector(Src0, dl);
1051 MachineMemOperand *MMO = DAG.getMachineFunction().
1052 getMachineMemOperand(MLD->getPointerInfo(),
1053 MachineMemOperand::MOLoad, LoMemVT.getStoreSize(),
1054 Alignment, MLD->getAAInfo(), MLD->getRanges());
1056 Lo = DAG.getMaskedLoad(LoVT, dl, Ch, Ptr, MaskLo, Src0Lo, LoMemVT, MMO,
1059 unsigned IncrementSize = LoMemVT.getSizeInBits()/8;
1060 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
1061 DAG.getConstant(IncrementSize, dl, Ptr.getValueType()));
1063 MMO = DAG.getMachineFunction().
1064 getMachineMemOperand(MLD->getPointerInfo(),
1065 MachineMemOperand::MOLoad, HiMemVT.getStoreSize(),
1066 SecondHalfAlignment, MLD->getAAInfo(), MLD->getRanges());
1068 Hi = DAG.getMaskedLoad(HiVT, dl, Ch, Ptr, MaskHi, Src0Hi, HiMemVT, MMO,
1072 // Build a factor node to remember that this load is independent of the
1074 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
1077 // Legalized the chain result - switch anything that used the old chain to
1079 ReplaceValueWith(SDValue(MLD, 1), Ch);
1083 void DAGTypeLegalizer::SplitVecRes_MGATHER(MaskedGatherSDNode *MGT,
1084 SDValue &Lo, SDValue &Hi) {
1087 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(MGT->getValueType(0));
1089 SDValue Ch = MGT->getChain();
1090 SDValue Ptr = MGT->getBasePtr();
1091 SDValue Mask = MGT->getMask();
1092 unsigned Alignment = MGT->getOriginalAlignment();
1094 SDValue MaskLo, MaskHi;
1095 std::tie(MaskLo, MaskHi) = DAG.SplitVector(Mask, dl);
1097 EVT MemoryVT = MGT->getMemoryVT();
1098 EVT LoMemVT, HiMemVT;
1099 std::tie(LoMemVT, HiMemVT) = DAG.GetSplitDestVTs(MemoryVT);
1101 SDValue Src0Lo, Src0Hi;
1102 std::tie(Src0Lo, Src0Hi) = DAG.SplitVector(MGT->getValue(), dl);
1104 SDValue IndexHi, IndexLo;
1105 std::tie(IndexLo, IndexHi) = DAG.SplitVector(MGT->getIndex(), dl);
1107 MachineMemOperand *MMO = DAG.getMachineFunction().
1108 getMachineMemOperand(MGT->getPointerInfo(),
1109 MachineMemOperand::MOLoad, LoMemVT.getStoreSize(),
1110 Alignment, MGT->getAAInfo(), MGT->getRanges());
1112 SDValue OpsLo[] = {Ch, Src0Lo, MaskLo, Ptr, IndexLo};
1113 Lo = DAG.getMaskedGather(DAG.getVTList(LoVT, MVT::Other), LoVT, dl, OpsLo,
1116 SDValue OpsHi[] = {Ch, Src0Hi, MaskHi, Ptr, IndexHi};
1117 Hi = DAG.getMaskedGather(DAG.getVTList(HiVT, MVT::Other), HiVT, dl, OpsHi,
1120 // Build a factor node to remember that this load is independent of the
1122 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
1125 // Legalized the chain result - switch anything that used the old chain to
1127 ReplaceValueWith(SDValue(MGT, 1), Ch);
1131 void DAGTypeLegalizer::SplitVecRes_SETCC(SDNode *N, SDValue &Lo, SDValue &Hi) {
1132 assert(N->getValueType(0).isVector() &&
1133 N->getOperand(0).getValueType().isVector() &&
1134 "Operand types must be vectors");
1138 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(N->getValueType(0));
1141 SDValue LL, LH, RL, RH;
1142 std::tie(LL, LH) = DAG.SplitVectorOperand(N, 0);
1143 std::tie(RL, RH) = DAG.SplitVectorOperand(N, 1);
1145 Lo = DAG.getNode(N->getOpcode(), DL, LoVT, LL, RL, N->getOperand(2));
1146 Hi = DAG.getNode(N->getOpcode(), DL, HiVT, LH, RH, N->getOperand(2));
1149 void DAGTypeLegalizer::SplitVecRes_UnaryOp(SDNode *N, SDValue &Lo,
1151 // Get the dest types - they may not match the input types, e.g. int_to_fp.
1154 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(N->getValueType(0));
1156 // If the input also splits, handle it directly for a compile time speedup.
1157 // Otherwise split it by hand.
1158 EVT InVT = N->getOperand(0).getValueType();
1159 if (getTypeAction(InVT) == TargetLowering::TypeSplitVector)
1160 GetSplitVector(N->getOperand(0), Lo, Hi);
1162 std::tie(Lo, Hi) = DAG.SplitVectorOperand(N, 0);
1164 if (N->getOpcode() == ISD::FP_ROUND) {
1165 Lo = DAG.getNode(N->getOpcode(), dl, LoVT, Lo, N->getOperand(1));
1166 Hi = DAG.getNode(N->getOpcode(), dl, HiVT, Hi, N->getOperand(1));
1167 } else if (N->getOpcode() == ISD::CONVERT_RNDSAT) {
1168 SDValue DTyOpLo = DAG.getValueType(LoVT);
1169 SDValue DTyOpHi = DAG.getValueType(HiVT);
1170 SDValue STyOpLo = DAG.getValueType(Lo.getValueType());
1171 SDValue STyOpHi = DAG.getValueType(Hi.getValueType());
1172 SDValue RndOp = N->getOperand(3);
1173 SDValue SatOp = N->getOperand(4);
1174 ISD::CvtCode CvtCode = cast<CvtRndSatSDNode>(N)->getCvtCode();
1175 Lo = DAG.getConvertRndSat(LoVT, dl, Lo, DTyOpLo, STyOpLo, RndOp, SatOp,
1177 Hi = DAG.getConvertRndSat(HiVT, dl, Hi, DTyOpHi, STyOpHi, RndOp, SatOp,
1180 Lo = DAG.getNode(N->getOpcode(), dl, LoVT, Lo);
1181 Hi = DAG.getNode(N->getOpcode(), dl, HiVT, Hi);
1185 void DAGTypeLegalizer::SplitVecRes_ExtendOp(SDNode *N, SDValue &Lo,
1188 EVT SrcVT = N->getOperand(0).getValueType();
1189 EVT DestVT = N->getValueType(0);
1191 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(DestVT);
1193 // We can do better than a generic split operation if the extend is doing
1194 // more than just doubling the width of the elements and the following are
1196 // - The number of vector elements is even,
1197 // - the source type is legal,
1198 // - the type of a split source is illegal,
1199 // - the type of an extended (by doubling element size) source is legal, and
1200 // - the type of that extended source when split is legal.
1202 // This won't necessarily completely legalize the operation, but it will
1203 // more effectively move in the right direction and prevent falling down
1204 // to scalarization in many cases due to the input vector being split too
1206 unsigned NumElements = SrcVT.getVectorNumElements();
1207 if ((NumElements & 1) == 0 &&
1208 SrcVT.getSizeInBits() * 2 < DestVT.getSizeInBits()) {
1209 LLVMContext &Ctx = *DAG.getContext();
1210 EVT NewSrcVT = EVT::getVectorVT(
1211 Ctx, EVT::getIntegerVT(
1212 Ctx, SrcVT.getVectorElementType().getSizeInBits() * 2),
1215 EVT::getVectorVT(Ctx, SrcVT.getVectorElementType(), NumElements / 2);
1216 EVT SplitLoVT, SplitHiVT;
1217 std::tie(SplitLoVT, SplitHiVT) = DAG.GetSplitDestVTs(NewSrcVT);
1218 if (TLI.isTypeLegal(SrcVT) && !TLI.isTypeLegal(SplitSrcVT) &&
1219 TLI.isTypeLegal(NewSrcVT) && TLI.isTypeLegal(SplitLoVT)) {
1220 DEBUG(dbgs() << "Split vector extend via incremental extend:";
1221 N->dump(&DAG); dbgs() << "\n");
1222 // Extend the source vector by one step.
1224 DAG.getNode(N->getOpcode(), dl, NewSrcVT, N->getOperand(0));
1225 // Get the low and high halves of the new, extended one step, vector.
1226 std::tie(Lo, Hi) = DAG.SplitVector(NewSrc, dl);
1227 // Extend those vector halves the rest of the way.
1228 Lo = DAG.getNode(N->getOpcode(), dl, LoVT, Lo);
1229 Hi = DAG.getNode(N->getOpcode(), dl, HiVT, Hi);
1233 // Fall back to the generic unary operator splitting otherwise.
1234 SplitVecRes_UnaryOp(N, Lo, Hi);
1237 void DAGTypeLegalizer::SplitVecRes_VECTOR_SHUFFLE(ShuffleVectorSDNode *N,
1238 SDValue &Lo, SDValue &Hi) {
1239 // The low and high parts of the original input give four input vectors.
1242 GetSplitVector(N->getOperand(0), Inputs[0], Inputs[1]);
1243 GetSplitVector(N->getOperand(1), Inputs[2], Inputs[3]);
1244 EVT NewVT = Inputs[0].getValueType();
1245 unsigned NewElts = NewVT.getVectorNumElements();
1247 // If Lo or Hi uses elements from at most two of the four input vectors, then
1248 // express it as a vector shuffle of those two inputs. Otherwise extract the
1249 // input elements by hand and construct the Lo/Hi output using a BUILD_VECTOR.
1250 SmallVector<int, 16> Ops;
1251 for (unsigned High = 0; High < 2; ++High) {
1252 SDValue &Output = High ? Hi : Lo;
1254 // Build a shuffle mask for the output, discovering on the fly which
1255 // input vectors to use as shuffle operands (recorded in InputUsed).
1256 // If building a suitable shuffle vector proves too hard, then bail
1257 // out with useBuildVector set.
1258 unsigned InputUsed[2] = { -1U, -1U }; // Not yet discovered.
1259 unsigned FirstMaskIdx = High * NewElts;
1260 bool useBuildVector = false;
1261 for (unsigned MaskOffset = 0; MaskOffset < NewElts; ++MaskOffset) {
1262 // The mask element. This indexes into the input.
1263 int Idx = N->getMaskElt(FirstMaskIdx + MaskOffset);
1265 // The input vector this mask element indexes into.
1266 unsigned Input = (unsigned)Idx / NewElts;
1268 if (Input >= array_lengthof(Inputs)) {
1269 // The mask element does not index into any input vector.
1274 // Turn the index into an offset from the start of the input vector.
1275 Idx -= Input * NewElts;
1277 // Find or create a shuffle vector operand to hold this input.
1279 for (OpNo = 0; OpNo < array_lengthof(InputUsed); ++OpNo) {
1280 if (InputUsed[OpNo] == Input) {
1281 // This input vector is already an operand.
1283 } else if (InputUsed[OpNo] == -1U) {
1284 // Create a new operand for this input vector.
1285 InputUsed[OpNo] = Input;
1290 if (OpNo >= array_lengthof(InputUsed)) {
1291 // More than two input vectors used! Give up on trying to create a
1292 // shuffle vector. Insert all elements into a BUILD_VECTOR instead.
1293 useBuildVector = true;
1297 // Add the mask index for the new shuffle vector.
1298 Ops.push_back(Idx + OpNo * NewElts);
1301 if (useBuildVector) {
1302 EVT EltVT = NewVT.getVectorElementType();
1303 SmallVector<SDValue, 16> SVOps;
1305 // Extract the input elements by hand.
1306 for (unsigned MaskOffset = 0; MaskOffset < NewElts; ++MaskOffset) {
1307 // The mask element. This indexes into the input.
1308 int Idx = N->getMaskElt(FirstMaskIdx + MaskOffset);
1310 // The input vector this mask element indexes into.
1311 unsigned Input = (unsigned)Idx / NewElts;
1313 if (Input >= array_lengthof(Inputs)) {
1314 // The mask element is "undef" or indexes off the end of the input.
1315 SVOps.push_back(DAG.getUNDEF(EltVT));
1319 // Turn the index into an offset from the start of the input vector.
1320 Idx -= Input * NewElts;
1322 // Extract the vector element by hand.
1323 SVOps.push_back(DAG.getNode(
1324 ISD::EXTRACT_VECTOR_ELT, dl, EltVT, Inputs[Input],
1325 DAG.getConstant(Idx, dl, TLI.getVectorIdxTy(DAG.getDataLayout()))));
1328 // Construct the Lo/Hi output using a BUILD_VECTOR.
1329 Output = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, SVOps);
1330 } else if (InputUsed[0] == -1U) {
1331 // No input vectors were used! The result is undefined.
1332 Output = DAG.getUNDEF(NewVT);
1334 SDValue Op0 = Inputs[InputUsed[0]];
1335 // If only one input was used, use an undefined vector for the other.
1336 SDValue Op1 = InputUsed[1] == -1U ?
1337 DAG.getUNDEF(NewVT) : Inputs[InputUsed[1]];
1338 // At least one input vector was used. Create a new shuffle vector.
1339 Output = DAG.getVectorShuffle(NewVT, dl, Op0, Op1, &Ops[0]);
1347 //===----------------------------------------------------------------------===//
1348 // Operand Vector Splitting
1349 //===----------------------------------------------------------------------===//
1351 /// SplitVectorOperand - This method is called when the specified operand of the
1352 /// specified node is found to need vector splitting. At this point, all of the
1353 /// result types of the node are known to be legal, but other operands of the
1354 /// node may need legalization as well as the specified one.
1355 bool DAGTypeLegalizer::SplitVectorOperand(SDNode *N, unsigned OpNo) {
1356 DEBUG(dbgs() << "Split node operand: ";
1359 SDValue Res = SDValue();
1361 // See if the target wants to custom split this node.
1362 if (CustomLowerNode(N, N->getOperand(OpNo).getValueType(), false))
1365 if (!Res.getNode()) {
1366 switch (N->getOpcode()) {
1369 dbgs() << "SplitVectorOperand Op #" << OpNo << ": ";
1373 report_fatal_error("Do not know how to split this operator's "
1376 case ISD::SETCC: Res = SplitVecOp_VSETCC(N); break;
1377 case ISD::BITCAST: Res = SplitVecOp_BITCAST(N); break;
1378 case ISD::EXTRACT_SUBVECTOR: Res = SplitVecOp_EXTRACT_SUBVECTOR(N); break;
1379 case ISD::EXTRACT_VECTOR_ELT:Res = SplitVecOp_EXTRACT_VECTOR_ELT(N); break;
1380 case ISD::CONCAT_VECTORS: Res = SplitVecOp_CONCAT_VECTORS(N); break;
1382 Res = SplitVecOp_TruncateHelper(N);
1384 case ISD::FP_ROUND: Res = SplitVecOp_FP_ROUND(N); break;
1385 case ISD::FCOPYSIGN: Res = SplitVecOp_FCOPYSIGN(N); break;
1387 Res = SplitVecOp_STORE(cast<StoreSDNode>(N), OpNo);
1390 Res = SplitVecOp_MSTORE(cast<MaskedStoreSDNode>(N), OpNo);
1393 Res = SplitVecOp_MSCATTER(cast<MaskedScatterSDNode>(N), OpNo);
1396 Res = SplitVecOp_MGATHER(cast<MaskedGatherSDNode>(N), OpNo);
1399 Res = SplitVecOp_VSELECT(N, OpNo);
1401 case ISD::FP_TO_SINT:
1402 case ISD::FP_TO_UINT:
1403 if (N->getValueType(0).bitsLT(N->getOperand(0)->getValueType(0)))
1404 Res = SplitVecOp_TruncateHelper(N);
1406 Res = SplitVecOp_UnaryOp(N);
1408 case ISD::SINT_TO_FP:
1409 case ISD::UINT_TO_FP:
1410 if (N->getValueType(0).bitsLT(N->getOperand(0)->getValueType(0)))
1411 Res = SplitVecOp_TruncateHelper(N);
1413 Res = SplitVecOp_UnaryOp(N);
1418 case ISD::FP_EXTEND:
1419 case ISD::SIGN_EXTEND:
1420 case ISD::ZERO_EXTEND:
1421 case ISD::ANY_EXTEND:
1423 Res = SplitVecOp_UnaryOp(N);
1428 // If the result is null, the sub-method took care of registering results etc.
1429 if (!Res.getNode()) return false;
1431 // If the result is N, the sub-method updated N in place. Tell the legalizer
1433 if (Res.getNode() == N)
1436 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 &&
1437 "Invalid operand expansion");
1439 ReplaceValueWith(SDValue(N, 0), Res);
1443 SDValue DAGTypeLegalizer::SplitVecOp_VSELECT(SDNode *N, unsigned OpNo) {
1444 // The only possibility for an illegal operand is the mask, since result type
1445 // legalization would have handled this node already otherwise.
1446 assert(OpNo == 0 && "Illegal operand must be mask");
1448 SDValue Mask = N->getOperand(0);
1449 SDValue Src0 = N->getOperand(1);
1450 SDValue Src1 = N->getOperand(2);
1451 EVT Src0VT = Src0.getValueType();
1453 assert(Mask.getValueType().isVector() && "VSELECT without a vector mask?");
1456 GetSplitVector(N->getOperand(0), Lo, Hi);
1457 assert(Lo.getValueType() == Hi.getValueType() &&
1458 "Lo and Hi have differing types");
1461 std::tie(LoOpVT, HiOpVT) = DAG.GetSplitDestVTs(Src0VT);
1462 assert(LoOpVT == HiOpVT && "Asymmetric vector split?");
1464 SDValue LoOp0, HiOp0, LoOp1, HiOp1, LoMask, HiMask;
1465 std::tie(LoOp0, HiOp0) = DAG.SplitVector(Src0, DL);
1466 std::tie(LoOp1, HiOp1) = DAG.SplitVector(Src1, DL);
1467 std::tie(LoMask, HiMask) = DAG.SplitVector(Mask, DL);
1470 DAG.getNode(ISD::VSELECT, DL, LoOpVT, LoMask, LoOp0, LoOp1);
1472 DAG.getNode(ISD::VSELECT, DL, HiOpVT, HiMask, HiOp0, HiOp1);
1474 return DAG.getNode(ISD::CONCAT_VECTORS, DL, Src0VT, LoSelect, HiSelect);
1477 SDValue DAGTypeLegalizer::SplitVecOp_UnaryOp(SDNode *N) {
1478 // The result has a legal vector type, but the input needs splitting.
1479 EVT ResVT = N->getValueType(0);
1482 GetSplitVector(N->getOperand(0), Lo, Hi);
1483 EVT InVT = Lo.getValueType();
1485 EVT OutVT = EVT::getVectorVT(*DAG.getContext(), ResVT.getVectorElementType(),
1486 InVT.getVectorNumElements());
1488 Lo = DAG.getNode(N->getOpcode(), dl, OutVT, Lo);
1489 Hi = DAG.getNode(N->getOpcode(), dl, OutVT, Hi);
1491 return DAG.getNode(ISD::CONCAT_VECTORS, dl, ResVT, Lo, Hi);
1494 SDValue DAGTypeLegalizer::SplitVecOp_BITCAST(SDNode *N) {
1495 // For example, i64 = BITCAST v4i16 on alpha. Typically the vector will
1496 // end up being split all the way down to individual components. Convert the
1497 // split pieces into integers and reassemble.
1499 GetSplitVector(N->getOperand(0), Lo, Hi);
1500 Lo = BitConvertToInteger(Lo);
1501 Hi = BitConvertToInteger(Hi);
1503 if (DAG.getDataLayout().isBigEndian())
1506 return DAG.getNode(ISD::BITCAST, SDLoc(N), N->getValueType(0),
1507 JoinIntegers(Lo, Hi));
1510 SDValue DAGTypeLegalizer::SplitVecOp_EXTRACT_SUBVECTOR(SDNode *N) {
1511 // We know that the extracted result type is legal.
1512 EVT SubVT = N->getValueType(0);
1513 SDValue Idx = N->getOperand(1);
1516 GetSplitVector(N->getOperand(0), Lo, Hi);
1518 uint64_t LoElts = Lo.getValueType().getVectorNumElements();
1519 uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
1521 if (IdxVal < LoElts) {
1522 assert(IdxVal + SubVT.getVectorNumElements() <= LoElts &&
1523 "Extracted subvector crosses vector split!");
1524 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, Lo, Idx);
1526 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, Hi,
1527 DAG.getConstant(IdxVal - LoElts, dl,
1528 Idx.getValueType()));
1532 SDValue DAGTypeLegalizer::SplitVecOp_EXTRACT_VECTOR_ELT(SDNode *N) {
1533 SDValue Vec = N->getOperand(0);
1534 SDValue Idx = N->getOperand(1);
1535 EVT VecVT = Vec.getValueType();
1537 if (isa<ConstantSDNode>(Idx)) {
1538 uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
1539 assert(IdxVal < VecVT.getVectorNumElements() && "Invalid vector index!");
1542 GetSplitVector(Vec, Lo, Hi);
1544 uint64_t LoElts = Lo.getValueType().getVectorNumElements();
1546 if (IdxVal < LoElts)
1547 return SDValue(DAG.UpdateNodeOperands(N, Lo, Idx), 0);
1548 return SDValue(DAG.UpdateNodeOperands(N, Hi,
1549 DAG.getConstant(IdxVal - LoElts, SDLoc(N),
1550 Idx.getValueType())), 0);
1553 // See if the target wants to custom expand this node.
1554 if (CustomLowerNode(N, N->getValueType(0), true))
1557 // Store the vector to the stack.
1558 EVT EltVT = VecVT.getVectorElementType();
1560 SDValue StackPtr = DAG.CreateStackTemporary(VecVT);
1561 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Vec, StackPtr,
1562 MachinePointerInfo(), false, false, 0);
1564 // Load back the required element.
1565 StackPtr = GetVectorElementPointer(StackPtr, EltVT, Idx);
1566 return DAG.getExtLoad(ISD::EXTLOAD, dl, N->getValueType(0), Store, StackPtr,
1567 MachinePointerInfo(), EltVT, false, false, false, 0);
1570 SDValue DAGTypeLegalizer::SplitVecOp_MGATHER(MaskedGatherSDNode *MGT,
1574 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(MGT->getValueType(0));
1576 SDValue Ch = MGT->getChain();
1577 SDValue Ptr = MGT->getBasePtr();
1578 SDValue Index = MGT->getIndex();
1579 SDValue Mask = MGT->getMask();
1580 unsigned Alignment = MGT->getOriginalAlignment();
1582 SDValue MaskLo, MaskHi;
1583 std::tie(MaskLo, MaskHi) = DAG.SplitVector(Mask, dl);
1585 EVT MemoryVT = MGT->getMemoryVT();
1586 EVT LoMemVT, HiMemVT;
1587 std::tie(LoMemVT, HiMemVT) = DAG.GetSplitDestVTs(MemoryVT);
1589 SDValue Src0Lo, Src0Hi;
1590 std::tie(Src0Lo, Src0Hi) = DAG.SplitVector(MGT->getValue(), dl);
1592 SDValue IndexHi, IndexLo;
1593 if (Index.getNode())
1594 std::tie(IndexLo, IndexHi) = DAG.SplitVector(Index, dl);
1596 IndexLo = IndexHi = Index;
1598 MachineMemOperand *MMO = DAG.getMachineFunction().
1599 getMachineMemOperand(MGT->getPointerInfo(),
1600 MachineMemOperand::MOLoad, LoMemVT.getStoreSize(),
1601 Alignment, MGT->getAAInfo(), MGT->getRanges());
1603 SDValue OpsLo[] = {Ch, Src0Lo, MaskLo, Ptr, IndexLo};
1604 SDValue Lo = DAG.getMaskedGather(DAG.getVTList(LoVT, MVT::Other), LoVT, dl,
1607 MMO = DAG.getMachineFunction().
1608 getMachineMemOperand(MGT->getPointerInfo(),
1609 MachineMemOperand::MOLoad, HiMemVT.getStoreSize(),
1610 Alignment, MGT->getAAInfo(),
1613 SDValue OpsHi[] = {Ch, Src0Hi, MaskHi, Ptr, IndexHi};
1614 SDValue Hi = DAG.getMaskedGather(DAG.getVTList(HiVT, MVT::Other), HiVT, dl,
1617 // Build a factor node to remember that this load is independent of the
1619 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
1622 // Legalized the chain result - switch anything that used the old chain to
1624 ReplaceValueWith(SDValue(MGT, 1), Ch);
1626 SDValue Res = DAG.getNode(ISD::CONCAT_VECTORS, dl, MGT->getValueType(0), Lo,
1628 ReplaceValueWith(SDValue(MGT, 0), Res);
1632 SDValue DAGTypeLegalizer::SplitVecOp_MSTORE(MaskedStoreSDNode *N,
1634 SDValue Ch = N->getChain();
1635 SDValue Ptr = N->getBasePtr();
1636 SDValue Mask = N->getMask();
1637 SDValue Data = N->getValue();
1638 EVT MemoryVT = N->getMemoryVT();
1639 unsigned Alignment = N->getOriginalAlignment();
1642 EVT LoMemVT, HiMemVT;
1643 std::tie(LoMemVT, HiMemVT) = DAG.GetSplitDestVTs(MemoryVT);
1645 SDValue DataLo, DataHi;
1646 GetSplitVector(Data, DataLo, DataHi);
1647 SDValue MaskLo, MaskHi;
1648 GetSplitVector(Mask, MaskLo, MaskHi);
1650 // if Alignment is equal to the vector size,
1651 // take the half of it for the second part
1652 unsigned SecondHalfAlignment =
1653 (Alignment == Data->getValueType(0).getSizeInBits()/8) ?
1654 Alignment/2 : Alignment;
1657 MachineMemOperand *MMO = DAG.getMachineFunction().
1658 getMachineMemOperand(N->getPointerInfo(),
1659 MachineMemOperand::MOStore, LoMemVT.getStoreSize(),
1660 Alignment, N->getAAInfo(), N->getRanges());
1662 Lo = DAG.getMaskedStore(Ch, DL, DataLo, Ptr, MaskLo, LoMemVT, MMO,
1663 N->isTruncatingStore());
1665 unsigned IncrementSize = LoMemVT.getSizeInBits()/8;
1666 Ptr = DAG.getNode(ISD::ADD, DL, Ptr.getValueType(), Ptr,
1667 DAG.getConstant(IncrementSize, DL, Ptr.getValueType()));
1669 MMO = DAG.getMachineFunction().
1670 getMachineMemOperand(N->getPointerInfo(),
1671 MachineMemOperand::MOStore, HiMemVT.getStoreSize(),
1672 SecondHalfAlignment, N->getAAInfo(), N->getRanges());
1674 Hi = DAG.getMaskedStore(Ch, DL, DataHi, Ptr, MaskHi, HiMemVT, MMO,
1675 N->isTruncatingStore());
1677 // Build a factor node to remember that this store is independent of the
1679 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Lo, Hi);
1682 SDValue DAGTypeLegalizer::SplitVecOp_MSCATTER(MaskedScatterSDNode *N,
1684 SDValue Ch = N->getChain();
1685 SDValue Ptr = N->getBasePtr();
1686 SDValue Mask = N->getMask();
1687 SDValue Index = N->getIndex();
1688 SDValue Data = N->getValue();
1689 EVT MemoryVT = N->getMemoryVT();
1690 unsigned Alignment = N->getOriginalAlignment();
1693 EVT LoMemVT, HiMemVT;
1694 std::tie(LoMemVT, HiMemVT) = DAG.GetSplitDestVTs(MemoryVT);
1696 SDValue DataLo, DataHi;
1697 GetSplitVector(Data, DataLo, DataHi);
1698 SDValue MaskLo, MaskHi;
1699 GetSplitVector(Mask, MaskLo, MaskHi);
1701 SDValue PtrLo, PtrHi;
1702 if (Ptr.getValueType().isVector()) // gather form vector of pointers
1703 std::tie(PtrLo, PtrHi) = DAG.SplitVector(Ptr, DL);
1705 PtrLo = PtrHi = Ptr;
1707 SDValue IndexHi, IndexLo;
1708 if (Index.getNode())
1709 std::tie(IndexLo, IndexHi) = DAG.SplitVector(Index, DL);
1711 IndexLo = IndexHi = Index;
1714 MachineMemOperand *MMO = DAG.getMachineFunction().
1715 getMachineMemOperand(N->getPointerInfo(),
1716 MachineMemOperand::MOStore, LoMemVT.getStoreSize(),
1717 Alignment, N->getAAInfo(), N->getRanges());
1719 SDValue OpsLo[] = {Ch, DataLo, MaskLo, PtrLo, IndexLo};
1720 Lo = DAG.getMaskedScatter(DAG.getVTList(MVT::Other), DataLo.getValueType(),
1723 MMO = DAG.getMachineFunction().
1724 getMachineMemOperand(N->getPointerInfo(),
1725 MachineMemOperand::MOStore, HiMemVT.getStoreSize(),
1726 Alignment, N->getAAInfo(), N->getRanges());
1728 SDValue OpsHi[] = {Ch, DataHi, MaskHi, PtrHi, IndexHi};
1729 Hi = DAG.getMaskedScatter(DAG.getVTList(MVT::Other), DataHi.getValueType(),
1732 // Build a factor node to remember that this store is independent of the
1734 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Lo, Hi);
1737 SDValue DAGTypeLegalizer::SplitVecOp_STORE(StoreSDNode *N, unsigned OpNo) {
1738 assert(N->isUnindexed() && "Indexed store of vector?");
1739 assert(OpNo == 1 && "Can only split the stored value");
1742 bool isTruncating = N->isTruncatingStore();
1743 SDValue Ch = N->getChain();
1744 SDValue Ptr = N->getBasePtr();
1745 EVT MemoryVT = N->getMemoryVT();
1746 unsigned Alignment = N->getOriginalAlignment();
1747 bool isVol = N->isVolatile();
1748 bool isNT = N->isNonTemporal();
1749 AAMDNodes AAInfo = N->getAAInfo();
1751 GetSplitVector(N->getOperand(1), Lo, Hi);
1753 EVT LoMemVT, HiMemVT;
1754 std::tie(LoMemVT, HiMemVT) = DAG.GetSplitDestVTs(MemoryVT);
1756 unsigned IncrementSize = LoMemVT.getSizeInBits()/8;
1759 Lo = DAG.getTruncStore(Ch, DL, Lo, Ptr, N->getPointerInfo(),
1760 LoMemVT, isVol, isNT, Alignment, AAInfo);
1762 Lo = DAG.getStore(Ch, DL, Lo, Ptr, N->getPointerInfo(),
1763 isVol, isNT, Alignment, AAInfo);
1765 // Increment the pointer to the other half.
1766 Ptr = DAG.getNode(ISD::ADD, DL, Ptr.getValueType(), Ptr,
1767 DAG.getConstant(IncrementSize, DL, Ptr.getValueType()));
1770 Hi = DAG.getTruncStore(Ch, DL, Hi, Ptr,
1771 N->getPointerInfo().getWithOffset(IncrementSize),
1772 HiMemVT, isVol, isNT, Alignment, AAInfo);
1774 Hi = DAG.getStore(Ch, DL, Hi, Ptr,
1775 N->getPointerInfo().getWithOffset(IncrementSize),
1776 isVol, isNT, Alignment, AAInfo);
1778 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Lo, Hi);
1781 SDValue DAGTypeLegalizer::SplitVecOp_CONCAT_VECTORS(SDNode *N) {
1784 // The input operands all must have the same type, and we know the result
1785 // type is valid. Convert this to a buildvector which extracts all the
1787 // TODO: If the input elements are power-two vectors, we could convert this to
1788 // a new CONCAT_VECTORS node with elements that are half-wide.
1789 SmallVector<SDValue, 32> Elts;
1790 EVT EltVT = N->getValueType(0).getVectorElementType();
1791 for (const SDValue &Op : N->op_values()) {
1792 for (unsigned i = 0, e = Op.getValueType().getVectorNumElements();
1794 Elts.push_back(DAG.getNode(
1795 ISD::EXTRACT_VECTOR_ELT, DL, EltVT, Op,
1796 DAG.getConstant(i, DL, TLI.getVectorIdxTy(DAG.getDataLayout()))));
1800 return DAG.getNode(ISD::BUILD_VECTOR, DL, N->getValueType(0), Elts);
1803 SDValue DAGTypeLegalizer::SplitVecOp_TruncateHelper(SDNode *N) {
1804 // The result type is legal, but the input type is illegal. If splitting
1805 // ends up with the result type of each half still being legal, just
1806 // do that. If, however, that would result in an illegal result type,
1807 // we can try to get more clever with power-two vectors. Specifically,
1808 // split the input type, but also widen the result element size, then
1809 // concatenate the halves and truncate again. For example, consider a target
1810 // where v8i8 is legal and v8i32 is not (ARM, which doesn't have 256-bit
1811 // vectors). To perform a "%res = v8i8 trunc v8i32 %in" we do:
1812 // %inlo = v4i32 extract_subvector %in, 0
1813 // %inhi = v4i32 extract_subvector %in, 4
1814 // %lo16 = v4i16 trunc v4i32 %inlo
1815 // %hi16 = v4i16 trunc v4i32 %inhi
1816 // %in16 = v8i16 concat_vectors v4i16 %lo16, v4i16 %hi16
1817 // %res = v8i8 trunc v8i16 %in16
1819 // Without this transform, the original truncate would end up being
1820 // scalarized, which is pretty much always a last resort.
1821 SDValue InVec = N->getOperand(0);
1822 EVT InVT = InVec->getValueType(0);
1823 EVT OutVT = N->getValueType(0);
1824 unsigned NumElements = OutVT.getVectorNumElements();
1825 bool IsFloat = OutVT.isFloatingPoint();
1827 // Widening should have already made sure this is a power-two vector
1828 // if we're trying to split it at all. assert() that's true, just in case.
1829 assert(!(NumElements & 1) && "Splitting vector, but not in half!");
1831 unsigned InElementSize = InVT.getVectorElementType().getSizeInBits();
1832 unsigned OutElementSize = OutVT.getVectorElementType().getSizeInBits();
1834 // If the input elements are only 1/2 the width of the result elements,
1835 // just use the normal splitting. Our trick only work if there's room
1836 // to split more than once.
1837 if (InElementSize <= OutElementSize * 2)
1838 return SplitVecOp_UnaryOp(N);
1841 // Extract the halves of the input via extract_subvector.
1842 SDValue InLoVec, InHiVec;
1843 std::tie(InLoVec, InHiVec) = DAG.SplitVector(InVec, DL);
1844 // Truncate them to 1/2 the element size.
1845 EVT HalfElementVT = IsFloat ?
1846 EVT::getFloatingPointVT(InElementSize/2) :
1847 EVT::getIntegerVT(*DAG.getContext(), InElementSize/2);
1848 EVT HalfVT = EVT::getVectorVT(*DAG.getContext(), HalfElementVT,
1850 SDValue HalfLo = DAG.getNode(N->getOpcode(), DL, HalfVT, InLoVec);
1851 SDValue HalfHi = DAG.getNode(N->getOpcode(), DL, HalfVT, InHiVec);
1852 // Concatenate them to get the full intermediate truncation result.
1853 EVT InterVT = EVT::getVectorVT(*DAG.getContext(), HalfElementVT, NumElements);
1854 SDValue InterVec = DAG.getNode(ISD::CONCAT_VECTORS, DL, InterVT, HalfLo,
1856 // Now finish up by truncating all the way down to the original result
1857 // type. This should normally be something that ends up being legal directly,
1858 // but in theory if a target has very wide vectors and an annoyingly
1859 // restricted set of legal types, this split can chain to build things up.
1861 ? DAG.getNode(ISD::FP_ROUND, DL, OutVT, InterVec,
1862 DAG.getTargetConstant(
1863 0, DL, TLI.getPointerTy(DAG.getDataLayout())))
1864 : DAG.getNode(ISD::TRUNCATE, DL, OutVT, InterVec);
1867 SDValue DAGTypeLegalizer::SplitVecOp_VSETCC(SDNode *N) {
1868 assert(N->getValueType(0).isVector() &&
1869 N->getOperand(0).getValueType().isVector() &&
1870 "Operand types must be vectors");
1871 // The result has a legal vector type, but the input needs splitting.
1872 SDValue Lo0, Hi0, Lo1, Hi1, LoRes, HiRes;
1874 GetSplitVector(N->getOperand(0), Lo0, Hi0);
1875 GetSplitVector(N->getOperand(1), Lo1, Hi1);
1876 unsigned PartElements = Lo0.getValueType().getVectorNumElements();
1877 EVT PartResVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1, PartElements);
1878 EVT WideResVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1, 2*PartElements);
1880 LoRes = DAG.getNode(ISD::SETCC, DL, PartResVT, Lo0, Lo1, N->getOperand(2));
1881 HiRes = DAG.getNode(ISD::SETCC, DL, PartResVT, Hi0, Hi1, N->getOperand(2));
1882 SDValue Con = DAG.getNode(ISD::CONCAT_VECTORS, DL, WideResVT, LoRes, HiRes);
1883 return PromoteTargetBoolean(Con, N->getValueType(0));
1887 SDValue DAGTypeLegalizer::SplitVecOp_FP_ROUND(SDNode *N) {
1888 // The result has a legal vector type, but the input needs splitting.
1889 EVT ResVT = N->getValueType(0);
1892 GetSplitVector(N->getOperand(0), Lo, Hi);
1893 EVT InVT = Lo.getValueType();
1895 EVT OutVT = EVT::getVectorVT(*DAG.getContext(), ResVT.getVectorElementType(),
1896 InVT.getVectorNumElements());
1898 Lo = DAG.getNode(ISD::FP_ROUND, DL, OutVT, Lo, N->getOperand(1));
1899 Hi = DAG.getNode(ISD::FP_ROUND, DL, OutVT, Hi, N->getOperand(1));
1901 return DAG.getNode(ISD::CONCAT_VECTORS, DL, ResVT, Lo, Hi);
1904 SDValue DAGTypeLegalizer::SplitVecOp_FCOPYSIGN(SDNode *N) {
1905 // The result (and the first input) has a legal vector type, but the second
1906 // input needs splitting.
1907 return DAG.UnrollVectorOp(N, N->getValueType(0).getVectorNumElements());
1911 //===----------------------------------------------------------------------===//
1912 // Result Vector Widening
1913 //===----------------------------------------------------------------------===//
1915 void DAGTypeLegalizer::WidenVectorResult(SDNode *N, unsigned ResNo) {
1916 DEBUG(dbgs() << "Widen node result " << ResNo << ": ";
1920 // See if the target wants to custom widen this node.
1921 if (CustomWidenLowerNode(N, N->getValueType(ResNo)))
1924 SDValue Res = SDValue();
1925 switch (N->getOpcode()) {
1928 dbgs() << "WidenVectorResult #" << ResNo << ": ";
1932 llvm_unreachable("Do not know how to widen the result of this operator!");
1934 case ISD::MERGE_VALUES: Res = WidenVecRes_MERGE_VALUES(N, ResNo); break;
1935 case ISD::BITCAST: Res = WidenVecRes_BITCAST(N); break;
1936 case ISD::BUILD_VECTOR: Res = WidenVecRes_BUILD_VECTOR(N); break;
1937 case ISD::CONCAT_VECTORS: Res = WidenVecRes_CONCAT_VECTORS(N); break;
1938 case ISD::CONVERT_RNDSAT: Res = WidenVecRes_CONVERT_RNDSAT(N); break;
1939 case ISD::EXTRACT_SUBVECTOR: Res = WidenVecRes_EXTRACT_SUBVECTOR(N); break;
1940 case ISD::FP_ROUND_INREG: Res = WidenVecRes_InregOp(N); break;
1941 case ISD::INSERT_VECTOR_ELT: Res = WidenVecRes_INSERT_VECTOR_ELT(N); break;
1942 case ISD::LOAD: Res = WidenVecRes_LOAD(N); break;
1943 case ISD::SCALAR_TO_VECTOR: Res = WidenVecRes_SCALAR_TO_VECTOR(N); break;
1944 case ISD::SIGN_EXTEND_INREG: Res = WidenVecRes_InregOp(N); break;
1946 case ISD::SELECT: Res = WidenVecRes_SELECT(N); break;
1947 case ISD::SELECT_CC: Res = WidenVecRes_SELECT_CC(N); break;
1948 case ISD::SETCC: Res = WidenVecRes_SETCC(N); break;
1949 case ISD::UNDEF: Res = WidenVecRes_UNDEF(N); break;
1950 case ISD::VECTOR_SHUFFLE:
1951 Res = WidenVecRes_VECTOR_SHUFFLE(cast<ShuffleVectorSDNode>(N));
1954 Res = WidenVecRes_MLOAD(cast<MaskedLoadSDNode>(N));
1969 Res = WidenVecRes_Binary(N);
1982 Res = WidenVecRes_BinaryCanTrap(N);
1985 case ISD::FCOPYSIGN:
1986 Res = WidenVecRes_FCOPYSIGN(N);
1990 Res = WidenVecRes_POWI(N);
1996 Res = WidenVecRes_Shift(N);
1999 case ISD::ANY_EXTEND:
2000 case ISD::FP_EXTEND:
2002 case ISD::FP_TO_SINT:
2003 case ISD::FP_TO_UINT:
2004 case ISD::SIGN_EXTEND:
2005 case ISD::SINT_TO_FP:
2007 case ISD::UINT_TO_FP:
2008 case ISD::ZERO_EXTEND:
2009 Res = WidenVecRes_Convert(N);
2025 case ISD::FNEARBYINT:
2032 Res = WidenVecRes_Unary(N);
2035 Res = WidenVecRes_Ternary(N);
2039 // If Res is null, the sub-method took care of registering the result.
2041 SetWidenedVector(SDValue(N, ResNo), Res);
2044 SDValue DAGTypeLegalizer::WidenVecRes_Ternary(SDNode *N) {
2045 // Ternary op widening.
2047 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2048 SDValue InOp1 = GetWidenedVector(N->getOperand(0));
2049 SDValue InOp2 = GetWidenedVector(N->getOperand(1));
2050 SDValue InOp3 = GetWidenedVector(N->getOperand(2));
2051 return DAG.getNode(N->getOpcode(), dl, WidenVT, InOp1, InOp2, InOp3);
2054 SDValue DAGTypeLegalizer::WidenVecRes_Binary(SDNode *N) {
2055 // Binary op widening.
2057 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2058 SDValue InOp1 = GetWidenedVector(N->getOperand(0));
2059 SDValue InOp2 = GetWidenedVector(N->getOperand(1));
2060 return DAG.getNode(N->getOpcode(), dl, WidenVT, InOp1, InOp2);
2063 SDValue DAGTypeLegalizer::WidenVecRes_BinaryCanTrap(SDNode *N) {
2064 // Binary op widening for operations that can trap.
2065 unsigned Opcode = N->getOpcode();
2067 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2068 EVT WidenEltVT = WidenVT.getVectorElementType();
2070 unsigned NumElts = VT.getVectorNumElements();
2071 while (!TLI.isTypeLegal(VT) && NumElts != 1) {
2072 NumElts = NumElts / 2;
2073 VT = EVT::getVectorVT(*DAG.getContext(), WidenEltVT, NumElts);
2076 if (NumElts != 1 && !TLI.canOpTrap(N->getOpcode(), VT)) {
2077 // Operation doesn't trap so just widen as normal.
2078 SDValue InOp1 = GetWidenedVector(N->getOperand(0));
2079 SDValue InOp2 = GetWidenedVector(N->getOperand(1));
2080 return DAG.getNode(N->getOpcode(), dl, WidenVT, InOp1, InOp2);
2083 // No legal vector version so unroll the vector operation and then widen.
2085 return DAG.UnrollVectorOp(N, WidenVT.getVectorNumElements());
2087 // Since the operation can trap, apply operation on the original vector.
2089 SDValue InOp1 = GetWidenedVector(N->getOperand(0));
2090 SDValue InOp2 = GetWidenedVector(N->getOperand(1));
2091 unsigned CurNumElts = N->getValueType(0).getVectorNumElements();
2093 SmallVector<SDValue, 16> ConcatOps(CurNumElts);
2094 unsigned ConcatEnd = 0; // Current ConcatOps index.
2095 int Idx = 0; // Current Idx into input vectors.
2097 // NumElts := greatest legal vector size (at most WidenVT)
2098 // while (orig. vector has unhandled elements) {
2099 // take munches of size NumElts from the beginning and add to ConcatOps
2100 // NumElts := next smaller supported vector size or 1
2102 while (CurNumElts != 0) {
2103 while (CurNumElts >= NumElts) {
2104 SDValue EOp1 = DAG.getNode(
2105 ISD::EXTRACT_SUBVECTOR, dl, VT, InOp1,
2106 DAG.getConstant(Idx, dl, TLI.getVectorIdxTy(DAG.getDataLayout())));
2107 SDValue EOp2 = DAG.getNode(
2108 ISD::EXTRACT_SUBVECTOR, dl, VT, InOp2,
2109 DAG.getConstant(Idx, dl, TLI.getVectorIdxTy(DAG.getDataLayout())));
2110 ConcatOps[ConcatEnd++] = DAG.getNode(Opcode, dl, VT, EOp1, EOp2);
2112 CurNumElts -= NumElts;
2115 NumElts = NumElts / 2;
2116 VT = EVT::getVectorVT(*DAG.getContext(), WidenEltVT, NumElts);
2117 } while (!TLI.isTypeLegal(VT) && NumElts != 1);
2120 for (unsigned i = 0; i != CurNumElts; ++i, ++Idx) {
2121 SDValue EOp1 = DAG.getNode(
2122 ISD::EXTRACT_VECTOR_ELT, dl, WidenEltVT, InOp1,
2123 DAG.getConstant(Idx, dl, TLI.getVectorIdxTy(DAG.getDataLayout())));
2124 SDValue EOp2 = DAG.getNode(
2125 ISD::EXTRACT_VECTOR_ELT, dl, WidenEltVT, InOp2,
2126 DAG.getConstant(Idx, dl, TLI.getVectorIdxTy(DAG.getDataLayout())));
2127 ConcatOps[ConcatEnd++] = DAG.getNode(Opcode, dl, WidenEltVT,
2134 // Check to see if we have a single operation with the widen type.
2135 if (ConcatEnd == 1) {
2136 VT = ConcatOps[0].getValueType();
2138 return ConcatOps[0];
2141 // while (Some element of ConcatOps is not of type MaxVT) {
2142 // From the end of ConcatOps, collect elements of the same type and put
2143 // them into an op of the next larger supported type
2145 while (ConcatOps[ConcatEnd-1].getValueType() != MaxVT) {
2146 Idx = ConcatEnd - 1;
2147 VT = ConcatOps[Idx--].getValueType();
2148 while (Idx >= 0 && ConcatOps[Idx].getValueType() == VT)
2151 int NextSize = VT.isVector() ? VT.getVectorNumElements() : 1;
2155 NextVT = EVT::getVectorVT(*DAG.getContext(), WidenEltVT, NextSize);
2156 } while (!TLI.isTypeLegal(NextVT));
2158 if (!VT.isVector()) {
2159 // Scalar type, create an INSERT_VECTOR_ELEMENT of type NextVT
2160 SDValue VecOp = DAG.getUNDEF(NextVT);
2161 unsigned NumToInsert = ConcatEnd - Idx - 1;
2162 for (unsigned i = 0, OpIdx = Idx+1; i < NumToInsert; i++, OpIdx++) {
2163 VecOp = DAG.getNode(
2164 ISD::INSERT_VECTOR_ELT, dl, NextVT, VecOp, ConcatOps[OpIdx],
2165 DAG.getConstant(i, dl, TLI.getVectorIdxTy(DAG.getDataLayout())));
2167 ConcatOps[Idx+1] = VecOp;
2168 ConcatEnd = Idx + 2;
2170 // Vector type, create a CONCAT_VECTORS of type NextVT
2171 SDValue undefVec = DAG.getUNDEF(VT);
2172 unsigned OpsToConcat = NextSize/VT.getVectorNumElements();
2173 SmallVector<SDValue, 16> SubConcatOps(OpsToConcat);
2174 unsigned RealVals = ConcatEnd - Idx - 1;
2175 unsigned SubConcatEnd = 0;
2176 unsigned SubConcatIdx = Idx + 1;
2177 while (SubConcatEnd < RealVals)
2178 SubConcatOps[SubConcatEnd++] = ConcatOps[++Idx];
2179 while (SubConcatEnd < OpsToConcat)
2180 SubConcatOps[SubConcatEnd++] = undefVec;
2181 ConcatOps[SubConcatIdx] = DAG.getNode(ISD::CONCAT_VECTORS, dl,
2182 NextVT, SubConcatOps);
2183 ConcatEnd = SubConcatIdx + 1;
2187 // Check to see if we have a single operation with the widen type.
2188 if (ConcatEnd == 1) {
2189 VT = ConcatOps[0].getValueType();
2191 return ConcatOps[0];
2194 // add undefs of size MaxVT until ConcatOps grows to length of WidenVT
2195 unsigned NumOps = WidenVT.getVectorNumElements()/MaxVT.getVectorNumElements();
2196 if (NumOps != ConcatEnd ) {
2197 SDValue UndefVal = DAG.getUNDEF(MaxVT);
2198 for (unsigned j = ConcatEnd; j < NumOps; ++j)
2199 ConcatOps[j] = UndefVal;
2201 return DAG.getNode(ISD::CONCAT_VECTORS, dl, WidenVT,
2202 makeArrayRef(ConcatOps.data(), NumOps));
2205 SDValue DAGTypeLegalizer::WidenVecRes_Convert(SDNode *N) {
2206 SDValue InOp = N->getOperand(0);
2209 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2210 unsigned WidenNumElts = WidenVT.getVectorNumElements();
2212 EVT InVT = InOp.getValueType();
2213 EVT InEltVT = InVT.getVectorElementType();
2214 EVT InWidenVT = EVT::getVectorVT(*DAG.getContext(), InEltVT, WidenNumElts);
2216 unsigned Opcode = N->getOpcode();
2217 unsigned InVTNumElts = InVT.getVectorNumElements();
2219 if (getTypeAction(InVT) == TargetLowering::TypeWidenVector) {
2220 InOp = GetWidenedVector(N->getOperand(0));
2221 InVT = InOp.getValueType();
2222 InVTNumElts = InVT.getVectorNumElements();
2223 if (InVTNumElts == WidenNumElts) {
2224 if (N->getNumOperands() == 1)
2225 return DAG.getNode(Opcode, DL, WidenVT, InOp);
2226 return DAG.getNode(Opcode, DL, WidenVT, InOp, N->getOperand(1));
2230 if (TLI.isTypeLegal(InWidenVT)) {
2231 // Because the result and the input are different vector types, widening
2232 // the result could create a legal type but widening the input might make
2233 // it an illegal type that might lead to repeatedly splitting the input
2234 // and then widening it. To avoid this, we widen the input only if
2235 // it results in a legal type.
2236 if (WidenNumElts % InVTNumElts == 0) {
2237 // Widen the input and call convert on the widened input vector.
2238 unsigned NumConcat = WidenNumElts/InVTNumElts;
2239 SmallVector<SDValue, 16> Ops(NumConcat);
2241 SDValue UndefVal = DAG.getUNDEF(InVT);
2242 for (unsigned i = 1; i != NumConcat; ++i)
2244 SDValue InVec = DAG.getNode(ISD::CONCAT_VECTORS, DL, InWidenVT, Ops);
2245 if (N->getNumOperands() == 1)
2246 return DAG.getNode(Opcode, DL, WidenVT, InVec);
2247 return DAG.getNode(Opcode, DL, WidenVT, InVec, N->getOperand(1));
2250 if (InVTNumElts % WidenNumElts == 0) {
2251 SDValue InVal = DAG.getNode(
2252 ISD::EXTRACT_SUBVECTOR, DL, InWidenVT, InOp,
2253 DAG.getConstant(0, DL, TLI.getVectorIdxTy(DAG.getDataLayout())));
2254 // Extract the input and convert the shorten input vector.
2255 if (N->getNumOperands() == 1)
2256 return DAG.getNode(Opcode, DL, WidenVT, InVal);
2257 return DAG.getNode(Opcode, DL, WidenVT, InVal, N->getOperand(1));
2261 // Otherwise unroll into some nasty scalar code and rebuild the vector.
2262 SmallVector<SDValue, 16> Ops(WidenNumElts);
2263 EVT EltVT = WidenVT.getVectorElementType();
2264 unsigned MinElts = std::min(InVTNumElts, WidenNumElts);
2266 for (i=0; i < MinElts; ++i) {
2267 SDValue Val = DAG.getNode(
2268 ISD::EXTRACT_VECTOR_ELT, DL, InEltVT, InOp,
2269 DAG.getConstant(i, DL, TLI.getVectorIdxTy(DAG.getDataLayout())));
2270 if (N->getNumOperands() == 1)
2271 Ops[i] = DAG.getNode(Opcode, DL, EltVT, Val);
2273 Ops[i] = DAG.getNode(Opcode, DL, EltVT, Val, N->getOperand(1));
2276 SDValue UndefVal = DAG.getUNDEF(EltVT);
2277 for (; i < WidenNumElts; ++i)
2280 return DAG.getNode(ISD::BUILD_VECTOR, DL, WidenVT, Ops);
2283 SDValue DAGTypeLegalizer::WidenVecRes_FCOPYSIGN(SDNode *N) {
2284 // If this is an FCOPYSIGN with same input types, we can treat it as a
2285 // normal (can trap) binary op.
2286 if (N->getOperand(0).getValueType() == N->getOperand(1).getValueType())
2287 return WidenVecRes_BinaryCanTrap(N);
2289 // If the types are different, fall back to unrolling.
2290 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2291 return DAG.UnrollVectorOp(N, WidenVT.getVectorNumElements());
2294 SDValue DAGTypeLegalizer::WidenVecRes_POWI(SDNode *N) {
2295 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2296 SDValue InOp = GetWidenedVector(N->getOperand(0));
2297 SDValue ShOp = N->getOperand(1);
2298 return DAG.getNode(N->getOpcode(), SDLoc(N), WidenVT, InOp, ShOp);
2301 SDValue DAGTypeLegalizer::WidenVecRes_Shift(SDNode *N) {
2302 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2303 SDValue InOp = GetWidenedVector(N->getOperand(0));
2304 SDValue ShOp = N->getOperand(1);
2306 EVT ShVT = ShOp.getValueType();
2307 if (getTypeAction(ShVT) == TargetLowering::TypeWidenVector) {
2308 ShOp = GetWidenedVector(ShOp);
2309 ShVT = ShOp.getValueType();
2311 EVT ShWidenVT = EVT::getVectorVT(*DAG.getContext(),
2312 ShVT.getVectorElementType(),
2313 WidenVT.getVectorNumElements());
2314 if (ShVT != ShWidenVT)
2315 ShOp = ModifyToType(ShOp, ShWidenVT);
2317 return DAG.getNode(N->getOpcode(), SDLoc(N), WidenVT, InOp, ShOp);
2320 SDValue DAGTypeLegalizer::WidenVecRes_Unary(SDNode *N) {
2321 // Unary op widening.
2322 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2323 SDValue InOp = GetWidenedVector(N->getOperand(0));
2324 return DAG.getNode(N->getOpcode(), SDLoc(N), WidenVT, InOp);
2327 SDValue DAGTypeLegalizer::WidenVecRes_InregOp(SDNode *N) {
2328 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2329 EVT ExtVT = EVT::getVectorVT(*DAG.getContext(),
2330 cast<VTSDNode>(N->getOperand(1))->getVT()
2331 .getVectorElementType(),
2332 WidenVT.getVectorNumElements());
2333 SDValue WidenLHS = GetWidenedVector(N->getOperand(0));
2334 return DAG.getNode(N->getOpcode(), SDLoc(N),
2335 WidenVT, WidenLHS, DAG.getValueType(ExtVT));
2338 SDValue DAGTypeLegalizer::WidenVecRes_MERGE_VALUES(SDNode *N, unsigned ResNo) {
2339 SDValue WidenVec = DisintegrateMERGE_VALUES(N, ResNo);
2340 return GetWidenedVector(WidenVec);
2343 SDValue DAGTypeLegalizer::WidenVecRes_BITCAST(SDNode *N) {
2344 SDValue InOp = N->getOperand(0);
2345 EVT InVT = InOp.getValueType();
2346 EVT VT = N->getValueType(0);
2347 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
2350 switch (getTypeAction(InVT)) {
2351 case TargetLowering::TypeLegal:
2353 case TargetLowering::TypePromoteInteger:
2354 // If the incoming type is a vector that is being promoted, then
2355 // we know that the elements are arranged differently and that we
2356 // must perform the conversion using a stack slot.
2357 if (InVT.isVector())
2360 // If the InOp is promoted to the same size, convert it. Otherwise,
2361 // fall out of the switch and widen the promoted input.
2362 InOp = GetPromotedInteger(InOp);
2363 InVT = InOp.getValueType();
2364 if (WidenVT.bitsEq(InVT))
2365 return DAG.getNode(ISD::BITCAST, dl, WidenVT, InOp);
2367 case TargetLowering::TypeSoftenFloat:
2368 case TargetLowering::TypePromoteFloat:
2369 case TargetLowering::TypeExpandInteger:
2370 case TargetLowering::TypeExpandFloat:
2371 case TargetLowering::TypeScalarizeVector:
2372 case TargetLowering::TypeSplitVector:
2374 case TargetLowering::TypeWidenVector:
2375 // If the InOp is widened to the same size, convert it. Otherwise, fall
2376 // out of the switch and widen the widened input.
2377 InOp = GetWidenedVector(InOp);
2378 InVT = InOp.getValueType();
2379 if (WidenVT.bitsEq(InVT))
2380 // The input widens to the same size. Convert to the widen value.
2381 return DAG.getNode(ISD::BITCAST, dl, WidenVT, InOp);
2385 unsigned WidenSize = WidenVT.getSizeInBits();
2386 unsigned InSize = InVT.getSizeInBits();
2387 // x86mmx is not an acceptable vector element type, so don't try.
2388 if (WidenSize % InSize == 0 && InVT != MVT::x86mmx) {
2389 // Determine new input vector type. The new input vector type will use
2390 // the same element type (if its a vector) or use the input type as a
2391 // vector. It is the same size as the type to widen to.
2393 unsigned NewNumElts = WidenSize / InSize;
2394 if (InVT.isVector()) {
2395 EVT InEltVT = InVT.getVectorElementType();
2396 NewInVT = EVT::getVectorVT(*DAG.getContext(), InEltVT,
2397 WidenSize / InEltVT.getSizeInBits());
2399 NewInVT = EVT::getVectorVT(*DAG.getContext(), InVT, NewNumElts);
2402 if (TLI.isTypeLegal(NewInVT)) {
2403 // Because the result and the input are different vector types, widening
2404 // the result could create a legal type but widening the input might make
2405 // it an illegal type that might lead to repeatedly splitting the input
2406 // and then widening it. To avoid this, we widen the input only if
2407 // it results in a legal type.
2408 SmallVector<SDValue, 16> Ops(NewNumElts);
2409 SDValue UndefVal = DAG.getUNDEF(InVT);
2411 for (unsigned i = 1; i < NewNumElts; ++i)
2415 if (InVT.isVector())
2416 NewVec = DAG.getNode(ISD::CONCAT_VECTORS, dl, NewInVT, Ops);
2418 NewVec = DAG.getNode(ISD::BUILD_VECTOR, dl, NewInVT, Ops);
2419 return DAG.getNode(ISD::BITCAST, dl, WidenVT, NewVec);
2423 return CreateStackStoreLoad(InOp, WidenVT);
2426 SDValue DAGTypeLegalizer::WidenVecRes_BUILD_VECTOR(SDNode *N) {
2428 // Build a vector with undefined for the new nodes.
2429 EVT VT = N->getValueType(0);
2431 // Integer BUILD_VECTOR operands may be larger than the node's vector element
2432 // type. The UNDEFs need to have the same type as the existing operands.
2433 EVT EltVT = N->getOperand(0).getValueType();
2434 unsigned NumElts = VT.getVectorNumElements();
2436 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
2437 unsigned WidenNumElts = WidenVT.getVectorNumElements();
2439 SmallVector<SDValue, 16> NewOps(N->op_begin(), N->op_end());
2440 assert(WidenNumElts >= NumElts && "Shrinking vector instead of widening!");
2441 NewOps.append(WidenNumElts - NumElts, DAG.getUNDEF(EltVT));
2443 return DAG.getNode(ISD::BUILD_VECTOR, dl, WidenVT, NewOps);
2446 SDValue DAGTypeLegalizer::WidenVecRes_CONCAT_VECTORS(SDNode *N) {
2447 EVT InVT = N->getOperand(0).getValueType();
2448 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2450 unsigned WidenNumElts = WidenVT.getVectorNumElements();
2451 unsigned NumInElts = InVT.getVectorNumElements();
2452 unsigned NumOperands = N->getNumOperands();
2454 bool InputWidened = false; // Indicates we need to widen the input.
2455 if (getTypeAction(InVT) != TargetLowering::TypeWidenVector) {
2456 if (WidenVT.getVectorNumElements() % InVT.getVectorNumElements() == 0) {
2457 // Add undef vectors to widen to correct length.
2458 unsigned NumConcat = WidenVT.getVectorNumElements() /
2459 InVT.getVectorNumElements();
2460 SDValue UndefVal = DAG.getUNDEF(InVT);
2461 SmallVector<SDValue, 16> Ops(NumConcat);
2462 for (unsigned i=0; i < NumOperands; ++i)
2463 Ops[i] = N->getOperand(i);
2464 for (unsigned i = NumOperands; i != NumConcat; ++i)
2466 return DAG.getNode(ISD::CONCAT_VECTORS, dl, WidenVT, Ops);
2469 InputWidened = true;
2470 if (WidenVT == TLI.getTypeToTransformTo(*DAG.getContext(), InVT)) {
2471 // The inputs and the result are widen to the same value.
2473 for (i=1; i < NumOperands; ++i)
2474 if (N->getOperand(i).getOpcode() != ISD::UNDEF)
2477 if (i == NumOperands)
2478 // Everything but the first operand is an UNDEF so just return the
2479 // widened first operand.
2480 return GetWidenedVector(N->getOperand(0));
2482 if (NumOperands == 2) {
2483 // Replace concat of two operands with a shuffle.
2484 SmallVector<int, 16> MaskOps(WidenNumElts, -1);
2485 for (unsigned i = 0; i < NumInElts; ++i) {
2487 MaskOps[i + NumInElts] = i + WidenNumElts;
2489 return DAG.getVectorShuffle(WidenVT, dl,
2490 GetWidenedVector(N->getOperand(0)),
2491 GetWidenedVector(N->getOperand(1)),
2497 // Fall back to use extracts and build vector.
2498 EVT EltVT = WidenVT.getVectorElementType();
2499 SmallVector<SDValue, 16> Ops(WidenNumElts);
2501 for (unsigned i=0; i < NumOperands; ++i) {
2502 SDValue InOp = N->getOperand(i);
2504 InOp = GetWidenedVector(InOp);
2505 for (unsigned j=0; j < NumInElts; ++j)
2506 Ops[Idx++] = DAG.getNode(
2507 ISD::EXTRACT_VECTOR_ELT, dl, EltVT, InOp,
2508 DAG.getConstant(j, dl, TLI.getVectorIdxTy(DAG.getDataLayout())));
2510 SDValue UndefVal = DAG.getUNDEF(EltVT);
2511 for (; Idx < WidenNumElts; ++Idx)
2512 Ops[Idx] = UndefVal;
2513 return DAG.getNode(ISD::BUILD_VECTOR, dl, WidenVT, Ops);
2516 SDValue DAGTypeLegalizer::WidenVecRes_CONVERT_RNDSAT(SDNode *N) {
2518 SDValue InOp = N->getOperand(0);
2519 SDValue RndOp = N->getOperand(3);
2520 SDValue SatOp = N->getOperand(4);
2522 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2523 unsigned WidenNumElts = WidenVT.getVectorNumElements();
2525 EVT InVT = InOp.getValueType();
2526 EVT InEltVT = InVT.getVectorElementType();
2527 EVT InWidenVT = EVT::getVectorVT(*DAG.getContext(), InEltVT, WidenNumElts);
2529 SDValue DTyOp = DAG.getValueType(WidenVT);
2530 SDValue STyOp = DAG.getValueType(InWidenVT);
2531 ISD::CvtCode CvtCode = cast<CvtRndSatSDNode>(N)->getCvtCode();
2533 unsigned InVTNumElts = InVT.getVectorNumElements();
2534 if (getTypeAction(InVT) == TargetLowering::TypeWidenVector) {
2535 InOp = GetWidenedVector(InOp);
2536 InVT = InOp.getValueType();
2537 InVTNumElts = InVT.getVectorNumElements();
2538 if (InVTNumElts == WidenNumElts)
2539 return DAG.getConvertRndSat(WidenVT, dl, InOp, DTyOp, STyOp, RndOp,
2543 if (TLI.isTypeLegal(InWidenVT)) {
2544 // Because the result and the input are different vector types, widening
2545 // the result could create a legal type but widening the input might make
2546 // it an illegal type that might lead to repeatedly splitting the input
2547 // and then widening it. To avoid this, we widen the input only if
2548 // it results in a legal type.
2549 if (WidenNumElts % InVTNumElts == 0) {
2550 // Widen the input and call convert on the widened input vector.
2551 unsigned NumConcat = WidenNumElts/InVTNumElts;
2552 SmallVector<SDValue, 16> Ops(NumConcat);
2554 SDValue UndefVal = DAG.getUNDEF(InVT);
2555 for (unsigned i = 1; i != NumConcat; ++i)
2558 InOp = DAG.getNode(ISD::CONCAT_VECTORS, dl, InWidenVT, Ops);
2559 return DAG.getConvertRndSat(WidenVT, dl, InOp, DTyOp, STyOp, RndOp,
2563 if (InVTNumElts % WidenNumElts == 0) {
2564 // Extract the input and convert the shorten input vector.
2566 ISD::EXTRACT_SUBVECTOR, dl, InWidenVT, InOp,
2567 DAG.getConstant(0, dl, TLI.getVectorIdxTy(DAG.getDataLayout())));
2568 return DAG.getConvertRndSat(WidenVT, dl, InOp, DTyOp, STyOp, RndOp,
2573 // Otherwise unroll into some nasty scalar code and rebuild the vector.
2574 SmallVector<SDValue, 16> Ops(WidenNumElts);
2575 EVT EltVT = WidenVT.getVectorElementType();
2576 DTyOp = DAG.getValueType(EltVT);
2577 STyOp = DAG.getValueType(InEltVT);
2579 unsigned MinElts = std::min(InVTNumElts, WidenNumElts);
2581 for (i=0; i < MinElts; ++i) {
2582 SDValue ExtVal = DAG.getNode(
2583 ISD::EXTRACT_VECTOR_ELT, dl, InEltVT, InOp,
2584 DAG.getConstant(i, dl, TLI.getVectorIdxTy(DAG.getDataLayout())));
2585 Ops[i] = DAG.getConvertRndSat(WidenVT, dl, ExtVal, DTyOp, STyOp, RndOp,
2589 SDValue UndefVal = DAG.getUNDEF(EltVT);
2590 for (; i < WidenNumElts; ++i)
2593 return DAG.getNode(ISD::BUILD_VECTOR, dl, WidenVT, Ops);
2596 SDValue DAGTypeLegalizer::WidenVecRes_EXTRACT_SUBVECTOR(SDNode *N) {
2597 EVT VT = N->getValueType(0);
2598 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
2599 unsigned WidenNumElts = WidenVT.getVectorNumElements();
2600 SDValue InOp = N->getOperand(0);
2601 SDValue Idx = N->getOperand(1);
2604 if (getTypeAction(InOp.getValueType()) == TargetLowering::TypeWidenVector)
2605 InOp = GetWidenedVector(InOp);
2607 EVT InVT = InOp.getValueType();
2609 // Check if we can just return the input vector after widening.
2610 uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
2611 if (IdxVal == 0 && InVT == WidenVT)
2614 // Check if we can extract from the vector.
2615 unsigned InNumElts = InVT.getVectorNumElements();
2616 if (IdxVal % WidenNumElts == 0 && IdxVal + WidenNumElts < InNumElts)
2617 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, WidenVT, InOp, Idx);
2619 // We could try widening the input to the right length but for now, extract
2620 // the original elements, fill the rest with undefs and build a vector.
2621 SmallVector<SDValue, 16> Ops(WidenNumElts);
2622 EVT EltVT = VT.getVectorElementType();
2623 unsigned NumElts = VT.getVectorNumElements();
2625 for (i=0; i < NumElts; ++i)
2627 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, InOp,
2628 DAG.getConstant(IdxVal + i, dl,
2629 TLI.getVectorIdxTy(DAG.getDataLayout())));
2631 SDValue UndefVal = DAG.getUNDEF(EltVT);
2632 for (; i < WidenNumElts; ++i)
2634 return DAG.getNode(ISD::BUILD_VECTOR, dl, WidenVT, Ops);
2637 SDValue DAGTypeLegalizer::WidenVecRes_INSERT_VECTOR_ELT(SDNode *N) {
2638 SDValue InOp = GetWidenedVector(N->getOperand(0));
2639 return DAG.getNode(ISD::INSERT_VECTOR_ELT, SDLoc(N),
2640 InOp.getValueType(), InOp,
2641 N->getOperand(1), N->getOperand(2));
2644 SDValue DAGTypeLegalizer::WidenVecRes_LOAD(SDNode *N) {
2645 LoadSDNode *LD = cast<LoadSDNode>(N);
2646 ISD::LoadExtType ExtType = LD->getExtensionType();
2649 SmallVector<SDValue, 16> LdChain; // Chain for the series of load
2650 if (ExtType != ISD::NON_EXTLOAD)
2651 Result = GenWidenVectorExtLoads(LdChain, LD, ExtType);
2653 Result = GenWidenVectorLoads(LdChain, LD);
2655 // If we generate a single load, we can use that for the chain. Otherwise,
2656 // build a factor node to remember the multiple loads are independent and
2659 if (LdChain.size() == 1)
2660 NewChain = LdChain[0];
2662 NewChain = DAG.getNode(ISD::TokenFactor, SDLoc(LD), MVT::Other, LdChain);
2664 // Modified the chain - switch anything that used the old chain to use
2666 ReplaceValueWith(SDValue(N, 1), NewChain);
2671 SDValue DAGTypeLegalizer::WidenVecRes_MLOAD(MaskedLoadSDNode *N) {
2673 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(),N->getValueType(0));
2674 SDValue Mask = N->getMask();
2675 EVT MaskVT = Mask.getValueType();
2676 SDValue Src0 = GetWidenedVector(N->getSrc0());
2677 ISD::LoadExtType ExtType = N->getExtensionType();
2680 if (getTypeAction(MaskVT) == TargetLowering::TypeWidenVector)
2681 Mask = GetWidenedVector(Mask);
2683 EVT BoolVT = getSetCCResultType(WidenVT);
2685 // We can't use ModifyToType() because we should fill the mask with
2687 unsigned WidenNumElts = BoolVT.getVectorNumElements();
2688 unsigned MaskNumElts = MaskVT.getVectorNumElements();
2690 unsigned NumConcat = WidenNumElts / MaskNumElts;
2691 SmallVector<SDValue, 16> Ops(NumConcat);
2692 SDValue ZeroVal = DAG.getConstant(0, dl, MaskVT);
2694 for (unsigned i = 1; i != NumConcat; ++i)
2697 Mask = DAG.getNode(ISD::CONCAT_VECTORS, dl, BoolVT, Ops);
2700 SDValue Res = DAG.getMaskedLoad(WidenVT, dl, N->getChain(), N->getBasePtr(),
2701 Mask, Src0, N->getMemoryVT(),
2702 N->getMemOperand(), ExtType);
2703 // Legalized the chain result - switch anything that used the old chain to
2705 ReplaceValueWith(SDValue(N, 1), Res.getValue(1));
2709 SDValue DAGTypeLegalizer::WidenVecRes_SCALAR_TO_VECTOR(SDNode *N) {
2710 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2711 return DAG.getNode(ISD::SCALAR_TO_VECTOR, SDLoc(N),
2712 WidenVT, N->getOperand(0));
2715 SDValue DAGTypeLegalizer::WidenVecRes_SELECT(SDNode *N) {
2716 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2717 unsigned WidenNumElts = WidenVT.getVectorNumElements();
2719 SDValue Cond1 = N->getOperand(0);
2720 EVT CondVT = Cond1.getValueType();
2721 if (CondVT.isVector()) {
2722 EVT CondEltVT = CondVT.getVectorElementType();
2723 EVT CondWidenVT = EVT::getVectorVT(*DAG.getContext(),
2724 CondEltVT, WidenNumElts);
2725 if (getTypeAction(CondVT) == TargetLowering::TypeWidenVector)
2726 Cond1 = GetWidenedVector(Cond1);
2728 // If we have to split the condition there is no point in widening the
2729 // select. This would result in an cycle of widening the select ->
2730 // widening the condition operand -> splitting the condition operand ->
2731 // splitting the select -> widening the select. Instead split this select
2732 // further and widen the resulting type.
2733 if (getTypeAction(CondVT) == TargetLowering::TypeSplitVector) {
2734 SDValue SplitSelect = SplitVecOp_VSELECT(N, 0);
2735 SDValue Res = ModifyToType(SplitSelect, WidenVT);
2739 if (Cond1.getValueType() != CondWidenVT)
2740 Cond1 = ModifyToType(Cond1, CondWidenVT);
2743 SDValue InOp1 = GetWidenedVector(N->getOperand(1));
2744 SDValue InOp2 = GetWidenedVector(N->getOperand(2));
2745 assert(InOp1.getValueType() == WidenVT && InOp2.getValueType() == WidenVT);
2746 return DAG.getNode(N->getOpcode(), SDLoc(N),
2747 WidenVT, Cond1, InOp1, InOp2);
2750 SDValue DAGTypeLegalizer::WidenVecRes_SELECT_CC(SDNode *N) {
2751 SDValue InOp1 = GetWidenedVector(N->getOperand(2));
2752 SDValue InOp2 = GetWidenedVector(N->getOperand(3));
2753 return DAG.getNode(ISD::SELECT_CC, SDLoc(N),
2754 InOp1.getValueType(), N->getOperand(0),
2755 N->getOperand(1), InOp1, InOp2, N->getOperand(4));
2758 SDValue DAGTypeLegalizer::WidenVecRes_SETCC(SDNode *N) {
2759 assert(N->getValueType(0).isVector() ==
2760 N->getOperand(0).getValueType().isVector() &&
2761 "Scalar/Vector type mismatch");
2762 if (N->getValueType(0).isVector()) return WidenVecRes_VSETCC(N);
2764 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2765 SDValue InOp1 = GetWidenedVector(N->getOperand(0));
2766 SDValue InOp2 = GetWidenedVector(N->getOperand(1));
2767 return DAG.getNode(ISD::SETCC, SDLoc(N), WidenVT,
2768 InOp1, InOp2, N->getOperand(2));
2771 SDValue DAGTypeLegalizer::WidenVecRes_UNDEF(SDNode *N) {
2772 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2773 return DAG.getUNDEF(WidenVT);
2776 SDValue DAGTypeLegalizer::WidenVecRes_VECTOR_SHUFFLE(ShuffleVectorSDNode *N) {
2777 EVT VT = N->getValueType(0);
2780 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
2781 unsigned NumElts = VT.getVectorNumElements();
2782 unsigned WidenNumElts = WidenVT.getVectorNumElements();
2784 SDValue InOp1 = GetWidenedVector(N->getOperand(0));
2785 SDValue InOp2 = GetWidenedVector(N->getOperand(1));
2787 // Adjust mask based on new input vector length.
2788 SmallVector<int, 16> NewMask;
2789 for (unsigned i = 0; i != NumElts; ++i) {
2790 int Idx = N->getMaskElt(i);
2791 if (Idx < (int)NumElts)
2792 NewMask.push_back(Idx);
2794 NewMask.push_back(Idx - NumElts + WidenNumElts);
2796 for (unsigned i = NumElts; i != WidenNumElts; ++i)
2797 NewMask.push_back(-1);
2798 return DAG.getVectorShuffle(WidenVT, dl, InOp1, InOp2, &NewMask[0]);
2801 SDValue DAGTypeLegalizer::WidenVecRes_VSETCC(SDNode *N) {
2802 assert(N->getValueType(0).isVector() &&
2803 N->getOperand(0).getValueType().isVector() &&
2804 "Operands must be vectors");
2805 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2806 unsigned WidenNumElts = WidenVT.getVectorNumElements();
2808 SDValue InOp1 = N->getOperand(0);
2809 EVT InVT = InOp1.getValueType();
2810 assert(InVT.isVector() && "can not widen non-vector type");
2811 EVT WidenInVT = EVT::getVectorVT(*DAG.getContext(),
2812 InVT.getVectorElementType(), WidenNumElts);
2814 // The input and output types often differ here, and it could be that while
2815 // we'd prefer to widen the result type, the input operands have been split.
2816 // In this case, we also need to split the result of this node as well.
2817 if (getTypeAction(InVT) == TargetLowering::TypeSplitVector) {
2818 SDValue SplitVSetCC = SplitVecOp_VSETCC(N);
2819 SDValue Res = ModifyToType(SplitVSetCC, WidenVT);
2823 InOp1 = GetWidenedVector(InOp1);
2824 SDValue InOp2 = GetWidenedVector(N->getOperand(1));
2826 // Assume that the input and output will be widen appropriately. If not,
2827 // we will have to unroll it at some point.
2828 assert(InOp1.getValueType() == WidenInVT &&
2829 InOp2.getValueType() == WidenInVT &&
2830 "Input not widened to expected type!");
2832 return DAG.getNode(ISD::SETCC, SDLoc(N),
2833 WidenVT, InOp1, InOp2, N->getOperand(2));
2837 //===----------------------------------------------------------------------===//
2838 // Widen Vector Operand
2839 //===----------------------------------------------------------------------===//
2840 bool DAGTypeLegalizer::WidenVectorOperand(SDNode *N, unsigned OpNo) {
2841 DEBUG(dbgs() << "Widen node operand " << OpNo << ": ";
2844 SDValue Res = SDValue();
2846 // See if the target wants to custom widen this node.
2847 if (CustomLowerNode(N, N->getOperand(OpNo).getValueType(), false))
2850 switch (N->getOpcode()) {
2853 dbgs() << "WidenVectorOperand op #" << OpNo << ": ";
2857 llvm_unreachable("Do not know how to widen this operator's operand!");
2859 case ISD::BITCAST: Res = WidenVecOp_BITCAST(N); break;
2860 case ISD::CONCAT_VECTORS: Res = WidenVecOp_CONCAT_VECTORS(N); break;
2861 case ISD::EXTRACT_SUBVECTOR: Res = WidenVecOp_EXTRACT_SUBVECTOR(N); break;
2862 case ISD::EXTRACT_VECTOR_ELT: Res = WidenVecOp_EXTRACT_VECTOR_ELT(N); break;
2863 case ISD::STORE: Res = WidenVecOp_STORE(N); break;
2864 case ISD::MSTORE: Res = WidenVecOp_MSTORE(N, OpNo); break;
2865 case ISD::SETCC: Res = WidenVecOp_SETCC(N); break;
2866 case ISD::FCOPYSIGN: Res = WidenVecOp_FCOPYSIGN(N); break;
2868 case ISD::ANY_EXTEND:
2869 case ISD::SIGN_EXTEND:
2870 case ISD::ZERO_EXTEND:
2871 Res = WidenVecOp_EXTEND(N);
2874 case ISD::FP_EXTEND:
2875 case ISD::FP_TO_SINT:
2876 case ISD::FP_TO_UINT:
2877 case ISD::SINT_TO_FP:
2878 case ISD::UINT_TO_FP:
2880 Res = WidenVecOp_Convert(N);
2884 // If Res is null, the sub-method took care of registering the result.
2885 if (!Res.getNode()) return false;
2887 // If the result is N, the sub-method updated N in place. Tell the legalizer
2889 if (Res.getNode() == N)
2893 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 &&
2894 "Invalid operand expansion");
2896 ReplaceValueWith(SDValue(N, 0), Res);
2900 SDValue DAGTypeLegalizer::WidenVecOp_EXTEND(SDNode *N) {
2902 EVT VT = N->getValueType(0);
2904 SDValue InOp = N->getOperand(0);
2905 // If some legalization strategy other than widening is used on the operand,
2906 // we can't safely assume that just extending the low lanes is the correct
2908 if (getTypeAction(InOp.getValueType()) != TargetLowering::TypeWidenVector)
2909 return WidenVecOp_Convert(N);
2910 InOp = GetWidenedVector(InOp);
2911 assert(VT.getVectorNumElements() <
2912 InOp.getValueType().getVectorNumElements() &&
2913 "Input wasn't widened!");
2915 // We may need to further widen the operand until it has the same total
2916 // vector size as the result.
2917 EVT InVT = InOp.getValueType();
2918 if (InVT.getSizeInBits() != VT.getSizeInBits()) {
2919 EVT InEltVT = InVT.getVectorElementType();
2920 for (int i = MVT::FIRST_VECTOR_VALUETYPE, e = MVT::LAST_VECTOR_VALUETYPE; i < e; ++i) {
2921 EVT FixedVT = (MVT::SimpleValueType)i;
2922 EVT FixedEltVT = FixedVT.getVectorElementType();
2923 if (TLI.isTypeLegal(FixedVT) &&
2924 FixedVT.getSizeInBits() == VT.getSizeInBits() &&
2925 FixedEltVT == InEltVT) {
2926 assert(FixedVT.getVectorNumElements() >= VT.getVectorNumElements() &&
2927 "Not enough elements in the fixed type for the operand!");
2928 assert(FixedVT.getVectorNumElements() != InVT.getVectorNumElements() &&
2929 "We can't have the same type as we started with!");
2930 if (FixedVT.getVectorNumElements() > InVT.getVectorNumElements())
2932 ISD::INSERT_SUBVECTOR, DL, FixedVT, DAG.getUNDEF(FixedVT), InOp,
2933 DAG.getConstant(0, DL, TLI.getVectorIdxTy(DAG.getDataLayout())));
2936 ISD::EXTRACT_SUBVECTOR, DL, FixedVT, InOp,
2937 DAG.getConstant(0, DL, TLI.getVectorIdxTy(DAG.getDataLayout())));
2941 InVT = InOp.getValueType();
2942 if (InVT.getSizeInBits() != VT.getSizeInBits())
2943 // We couldn't find a legal vector type that was a widening of the input
2944 // and could be extended in-register to the result type, so we have to
2946 return WidenVecOp_Convert(N);
2949 // Use special DAG nodes to represent the operation of extending the
2951 switch (N->getOpcode()) {
2953 llvm_unreachable("Extend legalization on on extend operation!");
2954 case ISD::ANY_EXTEND:
2955 return DAG.getAnyExtendVectorInReg(InOp, DL, VT);
2956 case ISD::SIGN_EXTEND:
2957 return DAG.getSignExtendVectorInReg(InOp, DL, VT);
2958 case ISD::ZERO_EXTEND:
2959 return DAG.getZeroExtendVectorInReg(InOp, DL, VT);
2963 SDValue DAGTypeLegalizer::WidenVecOp_FCOPYSIGN(SDNode *N) {
2964 // The result (and first input) is legal, but the second input is illegal.
2965 // We can't do much to fix that, so just unroll and let the extracts off of
2966 // the second input be widened as needed later.
2967 return DAG.UnrollVectorOp(N);
2970 SDValue DAGTypeLegalizer::WidenVecOp_Convert(SDNode *N) {
2971 // Since the result is legal and the input is illegal, it is unlikely
2972 // that we can fix the input to a legal type so unroll the convert
2973 // into some scalar code and create a nasty build vector.
2974 EVT VT = N->getValueType(0);
2975 EVT EltVT = VT.getVectorElementType();
2977 unsigned NumElts = VT.getVectorNumElements();
2978 SDValue InOp = N->getOperand(0);
2979 if (getTypeAction(InOp.getValueType()) == TargetLowering::TypeWidenVector)
2980 InOp = GetWidenedVector(InOp);
2981 EVT InVT = InOp.getValueType();
2982 EVT InEltVT = InVT.getVectorElementType();
2984 unsigned Opcode = N->getOpcode();
2985 SmallVector<SDValue, 16> Ops(NumElts);
2986 for (unsigned i=0; i < NumElts; ++i)
2987 Ops[i] = DAG.getNode(
2990 ISD::EXTRACT_VECTOR_ELT, dl, InEltVT, InOp,
2991 DAG.getConstant(i, dl, TLI.getVectorIdxTy(DAG.getDataLayout()))));
2993 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
2996 SDValue DAGTypeLegalizer::WidenVecOp_BITCAST(SDNode *N) {
2997 EVT VT = N->getValueType(0);
2998 SDValue InOp = GetWidenedVector(N->getOperand(0));
2999 EVT InWidenVT = InOp.getValueType();
3002 // Check if we can convert between two legal vector types and extract.
3003 unsigned InWidenSize = InWidenVT.getSizeInBits();
3004 unsigned Size = VT.getSizeInBits();
3005 // x86mmx is not an acceptable vector element type, so don't try.
3006 if (InWidenSize % Size == 0 && !VT.isVector() && VT != MVT::x86mmx) {
3007 unsigned NewNumElts = InWidenSize / Size;
3008 EVT NewVT = EVT::getVectorVT(*DAG.getContext(), VT, NewNumElts);
3009 if (TLI.isTypeLegal(NewVT)) {
3010 SDValue BitOp = DAG.getNode(ISD::BITCAST, dl, NewVT, InOp);
3012 ISD::EXTRACT_VECTOR_ELT, dl, VT, BitOp,
3013 DAG.getConstant(0, dl, TLI.getVectorIdxTy(DAG.getDataLayout())));
3017 return CreateStackStoreLoad(InOp, VT);
3020 SDValue DAGTypeLegalizer::WidenVecOp_CONCAT_VECTORS(SDNode *N) {
3021 // If the input vector is not legal, it is likely that we will not find a
3022 // legal vector of the same size. Replace the concatenate vector with a
3023 // nasty build vector.
3024 EVT VT = N->getValueType(0);
3025 EVT EltVT = VT.getVectorElementType();
3027 unsigned NumElts = VT.getVectorNumElements();
3028 SmallVector<SDValue, 16> Ops(NumElts);
3030 EVT InVT = N->getOperand(0).getValueType();
3031 unsigned NumInElts = InVT.getVectorNumElements();
3034 unsigned NumOperands = N->getNumOperands();
3035 for (unsigned i=0; i < NumOperands; ++i) {
3036 SDValue InOp = N->getOperand(i);
3037 if (getTypeAction(InOp.getValueType()) == TargetLowering::TypeWidenVector)
3038 InOp = GetWidenedVector(InOp);
3039 for (unsigned j=0; j < NumInElts; ++j)
3040 Ops[Idx++] = DAG.getNode(
3041 ISD::EXTRACT_VECTOR_ELT, dl, EltVT, InOp,
3042 DAG.getConstant(j, dl, TLI.getVectorIdxTy(DAG.getDataLayout())));
3044 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
3047 SDValue DAGTypeLegalizer::WidenVecOp_EXTRACT_SUBVECTOR(SDNode *N) {
3048 SDValue InOp = GetWidenedVector(N->getOperand(0));
3049 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, SDLoc(N),
3050 N->getValueType(0), InOp, N->getOperand(1));
3053 SDValue DAGTypeLegalizer::WidenVecOp_EXTRACT_VECTOR_ELT(SDNode *N) {
3054 SDValue InOp = GetWidenedVector(N->getOperand(0));
3055 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SDLoc(N),
3056 N->getValueType(0), InOp, N->getOperand(1));
3059 SDValue DAGTypeLegalizer::WidenVecOp_STORE(SDNode *N) {
3060 // We have to widen the value but we want only to store the original
3062 StoreSDNode *ST = cast<StoreSDNode>(N);
3064 SmallVector<SDValue, 16> StChain;
3065 if (ST->isTruncatingStore())
3066 GenWidenVectorTruncStores(StChain, ST);
3068 GenWidenVectorStores(StChain, ST);
3070 if (StChain.size() == 1)
3073 return DAG.getNode(ISD::TokenFactor, SDLoc(ST), MVT::Other, StChain);
3076 SDValue DAGTypeLegalizer::WidenVecOp_MSTORE(SDNode *N, unsigned OpNo) {
3077 MaskedStoreSDNode *MST = cast<MaskedStoreSDNode>(N);
3078 SDValue Mask = MST->getMask();
3079 EVT MaskVT = Mask.getValueType();
3080 SDValue StVal = MST->getValue();
3082 SDValue WideVal = GetWidenedVector(StVal);
3085 if (OpNo == 2 || getTypeAction(MaskVT) == TargetLowering::TypeWidenVector)
3086 Mask = GetWidenedVector(Mask);
3088 // The mask should be widened as well
3089 EVT BoolVT = getSetCCResultType(WideVal.getValueType());
3090 // We can't use ModifyToType() because we should fill the mask with
3092 unsigned WidenNumElts = BoolVT.getVectorNumElements();
3093 unsigned MaskNumElts = MaskVT.getVectorNumElements();
3095 unsigned NumConcat = WidenNumElts / MaskNumElts;
3096 SmallVector<SDValue, 16> Ops(NumConcat);
3097 SDValue ZeroVal = DAG.getConstant(0, dl, MaskVT);
3099 for (unsigned i = 1; i != NumConcat; ++i)
3102 Mask = DAG.getNode(ISD::CONCAT_VECTORS, dl, BoolVT, Ops);
3104 assert(Mask.getValueType().getVectorNumElements() ==
3105 WideVal.getValueType().getVectorNumElements() &&
3106 "Mask and data vectors should have the same number of elements");
3107 return DAG.getMaskedStore(MST->getChain(), dl, WideVal, MST->getBasePtr(),
3108 Mask, MST->getMemoryVT(), MST->getMemOperand(),
3112 SDValue DAGTypeLegalizer::WidenVecOp_SETCC(SDNode *N) {
3113 SDValue InOp0 = GetWidenedVector(N->getOperand(0));
3114 SDValue InOp1 = GetWidenedVector(N->getOperand(1));
3117 // WARNING: In this code we widen the compare instruction with garbage.
3118 // This garbage may contain denormal floats which may be slow. Is this a real
3119 // concern ? Should we zero the unused lanes if this is a float compare ?
3121 // Get a new SETCC node to compare the newly widened operands.
3122 // Only some of the compared elements are legal.
3123 EVT SVT = TLI.getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(),
3124 InOp0.getValueType());
3125 SDValue WideSETCC = DAG.getNode(ISD::SETCC, SDLoc(N),
3126 SVT, InOp0, InOp1, N->getOperand(2));
3128 // Extract the needed results from the result vector.
3129 EVT ResVT = EVT::getVectorVT(*DAG.getContext(),
3130 SVT.getVectorElementType(),
3131 N->getValueType(0).getVectorNumElements());
3132 SDValue CC = DAG.getNode(
3133 ISD::EXTRACT_SUBVECTOR, dl, ResVT, WideSETCC,
3134 DAG.getConstant(0, dl, TLI.getVectorIdxTy(DAG.getDataLayout())));
3136 return PromoteTargetBoolean(CC, N->getValueType(0));
3140 //===----------------------------------------------------------------------===//
3141 // Vector Widening Utilities
3142 //===----------------------------------------------------------------------===//
3144 // Utility function to find the type to chop up a widen vector for load/store
3145 // TLI: Target lowering used to determine legal types.
3146 // Width: Width left need to load/store.
3147 // WidenVT: The widen vector type to load to/store from
3148 // Align: If 0, don't allow use of a wider type
3149 // WidenEx: If Align is not 0, the amount additional we can load/store from.
3151 static EVT FindMemType(SelectionDAG& DAG, const TargetLowering &TLI,
3152 unsigned Width, EVT WidenVT,
3153 unsigned Align = 0, unsigned WidenEx = 0) {
3154 EVT WidenEltVT = WidenVT.getVectorElementType();
3155 unsigned WidenWidth = WidenVT.getSizeInBits();
3156 unsigned WidenEltWidth = WidenEltVT.getSizeInBits();
3157 unsigned AlignInBits = Align*8;
3159 // If we have one element to load/store, return it.
3160 EVT RetVT = WidenEltVT;
3161 if (Width == WidenEltWidth)
3164 // See if there is larger legal integer than the element type to load/store
3166 for (VT = (unsigned)MVT::LAST_INTEGER_VALUETYPE;
3167 VT >= (unsigned)MVT::FIRST_INTEGER_VALUETYPE; --VT) {
3168 EVT MemVT((MVT::SimpleValueType) VT);
3169 unsigned MemVTWidth = MemVT.getSizeInBits();
3170 if (MemVT.getSizeInBits() <= WidenEltWidth)
3172 auto Action = TLI.getTypeAction(*DAG.getContext(), MemVT);
3173 if ((Action == TargetLowering::TypeLegal ||
3174 Action == TargetLowering::TypePromoteInteger) &&
3175 (WidenWidth % MemVTWidth) == 0 &&
3176 isPowerOf2_32(WidenWidth / MemVTWidth) &&
3177 (MemVTWidth <= Width ||
3178 (Align!=0 && MemVTWidth<=AlignInBits && MemVTWidth<=Width+WidenEx))) {
3184 // See if there is a larger vector type to load/store that has the same vector
3185 // element type and is evenly divisible with the WidenVT.
3186 for (VT = (unsigned)MVT::LAST_VECTOR_VALUETYPE;
3187 VT >= (unsigned)MVT::FIRST_VECTOR_VALUETYPE; --VT) {
3188 EVT MemVT = (MVT::SimpleValueType) VT;
3189 unsigned MemVTWidth = MemVT.getSizeInBits();
3190 if (TLI.isTypeLegal(MemVT) && WidenEltVT == MemVT.getVectorElementType() &&
3191 (WidenWidth % MemVTWidth) == 0 &&
3192 isPowerOf2_32(WidenWidth / MemVTWidth) &&
3193 (MemVTWidth <= Width ||
3194 (Align!=0 && MemVTWidth<=AlignInBits && MemVTWidth<=Width+WidenEx))) {
3195 if (RetVT.getSizeInBits() < MemVTWidth || MemVT == WidenVT)
3203 // Builds a vector type from scalar loads
3204 // VecTy: Resulting Vector type
3205 // LDOps: Load operators to build a vector type
3206 // [Start,End) the list of loads to use.
3207 static SDValue BuildVectorFromScalar(SelectionDAG& DAG, EVT VecTy,
3208 SmallVectorImpl<SDValue> &LdOps,
3209 unsigned Start, unsigned End) {
3210 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3211 SDLoc dl(LdOps[Start]);
3212 EVT LdTy = LdOps[Start].getValueType();
3213 unsigned Width = VecTy.getSizeInBits();
3214 unsigned NumElts = Width / LdTy.getSizeInBits();
3215 EVT NewVecVT = EVT::getVectorVT(*DAG.getContext(), LdTy, NumElts);
3218 SDValue VecOp = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, NewVecVT,LdOps[Start]);
3220 for (unsigned i = Start + 1; i != End; ++i) {
3221 EVT NewLdTy = LdOps[i].getValueType();
3222 if (NewLdTy != LdTy) {
3223 NumElts = Width / NewLdTy.getSizeInBits();
3224 NewVecVT = EVT::getVectorVT(*DAG.getContext(), NewLdTy, NumElts);
3225 VecOp = DAG.getNode(ISD::BITCAST, dl, NewVecVT, VecOp);
3226 // Readjust position and vector position based on new load type
3227 Idx = Idx * LdTy.getSizeInBits() / NewLdTy.getSizeInBits();
3230 VecOp = DAG.getNode(
3231 ISD::INSERT_VECTOR_ELT, dl, NewVecVT, VecOp, LdOps[i],
3232 DAG.getConstant(Idx++, dl, TLI.getVectorIdxTy(DAG.getDataLayout())));
3234 return DAG.getNode(ISD::BITCAST, dl, VecTy, VecOp);
3237 SDValue DAGTypeLegalizer::GenWidenVectorLoads(SmallVectorImpl<SDValue> &LdChain,
3239 // The strategy assumes that we can efficiently load powers of two widths.
3240 // The routines chops the vector into the largest vector loads with the same
3241 // element type or scalar loads and then recombines it to the widen vector
3243 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(),LD->getValueType(0));
3244 unsigned WidenWidth = WidenVT.getSizeInBits();
3245 EVT LdVT = LD->getMemoryVT();
3247 assert(LdVT.isVector() && WidenVT.isVector());
3248 assert(LdVT.getVectorElementType() == WidenVT.getVectorElementType());
3251 SDValue Chain = LD->getChain();
3252 SDValue BasePtr = LD->getBasePtr();
3253 unsigned Align = LD->getAlignment();
3254 bool isVolatile = LD->isVolatile();
3255 bool isNonTemporal = LD->isNonTemporal();
3256 bool isInvariant = LD->isInvariant();
3257 AAMDNodes AAInfo = LD->getAAInfo();
3259 int LdWidth = LdVT.getSizeInBits();
3260 int WidthDiff = WidenWidth - LdWidth; // Difference
3261 unsigned LdAlign = (isVolatile) ? 0 : Align; // Allow wider loads
3263 // Find the vector type that can load from.
3264 EVT NewVT = FindMemType(DAG, TLI, LdWidth, WidenVT, LdAlign, WidthDiff);
3265 int NewVTWidth = NewVT.getSizeInBits();
3266 SDValue LdOp = DAG.getLoad(NewVT, dl, Chain, BasePtr, LD->getPointerInfo(),
3267 isVolatile, isNonTemporal, isInvariant, Align,
3269 LdChain.push_back(LdOp.getValue(1));
3271 // Check if we can load the element with one instruction
3272 if (LdWidth <= NewVTWidth) {
3273 if (!NewVT.isVector()) {
3274 unsigned NumElts = WidenWidth / NewVTWidth;
3275 EVT NewVecVT = EVT::getVectorVT(*DAG.getContext(), NewVT, NumElts);
3276 SDValue VecOp = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, NewVecVT, LdOp);
3277 return DAG.getNode(ISD::BITCAST, dl, WidenVT, VecOp);
3279 if (NewVT == WidenVT)
3282 assert(WidenWidth % NewVTWidth == 0);
3283 unsigned NumConcat = WidenWidth / NewVTWidth;
3284 SmallVector<SDValue, 16> ConcatOps(NumConcat);
3285 SDValue UndefVal = DAG.getUNDEF(NewVT);
3286 ConcatOps[0] = LdOp;
3287 for (unsigned i = 1; i != NumConcat; ++i)
3288 ConcatOps[i] = UndefVal;
3289 return DAG.getNode(ISD::CONCAT_VECTORS, dl, WidenVT, ConcatOps);
3292 // Load vector by using multiple loads from largest vector to scalar
3293 SmallVector<SDValue, 16> LdOps;
3294 LdOps.push_back(LdOp);
3296 LdWidth -= NewVTWidth;
3297 unsigned Offset = 0;
3299 while (LdWidth > 0) {
3300 unsigned Increment = NewVTWidth / 8;
3301 Offset += Increment;
3302 BasePtr = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(), BasePtr,
3303 DAG.getConstant(Increment, dl, BasePtr.getValueType()));
3306 if (LdWidth < NewVTWidth) {
3307 // Our current type we are using is too large, find a better size
3308 NewVT = FindMemType(DAG, TLI, LdWidth, WidenVT, LdAlign, WidthDiff);
3309 NewVTWidth = NewVT.getSizeInBits();
3310 L = DAG.getLoad(NewVT, dl, Chain, BasePtr,
3311 LD->getPointerInfo().getWithOffset(Offset), isVolatile,
3312 isNonTemporal, isInvariant, MinAlign(Align, Increment),
3314 LdChain.push_back(L.getValue(1));
3315 if (L->getValueType(0).isVector()) {
3316 SmallVector<SDValue, 16> Loads;
3318 unsigned size = L->getValueSizeInBits(0);
3319 while (size < LdOp->getValueSizeInBits(0)) {
3320 Loads.push_back(DAG.getUNDEF(L->getValueType(0)));
3321 size += L->getValueSizeInBits(0);
3323 L = DAG.getNode(ISD::CONCAT_VECTORS, dl, LdOp->getValueType(0), Loads);
3326 L = DAG.getLoad(NewVT, dl, Chain, BasePtr,
3327 LD->getPointerInfo().getWithOffset(Offset), isVolatile,
3328 isNonTemporal, isInvariant, MinAlign(Align, Increment),
3330 LdChain.push_back(L.getValue(1));
3336 LdWidth -= NewVTWidth;
3339 // Build the vector from the loads operations
3340 unsigned End = LdOps.size();
3341 if (!LdOps[0].getValueType().isVector())
3342 // All the loads are scalar loads.
3343 return BuildVectorFromScalar(DAG, WidenVT, LdOps, 0, End);
3345 // If the load contains vectors, build the vector using concat vector.
3346 // All of the vectors used to loads are power of 2 and the scalars load
3347 // can be combined to make a power of 2 vector.
3348 SmallVector<SDValue, 16> ConcatOps(End);
3351 EVT LdTy = LdOps[i].getValueType();
3352 // First combine the scalar loads to a vector
3353 if (!LdTy.isVector()) {
3354 for (--i; i >= 0; --i) {
3355 LdTy = LdOps[i].getValueType();
3356 if (LdTy.isVector())
3359 ConcatOps[--Idx] = BuildVectorFromScalar(DAG, LdTy, LdOps, i+1, End);
3361 ConcatOps[--Idx] = LdOps[i];
3362 for (--i; i >= 0; --i) {
3363 EVT NewLdTy = LdOps[i].getValueType();
3364 if (NewLdTy != LdTy) {
3365 // Create a larger vector
3366 ConcatOps[End-1] = DAG.getNode(ISD::CONCAT_VECTORS, dl, NewLdTy,
3367 makeArrayRef(&ConcatOps[Idx], End - Idx));
3371 ConcatOps[--Idx] = LdOps[i];
3374 if (WidenWidth == LdTy.getSizeInBits()*(End - Idx))
3375 return DAG.getNode(ISD::CONCAT_VECTORS, dl, WidenVT,
3376 makeArrayRef(&ConcatOps[Idx], End - Idx));
3378 // We need to fill the rest with undefs to build the vector
3379 unsigned NumOps = WidenWidth / LdTy.getSizeInBits();
3380 SmallVector<SDValue, 16> WidenOps(NumOps);
3381 SDValue UndefVal = DAG.getUNDEF(LdTy);
3384 for (; i != End-Idx; ++i)
3385 WidenOps[i] = ConcatOps[Idx+i];
3386 for (; i != NumOps; ++i)
3387 WidenOps[i] = UndefVal;
3389 return DAG.getNode(ISD::CONCAT_VECTORS, dl, WidenVT, WidenOps);
3393 DAGTypeLegalizer::GenWidenVectorExtLoads(SmallVectorImpl<SDValue> &LdChain,
3395 ISD::LoadExtType ExtType) {
3396 // For extension loads, it may not be more efficient to chop up the vector
3397 // and then extended it. Instead, we unroll the load and build a new vector.
3398 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(),LD->getValueType(0));
3399 EVT LdVT = LD->getMemoryVT();
3401 assert(LdVT.isVector() && WidenVT.isVector());
3404 SDValue Chain = LD->getChain();
3405 SDValue BasePtr = LD->getBasePtr();
3406 unsigned Align = LD->getAlignment();
3407 bool isVolatile = LD->isVolatile();
3408 bool isNonTemporal = LD->isNonTemporal();
3409 bool isInvariant = LD->isInvariant();
3410 AAMDNodes AAInfo = LD->getAAInfo();
3412 EVT EltVT = WidenVT.getVectorElementType();
3413 EVT LdEltVT = LdVT.getVectorElementType();
3414 unsigned NumElts = LdVT.getVectorNumElements();
3416 // Load each element and widen
3417 unsigned WidenNumElts = WidenVT.getVectorNumElements();
3418 SmallVector<SDValue, 16> Ops(WidenNumElts);
3419 unsigned Increment = LdEltVT.getSizeInBits() / 8;
3420 Ops[0] = DAG.getExtLoad(ExtType, dl, EltVT, Chain, BasePtr,
3421 LD->getPointerInfo(),
3422 LdEltVT, isVolatile, isNonTemporal, isInvariant,
3424 LdChain.push_back(Ops[0].getValue(1));
3425 unsigned i = 0, Offset = Increment;
3426 for (i=1; i < NumElts; ++i, Offset += Increment) {
3427 SDValue NewBasePtr = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(),
3429 DAG.getConstant(Offset, dl,
3430 BasePtr.getValueType()));
3431 Ops[i] = DAG.getExtLoad(ExtType, dl, EltVT, Chain, NewBasePtr,
3432 LD->getPointerInfo().getWithOffset(Offset), LdEltVT,
3433 isVolatile, isNonTemporal, isInvariant, Align,
3435 LdChain.push_back(Ops[i].getValue(1));
3438 // Fill the rest with undefs
3439 SDValue UndefVal = DAG.getUNDEF(EltVT);
3440 for (; i != WidenNumElts; ++i)
3443 return DAG.getNode(ISD::BUILD_VECTOR, dl, WidenVT, Ops);
3447 void DAGTypeLegalizer::GenWidenVectorStores(SmallVectorImpl<SDValue> &StChain,
3449 // The strategy assumes that we can efficiently store powers of two widths.
3450 // The routines chops the vector into the largest vector stores with the same
3451 // element type or scalar stores.
3452 SDValue Chain = ST->getChain();
3453 SDValue BasePtr = ST->getBasePtr();
3454 unsigned Align = ST->getAlignment();
3455 bool isVolatile = ST->isVolatile();
3456 bool isNonTemporal = ST->isNonTemporal();
3457 AAMDNodes AAInfo = ST->getAAInfo();
3458 SDValue ValOp = GetWidenedVector(ST->getValue());
3461 EVT StVT = ST->getMemoryVT();
3462 unsigned StWidth = StVT.getSizeInBits();
3463 EVT ValVT = ValOp.getValueType();
3464 unsigned ValWidth = ValVT.getSizeInBits();
3465 EVT ValEltVT = ValVT.getVectorElementType();
3466 unsigned ValEltWidth = ValEltVT.getSizeInBits();
3467 assert(StVT.getVectorElementType() == ValEltVT);
3469 int Idx = 0; // current index to store
3470 unsigned Offset = 0; // offset from base to store
3471 while (StWidth != 0) {
3472 // Find the largest vector type we can store with
3473 EVT NewVT = FindMemType(DAG, TLI, StWidth, ValVT);
3474 unsigned NewVTWidth = NewVT.getSizeInBits();
3475 unsigned Increment = NewVTWidth / 8;
3476 if (NewVT.isVector()) {
3477 unsigned NumVTElts = NewVT.getVectorNumElements();
3479 SDValue EOp = DAG.getNode(
3480 ISD::EXTRACT_SUBVECTOR, dl, NewVT, ValOp,
3481 DAG.getConstant(Idx, dl, TLI.getVectorIdxTy(DAG.getDataLayout())));
3482 StChain.push_back(DAG.getStore(Chain, dl, EOp, BasePtr,
3483 ST->getPointerInfo().getWithOffset(Offset),
3484 isVolatile, isNonTemporal,
3485 MinAlign(Align, Offset), AAInfo));
3486 StWidth -= NewVTWidth;
3487 Offset += Increment;
3489 BasePtr = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(), BasePtr,
3490 DAG.getConstant(Increment, dl,
3491 BasePtr.getValueType()));
3492 } while (StWidth != 0 && StWidth >= NewVTWidth);
3494 // Cast the vector to the scalar type we can store
3495 unsigned NumElts = ValWidth / NewVTWidth;
3496 EVT NewVecVT = EVT::getVectorVT(*DAG.getContext(), NewVT, NumElts);
3497 SDValue VecOp = DAG.getNode(ISD::BITCAST, dl, NewVecVT, ValOp);
3498 // Readjust index position based on new vector type
3499 Idx = Idx * ValEltWidth / NewVTWidth;
3501 SDValue EOp = DAG.getNode(
3502 ISD::EXTRACT_VECTOR_ELT, dl, NewVT, VecOp,
3503 DAG.getConstant(Idx++, dl,
3504 TLI.getVectorIdxTy(DAG.getDataLayout())));
3505 StChain.push_back(DAG.getStore(Chain, dl, EOp, BasePtr,
3506 ST->getPointerInfo().getWithOffset(Offset),
3507 isVolatile, isNonTemporal,
3508 MinAlign(Align, Offset), AAInfo));
3509 StWidth -= NewVTWidth;
3510 Offset += Increment;
3511 BasePtr = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(), BasePtr,
3512 DAG.getConstant(Increment, dl,
3513 BasePtr.getValueType()));
3514 } while (StWidth != 0 && StWidth >= NewVTWidth);
3515 // Restore index back to be relative to the original widen element type
3516 Idx = Idx * NewVTWidth / ValEltWidth;
3522 DAGTypeLegalizer::GenWidenVectorTruncStores(SmallVectorImpl<SDValue> &StChain,
3524 // For extension loads, it may not be more efficient to truncate the vector
3525 // and then store it. Instead, we extract each element and then store it.
3526 SDValue Chain = ST->getChain();
3527 SDValue BasePtr = ST->getBasePtr();
3528 unsigned Align = ST->getAlignment();
3529 bool isVolatile = ST->isVolatile();
3530 bool isNonTemporal = ST->isNonTemporal();
3531 AAMDNodes AAInfo = ST->getAAInfo();
3532 SDValue ValOp = GetWidenedVector(ST->getValue());
3535 EVT StVT = ST->getMemoryVT();
3536 EVT ValVT = ValOp.getValueType();
3538 // It must be true that we the widen vector type is bigger than where
3539 // we need to store.
3540 assert(StVT.isVector() && ValOp.getValueType().isVector());
3541 assert(StVT.bitsLT(ValOp.getValueType()));
3543 // For truncating stores, we can not play the tricks of chopping legal
3544 // vector types and bit cast it to the right type. Instead, we unroll
3546 EVT StEltVT = StVT.getVectorElementType();
3547 EVT ValEltVT = ValVT.getVectorElementType();
3548 unsigned Increment = ValEltVT.getSizeInBits() / 8;
3549 unsigned NumElts = StVT.getVectorNumElements();
3550 SDValue EOp = DAG.getNode(
3551 ISD::EXTRACT_VECTOR_ELT, dl, ValEltVT, ValOp,
3552 DAG.getConstant(0, dl, TLI.getVectorIdxTy(DAG.getDataLayout())));
3553 StChain.push_back(DAG.getTruncStore(Chain, dl, EOp, BasePtr,
3554 ST->getPointerInfo(), StEltVT,
3555 isVolatile, isNonTemporal, Align,
3557 unsigned Offset = Increment;
3558 for (unsigned i=1; i < NumElts; ++i, Offset += Increment) {
3559 SDValue NewBasePtr = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(),
3561 DAG.getConstant(Offset, dl,
3562 BasePtr.getValueType()));
3563 SDValue EOp = DAG.getNode(
3564 ISD::EXTRACT_VECTOR_ELT, dl, ValEltVT, ValOp,
3565 DAG.getConstant(0, dl, TLI.getVectorIdxTy(DAG.getDataLayout())));
3566 StChain.push_back(DAG.getTruncStore(Chain, dl, EOp, NewBasePtr,
3567 ST->getPointerInfo().getWithOffset(Offset),
3568 StEltVT, isVolatile, isNonTemporal,
3569 MinAlign(Align, Offset), AAInfo));
3573 /// Modifies a vector input (widen or narrows) to a vector of NVT. The
3574 /// input vector must have the same element type as NVT.
3575 SDValue DAGTypeLegalizer::ModifyToType(SDValue InOp, EVT NVT) {
3576 // Note that InOp might have been widened so it might already have
3577 // the right width or it might need be narrowed.
3578 EVT InVT = InOp.getValueType();
3579 assert(InVT.getVectorElementType() == NVT.getVectorElementType() &&
3580 "input and widen element type must match");
3583 // Check if InOp already has the right width.
3587 unsigned InNumElts = InVT.getVectorNumElements();
3588 unsigned WidenNumElts = NVT.getVectorNumElements();
3589 if (WidenNumElts > InNumElts && WidenNumElts % InNumElts == 0) {
3590 unsigned NumConcat = WidenNumElts / InNumElts;
3591 SmallVector<SDValue, 16> Ops(NumConcat);
3592 SDValue UndefVal = DAG.getUNDEF(InVT);
3594 for (unsigned i = 1; i != NumConcat; ++i)
3597 return DAG.getNode(ISD::CONCAT_VECTORS, dl, NVT, Ops);
3600 if (WidenNumElts < InNumElts && InNumElts % WidenNumElts)
3602 ISD::EXTRACT_SUBVECTOR, dl, NVT, InOp,
3603 DAG.getConstant(0, dl, TLI.getVectorIdxTy(DAG.getDataLayout())));
3605 // Fall back to extract and build.
3606 SmallVector<SDValue, 16> Ops(WidenNumElts);
3607 EVT EltVT = NVT.getVectorElementType();
3608 unsigned MinNumElts = std::min(WidenNumElts, InNumElts);
3610 for (Idx = 0; Idx < MinNumElts; ++Idx)
3611 Ops[Idx] = DAG.getNode(
3612 ISD::EXTRACT_VECTOR_ELT, dl, EltVT, InOp,
3613 DAG.getConstant(Idx, dl, TLI.getVectorIdxTy(DAG.getDataLayout())));
3615 SDValue UndefVal = DAG.getUNDEF(EltVT);
3616 for ( ; Idx < WidenNumElts; ++Idx)
3617 Ops[Idx] = UndefVal;
3618 return DAG.getNode(ISD::BUILD_VECTOR, dl, NVT, Ops);