1 //===-- LegalizeVectorOps.cpp - Implement SelectionDAG::LegalizeVectors ---===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the SelectionDAG::LegalizeVectors method.
12 // The vector legalizer looks for vector operations which might need to be
13 // scalarized and legalizes them. This is a separate step from Legalize because
14 // scalarizing can introduce illegal types. For example, suppose we have an
15 // ISD::SDIV of type v2i64 on x86-32. The type is legal (for example, addition
16 // on a v2i64 is legal), but ISD::SDIV isn't legal, so we have to unroll the
17 // operation, which introduces nodes with the illegal type i64 which must be
18 // expanded. Similarly, suppose we have an ISD::SRA of type v16i8 on PowerPC;
19 // the operation must be unrolled, which introduces nodes with the illegal
20 // type i8 which must be promoted.
22 // This does not legalize vector manipulations like ISD::BUILD_VECTOR,
23 // or operations that happen to take a vector which are custom-lowered;
24 // the legalization for such operations never produces nodes
25 // with illegal types, so it's okay to put off legalizing them until
26 // SelectionDAG::Legalize runs.
28 //===----------------------------------------------------------------------===//
30 #include "llvm/CodeGen/SelectionDAG.h"
31 #include "llvm/Target/TargetLowering.h"
35 class VectorLegalizer {
37 const TargetLowering &TLI;
38 bool Changed; // Keep track of whether anything changed
40 /// LegalizedNodes - For nodes that are of legal width, and that have more
41 /// than one use, this map indicates what regularized operand to use. This
42 /// allows us to avoid legalizing the same thing more than once.
43 SmallDenseMap<SDValue, SDValue, 64> LegalizedNodes;
45 // Adds a node to the translation cache
46 void AddLegalizedOperand(SDValue From, SDValue To) {
47 LegalizedNodes.insert(std::make_pair(From, To));
48 // If someone requests legalization of the new node, return itself.
50 LegalizedNodes.insert(std::make_pair(To, To));
53 // Legalizes the given node
54 SDValue LegalizeOp(SDValue Op);
55 // Assuming the node is legal, "legalize" the results
56 SDValue TranslateLegalizeResults(SDValue Op, SDValue Result);
57 // Implements unrolling a VSETCC.
58 SDValue UnrollVSETCC(SDValue Op);
59 // Implements expansion for FNEG; falls back to UnrollVectorOp if FSUB
61 // Implements expansion for UINT_TO_FLOAT; falls back to UnrollVectorOp if
62 // SINT_TO_FLOAT and SHR on vectors isn't legal.
63 SDValue ExpandUINT_TO_FLOAT(SDValue Op);
64 // Implement expansion for SIGN_EXTEND_INREG using SRL and SRA.
65 SDValue ExpandSEXTINREG(SDValue Op);
66 // Implement vselect in terms of XOR, AND, OR when blend is not supported
68 SDValue ExpandVSELECT(SDValue Op);
69 SDValue ExpandSELECT(SDValue Op);
70 SDValue ExpandLoad(SDValue Op);
71 SDValue ExpandStore(SDValue Op);
72 SDValue ExpandFNEG(SDValue Op);
73 // Implements vector promotion; this is essentially just bitcasting the
74 // operands to a different type and bitcasting the result back to the
76 SDValue PromoteVectorOp(SDValue Op);
77 // Implements [SU]INT_TO_FP vector promotion; this is a [zs]ext of the input
78 // operand to the next size up.
79 SDValue PromoteVectorOpINT_TO_FP(SDValue Op);
83 VectorLegalizer(SelectionDAG& dag) :
84 DAG(dag), TLI(dag.getTargetLoweringInfo()), Changed(false) {}
87 bool VectorLegalizer::Run() {
88 // The legalize process is inherently a bottom-up recursive process (users
89 // legalize their uses before themselves). Given infinite stack space, we
90 // could just start legalizing on the root and traverse the whole graph. In
91 // practice however, this causes us to run out of stack space on large basic
92 // blocks. To avoid this problem, compute an ordering of the nodes where each
93 // node is only legalized after all of its operands are legalized.
94 DAG.AssignTopologicalOrder();
95 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(),
96 E = prior(DAG.allnodes_end()); I != llvm::next(E); ++I)
97 LegalizeOp(SDValue(I, 0));
99 // Finally, it's possible the root changed. Get the new root.
100 SDValue OldRoot = DAG.getRoot();
101 assert(LegalizedNodes.count(OldRoot) && "Root didn't get legalized?");
102 DAG.setRoot(LegalizedNodes[OldRoot]);
104 LegalizedNodes.clear();
106 // Remove dead nodes now.
107 DAG.RemoveDeadNodes();
112 SDValue VectorLegalizer::TranslateLegalizeResults(SDValue Op, SDValue Result) {
113 // Generic legalization: just pass the operand through.
114 for (unsigned i = 0, e = Op.getNode()->getNumValues(); i != e; ++i)
115 AddLegalizedOperand(Op.getValue(i), Result.getValue(i));
116 return Result.getValue(Op.getResNo());
119 SDValue VectorLegalizer::LegalizeOp(SDValue Op) {
120 // Note that LegalizeOp may be reentered even from single-use nodes, which
121 // means that we always must cache transformed nodes.
122 DenseMap<SDValue, SDValue>::iterator I = LegalizedNodes.find(Op);
123 if (I != LegalizedNodes.end()) return I->second;
125 SDNode* Node = Op.getNode();
127 // Legalize the operands
128 SmallVector<SDValue, 8> Ops;
129 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
130 Ops.push_back(LegalizeOp(Node->getOperand(i)));
133 SDValue(DAG.UpdateNodeOperands(Op.getNode(), Ops.data(), Ops.size()), 0);
135 if (Op.getOpcode() == ISD::LOAD) {
136 LoadSDNode *LD = cast<LoadSDNode>(Op.getNode());
137 ISD::LoadExtType ExtType = LD->getExtensionType();
138 if (LD->getMemoryVT().isVector() && ExtType != ISD::NON_EXTLOAD) {
139 if (TLI.isLoadExtLegal(LD->getExtensionType(), LD->getMemoryVT()))
140 return TranslateLegalizeResults(Op, Result);
142 return LegalizeOp(ExpandLoad(Op));
144 } else if (Op.getOpcode() == ISD::STORE) {
145 StoreSDNode *ST = cast<StoreSDNode>(Op.getNode());
146 EVT StVT = ST->getMemoryVT();
147 MVT ValVT = ST->getValue().getSimpleValueType();
148 if (StVT.isVector() && ST->isTruncatingStore())
149 switch (TLI.getTruncStoreAction(ValVT, StVT.getSimpleVT())) {
150 default: llvm_unreachable("This action is not supported yet!");
151 case TargetLowering::Legal:
152 return TranslateLegalizeResults(Op, Result);
153 case TargetLowering::Custom:
155 return LegalizeOp(TLI.LowerOperation(Result, DAG));
156 case TargetLowering::Expand:
158 return LegalizeOp(ExpandStore(Op));
162 bool HasVectorValue = false;
163 for (SDNode::value_iterator J = Node->value_begin(), E = Node->value_end();
166 HasVectorValue |= J->isVector();
168 return TranslateLegalizeResults(Op, Result);
171 switch (Op.getOpcode()) {
173 return TranslateLegalizeResults(Op, Result);
196 case ISD::CTLZ_ZERO_UNDEF:
197 case ISD::CTTZ_ZERO_UNDEF:
203 case ISD::ZERO_EXTEND:
204 case ISD::ANY_EXTEND:
206 case ISD::SIGN_EXTEND:
207 case ISD::FP_TO_SINT:
208 case ISD::FP_TO_UINT:
224 case ISD::FNEARBYINT:
229 case ISD::SIGN_EXTEND_INREG:
230 QueryType = Node->getValueType(0);
232 case ISD::FP_ROUND_INREG:
233 QueryType = cast<VTSDNode>(Node->getOperand(1))->getVT();
235 case ISD::SINT_TO_FP:
236 case ISD::UINT_TO_FP:
237 QueryType = Node->getOperand(0).getValueType();
241 switch (TLI.getOperationAction(Node->getOpcode(), QueryType)) {
242 case TargetLowering::Promote:
243 switch (Op.getOpcode()) {
245 // "Promote" the operation by bitcasting
246 Result = PromoteVectorOp(Op);
249 case ISD::SINT_TO_FP:
250 case ISD::UINT_TO_FP:
251 // "Promote" the operation by extending the operand.
252 Result = PromoteVectorOpINT_TO_FP(Op);
257 case TargetLowering::Legal: break;
258 case TargetLowering::Custom: {
259 SDValue Tmp1 = TLI.LowerOperation(Op, DAG);
260 if (Tmp1.getNode()) {
266 case TargetLowering::Expand:
267 if (Node->getOpcode() == ISD::SIGN_EXTEND_INREG)
268 Result = ExpandSEXTINREG(Op);
269 else if (Node->getOpcode() == ISD::VSELECT)
270 Result = ExpandVSELECT(Op);
271 else if (Node->getOpcode() == ISD::SELECT)
272 Result = ExpandSELECT(Op);
273 else if (Node->getOpcode() == ISD::UINT_TO_FP)
274 Result = ExpandUINT_TO_FLOAT(Op);
275 else if (Node->getOpcode() == ISD::FNEG)
276 Result = ExpandFNEG(Op);
277 else if (Node->getOpcode() == ISD::SETCC)
278 Result = UnrollVSETCC(Op);
280 Result = DAG.UnrollVectorOp(Op.getNode());
284 // Make sure that the generated code is itself legal.
286 Result = LegalizeOp(Result);
290 // Note that LegalizeOp may be reentered even from single-use nodes, which
291 // means that we always must cache transformed nodes.
292 AddLegalizedOperand(Op, Result);
296 SDValue VectorLegalizer::PromoteVectorOp(SDValue Op) {
297 // Vector "promotion" is basically just bitcasting and doing the operation
298 // in a different type. For example, x86 promotes ISD::AND on v2i32 to
300 MVT VT = Op.getSimpleValueType();
301 assert(Op.getNode()->getNumValues() == 1 &&
302 "Can't promote a vector with multiple results!");
303 MVT NVT = TLI.getTypeToPromoteTo(Op.getOpcode(), VT);
304 DebugLoc dl = Op.getDebugLoc();
305 SmallVector<SDValue, 4> Operands(Op.getNumOperands());
307 for (unsigned j = 0; j != Op.getNumOperands(); ++j) {
308 if (Op.getOperand(j).getValueType().isVector())
309 Operands[j] = DAG.getNode(ISD::BITCAST, dl, NVT, Op.getOperand(j));
311 Operands[j] = Op.getOperand(j);
314 Op = DAG.getNode(Op.getOpcode(), dl, NVT, &Operands[0], Operands.size());
316 return DAG.getNode(ISD::BITCAST, dl, VT, Op);
319 SDValue VectorLegalizer::PromoteVectorOpINT_TO_FP(SDValue Op) {
320 // INT_TO_FP operations may require the input operand be promoted even
321 // when the type is otherwise legal.
322 EVT VT = Op.getOperand(0).getValueType();
323 assert(Op.getNode()->getNumValues() == 1 &&
324 "Can't promote a vector with multiple results!");
326 // Normal getTypeToPromoteTo() doesn't work here, as that will promote
327 // by widening the vector w/ the same element width and twice the number
328 // of elements. We want the other way around, the same number of elements,
329 // each twice the width.
331 // Increase the bitwidth of the element to the next pow-of-two
332 // (which is greater than 8 bits).
333 unsigned NumElts = VT.getVectorNumElements();
334 EVT EltVT = VT.getVectorElementType();
335 EltVT = EVT::getIntegerVT(*DAG.getContext(), 2 * EltVT.getSizeInBits());
336 assert(EltVT.isSimple() && "Promoting to a non-simple vector type!");
338 // Build a new vector type and check if it is legal.
339 MVT NVT = MVT::getVectorVT(EltVT.getSimpleVT(), NumElts);
341 DebugLoc dl = Op.getDebugLoc();
342 SmallVector<SDValue, 4> Operands(Op.getNumOperands());
344 unsigned Opc = Op.getOpcode() == ISD::UINT_TO_FP ? ISD::ZERO_EXTEND :
346 for (unsigned j = 0; j != Op.getNumOperands(); ++j) {
347 if (Op.getOperand(j).getValueType().isVector())
348 Operands[j] = DAG.getNode(Opc, dl, NVT, Op.getOperand(j));
350 Operands[j] = Op.getOperand(j);
353 return DAG.getNode(Op.getOpcode(), dl, Op.getValueType(), &Operands[0],
358 SDValue VectorLegalizer::ExpandLoad(SDValue Op) {
359 DebugLoc dl = Op.getDebugLoc();
360 LoadSDNode *LD = cast<LoadSDNode>(Op.getNode());
361 SDValue Chain = LD->getChain();
362 SDValue BasePTR = LD->getBasePtr();
363 EVT SrcVT = LD->getMemoryVT();
364 ISD::LoadExtType ExtType = LD->getExtensionType();
366 SmallVector<SDValue, 8> LoadVals;
367 SmallVector<SDValue, 8> LoadChains;
368 unsigned NumElem = SrcVT.getVectorNumElements();
369 unsigned Stride = SrcVT.getScalarType().getSizeInBits()/8;
371 for (unsigned Idx=0; Idx<NumElem; Idx++) {
372 SDValue ScalarLoad = DAG.getExtLoad(ExtType, dl,
373 Op.getNode()->getValueType(0).getScalarType(),
374 Chain, BasePTR, LD->getPointerInfo().getWithOffset(Idx * Stride),
375 SrcVT.getScalarType(),
376 LD->isVolatile(), LD->isNonTemporal(),
379 BasePTR = DAG.getNode(ISD::ADD, dl, BasePTR.getValueType(), BasePTR,
380 DAG.getIntPtrConstant(Stride));
382 LoadVals.push_back(ScalarLoad.getValue(0));
383 LoadChains.push_back(ScalarLoad.getValue(1));
386 SDValue NewChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
387 &LoadChains[0], LoadChains.size());
388 SDValue Value = DAG.getNode(ISD::BUILD_VECTOR, dl,
389 Op.getNode()->getValueType(0), &LoadVals[0], LoadVals.size());
391 AddLegalizedOperand(Op.getValue(0), Value);
392 AddLegalizedOperand(Op.getValue(1), NewChain);
394 return (Op.getResNo() ? NewChain : Value);
397 SDValue VectorLegalizer::ExpandStore(SDValue Op) {
398 DebugLoc dl = Op.getDebugLoc();
399 StoreSDNode *ST = cast<StoreSDNode>(Op.getNode());
400 SDValue Chain = ST->getChain();
401 SDValue BasePTR = ST->getBasePtr();
402 SDValue Value = ST->getValue();
403 EVT StVT = ST->getMemoryVT();
405 unsigned Alignment = ST->getAlignment();
406 bool isVolatile = ST->isVolatile();
407 bool isNonTemporal = ST->isNonTemporal();
409 unsigned NumElem = StVT.getVectorNumElements();
410 // The type of the data we want to save
411 EVT RegVT = Value.getValueType();
412 EVT RegSclVT = RegVT.getScalarType();
413 // The type of data as saved in memory.
414 EVT MemSclVT = StVT.getScalarType();
416 // Cast floats into integers
417 unsigned ScalarSize = MemSclVT.getSizeInBits();
419 // Round odd types to the next pow of two.
420 if (!isPowerOf2_32(ScalarSize))
421 ScalarSize = NextPowerOf2(ScalarSize);
423 // Store Stride in bytes
424 unsigned Stride = ScalarSize/8;
425 // Extract each of the elements from the original vector
426 // and save them into memory individually.
427 SmallVector<SDValue, 8> Stores;
428 for (unsigned Idx = 0; Idx < NumElem; Idx++) {
429 SDValue Ex = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
430 RegSclVT, Value, DAG.getIntPtrConstant(Idx));
432 // This scalar TruncStore may be illegal, but we legalize it later.
433 SDValue Store = DAG.getTruncStore(Chain, dl, Ex, BasePTR,
434 ST->getPointerInfo().getWithOffset(Idx*Stride), MemSclVT,
435 isVolatile, isNonTemporal, Alignment);
437 BasePTR = DAG.getNode(ISD::ADD, dl, BasePTR.getValueType(), BasePTR,
438 DAG.getIntPtrConstant(Stride));
440 Stores.push_back(Store);
442 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
443 &Stores[0], Stores.size());
444 AddLegalizedOperand(Op, TF);
448 SDValue VectorLegalizer::ExpandSELECT(SDValue Op) {
449 // Lower a select instruction where the condition is a scalar and the
450 // operands are vectors. Lower this select to VSELECT and implement it
451 // using XOR AND OR. The selector bit is broadcasted.
452 EVT VT = Op.getValueType();
453 DebugLoc DL = Op.getDebugLoc();
455 SDValue Mask = Op.getOperand(0);
456 SDValue Op1 = Op.getOperand(1);
457 SDValue Op2 = Op.getOperand(2);
459 assert(VT.isVector() && !Mask.getValueType().isVector()
460 && Op1.getValueType() == Op2.getValueType() && "Invalid type");
462 unsigned NumElem = VT.getVectorNumElements();
464 // If we can't even use the basic vector operations of
465 // AND,OR,XOR, we will have to scalarize the op.
466 // Notice that the operation may be 'promoted' which means that it is
467 // 'bitcasted' to another type which is handled.
468 // Also, we need to be able to construct a splat vector using BUILD_VECTOR.
469 if (TLI.getOperationAction(ISD::AND, VT) == TargetLowering::Expand ||
470 TLI.getOperationAction(ISD::XOR, VT) == TargetLowering::Expand ||
471 TLI.getOperationAction(ISD::OR, VT) == TargetLowering::Expand ||
472 TLI.getOperationAction(ISD::BUILD_VECTOR, VT) == TargetLowering::Expand)
473 return DAG.UnrollVectorOp(Op.getNode());
475 // Generate a mask operand.
476 EVT MaskTy = TLI.getSetCCResultType(VT);
477 assert(MaskTy.isVector() && "Invalid CC type");
478 assert(MaskTy.getSizeInBits() == Op1.getValueType().getSizeInBits()
479 && "Invalid mask size");
481 // What is the size of each element in the vector mask.
482 EVT BitTy = MaskTy.getScalarType();
484 Mask = DAG.getNode(ISD::SELECT, DL, BitTy, Mask,
485 DAG.getConstant(APInt::getAllOnesValue(BitTy.getSizeInBits()), BitTy),
486 DAG.getConstant(0, BitTy));
488 // Broadcast the mask so that the entire vector is all-one or all zero.
489 SmallVector<SDValue, 8> Ops(NumElem, Mask);
490 Mask = DAG.getNode(ISD::BUILD_VECTOR, DL, MaskTy, &Ops[0], Ops.size());
492 // Bitcast the operands to be the same type as the mask.
493 // This is needed when we select between FP types because
494 // the mask is a vector of integers.
495 Op1 = DAG.getNode(ISD::BITCAST, DL, MaskTy, Op1);
496 Op2 = DAG.getNode(ISD::BITCAST, DL, MaskTy, Op2);
498 SDValue AllOnes = DAG.getConstant(
499 APInt::getAllOnesValue(BitTy.getSizeInBits()), MaskTy);
500 SDValue NotMask = DAG.getNode(ISD::XOR, DL, MaskTy, Mask, AllOnes);
502 Op1 = DAG.getNode(ISD::AND, DL, MaskTy, Op1, Mask);
503 Op2 = DAG.getNode(ISD::AND, DL, MaskTy, Op2, NotMask);
504 SDValue Val = DAG.getNode(ISD::OR, DL, MaskTy, Op1, Op2);
505 return DAG.getNode(ISD::BITCAST, DL, Op.getValueType(), Val);
508 SDValue VectorLegalizer::ExpandSEXTINREG(SDValue Op) {
509 EVT VT = Op.getValueType();
511 // Make sure that the SRA and SHL instructions are available.
512 if (TLI.getOperationAction(ISD::SRA, VT) == TargetLowering::Expand ||
513 TLI.getOperationAction(ISD::SHL, VT) == TargetLowering::Expand)
514 return DAG.UnrollVectorOp(Op.getNode());
516 DebugLoc DL = Op.getDebugLoc();
517 EVT OrigTy = cast<VTSDNode>(Op->getOperand(1))->getVT();
519 unsigned BW = VT.getScalarType().getSizeInBits();
520 unsigned OrigBW = OrigTy.getScalarType().getSizeInBits();
521 SDValue ShiftSz = DAG.getConstant(BW - OrigBW, VT);
523 Op = Op.getOperand(0);
524 Op = DAG.getNode(ISD::SHL, DL, VT, Op, ShiftSz);
525 return DAG.getNode(ISD::SRA, DL, VT, Op, ShiftSz);
528 SDValue VectorLegalizer::ExpandVSELECT(SDValue Op) {
529 // Implement VSELECT in terms of XOR, AND, OR
530 // on platforms which do not support blend natively.
531 EVT VT = Op.getOperand(0).getValueType();
532 DebugLoc DL = Op.getDebugLoc();
534 SDValue Mask = Op.getOperand(0);
535 SDValue Op1 = Op.getOperand(1);
536 SDValue Op2 = Op.getOperand(2);
538 // If we can't even use the basic vector operations of
539 // AND,OR,XOR, we will have to scalarize the op.
540 // Notice that the operation may be 'promoted' which means that it is
541 // 'bitcasted' to another type which is handled.
542 // This operation also isn't safe with AND, OR, XOR when the boolean
543 // type is 0/1 as we need an all ones vector constant to mask with.
544 // FIXME: Sign extend 1 to all ones if thats legal on the target.
545 if (TLI.getOperationAction(ISD::AND, VT) == TargetLowering::Expand ||
546 TLI.getOperationAction(ISD::XOR, VT) == TargetLowering::Expand ||
547 TLI.getOperationAction(ISD::OR, VT) == TargetLowering::Expand ||
548 TLI.getBooleanContents(true) !=
549 TargetLowering::ZeroOrNegativeOneBooleanContent)
550 return DAG.UnrollVectorOp(Op.getNode());
552 assert(VT.getSizeInBits() == Op1.getValueType().getSizeInBits()
553 && "Invalid mask size");
554 // Bitcast the operands to be the same type as the mask.
555 // This is needed when we select between FP types because
556 // the mask is a vector of integers.
557 Op1 = DAG.getNode(ISD::BITCAST, DL, VT, Op1);
558 Op2 = DAG.getNode(ISD::BITCAST, DL, VT, Op2);
560 SDValue AllOnes = DAG.getConstant(
561 APInt::getAllOnesValue(VT.getScalarType().getSizeInBits()), VT);
562 SDValue NotMask = DAG.getNode(ISD::XOR, DL, VT, Mask, AllOnes);
564 Op1 = DAG.getNode(ISD::AND, DL, VT, Op1, Mask);
565 Op2 = DAG.getNode(ISD::AND, DL, VT, Op2, NotMask);
566 SDValue Val = DAG.getNode(ISD::OR, DL, VT, Op1, Op2);
567 return DAG.getNode(ISD::BITCAST, DL, Op.getValueType(), Val);
570 SDValue VectorLegalizer::ExpandUINT_TO_FLOAT(SDValue Op) {
571 EVT VT = Op.getOperand(0).getValueType();
572 DebugLoc DL = Op.getDebugLoc();
574 // Make sure that the SINT_TO_FP and SRL instructions are available.
575 if (TLI.getOperationAction(ISD::SINT_TO_FP, VT) == TargetLowering::Expand ||
576 TLI.getOperationAction(ISD::SRL, VT) == TargetLowering::Expand)
577 return DAG.UnrollVectorOp(Op.getNode());
579 EVT SVT = VT.getScalarType();
580 assert((SVT.getSizeInBits() == 64 || SVT.getSizeInBits() == 32) &&
581 "Elements in vector-UINT_TO_FP must be 32 or 64 bits wide");
583 unsigned BW = SVT.getSizeInBits();
584 SDValue HalfWord = DAG.getConstant(BW/2, VT);
586 // Constants to clear the upper part of the word.
587 // Notice that we can also use SHL+SHR, but using a constant is slightly
589 uint64_t HWMask = (SVT.getSizeInBits()==64)?0x00000000FFFFFFFF:0x0000FFFF;
590 SDValue HalfWordMask = DAG.getConstant(HWMask, VT);
592 // Two to the power of half-word-size.
593 SDValue TWOHW = DAG.getConstantFP((1<<(BW/2)), Op.getValueType());
595 // Clear upper part of LO, lower HI
596 SDValue HI = DAG.getNode(ISD::SRL, DL, VT, Op.getOperand(0), HalfWord);
597 SDValue LO = DAG.getNode(ISD::AND, DL, VT, Op.getOperand(0), HalfWordMask);
599 // Convert hi and lo to floats
600 // Convert the hi part back to the upper values
601 SDValue fHI = DAG.getNode(ISD::SINT_TO_FP, DL, Op.getValueType(), HI);
602 fHI = DAG.getNode(ISD::FMUL, DL, Op.getValueType(), fHI, TWOHW);
603 SDValue fLO = DAG.getNode(ISD::SINT_TO_FP, DL, Op.getValueType(), LO);
605 // Add the two halves
606 return DAG.getNode(ISD::FADD, DL, Op.getValueType(), fHI, fLO);
610 SDValue VectorLegalizer::ExpandFNEG(SDValue Op) {
611 if (TLI.isOperationLegalOrCustom(ISD::FSUB, Op.getValueType())) {
612 SDValue Zero = DAG.getConstantFP(-0.0, Op.getValueType());
613 return DAG.getNode(ISD::FSUB, Op.getDebugLoc(), Op.getValueType(),
614 Zero, Op.getOperand(0));
616 return DAG.UnrollVectorOp(Op.getNode());
619 SDValue VectorLegalizer::UnrollVSETCC(SDValue Op) {
620 EVT VT = Op.getValueType();
621 unsigned NumElems = VT.getVectorNumElements();
622 EVT EltVT = VT.getVectorElementType();
623 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1), CC = Op.getOperand(2);
624 EVT TmpEltVT = LHS.getValueType().getVectorElementType();
625 DebugLoc dl = Op.getDebugLoc();
626 SmallVector<SDValue, 8> Ops(NumElems);
627 for (unsigned i = 0; i < NumElems; ++i) {
628 SDValue LHSElem = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, TmpEltVT, LHS,
629 DAG.getIntPtrConstant(i));
630 SDValue RHSElem = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, TmpEltVT, RHS,
631 DAG.getIntPtrConstant(i));
632 Ops[i] = DAG.getNode(ISD::SETCC, dl, TLI.getSetCCResultType(TmpEltVT),
633 LHSElem, RHSElem, CC);
634 Ops[i] = DAG.getNode(ISD::SELECT, dl, EltVT, Ops[i],
635 DAG.getConstant(APInt::getAllOnesValue
636 (EltVT.getSizeInBits()), EltVT),
637 DAG.getConstant(0, EltVT));
639 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &Ops[0], NumElems);
644 bool SelectionDAG::LegalizeVectors() {
645 return VectorLegalizer(*this).Run();