1 //===----- LegalizeIntegerTypes.cpp - Legalization of integer types -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements integer type expansion and promotion for LegalizeTypes.
11 // Promotion is the act of changing a computation in an illegal type into a
12 // computation in a larger type. For example, implementing i8 arithmetic in an
13 // i32 register (often needed on powerpc).
14 // Expansion is the act of changing a computation in an illegal type into a
15 // computation in two identical registers of a smaller type. For example,
16 // implementing i64 arithmetic in two i32 registers (often needed on 32-bit
19 //===----------------------------------------------------------------------===//
21 #include "LegalizeTypes.h"
22 #include "llvm/CodeGen/PseudoSourceValue.h"
23 #include "llvm/Support/ErrorHandling.h"
24 #include "llvm/Support/raw_ostream.h"
27 //===----------------------------------------------------------------------===//
28 // Integer Result Promotion
29 //===----------------------------------------------------------------------===//
31 /// PromoteIntegerResult - This method is called when a result of a node is
32 /// found to be in need of promotion to a larger type. At this point, the node
33 /// may also have invalid operands or may have other results that need
34 /// expansion, we just know that (at least) one result needs promotion.
35 void DAGTypeLegalizer::PromoteIntegerResult(SDNode *N, unsigned ResNo) {
36 DEBUG(errs() << "Promote integer result: "; N->dump(&DAG); errs() << "\n");
37 SDValue Res = SDValue();
39 // See if the target wants to custom expand this node.
40 if (CustomLowerNode(N, N->getValueType(ResNo), true))
43 switch (N->getOpcode()) {
46 errs() << "PromoteIntegerResult #" << ResNo << ": ";
47 N->dump(&DAG); errs() << "\n";
49 llvm_unreachable("Do not know how to promote this operator!");
50 case ISD::AssertSext: Res = PromoteIntRes_AssertSext(N); break;
51 case ISD::AssertZext: Res = PromoteIntRes_AssertZext(N); break;
52 case ISD::BIT_CONVERT: Res = PromoteIntRes_BIT_CONVERT(N); break;
53 case ISD::BSWAP: Res = PromoteIntRes_BSWAP(N); break;
54 case ISD::BUILD_PAIR: Res = PromoteIntRes_BUILD_PAIR(N); break;
55 case ISD::Constant: Res = PromoteIntRes_Constant(N); break;
56 case ISD::CONVERT_RNDSAT:
57 Res = PromoteIntRes_CONVERT_RNDSAT(N); break;
58 case ISD::CTLZ: Res = PromoteIntRes_CTLZ(N); break;
59 case ISD::CTPOP: Res = PromoteIntRes_CTPOP(N); break;
60 case ISD::CTTZ: Res = PromoteIntRes_CTTZ(N); break;
61 case ISD::EXTRACT_VECTOR_ELT:
62 Res = PromoteIntRes_EXTRACT_VECTOR_ELT(N); break;
63 case ISD::LOAD: Res = PromoteIntRes_LOAD(cast<LoadSDNode>(N));break;
64 case ISD::SELECT: Res = PromoteIntRes_SELECT(N); break;
65 case ISD::SELECT_CC: Res = PromoteIntRes_SELECT_CC(N); break;
66 case ISD::SETCC: Res = PromoteIntRes_SETCC(N); break;
67 case ISD::SHL: Res = PromoteIntRes_SHL(N); break;
68 case ISD::SIGN_EXTEND_INREG:
69 Res = PromoteIntRes_SIGN_EXTEND_INREG(N); break;
70 case ISD::SRA: Res = PromoteIntRes_SRA(N); break;
71 case ISD::SRL: Res = PromoteIntRes_SRL(N); break;
72 case ISD::TRUNCATE: Res = PromoteIntRes_TRUNCATE(N); break;
73 case ISD::UNDEF: Res = PromoteIntRes_UNDEF(N); break;
74 case ISD::VAARG: Res = PromoteIntRes_VAARG(N); break;
76 case ISD::SIGN_EXTEND:
77 case ISD::ZERO_EXTEND:
78 case ISD::ANY_EXTEND: Res = PromoteIntRes_INT_EXTEND(N); break;
81 case ISD::FP_TO_UINT: Res = PromoteIntRes_FP_TO_XINT(N); break;
88 case ISD::MUL: Res = PromoteIntRes_SimpleIntBinOp(N); break;
91 case ISD::SREM: Res = PromoteIntRes_SDIV(N); break;
94 case ISD::UREM: Res = PromoteIntRes_UDIV(N); break;
97 case ISD::SSUBO: Res = PromoteIntRes_SADDSUBO(N, ResNo); break;
99 case ISD::USUBO: Res = PromoteIntRes_UADDSUBO(N, ResNo); break;
101 case ISD::UMULO: Res = PromoteIntRes_XMULO(N, ResNo); break;
103 case ISD::ATOMIC_LOAD_ADD:
104 case ISD::ATOMIC_LOAD_SUB:
105 case ISD::ATOMIC_LOAD_AND:
106 case ISD::ATOMIC_LOAD_OR:
107 case ISD::ATOMIC_LOAD_XOR:
108 case ISD::ATOMIC_LOAD_NAND:
109 case ISD::ATOMIC_LOAD_MIN:
110 case ISD::ATOMIC_LOAD_MAX:
111 case ISD::ATOMIC_LOAD_UMIN:
112 case ISD::ATOMIC_LOAD_UMAX:
113 case ISD::ATOMIC_SWAP:
114 Res = PromoteIntRes_Atomic1(cast<AtomicSDNode>(N)); break;
116 case ISD::ATOMIC_CMP_SWAP:
117 Res = PromoteIntRes_Atomic2(cast<AtomicSDNode>(N)); break;
120 // If the result is null then the sub-method took care of registering it.
122 SetPromotedInteger(SDValue(N, ResNo), Res);
125 SDValue DAGTypeLegalizer::PromoteIntRes_AssertSext(SDNode *N) {
126 // Sign-extend the new bits, and continue the assertion.
127 SDValue Op = SExtPromotedInteger(N->getOperand(0));
128 return DAG.getNode(ISD::AssertSext, N->getDebugLoc(),
129 Op.getValueType(), Op, N->getOperand(1));
132 SDValue DAGTypeLegalizer::PromoteIntRes_AssertZext(SDNode *N) {
133 // Zero the new bits, and continue the assertion.
134 SDValue Op = ZExtPromotedInteger(N->getOperand(0));
135 return DAG.getNode(ISD::AssertZext, N->getDebugLoc(),
136 Op.getValueType(), Op, N->getOperand(1));
139 SDValue DAGTypeLegalizer::PromoteIntRes_Atomic1(AtomicSDNode *N) {
140 SDValue Op2 = GetPromotedInteger(N->getOperand(2));
141 SDValue Res = DAG.getAtomic(N->getOpcode(), N->getDebugLoc(),
143 N->getChain(), N->getBasePtr(),
144 Op2, N->getSrcValue(), N->getAlignment());
145 // Legalized the chain result - switch anything that used the old chain to
147 ReplaceValueWith(SDValue(N, 1), Res.getValue(1));
151 SDValue DAGTypeLegalizer::PromoteIntRes_Atomic2(AtomicSDNode *N) {
152 SDValue Op2 = GetPromotedInteger(N->getOperand(2));
153 SDValue Op3 = GetPromotedInteger(N->getOperand(3));
154 SDValue Res = DAG.getAtomic(N->getOpcode(), N->getDebugLoc(),
155 N->getMemoryVT(), N->getChain(), N->getBasePtr(),
156 Op2, Op3, N->getSrcValue(), N->getAlignment());
157 // Legalized the chain result - switch anything that used the old chain to
159 ReplaceValueWith(SDValue(N, 1), Res.getValue(1));
163 SDValue DAGTypeLegalizer::PromoteIntRes_BIT_CONVERT(SDNode *N) {
164 SDValue InOp = N->getOperand(0);
165 EVT InVT = InOp.getValueType();
166 EVT NInVT = TLI.getTypeToTransformTo(*DAG.getContext(), InVT);
167 EVT OutVT = N->getValueType(0);
168 EVT NOutVT = TLI.getTypeToTransformTo(*DAG.getContext(), OutVT);
169 DebugLoc dl = N->getDebugLoc();
171 switch (getTypeAction(InVT)) {
173 assert(false && "Unknown type action!");
178 if (NOutVT.bitsEq(NInVT))
179 // The input promotes to the same size. Convert the promoted value.
180 return DAG.getNode(ISD::BIT_CONVERT, dl,
181 NOutVT, GetPromotedInteger(InOp));
184 // Promote the integer operand by hand.
185 return DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT, GetSoftenedFloat(InOp));
189 case ScalarizeVector:
190 // Convert the element to an integer and promote it by hand.
191 return DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT,
192 BitConvertToInteger(GetScalarizedVector(InOp)));
194 // For example, i32 = BIT_CONVERT v2i16 on alpha. Convert the split
195 // pieces of the input into integers and reassemble in the final type.
197 GetSplitVector(N->getOperand(0), Lo, Hi);
198 Lo = BitConvertToInteger(Lo);
199 Hi = BitConvertToInteger(Hi);
201 if (TLI.isBigEndian())
204 InOp = DAG.getNode(ISD::ANY_EXTEND, dl,
205 EVT::getIntegerVT(*DAG.getContext(), NOutVT.getSizeInBits()),
206 JoinIntegers(Lo, Hi));
207 return DAG.getNode(ISD::BIT_CONVERT, dl, NOutVT, InOp);
210 if (OutVT.bitsEq(NInVT))
211 // The input is widened to the same size. Convert to the widened value.
212 return DAG.getNode(ISD::BIT_CONVERT, dl, OutVT, GetWidenedVector(InOp));
215 return DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT,
216 CreateStackStoreLoad(InOp, OutVT));
219 SDValue DAGTypeLegalizer::PromoteIntRes_BSWAP(SDNode *N) {
220 SDValue Op = GetPromotedInteger(N->getOperand(0));
221 EVT OVT = N->getValueType(0);
222 EVT NVT = Op.getValueType();
223 DebugLoc dl = N->getDebugLoc();
225 unsigned DiffBits = NVT.getSizeInBits() - OVT.getSizeInBits();
226 return DAG.getNode(ISD::SRL, dl, NVT, DAG.getNode(ISD::BSWAP, dl, NVT, Op),
227 DAG.getConstant(DiffBits, TLI.getPointerTy()));
230 SDValue DAGTypeLegalizer::PromoteIntRes_BUILD_PAIR(SDNode *N) {
231 // The pair element type may be legal, or may not promote to the same type as
232 // the result, for example i14 = BUILD_PAIR (i7, i7). Handle all cases.
233 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(),
234 TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)),
235 JoinIntegers(N->getOperand(0), N->getOperand(1)));
238 SDValue DAGTypeLegalizer::PromoteIntRes_Constant(SDNode *N) {
239 EVT VT = N->getValueType(0);
240 // FIXME there is no actual debug info here
241 DebugLoc dl = N->getDebugLoc();
242 // Zero extend things like i1, sign extend everything else. It shouldn't
243 // matter in theory which one we pick, but this tends to give better code?
244 unsigned Opc = VT.isByteSized() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
245 SDValue Result = DAG.getNode(Opc, dl, TLI.getTypeToTransformTo(*DAG.getContext(), VT),
247 assert(isa<ConstantSDNode>(Result) && "Didn't constant fold ext?");
251 SDValue DAGTypeLegalizer::PromoteIntRes_CONVERT_RNDSAT(SDNode *N) {
252 ISD::CvtCode CvtCode = cast<CvtRndSatSDNode>(N)->getCvtCode();
253 assert ((CvtCode == ISD::CVT_SS || CvtCode == ISD::CVT_SU ||
254 CvtCode == ISD::CVT_US || CvtCode == ISD::CVT_UU ||
255 CvtCode == ISD::CVT_SF || CvtCode == ISD::CVT_UF) &&
256 "can only promote integers");
257 EVT OutVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
258 return DAG.getConvertRndSat(OutVT, N->getDebugLoc(), N->getOperand(0),
259 N->getOperand(1), N->getOperand(2),
260 N->getOperand(3), N->getOperand(4), CvtCode);
263 SDValue DAGTypeLegalizer::PromoteIntRes_CTLZ(SDNode *N) {
264 // Zero extend to the promoted type and do the count there.
265 SDValue Op = ZExtPromotedInteger(N->getOperand(0));
266 DebugLoc dl = N->getDebugLoc();
267 EVT OVT = N->getValueType(0);
268 EVT NVT = Op.getValueType();
269 Op = DAG.getNode(ISD::CTLZ, dl, NVT, Op);
270 // Subtract off the extra leading bits in the bigger type.
271 return DAG.getNode(ISD::SUB, dl, NVT, Op,
272 DAG.getConstant(NVT.getSizeInBits() -
273 OVT.getSizeInBits(), NVT));
276 SDValue DAGTypeLegalizer::PromoteIntRes_CTPOP(SDNode *N) {
277 // Zero extend to the promoted type and do the count there.
278 SDValue Op = ZExtPromotedInteger(N->getOperand(0));
279 return DAG.getNode(ISD::CTPOP, N->getDebugLoc(), Op.getValueType(), Op);
282 SDValue DAGTypeLegalizer::PromoteIntRes_CTTZ(SDNode *N) {
283 SDValue Op = GetPromotedInteger(N->getOperand(0));
284 EVT OVT = N->getValueType(0);
285 EVT NVT = Op.getValueType();
286 DebugLoc dl = N->getDebugLoc();
287 // The count is the same in the promoted type except if the original
288 // value was zero. This can be handled by setting the bit just off
289 // the top of the original type.
290 APInt TopBit(NVT.getSizeInBits(), 0);
291 TopBit.set(OVT.getSizeInBits());
292 Op = DAG.getNode(ISD::OR, dl, NVT, Op, DAG.getConstant(TopBit, NVT));
293 return DAG.getNode(ISD::CTTZ, dl, NVT, Op);
296 SDValue DAGTypeLegalizer::PromoteIntRes_EXTRACT_VECTOR_ELT(SDNode *N) {
297 DebugLoc dl = N->getDebugLoc();
298 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
299 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, NVT, N->getOperand(0),
303 SDValue DAGTypeLegalizer::PromoteIntRes_FP_TO_XINT(SDNode *N) {
304 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
305 unsigned NewOpc = N->getOpcode();
306 DebugLoc dl = N->getDebugLoc();
308 // If we're promoting a UINT to a larger size and the larger FP_TO_UINT is
309 // not Legal, check to see if we can use FP_TO_SINT instead. (If both UINT
310 // and SINT conversions are Custom, there is no way to tell which is preferable.
311 // We choose SINT because that's the right thing on PPC.)
312 if (N->getOpcode() == ISD::FP_TO_UINT &&
313 !TLI.isOperationLegal(ISD::FP_TO_UINT, NVT) &&
314 TLI.isOperationLegalOrCustom(ISD::FP_TO_SINT, NVT))
315 NewOpc = ISD::FP_TO_SINT;
317 SDValue Res = DAG.getNode(NewOpc, dl, NVT, N->getOperand(0));
319 // Assert that the converted value fits in the original type. If it doesn't
320 // (eg: because the value being converted is too big), then the result of the
321 // original operation was undefined anyway, so the assert is still correct.
322 return DAG.getNode(N->getOpcode() == ISD::FP_TO_UINT ?
323 ISD::AssertZext : ISD::AssertSext, dl,
324 NVT, Res, DAG.getValueType(N->getValueType(0)));
327 SDValue DAGTypeLegalizer::PromoteIntRes_INT_EXTEND(SDNode *N) {
328 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
329 DebugLoc dl = N->getDebugLoc();
331 if (getTypeAction(N->getOperand(0).getValueType()) == PromoteInteger) {
332 SDValue Res = GetPromotedInteger(N->getOperand(0));
333 assert(Res.getValueType().bitsLE(NVT) && "Extension doesn't make sense!");
335 // If the result and operand types are the same after promotion, simplify
336 // to an in-register extension.
337 if (NVT == Res.getValueType()) {
338 // The high bits are not guaranteed to be anything. Insert an extend.
339 if (N->getOpcode() == ISD::SIGN_EXTEND)
340 return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NVT, Res,
341 DAG.getValueType(N->getOperand(0).getValueType()));
342 if (N->getOpcode() == ISD::ZERO_EXTEND)
343 return DAG.getZeroExtendInReg(Res, dl, N->getOperand(0).getValueType());
344 assert(N->getOpcode() == ISD::ANY_EXTEND && "Unknown integer extension!");
349 // Otherwise, just extend the original operand all the way to the larger type.
350 return DAG.getNode(N->getOpcode(), dl, NVT, N->getOperand(0));
353 SDValue DAGTypeLegalizer::PromoteIntRes_LOAD(LoadSDNode *N) {
354 assert(ISD::isUNINDEXEDLoad(N) && "Indexed load during type legalization!");
355 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
356 ISD::LoadExtType ExtType =
357 ISD::isNON_EXTLoad(N) ? ISD::EXTLOAD : N->getExtensionType();
358 DebugLoc dl = N->getDebugLoc();
359 SDValue Res = DAG.getExtLoad(ExtType, dl, NVT, N->getChain(), N->getBasePtr(),
360 N->getSrcValue(), N->getSrcValueOffset(),
361 N->getMemoryVT(), N->isVolatile(),
364 // Legalized the chain result - switch anything that used the old chain to
366 ReplaceValueWith(SDValue(N, 1), Res.getValue(1));
370 /// Promote the overflow flag of an overflowing arithmetic node.
371 SDValue DAGTypeLegalizer::PromoteIntRes_Overflow(SDNode *N) {
372 // Simply change the return type of the boolean result.
373 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(1));
374 EVT ValueVTs[] = { N->getValueType(0), NVT };
375 SDValue Ops[] = { N->getOperand(0), N->getOperand(1) };
376 SDValue Res = DAG.getNode(N->getOpcode(), N->getDebugLoc(),
377 DAG.getVTList(ValueVTs, 2), Ops, 2);
379 // Modified the sum result - switch anything that used the old sum to use
381 ReplaceValueWith(SDValue(N, 0), Res);
383 return SDValue(Res.getNode(), 1);
386 SDValue DAGTypeLegalizer::PromoteIntRes_SADDSUBO(SDNode *N, unsigned ResNo) {
388 return PromoteIntRes_Overflow(N);
390 // The operation overflowed iff the result in the larger type is not the
391 // sign extension of its truncation to the original type.
392 SDValue LHS = SExtPromotedInteger(N->getOperand(0));
393 SDValue RHS = SExtPromotedInteger(N->getOperand(1));
394 EVT OVT = N->getOperand(0).getValueType();
395 EVT NVT = LHS.getValueType();
396 DebugLoc dl = N->getDebugLoc();
398 // Do the arithmetic in the larger type.
399 unsigned Opcode = N->getOpcode() == ISD::SADDO ? ISD::ADD : ISD::SUB;
400 SDValue Res = DAG.getNode(Opcode, dl, NVT, LHS, RHS);
402 // Calculate the overflow flag: sign extend the arithmetic result from
403 // the original type.
404 SDValue Ofl = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NVT, Res,
405 DAG.getValueType(OVT));
406 // Overflowed if and only if this is not equal to Res.
407 Ofl = DAG.getSetCC(dl, N->getValueType(1), Ofl, Res, ISD::SETNE);
409 // Use the calculated overflow everywhere.
410 ReplaceValueWith(SDValue(N, 1), Ofl);
415 SDValue DAGTypeLegalizer::PromoteIntRes_SDIV(SDNode *N) {
416 // Sign extend the input.
417 SDValue LHS = SExtPromotedInteger(N->getOperand(0));
418 SDValue RHS = SExtPromotedInteger(N->getOperand(1));
419 return DAG.getNode(N->getOpcode(), N->getDebugLoc(),
420 LHS.getValueType(), LHS, RHS);
423 SDValue DAGTypeLegalizer::PromoteIntRes_SELECT(SDNode *N) {
424 SDValue LHS = GetPromotedInteger(N->getOperand(1));
425 SDValue RHS = GetPromotedInteger(N->getOperand(2));
426 return DAG.getNode(ISD::SELECT, N->getDebugLoc(),
427 LHS.getValueType(), N->getOperand(0),LHS,RHS);
430 SDValue DAGTypeLegalizer::PromoteIntRes_SELECT_CC(SDNode *N) {
431 SDValue LHS = GetPromotedInteger(N->getOperand(2));
432 SDValue RHS = GetPromotedInteger(N->getOperand(3));
433 return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(),
434 LHS.getValueType(), N->getOperand(0),
435 N->getOperand(1), LHS, RHS, N->getOperand(4));
438 SDValue DAGTypeLegalizer::PromoteIntRes_SETCC(SDNode *N) {
439 EVT SVT = TLI.getSetCCResultType(N->getOperand(0).getValueType());
440 assert(isTypeLegal(SVT) && "Illegal SetCC type!");
441 DebugLoc dl = N->getDebugLoc();
443 // Get the SETCC result using the canonical SETCC type.
444 SDValue SetCC = DAG.getNode(ISD::SETCC, dl, SVT, N->getOperand(0),
445 N->getOperand(1), N->getOperand(2));
447 // Convert to the expected type.
448 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
449 assert(NVT.bitsLE(SVT) && "Integer type overpromoted?");
450 return DAG.getNode(ISD::TRUNCATE, dl, NVT, SetCC);
453 SDValue DAGTypeLegalizer::PromoteIntRes_SHL(SDNode *N) {
454 return DAG.getNode(ISD::SHL, N->getDebugLoc(),
455 TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)),
456 GetPromotedInteger(N->getOperand(0)), N->getOperand(1));
459 SDValue DAGTypeLegalizer::PromoteIntRes_SIGN_EXTEND_INREG(SDNode *N) {
460 SDValue Op = GetPromotedInteger(N->getOperand(0));
461 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(),
462 Op.getValueType(), Op, N->getOperand(1));
465 SDValue DAGTypeLegalizer::PromoteIntRes_SimpleIntBinOp(SDNode *N) {
466 // The input may have strange things in the top bits of the registers, but
467 // these operations don't care. They may have weird bits going out, but
468 // that too is okay if they are integer operations.
469 SDValue LHS = GetPromotedInteger(N->getOperand(0));
470 SDValue RHS = GetPromotedInteger(N->getOperand(1));
471 return DAG.getNode(N->getOpcode(), N->getDebugLoc(),
472 LHS.getValueType(), LHS, RHS);
475 SDValue DAGTypeLegalizer::PromoteIntRes_SRA(SDNode *N) {
476 // The input value must be properly sign extended.
477 SDValue Res = SExtPromotedInteger(N->getOperand(0));
478 return DAG.getNode(ISD::SRA, N->getDebugLoc(),
479 Res.getValueType(), Res, N->getOperand(1));
482 SDValue DAGTypeLegalizer::PromoteIntRes_SRL(SDNode *N) {
483 // The input value must be properly zero extended.
484 EVT VT = N->getValueType(0);
485 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
486 SDValue Res = ZExtPromotedInteger(N->getOperand(0));
487 return DAG.getNode(ISD::SRL, N->getDebugLoc(), NVT, Res, N->getOperand(1));
490 SDValue DAGTypeLegalizer::PromoteIntRes_TRUNCATE(SDNode *N) {
491 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
494 switch (getTypeAction(N->getOperand(0).getValueType())) {
495 default: llvm_unreachable("Unknown type action!");
498 Res = N->getOperand(0);
501 Res = GetPromotedInteger(N->getOperand(0));
505 // Truncate to NVT instead of VT
506 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), NVT, Res);
509 SDValue DAGTypeLegalizer::PromoteIntRes_UADDSUBO(SDNode *N, unsigned ResNo) {
511 return PromoteIntRes_Overflow(N);
513 // The operation overflowed iff the result in the larger type is not the
514 // zero extension of its truncation to the original type.
515 SDValue LHS = ZExtPromotedInteger(N->getOperand(0));
516 SDValue RHS = ZExtPromotedInteger(N->getOperand(1));
517 EVT OVT = N->getOperand(0).getValueType();
518 EVT NVT = LHS.getValueType();
519 DebugLoc dl = N->getDebugLoc();
521 // Do the arithmetic in the larger type.
522 unsigned Opcode = N->getOpcode() == ISD::UADDO ? ISD::ADD : ISD::SUB;
523 SDValue Res = DAG.getNode(Opcode, dl, NVT, LHS, RHS);
525 // Calculate the overflow flag: zero extend the arithmetic result from
526 // the original type.
527 SDValue Ofl = DAG.getZeroExtendInReg(Res, dl, OVT);
528 // Overflowed if and only if this is not equal to Res.
529 Ofl = DAG.getSetCC(dl, N->getValueType(1), Ofl, Res, ISD::SETNE);
531 // Use the calculated overflow everywhere.
532 ReplaceValueWith(SDValue(N, 1), Ofl);
537 SDValue DAGTypeLegalizer::PromoteIntRes_UDIV(SDNode *N) {
538 // Zero extend the input.
539 SDValue LHS = ZExtPromotedInteger(N->getOperand(0));
540 SDValue RHS = ZExtPromotedInteger(N->getOperand(1));
541 return DAG.getNode(N->getOpcode(), N->getDebugLoc(),
542 LHS.getValueType(), LHS, RHS);
545 SDValue DAGTypeLegalizer::PromoteIntRes_UNDEF(SDNode *N) {
546 return DAG.getUNDEF(TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)));
549 SDValue DAGTypeLegalizer::PromoteIntRes_VAARG(SDNode *N) {
550 SDValue Chain = N->getOperand(0); // Get the chain.
551 SDValue Ptr = N->getOperand(1); // Get the pointer.
552 EVT VT = N->getValueType(0);
553 DebugLoc dl = N->getDebugLoc();
555 EVT RegVT = TLI.getRegisterType(*DAG.getContext(), VT);
556 unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), VT);
557 // The argument is passed as NumRegs registers of type RegVT.
559 SmallVector<SDValue, 8> Parts(NumRegs);
560 for (unsigned i = 0; i < NumRegs; ++i) {
561 Parts[i] = DAG.getVAArg(RegVT, dl, Chain, Ptr, N->getOperand(2));
562 Chain = Parts[i].getValue(1);
565 // Handle endianness of the load.
566 if (TLI.isBigEndian())
567 std::reverse(Parts.begin(), Parts.end());
569 // Assemble the parts in the promoted type.
570 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
571 SDValue Res = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Parts[0]);
572 for (unsigned i = 1; i < NumRegs; ++i) {
573 SDValue Part = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Parts[i]);
574 // Shift it to the right position and "or" it in.
575 Part = DAG.getNode(ISD::SHL, dl, NVT, Part,
576 DAG.getConstant(i * RegVT.getSizeInBits(),
577 TLI.getPointerTy()));
578 Res = DAG.getNode(ISD::OR, dl, NVT, Res, Part);
581 // Modified the chain result - switch anything that used the old chain to
583 ReplaceValueWith(SDValue(N, 1), Chain);
588 SDValue DAGTypeLegalizer::PromoteIntRes_XMULO(SDNode *N, unsigned ResNo) {
589 assert(ResNo == 1 && "Only boolean result promotion currently supported!");
590 return PromoteIntRes_Overflow(N);
593 //===----------------------------------------------------------------------===//
594 // Integer Operand Promotion
595 //===----------------------------------------------------------------------===//
597 /// PromoteIntegerOperand - This method is called when the specified operand of
598 /// the specified node is found to need promotion. At this point, all of the
599 /// result types of the node are known to be legal, but other operands of the
600 /// node may need promotion or expansion as well as the specified one.
601 bool DAGTypeLegalizer::PromoteIntegerOperand(SDNode *N, unsigned OpNo) {
602 DEBUG(errs() << "Promote integer operand: "; N->dump(&DAG); errs() << "\n");
603 SDValue Res = SDValue();
605 if (CustomLowerNode(N, N->getOperand(OpNo).getValueType(), false))
608 switch (N->getOpcode()) {
611 errs() << "PromoteIntegerOperand Op #" << OpNo << ": ";
612 N->dump(&DAG); errs() << "\n";
614 llvm_unreachable("Do not know how to promote this operator's operand!");
616 case ISD::ANY_EXTEND: Res = PromoteIntOp_ANY_EXTEND(N); break;
617 case ISD::BIT_CONVERT: Res = PromoteIntOp_BIT_CONVERT(N); break;
618 case ISD::BR_CC: Res = PromoteIntOp_BR_CC(N, OpNo); break;
619 case ISD::BRCOND: Res = PromoteIntOp_BRCOND(N, OpNo); break;
620 case ISD::BUILD_PAIR: Res = PromoteIntOp_BUILD_PAIR(N); break;
621 case ISD::BUILD_VECTOR: Res = PromoteIntOp_BUILD_VECTOR(N); break;
622 case ISD::CONVERT_RNDSAT:
623 Res = PromoteIntOp_CONVERT_RNDSAT(N); break;
624 case ISD::INSERT_VECTOR_ELT:
625 Res = PromoteIntOp_INSERT_VECTOR_ELT(N, OpNo);break;
626 case ISD::MEMBARRIER: Res = PromoteIntOp_MEMBARRIER(N); break;
627 case ISD::SCALAR_TO_VECTOR:
628 Res = PromoteIntOp_SCALAR_TO_VECTOR(N); break;
629 case ISD::SELECT: Res = PromoteIntOp_SELECT(N, OpNo); break;
630 case ISD::SELECT_CC: Res = PromoteIntOp_SELECT_CC(N, OpNo); break;
631 case ISD::SETCC: Res = PromoteIntOp_SETCC(N, OpNo); break;
632 case ISD::SIGN_EXTEND: Res = PromoteIntOp_SIGN_EXTEND(N); break;
633 case ISD::SINT_TO_FP: Res = PromoteIntOp_SINT_TO_FP(N); break;
634 case ISD::STORE: Res = PromoteIntOp_STORE(cast<StoreSDNode>(N),
636 case ISD::TRUNCATE: Res = PromoteIntOp_TRUNCATE(N); break;
637 case ISD::UINT_TO_FP: Res = PromoteIntOp_UINT_TO_FP(N); break;
638 case ISD::ZERO_EXTEND: Res = PromoteIntOp_ZERO_EXTEND(N); break;
644 case ISD::ROTR: Res = PromoteIntOp_Shift(N); break;
647 // If the result is null, the sub-method took care of registering results etc.
648 if (!Res.getNode()) return false;
650 // If the result is N, the sub-method updated N in place. Tell the legalizer
652 if (Res.getNode() == N)
655 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 &&
656 "Invalid operand expansion");
658 ReplaceValueWith(SDValue(N, 0), Res);
662 /// PromoteSetCCOperands - Promote the operands of a comparison. This code is
663 /// shared among BR_CC, SELECT_CC, and SETCC handlers.
664 void DAGTypeLegalizer::PromoteSetCCOperands(SDValue &NewLHS,SDValue &NewRHS,
665 ISD::CondCode CCCode) {
666 // We have to insert explicit sign or zero extends. Note that we could
667 // insert sign extends for ALL conditions, but zero extend is cheaper on
668 // many machines (an AND instead of two shifts), so prefer it.
670 default: llvm_unreachable("Unknown integer comparison!");
677 // ALL of these operations will work if we either sign or zero extend
678 // the operands (including the unsigned comparisons!). Zero extend is
679 // usually a simpler/cheaper operation, so prefer it.
680 NewLHS = ZExtPromotedInteger(NewLHS);
681 NewRHS = ZExtPromotedInteger(NewRHS);
687 NewLHS = SExtPromotedInteger(NewLHS);
688 NewRHS = SExtPromotedInteger(NewRHS);
693 SDValue DAGTypeLegalizer::PromoteIntOp_ANY_EXTEND(SDNode *N) {
694 SDValue Op = GetPromotedInteger(N->getOperand(0));
695 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), N->getValueType(0), Op);
698 SDValue DAGTypeLegalizer::PromoteIntOp_BIT_CONVERT(SDNode *N) {
699 // This should only occur in unusual situations like bitcasting to an
700 // x86_fp80, so just turn it into a store+load
701 return CreateStackStoreLoad(N->getOperand(0), N->getValueType(0));
704 SDValue DAGTypeLegalizer::PromoteIntOp_BR_CC(SDNode *N, unsigned OpNo) {
705 assert(OpNo == 2 && "Don't know how to promote this operand!");
707 SDValue LHS = N->getOperand(2);
708 SDValue RHS = N->getOperand(3);
709 PromoteSetCCOperands(LHS, RHS, cast<CondCodeSDNode>(N->getOperand(1))->get());
711 // The chain (Op#0), CC (#1) and basic block destination (Op#4) are always
713 return DAG.UpdateNodeOperands(SDValue(N, 0), N->getOperand(0),
714 N->getOperand(1), LHS, RHS, N->getOperand(4));
717 SDValue DAGTypeLegalizer::PromoteIntOp_BRCOND(SDNode *N, unsigned OpNo) {
718 assert(OpNo == 1 && "only know how to promote condition");
720 // Promote all the way up to the canonical SetCC type.
721 EVT SVT = TLI.getSetCCResultType(MVT::Other);
722 SDValue Cond = PromoteTargetBoolean(N->getOperand(1), SVT);
724 // The chain (Op#0) and basic block destination (Op#2) are always legal types.
725 return DAG.UpdateNodeOperands(SDValue(N, 0), N->getOperand(0), Cond,
729 SDValue DAGTypeLegalizer::PromoteIntOp_BUILD_PAIR(SDNode *N) {
730 // Since the result type is legal, the operands must promote to it.
731 EVT OVT = N->getOperand(0).getValueType();
732 SDValue Lo = ZExtPromotedInteger(N->getOperand(0));
733 SDValue Hi = GetPromotedInteger(N->getOperand(1));
734 assert(Lo.getValueType() == N->getValueType(0) && "Operand over promoted?");
735 DebugLoc dl = N->getDebugLoc();
737 Hi = DAG.getNode(ISD::SHL, dl, N->getValueType(0), Hi,
738 DAG.getConstant(OVT.getSizeInBits(), TLI.getPointerTy()));
739 return DAG.getNode(ISD::OR, dl, N->getValueType(0), Lo, Hi);
742 SDValue DAGTypeLegalizer::PromoteIntOp_BUILD_VECTOR(SDNode *N) {
743 // The vector type is legal but the element type is not. This implies
744 // that the vector is a power-of-two in length and that the element
745 // type does not have a strange size (eg: it is not i1).
746 EVT VecVT = N->getValueType(0);
747 unsigned NumElts = VecVT.getVectorNumElements();
748 assert(!(NumElts & 1) && "Legal vector of one illegal element?");
750 // Promote the inserted value. The type does not need to match the
751 // vector element type. Check that any extra bits introduced will be
753 assert(N->getOperand(0).getValueType().getSizeInBits() >=
754 N->getValueType(0).getVectorElementType().getSizeInBits() &&
755 "Type of inserted value narrower than vector element type!");
757 SmallVector<SDValue, 16> NewOps;
758 for (unsigned i = 0; i < NumElts; ++i)
759 NewOps.push_back(GetPromotedInteger(N->getOperand(i)));
761 return DAG.UpdateNodeOperands(SDValue(N, 0), &NewOps[0], NumElts);
764 SDValue DAGTypeLegalizer::PromoteIntOp_CONVERT_RNDSAT(SDNode *N) {
765 ISD::CvtCode CvtCode = cast<CvtRndSatSDNode>(N)->getCvtCode();
766 assert ((CvtCode == ISD::CVT_SS || CvtCode == ISD::CVT_SU ||
767 CvtCode == ISD::CVT_US || CvtCode == ISD::CVT_UU ||
768 CvtCode == ISD::CVT_FS || CvtCode == ISD::CVT_FU) &&
769 "can only promote integer arguments");
770 SDValue InOp = GetPromotedInteger(N->getOperand(0));
771 return DAG.getConvertRndSat(N->getValueType(0), N->getDebugLoc(), InOp,
772 N->getOperand(1), N->getOperand(2),
773 N->getOperand(3), N->getOperand(4), CvtCode);
776 SDValue DAGTypeLegalizer::PromoteIntOp_INSERT_VECTOR_ELT(SDNode *N,
779 // Promote the inserted value. This is valid because the type does not
780 // have to match the vector element type.
782 // Check that any extra bits introduced will be truncated away.
783 assert(N->getOperand(1).getValueType().getSizeInBits() >=
784 N->getValueType(0).getVectorElementType().getSizeInBits() &&
785 "Type of inserted value narrower than vector element type!");
786 return DAG.UpdateNodeOperands(SDValue(N, 0), N->getOperand(0),
787 GetPromotedInteger(N->getOperand(1)),
791 assert(OpNo == 2 && "Different operand and result vector types?");
793 // Promote the index.
794 SDValue Idx = ZExtPromotedInteger(N->getOperand(2));
795 return DAG.UpdateNodeOperands(SDValue(N, 0), N->getOperand(0),
796 N->getOperand(1), Idx);
799 SDValue DAGTypeLegalizer::PromoteIntOp_MEMBARRIER(SDNode *N) {
801 DebugLoc dl = N->getDebugLoc();
802 NewOps[0] = N->getOperand(0);
803 for (unsigned i = 1; i < array_lengthof(NewOps); ++i) {
804 SDValue Flag = GetPromotedInteger(N->getOperand(i));
805 NewOps[i] = DAG.getZeroExtendInReg(Flag, dl, MVT::i1);
807 return DAG.UpdateNodeOperands(SDValue (N, 0), NewOps,
808 array_lengthof(NewOps));
811 SDValue DAGTypeLegalizer::PromoteIntOp_SCALAR_TO_VECTOR(SDNode *N) {
812 // Integer SCALAR_TO_VECTOR operands are implicitly truncated, so just promote
813 // the operand in place.
814 return DAG.UpdateNodeOperands(SDValue(N, 0),
815 GetPromotedInteger(N->getOperand(0)));
818 SDValue DAGTypeLegalizer::PromoteIntOp_SELECT(SDNode *N, unsigned OpNo) {
819 assert(OpNo == 0 && "Only know how to promote condition");
821 // Promote all the way up to the canonical SetCC type.
822 EVT SVT = TLI.getSetCCResultType(N->getOperand(1).getValueType());
823 SDValue Cond = PromoteTargetBoolean(N->getOperand(0), SVT);
825 return DAG.UpdateNodeOperands(SDValue(N, 0), Cond,
826 N->getOperand(1), N->getOperand(2));
829 SDValue DAGTypeLegalizer::PromoteIntOp_SELECT_CC(SDNode *N, unsigned OpNo) {
830 assert(OpNo == 0 && "Don't know how to promote this operand!");
832 SDValue LHS = N->getOperand(0);
833 SDValue RHS = N->getOperand(1);
834 PromoteSetCCOperands(LHS, RHS, cast<CondCodeSDNode>(N->getOperand(4))->get());
836 // The CC (#4) and the possible return values (#2 and #3) have legal types.
837 return DAG.UpdateNodeOperands(SDValue(N, 0), LHS, RHS, N->getOperand(2),
838 N->getOperand(3), N->getOperand(4));
841 SDValue DAGTypeLegalizer::PromoteIntOp_SETCC(SDNode *N, unsigned OpNo) {
842 assert(OpNo == 0 && "Don't know how to promote this operand!");
844 SDValue LHS = N->getOperand(0);
845 SDValue RHS = N->getOperand(1);
846 PromoteSetCCOperands(LHS, RHS, cast<CondCodeSDNode>(N->getOperand(2))->get());
848 // The CC (#2) is always legal.
849 return DAG.UpdateNodeOperands(SDValue(N, 0), LHS, RHS, N->getOperand(2));
852 SDValue DAGTypeLegalizer::PromoteIntOp_Shift(SDNode *N) {
853 return DAG.UpdateNodeOperands(SDValue(N, 0), N->getOperand(0),
854 ZExtPromotedInteger(N->getOperand(1)));
857 SDValue DAGTypeLegalizer::PromoteIntOp_SIGN_EXTEND(SDNode *N) {
858 SDValue Op = GetPromotedInteger(N->getOperand(0));
859 DebugLoc dl = N->getDebugLoc();
860 Op = DAG.getNode(ISD::ANY_EXTEND, dl, N->getValueType(0), Op);
861 return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Op.getValueType(),
862 Op, DAG.getValueType(N->getOperand(0).getValueType()));
865 SDValue DAGTypeLegalizer::PromoteIntOp_SINT_TO_FP(SDNode *N) {
866 return DAG.UpdateNodeOperands(SDValue(N, 0),
867 SExtPromotedInteger(N->getOperand(0)));
870 SDValue DAGTypeLegalizer::PromoteIntOp_STORE(StoreSDNode *N, unsigned OpNo){
871 assert(ISD::isUNINDEXEDStore(N) && "Indexed store during type legalization!");
872 SDValue Ch = N->getChain(), Ptr = N->getBasePtr();
873 int SVOffset = N->getSrcValueOffset();
874 unsigned Alignment = N->getAlignment();
875 bool isVolatile = N->isVolatile();
876 DebugLoc dl = N->getDebugLoc();
878 SDValue Val = GetPromotedInteger(N->getValue()); // Get promoted value.
880 // Truncate the value and store the result.
881 return DAG.getTruncStore(Ch, dl, Val, Ptr, N->getSrcValue(),
882 SVOffset, N->getMemoryVT(),
883 isVolatile, Alignment);
886 SDValue DAGTypeLegalizer::PromoteIntOp_TRUNCATE(SDNode *N) {
887 SDValue Op = GetPromotedInteger(N->getOperand(0));
888 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), N->getValueType(0), Op);
891 SDValue DAGTypeLegalizer::PromoteIntOp_UINT_TO_FP(SDNode *N) {
892 return DAG.UpdateNodeOperands(SDValue(N, 0),
893 ZExtPromotedInteger(N->getOperand(0)));
896 SDValue DAGTypeLegalizer::PromoteIntOp_ZERO_EXTEND(SDNode *N) {
897 DebugLoc dl = N->getDebugLoc();
898 SDValue Op = GetPromotedInteger(N->getOperand(0));
899 Op = DAG.getNode(ISD::ANY_EXTEND, dl, N->getValueType(0), Op);
900 return DAG.getZeroExtendInReg(Op, dl, N->getOperand(0).getValueType());
904 //===----------------------------------------------------------------------===//
905 // Integer Result Expansion
906 //===----------------------------------------------------------------------===//
908 /// ExpandIntegerResult - This method is called when the specified result of the
909 /// specified node is found to need expansion. At this point, the node may also
910 /// have invalid operands or may have other results that need promotion, we just
911 /// know that (at least) one result needs expansion.
912 void DAGTypeLegalizer::ExpandIntegerResult(SDNode *N, unsigned ResNo) {
913 DEBUG(errs() << "Expand integer result: "; N->dump(&DAG); errs() << "\n");
917 // See if the target wants to custom expand this node.
918 if (CustomLowerNode(N, N->getValueType(ResNo), true))
921 switch (N->getOpcode()) {
924 errs() << "ExpandIntegerResult #" << ResNo << ": ";
925 N->dump(&DAG); errs() << "\n";
927 llvm_unreachable("Do not know how to expand the result of this operator!");
929 case ISD::MERGE_VALUES: SplitRes_MERGE_VALUES(N, Lo, Hi); break;
930 case ISD::SELECT: SplitRes_SELECT(N, Lo, Hi); break;
931 case ISD::SELECT_CC: SplitRes_SELECT_CC(N, Lo, Hi); break;
932 case ISD::UNDEF: SplitRes_UNDEF(N, Lo, Hi); break;
934 case ISD::BIT_CONVERT: ExpandRes_BIT_CONVERT(N, Lo, Hi); break;
935 case ISD::BUILD_PAIR: ExpandRes_BUILD_PAIR(N, Lo, Hi); break;
936 case ISD::EXTRACT_ELEMENT: ExpandRes_EXTRACT_ELEMENT(N, Lo, Hi); break;
937 case ISD::EXTRACT_VECTOR_ELT: ExpandRes_EXTRACT_VECTOR_ELT(N, Lo, Hi); break;
938 case ISD::VAARG: ExpandRes_VAARG(N, Lo, Hi); break;
940 case ISD::ANY_EXTEND: ExpandIntRes_ANY_EXTEND(N, Lo, Hi); break;
941 case ISD::AssertSext: ExpandIntRes_AssertSext(N, Lo, Hi); break;
942 case ISD::AssertZext: ExpandIntRes_AssertZext(N, Lo, Hi); break;
943 case ISD::BSWAP: ExpandIntRes_BSWAP(N, Lo, Hi); break;
944 case ISD::Constant: ExpandIntRes_Constant(N, Lo, Hi); break;
945 case ISD::CTLZ: ExpandIntRes_CTLZ(N, Lo, Hi); break;
946 case ISD::CTPOP: ExpandIntRes_CTPOP(N, Lo, Hi); break;
947 case ISD::CTTZ: ExpandIntRes_CTTZ(N, Lo, Hi); break;
948 case ISD::FP_TO_SINT: ExpandIntRes_FP_TO_SINT(N, Lo, Hi); break;
949 case ISD::FP_TO_UINT: ExpandIntRes_FP_TO_UINT(N, Lo, Hi); break;
950 case ISD::LOAD: ExpandIntRes_LOAD(cast<LoadSDNode>(N), Lo, Hi); break;
951 case ISD::MUL: ExpandIntRes_MUL(N, Lo, Hi); break;
952 case ISD::SDIV: ExpandIntRes_SDIV(N, Lo, Hi); break;
953 case ISD::SIGN_EXTEND: ExpandIntRes_SIGN_EXTEND(N, Lo, Hi); break;
954 case ISD::SIGN_EXTEND_INREG: ExpandIntRes_SIGN_EXTEND_INREG(N, Lo, Hi); break;
955 case ISD::SREM: ExpandIntRes_SREM(N, Lo, Hi); break;
956 case ISD::TRUNCATE: ExpandIntRes_TRUNCATE(N, Lo, Hi); break;
957 case ISD::UDIV: ExpandIntRes_UDIV(N, Lo, Hi); break;
958 case ISD::UREM: ExpandIntRes_UREM(N, Lo, Hi); break;
959 case ISD::ZERO_EXTEND: ExpandIntRes_ZERO_EXTEND(N, Lo, Hi); break;
963 case ISD::XOR: ExpandIntRes_Logical(N, Lo, Hi); break;
966 case ISD::SUB: ExpandIntRes_ADDSUB(N, Lo, Hi); break;
969 case ISD::SUBC: ExpandIntRes_ADDSUBC(N, Lo, Hi); break;
972 case ISD::SUBE: ExpandIntRes_ADDSUBE(N, Lo, Hi); break;
976 case ISD::SRL: ExpandIntRes_Shift(N, Lo, Hi); break;
979 // If Lo/Hi is null, the sub-method took care of registering results etc.
981 SetExpandedInteger(SDValue(N, ResNo), Lo, Hi);
984 /// ExpandShiftByConstant - N is a shift by a value that needs to be expanded,
985 /// and the shift amount is a constant 'Amt'. Expand the operation.
986 void DAGTypeLegalizer::ExpandShiftByConstant(SDNode *N, unsigned Amt,
987 SDValue &Lo, SDValue &Hi) {
988 DebugLoc dl = N->getDebugLoc();
989 // Expand the incoming operand to be shifted, so that we have its parts
991 GetExpandedInteger(N->getOperand(0), InL, InH);
993 EVT NVT = InL.getValueType();
994 unsigned VTBits = N->getValueType(0).getSizeInBits();
995 unsigned NVTBits = NVT.getSizeInBits();
996 EVT ShTy = N->getOperand(1).getValueType();
998 if (N->getOpcode() == ISD::SHL) {
1000 Lo = Hi = DAG.getConstant(0, NVT);
1001 } else if (Amt > NVTBits) {
1002 Lo = DAG.getConstant(0, NVT);
1003 Hi = DAG.getNode(ISD::SHL, dl,
1004 NVT, InL, DAG.getConstant(Amt-NVTBits,ShTy));
1005 } else if (Amt == NVTBits) {
1006 Lo = DAG.getConstant(0, NVT);
1008 } else if (Amt == 1 &&
1009 TLI.isOperationLegalOrCustom(ISD::ADDC,
1010 TLI.getTypeToExpandTo(*DAG.getContext(), NVT))) {
1011 // Emit this X << 1 as X+X.
1012 SDVTList VTList = DAG.getVTList(NVT, MVT::Flag);
1013 SDValue LoOps[2] = { InL, InL };
1014 Lo = DAG.getNode(ISD::ADDC, dl, VTList, LoOps, 2);
1015 SDValue HiOps[3] = { InH, InH, Lo.getValue(1) };
1016 Hi = DAG.getNode(ISD::ADDE, dl, VTList, HiOps, 3);
1018 Lo = DAG.getNode(ISD::SHL, dl, NVT, InL, DAG.getConstant(Amt, ShTy));
1019 Hi = DAG.getNode(ISD::OR, dl, NVT,
1020 DAG.getNode(ISD::SHL, dl, NVT, InH,
1021 DAG.getConstant(Amt, ShTy)),
1022 DAG.getNode(ISD::SRL, dl, NVT, InL,
1023 DAG.getConstant(NVTBits-Amt, ShTy)));
1028 if (N->getOpcode() == ISD::SRL) {
1030 Lo = DAG.getConstant(0, NVT);
1031 Hi = DAG.getConstant(0, NVT);
1032 } else if (Amt > NVTBits) {
1033 Lo = DAG.getNode(ISD::SRL, dl,
1034 NVT, InH, DAG.getConstant(Amt-NVTBits,ShTy));
1035 Hi = DAG.getConstant(0, NVT);
1036 } else if (Amt == NVTBits) {
1038 Hi = DAG.getConstant(0, NVT);
1040 Lo = DAG.getNode(ISD::OR, dl, NVT,
1041 DAG.getNode(ISD::SRL, dl, NVT, InL,
1042 DAG.getConstant(Amt, ShTy)),
1043 DAG.getNode(ISD::SHL, dl, NVT, InH,
1044 DAG.getConstant(NVTBits-Amt, ShTy)));
1045 Hi = DAG.getNode(ISD::SRL, dl, NVT, InH, DAG.getConstant(Amt, ShTy));
1050 assert(N->getOpcode() == ISD::SRA && "Unknown shift!");
1052 Hi = Lo = DAG.getNode(ISD::SRA, dl, NVT, InH,
1053 DAG.getConstant(NVTBits-1, ShTy));
1054 } else if (Amt > NVTBits) {
1055 Lo = DAG.getNode(ISD::SRA, dl, NVT, InH,
1056 DAG.getConstant(Amt-NVTBits, ShTy));
1057 Hi = DAG.getNode(ISD::SRA, dl, NVT, InH,
1058 DAG.getConstant(NVTBits-1, ShTy));
1059 } else if (Amt == NVTBits) {
1061 Hi = DAG.getNode(ISD::SRA, dl, NVT, InH,
1062 DAG.getConstant(NVTBits-1, ShTy));
1064 Lo = DAG.getNode(ISD::OR, dl, NVT,
1065 DAG.getNode(ISD::SRL, dl, NVT, InL,
1066 DAG.getConstant(Amt, ShTy)),
1067 DAG.getNode(ISD::SHL, dl, NVT, InH,
1068 DAG.getConstant(NVTBits-Amt, ShTy)));
1069 Hi = DAG.getNode(ISD::SRA, dl, NVT, InH, DAG.getConstant(Amt, ShTy));
1073 /// ExpandShiftWithKnownAmountBit - Try to determine whether we can simplify
1074 /// this shift based on knowledge of the high bit of the shift amount. If we
1075 /// can tell this, we know that it is >= 32 or < 32, without knowing the actual
1077 bool DAGTypeLegalizer::
1078 ExpandShiftWithKnownAmountBit(SDNode *N, SDValue &Lo, SDValue &Hi) {
1079 SDValue Amt = N->getOperand(1);
1080 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1081 EVT ShTy = Amt.getValueType();
1082 unsigned ShBits = ShTy.getSizeInBits();
1083 unsigned NVTBits = NVT.getSizeInBits();
1084 assert(isPowerOf2_32(NVTBits) &&
1085 "Expanded integer type size not a power of two!");
1086 DebugLoc dl = N->getDebugLoc();
1088 APInt HighBitMask = APInt::getHighBitsSet(ShBits, ShBits - Log2_32(NVTBits));
1089 APInt KnownZero, KnownOne;
1090 DAG.ComputeMaskedBits(N->getOperand(1), HighBitMask, KnownZero, KnownOne);
1092 // If we don't know anything about the high bits, exit.
1093 if (((KnownZero|KnownOne) & HighBitMask) == 0)
1096 // Get the incoming operand to be shifted.
1098 GetExpandedInteger(N->getOperand(0), InL, InH);
1100 // If we know that any of the high bits of the shift amount are one, then we
1101 // can do this as a couple of simple shifts.
1102 if (KnownOne.intersects(HighBitMask)) {
1103 // Mask out the high bit, which we know is set.
1104 Amt = DAG.getNode(ISD::AND, dl, ShTy, Amt,
1105 DAG.getConstant(~HighBitMask, ShTy));
1107 switch (N->getOpcode()) {
1108 default: llvm_unreachable("Unknown shift");
1110 Lo = DAG.getConstant(0, NVT); // Low part is zero.
1111 Hi = DAG.getNode(ISD::SHL, dl, NVT, InL, Amt); // High part from Lo part.
1114 Hi = DAG.getConstant(0, NVT); // Hi part is zero.
1115 Lo = DAG.getNode(ISD::SRL, dl, NVT, InH, Amt); // Lo part from Hi part.
1118 Hi = DAG.getNode(ISD::SRA, dl, NVT, InH, // Sign extend high part.
1119 DAG.getConstant(NVTBits-1, ShTy));
1120 Lo = DAG.getNode(ISD::SRA, dl, NVT, InH, Amt); // Lo part from Hi part.
1126 // FIXME: This code is broken for shifts with a zero amount!
1127 // If we know that all of the high bits of the shift amount are zero, then we
1128 // can do this as a couple of simple shifts.
1129 if ((KnownZero & HighBitMask) == HighBitMask) {
1131 SDValue Amt2 = DAG.getNode(ISD::SUB, ShTy,
1132 DAG.getConstant(NVTBits, ShTy),
1135 switch (N->getOpcode()) {
1136 default: llvm_unreachable("Unknown shift");
1137 case ISD::SHL: Op1 = ISD::SHL; Op2 = ISD::SRL; break;
1139 case ISD::SRA: Op1 = ISD::SRL; Op2 = ISD::SHL; break;
1142 Lo = DAG.getNode(N->getOpcode(), NVT, InL, Amt);
1143 Hi = DAG.getNode(ISD::OR, NVT,
1144 DAG.getNode(Op1, NVT, InH, Amt),
1145 DAG.getNode(Op2, NVT, InL, Amt2));
1153 /// ExpandShiftWithUnknownAmountBit - Fully general expansion of integer shift
1155 bool DAGTypeLegalizer::
1156 ExpandShiftWithUnknownAmountBit(SDNode *N, SDValue &Lo, SDValue &Hi) {
1157 SDValue Amt = N->getOperand(1);
1158 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1159 EVT ShTy = Amt.getValueType();
1160 unsigned NVTBits = NVT.getSizeInBits();
1161 assert(isPowerOf2_32(NVTBits) &&
1162 "Expanded integer type size not a power of two!");
1163 DebugLoc dl = N->getDebugLoc();
1165 // Get the incoming operand to be shifted.
1167 GetExpandedInteger(N->getOperand(0), InL, InH);
1169 SDValue NVBitsNode = DAG.getConstant(NVTBits, ShTy);
1170 SDValue AmtExcess = DAG.getNode(ISD::SUB, dl, ShTy, Amt, NVBitsNode);
1171 SDValue AmtLack = DAG.getNode(ISD::SUB, dl, ShTy, NVBitsNode, Amt);
1172 SDValue isShort = DAG.getSetCC(dl, TLI.getSetCCResultType(ShTy),
1173 Amt, NVBitsNode, ISD::SETULT);
1175 SDValue LoS, HiS, LoL, HiL;
1176 switch (N->getOpcode()) {
1177 default: llvm_unreachable("Unknown shift");
1179 // Short: ShAmt < NVTBits
1180 LoS = DAG.getNode(ISD::SHL, dl, NVT, InL, Amt);
1181 HiS = DAG.getNode(ISD::OR, dl, NVT,
1182 DAG.getNode(ISD::SHL, dl, NVT, InH, Amt),
1183 // FIXME: If Amt is zero, the following shift generates an undefined result
1184 // on some architectures.
1185 DAG.getNode(ISD::SRL, dl, NVT, InL, AmtLack));
1187 // Long: ShAmt >= NVTBits
1188 LoL = DAG.getConstant(0, NVT); // Lo part is zero.
1189 HiL = DAG.getNode(ISD::SHL, dl, NVT, InL, AmtExcess); // Hi from Lo part.
1191 Lo = DAG.getNode(ISD::SELECT, dl, NVT, isShort, LoS, LoL);
1192 Hi = DAG.getNode(ISD::SELECT, dl, NVT, isShort, HiS, HiL);
1195 // Short: ShAmt < NVTBits
1196 HiS = DAG.getNode(ISD::SRL, dl, NVT, InH, Amt);
1197 LoS = DAG.getNode(ISD::OR, dl, NVT,
1198 DAG.getNode(ISD::SRL, dl, NVT, InL, Amt),
1199 // FIXME: If Amt is zero, the following shift generates an undefined result
1200 // on some architectures.
1201 DAG.getNode(ISD::SHL, dl, NVT, InH, AmtLack));
1203 // Long: ShAmt >= NVTBits
1204 HiL = DAG.getConstant(0, NVT); // Hi part is zero.
1205 LoL = DAG.getNode(ISD::SRL, dl, NVT, InH, AmtExcess); // Lo from Hi part.
1207 Lo = DAG.getNode(ISD::SELECT, dl, NVT, isShort, LoS, LoL);
1208 Hi = DAG.getNode(ISD::SELECT, dl, NVT, isShort, HiS, HiL);
1211 // Short: ShAmt < NVTBits
1212 HiS = DAG.getNode(ISD::SRA, dl, NVT, InH, Amt);
1213 LoS = DAG.getNode(ISD::OR, dl, NVT,
1214 DAG.getNode(ISD::SRL, dl, NVT, InL, Amt),
1215 // FIXME: If Amt is zero, the following shift generates an undefined result
1216 // on some architectures.
1217 DAG.getNode(ISD::SHL, dl, NVT, InH, AmtLack));
1219 // Long: ShAmt >= NVTBits
1220 HiL = DAG.getNode(ISD::SRA, dl, NVT, InH, // Sign of Hi part.
1221 DAG.getConstant(NVTBits-1, ShTy));
1222 LoL = DAG.getNode(ISD::SRA, dl, NVT, InH, AmtExcess); // Lo from Hi part.
1224 Lo = DAG.getNode(ISD::SELECT, dl, NVT, isShort, LoS, LoL);
1225 Hi = DAG.getNode(ISD::SELECT, dl, NVT, isShort, HiS, HiL);
1232 void DAGTypeLegalizer::ExpandIntRes_ADDSUB(SDNode *N,
1233 SDValue &Lo, SDValue &Hi) {
1234 DebugLoc dl = N->getDebugLoc();
1235 // Expand the subcomponents.
1236 SDValue LHSL, LHSH, RHSL, RHSH;
1237 GetExpandedInteger(N->getOperand(0), LHSL, LHSH);
1238 GetExpandedInteger(N->getOperand(1), RHSL, RHSH);
1240 EVT NVT = LHSL.getValueType();
1241 SDValue LoOps[2] = { LHSL, RHSL };
1242 SDValue HiOps[3] = { LHSH, RHSH };
1244 // Do not generate ADDC/ADDE or SUBC/SUBE if the target does not support
1245 // them. TODO: Teach operation legalization how to expand unsupported
1246 // ADDC/ADDE/SUBC/SUBE. The problem is that these operations generate
1247 // a carry of type MVT::Flag, but there doesn't seem to be any way to
1248 // generate a value of this type in the expanded code sequence.
1250 TLI.isOperationLegalOrCustom(N->getOpcode() == ISD::ADD ?
1251 ISD::ADDC : ISD::SUBC,
1252 TLI.getTypeToExpandTo(*DAG.getContext(), NVT));
1255 SDVTList VTList = DAG.getVTList(NVT, MVT::Flag);
1256 if (N->getOpcode() == ISD::ADD) {
1257 Lo = DAG.getNode(ISD::ADDC, dl, VTList, LoOps, 2);
1258 HiOps[2] = Lo.getValue(1);
1259 Hi = DAG.getNode(ISD::ADDE, dl, VTList, HiOps, 3);
1261 Lo = DAG.getNode(ISD::SUBC, dl, VTList, LoOps, 2);
1262 HiOps[2] = Lo.getValue(1);
1263 Hi = DAG.getNode(ISD::SUBE, dl, VTList, HiOps, 3);
1266 if (N->getOpcode() == ISD::ADD) {
1267 Lo = DAG.getNode(ISD::ADD, dl, NVT, LoOps, 2);
1268 Hi = DAG.getNode(ISD::ADD, dl, NVT, HiOps, 2);
1269 SDValue Cmp1 = DAG.getSetCC(dl, TLI.getSetCCResultType(NVT), Lo, LoOps[0],
1271 SDValue Carry1 = DAG.getNode(ISD::SELECT, dl, NVT, Cmp1,
1272 DAG.getConstant(1, NVT),
1273 DAG.getConstant(0, NVT));
1274 SDValue Cmp2 = DAG.getSetCC(dl, TLI.getSetCCResultType(NVT), Lo, LoOps[1],
1276 SDValue Carry2 = DAG.getNode(ISD::SELECT, dl, NVT, Cmp2,
1277 DAG.getConstant(1, NVT), Carry1);
1278 Hi = DAG.getNode(ISD::ADD, dl, NVT, Hi, Carry2);
1280 Lo = DAG.getNode(ISD::SUB, dl, NVT, LoOps, 2);
1281 Hi = DAG.getNode(ISD::SUB, dl, NVT, HiOps, 2);
1283 DAG.getSetCC(dl, TLI.getSetCCResultType(LoOps[0].getValueType()),
1284 LoOps[0], LoOps[1], ISD::SETULT);
1285 SDValue Borrow = DAG.getNode(ISD::SELECT, dl, NVT, Cmp,
1286 DAG.getConstant(1, NVT),
1287 DAG.getConstant(0, NVT));
1288 Hi = DAG.getNode(ISD::SUB, dl, NVT, Hi, Borrow);
1293 void DAGTypeLegalizer::ExpandIntRes_ADDSUBC(SDNode *N,
1294 SDValue &Lo, SDValue &Hi) {
1295 // Expand the subcomponents.
1296 SDValue LHSL, LHSH, RHSL, RHSH;
1297 DebugLoc dl = N->getDebugLoc();
1298 GetExpandedInteger(N->getOperand(0), LHSL, LHSH);
1299 GetExpandedInteger(N->getOperand(1), RHSL, RHSH);
1300 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag);
1301 SDValue LoOps[2] = { LHSL, RHSL };
1302 SDValue HiOps[3] = { LHSH, RHSH };
1304 if (N->getOpcode() == ISD::ADDC) {
1305 Lo = DAG.getNode(ISD::ADDC, dl, VTList, LoOps, 2);
1306 HiOps[2] = Lo.getValue(1);
1307 Hi = DAG.getNode(ISD::ADDE, dl, VTList, HiOps, 3);
1309 Lo = DAG.getNode(ISD::SUBC, dl, VTList, LoOps, 2);
1310 HiOps[2] = Lo.getValue(1);
1311 Hi = DAG.getNode(ISD::SUBE, dl, VTList, HiOps, 3);
1314 // Legalized the flag result - switch anything that used the old flag to
1316 ReplaceValueWith(SDValue(N, 1), Hi.getValue(1));
1319 void DAGTypeLegalizer::ExpandIntRes_ADDSUBE(SDNode *N,
1320 SDValue &Lo, SDValue &Hi) {
1321 // Expand the subcomponents.
1322 SDValue LHSL, LHSH, RHSL, RHSH;
1323 DebugLoc dl = N->getDebugLoc();
1324 GetExpandedInteger(N->getOperand(0), LHSL, LHSH);
1325 GetExpandedInteger(N->getOperand(1), RHSL, RHSH);
1326 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag);
1327 SDValue LoOps[3] = { LHSL, RHSL, N->getOperand(2) };
1328 SDValue HiOps[3] = { LHSH, RHSH };
1330 Lo = DAG.getNode(N->getOpcode(), dl, VTList, LoOps, 3);
1331 HiOps[2] = Lo.getValue(1);
1332 Hi = DAG.getNode(N->getOpcode(), dl, VTList, HiOps, 3);
1334 // Legalized the flag result - switch anything that used the old flag to
1336 ReplaceValueWith(SDValue(N, 1), Hi.getValue(1));
1339 void DAGTypeLegalizer::ExpandIntRes_ANY_EXTEND(SDNode *N,
1340 SDValue &Lo, SDValue &Hi) {
1341 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1342 DebugLoc dl = N->getDebugLoc();
1343 SDValue Op = N->getOperand(0);
1344 if (Op.getValueType().bitsLE(NVT)) {
1345 // The low part is any extension of the input (which degenerates to a copy).
1346 Lo = DAG.getNode(ISD::ANY_EXTEND, dl, NVT, Op);
1347 Hi = DAG.getUNDEF(NVT); // The high part is undefined.
1349 // For example, extension of an i48 to an i64. The operand type necessarily
1350 // promotes to the result type, so will end up being expanded too.
1351 assert(getTypeAction(Op.getValueType()) == PromoteInteger &&
1352 "Only know how to promote this result!");
1353 SDValue Res = GetPromotedInteger(Op);
1354 assert(Res.getValueType() == N->getValueType(0) &&
1355 "Operand over promoted?");
1356 // Split the promoted operand. This will simplify when it is expanded.
1357 SplitInteger(Res, Lo, Hi);
1361 void DAGTypeLegalizer::ExpandIntRes_AssertSext(SDNode *N,
1362 SDValue &Lo, SDValue &Hi) {
1363 DebugLoc dl = N->getDebugLoc();
1364 GetExpandedInteger(N->getOperand(0), Lo, Hi);
1365 EVT NVT = Lo.getValueType();
1366 EVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
1367 unsigned NVTBits = NVT.getSizeInBits();
1368 unsigned EVTBits = EVT.getSizeInBits();
1370 if (NVTBits < EVTBits) {
1371 Hi = DAG.getNode(ISD::AssertSext, dl, NVT, Hi,
1372 DAG.getValueType(EVT::getIntegerVT(*DAG.getContext(), EVTBits - NVTBits)));
1374 Lo = DAG.getNode(ISD::AssertSext, dl, NVT, Lo, DAG.getValueType(EVT));
1375 // The high part replicates the sign bit of Lo, make it explicit.
1376 Hi = DAG.getNode(ISD::SRA, dl, NVT, Lo,
1377 DAG.getConstant(NVTBits-1, TLI.getPointerTy()));
1381 void DAGTypeLegalizer::ExpandIntRes_AssertZext(SDNode *N,
1382 SDValue &Lo, SDValue &Hi) {
1383 DebugLoc dl = N->getDebugLoc();
1384 GetExpandedInteger(N->getOperand(0), Lo, Hi);
1385 EVT NVT = Lo.getValueType();
1386 EVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
1387 unsigned NVTBits = NVT.getSizeInBits();
1388 unsigned EVTBits = EVT.getSizeInBits();
1390 if (NVTBits < EVTBits) {
1391 Hi = DAG.getNode(ISD::AssertZext, dl, NVT, Hi,
1392 DAG.getValueType(EVT::getIntegerVT(*DAG.getContext(), EVTBits - NVTBits)));
1394 Lo = DAG.getNode(ISD::AssertZext, dl, NVT, Lo, DAG.getValueType(EVT));
1395 // The high part must be zero, make it explicit.
1396 Hi = DAG.getConstant(0, NVT);
1400 void DAGTypeLegalizer::ExpandIntRes_BSWAP(SDNode *N,
1401 SDValue &Lo, SDValue &Hi) {
1402 DebugLoc dl = N->getDebugLoc();
1403 GetExpandedInteger(N->getOperand(0), Hi, Lo); // Note swapped operands.
1404 Lo = DAG.getNode(ISD::BSWAP, dl, Lo.getValueType(), Lo);
1405 Hi = DAG.getNode(ISD::BSWAP, dl, Hi.getValueType(), Hi);
1408 void DAGTypeLegalizer::ExpandIntRes_Constant(SDNode *N,
1409 SDValue &Lo, SDValue &Hi) {
1410 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1411 unsigned NBitWidth = NVT.getSizeInBits();
1412 const APInt &Cst = cast<ConstantSDNode>(N)->getAPIntValue();
1413 Lo = DAG.getConstant(APInt(Cst).trunc(NBitWidth), NVT);
1414 Hi = DAG.getConstant(Cst.lshr(NBitWidth).trunc(NBitWidth), NVT);
1417 void DAGTypeLegalizer::ExpandIntRes_CTLZ(SDNode *N,
1418 SDValue &Lo, SDValue &Hi) {
1419 DebugLoc dl = N->getDebugLoc();
1420 // ctlz (HiLo) -> Hi != 0 ? ctlz(Hi) : (ctlz(Lo)+32)
1421 GetExpandedInteger(N->getOperand(0), Lo, Hi);
1422 EVT NVT = Lo.getValueType();
1424 SDValue HiNotZero = DAG.getSetCC(dl, TLI.getSetCCResultType(NVT), Hi,
1425 DAG.getConstant(0, NVT), ISD::SETNE);
1427 SDValue LoLZ = DAG.getNode(ISD::CTLZ, dl, NVT, Lo);
1428 SDValue HiLZ = DAG.getNode(ISD::CTLZ, dl, NVT, Hi);
1430 Lo = DAG.getNode(ISD::SELECT, dl, NVT, HiNotZero, HiLZ,
1431 DAG.getNode(ISD::ADD, dl, NVT, LoLZ,
1432 DAG.getConstant(NVT.getSizeInBits(), NVT)));
1433 Hi = DAG.getConstant(0, NVT);
1436 void DAGTypeLegalizer::ExpandIntRes_CTPOP(SDNode *N,
1437 SDValue &Lo, SDValue &Hi) {
1438 DebugLoc dl = N->getDebugLoc();
1439 // ctpop(HiLo) -> ctpop(Hi)+ctpop(Lo)
1440 GetExpandedInteger(N->getOperand(0), Lo, Hi);
1441 EVT NVT = Lo.getValueType();
1442 Lo = DAG.getNode(ISD::ADD, dl, NVT, DAG.getNode(ISD::CTPOP, dl, NVT, Lo),
1443 DAG.getNode(ISD::CTPOP, dl, NVT, Hi));
1444 Hi = DAG.getConstant(0, NVT);
1447 void DAGTypeLegalizer::ExpandIntRes_CTTZ(SDNode *N,
1448 SDValue &Lo, SDValue &Hi) {
1449 DebugLoc dl = N->getDebugLoc();
1450 // cttz (HiLo) -> Lo != 0 ? cttz(Lo) : (cttz(Hi)+32)
1451 GetExpandedInteger(N->getOperand(0), Lo, Hi);
1452 EVT NVT = Lo.getValueType();
1454 SDValue LoNotZero = DAG.getSetCC(dl, TLI.getSetCCResultType(NVT), Lo,
1455 DAG.getConstant(0, NVT), ISD::SETNE);
1457 SDValue LoLZ = DAG.getNode(ISD::CTTZ, dl, NVT, Lo);
1458 SDValue HiLZ = DAG.getNode(ISD::CTTZ, dl, NVT, Hi);
1460 Lo = DAG.getNode(ISD::SELECT, dl, NVT, LoNotZero, LoLZ,
1461 DAG.getNode(ISD::ADD, dl, NVT, HiLZ,
1462 DAG.getConstant(NVT.getSizeInBits(), NVT)));
1463 Hi = DAG.getConstant(0, NVT);
1466 void DAGTypeLegalizer::ExpandIntRes_FP_TO_SINT(SDNode *N, SDValue &Lo,
1468 DebugLoc dl = N->getDebugLoc();
1469 EVT VT = N->getValueType(0);
1470 SDValue Op = N->getOperand(0);
1471 RTLIB::Libcall LC = RTLIB::getFPTOSINT(Op.getValueType(), VT);
1472 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected fp-to-sint conversion!");
1473 SplitInteger(MakeLibCall(LC, VT, &Op, 1, true/*irrelevant*/, dl), Lo, Hi);
1476 void DAGTypeLegalizer::ExpandIntRes_FP_TO_UINT(SDNode *N, SDValue &Lo,
1478 DebugLoc dl = N->getDebugLoc();
1479 EVT VT = N->getValueType(0);
1480 SDValue Op = N->getOperand(0);
1481 RTLIB::Libcall LC = RTLIB::getFPTOUINT(Op.getValueType(), VT);
1482 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected fp-to-uint conversion!");
1483 SplitInteger(MakeLibCall(LC, VT, &Op, 1, false/*irrelevant*/, dl), Lo, Hi);
1486 void DAGTypeLegalizer::ExpandIntRes_LOAD(LoadSDNode *N,
1487 SDValue &Lo, SDValue &Hi) {
1488 if (ISD::isNormalLoad(N)) {
1489 ExpandRes_NormalLoad(N, Lo, Hi);
1493 assert(ISD::isUNINDEXEDLoad(N) && "Indexed load during type legalization!");
1495 EVT VT = N->getValueType(0);
1496 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
1497 SDValue Ch = N->getChain();
1498 SDValue Ptr = N->getBasePtr();
1499 ISD::LoadExtType ExtType = N->getExtensionType();
1500 int SVOffset = N->getSrcValueOffset();
1501 unsigned Alignment = N->getAlignment();
1502 bool isVolatile = N->isVolatile();
1503 DebugLoc dl = N->getDebugLoc();
1505 assert(NVT.isByteSized() && "Expanded type not byte sized!");
1507 if (N->getMemoryVT().bitsLE(NVT)) {
1508 EVT MemVT = N->getMemoryVT();
1510 Lo = DAG.getExtLoad(ExtType, dl, NVT, Ch, Ptr, N->getSrcValue(), SVOffset,
1511 MemVT, isVolatile, Alignment);
1513 // Remember the chain.
1514 Ch = Lo.getValue(1);
1516 if (ExtType == ISD::SEXTLOAD) {
1517 // The high part is obtained by SRA'ing all but one of the bits of the
1519 unsigned LoSize = Lo.getValueType().getSizeInBits();
1520 Hi = DAG.getNode(ISD::SRA, dl, NVT, Lo,
1521 DAG.getConstant(LoSize-1, TLI.getPointerTy()));
1522 } else if (ExtType == ISD::ZEXTLOAD) {
1523 // The high part is just a zero.
1524 Hi = DAG.getConstant(0, NVT);
1526 assert(ExtType == ISD::EXTLOAD && "Unknown extload!");
1527 // The high part is undefined.
1528 Hi = DAG.getUNDEF(NVT);
1530 } else if (TLI.isLittleEndian()) {
1531 // Little-endian - low bits are at low addresses.
1532 Lo = DAG.getLoad(NVT, dl, Ch, Ptr, N->getSrcValue(), SVOffset,
1533 isVolatile, Alignment);
1535 unsigned ExcessBits =
1536 N->getMemoryVT().getSizeInBits() - NVT.getSizeInBits();
1537 EVT NEVT = EVT::getIntegerVT(*DAG.getContext(), ExcessBits);
1539 // Increment the pointer to the other half.
1540 unsigned IncrementSize = NVT.getSizeInBits()/8;
1541 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
1542 DAG.getIntPtrConstant(IncrementSize));
1543 Hi = DAG.getExtLoad(ExtType, dl, NVT, Ch, Ptr, N->getSrcValue(),
1544 SVOffset+IncrementSize, NEVT,
1545 isVolatile, MinAlign(Alignment, IncrementSize));
1547 // Build a factor node to remember that this load is independent of the
1549 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
1552 // Big-endian - high bits are at low addresses. Favor aligned loads at
1553 // the cost of some bit-fiddling.
1554 EVT MemVT = N->getMemoryVT();
1555 unsigned EBytes = MemVT.getStoreSize();
1556 unsigned IncrementSize = NVT.getSizeInBits()/8;
1557 unsigned ExcessBits = (EBytes - IncrementSize)*8;
1559 // Load both the high bits and maybe some of the low bits.
1560 Hi = DAG.getExtLoad(ExtType, dl, NVT, Ch, Ptr, N->getSrcValue(), SVOffset,
1561 EVT::getIntegerVT(*DAG.getContext(),
1562 MemVT.getSizeInBits() - ExcessBits),
1563 isVolatile, Alignment);
1565 // Increment the pointer to the other half.
1566 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
1567 DAG.getIntPtrConstant(IncrementSize));
1568 // Load the rest of the low bits.
1569 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, NVT, Ch, Ptr, N->getSrcValue(),
1570 SVOffset+IncrementSize,
1571 EVT::getIntegerVT(*DAG.getContext(), ExcessBits),
1572 isVolatile, MinAlign(Alignment, IncrementSize));
1574 // Build a factor node to remember that this load is independent of the
1576 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
1579 if (ExcessBits < NVT.getSizeInBits()) {
1580 // Transfer low bits from the bottom of Hi to the top of Lo.
1581 Lo = DAG.getNode(ISD::OR, dl, NVT, Lo,
1582 DAG.getNode(ISD::SHL, dl, NVT, Hi,
1583 DAG.getConstant(ExcessBits,
1584 TLI.getPointerTy())));
1585 // Move high bits to the right position in Hi.
1586 Hi = DAG.getNode(ExtType == ISD::SEXTLOAD ? ISD::SRA : ISD::SRL, dl,
1588 DAG.getConstant(NVT.getSizeInBits() - ExcessBits,
1589 TLI.getPointerTy()));
1593 // Legalized the chain result - switch anything that used the old chain to
1595 ReplaceValueWith(SDValue(N, 1), Ch);
1598 void DAGTypeLegalizer::ExpandIntRes_Logical(SDNode *N,
1599 SDValue &Lo, SDValue &Hi) {
1600 DebugLoc dl = N->getDebugLoc();
1601 SDValue LL, LH, RL, RH;
1602 GetExpandedInteger(N->getOperand(0), LL, LH);
1603 GetExpandedInteger(N->getOperand(1), RL, RH);
1604 Lo = DAG.getNode(N->getOpcode(), dl, LL.getValueType(), LL, RL);
1605 Hi = DAG.getNode(N->getOpcode(), dl, LL.getValueType(), LH, RH);
1608 void DAGTypeLegalizer::ExpandIntRes_MUL(SDNode *N,
1609 SDValue &Lo, SDValue &Hi) {
1610 EVT VT = N->getValueType(0);
1611 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
1612 DebugLoc dl = N->getDebugLoc();
1614 bool HasMULHS = TLI.isOperationLegalOrCustom(ISD::MULHS, NVT);
1615 bool HasMULHU = TLI.isOperationLegalOrCustom(ISD::MULHU, NVT);
1616 bool HasSMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::SMUL_LOHI, NVT);
1617 bool HasUMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::UMUL_LOHI, NVT);
1618 if (HasMULHU || HasMULHS || HasUMUL_LOHI || HasSMUL_LOHI) {
1619 SDValue LL, LH, RL, RH;
1620 GetExpandedInteger(N->getOperand(0), LL, LH);
1621 GetExpandedInteger(N->getOperand(1), RL, RH);
1622 unsigned OuterBitSize = VT.getSizeInBits();
1623 unsigned InnerBitSize = NVT.getSizeInBits();
1624 unsigned LHSSB = DAG.ComputeNumSignBits(N->getOperand(0));
1625 unsigned RHSSB = DAG.ComputeNumSignBits(N->getOperand(1));
1627 APInt HighMask = APInt::getHighBitsSet(OuterBitSize, InnerBitSize);
1628 if (DAG.MaskedValueIsZero(N->getOperand(0), HighMask) &&
1629 DAG.MaskedValueIsZero(N->getOperand(1), HighMask)) {
1630 // The inputs are both zero-extended.
1632 // We can emit a umul_lohi.
1633 Lo = DAG.getNode(ISD::UMUL_LOHI, dl, DAG.getVTList(NVT, NVT), LL, RL);
1634 Hi = SDValue(Lo.getNode(), 1);
1638 // We can emit a mulhu+mul.
1639 Lo = DAG.getNode(ISD::MUL, dl, NVT, LL, RL);
1640 Hi = DAG.getNode(ISD::MULHU, dl, NVT, LL, RL);
1644 if (LHSSB > InnerBitSize && RHSSB > InnerBitSize) {
1645 // The input values are both sign-extended.
1647 // We can emit a smul_lohi.
1648 Lo = DAG.getNode(ISD::SMUL_LOHI, dl, DAG.getVTList(NVT, NVT), LL, RL);
1649 Hi = SDValue(Lo.getNode(), 1);
1653 // We can emit a mulhs+mul.
1654 Lo = DAG.getNode(ISD::MUL, dl, NVT, LL, RL);
1655 Hi = DAG.getNode(ISD::MULHS, dl, NVT, LL, RL);
1660 // Lo,Hi = umul LHS, RHS.
1661 SDValue UMulLOHI = DAG.getNode(ISD::UMUL_LOHI, dl,
1662 DAG.getVTList(NVT, NVT), LL, RL);
1664 Hi = UMulLOHI.getValue(1);
1665 RH = DAG.getNode(ISD::MUL, dl, NVT, LL, RH);
1666 LH = DAG.getNode(ISD::MUL, dl, NVT, LH, RL);
1667 Hi = DAG.getNode(ISD::ADD, dl, NVT, Hi, RH);
1668 Hi = DAG.getNode(ISD::ADD, dl, NVT, Hi, LH);
1672 Lo = DAG.getNode(ISD::MUL, dl, NVT, LL, RL);
1673 Hi = DAG.getNode(ISD::MULHU, dl, NVT, LL, RL);
1674 RH = DAG.getNode(ISD::MUL, dl, NVT, LL, RH);
1675 LH = DAG.getNode(ISD::MUL, dl, NVT, LH, RL);
1676 Hi = DAG.getNode(ISD::ADD, dl, NVT, Hi, RH);
1677 Hi = DAG.getNode(ISD::ADD, dl, NVT, Hi, LH);
1682 // If nothing else, we can make a libcall.
1683 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
1685 LC = RTLIB::MUL_I16;
1686 else if (VT == MVT::i32)
1687 LC = RTLIB::MUL_I32;
1688 else if (VT == MVT::i64)
1689 LC = RTLIB::MUL_I64;
1690 else if (VT == MVT::i128)
1691 LC = RTLIB::MUL_I128;
1692 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported MUL!");
1694 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
1695 SplitInteger(MakeLibCall(LC, VT, Ops, 2, true/*irrelevant*/, dl), Lo, Hi);
1698 void DAGTypeLegalizer::ExpandIntRes_SDIV(SDNode *N,
1699 SDValue &Lo, SDValue &Hi) {
1700 EVT VT = N->getValueType(0);
1701 DebugLoc dl = N->getDebugLoc();
1703 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
1705 LC = RTLIB::SDIV_I16;
1706 else if (VT == MVT::i32)
1707 LC = RTLIB::SDIV_I32;
1708 else if (VT == MVT::i64)
1709 LC = RTLIB::SDIV_I64;
1710 else if (VT == MVT::i128)
1711 LC = RTLIB::SDIV_I128;
1712 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported SDIV!");
1714 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
1715 SplitInteger(MakeLibCall(LC, VT, Ops, 2, true, dl), Lo, Hi);
1718 void DAGTypeLegalizer::ExpandIntRes_Shift(SDNode *N,
1719 SDValue &Lo, SDValue &Hi) {
1720 EVT VT = N->getValueType(0);
1721 DebugLoc dl = N->getDebugLoc();
1723 // If we can emit an efficient shift operation, do so now. Check to see if
1724 // the RHS is a constant.
1725 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N->getOperand(1)))
1726 return ExpandShiftByConstant(N, CN->getZExtValue(), Lo, Hi);
1728 // If we can determine that the high bit of the shift is zero or one, even if
1729 // the low bits are variable, emit this shift in an optimized form.
1730 if (ExpandShiftWithKnownAmountBit(N, Lo, Hi))
1733 // If this target supports shift_PARTS, use it. First, map to the _PARTS opc.
1735 if (N->getOpcode() == ISD::SHL) {
1736 PartsOpc = ISD::SHL_PARTS;
1737 } else if (N->getOpcode() == ISD::SRL) {
1738 PartsOpc = ISD::SRL_PARTS;
1740 assert(N->getOpcode() == ISD::SRA && "Unknown shift!");
1741 PartsOpc = ISD::SRA_PARTS;
1744 // Next check to see if the target supports this SHL_PARTS operation or if it
1745 // will custom expand it.
1746 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
1747 TargetLowering::LegalizeAction Action = TLI.getOperationAction(PartsOpc, NVT);
1748 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) ||
1749 Action == TargetLowering::Custom) {
1750 // Expand the subcomponents.
1752 GetExpandedInteger(N->getOperand(0), LHSL, LHSH);
1754 SDValue Ops[] = { LHSL, LHSH, N->getOperand(1) };
1755 EVT VT = LHSL.getValueType();
1756 Lo = DAG.getNode(PartsOpc, dl, DAG.getVTList(VT, VT), Ops, 3);
1757 Hi = Lo.getValue(1);
1761 // Otherwise, emit a libcall.
1762 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
1764 if (N->getOpcode() == ISD::SHL) {
1765 isSigned = false; /*sign irrelevant*/
1767 LC = RTLIB::SHL_I16;
1768 else if (VT == MVT::i32)
1769 LC = RTLIB::SHL_I32;
1770 else if (VT == MVT::i64)
1771 LC = RTLIB::SHL_I64;
1772 else if (VT == MVT::i128)
1773 LC = RTLIB::SHL_I128;
1774 } else if (N->getOpcode() == ISD::SRL) {
1777 LC = RTLIB::SRL_I16;
1778 else if (VT == MVT::i32)
1779 LC = RTLIB::SRL_I32;
1780 else if (VT == MVT::i64)
1781 LC = RTLIB::SRL_I64;
1782 else if (VT == MVT::i128)
1783 LC = RTLIB::SRL_I128;
1785 assert(N->getOpcode() == ISD::SRA && "Unknown shift!");
1788 LC = RTLIB::SRA_I16;
1789 else if (VT == MVT::i32)
1790 LC = RTLIB::SRA_I32;
1791 else if (VT == MVT::i64)
1792 LC = RTLIB::SRA_I64;
1793 else if (VT == MVT::i128)
1794 LC = RTLIB::SRA_I128;
1797 if (LC != RTLIB::UNKNOWN_LIBCALL && TLI.getLibcallName(LC)) {
1798 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
1799 SplitInteger(MakeLibCall(LC, VT, Ops, 2, isSigned, dl), Lo, Hi);
1803 if (!ExpandShiftWithUnknownAmountBit(N, Lo, Hi))
1804 llvm_unreachable("Unsupported shift!");
1807 void DAGTypeLegalizer::ExpandIntRes_SIGN_EXTEND(SDNode *N,
1808 SDValue &Lo, SDValue &Hi) {
1809 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1810 DebugLoc dl = N->getDebugLoc();
1811 SDValue Op = N->getOperand(0);
1812 if (Op.getValueType().bitsLE(NVT)) {
1813 // The low part is sign extension of the input (degenerates to a copy).
1814 Lo = DAG.getNode(ISD::SIGN_EXTEND, dl, NVT, N->getOperand(0));
1815 // The high part is obtained by SRA'ing all but one of the bits of low part.
1816 unsigned LoSize = NVT.getSizeInBits();
1817 Hi = DAG.getNode(ISD::SRA, dl, NVT, Lo,
1818 DAG.getConstant(LoSize-1, TLI.getPointerTy()));
1820 // For example, extension of an i48 to an i64. The operand type necessarily
1821 // promotes to the result type, so will end up being expanded too.
1822 assert(getTypeAction(Op.getValueType()) == PromoteInteger &&
1823 "Only know how to promote this result!");
1824 SDValue Res = GetPromotedInteger(Op);
1825 assert(Res.getValueType() == N->getValueType(0) &&
1826 "Operand over promoted?");
1827 // Split the promoted operand. This will simplify when it is expanded.
1828 SplitInteger(Res, Lo, Hi);
1829 unsigned ExcessBits =
1830 Op.getValueType().getSizeInBits() - NVT.getSizeInBits();
1831 Hi = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Hi.getValueType(), Hi,
1832 DAG.getValueType(EVT::getIntegerVT(*DAG.getContext(), ExcessBits)));
1836 void DAGTypeLegalizer::
1837 ExpandIntRes_SIGN_EXTEND_INREG(SDNode *N, SDValue &Lo, SDValue &Hi) {
1838 DebugLoc dl = N->getDebugLoc();
1839 GetExpandedInteger(N->getOperand(0), Lo, Hi);
1840 EVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
1842 if (EVT.bitsLE(Lo.getValueType())) {
1843 // sext_inreg the low part if needed.
1844 Lo = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Lo.getValueType(), Lo,
1847 // The high part gets the sign extension from the lo-part. This handles
1848 // things like sextinreg V:i64 from i8.
1849 Hi = DAG.getNode(ISD::SRA, dl, Hi.getValueType(), Lo,
1850 DAG.getConstant(Hi.getValueType().getSizeInBits()-1,
1851 TLI.getPointerTy()));
1853 // For example, extension of an i48 to an i64. Leave the low part alone,
1854 // sext_inreg the high part.
1855 unsigned ExcessBits =
1856 EVT.getSizeInBits() - Lo.getValueType().getSizeInBits();
1857 Hi = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Hi.getValueType(), Hi,
1858 DAG.getValueType(EVT::getIntegerVT(*DAG.getContext(), ExcessBits)));
1862 void DAGTypeLegalizer::ExpandIntRes_SREM(SDNode *N,
1863 SDValue &Lo, SDValue &Hi) {
1864 EVT VT = N->getValueType(0);
1865 DebugLoc dl = N->getDebugLoc();
1867 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
1869 LC = RTLIB::SREM_I16;
1870 else if (VT == MVT::i32)
1871 LC = RTLIB::SREM_I32;
1872 else if (VT == MVT::i64)
1873 LC = RTLIB::SREM_I64;
1874 else if (VT == MVT::i128)
1875 LC = RTLIB::SREM_I128;
1876 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported SREM!");
1878 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
1879 SplitInteger(MakeLibCall(LC, VT, Ops, 2, true, dl), Lo, Hi);
1882 void DAGTypeLegalizer::ExpandIntRes_TRUNCATE(SDNode *N,
1883 SDValue &Lo, SDValue &Hi) {
1884 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1885 DebugLoc dl = N->getDebugLoc();
1886 Lo = DAG.getNode(ISD::TRUNCATE, dl, NVT, N->getOperand(0));
1887 Hi = DAG.getNode(ISD::SRL, dl,
1888 N->getOperand(0).getValueType(), N->getOperand(0),
1889 DAG.getConstant(NVT.getSizeInBits(), TLI.getPointerTy()));
1890 Hi = DAG.getNode(ISD::TRUNCATE, dl, NVT, Hi);
1893 void DAGTypeLegalizer::ExpandIntRes_UDIV(SDNode *N,
1894 SDValue &Lo, SDValue &Hi) {
1895 EVT VT = N->getValueType(0);
1896 DebugLoc dl = N->getDebugLoc();
1898 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
1900 LC = RTLIB::UDIV_I16;
1901 else if (VT == MVT::i32)
1902 LC = RTLIB::UDIV_I32;
1903 else if (VT == MVT::i64)
1904 LC = RTLIB::UDIV_I64;
1905 else if (VT == MVT::i128)
1906 LC = RTLIB::UDIV_I128;
1907 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported UDIV!");
1909 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
1910 SplitInteger(MakeLibCall(LC, VT, Ops, 2, false, dl), Lo, Hi);
1913 void DAGTypeLegalizer::ExpandIntRes_UREM(SDNode *N,
1914 SDValue &Lo, SDValue &Hi) {
1915 EVT VT = N->getValueType(0);
1916 DebugLoc dl = N->getDebugLoc();
1918 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
1920 LC = RTLIB::UREM_I16;
1921 else if (VT == MVT::i32)
1922 LC = RTLIB::UREM_I32;
1923 else if (VT == MVT::i64)
1924 LC = RTLIB::UREM_I64;
1925 else if (VT == MVT::i128)
1926 LC = RTLIB::UREM_I128;
1927 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported UREM!");
1929 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
1930 SplitInteger(MakeLibCall(LC, VT, Ops, 2, false, dl), Lo, Hi);
1933 void DAGTypeLegalizer::ExpandIntRes_ZERO_EXTEND(SDNode *N,
1934 SDValue &Lo, SDValue &Hi) {
1935 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1936 DebugLoc dl = N->getDebugLoc();
1937 SDValue Op = N->getOperand(0);
1938 if (Op.getValueType().bitsLE(NVT)) {
1939 // The low part is zero extension of the input (degenerates to a copy).
1940 Lo = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, N->getOperand(0));
1941 Hi = DAG.getConstant(0, NVT); // The high part is just a zero.
1943 // For example, extension of an i48 to an i64. The operand type necessarily
1944 // promotes to the result type, so will end up being expanded too.
1945 assert(getTypeAction(Op.getValueType()) == PromoteInteger &&
1946 "Only know how to promote this result!");
1947 SDValue Res = GetPromotedInteger(Op);
1948 assert(Res.getValueType() == N->getValueType(0) &&
1949 "Operand over promoted?");
1950 // Split the promoted operand. This will simplify when it is expanded.
1951 SplitInteger(Res, Lo, Hi);
1952 unsigned ExcessBits =
1953 Op.getValueType().getSizeInBits() - NVT.getSizeInBits();
1954 Hi = DAG.getZeroExtendInReg(Hi, dl, EVT::getIntegerVT(*DAG.getContext(), ExcessBits));
1959 //===----------------------------------------------------------------------===//
1960 // Integer Operand Expansion
1961 //===----------------------------------------------------------------------===//
1963 /// ExpandIntegerOperand - This method is called when the specified operand of
1964 /// the specified node is found to need expansion. At this point, all of the
1965 /// result types of the node are known to be legal, but other operands of the
1966 /// node may need promotion or expansion as well as the specified one.
1967 bool DAGTypeLegalizer::ExpandIntegerOperand(SDNode *N, unsigned OpNo) {
1968 DEBUG(errs() << "Expand integer operand: "; N->dump(&DAG); errs() << "\n");
1969 SDValue Res = SDValue();
1971 if (CustomLowerNode(N, N->getOperand(OpNo).getValueType(), false))
1974 switch (N->getOpcode()) {
1977 errs() << "ExpandIntegerOperand Op #" << OpNo << ": ";
1978 N->dump(&DAG); errs() << "\n";
1980 llvm_unreachable("Do not know how to expand this operator's operand!");
1982 case ISD::BIT_CONVERT: Res = ExpandOp_BIT_CONVERT(N); break;
1983 case ISD::BR_CC: Res = ExpandIntOp_BR_CC(N); break;
1984 case ISD::BUILD_VECTOR: Res = ExpandOp_BUILD_VECTOR(N); break;
1985 case ISD::EXTRACT_ELEMENT: Res = ExpandOp_EXTRACT_ELEMENT(N); break;
1986 case ISD::INSERT_VECTOR_ELT: Res = ExpandOp_INSERT_VECTOR_ELT(N); break;
1987 case ISD::SCALAR_TO_VECTOR: Res = ExpandOp_SCALAR_TO_VECTOR(N); break;
1988 case ISD::SELECT_CC: Res = ExpandIntOp_SELECT_CC(N); break;
1989 case ISD::SETCC: Res = ExpandIntOp_SETCC(N); break;
1990 case ISD::SINT_TO_FP: Res = ExpandIntOp_SINT_TO_FP(N); break;
1991 case ISD::STORE: Res = ExpandIntOp_STORE(cast<StoreSDNode>(N), OpNo); break;
1992 case ISD::TRUNCATE: Res = ExpandIntOp_TRUNCATE(N); break;
1993 case ISD::UINT_TO_FP: Res = ExpandIntOp_UINT_TO_FP(N); break;
1999 case ISD::ROTR: Res = ExpandIntOp_Shift(N); break;
2000 case ISD::RETURNADDR:
2001 case ISD::FRAMEADDR: Res = ExpandIntOp_RETURNADDR(N); break;
2004 // If the result is null, the sub-method took care of registering results etc.
2005 if (!Res.getNode()) return false;
2007 // If the result is N, the sub-method updated N in place. Tell the legalizer
2009 if (Res.getNode() == N)
2012 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 &&
2013 "Invalid operand expansion");
2015 ReplaceValueWith(SDValue(N, 0), Res);
2019 /// IntegerExpandSetCCOperands - Expand the operands of a comparison. This code
2020 /// is shared among BR_CC, SELECT_CC, and SETCC handlers.
2021 void DAGTypeLegalizer::IntegerExpandSetCCOperands(SDValue &NewLHS,
2023 ISD::CondCode &CCCode,
2025 SDValue LHSLo, LHSHi, RHSLo, RHSHi;
2026 GetExpandedInteger(NewLHS, LHSLo, LHSHi);
2027 GetExpandedInteger(NewRHS, RHSLo, RHSHi);
2029 if (CCCode == ISD::SETEQ || CCCode == ISD::SETNE) {
2030 if (RHSLo == RHSHi) {
2031 if (ConstantSDNode *RHSCST = dyn_cast<ConstantSDNode>(RHSLo)) {
2032 if (RHSCST->isAllOnesValue()) {
2033 // Equality comparison to -1.
2034 NewLHS = DAG.getNode(ISD::AND, dl,
2035 LHSLo.getValueType(), LHSLo, LHSHi);
2042 NewLHS = DAG.getNode(ISD::XOR, dl, LHSLo.getValueType(), LHSLo, RHSLo);
2043 NewRHS = DAG.getNode(ISD::XOR, dl, LHSLo.getValueType(), LHSHi, RHSHi);
2044 NewLHS = DAG.getNode(ISD::OR, dl, NewLHS.getValueType(), NewLHS, NewRHS);
2045 NewRHS = DAG.getConstant(0, NewLHS.getValueType());
2049 // If this is a comparison of the sign bit, just look at the top part.
2051 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(NewRHS))
2052 if ((CCCode == ISD::SETLT && CST->isNullValue()) || // X < 0
2053 (CCCode == ISD::SETGT && CST->isAllOnesValue())) { // X > -1
2059 // FIXME: This generated code sucks.
2060 ISD::CondCode LowCC;
2062 default: llvm_unreachable("Unknown integer setcc!");
2064 case ISD::SETULT: LowCC = ISD::SETULT; break;
2066 case ISD::SETUGT: LowCC = ISD::SETUGT; break;
2068 case ISD::SETULE: LowCC = ISD::SETULE; break;
2070 case ISD::SETUGE: LowCC = ISD::SETUGE; break;
2073 // Tmp1 = lo(op1) < lo(op2) // Always unsigned comparison
2074 // Tmp2 = hi(op1) < hi(op2) // Signedness depends on operands
2075 // dest = hi(op1) == hi(op2) ? Tmp1 : Tmp2;
2077 // NOTE: on targets without efficient SELECT of bools, we can always use
2078 // this identity: (B1 ? B2 : B3) --> (B1 & B2)|(!B1&B3)
2079 TargetLowering::DAGCombinerInfo DagCombineInfo(DAG, false, true, true, NULL);
2081 Tmp1 = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSLo.getValueType()),
2082 LHSLo, RHSLo, LowCC, false, DagCombineInfo, dl);
2083 if (!Tmp1.getNode())
2084 Tmp1 = DAG.getSetCC(dl, TLI.getSetCCResultType(LHSLo.getValueType()),
2085 LHSLo, RHSLo, LowCC);
2086 Tmp2 = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSHi.getValueType()),
2087 LHSHi, RHSHi, CCCode, false, DagCombineInfo, dl);
2088 if (!Tmp2.getNode())
2089 Tmp2 = DAG.getNode(ISD::SETCC, dl,
2090 TLI.getSetCCResultType(LHSHi.getValueType()),
2091 LHSHi, RHSHi, DAG.getCondCode(CCCode));
2093 ConstantSDNode *Tmp1C = dyn_cast<ConstantSDNode>(Tmp1.getNode());
2094 ConstantSDNode *Tmp2C = dyn_cast<ConstantSDNode>(Tmp2.getNode());
2095 if ((Tmp1C && Tmp1C->isNullValue()) ||
2096 (Tmp2C && Tmp2C->isNullValue() &&
2097 (CCCode == ISD::SETLE || CCCode == ISD::SETGE ||
2098 CCCode == ISD::SETUGE || CCCode == ISD::SETULE)) ||
2099 (Tmp2C && Tmp2C->getAPIntValue() == 1 &&
2100 (CCCode == ISD::SETLT || CCCode == ISD::SETGT ||
2101 CCCode == ISD::SETUGT || CCCode == ISD::SETULT))) {
2102 // low part is known false, returns high part.
2103 // For LE / GE, if high part is known false, ignore the low part.
2104 // For LT / GT, if high part is known true, ignore the low part.
2110 NewLHS = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSHi.getValueType()),
2111 LHSHi, RHSHi, ISD::SETEQ, false,
2112 DagCombineInfo, dl);
2113 if (!NewLHS.getNode())
2114 NewLHS = DAG.getSetCC(dl, TLI.getSetCCResultType(LHSHi.getValueType()),
2115 LHSHi, RHSHi, ISD::SETEQ);
2116 NewLHS = DAG.getNode(ISD::SELECT, dl, Tmp1.getValueType(),
2117 NewLHS, Tmp1, Tmp2);
2121 SDValue DAGTypeLegalizer::ExpandIntOp_BR_CC(SDNode *N) {
2122 SDValue NewLHS = N->getOperand(2), NewRHS = N->getOperand(3);
2123 ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(1))->get();
2124 IntegerExpandSetCCOperands(NewLHS, NewRHS, CCCode, N->getDebugLoc());
2126 // If ExpandSetCCOperands returned a scalar, we need to compare the result
2127 // against zero to select between true and false values.
2128 if (NewRHS.getNode() == 0) {
2129 NewRHS = DAG.getConstant(0, NewLHS.getValueType());
2130 CCCode = ISD::SETNE;
2133 // Update N to have the operands specified.
2134 return DAG.UpdateNodeOperands(SDValue(N, 0), N->getOperand(0),
2135 DAG.getCondCode(CCCode), NewLHS, NewRHS,
2139 SDValue DAGTypeLegalizer::ExpandIntOp_SELECT_CC(SDNode *N) {
2140 SDValue NewLHS = N->getOperand(0), NewRHS = N->getOperand(1);
2141 ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(4))->get();
2142 IntegerExpandSetCCOperands(NewLHS, NewRHS, CCCode, N->getDebugLoc());
2144 // If ExpandSetCCOperands returned a scalar, we need to compare the result
2145 // against zero to select between true and false values.
2146 if (NewRHS.getNode() == 0) {
2147 NewRHS = DAG.getConstant(0, NewLHS.getValueType());
2148 CCCode = ISD::SETNE;
2151 // Update N to have the operands specified.
2152 return DAG.UpdateNodeOperands(SDValue(N, 0), NewLHS, NewRHS,
2153 N->getOperand(2), N->getOperand(3),
2154 DAG.getCondCode(CCCode));
2157 SDValue DAGTypeLegalizer::ExpandIntOp_SETCC(SDNode *N) {
2158 SDValue NewLHS = N->getOperand(0), NewRHS = N->getOperand(1);
2159 ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(2))->get();
2160 IntegerExpandSetCCOperands(NewLHS, NewRHS, CCCode, N->getDebugLoc());
2162 // If ExpandSetCCOperands returned a scalar, use it.
2163 if (NewRHS.getNode() == 0) {
2164 assert(NewLHS.getValueType() == N->getValueType(0) &&
2165 "Unexpected setcc expansion!");
2169 // Otherwise, update N to have the operands specified.
2170 return DAG.UpdateNodeOperands(SDValue(N, 0), NewLHS, NewRHS,
2171 DAG.getCondCode(CCCode));
2174 SDValue DAGTypeLegalizer::ExpandIntOp_Shift(SDNode *N) {
2175 // The value being shifted is legal, but the shift amount is too big.
2176 // It follows that either the result of the shift is undefined, or the
2177 // upper half of the shift amount is zero. Just use the lower half.
2179 GetExpandedInteger(N->getOperand(1), Lo, Hi);
2180 return DAG.UpdateNodeOperands(SDValue(N, 0), N->getOperand(0), Lo);
2183 SDValue DAGTypeLegalizer::ExpandIntOp_RETURNADDR(SDNode *N) {
2184 // The argument of RETURNADDR / FRAMEADDR builtin is 32 bit contant. This
2185 // surely makes pretty nice problems on 8/16 bit targets. Just truncate this
2186 // constant to valid type.
2188 GetExpandedInteger(N->getOperand(0), Lo, Hi);
2189 return DAG.UpdateNodeOperands(SDValue(N, 0), Lo);
2192 SDValue DAGTypeLegalizer::ExpandIntOp_SINT_TO_FP(SDNode *N) {
2193 SDValue Op = N->getOperand(0);
2194 EVT DstVT = N->getValueType(0);
2195 RTLIB::Libcall LC = RTLIB::getSINTTOFP(Op.getValueType(), DstVT);
2196 assert(LC != RTLIB::UNKNOWN_LIBCALL &&
2197 "Don't know how to expand this SINT_TO_FP!");
2198 return MakeLibCall(LC, DstVT, &Op, 1, true, N->getDebugLoc());
2201 SDValue DAGTypeLegalizer::ExpandIntOp_STORE(StoreSDNode *N, unsigned OpNo) {
2202 if (ISD::isNormalStore(N))
2203 return ExpandOp_NormalStore(N, OpNo);
2205 assert(ISD::isUNINDEXEDStore(N) && "Indexed store during type legalization!");
2206 assert(OpNo == 1 && "Can only expand the stored value so far");
2208 EVT VT = N->getOperand(1).getValueType();
2209 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
2210 SDValue Ch = N->getChain();
2211 SDValue Ptr = N->getBasePtr();
2212 int SVOffset = N->getSrcValueOffset();
2213 unsigned Alignment = N->getAlignment();
2214 bool isVolatile = N->isVolatile();
2215 DebugLoc dl = N->getDebugLoc();
2218 assert(NVT.isByteSized() && "Expanded type not byte sized!");
2220 if (N->getMemoryVT().bitsLE(NVT)) {
2221 GetExpandedInteger(N->getValue(), Lo, Hi);
2222 return DAG.getTruncStore(Ch, dl, Lo, Ptr, N->getSrcValue(), SVOffset,
2223 N->getMemoryVT(), isVolatile, Alignment);
2224 } else if (TLI.isLittleEndian()) {
2225 // Little-endian - low bits are at low addresses.
2226 GetExpandedInteger(N->getValue(), Lo, Hi);
2228 Lo = DAG.getStore(Ch, dl, Lo, Ptr, N->getSrcValue(), SVOffset,
2229 isVolatile, Alignment);
2231 unsigned ExcessBits =
2232 N->getMemoryVT().getSizeInBits() - NVT.getSizeInBits();
2233 EVT NEVT = EVT::getIntegerVT(*DAG.getContext(), ExcessBits);
2235 // Increment the pointer to the other half.
2236 unsigned IncrementSize = NVT.getSizeInBits()/8;
2237 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
2238 DAG.getIntPtrConstant(IncrementSize));
2239 Hi = DAG.getTruncStore(Ch, dl, Hi, Ptr, N->getSrcValue(),
2240 SVOffset+IncrementSize, NEVT,
2241 isVolatile, MinAlign(Alignment, IncrementSize));
2242 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi);
2244 // Big-endian - high bits are at low addresses. Favor aligned stores at
2245 // the cost of some bit-fiddling.
2246 GetExpandedInteger(N->getValue(), Lo, Hi);
2248 EVT ExtVT = N->getMemoryVT();
2249 unsigned EBytes = ExtVT.getStoreSize();
2250 unsigned IncrementSize = NVT.getSizeInBits()/8;
2251 unsigned ExcessBits = (EBytes - IncrementSize)*8;
2252 EVT HiVT = EVT::getIntegerVT(*DAG.getContext(), ExtVT.getSizeInBits() - ExcessBits);
2254 if (ExcessBits < NVT.getSizeInBits()) {
2255 // Transfer high bits from the top of Lo to the bottom of Hi.
2256 Hi = DAG.getNode(ISD::SHL, dl, NVT, Hi,
2257 DAG.getConstant(NVT.getSizeInBits() - ExcessBits,
2258 TLI.getPointerTy()));
2259 Hi = DAG.getNode(ISD::OR, dl, NVT, Hi,
2260 DAG.getNode(ISD::SRL, dl, NVT, Lo,
2261 DAG.getConstant(ExcessBits,
2262 TLI.getPointerTy())));
2265 // Store both the high bits and maybe some of the low bits.
2266 Hi = DAG.getTruncStore(Ch, dl, Hi, Ptr, N->getSrcValue(),
2267 SVOffset, HiVT, isVolatile, Alignment);
2269 // Increment the pointer to the other half.
2270 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
2271 DAG.getIntPtrConstant(IncrementSize));
2272 // Store the lowest ExcessBits bits in the second half.
2273 Lo = DAG.getTruncStore(Ch, dl, Lo, Ptr, N->getSrcValue(),
2274 SVOffset+IncrementSize,
2275 EVT::getIntegerVT(*DAG.getContext(), ExcessBits),
2276 isVolatile, MinAlign(Alignment, IncrementSize));
2277 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi);
2281 SDValue DAGTypeLegalizer::ExpandIntOp_TRUNCATE(SDNode *N) {
2283 GetExpandedInteger(N->getOperand(0), InL, InH);
2284 // Just truncate the low part of the source.
2285 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), N->getValueType(0), InL);
2288 SDValue DAGTypeLegalizer::ExpandIntOp_UINT_TO_FP(SDNode *N) {
2289 SDValue Op = N->getOperand(0);
2290 EVT SrcVT = Op.getValueType();
2291 EVT DstVT = N->getValueType(0);
2292 DebugLoc dl = N->getDebugLoc();
2294 if (TLI.getOperationAction(ISD::SINT_TO_FP, SrcVT) == TargetLowering::Custom){
2295 // Do a signed conversion then adjust the result.
2296 SDValue SignedConv = DAG.getNode(ISD::SINT_TO_FP, dl, DstVT, Op);
2297 SignedConv = TLI.LowerOperation(SignedConv, DAG);
2299 // The result of the signed conversion needs adjusting if the 'sign bit' of
2300 // the incoming integer was set. To handle this, we dynamically test to see
2301 // if it is set, and, if so, add a fudge factor.
2303 const uint64_t F32TwoE32 = 0x4F800000ULL;
2304 const uint64_t F32TwoE64 = 0x5F800000ULL;
2305 const uint64_t F32TwoE128 = 0x7F800000ULL;
2308 if (SrcVT == MVT::i32)
2309 FF = APInt(32, F32TwoE32);
2310 else if (SrcVT == MVT::i64)
2311 FF = APInt(32, F32TwoE64);
2312 else if (SrcVT == MVT::i128)
2313 FF = APInt(32, F32TwoE128);
2315 assert(false && "Unsupported UINT_TO_FP!");
2317 // Check whether the sign bit is set.
2319 GetExpandedInteger(Op, Lo, Hi);
2320 SDValue SignSet = DAG.getSetCC(dl,
2321 TLI.getSetCCResultType(Hi.getValueType()),
2322 Hi, DAG.getConstant(0, Hi.getValueType()),
2325 // Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits.
2326 SDValue FudgePtr = DAG.getConstantPool(
2327 ConstantInt::get(*DAG.getContext(), FF.zext(64)),
2328 TLI.getPointerTy());
2330 // Get a pointer to FF if the sign bit was set, or to 0 otherwise.
2331 SDValue Zero = DAG.getIntPtrConstant(0);
2332 SDValue Four = DAG.getIntPtrConstant(4);
2333 if (TLI.isBigEndian()) std::swap(Zero, Four);
2334 SDValue Offset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(), SignSet,
2336 unsigned Alignment = cast<ConstantPoolSDNode>(FudgePtr)->getAlignment();
2337 FudgePtr = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(), FudgePtr, Offset);
2338 Alignment = std::min(Alignment, 4u);
2340 // Load the value out, extending it from f32 to the destination float type.
2341 // FIXME: Avoid the extend by constructing the right constant pool?
2342 SDValue Fudge = DAG.getExtLoad(ISD::EXTLOAD, dl, DstVT, DAG.getEntryNode(),
2343 FudgePtr, NULL, 0, MVT::f32,
2345 return DAG.getNode(ISD::FADD, dl, DstVT, SignedConv, Fudge);
2348 // Otherwise, use a libcall.
2349 RTLIB::Libcall LC = RTLIB::getUINTTOFP(SrcVT, DstVT);
2350 assert(LC != RTLIB::UNKNOWN_LIBCALL &&
2351 "Don't know how to expand this UINT_TO_FP!");
2352 return MakeLibCall(LC, DstVT, &Op, 1, true, dl);