1 //===----- LegalizeIntegerTypes.cpp - Legalization of integer types -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements integer type expansion and promotion for LegalizeTypes.
11 // Promotion is the act of changing a computation in an illegal type into a
12 // computation in a larger type. For example, implementing i8 arithmetic in an
13 // i32 register (often needed on powerpc).
14 // Expansion is the act of changing a computation in an illegal type into a
15 // computation in two identical registers of a smaller type. For example,
16 // implementing i64 arithmetic in two i32 registers (often needed on 32-bit
19 //===----------------------------------------------------------------------===//
21 #include "LegalizeTypes.h"
22 #include "llvm/CodeGen/PseudoSourceValue.h"
23 #include "llvm/Support/ErrorHandling.h"
24 #include "llvm/Support/raw_ostream.h"
27 //===----------------------------------------------------------------------===//
28 // Integer Result Promotion
29 //===----------------------------------------------------------------------===//
31 /// PromoteIntegerResult - This method is called when a result of a node is
32 /// found to be in need of promotion to a larger type. At this point, the node
33 /// may also have invalid operands or may have other results that need
34 /// expansion, we just know that (at least) one result needs promotion.
35 void DAGTypeLegalizer::PromoteIntegerResult(SDNode *N, unsigned ResNo) {
36 DEBUG(dbgs() << "Promote integer result: "; N->dump(&DAG); dbgs() << "\n");
37 SDValue Res = SDValue();
39 // See if the target wants to custom expand this node.
40 if (CustomLowerNode(N, N->getValueType(ResNo), true))
43 switch (N->getOpcode()) {
46 dbgs() << "PromoteIntegerResult #" << ResNo << ": ";
47 N->dump(&DAG); dbgs() << "\n";
49 llvm_unreachable("Do not know how to promote this operator!");
50 case ISD::AssertSext: Res = PromoteIntRes_AssertSext(N); break;
51 case ISD::AssertZext: Res = PromoteIntRes_AssertZext(N); break;
52 case ISD::BIT_CONVERT: Res = PromoteIntRes_BIT_CONVERT(N); break;
53 case ISD::BSWAP: Res = PromoteIntRes_BSWAP(N); break;
54 case ISD::BUILD_PAIR: Res = PromoteIntRes_BUILD_PAIR(N); break;
55 case ISD::Constant: Res = PromoteIntRes_Constant(N); break;
56 case ISD::CONVERT_RNDSAT:
57 Res = PromoteIntRes_CONVERT_RNDSAT(N); break;
58 case ISD::CTLZ: Res = PromoteIntRes_CTLZ(N); break;
59 case ISD::CTPOP: Res = PromoteIntRes_CTPOP(N); break;
60 case ISD::CTTZ: Res = PromoteIntRes_CTTZ(N); break;
61 case ISD::EXTRACT_VECTOR_ELT:
62 Res = PromoteIntRes_EXTRACT_VECTOR_ELT(N); break;
63 case ISD::LOAD: Res = PromoteIntRes_LOAD(cast<LoadSDNode>(N));break;
64 case ISD::SELECT: Res = PromoteIntRes_SELECT(N); break;
65 case ISD::SELECT_CC: Res = PromoteIntRes_SELECT_CC(N); break;
66 case ISD::SETCC: Res = PromoteIntRes_SETCC(N); break;
67 case ISD::SHL: Res = PromoteIntRes_SHL(N); break;
68 case ISD::SIGN_EXTEND_INREG:
69 Res = PromoteIntRes_SIGN_EXTEND_INREG(N); break;
70 case ISD::SRA: Res = PromoteIntRes_SRA(N); break;
71 case ISD::SRL: Res = PromoteIntRes_SRL(N); break;
72 case ISD::TRUNCATE: Res = PromoteIntRes_TRUNCATE(N); break;
73 case ISD::UNDEF: Res = PromoteIntRes_UNDEF(N); break;
74 case ISD::VAARG: Res = PromoteIntRes_VAARG(N); break;
76 case ISD::SIGN_EXTEND:
77 case ISD::ZERO_EXTEND:
78 case ISD::ANY_EXTEND: Res = PromoteIntRes_INT_EXTEND(N); break;
81 case ISD::FP_TO_UINT: Res = PromoteIntRes_FP_TO_XINT(N); break;
83 case ISD::FP32_TO_FP16:Res = PromoteIntRes_FP32_TO_FP16(N); break;
90 case ISD::MUL: Res = PromoteIntRes_SimpleIntBinOp(N); break;
93 case ISD::SREM: Res = PromoteIntRes_SDIV(N); break;
96 case ISD::UREM: Res = PromoteIntRes_UDIV(N); break;
99 case ISD::SSUBO: Res = PromoteIntRes_SADDSUBO(N, ResNo); break;
101 case ISD::USUBO: Res = PromoteIntRes_UADDSUBO(N, ResNo); break;
103 case ISD::UMULO: Res = PromoteIntRes_XMULO(N, ResNo); break;
105 case ISD::ATOMIC_LOAD_ADD:
106 case ISD::ATOMIC_LOAD_SUB:
107 case ISD::ATOMIC_LOAD_AND:
108 case ISD::ATOMIC_LOAD_OR:
109 case ISD::ATOMIC_LOAD_XOR:
110 case ISD::ATOMIC_LOAD_NAND:
111 case ISD::ATOMIC_LOAD_MIN:
112 case ISD::ATOMIC_LOAD_MAX:
113 case ISD::ATOMIC_LOAD_UMIN:
114 case ISD::ATOMIC_LOAD_UMAX:
115 case ISD::ATOMIC_SWAP:
116 Res = PromoteIntRes_Atomic1(cast<AtomicSDNode>(N)); break;
118 case ISD::ATOMIC_CMP_SWAP:
119 Res = PromoteIntRes_Atomic2(cast<AtomicSDNode>(N)); break;
122 // If the result is null then the sub-method took care of registering it.
124 SetPromotedInteger(SDValue(N, ResNo), Res);
127 SDValue DAGTypeLegalizer::PromoteIntRes_AssertSext(SDNode *N) {
128 // Sign-extend the new bits, and continue the assertion.
129 SDValue Op = SExtPromotedInteger(N->getOperand(0));
130 return DAG.getNode(ISD::AssertSext, N->getDebugLoc(),
131 Op.getValueType(), Op, N->getOperand(1));
134 SDValue DAGTypeLegalizer::PromoteIntRes_AssertZext(SDNode *N) {
135 // Zero the new bits, and continue the assertion.
136 SDValue Op = ZExtPromotedInteger(N->getOperand(0));
137 return DAG.getNode(ISD::AssertZext, N->getDebugLoc(),
138 Op.getValueType(), Op, N->getOperand(1));
141 SDValue DAGTypeLegalizer::PromoteIntRes_Atomic1(AtomicSDNode *N) {
142 SDValue Op2 = GetPromotedInteger(N->getOperand(2));
143 SDValue Res = DAG.getAtomic(N->getOpcode(), N->getDebugLoc(),
145 N->getChain(), N->getBasePtr(),
146 Op2, N->getSrcValue(), N->getAlignment());
147 // Legalized the chain result - switch anything that used the old chain to
149 ReplaceValueWith(SDValue(N, 1), Res.getValue(1));
153 SDValue DAGTypeLegalizer::PromoteIntRes_Atomic2(AtomicSDNode *N) {
154 SDValue Op2 = GetPromotedInteger(N->getOperand(2));
155 SDValue Op3 = GetPromotedInteger(N->getOperand(3));
156 SDValue Res = DAG.getAtomic(N->getOpcode(), N->getDebugLoc(),
157 N->getMemoryVT(), N->getChain(), N->getBasePtr(),
158 Op2, Op3, N->getSrcValue(), N->getAlignment());
159 // Legalized the chain result - switch anything that used the old chain to
161 ReplaceValueWith(SDValue(N, 1), Res.getValue(1));
165 SDValue DAGTypeLegalizer::PromoteIntRes_BIT_CONVERT(SDNode *N) {
166 SDValue InOp = N->getOperand(0);
167 EVT InVT = InOp.getValueType();
168 EVT NInVT = TLI.getTypeToTransformTo(*DAG.getContext(), InVT);
169 EVT OutVT = N->getValueType(0);
170 EVT NOutVT = TLI.getTypeToTransformTo(*DAG.getContext(), OutVT);
171 DebugLoc dl = N->getDebugLoc();
173 switch (getTypeAction(InVT)) {
175 assert(false && "Unknown type action!");
180 if (NOutVT.bitsEq(NInVT))
181 // The input promotes to the same size. Convert the promoted value.
182 return DAG.getNode(ISD::BIT_CONVERT, dl,
183 NOutVT, GetPromotedInteger(InOp));
186 // Promote the integer operand by hand.
187 return DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT, GetSoftenedFloat(InOp));
191 case ScalarizeVector:
192 // Convert the element to an integer and promote it by hand.
193 return DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT,
194 BitConvertToInteger(GetScalarizedVector(InOp)));
196 // For example, i32 = BIT_CONVERT v2i16 on alpha. Convert the split
197 // pieces of the input into integers and reassemble in the final type.
199 GetSplitVector(N->getOperand(0), Lo, Hi);
200 Lo = BitConvertToInteger(Lo);
201 Hi = BitConvertToInteger(Hi);
203 if (TLI.isBigEndian())
206 InOp = DAG.getNode(ISD::ANY_EXTEND, dl,
207 EVT::getIntegerVT(*DAG.getContext(),
208 NOutVT.getSizeInBits()),
209 JoinIntegers(Lo, Hi));
210 return DAG.getNode(ISD::BIT_CONVERT, dl, NOutVT, InOp);
213 if (OutVT.bitsEq(NInVT))
214 // The input is widened to the same size. Convert to the widened value.
215 return DAG.getNode(ISD::BIT_CONVERT, dl, OutVT, GetWidenedVector(InOp));
218 return DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT,
219 CreateStackStoreLoad(InOp, OutVT));
222 SDValue DAGTypeLegalizer::PromoteIntRes_BSWAP(SDNode *N) {
223 SDValue Op = GetPromotedInteger(N->getOperand(0));
224 EVT OVT = N->getValueType(0);
225 EVT NVT = Op.getValueType();
226 DebugLoc dl = N->getDebugLoc();
228 unsigned DiffBits = NVT.getSizeInBits() - OVT.getSizeInBits();
229 return DAG.getNode(ISD::SRL, dl, NVT, DAG.getNode(ISD::BSWAP, dl, NVT, Op),
230 DAG.getConstant(DiffBits, TLI.getPointerTy()));
233 SDValue DAGTypeLegalizer::PromoteIntRes_BUILD_PAIR(SDNode *N) {
234 // The pair element type may be legal, or may not promote to the same type as
235 // the result, for example i14 = BUILD_PAIR (i7, i7). Handle all cases.
236 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(),
237 TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)),
238 JoinIntegers(N->getOperand(0), N->getOperand(1)));
241 SDValue DAGTypeLegalizer::PromoteIntRes_Constant(SDNode *N) {
242 EVT VT = N->getValueType(0);
243 // FIXME there is no actual debug info here
244 DebugLoc dl = N->getDebugLoc();
245 // Zero extend things like i1, sign extend everything else. It shouldn't
246 // matter in theory which one we pick, but this tends to give better code?
247 unsigned Opc = VT.isByteSized() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
248 SDValue Result = DAG.getNode(Opc, dl, TLI.getTypeToTransformTo(*DAG.getContext(), VT),
250 assert(isa<ConstantSDNode>(Result) && "Didn't constant fold ext?");
254 SDValue DAGTypeLegalizer::PromoteIntRes_CONVERT_RNDSAT(SDNode *N) {
255 ISD::CvtCode CvtCode = cast<CvtRndSatSDNode>(N)->getCvtCode();
256 assert ((CvtCode == ISD::CVT_SS || CvtCode == ISD::CVT_SU ||
257 CvtCode == ISD::CVT_US || CvtCode == ISD::CVT_UU ||
258 CvtCode == ISD::CVT_SF || CvtCode == ISD::CVT_UF) &&
259 "can only promote integers");
260 EVT OutVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
261 return DAG.getConvertRndSat(OutVT, N->getDebugLoc(), N->getOperand(0),
262 N->getOperand(1), N->getOperand(2),
263 N->getOperand(3), N->getOperand(4), CvtCode);
266 SDValue DAGTypeLegalizer::PromoteIntRes_CTLZ(SDNode *N) {
267 // Zero extend to the promoted type and do the count there.
268 SDValue Op = ZExtPromotedInteger(N->getOperand(0));
269 DebugLoc dl = N->getDebugLoc();
270 EVT OVT = N->getValueType(0);
271 EVT NVT = Op.getValueType();
272 Op = DAG.getNode(ISD::CTLZ, dl, NVT, Op);
273 // Subtract off the extra leading bits in the bigger type.
274 return DAG.getNode(ISD::SUB, dl, NVT, Op,
275 DAG.getConstant(NVT.getSizeInBits() -
276 OVT.getSizeInBits(), NVT));
279 SDValue DAGTypeLegalizer::PromoteIntRes_CTPOP(SDNode *N) {
280 // Zero extend to the promoted type and do the count there.
281 SDValue Op = ZExtPromotedInteger(N->getOperand(0));
282 return DAG.getNode(ISD::CTPOP, N->getDebugLoc(), Op.getValueType(), Op);
285 SDValue DAGTypeLegalizer::PromoteIntRes_CTTZ(SDNode *N) {
286 SDValue Op = GetPromotedInteger(N->getOperand(0));
287 EVT OVT = N->getValueType(0);
288 EVT NVT = Op.getValueType();
289 DebugLoc dl = N->getDebugLoc();
290 // The count is the same in the promoted type except if the original
291 // value was zero. This can be handled by setting the bit just off
292 // the top of the original type.
293 APInt TopBit(NVT.getSizeInBits(), 0);
294 TopBit.set(OVT.getSizeInBits());
295 Op = DAG.getNode(ISD::OR, dl, NVT, Op, DAG.getConstant(TopBit, NVT));
296 return DAG.getNode(ISD::CTTZ, dl, NVT, Op);
299 SDValue DAGTypeLegalizer::PromoteIntRes_EXTRACT_VECTOR_ELT(SDNode *N) {
300 DebugLoc dl = N->getDebugLoc();
301 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
302 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, NVT, N->getOperand(0),
306 SDValue DAGTypeLegalizer::PromoteIntRes_FP_TO_XINT(SDNode *N) {
307 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
308 unsigned NewOpc = N->getOpcode();
309 DebugLoc dl = N->getDebugLoc();
311 // If we're promoting a UINT to a larger size and the larger FP_TO_UINT is
312 // not Legal, check to see if we can use FP_TO_SINT instead. (If both UINT
313 // and SINT conversions are Custom, there is no way to tell which is preferable.
314 // We choose SINT because that's the right thing on PPC.)
315 if (N->getOpcode() == ISD::FP_TO_UINT &&
316 !TLI.isOperationLegal(ISD::FP_TO_UINT, NVT) &&
317 TLI.isOperationLegalOrCustom(ISD::FP_TO_SINT, NVT))
318 NewOpc = ISD::FP_TO_SINT;
320 SDValue Res = DAG.getNode(NewOpc, dl, NVT, N->getOperand(0));
322 // Assert that the converted value fits in the original type. If it doesn't
323 // (eg: because the value being converted is too big), then the result of the
324 // original operation was undefined anyway, so the assert is still correct.
325 return DAG.getNode(N->getOpcode() == ISD::FP_TO_UINT ?
326 ISD::AssertZext : ISD::AssertSext, dl,
327 NVT, Res, DAG.getValueType(N->getValueType(0)));
330 SDValue DAGTypeLegalizer::PromoteIntRes_FP32_TO_FP16(SDNode *N) {
331 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
332 DebugLoc dl = N->getDebugLoc();
334 SDValue Res = DAG.getNode(N->getOpcode(), dl, NVT, N->getOperand(0));
336 return DAG.getNode(ISD::AssertZext, dl,
337 NVT, Res, DAG.getValueType(N->getValueType(0)));
340 SDValue DAGTypeLegalizer::PromoteIntRes_INT_EXTEND(SDNode *N) {
341 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
342 DebugLoc dl = N->getDebugLoc();
344 if (getTypeAction(N->getOperand(0).getValueType()) == PromoteInteger) {
345 SDValue Res = GetPromotedInteger(N->getOperand(0));
346 assert(Res.getValueType().bitsLE(NVT) && "Extension doesn't make sense!");
348 // If the result and operand types are the same after promotion, simplify
349 // to an in-register extension.
350 if (NVT == Res.getValueType()) {
351 // The high bits are not guaranteed to be anything. Insert an extend.
352 if (N->getOpcode() == ISD::SIGN_EXTEND)
353 return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NVT, Res,
354 DAG.getValueType(N->getOperand(0).getValueType()));
355 if (N->getOpcode() == ISD::ZERO_EXTEND)
356 return DAG.getZeroExtendInReg(Res, dl, N->getOperand(0).getValueType());
357 assert(N->getOpcode() == ISD::ANY_EXTEND && "Unknown integer extension!");
362 // Otherwise, just extend the original operand all the way to the larger type.
363 return DAG.getNode(N->getOpcode(), dl, NVT, N->getOperand(0));
366 SDValue DAGTypeLegalizer::PromoteIntRes_LOAD(LoadSDNode *N) {
367 assert(ISD::isUNINDEXEDLoad(N) && "Indexed load during type legalization!");
368 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
369 ISD::LoadExtType ExtType =
370 ISD::isNON_EXTLoad(N) ? ISD::EXTLOAD : N->getExtensionType();
371 DebugLoc dl = N->getDebugLoc();
372 SDValue Res = DAG.getExtLoad(ExtType, dl, NVT, N->getChain(), N->getBasePtr(),
373 N->getSrcValue(), N->getSrcValueOffset(),
374 N->getMemoryVT(), N->isVolatile(),
375 N->isNonTemporal(), N->getAlignment());
377 // Legalized the chain result - switch anything that used the old chain to
379 ReplaceValueWith(SDValue(N, 1), Res.getValue(1));
383 /// Promote the overflow flag of an overflowing arithmetic node.
384 SDValue DAGTypeLegalizer::PromoteIntRes_Overflow(SDNode *N) {
385 // Simply change the return type of the boolean result.
386 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(1));
387 EVT ValueVTs[] = { N->getValueType(0), NVT };
388 SDValue Ops[] = { N->getOperand(0), N->getOperand(1) };
389 SDValue Res = DAG.getNode(N->getOpcode(), N->getDebugLoc(),
390 DAG.getVTList(ValueVTs, 2), Ops, 2);
392 // Modified the sum result - switch anything that used the old sum to use
394 ReplaceValueWith(SDValue(N, 0), Res);
396 return SDValue(Res.getNode(), 1);
399 SDValue DAGTypeLegalizer::PromoteIntRes_SADDSUBO(SDNode *N, unsigned ResNo) {
401 return PromoteIntRes_Overflow(N);
403 // The operation overflowed iff the result in the larger type is not the
404 // sign extension of its truncation to the original type.
405 SDValue LHS = SExtPromotedInteger(N->getOperand(0));
406 SDValue RHS = SExtPromotedInteger(N->getOperand(1));
407 EVT OVT = N->getOperand(0).getValueType();
408 EVT NVT = LHS.getValueType();
409 DebugLoc dl = N->getDebugLoc();
411 // Do the arithmetic in the larger type.
412 unsigned Opcode = N->getOpcode() == ISD::SADDO ? ISD::ADD : ISD::SUB;
413 SDValue Res = DAG.getNode(Opcode, dl, NVT, LHS, RHS);
415 // Calculate the overflow flag: sign extend the arithmetic result from
416 // the original type.
417 SDValue Ofl = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NVT, Res,
418 DAG.getValueType(OVT));
419 // Overflowed if and only if this is not equal to Res.
420 Ofl = DAG.getSetCC(dl, N->getValueType(1), Ofl, Res, ISD::SETNE);
422 // Use the calculated overflow everywhere.
423 ReplaceValueWith(SDValue(N, 1), Ofl);
428 SDValue DAGTypeLegalizer::PromoteIntRes_SDIV(SDNode *N) {
429 // Sign extend the input.
430 SDValue LHS = SExtPromotedInteger(N->getOperand(0));
431 SDValue RHS = SExtPromotedInteger(N->getOperand(1));
432 return DAG.getNode(N->getOpcode(), N->getDebugLoc(),
433 LHS.getValueType(), LHS, RHS);
436 SDValue DAGTypeLegalizer::PromoteIntRes_SELECT(SDNode *N) {
437 SDValue LHS = GetPromotedInteger(N->getOperand(1));
438 SDValue RHS = GetPromotedInteger(N->getOperand(2));
439 return DAG.getNode(ISD::SELECT, N->getDebugLoc(),
440 LHS.getValueType(), N->getOperand(0),LHS,RHS);
443 SDValue DAGTypeLegalizer::PromoteIntRes_SELECT_CC(SDNode *N) {
444 SDValue LHS = GetPromotedInteger(N->getOperand(2));
445 SDValue RHS = GetPromotedInteger(N->getOperand(3));
446 return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(),
447 LHS.getValueType(), N->getOperand(0),
448 N->getOperand(1), LHS, RHS, N->getOperand(4));
451 SDValue DAGTypeLegalizer::PromoteIntRes_SETCC(SDNode *N) {
452 EVT SVT = TLI.getSetCCResultType(N->getOperand(0).getValueType());
453 assert(isTypeLegal(SVT) && "Illegal SetCC type!");
454 DebugLoc dl = N->getDebugLoc();
456 // Get the SETCC result using the canonical SETCC type.
457 SDValue SetCC = DAG.getNode(ISD::SETCC, dl, SVT, N->getOperand(0),
458 N->getOperand(1), N->getOperand(2));
460 // Convert to the expected type.
461 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
462 assert(NVT.bitsLE(SVT) && "Integer type overpromoted?");
463 return DAG.getNode(ISD::TRUNCATE, dl, NVT, SetCC);
466 SDValue DAGTypeLegalizer::PromoteIntRes_SHL(SDNode *N) {
467 return DAG.getNode(ISD::SHL, N->getDebugLoc(),
468 TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)),
469 GetPromotedInteger(N->getOperand(0)), N->getOperand(1));
472 SDValue DAGTypeLegalizer::PromoteIntRes_SIGN_EXTEND_INREG(SDNode *N) {
473 SDValue Op = GetPromotedInteger(N->getOperand(0));
474 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(),
475 Op.getValueType(), Op, N->getOperand(1));
478 SDValue DAGTypeLegalizer::PromoteIntRes_SimpleIntBinOp(SDNode *N) {
479 // The input may have strange things in the top bits of the registers, but
480 // these operations don't care. They may have weird bits going out, but
481 // that too is okay if they are integer operations.
482 SDValue LHS = GetPromotedInteger(N->getOperand(0));
483 SDValue RHS = GetPromotedInteger(N->getOperand(1));
484 return DAG.getNode(N->getOpcode(), N->getDebugLoc(),
485 LHS.getValueType(), LHS, RHS);
488 SDValue DAGTypeLegalizer::PromoteIntRes_SRA(SDNode *N) {
489 // The input value must be properly sign extended.
490 SDValue Res = SExtPromotedInteger(N->getOperand(0));
491 return DAG.getNode(ISD::SRA, N->getDebugLoc(),
492 Res.getValueType(), Res, N->getOperand(1));
495 SDValue DAGTypeLegalizer::PromoteIntRes_SRL(SDNode *N) {
496 // The input value must be properly zero extended.
497 EVT VT = N->getValueType(0);
498 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
499 SDValue Res = ZExtPromotedInteger(N->getOperand(0));
500 return DAG.getNode(ISD::SRL, N->getDebugLoc(), NVT, Res, N->getOperand(1));
503 SDValue DAGTypeLegalizer::PromoteIntRes_TRUNCATE(SDNode *N) {
504 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
507 switch (getTypeAction(N->getOperand(0).getValueType())) {
508 default: llvm_unreachable("Unknown type action!");
511 Res = N->getOperand(0);
514 Res = GetPromotedInteger(N->getOperand(0));
518 // Truncate to NVT instead of VT
519 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), NVT, Res);
522 SDValue DAGTypeLegalizer::PromoteIntRes_UADDSUBO(SDNode *N, unsigned ResNo) {
524 return PromoteIntRes_Overflow(N);
526 // The operation overflowed iff the result in the larger type is not the
527 // zero extension of its truncation to the original type.
528 SDValue LHS = ZExtPromotedInteger(N->getOperand(0));
529 SDValue RHS = ZExtPromotedInteger(N->getOperand(1));
530 EVT OVT = N->getOperand(0).getValueType();
531 EVT NVT = LHS.getValueType();
532 DebugLoc dl = N->getDebugLoc();
534 // Do the arithmetic in the larger type.
535 unsigned Opcode = N->getOpcode() == ISD::UADDO ? ISD::ADD : ISD::SUB;
536 SDValue Res = DAG.getNode(Opcode, dl, NVT, LHS, RHS);
538 // Calculate the overflow flag: zero extend the arithmetic result from
539 // the original type.
540 SDValue Ofl = DAG.getZeroExtendInReg(Res, dl, OVT);
541 // Overflowed if and only if this is not equal to Res.
542 Ofl = DAG.getSetCC(dl, N->getValueType(1), Ofl, Res, ISD::SETNE);
544 // Use the calculated overflow everywhere.
545 ReplaceValueWith(SDValue(N, 1), Ofl);
550 SDValue DAGTypeLegalizer::PromoteIntRes_UDIV(SDNode *N) {
551 // Zero extend the input.
552 SDValue LHS = ZExtPromotedInteger(N->getOperand(0));
553 SDValue RHS = ZExtPromotedInteger(N->getOperand(1));
554 return DAG.getNode(N->getOpcode(), N->getDebugLoc(),
555 LHS.getValueType(), LHS, RHS);
558 SDValue DAGTypeLegalizer::PromoteIntRes_UNDEF(SDNode *N) {
559 return DAG.getUNDEF(TLI.getTypeToTransformTo(*DAG.getContext(),
560 N->getValueType(0)));
563 SDValue DAGTypeLegalizer::PromoteIntRes_VAARG(SDNode *N) {
564 SDValue Chain = N->getOperand(0); // Get the chain.
565 SDValue Ptr = N->getOperand(1); // Get the pointer.
566 EVT VT = N->getValueType(0);
567 DebugLoc dl = N->getDebugLoc();
569 EVT RegVT = TLI.getRegisterType(*DAG.getContext(), VT);
570 unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), VT);
571 // The argument is passed as NumRegs registers of type RegVT.
573 SmallVector<SDValue, 8> Parts(NumRegs);
574 for (unsigned i = 0; i < NumRegs; ++i) {
575 Parts[i] = DAG.getVAArg(RegVT, dl, Chain, Ptr, N->getOperand(2));
576 Chain = Parts[i].getValue(1);
579 // Handle endianness of the load.
580 if (TLI.isBigEndian())
581 std::reverse(Parts.begin(), Parts.end());
583 // Assemble the parts in the promoted type.
584 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
585 SDValue Res = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Parts[0]);
586 for (unsigned i = 1; i < NumRegs; ++i) {
587 SDValue Part = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Parts[i]);
588 // Shift it to the right position and "or" it in.
589 Part = DAG.getNode(ISD::SHL, dl, NVT, Part,
590 DAG.getConstant(i * RegVT.getSizeInBits(),
591 TLI.getPointerTy()));
592 Res = DAG.getNode(ISD::OR, dl, NVT, Res, Part);
595 // Modified the chain result - switch anything that used the old chain to
597 ReplaceValueWith(SDValue(N, 1), Chain);
602 SDValue DAGTypeLegalizer::PromoteIntRes_XMULO(SDNode *N, unsigned ResNo) {
603 assert(ResNo == 1 && "Only boolean result promotion currently supported!");
604 return PromoteIntRes_Overflow(N);
607 //===----------------------------------------------------------------------===//
608 // Integer Operand Promotion
609 //===----------------------------------------------------------------------===//
611 /// PromoteIntegerOperand - This method is called when the specified operand of
612 /// the specified node is found to need promotion. At this point, all of the
613 /// result types of the node are known to be legal, but other operands of the
614 /// node may need promotion or expansion as well as the specified one.
615 bool DAGTypeLegalizer::PromoteIntegerOperand(SDNode *N, unsigned OpNo) {
616 DEBUG(dbgs() << "Promote integer operand: "; N->dump(&DAG); dbgs() << "\n");
617 SDValue Res = SDValue();
619 if (CustomLowerNode(N, N->getOperand(OpNo).getValueType(), false))
622 switch (N->getOpcode()) {
625 dbgs() << "PromoteIntegerOperand Op #" << OpNo << ": ";
626 N->dump(&DAG); dbgs() << "\n";
628 llvm_unreachable("Do not know how to promote this operator's operand!");
630 case ISD::ANY_EXTEND: Res = PromoteIntOp_ANY_EXTEND(N); break;
631 case ISD::BIT_CONVERT: Res = PromoteIntOp_BIT_CONVERT(N); break;
632 case ISD::BR_CC: Res = PromoteIntOp_BR_CC(N, OpNo); break;
633 case ISD::BRCOND: Res = PromoteIntOp_BRCOND(N, OpNo); break;
634 case ISD::BUILD_PAIR: Res = PromoteIntOp_BUILD_PAIR(N); break;
635 case ISD::BUILD_VECTOR: Res = PromoteIntOp_BUILD_VECTOR(N); break;
636 case ISD::CONVERT_RNDSAT:
637 Res = PromoteIntOp_CONVERT_RNDSAT(N); break;
638 case ISD::INSERT_VECTOR_ELT:
639 Res = PromoteIntOp_INSERT_VECTOR_ELT(N, OpNo);break;
640 case ISD::MEMBARRIER: Res = PromoteIntOp_MEMBARRIER(N); break;
641 case ISD::SCALAR_TO_VECTOR:
642 Res = PromoteIntOp_SCALAR_TO_VECTOR(N); break;
643 case ISD::SELECT: Res = PromoteIntOp_SELECT(N, OpNo); break;
644 case ISD::SELECT_CC: Res = PromoteIntOp_SELECT_CC(N, OpNo); break;
645 case ISD::SETCC: Res = PromoteIntOp_SETCC(N, OpNo); break;
646 case ISD::SIGN_EXTEND: Res = PromoteIntOp_SIGN_EXTEND(N); break;
647 case ISD::SINT_TO_FP: Res = PromoteIntOp_SINT_TO_FP(N); break;
648 case ISD::STORE: Res = PromoteIntOp_STORE(cast<StoreSDNode>(N),
650 case ISD::TRUNCATE: Res = PromoteIntOp_TRUNCATE(N); break;
651 case ISD::FP16_TO_FP32:
652 case ISD::UINT_TO_FP: Res = PromoteIntOp_UINT_TO_FP(N); break;
653 case ISD::ZERO_EXTEND: Res = PromoteIntOp_ZERO_EXTEND(N); break;
659 case ISD::ROTR: Res = PromoteIntOp_Shift(N); break;
662 // If the result is null, the sub-method took care of registering results etc.
663 if (!Res.getNode()) return false;
665 // If the result is N, the sub-method updated N in place. Tell the legalizer
667 if (Res.getNode() == N)
670 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 &&
671 "Invalid operand expansion");
673 ReplaceValueWith(SDValue(N, 0), Res);
677 /// PromoteSetCCOperands - Promote the operands of a comparison. This code is
678 /// shared among BR_CC, SELECT_CC, and SETCC handlers.
679 void DAGTypeLegalizer::PromoteSetCCOperands(SDValue &NewLHS,SDValue &NewRHS,
680 ISD::CondCode CCCode) {
681 // We have to insert explicit sign or zero extends. Note that we could
682 // insert sign extends for ALL conditions, but zero extend is cheaper on
683 // many machines (an AND instead of two shifts), so prefer it.
685 default: llvm_unreachable("Unknown integer comparison!");
692 // ALL of these operations will work if we either sign or zero extend
693 // the operands (including the unsigned comparisons!). Zero extend is
694 // usually a simpler/cheaper operation, so prefer it.
695 NewLHS = ZExtPromotedInteger(NewLHS);
696 NewRHS = ZExtPromotedInteger(NewRHS);
702 NewLHS = SExtPromotedInteger(NewLHS);
703 NewRHS = SExtPromotedInteger(NewRHS);
708 SDValue DAGTypeLegalizer::PromoteIntOp_ANY_EXTEND(SDNode *N) {
709 SDValue Op = GetPromotedInteger(N->getOperand(0));
710 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), N->getValueType(0), Op);
713 SDValue DAGTypeLegalizer::PromoteIntOp_BIT_CONVERT(SDNode *N) {
714 // This should only occur in unusual situations like bitcasting to an
715 // x86_fp80, so just turn it into a store+load
716 return CreateStackStoreLoad(N->getOperand(0), N->getValueType(0));
719 SDValue DAGTypeLegalizer::PromoteIntOp_BR_CC(SDNode *N, unsigned OpNo) {
720 assert(OpNo == 2 && "Don't know how to promote this operand!");
722 SDValue LHS = N->getOperand(2);
723 SDValue RHS = N->getOperand(3);
724 PromoteSetCCOperands(LHS, RHS, cast<CondCodeSDNode>(N->getOperand(1))->get());
726 // The chain (Op#0), CC (#1) and basic block destination (Op#4) are always
728 return DAG.UpdateNodeOperands(SDValue(N, 0), N->getOperand(0),
729 N->getOperand(1), LHS, RHS, N->getOperand(4));
732 SDValue DAGTypeLegalizer::PromoteIntOp_BRCOND(SDNode *N, unsigned OpNo) {
733 assert(OpNo == 1 && "only know how to promote condition");
735 // Promote all the way up to the canonical SetCC type.
736 EVT SVT = TLI.getSetCCResultType(MVT::Other);
737 SDValue Cond = PromoteTargetBoolean(N->getOperand(1), SVT);
739 // The chain (Op#0) and basic block destination (Op#2) are always legal types.
740 return DAG.UpdateNodeOperands(SDValue(N, 0), N->getOperand(0), Cond,
744 SDValue DAGTypeLegalizer::PromoteIntOp_BUILD_PAIR(SDNode *N) {
745 // Since the result type is legal, the operands must promote to it.
746 EVT OVT = N->getOperand(0).getValueType();
747 SDValue Lo = ZExtPromotedInteger(N->getOperand(0));
748 SDValue Hi = GetPromotedInteger(N->getOperand(1));
749 assert(Lo.getValueType() == N->getValueType(0) && "Operand over promoted?");
750 DebugLoc dl = N->getDebugLoc();
752 Hi = DAG.getNode(ISD::SHL, dl, N->getValueType(0), Hi,
753 DAG.getConstant(OVT.getSizeInBits(), TLI.getPointerTy()));
754 return DAG.getNode(ISD::OR, dl, N->getValueType(0), Lo, Hi);
757 SDValue DAGTypeLegalizer::PromoteIntOp_BUILD_VECTOR(SDNode *N) {
758 // The vector type is legal but the element type is not. This implies
759 // that the vector is a power-of-two in length and that the element
760 // type does not have a strange size (eg: it is not i1).
761 EVT VecVT = N->getValueType(0);
762 unsigned NumElts = VecVT.getVectorNumElements();
763 assert(!(NumElts & 1) && "Legal vector of one illegal element?");
765 // Promote the inserted value. The type does not need to match the
766 // vector element type. Check that any extra bits introduced will be
768 assert(N->getOperand(0).getValueType().getSizeInBits() >=
769 N->getValueType(0).getVectorElementType().getSizeInBits() &&
770 "Type of inserted value narrower than vector element type!");
772 SmallVector<SDValue, 16> NewOps;
773 for (unsigned i = 0; i < NumElts; ++i)
774 NewOps.push_back(GetPromotedInteger(N->getOperand(i)));
776 return DAG.UpdateNodeOperands(SDValue(N, 0), &NewOps[0], NumElts);
779 SDValue DAGTypeLegalizer::PromoteIntOp_CONVERT_RNDSAT(SDNode *N) {
780 ISD::CvtCode CvtCode = cast<CvtRndSatSDNode>(N)->getCvtCode();
781 assert ((CvtCode == ISD::CVT_SS || CvtCode == ISD::CVT_SU ||
782 CvtCode == ISD::CVT_US || CvtCode == ISD::CVT_UU ||
783 CvtCode == ISD::CVT_FS || CvtCode == ISD::CVT_FU) &&
784 "can only promote integer arguments");
785 SDValue InOp = GetPromotedInteger(N->getOperand(0));
786 return DAG.getConvertRndSat(N->getValueType(0), N->getDebugLoc(), InOp,
787 N->getOperand(1), N->getOperand(2),
788 N->getOperand(3), N->getOperand(4), CvtCode);
791 SDValue DAGTypeLegalizer::PromoteIntOp_INSERT_VECTOR_ELT(SDNode *N,
794 // Promote the inserted value. This is valid because the type does not
795 // have to match the vector element type.
797 // Check that any extra bits introduced will be truncated away.
798 assert(N->getOperand(1).getValueType().getSizeInBits() >=
799 N->getValueType(0).getVectorElementType().getSizeInBits() &&
800 "Type of inserted value narrower than vector element type!");
801 return DAG.UpdateNodeOperands(SDValue(N, 0), N->getOperand(0),
802 GetPromotedInteger(N->getOperand(1)),
806 assert(OpNo == 2 && "Different operand and result vector types?");
808 // Promote the index.
809 SDValue Idx = ZExtPromotedInteger(N->getOperand(2));
810 return DAG.UpdateNodeOperands(SDValue(N, 0), N->getOperand(0),
811 N->getOperand(1), Idx);
814 SDValue DAGTypeLegalizer::PromoteIntOp_MEMBARRIER(SDNode *N) {
816 DebugLoc dl = N->getDebugLoc();
817 NewOps[0] = N->getOperand(0);
818 for (unsigned i = 1; i < array_lengthof(NewOps); ++i) {
819 SDValue Flag = GetPromotedInteger(N->getOperand(i));
820 NewOps[i] = DAG.getZeroExtendInReg(Flag, dl, MVT::i1);
822 return DAG.UpdateNodeOperands(SDValue (N, 0), NewOps,
823 array_lengthof(NewOps));
826 SDValue DAGTypeLegalizer::PromoteIntOp_SCALAR_TO_VECTOR(SDNode *N) {
827 // Integer SCALAR_TO_VECTOR operands are implicitly truncated, so just promote
828 // the operand in place.
829 return DAG.UpdateNodeOperands(SDValue(N, 0),
830 GetPromotedInteger(N->getOperand(0)));
833 SDValue DAGTypeLegalizer::PromoteIntOp_SELECT(SDNode *N, unsigned OpNo) {
834 assert(OpNo == 0 && "Only know how to promote condition");
836 // Promote all the way up to the canonical SetCC type.
837 EVT SVT = TLI.getSetCCResultType(N->getOperand(1).getValueType());
838 SDValue Cond = PromoteTargetBoolean(N->getOperand(0), SVT);
840 return DAG.UpdateNodeOperands(SDValue(N, 0), Cond,
841 N->getOperand(1), N->getOperand(2));
844 SDValue DAGTypeLegalizer::PromoteIntOp_SELECT_CC(SDNode *N, unsigned OpNo) {
845 assert(OpNo == 0 && "Don't know how to promote this operand!");
847 SDValue LHS = N->getOperand(0);
848 SDValue RHS = N->getOperand(1);
849 PromoteSetCCOperands(LHS, RHS, cast<CondCodeSDNode>(N->getOperand(4))->get());
851 // The CC (#4) and the possible return values (#2 and #3) have legal types.
852 return DAG.UpdateNodeOperands(SDValue(N, 0), LHS, RHS, N->getOperand(2),
853 N->getOperand(3), N->getOperand(4));
856 SDValue DAGTypeLegalizer::PromoteIntOp_SETCC(SDNode *N, unsigned OpNo) {
857 assert(OpNo == 0 && "Don't know how to promote this operand!");
859 SDValue LHS = N->getOperand(0);
860 SDValue RHS = N->getOperand(1);
861 PromoteSetCCOperands(LHS, RHS, cast<CondCodeSDNode>(N->getOperand(2))->get());
863 // The CC (#2) is always legal.
864 return DAG.UpdateNodeOperands(SDValue(N, 0), LHS, RHS, N->getOperand(2));
867 SDValue DAGTypeLegalizer::PromoteIntOp_Shift(SDNode *N) {
868 return DAG.UpdateNodeOperands(SDValue(N, 0), N->getOperand(0),
869 ZExtPromotedInteger(N->getOperand(1)));
872 SDValue DAGTypeLegalizer::PromoteIntOp_SIGN_EXTEND(SDNode *N) {
873 SDValue Op = GetPromotedInteger(N->getOperand(0));
874 DebugLoc dl = N->getDebugLoc();
875 Op = DAG.getNode(ISD::ANY_EXTEND, dl, N->getValueType(0), Op);
876 return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Op.getValueType(),
877 Op, DAG.getValueType(N->getOperand(0).getValueType()));
880 SDValue DAGTypeLegalizer::PromoteIntOp_SINT_TO_FP(SDNode *N) {
881 return DAG.UpdateNodeOperands(SDValue(N, 0),
882 SExtPromotedInteger(N->getOperand(0)));
885 SDValue DAGTypeLegalizer::PromoteIntOp_STORE(StoreSDNode *N, unsigned OpNo){
886 assert(ISD::isUNINDEXEDStore(N) && "Indexed store during type legalization!");
887 SDValue Ch = N->getChain(), Ptr = N->getBasePtr();
888 int SVOffset = N->getSrcValueOffset();
889 unsigned Alignment = N->getAlignment();
890 bool isVolatile = N->isVolatile();
891 bool isNonTemporal = N->isNonTemporal();
892 DebugLoc dl = N->getDebugLoc();
894 SDValue Val = GetPromotedInteger(N->getValue()); // Get promoted value.
896 // Truncate the value and store the result.
897 return DAG.getTruncStore(Ch, dl, Val, Ptr, N->getSrcValue(),
898 SVOffset, N->getMemoryVT(),
899 isVolatile, isNonTemporal, Alignment);
902 SDValue DAGTypeLegalizer::PromoteIntOp_TRUNCATE(SDNode *N) {
903 SDValue Op = GetPromotedInteger(N->getOperand(0));
904 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), N->getValueType(0), Op);
907 SDValue DAGTypeLegalizer::PromoteIntOp_UINT_TO_FP(SDNode *N) {
908 return DAG.UpdateNodeOperands(SDValue(N, 0),
909 ZExtPromotedInteger(N->getOperand(0)));
912 SDValue DAGTypeLegalizer::PromoteIntOp_ZERO_EXTEND(SDNode *N) {
913 DebugLoc dl = N->getDebugLoc();
914 SDValue Op = GetPromotedInteger(N->getOperand(0));
915 Op = DAG.getNode(ISD::ANY_EXTEND, dl, N->getValueType(0), Op);
916 return DAG.getZeroExtendInReg(Op, dl, N->getOperand(0).getValueType());
920 //===----------------------------------------------------------------------===//
921 // Integer Result Expansion
922 //===----------------------------------------------------------------------===//
924 /// ExpandIntegerResult - This method is called when the specified result of the
925 /// specified node is found to need expansion. At this point, the node may also
926 /// have invalid operands or may have other results that need promotion, we just
927 /// know that (at least) one result needs expansion.
928 void DAGTypeLegalizer::ExpandIntegerResult(SDNode *N, unsigned ResNo) {
929 DEBUG(dbgs() << "Expand integer result: "; N->dump(&DAG); dbgs() << "\n");
933 // See if the target wants to custom expand this node.
934 if (CustomLowerNode(N, N->getValueType(ResNo), true))
937 switch (N->getOpcode()) {
940 dbgs() << "ExpandIntegerResult #" << ResNo << ": ";
941 N->dump(&DAG); dbgs() << "\n";
943 llvm_unreachable("Do not know how to expand the result of this operator!");
945 case ISD::MERGE_VALUES: SplitRes_MERGE_VALUES(N, Lo, Hi); break;
946 case ISD::SELECT: SplitRes_SELECT(N, Lo, Hi); break;
947 case ISD::SELECT_CC: SplitRes_SELECT_CC(N, Lo, Hi); break;
948 case ISD::UNDEF: SplitRes_UNDEF(N, Lo, Hi); break;
950 case ISD::BIT_CONVERT: ExpandRes_BIT_CONVERT(N, Lo, Hi); break;
951 case ISD::BUILD_PAIR: ExpandRes_BUILD_PAIR(N, Lo, Hi); break;
952 case ISD::EXTRACT_ELEMENT: ExpandRes_EXTRACT_ELEMENT(N, Lo, Hi); break;
953 case ISD::EXTRACT_VECTOR_ELT: ExpandRes_EXTRACT_VECTOR_ELT(N, Lo, Hi); break;
954 case ISD::VAARG: ExpandRes_VAARG(N, Lo, Hi); break;
956 case ISD::ANY_EXTEND: ExpandIntRes_ANY_EXTEND(N, Lo, Hi); break;
957 case ISD::AssertSext: ExpandIntRes_AssertSext(N, Lo, Hi); break;
958 case ISD::AssertZext: ExpandIntRes_AssertZext(N, Lo, Hi); break;
959 case ISD::BSWAP: ExpandIntRes_BSWAP(N, Lo, Hi); break;
960 case ISD::Constant: ExpandIntRes_Constant(N, Lo, Hi); break;
961 case ISD::CTLZ: ExpandIntRes_CTLZ(N, Lo, Hi); break;
962 case ISD::CTPOP: ExpandIntRes_CTPOP(N, Lo, Hi); break;
963 case ISD::CTTZ: ExpandIntRes_CTTZ(N, Lo, Hi); break;
964 case ISD::FP_TO_SINT: ExpandIntRes_FP_TO_SINT(N, Lo, Hi); break;
965 case ISD::FP_TO_UINT: ExpandIntRes_FP_TO_UINT(N, Lo, Hi); break;
966 case ISD::LOAD: ExpandIntRes_LOAD(cast<LoadSDNode>(N), Lo, Hi); break;
967 case ISD::MUL: ExpandIntRes_MUL(N, Lo, Hi); break;
968 case ISD::SDIV: ExpandIntRes_SDIV(N, Lo, Hi); break;
969 case ISD::SIGN_EXTEND: ExpandIntRes_SIGN_EXTEND(N, Lo, Hi); break;
970 case ISD::SIGN_EXTEND_INREG: ExpandIntRes_SIGN_EXTEND_INREG(N, Lo, Hi); break;
971 case ISD::SREM: ExpandIntRes_SREM(N, Lo, Hi); break;
972 case ISD::TRUNCATE: ExpandIntRes_TRUNCATE(N, Lo, Hi); break;
973 case ISD::UDIV: ExpandIntRes_UDIV(N, Lo, Hi); break;
974 case ISD::UREM: ExpandIntRes_UREM(N, Lo, Hi); break;
975 case ISD::ZERO_EXTEND: ExpandIntRes_ZERO_EXTEND(N, Lo, Hi); break;
979 case ISD::XOR: ExpandIntRes_Logical(N, Lo, Hi); break;
982 case ISD::SUB: ExpandIntRes_ADDSUB(N, Lo, Hi); break;
985 case ISD::SUBC: ExpandIntRes_ADDSUBC(N, Lo, Hi); break;
988 case ISD::SUBE: ExpandIntRes_ADDSUBE(N, Lo, Hi); break;
992 case ISD::SRL: ExpandIntRes_Shift(N, Lo, Hi); break;
995 // If Lo/Hi is null, the sub-method took care of registering results etc.
997 SetExpandedInteger(SDValue(N, ResNo), Lo, Hi);
1000 /// ExpandShiftByConstant - N is a shift by a value that needs to be expanded,
1001 /// and the shift amount is a constant 'Amt'. Expand the operation.
1002 void DAGTypeLegalizer::ExpandShiftByConstant(SDNode *N, unsigned Amt,
1003 SDValue &Lo, SDValue &Hi) {
1004 DebugLoc dl = N->getDebugLoc();
1005 // Expand the incoming operand to be shifted, so that we have its parts
1007 GetExpandedInteger(N->getOperand(0), InL, InH);
1009 EVT NVT = InL.getValueType();
1010 unsigned VTBits = N->getValueType(0).getSizeInBits();
1011 unsigned NVTBits = NVT.getSizeInBits();
1012 EVT ShTy = N->getOperand(1).getValueType();
1014 if (N->getOpcode() == ISD::SHL) {
1016 Lo = Hi = DAG.getConstant(0, NVT);
1017 } else if (Amt > NVTBits) {
1018 Lo = DAG.getConstant(0, NVT);
1019 Hi = DAG.getNode(ISD::SHL, dl,
1020 NVT, InL, DAG.getConstant(Amt-NVTBits,ShTy));
1021 } else if (Amt == NVTBits) {
1022 Lo = DAG.getConstant(0, NVT);
1024 } else if (Amt == 1 &&
1025 TLI.isOperationLegalOrCustom(ISD::ADDC,
1026 TLI.getTypeToExpandTo(*DAG.getContext(), NVT))) {
1027 // Emit this X << 1 as X+X.
1028 SDVTList VTList = DAG.getVTList(NVT, MVT::Flag);
1029 SDValue LoOps[2] = { InL, InL };
1030 Lo = DAG.getNode(ISD::ADDC, dl, VTList, LoOps, 2);
1031 SDValue HiOps[3] = { InH, InH, Lo.getValue(1) };
1032 Hi = DAG.getNode(ISD::ADDE, dl, VTList, HiOps, 3);
1034 Lo = DAG.getNode(ISD::SHL, dl, NVT, InL, DAG.getConstant(Amt, ShTy));
1035 Hi = DAG.getNode(ISD::OR, dl, NVT,
1036 DAG.getNode(ISD::SHL, dl, NVT, InH,
1037 DAG.getConstant(Amt, ShTy)),
1038 DAG.getNode(ISD::SRL, dl, NVT, InL,
1039 DAG.getConstant(NVTBits-Amt, ShTy)));
1044 if (N->getOpcode() == ISD::SRL) {
1046 Lo = DAG.getConstant(0, NVT);
1047 Hi = DAG.getConstant(0, NVT);
1048 } else if (Amt > NVTBits) {
1049 Lo = DAG.getNode(ISD::SRL, dl,
1050 NVT, InH, DAG.getConstant(Amt-NVTBits,ShTy));
1051 Hi = DAG.getConstant(0, NVT);
1052 } else if (Amt == NVTBits) {
1054 Hi = DAG.getConstant(0, NVT);
1056 Lo = DAG.getNode(ISD::OR, dl, NVT,
1057 DAG.getNode(ISD::SRL, dl, NVT, InL,
1058 DAG.getConstant(Amt, ShTy)),
1059 DAG.getNode(ISD::SHL, dl, NVT, InH,
1060 DAG.getConstant(NVTBits-Amt, ShTy)));
1061 Hi = DAG.getNode(ISD::SRL, dl, NVT, InH, DAG.getConstant(Amt, ShTy));
1066 assert(N->getOpcode() == ISD::SRA && "Unknown shift!");
1068 Hi = Lo = DAG.getNode(ISD::SRA, dl, NVT, InH,
1069 DAG.getConstant(NVTBits-1, ShTy));
1070 } else if (Amt > NVTBits) {
1071 Lo = DAG.getNode(ISD::SRA, dl, NVT, InH,
1072 DAG.getConstant(Amt-NVTBits, ShTy));
1073 Hi = DAG.getNode(ISD::SRA, dl, NVT, InH,
1074 DAG.getConstant(NVTBits-1, ShTy));
1075 } else if (Amt == NVTBits) {
1077 Hi = DAG.getNode(ISD::SRA, dl, NVT, InH,
1078 DAG.getConstant(NVTBits-1, ShTy));
1080 Lo = DAG.getNode(ISD::OR, dl, NVT,
1081 DAG.getNode(ISD::SRL, dl, NVT, InL,
1082 DAG.getConstant(Amt, ShTy)),
1083 DAG.getNode(ISD::SHL, dl, NVT, InH,
1084 DAG.getConstant(NVTBits-Amt, ShTy)));
1085 Hi = DAG.getNode(ISD::SRA, dl, NVT, InH, DAG.getConstant(Amt, ShTy));
1089 /// ExpandShiftWithKnownAmountBit - Try to determine whether we can simplify
1090 /// this shift based on knowledge of the high bit of the shift amount. If we
1091 /// can tell this, we know that it is >= 32 or < 32, without knowing the actual
1093 bool DAGTypeLegalizer::
1094 ExpandShiftWithKnownAmountBit(SDNode *N, SDValue &Lo, SDValue &Hi) {
1095 SDValue Amt = N->getOperand(1);
1096 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1097 EVT ShTy = Amt.getValueType();
1098 unsigned ShBits = ShTy.getScalarType().getSizeInBits();
1099 unsigned NVTBits = NVT.getScalarType().getSizeInBits();
1100 assert(isPowerOf2_32(NVTBits) &&
1101 "Expanded integer type size not a power of two!");
1102 DebugLoc dl = N->getDebugLoc();
1104 APInt HighBitMask = APInt::getHighBitsSet(ShBits, ShBits - Log2_32(NVTBits));
1105 APInt KnownZero, KnownOne;
1106 DAG.ComputeMaskedBits(N->getOperand(1), HighBitMask, KnownZero, KnownOne);
1108 // If we don't know anything about the high bits, exit.
1109 if (((KnownZero|KnownOne) & HighBitMask) == 0)
1112 // Get the incoming operand to be shifted.
1114 GetExpandedInteger(N->getOperand(0), InL, InH);
1116 // If we know that any of the high bits of the shift amount are one, then we
1117 // can do this as a couple of simple shifts.
1118 if (KnownOne.intersects(HighBitMask)) {
1119 // Mask out the high bit, which we know is set.
1120 Amt = DAG.getNode(ISD::AND, dl, ShTy, Amt,
1121 DAG.getConstant(~HighBitMask, ShTy));
1123 switch (N->getOpcode()) {
1124 default: llvm_unreachable("Unknown shift");
1126 Lo = DAG.getConstant(0, NVT); // Low part is zero.
1127 Hi = DAG.getNode(ISD::SHL, dl, NVT, InL, Amt); // High part from Lo part.
1130 Hi = DAG.getConstant(0, NVT); // Hi part is zero.
1131 Lo = DAG.getNode(ISD::SRL, dl, NVT, InH, Amt); // Lo part from Hi part.
1134 Hi = DAG.getNode(ISD::SRA, dl, NVT, InH, // Sign extend high part.
1135 DAG.getConstant(NVTBits-1, ShTy));
1136 Lo = DAG.getNode(ISD::SRA, dl, NVT, InH, Amt); // Lo part from Hi part.
1142 // FIXME: This code is broken for shifts with a zero amount!
1143 // If we know that all of the high bits of the shift amount are zero, then we
1144 // can do this as a couple of simple shifts.
1145 if ((KnownZero & HighBitMask) == HighBitMask) {
1147 SDValue Amt2 = DAG.getNode(ISD::SUB, ShTy,
1148 DAG.getConstant(NVTBits, ShTy),
1151 switch (N->getOpcode()) {
1152 default: llvm_unreachable("Unknown shift");
1153 case ISD::SHL: Op1 = ISD::SHL; Op2 = ISD::SRL; break;
1155 case ISD::SRA: Op1 = ISD::SRL; Op2 = ISD::SHL; break;
1158 Lo = DAG.getNode(N->getOpcode(), NVT, InL, Amt);
1159 Hi = DAG.getNode(ISD::OR, NVT,
1160 DAG.getNode(Op1, NVT, InH, Amt),
1161 DAG.getNode(Op2, NVT, InL, Amt2));
1169 /// ExpandShiftWithUnknownAmountBit - Fully general expansion of integer shift
1171 bool DAGTypeLegalizer::
1172 ExpandShiftWithUnknownAmountBit(SDNode *N, SDValue &Lo, SDValue &Hi) {
1173 SDValue Amt = N->getOperand(1);
1174 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1175 EVT ShTy = Amt.getValueType();
1176 unsigned NVTBits = NVT.getSizeInBits();
1177 assert(isPowerOf2_32(NVTBits) &&
1178 "Expanded integer type size not a power of two!");
1179 DebugLoc dl = N->getDebugLoc();
1181 // Get the incoming operand to be shifted.
1183 GetExpandedInteger(N->getOperand(0), InL, InH);
1185 SDValue NVBitsNode = DAG.getConstant(NVTBits, ShTy);
1186 SDValue AmtExcess = DAG.getNode(ISD::SUB, dl, ShTy, Amt, NVBitsNode);
1187 SDValue AmtLack = DAG.getNode(ISD::SUB, dl, ShTy, NVBitsNode, Amt);
1188 SDValue isShort = DAG.getSetCC(dl, TLI.getSetCCResultType(ShTy),
1189 Amt, NVBitsNode, ISD::SETULT);
1191 SDValue LoS, HiS, LoL, HiL;
1192 switch (N->getOpcode()) {
1193 default: llvm_unreachable("Unknown shift");
1195 // Short: ShAmt < NVTBits
1196 LoS = DAG.getNode(ISD::SHL, dl, NVT, InL, Amt);
1197 HiS = DAG.getNode(ISD::OR, dl, NVT,
1198 DAG.getNode(ISD::SHL, dl, NVT, InH, Amt),
1199 // FIXME: If Amt is zero, the following shift generates an undefined result
1200 // on some architectures.
1201 DAG.getNode(ISD::SRL, dl, NVT, InL, AmtLack));
1203 // Long: ShAmt >= NVTBits
1204 LoL = DAG.getConstant(0, NVT); // Lo part is zero.
1205 HiL = DAG.getNode(ISD::SHL, dl, NVT, InL, AmtExcess); // Hi from Lo part.
1207 Lo = DAG.getNode(ISD::SELECT, dl, NVT, isShort, LoS, LoL);
1208 Hi = DAG.getNode(ISD::SELECT, dl, NVT, isShort, HiS, HiL);
1211 // Short: ShAmt < NVTBits
1212 HiS = DAG.getNode(ISD::SRL, dl, NVT, InH, Amt);
1213 LoS = DAG.getNode(ISD::OR, dl, NVT,
1214 DAG.getNode(ISD::SRL, dl, NVT, InL, Amt),
1215 // FIXME: If Amt is zero, the following shift generates an undefined result
1216 // on some architectures.
1217 DAG.getNode(ISD::SHL, dl, NVT, InH, AmtLack));
1219 // Long: ShAmt >= NVTBits
1220 HiL = DAG.getConstant(0, NVT); // Hi part is zero.
1221 LoL = DAG.getNode(ISD::SRL, dl, NVT, InH, AmtExcess); // Lo from Hi part.
1223 Lo = DAG.getNode(ISD::SELECT, dl, NVT, isShort, LoS, LoL);
1224 Hi = DAG.getNode(ISD::SELECT, dl, NVT, isShort, HiS, HiL);
1227 // Short: ShAmt < NVTBits
1228 HiS = DAG.getNode(ISD::SRA, dl, NVT, InH, Amt);
1229 LoS = DAG.getNode(ISD::OR, dl, NVT,
1230 DAG.getNode(ISD::SRL, dl, NVT, InL, Amt),
1231 // FIXME: If Amt is zero, the following shift generates an undefined result
1232 // on some architectures.
1233 DAG.getNode(ISD::SHL, dl, NVT, InH, AmtLack));
1235 // Long: ShAmt >= NVTBits
1236 HiL = DAG.getNode(ISD::SRA, dl, NVT, InH, // Sign of Hi part.
1237 DAG.getConstant(NVTBits-1, ShTy));
1238 LoL = DAG.getNode(ISD::SRA, dl, NVT, InH, AmtExcess); // Lo from Hi part.
1240 Lo = DAG.getNode(ISD::SELECT, dl, NVT, isShort, LoS, LoL);
1241 Hi = DAG.getNode(ISD::SELECT, dl, NVT, isShort, HiS, HiL);
1248 void DAGTypeLegalizer::ExpandIntRes_ADDSUB(SDNode *N,
1249 SDValue &Lo, SDValue &Hi) {
1250 DebugLoc dl = N->getDebugLoc();
1251 // Expand the subcomponents.
1252 SDValue LHSL, LHSH, RHSL, RHSH;
1253 GetExpandedInteger(N->getOperand(0), LHSL, LHSH);
1254 GetExpandedInteger(N->getOperand(1), RHSL, RHSH);
1256 EVT NVT = LHSL.getValueType();
1257 SDValue LoOps[2] = { LHSL, RHSL };
1258 SDValue HiOps[3] = { LHSH, RHSH };
1260 // Do not generate ADDC/ADDE or SUBC/SUBE if the target does not support
1261 // them. TODO: Teach operation legalization how to expand unsupported
1262 // ADDC/ADDE/SUBC/SUBE. The problem is that these operations generate
1263 // a carry of type MVT::Flag, but there doesn't seem to be any way to
1264 // generate a value of this type in the expanded code sequence.
1266 TLI.isOperationLegalOrCustom(N->getOpcode() == ISD::ADD ?
1267 ISD::ADDC : ISD::SUBC,
1268 TLI.getTypeToExpandTo(*DAG.getContext(), NVT));
1271 SDVTList VTList = DAG.getVTList(NVT, MVT::Flag);
1272 if (N->getOpcode() == ISD::ADD) {
1273 Lo = DAG.getNode(ISD::ADDC, dl, VTList, LoOps, 2);
1274 HiOps[2] = Lo.getValue(1);
1275 Hi = DAG.getNode(ISD::ADDE, dl, VTList, HiOps, 3);
1277 Lo = DAG.getNode(ISD::SUBC, dl, VTList, LoOps, 2);
1278 HiOps[2] = Lo.getValue(1);
1279 Hi = DAG.getNode(ISD::SUBE, dl, VTList, HiOps, 3);
1282 if (N->getOpcode() == ISD::ADD) {
1283 Lo = DAG.getNode(ISD::ADD, dl, NVT, LoOps, 2);
1284 Hi = DAG.getNode(ISD::ADD, dl, NVT, HiOps, 2);
1285 SDValue Cmp1 = DAG.getSetCC(dl, TLI.getSetCCResultType(NVT), Lo, LoOps[0],
1287 SDValue Carry1 = DAG.getNode(ISD::SELECT, dl, NVT, Cmp1,
1288 DAG.getConstant(1, NVT),
1289 DAG.getConstant(0, NVT));
1290 SDValue Cmp2 = DAG.getSetCC(dl, TLI.getSetCCResultType(NVT), Lo, LoOps[1],
1292 SDValue Carry2 = DAG.getNode(ISD::SELECT, dl, NVT, Cmp2,
1293 DAG.getConstant(1, NVT), Carry1);
1294 Hi = DAG.getNode(ISD::ADD, dl, NVT, Hi, Carry2);
1296 Lo = DAG.getNode(ISD::SUB, dl, NVT, LoOps, 2);
1297 Hi = DAG.getNode(ISD::SUB, dl, NVT, HiOps, 2);
1299 DAG.getSetCC(dl, TLI.getSetCCResultType(LoOps[0].getValueType()),
1300 LoOps[0], LoOps[1], ISD::SETULT);
1301 SDValue Borrow = DAG.getNode(ISD::SELECT, dl, NVT, Cmp,
1302 DAG.getConstant(1, NVT),
1303 DAG.getConstant(0, NVT));
1304 Hi = DAG.getNode(ISD::SUB, dl, NVT, Hi, Borrow);
1309 void DAGTypeLegalizer::ExpandIntRes_ADDSUBC(SDNode *N,
1310 SDValue &Lo, SDValue &Hi) {
1311 // Expand the subcomponents.
1312 SDValue LHSL, LHSH, RHSL, RHSH;
1313 DebugLoc dl = N->getDebugLoc();
1314 GetExpandedInteger(N->getOperand(0), LHSL, LHSH);
1315 GetExpandedInteger(N->getOperand(1), RHSL, RHSH);
1316 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag);
1317 SDValue LoOps[2] = { LHSL, RHSL };
1318 SDValue HiOps[3] = { LHSH, RHSH };
1320 if (N->getOpcode() == ISD::ADDC) {
1321 Lo = DAG.getNode(ISD::ADDC, dl, VTList, LoOps, 2);
1322 HiOps[2] = Lo.getValue(1);
1323 Hi = DAG.getNode(ISD::ADDE, dl, VTList, HiOps, 3);
1325 Lo = DAG.getNode(ISD::SUBC, dl, VTList, LoOps, 2);
1326 HiOps[2] = Lo.getValue(1);
1327 Hi = DAG.getNode(ISD::SUBE, dl, VTList, HiOps, 3);
1330 // Legalized the flag result - switch anything that used the old flag to
1332 ReplaceValueWith(SDValue(N, 1), Hi.getValue(1));
1335 void DAGTypeLegalizer::ExpandIntRes_ADDSUBE(SDNode *N,
1336 SDValue &Lo, SDValue &Hi) {
1337 // Expand the subcomponents.
1338 SDValue LHSL, LHSH, RHSL, RHSH;
1339 DebugLoc dl = N->getDebugLoc();
1340 GetExpandedInteger(N->getOperand(0), LHSL, LHSH);
1341 GetExpandedInteger(N->getOperand(1), RHSL, RHSH);
1342 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag);
1343 SDValue LoOps[3] = { LHSL, RHSL, N->getOperand(2) };
1344 SDValue HiOps[3] = { LHSH, RHSH };
1346 Lo = DAG.getNode(N->getOpcode(), dl, VTList, LoOps, 3);
1347 HiOps[2] = Lo.getValue(1);
1348 Hi = DAG.getNode(N->getOpcode(), dl, VTList, HiOps, 3);
1350 // Legalized the flag result - switch anything that used the old flag to
1352 ReplaceValueWith(SDValue(N, 1), Hi.getValue(1));
1355 void DAGTypeLegalizer::ExpandIntRes_ANY_EXTEND(SDNode *N,
1356 SDValue &Lo, SDValue &Hi) {
1357 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1358 DebugLoc dl = N->getDebugLoc();
1359 SDValue Op = N->getOperand(0);
1360 if (Op.getValueType().bitsLE(NVT)) {
1361 // The low part is any extension of the input (which degenerates to a copy).
1362 Lo = DAG.getNode(ISD::ANY_EXTEND, dl, NVT, Op);
1363 Hi = DAG.getUNDEF(NVT); // The high part is undefined.
1365 // For example, extension of an i48 to an i64. The operand type necessarily
1366 // promotes to the result type, so will end up being expanded too.
1367 assert(getTypeAction(Op.getValueType()) == PromoteInteger &&
1368 "Only know how to promote this result!");
1369 SDValue Res = GetPromotedInteger(Op);
1370 assert(Res.getValueType() == N->getValueType(0) &&
1371 "Operand over promoted?");
1372 // Split the promoted operand. This will simplify when it is expanded.
1373 SplitInteger(Res, Lo, Hi);
1377 void DAGTypeLegalizer::ExpandIntRes_AssertSext(SDNode *N,
1378 SDValue &Lo, SDValue &Hi) {
1379 DebugLoc dl = N->getDebugLoc();
1380 GetExpandedInteger(N->getOperand(0), Lo, Hi);
1381 EVT NVT = Lo.getValueType();
1382 EVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
1383 unsigned NVTBits = NVT.getSizeInBits();
1384 unsigned EVTBits = EVT.getSizeInBits();
1386 if (NVTBits < EVTBits) {
1387 Hi = DAG.getNode(ISD::AssertSext, dl, NVT, Hi,
1388 DAG.getValueType(EVT::getIntegerVT(*DAG.getContext(),
1389 EVTBits - NVTBits)));
1391 Lo = DAG.getNode(ISD::AssertSext, dl, NVT, Lo, DAG.getValueType(EVT));
1392 // The high part replicates the sign bit of Lo, make it explicit.
1393 Hi = DAG.getNode(ISD::SRA, dl, NVT, Lo,
1394 DAG.getConstant(NVTBits-1, TLI.getPointerTy()));
1398 void DAGTypeLegalizer::ExpandIntRes_AssertZext(SDNode *N,
1399 SDValue &Lo, SDValue &Hi) {
1400 DebugLoc dl = N->getDebugLoc();
1401 GetExpandedInteger(N->getOperand(0), Lo, Hi);
1402 EVT NVT = Lo.getValueType();
1403 EVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
1404 unsigned NVTBits = NVT.getSizeInBits();
1405 unsigned EVTBits = EVT.getSizeInBits();
1407 if (NVTBits < EVTBits) {
1408 Hi = DAG.getNode(ISD::AssertZext, dl, NVT, Hi,
1409 DAG.getValueType(EVT::getIntegerVT(*DAG.getContext(), EVTBits - NVTBits)));
1411 Lo = DAG.getNode(ISD::AssertZext, dl, NVT, Lo, DAG.getValueType(EVT));
1412 // The high part must be zero, make it explicit.
1413 Hi = DAG.getConstant(0, NVT);
1417 void DAGTypeLegalizer::ExpandIntRes_BSWAP(SDNode *N,
1418 SDValue &Lo, SDValue &Hi) {
1419 DebugLoc dl = N->getDebugLoc();
1420 GetExpandedInteger(N->getOperand(0), Hi, Lo); // Note swapped operands.
1421 Lo = DAG.getNode(ISD::BSWAP, dl, Lo.getValueType(), Lo);
1422 Hi = DAG.getNode(ISD::BSWAP, dl, Hi.getValueType(), Hi);
1425 void DAGTypeLegalizer::ExpandIntRes_Constant(SDNode *N,
1426 SDValue &Lo, SDValue &Hi) {
1427 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1428 unsigned NBitWidth = NVT.getSizeInBits();
1429 const APInt &Cst = cast<ConstantSDNode>(N)->getAPIntValue();
1430 Lo = DAG.getConstant(APInt(Cst).trunc(NBitWidth), NVT);
1431 Hi = DAG.getConstant(Cst.lshr(NBitWidth).trunc(NBitWidth), NVT);
1434 void DAGTypeLegalizer::ExpandIntRes_CTLZ(SDNode *N,
1435 SDValue &Lo, SDValue &Hi) {
1436 DebugLoc dl = N->getDebugLoc();
1437 // ctlz (HiLo) -> Hi != 0 ? ctlz(Hi) : (ctlz(Lo)+32)
1438 GetExpandedInteger(N->getOperand(0), Lo, Hi);
1439 EVT NVT = Lo.getValueType();
1441 SDValue HiNotZero = DAG.getSetCC(dl, TLI.getSetCCResultType(NVT), Hi,
1442 DAG.getConstant(0, NVT), ISD::SETNE);
1444 SDValue LoLZ = DAG.getNode(ISD::CTLZ, dl, NVT, Lo);
1445 SDValue HiLZ = DAG.getNode(ISD::CTLZ, dl, NVT, Hi);
1447 Lo = DAG.getNode(ISD::SELECT, dl, NVT, HiNotZero, HiLZ,
1448 DAG.getNode(ISD::ADD, dl, NVT, LoLZ,
1449 DAG.getConstant(NVT.getSizeInBits(), NVT)));
1450 Hi = DAG.getConstant(0, NVT);
1453 void DAGTypeLegalizer::ExpandIntRes_CTPOP(SDNode *N,
1454 SDValue &Lo, SDValue &Hi) {
1455 DebugLoc dl = N->getDebugLoc();
1456 // ctpop(HiLo) -> ctpop(Hi)+ctpop(Lo)
1457 GetExpandedInteger(N->getOperand(0), Lo, Hi);
1458 EVT NVT = Lo.getValueType();
1459 Lo = DAG.getNode(ISD::ADD, dl, NVT, DAG.getNode(ISD::CTPOP, dl, NVT, Lo),
1460 DAG.getNode(ISD::CTPOP, dl, NVT, Hi));
1461 Hi = DAG.getConstant(0, NVT);
1464 void DAGTypeLegalizer::ExpandIntRes_CTTZ(SDNode *N,
1465 SDValue &Lo, SDValue &Hi) {
1466 DebugLoc dl = N->getDebugLoc();
1467 // cttz (HiLo) -> Lo != 0 ? cttz(Lo) : (cttz(Hi)+32)
1468 GetExpandedInteger(N->getOperand(0), Lo, Hi);
1469 EVT NVT = Lo.getValueType();
1471 SDValue LoNotZero = DAG.getSetCC(dl, TLI.getSetCCResultType(NVT), Lo,
1472 DAG.getConstant(0, NVT), ISD::SETNE);
1474 SDValue LoLZ = DAG.getNode(ISD::CTTZ, dl, NVT, Lo);
1475 SDValue HiLZ = DAG.getNode(ISD::CTTZ, dl, NVT, Hi);
1477 Lo = DAG.getNode(ISD::SELECT, dl, NVT, LoNotZero, LoLZ,
1478 DAG.getNode(ISD::ADD, dl, NVT, HiLZ,
1479 DAG.getConstant(NVT.getSizeInBits(), NVT)));
1480 Hi = DAG.getConstant(0, NVT);
1483 void DAGTypeLegalizer::ExpandIntRes_FP_TO_SINT(SDNode *N, SDValue &Lo,
1485 DebugLoc dl = N->getDebugLoc();
1486 EVT VT = N->getValueType(0);
1487 SDValue Op = N->getOperand(0);
1488 RTLIB::Libcall LC = RTLIB::getFPTOSINT(Op.getValueType(), VT);
1489 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected fp-to-sint conversion!");
1490 SplitInteger(MakeLibCall(LC, VT, &Op, 1, true/*irrelevant*/, dl), Lo, Hi);
1493 void DAGTypeLegalizer::ExpandIntRes_FP_TO_UINT(SDNode *N, SDValue &Lo,
1495 DebugLoc dl = N->getDebugLoc();
1496 EVT VT = N->getValueType(0);
1497 SDValue Op = N->getOperand(0);
1498 RTLIB::Libcall LC = RTLIB::getFPTOUINT(Op.getValueType(), VT);
1499 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected fp-to-uint conversion!");
1500 SplitInteger(MakeLibCall(LC, VT, &Op, 1, false/*irrelevant*/, dl), Lo, Hi);
1503 void DAGTypeLegalizer::ExpandIntRes_LOAD(LoadSDNode *N,
1504 SDValue &Lo, SDValue &Hi) {
1505 if (ISD::isNormalLoad(N)) {
1506 ExpandRes_NormalLoad(N, Lo, Hi);
1510 assert(ISD::isUNINDEXEDLoad(N) && "Indexed load during type legalization!");
1512 EVT VT = N->getValueType(0);
1513 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
1514 SDValue Ch = N->getChain();
1515 SDValue Ptr = N->getBasePtr();
1516 ISD::LoadExtType ExtType = N->getExtensionType();
1517 int SVOffset = N->getSrcValueOffset();
1518 unsigned Alignment = N->getAlignment();
1519 bool isVolatile = N->isVolatile();
1520 bool isNonTemporal = N->isNonTemporal();
1521 DebugLoc dl = N->getDebugLoc();
1523 assert(NVT.isByteSized() && "Expanded type not byte sized!");
1525 if (N->getMemoryVT().bitsLE(NVT)) {
1526 EVT MemVT = N->getMemoryVT();
1528 Lo = DAG.getExtLoad(ExtType, dl, NVT, Ch, Ptr, N->getSrcValue(), SVOffset,
1529 MemVT, isVolatile, isNonTemporal, Alignment);
1531 // Remember the chain.
1532 Ch = Lo.getValue(1);
1534 if (ExtType == ISD::SEXTLOAD) {
1535 // The high part is obtained by SRA'ing all but one of the bits of the
1537 unsigned LoSize = Lo.getValueType().getSizeInBits();
1538 Hi = DAG.getNode(ISD::SRA, dl, NVT, Lo,
1539 DAG.getConstant(LoSize-1, TLI.getPointerTy()));
1540 } else if (ExtType == ISD::ZEXTLOAD) {
1541 // The high part is just a zero.
1542 Hi = DAG.getConstant(0, NVT);
1544 assert(ExtType == ISD::EXTLOAD && "Unknown extload!");
1545 // The high part is undefined.
1546 Hi = DAG.getUNDEF(NVT);
1548 } else if (TLI.isLittleEndian()) {
1549 // Little-endian - low bits are at low addresses.
1550 Lo = DAG.getLoad(NVT, dl, Ch, Ptr, N->getSrcValue(), SVOffset,
1551 isVolatile, isNonTemporal, Alignment);
1553 unsigned ExcessBits =
1554 N->getMemoryVT().getSizeInBits() - NVT.getSizeInBits();
1555 EVT NEVT = EVT::getIntegerVT(*DAG.getContext(), ExcessBits);
1557 // Increment the pointer to the other half.
1558 unsigned IncrementSize = NVT.getSizeInBits()/8;
1559 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
1560 DAG.getIntPtrConstant(IncrementSize));
1561 Hi = DAG.getExtLoad(ExtType, dl, NVT, Ch, Ptr, N->getSrcValue(),
1562 SVOffset+IncrementSize, NEVT,
1563 isVolatile, isNonTemporal,
1564 MinAlign(Alignment, IncrementSize));
1566 // Build a factor node to remember that this load is independent of the
1568 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
1571 // Big-endian - high bits are at low addresses. Favor aligned loads at
1572 // the cost of some bit-fiddling.
1573 EVT MemVT = N->getMemoryVT();
1574 unsigned EBytes = MemVT.getStoreSize();
1575 unsigned IncrementSize = NVT.getSizeInBits()/8;
1576 unsigned ExcessBits = (EBytes - IncrementSize)*8;
1578 // Load both the high bits and maybe some of the low bits.
1579 Hi = DAG.getExtLoad(ExtType, dl, NVT, Ch, Ptr, N->getSrcValue(), SVOffset,
1580 EVT::getIntegerVT(*DAG.getContext(),
1581 MemVT.getSizeInBits() - ExcessBits),
1582 isVolatile, isNonTemporal, Alignment);
1584 // Increment the pointer to the other half.
1585 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
1586 DAG.getIntPtrConstant(IncrementSize));
1587 // Load the rest of the low bits.
1588 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, NVT, Ch, Ptr, N->getSrcValue(),
1589 SVOffset+IncrementSize,
1590 EVT::getIntegerVT(*DAG.getContext(), ExcessBits),
1591 isVolatile, isNonTemporal,
1592 MinAlign(Alignment, IncrementSize));
1594 // Build a factor node to remember that this load is independent of the
1596 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
1599 if (ExcessBits < NVT.getSizeInBits()) {
1600 // Transfer low bits from the bottom of Hi to the top of Lo.
1601 Lo = DAG.getNode(ISD::OR, dl, NVT, Lo,
1602 DAG.getNode(ISD::SHL, dl, NVT, Hi,
1603 DAG.getConstant(ExcessBits,
1604 TLI.getPointerTy())));
1605 // Move high bits to the right position in Hi.
1606 Hi = DAG.getNode(ExtType == ISD::SEXTLOAD ? ISD::SRA : ISD::SRL, dl,
1608 DAG.getConstant(NVT.getSizeInBits() - ExcessBits,
1609 TLI.getPointerTy()));
1613 // Legalized the chain result - switch anything that used the old chain to
1615 ReplaceValueWith(SDValue(N, 1), Ch);
1618 void DAGTypeLegalizer::ExpandIntRes_Logical(SDNode *N,
1619 SDValue &Lo, SDValue &Hi) {
1620 DebugLoc dl = N->getDebugLoc();
1621 SDValue LL, LH, RL, RH;
1622 GetExpandedInteger(N->getOperand(0), LL, LH);
1623 GetExpandedInteger(N->getOperand(1), RL, RH);
1624 Lo = DAG.getNode(N->getOpcode(), dl, LL.getValueType(), LL, RL);
1625 Hi = DAG.getNode(N->getOpcode(), dl, LL.getValueType(), LH, RH);
1628 void DAGTypeLegalizer::ExpandIntRes_MUL(SDNode *N,
1629 SDValue &Lo, SDValue &Hi) {
1630 EVT VT = N->getValueType(0);
1631 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
1632 DebugLoc dl = N->getDebugLoc();
1634 bool HasMULHS = TLI.isOperationLegalOrCustom(ISD::MULHS, NVT);
1635 bool HasMULHU = TLI.isOperationLegalOrCustom(ISD::MULHU, NVT);
1636 bool HasSMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::SMUL_LOHI, NVT);
1637 bool HasUMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::UMUL_LOHI, NVT);
1638 if (HasMULHU || HasMULHS || HasUMUL_LOHI || HasSMUL_LOHI) {
1639 SDValue LL, LH, RL, RH;
1640 GetExpandedInteger(N->getOperand(0), LL, LH);
1641 GetExpandedInteger(N->getOperand(1), RL, RH);
1642 unsigned OuterBitSize = VT.getSizeInBits();
1643 unsigned InnerBitSize = NVT.getSizeInBits();
1644 unsigned LHSSB = DAG.ComputeNumSignBits(N->getOperand(0));
1645 unsigned RHSSB = DAG.ComputeNumSignBits(N->getOperand(1));
1647 APInt HighMask = APInt::getHighBitsSet(OuterBitSize, InnerBitSize);
1648 if (DAG.MaskedValueIsZero(N->getOperand(0), HighMask) &&
1649 DAG.MaskedValueIsZero(N->getOperand(1), HighMask)) {
1650 // The inputs are both zero-extended.
1652 // We can emit a umul_lohi.
1653 Lo = DAG.getNode(ISD::UMUL_LOHI, dl, DAG.getVTList(NVT, NVT), LL, RL);
1654 Hi = SDValue(Lo.getNode(), 1);
1658 // We can emit a mulhu+mul.
1659 Lo = DAG.getNode(ISD::MUL, dl, NVT, LL, RL);
1660 Hi = DAG.getNode(ISD::MULHU, dl, NVT, LL, RL);
1664 if (LHSSB > InnerBitSize && RHSSB > InnerBitSize) {
1665 // The input values are both sign-extended.
1667 // We can emit a smul_lohi.
1668 Lo = DAG.getNode(ISD::SMUL_LOHI, dl, DAG.getVTList(NVT, NVT), LL, RL);
1669 Hi = SDValue(Lo.getNode(), 1);
1673 // We can emit a mulhs+mul.
1674 Lo = DAG.getNode(ISD::MUL, dl, NVT, LL, RL);
1675 Hi = DAG.getNode(ISD::MULHS, dl, NVT, LL, RL);
1680 // Lo,Hi = umul LHS, RHS.
1681 SDValue UMulLOHI = DAG.getNode(ISD::UMUL_LOHI, dl,
1682 DAG.getVTList(NVT, NVT), LL, RL);
1684 Hi = UMulLOHI.getValue(1);
1685 RH = DAG.getNode(ISD::MUL, dl, NVT, LL, RH);
1686 LH = DAG.getNode(ISD::MUL, dl, NVT, LH, RL);
1687 Hi = DAG.getNode(ISD::ADD, dl, NVT, Hi, RH);
1688 Hi = DAG.getNode(ISD::ADD, dl, NVT, Hi, LH);
1692 Lo = DAG.getNode(ISD::MUL, dl, NVT, LL, RL);
1693 Hi = DAG.getNode(ISD::MULHU, dl, NVT, LL, RL);
1694 RH = DAG.getNode(ISD::MUL, dl, NVT, LL, RH);
1695 LH = DAG.getNode(ISD::MUL, dl, NVT, LH, RL);
1696 Hi = DAG.getNode(ISD::ADD, dl, NVT, Hi, RH);
1697 Hi = DAG.getNode(ISD::ADD, dl, NVT, Hi, LH);
1702 // If nothing else, we can make a libcall.
1703 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
1705 LC = RTLIB::MUL_I16;
1706 else if (VT == MVT::i32)
1707 LC = RTLIB::MUL_I32;
1708 else if (VT == MVT::i64)
1709 LC = RTLIB::MUL_I64;
1710 else if (VT == MVT::i128)
1711 LC = RTLIB::MUL_I128;
1712 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported MUL!");
1714 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
1715 SplitInteger(MakeLibCall(LC, VT, Ops, 2, true/*irrelevant*/, dl), Lo, Hi);
1718 void DAGTypeLegalizer::ExpandIntRes_SDIV(SDNode *N,
1719 SDValue &Lo, SDValue &Hi) {
1720 EVT VT = N->getValueType(0);
1721 DebugLoc dl = N->getDebugLoc();
1723 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
1725 LC = RTLIB::SDIV_I16;
1726 else if (VT == MVT::i32)
1727 LC = RTLIB::SDIV_I32;
1728 else if (VT == MVT::i64)
1729 LC = RTLIB::SDIV_I64;
1730 else if (VT == MVT::i128)
1731 LC = RTLIB::SDIV_I128;
1732 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported SDIV!");
1734 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
1735 SplitInteger(MakeLibCall(LC, VT, Ops, 2, true, dl), Lo, Hi);
1738 void DAGTypeLegalizer::ExpandIntRes_Shift(SDNode *N,
1739 SDValue &Lo, SDValue &Hi) {
1740 EVT VT = N->getValueType(0);
1741 DebugLoc dl = N->getDebugLoc();
1743 // If we can emit an efficient shift operation, do so now. Check to see if
1744 // the RHS is a constant.
1745 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N->getOperand(1)))
1746 return ExpandShiftByConstant(N, CN->getZExtValue(), Lo, Hi);
1748 // If we can determine that the high bit of the shift is zero or one, even if
1749 // the low bits are variable, emit this shift in an optimized form.
1750 if (ExpandShiftWithKnownAmountBit(N, Lo, Hi))
1753 // If this target supports shift_PARTS, use it. First, map to the _PARTS opc.
1755 if (N->getOpcode() == ISD::SHL) {
1756 PartsOpc = ISD::SHL_PARTS;
1757 } else if (N->getOpcode() == ISD::SRL) {
1758 PartsOpc = ISD::SRL_PARTS;
1760 assert(N->getOpcode() == ISD::SRA && "Unknown shift!");
1761 PartsOpc = ISD::SRA_PARTS;
1764 // Next check to see if the target supports this SHL_PARTS operation or if it
1765 // will custom expand it.
1766 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
1767 TargetLowering::LegalizeAction Action = TLI.getOperationAction(PartsOpc, NVT);
1768 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) ||
1769 Action == TargetLowering::Custom) {
1770 // Expand the subcomponents.
1772 GetExpandedInteger(N->getOperand(0), LHSL, LHSH);
1774 SDValue Ops[] = { LHSL, LHSH, N->getOperand(1) };
1775 EVT VT = LHSL.getValueType();
1776 Lo = DAG.getNode(PartsOpc, dl, DAG.getVTList(VT, VT), Ops, 3);
1777 Hi = Lo.getValue(1);
1781 // Otherwise, emit a libcall.
1782 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
1784 if (N->getOpcode() == ISD::SHL) {
1785 isSigned = false; /*sign irrelevant*/
1787 LC = RTLIB::SHL_I16;
1788 else if (VT == MVT::i32)
1789 LC = RTLIB::SHL_I32;
1790 else if (VT == MVT::i64)
1791 LC = RTLIB::SHL_I64;
1792 else if (VT == MVT::i128)
1793 LC = RTLIB::SHL_I128;
1794 } else if (N->getOpcode() == ISD::SRL) {
1797 LC = RTLIB::SRL_I16;
1798 else if (VT == MVT::i32)
1799 LC = RTLIB::SRL_I32;
1800 else if (VT == MVT::i64)
1801 LC = RTLIB::SRL_I64;
1802 else if (VT == MVT::i128)
1803 LC = RTLIB::SRL_I128;
1805 assert(N->getOpcode() == ISD::SRA && "Unknown shift!");
1808 LC = RTLIB::SRA_I16;
1809 else if (VT == MVT::i32)
1810 LC = RTLIB::SRA_I32;
1811 else if (VT == MVT::i64)
1812 LC = RTLIB::SRA_I64;
1813 else if (VT == MVT::i128)
1814 LC = RTLIB::SRA_I128;
1817 if (LC != RTLIB::UNKNOWN_LIBCALL && TLI.getLibcallName(LC)) {
1818 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
1819 SplitInteger(MakeLibCall(LC, VT, Ops, 2, isSigned, dl), Lo, Hi);
1823 if (!ExpandShiftWithUnknownAmountBit(N, Lo, Hi))
1824 llvm_unreachable("Unsupported shift!");
1827 void DAGTypeLegalizer::ExpandIntRes_SIGN_EXTEND(SDNode *N,
1828 SDValue &Lo, SDValue &Hi) {
1829 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1830 DebugLoc dl = N->getDebugLoc();
1831 SDValue Op = N->getOperand(0);
1832 if (Op.getValueType().bitsLE(NVT)) {
1833 // The low part is sign extension of the input (degenerates to a copy).
1834 Lo = DAG.getNode(ISD::SIGN_EXTEND, dl, NVT, N->getOperand(0));
1835 // The high part is obtained by SRA'ing all but one of the bits of low part.
1836 unsigned LoSize = NVT.getSizeInBits();
1837 Hi = DAG.getNode(ISD::SRA, dl, NVT, Lo,
1838 DAG.getConstant(LoSize-1, TLI.getPointerTy()));
1840 // For example, extension of an i48 to an i64. The operand type necessarily
1841 // promotes to the result type, so will end up being expanded too.
1842 assert(getTypeAction(Op.getValueType()) == PromoteInteger &&
1843 "Only know how to promote this result!");
1844 SDValue Res = GetPromotedInteger(Op);
1845 assert(Res.getValueType() == N->getValueType(0) &&
1846 "Operand over promoted?");
1847 // Split the promoted operand. This will simplify when it is expanded.
1848 SplitInteger(Res, Lo, Hi);
1849 unsigned ExcessBits =
1850 Op.getValueType().getSizeInBits() - NVT.getSizeInBits();
1851 Hi = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Hi.getValueType(), Hi,
1852 DAG.getValueType(EVT::getIntegerVT(*DAG.getContext(), ExcessBits)));
1856 void DAGTypeLegalizer::
1857 ExpandIntRes_SIGN_EXTEND_INREG(SDNode *N, SDValue &Lo, SDValue &Hi) {
1858 DebugLoc dl = N->getDebugLoc();
1859 GetExpandedInteger(N->getOperand(0), Lo, Hi);
1860 EVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
1862 if (EVT.bitsLE(Lo.getValueType())) {
1863 // sext_inreg the low part if needed.
1864 Lo = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Lo.getValueType(), Lo,
1867 // The high part gets the sign extension from the lo-part. This handles
1868 // things like sextinreg V:i64 from i8.
1869 Hi = DAG.getNode(ISD::SRA, dl, Hi.getValueType(), Lo,
1870 DAG.getConstant(Hi.getValueType().getSizeInBits()-1,
1871 TLI.getPointerTy()));
1873 // For example, extension of an i48 to an i64. Leave the low part alone,
1874 // sext_inreg the high part.
1875 unsigned ExcessBits =
1876 EVT.getSizeInBits() - Lo.getValueType().getSizeInBits();
1877 Hi = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Hi.getValueType(), Hi,
1878 DAG.getValueType(EVT::getIntegerVT(*DAG.getContext(), ExcessBits)));
1882 void DAGTypeLegalizer::ExpandIntRes_SREM(SDNode *N,
1883 SDValue &Lo, SDValue &Hi) {
1884 EVT VT = N->getValueType(0);
1885 DebugLoc dl = N->getDebugLoc();
1887 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
1889 LC = RTLIB::SREM_I16;
1890 else if (VT == MVT::i32)
1891 LC = RTLIB::SREM_I32;
1892 else if (VT == MVT::i64)
1893 LC = RTLIB::SREM_I64;
1894 else if (VT == MVT::i128)
1895 LC = RTLIB::SREM_I128;
1896 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported SREM!");
1898 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
1899 SplitInteger(MakeLibCall(LC, VT, Ops, 2, true, dl), Lo, Hi);
1902 void DAGTypeLegalizer::ExpandIntRes_TRUNCATE(SDNode *N,
1903 SDValue &Lo, SDValue &Hi) {
1904 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1905 DebugLoc dl = N->getDebugLoc();
1906 Lo = DAG.getNode(ISD::TRUNCATE, dl, NVT, N->getOperand(0));
1907 Hi = DAG.getNode(ISD::SRL, dl,
1908 N->getOperand(0).getValueType(), N->getOperand(0),
1909 DAG.getConstant(NVT.getSizeInBits(), TLI.getPointerTy()));
1910 Hi = DAG.getNode(ISD::TRUNCATE, dl, NVT, Hi);
1913 void DAGTypeLegalizer::ExpandIntRes_UDIV(SDNode *N,
1914 SDValue &Lo, SDValue &Hi) {
1915 EVT VT = N->getValueType(0);
1916 DebugLoc dl = N->getDebugLoc();
1918 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
1920 LC = RTLIB::UDIV_I16;
1921 else if (VT == MVT::i32)
1922 LC = RTLIB::UDIV_I32;
1923 else if (VT == MVT::i64)
1924 LC = RTLIB::UDIV_I64;
1925 else if (VT == MVT::i128)
1926 LC = RTLIB::UDIV_I128;
1927 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported UDIV!");
1929 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
1930 SplitInteger(MakeLibCall(LC, VT, Ops, 2, false, dl), Lo, Hi);
1933 void DAGTypeLegalizer::ExpandIntRes_UREM(SDNode *N,
1934 SDValue &Lo, SDValue &Hi) {
1935 EVT VT = N->getValueType(0);
1936 DebugLoc dl = N->getDebugLoc();
1938 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
1940 LC = RTLIB::UREM_I16;
1941 else if (VT == MVT::i32)
1942 LC = RTLIB::UREM_I32;
1943 else if (VT == MVT::i64)
1944 LC = RTLIB::UREM_I64;
1945 else if (VT == MVT::i128)
1946 LC = RTLIB::UREM_I128;
1947 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported UREM!");
1949 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
1950 SplitInteger(MakeLibCall(LC, VT, Ops, 2, false, dl), Lo, Hi);
1953 void DAGTypeLegalizer::ExpandIntRes_ZERO_EXTEND(SDNode *N,
1954 SDValue &Lo, SDValue &Hi) {
1955 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1956 DebugLoc dl = N->getDebugLoc();
1957 SDValue Op = N->getOperand(0);
1958 if (Op.getValueType().bitsLE(NVT)) {
1959 // The low part is zero extension of the input (degenerates to a copy).
1960 Lo = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, N->getOperand(0));
1961 Hi = DAG.getConstant(0, NVT); // The high part is just a zero.
1963 // For example, extension of an i48 to an i64. The operand type necessarily
1964 // promotes to the result type, so will end up being expanded too.
1965 assert(getTypeAction(Op.getValueType()) == PromoteInteger &&
1966 "Only know how to promote this result!");
1967 SDValue Res = GetPromotedInteger(Op);
1968 assert(Res.getValueType() == N->getValueType(0) &&
1969 "Operand over promoted?");
1970 // Split the promoted operand. This will simplify when it is expanded.
1971 SplitInteger(Res, Lo, Hi);
1972 unsigned ExcessBits =
1973 Op.getValueType().getSizeInBits() - NVT.getSizeInBits();
1974 Hi = DAG.getZeroExtendInReg(Hi, dl,
1975 EVT::getIntegerVT(*DAG.getContext(), ExcessBits));
1980 //===----------------------------------------------------------------------===//
1981 // Integer Operand Expansion
1982 //===----------------------------------------------------------------------===//
1984 /// ExpandIntegerOperand - This method is called when the specified operand of
1985 /// the specified node is found to need expansion. At this point, all of the
1986 /// result types of the node are known to be legal, but other operands of the
1987 /// node may need promotion or expansion as well as the specified one.
1988 bool DAGTypeLegalizer::ExpandIntegerOperand(SDNode *N, unsigned OpNo) {
1989 DEBUG(dbgs() << "Expand integer operand: "; N->dump(&DAG); dbgs() << "\n");
1990 SDValue Res = SDValue();
1992 if (CustomLowerNode(N, N->getOperand(OpNo).getValueType(), false))
1995 switch (N->getOpcode()) {
1998 dbgs() << "ExpandIntegerOperand Op #" << OpNo << ": ";
1999 N->dump(&DAG); dbgs() << "\n";
2001 llvm_unreachable("Do not know how to expand this operator's operand!");
2003 case ISD::BIT_CONVERT: Res = ExpandOp_BIT_CONVERT(N); break;
2004 case ISD::BR_CC: Res = ExpandIntOp_BR_CC(N); break;
2005 case ISD::BUILD_VECTOR: Res = ExpandOp_BUILD_VECTOR(N); break;
2006 case ISD::EXTRACT_ELEMENT: Res = ExpandOp_EXTRACT_ELEMENT(N); break;
2007 case ISD::INSERT_VECTOR_ELT: Res = ExpandOp_INSERT_VECTOR_ELT(N); break;
2008 case ISD::SCALAR_TO_VECTOR: Res = ExpandOp_SCALAR_TO_VECTOR(N); break;
2009 case ISD::SELECT_CC: Res = ExpandIntOp_SELECT_CC(N); break;
2010 case ISD::SETCC: Res = ExpandIntOp_SETCC(N); break;
2011 case ISD::SINT_TO_FP: Res = ExpandIntOp_SINT_TO_FP(N); break;
2012 case ISD::STORE: Res = ExpandIntOp_STORE(cast<StoreSDNode>(N), OpNo); break;
2013 case ISD::TRUNCATE: Res = ExpandIntOp_TRUNCATE(N); break;
2014 case ISD::UINT_TO_FP: Res = ExpandIntOp_UINT_TO_FP(N); break;
2020 case ISD::ROTR: Res = ExpandIntOp_Shift(N); break;
2021 case ISD::RETURNADDR:
2022 case ISD::FRAMEADDR: Res = ExpandIntOp_RETURNADDR(N); break;
2025 // If the result is null, the sub-method took care of registering results etc.
2026 if (!Res.getNode()) return false;
2028 // If the result is N, the sub-method updated N in place. Tell the legalizer
2030 if (Res.getNode() == N)
2033 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 &&
2034 "Invalid operand expansion");
2036 ReplaceValueWith(SDValue(N, 0), Res);
2040 /// IntegerExpandSetCCOperands - Expand the operands of a comparison. This code
2041 /// is shared among BR_CC, SELECT_CC, and SETCC handlers.
2042 void DAGTypeLegalizer::IntegerExpandSetCCOperands(SDValue &NewLHS,
2044 ISD::CondCode &CCCode,
2046 SDValue LHSLo, LHSHi, RHSLo, RHSHi;
2047 GetExpandedInteger(NewLHS, LHSLo, LHSHi);
2048 GetExpandedInteger(NewRHS, RHSLo, RHSHi);
2050 if (CCCode == ISD::SETEQ || CCCode == ISD::SETNE) {
2051 if (RHSLo == RHSHi) {
2052 if (ConstantSDNode *RHSCST = dyn_cast<ConstantSDNode>(RHSLo)) {
2053 if (RHSCST->isAllOnesValue()) {
2054 // Equality comparison to -1.
2055 NewLHS = DAG.getNode(ISD::AND, dl,
2056 LHSLo.getValueType(), LHSLo, LHSHi);
2063 NewLHS = DAG.getNode(ISD::XOR, dl, LHSLo.getValueType(), LHSLo, RHSLo);
2064 NewRHS = DAG.getNode(ISD::XOR, dl, LHSLo.getValueType(), LHSHi, RHSHi);
2065 NewLHS = DAG.getNode(ISD::OR, dl, NewLHS.getValueType(), NewLHS, NewRHS);
2066 NewRHS = DAG.getConstant(0, NewLHS.getValueType());
2070 // If this is a comparison of the sign bit, just look at the top part.
2072 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(NewRHS))
2073 if ((CCCode == ISD::SETLT && CST->isNullValue()) || // X < 0
2074 (CCCode == ISD::SETGT && CST->isAllOnesValue())) { // X > -1
2080 // FIXME: This generated code sucks.
2081 ISD::CondCode LowCC;
2083 default: llvm_unreachable("Unknown integer setcc!");
2085 case ISD::SETULT: LowCC = ISD::SETULT; break;
2087 case ISD::SETUGT: LowCC = ISD::SETUGT; break;
2089 case ISD::SETULE: LowCC = ISD::SETULE; break;
2091 case ISD::SETUGE: LowCC = ISD::SETUGE; break;
2094 // Tmp1 = lo(op1) < lo(op2) // Always unsigned comparison
2095 // Tmp2 = hi(op1) < hi(op2) // Signedness depends on operands
2096 // dest = hi(op1) == hi(op2) ? Tmp1 : Tmp2;
2098 // NOTE: on targets without efficient SELECT of bools, we can always use
2099 // this identity: (B1 ? B2 : B3) --> (B1 & B2)|(!B1&B3)
2100 TargetLowering::DAGCombinerInfo DagCombineInfo(DAG, false, true, true, NULL);
2102 Tmp1 = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSLo.getValueType()),
2103 LHSLo, RHSLo, LowCC, false, DagCombineInfo, dl);
2104 if (!Tmp1.getNode())
2105 Tmp1 = DAG.getSetCC(dl, TLI.getSetCCResultType(LHSLo.getValueType()),
2106 LHSLo, RHSLo, LowCC);
2107 Tmp2 = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSHi.getValueType()),
2108 LHSHi, RHSHi, CCCode, false, DagCombineInfo, dl);
2109 if (!Tmp2.getNode())
2110 Tmp2 = DAG.getNode(ISD::SETCC, dl,
2111 TLI.getSetCCResultType(LHSHi.getValueType()),
2112 LHSHi, RHSHi, DAG.getCondCode(CCCode));
2114 ConstantSDNode *Tmp1C = dyn_cast<ConstantSDNode>(Tmp1.getNode());
2115 ConstantSDNode *Tmp2C = dyn_cast<ConstantSDNode>(Tmp2.getNode());
2116 if ((Tmp1C && Tmp1C->isNullValue()) ||
2117 (Tmp2C && Tmp2C->isNullValue() &&
2118 (CCCode == ISD::SETLE || CCCode == ISD::SETGE ||
2119 CCCode == ISD::SETUGE || CCCode == ISD::SETULE)) ||
2120 (Tmp2C && Tmp2C->getAPIntValue() == 1 &&
2121 (CCCode == ISD::SETLT || CCCode == ISD::SETGT ||
2122 CCCode == ISD::SETUGT || CCCode == ISD::SETULT))) {
2123 // low part is known false, returns high part.
2124 // For LE / GE, if high part is known false, ignore the low part.
2125 // For LT / GT, if high part is known true, ignore the low part.
2131 NewLHS = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSHi.getValueType()),
2132 LHSHi, RHSHi, ISD::SETEQ, false,
2133 DagCombineInfo, dl);
2134 if (!NewLHS.getNode())
2135 NewLHS = DAG.getSetCC(dl, TLI.getSetCCResultType(LHSHi.getValueType()),
2136 LHSHi, RHSHi, ISD::SETEQ);
2137 NewLHS = DAG.getNode(ISD::SELECT, dl, Tmp1.getValueType(),
2138 NewLHS, Tmp1, Tmp2);
2142 SDValue DAGTypeLegalizer::ExpandIntOp_BR_CC(SDNode *N) {
2143 SDValue NewLHS = N->getOperand(2), NewRHS = N->getOperand(3);
2144 ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(1))->get();
2145 IntegerExpandSetCCOperands(NewLHS, NewRHS, CCCode, N->getDebugLoc());
2147 // If ExpandSetCCOperands returned a scalar, we need to compare the result
2148 // against zero to select between true and false values.
2149 if (NewRHS.getNode() == 0) {
2150 NewRHS = DAG.getConstant(0, NewLHS.getValueType());
2151 CCCode = ISD::SETNE;
2154 // Update N to have the operands specified.
2155 return DAG.UpdateNodeOperands(SDValue(N, 0), N->getOperand(0),
2156 DAG.getCondCode(CCCode), NewLHS, NewRHS,
2160 SDValue DAGTypeLegalizer::ExpandIntOp_SELECT_CC(SDNode *N) {
2161 SDValue NewLHS = N->getOperand(0), NewRHS = N->getOperand(1);
2162 ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(4))->get();
2163 IntegerExpandSetCCOperands(NewLHS, NewRHS, CCCode, N->getDebugLoc());
2165 // If ExpandSetCCOperands returned a scalar, we need to compare the result
2166 // against zero to select between true and false values.
2167 if (NewRHS.getNode() == 0) {
2168 NewRHS = DAG.getConstant(0, NewLHS.getValueType());
2169 CCCode = ISD::SETNE;
2172 // Update N to have the operands specified.
2173 return DAG.UpdateNodeOperands(SDValue(N, 0), NewLHS, NewRHS,
2174 N->getOperand(2), N->getOperand(3),
2175 DAG.getCondCode(CCCode));
2178 SDValue DAGTypeLegalizer::ExpandIntOp_SETCC(SDNode *N) {
2179 SDValue NewLHS = N->getOperand(0), NewRHS = N->getOperand(1);
2180 ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(2))->get();
2181 IntegerExpandSetCCOperands(NewLHS, NewRHS, CCCode, N->getDebugLoc());
2183 // If ExpandSetCCOperands returned a scalar, use it.
2184 if (NewRHS.getNode() == 0) {
2185 assert(NewLHS.getValueType() == N->getValueType(0) &&
2186 "Unexpected setcc expansion!");
2190 // Otherwise, update N to have the operands specified.
2191 return DAG.UpdateNodeOperands(SDValue(N, 0), NewLHS, NewRHS,
2192 DAG.getCondCode(CCCode));
2195 SDValue DAGTypeLegalizer::ExpandIntOp_Shift(SDNode *N) {
2196 // The value being shifted is legal, but the shift amount is too big.
2197 // It follows that either the result of the shift is undefined, or the
2198 // upper half of the shift amount is zero. Just use the lower half.
2200 GetExpandedInteger(N->getOperand(1), Lo, Hi);
2201 return DAG.UpdateNodeOperands(SDValue(N, 0), N->getOperand(0), Lo);
2204 SDValue DAGTypeLegalizer::ExpandIntOp_RETURNADDR(SDNode *N) {
2205 // The argument of RETURNADDR / FRAMEADDR builtin is 32 bit contant. This
2206 // surely makes pretty nice problems on 8/16 bit targets. Just truncate this
2207 // constant to valid type.
2209 GetExpandedInteger(N->getOperand(0), Lo, Hi);
2210 return DAG.UpdateNodeOperands(SDValue(N, 0), Lo);
2213 SDValue DAGTypeLegalizer::ExpandIntOp_SINT_TO_FP(SDNode *N) {
2214 SDValue Op = N->getOperand(0);
2215 EVT DstVT = N->getValueType(0);
2216 RTLIB::Libcall LC = RTLIB::getSINTTOFP(Op.getValueType(), DstVT);
2217 assert(LC != RTLIB::UNKNOWN_LIBCALL &&
2218 "Don't know how to expand this SINT_TO_FP!");
2219 return MakeLibCall(LC, DstVT, &Op, 1, true, N->getDebugLoc());
2222 SDValue DAGTypeLegalizer::ExpandIntOp_STORE(StoreSDNode *N, unsigned OpNo) {
2223 if (ISD::isNormalStore(N))
2224 return ExpandOp_NormalStore(N, OpNo);
2226 assert(ISD::isUNINDEXEDStore(N) && "Indexed store during type legalization!");
2227 assert(OpNo == 1 && "Can only expand the stored value so far");
2229 EVT VT = N->getOperand(1).getValueType();
2230 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
2231 SDValue Ch = N->getChain();
2232 SDValue Ptr = N->getBasePtr();
2233 int SVOffset = N->getSrcValueOffset();
2234 unsigned Alignment = N->getAlignment();
2235 bool isVolatile = N->isVolatile();
2236 bool isNonTemporal = N->isNonTemporal();
2237 DebugLoc dl = N->getDebugLoc();
2240 assert(NVT.isByteSized() && "Expanded type not byte sized!");
2242 if (N->getMemoryVT().bitsLE(NVT)) {
2243 GetExpandedInteger(N->getValue(), Lo, Hi);
2244 return DAG.getTruncStore(Ch, dl, Lo, Ptr, N->getSrcValue(), SVOffset,
2245 N->getMemoryVT(), isVolatile, isNonTemporal,
2247 } else if (TLI.isLittleEndian()) {
2248 // Little-endian - low bits are at low addresses.
2249 GetExpandedInteger(N->getValue(), Lo, Hi);
2251 Lo = DAG.getStore(Ch, dl, Lo, Ptr, N->getSrcValue(), SVOffset,
2252 isVolatile, isNonTemporal, Alignment);
2254 unsigned ExcessBits =
2255 N->getMemoryVT().getSizeInBits() - NVT.getSizeInBits();
2256 EVT NEVT = EVT::getIntegerVT(*DAG.getContext(), ExcessBits);
2258 // Increment the pointer to the other half.
2259 unsigned IncrementSize = NVT.getSizeInBits()/8;
2260 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
2261 DAG.getIntPtrConstant(IncrementSize));
2262 Hi = DAG.getTruncStore(Ch, dl, Hi, Ptr, N->getSrcValue(),
2263 SVOffset+IncrementSize, NEVT,
2264 isVolatile, isNonTemporal,
2265 MinAlign(Alignment, IncrementSize));
2266 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi);
2268 // Big-endian - high bits are at low addresses. Favor aligned stores at
2269 // the cost of some bit-fiddling.
2270 GetExpandedInteger(N->getValue(), Lo, Hi);
2272 EVT ExtVT = N->getMemoryVT();
2273 unsigned EBytes = ExtVT.getStoreSize();
2274 unsigned IncrementSize = NVT.getSizeInBits()/8;
2275 unsigned ExcessBits = (EBytes - IncrementSize)*8;
2276 EVT HiVT = EVT::getIntegerVT(*DAG.getContext(),
2277 ExtVT.getSizeInBits() - ExcessBits);
2279 if (ExcessBits < NVT.getSizeInBits()) {
2280 // Transfer high bits from the top of Lo to the bottom of Hi.
2281 Hi = DAG.getNode(ISD::SHL, dl, NVT, Hi,
2282 DAG.getConstant(NVT.getSizeInBits() - ExcessBits,
2283 TLI.getPointerTy()));
2284 Hi = DAG.getNode(ISD::OR, dl, NVT, Hi,
2285 DAG.getNode(ISD::SRL, dl, NVT, Lo,
2286 DAG.getConstant(ExcessBits,
2287 TLI.getPointerTy())));
2290 // Store both the high bits and maybe some of the low bits.
2291 Hi = DAG.getTruncStore(Ch, dl, Hi, Ptr, N->getSrcValue(),
2292 SVOffset, HiVT, isVolatile, isNonTemporal,
2295 // Increment the pointer to the other half.
2296 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
2297 DAG.getIntPtrConstant(IncrementSize));
2298 // Store the lowest ExcessBits bits in the second half.
2299 Lo = DAG.getTruncStore(Ch, dl, Lo, Ptr, N->getSrcValue(),
2300 SVOffset+IncrementSize,
2301 EVT::getIntegerVT(*DAG.getContext(), ExcessBits),
2302 isVolatile, isNonTemporal,
2303 MinAlign(Alignment, IncrementSize));
2304 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi);
2308 SDValue DAGTypeLegalizer::ExpandIntOp_TRUNCATE(SDNode *N) {
2310 GetExpandedInteger(N->getOperand(0), InL, InH);
2311 // Just truncate the low part of the source.
2312 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), N->getValueType(0), InL);
2315 SDValue DAGTypeLegalizer::ExpandIntOp_UINT_TO_FP(SDNode *N) {
2316 SDValue Op = N->getOperand(0);
2317 EVT SrcVT = Op.getValueType();
2318 EVT DstVT = N->getValueType(0);
2319 DebugLoc dl = N->getDebugLoc();
2321 if (TLI.getOperationAction(ISD::SINT_TO_FP, SrcVT) == TargetLowering::Custom){
2322 // Do a signed conversion then adjust the result.
2323 SDValue SignedConv = DAG.getNode(ISD::SINT_TO_FP, dl, DstVT, Op);
2324 SignedConv = TLI.LowerOperation(SignedConv, DAG);
2326 // The result of the signed conversion needs adjusting if the 'sign bit' of
2327 // the incoming integer was set. To handle this, we dynamically test to see
2328 // if it is set, and, if so, add a fudge factor.
2330 const uint64_t F32TwoE32 = 0x4F800000ULL;
2331 const uint64_t F32TwoE64 = 0x5F800000ULL;
2332 const uint64_t F32TwoE128 = 0x7F800000ULL;
2335 if (SrcVT == MVT::i32)
2336 FF = APInt(32, F32TwoE32);
2337 else if (SrcVT == MVT::i64)
2338 FF = APInt(32, F32TwoE64);
2339 else if (SrcVT == MVT::i128)
2340 FF = APInt(32, F32TwoE128);
2342 assert(false && "Unsupported UINT_TO_FP!");
2344 // Check whether the sign bit is set.
2346 GetExpandedInteger(Op, Lo, Hi);
2347 SDValue SignSet = DAG.getSetCC(dl,
2348 TLI.getSetCCResultType(Hi.getValueType()),
2349 Hi, DAG.getConstant(0, Hi.getValueType()),
2352 // Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits.
2353 SDValue FudgePtr = DAG.getConstantPool(
2354 ConstantInt::get(*DAG.getContext(), FF.zext(64)),
2355 TLI.getPointerTy());
2357 // Get a pointer to FF if the sign bit was set, or to 0 otherwise.
2358 SDValue Zero = DAG.getIntPtrConstant(0);
2359 SDValue Four = DAG.getIntPtrConstant(4);
2360 if (TLI.isBigEndian()) std::swap(Zero, Four);
2361 SDValue Offset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(), SignSet,
2363 unsigned Alignment = cast<ConstantPoolSDNode>(FudgePtr)->getAlignment();
2364 FudgePtr = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(), FudgePtr, Offset);
2365 Alignment = std::min(Alignment, 4u);
2367 // Load the value out, extending it from f32 to the destination float type.
2368 // FIXME: Avoid the extend by constructing the right constant pool?
2369 SDValue Fudge = DAG.getExtLoad(ISD::EXTLOAD, dl, DstVT, DAG.getEntryNode(),
2370 FudgePtr, NULL, 0, MVT::f32,
2371 false, false, Alignment);
2372 return DAG.getNode(ISD::FADD, dl, DstVT, SignedConv, Fudge);
2375 // Otherwise, use a libcall.
2376 RTLIB::Libcall LC = RTLIB::getUINTTOFP(SrcVT, DstVT);
2377 assert(LC != RTLIB::UNKNOWN_LIBCALL &&
2378 "Don't know how to expand this UINT_TO_FP!");
2379 return MakeLibCall(LC, DstVT, &Op, 1, true, dl);