1 //===----- LegalizeIntegerTypes.cpp - Legalization of integer types -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements integer type expansion and promotion for LegalizeTypes.
11 // Promotion is the act of changing a computation in an illegal type into a
12 // computation in a larger type. For example, implementing i8 arithmetic in an
13 // i32 register (often needed on powerpc).
14 // Expansion is the act of changing a computation in an illegal type into a
15 // computation in two identical registers of a smaller type. For example,
16 // implementing i64 arithmetic in two i32 registers (often needed on 32-bit
19 //===----------------------------------------------------------------------===//
21 #include "LegalizeTypes.h"
22 #include "llvm/CodeGen/PseudoSourceValue.h"
25 //===----------------------------------------------------------------------===//
26 // Integer Result Promotion
27 //===----------------------------------------------------------------------===//
29 /// PromoteIntegerResult - This method is called when a result of a node is
30 /// found to be in need of promotion to a larger type. At this point, the node
31 /// may also have invalid operands or may have other results that need
32 /// expansion, we just know that (at least) one result needs promotion.
33 void DAGTypeLegalizer::PromoteIntegerResult(SDNode *N, unsigned ResNo) {
34 DEBUG(cerr << "Promote integer result: "; N->dump(&DAG); cerr << "\n");
35 SDValue Res = SDValue();
37 // See if the target wants to custom expand this node.
38 if (CustomLowerResults(N, N->getValueType(ResNo), true))
41 switch (N->getOpcode()) {
44 cerr << "PromoteIntegerResult #" << ResNo << ": ";
45 N->dump(&DAG); cerr << "\n";
47 assert(0 && "Do not know how to promote this operator!");
49 case ISD::AssertSext: Res = PromoteIntRes_AssertSext(N); break;
50 case ISD::AssertZext: Res = PromoteIntRes_AssertZext(N); break;
51 case ISD::BIT_CONVERT: Res = PromoteIntRes_BIT_CONVERT(N); break;
52 case ISD::BSWAP: Res = PromoteIntRes_BSWAP(N); break;
53 case ISD::BUILD_PAIR: Res = PromoteIntRes_BUILD_PAIR(N); break;
54 case ISD::Constant: Res = PromoteIntRes_Constant(N); break;
55 case ISD::CONVERT_RNDSAT:
56 Res = PromoteIntRes_CONVERT_RNDSAT(N); break;
57 case ISD::CTLZ: Res = PromoteIntRes_CTLZ(N); break;
58 case ISD::CTPOP: Res = PromoteIntRes_CTPOP(N); break;
59 case ISD::CTTZ: Res = PromoteIntRes_CTTZ(N); break;
60 case ISD::EXTRACT_VECTOR_ELT:
61 Res = PromoteIntRes_EXTRACT_VECTOR_ELT(N); break;
62 case ISD::LOAD: Res = PromoteIntRes_LOAD(cast<LoadSDNode>(N));break;
63 case ISD::SELECT: Res = PromoteIntRes_SELECT(N); break;
64 case ISD::SELECT_CC: Res = PromoteIntRes_SELECT_CC(N); break;
65 case ISD::SETCC: Res = PromoteIntRes_SETCC(N); break;
66 case ISD::SHL: Res = PromoteIntRes_SHL(N); break;
67 case ISD::SIGN_EXTEND_INREG:
68 Res = PromoteIntRes_SIGN_EXTEND_INREG(N); break;
69 case ISD::SRA: Res = PromoteIntRes_SRA(N); break;
70 case ISD::SRL: Res = PromoteIntRes_SRL(N); break;
71 case ISD::TRUNCATE: Res = PromoteIntRes_TRUNCATE(N); break;
72 case ISD::UNDEF: Res = PromoteIntRes_UNDEF(N); break;
73 case ISD::VAARG: Res = PromoteIntRes_VAARG(N); break;
75 case ISD::SIGN_EXTEND:
76 case ISD::ZERO_EXTEND:
77 case ISD::ANY_EXTEND: Res = PromoteIntRes_INT_EXTEND(N); break;
80 case ISD::FP_TO_UINT: Res = PromoteIntRes_FP_TO_XINT(N); break;
87 case ISD::MUL: Res = PromoteIntRes_SimpleIntBinOp(N); break;
90 case ISD::SREM: Res = PromoteIntRes_SDIV(N); break;
93 case ISD::UREM: Res = PromoteIntRes_UDIV(N); break;
96 case ISD::SSUBO: Res = PromoteIntRes_SADDSUBO(N, ResNo); break;
98 case ISD::USUBO: Res = PromoteIntRes_UADDSUBO(N, ResNo); break;
100 case ISD::UMULO: Res = PromoteIntRes_XMULO(N, ResNo); break;
102 case ISD::ATOMIC_LOAD_ADD:
103 case ISD::ATOMIC_LOAD_SUB:
104 case ISD::ATOMIC_LOAD_AND:
105 case ISD::ATOMIC_LOAD_OR:
106 case ISD::ATOMIC_LOAD_XOR:
107 case ISD::ATOMIC_LOAD_NAND:
108 case ISD::ATOMIC_LOAD_MIN:
109 case ISD::ATOMIC_LOAD_MAX:
110 case ISD::ATOMIC_LOAD_UMIN:
111 case ISD::ATOMIC_LOAD_UMAX:
112 case ISD::ATOMIC_SWAP:
113 Res = PromoteIntRes_Atomic1(cast<AtomicSDNode>(N)); break;
115 case ISD::ATOMIC_CMP_SWAP:
116 Res = PromoteIntRes_Atomic2(cast<AtomicSDNode>(N)); break;
119 // If the result is null then the sub-method took care of registering it.
121 SetPromotedInteger(SDValue(N, ResNo), Res);
124 SDValue DAGTypeLegalizer::PromoteIntRes_AssertSext(SDNode *N) {
125 // Sign-extend the new bits, and continue the assertion.
126 SDValue Op = SExtPromotedInteger(N->getOperand(0));
127 return DAG.getNode(ISD::AssertSext, N->getDebugLoc(),
128 Op.getValueType(), Op, N->getOperand(1));
131 SDValue DAGTypeLegalizer::PromoteIntRes_AssertZext(SDNode *N) {
132 // Zero the new bits, and continue the assertion.
133 SDValue Op = ZExtPromotedInteger(N->getOperand(0));
134 return DAG.getNode(ISD::AssertZext, N->getDebugLoc(),
135 Op.getValueType(), Op, N->getOperand(1));
138 SDValue DAGTypeLegalizer::PromoteIntRes_Atomic1(AtomicSDNode *N) {
139 SDValue Op2 = GetPromotedInteger(N->getOperand(2));
140 SDValue Res = DAG.getAtomic(N->getOpcode(), N->getDebugLoc(),
142 N->getChain(), N->getBasePtr(),
143 Op2, N->getSrcValue(), N->getAlignment());
144 // Legalized the chain result - switch anything that used the old chain to
146 ReplaceValueWith(SDValue(N, 1), Res.getValue(1));
150 SDValue DAGTypeLegalizer::PromoteIntRes_Atomic2(AtomicSDNode *N) {
151 SDValue Op2 = GetPromotedInteger(N->getOperand(2));
152 SDValue Op3 = GetPromotedInteger(N->getOperand(3));
153 SDValue Res = DAG.getAtomic(N->getOpcode(), N->getDebugLoc(),
154 N->getMemoryVT(), N->getChain(), N->getBasePtr(),
155 Op2, Op3, N->getSrcValue(), N->getAlignment());
156 // Legalized the chain result - switch anything that used the old chain to
158 ReplaceValueWith(SDValue(N, 1), Res.getValue(1));
162 SDValue DAGTypeLegalizer::PromoteIntRes_BIT_CONVERT(SDNode *N) {
163 SDValue InOp = N->getOperand(0);
164 MVT InVT = InOp.getValueType();
165 MVT NInVT = TLI.getTypeToTransformTo(InVT);
166 MVT OutVT = N->getValueType(0);
167 MVT NOutVT = TLI.getTypeToTransformTo(OutVT);
168 DebugLoc dl = N->getDebugLoc();
170 switch (getTypeAction(InVT)) {
172 assert(false && "Unknown type action!");
177 if (NOutVT.bitsEq(NInVT))
178 // The input promotes to the same size. Convert the promoted value.
179 return DAG.getNode(ISD::BIT_CONVERT, dl,
180 NOutVT, GetPromotedInteger(InOp));
183 // Promote the integer operand by hand.
184 return DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT, GetSoftenedFloat(InOp));
188 case ScalarizeVector:
189 // Convert the element to an integer and promote it by hand.
190 return DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT,
191 BitConvertToInteger(GetScalarizedVector(InOp)));
193 // For example, i32 = BIT_CONVERT v2i16 on alpha. Convert the split
194 // pieces of the input into integers and reassemble in the final type.
196 GetSplitVector(N->getOperand(0), Lo, Hi);
197 Lo = BitConvertToInteger(Lo);
198 Hi = BitConvertToInteger(Hi);
200 if (TLI.isBigEndian())
203 InOp = DAG.getNode(ISD::ANY_EXTEND, dl,
204 MVT::getIntegerVT(NOutVT.getSizeInBits()),
205 JoinIntegers(Lo, Hi));
206 return DAG.getNode(ISD::BIT_CONVERT, dl, NOutVT, InOp);
209 if (OutVT.bitsEq(NInVT))
210 // The input is widened to the same size. Convert to the widened value.
211 return DAG.getNode(ISD::BIT_CONVERT, dl, OutVT, GetWidenedVector(InOp));
214 // Otherwise, lower the bit-convert to a store/load from the stack.
215 // Create the stack frame object. Make sure it is aligned for both
216 // the source and destination types.
217 SDValue FIPtr = DAG.CreateStackTemporary(InVT, OutVT);
218 int FI = cast<FrameIndexSDNode>(FIPtr.getNode())->getIndex();
219 const Value *SV = PseudoSourceValue::getFixedStack(FI);
221 // Emit a store to the stack slot.
222 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, InOp, FIPtr, SV, 0);
224 // Result is an extending load from the stack slot.
225 return DAG.getExtLoad(ISD::EXTLOAD, dl, NOutVT, Store, FIPtr, SV, 0, OutVT);
228 SDValue DAGTypeLegalizer::PromoteIntRes_BSWAP(SDNode *N) {
229 SDValue Op = GetPromotedInteger(N->getOperand(0));
230 MVT OVT = N->getValueType(0);
231 MVT NVT = Op.getValueType();
232 DebugLoc dl = N->getDebugLoc();
234 unsigned DiffBits = NVT.getSizeInBits() - OVT.getSizeInBits();
235 return DAG.getNode(ISD::SRL, dl, NVT, DAG.getNode(ISD::BSWAP, dl, NVT, Op),
236 DAG.getConstant(DiffBits, TLI.getPointerTy()));
239 SDValue DAGTypeLegalizer::PromoteIntRes_BUILD_PAIR(SDNode *N) {
240 // The pair element type may be legal, or may not promote to the same type as
241 // the result, for example i14 = BUILD_PAIR (i7, i7). Handle all cases.
242 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(),
243 TLI.getTypeToTransformTo(N->getValueType(0)),
244 JoinIntegers(N->getOperand(0), N->getOperand(1)));
247 SDValue DAGTypeLegalizer::PromoteIntRes_Constant(SDNode *N) {
248 MVT VT = N->getValueType(0);
249 // FIXME there is no actual debug info here
250 DebugLoc dl = N->getDebugLoc();
251 // Zero extend things like i1, sign extend everything else. It shouldn't
252 // matter in theory which one we pick, but this tends to give better code?
253 unsigned Opc = VT.isByteSized() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
254 SDValue Result = DAG.getNode(Opc, dl, TLI.getTypeToTransformTo(VT),
256 assert(isa<ConstantSDNode>(Result) && "Didn't constant fold ext?");
260 SDValue DAGTypeLegalizer::PromoteIntRes_CONVERT_RNDSAT(SDNode *N) {
261 ISD::CvtCode CvtCode = cast<CvtRndSatSDNode>(N)->getCvtCode();
262 assert ((CvtCode == ISD::CVT_SS || CvtCode == ISD::CVT_SU ||
263 CvtCode == ISD::CVT_US || CvtCode == ISD::CVT_UU ||
264 CvtCode == ISD::CVT_SF || CvtCode == ISD::CVT_UF) &&
265 "can only promote integers");
266 MVT OutVT = TLI.getTypeToTransformTo(N->getValueType(0));
267 return DAG.getConvertRndSat(OutVT, N->getDebugLoc(), N->getOperand(0),
268 N->getOperand(1), N->getOperand(2),
269 N->getOperand(3), N->getOperand(4), CvtCode);
272 SDValue DAGTypeLegalizer::PromoteIntRes_CTLZ(SDNode *N) {
273 // Zero extend to the promoted type and do the count there.
274 SDValue Op = ZExtPromotedInteger(N->getOperand(0));
275 DebugLoc dl = N->getDebugLoc();
276 MVT OVT = N->getValueType(0);
277 MVT NVT = Op.getValueType();
278 Op = DAG.getNode(ISD::CTLZ, dl, NVT, Op);
279 // Subtract off the extra leading bits in the bigger type.
280 return DAG.getNode(ISD::SUB, dl, NVT, Op,
281 DAG.getConstant(NVT.getSizeInBits() -
282 OVT.getSizeInBits(), NVT));
285 SDValue DAGTypeLegalizer::PromoteIntRes_CTPOP(SDNode *N) {
286 // Zero extend to the promoted type and do the count there.
287 SDValue Op = ZExtPromotedInteger(N->getOperand(0));
288 return DAG.getNode(ISD::CTPOP, N->getDebugLoc(), Op.getValueType(), Op);
291 SDValue DAGTypeLegalizer::PromoteIntRes_CTTZ(SDNode *N) {
292 SDValue Op = GetPromotedInteger(N->getOperand(0));
293 MVT OVT = N->getValueType(0);
294 MVT NVT = Op.getValueType();
295 DebugLoc dl = N->getDebugLoc();
296 // The count is the same in the promoted type except if the original
297 // value was zero. This can be handled by setting the bit just off
298 // the top of the original type.
299 APInt TopBit(NVT.getSizeInBits(), 0);
300 TopBit.set(OVT.getSizeInBits());
301 Op = DAG.getNode(ISD::OR, dl, NVT, Op, DAG.getConstant(TopBit, NVT));
302 return DAG.getNode(ISD::CTTZ, dl, NVT, Op);
305 SDValue DAGTypeLegalizer::PromoteIntRes_EXTRACT_VECTOR_ELT(SDNode *N) {
306 MVT OldVT = N->getValueType(0);
307 SDValue OldVec = N->getOperand(0);
308 if (getTypeAction(OldVec.getValueType()) == WidenVector)
309 OldVec = GetWidenedVector(N->getOperand(0));
310 unsigned OldElts = OldVec.getValueType().getVectorNumElements();
311 DebugLoc dl = N->getDebugLoc();
314 assert(!isTypeLegal(OldVec.getValueType()) &&
315 "Legal one-element vector of a type needing promotion!");
316 // It is tempting to follow GetScalarizedVector by a call to
317 // GetPromotedInteger, but this would be wrong because the
318 // scalarized value may not yet have been processed.
319 return DAG.getNode(ISD::ANY_EXTEND, dl, TLI.getTypeToTransformTo(OldVT),
320 GetScalarizedVector(OldVec));
323 // Convert to a vector half as long with an element type of twice the width,
324 // for example <4 x i16> -> <2 x i32>.
325 assert(!(OldElts & 1) && "Odd length vectors not supported!");
326 MVT NewVT = MVT::getIntegerVT(2 * OldVT.getSizeInBits());
327 assert(OldVT.isSimple() && NewVT.isSimple());
329 SDValue NewVec = DAG.getNode(ISD::BIT_CONVERT, dl,
330 MVT::getVectorVT(NewVT, OldElts / 2),
333 // Extract the element at OldIdx / 2 from the new vector.
334 SDValue OldIdx = N->getOperand(1);
335 SDValue NewIdx = DAG.getNode(ISD::SRL, dl, OldIdx.getValueType(), OldIdx,
336 DAG.getConstant(1, TLI.getPointerTy()));
337 SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, NewVT, NewVec, NewIdx);
339 // Select the appropriate half of the element: Lo if OldIdx was even,
342 SDValue Hi = DAG.getNode(ISD::SRL, dl, NewVT, Elt,
343 DAG.getConstant(OldVT.getSizeInBits(),
344 TLI.getPointerTy()));
345 if (TLI.isBigEndian())
348 // Extend to the promoted type.
349 SDValue Odd = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, OldIdx);
350 SDValue Res = DAG.getNode(ISD::SELECT, dl, NewVT, Odd, Hi, Lo);
351 return DAG.getNode(ISD::ANY_EXTEND, dl, TLI.getTypeToTransformTo(OldVT), Res);
354 SDValue DAGTypeLegalizer::PromoteIntRes_FP_TO_XINT(SDNode *N) {
355 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
356 unsigned NewOpc = N->getOpcode();
357 DebugLoc dl = N->getDebugLoc();
359 // If we're promoting a UINT to a larger size, check to see if the new node
360 // will be legal. If it isn't, check to see if FP_TO_SINT is legal, since
361 // we can use that instead. This allows us to generate better code for
362 // FP_TO_UINT for small destination sizes on targets where FP_TO_UINT is not
363 // legal, such as PowerPC.
364 if (N->getOpcode() == ISD::FP_TO_UINT &&
365 !TLI.isOperationLegalOrCustom(ISD::FP_TO_UINT, NVT) &&
366 TLI.isOperationLegalOrCustom(ISD::FP_TO_SINT, NVT))
367 NewOpc = ISD::FP_TO_SINT;
369 SDValue Res = DAG.getNode(NewOpc, dl, NVT, N->getOperand(0));
371 // Assert that the converted value fits in the original type. If it doesn't
372 // (eg: because the value being converted is too big), then the result of the
373 // original operation was undefined anyway, so the assert is still correct.
374 return DAG.getNode(N->getOpcode() == ISD::FP_TO_UINT ?
375 ISD::AssertZext : ISD::AssertSext, dl,
376 NVT, Res, DAG.getValueType(N->getValueType(0)));
379 SDValue DAGTypeLegalizer::PromoteIntRes_INT_EXTEND(SDNode *N) {
380 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
381 DebugLoc dl = N->getDebugLoc();
383 if (getTypeAction(N->getOperand(0).getValueType()) == PromoteInteger) {
384 SDValue Res = GetPromotedInteger(N->getOperand(0));
385 assert(Res.getValueType().bitsLE(NVT) && "Extension doesn't make sense!");
387 // If the result and operand types are the same after promotion, simplify
388 // to an in-register extension.
389 if (NVT == Res.getValueType()) {
390 // The high bits are not guaranteed to be anything. Insert an extend.
391 if (N->getOpcode() == ISD::SIGN_EXTEND)
392 return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NVT, Res,
393 DAG.getValueType(N->getOperand(0).getValueType()));
394 if (N->getOpcode() == ISD::ZERO_EXTEND)
395 return DAG.getZeroExtendInReg(Res, dl, N->getOperand(0).getValueType());
396 assert(N->getOpcode() == ISD::ANY_EXTEND && "Unknown integer extension!");
401 // Otherwise, just extend the original operand all the way to the larger type.
402 return DAG.getNode(N->getOpcode(), dl, NVT, N->getOperand(0));
405 SDValue DAGTypeLegalizer::PromoteIntRes_LOAD(LoadSDNode *N) {
406 assert(ISD::isUNINDEXEDLoad(N) && "Indexed load during type legalization!");
407 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
408 ISD::LoadExtType ExtType =
409 ISD::isNON_EXTLoad(N) ? ISD::EXTLOAD : N->getExtensionType();
410 DebugLoc dl = N->getDebugLoc();
411 SDValue Res = DAG.getExtLoad(ExtType, dl, NVT, N->getChain(), N->getBasePtr(),
412 N->getSrcValue(), N->getSrcValueOffset(),
413 N->getMemoryVT(), N->isVolatile(),
416 // Legalized the chain result - switch anything that used the old chain to
418 ReplaceValueWith(SDValue(N, 1), Res.getValue(1));
422 /// Promote the overflow flag of an overflowing arithmetic node.
423 SDValue DAGTypeLegalizer::PromoteIntRes_Overflow(SDNode *N) {
424 // Simply change the return type of the boolean result.
425 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(1));
426 MVT ValueVTs[] = { N->getValueType(0), NVT };
427 SDValue Ops[] = { N->getOperand(0), N->getOperand(1) };
428 SDValue Res = DAG.getNode(N->getOpcode(), N->getDebugLoc(),
429 DAG.getVTList(ValueVTs, 2), Ops, 2);
431 // Modified the sum result - switch anything that used the old sum to use
433 ReplaceValueWith(SDValue(N, 0), Res);
435 return SDValue(Res.getNode(), 1);
438 SDValue DAGTypeLegalizer::PromoteIntRes_SADDSUBO(SDNode *N, unsigned ResNo) {
440 return PromoteIntRes_Overflow(N);
442 // The operation overflowed iff the result in the larger type is not the
443 // sign extension of its truncation to the original type.
444 SDValue LHS = SExtPromotedInteger(N->getOperand(0));
445 SDValue RHS = SExtPromotedInteger(N->getOperand(1));
446 MVT OVT = N->getOperand(0).getValueType();
447 MVT NVT = LHS.getValueType();
448 DebugLoc dl = N->getDebugLoc();
450 // Do the arithmetic in the larger type.
451 unsigned Opcode = N->getOpcode() == ISD::SADDO ? ISD::ADD : ISD::SUB;
452 SDValue Res = DAG.getNode(Opcode, dl, NVT, LHS, RHS);
454 // Calculate the overflow flag: sign extend the arithmetic result from
455 // the original type.
456 SDValue Ofl = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NVT, Res,
457 DAG.getValueType(OVT));
458 // Overflowed if and only if this is not equal to Res.
459 Ofl = DAG.getSetCC(dl, N->getValueType(1), Ofl, Res, ISD::SETNE);
461 // Use the calculated overflow everywhere.
462 ReplaceValueWith(SDValue(N, 1), Ofl);
467 SDValue DAGTypeLegalizer::PromoteIntRes_SDIV(SDNode *N) {
468 // Sign extend the input.
469 SDValue LHS = SExtPromotedInteger(N->getOperand(0));
470 SDValue RHS = SExtPromotedInteger(N->getOperand(1));
471 return DAG.getNode(N->getOpcode(), N->getDebugLoc(),
472 LHS.getValueType(), LHS, RHS);
475 SDValue DAGTypeLegalizer::PromoteIntRes_SELECT(SDNode *N) {
476 SDValue LHS = GetPromotedInteger(N->getOperand(1));
477 SDValue RHS = GetPromotedInteger(N->getOperand(2));
478 return DAG.getNode(ISD::SELECT, N->getDebugLoc(),
479 LHS.getValueType(), N->getOperand(0),LHS,RHS);
482 SDValue DAGTypeLegalizer::PromoteIntRes_SELECT_CC(SDNode *N) {
483 SDValue LHS = GetPromotedInteger(N->getOperand(2));
484 SDValue RHS = GetPromotedInteger(N->getOperand(3));
485 return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(),
486 LHS.getValueType(), N->getOperand(0),
487 N->getOperand(1), LHS, RHS, N->getOperand(4));
490 SDValue DAGTypeLegalizer::PromoteIntRes_SETCC(SDNode *N) {
491 MVT SVT = TLI.getSetCCResultType(N->getOperand(0).getValueType());
492 assert(isTypeLegal(SVT) && "Illegal SetCC type!");
493 DebugLoc dl = N->getDebugLoc();
495 // Get the SETCC result using the canonical SETCC type.
496 SDValue SetCC = DAG.getNode(ISD::SETCC, dl, SVT, N->getOperand(0),
497 N->getOperand(1), N->getOperand(2));
499 // Convert to the expected type.
500 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
501 assert(NVT.bitsLE(SVT) && "Integer type overpromoted?");
502 return DAG.getNode(ISD::TRUNCATE, dl, NVT, SetCC);
505 SDValue DAGTypeLegalizer::PromoteIntRes_SHL(SDNode *N) {
506 return DAG.getNode(ISD::SHL, N->getDebugLoc(),
507 TLI.getTypeToTransformTo(N->getValueType(0)),
508 GetPromotedInteger(N->getOperand(0)), N->getOperand(1));
511 SDValue DAGTypeLegalizer::PromoteIntRes_SIGN_EXTEND_INREG(SDNode *N) {
512 SDValue Op = GetPromotedInteger(N->getOperand(0));
513 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(),
514 Op.getValueType(), Op, N->getOperand(1));
517 SDValue DAGTypeLegalizer::PromoteIntRes_SimpleIntBinOp(SDNode *N) {
518 // The input may have strange things in the top bits of the registers, but
519 // these operations don't care. They may have weird bits going out, but
520 // that too is okay if they are integer operations.
521 SDValue LHS = GetPromotedInteger(N->getOperand(0));
522 SDValue RHS = GetPromotedInteger(N->getOperand(1));
523 return DAG.getNode(N->getOpcode(), N->getDebugLoc(),
524 LHS.getValueType(), LHS, RHS);
527 SDValue DAGTypeLegalizer::PromoteIntRes_SRA(SDNode *N) {
528 // The input value must be properly sign extended.
529 SDValue Res = SExtPromotedInteger(N->getOperand(0));
530 return DAG.getNode(ISD::SRA, N->getDebugLoc(),
531 Res.getValueType(), Res, N->getOperand(1));
534 SDValue DAGTypeLegalizer::PromoteIntRes_SRL(SDNode *N) {
535 // The input value must be properly zero extended.
536 MVT VT = N->getValueType(0);
537 MVT NVT = TLI.getTypeToTransformTo(VT);
538 SDValue Res = ZExtPromotedInteger(N->getOperand(0));
539 return DAG.getNode(ISD::SRL, N->getDebugLoc(), NVT, Res, N->getOperand(1));
542 SDValue DAGTypeLegalizer::PromoteIntRes_TRUNCATE(SDNode *N) {
543 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
546 switch (getTypeAction(N->getOperand(0).getValueType())) {
547 default: assert(0 && "Unknown type action!");
550 Res = N->getOperand(0);
553 Res = GetPromotedInteger(N->getOperand(0));
557 // Truncate to NVT instead of VT
558 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), NVT, Res);
561 SDValue DAGTypeLegalizer::PromoteIntRes_UADDSUBO(SDNode *N, unsigned ResNo) {
563 return PromoteIntRes_Overflow(N);
565 // The operation overflowed iff the result in the larger type is not the
566 // zero extension of its truncation to the original type.
567 SDValue LHS = ZExtPromotedInteger(N->getOperand(0));
568 SDValue RHS = ZExtPromotedInteger(N->getOperand(1));
569 MVT OVT = N->getOperand(0).getValueType();
570 MVT NVT = LHS.getValueType();
571 DebugLoc dl = N->getDebugLoc();
573 // Do the arithmetic in the larger type.
574 unsigned Opcode = N->getOpcode() == ISD::UADDO ? ISD::ADD : ISD::SUB;
575 SDValue Res = DAG.getNode(Opcode, dl, NVT, LHS, RHS);
577 // Calculate the overflow flag: zero extend the arithmetic result from
578 // the original type.
579 SDValue Ofl = DAG.getZeroExtendInReg(Res, dl, OVT);
580 // Overflowed if and only if this is not equal to Res.
581 Ofl = DAG.getSetCC(dl, N->getValueType(1), Ofl, Res, ISD::SETNE);
583 // Use the calculated overflow everywhere.
584 ReplaceValueWith(SDValue(N, 1), Ofl);
589 SDValue DAGTypeLegalizer::PromoteIntRes_UDIV(SDNode *N) {
590 // Zero extend the input.
591 SDValue LHS = ZExtPromotedInteger(N->getOperand(0));
592 SDValue RHS = ZExtPromotedInteger(N->getOperand(1));
593 return DAG.getNode(N->getOpcode(), N->getDebugLoc(),
594 LHS.getValueType(), LHS, RHS);
597 SDValue DAGTypeLegalizer::PromoteIntRes_UNDEF(SDNode *N) {
598 return DAG.getUNDEF(TLI.getTypeToTransformTo(N->getValueType(0)));
601 SDValue DAGTypeLegalizer::PromoteIntRes_VAARG(SDNode *N) {
602 SDValue Chain = N->getOperand(0); // Get the chain.
603 SDValue Ptr = N->getOperand(1); // Get the pointer.
604 MVT VT = N->getValueType(0);
605 DebugLoc dl = N->getDebugLoc();
607 MVT RegVT = TLI.getRegisterType(VT);
608 unsigned NumRegs = TLI.getNumRegisters(VT);
609 // The argument is passed as NumRegs registers of type RegVT.
611 SmallVector<SDValue, 8> Parts(NumRegs);
612 for (unsigned i = 0; i < NumRegs; ++i) {
613 Parts[i] = DAG.getVAArg(RegVT, dl, Chain, Ptr, N->getOperand(2));
614 Chain = Parts[i].getValue(1);
617 // Handle endianness of the load.
618 if (TLI.isBigEndian())
619 std::reverse(Parts.begin(), Parts.end());
621 // Assemble the parts in the promoted type.
622 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
623 SDValue Res = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Parts[0]);
624 for (unsigned i = 1; i < NumRegs; ++i) {
625 SDValue Part = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Parts[i]);
626 // Shift it to the right position and "or" it in.
627 Part = DAG.getNode(ISD::SHL, dl, NVT, Part,
628 DAG.getConstant(i * RegVT.getSizeInBits(),
629 TLI.getPointerTy()));
630 Res = DAG.getNode(ISD::OR, dl, NVT, Res, Part);
633 // Modified the chain result - switch anything that used the old chain to
635 ReplaceValueWith(SDValue(N, 1), Chain);
640 SDValue DAGTypeLegalizer::PromoteIntRes_XMULO(SDNode *N, unsigned ResNo) {
641 assert(ResNo == 1 && "Only boolean result promotion currently supported!");
642 return PromoteIntRes_Overflow(N);
645 //===----------------------------------------------------------------------===//
646 // Integer Operand Promotion
647 //===----------------------------------------------------------------------===//
649 /// PromoteIntegerOperand - This method is called when the specified operand of
650 /// the specified node is found to need promotion. At this point, all of the
651 /// result types of the node are known to be legal, but other operands of the
652 /// node may need promotion or expansion as well as the specified one.
653 bool DAGTypeLegalizer::PromoteIntegerOperand(SDNode *N, unsigned OpNo) {
654 DEBUG(cerr << "Promote integer operand: "; N->dump(&DAG); cerr << "\n");
655 SDValue Res = SDValue();
657 if (CustomLowerResults(N, N->getOperand(OpNo).getValueType(), false))
660 switch (N->getOpcode()) {
663 cerr << "PromoteIntegerOperand Op #" << OpNo << ": ";
664 N->dump(&DAG); cerr << "\n";
666 assert(0 && "Do not know how to promote this operator's operand!");
669 case ISD::ANY_EXTEND: Res = PromoteIntOp_ANY_EXTEND(N); break;
670 case ISD::BR_CC: Res = PromoteIntOp_BR_CC(N, OpNo); break;
671 case ISD::BRCOND: Res = PromoteIntOp_BRCOND(N, OpNo); break;
672 case ISD::BUILD_PAIR: Res = PromoteIntOp_BUILD_PAIR(N); break;
673 case ISD::BUILD_VECTOR: Res = PromoteIntOp_BUILD_VECTOR(N); break;
674 case ISD::CONVERT_RNDSAT:
675 Res = PromoteIntOp_CONVERT_RNDSAT(N); break;
676 case ISD::INSERT_VECTOR_ELT:
677 Res = PromoteIntOp_INSERT_VECTOR_ELT(N, OpNo);break;
678 case ISD::MEMBARRIER: Res = PromoteIntOp_MEMBARRIER(N); break;
679 case ISD::SELECT: Res = PromoteIntOp_SELECT(N, OpNo); break;
680 case ISD::SELECT_CC: Res = PromoteIntOp_SELECT_CC(N, OpNo); break;
681 case ISD::SETCC: Res = PromoteIntOp_SETCC(N, OpNo); break;
682 case ISD::SIGN_EXTEND: Res = PromoteIntOp_SIGN_EXTEND(N); break;
683 case ISD::SINT_TO_FP: Res = PromoteIntOp_SINT_TO_FP(N); break;
684 case ISD::STORE: Res = PromoteIntOp_STORE(cast<StoreSDNode>(N),
686 case ISD::TRUNCATE: Res = PromoteIntOp_TRUNCATE(N); break;
687 case ISD::UINT_TO_FP: Res = PromoteIntOp_UINT_TO_FP(N); break;
688 case ISD::ZERO_EXTEND: Res = PromoteIntOp_ZERO_EXTEND(N); break;
694 case ISD::ROTR: Res = PromoteIntOp_Shift(N); break;
697 // If the result is null, the sub-method took care of registering results etc.
698 if (!Res.getNode()) return false;
700 // If the result is N, the sub-method updated N in place. Tell the legalizer
702 if (Res.getNode() == N)
705 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 &&
706 "Invalid operand expansion");
708 ReplaceValueWith(SDValue(N, 0), Res);
712 /// PromoteSetCCOperands - Promote the operands of a comparison. This code is
713 /// shared among BR_CC, SELECT_CC, and SETCC handlers.
714 void DAGTypeLegalizer::PromoteSetCCOperands(SDValue &NewLHS,SDValue &NewRHS,
715 ISD::CondCode CCCode) {
716 // We have to insert explicit sign or zero extends. Note that we could
717 // insert sign extends for ALL conditions, but zero extend is cheaper on
718 // many machines (an AND instead of two shifts), so prefer it.
720 default: assert(0 && "Unknown integer comparison!");
727 // ALL of these operations will work if we either sign or zero extend
728 // the operands (including the unsigned comparisons!). Zero extend is
729 // usually a simpler/cheaper operation, so prefer it.
730 NewLHS = ZExtPromotedInteger(NewLHS);
731 NewRHS = ZExtPromotedInteger(NewRHS);
737 NewLHS = SExtPromotedInteger(NewLHS);
738 NewRHS = SExtPromotedInteger(NewRHS);
743 SDValue DAGTypeLegalizer::PromoteIntOp_ANY_EXTEND(SDNode *N) {
744 SDValue Op = GetPromotedInteger(N->getOperand(0));
745 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), N->getValueType(0), Op);
748 SDValue DAGTypeLegalizer::PromoteIntOp_BR_CC(SDNode *N, unsigned OpNo) {
749 assert(OpNo == 2 && "Don't know how to promote this operand!");
751 SDValue LHS = N->getOperand(2);
752 SDValue RHS = N->getOperand(3);
753 PromoteSetCCOperands(LHS, RHS, cast<CondCodeSDNode>(N->getOperand(1))->get());
755 // The chain (Op#0), CC (#1) and basic block destination (Op#4) are always
757 return DAG.UpdateNodeOperands(SDValue(N, 0), N->getOperand(0),
758 N->getOperand(1), LHS, RHS, N->getOperand(4));
761 SDValue DAGTypeLegalizer::PromoteIntOp_BRCOND(SDNode *N, unsigned OpNo) {
762 assert(OpNo == 1 && "only know how to promote condition");
764 // Promote all the way up to the canonical SetCC type.
765 MVT SVT = TLI.getSetCCResultType(MVT::Other);
766 SDValue Cond = PromoteTargetBoolean(N->getOperand(1), SVT);
768 // The chain (Op#0) and basic block destination (Op#2) are always legal types.
769 return DAG.UpdateNodeOperands(SDValue(N, 0), N->getOperand(0), Cond,
773 SDValue DAGTypeLegalizer::PromoteIntOp_BUILD_PAIR(SDNode *N) {
774 // Since the result type is legal, the operands must promote to it.
775 MVT OVT = N->getOperand(0).getValueType();
776 SDValue Lo = ZExtPromotedInteger(N->getOperand(0));
777 SDValue Hi = GetPromotedInteger(N->getOperand(1));
778 assert(Lo.getValueType() == N->getValueType(0) && "Operand over promoted?");
779 DebugLoc dl = N->getDebugLoc();
781 Hi = DAG.getNode(ISD::SHL, dl, N->getValueType(0), Hi,
782 DAG.getConstant(OVT.getSizeInBits(), TLI.getPointerTy()));
783 return DAG.getNode(ISD::OR, dl, N->getValueType(0), Lo, Hi);
786 SDValue DAGTypeLegalizer::PromoteIntOp_BUILD_VECTOR(SDNode *N) {
787 // The vector type is legal but the element type is not. This implies
788 // that the vector is a power-of-two in length and that the element
789 // type does not have a strange size (eg: it is not i1).
790 MVT VecVT = N->getValueType(0);
791 unsigned NumElts = VecVT.getVectorNumElements();
792 assert(!(NumElts & 1) && "Legal vector of one illegal element?");
793 DebugLoc dl = N->getDebugLoc();
795 // Build a vector of half the length out of elements of twice the bitwidth.
796 // For example <4 x i16> -> <2 x i32>.
797 MVT OldVT = N->getOperand(0).getValueType();
798 MVT NewVT = MVT::getIntegerVT(2 * OldVT.getSizeInBits());
799 assert(OldVT.isSimple() && NewVT.isSimple());
801 std::vector<SDValue> NewElts;
802 NewElts.reserve(NumElts/2);
804 for (unsigned i = 0; i < NumElts; i += 2) {
805 // Combine two successive elements into one promoted element.
806 SDValue Lo = N->getOperand(i);
807 SDValue Hi = N->getOperand(i+1);
808 if (TLI.isBigEndian())
810 NewElts.push_back(JoinIntegers(Lo, Hi));
813 SDValue NewVec = DAG.getNode(ISD::BUILD_VECTOR, dl,
814 MVT::getVectorVT(NewVT, NewElts.size()),
815 &NewElts[0], NewElts.size());
817 // Convert the new vector to the old vector type.
818 return DAG.getNode(ISD::BIT_CONVERT, dl, VecVT, NewVec);
821 SDValue DAGTypeLegalizer::PromoteIntOp_CONVERT_RNDSAT(SDNode *N) {
822 ISD::CvtCode CvtCode = cast<CvtRndSatSDNode>(N)->getCvtCode();
823 assert ((CvtCode == ISD::CVT_SS || CvtCode == ISD::CVT_SU ||
824 CvtCode == ISD::CVT_US || CvtCode == ISD::CVT_UU ||
825 CvtCode == ISD::CVT_FS || CvtCode == ISD::CVT_FU) &&
826 "can only promote integer arguments");
827 SDValue InOp = GetPromotedInteger(N->getOperand(0));
828 return DAG.getConvertRndSat(N->getValueType(0), N->getDebugLoc(), InOp,
829 N->getOperand(1), N->getOperand(2),
830 N->getOperand(3), N->getOperand(4), CvtCode);
833 SDValue DAGTypeLegalizer::PromoteIntOp_INSERT_VECTOR_ELT(SDNode *N,
836 // Promote the inserted value. This is valid because the type does not
837 // have to match the vector element type.
839 // Check that any extra bits introduced will be truncated away.
840 assert(N->getOperand(1).getValueType().getSizeInBits() >=
841 N->getValueType(0).getVectorElementType().getSizeInBits() &&
842 "Type of inserted value narrower than vector element type!");
843 return DAG.UpdateNodeOperands(SDValue(N, 0), N->getOperand(0),
844 GetPromotedInteger(N->getOperand(1)),
848 assert(OpNo == 2 && "Different operand and result vector types?");
850 // Promote the index.
851 SDValue Idx = ZExtPromotedInteger(N->getOperand(2));
852 return DAG.UpdateNodeOperands(SDValue(N, 0), N->getOperand(0),
853 N->getOperand(1), Idx);
856 SDValue DAGTypeLegalizer::PromoteIntOp_MEMBARRIER(SDNode *N) {
858 DebugLoc dl = N->getDebugLoc();
859 NewOps[0] = N->getOperand(0);
860 for (unsigned i = 1; i < array_lengthof(NewOps); ++i) {
861 SDValue Flag = GetPromotedInteger(N->getOperand(i));
862 NewOps[i] = DAG.getZeroExtendInReg(Flag, dl, MVT::i1);
864 return DAG.UpdateNodeOperands(SDValue (N, 0), NewOps,
865 array_lengthof(NewOps));
868 SDValue DAGTypeLegalizer::PromoteIntOp_SELECT(SDNode *N, unsigned OpNo) {
869 assert(OpNo == 0 && "Only know how to promote condition");
871 // Promote all the way up to the canonical SetCC type.
872 MVT SVT = TLI.getSetCCResultType(N->getOperand(1).getValueType());
873 SDValue Cond = PromoteTargetBoolean(N->getOperand(0), SVT);
875 return DAG.UpdateNodeOperands(SDValue(N, 0), Cond,
876 N->getOperand(1), N->getOperand(2));
879 SDValue DAGTypeLegalizer::PromoteIntOp_SELECT_CC(SDNode *N, unsigned OpNo) {
880 assert(OpNo == 0 && "Don't know how to promote this operand!");
882 SDValue LHS = N->getOperand(0);
883 SDValue RHS = N->getOperand(1);
884 PromoteSetCCOperands(LHS, RHS, cast<CondCodeSDNode>(N->getOperand(4))->get());
886 // The CC (#4) and the possible return values (#2 and #3) have legal types.
887 return DAG.UpdateNodeOperands(SDValue(N, 0), LHS, RHS, N->getOperand(2),
888 N->getOperand(3), N->getOperand(4));
891 SDValue DAGTypeLegalizer::PromoteIntOp_SETCC(SDNode *N, unsigned OpNo) {
892 assert(OpNo == 0 && "Don't know how to promote this operand!");
894 SDValue LHS = N->getOperand(0);
895 SDValue RHS = N->getOperand(1);
896 PromoteSetCCOperands(LHS, RHS, cast<CondCodeSDNode>(N->getOperand(2))->get());
898 // The CC (#2) is always legal.
899 return DAG.UpdateNodeOperands(SDValue(N, 0), LHS, RHS, N->getOperand(2));
902 SDValue DAGTypeLegalizer::PromoteIntOp_Shift(SDNode *N) {
903 return DAG.UpdateNodeOperands(SDValue(N, 0), N->getOperand(0),
904 ZExtPromotedInteger(N->getOperand(1)));
907 SDValue DAGTypeLegalizer::PromoteIntOp_SIGN_EXTEND(SDNode *N) {
908 SDValue Op = GetPromotedInteger(N->getOperand(0));
909 DebugLoc dl = N->getDebugLoc();
910 Op = DAG.getNode(ISD::ANY_EXTEND, dl, N->getValueType(0), Op);
911 return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Op.getValueType(),
912 Op, DAG.getValueType(N->getOperand(0).getValueType()));
915 SDValue DAGTypeLegalizer::PromoteIntOp_SINT_TO_FP(SDNode *N) {
916 return DAG.UpdateNodeOperands(SDValue(N, 0),
917 SExtPromotedInteger(N->getOperand(0)));
920 SDValue DAGTypeLegalizer::PromoteIntOp_STORE(StoreSDNode *N, unsigned OpNo){
921 assert(ISD::isUNINDEXEDStore(N) && "Indexed store during type legalization!");
922 SDValue Ch = N->getChain(), Ptr = N->getBasePtr();
923 int SVOffset = N->getSrcValueOffset();
924 unsigned Alignment = N->getAlignment();
925 bool isVolatile = N->isVolatile();
926 DebugLoc dl = N->getDebugLoc();
928 SDValue Val = GetPromotedInteger(N->getValue()); // Get promoted value.
930 // Truncate the value and store the result.
931 return DAG.getTruncStore(Ch, dl, Val, Ptr, N->getSrcValue(),
932 SVOffset, N->getMemoryVT(),
933 isVolatile, Alignment);
936 SDValue DAGTypeLegalizer::PromoteIntOp_TRUNCATE(SDNode *N) {
937 SDValue Op = GetPromotedInteger(N->getOperand(0));
938 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), N->getValueType(0), Op);
941 SDValue DAGTypeLegalizer::PromoteIntOp_UINT_TO_FP(SDNode *N) {
942 return DAG.UpdateNodeOperands(SDValue(N, 0),
943 ZExtPromotedInteger(N->getOperand(0)));
946 SDValue DAGTypeLegalizer::PromoteIntOp_ZERO_EXTEND(SDNode *N) {
947 DebugLoc dl = N->getDebugLoc();
948 SDValue Op = GetPromotedInteger(N->getOperand(0));
949 Op = DAG.getNode(ISD::ANY_EXTEND, dl, N->getValueType(0), Op);
950 return DAG.getZeroExtendInReg(Op, dl, N->getOperand(0).getValueType());
954 //===----------------------------------------------------------------------===//
955 // Integer Result Expansion
956 //===----------------------------------------------------------------------===//
958 /// ExpandIntegerResult - This method is called when the specified result of the
959 /// specified node is found to need expansion. At this point, the node may also
960 /// have invalid operands or may have other results that need promotion, we just
961 /// know that (at least) one result needs expansion.
962 void DAGTypeLegalizer::ExpandIntegerResult(SDNode *N, unsigned ResNo) {
963 DEBUG(cerr << "Expand integer result: "; N->dump(&DAG); cerr << "\n");
967 // See if the target wants to custom expand this node.
968 if (CustomLowerResults(N, N->getValueType(ResNo), true))
971 switch (N->getOpcode()) {
974 cerr << "ExpandIntegerResult #" << ResNo << ": ";
975 N->dump(&DAG); cerr << "\n";
977 assert(0 && "Do not know how to expand the result of this operator!");
980 case ISD::MERGE_VALUES: SplitRes_MERGE_VALUES(N, Lo, Hi); break;
981 case ISD::SELECT: SplitRes_SELECT(N, Lo, Hi); break;
982 case ISD::SELECT_CC: SplitRes_SELECT_CC(N, Lo, Hi); break;
983 case ISD::UNDEF: SplitRes_UNDEF(N, Lo, Hi); break;
985 case ISD::BIT_CONVERT: ExpandRes_BIT_CONVERT(N, Lo, Hi); break;
986 case ISD::BUILD_PAIR: ExpandRes_BUILD_PAIR(N, Lo, Hi); break;
987 case ISD::EXTRACT_ELEMENT: ExpandRes_EXTRACT_ELEMENT(N, Lo, Hi); break;
988 case ISD::EXTRACT_VECTOR_ELT: ExpandRes_EXTRACT_VECTOR_ELT(N, Lo, Hi); break;
989 case ISD::VAARG: ExpandRes_VAARG(N, Lo, Hi); break;
991 case ISD::ANY_EXTEND: ExpandIntRes_ANY_EXTEND(N, Lo, Hi); break;
992 case ISD::AssertSext: ExpandIntRes_AssertSext(N, Lo, Hi); break;
993 case ISD::AssertZext: ExpandIntRes_AssertZext(N, Lo, Hi); break;
994 case ISD::BSWAP: ExpandIntRes_BSWAP(N, Lo, Hi); break;
995 case ISD::Constant: ExpandIntRes_Constant(N, Lo, Hi); break;
996 case ISD::CTLZ: ExpandIntRes_CTLZ(N, Lo, Hi); break;
997 case ISD::CTPOP: ExpandIntRes_CTPOP(N, Lo, Hi); break;
998 case ISD::CTTZ: ExpandIntRes_CTTZ(N, Lo, Hi); break;
999 case ISD::FP_TO_SINT: ExpandIntRes_FP_TO_SINT(N, Lo, Hi); break;
1000 case ISD::FP_TO_UINT: ExpandIntRes_FP_TO_UINT(N, Lo, Hi); break;
1001 case ISD::LOAD: ExpandIntRes_LOAD(cast<LoadSDNode>(N), Lo, Hi); break;
1002 case ISD::MUL: ExpandIntRes_MUL(N, Lo, Hi); break;
1003 case ISD::SDIV: ExpandIntRes_SDIV(N, Lo, Hi); break;
1004 case ISD::SIGN_EXTEND: ExpandIntRes_SIGN_EXTEND(N, Lo, Hi); break;
1005 case ISD::SIGN_EXTEND_INREG: ExpandIntRes_SIGN_EXTEND_INREG(N, Lo, Hi); break;
1006 case ISD::SREM: ExpandIntRes_SREM(N, Lo, Hi); break;
1007 case ISD::TRUNCATE: ExpandIntRes_TRUNCATE(N, Lo, Hi); break;
1008 case ISD::UDIV: ExpandIntRes_UDIV(N, Lo, Hi); break;
1009 case ISD::UREM: ExpandIntRes_UREM(N, Lo, Hi); break;
1010 case ISD::ZERO_EXTEND: ExpandIntRes_ZERO_EXTEND(N, Lo, Hi); break;
1014 case ISD::XOR: ExpandIntRes_Logical(N, Lo, Hi); break;
1017 case ISD::SUB: ExpandIntRes_ADDSUB(N, Lo, Hi); break;
1020 case ISD::SUBC: ExpandIntRes_ADDSUBC(N, Lo, Hi); break;
1023 case ISD::SUBE: ExpandIntRes_ADDSUBE(N, Lo, Hi); break;
1027 case ISD::SRL: ExpandIntRes_Shift(N, Lo, Hi); break;
1030 // If Lo/Hi is null, the sub-method took care of registering results etc.
1032 SetExpandedInteger(SDValue(N, ResNo), Lo, Hi);
1035 /// ExpandShiftByConstant - N is a shift by a value that needs to be expanded,
1036 /// and the shift amount is a constant 'Amt'. Expand the operation.
1037 void DAGTypeLegalizer::ExpandShiftByConstant(SDNode *N, unsigned Amt,
1038 SDValue &Lo, SDValue &Hi) {
1039 DebugLoc dl = N->getDebugLoc();
1040 // Expand the incoming operand to be shifted, so that we have its parts
1042 GetExpandedInteger(N->getOperand(0), InL, InH);
1044 MVT NVT = InL.getValueType();
1045 unsigned VTBits = N->getValueType(0).getSizeInBits();
1046 unsigned NVTBits = NVT.getSizeInBits();
1047 MVT ShTy = N->getOperand(1).getValueType();
1049 if (N->getOpcode() == ISD::SHL) {
1051 Lo = Hi = DAG.getConstant(0, NVT);
1052 } else if (Amt > NVTBits) {
1053 Lo = DAG.getConstant(0, NVT);
1054 Hi = DAG.getNode(ISD::SHL, dl,
1055 NVT, InL, DAG.getConstant(Amt-NVTBits,ShTy));
1056 } else if (Amt == NVTBits) {
1057 Lo = DAG.getConstant(0, NVT);
1059 } else if (Amt == 1 &&
1060 TLI.isOperationLegalOrCustom(ISD::ADDC,
1061 TLI.getTypeToExpandTo(NVT))) {
1062 // Emit this X << 1 as X+X.
1063 SDVTList VTList = DAG.getVTList(NVT, MVT::Flag);
1064 SDValue LoOps[2] = { InL, InL };
1065 Lo = DAG.getNode(ISD::ADDC, dl, VTList, LoOps, 2);
1066 SDValue HiOps[3] = { InH, InH, Lo.getValue(1) };
1067 Hi = DAG.getNode(ISD::ADDE, dl, VTList, HiOps, 3);
1069 Lo = DAG.getNode(ISD::SHL, dl, NVT, InL, DAG.getConstant(Amt, ShTy));
1070 Hi = DAG.getNode(ISD::OR, dl, NVT,
1071 DAG.getNode(ISD::SHL, dl, NVT, InH,
1072 DAG.getConstant(Amt, ShTy)),
1073 DAG.getNode(ISD::SRL, dl, NVT, InL,
1074 DAG.getConstant(NVTBits-Amt, ShTy)));
1079 if (N->getOpcode() == ISD::SRL) {
1081 Lo = DAG.getConstant(0, NVT);
1082 Hi = DAG.getConstant(0, NVT);
1083 } else if (Amt > NVTBits) {
1084 Lo = DAG.getNode(ISD::SRL, dl,
1085 NVT, InH, DAG.getConstant(Amt-NVTBits,ShTy));
1086 Hi = DAG.getConstant(0, NVT);
1087 } else if (Amt == NVTBits) {
1089 Hi = DAG.getConstant(0, NVT);
1091 Lo = DAG.getNode(ISD::OR, dl, NVT,
1092 DAG.getNode(ISD::SRL, dl, NVT, InL,
1093 DAG.getConstant(Amt, ShTy)),
1094 DAG.getNode(ISD::SHL, dl, NVT, InH,
1095 DAG.getConstant(NVTBits-Amt, ShTy)));
1096 Hi = DAG.getNode(ISD::SRL, dl, NVT, InH, DAG.getConstant(Amt, ShTy));
1101 assert(N->getOpcode() == ISD::SRA && "Unknown shift!");
1103 Hi = Lo = DAG.getNode(ISD::SRA, dl, NVT, InH,
1104 DAG.getConstant(NVTBits-1, ShTy));
1105 } else if (Amt > NVTBits) {
1106 Lo = DAG.getNode(ISD::SRA, dl, NVT, InH,
1107 DAG.getConstant(Amt-NVTBits, ShTy));
1108 Hi = DAG.getNode(ISD::SRA, dl, NVT, InH,
1109 DAG.getConstant(NVTBits-1, ShTy));
1110 } else if (Amt == NVTBits) {
1112 Hi = DAG.getNode(ISD::SRA, dl, NVT, InH,
1113 DAG.getConstant(NVTBits-1, ShTy));
1115 Lo = DAG.getNode(ISD::OR, dl, NVT,
1116 DAG.getNode(ISD::SRL, dl, NVT, InL,
1117 DAG.getConstant(Amt, ShTy)),
1118 DAG.getNode(ISD::SHL, dl, NVT, InH,
1119 DAG.getConstant(NVTBits-Amt, ShTy)));
1120 Hi = DAG.getNode(ISD::SRA, dl, NVT, InH, DAG.getConstant(Amt, ShTy));
1124 /// ExpandShiftWithKnownAmountBit - Try to determine whether we can simplify
1125 /// this shift based on knowledge of the high bit of the shift amount. If we
1126 /// can tell this, we know that it is >= 32 or < 32, without knowing the actual
1128 bool DAGTypeLegalizer::
1129 ExpandShiftWithKnownAmountBit(SDNode *N, SDValue &Lo, SDValue &Hi) {
1130 SDValue Amt = N->getOperand(1);
1131 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
1132 MVT ShTy = Amt.getValueType();
1133 unsigned ShBits = ShTy.getSizeInBits();
1134 unsigned NVTBits = NVT.getSizeInBits();
1135 assert(isPowerOf2_32(NVTBits) &&
1136 "Expanded integer type size not a power of two!");
1137 DebugLoc dl = N->getDebugLoc();
1139 APInt HighBitMask = APInt::getHighBitsSet(ShBits, ShBits - Log2_32(NVTBits));
1140 APInt KnownZero, KnownOne;
1141 DAG.ComputeMaskedBits(N->getOperand(1), HighBitMask, KnownZero, KnownOne);
1143 // If we don't know anything about the high bits, exit.
1144 if (((KnownZero|KnownOne) & HighBitMask) == 0)
1147 // Get the incoming operand to be shifted.
1149 GetExpandedInteger(N->getOperand(0), InL, InH);
1151 // If we know that any of the high bits of the shift amount are one, then we
1152 // can do this as a couple of simple shifts.
1153 if (KnownOne.intersects(HighBitMask)) {
1154 // Mask out the high bit, which we know is set.
1155 Amt = DAG.getNode(ISD::AND, dl, ShTy, Amt,
1156 DAG.getConstant(~HighBitMask, ShTy));
1158 switch (N->getOpcode()) {
1159 default: assert(0 && "Unknown shift");
1161 Lo = DAG.getConstant(0, NVT); // Low part is zero.
1162 Hi = DAG.getNode(ISD::SHL, dl, NVT, InL, Amt); // High part from Lo part.
1165 Hi = DAG.getConstant(0, NVT); // Hi part is zero.
1166 Lo = DAG.getNode(ISD::SRL, dl, NVT, InH, Amt); // Lo part from Hi part.
1169 Hi = DAG.getNode(ISD::SRA, dl, NVT, InH, // Sign extend high part.
1170 DAG.getConstant(NVTBits-1, ShTy));
1171 Lo = DAG.getNode(ISD::SRA, dl, NVT, InH, Amt); // Lo part from Hi part.
1177 // FIXME: This code is broken for shifts with a zero amount!
1178 // If we know that all of the high bits of the shift amount are zero, then we
1179 // can do this as a couple of simple shifts.
1180 if ((KnownZero & HighBitMask) == HighBitMask) {
1182 SDValue Amt2 = DAG.getNode(ISD::SUB, ShTy,
1183 DAG.getConstant(NVTBits, ShTy),
1186 switch (N->getOpcode()) {
1187 default: assert(0 && "Unknown shift");
1188 case ISD::SHL: Op1 = ISD::SHL; Op2 = ISD::SRL; break;
1190 case ISD::SRA: Op1 = ISD::SRL; Op2 = ISD::SHL; break;
1193 Lo = DAG.getNode(N->getOpcode(), NVT, InL, Amt);
1194 Hi = DAG.getNode(ISD::OR, NVT,
1195 DAG.getNode(Op1, NVT, InH, Amt),
1196 DAG.getNode(Op2, NVT, InL, Amt2));
1204 void DAGTypeLegalizer::ExpandIntRes_ADDSUB(SDNode *N,
1205 SDValue &Lo, SDValue &Hi) {
1206 DebugLoc dl = N->getDebugLoc();
1207 // Expand the subcomponents.
1208 SDValue LHSL, LHSH, RHSL, RHSH;
1209 GetExpandedInteger(N->getOperand(0), LHSL, LHSH);
1210 GetExpandedInteger(N->getOperand(1), RHSL, RHSH);
1212 MVT NVT = LHSL.getValueType();
1213 SDValue LoOps[2] = { LHSL, RHSL };
1214 SDValue HiOps[3] = { LHSH, RHSH };
1216 // Do not generate ADDC/ADDE or SUBC/SUBE if the target does not support
1217 // them. TODO: Teach operation legalization how to expand unsupported
1218 // ADDC/ADDE/SUBC/SUBE. The problem is that these operations generate
1219 // a carry of type MVT::Flag, but there doesn't seem to be any way to
1220 // generate a value of this type in the expanded code sequence.
1222 TLI.isOperationLegalOrCustom(N->getOpcode() == ISD::ADD ?
1223 ISD::ADDC : ISD::SUBC,
1224 TLI.getTypeToExpandTo(NVT));
1227 SDVTList VTList = DAG.getVTList(NVT, MVT::Flag);
1228 if (N->getOpcode() == ISD::ADD) {
1229 Lo = DAG.getNode(ISD::ADDC, dl, VTList, LoOps, 2);
1230 HiOps[2] = Lo.getValue(1);
1231 Hi = DAG.getNode(ISD::ADDE, dl, VTList, HiOps, 3);
1233 Lo = DAG.getNode(ISD::SUBC, dl, VTList, LoOps, 2);
1234 HiOps[2] = Lo.getValue(1);
1235 Hi = DAG.getNode(ISD::SUBE, dl, VTList, HiOps, 3);
1238 if (N->getOpcode() == ISD::ADD) {
1239 Lo = DAG.getNode(ISD::ADD, dl, NVT, LoOps, 2);
1240 Hi = DAG.getNode(ISD::ADD, dl, NVT, HiOps, 2);
1241 SDValue Cmp1 = DAG.getSetCC(dl, TLI.getSetCCResultType(NVT), Lo, LoOps[0],
1243 SDValue Carry1 = DAG.getNode(ISD::SELECT, dl, NVT, Cmp1,
1244 DAG.getConstant(1, NVT),
1245 DAG.getConstant(0, NVT));
1246 SDValue Cmp2 = DAG.getSetCC(dl, TLI.getSetCCResultType(NVT), Lo, LoOps[1],
1248 SDValue Carry2 = DAG.getNode(ISD::SELECT, dl, NVT, Cmp2,
1249 DAG.getConstant(1, NVT), Carry1);
1250 Hi = DAG.getNode(ISD::ADD, dl, NVT, Hi, Carry2);
1252 Lo = DAG.getNode(ISD::SUB, dl, NVT, LoOps, 2);
1253 Hi = DAG.getNode(ISD::SUB, dl, NVT, HiOps, 2);
1255 DAG.getSetCC(dl, TLI.getSetCCResultType(LoOps[0].getValueType()),
1256 LoOps[0], LoOps[1], ISD::SETULT);
1257 SDValue Borrow = DAG.getNode(ISD::SELECT, dl, NVT, Cmp,
1258 DAG.getConstant(1, NVT),
1259 DAG.getConstant(0, NVT));
1260 Hi = DAG.getNode(ISD::SUB, dl, NVT, Hi, Borrow);
1265 void DAGTypeLegalizer::ExpandIntRes_ADDSUBC(SDNode *N,
1266 SDValue &Lo, SDValue &Hi) {
1267 // Expand the subcomponents.
1268 SDValue LHSL, LHSH, RHSL, RHSH;
1269 DebugLoc dl = N->getDebugLoc();
1270 GetExpandedInteger(N->getOperand(0), LHSL, LHSH);
1271 GetExpandedInteger(N->getOperand(1), RHSL, RHSH);
1272 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag);
1273 SDValue LoOps[2] = { LHSL, RHSL };
1274 SDValue HiOps[3] = { LHSH, RHSH };
1276 if (N->getOpcode() == ISD::ADDC) {
1277 Lo = DAG.getNode(ISD::ADDC, dl, VTList, LoOps, 2);
1278 HiOps[2] = Lo.getValue(1);
1279 Hi = DAG.getNode(ISD::ADDE, dl, VTList, HiOps, 3);
1281 Lo = DAG.getNode(ISD::SUBC, dl, VTList, LoOps, 2);
1282 HiOps[2] = Lo.getValue(1);
1283 Hi = DAG.getNode(ISD::SUBE, dl, VTList, HiOps, 3);
1286 // Legalized the flag result - switch anything that used the old flag to
1288 ReplaceValueWith(SDValue(N, 1), Hi.getValue(1));
1291 void DAGTypeLegalizer::ExpandIntRes_ADDSUBE(SDNode *N,
1292 SDValue &Lo, SDValue &Hi) {
1293 // Expand the subcomponents.
1294 SDValue LHSL, LHSH, RHSL, RHSH;
1295 DebugLoc dl = N->getDebugLoc();
1296 GetExpandedInteger(N->getOperand(0), LHSL, LHSH);
1297 GetExpandedInteger(N->getOperand(1), RHSL, RHSH);
1298 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag);
1299 SDValue LoOps[3] = { LHSL, RHSL, N->getOperand(2) };
1300 SDValue HiOps[3] = { LHSH, RHSH };
1302 Lo = DAG.getNode(N->getOpcode(), dl, VTList, LoOps, 3);
1303 HiOps[2] = Lo.getValue(1);
1304 Hi = DAG.getNode(N->getOpcode(), dl, VTList, HiOps, 3);
1306 // Legalized the flag result - switch anything that used the old flag to
1308 ReplaceValueWith(SDValue(N, 1), Hi.getValue(1));
1311 void DAGTypeLegalizer::ExpandIntRes_ANY_EXTEND(SDNode *N,
1312 SDValue &Lo, SDValue &Hi) {
1313 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
1314 DebugLoc dl = N->getDebugLoc();
1315 SDValue Op = N->getOperand(0);
1316 if (Op.getValueType().bitsLE(NVT)) {
1317 // The low part is any extension of the input (which degenerates to a copy).
1318 Lo = DAG.getNode(ISD::ANY_EXTEND, dl, NVT, Op);
1319 Hi = DAG.getUNDEF(NVT); // The high part is undefined.
1321 // For example, extension of an i48 to an i64. The operand type necessarily
1322 // promotes to the result type, so will end up being expanded too.
1323 assert(getTypeAction(Op.getValueType()) == PromoteInteger &&
1324 "Only know how to promote this result!");
1325 SDValue Res = GetPromotedInteger(Op);
1326 assert(Res.getValueType() == N->getValueType(0) &&
1327 "Operand over promoted?");
1328 // Split the promoted operand. This will simplify when it is expanded.
1329 SplitInteger(Res, Lo, Hi);
1333 void DAGTypeLegalizer::ExpandIntRes_AssertSext(SDNode *N,
1334 SDValue &Lo, SDValue &Hi) {
1335 DebugLoc dl = N->getDebugLoc();
1336 GetExpandedInteger(N->getOperand(0), Lo, Hi);
1337 MVT NVT = Lo.getValueType();
1338 MVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
1339 unsigned NVTBits = NVT.getSizeInBits();
1340 unsigned EVTBits = EVT.getSizeInBits();
1342 if (NVTBits < EVTBits) {
1343 Hi = DAG.getNode(ISD::AssertSext, dl, NVT, Hi,
1344 DAG.getValueType(MVT::getIntegerVT(EVTBits - NVTBits)));
1346 Lo = DAG.getNode(ISD::AssertSext, dl, NVT, Lo, DAG.getValueType(EVT));
1347 // The high part replicates the sign bit of Lo, make it explicit.
1348 Hi = DAG.getNode(ISD::SRA, dl, NVT, Lo,
1349 DAG.getConstant(NVTBits-1, TLI.getPointerTy()));
1353 void DAGTypeLegalizer::ExpandIntRes_AssertZext(SDNode *N,
1354 SDValue &Lo, SDValue &Hi) {
1355 DebugLoc dl = N->getDebugLoc();
1356 GetExpandedInteger(N->getOperand(0), Lo, Hi);
1357 MVT NVT = Lo.getValueType();
1358 MVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
1359 unsigned NVTBits = NVT.getSizeInBits();
1360 unsigned EVTBits = EVT.getSizeInBits();
1362 if (NVTBits < EVTBits) {
1363 Hi = DAG.getNode(ISD::AssertZext, dl, NVT, Hi,
1364 DAG.getValueType(MVT::getIntegerVT(EVTBits - NVTBits)));
1366 Lo = DAG.getNode(ISD::AssertZext, dl, NVT, Lo, DAG.getValueType(EVT));
1367 // The high part must be zero, make it explicit.
1368 Hi = DAG.getConstant(0, NVT);
1372 void DAGTypeLegalizer::ExpandIntRes_BSWAP(SDNode *N,
1373 SDValue &Lo, SDValue &Hi) {
1374 DebugLoc dl = N->getDebugLoc();
1375 GetExpandedInteger(N->getOperand(0), Hi, Lo); // Note swapped operands.
1376 Lo = DAG.getNode(ISD::BSWAP, dl, Lo.getValueType(), Lo);
1377 Hi = DAG.getNode(ISD::BSWAP, dl, Hi.getValueType(), Hi);
1380 void DAGTypeLegalizer::ExpandIntRes_Constant(SDNode *N,
1381 SDValue &Lo, SDValue &Hi) {
1382 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
1383 unsigned NBitWidth = NVT.getSizeInBits();
1384 const APInt &Cst = cast<ConstantSDNode>(N)->getAPIntValue();
1385 Lo = DAG.getConstant(APInt(Cst).trunc(NBitWidth), NVT);
1386 Hi = DAG.getConstant(Cst.lshr(NBitWidth).trunc(NBitWidth), NVT);
1389 void DAGTypeLegalizer::ExpandIntRes_CTLZ(SDNode *N,
1390 SDValue &Lo, SDValue &Hi) {
1391 DebugLoc dl = N->getDebugLoc();
1392 // ctlz (HiLo) -> Hi != 0 ? ctlz(Hi) : (ctlz(Lo)+32)
1393 GetExpandedInteger(N->getOperand(0), Lo, Hi);
1394 MVT NVT = Lo.getValueType();
1396 SDValue HiNotZero = DAG.getSetCC(dl, TLI.getSetCCResultType(NVT), Hi,
1397 DAG.getConstant(0, NVT), ISD::SETNE);
1399 SDValue LoLZ = DAG.getNode(ISD::CTLZ, dl, NVT, Lo);
1400 SDValue HiLZ = DAG.getNode(ISD::CTLZ, dl, NVT, Hi);
1402 Lo = DAG.getNode(ISD::SELECT, dl, NVT, HiNotZero, HiLZ,
1403 DAG.getNode(ISD::ADD, dl, NVT, LoLZ,
1404 DAG.getConstant(NVT.getSizeInBits(), NVT)));
1405 Hi = DAG.getConstant(0, NVT);
1408 void DAGTypeLegalizer::ExpandIntRes_CTPOP(SDNode *N,
1409 SDValue &Lo, SDValue &Hi) {
1410 DebugLoc dl = N->getDebugLoc();
1411 // ctpop(HiLo) -> ctpop(Hi)+ctpop(Lo)
1412 GetExpandedInteger(N->getOperand(0), Lo, Hi);
1413 MVT NVT = Lo.getValueType();
1414 Lo = DAG.getNode(ISD::ADD, dl, NVT, DAG.getNode(ISD::CTPOP, dl, NVT, Lo),
1415 DAG.getNode(ISD::CTPOP, dl, NVT, Hi));
1416 Hi = DAG.getConstant(0, NVT);
1419 void DAGTypeLegalizer::ExpandIntRes_CTTZ(SDNode *N,
1420 SDValue &Lo, SDValue &Hi) {
1421 DebugLoc dl = N->getDebugLoc();
1422 // cttz (HiLo) -> Lo != 0 ? cttz(Lo) : (cttz(Hi)+32)
1423 GetExpandedInteger(N->getOperand(0), Lo, Hi);
1424 MVT NVT = Lo.getValueType();
1426 SDValue LoNotZero = DAG.getSetCC(dl, TLI.getSetCCResultType(NVT), Lo,
1427 DAG.getConstant(0, NVT), ISD::SETNE);
1429 SDValue LoLZ = DAG.getNode(ISD::CTTZ, dl, NVT, Lo);
1430 SDValue HiLZ = DAG.getNode(ISD::CTTZ, dl, NVT, Hi);
1432 Lo = DAG.getNode(ISD::SELECT, dl, NVT, LoNotZero, LoLZ,
1433 DAG.getNode(ISD::ADD, dl, NVT, HiLZ,
1434 DAG.getConstant(NVT.getSizeInBits(), NVT)));
1435 Hi = DAG.getConstant(0, NVT);
1438 void DAGTypeLegalizer::ExpandIntRes_FP_TO_SINT(SDNode *N, SDValue &Lo,
1440 DebugLoc dl = N->getDebugLoc();
1441 MVT VT = N->getValueType(0);
1442 SDValue Op = N->getOperand(0);
1443 RTLIB::Libcall LC = RTLIB::getFPTOSINT(Op.getValueType(), VT);
1444 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected fp-to-sint conversion!");
1445 SplitInteger(MakeLibCall(LC, VT, &Op, 1, true/*irrelevant*/, dl), Lo, Hi);
1448 void DAGTypeLegalizer::ExpandIntRes_FP_TO_UINT(SDNode *N, SDValue &Lo,
1450 DebugLoc dl = N->getDebugLoc();
1451 MVT VT = N->getValueType(0);
1452 SDValue Op = N->getOperand(0);
1453 RTLIB::Libcall LC = RTLIB::getFPTOUINT(Op.getValueType(), VT);
1454 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected fp-to-uint conversion!");
1455 SplitInteger(MakeLibCall(LC, VT, &Op, 1, false/*irrelevant*/, dl), Lo, Hi);
1458 void DAGTypeLegalizer::ExpandIntRes_LOAD(LoadSDNode *N,
1459 SDValue &Lo, SDValue &Hi) {
1460 if (ISD::isNormalLoad(N)) {
1461 ExpandRes_NormalLoad(N, Lo, Hi);
1465 assert(ISD::isUNINDEXEDLoad(N) && "Indexed load during type legalization!");
1467 MVT VT = N->getValueType(0);
1468 MVT NVT = TLI.getTypeToTransformTo(VT);
1469 SDValue Ch = N->getChain();
1470 SDValue Ptr = N->getBasePtr();
1471 ISD::LoadExtType ExtType = N->getExtensionType();
1472 int SVOffset = N->getSrcValueOffset();
1473 unsigned Alignment = N->getAlignment();
1474 bool isVolatile = N->isVolatile();
1475 DebugLoc dl = N->getDebugLoc();
1477 assert(NVT.isByteSized() && "Expanded type not byte sized!");
1479 if (N->getMemoryVT().bitsLE(NVT)) {
1480 MVT EVT = N->getMemoryVT();
1482 Lo = DAG.getExtLoad(ExtType, dl, NVT, Ch, Ptr, N->getSrcValue(), SVOffset,
1483 EVT, isVolatile, Alignment);
1485 // Remember the chain.
1486 Ch = Lo.getValue(1);
1488 if (ExtType == ISD::SEXTLOAD) {
1489 // The high part is obtained by SRA'ing all but one of the bits of the
1491 unsigned LoSize = Lo.getValueType().getSizeInBits();
1492 Hi = DAG.getNode(ISD::SRA, dl, NVT, Lo,
1493 DAG.getConstant(LoSize-1, TLI.getPointerTy()));
1494 } else if (ExtType == ISD::ZEXTLOAD) {
1495 // The high part is just a zero.
1496 Hi = DAG.getConstant(0, NVT);
1498 assert(ExtType == ISD::EXTLOAD && "Unknown extload!");
1499 // The high part is undefined.
1500 Hi = DAG.getUNDEF(NVT);
1502 } else if (TLI.isLittleEndian()) {
1503 // Little-endian - low bits are at low addresses.
1504 Lo = DAG.getLoad(NVT, dl, Ch, Ptr, N->getSrcValue(), SVOffset,
1505 isVolatile, Alignment);
1507 unsigned ExcessBits =
1508 N->getMemoryVT().getSizeInBits() - NVT.getSizeInBits();
1509 MVT NEVT = MVT::getIntegerVT(ExcessBits);
1511 // Increment the pointer to the other half.
1512 unsigned IncrementSize = NVT.getSizeInBits()/8;
1513 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
1514 DAG.getIntPtrConstant(IncrementSize));
1515 Hi = DAG.getExtLoad(ExtType, dl, NVT, Ch, Ptr, N->getSrcValue(),
1516 SVOffset+IncrementSize, NEVT,
1517 isVolatile, MinAlign(Alignment, IncrementSize));
1519 // Build a factor node to remember that this load is independent of the
1521 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
1524 // Big-endian - high bits are at low addresses. Favor aligned loads at
1525 // the cost of some bit-fiddling.
1526 MVT EVT = N->getMemoryVT();
1527 unsigned EBytes = EVT.getStoreSizeInBits()/8;
1528 unsigned IncrementSize = NVT.getSizeInBits()/8;
1529 unsigned ExcessBits = (EBytes - IncrementSize)*8;
1531 // Load both the high bits and maybe some of the low bits.
1532 Hi = DAG.getExtLoad(ExtType, dl, NVT, Ch, Ptr, N->getSrcValue(), SVOffset,
1533 MVT::getIntegerVT(EVT.getSizeInBits() - ExcessBits),
1534 isVolatile, Alignment);
1536 // Increment the pointer to the other half.
1537 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
1538 DAG.getIntPtrConstant(IncrementSize));
1539 // Load the rest of the low bits.
1540 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, NVT, Ch, Ptr, N->getSrcValue(),
1541 SVOffset+IncrementSize,
1542 MVT::getIntegerVT(ExcessBits),
1543 isVolatile, MinAlign(Alignment, IncrementSize));
1545 // Build a factor node to remember that this load is independent of the
1547 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
1550 if (ExcessBits < NVT.getSizeInBits()) {
1551 // Transfer low bits from the bottom of Hi to the top of Lo.
1552 Lo = DAG.getNode(ISD::OR, dl, NVT, Lo,
1553 DAG.getNode(ISD::SHL, dl, NVT, Hi,
1554 DAG.getConstant(ExcessBits,
1555 TLI.getPointerTy())));
1556 // Move high bits to the right position in Hi.
1557 Hi = DAG.getNode(ExtType == ISD::SEXTLOAD ? ISD::SRA : ISD::SRL, dl,
1559 DAG.getConstant(NVT.getSizeInBits() - ExcessBits,
1560 TLI.getPointerTy()));
1564 // Legalized the chain result - switch anything that used the old chain to
1566 ReplaceValueWith(SDValue(N, 1), Ch);
1569 void DAGTypeLegalizer::ExpandIntRes_Logical(SDNode *N,
1570 SDValue &Lo, SDValue &Hi) {
1571 DebugLoc dl = N->getDebugLoc();
1572 SDValue LL, LH, RL, RH;
1573 GetExpandedInteger(N->getOperand(0), LL, LH);
1574 GetExpandedInteger(N->getOperand(1), RL, RH);
1575 Lo = DAG.getNode(N->getOpcode(), dl, LL.getValueType(), LL, RL);
1576 Hi = DAG.getNode(N->getOpcode(), dl, LL.getValueType(), LH, RH);
1579 void DAGTypeLegalizer::ExpandIntRes_MUL(SDNode *N,
1580 SDValue &Lo, SDValue &Hi) {
1581 MVT VT = N->getValueType(0);
1582 MVT NVT = TLI.getTypeToTransformTo(VT);
1583 DebugLoc dl = N->getDebugLoc();
1585 bool HasMULHS = TLI.isOperationLegalOrCustom(ISD::MULHS, NVT);
1586 bool HasMULHU = TLI.isOperationLegalOrCustom(ISD::MULHU, NVT);
1587 bool HasSMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::SMUL_LOHI, NVT);
1588 bool HasUMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::UMUL_LOHI, NVT);
1589 if (HasMULHU || HasMULHS || HasUMUL_LOHI || HasSMUL_LOHI) {
1590 SDValue LL, LH, RL, RH;
1591 GetExpandedInteger(N->getOperand(0), LL, LH);
1592 GetExpandedInteger(N->getOperand(1), RL, RH);
1593 unsigned OuterBitSize = VT.getSizeInBits();
1594 unsigned InnerBitSize = NVT.getSizeInBits();
1595 unsigned LHSSB = DAG.ComputeNumSignBits(N->getOperand(0));
1596 unsigned RHSSB = DAG.ComputeNumSignBits(N->getOperand(1));
1598 APInt HighMask = APInt::getHighBitsSet(OuterBitSize, InnerBitSize);
1599 if (DAG.MaskedValueIsZero(N->getOperand(0), HighMask) &&
1600 DAG.MaskedValueIsZero(N->getOperand(1), HighMask)) {
1601 // The inputs are both zero-extended.
1603 // We can emit a umul_lohi.
1604 Lo = DAG.getNode(ISD::UMUL_LOHI, dl, DAG.getVTList(NVT, NVT), LL, RL);
1605 Hi = SDValue(Lo.getNode(), 1);
1609 // We can emit a mulhu+mul.
1610 Lo = DAG.getNode(ISD::MUL, dl, NVT, LL, RL);
1611 Hi = DAG.getNode(ISD::MULHU, dl, NVT, LL, RL);
1615 if (LHSSB > InnerBitSize && RHSSB > InnerBitSize) {
1616 // The input values are both sign-extended.
1618 // We can emit a smul_lohi.
1619 Lo = DAG.getNode(ISD::SMUL_LOHI, dl, DAG.getVTList(NVT, NVT), LL, RL);
1620 Hi = SDValue(Lo.getNode(), 1);
1624 // We can emit a mulhs+mul.
1625 Lo = DAG.getNode(ISD::MUL, dl, NVT, LL, RL);
1626 Hi = DAG.getNode(ISD::MULHS, dl, NVT, LL, RL);
1631 // Lo,Hi = umul LHS, RHS.
1632 SDValue UMulLOHI = DAG.getNode(ISD::UMUL_LOHI, dl,
1633 DAG.getVTList(NVT, NVT), LL, RL);
1635 Hi = UMulLOHI.getValue(1);
1636 RH = DAG.getNode(ISD::MUL, dl, NVT, LL, RH);
1637 LH = DAG.getNode(ISD::MUL, dl, NVT, LH, RL);
1638 Hi = DAG.getNode(ISD::ADD, dl, NVT, Hi, RH);
1639 Hi = DAG.getNode(ISD::ADD, dl, NVT, Hi, LH);
1643 Lo = DAG.getNode(ISD::MUL, dl, NVT, LL, RL);
1644 Hi = DAG.getNode(ISD::MULHU, dl, NVT, LL, RL);
1645 RH = DAG.getNode(ISD::MUL, dl, NVT, LL, RH);
1646 LH = DAG.getNode(ISD::MUL, dl, NVT, LH, RL);
1647 Hi = DAG.getNode(ISD::ADD, dl, NVT, Hi, RH);
1648 Hi = DAG.getNode(ISD::ADD, dl, NVT, Hi, LH);
1653 // If nothing else, we can make a libcall.
1654 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
1656 LC = RTLIB::MUL_I16;
1657 else if (VT == MVT::i32)
1658 LC = RTLIB::MUL_I32;
1659 else if (VT == MVT::i64)
1660 LC = RTLIB::MUL_I64;
1661 else if (VT == MVT::i128)
1662 LC = RTLIB::MUL_I128;
1663 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported MUL!");
1665 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
1666 SplitInteger(MakeLibCall(LC, VT, Ops, 2, true/*irrelevant*/, dl), Lo, Hi);
1669 void DAGTypeLegalizer::ExpandIntRes_SDIV(SDNode *N,
1670 SDValue &Lo, SDValue &Hi) {
1671 MVT VT = N->getValueType(0);
1672 DebugLoc dl = N->getDebugLoc();
1674 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
1676 LC = RTLIB::SDIV_I32;
1677 else if (VT == MVT::i64)
1678 LC = RTLIB::SDIV_I64;
1679 else if (VT == MVT::i128)
1680 LC = RTLIB::SDIV_I128;
1681 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported SDIV!");
1683 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
1684 SplitInteger(MakeLibCall(LC, VT, Ops, 2, true, dl), Lo, Hi);
1687 void DAGTypeLegalizer::ExpandIntRes_Shift(SDNode *N,
1688 SDValue &Lo, SDValue &Hi) {
1689 MVT VT = N->getValueType(0);
1690 DebugLoc dl = N->getDebugLoc();
1692 // If we can emit an efficient shift operation, do so now. Check to see if
1693 // the RHS is a constant.
1694 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N->getOperand(1)))
1695 return ExpandShiftByConstant(N, CN->getZExtValue(), Lo, Hi);
1697 // If we can determine that the high bit of the shift is zero or one, even if
1698 // the low bits are variable, emit this shift in an optimized form.
1699 if (ExpandShiftWithKnownAmountBit(N, Lo, Hi))
1702 // If this target supports shift_PARTS, use it. First, map to the _PARTS opc.
1704 if (N->getOpcode() == ISD::SHL) {
1705 PartsOpc = ISD::SHL_PARTS;
1706 } else if (N->getOpcode() == ISD::SRL) {
1707 PartsOpc = ISD::SRL_PARTS;
1709 assert(N->getOpcode() == ISD::SRA && "Unknown shift!");
1710 PartsOpc = ISD::SRA_PARTS;
1713 // Next check to see if the target supports this SHL_PARTS operation or if it
1714 // will custom expand it.
1715 MVT NVT = TLI.getTypeToTransformTo(VT);
1716 TargetLowering::LegalizeAction Action = TLI.getOperationAction(PartsOpc, NVT);
1717 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) ||
1718 Action == TargetLowering::Custom) {
1719 // Expand the subcomponents.
1721 GetExpandedInteger(N->getOperand(0), LHSL, LHSH);
1723 SDValue Ops[] = { LHSL, LHSH, N->getOperand(1) };
1724 MVT VT = LHSL.getValueType();
1725 Lo = DAG.getNode(PartsOpc, dl, DAG.getNodeValueTypes(VT, VT), 2, Ops, 3);
1726 Hi = Lo.getValue(1);
1730 // Otherwise, emit a libcall.
1731 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
1733 if (N->getOpcode() == ISD::SHL) {
1734 isSigned = false; /*sign irrelevant*/
1736 LC = RTLIB::SHL_I16;
1737 else if (VT == MVT::i32)
1738 LC = RTLIB::SHL_I32;
1739 else if (VT == MVT::i64)
1740 LC = RTLIB::SHL_I64;
1741 else if (VT == MVT::i128)
1742 LC = RTLIB::SHL_I128;
1743 } else if (N->getOpcode() == ISD::SRL) {
1746 LC = RTLIB::SRL_I16;
1747 else if (VT == MVT::i32)
1748 LC = RTLIB::SRL_I32;
1749 else if (VT == MVT::i64)
1750 LC = RTLIB::SRL_I64;
1751 else if (VT == MVT::i128)
1752 LC = RTLIB::SRL_I128;
1754 assert(N->getOpcode() == ISD::SRA && "Unknown shift!");
1757 LC = RTLIB::SRA_I16;
1758 else if (VT == MVT::i32)
1759 LC = RTLIB::SRA_I32;
1760 else if (VT == MVT::i64)
1761 LC = RTLIB::SRA_I64;
1762 else if (VT == MVT::i128)
1763 LC = RTLIB::SRA_I128;
1765 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported shift!");
1767 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
1768 SplitInteger(MakeLibCall(LC, VT, Ops, 2, isSigned, dl), Lo, Hi);
1771 void DAGTypeLegalizer::ExpandIntRes_SIGN_EXTEND(SDNode *N,
1772 SDValue &Lo, SDValue &Hi) {
1773 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
1774 DebugLoc dl = N->getDebugLoc();
1775 SDValue Op = N->getOperand(0);
1776 if (Op.getValueType().bitsLE(NVT)) {
1777 // The low part is sign extension of the input (degenerates to a copy).
1778 Lo = DAG.getNode(ISD::SIGN_EXTEND, dl, NVT, N->getOperand(0));
1779 // The high part is obtained by SRA'ing all but one of the bits of low part.
1780 unsigned LoSize = NVT.getSizeInBits();
1781 Hi = DAG.getNode(ISD::SRA, dl, NVT, Lo,
1782 DAG.getConstant(LoSize-1, TLI.getPointerTy()));
1784 // For example, extension of an i48 to an i64. The operand type necessarily
1785 // promotes to the result type, so will end up being expanded too.
1786 assert(getTypeAction(Op.getValueType()) == PromoteInteger &&
1787 "Only know how to promote this result!");
1788 SDValue Res = GetPromotedInteger(Op);
1789 assert(Res.getValueType() == N->getValueType(0) &&
1790 "Operand over promoted?");
1791 // Split the promoted operand. This will simplify when it is expanded.
1792 SplitInteger(Res, Lo, Hi);
1793 unsigned ExcessBits =
1794 Op.getValueType().getSizeInBits() - NVT.getSizeInBits();
1795 Hi = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Hi.getValueType(), Hi,
1796 DAG.getValueType(MVT::getIntegerVT(ExcessBits)));
1800 void DAGTypeLegalizer::
1801 ExpandIntRes_SIGN_EXTEND_INREG(SDNode *N, SDValue &Lo, SDValue &Hi) {
1802 DebugLoc dl = N->getDebugLoc();
1803 GetExpandedInteger(N->getOperand(0), Lo, Hi);
1804 MVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
1806 if (EVT.bitsLE(Lo.getValueType())) {
1807 // sext_inreg the low part if needed.
1808 Lo = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Lo.getValueType(), Lo,
1811 // The high part gets the sign extension from the lo-part. This handles
1812 // things like sextinreg V:i64 from i8.
1813 Hi = DAG.getNode(ISD::SRA, dl, Hi.getValueType(), Lo,
1814 DAG.getConstant(Hi.getValueType().getSizeInBits()-1,
1815 TLI.getPointerTy()));
1817 // For example, extension of an i48 to an i64. Leave the low part alone,
1818 // sext_inreg the high part.
1819 unsigned ExcessBits =
1820 EVT.getSizeInBits() - Lo.getValueType().getSizeInBits();
1821 Hi = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Hi.getValueType(), Hi,
1822 DAG.getValueType(MVT::getIntegerVT(ExcessBits)));
1826 void DAGTypeLegalizer::ExpandIntRes_SREM(SDNode *N,
1827 SDValue &Lo, SDValue &Hi) {
1828 MVT VT = N->getValueType(0);
1829 DebugLoc dl = N->getDebugLoc();
1831 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
1833 LC = RTLIB::SREM_I32;
1834 else if (VT == MVT::i64)
1835 LC = RTLIB::SREM_I64;
1836 else if (VT == MVT::i128)
1837 LC = RTLIB::SREM_I128;
1838 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported SREM!");
1840 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
1841 SplitInteger(MakeLibCall(LC, VT, Ops, 2, true, dl), Lo, Hi);
1844 void DAGTypeLegalizer::ExpandIntRes_TRUNCATE(SDNode *N,
1845 SDValue &Lo, SDValue &Hi) {
1846 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
1847 DebugLoc dl = N->getDebugLoc();
1848 Lo = DAG.getNode(ISD::TRUNCATE, dl, NVT, N->getOperand(0));
1849 Hi = DAG.getNode(ISD::SRL, dl,
1850 N->getOperand(0).getValueType(), N->getOperand(0),
1851 DAG.getConstant(NVT.getSizeInBits(), TLI.getPointerTy()));
1852 Hi = DAG.getNode(ISD::TRUNCATE, dl, NVT, Hi);
1855 void DAGTypeLegalizer::ExpandIntRes_UDIV(SDNode *N,
1856 SDValue &Lo, SDValue &Hi) {
1857 MVT VT = N->getValueType(0);
1858 DebugLoc dl = N->getDebugLoc();
1860 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
1862 LC = RTLIB::UDIV_I32;
1863 else if (VT == MVT::i64)
1864 LC = RTLIB::UDIV_I64;
1865 else if (VT == MVT::i128)
1866 LC = RTLIB::UDIV_I128;
1867 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported UDIV!");
1869 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
1870 SplitInteger(MakeLibCall(LC, VT, Ops, 2, false, dl), Lo, Hi);
1873 void DAGTypeLegalizer::ExpandIntRes_UREM(SDNode *N,
1874 SDValue &Lo, SDValue &Hi) {
1875 MVT VT = N->getValueType(0);
1876 DebugLoc dl = N->getDebugLoc();
1878 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
1880 LC = RTLIB::UREM_I32;
1881 else if (VT == MVT::i64)
1882 LC = RTLIB::UREM_I64;
1883 else if (VT == MVT::i128)
1884 LC = RTLIB::UREM_I128;
1885 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported UREM!");
1887 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
1888 SplitInteger(MakeLibCall(LC, VT, Ops, 2, false, dl), Lo, Hi);
1891 void DAGTypeLegalizer::ExpandIntRes_ZERO_EXTEND(SDNode *N,
1892 SDValue &Lo, SDValue &Hi) {
1893 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
1894 DebugLoc dl = N->getDebugLoc();
1895 SDValue Op = N->getOperand(0);
1896 if (Op.getValueType().bitsLE(NVT)) {
1897 // The low part is zero extension of the input (degenerates to a copy).
1898 Lo = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, N->getOperand(0));
1899 Hi = DAG.getConstant(0, NVT); // The high part is just a zero.
1901 // For example, extension of an i48 to an i64. The operand type necessarily
1902 // promotes to the result type, so will end up being expanded too.
1903 assert(getTypeAction(Op.getValueType()) == PromoteInteger &&
1904 "Only know how to promote this result!");
1905 SDValue Res = GetPromotedInteger(Op);
1906 assert(Res.getValueType() == N->getValueType(0) &&
1907 "Operand over promoted?");
1908 // Split the promoted operand. This will simplify when it is expanded.
1909 SplitInteger(Res, Lo, Hi);
1910 unsigned ExcessBits =
1911 Op.getValueType().getSizeInBits() - NVT.getSizeInBits();
1912 Hi = DAG.getZeroExtendInReg(Hi, dl, MVT::getIntegerVT(ExcessBits));
1917 //===----------------------------------------------------------------------===//
1918 // Integer Operand Expansion
1919 //===----------------------------------------------------------------------===//
1921 /// ExpandIntegerOperand - This method is called when the specified operand of
1922 /// the specified node is found to need expansion. At this point, all of the
1923 /// result types of the node are known to be legal, but other operands of the
1924 /// node may need promotion or expansion as well as the specified one.
1925 bool DAGTypeLegalizer::ExpandIntegerOperand(SDNode *N, unsigned OpNo) {
1926 DEBUG(cerr << "Expand integer operand: "; N->dump(&DAG); cerr << "\n");
1927 SDValue Res = SDValue();
1929 if (CustomLowerResults(N, N->getOperand(OpNo).getValueType(), false))
1932 switch (N->getOpcode()) {
1935 cerr << "ExpandIntegerOperand Op #" << OpNo << ": ";
1936 N->dump(&DAG); cerr << "\n";
1938 assert(0 && "Do not know how to expand this operator's operand!");
1941 case ISD::BIT_CONVERT: Res = ExpandOp_BIT_CONVERT(N); break;
1942 case ISD::BR_CC: Res = ExpandIntOp_BR_CC(N); break;
1943 case ISD::BUILD_VECTOR: Res = ExpandOp_BUILD_VECTOR(N); break;
1944 case ISD::EXTRACT_ELEMENT: Res = ExpandOp_EXTRACT_ELEMENT(N); break;
1945 case ISD::INSERT_VECTOR_ELT: Res = ExpandOp_INSERT_VECTOR_ELT(N); break;
1946 case ISD::SCALAR_TO_VECTOR: Res = ExpandOp_SCALAR_TO_VECTOR(N); break;
1947 case ISD::SELECT_CC: Res = ExpandIntOp_SELECT_CC(N); break;
1948 case ISD::SETCC: Res = ExpandIntOp_SETCC(N); break;
1949 case ISD::SINT_TO_FP: Res = ExpandIntOp_SINT_TO_FP(N); break;
1950 case ISD::STORE: Res = ExpandIntOp_STORE(cast<StoreSDNode>(N), OpNo); break;
1951 case ISD::TRUNCATE: Res = ExpandIntOp_TRUNCATE(N); break;
1952 case ISD::UINT_TO_FP: Res = ExpandIntOp_UINT_TO_FP(N); break;
1958 case ISD::ROTR: Res = ExpandIntOp_Shift(N); break;
1961 // If the result is null, the sub-method took care of registering results etc.
1962 if (!Res.getNode()) return false;
1964 // If the result is N, the sub-method updated N in place. Tell the legalizer
1966 if (Res.getNode() == N)
1969 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 &&
1970 "Invalid operand expansion");
1972 ReplaceValueWith(SDValue(N, 0), Res);
1976 /// IntegerExpandSetCCOperands - Expand the operands of a comparison. This code
1977 /// is shared among BR_CC, SELECT_CC, and SETCC handlers.
1978 void DAGTypeLegalizer::IntegerExpandSetCCOperands(SDValue &NewLHS,
1980 ISD::CondCode &CCCode,
1982 SDValue LHSLo, LHSHi, RHSLo, RHSHi;
1983 GetExpandedInteger(NewLHS, LHSLo, LHSHi);
1984 GetExpandedInteger(NewRHS, RHSLo, RHSHi);
1986 MVT VT = NewLHS.getValueType();
1988 if (CCCode == ISD::SETEQ || CCCode == ISD::SETNE) {
1989 if (RHSLo == RHSHi) {
1990 if (ConstantSDNode *RHSCST = dyn_cast<ConstantSDNode>(RHSLo)) {
1991 if (RHSCST->isAllOnesValue()) {
1992 // Equality comparison to -1.
1993 NewLHS = DAG.getNode(ISD::AND, dl,
1994 LHSLo.getValueType(), LHSLo, LHSHi);
2001 NewLHS = DAG.getNode(ISD::XOR, dl, LHSLo.getValueType(), LHSLo, RHSLo);
2002 NewRHS = DAG.getNode(ISD::XOR, dl, LHSLo.getValueType(), LHSHi, RHSHi);
2003 NewLHS = DAG.getNode(ISD::OR, dl, NewLHS.getValueType(), NewLHS, NewRHS);
2004 NewRHS = DAG.getConstant(0, NewLHS.getValueType());
2008 // If this is a comparison of the sign bit, just look at the top part.
2010 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(NewRHS))
2011 if ((CCCode == ISD::SETLT && CST->isNullValue()) || // X < 0
2012 (CCCode == ISD::SETGT && CST->isAllOnesValue())) { // X > -1
2018 // FIXME: This generated code sucks.
2019 ISD::CondCode LowCC;
2021 default: assert(0 && "Unknown integer setcc!");
2023 case ISD::SETULT: LowCC = ISD::SETULT; break;
2025 case ISD::SETUGT: LowCC = ISD::SETUGT; break;
2027 case ISD::SETULE: LowCC = ISD::SETULE; break;
2029 case ISD::SETUGE: LowCC = ISD::SETUGE; break;
2032 // Tmp1 = lo(op1) < lo(op2) // Always unsigned comparison
2033 // Tmp2 = hi(op1) < hi(op2) // Signedness depends on operands
2034 // dest = hi(op1) == hi(op2) ? Tmp1 : Tmp2;
2036 // NOTE: on targets without efficient SELECT of bools, we can always use
2037 // this identity: (B1 ? B2 : B3) --> (B1 & B2)|(!B1&B3)
2038 TargetLowering::DAGCombinerInfo DagCombineInfo(DAG, false, true, NULL);
2040 Tmp1 = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSLo.getValueType()),
2041 LHSLo, RHSLo, LowCC, false, DagCombineInfo, dl);
2042 if (!Tmp1.getNode())
2043 Tmp1 = DAG.getSetCC(dl, TLI.getSetCCResultType(LHSLo.getValueType()),
2044 LHSLo, RHSLo, LowCC);
2045 Tmp2 = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSHi.getValueType()),
2046 LHSHi, RHSHi, CCCode, false, DagCombineInfo, dl);
2047 if (!Tmp2.getNode())
2048 Tmp2 = DAG.getNode(ISD::SETCC, dl,
2049 TLI.getSetCCResultType(LHSHi.getValueType()),
2050 LHSHi, RHSHi, DAG.getCondCode(CCCode));
2052 ConstantSDNode *Tmp1C = dyn_cast<ConstantSDNode>(Tmp1.getNode());
2053 ConstantSDNode *Tmp2C = dyn_cast<ConstantSDNode>(Tmp2.getNode());
2054 if ((Tmp1C && Tmp1C->isNullValue()) ||
2055 (Tmp2C && Tmp2C->isNullValue() &&
2056 (CCCode == ISD::SETLE || CCCode == ISD::SETGE ||
2057 CCCode == ISD::SETUGE || CCCode == ISD::SETULE)) ||
2058 (Tmp2C && Tmp2C->getAPIntValue() == 1 &&
2059 (CCCode == ISD::SETLT || CCCode == ISD::SETGT ||
2060 CCCode == ISD::SETUGT || CCCode == ISD::SETULT))) {
2061 // low part is known false, returns high part.
2062 // For LE / GE, if high part is known false, ignore the low part.
2063 // For LT / GT, if high part is known true, ignore the low part.
2069 NewLHS = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSHi.getValueType()),
2070 LHSHi, RHSHi, ISD::SETEQ, false,
2071 DagCombineInfo, dl);
2072 if (!NewLHS.getNode())
2073 NewLHS = DAG.getSetCC(dl, TLI.getSetCCResultType(LHSHi.getValueType()),
2074 LHSHi, RHSHi, ISD::SETEQ);
2075 NewLHS = DAG.getNode(ISD::SELECT, dl, Tmp1.getValueType(),
2076 NewLHS, Tmp1, Tmp2);
2080 SDValue DAGTypeLegalizer::ExpandIntOp_BR_CC(SDNode *N) {
2081 SDValue NewLHS = N->getOperand(2), NewRHS = N->getOperand(3);
2082 ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(1))->get();
2083 IntegerExpandSetCCOperands(NewLHS, NewRHS, CCCode, N->getDebugLoc());
2085 // If ExpandSetCCOperands returned a scalar, we need to compare the result
2086 // against zero to select between true and false values.
2087 if (NewRHS.getNode() == 0) {
2088 NewRHS = DAG.getConstant(0, NewLHS.getValueType());
2089 CCCode = ISD::SETNE;
2092 // Update N to have the operands specified.
2093 return DAG.UpdateNodeOperands(SDValue(N, 0), N->getOperand(0),
2094 DAG.getCondCode(CCCode), NewLHS, NewRHS,
2098 SDValue DAGTypeLegalizer::ExpandIntOp_SELECT_CC(SDNode *N) {
2099 SDValue NewLHS = N->getOperand(0), NewRHS = N->getOperand(1);
2100 ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(4))->get();
2101 IntegerExpandSetCCOperands(NewLHS, NewRHS, CCCode, N->getDebugLoc());
2103 // If ExpandSetCCOperands returned a scalar, we need to compare the result
2104 // against zero to select between true and false values.
2105 if (NewRHS.getNode() == 0) {
2106 NewRHS = DAG.getConstant(0, NewLHS.getValueType());
2107 CCCode = ISD::SETNE;
2110 // Update N to have the operands specified.
2111 return DAG.UpdateNodeOperands(SDValue(N, 0), NewLHS, NewRHS,
2112 N->getOperand(2), N->getOperand(3),
2113 DAG.getCondCode(CCCode));
2116 SDValue DAGTypeLegalizer::ExpandIntOp_SETCC(SDNode *N) {
2117 SDValue NewLHS = N->getOperand(0), NewRHS = N->getOperand(1);
2118 ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(2))->get();
2119 IntegerExpandSetCCOperands(NewLHS, NewRHS, CCCode, N->getDebugLoc());
2121 // If ExpandSetCCOperands returned a scalar, use it.
2122 if (NewRHS.getNode() == 0) {
2123 assert(NewLHS.getValueType() == N->getValueType(0) &&
2124 "Unexpected setcc expansion!");
2128 // Otherwise, update N to have the operands specified.
2129 return DAG.UpdateNodeOperands(SDValue(N, 0), NewLHS, NewRHS,
2130 DAG.getCondCode(CCCode));
2133 SDValue DAGTypeLegalizer::ExpandIntOp_Shift(SDNode *N) {
2134 // The value being shifted is legal, but the shift amount is too big.
2135 // It follows that either the result of the shift is undefined, or the
2136 // upper half of the shift amount is zero. Just use the lower half.
2138 GetExpandedInteger(N->getOperand(1), Lo, Hi);
2139 return DAG.UpdateNodeOperands(SDValue(N, 0), N->getOperand(0), Lo);
2142 SDValue DAGTypeLegalizer::ExpandIntOp_SINT_TO_FP(SDNode *N) {
2143 SDValue Op = N->getOperand(0);
2144 MVT DstVT = N->getValueType(0);
2145 RTLIB::Libcall LC = RTLIB::getSINTTOFP(Op.getValueType(), DstVT);
2146 assert(LC != RTLIB::UNKNOWN_LIBCALL &&
2147 "Don't know how to expand this SINT_TO_FP!");
2148 return MakeLibCall(LC, DstVT, &Op, 1, true, N->getDebugLoc());
2151 SDValue DAGTypeLegalizer::ExpandIntOp_STORE(StoreSDNode *N, unsigned OpNo) {
2152 if (ISD::isNormalStore(N))
2153 return ExpandOp_NormalStore(N, OpNo);
2155 assert(ISD::isUNINDEXEDStore(N) && "Indexed store during type legalization!");
2156 assert(OpNo == 1 && "Can only expand the stored value so far");
2158 MVT VT = N->getOperand(1).getValueType();
2159 MVT NVT = TLI.getTypeToTransformTo(VT);
2160 SDValue Ch = N->getChain();
2161 SDValue Ptr = N->getBasePtr();
2162 int SVOffset = N->getSrcValueOffset();
2163 unsigned Alignment = N->getAlignment();
2164 bool isVolatile = N->isVolatile();
2165 DebugLoc dl = N->getDebugLoc();
2168 assert(NVT.isByteSized() && "Expanded type not byte sized!");
2170 if (N->getMemoryVT().bitsLE(NVT)) {
2171 GetExpandedInteger(N->getValue(), Lo, Hi);
2172 return DAG.getTruncStore(Ch, dl, Lo, Ptr, N->getSrcValue(), SVOffset,
2173 N->getMemoryVT(), isVolatile, Alignment);
2174 } else if (TLI.isLittleEndian()) {
2175 // Little-endian - low bits are at low addresses.
2176 GetExpandedInteger(N->getValue(), Lo, Hi);
2178 Lo = DAG.getStore(Ch, dl, Lo, Ptr, N->getSrcValue(), SVOffset,
2179 isVolatile, Alignment);
2181 unsigned ExcessBits =
2182 N->getMemoryVT().getSizeInBits() - NVT.getSizeInBits();
2183 MVT NEVT = MVT::getIntegerVT(ExcessBits);
2185 // Increment the pointer to the other half.
2186 unsigned IncrementSize = NVT.getSizeInBits()/8;
2187 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
2188 DAG.getIntPtrConstant(IncrementSize));
2189 Hi = DAG.getTruncStore(Ch, dl, Hi, Ptr, N->getSrcValue(),
2190 SVOffset+IncrementSize, NEVT,
2191 isVolatile, MinAlign(Alignment, IncrementSize));
2192 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi);
2194 // Big-endian - high bits are at low addresses. Favor aligned stores at
2195 // the cost of some bit-fiddling.
2196 GetExpandedInteger(N->getValue(), Lo, Hi);
2198 MVT EVT = N->getMemoryVT();
2199 unsigned EBytes = EVT.getStoreSizeInBits()/8;
2200 unsigned IncrementSize = NVT.getSizeInBits()/8;
2201 unsigned ExcessBits = (EBytes - IncrementSize)*8;
2202 MVT HiVT = MVT::getIntegerVT(EVT.getSizeInBits() - ExcessBits);
2204 if (ExcessBits < NVT.getSizeInBits()) {
2205 // Transfer high bits from the top of Lo to the bottom of Hi.
2206 Hi = DAG.getNode(ISD::SHL, dl, NVT, Hi,
2207 DAG.getConstant(NVT.getSizeInBits() - ExcessBits,
2208 TLI.getPointerTy()));
2209 Hi = DAG.getNode(ISD::OR, dl, NVT, Hi,
2210 DAG.getNode(ISD::SRL, dl, NVT, Lo,
2211 DAG.getConstant(ExcessBits,
2212 TLI.getPointerTy())));
2215 // Store both the high bits and maybe some of the low bits.
2216 Hi = DAG.getTruncStore(Ch, dl, Hi, Ptr, N->getSrcValue(),
2217 SVOffset, HiVT, isVolatile, Alignment);
2219 // Increment the pointer to the other half.
2220 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
2221 DAG.getIntPtrConstant(IncrementSize));
2222 // Store the lowest ExcessBits bits in the second half.
2223 Lo = DAG.getTruncStore(Ch, dl, Lo, Ptr, N->getSrcValue(),
2224 SVOffset+IncrementSize,
2225 MVT::getIntegerVT(ExcessBits),
2226 isVolatile, MinAlign(Alignment, IncrementSize));
2227 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi);
2231 SDValue DAGTypeLegalizer::ExpandIntOp_TRUNCATE(SDNode *N) {
2233 GetExpandedInteger(N->getOperand(0), InL, InH);
2234 // Just truncate the low part of the source.
2235 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), N->getValueType(0), InL);
2238 SDValue DAGTypeLegalizer::ExpandIntOp_UINT_TO_FP(SDNode *N) {
2239 SDValue Op = N->getOperand(0);
2240 MVT SrcVT = Op.getValueType();
2241 MVT DstVT = N->getValueType(0);
2242 DebugLoc dl = N->getDebugLoc();
2244 if (TLI.getOperationAction(ISD::SINT_TO_FP, SrcVT) == TargetLowering::Custom){
2245 // Do a signed conversion then adjust the result.
2246 SDValue SignedConv = DAG.getNode(ISD::SINT_TO_FP, dl, DstVT, Op);
2247 SignedConv = TLI.LowerOperation(SignedConv, DAG);
2249 // The result of the signed conversion needs adjusting if the 'sign bit' of
2250 // the incoming integer was set. To handle this, we dynamically test to see
2251 // if it is set, and, if so, add a fudge factor.
2253 const uint64_t F32TwoE32 = 0x4F800000ULL;
2254 const uint64_t F32TwoE64 = 0x5F800000ULL;
2255 const uint64_t F32TwoE128 = 0x7F800000ULL;
2258 if (SrcVT == MVT::i32)
2259 FF = APInt(32, F32TwoE32);
2260 else if (SrcVT == MVT::i64)
2261 FF = APInt(32, F32TwoE64);
2262 else if (SrcVT == MVT::i128)
2263 FF = APInt(32, F32TwoE128);
2265 assert(false && "Unsupported UINT_TO_FP!");
2267 // Check whether the sign bit is set.
2269 GetExpandedInteger(Op, Lo, Hi);
2270 SDValue SignSet = DAG.getSetCC(dl,
2271 TLI.getSetCCResultType(Hi.getValueType()),
2272 Hi, DAG.getConstant(0, Hi.getValueType()),
2275 // Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits.
2276 SDValue FudgePtr = DAG.getConstantPool(ConstantInt::get(FF.zext(64)),
2277 TLI.getPointerTy());
2279 // Get a pointer to FF if the sign bit was set, or to 0 otherwise.
2280 SDValue Zero = DAG.getIntPtrConstant(0);
2281 SDValue Four = DAG.getIntPtrConstant(4);
2282 if (TLI.isBigEndian()) std::swap(Zero, Four);
2283 SDValue Offset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(), SignSet,
2285 unsigned Alignment =
2286 1 << cast<ConstantPoolSDNode>(FudgePtr)->getAlignment();
2287 FudgePtr = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(), FudgePtr, Offset);
2288 Alignment = std::min(Alignment, 4u);
2290 // Load the value out, extending it from f32 to the destination float type.
2291 // FIXME: Avoid the extend by constructing the right constant pool?
2292 SDValue Fudge = DAG.getExtLoad(ISD::EXTLOAD, dl, DstVT, DAG.getEntryNode(),
2293 FudgePtr, NULL, 0, MVT::f32,
2295 return DAG.getNode(ISD::FADD, dl, DstVT, SignedConv, Fudge);
2298 // Otherwise, use a libcall.
2299 RTLIB::Libcall LC = RTLIB::getUINTTOFP(SrcVT, DstVT);
2300 assert(LC != RTLIB::UNKNOWN_LIBCALL &&
2301 "Don't know how to expand this UINT_TO_FP!");
2302 return MakeLibCall(LC, DstVT, &Op, 1, true, dl);