1 //===----- LegalizeIntegerTypes.cpp - Legalization of integer types -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements integer type expansion and promotion for LegalizeTypes.
11 // Promotion is the act of changing a computation in an illegal type into a
12 // computation in a larger type. For example, implementing i8 arithmetic in an
13 // i32 register (often needed on powerpc).
14 // Expansion is the act of changing a computation in an illegal type into a
15 // computation in two identical registers of a smaller type. For example,
16 // implementing i64 arithmetic in two i32 registers (often needed on 32-bit
19 //===----------------------------------------------------------------------===//
21 #include "LegalizeTypes.h"
22 #include "llvm/IR/DerivedTypes.h"
23 #include "llvm/Support/ErrorHandling.h"
24 #include "llvm/Support/raw_ostream.h"
27 #define DEBUG_TYPE "legalize-types"
29 //===----------------------------------------------------------------------===//
30 // Integer Result Promotion
31 //===----------------------------------------------------------------------===//
33 /// PromoteIntegerResult - This method is called when a result of a node is
34 /// found to be in need of promotion to a larger type. At this point, the node
35 /// may also have invalid operands or may have other results that need
36 /// expansion, we just know that (at least) one result needs promotion.
37 void DAGTypeLegalizer::PromoteIntegerResult(SDNode *N, unsigned ResNo) {
38 DEBUG(dbgs() << "Promote integer result: "; N->dump(&DAG); dbgs() << "\n");
39 SDValue Res = SDValue();
41 // See if the target wants to custom expand this node.
42 if (CustomLowerNode(N, N->getValueType(ResNo), true))
45 switch (N->getOpcode()) {
48 dbgs() << "PromoteIntegerResult #" << ResNo << ": ";
49 N->dump(&DAG); dbgs() << "\n";
51 llvm_unreachable("Do not know how to promote this operator!");
52 case ISD::MERGE_VALUES:Res = PromoteIntRes_MERGE_VALUES(N, ResNo); break;
53 case ISD::AssertSext: Res = PromoteIntRes_AssertSext(N); break;
54 case ISD::AssertZext: Res = PromoteIntRes_AssertZext(N); break;
55 case ISD::BITCAST: Res = PromoteIntRes_BITCAST(N); break;
56 case ISD::BSWAP: Res = PromoteIntRes_BSWAP(N); break;
57 case ISD::BUILD_PAIR: Res = PromoteIntRes_BUILD_PAIR(N); break;
58 case ISD::Constant: Res = PromoteIntRes_Constant(N); break;
59 case ISD::CONVERT_RNDSAT:
60 Res = PromoteIntRes_CONVERT_RNDSAT(N); break;
61 case ISD::CTLZ_ZERO_UNDEF:
62 case ISD::CTLZ: Res = PromoteIntRes_CTLZ(N); break;
63 case ISD::CTPOP: Res = PromoteIntRes_CTPOP(N); break;
64 case ISD::CTTZ_ZERO_UNDEF:
65 case ISD::CTTZ: Res = PromoteIntRes_CTTZ(N); break;
66 case ISD::EXTRACT_VECTOR_ELT:
67 Res = PromoteIntRes_EXTRACT_VECTOR_ELT(N); break;
68 case ISD::LOAD: Res = PromoteIntRes_LOAD(cast<LoadSDNode>(N));break;
69 case ISD::SELECT: Res = PromoteIntRes_SELECT(N); break;
70 case ISD::VSELECT: Res = PromoteIntRes_VSELECT(N); break;
71 case ISD::SELECT_CC: Res = PromoteIntRes_SELECT_CC(N); break;
72 case ISD::SETCC: Res = PromoteIntRes_SETCC(N); break;
73 case ISD::SHL: Res = PromoteIntRes_SHL(N); break;
74 case ISD::SIGN_EXTEND_INREG:
75 Res = PromoteIntRes_SIGN_EXTEND_INREG(N); break;
76 case ISD::SRA: Res = PromoteIntRes_SRA(N); break;
77 case ISD::SRL: Res = PromoteIntRes_SRL(N); break;
78 case ISD::TRUNCATE: Res = PromoteIntRes_TRUNCATE(N); break;
79 case ISD::UNDEF: Res = PromoteIntRes_UNDEF(N); break;
80 case ISD::VAARG: Res = PromoteIntRes_VAARG(N); break;
82 case ISD::EXTRACT_SUBVECTOR:
83 Res = PromoteIntRes_EXTRACT_SUBVECTOR(N); break;
84 case ISD::VECTOR_SHUFFLE:
85 Res = PromoteIntRes_VECTOR_SHUFFLE(N); break;
86 case ISD::INSERT_VECTOR_ELT:
87 Res = PromoteIntRes_INSERT_VECTOR_ELT(N); break;
88 case ISD::BUILD_VECTOR:
89 Res = PromoteIntRes_BUILD_VECTOR(N); break;
90 case ISD::SCALAR_TO_VECTOR:
91 Res = PromoteIntRes_SCALAR_TO_VECTOR(N); break;
92 case ISD::CONCAT_VECTORS:
93 Res = PromoteIntRes_CONCAT_VECTORS(N); break;
95 case ISD::SIGN_EXTEND:
96 case ISD::ZERO_EXTEND:
97 case ISD::ANY_EXTEND: Res = PromoteIntRes_INT_EXTEND(N); break;
100 case ISD::FP_TO_UINT: Res = PromoteIntRes_FP_TO_XINT(N); break;
102 case ISD::FP_TO_FP16: Res = PromoteIntRes_FP_TO_FP16(N); break;
109 case ISD::MUL: Res = PromoteIntRes_SimpleIntBinOp(N); break;
112 case ISD::SREM: Res = PromoteIntRes_SDIV(N); break;
115 case ISD::UREM: Res = PromoteIntRes_UDIV(N); break;
118 case ISD::SSUBO: Res = PromoteIntRes_SADDSUBO(N, ResNo); break;
120 case ISD::USUBO: Res = PromoteIntRes_UADDSUBO(N, ResNo); break;
122 case ISD::UMULO: Res = PromoteIntRes_XMULO(N, ResNo); break;
124 case ISD::ATOMIC_LOAD:
125 Res = PromoteIntRes_Atomic0(cast<AtomicSDNode>(N)); break;
127 case ISD::ATOMIC_LOAD_ADD:
128 case ISD::ATOMIC_LOAD_SUB:
129 case ISD::ATOMIC_LOAD_AND:
130 case ISD::ATOMIC_LOAD_OR:
131 case ISD::ATOMIC_LOAD_XOR:
132 case ISD::ATOMIC_LOAD_NAND:
133 case ISD::ATOMIC_LOAD_MIN:
134 case ISD::ATOMIC_LOAD_MAX:
135 case ISD::ATOMIC_LOAD_UMIN:
136 case ISD::ATOMIC_LOAD_UMAX:
137 case ISD::ATOMIC_SWAP:
138 Res = PromoteIntRes_Atomic1(cast<AtomicSDNode>(N)); break;
140 case ISD::ATOMIC_CMP_SWAP:
141 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS:
142 Res = PromoteIntRes_AtomicCmpSwap(cast<AtomicSDNode>(N), ResNo);
146 // If the result is null then the sub-method took care of registering it.
148 SetPromotedInteger(SDValue(N, ResNo), Res);
151 SDValue DAGTypeLegalizer::PromoteIntRes_MERGE_VALUES(SDNode *N,
153 SDValue Op = DisintegrateMERGE_VALUES(N, ResNo);
154 return GetPromotedInteger(Op);
157 SDValue DAGTypeLegalizer::PromoteIntRes_AssertSext(SDNode *N) {
158 // Sign-extend the new bits, and continue the assertion.
159 SDValue Op = SExtPromotedInteger(N->getOperand(0));
160 return DAG.getNode(ISD::AssertSext, SDLoc(N),
161 Op.getValueType(), Op, N->getOperand(1));
164 SDValue DAGTypeLegalizer::PromoteIntRes_AssertZext(SDNode *N) {
165 // Zero the new bits, and continue the assertion.
166 SDValue Op = ZExtPromotedInteger(N->getOperand(0));
167 return DAG.getNode(ISD::AssertZext, SDLoc(N),
168 Op.getValueType(), Op, N->getOperand(1));
171 SDValue DAGTypeLegalizer::PromoteIntRes_Atomic0(AtomicSDNode *N) {
172 EVT ResVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
173 SDValue Res = DAG.getAtomic(N->getOpcode(), SDLoc(N),
174 N->getMemoryVT(), ResVT,
175 N->getChain(), N->getBasePtr(),
176 N->getMemOperand(), N->getOrdering(),
178 // Legalized the chain result - switch anything that used the old chain to
180 ReplaceValueWith(SDValue(N, 1), Res.getValue(1));
184 SDValue DAGTypeLegalizer::PromoteIntRes_Atomic1(AtomicSDNode *N) {
185 SDValue Op2 = GetPromotedInteger(N->getOperand(2));
186 SDValue Res = DAG.getAtomic(N->getOpcode(), SDLoc(N),
188 N->getChain(), N->getBasePtr(),
189 Op2, N->getMemOperand(), N->getOrdering(),
191 // Legalized the chain result - switch anything that used the old chain to
193 ReplaceValueWith(SDValue(N, 1), Res.getValue(1));
197 SDValue DAGTypeLegalizer::PromoteIntRes_AtomicCmpSwap(AtomicSDNode *N,
200 assert(N->getOpcode() == ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS);
201 EVT SVT = getSetCCResultType(N->getOperand(2).getValueType());
202 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(1));
204 // Only use the result of getSetCCResultType if it is legal,
205 // otherwise just use the promoted result type (NVT).
206 if (!TLI.isTypeLegal(SVT))
209 SDVTList VTs = DAG.getVTList(N->getValueType(0), SVT, MVT::Other);
210 SDValue Res = DAG.getAtomicCmpSwap(
211 ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, SDLoc(N), N->getMemoryVT(), VTs,
212 N->getChain(), N->getBasePtr(), N->getOperand(2), N->getOperand(3),
213 N->getMemOperand(), N->getSuccessOrdering(), N->getFailureOrdering(),
215 ReplaceValueWith(SDValue(N, 0), Res.getValue(0));
216 ReplaceValueWith(SDValue(N, 2), Res.getValue(2));
217 return Res.getValue(1);
220 SDValue Op2 = GetPromotedInteger(N->getOperand(2));
221 SDValue Op3 = GetPromotedInteger(N->getOperand(3));
223 DAG.getVTList(Op2.getValueType(), N->getValueType(1), MVT::Other);
224 SDValue Res = DAG.getAtomicCmpSwap(
225 N->getOpcode(), SDLoc(N), N->getMemoryVT(), VTs, N->getChain(),
226 N->getBasePtr(), Op2, Op3, N->getMemOperand(), N->getSuccessOrdering(),
227 N->getFailureOrdering(), N->getSynchScope());
228 // Update the use to N with the newly created Res.
229 for (unsigned i = 1, NumResults = N->getNumValues(); i < NumResults; ++i)
230 ReplaceValueWith(SDValue(N, i), Res.getValue(i));
234 SDValue DAGTypeLegalizer::PromoteIntRes_BITCAST(SDNode *N) {
235 SDValue InOp = N->getOperand(0);
236 EVT InVT = InOp.getValueType();
237 EVT NInVT = TLI.getTypeToTransformTo(*DAG.getContext(), InVT);
238 EVT OutVT = N->getValueType(0);
239 EVT NOutVT = TLI.getTypeToTransformTo(*DAG.getContext(), OutVT);
242 switch (getTypeAction(InVT)) {
243 case TargetLowering::TypeLegal:
245 case TargetLowering::TypePromoteInteger:
246 if (NOutVT.bitsEq(NInVT) && !NOutVT.isVector() && !NInVT.isVector())
247 // The input promotes to the same size. Convert the promoted value.
248 return DAG.getNode(ISD::BITCAST, dl, NOutVT, GetPromotedInteger(InOp));
250 case TargetLowering::TypeSoftenFloat:
251 // Promote the integer operand by hand.
252 return DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT, GetSoftenedFloat(InOp));
253 case TargetLowering::TypeExpandInteger:
254 case TargetLowering::TypeExpandFloat:
256 case TargetLowering::TypeScalarizeVector:
257 // Convert the element to an integer and promote it by hand.
258 if (!NOutVT.isVector())
259 return DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT,
260 BitConvertToInteger(GetScalarizedVector(InOp)));
262 case TargetLowering::TypeSplitVector: {
263 // For example, i32 = BITCAST v2i16 on alpha. Convert the split
264 // pieces of the input into integers and reassemble in the final type.
266 GetSplitVector(N->getOperand(0), Lo, Hi);
267 Lo = BitConvertToInteger(Lo);
268 Hi = BitConvertToInteger(Hi);
270 if (TLI.isBigEndian())
273 InOp = DAG.getNode(ISD::ANY_EXTEND, dl,
274 EVT::getIntegerVT(*DAG.getContext(),
275 NOutVT.getSizeInBits()),
276 JoinIntegers(Lo, Hi));
277 return DAG.getNode(ISD::BITCAST, dl, NOutVT, InOp);
279 case TargetLowering::TypeWidenVector:
280 // The input is widened to the same size. Convert to the widened value.
281 // Make sure that the outgoing value is not a vector, because this would
282 // make us bitcast between two vectors which are legalized in different ways.
283 if (NOutVT.bitsEq(NInVT) && !NOutVT.isVector())
284 return DAG.getNode(ISD::BITCAST, dl, NOutVT, GetWidenedVector(InOp));
287 return DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT,
288 CreateStackStoreLoad(InOp, OutVT));
291 SDValue DAGTypeLegalizer::PromoteIntRes_BSWAP(SDNode *N) {
292 SDValue Op = GetPromotedInteger(N->getOperand(0));
293 EVT OVT = N->getValueType(0);
294 EVT NVT = Op.getValueType();
297 unsigned DiffBits = NVT.getScalarSizeInBits() - OVT.getScalarSizeInBits();
298 return DAG.getNode(ISD::SRL, dl, NVT, DAG.getNode(ISD::BSWAP, dl, NVT, Op),
299 DAG.getConstant(DiffBits, TLI.getShiftAmountTy(NVT)));
302 SDValue DAGTypeLegalizer::PromoteIntRes_BUILD_PAIR(SDNode *N) {
303 // The pair element type may be legal, or may not promote to the same type as
304 // the result, for example i14 = BUILD_PAIR (i7, i7). Handle all cases.
305 return DAG.getNode(ISD::ANY_EXTEND, SDLoc(N),
306 TLI.getTypeToTransformTo(*DAG.getContext(),
307 N->getValueType(0)), JoinIntegers(N->getOperand(0),
311 SDValue DAGTypeLegalizer::PromoteIntRes_Constant(SDNode *N) {
312 EVT VT = N->getValueType(0);
313 // FIXME there is no actual debug info here
315 // Zero extend things like i1, sign extend everything else. It shouldn't
316 // matter in theory which one we pick, but this tends to give better code?
317 unsigned Opc = VT.isByteSized() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
318 SDValue Result = DAG.getNode(Opc, dl,
319 TLI.getTypeToTransformTo(*DAG.getContext(), VT),
321 assert(isa<ConstantSDNode>(Result) && "Didn't constant fold ext?");
325 SDValue DAGTypeLegalizer::PromoteIntRes_CONVERT_RNDSAT(SDNode *N) {
326 ISD::CvtCode CvtCode = cast<CvtRndSatSDNode>(N)->getCvtCode();
327 assert ((CvtCode == ISD::CVT_SS || CvtCode == ISD::CVT_SU ||
328 CvtCode == ISD::CVT_US || CvtCode == ISD::CVT_UU ||
329 CvtCode == ISD::CVT_SF || CvtCode == ISD::CVT_UF) &&
330 "can only promote integers");
331 EVT OutVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
332 return DAG.getConvertRndSat(OutVT, SDLoc(N), N->getOperand(0),
333 N->getOperand(1), N->getOperand(2),
334 N->getOperand(3), N->getOperand(4), CvtCode);
337 SDValue DAGTypeLegalizer::PromoteIntRes_CTLZ(SDNode *N) {
338 // Zero extend to the promoted type and do the count there.
339 SDValue Op = ZExtPromotedInteger(N->getOperand(0));
341 EVT OVT = N->getValueType(0);
342 EVT NVT = Op.getValueType();
343 Op = DAG.getNode(N->getOpcode(), dl, NVT, Op);
344 // Subtract off the extra leading bits in the bigger type.
346 ISD::SUB, dl, NVT, Op,
347 DAG.getConstant(NVT.getScalarSizeInBits() - OVT.getScalarSizeInBits(),
351 SDValue DAGTypeLegalizer::PromoteIntRes_CTPOP(SDNode *N) {
352 // Zero extend to the promoted type and do the count there.
353 SDValue Op = ZExtPromotedInteger(N->getOperand(0));
354 return DAG.getNode(ISD::CTPOP, SDLoc(N), Op.getValueType(), Op);
357 SDValue DAGTypeLegalizer::PromoteIntRes_CTTZ(SDNode *N) {
358 SDValue Op = GetPromotedInteger(N->getOperand(0));
359 EVT OVT = N->getValueType(0);
360 EVT NVT = Op.getValueType();
362 if (N->getOpcode() == ISD::CTTZ) {
363 // The count is the same in the promoted type except if the original
364 // value was zero. This can be handled by setting the bit just off
365 // the top of the original type.
366 auto TopBit = APInt::getOneBitSet(NVT.getScalarSizeInBits(),
367 OVT.getScalarSizeInBits());
368 Op = DAG.getNode(ISD::OR, dl, NVT, Op, DAG.getConstant(TopBit, NVT));
370 return DAG.getNode(N->getOpcode(), dl, NVT, Op);
373 SDValue DAGTypeLegalizer::PromoteIntRes_EXTRACT_VECTOR_ELT(SDNode *N) {
375 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
376 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, NVT, N->getOperand(0),
380 SDValue DAGTypeLegalizer::PromoteIntRes_FP_TO_XINT(SDNode *N) {
381 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
382 unsigned NewOpc = N->getOpcode();
385 // If we're promoting a UINT to a larger size and the larger FP_TO_UINT is
386 // not Legal, check to see if we can use FP_TO_SINT instead. (If both UINT
387 // and SINT conversions are Custom, there is no way to tell which is
388 // preferable. We choose SINT because that's the right thing on PPC.)
389 if (N->getOpcode() == ISD::FP_TO_UINT &&
390 !TLI.isOperationLegal(ISD::FP_TO_UINT, NVT) &&
391 TLI.isOperationLegalOrCustom(ISD::FP_TO_SINT, NVT))
392 NewOpc = ISD::FP_TO_SINT;
394 SDValue Res = DAG.getNode(NewOpc, dl, NVT, N->getOperand(0));
396 // Assert that the converted value fits in the original type. If it doesn't
397 // (eg: because the value being converted is too big), then the result of the
398 // original operation was undefined anyway, so the assert is still correct.
399 return DAG.getNode(N->getOpcode() == ISD::FP_TO_UINT ?
400 ISD::AssertZext : ISD::AssertSext, dl, NVT, Res,
401 DAG.getValueType(N->getValueType(0).getScalarType()));
404 SDValue DAGTypeLegalizer::PromoteIntRes_FP_TO_FP16(SDNode *N) {
405 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
408 SDValue Res = DAG.getNode(N->getOpcode(), dl, NVT, N->getOperand(0));
410 return DAG.getNode(ISD::AssertZext, dl,
411 NVT, Res, DAG.getValueType(N->getValueType(0)));
414 SDValue DAGTypeLegalizer::PromoteIntRes_INT_EXTEND(SDNode *N) {
415 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
418 if (getTypeAction(N->getOperand(0).getValueType())
419 == TargetLowering::TypePromoteInteger) {
420 SDValue Res = GetPromotedInteger(N->getOperand(0));
421 assert(Res.getValueType().bitsLE(NVT) && "Extension doesn't make sense!");
423 // If the result and operand types are the same after promotion, simplify
424 // to an in-register extension.
425 if (NVT == Res.getValueType()) {
426 // The high bits are not guaranteed to be anything. Insert an extend.
427 if (N->getOpcode() == ISD::SIGN_EXTEND)
428 return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NVT, Res,
429 DAG.getValueType(N->getOperand(0).getValueType()));
430 if (N->getOpcode() == ISD::ZERO_EXTEND)
431 return DAG.getZeroExtendInReg(Res, dl,
432 N->getOperand(0).getValueType().getScalarType());
433 assert(N->getOpcode() == ISD::ANY_EXTEND && "Unknown integer extension!");
438 // Otherwise, just extend the original operand all the way to the larger type.
439 return DAG.getNode(N->getOpcode(), dl, NVT, N->getOperand(0));
442 SDValue DAGTypeLegalizer::PromoteIntRes_LOAD(LoadSDNode *N) {
443 assert(ISD::isUNINDEXEDLoad(N) && "Indexed load during type legalization!");
444 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
445 ISD::LoadExtType ExtType =
446 ISD::isNON_EXTLoad(N) ? ISD::EXTLOAD : N->getExtensionType();
448 SDValue Res = DAG.getExtLoad(ExtType, dl, NVT, N->getChain(), N->getBasePtr(),
449 N->getMemoryVT(), N->getMemOperand());
451 // Legalized the chain result - switch anything that used the old chain to
453 ReplaceValueWith(SDValue(N, 1), Res.getValue(1));
457 /// Promote the overflow flag of an overflowing arithmetic node.
458 SDValue DAGTypeLegalizer::PromoteIntRes_Overflow(SDNode *N) {
459 // Simply change the return type of the boolean result.
460 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(1));
461 EVT ValueVTs[] = { N->getValueType(0), NVT };
462 SDValue Ops[] = { N->getOperand(0), N->getOperand(1) };
463 SDValue Res = DAG.getNode(N->getOpcode(), SDLoc(N),
464 DAG.getVTList(ValueVTs), Ops);
466 // Modified the sum result - switch anything that used the old sum to use
468 ReplaceValueWith(SDValue(N, 0), Res);
470 return SDValue(Res.getNode(), 1);
473 SDValue DAGTypeLegalizer::PromoteIntRes_SADDSUBO(SDNode *N, unsigned ResNo) {
475 return PromoteIntRes_Overflow(N);
477 // The operation overflowed iff the result in the larger type is not the
478 // sign extension of its truncation to the original type.
479 SDValue LHS = SExtPromotedInteger(N->getOperand(0));
480 SDValue RHS = SExtPromotedInteger(N->getOperand(1));
481 EVT OVT = N->getOperand(0).getValueType();
482 EVT NVT = LHS.getValueType();
485 // Do the arithmetic in the larger type.
486 unsigned Opcode = N->getOpcode() == ISD::SADDO ? ISD::ADD : ISD::SUB;
487 SDValue Res = DAG.getNode(Opcode, dl, NVT, LHS, RHS);
489 // Calculate the overflow flag: sign extend the arithmetic result from
490 // the original type.
491 SDValue Ofl = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NVT, Res,
492 DAG.getValueType(OVT));
493 // Overflowed if and only if this is not equal to Res.
494 Ofl = DAG.getSetCC(dl, N->getValueType(1), Ofl, Res, ISD::SETNE);
496 // Use the calculated overflow everywhere.
497 ReplaceValueWith(SDValue(N, 1), Ofl);
502 SDValue DAGTypeLegalizer::PromoteIntRes_SDIV(SDNode *N) {
503 // Sign extend the input.
504 SDValue LHS = SExtPromotedInteger(N->getOperand(0));
505 SDValue RHS = SExtPromotedInteger(N->getOperand(1));
506 return DAG.getNode(N->getOpcode(), SDLoc(N),
507 LHS.getValueType(), LHS, RHS);
510 SDValue DAGTypeLegalizer::PromoteIntRes_SELECT(SDNode *N) {
511 SDValue LHS = GetPromotedInteger(N->getOperand(1));
512 SDValue RHS = GetPromotedInteger(N->getOperand(2));
513 return DAG.getSelect(SDLoc(N),
514 LHS.getValueType(), N->getOperand(0), LHS, RHS);
517 SDValue DAGTypeLegalizer::PromoteIntRes_VSELECT(SDNode *N) {
518 SDValue Mask = N->getOperand(0);
519 EVT OpTy = N->getOperand(1).getValueType();
521 // Promote all the way up to the canonical SetCC type.
522 Mask = PromoteTargetBoolean(Mask, OpTy);
523 SDValue LHS = GetPromotedInteger(N->getOperand(1));
524 SDValue RHS = GetPromotedInteger(N->getOperand(2));
525 return DAG.getNode(ISD::VSELECT, SDLoc(N),
526 LHS.getValueType(), Mask, LHS, RHS);
529 SDValue DAGTypeLegalizer::PromoteIntRes_SELECT_CC(SDNode *N) {
530 SDValue LHS = GetPromotedInteger(N->getOperand(2));
531 SDValue RHS = GetPromotedInteger(N->getOperand(3));
532 return DAG.getNode(ISD::SELECT_CC, SDLoc(N),
533 LHS.getValueType(), N->getOperand(0),
534 N->getOperand(1), LHS, RHS, N->getOperand(4));
537 SDValue DAGTypeLegalizer::PromoteIntRes_SETCC(SDNode *N) {
538 EVT SVT = getSetCCResultType(N->getOperand(0).getValueType());
540 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
542 // Only use the result of getSetCCResultType if it is legal,
543 // otherwise just use the promoted result type (NVT).
544 if (!TLI.isTypeLegal(SVT))
548 assert(SVT.isVector() == N->getOperand(0).getValueType().isVector() &&
549 "Vector compare must return a vector result!");
551 SDValue LHS = N->getOperand(0);
552 SDValue RHS = N->getOperand(1);
553 if (LHS.getValueType() != RHS.getValueType()) {
554 if (getTypeAction(LHS.getValueType()) == TargetLowering::TypePromoteInteger &&
555 !LHS.getValueType().isVector())
556 LHS = GetPromotedInteger(LHS);
557 if (getTypeAction(RHS.getValueType()) == TargetLowering::TypePromoteInteger &&
558 !RHS.getValueType().isVector())
559 RHS = GetPromotedInteger(RHS);
562 // Get the SETCC result using the canonical SETCC type.
563 SDValue SetCC = DAG.getNode(N->getOpcode(), dl, SVT, LHS, RHS,
566 assert(NVT.bitsLE(SVT) && "Integer type overpromoted?");
567 // Convert to the expected type.
568 return DAG.getNode(ISD::TRUNCATE, dl, NVT, SetCC);
571 SDValue DAGTypeLegalizer::PromoteIntRes_SHL(SDNode *N) {
572 SDValue Res = GetPromotedInteger(N->getOperand(0));
573 SDValue Amt = N->getOperand(1);
574 Amt = Amt.getValueType().isVector() ? ZExtPromotedInteger(Amt) : Amt;
575 return DAG.getNode(ISD::SHL, SDLoc(N), Res.getValueType(), Res, Amt);
578 SDValue DAGTypeLegalizer::PromoteIntRes_SIGN_EXTEND_INREG(SDNode *N) {
579 SDValue Op = GetPromotedInteger(N->getOperand(0));
580 return DAG.getNode(ISD::SIGN_EXTEND_INREG, SDLoc(N),
581 Op.getValueType(), Op, N->getOperand(1));
584 SDValue DAGTypeLegalizer::PromoteIntRes_SimpleIntBinOp(SDNode *N) {
585 // The input may have strange things in the top bits of the registers, but
586 // these operations don't care. They may have weird bits going out, but
587 // that too is okay if they are integer operations.
588 SDValue LHS = GetPromotedInteger(N->getOperand(0));
589 SDValue RHS = GetPromotedInteger(N->getOperand(1));
590 return DAG.getNode(N->getOpcode(), SDLoc(N),
591 LHS.getValueType(), LHS, RHS);
594 SDValue DAGTypeLegalizer::PromoteIntRes_SRA(SDNode *N) {
595 // The input value must be properly sign extended.
596 SDValue Res = SExtPromotedInteger(N->getOperand(0));
597 SDValue Amt = N->getOperand(1);
598 Amt = Amt.getValueType().isVector() ? ZExtPromotedInteger(Amt) : Amt;
599 return DAG.getNode(ISD::SRA, SDLoc(N), Res.getValueType(), Res, Amt);
602 SDValue DAGTypeLegalizer::PromoteIntRes_SRL(SDNode *N) {
603 // The input value must be properly zero extended.
604 SDValue Res = ZExtPromotedInteger(N->getOperand(0));
605 SDValue Amt = N->getOperand(1);
606 Amt = Amt.getValueType().isVector() ? ZExtPromotedInteger(Amt) : Amt;
607 return DAG.getNode(ISD::SRL, SDLoc(N), Res.getValueType(), Res, Amt);
610 SDValue DAGTypeLegalizer::PromoteIntRes_TRUNCATE(SDNode *N) {
611 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
613 SDValue InOp = N->getOperand(0);
616 switch (getTypeAction(InOp.getValueType())) {
617 default: llvm_unreachable("Unknown type action!");
618 case TargetLowering::TypeLegal:
619 case TargetLowering::TypeExpandInteger:
622 case TargetLowering::TypePromoteInteger:
623 Res = GetPromotedInteger(InOp);
625 case TargetLowering::TypeSplitVector:
626 EVT InVT = InOp.getValueType();
627 assert(InVT.isVector() && "Cannot split scalar types");
628 unsigned NumElts = InVT.getVectorNumElements();
629 assert(NumElts == NVT.getVectorNumElements() &&
630 "Dst and Src must have the same number of elements");
631 assert(isPowerOf2_32(NumElts) &&
632 "Promoted vector type must be a power of two");
635 GetSplitVector(InOp, EOp1, EOp2);
637 EVT HalfNVT = EVT::getVectorVT(*DAG.getContext(), NVT.getScalarType(),
639 EOp1 = DAG.getNode(ISD::TRUNCATE, dl, HalfNVT, EOp1);
640 EOp2 = DAG.getNode(ISD::TRUNCATE, dl, HalfNVT, EOp2);
642 return DAG.getNode(ISD::CONCAT_VECTORS, dl, NVT, EOp1, EOp2);
645 // Truncate to NVT instead of VT
646 return DAG.getNode(ISD::TRUNCATE, dl, NVT, Res);
649 SDValue DAGTypeLegalizer::PromoteIntRes_UADDSUBO(SDNode *N, unsigned ResNo) {
651 return PromoteIntRes_Overflow(N);
653 // The operation overflowed iff the result in the larger type is not the
654 // zero extension of its truncation to the original type.
655 SDValue LHS = ZExtPromotedInteger(N->getOperand(0));
656 SDValue RHS = ZExtPromotedInteger(N->getOperand(1));
657 EVT OVT = N->getOperand(0).getValueType();
658 EVT NVT = LHS.getValueType();
661 // Do the arithmetic in the larger type.
662 unsigned Opcode = N->getOpcode() == ISD::UADDO ? ISD::ADD : ISD::SUB;
663 SDValue Res = DAG.getNode(Opcode, dl, NVT, LHS, RHS);
665 // Calculate the overflow flag: zero extend the arithmetic result from
666 // the original type.
667 SDValue Ofl = DAG.getZeroExtendInReg(Res, dl, OVT);
668 // Overflowed if and only if this is not equal to Res.
669 Ofl = DAG.getSetCC(dl, N->getValueType(1), Ofl, Res, ISD::SETNE);
671 // Use the calculated overflow everywhere.
672 ReplaceValueWith(SDValue(N, 1), Ofl);
677 SDValue DAGTypeLegalizer::PromoteIntRes_XMULO(SDNode *N, unsigned ResNo) {
678 // Promote the overflow bit trivially.
680 return PromoteIntRes_Overflow(N);
682 SDValue LHS = N->getOperand(0), RHS = N->getOperand(1);
684 EVT SmallVT = LHS.getValueType();
686 // To determine if the result overflowed in a larger type, we extend the
687 // input to the larger type, do the multiply (checking if it overflows),
688 // then also check the high bits of the result to see if overflow happened
690 if (N->getOpcode() == ISD::SMULO) {
691 LHS = SExtPromotedInteger(LHS);
692 RHS = SExtPromotedInteger(RHS);
694 LHS = ZExtPromotedInteger(LHS);
695 RHS = ZExtPromotedInteger(RHS);
697 SDVTList VTs = DAG.getVTList(LHS.getValueType(), N->getValueType(1));
698 SDValue Mul = DAG.getNode(N->getOpcode(), DL, VTs, LHS, RHS);
700 // Overflow occurred if it occurred in the larger type, or if the high part
701 // of the result does not zero/sign-extend the low part. Check this second
702 // possibility first.
704 if (N->getOpcode() == ISD::UMULO) {
705 // Unsigned overflow occurred if the high part is non-zero.
706 SDValue Hi = DAG.getNode(ISD::SRL, DL, Mul.getValueType(), Mul,
707 DAG.getIntPtrConstant(SmallVT.getSizeInBits()));
708 Overflow = DAG.getSetCC(DL, N->getValueType(1), Hi,
709 DAG.getConstant(0, Hi.getValueType()), ISD::SETNE);
711 // Signed overflow occurred if the high part does not sign extend the low.
712 SDValue SExt = DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, Mul.getValueType(),
713 Mul, DAG.getValueType(SmallVT));
714 Overflow = DAG.getSetCC(DL, N->getValueType(1), SExt, Mul, ISD::SETNE);
717 // The only other way for overflow to occur is if the multiplication in the
718 // larger type itself overflowed.
719 Overflow = DAG.getNode(ISD::OR, DL, N->getValueType(1), Overflow,
720 SDValue(Mul.getNode(), 1));
722 // Use the calculated overflow everywhere.
723 ReplaceValueWith(SDValue(N, 1), Overflow);
727 SDValue DAGTypeLegalizer::PromoteIntRes_UDIV(SDNode *N) {
728 // Zero extend the input.
729 SDValue LHS = ZExtPromotedInteger(N->getOperand(0));
730 SDValue RHS = ZExtPromotedInteger(N->getOperand(1));
731 return DAG.getNode(N->getOpcode(), SDLoc(N),
732 LHS.getValueType(), LHS, RHS);
735 SDValue DAGTypeLegalizer::PromoteIntRes_UNDEF(SDNode *N) {
736 return DAG.getUNDEF(TLI.getTypeToTransformTo(*DAG.getContext(),
737 N->getValueType(0)));
740 SDValue DAGTypeLegalizer::PromoteIntRes_VAARG(SDNode *N) {
741 SDValue Chain = N->getOperand(0); // Get the chain.
742 SDValue Ptr = N->getOperand(1); // Get the pointer.
743 EVT VT = N->getValueType(0);
746 MVT RegVT = TLI.getRegisterType(*DAG.getContext(), VT);
747 unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), VT);
748 // The argument is passed as NumRegs registers of type RegVT.
750 SmallVector<SDValue, 8> Parts(NumRegs);
751 for (unsigned i = 0; i < NumRegs; ++i) {
752 Parts[i] = DAG.getVAArg(RegVT, dl, Chain, Ptr, N->getOperand(2),
753 N->getConstantOperandVal(3));
754 Chain = Parts[i].getValue(1);
757 // Handle endianness of the load.
758 if (TLI.isBigEndian())
759 std::reverse(Parts.begin(), Parts.end());
761 // Assemble the parts in the promoted type.
762 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
763 SDValue Res = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Parts[0]);
764 for (unsigned i = 1; i < NumRegs; ++i) {
765 SDValue Part = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Parts[i]);
766 // Shift it to the right position and "or" it in.
767 Part = DAG.getNode(ISD::SHL, dl, NVT, Part,
768 DAG.getConstant(i * RegVT.getSizeInBits(),
769 TLI.getPointerTy()));
770 Res = DAG.getNode(ISD::OR, dl, NVT, Res, Part);
773 // Modified the chain result - switch anything that used the old chain to
775 ReplaceValueWith(SDValue(N, 1), Chain);
780 //===----------------------------------------------------------------------===//
781 // Integer Operand Promotion
782 //===----------------------------------------------------------------------===//
784 /// PromoteIntegerOperand - This method is called when the specified operand of
785 /// the specified node is found to need promotion. At this point, all of the
786 /// result types of the node are known to be legal, but other operands of the
787 /// node may need promotion or expansion as well as the specified one.
788 bool DAGTypeLegalizer::PromoteIntegerOperand(SDNode *N, unsigned OpNo) {
789 DEBUG(dbgs() << "Promote integer operand: "; N->dump(&DAG); dbgs() << "\n");
790 SDValue Res = SDValue();
792 if (CustomLowerNode(N, N->getOperand(OpNo).getValueType(), false))
795 switch (N->getOpcode()) {
798 dbgs() << "PromoteIntegerOperand Op #" << OpNo << ": ";
799 N->dump(&DAG); dbgs() << "\n";
801 llvm_unreachable("Do not know how to promote this operator's operand!");
803 case ISD::ANY_EXTEND: Res = PromoteIntOp_ANY_EXTEND(N); break;
804 case ISD::ATOMIC_STORE:
805 Res = PromoteIntOp_ATOMIC_STORE(cast<AtomicSDNode>(N));
807 case ISD::BITCAST: Res = PromoteIntOp_BITCAST(N); break;
808 case ISD::BR_CC: Res = PromoteIntOp_BR_CC(N, OpNo); break;
809 case ISD::BRCOND: Res = PromoteIntOp_BRCOND(N, OpNo); break;
810 case ISD::BUILD_PAIR: Res = PromoteIntOp_BUILD_PAIR(N); break;
811 case ISD::BUILD_VECTOR: Res = PromoteIntOp_BUILD_VECTOR(N); break;
812 case ISD::CONCAT_VECTORS: Res = PromoteIntOp_CONCAT_VECTORS(N); break;
813 case ISD::EXTRACT_VECTOR_ELT: Res = PromoteIntOp_EXTRACT_VECTOR_ELT(N); break;
814 case ISD::CONVERT_RNDSAT:
815 Res = PromoteIntOp_CONVERT_RNDSAT(N); break;
816 case ISD::INSERT_VECTOR_ELT:
817 Res = PromoteIntOp_INSERT_VECTOR_ELT(N, OpNo);break;
818 case ISD::SCALAR_TO_VECTOR:
819 Res = PromoteIntOp_SCALAR_TO_VECTOR(N); break;
821 case ISD::SELECT: Res = PromoteIntOp_SELECT(N, OpNo); break;
822 case ISD::SELECT_CC: Res = PromoteIntOp_SELECT_CC(N, OpNo); break;
823 case ISD::SETCC: Res = PromoteIntOp_SETCC(N, OpNo); break;
824 case ISD::SIGN_EXTEND: Res = PromoteIntOp_SIGN_EXTEND(N); break;
825 case ISD::SINT_TO_FP: Res = PromoteIntOp_SINT_TO_FP(N); break;
826 case ISD::STORE: Res = PromoteIntOp_STORE(cast<StoreSDNode>(N),
828 case ISD::MSTORE: Res = PromoteIntOp_MSTORE(cast<MaskedStoreSDNode>(N),
830 case ISD::MLOAD: Res = PromoteIntOp_MLOAD(cast<MaskedLoadSDNode>(N),
832 case ISD::TRUNCATE: Res = PromoteIntOp_TRUNCATE(N); break;
833 case ISD::FP16_TO_FP:
834 case ISD::UINT_TO_FP: Res = PromoteIntOp_UINT_TO_FP(N); break;
835 case ISD::ZERO_EXTEND: Res = PromoteIntOp_ZERO_EXTEND(N); break;
841 case ISD::ROTR: Res = PromoteIntOp_Shift(N); break;
844 // If the result is null, the sub-method took care of registering results etc.
845 if (!Res.getNode()) return false;
847 // If the result is N, the sub-method updated N in place. Tell the legalizer
849 if (Res.getNode() == N)
852 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 &&
853 "Invalid operand expansion");
855 ReplaceValueWith(SDValue(N, 0), Res);
859 /// PromoteSetCCOperands - Promote the operands of a comparison. This code is
860 /// shared among BR_CC, SELECT_CC, and SETCC handlers.
861 void DAGTypeLegalizer::PromoteSetCCOperands(SDValue &NewLHS,SDValue &NewRHS,
862 ISD::CondCode CCCode) {
863 // We have to insert explicit sign or zero extends. Note that we could
864 // insert sign extends for ALL conditions, but zero extend is cheaper on
865 // many machines (an AND instead of two shifts), so prefer it.
867 default: llvm_unreachable("Unknown integer comparison!");
870 SDValue OpL = GetPromotedInteger(NewLHS);
871 SDValue OpR = GetPromotedInteger(NewRHS);
873 // We would prefer to promote the comparison operand with sign extension,
874 // if we find the operand is actually to truncate an AssertSext. With this
875 // optimization, we can avoid inserting real truncate instruction, which
876 // is redudant eventually.
877 if (OpL->getOpcode() == ISD::AssertSext &&
878 cast<VTSDNode>(OpL->getOperand(1))->getVT() == NewLHS.getValueType() &&
879 OpR->getOpcode() == ISD::AssertSext &&
880 cast<VTSDNode>(OpR->getOperand(1))->getVT() == NewRHS.getValueType()) {
884 NewLHS = ZExtPromotedInteger(NewLHS);
885 NewRHS = ZExtPromotedInteger(NewRHS);
893 // ALL of these operations will work if we either sign or zero extend
894 // the operands (including the unsigned comparisons!). Zero extend is
895 // usually a simpler/cheaper operation, so prefer it.
896 NewLHS = ZExtPromotedInteger(NewLHS);
897 NewRHS = ZExtPromotedInteger(NewRHS);
903 NewLHS = SExtPromotedInteger(NewLHS);
904 NewRHS = SExtPromotedInteger(NewRHS);
909 SDValue DAGTypeLegalizer::PromoteIntOp_ANY_EXTEND(SDNode *N) {
910 SDValue Op = GetPromotedInteger(N->getOperand(0));
911 return DAG.getNode(ISD::ANY_EXTEND, SDLoc(N), N->getValueType(0), Op);
914 SDValue DAGTypeLegalizer::PromoteIntOp_ATOMIC_STORE(AtomicSDNode *N) {
915 SDValue Op2 = GetPromotedInteger(N->getOperand(2));
916 return DAG.getAtomic(N->getOpcode(), SDLoc(N), N->getMemoryVT(),
917 N->getChain(), N->getBasePtr(), Op2, N->getMemOperand(),
918 N->getOrdering(), N->getSynchScope());
921 SDValue DAGTypeLegalizer::PromoteIntOp_BITCAST(SDNode *N) {
922 // This should only occur in unusual situations like bitcasting to an
923 // x86_fp80, so just turn it into a store+load
924 return CreateStackStoreLoad(N->getOperand(0), N->getValueType(0));
927 SDValue DAGTypeLegalizer::PromoteIntOp_BR_CC(SDNode *N, unsigned OpNo) {
928 assert(OpNo == 2 && "Don't know how to promote this operand!");
930 SDValue LHS = N->getOperand(2);
931 SDValue RHS = N->getOperand(3);
932 PromoteSetCCOperands(LHS, RHS, cast<CondCodeSDNode>(N->getOperand(1))->get());
934 // The chain (Op#0), CC (#1) and basic block destination (Op#4) are always
936 return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0),
937 N->getOperand(1), LHS, RHS, N->getOperand(4)),
941 SDValue DAGTypeLegalizer::PromoteIntOp_BRCOND(SDNode *N, unsigned OpNo) {
942 assert(OpNo == 1 && "only know how to promote condition");
944 // Promote all the way up to the canonical SetCC type.
945 SDValue Cond = PromoteTargetBoolean(N->getOperand(1), MVT::Other);
947 // The chain (Op#0) and basic block destination (Op#2) are always legal types.
948 return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0), Cond,
949 N->getOperand(2)), 0);
952 SDValue DAGTypeLegalizer::PromoteIntOp_BUILD_PAIR(SDNode *N) {
953 // Since the result type is legal, the operands must promote to it.
954 EVT OVT = N->getOperand(0).getValueType();
955 SDValue Lo = ZExtPromotedInteger(N->getOperand(0));
956 SDValue Hi = GetPromotedInteger(N->getOperand(1));
957 assert(Lo.getValueType() == N->getValueType(0) && "Operand over promoted?");
960 Hi = DAG.getNode(ISD::SHL, dl, N->getValueType(0), Hi,
961 DAG.getConstant(OVT.getSizeInBits(), TLI.getPointerTy()));
962 return DAG.getNode(ISD::OR, dl, N->getValueType(0), Lo, Hi);
965 SDValue DAGTypeLegalizer::PromoteIntOp_BUILD_VECTOR(SDNode *N) {
966 // The vector type is legal but the element type is not. This implies
967 // that the vector is a power-of-two in length and that the element
968 // type does not have a strange size (eg: it is not i1).
969 EVT VecVT = N->getValueType(0);
970 unsigned NumElts = VecVT.getVectorNumElements();
971 assert(!((NumElts & 1) && (!TLI.isTypeLegal(VecVT))) &&
972 "Legal vector of one illegal element?");
974 // Promote the inserted value. The type does not need to match the
975 // vector element type. Check that any extra bits introduced will be
977 assert(N->getOperand(0).getValueType().getSizeInBits() >=
978 N->getValueType(0).getVectorElementType().getSizeInBits() &&
979 "Type of inserted value narrower than vector element type!");
981 SmallVector<SDValue, 16> NewOps;
982 for (unsigned i = 0; i < NumElts; ++i)
983 NewOps.push_back(GetPromotedInteger(N->getOperand(i)));
985 return SDValue(DAG.UpdateNodeOperands(N, NewOps), 0);
988 SDValue DAGTypeLegalizer::PromoteIntOp_CONVERT_RNDSAT(SDNode *N) {
989 ISD::CvtCode CvtCode = cast<CvtRndSatSDNode>(N)->getCvtCode();
990 assert ((CvtCode == ISD::CVT_SS || CvtCode == ISD::CVT_SU ||
991 CvtCode == ISD::CVT_US || CvtCode == ISD::CVT_UU ||
992 CvtCode == ISD::CVT_FS || CvtCode == ISD::CVT_FU) &&
993 "can only promote integer arguments");
994 SDValue InOp = GetPromotedInteger(N->getOperand(0));
995 return DAG.getConvertRndSat(N->getValueType(0), SDLoc(N), InOp,
996 N->getOperand(1), N->getOperand(2),
997 N->getOperand(3), N->getOperand(4), CvtCode);
1000 SDValue DAGTypeLegalizer::PromoteIntOp_INSERT_VECTOR_ELT(SDNode *N,
1003 // Promote the inserted value. This is valid because the type does not
1004 // have to match the vector element type.
1006 // Check that any extra bits introduced will be truncated away.
1007 assert(N->getOperand(1).getValueType().getSizeInBits() >=
1008 N->getValueType(0).getVectorElementType().getSizeInBits() &&
1009 "Type of inserted value narrower than vector element type!");
1010 return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0),
1011 GetPromotedInteger(N->getOperand(1)),
1016 assert(OpNo == 2 && "Different operand and result vector types?");
1018 // Promote the index.
1019 SDValue Idx = DAG.getZExtOrTrunc(N->getOperand(2), SDLoc(N),
1020 TLI.getVectorIdxTy());
1021 return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0),
1022 N->getOperand(1), Idx), 0);
1025 SDValue DAGTypeLegalizer::PromoteIntOp_SCALAR_TO_VECTOR(SDNode *N) {
1026 // Integer SCALAR_TO_VECTOR operands are implicitly truncated, so just promote
1027 // the operand in place.
1028 return SDValue(DAG.UpdateNodeOperands(N,
1029 GetPromotedInteger(N->getOperand(0))), 0);
1032 SDValue DAGTypeLegalizer::PromoteIntOp_SELECT(SDNode *N, unsigned OpNo) {
1033 assert(OpNo == 0 && "Only know how to promote the condition!");
1034 SDValue Cond = N->getOperand(0);
1035 EVT OpTy = N->getOperand(1).getValueType();
1037 // Promote all the way up to the canonical SetCC type.
1038 EVT OpVT = N->getOpcode() == ISD::SELECT ? OpTy.getScalarType() : OpTy;
1039 Cond = PromoteTargetBoolean(Cond, OpVT);
1041 return SDValue(DAG.UpdateNodeOperands(N, Cond, N->getOperand(1),
1042 N->getOperand(2)), 0);
1045 SDValue DAGTypeLegalizer::PromoteIntOp_SELECT_CC(SDNode *N, unsigned OpNo) {
1046 assert(OpNo == 0 && "Don't know how to promote this operand!");
1048 SDValue LHS = N->getOperand(0);
1049 SDValue RHS = N->getOperand(1);
1050 PromoteSetCCOperands(LHS, RHS, cast<CondCodeSDNode>(N->getOperand(4))->get());
1052 // The CC (#4) and the possible return values (#2 and #3) have legal types.
1053 return SDValue(DAG.UpdateNodeOperands(N, LHS, RHS, N->getOperand(2),
1054 N->getOperand(3), N->getOperand(4)), 0);
1057 SDValue DAGTypeLegalizer::PromoteIntOp_SETCC(SDNode *N, unsigned OpNo) {
1058 assert(OpNo == 0 && "Don't know how to promote this operand!");
1060 SDValue LHS = N->getOperand(0);
1061 SDValue RHS = N->getOperand(1);
1062 PromoteSetCCOperands(LHS, RHS, cast<CondCodeSDNode>(N->getOperand(2))->get());
1064 // The CC (#2) is always legal.
1065 return SDValue(DAG.UpdateNodeOperands(N, LHS, RHS, N->getOperand(2)), 0);
1068 SDValue DAGTypeLegalizer::PromoteIntOp_Shift(SDNode *N) {
1069 return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0),
1070 ZExtPromotedInteger(N->getOperand(1))), 0);
1073 SDValue DAGTypeLegalizer::PromoteIntOp_SIGN_EXTEND(SDNode *N) {
1074 SDValue Op = GetPromotedInteger(N->getOperand(0));
1076 Op = DAG.getNode(ISD::ANY_EXTEND, dl, N->getValueType(0), Op);
1077 return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Op.getValueType(),
1078 Op, DAG.getValueType(N->getOperand(0).getValueType()));
1081 SDValue DAGTypeLegalizer::PromoteIntOp_SINT_TO_FP(SDNode *N) {
1082 return SDValue(DAG.UpdateNodeOperands(N,
1083 SExtPromotedInteger(N->getOperand(0))), 0);
1086 SDValue DAGTypeLegalizer::PromoteIntOp_STORE(StoreSDNode *N, unsigned OpNo){
1087 assert(ISD::isUNINDEXEDStore(N) && "Indexed store during type legalization!");
1088 SDValue Ch = N->getChain(), Ptr = N->getBasePtr();
1091 SDValue Val = GetPromotedInteger(N->getValue()); // Get promoted value.
1093 // Truncate the value and store the result.
1094 return DAG.getTruncStore(Ch, dl, Val, Ptr,
1095 N->getMemoryVT(), N->getMemOperand());
1098 SDValue DAGTypeLegalizer::PromoteIntOp_MSTORE(MaskedStoreSDNode *N, unsigned OpNo){
1100 assert(OpNo == 2 && "Only know how to promote the mask!");
1101 EVT DataVT = N->getOperand(3).getValueType();
1102 SDValue Mask = PromoteTargetBoolean(N->getOperand(OpNo), DataVT);
1103 SmallVector<SDValue, 4> NewOps(N->op_begin(), N->op_end());
1104 NewOps[OpNo] = Mask;
1105 return SDValue(DAG.UpdateNodeOperands(N, NewOps), 0);
1108 SDValue DAGTypeLegalizer::PromoteIntOp_MLOAD(MaskedLoadSDNode *N, unsigned OpNo){
1109 assert(OpNo == 2 && "Only know how to promote the mask!");
1110 EVT DataVT = N->getValueType(0);
1111 SDValue Mask = PromoteTargetBoolean(N->getOperand(OpNo), DataVT);
1112 SmallVector<SDValue, 4> NewOps(N->op_begin(), N->op_end());
1113 NewOps[OpNo] = Mask;
1114 return SDValue(DAG.UpdateNodeOperands(N, NewOps), 0);
1117 SDValue DAGTypeLegalizer::PromoteIntOp_TRUNCATE(SDNode *N) {
1118 SDValue Op = GetPromotedInteger(N->getOperand(0));
1119 return DAG.getNode(ISD::TRUNCATE, SDLoc(N), N->getValueType(0), Op);
1122 SDValue DAGTypeLegalizer::PromoteIntOp_UINT_TO_FP(SDNode *N) {
1123 return SDValue(DAG.UpdateNodeOperands(N,
1124 ZExtPromotedInteger(N->getOperand(0))), 0);
1127 SDValue DAGTypeLegalizer::PromoteIntOp_ZERO_EXTEND(SDNode *N) {
1129 SDValue Op = GetPromotedInteger(N->getOperand(0));
1130 Op = DAG.getNode(ISD::ANY_EXTEND, dl, N->getValueType(0), Op);
1131 return DAG.getZeroExtendInReg(Op, dl,
1132 N->getOperand(0).getValueType().getScalarType());
1136 //===----------------------------------------------------------------------===//
1137 // Integer Result Expansion
1138 //===----------------------------------------------------------------------===//
1140 /// ExpandIntegerResult - This method is called when the specified result of the
1141 /// specified node is found to need expansion. At this point, the node may also
1142 /// have invalid operands or may have other results that need promotion, we just
1143 /// know that (at least) one result needs expansion.
1144 void DAGTypeLegalizer::ExpandIntegerResult(SDNode *N, unsigned ResNo) {
1145 DEBUG(dbgs() << "Expand integer result: "; N->dump(&DAG); dbgs() << "\n");
1147 Lo = Hi = SDValue();
1149 // See if the target wants to custom expand this node.
1150 if (CustomLowerNode(N, N->getValueType(ResNo), true))
1153 switch (N->getOpcode()) {
1156 dbgs() << "ExpandIntegerResult #" << ResNo << ": ";
1157 N->dump(&DAG); dbgs() << "\n";
1159 llvm_unreachable("Do not know how to expand the result of this operator!");
1161 case ISD::MERGE_VALUES: SplitRes_MERGE_VALUES(N, ResNo, Lo, Hi); break;
1162 case ISD::SELECT: SplitRes_SELECT(N, Lo, Hi); break;
1163 case ISD::SELECT_CC: SplitRes_SELECT_CC(N, Lo, Hi); break;
1164 case ISD::UNDEF: SplitRes_UNDEF(N, Lo, Hi); break;
1166 case ISD::BITCAST: ExpandRes_BITCAST(N, Lo, Hi); break;
1167 case ISD::BUILD_PAIR: ExpandRes_BUILD_PAIR(N, Lo, Hi); break;
1168 case ISD::EXTRACT_ELEMENT: ExpandRes_EXTRACT_ELEMENT(N, Lo, Hi); break;
1169 case ISD::EXTRACT_VECTOR_ELT: ExpandRes_EXTRACT_VECTOR_ELT(N, Lo, Hi); break;
1170 case ISD::VAARG: ExpandRes_VAARG(N, Lo, Hi); break;
1172 case ISD::ANY_EXTEND: ExpandIntRes_ANY_EXTEND(N, Lo, Hi); break;
1173 case ISD::AssertSext: ExpandIntRes_AssertSext(N, Lo, Hi); break;
1174 case ISD::AssertZext: ExpandIntRes_AssertZext(N, Lo, Hi); break;
1175 case ISD::BSWAP: ExpandIntRes_BSWAP(N, Lo, Hi); break;
1176 case ISD::Constant: ExpandIntRes_Constant(N, Lo, Hi); break;
1177 case ISD::CTLZ_ZERO_UNDEF:
1178 case ISD::CTLZ: ExpandIntRes_CTLZ(N, Lo, Hi); break;
1179 case ISD::CTPOP: ExpandIntRes_CTPOP(N, Lo, Hi); break;
1180 case ISD::CTTZ_ZERO_UNDEF:
1181 case ISD::CTTZ: ExpandIntRes_CTTZ(N, Lo, Hi); break;
1182 case ISD::FP_TO_SINT: ExpandIntRes_FP_TO_SINT(N, Lo, Hi); break;
1183 case ISD::FP_TO_UINT: ExpandIntRes_FP_TO_UINT(N, Lo, Hi); break;
1184 case ISD::LOAD: ExpandIntRes_LOAD(cast<LoadSDNode>(N), Lo, Hi); break;
1185 case ISD::MUL: ExpandIntRes_MUL(N, Lo, Hi); break;
1186 case ISD::SDIV: ExpandIntRes_SDIV(N, Lo, Hi); break;
1187 case ISD::SIGN_EXTEND: ExpandIntRes_SIGN_EXTEND(N, Lo, Hi); break;
1188 case ISD::SIGN_EXTEND_INREG: ExpandIntRes_SIGN_EXTEND_INREG(N, Lo, Hi); break;
1189 case ISD::SREM: ExpandIntRes_SREM(N, Lo, Hi); break;
1190 case ISD::TRUNCATE: ExpandIntRes_TRUNCATE(N, Lo, Hi); break;
1191 case ISD::UDIV: ExpandIntRes_UDIV(N, Lo, Hi); break;
1192 case ISD::UREM: ExpandIntRes_UREM(N, Lo, Hi); break;
1193 case ISD::ZERO_EXTEND: ExpandIntRes_ZERO_EXTEND(N, Lo, Hi); break;
1194 case ISD::ATOMIC_LOAD: ExpandIntRes_ATOMIC_LOAD(N, Lo, Hi); break;
1196 case ISD::ATOMIC_LOAD_ADD:
1197 case ISD::ATOMIC_LOAD_SUB:
1198 case ISD::ATOMIC_LOAD_AND:
1199 case ISD::ATOMIC_LOAD_OR:
1200 case ISD::ATOMIC_LOAD_XOR:
1201 case ISD::ATOMIC_LOAD_NAND:
1202 case ISD::ATOMIC_LOAD_MIN:
1203 case ISD::ATOMIC_LOAD_MAX:
1204 case ISD::ATOMIC_LOAD_UMIN:
1205 case ISD::ATOMIC_LOAD_UMAX:
1206 case ISD::ATOMIC_SWAP:
1207 case ISD::ATOMIC_CMP_SWAP: {
1208 std::pair<SDValue, SDValue> Tmp = ExpandAtomic(N);
1209 SplitInteger(Tmp.first, Lo, Hi);
1210 ReplaceValueWith(SDValue(N, 1), Tmp.second);
1213 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS: {
1214 AtomicSDNode *AN = cast<AtomicSDNode>(N);
1215 SDVTList VTs = DAG.getVTList(N->getValueType(0), MVT::Other);
1216 SDValue Tmp = DAG.getAtomicCmpSwap(
1217 ISD::ATOMIC_CMP_SWAP, SDLoc(N), AN->getMemoryVT(), VTs,
1218 N->getOperand(0), N->getOperand(1), N->getOperand(2), N->getOperand(3),
1219 AN->getMemOperand(), AN->getSuccessOrdering(), AN->getFailureOrdering(),
1220 AN->getSynchScope());
1222 // Expanding to the strong ATOMIC_CMP_SWAP node means we can determine
1223 // success simply by comparing the loaded value against the ingoing
1225 SDValue Success = DAG.getSetCC(SDLoc(N), N->getValueType(1), Tmp,
1226 N->getOperand(2), ISD::SETEQ);
1228 SplitInteger(Tmp, Lo, Hi);
1229 ReplaceValueWith(SDValue(N, 1), Success);
1230 ReplaceValueWith(SDValue(N, 2), Tmp.getValue(1));
1236 case ISD::XOR: ExpandIntRes_Logical(N, Lo, Hi); break;
1239 case ISD::SUB: ExpandIntRes_ADDSUB(N, Lo, Hi); break;
1242 case ISD::SUBC: ExpandIntRes_ADDSUBC(N, Lo, Hi); break;
1245 case ISD::SUBE: ExpandIntRes_ADDSUBE(N, Lo, Hi); break;
1249 case ISD::SRL: ExpandIntRes_Shift(N, Lo, Hi); break;
1252 case ISD::SSUBO: ExpandIntRes_SADDSUBO(N, Lo, Hi); break;
1254 case ISD::USUBO: ExpandIntRes_UADDSUBO(N, Lo, Hi); break;
1256 case ISD::SMULO: ExpandIntRes_XMULO(N, Lo, Hi); break;
1259 // If Lo/Hi is null, the sub-method took care of registering results etc.
1261 SetExpandedInteger(SDValue(N, ResNo), Lo, Hi);
1264 /// Lower an atomic node to the appropriate builtin call.
1265 std::pair <SDValue, SDValue> DAGTypeLegalizer::ExpandAtomic(SDNode *Node) {
1266 unsigned Opc = Node->getOpcode();
1267 MVT VT = cast<AtomicSDNode>(Node)->getMemoryVT().getSimpleVT();
1272 llvm_unreachable("Unhandled atomic intrinsic Expand!");
1273 case ISD::ATOMIC_SWAP:
1274 switch (VT.SimpleTy) {
1275 default: llvm_unreachable("Unexpected value type for atomic!");
1276 case MVT::i8: LC = RTLIB::SYNC_LOCK_TEST_AND_SET_1; break;
1277 case MVT::i16: LC = RTLIB::SYNC_LOCK_TEST_AND_SET_2; break;
1278 case MVT::i32: LC = RTLIB::SYNC_LOCK_TEST_AND_SET_4; break;
1279 case MVT::i64: LC = RTLIB::SYNC_LOCK_TEST_AND_SET_8; break;
1280 case MVT::i128:LC = RTLIB::SYNC_LOCK_TEST_AND_SET_16;break;
1283 case ISD::ATOMIC_CMP_SWAP:
1284 switch (VT.SimpleTy) {
1285 default: llvm_unreachable("Unexpected value type for atomic!");
1286 case MVT::i8: LC = RTLIB::SYNC_VAL_COMPARE_AND_SWAP_1; break;
1287 case MVT::i16: LC = RTLIB::SYNC_VAL_COMPARE_AND_SWAP_2; break;
1288 case MVT::i32: LC = RTLIB::SYNC_VAL_COMPARE_AND_SWAP_4; break;
1289 case MVT::i64: LC = RTLIB::SYNC_VAL_COMPARE_AND_SWAP_8; break;
1290 case MVT::i128:LC = RTLIB::SYNC_VAL_COMPARE_AND_SWAP_16;break;
1293 case ISD::ATOMIC_LOAD_ADD:
1294 switch (VT.SimpleTy) {
1295 default: llvm_unreachable("Unexpected value type for atomic!");
1296 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_ADD_1; break;
1297 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_ADD_2; break;
1298 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_ADD_4; break;
1299 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_ADD_8; break;
1300 case MVT::i128:LC = RTLIB::SYNC_FETCH_AND_ADD_16;break;
1303 case ISD::ATOMIC_LOAD_SUB:
1304 switch (VT.SimpleTy) {
1305 default: llvm_unreachable("Unexpected value type for atomic!");
1306 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_SUB_1; break;
1307 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_SUB_2; break;
1308 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_SUB_4; break;
1309 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_SUB_8; break;
1310 case MVT::i128:LC = RTLIB::SYNC_FETCH_AND_SUB_16;break;
1313 case ISD::ATOMIC_LOAD_AND:
1314 switch (VT.SimpleTy) {
1315 default: llvm_unreachable("Unexpected value type for atomic!");
1316 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_AND_1; break;
1317 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_AND_2; break;
1318 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_AND_4; break;
1319 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_AND_8; break;
1320 case MVT::i128:LC = RTLIB::SYNC_FETCH_AND_AND_16;break;
1323 case ISD::ATOMIC_LOAD_OR:
1324 switch (VT.SimpleTy) {
1325 default: llvm_unreachable("Unexpected value type for atomic!");
1326 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_OR_1; break;
1327 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_OR_2; break;
1328 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_OR_4; break;
1329 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_OR_8; break;
1330 case MVT::i128:LC = RTLIB::SYNC_FETCH_AND_OR_16;break;
1333 case ISD::ATOMIC_LOAD_XOR:
1334 switch (VT.SimpleTy) {
1335 default: llvm_unreachable("Unexpected value type for atomic!");
1336 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_XOR_1; break;
1337 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_XOR_2; break;
1338 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_XOR_4; break;
1339 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_XOR_8; break;
1340 case MVT::i128:LC = RTLIB::SYNC_FETCH_AND_XOR_16;break;
1343 case ISD::ATOMIC_LOAD_NAND:
1344 switch (VT.SimpleTy) {
1345 default: llvm_unreachable("Unexpected value type for atomic!");
1346 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_NAND_1; break;
1347 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_NAND_2; break;
1348 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_NAND_4; break;
1349 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_NAND_8; break;
1350 case MVT::i128:LC = RTLIB::SYNC_FETCH_AND_NAND_16;break;
1355 return ExpandChainLibCall(LC, Node, false);
1358 /// ExpandShiftByConstant - N is a shift by a value that needs to be expanded,
1359 /// and the shift amount is a constant 'Amt'. Expand the operation.
1360 void DAGTypeLegalizer::ExpandShiftByConstant(SDNode *N, unsigned Amt,
1361 SDValue &Lo, SDValue &Hi) {
1362 assert(Amt && "Expected zero shifts to be already optimized away.");
1364 // Expand the incoming operand to be shifted, so that we have its parts
1366 GetExpandedInteger(N->getOperand(0), InL, InH);
1368 EVT NVT = InL.getValueType();
1369 unsigned VTBits = N->getValueType(0).getSizeInBits();
1370 unsigned NVTBits = NVT.getSizeInBits();
1371 EVT ShTy = N->getOperand(1).getValueType();
1373 if (N->getOpcode() == ISD::SHL) {
1375 Lo = Hi = DAG.getConstant(0, NVT);
1376 } else if (Amt > NVTBits) {
1377 Lo = DAG.getConstant(0, NVT);
1378 Hi = DAG.getNode(ISD::SHL, DL,
1379 NVT, InL, DAG.getConstant(Amt-NVTBits, ShTy));
1380 } else if (Amt == NVTBits) {
1381 Lo = DAG.getConstant(0, NVT);
1383 } else if (Amt == 1 &&
1384 TLI.isOperationLegalOrCustom(ISD::ADDC,
1385 TLI.getTypeToExpandTo(*DAG.getContext(), NVT))) {
1386 // Emit this X << 1 as X+X.
1387 SDVTList VTList = DAG.getVTList(NVT, MVT::Glue);
1388 SDValue LoOps[2] = { InL, InL };
1389 Lo = DAG.getNode(ISD::ADDC, DL, VTList, LoOps);
1390 SDValue HiOps[3] = { InH, InH, Lo.getValue(1) };
1391 Hi = DAG.getNode(ISD::ADDE, DL, VTList, HiOps);
1393 Lo = DAG.getNode(ISD::SHL, DL, NVT, InL, DAG.getConstant(Amt, ShTy));
1394 Hi = DAG.getNode(ISD::OR, DL, NVT,
1395 DAG.getNode(ISD::SHL, DL, NVT, InH,
1396 DAG.getConstant(Amt, ShTy)),
1397 DAG.getNode(ISD::SRL, DL, NVT, InL,
1398 DAG.getConstant(NVTBits-Amt, ShTy)));
1403 if (N->getOpcode() == ISD::SRL) {
1405 Lo = DAG.getConstant(0, NVT);
1406 Hi = DAG.getConstant(0, NVT);
1407 } else if (Amt > NVTBits) {
1408 Lo = DAG.getNode(ISD::SRL, DL,
1409 NVT, InH, DAG.getConstant(Amt-NVTBits,ShTy));
1410 Hi = DAG.getConstant(0, NVT);
1411 } else if (Amt == NVTBits) {
1413 Hi = DAG.getConstant(0, NVT);
1415 Lo = DAG.getNode(ISD::OR, DL, NVT,
1416 DAG.getNode(ISD::SRL, DL, NVT, InL,
1417 DAG.getConstant(Amt, ShTy)),
1418 DAG.getNode(ISD::SHL, DL, NVT, InH,
1419 DAG.getConstant(NVTBits-Amt, ShTy)));
1420 Hi = DAG.getNode(ISD::SRL, DL, NVT, InH, DAG.getConstant(Amt, ShTy));
1425 assert(N->getOpcode() == ISD::SRA && "Unknown shift!");
1427 Hi = Lo = DAG.getNode(ISD::SRA, DL, NVT, InH,
1428 DAG.getConstant(NVTBits-1, ShTy));
1429 } else if (Amt > NVTBits) {
1430 Lo = DAG.getNode(ISD::SRA, DL, NVT, InH,
1431 DAG.getConstant(Amt-NVTBits, ShTy));
1432 Hi = DAG.getNode(ISD::SRA, DL, NVT, InH,
1433 DAG.getConstant(NVTBits-1, ShTy));
1434 } else if (Amt == NVTBits) {
1436 Hi = DAG.getNode(ISD::SRA, DL, NVT, InH,
1437 DAG.getConstant(NVTBits-1, ShTy));
1439 Lo = DAG.getNode(ISD::OR, DL, NVT,
1440 DAG.getNode(ISD::SRL, DL, NVT, InL,
1441 DAG.getConstant(Amt, ShTy)),
1442 DAG.getNode(ISD::SHL, DL, NVT, InH,
1443 DAG.getConstant(NVTBits-Amt, ShTy)));
1444 Hi = DAG.getNode(ISD::SRA, DL, NVT, InH, DAG.getConstant(Amt, ShTy));
1448 /// ExpandShiftWithKnownAmountBit - Try to determine whether we can simplify
1449 /// this shift based on knowledge of the high bit of the shift amount. If we
1450 /// can tell this, we know that it is >= 32 or < 32, without knowing the actual
1452 bool DAGTypeLegalizer::
1453 ExpandShiftWithKnownAmountBit(SDNode *N, SDValue &Lo, SDValue &Hi) {
1454 SDValue Amt = N->getOperand(1);
1455 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1456 EVT ShTy = Amt.getValueType();
1457 unsigned ShBits = ShTy.getScalarType().getSizeInBits();
1458 unsigned NVTBits = NVT.getScalarType().getSizeInBits();
1459 assert(isPowerOf2_32(NVTBits) &&
1460 "Expanded integer type size not a power of two!");
1463 APInt HighBitMask = APInt::getHighBitsSet(ShBits, ShBits - Log2_32(NVTBits));
1464 APInt KnownZero, KnownOne;
1465 DAG.computeKnownBits(N->getOperand(1), KnownZero, KnownOne);
1467 // If we don't know anything about the high bits, exit.
1468 if (((KnownZero|KnownOne) & HighBitMask) == 0)
1471 // Get the incoming operand to be shifted.
1473 GetExpandedInteger(N->getOperand(0), InL, InH);
1475 // If we know that any of the high bits of the shift amount are one, then we
1476 // can do this as a couple of simple shifts.
1477 if (KnownOne.intersects(HighBitMask)) {
1478 // Mask out the high bit, which we know is set.
1479 Amt = DAG.getNode(ISD::AND, dl, ShTy, Amt,
1480 DAG.getConstant(~HighBitMask, ShTy));
1482 switch (N->getOpcode()) {
1483 default: llvm_unreachable("Unknown shift");
1485 Lo = DAG.getConstant(0, NVT); // Low part is zero.
1486 Hi = DAG.getNode(ISD::SHL, dl, NVT, InL, Amt); // High part from Lo part.
1489 Hi = DAG.getConstant(0, NVT); // Hi part is zero.
1490 Lo = DAG.getNode(ISD::SRL, dl, NVT, InH, Amt); // Lo part from Hi part.
1493 Hi = DAG.getNode(ISD::SRA, dl, NVT, InH, // Sign extend high part.
1494 DAG.getConstant(NVTBits-1, ShTy));
1495 Lo = DAG.getNode(ISD::SRA, dl, NVT, InH, Amt); // Lo part from Hi part.
1500 // If we know that all of the high bits of the shift amount are zero, then we
1501 // can do this as a couple of simple shifts.
1502 if ((KnownZero & HighBitMask) == HighBitMask) {
1503 // Calculate 31-x. 31 is used instead of 32 to avoid creating an undefined
1504 // shift if x is zero. We can use XOR here because x is known to be smaller
1506 SDValue Amt2 = DAG.getNode(ISD::XOR, dl, ShTy, Amt,
1507 DAG.getConstant(NVTBits-1, ShTy));
1510 switch (N->getOpcode()) {
1511 default: llvm_unreachable("Unknown shift");
1512 case ISD::SHL: Op1 = ISD::SHL; Op2 = ISD::SRL; break;
1514 case ISD::SRA: Op1 = ISD::SRL; Op2 = ISD::SHL; break;
1517 // When shifting right the arithmetic for Lo and Hi is swapped.
1518 if (N->getOpcode() != ISD::SHL)
1519 std::swap(InL, InH);
1521 // Use a little trick to get the bits that move from Lo to Hi. First
1522 // shift by one bit.
1523 SDValue Sh1 = DAG.getNode(Op2, dl, NVT, InL, DAG.getConstant(1, ShTy));
1524 // Then compute the remaining shift with amount-1.
1525 SDValue Sh2 = DAG.getNode(Op2, dl, NVT, Sh1, Amt2);
1527 Lo = DAG.getNode(N->getOpcode(), dl, NVT, InL, Amt);
1528 Hi = DAG.getNode(ISD::OR, dl, NVT, DAG.getNode(Op1, dl, NVT, InH, Amt),Sh2);
1530 if (N->getOpcode() != ISD::SHL)
1538 /// ExpandShiftWithUnknownAmountBit - Fully general expansion of integer shift
1540 bool DAGTypeLegalizer::
1541 ExpandShiftWithUnknownAmountBit(SDNode *N, SDValue &Lo, SDValue &Hi) {
1542 SDValue Amt = N->getOperand(1);
1543 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1544 EVT ShTy = Amt.getValueType();
1545 unsigned NVTBits = NVT.getSizeInBits();
1546 assert(isPowerOf2_32(NVTBits) &&
1547 "Expanded integer type size not a power of two!");
1550 // Get the incoming operand to be shifted.
1552 GetExpandedInteger(N->getOperand(0), InL, InH);
1554 SDValue NVBitsNode = DAG.getConstant(NVTBits, ShTy);
1555 SDValue AmtExcess = DAG.getNode(ISD::SUB, dl, ShTy, Amt, NVBitsNode);
1556 SDValue AmtLack = DAG.getNode(ISD::SUB, dl, ShTy, NVBitsNode, Amt);
1557 SDValue isShort = DAG.getSetCC(dl, getSetCCResultType(ShTy),
1558 Amt, NVBitsNode, ISD::SETULT);
1560 SDValue LoS, HiS, LoL, HiL;
1561 switch (N->getOpcode()) {
1562 default: llvm_unreachable("Unknown shift");
1564 // Short: ShAmt < NVTBits
1565 LoS = DAG.getNode(ISD::SHL, dl, NVT, InL, Amt);
1566 HiS = DAG.getNode(ISD::OR, dl, NVT,
1567 DAG.getNode(ISD::SHL, dl, NVT, InH, Amt),
1568 // FIXME: If Amt is zero, the following shift generates an undefined result
1569 // on some architectures.
1570 DAG.getNode(ISD::SRL, dl, NVT, InL, AmtLack));
1572 // Long: ShAmt >= NVTBits
1573 LoL = DAG.getConstant(0, NVT); // Lo part is zero.
1574 HiL = DAG.getNode(ISD::SHL, dl, NVT, InL, AmtExcess); // Hi from Lo part.
1576 Lo = DAG.getSelect(dl, NVT, isShort, LoS, LoL);
1577 Hi = DAG.getSelect(dl, NVT, isShort, HiS, HiL);
1580 // Short: ShAmt < NVTBits
1581 HiS = DAG.getNode(ISD::SRL, dl, NVT, InH, Amt);
1582 LoS = DAG.getNode(ISD::OR, dl, NVT,
1583 DAG.getNode(ISD::SRL, dl, NVT, InL, Amt),
1584 // FIXME: If Amt is zero, the following shift generates an undefined result
1585 // on some architectures.
1586 DAG.getNode(ISD::SHL, dl, NVT, InH, AmtLack));
1588 // Long: ShAmt >= NVTBits
1589 HiL = DAG.getConstant(0, NVT); // Hi part is zero.
1590 LoL = DAG.getNode(ISD::SRL, dl, NVT, InH, AmtExcess); // Lo from Hi part.
1592 Lo = DAG.getSelect(dl, NVT, isShort, LoS, LoL);
1593 Hi = DAG.getSelect(dl, NVT, isShort, HiS, HiL);
1596 // Short: ShAmt < NVTBits
1597 HiS = DAG.getNode(ISD::SRA, dl, NVT, InH, Amt);
1598 LoS = DAG.getNode(ISD::OR, dl, NVT,
1599 DAG.getNode(ISD::SRL, dl, NVT, InL, Amt),
1600 // FIXME: If Amt is zero, the following shift generates an undefined result
1601 // on some architectures.
1602 DAG.getNode(ISD::SHL, dl, NVT, InH, AmtLack));
1604 // Long: ShAmt >= NVTBits
1605 HiL = DAG.getNode(ISD::SRA, dl, NVT, InH, // Sign of Hi part.
1606 DAG.getConstant(NVTBits-1, ShTy));
1607 LoL = DAG.getNode(ISD::SRA, dl, NVT, InH, AmtExcess); // Lo from Hi part.
1609 Lo = DAG.getSelect(dl, NVT, isShort, LoS, LoL);
1610 Hi = DAG.getSelect(dl, NVT, isShort, HiS, HiL);
1615 void DAGTypeLegalizer::ExpandIntRes_ADDSUB(SDNode *N,
1616 SDValue &Lo, SDValue &Hi) {
1618 // Expand the subcomponents.
1619 SDValue LHSL, LHSH, RHSL, RHSH;
1620 GetExpandedInteger(N->getOperand(0), LHSL, LHSH);
1621 GetExpandedInteger(N->getOperand(1), RHSL, RHSH);
1623 EVT NVT = LHSL.getValueType();
1624 SDValue LoOps[2] = { LHSL, RHSL };
1625 SDValue HiOps[3] = { LHSH, RHSH };
1627 // Do not generate ADDC/ADDE or SUBC/SUBE if the target does not support
1628 // them. TODO: Teach operation legalization how to expand unsupported
1629 // ADDC/ADDE/SUBC/SUBE. The problem is that these operations generate
1630 // a carry of type MVT::Glue, but there doesn't seem to be any way to
1631 // generate a value of this type in the expanded code sequence.
1633 TLI.isOperationLegalOrCustom(N->getOpcode() == ISD::ADD ?
1634 ISD::ADDC : ISD::SUBC,
1635 TLI.getTypeToExpandTo(*DAG.getContext(), NVT));
1638 SDVTList VTList = DAG.getVTList(NVT, MVT::Glue);
1639 if (N->getOpcode() == ISD::ADD) {
1640 Lo = DAG.getNode(ISD::ADDC, dl, VTList, LoOps);
1641 HiOps[2] = Lo.getValue(1);
1642 Hi = DAG.getNode(ISD::ADDE, dl, VTList, HiOps);
1644 Lo = DAG.getNode(ISD::SUBC, dl, VTList, LoOps);
1645 HiOps[2] = Lo.getValue(1);
1646 Hi = DAG.getNode(ISD::SUBE, dl, VTList, HiOps);
1651 if (N->getOpcode() == ISD::ADD) {
1652 Lo = DAG.getNode(ISD::ADD, dl, NVT, LoOps);
1653 Hi = DAG.getNode(ISD::ADD, dl, NVT, makeArrayRef(HiOps, 2));
1654 SDValue Cmp1 = DAG.getSetCC(dl, getSetCCResultType(NVT), Lo, LoOps[0],
1656 SDValue Carry1 = DAG.getSelect(dl, NVT, Cmp1,
1657 DAG.getConstant(1, NVT),
1658 DAG.getConstant(0, NVT));
1659 SDValue Cmp2 = DAG.getSetCC(dl, getSetCCResultType(NVT), Lo, LoOps[1],
1661 SDValue Carry2 = DAG.getSelect(dl, NVT, Cmp2,
1662 DAG.getConstant(1, NVT), Carry1);
1663 Hi = DAG.getNode(ISD::ADD, dl, NVT, Hi, Carry2);
1665 Lo = DAG.getNode(ISD::SUB, dl, NVT, LoOps);
1666 Hi = DAG.getNode(ISD::SUB, dl, NVT, makeArrayRef(HiOps, 2));
1668 DAG.getSetCC(dl, getSetCCResultType(LoOps[0].getValueType()),
1669 LoOps[0], LoOps[1], ISD::SETULT);
1670 SDValue Borrow = DAG.getSelect(dl, NVT, Cmp,
1671 DAG.getConstant(1, NVT),
1672 DAG.getConstant(0, NVT));
1673 Hi = DAG.getNode(ISD::SUB, dl, NVT, Hi, Borrow);
1677 void DAGTypeLegalizer::ExpandIntRes_ADDSUBC(SDNode *N,
1678 SDValue &Lo, SDValue &Hi) {
1679 // Expand the subcomponents.
1680 SDValue LHSL, LHSH, RHSL, RHSH;
1682 GetExpandedInteger(N->getOperand(0), LHSL, LHSH);
1683 GetExpandedInteger(N->getOperand(1), RHSL, RHSH);
1684 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Glue);
1685 SDValue LoOps[2] = { LHSL, RHSL };
1686 SDValue HiOps[3] = { LHSH, RHSH };
1688 if (N->getOpcode() == ISD::ADDC) {
1689 Lo = DAG.getNode(ISD::ADDC, dl, VTList, LoOps);
1690 HiOps[2] = Lo.getValue(1);
1691 Hi = DAG.getNode(ISD::ADDE, dl, VTList, HiOps);
1693 Lo = DAG.getNode(ISD::SUBC, dl, VTList, LoOps);
1694 HiOps[2] = Lo.getValue(1);
1695 Hi = DAG.getNode(ISD::SUBE, dl, VTList, HiOps);
1698 // Legalized the flag result - switch anything that used the old flag to
1700 ReplaceValueWith(SDValue(N, 1), Hi.getValue(1));
1703 void DAGTypeLegalizer::ExpandIntRes_ADDSUBE(SDNode *N,
1704 SDValue &Lo, SDValue &Hi) {
1705 // Expand the subcomponents.
1706 SDValue LHSL, LHSH, RHSL, RHSH;
1708 GetExpandedInteger(N->getOperand(0), LHSL, LHSH);
1709 GetExpandedInteger(N->getOperand(1), RHSL, RHSH);
1710 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Glue);
1711 SDValue LoOps[3] = { LHSL, RHSL, N->getOperand(2) };
1712 SDValue HiOps[3] = { LHSH, RHSH };
1714 Lo = DAG.getNode(N->getOpcode(), dl, VTList, LoOps);
1715 HiOps[2] = Lo.getValue(1);
1716 Hi = DAG.getNode(N->getOpcode(), dl, VTList, HiOps);
1718 // Legalized the flag result - switch anything that used the old flag to
1720 ReplaceValueWith(SDValue(N, 1), Hi.getValue(1));
1723 void DAGTypeLegalizer::ExpandIntRes_MERGE_VALUES(SDNode *N, unsigned ResNo,
1724 SDValue &Lo, SDValue &Hi) {
1725 SDValue Res = DisintegrateMERGE_VALUES(N, ResNo);
1726 SplitInteger(Res, Lo, Hi);
1729 void DAGTypeLegalizer::ExpandIntRes_ANY_EXTEND(SDNode *N,
1730 SDValue &Lo, SDValue &Hi) {
1731 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1733 SDValue Op = N->getOperand(0);
1734 if (Op.getValueType().bitsLE(NVT)) {
1735 // The low part is any extension of the input (which degenerates to a copy).
1736 Lo = DAG.getNode(ISD::ANY_EXTEND, dl, NVT, Op);
1737 Hi = DAG.getUNDEF(NVT); // The high part is undefined.
1739 // For example, extension of an i48 to an i64. The operand type necessarily
1740 // promotes to the result type, so will end up being expanded too.
1741 assert(getTypeAction(Op.getValueType()) ==
1742 TargetLowering::TypePromoteInteger &&
1743 "Only know how to promote this result!");
1744 SDValue Res = GetPromotedInteger(Op);
1745 assert(Res.getValueType() == N->getValueType(0) &&
1746 "Operand over promoted?");
1747 // Split the promoted operand. This will simplify when it is expanded.
1748 SplitInteger(Res, Lo, Hi);
1752 void DAGTypeLegalizer::ExpandIntRes_AssertSext(SDNode *N,
1753 SDValue &Lo, SDValue &Hi) {
1755 GetExpandedInteger(N->getOperand(0), Lo, Hi);
1756 EVT NVT = Lo.getValueType();
1757 EVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
1758 unsigned NVTBits = NVT.getSizeInBits();
1759 unsigned EVTBits = EVT.getSizeInBits();
1761 if (NVTBits < EVTBits) {
1762 Hi = DAG.getNode(ISD::AssertSext, dl, NVT, Hi,
1763 DAG.getValueType(EVT::getIntegerVT(*DAG.getContext(),
1764 EVTBits - NVTBits)));
1766 Lo = DAG.getNode(ISD::AssertSext, dl, NVT, Lo, DAG.getValueType(EVT));
1767 // The high part replicates the sign bit of Lo, make it explicit.
1768 Hi = DAG.getNode(ISD::SRA, dl, NVT, Lo,
1769 DAG.getConstant(NVTBits-1, TLI.getPointerTy()));
1773 void DAGTypeLegalizer::ExpandIntRes_AssertZext(SDNode *N,
1774 SDValue &Lo, SDValue &Hi) {
1776 GetExpandedInteger(N->getOperand(0), Lo, Hi);
1777 EVT NVT = Lo.getValueType();
1778 EVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
1779 unsigned NVTBits = NVT.getSizeInBits();
1780 unsigned EVTBits = EVT.getSizeInBits();
1782 if (NVTBits < EVTBits) {
1783 Hi = DAG.getNode(ISD::AssertZext, dl, NVT, Hi,
1784 DAG.getValueType(EVT::getIntegerVT(*DAG.getContext(),
1785 EVTBits - NVTBits)));
1787 Lo = DAG.getNode(ISD::AssertZext, dl, NVT, Lo, DAG.getValueType(EVT));
1788 // The high part must be zero, make it explicit.
1789 Hi = DAG.getConstant(0, NVT);
1793 void DAGTypeLegalizer::ExpandIntRes_BSWAP(SDNode *N,
1794 SDValue &Lo, SDValue &Hi) {
1796 GetExpandedInteger(N->getOperand(0), Hi, Lo); // Note swapped operands.
1797 Lo = DAG.getNode(ISD::BSWAP, dl, Lo.getValueType(), Lo);
1798 Hi = DAG.getNode(ISD::BSWAP, dl, Hi.getValueType(), Hi);
1801 void DAGTypeLegalizer::ExpandIntRes_Constant(SDNode *N,
1802 SDValue &Lo, SDValue &Hi) {
1803 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1804 unsigned NBitWidth = NVT.getSizeInBits();
1805 auto Constant = cast<ConstantSDNode>(N);
1806 const APInt &Cst = Constant->getAPIntValue();
1807 bool IsTarget = Constant->isTargetOpcode();
1808 bool IsOpaque = Constant->isOpaque();
1809 Lo = DAG.getConstant(Cst.trunc(NBitWidth), NVT, IsTarget, IsOpaque);
1810 Hi = DAG.getConstant(Cst.lshr(NBitWidth).trunc(NBitWidth), NVT, IsTarget,
1814 void DAGTypeLegalizer::ExpandIntRes_CTLZ(SDNode *N,
1815 SDValue &Lo, SDValue &Hi) {
1817 // ctlz (HiLo) -> Hi != 0 ? ctlz(Hi) : (ctlz(Lo)+32)
1818 GetExpandedInteger(N->getOperand(0), Lo, Hi);
1819 EVT NVT = Lo.getValueType();
1821 SDValue HiNotZero = DAG.getSetCC(dl, getSetCCResultType(NVT), Hi,
1822 DAG.getConstant(0, NVT), ISD::SETNE);
1824 SDValue LoLZ = DAG.getNode(N->getOpcode(), dl, NVT, Lo);
1825 SDValue HiLZ = DAG.getNode(ISD::CTLZ_ZERO_UNDEF, dl, NVT, Hi);
1827 Lo = DAG.getSelect(dl, NVT, HiNotZero, HiLZ,
1828 DAG.getNode(ISD::ADD, dl, NVT, LoLZ,
1829 DAG.getConstant(NVT.getSizeInBits(), NVT)));
1830 Hi = DAG.getConstant(0, NVT);
1833 void DAGTypeLegalizer::ExpandIntRes_CTPOP(SDNode *N,
1834 SDValue &Lo, SDValue &Hi) {
1836 // ctpop(HiLo) -> ctpop(Hi)+ctpop(Lo)
1837 GetExpandedInteger(N->getOperand(0), Lo, Hi);
1838 EVT NVT = Lo.getValueType();
1839 Lo = DAG.getNode(ISD::ADD, dl, NVT, DAG.getNode(ISD::CTPOP, dl, NVT, Lo),
1840 DAG.getNode(ISD::CTPOP, dl, NVT, Hi));
1841 Hi = DAG.getConstant(0, NVT);
1844 void DAGTypeLegalizer::ExpandIntRes_CTTZ(SDNode *N,
1845 SDValue &Lo, SDValue &Hi) {
1847 // cttz (HiLo) -> Lo != 0 ? cttz(Lo) : (cttz(Hi)+32)
1848 GetExpandedInteger(N->getOperand(0), Lo, Hi);
1849 EVT NVT = Lo.getValueType();
1851 SDValue LoNotZero = DAG.getSetCC(dl, getSetCCResultType(NVT), Lo,
1852 DAG.getConstant(0, NVT), ISD::SETNE);
1854 SDValue LoLZ = DAG.getNode(ISD::CTTZ_ZERO_UNDEF, dl, NVT, Lo);
1855 SDValue HiLZ = DAG.getNode(N->getOpcode(), dl, NVT, Hi);
1857 Lo = DAG.getSelect(dl, NVT, LoNotZero, LoLZ,
1858 DAG.getNode(ISD::ADD, dl, NVT, HiLZ,
1859 DAG.getConstant(NVT.getSizeInBits(), NVT)));
1860 Hi = DAG.getConstant(0, NVT);
1863 void DAGTypeLegalizer::ExpandIntRes_FP_TO_SINT(SDNode *N, SDValue &Lo,
1866 EVT VT = N->getValueType(0);
1867 SDValue Op = N->getOperand(0);
1868 RTLIB::Libcall LC = RTLIB::getFPTOSINT(Op.getValueType(), VT);
1869 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected fp-to-sint conversion!");
1870 SplitInteger(TLI.makeLibCall(DAG, LC, VT, &Op, 1, true/*irrelevant*/,
1875 void DAGTypeLegalizer::ExpandIntRes_FP_TO_UINT(SDNode *N, SDValue &Lo,
1878 EVT VT = N->getValueType(0);
1879 SDValue Op = N->getOperand(0);
1880 RTLIB::Libcall LC = RTLIB::getFPTOUINT(Op.getValueType(), VT);
1881 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected fp-to-uint conversion!");
1882 SplitInteger(TLI.makeLibCall(DAG, LC, VT, &Op, 1, false/*irrelevant*/,
1887 void DAGTypeLegalizer::ExpandIntRes_LOAD(LoadSDNode *N,
1888 SDValue &Lo, SDValue &Hi) {
1889 if (ISD::isNormalLoad(N)) {
1890 ExpandRes_NormalLoad(N, Lo, Hi);
1894 assert(ISD::isUNINDEXEDLoad(N) && "Indexed load during type legalization!");
1896 EVT VT = N->getValueType(0);
1897 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
1898 SDValue Ch = N->getChain();
1899 SDValue Ptr = N->getBasePtr();
1900 ISD::LoadExtType ExtType = N->getExtensionType();
1901 unsigned Alignment = N->getAlignment();
1902 bool isVolatile = N->isVolatile();
1903 bool isNonTemporal = N->isNonTemporal();
1904 bool isInvariant = N->isInvariant();
1905 AAMDNodes AAInfo = N->getAAInfo();
1908 assert(NVT.isByteSized() && "Expanded type not byte sized!");
1910 if (N->getMemoryVT().bitsLE(NVT)) {
1911 EVT MemVT = N->getMemoryVT();
1913 Lo = DAG.getExtLoad(ExtType, dl, NVT, Ch, Ptr, N->getPointerInfo(),
1914 MemVT, isVolatile, isNonTemporal, isInvariant,
1917 // Remember the chain.
1918 Ch = Lo.getValue(1);
1920 if (ExtType == ISD::SEXTLOAD) {
1921 // The high part is obtained by SRA'ing all but one of the bits of the
1923 unsigned LoSize = Lo.getValueType().getSizeInBits();
1924 Hi = DAG.getNode(ISD::SRA, dl, NVT, Lo,
1925 DAG.getConstant(LoSize-1, TLI.getPointerTy()));
1926 } else if (ExtType == ISD::ZEXTLOAD) {
1927 // The high part is just a zero.
1928 Hi = DAG.getConstant(0, NVT);
1930 assert(ExtType == ISD::EXTLOAD && "Unknown extload!");
1931 // The high part is undefined.
1932 Hi = DAG.getUNDEF(NVT);
1934 } else if (TLI.isLittleEndian()) {
1935 // Little-endian - low bits are at low addresses.
1936 Lo = DAG.getLoad(NVT, dl, Ch, Ptr, N->getPointerInfo(),
1937 isVolatile, isNonTemporal, isInvariant, Alignment,
1940 unsigned ExcessBits =
1941 N->getMemoryVT().getSizeInBits() - NVT.getSizeInBits();
1942 EVT NEVT = EVT::getIntegerVT(*DAG.getContext(), ExcessBits);
1944 // Increment the pointer to the other half.
1945 unsigned IncrementSize = NVT.getSizeInBits()/8;
1946 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
1947 DAG.getConstant(IncrementSize, Ptr.getValueType()));
1948 Hi = DAG.getExtLoad(ExtType, dl, NVT, Ch, Ptr,
1949 N->getPointerInfo().getWithOffset(IncrementSize), NEVT,
1950 isVolatile, isNonTemporal, isInvariant,
1951 MinAlign(Alignment, IncrementSize), AAInfo);
1953 // Build a factor node to remember that this load is independent of the
1955 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
1958 // Big-endian - high bits are at low addresses. Favor aligned loads at
1959 // the cost of some bit-fiddling.
1960 EVT MemVT = N->getMemoryVT();
1961 unsigned EBytes = MemVT.getStoreSize();
1962 unsigned IncrementSize = NVT.getSizeInBits()/8;
1963 unsigned ExcessBits = (EBytes - IncrementSize)*8;
1965 // Load both the high bits and maybe some of the low bits.
1966 Hi = DAG.getExtLoad(ExtType, dl, NVT, Ch, Ptr, N->getPointerInfo(),
1967 EVT::getIntegerVT(*DAG.getContext(),
1968 MemVT.getSizeInBits() - ExcessBits),
1969 isVolatile, isNonTemporal, isInvariant, Alignment,
1972 // Increment the pointer to the other half.
1973 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
1974 DAG.getConstant(IncrementSize, Ptr.getValueType()));
1975 // Load the rest of the low bits.
1976 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, NVT, Ch, Ptr,
1977 N->getPointerInfo().getWithOffset(IncrementSize),
1978 EVT::getIntegerVT(*DAG.getContext(), ExcessBits),
1979 isVolatile, isNonTemporal, isInvariant,
1980 MinAlign(Alignment, IncrementSize), AAInfo);
1982 // Build a factor node to remember that this load is independent of the
1984 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
1987 if (ExcessBits < NVT.getSizeInBits()) {
1988 // Transfer low bits from the bottom of Hi to the top of Lo.
1989 Lo = DAG.getNode(ISD::OR, dl, NVT, Lo,
1990 DAG.getNode(ISD::SHL, dl, NVT, Hi,
1991 DAG.getConstant(ExcessBits,
1992 TLI.getPointerTy())));
1993 // Move high bits to the right position in Hi.
1994 Hi = DAG.getNode(ExtType == ISD::SEXTLOAD ? ISD::SRA : ISD::SRL, dl,
1996 DAG.getConstant(NVT.getSizeInBits() - ExcessBits,
1997 TLI.getPointerTy()));
2001 // Legalized the chain result - switch anything that used the old chain to
2003 ReplaceValueWith(SDValue(N, 1), Ch);
2006 void DAGTypeLegalizer::ExpandIntRes_Logical(SDNode *N,
2007 SDValue &Lo, SDValue &Hi) {
2009 SDValue LL, LH, RL, RH;
2010 GetExpandedInteger(N->getOperand(0), LL, LH);
2011 GetExpandedInteger(N->getOperand(1), RL, RH);
2012 Lo = DAG.getNode(N->getOpcode(), dl, LL.getValueType(), LL, RL);
2013 Hi = DAG.getNode(N->getOpcode(), dl, LL.getValueType(), LH, RH);
2016 void DAGTypeLegalizer::ExpandIntRes_MUL(SDNode *N,
2017 SDValue &Lo, SDValue &Hi) {
2018 EVT VT = N->getValueType(0);
2019 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
2022 SDValue LL, LH, RL, RH;
2023 GetExpandedInteger(N->getOperand(0), LL, LH);
2024 GetExpandedInteger(N->getOperand(1), RL, RH);
2026 if (TLI.expandMUL(N, Lo, Hi, NVT, DAG, LL, LH, RL, RH))
2029 // If nothing else, we can make a libcall.
2030 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
2032 LC = RTLIB::MUL_I16;
2033 else if (VT == MVT::i32)
2034 LC = RTLIB::MUL_I32;
2035 else if (VT == MVT::i64)
2036 LC = RTLIB::MUL_I64;
2037 else if (VT == MVT::i128)
2038 LC = RTLIB::MUL_I128;
2039 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported MUL!");
2041 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
2042 SplitInteger(TLI.makeLibCall(DAG, LC, VT, Ops, 2, true/*irrelevant*/,
2047 void DAGTypeLegalizer::ExpandIntRes_SADDSUBO(SDNode *Node,
2048 SDValue &Lo, SDValue &Hi) {
2049 SDValue LHS = Node->getOperand(0);
2050 SDValue RHS = Node->getOperand(1);
2053 // Expand the result by simply replacing it with the equivalent
2054 // non-overflow-checking operation.
2055 SDValue Sum = DAG.getNode(Node->getOpcode() == ISD::SADDO ?
2056 ISD::ADD : ISD::SUB, dl, LHS.getValueType(),
2058 SplitInteger(Sum, Lo, Hi);
2060 // Compute the overflow.
2062 // LHSSign -> LHS >= 0
2063 // RHSSign -> RHS >= 0
2064 // SumSign -> Sum >= 0
2067 // Overflow -> (LHSSign == RHSSign) && (LHSSign != SumSign)
2069 // Overflow -> (LHSSign != RHSSign) && (LHSSign != SumSign)
2071 EVT OType = Node->getValueType(1);
2072 SDValue Zero = DAG.getConstant(0, LHS.getValueType());
2074 SDValue LHSSign = DAG.getSetCC(dl, OType, LHS, Zero, ISD::SETGE);
2075 SDValue RHSSign = DAG.getSetCC(dl, OType, RHS, Zero, ISD::SETGE);
2076 SDValue SignsMatch = DAG.getSetCC(dl, OType, LHSSign, RHSSign,
2077 Node->getOpcode() == ISD::SADDO ?
2078 ISD::SETEQ : ISD::SETNE);
2080 SDValue SumSign = DAG.getSetCC(dl, OType, Sum, Zero, ISD::SETGE);
2081 SDValue SumSignNE = DAG.getSetCC(dl, OType, LHSSign, SumSign, ISD::SETNE);
2083 SDValue Cmp = DAG.getNode(ISD::AND, dl, OType, SignsMatch, SumSignNE);
2085 // Use the calculated overflow everywhere.
2086 ReplaceValueWith(SDValue(Node, 1), Cmp);
2089 void DAGTypeLegalizer::ExpandIntRes_SDIV(SDNode *N,
2090 SDValue &Lo, SDValue &Hi) {
2091 EVT VT = N->getValueType(0);
2094 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
2096 LC = RTLIB::SDIV_I16;
2097 else if (VT == MVT::i32)
2098 LC = RTLIB::SDIV_I32;
2099 else if (VT == MVT::i64)
2100 LC = RTLIB::SDIV_I64;
2101 else if (VT == MVT::i128)
2102 LC = RTLIB::SDIV_I128;
2103 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported SDIV!");
2105 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
2106 SplitInteger(TLI.makeLibCall(DAG, LC, VT, Ops, 2, true, dl).first, Lo, Hi);
2109 void DAGTypeLegalizer::ExpandIntRes_Shift(SDNode *N,
2110 SDValue &Lo, SDValue &Hi) {
2111 EVT VT = N->getValueType(0);
2114 // If we can emit an efficient shift operation, do so now. Check to see if
2115 // the RHS is a constant.
2116 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N->getOperand(1)))
2117 return ExpandShiftByConstant(N, CN->getZExtValue(), Lo, Hi);
2119 // If we can determine that the high bit of the shift is zero or one, even if
2120 // the low bits are variable, emit this shift in an optimized form.
2121 if (ExpandShiftWithKnownAmountBit(N, Lo, Hi))
2124 // If this target supports shift_PARTS, use it. First, map to the _PARTS opc.
2126 if (N->getOpcode() == ISD::SHL) {
2127 PartsOpc = ISD::SHL_PARTS;
2128 } else if (N->getOpcode() == ISD::SRL) {
2129 PartsOpc = ISD::SRL_PARTS;
2131 assert(N->getOpcode() == ISD::SRA && "Unknown shift!");
2132 PartsOpc = ISD::SRA_PARTS;
2135 // Next check to see if the target supports this SHL_PARTS operation or if it
2136 // will custom expand it.
2137 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
2138 TargetLowering::LegalizeAction Action = TLI.getOperationAction(PartsOpc, NVT);
2139 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) ||
2140 Action == TargetLowering::Custom) {
2141 // Expand the subcomponents.
2143 GetExpandedInteger(N->getOperand(0), LHSL, LHSH);
2144 EVT VT = LHSL.getValueType();
2146 // If the shift amount operand is coming from a vector legalization it may
2147 // have an illegal type. Fix that first by casting the operand, otherwise
2148 // the new SHL_PARTS operation would need further legalization.
2149 SDValue ShiftOp = N->getOperand(1);
2150 EVT ShiftTy = TLI.getShiftAmountTy(VT);
2151 assert(ShiftTy.getScalarType().getSizeInBits() >=
2152 Log2_32_Ceil(VT.getScalarType().getSizeInBits()) &&
2153 "ShiftAmountTy is too small to cover the range of this type!");
2154 if (ShiftOp.getValueType() != ShiftTy)
2155 ShiftOp = DAG.getZExtOrTrunc(ShiftOp, dl, ShiftTy);
2157 SDValue Ops[] = { LHSL, LHSH, ShiftOp };
2158 Lo = DAG.getNode(PartsOpc, dl, DAG.getVTList(VT, VT), Ops);
2159 Hi = Lo.getValue(1);
2163 // Otherwise, emit a libcall.
2164 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
2166 if (N->getOpcode() == ISD::SHL) {
2167 isSigned = false; /*sign irrelevant*/
2169 LC = RTLIB::SHL_I16;
2170 else if (VT == MVT::i32)
2171 LC = RTLIB::SHL_I32;
2172 else if (VT == MVT::i64)
2173 LC = RTLIB::SHL_I64;
2174 else if (VT == MVT::i128)
2175 LC = RTLIB::SHL_I128;
2176 } else if (N->getOpcode() == ISD::SRL) {
2179 LC = RTLIB::SRL_I16;
2180 else if (VT == MVT::i32)
2181 LC = RTLIB::SRL_I32;
2182 else if (VT == MVT::i64)
2183 LC = RTLIB::SRL_I64;
2184 else if (VT == MVT::i128)
2185 LC = RTLIB::SRL_I128;
2187 assert(N->getOpcode() == ISD::SRA && "Unknown shift!");
2190 LC = RTLIB::SRA_I16;
2191 else if (VT == MVT::i32)
2192 LC = RTLIB::SRA_I32;
2193 else if (VT == MVT::i64)
2194 LC = RTLIB::SRA_I64;
2195 else if (VT == MVT::i128)
2196 LC = RTLIB::SRA_I128;
2199 if (LC != RTLIB::UNKNOWN_LIBCALL && TLI.getLibcallName(LC)) {
2200 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
2201 SplitInteger(TLI.makeLibCall(DAG, LC, VT, Ops, 2, isSigned, dl).first, Lo,
2206 if (!ExpandShiftWithUnknownAmountBit(N, Lo, Hi))
2207 llvm_unreachable("Unsupported shift!");
2210 void DAGTypeLegalizer::ExpandIntRes_SIGN_EXTEND(SDNode *N,
2211 SDValue &Lo, SDValue &Hi) {
2212 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2214 SDValue Op = N->getOperand(0);
2215 if (Op.getValueType().bitsLE(NVT)) {
2216 // The low part is sign extension of the input (degenerates to a copy).
2217 Lo = DAG.getNode(ISD::SIGN_EXTEND, dl, NVT, N->getOperand(0));
2218 // The high part is obtained by SRA'ing all but one of the bits of low part.
2219 unsigned LoSize = NVT.getSizeInBits();
2220 Hi = DAG.getNode(ISD::SRA, dl, NVT, Lo,
2221 DAG.getConstant(LoSize-1, TLI.getPointerTy()));
2223 // For example, extension of an i48 to an i64. The operand type necessarily
2224 // promotes to the result type, so will end up being expanded too.
2225 assert(getTypeAction(Op.getValueType()) ==
2226 TargetLowering::TypePromoteInteger &&
2227 "Only know how to promote this result!");
2228 SDValue Res = GetPromotedInteger(Op);
2229 assert(Res.getValueType() == N->getValueType(0) &&
2230 "Operand over promoted?");
2231 // Split the promoted operand. This will simplify when it is expanded.
2232 SplitInteger(Res, Lo, Hi);
2233 unsigned ExcessBits =
2234 Op.getValueType().getSizeInBits() - NVT.getSizeInBits();
2235 Hi = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Hi.getValueType(), Hi,
2236 DAG.getValueType(EVT::getIntegerVT(*DAG.getContext(),
2241 void DAGTypeLegalizer::
2242 ExpandIntRes_SIGN_EXTEND_INREG(SDNode *N, SDValue &Lo, SDValue &Hi) {
2244 GetExpandedInteger(N->getOperand(0), Lo, Hi);
2245 EVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
2247 if (EVT.bitsLE(Lo.getValueType())) {
2248 // sext_inreg the low part if needed.
2249 Lo = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Lo.getValueType(), Lo,
2252 // The high part gets the sign extension from the lo-part. This handles
2253 // things like sextinreg V:i64 from i8.
2254 Hi = DAG.getNode(ISD::SRA, dl, Hi.getValueType(), Lo,
2255 DAG.getConstant(Hi.getValueType().getSizeInBits()-1,
2256 TLI.getPointerTy()));
2258 // For example, extension of an i48 to an i64. Leave the low part alone,
2259 // sext_inreg the high part.
2260 unsigned ExcessBits =
2261 EVT.getSizeInBits() - Lo.getValueType().getSizeInBits();
2262 Hi = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Hi.getValueType(), Hi,
2263 DAG.getValueType(EVT::getIntegerVT(*DAG.getContext(),
2268 void DAGTypeLegalizer::ExpandIntRes_SREM(SDNode *N,
2269 SDValue &Lo, SDValue &Hi) {
2270 EVT VT = N->getValueType(0);
2273 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
2275 LC = RTLIB::SREM_I16;
2276 else if (VT == MVT::i32)
2277 LC = RTLIB::SREM_I32;
2278 else if (VT == MVT::i64)
2279 LC = RTLIB::SREM_I64;
2280 else if (VT == MVT::i128)
2281 LC = RTLIB::SREM_I128;
2282 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported SREM!");
2284 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
2285 SplitInteger(TLI.makeLibCall(DAG, LC, VT, Ops, 2, true, dl).first, Lo, Hi);
2288 void DAGTypeLegalizer::ExpandIntRes_TRUNCATE(SDNode *N,
2289 SDValue &Lo, SDValue &Hi) {
2290 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2292 Lo = DAG.getNode(ISD::TRUNCATE, dl, NVT, N->getOperand(0));
2293 Hi = DAG.getNode(ISD::SRL, dl,
2294 N->getOperand(0).getValueType(), N->getOperand(0),
2295 DAG.getConstant(NVT.getSizeInBits(), TLI.getPointerTy()));
2296 Hi = DAG.getNode(ISD::TRUNCATE, dl, NVT, Hi);
2299 void DAGTypeLegalizer::ExpandIntRes_UADDSUBO(SDNode *N,
2300 SDValue &Lo, SDValue &Hi) {
2301 SDValue LHS = N->getOperand(0);
2302 SDValue RHS = N->getOperand(1);
2305 // Expand the result by simply replacing it with the equivalent
2306 // non-overflow-checking operation.
2307 SDValue Sum = DAG.getNode(N->getOpcode() == ISD::UADDO ?
2308 ISD::ADD : ISD::SUB, dl, LHS.getValueType(),
2310 SplitInteger(Sum, Lo, Hi);
2312 // Calculate the overflow: addition overflows iff a + b < a, and subtraction
2313 // overflows iff a - b > a.
2314 SDValue Ofl = DAG.getSetCC(dl, N->getValueType(1), Sum, LHS,
2315 N->getOpcode () == ISD::UADDO ?
2316 ISD::SETULT : ISD::SETUGT);
2318 // Use the calculated overflow everywhere.
2319 ReplaceValueWith(SDValue(N, 1), Ofl);
2322 void DAGTypeLegalizer::ExpandIntRes_XMULO(SDNode *N,
2323 SDValue &Lo, SDValue &Hi) {
2324 EVT VT = N->getValueType(0);
2327 // A divide for UMULO should be faster than a function call.
2328 if (N->getOpcode() == ISD::UMULO) {
2329 SDValue LHS = N->getOperand(0), RHS = N->getOperand(1);
2331 SDValue MUL = DAG.getNode(ISD::MUL, dl, LHS.getValueType(), LHS, RHS);
2332 SplitInteger(MUL, Lo, Hi);
2334 // A divide for UMULO will be faster than a function call. Select to
2335 // make sure we aren't using 0.
2336 SDValue isZero = DAG.getSetCC(dl, getSetCCResultType(VT),
2337 RHS, DAG.getConstant(0, VT), ISD::SETEQ);
2338 SDValue NotZero = DAG.getSelect(dl, VT, isZero,
2339 DAG.getConstant(1, VT), RHS);
2340 SDValue DIV = DAG.getNode(ISD::UDIV, dl, VT, MUL, NotZero);
2341 SDValue Overflow = DAG.getSetCC(dl, N->getValueType(1), DIV, LHS,
2343 Overflow = DAG.getSelect(dl, N->getValueType(1), isZero,
2344 DAG.getConstant(0, N->getValueType(1)),
2346 ReplaceValueWith(SDValue(N, 1), Overflow);
2350 Type *RetTy = VT.getTypeForEVT(*DAG.getContext());
2351 EVT PtrVT = TLI.getPointerTy();
2352 Type *PtrTy = PtrVT.getTypeForEVT(*DAG.getContext());
2354 // Replace this with a libcall that will check overflow.
2355 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
2357 LC = RTLIB::MULO_I32;
2358 else if (VT == MVT::i64)
2359 LC = RTLIB::MULO_I64;
2360 else if (VT == MVT::i128)
2361 LC = RTLIB::MULO_I128;
2362 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported XMULO!");
2364 SDValue Temp = DAG.CreateStackTemporary(PtrVT);
2365 // Temporary for the overflow value, default it to zero.
2366 SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl,
2367 DAG.getConstant(0, PtrVT), Temp,
2368 MachinePointerInfo(), false, false, 0);
2370 TargetLowering::ArgListTy Args;
2371 TargetLowering::ArgListEntry Entry;
2372 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
2373 EVT ArgVT = N->getOperand(i).getValueType();
2374 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
2375 Entry.Node = N->getOperand(i);
2377 Entry.isSExt = true;
2378 Entry.isZExt = false;
2379 Args.push_back(Entry);
2382 // Also pass the address of the overflow check.
2384 Entry.Ty = PtrTy->getPointerTo();
2385 Entry.isSExt = true;
2386 Entry.isZExt = false;
2387 Args.push_back(Entry);
2389 SDValue Func = DAG.getExternalSymbol(TLI.getLibcallName(LC), PtrVT);
2391 TargetLowering::CallLoweringInfo CLI(DAG);
2392 CLI.setDebugLoc(dl).setChain(Chain)
2393 .setCallee(TLI.getLibcallCallingConv(LC), RetTy, Func, std::move(Args), 0)
2396 std::pair<SDValue, SDValue> CallInfo = TLI.LowerCallTo(CLI);
2398 SplitInteger(CallInfo.first, Lo, Hi);
2399 SDValue Temp2 = DAG.getLoad(PtrVT, dl, CallInfo.second, Temp,
2400 MachinePointerInfo(), false, false, false, 0);
2401 SDValue Ofl = DAG.getSetCC(dl, N->getValueType(1), Temp2,
2402 DAG.getConstant(0, PtrVT),
2404 // Use the overflow from the libcall everywhere.
2405 ReplaceValueWith(SDValue(N, 1), Ofl);
2408 void DAGTypeLegalizer::ExpandIntRes_UDIV(SDNode *N,
2409 SDValue &Lo, SDValue &Hi) {
2410 EVT VT = N->getValueType(0);
2413 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
2415 LC = RTLIB::UDIV_I16;
2416 else if (VT == MVT::i32)
2417 LC = RTLIB::UDIV_I32;
2418 else if (VT == MVT::i64)
2419 LC = RTLIB::UDIV_I64;
2420 else if (VT == MVT::i128)
2421 LC = RTLIB::UDIV_I128;
2422 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported UDIV!");
2424 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
2425 SplitInteger(TLI.makeLibCall(DAG, LC, VT, Ops, 2, false, dl).first, Lo, Hi);
2428 void DAGTypeLegalizer::ExpandIntRes_UREM(SDNode *N,
2429 SDValue &Lo, SDValue &Hi) {
2430 EVT VT = N->getValueType(0);
2433 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
2435 LC = RTLIB::UREM_I16;
2436 else if (VT == MVT::i32)
2437 LC = RTLIB::UREM_I32;
2438 else if (VT == MVT::i64)
2439 LC = RTLIB::UREM_I64;
2440 else if (VT == MVT::i128)
2441 LC = RTLIB::UREM_I128;
2442 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported UREM!");
2444 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
2445 SplitInteger(TLI.makeLibCall(DAG, LC, VT, Ops, 2, false, dl).first, Lo, Hi);
2448 void DAGTypeLegalizer::ExpandIntRes_ZERO_EXTEND(SDNode *N,
2449 SDValue &Lo, SDValue &Hi) {
2450 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2452 SDValue Op = N->getOperand(0);
2453 if (Op.getValueType().bitsLE(NVT)) {
2454 // The low part is zero extension of the input (degenerates to a copy).
2455 Lo = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, N->getOperand(0));
2456 Hi = DAG.getConstant(0, NVT); // The high part is just a zero.
2458 // For example, extension of an i48 to an i64. The operand type necessarily
2459 // promotes to the result type, so will end up being expanded too.
2460 assert(getTypeAction(Op.getValueType()) ==
2461 TargetLowering::TypePromoteInteger &&
2462 "Only know how to promote this result!");
2463 SDValue Res = GetPromotedInteger(Op);
2464 assert(Res.getValueType() == N->getValueType(0) &&
2465 "Operand over promoted?");
2466 // Split the promoted operand. This will simplify when it is expanded.
2467 SplitInteger(Res, Lo, Hi);
2468 unsigned ExcessBits =
2469 Op.getValueType().getSizeInBits() - NVT.getSizeInBits();
2470 Hi = DAG.getZeroExtendInReg(Hi, dl,
2471 EVT::getIntegerVT(*DAG.getContext(),
2476 void DAGTypeLegalizer::ExpandIntRes_ATOMIC_LOAD(SDNode *N,
2477 SDValue &Lo, SDValue &Hi) {
2479 EVT VT = cast<AtomicSDNode>(N)->getMemoryVT();
2480 SDVTList VTs = DAG.getVTList(VT, MVT::i1, MVT::Other);
2481 SDValue Zero = DAG.getConstant(0, VT);
2482 SDValue Swap = DAG.getAtomicCmpSwap(
2483 ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, dl,
2484 cast<AtomicSDNode>(N)->getMemoryVT(), VTs, N->getOperand(0),
2485 N->getOperand(1), Zero, Zero, cast<AtomicSDNode>(N)->getMemOperand(),
2486 cast<AtomicSDNode>(N)->getOrdering(),
2487 cast<AtomicSDNode>(N)->getOrdering(),
2488 cast<AtomicSDNode>(N)->getSynchScope());
2490 ReplaceValueWith(SDValue(N, 0), Swap.getValue(0));
2491 ReplaceValueWith(SDValue(N, 1), Swap.getValue(2));
2494 //===----------------------------------------------------------------------===//
2495 // Integer Operand Expansion
2496 //===----------------------------------------------------------------------===//
2498 /// ExpandIntegerOperand - This method is called when the specified operand of
2499 /// the specified node is found to need expansion. At this point, all of the
2500 /// result types of the node are known to be legal, but other operands of the
2501 /// node may need promotion or expansion as well as the specified one.
2502 bool DAGTypeLegalizer::ExpandIntegerOperand(SDNode *N, unsigned OpNo) {
2503 DEBUG(dbgs() << "Expand integer operand: "; N->dump(&DAG); dbgs() << "\n");
2504 SDValue Res = SDValue();
2506 if (CustomLowerNode(N, N->getOperand(OpNo).getValueType(), false))
2509 switch (N->getOpcode()) {
2512 dbgs() << "ExpandIntegerOperand Op #" << OpNo << ": ";
2513 N->dump(&DAG); dbgs() << "\n";
2515 llvm_unreachable("Do not know how to expand this operator's operand!");
2517 case ISD::BITCAST: Res = ExpandOp_BITCAST(N); break;
2518 case ISD::BR_CC: Res = ExpandIntOp_BR_CC(N); break;
2519 case ISD::BUILD_VECTOR: Res = ExpandOp_BUILD_VECTOR(N); break;
2520 case ISD::EXTRACT_ELEMENT: Res = ExpandOp_EXTRACT_ELEMENT(N); break;
2521 case ISD::INSERT_VECTOR_ELT: Res = ExpandOp_INSERT_VECTOR_ELT(N); break;
2522 case ISD::SCALAR_TO_VECTOR: Res = ExpandOp_SCALAR_TO_VECTOR(N); break;
2523 case ISD::SELECT_CC: Res = ExpandIntOp_SELECT_CC(N); break;
2524 case ISD::SETCC: Res = ExpandIntOp_SETCC(N); break;
2525 case ISD::SINT_TO_FP: Res = ExpandIntOp_SINT_TO_FP(N); break;
2526 case ISD::STORE: Res = ExpandIntOp_STORE(cast<StoreSDNode>(N), OpNo); break;
2527 case ISD::TRUNCATE: Res = ExpandIntOp_TRUNCATE(N); break;
2528 case ISD::UINT_TO_FP: Res = ExpandIntOp_UINT_TO_FP(N); break;
2534 case ISD::ROTR: Res = ExpandIntOp_Shift(N); break;
2535 case ISD::RETURNADDR:
2536 case ISD::FRAMEADDR: Res = ExpandIntOp_RETURNADDR(N); break;
2538 case ISD::ATOMIC_STORE: Res = ExpandIntOp_ATOMIC_STORE(N); break;
2541 // If the result is null, the sub-method took care of registering results etc.
2542 if (!Res.getNode()) return false;
2544 // If the result is N, the sub-method updated N in place. Tell the legalizer
2546 if (Res.getNode() == N)
2549 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 &&
2550 "Invalid operand expansion");
2552 ReplaceValueWith(SDValue(N, 0), Res);
2556 /// IntegerExpandSetCCOperands - Expand the operands of a comparison. This code
2557 /// is shared among BR_CC, SELECT_CC, and SETCC handlers.
2558 void DAGTypeLegalizer::IntegerExpandSetCCOperands(SDValue &NewLHS,
2560 ISD::CondCode &CCCode,
2562 SDValue LHSLo, LHSHi, RHSLo, RHSHi;
2563 GetExpandedInteger(NewLHS, LHSLo, LHSHi);
2564 GetExpandedInteger(NewRHS, RHSLo, RHSHi);
2566 if (CCCode == ISD::SETEQ || CCCode == ISD::SETNE) {
2567 if (RHSLo == RHSHi) {
2568 if (ConstantSDNode *RHSCST = dyn_cast<ConstantSDNode>(RHSLo)) {
2569 if (RHSCST->isAllOnesValue()) {
2570 // Equality comparison to -1.
2571 NewLHS = DAG.getNode(ISD::AND, dl,
2572 LHSLo.getValueType(), LHSLo, LHSHi);
2579 NewLHS = DAG.getNode(ISD::XOR, dl, LHSLo.getValueType(), LHSLo, RHSLo);
2580 NewRHS = DAG.getNode(ISD::XOR, dl, LHSLo.getValueType(), LHSHi, RHSHi);
2581 NewLHS = DAG.getNode(ISD::OR, dl, NewLHS.getValueType(), NewLHS, NewRHS);
2582 NewRHS = DAG.getConstant(0, NewLHS.getValueType());
2586 // If this is a comparison of the sign bit, just look at the top part.
2588 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(NewRHS))
2589 if ((CCCode == ISD::SETLT && CST->isNullValue()) || // X < 0
2590 (CCCode == ISD::SETGT && CST->isAllOnesValue())) { // X > -1
2596 // FIXME: This generated code sucks.
2597 ISD::CondCode LowCC;
2599 default: llvm_unreachable("Unknown integer setcc!");
2601 case ISD::SETULT: LowCC = ISD::SETULT; break;
2603 case ISD::SETUGT: LowCC = ISD::SETUGT; break;
2605 case ISD::SETULE: LowCC = ISD::SETULE; break;
2607 case ISD::SETUGE: LowCC = ISD::SETUGE; break;
2610 // Tmp1 = lo(op1) < lo(op2) // Always unsigned comparison
2611 // Tmp2 = hi(op1) < hi(op2) // Signedness depends on operands
2612 // dest = hi(op1) == hi(op2) ? Tmp1 : Tmp2;
2614 // NOTE: on targets without efficient SELECT of bools, we can always use
2615 // this identity: (B1 ? B2 : B3) --> (B1 & B2)|(!B1&B3)
2616 TargetLowering::DAGCombinerInfo DagCombineInfo(DAG, AfterLegalizeTypes, true,
2619 if (TLI.isTypeLegal(LHSLo.getValueType()) &&
2620 TLI.isTypeLegal(RHSLo.getValueType()))
2621 Tmp1 = TLI.SimplifySetCC(getSetCCResultType(LHSLo.getValueType()),
2622 LHSLo, RHSLo, LowCC, false, DagCombineInfo, dl);
2623 if (!Tmp1.getNode())
2624 Tmp1 = DAG.getSetCC(dl, getSetCCResultType(LHSLo.getValueType()),
2625 LHSLo, RHSLo, LowCC);
2626 if (TLI.isTypeLegal(LHSHi.getValueType()) &&
2627 TLI.isTypeLegal(RHSHi.getValueType()))
2628 Tmp2 = TLI.SimplifySetCC(getSetCCResultType(LHSHi.getValueType()),
2629 LHSHi, RHSHi, CCCode, false, DagCombineInfo, dl);
2630 if (!Tmp2.getNode())
2631 Tmp2 = DAG.getNode(ISD::SETCC, dl,
2632 getSetCCResultType(LHSHi.getValueType()),
2633 LHSHi, RHSHi, DAG.getCondCode(CCCode));
2635 ConstantSDNode *Tmp1C = dyn_cast<ConstantSDNode>(Tmp1.getNode());
2636 ConstantSDNode *Tmp2C = dyn_cast<ConstantSDNode>(Tmp2.getNode());
2637 if ((Tmp1C && Tmp1C->isNullValue()) ||
2638 (Tmp2C && Tmp2C->isNullValue() &&
2639 (CCCode == ISD::SETLE || CCCode == ISD::SETGE ||
2640 CCCode == ISD::SETUGE || CCCode == ISD::SETULE)) ||
2641 (Tmp2C && Tmp2C->getAPIntValue() == 1 &&
2642 (CCCode == ISD::SETLT || CCCode == ISD::SETGT ||
2643 CCCode == ISD::SETUGT || CCCode == ISD::SETULT))) {
2644 // low part is known false, returns high part.
2645 // For LE / GE, if high part is known false, ignore the low part.
2646 // For LT / GT, if high part is known true, ignore the low part.
2652 NewLHS = TLI.SimplifySetCC(getSetCCResultType(LHSHi.getValueType()),
2653 LHSHi, RHSHi, ISD::SETEQ, false,
2654 DagCombineInfo, dl);
2655 if (!NewLHS.getNode())
2656 NewLHS = DAG.getSetCC(dl, getSetCCResultType(LHSHi.getValueType()),
2657 LHSHi, RHSHi, ISD::SETEQ);
2658 NewLHS = DAG.getSelect(dl, Tmp1.getValueType(),
2659 NewLHS, Tmp1, Tmp2);
2663 SDValue DAGTypeLegalizer::ExpandIntOp_BR_CC(SDNode *N) {
2664 SDValue NewLHS = N->getOperand(2), NewRHS = N->getOperand(3);
2665 ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(1))->get();
2666 IntegerExpandSetCCOperands(NewLHS, NewRHS, CCCode, SDLoc(N));
2668 // If ExpandSetCCOperands returned a scalar, we need to compare the result
2669 // against zero to select between true and false values.
2670 if (!NewRHS.getNode()) {
2671 NewRHS = DAG.getConstant(0, NewLHS.getValueType());
2672 CCCode = ISD::SETNE;
2675 // Update N to have the operands specified.
2676 return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0),
2677 DAG.getCondCode(CCCode), NewLHS, NewRHS,
2678 N->getOperand(4)), 0);
2681 SDValue DAGTypeLegalizer::ExpandIntOp_SELECT_CC(SDNode *N) {
2682 SDValue NewLHS = N->getOperand(0), NewRHS = N->getOperand(1);
2683 ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(4))->get();
2684 IntegerExpandSetCCOperands(NewLHS, NewRHS, CCCode, SDLoc(N));
2686 // If ExpandSetCCOperands returned a scalar, we need to compare the result
2687 // against zero to select between true and false values.
2688 if (!NewRHS.getNode()) {
2689 NewRHS = DAG.getConstant(0, NewLHS.getValueType());
2690 CCCode = ISD::SETNE;
2693 // Update N to have the operands specified.
2694 return SDValue(DAG.UpdateNodeOperands(N, NewLHS, NewRHS,
2695 N->getOperand(2), N->getOperand(3),
2696 DAG.getCondCode(CCCode)), 0);
2699 SDValue DAGTypeLegalizer::ExpandIntOp_SETCC(SDNode *N) {
2700 SDValue NewLHS = N->getOperand(0), NewRHS = N->getOperand(1);
2701 ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(2))->get();
2702 IntegerExpandSetCCOperands(NewLHS, NewRHS, CCCode, SDLoc(N));
2704 // If ExpandSetCCOperands returned a scalar, use it.
2705 if (!NewRHS.getNode()) {
2706 assert(NewLHS.getValueType() == N->getValueType(0) &&
2707 "Unexpected setcc expansion!");
2711 // Otherwise, update N to have the operands specified.
2712 return SDValue(DAG.UpdateNodeOperands(N, NewLHS, NewRHS,
2713 DAG.getCondCode(CCCode)), 0);
2716 SDValue DAGTypeLegalizer::ExpandIntOp_Shift(SDNode *N) {
2717 // The value being shifted is legal, but the shift amount is too big.
2718 // It follows that either the result of the shift is undefined, or the
2719 // upper half of the shift amount is zero. Just use the lower half.
2721 GetExpandedInteger(N->getOperand(1), Lo, Hi);
2722 return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0), Lo), 0);
2725 SDValue DAGTypeLegalizer::ExpandIntOp_RETURNADDR(SDNode *N) {
2726 // The argument of RETURNADDR / FRAMEADDR builtin is 32 bit contant. This
2727 // surely makes pretty nice problems on 8/16 bit targets. Just truncate this
2728 // constant to valid type.
2730 GetExpandedInteger(N->getOperand(0), Lo, Hi);
2731 return SDValue(DAG.UpdateNodeOperands(N, Lo), 0);
2734 SDValue DAGTypeLegalizer::ExpandIntOp_SINT_TO_FP(SDNode *N) {
2735 SDValue Op = N->getOperand(0);
2736 EVT DstVT = N->getValueType(0);
2737 RTLIB::Libcall LC = RTLIB::getSINTTOFP(Op.getValueType(), DstVT);
2738 assert(LC != RTLIB::UNKNOWN_LIBCALL &&
2739 "Don't know how to expand this SINT_TO_FP!");
2740 return TLI.makeLibCall(DAG, LC, DstVT, &Op, 1, true, SDLoc(N)).first;
2743 SDValue DAGTypeLegalizer::ExpandIntOp_STORE(StoreSDNode *N, unsigned OpNo) {
2744 if (ISD::isNormalStore(N))
2745 return ExpandOp_NormalStore(N, OpNo);
2747 assert(ISD::isUNINDEXEDStore(N) && "Indexed store during type legalization!");
2748 assert(OpNo == 1 && "Can only expand the stored value so far");
2750 EVT VT = N->getOperand(1).getValueType();
2751 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
2752 SDValue Ch = N->getChain();
2753 SDValue Ptr = N->getBasePtr();
2754 unsigned Alignment = N->getAlignment();
2755 bool isVolatile = N->isVolatile();
2756 bool isNonTemporal = N->isNonTemporal();
2757 AAMDNodes AAInfo = N->getAAInfo();
2761 assert(NVT.isByteSized() && "Expanded type not byte sized!");
2763 if (N->getMemoryVT().bitsLE(NVT)) {
2764 GetExpandedInteger(N->getValue(), Lo, Hi);
2765 return DAG.getTruncStore(Ch, dl, Lo, Ptr, N->getPointerInfo(),
2766 N->getMemoryVT(), isVolatile, isNonTemporal,
2770 if (TLI.isLittleEndian()) {
2771 // Little-endian - low bits are at low addresses.
2772 GetExpandedInteger(N->getValue(), Lo, Hi);
2774 Lo = DAG.getStore(Ch, dl, Lo, Ptr, N->getPointerInfo(),
2775 isVolatile, isNonTemporal, Alignment, AAInfo);
2777 unsigned ExcessBits =
2778 N->getMemoryVT().getSizeInBits() - NVT.getSizeInBits();
2779 EVT NEVT = EVT::getIntegerVT(*DAG.getContext(), ExcessBits);
2781 // Increment the pointer to the other half.
2782 unsigned IncrementSize = NVT.getSizeInBits()/8;
2783 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
2784 DAG.getConstant(IncrementSize, Ptr.getValueType()));
2785 Hi = DAG.getTruncStore(Ch, dl, Hi, Ptr,
2786 N->getPointerInfo().getWithOffset(IncrementSize),
2787 NEVT, isVolatile, isNonTemporal,
2788 MinAlign(Alignment, IncrementSize), AAInfo);
2789 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi);
2792 // Big-endian - high bits are at low addresses. Favor aligned stores at
2793 // the cost of some bit-fiddling.
2794 GetExpandedInteger(N->getValue(), Lo, Hi);
2796 EVT ExtVT = N->getMemoryVT();
2797 unsigned EBytes = ExtVT.getStoreSize();
2798 unsigned IncrementSize = NVT.getSizeInBits()/8;
2799 unsigned ExcessBits = (EBytes - IncrementSize)*8;
2800 EVT HiVT = EVT::getIntegerVT(*DAG.getContext(),
2801 ExtVT.getSizeInBits() - ExcessBits);
2803 if (ExcessBits < NVT.getSizeInBits()) {
2804 // Transfer high bits from the top of Lo to the bottom of Hi.
2805 Hi = DAG.getNode(ISD::SHL, dl, NVT, Hi,
2806 DAG.getConstant(NVT.getSizeInBits() - ExcessBits,
2807 TLI.getPointerTy()));
2808 Hi = DAG.getNode(ISD::OR, dl, NVT, Hi,
2809 DAG.getNode(ISD::SRL, dl, NVT, Lo,
2810 DAG.getConstant(ExcessBits,
2811 TLI.getPointerTy())));
2814 // Store both the high bits and maybe some of the low bits.
2815 Hi = DAG.getTruncStore(Ch, dl, Hi, Ptr, N->getPointerInfo(),
2816 HiVT, isVolatile, isNonTemporal, Alignment, AAInfo);
2818 // Increment the pointer to the other half.
2819 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
2820 DAG.getConstant(IncrementSize, Ptr.getValueType()));
2821 // Store the lowest ExcessBits bits in the second half.
2822 Lo = DAG.getTruncStore(Ch, dl, Lo, Ptr,
2823 N->getPointerInfo().getWithOffset(IncrementSize),
2824 EVT::getIntegerVT(*DAG.getContext(), ExcessBits),
2825 isVolatile, isNonTemporal,
2826 MinAlign(Alignment, IncrementSize), AAInfo);
2827 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi);
2830 SDValue DAGTypeLegalizer::ExpandIntOp_TRUNCATE(SDNode *N) {
2832 GetExpandedInteger(N->getOperand(0), InL, InH);
2833 // Just truncate the low part of the source.
2834 return DAG.getNode(ISD::TRUNCATE, SDLoc(N), N->getValueType(0), InL);
2837 SDValue DAGTypeLegalizer::ExpandIntOp_UINT_TO_FP(SDNode *N) {
2838 SDValue Op = N->getOperand(0);
2839 EVT SrcVT = Op.getValueType();
2840 EVT DstVT = N->getValueType(0);
2843 // The following optimization is valid only if every value in SrcVT (when
2844 // treated as signed) is representable in DstVT. Check that the mantissa
2845 // size of DstVT is >= than the number of bits in SrcVT -1.
2846 const fltSemantics &sem = DAG.EVTToAPFloatSemantics(DstVT);
2847 if (APFloat::semanticsPrecision(sem) >= SrcVT.getSizeInBits()-1 &&
2848 TLI.getOperationAction(ISD::SINT_TO_FP, SrcVT) == TargetLowering::Custom){
2849 // Do a signed conversion then adjust the result.
2850 SDValue SignedConv = DAG.getNode(ISD::SINT_TO_FP, dl, DstVT, Op);
2851 SignedConv = TLI.LowerOperation(SignedConv, DAG);
2853 // The result of the signed conversion needs adjusting if the 'sign bit' of
2854 // the incoming integer was set. To handle this, we dynamically test to see
2855 // if it is set, and, if so, add a fudge factor.
2857 const uint64_t F32TwoE32 = 0x4F800000ULL;
2858 const uint64_t F32TwoE64 = 0x5F800000ULL;
2859 const uint64_t F32TwoE128 = 0x7F800000ULL;
2862 if (SrcVT == MVT::i32)
2863 FF = APInt(32, F32TwoE32);
2864 else if (SrcVT == MVT::i64)
2865 FF = APInt(32, F32TwoE64);
2866 else if (SrcVT == MVT::i128)
2867 FF = APInt(32, F32TwoE128);
2869 llvm_unreachable("Unsupported UINT_TO_FP!");
2871 // Check whether the sign bit is set.
2873 GetExpandedInteger(Op, Lo, Hi);
2874 SDValue SignSet = DAG.getSetCC(dl,
2875 getSetCCResultType(Hi.getValueType()),
2876 Hi, DAG.getConstant(0, Hi.getValueType()),
2879 // Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits.
2880 SDValue FudgePtr = DAG.getConstantPool(
2881 ConstantInt::get(*DAG.getContext(), FF.zext(64)),
2882 TLI.getPointerTy());
2884 // Get a pointer to FF if the sign bit was set, or to 0 otherwise.
2885 SDValue Zero = DAG.getIntPtrConstant(0);
2886 SDValue Four = DAG.getIntPtrConstant(4);
2887 if (TLI.isBigEndian()) std::swap(Zero, Four);
2888 SDValue Offset = DAG.getSelect(dl, Zero.getValueType(), SignSet,
2890 unsigned Alignment = cast<ConstantPoolSDNode>(FudgePtr)->getAlignment();
2891 FudgePtr = DAG.getNode(ISD::ADD, dl, FudgePtr.getValueType(),
2893 Alignment = std::min(Alignment, 4u);
2895 // Load the value out, extending it from f32 to the destination float type.
2896 // FIXME: Avoid the extend by constructing the right constant pool?
2897 SDValue Fudge = DAG.getExtLoad(ISD::EXTLOAD, dl, DstVT, DAG.getEntryNode(),
2899 MachinePointerInfo::getConstantPool(),
2901 false, false, false, Alignment);
2902 return DAG.getNode(ISD::FADD, dl, DstVT, SignedConv, Fudge);
2905 // Otherwise, use a libcall.
2906 RTLIB::Libcall LC = RTLIB::getUINTTOFP(SrcVT, DstVT);
2907 assert(LC != RTLIB::UNKNOWN_LIBCALL &&
2908 "Don't know how to expand this UINT_TO_FP!");
2909 return TLI.makeLibCall(DAG, LC, DstVT, &Op, 1, true, dl).first;
2912 SDValue DAGTypeLegalizer::ExpandIntOp_ATOMIC_STORE(SDNode *N) {
2914 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_SWAP, dl,
2915 cast<AtomicSDNode>(N)->getMemoryVT(),
2917 N->getOperand(1), N->getOperand(2),
2918 cast<AtomicSDNode>(N)->getMemOperand(),
2919 cast<AtomicSDNode>(N)->getOrdering(),
2920 cast<AtomicSDNode>(N)->getSynchScope());
2921 return Swap.getValue(1);
2925 SDValue DAGTypeLegalizer::PromoteIntRes_EXTRACT_SUBVECTOR(SDNode *N) {
2926 SDValue InOp0 = N->getOperand(0);
2927 EVT InVT = InOp0.getValueType();
2929 EVT OutVT = N->getValueType(0);
2930 EVT NOutVT = TLI.getTypeToTransformTo(*DAG.getContext(), OutVT);
2931 assert(NOutVT.isVector() && "This type must be promoted to a vector type");
2932 unsigned OutNumElems = OutVT.getVectorNumElements();
2933 EVT NOutVTElem = NOutVT.getVectorElementType();
2936 SDValue BaseIdx = N->getOperand(1);
2938 SmallVector<SDValue, 8> Ops;
2939 Ops.reserve(OutNumElems);
2940 for (unsigned i = 0; i != OutNumElems; ++i) {
2942 // Extract the element from the original vector.
2943 SDValue Index = DAG.getNode(ISD::ADD, dl, BaseIdx.getValueType(),
2944 BaseIdx, DAG.getConstant(i, BaseIdx.getValueType()));
2945 SDValue Ext = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
2946 InVT.getVectorElementType(), N->getOperand(0), Index);
2948 SDValue Op = DAG.getNode(ISD::ANY_EXTEND, dl, NOutVTElem, Ext);
2949 // Insert the converted element to the new vector.
2953 return DAG.getNode(ISD::BUILD_VECTOR, dl, NOutVT, Ops);
2957 SDValue DAGTypeLegalizer::PromoteIntRes_VECTOR_SHUFFLE(SDNode *N) {
2958 ShuffleVectorSDNode *SV = cast<ShuffleVectorSDNode>(N);
2959 EVT VT = N->getValueType(0);
2962 unsigned NumElts = VT.getVectorNumElements();
2963 SmallVector<int, 8> NewMask;
2964 for (unsigned i = 0; i != NumElts; ++i) {
2965 NewMask.push_back(SV->getMaskElt(i));
2968 SDValue V0 = GetPromotedInteger(N->getOperand(0));
2969 SDValue V1 = GetPromotedInteger(N->getOperand(1));
2970 EVT OutVT = V0.getValueType();
2972 return DAG.getVectorShuffle(OutVT, dl, V0, V1, &NewMask[0]);
2976 SDValue DAGTypeLegalizer::PromoteIntRes_BUILD_VECTOR(SDNode *N) {
2977 EVT OutVT = N->getValueType(0);
2978 EVT NOutVT = TLI.getTypeToTransformTo(*DAG.getContext(), OutVT);
2979 assert(NOutVT.isVector() && "This type must be promoted to a vector type");
2980 unsigned NumElems = N->getNumOperands();
2981 EVT NOutVTElem = NOutVT.getVectorElementType();
2985 SmallVector<SDValue, 8> Ops;
2986 Ops.reserve(NumElems);
2987 for (unsigned i = 0; i != NumElems; ++i) {
2989 // BUILD_VECTOR integer operand types are allowed to be larger than the
2990 // result's element type. This may still be true after the promotion. For
2991 // example, we might be promoting (<v?i1> = BV <i32>, <i32>, ...) to
2992 // (v?i16 = BV <i32>, <i32>, ...), and we can't any_extend <i32> to <i16>.
2993 if (N->getOperand(i).getValueType().bitsLT(NOutVTElem))
2994 Op = DAG.getNode(ISD::ANY_EXTEND, dl, NOutVTElem, N->getOperand(i));
2996 Op = N->getOperand(i);
3000 return DAG.getNode(ISD::BUILD_VECTOR, dl, NOutVT, Ops);
3003 SDValue DAGTypeLegalizer::PromoteIntRes_SCALAR_TO_VECTOR(SDNode *N) {
3007 assert(!N->getOperand(0).getValueType().isVector() &&
3008 "Input must be a scalar");
3010 EVT OutVT = N->getValueType(0);
3011 EVT NOutVT = TLI.getTypeToTransformTo(*DAG.getContext(), OutVT);
3012 assert(NOutVT.isVector() && "This type must be promoted to a vector type");
3013 EVT NOutVTElem = NOutVT.getVectorElementType();
3015 SDValue Op = DAG.getNode(ISD::ANY_EXTEND, dl, NOutVTElem, N->getOperand(0));
3017 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, NOutVT, Op);
3020 SDValue DAGTypeLegalizer::PromoteIntRes_CONCAT_VECTORS(SDNode *N) {
3023 EVT OutVT = N->getValueType(0);
3024 EVT NOutVT = TLI.getTypeToTransformTo(*DAG.getContext(), OutVT);
3025 assert(NOutVT.isVector() && "This type must be promoted to a vector type");
3027 EVT InElemTy = OutVT.getVectorElementType();
3028 EVT OutElemTy = NOutVT.getVectorElementType();
3030 unsigned NumElem = N->getOperand(0).getValueType().getVectorNumElements();
3031 unsigned NumOutElem = NOutVT.getVectorNumElements();
3032 unsigned NumOperands = N->getNumOperands();
3033 assert(NumElem * NumOperands == NumOutElem &&
3034 "Unexpected number of elements");
3036 // Take the elements from the first vector.
3037 SmallVector<SDValue, 8> Ops(NumOutElem);
3038 for (unsigned i = 0; i < NumOperands; ++i) {
3039 SDValue Op = N->getOperand(i);
3040 for (unsigned j = 0; j < NumElem; ++j) {
3041 SDValue Ext = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
3042 InElemTy, Op, DAG.getConstant(j,
3043 TLI.getVectorIdxTy()));
3044 Ops[i * NumElem + j] = DAG.getNode(ISD::ANY_EXTEND, dl, OutElemTy, Ext);
3048 return DAG.getNode(ISD::BUILD_VECTOR, dl, NOutVT, Ops);
3051 SDValue DAGTypeLegalizer::PromoteIntRes_INSERT_VECTOR_ELT(SDNode *N) {
3052 EVT OutVT = N->getValueType(0);
3053 EVT NOutVT = TLI.getTypeToTransformTo(*DAG.getContext(), OutVT);
3054 assert(NOutVT.isVector() && "This type must be promoted to a vector type");
3056 EVT NOutVTElem = NOutVT.getVectorElementType();
3059 SDValue V0 = GetPromotedInteger(N->getOperand(0));
3061 SDValue ConvElem = DAG.getNode(ISD::ANY_EXTEND, dl,
3062 NOutVTElem, N->getOperand(1));
3063 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, NOutVT,
3064 V0, ConvElem, N->getOperand(2));
3067 SDValue DAGTypeLegalizer::PromoteIntOp_EXTRACT_VECTOR_ELT(SDNode *N) {
3069 SDValue V0 = GetPromotedInteger(N->getOperand(0));
3070 SDValue V1 = DAG.getZExtOrTrunc(N->getOperand(1), dl, TLI.getVectorIdxTy());
3071 SDValue Ext = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
3072 V0->getValueType(0).getScalarType(), V0, V1);
3074 // EXTRACT_VECTOR_ELT can return types which are wider than the incoming
3075 // element types. If this is the case then we need to expand the outgoing
3076 // value and not truncate it.
3077 return DAG.getAnyExtOrTrunc(Ext, dl, N->getValueType(0));
3080 SDValue DAGTypeLegalizer::PromoteIntOp_CONCAT_VECTORS(SDNode *N) {
3082 unsigned NumElems = N->getNumOperands();
3084 EVT RetSclrTy = N->getValueType(0).getVectorElementType();
3086 SmallVector<SDValue, 8> NewOps;
3087 NewOps.reserve(NumElems);
3089 // For each incoming vector
3090 for (unsigned VecIdx = 0; VecIdx != NumElems; ++VecIdx) {
3091 SDValue Incoming = GetPromotedInteger(N->getOperand(VecIdx));
3092 EVT SclrTy = Incoming->getValueType(0).getVectorElementType();
3093 unsigned NumElem = Incoming->getValueType(0).getVectorNumElements();
3095 for (unsigned i=0; i<NumElem; ++i) {
3096 // Extract element from incoming vector
3097 SDValue Ex = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SclrTy,
3098 Incoming, DAG.getConstant(i, TLI.getVectorIdxTy()));
3099 SDValue Tr = DAG.getNode(ISD::TRUNCATE, dl, RetSclrTy, Ex);
3100 NewOps.push_back(Tr);
3104 return DAG.getNode(ISD::BUILD_VECTOR, dl, N->getValueType(0), NewOps);