1 //===----- LegalizeIntegerTypes.cpp - Legalization of integer types -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements integer type expansion and promotion for LegalizeTypes.
11 // Promotion is the act of changing a computation in an illegal type into a
12 // computation in a larger type. For example, implementing i8 arithmetic in an
13 // i32 register (often needed on powerpc).
14 // Expansion is the act of changing a computation in an illegal type into a
15 // computation in two identical registers of a smaller type. For example,
16 // implementing i64 arithmetic in two i32 registers (often needed on 32-bit
19 //===----------------------------------------------------------------------===//
21 #include "LegalizeTypes.h"
22 #include "llvm/IR/DerivedTypes.h"
23 #include "llvm/Support/ErrorHandling.h"
24 #include "llvm/Support/raw_ostream.h"
27 #define DEBUG_TYPE "legalize-types"
29 //===----------------------------------------------------------------------===//
30 // Integer Result Promotion
31 //===----------------------------------------------------------------------===//
33 /// PromoteIntegerResult - This method is called when a result of a node is
34 /// found to be in need of promotion to a larger type. At this point, the node
35 /// may also have invalid operands or may have other results that need
36 /// expansion, we just know that (at least) one result needs promotion.
37 void DAGTypeLegalizer::PromoteIntegerResult(SDNode *N, unsigned ResNo) {
38 DEBUG(dbgs() << "Promote integer result: "; N->dump(&DAG); dbgs() << "\n");
39 SDValue Res = SDValue();
41 // See if the target wants to custom expand this node.
42 if (CustomLowerNode(N, N->getValueType(ResNo), true))
45 switch (N->getOpcode()) {
48 dbgs() << "PromoteIntegerResult #" << ResNo << ": ";
49 N->dump(&DAG); dbgs() << "\n";
51 llvm_unreachable("Do not know how to promote this operator!");
52 case ISD::MERGE_VALUES:Res = PromoteIntRes_MERGE_VALUES(N, ResNo); break;
53 case ISD::AssertSext: Res = PromoteIntRes_AssertSext(N); break;
54 case ISD::AssertZext: Res = PromoteIntRes_AssertZext(N); break;
55 case ISD::BITCAST: Res = PromoteIntRes_BITCAST(N); break;
56 case ISD::BSWAP: Res = PromoteIntRes_BSWAP(N); break;
57 case ISD::BUILD_PAIR: Res = PromoteIntRes_BUILD_PAIR(N); break;
58 case ISD::Constant: Res = PromoteIntRes_Constant(N); break;
59 case ISD::CONVERT_RNDSAT:
60 Res = PromoteIntRes_CONVERT_RNDSAT(N); break;
61 case ISD::CTLZ_ZERO_UNDEF:
62 case ISD::CTLZ: Res = PromoteIntRes_CTLZ(N); break;
63 case ISD::CTPOP: Res = PromoteIntRes_CTPOP(N); break;
64 case ISD::CTTZ_ZERO_UNDEF:
65 case ISD::CTTZ: Res = PromoteIntRes_CTTZ(N); break;
66 case ISD::EXTRACT_VECTOR_ELT:
67 Res = PromoteIntRes_EXTRACT_VECTOR_ELT(N); break;
68 case ISD::LOAD: Res = PromoteIntRes_LOAD(cast<LoadSDNode>(N));break;
69 case ISD::MLOAD: Res = PromoteIntRes_MLOAD(cast<MaskedLoadSDNode>(N));break;
70 case ISD::SELECT: Res = PromoteIntRes_SELECT(N); break;
71 case ISD::VSELECT: Res = PromoteIntRes_VSELECT(N); break;
72 case ISD::SELECT_CC: Res = PromoteIntRes_SELECT_CC(N); break;
73 case ISD::SETCC: Res = PromoteIntRes_SETCC(N); break;
77 case ISD::UMAX: Res = PromoteIntRes_SimpleIntBinOp(N); break;
78 case ISD::SHL: Res = PromoteIntRes_SHL(N); break;
79 case ISD::SIGN_EXTEND_INREG:
80 Res = PromoteIntRes_SIGN_EXTEND_INREG(N); break;
81 case ISD::SRA: Res = PromoteIntRes_SRA(N); break;
82 case ISD::SRL: Res = PromoteIntRes_SRL(N); break;
83 case ISD::TRUNCATE: Res = PromoteIntRes_TRUNCATE(N); break;
84 case ISD::UNDEF: Res = PromoteIntRes_UNDEF(N); break;
85 case ISD::VAARG: Res = PromoteIntRes_VAARG(N); break;
87 case ISD::EXTRACT_SUBVECTOR:
88 Res = PromoteIntRes_EXTRACT_SUBVECTOR(N); break;
89 case ISD::VECTOR_SHUFFLE:
90 Res = PromoteIntRes_VECTOR_SHUFFLE(N); break;
91 case ISD::INSERT_VECTOR_ELT:
92 Res = PromoteIntRes_INSERT_VECTOR_ELT(N); break;
93 case ISD::BUILD_VECTOR:
94 Res = PromoteIntRes_BUILD_VECTOR(N); break;
95 case ISD::SCALAR_TO_VECTOR:
96 Res = PromoteIntRes_SCALAR_TO_VECTOR(N); break;
97 case ISD::CONCAT_VECTORS:
98 Res = PromoteIntRes_CONCAT_VECTORS(N); break;
100 case ISD::SIGN_EXTEND:
101 case ISD::ZERO_EXTEND:
102 case ISD::ANY_EXTEND: Res = PromoteIntRes_INT_EXTEND(N); break;
104 case ISD::FP_TO_SINT:
105 case ISD::FP_TO_UINT: Res = PromoteIntRes_FP_TO_XINT(N); break;
107 case ISD::FP_TO_FP16: Res = PromoteIntRes_FP_TO_FP16(N); break;
114 case ISD::MUL: Res = PromoteIntRes_SimpleIntBinOp(N); break;
117 case ISD::SREM: Res = PromoteIntRes_SDIV(N); break;
120 case ISD::UREM: Res = PromoteIntRes_UDIV(N); break;
123 case ISD::SSUBO: Res = PromoteIntRes_SADDSUBO(N, ResNo); break;
125 case ISD::USUBO: Res = PromoteIntRes_UADDSUBO(N, ResNo); break;
127 case ISD::UMULO: Res = PromoteIntRes_XMULO(N, ResNo); break;
129 case ISD::ATOMIC_LOAD:
130 Res = PromoteIntRes_Atomic0(cast<AtomicSDNode>(N)); break;
132 case ISD::ATOMIC_LOAD_ADD:
133 case ISD::ATOMIC_LOAD_SUB:
134 case ISD::ATOMIC_LOAD_AND:
135 case ISD::ATOMIC_LOAD_OR:
136 case ISD::ATOMIC_LOAD_XOR:
137 case ISD::ATOMIC_LOAD_NAND:
138 case ISD::ATOMIC_LOAD_MIN:
139 case ISD::ATOMIC_LOAD_MAX:
140 case ISD::ATOMIC_LOAD_UMIN:
141 case ISD::ATOMIC_LOAD_UMAX:
142 case ISD::ATOMIC_SWAP:
143 Res = PromoteIntRes_Atomic1(cast<AtomicSDNode>(N)); break;
145 case ISD::ATOMIC_CMP_SWAP:
146 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS:
147 Res = PromoteIntRes_AtomicCmpSwap(cast<AtomicSDNode>(N), ResNo);
151 Res = PromoteIntRes_SimpleIntBinOp(N);
155 // If the result is null then the sub-method took care of registering it.
157 SetPromotedInteger(SDValue(N, ResNo), Res);
160 SDValue DAGTypeLegalizer::PromoteIntRes_MERGE_VALUES(SDNode *N,
162 SDValue Op = DisintegrateMERGE_VALUES(N, ResNo);
163 return GetPromotedInteger(Op);
166 SDValue DAGTypeLegalizer::PromoteIntRes_AssertSext(SDNode *N) {
167 // Sign-extend the new bits, and continue the assertion.
168 SDValue Op = SExtPromotedInteger(N->getOperand(0));
169 return DAG.getNode(ISD::AssertSext, SDLoc(N),
170 Op.getValueType(), Op, N->getOperand(1));
173 SDValue DAGTypeLegalizer::PromoteIntRes_AssertZext(SDNode *N) {
174 // Zero the new bits, and continue the assertion.
175 SDValue Op = ZExtPromotedInteger(N->getOperand(0));
176 return DAG.getNode(ISD::AssertZext, SDLoc(N),
177 Op.getValueType(), Op, N->getOperand(1));
180 SDValue DAGTypeLegalizer::PromoteIntRes_Atomic0(AtomicSDNode *N) {
181 EVT ResVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
182 SDValue Res = DAG.getAtomic(N->getOpcode(), SDLoc(N),
183 N->getMemoryVT(), ResVT,
184 N->getChain(), N->getBasePtr(),
185 N->getMemOperand(), N->getOrdering(),
187 // Legalized the chain result - switch anything that used the old chain to
189 ReplaceValueWith(SDValue(N, 1), Res.getValue(1));
193 SDValue DAGTypeLegalizer::PromoteIntRes_Atomic1(AtomicSDNode *N) {
194 SDValue Op2 = GetPromotedInteger(N->getOperand(2));
195 SDValue Res = DAG.getAtomic(N->getOpcode(), SDLoc(N),
197 N->getChain(), N->getBasePtr(),
198 Op2, N->getMemOperand(), N->getOrdering(),
200 // Legalized the chain result - switch anything that used the old chain to
202 ReplaceValueWith(SDValue(N, 1), Res.getValue(1));
206 SDValue DAGTypeLegalizer::PromoteIntRes_AtomicCmpSwap(AtomicSDNode *N,
209 assert(N->getOpcode() == ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS);
210 EVT SVT = getSetCCResultType(N->getOperand(2).getValueType());
211 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(1));
213 // Only use the result of getSetCCResultType if it is legal,
214 // otherwise just use the promoted result type (NVT).
215 if (!TLI.isTypeLegal(SVT))
218 SDVTList VTs = DAG.getVTList(N->getValueType(0), SVT, MVT::Other);
219 SDValue Res = DAG.getAtomicCmpSwap(
220 ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, SDLoc(N), N->getMemoryVT(), VTs,
221 N->getChain(), N->getBasePtr(), N->getOperand(2), N->getOperand(3),
222 N->getMemOperand(), N->getSuccessOrdering(), N->getFailureOrdering(),
224 ReplaceValueWith(SDValue(N, 0), Res.getValue(0));
225 ReplaceValueWith(SDValue(N, 2), Res.getValue(2));
226 return Res.getValue(1);
229 SDValue Op2 = GetPromotedInteger(N->getOperand(2));
230 SDValue Op3 = GetPromotedInteger(N->getOperand(3));
232 DAG.getVTList(Op2.getValueType(), N->getValueType(1), MVT::Other);
233 SDValue Res = DAG.getAtomicCmpSwap(
234 N->getOpcode(), SDLoc(N), N->getMemoryVT(), VTs, N->getChain(),
235 N->getBasePtr(), Op2, Op3, N->getMemOperand(), N->getSuccessOrdering(),
236 N->getFailureOrdering(), N->getSynchScope());
237 // Update the use to N with the newly created Res.
238 for (unsigned i = 1, NumResults = N->getNumValues(); i < NumResults; ++i)
239 ReplaceValueWith(SDValue(N, i), Res.getValue(i));
243 SDValue DAGTypeLegalizer::PromoteIntRes_BITCAST(SDNode *N) {
244 SDValue InOp = N->getOperand(0);
245 EVT InVT = InOp.getValueType();
246 EVT NInVT = TLI.getTypeToTransformTo(*DAG.getContext(), InVT);
247 EVT OutVT = N->getValueType(0);
248 EVT NOutVT = TLI.getTypeToTransformTo(*DAG.getContext(), OutVT);
251 switch (getTypeAction(InVT)) {
252 case TargetLowering::TypeLegal:
254 case TargetLowering::TypePromoteInteger:
255 if (NOutVT.bitsEq(NInVT) && !NOutVT.isVector() && !NInVT.isVector())
256 // The input promotes to the same size. Convert the promoted value.
257 return DAG.getNode(ISD::BITCAST, dl, NOutVT, GetPromotedInteger(InOp));
259 case TargetLowering::TypeSoftenFloat:
260 // Promote the integer operand by hand.
261 return DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT, GetSoftenedFloat(InOp));
262 case TargetLowering::TypePromoteFloat: {
263 // Convert the promoted float by hand.
264 if (NOutVT.bitsEq(NInVT)) {
265 SDValue PromotedOp = GetPromotedFloat(InOp);
266 SDValue Trunc = DAG.getNode(ISD::FP_TO_FP16, dl, NOutVT, PromotedOp);
267 return DAG.getNode(ISD::AssertZext, dl, NOutVT, Trunc,
268 DAG.getValueType(OutVT));
272 case TargetLowering::TypeExpandInteger:
273 case TargetLowering::TypeExpandFloat:
275 case TargetLowering::TypeScalarizeVector:
276 // Convert the element to an integer and promote it by hand.
277 if (!NOutVT.isVector())
278 return DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT,
279 BitConvertToInteger(GetScalarizedVector(InOp)));
281 case TargetLowering::TypeSplitVector: {
282 // For example, i32 = BITCAST v2i16 on alpha. Convert the split
283 // pieces of the input into integers and reassemble in the final type.
285 GetSplitVector(N->getOperand(0), Lo, Hi);
286 Lo = BitConvertToInteger(Lo);
287 Hi = BitConvertToInteger(Hi);
289 if (DAG.getDataLayout().isBigEndian())
292 InOp = DAG.getNode(ISD::ANY_EXTEND, dl,
293 EVT::getIntegerVT(*DAG.getContext(),
294 NOutVT.getSizeInBits()),
295 JoinIntegers(Lo, Hi));
296 return DAG.getNode(ISD::BITCAST, dl, NOutVT, InOp);
298 case TargetLowering::TypeWidenVector:
299 // The input is widened to the same size. Convert to the widened value.
300 // Make sure that the outgoing value is not a vector, because this would
301 // make us bitcast between two vectors which are legalized in different ways.
302 if (NOutVT.bitsEq(NInVT) && !NOutVT.isVector())
303 return DAG.getNode(ISD::BITCAST, dl, NOutVT, GetWidenedVector(InOp));
306 return DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT,
307 CreateStackStoreLoad(InOp, OutVT));
310 SDValue DAGTypeLegalizer::PromoteIntRes_BSWAP(SDNode *N) {
311 SDValue Op = GetPromotedInteger(N->getOperand(0));
312 EVT OVT = N->getValueType(0);
313 EVT NVT = Op.getValueType();
316 unsigned DiffBits = NVT.getScalarSizeInBits() - OVT.getScalarSizeInBits();
318 ISD::SRL, dl, NVT, DAG.getNode(ISD::BSWAP, dl, NVT, Op),
319 DAG.getConstant(DiffBits, dl,
320 TLI.getShiftAmountTy(NVT, DAG.getDataLayout())));
323 SDValue DAGTypeLegalizer::PromoteIntRes_BUILD_PAIR(SDNode *N) {
324 // The pair element type may be legal, or may not promote to the same type as
325 // the result, for example i14 = BUILD_PAIR (i7, i7). Handle all cases.
326 return DAG.getNode(ISD::ANY_EXTEND, SDLoc(N),
327 TLI.getTypeToTransformTo(*DAG.getContext(),
328 N->getValueType(0)), JoinIntegers(N->getOperand(0),
332 SDValue DAGTypeLegalizer::PromoteIntRes_Constant(SDNode *N) {
333 EVT VT = N->getValueType(0);
334 // FIXME there is no actual debug info here
336 // Zero extend things like i1, sign extend everything else. It shouldn't
337 // matter in theory which one we pick, but this tends to give better code?
338 unsigned Opc = VT.isByteSized() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
339 SDValue Result = DAG.getNode(Opc, dl,
340 TLI.getTypeToTransformTo(*DAG.getContext(), VT),
342 assert(isa<ConstantSDNode>(Result) && "Didn't constant fold ext?");
346 SDValue DAGTypeLegalizer::PromoteIntRes_CONVERT_RNDSAT(SDNode *N) {
347 ISD::CvtCode CvtCode = cast<CvtRndSatSDNode>(N)->getCvtCode();
348 assert ((CvtCode == ISD::CVT_SS || CvtCode == ISD::CVT_SU ||
349 CvtCode == ISD::CVT_US || CvtCode == ISD::CVT_UU ||
350 CvtCode == ISD::CVT_SF || CvtCode == ISD::CVT_UF) &&
351 "can only promote integers");
352 EVT OutVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
353 return DAG.getConvertRndSat(OutVT, SDLoc(N), N->getOperand(0),
354 N->getOperand(1), N->getOperand(2),
355 N->getOperand(3), N->getOperand(4), CvtCode);
358 SDValue DAGTypeLegalizer::PromoteIntRes_CTLZ(SDNode *N) {
359 // Zero extend to the promoted type and do the count there.
360 SDValue Op = ZExtPromotedInteger(N->getOperand(0));
362 EVT OVT = N->getValueType(0);
363 EVT NVT = Op.getValueType();
364 Op = DAG.getNode(N->getOpcode(), dl, NVT, Op);
365 // Subtract off the extra leading bits in the bigger type.
367 ISD::SUB, dl, NVT, Op,
368 DAG.getConstant(NVT.getScalarSizeInBits() - OVT.getScalarSizeInBits(), dl,
372 SDValue DAGTypeLegalizer::PromoteIntRes_CTPOP(SDNode *N) {
373 // Zero extend to the promoted type and do the count there.
374 SDValue Op = ZExtPromotedInteger(N->getOperand(0));
375 return DAG.getNode(ISD::CTPOP, SDLoc(N), Op.getValueType(), Op);
378 SDValue DAGTypeLegalizer::PromoteIntRes_CTTZ(SDNode *N) {
379 SDValue Op = GetPromotedInteger(N->getOperand(0));
380 EVT OVT = N->getValueType(0);
381 EVT NVT = Op.getValueType();
383 if (N->getOpcode() == ISD::CTTZ) {
384 // The count is the same in the promoted type except if the original
385 // value was zero. This can be handled by setting the bit just off
386 // the top of the original type.
387 auto TopBit = APInt::getOneBitSet(NVT.getScalarSizeInBits(),
388 OVT.getScalarSizeInBits());
389 Op = DAG.getNode(ISD::OR, dl, NVT, Op, DAG.getConstant(TopBit, dl, NVT));
391 return DAG.getNode(N->getOpcode(), dl, NVT, Op);
394 SDValue DAGTypeLegalizer::PromoteIntRes_EXTRACT_VECTOR_ELT(SDNode *N) {
396 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
397 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, NVT, N->getOperand(0),
401 SDValue DAGTypeLegalizer::PromoteIntRes_FP_TO_XINT(SDNode *N) {
402 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
403 unsigned NewOpc = N->getOpcode();
406 // If we're promoting a UINT to a larger size and the larger FP_TO_UINT is
407 // not Legal, check to see if we can use FP_TO_SINT instead. (If both UINT
408 // and SINT conversions are Custom, there is no way to tell which is
409 // preferable. We choose SINT because that's the right thing on PPC.)
410 if (N->getOpcode() == ISD::FP_TO_UINT &&
411 !TLI.isOperationLegal(ISD::FP_TO_UINT, NVT) &&
412 TLI.isOperationLegalOrCustom(ISD::FP_TO_SINT, NVT))
413 NewOpc = ISD::FP_TO_SINT;
415 SDValue Res = DAG.getNode(NewOpc, dl, NVT, N->getOperand(0));
417 // Assert that the converted value fits in the original type. If it doesn't
418 // (eg: because the value being converted is too big), then the result of the
419 // original operation was undefined anyway, so the assert is still correct.
420 return DAG.getNode(N->getOpcode() == ISD::FP_TO_UINT ?
421 ISD::AssertZext : ISD::AssertSext, dl, NVT, Res,
422 DAG.getValueType(N->getValueType(0).getScalarType()));
425 SDValue DAGTypeLegalizer::PromoteIntRes_FP_TO_FP16(SDNode *N) {
426 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
429 SDValue Res = DAG.getNode(N->getOpcode(), dl, NVT, N->getOperand(0));
431 return DAG.getNode(ISD::AssertZext, dl,
432 NVT, Res, DAG.getValueType(N->getValueType(0)));
435 SDValue DAGTypeLegalizer::PromoteIntRes_INT_EXTEND(SDNode *N) {
436 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
439 if (getTypeAction(N->getOperand(0).getValueType())
440 == TargetLowering::TypePromoteInteger) {
441 SDValue Res = GetPromotedInteger(N->getOperand(0));
442 assert(Res.getValueType().bitsLE(NVT) && "Extension doesn't make sense!");
444 // If the result and operand types are the same after promotion, simplify
445 // to an in-register extension.
446 if (NVT == Res.getValueType()) {
447 // The high bits are not guaranteed to be anything. Insert an extend.
448 if (N->getOpcode() == ISD::SIGN_EXTEND)
449 return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NVT, Res,
450 DAG.getValueType(N->getOperand(0).getValueType()));
451 if (N->getOpcode() == ISD::ZERO_EXTEND)
452 return DAG.getZeroExtendInReg(Res, dl,
453 N->getOperand(0).getValueType().getScalarType());
454 assert(N->getOpcode() == ISD::ANY_EXTEND && "Unknown integer extension!");
459 // Otherwise, just extend the original operand all the way to the larger type.
460 return DAG.getNode(N->getOpcode(), dl, NVT, N->getOperand(0));
463 SDValue DAGTypeLegalizer::PromoteIntRes_LOAD(LoadSDNode *N) {
464 assert(ISD::isUNINDEXEDLoad(N) && "Indexed load during type legalization!");
465 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
466 ISD::LoadExtType ExtType =
467 ISD::isNON_EXTLoad(N) ? ISD::EXTLOAD : N->getExtensionType();
469 SDValue Res = DAG.getExtLoad(ExtType, dl, NVT, N->getChain(), N->getBasePtr(),
470 N->getMemoryVT(), N->getMemOperand());
472 // Legalized the chain result - switch anything that used the old chain to
474 ReplaceValueWith(SDValue(N, 1), Res.getValue(1));
478 SDValue DAGTypeLegalizer::PromoteIntRes_MLOAD(MaskedLoadSDNode *N) {
479 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
480 SDValue ExtSrc0 = GetPromotedInteger(N->getSrc0());
482 SDValue Mask = N->getMask();
483 EVT NewMaskVT = getSetCCResultType(NVT);
484 if (NewMaskVT != N->getMask().getValueType())
485 Mask = PromoteTargetBoolean(Mask, NewMaskVT);
488 SDValue Res = DAG.getMaskedLoad(NVT, dl, N->getChain(), N->getBasePtr(),
489 Mask, ExtSrc0, N->getMemoryVT(),
490 N->getMemOperand(), ISD::SEXTLOAD);
491 // Legalized the chain result - switch anything that used the old chain to
493 ReplaceValueWith(SDValue(N, 1), Res.getValue(1));
496 /// Promote the overflow flag of an overflowing arithmetic node.
497 SDValue DAGTypeLegalizer::PromoteIntRes_Overflow(SDNode *N) {
498 // Simply change the return type of the boolean result.
499 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(1));
500 EVT ValueVTs[] = { N->getValueType(0), NVT };
501 SDValue Ops[] = { N->getOperand(0), N->getOperand(1) };
502 SDValue Res = DAG.getNode(N->getOpcode(), SDLoc(N),
503 DAG.getVTList(ValueVTs), Ops);
505 // Modified the sum result - switch anything that used the old sum to use
507 ReplaceValueWith(SDValue(N, 0), Res);
509 return SDValue(Res.getNode(), 1);
512 SDValue DAGTypeLegalizer::PromoteIntRes_SADDSUBO(SDNode *N, unsigned ResNo) {
514 return PromoteIntRes_Overflow(N);
516 // The operation overflowed iff the result in the larger type is not the
517 // sign extension of its truncation to the original type.
518 SDValue LHS = SExtPromotedInteger(N->getOperand(0));
519 SDValue RHS = SExtPromotedInteger(N->getOperand(1));
520 EVT OVT = N->getOperand(0).getValueType();
521 EVT NVT = LHS.getValueType();
524 // Do the arithmetic in the larger type.
525 unsigned Opcode = N->getOpcode() == ISD::SADDO ? ISD::ADD : ISD::SUB;
526 SDValue Res = DAG.getNode(Opcode, dl, NVT, LHS, RHS);
528 // Calculate the overflow flag: sign extend the arithmetic result from
529 // the original type.
530 SDValue Ofl = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NVT, Res,
531 DAG.getValueType(OVT));
532 // Overflowed if and only if this is not equal to Res.
533 Ofl = DAG.getSetCC(dl, N->getValueType(1), Ofl, Res, ISD::SETNE);
535 // Use the calculated overflow everywhere.
536 ReplaceValueWith(SDValue(N, 1), Ofl);
541 SDValue DAGTypeLegalizer::PromoteIntRes_SDIV(SDNode *N) {
542 // Sign extend the input.
543 SDValue LHS = SExtPromotedInteger(N->getOperand(0));
544 SDValue RHS = SExtPromotedInteger(N->getOperand(1));
545 return DAG.getNode(N->getOpcode(), SDLoc(N),
546 LHS.getValueType(), LHS, RHS);
549 SDValue DAGTypeLegalizer::PromoteIntRes_SELECT(SDNode *N) {
550 SDValue LHS = GetPromotedInteger(N->getOperand(1));
551 SDValue RHS = GetPromotedInteger(N->getOperand(2));
552 return DAG.getSelect(SDLoc(N),
553 LHS.getValueType(), N->getOperand(0), LHS, RHS);
556 SDValue DAGTypeLegalizer::PromoteIntRes_VSELECT(SDNode *N) {
557 SDValue Mask = N->getOperand(0);
558 EVT OpTy = N->getOperand(1).getValueType();
560 // Promote all the way up to the canonical SetCC type.
561 Mask = PromoteTargetBoolean(Mask, OpTy);
562 SDValue LHS = GetPromotedInteger(N->getOperand(1));
563 SDValue RHS = GetPromotedInteger(N->getOperand(2));
564 return DAG.getNode(ISD::VSELECT, SDLoc(N),
565 LHS.getValueType(), Mask, LHS, RHS);
568 SDValue DAGTypeLegalizer::PromoteIntRes_SELECT_CC(SDNode *N) {
569 SDValue LHS = GetPromotedInteger(N->getOperand(2));
570 SDValue RHS = GetPromotedInteger(N->getOperand(3));
571 return DAG.getNode(ISD::SELECT_CC, SDLoc(N),
572 LHS.getValueType(), N->getOperand(0),
573 N->getOperand(1), LHS, RHS, N->getOperand(4));
576 SDValue DAGTypeLegalizer::PromoteIntRes_SETCC(SDNode *N) {
577 EVT SVT = getSetCCResultType(N->getOperand(0).getValueType());
579 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
581 // Only use the result of getSetCCResultType if it is legal,
582 // otherwise just use the promoted result type (NVT).
583 if (!TLI.isTypeLegal(SVT))
587 assert(SVT.isVector() == N->getOperand(0).getValueType().isVector() &&
588 "Vector compare must return a vector result!");
590 SDValue LHS = N->getOperand(0);
591 SDValue RHS = N->getOperand(1);
592 if (LHS.getValueType() != RHS.getValueType()) {
593 if (getTypeAction(LHS.getValueType()) == TargetLowering::TypePromoteInteger &&
594 !LHS.getValueType().isVector())
595 LHS = GetPromotedInteger(LHS);
596 if (getTypeAction(RHS.getValueType()) == TargetLowering::TypePromoteInteger &&
597 !RHS.getValueType().isVector())
598 RHS = GetPromotedInteger(RHS);
601 // Get the SETCC result using the canonical SETCC type.
602 SDValue SetCC = DAG.getNode(N->getOpcode(), dl, SVT, LHS, RHS,
605 assert(NVT.bitsLE(SVT) && "Integer type overpromoted?");
606 // Convert to the expected type.
607 return DAG.getNode(ISD::TRUNCATE, dl, NVT, SetCC);
610 SDValue DAGTypeLegalizer::PromoteIntRes_SHL(SDNode *N) {
611 SDValue LHS = N->getOperand(0);
612 SDValue RHS = N->getOperand(1);
613 if (getTypeAction(LHS.getValueType()) == TargetLowering::TypePromoteInteger)
614 LHS = GetPromotedInteger(LHS);
615 if (getTypeAction(RHS.getValueType()) == TargetLowering::TypePromoteInteger)
616 RHS = ZExtPromotedInteger(RHS);
617 return DAG.getNode(ISD::SHL, SDLoc(N), LHS.getValueType(), LHS, RHS);
620 SDValue DAGTypeLegalizer::PromoteIntRes_SIGN_EXTEND_INREG(SDNode *N) {
621 SDValue Op = GetPromotedInteger(N->getOperand(0));
622 return DAG.getNode(ISD::SIGN_EXTEND_INREG, SDLoc(N),
623 Op.getValueType(), Op, N->getOperand(1));
626 SDValue DAGTypeLegalizer::PromoteIntRes_SimpleIntBinOp(SDNode *N) {
627 // The input may have strange things in the top bits of the registers, but
628 // these operations don't care. They may have weird bits going out, but
629 // that too is okay if they are integer operations.
630 SDValue LHS = GetPromotedInteger(N->getOperand(0));
631 SDValue RHS = GetPromotedInteger(N->getOperand(1));
632 return DAG.getNode(N->getOpcode(), SDLoc(N),
633 LHS.getValueType(), LHS, RHS);
636 SDValue DAGTypeLegalizer::PromoteIntRes_SRA(SDNode *N) {
637 SDValue LHS = N->getOperand(0);
638 SDValue RHS = N->getOperand(1);
639 // The input value must be properly sign extended.
640 if (getTypeAction(LHS.getValueType()) == TargetLowering::TypePromoteInteger)
641 LHS = SExtPromotedInteger(LHS);
642 if (getTypeAction(RHS.getValueType()) == TargetLowering::TypePromoteInteger)
643 RHS = ZExtPromotedInteger(RHS);
644 return DAG.getNode(ISD::SRA, SDLoc(N), LHS.getValueType(), LHS, RHS);
647 SDValue DAGTypeLegalizer::PromoteIntRes_SRL(SDNode *N) {
648 SDValue LHS = N->getOperand(0);
649 SDValue RHS = N->getOperand(1);
650 // The input value must be properly zero extended.
651 if (getTypeAction(LHS.getValueType()) == TargetLowering::TypePromoteInteger)
652 LHS = ZExtPromotedInteger(LHS);
653 if (getTypeAction(RHS.getValueType()) == TargetLowering::TypePromoteInteger)
654 RHS = ZExtPromotedInteger(RHS);
655 return DAG.getNode(ISD::SRL, SDLoc(N), LHS.getValueType(), LHS, RHS);
658 SDValue DAGTypeLegalizer::PromoteIntRes_TRUNCATE(SDNode *N) {
659 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
661 SDValue InOp = N->getOperand(0);
664 switch (getTypeAction(InOp.getValueType())) {
665 default: llvm_unreachable("Unknown type action!");
666 case TargetLowering::TypeLegal:
667 case TargetLowering::TypeExpandInteger:
670 case TargetLowering::TypePromoteInteger:
671 Res = GetPromotedInteger(InOp);
673 case TargetLowering::TypeSplitVector:
674 EVT InVT = InOp.getValueType();
675 assert(InVT.isVector() && "Cannot split scalar types");
676 unsigned NumElts = InVT.getVectorNumElements();
677 assert(NumElts == NVT.getVectorNumElements() &&
678 "Dst and Src must have the same number of elements");
679 assert(isPowerOf2_32(NumElts) &&
680 "Promoted vector type must be a power of two");
683 GetSplitVector(InOp, EOp1, EOp2);
685 EVT HalfNVT = EVT::getVectorVT(*DAG.getContext(), NVT.getScalarType(),
687 EOp1 = DAG.getNode(ISD::TRUNCATE, dl, HalfNVT, EOp1);
688 EOp2 = DAG.getNode(ISD::TRUNCATE, dl, HalfNVT, EOp2);
690 return DAG.getNode(ISD::CONCAT_VECTORS, dl, NVT, EOp1, EOp2);
693 // Truncate to NVT instead of VT
694 return DAG.getNode(ISD::TRUNCATE, dl, NVT, Res);
697 SDValue DAGTypeLegalizer::PromoteIntRes_UADDSUBO(SDNode *N, unsigned ResNo) {
699 return PromoteIntRes_Overflow(N);
701 // The operation overflowed iff the result in the larger type is not the
702 // zero extension of its truncation to the original type.
703 SDValue LHS = ZExtPromotedInteger(N->getOperand(0));
704 SDValue RHS = ZExtPromotedInteger(N->getOperand(1));
705 EVT OVT = N->getOperand(0).getValueType();
706 EVT NVT = LHS.getValueType();
709 // Do the arithmetic in the larger type.
710 unsigned Opcode = N->getOpcode() == ISD::UADDO ? ISD::ADD : ISD::SUB;
711 SDValue Res = DAG.getNode(Opcode, dl, NVT, LHS, RHS);
713 // Calculate the overflow flag: zero extend the arithmetic result from
714 // the original type.
715 SDValue Ofl = DAG.getZeroExtendInReg(Res, dl, OVT);
716 // Overflowed if and only if this is not equal to Res.
717 Ofl = DAG.getSetCC(dl, N->getValueType(1), Ofl, Res, ISD::SETNE);
719 // Use the calculated overflow everywhere.
720 ReplaceValueWith(SDValue(N, 1), Ofl);
725 SDValue DAGTypeLegalizer::PromoteIntRes_XMULO(SDNode *N, unsigned ResNo) {
726 // Promote the overflow bit trivially.
728 return PromoteIntRes_Overflow(N);
730 SDValue LHS = N->getOperand(0), RHS = N->getOperand(1);
732 EVT SmallVT = LHS.getValueType();
734 // To determine if the result overflowed in a larger type, we extend the
735 // input to the larger type, do the multiply (checking if it overflows),
736 // then also check the high bits of the result to see if overflow happened
738 if (N->getOpcode() == ISD::SMULO) {
739 LHS = SExtPromotedInteger(LHS);
740 RHS = SExtPromotedInteger(RHS);
742 LHS = ZExtPromotedInteger(LHS);
743 RHS = ZExtPromotedInteger(RHS);
745 SDVTList VTs = DAG.getVTList(LHS.getValueType(), N->getValueType(1));
746 SDValue Mul = DAG.getNode(N->getOpcode(), DL, VTs, LHS, RHS);
748 // Overflow occurred if it occurred in the larger type, or if the high part
749 // of the result does not zero/sign-extend the low part. Check this second
750 // possibility first.
752 if (N->getOpcode() == ISD::UMULO) {
753 // Unsigned overflow occurred if the high part is non-zero.
754 SDValue Hi = DAG.getNode(ISD::SRL, DL, Mul.getValueType(), Mul,
755 DAG.getIntPtrConstant(SmallVT.getSizeInBits(),
757 Overflow = DAG.getSetCC(DL, N->getValueType(1), Hi,
758 DAG.getConstant(0, DL, Hi.getValueType()),
761 // Signed overflow occurred if the high part does not sign extend the low.
762 SDValue SExt = DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, Mul.getValueType(),
763 Mul, DAG.getValueType(SmallVT));
764 Overflow = DAG.getSetCC(DL, N->getValueType(1), SExt, Mul, ISD::SETNE);
767 // The only other way for overflow to occur is if the multiplication in the
768 // larger type itself overflowed.
769 Overflow = DAG.getNode(ISD::OR, DL, N->getValueType(1), Overflow,
770 SDValue(Mul.getNode(), 1));
772 // Use the calculated overflow everywhere.
773 ReplaceValueWith(SDValue(N, 1), Overflow);
777 SDValue DAGTypeLegalizer::PromoteIntRes_UDIV(SDNode *N) {
778 // Zero extend the input.
779 SDValue LHS = ZExtPromotedInteger(N->getOperand(0));
780 SDValue RHS = ZExtPromotedInteger(N->getOperand(1));
781 return DAG.getNode(N->getOpcode(), SDLoc(N),
782 LHS.getValueType(), LHS, RHS);
785 SDValue DAGTypeLegalizer::PromoteIntRes_UNDEF(SDNode *N) {
786 return DAG.getUNDEF(TLI.getTypeToTransformTo(*DAG.getContext(),
787 N->getValueType(0)));
790 SDValue DAGTypeLegalizer::PromoteIntRes_VAARG(SDNode *N) {
791 SDValue Chain = N->getOperand(0); // Get the chain.
792 SDValue Ptr = N->getOperand(1); // Get the pointer.
793 EVT VT = N->getValueType(0);
796 MVT RegVT = TLI.getRegisterType(*DAG.getContext(), VT);
797 unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), VT);
798 // The argument is passed as NumRegs registers of type RegVT.
800 SmallVector<SDValue, 8> Parts(NumRegs);
801 for (unsigned i = 0; i < NumRegs; ++i) {
802 Parts[i] = DAG.getVAArg(RegVT, dl, Chain, Ptr, N->getOperand(2),
803 N->getConstantOperandVal(3));
804 Chain = Parts[i].getValue(1);
807 // Handle endianness of the load.
808 if (DAG.getDataLayout().isBigEndian())
809 std::reverse(Parts.begin(), Parts.end());
811 // Assemble the parts in the promoted type.
812 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
813 SDValue Res = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Parts[0]);
814 for (unsigned i = 1; i < NumRegs; ++i) {
815 SDValue Part = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Parts[i]);
816 // Shift it to the right position and "or" it in.
817 Part = DAG.getNode(ISD::SHL, dl, NVT, Part,
818 DAG.getConstant(i * RegVT.getSizeInBits(), dl,
819 TLI.getPointerTy(DAG.getDataLayout())));
820 Res = DAG.getNode(ISD::OR, dl, NVT, Res, Part);
823 // Modified the chain result - switch anything that used the old chain to
825 ReplaceValueWith(SDValue(N, 1), Chain);
830 //===----------------------------------------------------------------------===//
831 // Integer Operand Promotion
832 //===----------------------------------------------------------------------===//
834 /// PromoteIntegerOperand - This method is called when the specified operand of
835 /// the specified node is found to need promotion. At this point, all of the
836 /// result types of the node are known to be legal, but other operands of the
837 /// node may need promotion or expansion as well as the specified one.
838 bool DAGTypeLegalizer::PromoteIntegerOperand(SDNode *N, unsigned OpNo) {
839 DEBUG(dbgs() << "Promote integer operand: "; N->dump(&DAG); dbgs() << "\n");
840 SDValue Res = SDValue();
842 if (CustomLowerNode(N, N->getOperand(OpNo).getValueType(), false))
845 switch (N->getOpcode()) {
848 dbgs() << "PromoteIntegerOperand Op #" << OpNo << ": ";
849 N->dump(&DAG); dbgs() << "\n";
851 llvm_unreachable("Do not know how to promote this operator's operand!");
853 case ISD::ANY_EXTEND: Res = PromoteIntOp_ANY_EXTEND(N); break;
854 case ISD::ATOMIC_STORE:
855 Res = PromoteIntOp_ATOMIC_STORE(cast<AtomicSDNode>(N));
857 case ISD::BITCAST: Res = PromoteIntOp_BITCAST(N); break;
858 case ISD::BR_CC: Res = PromoteIntOp_BR_CC(N, OpNo); break;
859 case ISD::BRCOND: Res = PromoteIntOp_BRCOND(N, OpNo); break;
860 case ISD::BUILD_PAIR: Res = PromoteIntOp_BUILD_PAIR(N); break;
861 case ISD::BUILD_VECTOR: Res = PromoteIntOp_BUILD_VECTOR(N); break;
862 case ISD::CONCAT_VECTORS: Res = PromoteIntOp_CONCAT_VECTORS(N); break;
863 case ISD::EXTRACT_VECTOR_ELT: Res = PromoteIntOp_EXTRACT_VECTOR_ELT(N); break;
864 case ISD::CONVERT_RNDSAT:
865 Res = PromoteIntOp_CONVERT_RNDSAT(N); break;
866 case ISD::INSERT_VECTOR_ELT:
867 Res = PromoteIntOp_INSERT_VECTOR_ELT(N, OpNo);break;
868 case ISD::SCALAR_TO_VECTOR:
869 Res = PromoteIntOp_SCALAR_TO_VECTOR(N); break;
871 case ISD::SELECT: Res = PromoteIntOp_SELECT(N, OpNo); break;
872 case ISD::SELECT_CC: Res = PromoteIntOp_SELECT_CC(N, OpNo); break;
873 case ISD::SETCC: Res = PromoteIntOp_SETCC(N, OpNo); break;
874 case ISD::SIGN_EXTEND: Res = PromoteIntOp_SIGN_EXTEND(N); break;
875 case ISD::SINT_TO_FP: Res = PromoteIntOp_SINT_TO_FP(N); break;
876 case ISD::STORE: Res = PromoteIntOp_STORE(cast<StoreSDNode>(N),
878 case ISD::MSTORE: Res = PromoteIntOp_MSTORE(cast<MaskedStoreSDNode>(N),
880 case ISD::MLOAD: Res = PromoteIntOp_MLOAD(cast<MaskedLoadSDNode>(N),
882 case ISD::TRUNCATE: Res = PromoteIntOp_TRUNCATE(N); break;
883 case ISD::FP16_TO_FP:
884 case ISD::UINT_TO_FP: Res = PromoteIntOp_UINT_TO_FP(N); break;
885 case ISD::ZERO_EXTEND: Res = PromoteIntOp_ZERO_EXTEND(N); break;
886 case ISD::EXTRACT_SUBVECTOR: Res = PromoteIntOp_EXTRACT_SUBVECTOR(N); break;
892 case ISD::ROTR: Res = PromoteIntOp_Shift(N); break;
895 // If the result is null, the sub-method took care of registering results etc.
896 if (!Res.getNode()) return false;
898 // If the result is N, the sub-method updated N in place. Tell the legalizer
900 if (Res.getNode() == N)
903 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 &&
904 "Invalid operand expansion");
906 ReplaceValueWith(SDValue(N, 0), Res);
910 /// PromoteSetCCOperands - Promote the operands of a comparison. This code is
911 /// shared among BR_CC, SELECT_CC, and SETCC handlers.
912 void DAGTypeLegalizer::PromoteSetCCOperands(SDValue &NewLHS,SDValue &NewRHS,
913 ISD::CondCode CCCode) {
914 // We have to insert explicit sign or zero extends. Note that we could
915 // insert sign extends for ALL conditions, but zero extend is cheaper on
916 // many machines (an AND instead of two shifts), so prefer it.
918 default: llvm_unreachable("Unknown integer comparison!");
921 SDValue OpL = GetPromotedInteger(NewLHS);
922 SDValue OpR = GetPromotedInteger(NewRHS);
924 // We would prefer to promote the comparison operand with sign extension,
925 // if we find the operand is actually to truncate an AssertSext. With this
926 // optimization, we can avoid inserting real truncate instruction, which
927 // is redudant eventually.
928 if (OpL->getOpcode() == ISD::AssertSext &&
929 cast<VTSDNode>(OpL->getOperand(1))->getVT() == NewLHS.getValueType() &&
930 OpR->getOpcode() == ISD::AssertSext &&
931 cast<VTSDNode>(OpR->getOperand(1))->getVT() == NewRHS.getValueType()) {
935 NewLHS = ZExtPromotedInteger(NewLHS);
936 NewRHS = ZExtPromotedInteger(NewRHS);
944 // ALL of these operations will work if we either sign or zero extend
945 // the operands (including the unsigned comparisons!). Zero extend is
946 // usually a simpler/cheaper operation, so prefer it.
947 NewLHS = ZExtPromotedInteger(NewLHS);
948 NewRHS = ZExtPromotedInteger(NewRHS);
954 NewLHS = SExtPromotedInteger(NewLHS);
955 NewRHS = SExtPromotedInteger(NewRHS);
960 SDValue DAGTypeLegalizer::PromoteIntOp_ANY_EXTEND(SDNode *N) {
961 SDValue Op = GetPromotedInteger(N->getOperand(0));
962 return DAG.getNode(ISD::ANY_EXTEND, SDLoc(N), N->getValueType(0), Op);
965 SDValue DAGTypeLegalizer::PromoteIntOp_ATOMIC_STORE(AtomicSDNode *N) {
966 SDValue Op2 = GetPromotedInteger(N->getOperand(2));
967 return DAG.getAtomic(N->getOpcode(), SDLoc(N), N->getMemoryVT(),
968 N->getChain(), N->getBasePtr(), Op2, N->getMemOperand(),
969 N->getOrdering(), N->getSynchScope());
972 SDValue DAGTypeLegalizer::PromoteIntOp_BITCAST(SDNode *N) {
973 // This should only occur in unusual situations like bitcasting to an
974 // x86_fp80, so just turn it into a store+load
975 return CreateStackStoreLoad(N->getOperand(0), N->getValueType(0));
978 SDValue DAGTypeLegalizer::PromoteIntOp_BR_CC(SDNode *N, unsigned OpNo) {
979 assert(OpNo == 2 && "Don't know how to promote this operand!");
981 SDValue LHS = N->getOperand(2);
982 SDValue RHS = N->getOperand(3);
983 PromoteSetCCOperands(LHS, RHS, cast<CondCodeSDNode>(N->getOperand(1))->get());
985 // The chain (Op#0), CC (#1) and basic block destination (Op#4) are always
987 return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0),
988 N->getOperand(1), LHS, RHS, N->getOperand(4)),
992 SDValue DAGTypeLegalizer::PromoteIntOp_BRCOND(SDNode *N, unsigned OpNo) {
993 assert(OpNo == 1 && "only know how to promote condition");
995 // Promote all the way up to the canonical SetCC type.
996 SDValue Cond = PromoteTargetBoolean(N->getOperand(1), MVT::Other);
998 // The chain (Op#0) and basic block destination (Op#2) are always legal types.
999 return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0), Cond,
1000 N->getOperand(2)), 0);
1003 SDValue DAGTypeLegalizer::PromoteIntOp_BUILD_PAIR(SDNode *N) {
1004 // Since the result type is legal, the operands must promote to it.
1005 EVT OVT = N->getOperand(0).getValueType();
1006 SDValue Lo = ZExtPromotedInteger(N->getOperand(0));
1007 SDValue Hi = GetPromotedInteger(N->getOperand(1));
1008 assert(Lo.getValueType() == N->getValueType(0) && "Operand over promoted?");
1011 Hi = DAG.getNode(ISD::SHL, dl, N->getValueType(0), Hi,
1012 DAG.getConstant(OVT.getSizeInBits(), dl,
1013 TLI.getPointerTy(DAG.getDataLayout())));
1014 return DAG.getNode(ISD::OR, dl, N->getValueType(0), Lo, Hi);
1017 SDValue DAGTypeLegalizer::PromoteIntOp_BUILD_VECTOR(SDNode *N) {
1018 // The vector type is legal but the element type is not. This implies
1019 // that the vector is a power-of-two in length and that the element
1020 // type does not have a strange size (eg: it is not i1).
1021 EVT VecVT = N->getValueType(0);
1022 unsigned NumElts = VecVT.getVectorNumElements();
1023 assert(!((NumElts & 1) && (!TLI.isTypeLegal(VecVT))) &&
1024 "Legal vector of one illegal element?");
1026 // Promote the inserted value. The type does not need to match the
1027 // vector element type. Check that any extra bits introduced will be
1029 assert(N->getOperand(0).getValueType().getSizeInBits() >=
1030 N->getValueType(0).getVectorElementType().getSizeInBits() &&
1031 "Type of inserted value narrower than vector element type!");
1033 SmallVector<SDValue, 16> NewOps;
1034 for (unsigned i = 0; i < NumElts; ++i)
1035 NewOps.push_back(GetPromotedInteger(N->getOperand(i)));
1037 return SDValue(DAG.UpdateNodeOperands(N, NewOps), 0);
1040 SDValue DAGTypeLegalizer::PromoteIntOp_CONVERT_RNDSAT(SDNode *N) {
1041 ISD::CvtCode CvtCode = cast<CvtRndSatSDNode>(N)->getCvtCode();
1042 assert ((CvtCode == ISD::CVT_SS || CvtCode == ISD::CVT_SU ||
1043 CvtCode == ISD::CVT_US || CvtCode == ISD::CVT_UU ||
1044 CvtCode == ISD::CVT_FS || CvtCode == ISD::CVT_FU) &&
1045 "can only promote integer arguments");
1046 SDValue InOp = GetPromotedInteger(N->getOperand(0));
1047 return DAG.getConvertRndSat(N->getValueType(0), SDLoc(N), InOp,
1048 N->getOperand(1), N->getOperand(2),
1049 N->getOperand(3), N->getOperand(4), CvtCode);
1052 SDValue DAGTypeLegalizer::PromoteIntOp_INSERT_VECTOR_ELT(SDNode *N,
1055 // Promote the inserted value. This is valid because the type does not
1056 // have to match the vector element type.
1058 // Check that any extra bits introduced will be truncated away.
1059 assert(N->getOperand(1).getValueType().getSizeInBits() >=
1060 N->getValueType(0).getVectorElementType().getSizeInBits() &&
1061 "Type of inserted value narrower than vector element type!");
1062 return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0),
1063 GetPromotedInteger(N->getOperand(1)),
1068 assert(OpNo == 2 && "Different operand and result vector types?");
1070 // Promote the index.
1071 SDValue Idx = DAG.getZExtOrTrunc(N->getOperand(2), SDLoc(N),
1072 TLI.getVectorIdxTy(DAG.getDataLayout()));
1073 return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0),
1074 N->getOperand(1), Idx), 0);
1077 SDValue DAGTypeLegalizer::PromoteIntOp_SCALAR_TO_VECTOR(SDNode *N) {
1078 // Integer SCALAR_TO_VECTOR operands are implicitly truncated, so just promote
1079 // the operand in place.
1080 return SDValue(DAG.UpdateNodeOperands(N,
1081 GetPromotedInteger(N->getOperand(0))), 0);
1084 SDValue DAGTypeLegalizer::PromoteIntOp_SELECT(SDNode *N, unsigned OpNo) {
1085 assert(OpNo == 0 && "Only know how to promote the condition!");
1086 SDValue Cond = N->getOperand(0);
1087 EVT OpTy = N->getOperand(1).getValueType();
1089 // Promote all the way up to the canonical SetCC type.
1090 EVT OpVT = N->getOpcode() == ISD::SELECT ? OpTy.getScalarType() : OpTy;
1091 Cond = PromoteTargetBoolean(Cond, OpVT);
1093 return SDValue(DAG.UpdateNodeOperands(N, Cond, N->getOperand(1),
1094 N->getOperand(2)), 0);
1097 SDValue DAGTypeLegalizer::PromoteIntOp_SELECT_CC(SDNode *N, unsigned OpNo) {
1098 assert(OpNo == 0 && "Don't know how to promote this operand!");
1100 SDValue LHS = N->getOperand(0);
1101 SDValue RHS = N->getOperand(1);
1102 PromoteSetCCOperands(LHS, RHS, cast<CondCodeSDNode>(N->getOperand(4))->get());
1104 // The CC (#4) and the possible return values (#2 and #3) have legal types.
1105 return SDValue(DAG.UpdateNodeOperands(N, LHS, RHS, N->getOperand(2),
1106 N->getOperand(3), N->getOperand(4)), 0);
1109 SDValue DAGTypeLegalizer::PromoteIntOp_SETCC(SDNode *N, unsigned OpNo) {
1110 assert(OpNo == 0 && "Don't know how to promote this operand!");
1112 SDValue LHS = N->getOperand(0);
1113 SDValue RHS = N->getOperand(1);
1114 PromoteSetCCOperands(LHS, RHS, cast<CondCodeSDNode>(N->getOperand(2))->get());
1116 // The CC (#2) is always legal.
1117 return SDValue(DAG.UpdateNodeOperands(N, LHS, RHS, N->getOperand(2)), 0);
1120 SDValue DAGTypeLegalizer::PromoteIntOp_Shift(SDNode *N) {
1121 return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0),
1122 ZExtPromotedInteger(N->getOperand(1))), 0);
1125 SDValue DAGTypeLegalizer::PromoteIntOp_SIGN_EXTEND(SDNode *N) {
1126 SDValue Op = GetPromotedInteger(N->getOperand(0));
1128 Op = DAG.getNode(ISD::ANY_EXTEND, dl, N->getValueType(0), Op);
1129 return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Op.getValueType(),
1130 Op, DAG.getValueType(N->getOperand(0).getValueType()));
1133 SDValue DAGTypeLegalizer::PromoteIntOp_SINT_TO_FP(SDNode *N) {
1134 return SDValue(DAG.UpdateNodeOperands(N,
1135 SExtPromotedInteger(N->getOperand(0))), 0);
1138 SDValue DAGTypeLegalizer::PromoteIntOp_STORE(StoreSDNode *N, unsigned OpNo){
1139 assert(ISD::isUNINDEXEDStore(N) && "Indexed store during type legalization!");
1140 SDValue Ch = N->getChain(), Ptr = N->getBasePtr();
1143 SDValue Val = GetPromotedInteger(N->getValue()); // Get promoted value.
1145 // Truncate the value and store the result.
1146 return DAG.getTruncStore(Ch, dl, Val, Ptr,
1147 N->getMemoryVT(), N->getMemOperand());
1150 SDValue DAGTypeLegalizer::PromoteIntOp_MSTORE(MaskedStoreSDNode *N, unsigned OpNo){
1152 SDValue DataOp = N->getValue();
1153 EVT DataVT = DataOp.getValueType();
1154 SDValue Mask = N->getMask();
1155 EVT MaskVT = Mask.getValueType();
1158 bool TruncateStore = false;
1159 if (!TLI.isTypeLegal(DataVT)) {
1160 if (getTypeAction(DataVT) == TargetLowering::TypePromoteInteger) {
1161 DataOp = GetPromotedInteger(DataOp);
1162 if (!TLI.isTypeLegal(MaskVT))
1163 Mask = PromoteTargetBoolean(Mask, DataOp.getValueType());
1164 TruncateStore = true;
1167 assert(getTypeAction(DataVT) == TargetLowering::TypeWidenVector &&
1168 "Unexpected data legalization in MSTORE");
1169 DataOp = GetWidenedVector(DataOp);
1171 if (getTypeAction(MaskVT) == TargetLowering::TypeWidenVector)
1172 Mask = GetWidenedVector(Mask);
1174 EVT BoolVT = getSetCCResultType(DataOp.getValueType());
1176 // We can't use ModifyToType() because we should fill the mask with
1178 unsigned WidenNumElts = BoolVT.getVectorNumElements();
1179 unsigned MaskNumElts = MaskVT.getVectorNumElements();
1181 unsigned NumConcat = WidenNumElts / MaskNumElts;
1182 SmallVector<SDValue, 16> Ops(NumConcat);
1183 SDValue ZeroVal = DAG.getConstant(0, dl, MaskVT);
1185 for (unsigned i = 1; i != NumConcat; ++i)
1188 Mask = DAG.getNode(ISD::CONCAT_VECTORS, dl, BoolVT, Ops);
1193 Mask = PromoteTargetBoolean(N->getMask(), DataOp.getValueType());
1194 return DAG.getMaskedStore(N->getChain(), dl, DataOp, N->getBasePtr(), Mask,
1195 N->getMemoryVT(), N->getMemOperand(),
1199 SDValue DAGTypeLegalizer::PromoteIntOp_MLOAD(MaskedLoadSDNode *N, unsigned OpNo){
1200 assert(OpNo == 2 && "Only know how to promote the mask!");
1201 EVT DataVT = N->getValueType(0);
1202 SDValue Mask = PromoteTargetBoolean(N->getOperand(OpNo), DataVT);
1203 SmallVector<SDValue, 4> NewOps(N->op_begin(), N->op_end());
1204 NewOps[OpNo] = Mask;
1205 return SDValue(DAG.UpdateNodeOperands(N, NewOps), 0);
1208 SDValue DAGTypeLegalizer::PromoteIntOp_TRUNCATE(SDNode *N) {
1209 SDValue Op = GetPromotedInteger(N->getOperand(0));
1210 return DAG.getNode(ISD::TRUNCATE, SDLoc(N), N->getValueType(0), Op);
1213 SDValue DAGTypeLegalizer::PromoteIntOp_UINT_TO_FP(SDNode *N) {
1214 return SDValue(DAG.UpdateNodeOperands(N,
1215 ZExtPromotedInteger(N->getOperand(0))), 0);
1218 SDValue DAGTypeLegalizer::PromoteIntOp_ZERO_EXTEND(SDNode *N) {
1220 SDValue Op = GetPromotedInteger(N->getOperand(0));
1221 Op = DAG.getNode(ISD::ANY_EXTEND, dl, N->getValueType(0), Op);
1222 return DAG.getZeroExtendInReg(Op, dl,
1223 N->getOperand(0).getValueType().getScalarType());
1227 //===----------------------------------------------------------------------===//
1228 // Integer Result Expansion
1229 //===----------------------------------------------------------------------===//
1231 /// ExpandIntegerResult - This method is called when the specified result of the
1232 /// specified node is found to need expansion. At this point, the node may also
1233 /// have invalid operands or may have other results that need promotion, we just
1234 /// know that (at least) one result needs expansion.
1235 void DAGTypeLegalizer::ExpandIntegerResult(SDNode *N, unsigned ResNo) {
1236 DEBUG(dbgs() << "Expand integer result: "; N->dump(&DAG); dbgs() << "\n");
1238 Lo = Hi = SDValue();
1240 // See if the target wants to custom expand this node.
1241 if (CustomLowerNode(N, N->getValueType(ResNo), true))
1244 switch (N->getOpcode()) {
1247 dbgs() << "ExpandIntegerResult #" << ResNo << ": ";
1248 N->dump(&DAG); dbgs() << "\n";
1250 llvm_unreachable("Do not know how to expand the result of this operator!");
1252 case ISD::MERGE_VALUES: SplitRes_MERGE_VALUES(N, ResNo, Lo, Hi); break;
1253 case ISD::SELECT: SplitRes_SELECT(N, Lo, Hi); break;
1254 case ISD::SELECT_CC: SplitRes_SELECT_CC(N, Lo, Hi); break;
1255 case ISD::UNDEF: SplitRes_UNDEF(N, Lo, Hi); break;
1257 case ISD::BITCAST: ExpandRes_BITCAST(N, Lo, Hi); break;
1258 case ISD::BUILD_PAIR: ExpandRes_BUILD_PAIR(N, Lo, Hi); break;
1259 case ISD::EXTRACT_ELEMENT: ExpandRes_EXTRACT_ELEMENT(N, Lo, Hi); break;
1260 case ISD::EXTRACT_VECTOR_ELT: ExpandRes_EXTRACT_VECTOR_ELT(N, Lo, Hi); break;
1261 case ISD::VAARG: ExpandRes_VAARG(N, Lo, Hi); break;
1263 case ISD::ANY_EXTEND: ExpandIntRes_ANY_EXTEND(N, Lo, Hi); break;
1264 case ISD::AssertSext: ExpandIntRes_AssertSext(N, Lo, Hi); break;
1265 case ISD::AssertZext: ExpandIntRes_AssertZext(N, Lo, Hi); break;
1266 case ISD::BSWAP: ExpandIntRes_BSWAP(N, Lo, Hi); break;
1267 case ISD::Constant: ExpandIntRes_Constant(N, Lo, Hi); break;
1268 case ISD::CTLZ_ZERO_UNDEF:
1269 case ISD::CTLZ: ExpandIntRes_CTLZ(N, Lo, Hi); break;
1270 case ISD::CTPOP: ExpandIntRes_CTPOP(N, Lo, Hi); break;
1271 case ISD::CTTZ_ZERO_UNDEF:
1272 case ISD::CTTZ: ExpandIntRes_CTTZ(N, Lo, Hi); break;
1273 case ISD::FP_TO_SINT: ExpandIntRes_FP_TO_SINT(N, Lo, Hi); break;
1274 case ISD::FP_TO_UINT: ExpandIntRes_FP_TO_UINT(N, Lo, Hi); break;
1275 case ISD::LOAD: ExpandIntRes_LOAD(cast<LoadSDNode>(N), Lo, Hi); break;
1276 case ISD::MUL: ExpandIntRes_MUL(N, Lo, Hi); break;
1277 case ISD::READCYCLECOUNTER: ExpandIntRes_READCYCLECOUNTER(N, Lo, Hi); break;
1278 case ISD::SDIV: ExpandIntRes_SDIV(N, Lo, Hi); break;
1279 case ISD::SIGN_EXTEND: ExpandIntRes_SIGN_EXTEND(N, Lo, Hi); break;
1280 case ISD::SIGN_EXTEND_INREG: ExpandIntRes_SIGN_EXTEND_INREG(N, Lo, Hi); break;
1281 case ISD::SREM: ExpandIntRes_SREM(N, Lo, Hi); break;
1282 case ISD::TRUNCATE: ExpandIntRes_TRUNCATE(N, Lo, Hi); break;
1283 case ISD::UDIV: ExpandIntRes_UDIV(N, Lo, Hi); break;
1284 case ISD::UREM: ExpandIntRes_UREM(N, Lo, Hi); break;
1285 case ISD::ZERO_EXTEND: ExpandIntRes_ZERO_EXTEND(N, Lo, Hi); break;
1286 case ISD::ATOMIC_LOAD: ExpandIntRes_ATOMIC_LOAD(N, Lo, Hi); break;
1288 case ISD::ATOMIC_LOAD_ADD:
1289 case ISD::ATOMIC_LOAD_SUB:
1290 case ISD::ATOMIC_LOAD_AND:
1291 case ISD::ATOMIC_LOAD_OR:
1292 case ISD::ATOMIC_LOAD_XOR:
1293 case ISD::ATOMIC_LOAD_NAND:
1294 case ISD::ATOMIC_LOAD_MIN:
1295 case ISD::ATOMIC_LOAD_MAX:
1296 case ISD::ATOMIC_LOAD_UMIN:
1297 case ISD::ATOMIC_LOAD_UMAX:
1298 case ISD::ATOMIC_SWAP:
1299 case ISD::ATOMIC_CMP_SWAP: {
1300 std::pair<SDValue, SDValue> Tmp = ExpandAtomic(N);
1301 SplitInteger(Tmp.first, Lo, Hi);
1302 ReplaceValueWith(SDValue(N, 1), Tmp.second);
1305 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS: {
1306 AtomicSDNode *AN = cast<AtomicSDNode>(N);
1307 SDVTList VTs = DAG.getVTList(N->getValueType(0), MVT::Other);
1308 SDValue Tmp = DAG.getAtomicCmpSwap(
1309 ISD::ATOMIC_CMP_SWAP, SDLoc(N), AN->getMemoryVT(), VTs,
1310 N->getOperand(0), N->getOperand(1), N->getOperand(2), N->getOperand(3),
1311 AN->getMemOperand(), AN->getSuccessOrdering(), AN->getFailureOrdering(),
1312 AN->getSynchScope());
1314 // Expanding to the strong ATOMIC_CMP_SWAP node means we can determine
1315 // success simply by comparing the loaded value against the ingoing
1317 SDValue Success = DAG.getSetCC(SDLoc(N), N->getValueType(1), Tmp,
1318 N->getOperand(2), ISD::SETEQ);
1320 SplitInteger(Tmp, Lo, Hi);
1321 ReplaceValueWith(SDValue(N, 1), Success);
1322 ReplaceValueWith(SDValue(N, 2), Tmp.getValue(1));
1328 case ISD::XOR: ExpandIntRes_Logical(N, Lo, Hi); break;
1331 case ISD::SUB: ExpandIntRes_ADDSUB(N, Lo, Hi); break;
1334 case ISD::SUBC: ExpandIntRes_ADDSUBC(N, Lo, Hi); break;
1337 case ISD::SUBE: ExpandIntRes_ADDSUBE(N, Lo, Hi); break;
1341 case ISD::SRL: ExpandIntRes_Shift(N, Lo, Hi); break;
1344 case ISD::SSUBO: ExpandIntRes_SADDSUBO(N, Lo, Hi); break;
1346 case ISD::USUBO: ExpandIntRes_UADDSUBO(N, Lo, Hi); break;
1348 case ISD::SMULO: ExpandIntRes_XMULO(N, Lo, Hi); break;
1351 // If Lo/Hi is null, the sub-method took care of registering results etc.
1353 SetExpandedInteger(SDValue(N, ResNo), Lo, Hi);
1356 /// Lower an atomic node to the appropriate builtin call.
1357 std::pair <SDValue, SDValue> DAGTypeLegalizer::ExpandAtomic(SDNode *Node) {
1358 unsigned Opc = Node->getOpcode();
1359 MVT VT = cast<AtomicSDNode>(Node)->getMemoryVT().getSimpleVT();
1360 RTLIB::Libcall LC = RTLIB::getATOMIC(Opc, VT);
1361 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected atomic op or value type!");
1363 return ExpandChainLibCall(LC, Node, false);
1366 /// N is a shift by a value that needs to be expanded,
1367 /// and the shift amount is a constant 'Amt'. Expand the operation.
1368 void DAGTypeLegalizer::ExpandShiftByConstant(SDNode *N, const APInt &Amt,
1369 SDValue &Lo, SDValue &Hi) {
1371 // Expand the incoming operand to be shifted, so that we have its parts
1373 GetExpandedInteger(N->getOperand(0), InL, InH);
1375 // Though Amt shouldn't usually be 0, it's possible. E.g. when legalization
1376 // splitted a vector shift, like this: <op1, op2> SHL <0, 2>.
1383 EVT NVT = InL.getValueType();
1384 unsigned VTBits = N->getValueType(0).getSizeInBits();
1385 unsigned NVTBits = NVT.getSizeInBits();
1386 EVT ShTy = N->getOperand(1).getValueType();
1388 if (N->getOpcode() == ISD::SHL) {
1389 if (Amt.ugt(VTBits)) {
1390 Lo = Hi = DAG.getConstant(0, DL, NVT);
1391 } else if (Amt.ugt(NVTBits)) {
1392 Lo = DAG.getConstant(0, DL, NVT);
1393 Hi = DAG.getNode(ISD::SHL, DL,
1394 NVT, InL, DAG.getConstant(Amt - NVTBits, DL, ShTy));
1395 } else if (Amt == NVTBits) {
1396 Lo = DAG.getConstant(0, DL, NVT);
1398 } else if (Amt == 1 &&
1399 TLI.isOperationLegalOrCustom(ISD::ADDC,
1400 TLI.getTypeToExpandTo(*DAG.getContext(), NVT))) {
1401 // Emit this X << 1 as X+X.
1402 SDVTList VTList = DAG.getVTList(NVT, MVT::Glue);
1403 SDValue LoOps[2] = { InL, InL };
1404 Lo = DAG.getNode(ISD::ADDC, DL, VTList, LoOps);
1405 SDValue HiOps[3] = { InH, InH, Lo.getValue(1) };
1406 Hi = DAG.getNode(ISD::ADDE, DL, VTList, HiOps);
1408 Lo = DAG.getNode(ISD::SHL, DL, NVT, InL, DAG.getConstant(Amt, DL, ShTy));
1409 Hi = DAG.getNode(ISD::OR, DL, NVT,
1410 DAG.getNode(ISD::SHL, DL, NVT, InH,
1411 DAG.getConstant(Amt, DL, ShTy)),
1412 DAG.getNode(ISD::SRL, DL, NVT, InL,
1413 DAG.getConstant(-Amt + NVTBits, DL, ShTy)));
1418 if (N->getOpcode() == ISD::SRL) {
1419 if (Amt.ugt(VTBits)) {
1420 Lo = Hi = DAG.getConstant(0, DL, NVT);
1421 } else if (Amt.ugt(NVTBits)) {
1422 Lo = DAG.getNode(ISD::SRL, DL,
1423 NVT, InH, DAG.getConstant(Amt - NVTBits, DL, ShTy));
1424 Hi = DAG.getConstant(0, DL, NVT);
1425 } else if (Amt == NVTBits) {
1427 Hi = DAG.getConstant(0, DL, NVT);
1429 Lo = DAG.getNode(ISD::OR, DL, NVT,
1430 DAG.getNode(ISD::SRL, DL, NVT, InL,
1431 DAG.getConstant(Amt, DL, ShTy)),
1432 DAG.getNode(ISD::SHL, DL, NVT, InH,
1433 DAG.getConstant(-Amt + NVTBits, DL, ShTy)));
1434 Hi = DAG.getNode(ISD::SRL, DL, NVT, InH, DAG.getConstant(Amt, DL, ShTy));
1439 assert(N->getOpcode() == ISD::SRA && "Unknown shift!");
1440 if (Amt.ugt(VTBits)) {
1441 Hi = Lo = DAG.getNode(ISD::SRA, DL, NVT, InH,
1442 DAG.getConstant(NVTBits - 1, DL, ShTy));
1443 } else if (Amt.ugt(NVTBits)) {
1444 Lo = DAG.getNode(ISD::SRA, DL, NVT, InH,
1445 DAG.getConstant(Amt - NVTBits, DL, ShTy));
1446 Hi = DAG.getNode(ISD::SRA, DL, NVT, InH,
1447 DAG.getConstant(NVTBits - 1, DL, ShTy));
1448 } else if (Amt == NVTBits) {
1450 Hi = DAG.getNode(ISD::SRA, DL, NVT, InH,
1451 DAG.getConstant(NVTBits - 1, DL, ShTy));
1453 Lo = DAG.getNode(ISD::OR, DL, NVT,
1454 DAG.getNode(ISD::SRL, DL, NVT, InL,
1455 DAG.getConstant(Amt, DL, ShTy)),
1456 DAG.getNode(ISD::SHL, DL, NVT, InH,
1457 DAG.getConstant(-Amt + NVTBits, DL, ShTy)));
1458 Hi = DAG.getNode(ISD::SRA, DL, NVT, InH, DAG.getConstant(Amt, DL, ShTy));
1462 /// ExpandShiftWithKnownAmountBit - Try to determine whether we can simplify
1463 /// this shift based on knowledge of the high bit of the shift amount. If we
1464 /// can tell this, we know that it is >= 32 or < 32, without knowing the actual
1466 bool DAGTypeLegalizer::
1467 ExpandShiftWithKnownAmountBit(SDNode *N, SDValue &Lo, SDValue &Hi) {
1468 SDValue Amt = N->getOperand(1);
1469 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1470 EVT ShTy = Amt.getValueType();
1471 unsigned ShBits = ShTy.getScalarType().getSizeInBits();
1472 unsigned NVTBits = NVT.getScalarType().getSizeInBits();
1473 assert(isPowerOf2_32(NVTBits) &&
1474 "Expanded integer type size not a power of two!");
1477 APInt HighBitMask = APInt::getHighBitsSet(ShBits, ShBits - Log2_32(NVTBits));
1478 APInt KnownZero, KnownOne;
1479 DAG.computeKnownBits(N->getOperand(1), KnownZero, KnownOne);
1481 // If we don't know anything about the high bits, exit.
1482 if (((KnownZero|KnownOne) & HighBitMask) == 0)
1485 // Get the incoming operand to be shifted.
1487 GetExpandedInteger(N->getOperand(0), InL, InH);
1489 // If we know that any of the high bits of the shift amount are one, then we
1490 // can do this as a couple of simple shifts.
1491 if (KnownOne.intersects(HighBitMask)) {
1492 // Mask out the high bit, which we know is set.
1493 Amt = DAG.getNode(ISD::AND, dl, ShTy, Amt,
1494 DAG.getConstant(~HighBitMask, dl, ShTy));
1496 switch (N->getOpcode()) {
1497 default: llvm_unreachable("Unknown shift");
1499 Lo = DAG.getConstant(0, dl, NVT); // Low part is zero.
1500 Hi = DAG.getNode(ISD::SHL, dl, NVT, InL, Amt); // High part from Lo part.
1503 Hi = DAG.getConstant(0, dl, NVT); // Hi part is zero.
1504 Lo = DAG.getNode(ISD::SRL, dl, NVT, InH, Amt); // Lo part from Hi part.
1507 Hi = DAG.getNode(ISD::SRA, dl, NVT, InH, // Sign extend high part.
1508 DAG.getConstant(NVTBits - 1, dl, ShTy));
1509 Lo = DAG.getNode(ISD::SRA, dl, NVT, InH, Amt); // Lo part from Hi part.
1514 // If we know that all of the high bits of the shift amount are zero, then we
1515 // can do this as a couple of simple shifts.
1516 if ((KnownZero & HighBitMask) == HighBitMask) {
1517 // Calculate 31-x. 31 is used instead of 32 to avoid creating an undefined
1518 // shift if x is zero. We can use XOR here because x is known to be smaller
1520 SDValue Amt2 = DAG.getNode(ISD::XOR, dl, ShTy, Amt,
1521 DAG.getConstant(NVTBits - 1, dl, ShTy));
1524 switch (N->getOpcode()) {
1525 default: llvm_unreachable("Unknown shift");
1526 case ISD::SHL: Op1 = ISD::SHL; Op2 = ISD::SRL; break;
1528 case ISD::SRA: Op1 = ISD::SRL; Op2 = ISD::SHL; break;
1531 // When shifting right the arithmetic for Lo and Hi is swapped.
1532 if (N->getOpcode() != ISD::SHL)
1533 std::swap(InL, InH);
1535 // Use a little trick to get the bits that move from Lo to Hi. First
1536 // shift by one bit.
1537 SDValue Sh1 = DAG.getNode(Op2, dl, NVT, InL, DAG.getConstant(1, dl, ShTy));
1538 // Then compute the remaining shift with amount-1.
1539 SDValue Sh2 = DAG.getNode(Op2, dl, NVT, Sh1, Amt2);
1541 Lo = DAG.getNode(N->getOpcode(), dl, NVT, InL, Amt);
1542 Hi = DAG.getNode(ISD::OR, dl, NVT, DAG.getNode(Op1, dl, NVT, InH, Amt),Sh2);
1544 if (N->getOpcode() != ISD::SHL)
1552 /// ExpandShiftWithUnknownAmountBit - Fully general expansion of integer shift
1554 bool DAGTypeLegalizer::
1555 ExpandShiftWithUnknownAmountBit(SDNode *N, SDValue &Lo, SDValue &Hi) {
1556 SDValue Amt = N->getOperand(1);
1557 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1558 EVT ShTy = Amt.getValueType();
1559 unsigned NVTBits = NVT.getSizeInBits();
1560 assert(isPowerOf2_32(NVTBits) &&
1561 "Expanded integer type size not a power of two!");
1564 // Get the incoming operand to be shifted.
1566 GetExpandedInteger(N->getOperand(0), InL, InH);
1568 SDValue NVBitsNode = DAG.getConstant(NVTBits, dl, ShTy);
1569 SDValue AmtExcess = DAG.getNode(ISD::SUB, dl, ShTy, Amt, NVBitsNode);
1570 SDValue AmtLack = DAG.getNode(ISD::SUB, dl, ShTy, NVBitsNode, Amt);
1571 SDValue isShort = DAG.getSetCC(dl, getSetCCResultType(ShTy),
1572 Amt, NVBitsNode, ISD::SETULT);
1573 SDValue isZero = DAG.getSetCC(dl, getSetCCResultType(ShTy),
1574 Amt, DAG.getConstant(0, dl, ShTy),
1577 SDValue LoS, HiS, LoL, HiL;
1578 switch (N->getOpcode()) {
1579 default: llvm_unreachable("Unknown shift");
1581 // Short: ShAmt < NVTBits
1582 LoS = DAG.getNode(ISD::SHL, dl, NVT, InL, Amt);
1583 HiS = DAG.getNode(ISD::OR, dl, NVT,
1584 DAG.getNode(ISD::SHL, dl, NVT, InH, Amt),
1585 DAG.getNode(ISD::SRL, dl, NVT, InL, AmtLack));
1587 // Long: ShAmt >= NVTBits
1588 LoL = DAG.getConstant(0, dl, NVT); // Lo part is zero.
1589 HiL = DAG.getNode(ISD::SHL, dl, NVT, InL, AmtExcess); // Hi from Lo part.
1591 Lo = DAG.getSelect(dl, NVT, isShort, LoS, LoL);
1592 Hi = DAG.getSelect(dl, NVT, isZero, InH,
1593 DAG.getSelect(dl, NVT, isShort, HiS, HiL));
1596 // Short: ShAmt < NVTBits
1597 HiS = DAG.getNode(ISD::SRL, dl, NVT, InH, Amt);
1598 LoS = DAG.getNode(ISD::OR, dl, NVT,
1599 DAG.getNode(ISD::SRL, dl, NVT, InL, Amt),
1600 // FIXME: If Amt is zero, the following shift generates an undefined result
1601 // on some architectures.
1602 DAG.getNode(ISD::SHL, dl, NVT, InH, AmtLack));
1604 // Long: ShAmt >= NVTBits
1605 HiL = DAG.getConstant(0, dl, NVT); // Hi part is zero.
1606 LoL = DAG.getNode(ISD::SRL, dl, NVT, InH, AmtExcess); // Lo from Hi part.
1608 Lo = DAG.getSelect(dl, NVT, isZero, InL,
1609 DAG.getSelect(dl, NVT, isShort, LoS, LoL));
1610 Hi = DAG.getSelect(dl, NVT, isShort, HiS, HiL);
1613 // Short: ShAmt < NVTBits
1614 HiS = DAG.getNode(ISD::SRA, dl, NVT, InH, Amt);
1615 LoS = DAG.getNode(ISD::OR, dl, NVT,
1616 DAG.getNode(ISD::SRL, dl, NVT, InL, Amt),
1617 DAG.getNode(ISD::SHL, dl, NVT, InH, AmtLack));
1619 // Long: ShAmt >= NVTBits
1620 HiL = DAG.getNode(ISD::SRA, dl, NVT, InH, // Sign of Hi part.
1621 DAG.getConstant(NVTBits - 1, dl, ShTy));
1622 LoL = DAG.getNode(ISD::SRA, dl, NVT, InH, AmtExcess); // Lo from Hi part.
1624 Lo = DAG.getSelect(dl, NVT, isZero, InL,
1625 DAG.getSelect(dl, NVT, isShort, LoS, LoL));
1626 Hi = DAG.getSelect(dl, NVT, isShort, HiS, HiL);
1631 void DAGTypeLegalizer::ExpandIntRes_ADDSUB(SDNode *N,
1632 SDValue &Lo, SDValue &Hi) {
1634 // Expand the subcomponents.
1635 SDValue LHSL, LHSH, RHSL, RHSH;
1636 GetExpandedInteger(N->getOperand(0), LHSL, LHSH);
1637 GetExpandedInteger(N->getOperand(1), RHSL, RHSH);
1639 EVT NVT = LHSL.getValueType();
1640 SDValue LoOps[2] = { LHSL, RHSL };
1641 SDValue HiOps[3] = { LHSH, RHSH };
1643 // Do not generate ADDC/ADDE or SUBC/SUBE if the target does not support
1644 // them. TODO: Teach operation legalization how to expand unsupported
1645 // ADDC/ADDE/SUBC/SUBE. The problem is that these operations generate
1646 // a carry of type MVT::Glue, but there doesn't seem to be any way to
1647 // generate a value of this type in the expanded code sequence.
1649 TLI.isOperationLegalOrCustom(N->getOpcode() == ISD::ADD ?
1650 ISD::ADDC : ISD::SUBC,
1651 TLI.getTypeToExpandTo(*DAG.getContext(), NVT));
1654 SDVTList VTList = DAG.getVTList(NVT, MVT::Glue);
1655 if (N->getOpcode() == ISD::ADD) {
1656 Lo = DAG.getNode(ISD::ADDC, dl, VTList, LoOps);
1657 HiOps[2] = Lo.getValue(1);
1658 Hi = DAG.getNode(ISD::ADDE, dl, VTList, HiOps);
1660 Lo = DAG.getNode(ISD::SUBC, dl, VTList, LoOps);
1661 HiOps[2] = Lo.getValue(1);
1662 Hi = DAG.getNode(ISD::SUBE, dl, VTList, HiOps);
1668 TLI.isOperationLegalOrCustom(N->getOpcode() == ISD::ADD ?
1669 ISD::UADDO : ISD::USUBO,
1670 TLI.getTypeToExpandTo(*DAG.getContext(), NVT));
1672 SDVTList VTList = DAG.getVTList(NVT, NVT);
1673 TargetLoweringBase::BooleanContent BoolType = TLI.getBooleanContents(NVT);
1675 if (N->getOpcode() == ISD::ADD) {
1677 Lo = DAG.getNode(ISD::UADDO, dl, VTList, LoOps);
1678 Hi = DAG.getNode(ISD::ADD, dl, NVT, makeArrayRef(HiOps, 2));
1681 Lo = DAG.getNode(ISD::USUBO, dl, VTList, LoOps);
1682 Hi = DAG.getNode(ISD::SUB, dl, NVT, makeArrayRef(HiOps, 2));
1684 SDValue OVF = Lo.getValue(1);
1687 case TargetLoweringBase::UndefinedBooleanContent:
1688 OVF = DAG.getNode(ISD::AND, dl, NVT, DAG.getConstant(1, dl, NVT), OVF);
1690 case TargetLoweringBase::ZeroOrOneBooleanContent:
1691 Hi = DAG.getNode(N->getOpcode(), dl, NVT, Hi, OVF);
1693 case TargetLoweringBase::ZeroOrNegativeOneBooleanContent:
1694 Hi = DAG.getNode(RevOpc, dl, NVT, Hi, OVF);
1699 if (N->getOpcode() == ISD::ADD) {
1700 Lo = DAG.getNode(ISD::ADD, dl, NVT, LoOps);
1701 Hi = DAG.getNode(ISD::ADD, dl, NVT, makeArrayRef(HiOps, 2));
1702 SDValue Cmp1 = DAG.getSetCC(dl, getSetCCResultType(NVT), Lo, LoOps[0],
1704 SDValue Carry1 = DAG.getSelect(dl, NVT, Cmp1,
1705 DAG.getConstant(1, dl, NVT),
1706 DAG.getConstant(0, dl, NVT));
1707 SDValue Cmp2 = DAG.getSetCC(dl, getSetCCResultType(NVT), Lo, LoOps[1],
1709 SDValue Carry2 = DAG.getSelect(dl, NVT, Cmp2,
1710 DAG.getConstant(1, dl, NVT), Carry1);
1711 Hi = DAG.getNode(ISD::ADD, dl, NVT, Hi, Carry2);
1713 Lo = DAG.getNode(ISD::SUB, dl, NVT, LoOps);
1714 Hi = DAG.getNode(ISD::SUB, dl, NVT, makeArrayRef(HiOps, 2));
1716 DAG.getSetCC(dl, getSetCCResultType(LoOps[0].getValueType()),
1717 LoOps[0], LoOps[1], ISD::SETULT);
1718 SDValue Borrow = DAG.getSelect(dl, NVT, Cmp,
1719 DAG.getConstant(1, dl, NVT),
1720 DAG.getConstant(0, dl, NVT));
1721 Hi = DAG.getNode(ISD::SUB, dl, NVT, Hi, Borrow);
1725 void DAGTypeLegalizer::ExpandIntRes_ADDSUBC(SDNode *N,
1726 SDValue &Lo, SDValue &Hi) {
1727 // Expand the subcomponents.
1728 SDValue LHSL, LHSH, RHSL, RHSH;
1730 GetExpandedInteger(N->getOperand(0), LHSL, LHSH);
1731 GetExpandedInteger(N->getOperand(1), RHSL, RHSH);
1732 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Glue);
1733 SDValue LoOps[2] = { LHSL, RHSL };
1734 SDValue HiOps[3] = { LHSH, RHSH };
1736 if (N->getOpcode() == ISD::ADDC) {
1737 Lo = DAG.getNode(ISD::ADDC, dl, VTList, LoOps);
1738 HiOps[2] = Lo.getValue(1);
1739 Hi = DAG.getNode(ISD::ADDE, dl, VTList, HiOps);
1741 Lo = DAG.getNode(ISD::SUBC, dl, VTList, LoOps);
1742 HiOps[2] = Lo.getValue(1);
1743 Hi = DAG.getNode(ISD::SUBE, dl, VTList, HiOps);
1746 // Legalized the flag result - switch anything that used the old flag to
1748 ReplaceValueWith(SDValue(N, 1), Hi.getValue(1));
1751 void DAGTypeLegalizer::ExpandIntRes_ADDSUBE(SDNode *N,
1752 SDValue &Lo, SDValue &Hi) {
1753 // Expand the subcomponents.
1754 SDValue LHSL, LHSH, RHSL, RHSH;
1756 GetExpandedInteger(N->getOperand(0), LHSL, LHSH);
1757 GetExpandedInteger(N->getOperand(1), RHSL, RHSH);
1758 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Glue);
1759 SDValue LoOps[3] = { LHSL, RHSL, N->getOperand(2) };
1760 SDValue HiOps[3] = { LHSH, RHSH };
1762 Lo = DAG.getNode(N->getOpcode(), dl, VTList, LoOps);
1763 HiOps[2] = Lo.getValue(1);
1764 Hi = DAG.getNode(N->getOpcode(), dl, VTList, HiOps);
1766 // Legalized the flag result - switch anything that used the old flag to
1768 ReplaceValueWith(SDValue(N, 1), Hi.getValue(1));
1771 void DAGTypeLegalizer::ExpandIntRes_ANY_EXTEND(SDNode *N,
1772 SDValue &Lo, SDValue &Hi) {
1773 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1775 SDValue Op = N->getOperand(0);
1776 if (Op.getValueType().bitsLE(NVT)) {
1777 // The low part is any extension of the input (which degenerates to a copy).
1778 Lo = DAG.getNode(ISD::ANY_EXTEND, dl, NVT, Op);
1779 Hi = DAG.getUNDEF(NVT); // The high part is undefined.
1781 // For example, extension of an i48 to an i64. The operand type necessarily
1782 // promotes to the result type, so will end up being expanded too.
1783 assert(getTypeAction(Op.getValueType()) ==
1784 TargetLowering::TypePromoteInteger &&
1785 "Only know how to promote this result!");
1786 SDValue Res = GetPromotedInteger(Op);
1787 assert(Res.getValueType() == N->getValueType(0) &&
1788 "Operand over promoted?");
1789 // Split the promoted operand. This will simplify when it is expanded.
1790 SplitInteger(Res, Lo, Hi);
1794 void DAGTypeLegalizer::ExpandIntRes_AssertSext(SDNode *N,
1795 SDValue &Lo, SDValue &Hi) {
1797 GetExpandedInteger(N->getOperand(0), Lo, Hi);
1798 EVT NVT = Lo.getValueType();
1799 EVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
1800 unsigned NVTBits = NVT.getSizeInBits();
1801 unsigned EVTBits = EVT.getSizeInBits();
1803 if (NVTBits < EVTBits) {
1804 Hi = DAG.getNode(ISD::AssertSext, dl, NVT, Hi,
1805 DAG.getValueType(EVT::getIntegerVT(*DAG.getContext(),
1806 EVTBits - NVTBits)));
1808 Lo = DAG.getNode(ISD::AssertSext, dl, NVT, Lo, DAG.getValueType(EVT));
1809 // The high part replicates the sign bit of Lo, make it explicit.
1810 Hi = DAG.getNode(ISD::SRA, dl, NVT, Lo,
1811 DAG.getConstant(NVTBits - 1, dl,
1812 TLI.getPointerTy(DAG.getDataLayout())));
1816 void DAGTypeLegalizer::ExpandIntRes_AssertZext(SDNode *N,
1817 SDValue &Lo, SDValue &Hi) {
1819 GetExpandedInteger(N->getOperand(0), Lo, Hi);
1820 EVT NVT = Lo.getValueType();
1821 EVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
1822 unsigned NVTBits = NVT.getSizeInBits();
1823 unsigned EVTBits = EVT.getSizeInBits();
1825 if (NVTBits < EVTBits) {
1826 Hi = DAG.getNode(ISD::AssertZext, dl, NVT, Hi,
1827 DAG.getValueType(EVT::getIntegerVT(*DAG.getContext(),
1828 EVTBits - NVTBits)));
1830 Lo = DAG.getNode(ISD::AssertZext, dl, NVT, Lo, DAG.getValueType(EVT));
1831 // The high part must be zero, make it explicit.
1832 Hi = DAG.getConstant(0, dl, NVT);
1836 void DAGTypeLegalizer::ExpandIntRes_BSWAP(SDNode *N,
1837 SDValue &Lo, SDValue &Hi) {
1839 GetExpandedInteger(N->getOperand(0), Hi, Lo); // Note swapped operands.
1840 Lo = DAG.getNode(ISD::BSWAP, dl, Lo.getValueType(), Lo);
1841 Hi = DAG.getNode(ISD::BSWAP, dl, Hi.getValueType(), Hi);
1844 void DAGTypeLegalizer::ExpandIntRes_Constant(SDNode *N,
1845 SDValue &Lo, SDValue &Hi) {
1846 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1847 unsigned NBitWidth = NVT.getSizeInBits();
1848 auto Constant = cast<ConstantSDNode>(N);
1849 const APInt &Cst = Constant->getAPIntValue();
1850 bool IsTarget = Constant->isTargetOpcode();
1851 bool IsOpaque = Constant->isOpaque();
1853 Lo = DAG.getConstant(Cst.trunc(NBitWidth), dl, NVT, IsTarget, IsOpaque);
1854 Hi = DAG.getConstant(Cst.lshr(NBitWidth).trunc(NBitWidth), dl, NVT, IsTarget,
1858 void DAGTypeLegalizer::ExpandIntRes_CTLZ(SDNode *N,
1859 SDValue &Lo, SDValue &Hi) {
1861 // ctlz (HiLo) -> Hi != 0 ? ctlz(Hi) : (ctlz(Lo)+32)
1862 GetExpandedInteger(N->getOperand(0), Lo, Hi);
1863 EVT NVT = Lo.getValueType();
1865 SDValue HiNotZero = DAG.getSetCC(dl, getSetCCResultType(NVT), Hi,
1866 DAG.getConstant(0, dl, NVT), ISD::SETNE);
1868 SDValue LoLZ = DAG.getNode(N->getOpcode(), dl, NVT, Lo);
1869 SDValue HiLZ = DAG.getNode(ISD::CTLZ_ZERO_UNDEF, dl, NVT, Hi);
1871 Lo = DAG.getSelect(dl, NVT, HiNotZero, HiLZ,
1872 DAG.getNode(ISD::ADD, dl, NVT, LoLZ,
1873 DAG.getConstant(NVT.getSizeInBits(), dl,
1875 Hi = DAG.getConstant(0, dl, NVT);
1878 void DAGTypeLegalizer::ExpandIntRes_CTPOP(SDNode *N,
1879 SDValue &Lo, SDValue &Hi) {
1881 // ctpop(HiLo) -> ctpop(Hi)+ctpop(Lo)
1882 GetExpandedInteger(N->getOperand(0), Lo, Hi);
1883 EVT NVT = Lo.getValueType();
1884 Lo = DAG.getNode(ISD::ADD, dl, NVT, DAG.getNode(ISD::CTPOP, dl, NVT, Lo),
1885 DAG.getNode(ISD::CTPOP, dl, NVT, Hi));
1886 Hi = DAG.getConstant(0, dl, NVT);
1889 void DAGTypeLegalizer::ExpandIntRes_CTTZ(SDNode *N,
1890 SDValue &Lo, SDValue &Hi) {
1892 // cttz (HiLo) -> Lo != 0 ? cttz(Lo) : (cttz(Hi)+32)
1893 GetExpandedInteger(N->getOperand(0), Lo, Hi);
1894 EVT NVT = Lo.getValueType();
1896 SDValue LoNotZero = DAG.getSetCC(dl, getSetCCResultType(NVT), Lo,
1897 DAG.getConstant(0, dl, NVT), ISD::SETNE);
1899 SDValue LoLZ = DAG.getNode(ISD::CTTZ_ZERO_UNDEF, dl, NVT, Lo);
1900 SDValue HiLZ = DAG.getNode(N->getOpcode(), dl, NVT, Hi);
1902 Lo = DAG.getSelect(dl, NVT, LoNotZero, LoLZ,
1903 DAG.getNode(ISD::ADD, dl, NVT, HiLZ,
1904 DAG.getConstant(NVT.getSizeInBits(), dl,
1906 Hi = DAG.getConstant(0, dl, NVT);
1909 void DAGTypeLegalizer::ExpandIntRes_FP_TO_SINT(SDNode *N, SDValue &Lo,
1912 EVT VT = N->getValueType(0);
1914 SDValue Op = N->getOperand(0);
1915 if (getTypeAction(Op.getValueType()) == TargetLowering::TypePromoteFloat)
1916 Op = GetPromotedFloat(Op);
1918 RTLIB::Libcall LC = RTLIB::getFPTOSINT(Op.getValueType(), VT);
1919 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected fp-to-sint conversion!");
1920 SplitInteger(TLI.makeLibCall(DAG, LC, VT, &Op, 1, true/*irrelevant*/,
1925 void DAGTypeLegalizer::ExpandIntRes_FP_TO_UINT(SDNode *N, SDValue &Lo,
1928 EVT VT = N->getValueType(0);
1930 SDValue Op = N->getOperand(0);
1931 if (getTypeAction(Op.getValueType()) == TargetLowering::TypePromoteFloat)
1932 Op = GetPromotedFloat(Op);
1934 RTLIB::Libcall LC = RTLIB::getFPTOUINT(Op.getValueType(), VT);
1935 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected fp-to-uint conversion!");
1936 SplitInteger(TLI.makeLibCall(DAG, LC, VT, &Op, 1, false/*irrelevant*/,
1941 void DAGTypeLegalizer::ExpandIntRes_LOAD(LoadSDNode *N,
1942 SDValue &Lo, SDValue &Hi) {
1943 if (ISD::isNormalLoad(N)) {
1944 ExpandRes_NormalLoad(N, Lo, Hi);
1948 assert(ISD::isUNINDEXEDLoad(N) && "Indexed load during type legalization!");
1950 EVT VT = N->getValueType(0);
1951 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
1952 SDValue Ch = N->getChain();
1953 SDValue Ptr = N->getBasePtr();
1954 ISD::LoadExtType ExtType = N->getExtensionType();
1955 unsigned Alignment = N->getAlignment();
1956 bool isVolatile = N->isVolatile();
1957 bool isNonTemporal = N->isNonTemporal();
1958 bool isInvariant = N->isInvariant();
1959 AAMDNodes AAInfo = N->getAAInfo();
1962 assert(NVT.isByteSized() && "Expanded type not byte sized!");
1964 if (N->getMemoryVT().bitsLE(NVT)) {
1965 EVT MemVT = N->getMemoryVT();
1967 Lo = DAG.getExtLoad(ExtType, dl, NVT, Ch, Ptr, N->getPointerInfo(),
1968 MemVT, isVolatile, isNonTemporal, isInvariant,
1971 // Remember the chain.
1972 Ch = Lo.getValue(1);
1974 if (ExtType == ISD::SEXTLOAD) {
1975 // The high part is obtained by SRA'ing all but one of the bits of the
1977 unsigned LoSize = Lo.getValueType().getSizeInBits();
1978 Hi = DAG.getNode(ISD::SRA, dl, NVT, Lo,
1979 DAG.getConstant(LoSize - 1, dl,
1980 TLI.getPointerTy(DAG.getDataLayout())));
1981 } else if (ExtType == ISD::ZEXTLOAD) {
1982 // The high part is just a zero.
1983 Hi = DAG.getConstant(0, dl, NVT);
1985 assert(ExtType == ISD::EXTLOAD && "Unknown extload!");
1986 // The high part is undefined.
1987 Hi = DAG.getUNDEF(NVT);
1989 } else if (DAG.getDataLayout().isLittleEndian()) {
1990 // Little-endian - low bits are at low addresses.
1991 Lo = DAG.getLoad(NVT, dl, Ch, Ptr, N->getPointerInfo(),
1992 isVolatile, isNonTemporal, isInvariant, Alignment,
1995 unsigned ExcessBits =
1996 N->getMemoryVT().getSizeInBits() - NVT.getSizeInBits();
1997 EVT NEVT = EVT::getIntegerVT(*DAG.getContext(), ExcessBits);
1999 // Increment the pointer to the other half.
2000 unsigned IncrementSize = NVT.getSizeInBits()/8;
2001 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
2002 DAG.getConstant(IncrementSize, dl, Ptr.getValueType()));
2003 Hi = DAG.getExtLoad(ExtType, dl, NVT, Ch, Ptr,
2004 N->getPointerInfo().getWithOffset(IncrementSize), NEVT,
2005 isVolatile, isNonTemporal, isInvariant,
2006 MinAlign(Alignment, IncrementSize), AAInfo);
2008 // Build a factor node to remember that this load is independent of the
2010 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
2013 // Big-endian - high bits are at low addresses. Favor aligned loads at
2014 // the cost of some bit-fiddling.
2015 EVT MemVT = N->getMemoryVT();
2016 unsigned EBytes = MemVT.getStoreSize();
2017 unsigned IncrementSize = NVT.getSizeInBits()/8;
2018 unsigned ExcessBits = (EBytes - IncrementSize)*8;
2020 // Load both the high bits and maybe some of the low bits.
2021 Hi = DAG.getExtLoad(ExtType, dl, NVT, Ch, Ptr, N->getPointerInfo(),
2022 EVT::getIntegerVT(*DAG.getContext(),
2023 MemVT.getSizeInBits() - ExcessBits),
2024 isVolatile, isNonTemporal, isInvariant, Alignment,
2027 // Increment the pointer to the other half.
2028 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
2029 DAG.getConstant(IncrementSize, dl, Ptr.getValueType()));
2030 // Load the rest of the low bits.
2031 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, NVT, Ch, Ptr,
2032 N->getPointerInfo().getWithOffset(IncrementSize),
2033 EVT::getIntegerVT(*DAG.getContext(), ExcessBits),
2034 isVolatile, isNonTemporal, isInvariant,
2035 MinAlign(Alignment, IncrementSize), AAInfo);
2037 // Build a factor node to remember that this load is independent of the
2039 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
2042 if (ExcessBits < NVT.getSizeInBits()) {
2043 // Transfer low bits from the bottom of Hi to the top of Lo.
2045 ISD::OR, dl, NVT, Lo,
2046 DAG.getNode(ISD::SHL, dl, NVT, Hi,
2047 DAG.getConstant(ExcessBits, dl,
2048 TLI.getPointerTy(DAG.getDataLayout()))));
2049 // Move high bits to the right position in Hi.
2050 Hi = DAG.getNode(ExtType == ISD::SEXTLOAD ? ISD::SRA : ISD::SRL, dl, NVT,
2052 DAG.getConstant(NVT.getSizeInBits() - ExcessBits, dl,
2053 TLI.getPointerTy(DAG.getDataLayout())));
2057 // Legalized the chain result - switch anything that used the old chain to
2059 ReplaceValueWith(SDValue(N, 1), Ch);
2062 void DAGTypeLegalizer::ExpandIntRes_Logical(SDNode *N,
2063 SDValue &Lo, SDValue &Hi) {
2065 SDValue LL, LH, RL, RH;
2066 GetExpandedInteger(N->getOperand(0), LL, LH);
2067 GetExpandedInteger(N->getOperand(1), RL, RH);
2068 Lo = DAG.getNode(N->getOpcode(), dl, LL.getValueType(), LL, RL);
2069 Hi = DAG.getNode(N->getOpcode(), dl, LL.getValueType(), LH, RH);
2072 void DAGTypeLegalizer::ExpandIntRes_MUL(SDNode *N,
2073 SDValue &Lo, SDValue &Hi) {
2074 EVT VT = N->getValueType(0);
2075 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
2078 SDValue LL, LH, RL, RH;
2079 GetExpandedInteger(N->getOperand(0), LL, LH);
2080 GetExpandedInteger(N->getOperand(1), RL, RH);
2082 if (TLI.expandMUL(N, Lo, Hi, NVT, DAG, LL, LH, RL, RH))
2085 // If nothing else, we can make a libcall.
2086 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
2088 LC = RTLIB::MUL_I16;
2089 else if (VT == MVT::i32)
2090 LC = RTLIB::MUL_I32;
2091 else if (VT == MVT::i64)
2092 LC = RTLIB::MUL_I64;
2093 else if (VT == MVT::i128)
2094 LC = RTLIB::MUL_I128;
2095 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported MUL!");
2097 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
2098 SplitInteger(TLI.makeLibCall(DAG, LC, VT, Ops, 2, true/*irrelevant*/,
2103 void DAGTypeLegalizer::ExpandIntRes_READCYCLECOUNTER(SDNode *N, SDValue &Lo,
2106 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2107 SDVTList VTs = DAG.getVTList(NVT, NVT, MVT::Other);
2108 SDValue R = DAG.getNode(N->getOpcode(), DL, VTs, N->getOperand(0));
2111 ReplaceValueWith(SDValue(N, 1), R.getValue(2));
2114 void DAGTypeLegalizer::ExpandIntRes_SADDSUBO(SDNode *Node,
2115 SDValue &Lo, SDValue &Hi) {
2116 SDValue LHS = Node->getOperand(0);
2117 SDValue RHS = Node->getOperand(1);
2120 // Expand the result by simply replacing it with the equivalent
2121 // non-overflow-checking operation.
2122 SDValue Sum = DAG.getNode(Node->getOpcode() == ISD::SADDO ?
2123 ISD::ADD : ISD::SUB, dl, LHS.getValueType(),
2125 SplitInteger(Sum, Lo, Hi);
2127 // Compute the overflow.
2129 // LHSSign -> LHS >= 0
2130 // RHSSign -> RHS >= 0
2131 // SumSign -> Sum >= 0
2134 // Overflow -> (LHSSign == RHSSign) && (LHSSign != SumSign)
2136 // Overflow -> (LHSSign != RHSSign) && (LHSSign != SumSign)
2138 EVT OType = Node->getValueType(1);
2139 SDValue Zero = DAG.getConstant(0, dl, LHS.getValueType());
2141 SDValue LHSSign = DAG.getSetCC(dl, OType, LHS, Zero, ISD::SETGE);
2142 SDValue RHSSign = DAG.getSetCC(dl, OType, RHS, Zero, ISD::SETGE);
2143 SDValue SignsMatch = DAG.getSetCC(dl, OType, LHSSign, RHSSign,
2144 Node->getOpcode() == ISD::SADDO ?
2145 ISD::SETEQ : ISD::SETNE);
2147 SDValue SumSign = DAG.getSetCC(dl, OType, Sum, Zero, ISD::SETGE);
2148 SDValue SumSignNE = DAG.getSetCC(dl, OType, LHSSign, SumSign, ISD::SETNE);
2150 SDValue Cmp = DAG.getNode(ISD::AND, dl, OType, SignsMatch, SumSignNE);
2152 // Use the calculated overflow everywhere.
2153 ReplaceValueWith(SDValue(Node, 1), Cmp);
2156 void DAGTypeLegalizer::ExpandIntRes_SDIV(SDNode *N,
2157 SDValue &Lo, SDValue &Hi) {
2158 EVT VT = N->getValueType(0);
2160 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
2162 if (TLI.getOperationAction(ISD::SDIVREM, VT) == TargetLowering::Custom) {
2163 SDValue Res = DAG.getNode(ISD::SDIVREM, dl, DAG.getVTList(VT, VT), Ops);
2164 SplitInteger(Res.getValue(0), Lo, Hi);
2168 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
2170 LC = RTLIB::SDIV_I16;
2171 else if (VT == MVT::i32)
2172 LC = RTLIB::SDIV_I32;
2173 else if (VT == MVT::i64)
2174 LC = RTLIB::SDIV_I64;
2175 else if (VT == MVT::i128)
2176 LC = RTLIB::SDIV_I128;
2177 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported SDIV!");
2179 SplitInteger(TLI.makeLibCall(DAG, LC, VT, Ops, 2, true, dl).first, Lo, Hi);
2182 void DAGTypeLegalizer::ExpandIntRes_Shift(SDNode *N,
2183 SDValue &Lo, SDValue &Hi) {
2184 EVT VT = N->getValueType(0);
2187 // If we can emit an efficient shift operation, do so now. Check to see if
2188 // the RHS is a constant.
2189 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N->getOperand(1)))
2190 return ExpandShiftByConstant(N, CN->getAPIntValue(), Lo, Hi);
2192 // If we can determine that the high bit of the shift is zero or one, even if
2193 // the low bits are variable, emit this shift in an optimized form.
2194 if (ExpandShiftWithKnownAmountBit(N, Lo, Hi))
2197 // If this target supports shift_PARTS, use it. First, map to the _PARTS opc.
2199 if (N->getOpcode() == ISD::SHL) {
2200 PartsOpc = ISD::SHL_PARTS;
2201 } else if (N->getOpcode() == ISD::SRL) {
2202 PartsOpc = ISD::SRL_PARTS;
2204 assert(N->getOpcode() == ISD::SRA && "Unknown shift!");
2205 PartsOpc = ISD::SRA_PARTS;
2208 // Next check to see if the target supports this SHL_PARTS operation or if it
2209 // will custom expand it.
2210 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
2211 TargetLowering::LegalizeAction Action = TLI.getOperationAction(PartsOpc, NVT);
2212 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) ||
2213 Action == TargetLowering::Custom) {
2214 // Expand the subcomponents.
2216 GetExpandedInteger(N->getOperand(0), LHSL, LHSH);
2217 EVT VT = LHSL.getValueType();
2219 // If the shift amount operand is coming from a vector legalization it may
2220 // have an illegal type. Fix that first by casting the operand, otherwise
2221 // the new SHL_PARTS operation would need further legalization.
2222 SDValue ShiftOp = N->getOperand(1);
2223 EVT ShiftTy = TLI.getShiftAmountTy(VT, DAG.getDataLayout());
2224 assert(ShiftTy.getScalarType().getSizeInBits() >=
2225 Log2_32_Ceil(VT.getScalarType().getSizeInBits()) &&
2226 "ShiftAmountTy is too small to cover the range of this type!");
2227 if (ShiftOp.getValueType() != ShiftTy)
2228 ShiftOp = DAG.getZExtOrTrunc(ShiftOp, dl, ShiftTy);
2230 SDValue Ops[] = { LHSL, LHSH, ShiftOp };
2231 Lo = DAG.getNode(PartsOpc, dl, DAG.getVTList(VT, VT), Ops);
2232 Hi = Lo.getValue(1);
2236 // Otherwise, emit a libcall.
2237 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
2239 if (N->getOpcode() == ISD::SHL) {
2240 isSigned = false; /*sign irrelevant*/
2242 LC = RTLIB::SHL_I16;
2243 else if (VT == MVT::i32)
2244 LC = RTLIB::SHL_I32;
2245 else if (VT == MVT::i64)
2246 LC = RTLIB::SHL_I64;
2247 else if (VT == MVT::i128)
2248 LC = RTLIB::SHL_I128;
2249 } else if (N->getOpcode() == ISD::SRL) {
2252 LC = RTLIB::SRL_I16;
2253 else if (VT == MVT::i32)
2254 LC = RTLIB::SRL_I32;
2255 else if (VT == MVT::i64)
2256 LC = RTLIB::SRL_I64;
2257 else if (VT == MVT::i128)
2258 LC = RTLIB::SRL_I128;
2260 assert(N->getOpcode() == ISD::SRA && "Unknown shift!");
2263 LC = RTLIB::SRA_I16;
2264 else if (VT == MVT::i32)
2265 LC = RTLIB::SRA_I32;
2266 else if (VT == MVT::i64)
2267 LC = RTLIB::SRA_I64;
2268 else if (VT == MVT::i128)
2269 LC = RTLIB::SRA_I128;
2272 if (LC != RTLIB::UNKNOWN_LIBCALL && TLI.getLibcallName(LC)) {
2273 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
2274 SplitInteger(TLI.makeLibCall(DAG, LC, VT, Ops, 2, isSigned, dl).first, Lo,
2279 if (!ExpandShiftWithUnknownAmountBit(N, Lo, Hi))
2280 llvm_unreachable("Unsupported shift!");
2283 void DAGTypeLegalizer::ExpandIntRes_SIGN_EXTEND(SDNode *N,
2284 SDValue &Lo, SDValue &Hi) {
2285 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2287 SDValue Op = N->getOperand(0);
2288 if (Op.getValueType().bitsLE(NVT)) {
2289 // The low part is sign extension of the input (degenerates to a copy).
2290 Lo = DAG.getNode(ISD::SIGN_EXTEND, dl, NVT, N->getOperand(0));
2291 // The high part is obtained by SRA'ing all but one of the bits of low part.
2292 unsigned LoSize = NVT.getSizeInBits();
2294 ISD::SRA, dl, NVT, Lo,
2295 DAG.getConstant(LoSize - 1, dl, TLI.getPointerTy(DAG.getDataLayout())));
2297 // For example, extension of an i48 to an i64. The operand type necessarily
2298 // promotes to the result type, so will end up being expanded too.
2299 assert(getTypeAction(Op.getValueType()) ==
2300 TargetLowering::TypePromoteInteger &&
2301 "Only know how to promote this result!");
2302 SDValue Res = GetPromotedInteger(Op);
2303 assert(Res.getValueType() == N->getValueType(0) &&
2304 "Operand over promoted?");
2305 // Split the promoted operand. This will simplify when it is expanded.
2306 SplitInteger(Res, Lo, Hi);
2307 unsigned ExcessBits =
2308 Op.getValueType().getSizeInBits() - NVT.getSizeInBits();
2309 Hi = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Hi.getValueType(), Hi,
2310 DAG.getValueType(EVT::getIntegerVT(*DAG.getContext(),
2315 void DAGTypeLegalizer::
2316 ExpandIntRes_SIGN_EXTEND_INREG(SDNode *N, SDValue &Lo, SDValue &Hi) {
2318 GetExpandedInteger(N->getOperand(0), Lo, Hi);
2319 EVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
2321 if (EVT.bitsLE(Lo.getValueType())) {
2322 // sext_inreg the low part if needed.
2323 Lo = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Lo.getValueType(), Lo,
2326 // The high part gets the sign extension from the lo-part. This handles
2327 // things like sextinreg V:i64 from i8.
2328 Hi = DAG.getNode(ISD::SRA, dl, Hi.getValueType(), Lo,
2329 DAG.getConstant(Hi.getValueType().getSizeInBits() - 1, dl,
2330 TLI.getPointerTy(DAG.getDataLayout())));
2332 // For example, extension of an i48 to an i64. Leave the low part alone,
2333 // sext_inreg the high part.
2334 unsigned ExcessBits =
2335 EVT.getSizeInBits() - Lo.getValueType().getSizeInBits();
2336 Hi = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Hi.getValueType(), Hi,
2337 DAG.getValueType(EVT::getIntegerVT(*DAG.getContext(),
2342 void DAGTypeLegalizer::ExpandIntRes_SREM(SDNode *N,
2343 SDValue &Lo, SDValue &Hi) {
2344 EVT VT = N->getValueType(0);
2346 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
2348 if (TLI.getOperationAction(ISD::SDIVREM, VT) == TargetLowering::Custom) {
2349 SDValue Res = DAG.getNode(ISD::SDIVREM, dl, DAG.getVTList(VT, VT), Ops);
2350 SplitInteger(Res.getValue(1), Lo, Hi);
2354 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
2356 LC = RTLIB::SREM_I16;
2357 else if (VT == MVT::i32)
2358 LC = RTLIB::SREM_I32;
2359 else if (VT == MVT::i64)
2360 LC = RTLIB::SREM_I64;
2361 else if (VT == MVT::i128)
2362 LC = RTLIB::SREM_I128;
2363 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported SREM!");
2365 SplitInteger(TLI.makeLibCall(DAG, LC, VT, Ops, 2, true, dl).first, Lo, Hi);
2368 void DAGTypeLegalizer::ExpandIntRes_TRUNCATE(SDNode *N,
2369 SDValue &Lo, SDValue &Hi) {
2370 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2372 Lo = DAG.getNode(ISD::TRUNCATE, dl, NVT, N->getOperand(0));
2373 Hi = DAG.getNode(ISD::SRL, dl, N->getOperand(0).getValueType(),
2375 DAG.getConstant(NVT.getSizeInBits(), dl,
2376 TLI.getPointerTy(DAG.getDataLayout())));
2377 Hi = DAG.getNode(ISD::TRUNCATE, dl, NVT, Hi);
2380 void DAGTypeLegalizer::ExpandIntRes_UADDSUBO(SDNode *N,
2381 SDValue &Lo, SDValue &Hi) {
2382 SDValue LHS = N->getOperand(0);
2383 SDValue RHS = N->getOperand(1);
2386 // Expand the result by simply replacing it with the equivalent
2387 // non-overflow-checking operation.
2388 SDValue Sum = DAG.getNode(N->getOpcode() == ISD::UADDO ?
2389 ISD::ADD : ISD::SUB, dl, LHS.getValueType(),
2391 SplitInteger(Sum, Lo, Hi);
2393 // Calculate the overflow: addition overflows iff a + b < a, and subtraction
2394 // overflows iff a - b > a.
2395 SDValue Ofl = DAG.getSetCC(dl, N->getValueType(1), Sum, LHS,
2396 N->getOpcode () == ISD::UADDO ?
2397 ISD::SETULT : ISD::SETUGT);
2399 // Use the calculated overflow everywhere.
2400 ReplaceValueWith(SDValue(N, 1), Ofl);
2403 void DAGTypeLegalizer::ExpandIntRes_XMULO(SDNode *N,
2404 SDValue &Lo, SDValue &Hi) {
2405 EVT VT = N->getValueType(0);
2408 // A divide for UMULO should be faster than a function call.
2409 if (N->getOpcode() == ISD::UMULO) {
2410 SDValue LHS = N->getOperand(0), RHS = N->getOperand(1);
2412 SDValue MUL = DAG.getNode(ISD::MUL, dl, LHS.getValueType(), LHS, RHS);
2413 SplitInteger(MUL, Lo, Hi);
2415 // A divide for UMULO will be faster than a function call. Select to
2416 // make sure we aren't using 0.
2417 SDValue isZero = DAG.getSetCC(dl, getSetCCResultType(VT),
2418 RHS, DAG.getConstant(0, dl, VT), ISD::SETEQ);
2419 SDValue NotZero = DAG.getSelect(dl, VT, isZero,
2420 DAG.getConstant(1, dl, VT), RHS);
2421 SDValue DIV = DAG.getNode(ISD::UDIV, dl, VT, MUL, NotZero);
2422 SDValue Overflow = DAG.getSetCC(dl, N->getValueType(1), DIV, LHS,
2424 Overflow = DAG.getSelect(dl, N->getValueType(1), isZero,
2425 DAG.getConstant(0, dl, N->getValueType(1)),
2427 ReplaceValueWith(SDValue(N, 1), Overflow);
2431 Type *RetTy = VT.getTypeForEVT(*DAG.getContext());
2432 EVT PtrVT = TLI.getPointerTy(DAG.getDataLayout());
2433 Type *PtrTy = PtrVT.getTypeForEVT(*DAG.getContext());
2435 // Replace this with a libcall that will check overflow.
2436 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
2438 LC = RTLIB::MULO_I32;
2439 else if (VT == MVT::i64)
2440 LC = RTLIB::MULO_I64;
2441 else if (VT == MVT::i128)
2442 LC = RTLIB::MULO_I128;
2443 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported XMULO!");
2445 SDValue Temp = DAG.CreateStackTemporary(PtrVT);
2446 // Temporary for the overflow value, default it to zero.
2447 SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl,
2448 DAG.getConstant(0, dl, PtrVT), Temp,
2449 MachinePointerInfo(), false, false, 0);
2451 TargetLowering::ArgListTy Args;
2452 TargetLowering::ArgListEntry Entry;
2453 for (const SDValue &Op : N->op_values()) {
2454 EVT ArgVT = Op.getValueType();
2455 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
2458 Entry.isSExt = true;
2459 Entry.isZExt = false;
2460 Args.push_back(Entry);
2463 // Also pass the address of the overflow check.
2465 Entry.Ty = PtrTy->getPointerTo();
2466 Entry.isSExt = true;
2467 Entry.isZExt = false;
2468 Args.push_back(Entry);
2470 SDValue Func = DAG.getExternalSymbol(TLI.getLibcallName(LC), PtrVT);
2472 TargetLowering::CallLoweringInfo CLI(DAG);
2473 CLI.setDebugLoc(dl).setChain(Chain)
2474 .setCallee(TLI.getLibcallCallingConv(LC), RetTy, Func, std::move(Args), 0)
2477 std::pair<SDValue, SDValue> CallInfo = TLI.LowerCallTo(CLI);
2479 SplitInteger(CallInfo.first, Lo, Hi);
2480 SDValue Temp2 = DAG.getLoad(PtrVT, dl, CallInfo.second, Temp,
2481 MachinePointerInfo(), false, false, false, 0);
2482 SDValue Ofl = DAG.getSetCC(dl, N->getValueType(1), Temp2,
2483 DAG.getConstant(0, dl, PtrVT),
2485 // Use the overflow from the libcall everywhere.
2486 ReplaceValueWith(SDValue(N, 1), Ofl);
2489 void DAGTypeLegalizer::ExpandIntRes_UDIV(SDNode *N,
2490 SDValue &Lo, SDValue &Hi) {
2491 EVT VT = N->getValueType(0);
2493 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
2495 if (TLI.getOperationAction(ISD::UDIVREM, VT) == TargetLowering::Custom) {
2496 SDValue Res = DAG.getNode(ISD::UDIVREM, dl, DAG.getVTList(VT, VT), Ops);
2497 SplitInteger(Res.getValue(0), Lo, Hi);
2501 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
2503 LC = RTLIB::UDIV_I16;
2504 else if (VT == MVT::i32)
2505 LC = RTLIB::UDIV_I32;
2506 else if (VT == MVT::i64)
2507 LC = RTLIB::UDIV_I64;
2508 else if (VT == MVT::i128)
2509 LC = RTLIB::UDIV_I128;
2510 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported UDIV!");
2512 SplitInteger(TLI.makeLibCall(DAG, LC, VT, Ops, 2, false, dl).first, Lo, Hi);
2515 void DAGTypeLegalizer::ExpandIntRes_UREM(SDNode *N,
2516 SDValue &Lo, SDValue &Hi) {
2517 EVT VT = N->getValueType(0);
2519 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
2521 if (TLI.getOperationAction(ISD::UDIVREM, VT) == TargetLowering::Custom) {
2522 SDValue Res = DAG.getNode(ISD::UDIVREM, dl, DAG.getVTList(VT, VT), Ops);
2523 SplitInteger(Res.getValue(1), Lo, Hi);
2527 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
2529 LC = RTLIB::UREM_I16;
2530 else if (VT == MVT::i32)
2531 LC = RTLIB::UREM_I32;
2532 else if (VT == MVT::i64)
2533 LC = RTLIB::UREM_I64;
2534 else if (VT == MVT::i128)
2535 LC = RTLIB::UREM_I128;
2536 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported UREM!");
2538 SplitInteger(TLI.makeLibCall(DAG, LC, VT, Ops, 2, false, dl).first, Lo, Hi);
2541 void DAGTypeLegalizer::ExpandIntRes_ZERO_EXTEND(SDNode *N,
2542 SDValue &Lo, SDValue &Hi) {
2543 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2545 SDValue Op = N->getOperand(0);
2546 if (Op.getValueType().bitsLE(NVT)) {
2547 // The low part is zero extension of the input (degenerates to a copy).
2548 Lo = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, N->getOperand(0));
2549 Hi = DAG.getConstant(0, dl, NVT); // The high part is just a zero.
2551 // For example, extension of an i48 to an i64. The operand type necessarily
2552 // promotes to the result type, so will end up being expanded too.
2553 assert(getTypeAction(Op.getValueType()) ==
2554 TargetLowering::TypePromoteInteger &&
2555 "Only know how to promote this result!");
2556 SDValue Res = GetPromotedInteger(Op);
2557 assert(Res.getValueType() == N->getValueType(0) &&
2558 "Operand over promoted?");
2559 // Split the promoted operand. This will simplify when it is expanded.
2560 SplitInteger(Res, Lo, Hi);
2561 unsigned ExcessBits =
2562 Op.getValueType().getSizeInBits() - NVT.getSizeInBits();
2563 Hi = DAG.getZeroExtendInReg(Hi, dl,
2564 EVT::getIntegerVT(*DAG.getContext(),
2569 void DAGTypeLegalizer::ExpandIntRes_ATOMIC_LOAD(SDNode *N,
2570 SDValue &Lo, SDValue &Hi) {
2572 EVT VT = cast<AtomicSDNode>(N)->getMemoryVT();
2573 SDVTList VTs = DAG.getVTList(VT, MVT::i1, MVT::Other);
2574 SDValue Zero = DAG.getConstant(0, dl, VT);
2575 SDValue Swap = DAG.getAtomicCmpSwap(
2576 ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, dl,
2577 cast<AtomicSDNode>(N)->getMemoryVT(), VTs, N->getOperand(0),
2578 N->getOperand(1), Zero, Zero, cast<AtomicSDNode>(N)->getMemOperand(),
2579 cast<AtomicSDNode>(N)->getOrdering(),
2580 cast<AtomicSDNode>(N)->getOrdering(),
2581 cast<AtomicSDNode>(N)->getSynchScope());
2583 ReplaceValueWith(SDValue(N, 0), Swap.getValue(0));
2584 ReplaceValueWith(SDValue(N, 1), Swap.getValue(2));
2587 //===----------------------------------------------------------------------===//
2588 // Integer Operand Expansion
2589 //===----------------------------------------------------------------------===//
2591 /// ExpandIntegerOperand - This method is called when the specified operand of
2592 /// the specified node is found to need expansion. At this point, all of the
2593 /// result types of the node are known to be legal, but other operands of the
2594 /// node may need promotion or expansion as well as the specified one.
2595 bool DAGTypeLegalizer::ExpandIntegerOperand(SDNode *N, unsigned OpNo) {
2596 DEBUG(dbgs() << "Expand integer operand: "; N->dump(&DAG); dbgs() << "\n");
2597 SDValue Res = SDValue();
2599 if (CustomLowerNode(N, N->getOperand(OpNo).getValueType(), false))
2602 switch (N->getOpcode()) {
2605 dbgs() << "ExpandIntegerOperand Op #" << OpNo << ": ";
2606 N->dump(&DAG); dbgs() << "\n";
2608 llvm_unreachable("Do not know how to expand this operator's operand!");
2610 case ISD::BITCAST: Res = ExpandOp_BITCAST(N); break;
2611 case ISD::BR_CC: Res = ExpandIntOp_BR_CC(N); break;
2612 case ISD::BUILD_VECTOR: Res = ExpandOp_BUILD_VECTOR(N); break;
2613 case ISD::EXTRACT_ELEMENT: Res = ExpandOp_EXTRACT_ELEMENT(N); break;
2614 case ISD::INSERT_VECTOR_ELT: Res = ExpandOp_INSERT_VECTOR_ELT(N); break;
2615 case ISD::SCALAR_TO_VECTOR: Res = ExpandOp_SCALAR_TO_VECTOR(N); break;
2616 case ISD::SELECT_CC: Res = ExpandIntOp_SELECT_CC(N); break;
2617 case ISD::SETCC: Res = ExpandIntOp_SETCC(N); break;
2618 case ISD::SINT_TO_FP: Res = ExpandIntOp_SINT_TO_FP(N); break;
2619 case ISD::STORE: Res = ExpandIntOp_STORE(cast<StoreSDNode>(N), OpNo); break;
2620 case ISD::TRUNCATE: Res = ExpandIntOp_TRUNCATE(N); break;
2621 case ISD::UINT_TO_FP: Res = ExpandIntOp_UINT_TO_FP(N); break;
2627 case ISD::ROTR: Res = ExpandIntOp_Shift(N); break;
2628 case ISD::RETURNADDR:
2629 case ISD::FRAMEADDR: Res = ExpandIntOp_RETURNADDR(N); break;
2631 case ISD::ATOMIC_STORE: Res = ExpandIntOp_ATOMIC_STORE(N); break;
2634 // If the result is null, the sub-method took care of registering results etc.
2635 if (!Res.getNode()) return false;
2637 // If the result is N, the sub-method updated N in place. Tell the legalizer
2639 if (Res.getNode() == N)
2642 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 &&
2643 "Invalid operand expansion");
2645 ReplaceValueWith(SDValue(N, 0), Res);
2649 /// IntegerExpandSetCCOperands - Expand the operands of a comparison. This code
2650 /// is shared among BR_CC, SELECT_CC, and SETCC handlers.
2651 void DAGTypeLegalizer::IntegerExpandSetCCOperands(SDValue &NewLHS,
2653 ISD::CondCode &CCCode,
2655 SDValue LHSLo, LHSHi, RHSLo, RHSHi;
2656 GetExpandedInteger(NewLHS, LHSLo, LHSHi);
2657 GetExpandedInteger(NewRHS, RHSLo, RHSHi);
2659 if (CCCode == ISD::SETEQ || CCCode == ISD::SETNE) {
2660 if (RHSLo == RHSHi) {
2661 if (ConstantSDNode *RHSCST = dyn_cast<ConstantSDNode>(RHSLo)) {
2662 if (RHSCST->isAllOnesValue()) {
2663 // Equality comparison to -1.
2664 NewLHS = DAG.getNode(ISD::AND, dl,
2665 LHSLo.getValueType(), LHSLo, LHSHi);
2672 NewLHS = DAG.getNode(ISD::XOR, dl, LHSLo.getValueType(), LHSLo, RHSLo);
2673 NewRHS = DAG.getNode(ISD::XOR, dl, LHSLo.getValueType(), LHSHi, RHSHi);
2674 NewLHS = DAG.getNode(ISD::OR, dl, NewLHS.getValueType(), NewLHS, NewRHS);
2675 NewRHS = DAG.getConstant(0, dl, NewLHS.getValueType());
2679 // If this is a comparison of the sign bit, just look at the top part.
2681 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(NewRHS))
2682 if ((CCCode == ISD::SETLT && CST->isNullValue()) || // X < 0
2683 (CCCode == ISD::SETGT && CST->isAllOnesValue())) { // X > -1
2689 // FIXME: This generated code sucks.
2690 ISD::CondCode LowCC;
2692 default: llvm_unreachable("Unknown integer setcc!");
2694 case ISD::SETULT: LowCC = ISD::SETULT; break;
2696 case ISD::SETUGT: LowCC = ISD::SETUGT; break;
2698 case ISD::SETULE: LowCC = ISD::SETULE; break;
2700 case ISD::SETUGE: LowCC = ISD::SETUGE; break;
2703 // Tmp1 = lo(op1) < lo(op2) // Always unsigned comparison
2704 // Tmp2 = hi(op1) < hi(op2) // Signedness depends on operands
2705 // dest = hi(op1) == hi(op2) ? Tmp1 : Tmp2;
2707 // NOTE: on targets without efficient SELECT of bools, we can always use
2708 // this identity: (B1 ? B2 : B3) --> (B1 & B2)|(!B1&B3)
2709 TargetLowering::DAGCombinerInfo DagCombineInfo(DAG, AfterLegalizeTypes, true,
2712 if (TLI.isTypeLegal(LHSLo.getValueType()) &&
2713 TLI.isTypeLegal(RHSLo.getValueType()))
2714 Tmp1 = TLI.SimplifySetCC(getSetCCResultType(LHSLo.getValueType()),
2715 LHSLo, RHSLo, LowCC, false, DagCombineInfo, dl);
2716 if (!Tmp1.getNode())
2717 Tmp1 = DAG.getSetCC(dl, getSetCCResultType(LHSLo.getValueType()),
2718 LHSLo, RHSLo, LowCC);
2719 if (TLI.isTypeLegal(LHSHi.getValueType()) &&
2720 TLI.isTypeLegal(RHSHi.getValueType()))
2721 Tmp2 = TLI.SimplifySetCC(getSetCCResultType(LHSHi.getValueType()),
2722 LHSHi, RHSHi, CCCode, false, DagCombineInfo, dl);
2723 if (!Tmp2.getNode())
2724 Tmp2 = DAG.getNode(ISD::SETCC, dl,
2725 getSetCCResultType(LHSHi.getValueType()),
2726 LHSHi, RHSHi, DAG.getCondCode(CCCode));
2728 ConstantSDNode *Tmp1C = dyn_cast<ConstantSDNode>(Tmp1.getNode());
2729 ConstantSDNode *Tmp2C = dyn_cast<ConstantSDNode>(Tmp2.getNode());
2730 if ((Tmp1C && Tmp1C->isNullValue()) ||
2731 (Tmp2C && Tmp2C->isNullValue() &&
2732 (CCCode == ISD::SETLE || CCCode == ISD::SETGE ||
2733 CCCode == ISD::SETUGE || CCCode == ISD::SETULE)) ||
2734 (Tmp2C && Tmp2C->getAPIntValue() == 1 &&
2735 (CCCode == ISD::SETLT || CCCode == ISD::SETGT ||
2736 CCCode == ISD::SETUGT || CCCode == ISD::SETULT))) {
2737 // low part is known false, returns high part.
2738 // For LE / GE, if high part is known false, ignore the low part.
2739 // For LT / GT, if high part is known true, ignore the low part.
2745 NewLHS = TLI.SimplifySetCC(getSetCCResultType(LHSHi.getValueType()),
2746 LHSHi, RHSHi, ISD::SETEQ, false,
2747 DagCombineInfo, dl);
2748 if (!NewLHS.getNode())
2749 NewLHS = DAG.getSetCC(dl, getSetCCResultType(LHSHi.getValueType()),
2750 LHSHi, RHSHi, ISD::SETEQ);
2751 NewLHS = DAG.getSelect(dl, Tmp1.getValueType(),
2752 NewLHS, Tmp1, Tmp2);
2756 SDValue DAGTypeLegalizer::ExpandIntOp_BR_CC(SDNode *N) {
2757 SDValue NewLHS = N->getOperand(2), NewRHS = N->getOperand(3);
2758 ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(1))->get();
2759 IntegerExpandSetCCOperands(NewLHS, NewRHS, CCCode, SDLoc(N));
2761 // If ExpandSetCCOperands returned a scalar, we need to compare the result
2762 // against zero to select between true and false values.
2763 if (!NewRHS.getNode()) {
2764 NewRHS = DAG.getConstant(0, SDLoc(N), NewLHS.getValueType());
2765 CCCode = ISD::SETNE;
2768 // Update N to have the operands specified.
2769 return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0),
2770 DAG.getCondCode(CCCode), NewLHS, NewRHS,
2771 N->getOperand(4)), 0);
2774 SDValue DAGTypeLegalizer::ExpandIntOp_SELECT_CC(SDNode *N) {
2775 SDValue NewLHS = N->getOperand(0), NewRHS = N->getOperand(1);
2776 ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(4))->get();
2777 IntegerExpandSetCCOperands(NewLHS, NewRHS, CCCode, SDLoc(N));
2779 // If ExpandSetCCOperands returned a scalar, we need to compare the result
2780 // against zero to select between true and false values.
2781 if (!NewRHS.getNode()) {
2782 NewRHS = DAG.getConstant(0, SDLoc(N), NewLHS.getValueType());
2783 CCCode = ISD::SETNE;
2786 // Update N to have the operands specified.
2787 return SDValue(DAG.UpdateNodeOperands(N, NewLHS, NewRHS,
2788 N->getOperand(2), N->getOperand(3),
2789 DAG.getCondCode(CCCode)), 0);
2792 SDValue DAGTypeLegalizer::ExpandIntOp_SETCC(SDNode *N) {
2793 SDValue NewLHS = N->getOperand(0), NewRHS = N->getOperand(1);
2794 ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(2))->get();
2795 IntegerExpandSetCCOperands(NewLHS, NewRHS, CCCode, SDLoc(N));
2797 // If ExpandSetCCOperands returned a scalar, use it.
2798 if (!NewRHS.getNode()) {
2799 assert(NewLHS.getValueType() == N->getValueType(0) &&
2800 "Unexpected setcc expansion!");
2804 // Otherwise, update N to have the operands specified.
2805 return SDValue(DAG.UpdateNodeOperands(N, NewLHS, NewRHS,
2806 DAG.getCondCode(CCCode)), 0);
2809 SDValue DAGTypeLegalizer::ExpandIntOp_Shift(SDNode *N) {
2810 // The value being shifted is legal, but the shift amount is too big.
2811 // It follows that either the result of the shift is undefined, or the
2812 // upper half of the shift amount is zero. Just use the lower half.
2814 GetExpandedInteger(N->getOperand(1), Lo, Hi);
2815 return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0), Lo), 0);
2818 SDValue DAGTypeLegalizer::ExpandIntOp_RETURNADDR(SDNode *N) {
2819 // The argument of RETURNADDR / FRAMEADDR builtin is 32 bit contant. This
2820 // surely makes pretty nice problems on 8/16 bit targets. Just truncate this
2821 // constant to valid type.
2823 GetExpandedInteger(N->getOperand(0), Lo, Hi);
2824 return SDValue(DAG.UpdateNodeOperands(N, Lo), 0);
2827 SDValue DAGTypeLegalizer::ExpandIntOp_SINT_TO_FP(SDNode *N) {
2828 SDValue Op = N->getOperand(0);
2829 EVT DstVT = N->getValueType(0);
2830 RTLIB::Libcall LC = RTLIB::getSINTTOFP(Op.getValueType(), DstVT);
2831 assert(LC != RTLIB::UNKNOWN_LIBCALL &&
2832 "Don't know how to expand this SINT_TO_FP!");
2833 return TLI.makeLibCall(DAG, LC, DstVT, &Op, 1, true, SDLoc(N)).first;
2836 SDValue DAGTypeLegalizer::ExpandIntOp_STORE(StoreSDNode *N, unsigned OpNo) {
2837 if (ISD::isNormalStore(N))
2838 return ExpandOp_NormalStore(N, OpNo);
2840 assert(ISD::isUNINDEXEDStore(N) && "Indexed store during type legalization!");
2841 assert(OpNo == 1 && "Can only expand the stored value so far");
2843 EVT VT = N->getOperand(1).getValueType();
2844 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
2845 SDValue Ch = N->getChain();
2846 SDValue Ptr = N->getBasePtr();
2847 unsigned Alignment = N->getAlignment();
2848 bool isVolatile = N->isVolatile();
2849 bool isNonTemporal = N->isNonTemporal();
2850 AAMDNodes AAInfo = N->getAAInfo();
2854 assert(NVT.isByteSized() && "Expanded type not byte sized!");
2856 if (N->getMemoryVT().bitsLE(NVT)) {
2857 GetExpandedInteger(N->getValue(), Lo, Hi);
2858 return DAG.getTruncStore(Ch, dl, Lo, Ptr, N->getPointerInfo(),
2859 N->getMemoryVT(), isVolatile, isNonTemporal,
2863 if (DAG.getDataLayout().isLittleEndian()) {
2864 // Little-endian - low bits are at low addresses.
2865 GetExpandedInteger(N->getValue(), Lo, Hi);
2867 Lo = DAG.getStore(Ch, dl, Lo, Ptr, N->getPointerInfo(),
2868 isVolatile, isNonTemporal, Alignment, AAInfo);
2870 unsigned ExcessBits =
2871 N->getMemoryVT().getSizeInBits() - NVT.getSizeInBits();
2872 EVT NEVT = EVT::getIntegerVT(*DAG.getContext(), ExcessBits);
2874 // Increment the pointer to the other half.
2875 unsigned IncrementSize = NVT.getSizeInBits()/8;
2876 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
2877 DAG.getConstant(IncrementSize, dl, Ptr.getValueType()));
2878 Hi = DAG.getTruncStore(Ch, dl, Hi, Ptr,
2879 N->getPointerInfo().getWithOffset(IncrementSize),
2880 NEVT, isVolatile, isNonTemporal,
2881 MinAlign(Alignment, IncrementSize), AAInfo);
2882 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi);
2885 // Big-endian - high bits are at low addresses. Favor aligned stores at
2886 // the cost of some bit-fiddling.
2887 GetExpandedInteger(N->getValue(), Lo, Hi);
2889 EVT ExtVT = N->getMemoryVT();
2890 unsigned EBytes = ExtVT.getStoreSize();
2891 unsigned IncrementSize = NVT.getSizeInBits()/8;
2892 unsigned ExcessBits = (EBytes - IncrementSize)*8;
2893 EVT HiVT = EVT::getIntegerVT(*DAG.getContext(),
2894 ExtVT.getSizeInBits() - ExcessBits);
2896 if (ExcessBits < NVT.getSizeInBits()) {
2897 // Transfer high bits from the top of Lo to the bottom of Hi.
2898 Hi = DAG.getNode(ISD::SHL, dl, NVT, Hi,
2899 DAG.getConstant(NVT.getSizeInBits() - ExcessBits, dl,
2900 TLI.getPointerTy(DAG.getDataLayout())));
2902 ISD::OR, dl, NVT, Hi,
2903 DAG.getNode(ISD::SRL, dl, NVT, Lo,
2904 DAG.getConstant(ExcessBits, dl,
2905 TLI.getPointerTy(DAG.getDataLayout()))));
2908 // Store both the high bits and maybe some of the low bits.
2909 Hi = DAG.getTruncStore(Ch, dl, Hi, Ptr, N->getPointerInfo(),
2910 HiVT, isVolatile, isNonTemporal, Alignment, AAInfo);
2912 // Increment the pointer to the other half.
2913 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
2914 DAG.getConstant(IncrementSize, dl, Ptr.getValueType()));
2915 // Store the lowest ExcessBits bits in the second half.
2916 Lo = DAG.getTruncStore(Ch, dl, Lo, Ptr,
2917 N->getPointerInfo().getWithOffset(IncrementSize),
2918 EVT::getIntegerVT(*DAG.getContext(), ExcessBits),
2919 isVolatile, isNonTemporal,
2920 MinAlign(Alignment, IncrementSize), AAInfo);
2921 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi);
2924 SDValue DAGTypeLegalizer::ExpandIntOp_TRUNCATE(SDNode *N) {
2926 GetExpandedInteger(N->getOperand(0), InL, InH);
2927 // Just truncate the low part of the source.
2928 return DAG.getNode(ISD::TRUNCATE, SDLoc(N), N->getValueType(0), InL);
2931 SDValue DAGTypeLegalizer::ExpandIntOp_UINT_TO_FP(SDNode *N) {
2932 SDValue Op = N->getOperand(0);
2933 EVT SrcVT = Op.getValueType();
2934 EVT DstVT = N->getValueType(0);
2937 // The following optimization is valid only if every value in SrcVT (when
2938 // treated as signed) is representable in DstVT. Check that the mantissa
2939 // size of DstVT is >= than the number of bits in SrcVT -1.
2940 const fltSemantics &sem = DAG.EVTToAPFloatSemantics(DstVT);
2941 if (APFloat::semanticsPrecision(sem) >= SrcVT.getSizeInBits()-1 &&
2942 TLI.getOperationAction(ISD::SINT_TO_FP, SrcVT) == TargetLowering::Custom){
2943 // Do a signed conversion then adjust the result.
2944 SDValue SignedConv = DAG.getNode(ISD::SINT_TO_FP, dl, DstVT, Op);
2945 SignedConv = TLI.LowerOperation(SignedConv, DAG);
2947 // The result of the signed conversion needs adjusting if the 'sign bit' of
2948 // the incoming integer was set. To handle this, we dynamically test to see
2949 // if it is set, and, if so, add a fudge factor.
2951 const uint64_t F32TwoE32 = 0x4F800000ULL;
2952 const uint64_t F32TwoE64 = 0x5F800000ULL;
2953 const uint64_t F32TwoE128 = 0x7F800000ULL;
2956 if (SrcVT == MVT::i32)
2957 FF = APInt(32, F32TwoE32);
2958 else if (SrcVT == MVT::i64)
2959 FF = APInt(32, F32TwoE64);
2960 else if (SrcVT == MVT::i128)
2961 FF = APInt(32, F32TwoE128);
2963 llvm_unreachable("Unsupported UINT_TO_FP!");
2965 // Check whether the sign bit is set.
2967 GetExpandedInteger(Op, Lo, Hi);
2968 SDValue SignSet = DAG.getSetCC(dl,
2969 getSetCCResultType(Hi.getValueType()),
2971 DAG.getConstant(0, dl, Hi.getValueType()),
2974 // Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits.
2976 DAG.getConstantPool(ConstantInt::get(*DAG.getContext(), FF.zext(64)),
2977 TLI.getPointerTy(DAG.getDataLayout()));
2979 // Get a pointer to FF if the sign bit was set, or to 0 otherwise.
2980 SDValue Zero = DAG.getIntPtrConstant(0, dl);
2981 SDValue Four = DAG.getIntPtrConstant(4, dl);
2982 if (DAG.getDataLayout().isBigEndian())
2983 std::swap(Zero, Four);
2984 SDValue Offset = DAG.getSelect(dl, Zero.getValueType(), SignSet,
2986 unsigned Alignment = cast<ConstantPoolSDNode>(FudgePtr)->getAlignment();
2987 FudgePtr = DAG.getNode(ISD::ADD, dl, FudgePtr.getValueType(),
2989 Alignment = std::min(Alignment, 4u);
2991 // Load the value out, extending it from f32 to the destination float type.
2992 // FIXME: Avoid the extend by constructing the right constant pool?
2993 SDValue Fudge = DAG.getExtLoad(
2994 ISD::EXTLOAD, dl, DstVT, DAG.getEntryNode(), FudgePtr,
2995 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()), MVT::f32,
2996 false, false, false, Alignment);
2997 return DAG.getNode(ISD::FADD, dl, DstVT, SignedConv, Fudge);
3000 // Otherwise, use a libcall.
3001 RTLIB::Libcall LC = RTLIB::getUINTTOFP(SrcVT, DstVT);
3002 assert(LC != RTLIB::UNKNOWN_LIBCALL &&
3003 "Don't know how to expand this UINT_TO_FP!");
3004 return TLI.makeLibCall(DAG, LC, DstVT, &Op, 1, true, dl).first;
3007 SDValue DAGTypeLegalizer::ExpandIntOp_ATOMIC_STORE(SDNode *N) {
3009 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_SWAP, dl,
3010 cast<AtomicSDNode>(N)->getMemoryVT(),
3012 N->getOperand(1), N->getOperand(2),
3013 cast<AtomicSDNode>(N)->getMemOperand(),
3014 cast<AtomicSDNode>(N)->getOrdering(),
3015 cast<AtomicSDNode>(N)->getSynchScope());
3016 return Swap.getValue(1);
3020 SDValue DAGTypeLegalizer::PromoteIntRes_EXTRACT_SUBVECTOR(SDNode *N) {
3021 SDValue InOp0 = N->getOperand(0);
3022 EVT InVT = InOp0.getValueType();
3024 EVT OutVT = N->getValueType(0);
3025 EVT NOutVT = TLI.getTypeToTransformTo(*DAG.getContext(), OutVT);
3026 assert(NOutVT.isVector() && "This type must be promoted to a vector type");
3027 unsigned OutNumElems = OutVT.getVectorNumElements();
3028 EVT NOutVTElem = NOutVT.getVectorElementType();
3031 SDValue BaseIdx = N->getOperand(1);
3033 SmallVector<SDValue, 8> Ops;
3034 Ops.reserve(OutNumElems);
3035 for (unsigned i = 0; i != OutNumElems; ++i) {
3037 // Extract the element from the original vector.
3038 SDValue Index = DAG.getNode(ISD::ADD, dl, BaseIdx.getValueType(),
3039 BaseIdx, DAG.getConstant(i, dl, BaseIdx.getValueType()));
3040 SDValue Ext = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
3041 InVT.getVectorElementType(), N->getOperand(0), Index);
3043 SDValue Op = DAG.getNode(ISD::ANY_EXTEND, dl, NOutVTElem, Ext);
3044 // Insert the converted element to the new vector.
3048 return DAG.getNode(ISD::BUILD_VECTOR, dl, NOutVT, Ops);
3052 SDValue DAGTypeLegalizer::PromoteIntRes_VECTOR_SHUFFLE(SDNode *N) {
3053 ShuffleVectorSDNode *SV = cast<ShuffleVectorSDNode>(N);
3054 EVT VT = N->getValueType(0);
3057 ArrayRef<int> NewMask = SV->getMask().slice(0, VT.getVectorNumElements());
3059 SDValue V0 = GetPromotedInteger(N->getOperand(0));
3060 SDValue V1 = GetPromotedInteger(N->getOperand(1));
3061 EVT OutVT = V0.getValueType();
3063 return DAG.getVectorShuffle(OutVT, dl, V0, V1, NewMask);
3067 SDValue DAGTypeLegalizer::PromoteIntRes_BUILD_VECTOR(SDNode *N) {
3068 EVT OutVT = N->getValueType(0);
3069 EVT NOutVT = TLI.getTypeToTransformTo(*DAG.getContext(), OutVT);
3070 assert(NOutVT.isVector() && "This type must be promoted to a vector type");
3071 unsigned NumElems = N->getNumOperands();
3072 EVT NOutVTElem = NOutVT.getVectorElementType();
3076 SmallVector<SDValue, 8> Ops;
3077 Ops.reserve(NumElems);
3078 for (unsigned i = 0; i != NumElems; ++i) {
3080 // BUILD_VECTOR integer operand types are allowed to be larger than the
3081 // result's element type. This may still be true after the promotion. For
3082 // example, we might be promoting (<v?i1> = BV <i32>, <i32>, ...) to
3083 // (v?i16 = BV <i32>, <i32>, ...), and we can't any_extend <i32> to <i16>.
3084 if (N->getOperand(i).getValueType().bitsLT(NOutVTElem))
3085 Op = DAG.getNode(ISD::ANY_EXTEND, dl, NOutVTElem, N->getOperand(i));
3087 Op = N->getOperand(i);
3091 return DAG.getNode(ISD::BUILD_VECTOR, dl, NOutVT, Ops);
3094 SDValue DAGTypeLegalizer::PromoteIntRes_SCALAR_TO_VECTOR(SDNode *N) {
3098 assert(!N->getOperand(0).getValueType().isVector() &&
3099 "Input must be a scalar");
3101 EVT OutVT = N->getValueType(0);
3102 EVT NOutVT = TLI.getTypeToTransformTo(*DAG.getContext(), OutVT);
3103 assert(NOutVT.isVector() && "This type must be promoted to a vector type");
3104 EVT NOutVTElem = NOutVT.getVectorElementType();
3106 SDValue Op = DAG.getNode(ISD::ANY_EXTEND, dl, NOutVTElem, N->getOperand(0));
3108 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, NOutVT, Op);
3111 SDValue DAGTypeLegalizer::PromoteIntRes_CONCAT_VECTORS(SDNode *N) {
3114 EVT OutVT = N->getValueType(0);
3115 EVT NOutVT = TLI.getTypeToTransformTo(*DAG.getContext(), OutVT);
3116 assert(NOutVT.isVector() && "This type must be promoted to a vector type");
3118 EVT InElemTy = OutVT.getVectorElementType();
3119 EVT OutElemTy = NOutVT.getVectorElementType();
3121 unsigned NumElem = N->getOperand(0).getValueType().getVectorNumElements();
3122 unsigned NumOutElem = NOutVT.getVectorNumElements();
3123 unsigned NumOperands = N->getNumOperands();
3124 assert(NumElem * NumOperands == NumOutElem &&
3125 "Unexpected number of elements");
3127 // Take the elements from the first vector.
3128 SmallVector<SDValue, 8> Ops(NumOutElem);
3129 for (unsigned i = 0; i < NumOperands; ++i) {
3130 SDValue Op = N->getOperand(i);
3131 for (unsigned j = 0; j < NumElem; ++j) {
3132 SDValue Ext = DAG.getNode(
3133 ISD::EXTRACT_VECTOR_ELT, dl, InElemTy, Op,
3134 DAG.getConstant(j, dl, TLI.getVectorIdxTy(DAG.getDataLayout())));
3135 Ops[i * NumElem + j] = DAG.getNode(ISD::ANY_EXTEND, dl, OutElemTy, Ext);
3139 return DAG.getNode(ISD::BUILD_VECTOR, dl, NOutVT, Ops);
3142 SDValue DAGTypeLegalizer::PromoteIntRes_INSERT_VECTOR_ELT(SDNode *N) {
3143 EVT OutVT = N->getValueType(0);
3144 EVT NOutVT = TLI.getTypeToTransformTo(*DAG.getContext(), OutVT);
3145 assert(NOutVT.isVector() && "This type must be promoted to a vector type");
3147 EVT NOutVTElem = NOutVT.getVectorElementType();
3150 SDValue V0 = GetPromotedInteger(N->getOperand(0));
3152 SDValue ConvElem = DAG.getNode(ISD::ANY_EXTEND, dl,
3153 NOutVTElem, N->getOperand(1));
3154 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, NOutVT,
3155 V0, ConvElem, N->getOperand(2));
3158 SDValue DAGTypeLegalizer::PromoteIntOp_EXTRACT_VECTOR_ELT(SDNode *N) {
3160 SDValue V0 = GetPromotedInteger(N->getOperand(0));
3161 SDValue V1 = DAG.getZExtOrTrunc(N->getOperand(1), dl,
3162 TLI.getVectorIdxTy(DAG.getDataLayout()));
3163 SDValue Ext = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
3164 V0->getValueType(0).getScalarType(), V0, V1);
3166 // EXTRACT_VECTOR_ELT can return types which are wider than the incoming
3167 // element types. If this is the case then we need to expand the outgoing
3168 // value and not truncate it.
3169 return DAG.getAnyExtOrTrunc(Ext, dl, N->getValueType(0));
3172 SDValue DAGTypeLegalizer::PromoteIntOp_EXTRACT_SUBVECTOR(SDNode *N) {
3174 SDValue V0 = GetPromotedInteger(N->getOperand(0));
3175 MVT InVT = V0.getValueType().getSimpleVT();
3176 MVT OutVT = MVT::getVectorVT(InVT.getVectorElementType(),
3177 N->getValueType(0).getVectorNumElements());
3178 SDValue Ext = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, OutVT, V0, N->getOperand(1));
3179 return DAG.getNode(ISD::TRUNCATE, dl, N->getValueType(0), Ext);
3182 SDValue DAGTypeLegalizer::PromoteIntOp_CONCAT_VECTORS(SDNode *N) {
3184 unsigned NumElems = N->getNumOperands();
3186 EVT RetSclrTy = N->getValueType(0).getVectorElementType();
3188 SmallVector<SDValue, 8> NewOps;
3189 NewOps.reserve(NumElems);
3191 // For each incoming vector
3192 for (unsigned VecIdx = 0; VecIdx != NumElems; ++VecIdx) {
3193 SDValue Incoming = GetPromotedInteger(N->getOperand(VecIdx));
3194 EVT SclrTy = Incoming->getValueType(0).getVectorElementType();
3195 unsigned NumElem = Incoming->getValueType(0).getVectorNumElements();
3197 for (unsigned i=0; i<NumElem; ++i) {
3198 // Extract element from incoming vector
3199 SDValue Ex = DAG.getNode(
3200 ISD::EXTRACT_VECTOR_ELT, dl, SclrTy, Incoming,
3201 DAG.getConstant(i, dl, TLI.getVectorIdxTy(DAG.getDataLayout())));
3202 SDValue Tr = DAG.getNode(ISD::TRUNCATE, dl, RetSclrTy, Ex);
3203 NewOps.push_back(Tr);
3207 return DAG.getNode(ISD::BUILD_VECTOR, dl, N->getValueType(0), NewOps);