1 //===-- LegalizeDAG.cpp - Implement SelectionDAG::Legalize ----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the SelectionDAG::Legalize method.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/CodeGen/SelectionDAG.h"
15 #include "llvm/CodeGen/MachineFunction.h"
16 #include "llvm/CodeGen/MachineFrameInfo.h"
17 #include "llvm/Support/MathExtras.h"
18 #include "llvm/Target/TargetLowering.h"
19 #include "llvm/Target/TargetData.h"
20 #include "llvm/Target/TargetOptions.h"
21 #include "llvm/CallingConv.h"
22 #include "llvm/Constants.h"
27 //===----------------------------------------------------------------------===//
28 /// SelectionDAGLegalize - This takes an arbitrary SelectionDAG as input and
29 /// hacks on it until the target machine can handle it. This involves
30 /// eliminating value sizes the machine cannot handle (promoting small sizes to
31 /// large sizes or splitting up large values into small values) as well as
32 /// eliminating operations the machine cannot handle.
34 /// This code also does a small amount of optimization and recognition of idioms
35 /// as part of its processing. For example, if a target does not support a
36 /// 'setcc' instruction efficiently, but does support 'brcc' instruction, this
37 /// will attempt merge setcc and brc instructions into brcc's.
40 class SelectionDAGLegalize {
44 /// LegalizeAction - This enum indicates what action we should take for each
45 /// value type the can occur in the program.
47 Legal, // The target natively supports this value type.
48 Promote, // This should be promoted to the next larger type.
49 Expand, // This integer type should be broken into smaller pieces.
52 /// ValueTypeActions - This is a bitvector that contains two bits for each
53 /// value type, where the two bits correspond to the LegalizeAction enum.
54 /// This can be queried with "getTypeAction(VT)".
55 unsigned long long ValueTypeActions;
57 /// NeedsAnotherIteration - This is set when we expand a large integer
58 /// operation into smaller integer operations, but the smaller operations are
59 /// not set. This occurs only rarely in practice, for targets that don't have
60 /// 32-bit or larger integer registers.
61 bool NeedsAnotherIteration;
63 /// LegalizedNodes - For nodes that are of legal width, and that have more
64 /// than one use, this map indicates what regularized operand to use. This
65 /// allows us to avoid legalizing the same thing more than once.
66 std::map<SDOperand, SDOperand> LegalizedNodes;
68 /// PromotedNodes - For nodes that are below legal width, and that have more
69 /// than one use, this map indicates what promoted value to use. This allows
70 /// us to avoid promoting the same thing more than once.
71 std::map<SDOperand, SDOperand> PromotedNodes;
73 /// ExpandedNodes - For nodes that need to be expanded, and which have more
74 /// than one use, this map indicates which which operands are the expanded
75 /// version of the input. This allows us to avoid expanding the same node
77 std::map<SDOperand, std::pair<SDOperand, SDOperand> > ExpandedNodes;
79 void AddLegalizedOperand(SDOperand From, SDOperand To) {
80 LegalizedNodes.insert(std::make_pair(From, To));
81 // If someone requests legalization of the new node, return itself.
83 LegalizedNodes.insert(std::make_pair(To, To));
85 void AddPromotedOperand(SDOperand From, SDOperand To) {
86 bool isNew = PromotedNodes.insert(std::make_pair(From, To)).second;
87 assert(isNew && "Got into the map somehow?");
88 // If someone requests legalization of the new node, return itself.
89 LegalizedNodes.insert(std::make_pair(To, To));
94 SelectionDAGLegalize(SelectionDAG &DAG);
96 /// Run - While there is still lowering to do, perform a pass over the DAG.
97 /// Most regularization can be done in a single pass, but targets that require
98 /// large values to be split into registers multiple times (e.g. i64 -> 4x
99 /// i16) require iteration for these values (the first iteration will demote
100 /// to i32, the second will demote to i16).
103 NeedsAnotherIteration = false;
105 } while (NeedsAnotherIteration);
108 /// getTypeAction - Return how we should legalize values of this type, either
109 /// it is already legal or we need to expand it into multiple registers of
110 /// smaller integer type, or we need to promote it to a larger type.
111 LegalizeAction getTypeAction(MVT::ValueType VT) const {
112 return (LegalizeAction)((ValueTypeActions >> (2*VT)) & 3);
115 /// isTypeLegal - Return true if this type is legal on this target.
117 bool isTypeLegal(MVT::ValueType VT) const {
118 return getTypeAction(VT) == Legal;
124 SDOperand LegalizeOp(SDOperand O);
125 void ExpandOp(SDOperand O, SDOperand &Lo, SDOperand &Hi);
126 SDOperand PromoteOp(SDOperand O);
128 SDOperand ExpandLibCall(const char *Name, SDNode *Node,
130 SDOperand ExpandIntToFP(bool isSigned, MVT::ValueType DestTy,
133 SDOperand ExpandBIT_CONVERT(MVT::ValueType DestVT, SDOperand SrcOp);
134 SDOperand ExpandLegalINT_TO_FP(bool isSigned,
136 MVT::ValueType DestVT);
137 SDOperand PromoteLegalINT_TO_FP(SDOperand LegalOp, MVT::ValueType DestVT,
139 SDOperand PromoteLegalFP_TO_INT(SDOperand LegalOp, MVT::ValueType DestVT,
142 bool ExpandShift(unsigned Opc, SDOperand Op, SDOperand Amt,
143 SDOperand &Lo, SDOperand &Hi);
144 void ExpandShiftParts(unsigned NodeOp, SDOperand Op, SDOperand Amt,
145 SDOperand &Lo, SDOperand &Hi);
146 void ExpandByParts(unsigned NodeOp, SDOperand LHS, SDOperand RHS,
147 SDOperand &Lo, SDOperand &Hi);
149 void SpliceCallInto(const SDOperand &CallResult, SDNode *OutChain);
151 SDOperand getIntPtrConstant(uint64_t Val) {
152 return DAG.getConstant(Val, TLI.getPointerTy());
157 static unsigned getScalarizedOpcode(unsigned VecOp, MVT::ValueType VT) {
159 default: assert(0 && "Don't know how to scalarize this opcode!");
160 case ISD::VADD: return MVT::isInteger(VT) ? ISD::ADD : ISD::FADD;
161 case ISD::VSUB: return MVT::isInteger(VT) ? ISD::SUB : ISD::FSUB;
162 case ISD::VMUL: return MVT::isInteger(VT) ? ISD::MUL : ISD::FMUL;
166 SelectionDAGLegalize::SelectionDAGLegalize(SelectionDAG &dag)
167 : TLI(dag.getTargetLoweringInfo()), DAG(dag),
168 ValueTypeActions(TLI.getValueTypeActions()) {
169 assert(MVT::LAST_VALUETYPE <= 32 &&
170 "Too many value types for ValueTypeActions to hold!");
173 /// ExpandLegalINT_TO_FP - This function is responsible for legalizing a
174 /// INT_TO_FP operation of the specified operand when the target requests that
175 /// we expand it. At this point, we know that the result and operand types are
176 /// legal for the target.
177 SDOperand SelectionDAGLegalize::ExpandLegalINT_TO_FP(bool isSigned,
179 MVT::ValueType DestVT) {
180 if (Op0.getValueType() == MVT::i32) {
181 // simple 32-bit [signed|unsigned] integer to float/double expansion
183 // get the stack frame index of a 8 byte buffer
184 MachineFunction &MF = DAG.getMachineFunction();
185 int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8);
186 // get address of 8 byte buffer
187 SDOperand StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy());
188 // word offset constant for Hi/Lo address computation
189 SDOperand WordOff = DAG.getConstant(sizeof(int), TLI.getPointerTy());
190 // set up Hi and Lo (into buffer) address based on endian
192 if (TLI.isLittleEndian()) {
193 Hi = DAG.getNode(ISD::ADD, TLI.getPointerTy(), StackSlot, WordOff);
197 Lo = DAG.getNode(ISD::ADD, TLI.getPointerTy(), StackSlot, WordOff);
199 // if signed map to unsigned space
202 // constant used to invert sign bit (signed to unsigned mapping)
203 SDOperand SignBit = DAG.getConstant(0x80000000u, MVT::i32);
204 Op0Mapped = DAG.getNode(ISD::XOR, MVT::i32, Op0, SignBit);
208 // store the lo of the constructed double - based on integer input
209 SDOperand Store1 = DAG.getNode(ISD::STORE, MVT::Other, DAG.getEntryNode(),
210 Op0Mapped, Lo, DAG.getSrcValue(NULL));
211 // initial hi portion of constructed double
212 SDOperand InitialHi = DAG.getConstant(0x43300000u, MVT::i32);
213 // store the hi of the constructed double - biased exponent
214 SDOperand Store2 = DAG.getNode(ISD::STORE, MVT::Other, Store1,
215 InitialHi, Hi, DAG.getSrcValue(NULL));
216 // load the constructed double
217 SDOperand Load = DAG.getLoad(MVT::f64, Store2, StackSlot,
218 DAG.getSrcValue(NULL));
219 // FP constant to bias correct the final result
220 SDOperand Bias = DAG.getConstantFP(isSigned ?
221 BitsToDouble(0x4330000080000000ULL)
222 : BitsToDouble(0x4330000000000000ULL),
225 SDOperand Sub = DAG.getNode(ISD::FSUB, MVT::f64, Load, Bias);
228 // handle final rounding
229 if (DestVT == MVT::f64) {
233 // if f32 then cast to f32
234 Result = DAG.getNode(ISD::FP_ROUND, MVT::f32, Sub);
236 return LegalizeOp(Result);
238 assert(!isSigned && "Legalize cannot Expand SINT_TO_FP for i64 yet");
239 SDOperand Tmp1 = DAG.getNode(ISD::SINT_TO_FP, DestVT, Op0);
241 SDOperand SignSet = DAG.getSetCC(TLI.getSetCCResultTy(), Op0,
242 DAG.getConstant(0, Op0.getValueType()),
244 SDOperand Zero = getIntPtrConstant(0), Four = getIntPtrConstant(4);
245 SDOperand CstOffset = DAG.getNode(ISD::SELECT, Zero.getValueType(),
246 SignSet, Four, Zero);
248 // If the sign bit of the integer is set, the large number will be treated
249 // as a negative number. To counteract this, the dynamic code adds an
250 // offset depending on the data type.
252 switch (Op0.getValueType()) {
253 default: assert(0 && "Unsupported integer type!");
254 case MVT::i8 : FF = 0x43800000ULL; break; // 2^8 (as a float)
255 case MVT::i16: FF = 0x47800000ULL; break; // 2^16 (as a float)
256 case MVT::i32: FF = 0x4F800000ULL; break; // 2^32 (as a float)
257 case MVT::i64: FF = 0x5F800000ULL; break; // 2^64 (as a float)
259 if (TLI.isLittleEndian()) FF <<= 32;
260 static Constant *FudgeFactor = ConstantUInt::get(Type::ULongTy, FF);
262 SDOperand CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy());
263 CPIdx = DAG.getNode(ISD::ADD, TLI.getPointerTy(), CPIdx, CstOffset);
264 SDOperand FudgeInReg;
265 if (DestVT == MVT::f32)
266 FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx,
267 DAG.getSrcValue(NULL));
269 assert(DestVT == MVT::f64 && "Unexpected conversion");
270 FudgeInReg = LegalizeOp(DAG.getExtLoad(ISD::EXTLOAD, MVT::f64,
271 DAG.getEntryNode(), CPIdx,
272 DAG.getSrcValue(NULL), MVT::f32));
275 return LegalizeOp(DAG.getNode(ISD::FADD, DestVT, Tmp1, FudgeInReg));
278 /// PromoteLegalINT_TO_FP - This function is responsible for legalizing a
279 /// *INT_TO_FP operation of the specified operand when the target requests that
280 /// we promote it. At this point, we know that the result and operand types are
281 /// legal for the target, and that there is a legal UINT_TO_FP or SINT_TO_FP
282 /// operation that takes a larger input.
283 SDOperand SelectionDAGLegalize::PromoteLegalINT_TO_FP(SDOperand LegalOp,
284 MVT::ValueType DestVT,
286 // First step, figure out the appropriate *INT_TO_FP operation to use.
287 MVT::ValueType NewInTy = LegalOp.getValueType();
289 unsigned OpToUse = 0;
291 // Scan for the appropriate larger type to use.
293 NewInTy = (MVT::ValueType)(NewInTy+1);
294 assert(MVT::isInteger(NewInTy) && "Ran out of possibilities!");
296 // If the target supports SINT_TO_FP of this type, use it.
297 switch (TLI.getOperationAction(ISD::SINT_TO_FP, NewInTy)) {
299 case TargetLowering::Legal:
300 if (!TLI.isTypeLegal(NewInTy))
301 break; // Can't use this datatype.
303 case TargetLowering::Custom:
304 OpToUse = ISD::SINT_TO_FP;
308 if (isSigned) continue;
310 // If the target supports UINT_TO_FP of this type, use it.
311 switch (TLI.getOperationAction(ISD::UINT_TO_FP, NewInTy)) {
313 case TargetLowering::Legal:
314 if (!TLI.isTypeLegal(NewInTy))
315 break; // Can't use this datatype.
317 case TargetLowering::Custom:
318 OpToUse = ISD::UINT_TO_FP;
323 // Otherwise, try a larger type.
326 // Okay, we found the operation and type to use. Zero extend our input to the
327 // desired type then run the operation on it.
328 SDOperand N = DAG.getNode(OpToUse, DestVT,
329 DAG.getNode(isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND,
331 // Make sure to legalize any nodes we create here.
332 return LegalizeOp(N);
335 /// PromoteLegalFP_TO_INT - This function is responsible for legalizing a
336 /// FP_TO_*INT operation of the specified operand when the target requests that
337 /// we promote it. At this point, we know that the result and operand types are
338 /// legal for the target, and that there is a legal FP_TO_UINT or FP_TO_SINT
339 /// operation that returns a larger result.
340 SDOperand SelectionDAGLegalize::PromoteLegalFP_TO_INT(SDOperand LegalOp,
341 MVT::ValueType DestVT,
343 // First step, figure out the appropriate FP_TO*INT operation to use.
344 MVT::ValueType NewOutTy = DestVT;
346 unsigned OpToUse = 0;
348 // Scan for the appropriate larger type to use.
350 NewOutTy = (MVT::ValueType)(NewOutTy+1);
351 assert(MVT::isInteger(NewOutTy) && "Ran out of possibilities!");
353 // If the target supports FP_TO_SINT returning this type, use it.
354 switch (TLI.getOperationAction(ISD::FP_TO_SINT, NewOutTy)) {
356 case TargetLowering::Legal:
357 if (!TLI.isTypeLegal(NewOutTy))
358 break; // Can't use this datatype.
360 case TargetLowering::Custom:
361 OpToUse = ISD::FP_TO_SINT;
366 // If the target supports FP_TO_UINT of this type, use it.
367 switch (TLI.getOperationAction(ISD::FP_TO_UINT, NewOutTy)) {
369 case TargetLowering::Legal:
370 if (!TLI.isTypeLegal(NewOutTy))
371 break; // Can't use this datatype.
373 case TargetLowering::Custom:
374 OpToUse = ISD::FP_TO_UINT;
379 // Otherwise, try a larger type.
382 // Okay, we found the operation and type to use. Truncate the result of the
383 // extended FP_TO_*INT operation to the desired size.
384 SDOperand N = DAG.getNode(ISD::TRUNCATE, DestVT,
385 DAG.getNode(OpToUse, NewOutTy, LegalOp));
386 // Make sure to legalize any nodes we create here in the next pass.
387 return LegalizeOp(N);
390 /// ComputeTopDownOrdering - Add the specified node to the Order list if it has
391 /// not been visited yet and if all of its operands have already been visited.
392 static void ComputeTopDownOrdering(SDNode *N, std::vector<SDNode*> &Order,
393 std::map<SDNode*, unsigned> &Visited) {
394 if (++Visited[N] != N->getNumOperands())
395 return; // Haven't visited all operands yet
399 if (N->hasOneUse()) { // Tail recurse in common case.
400 ComputeTopDownOrdering(*N->use_begin(), Order, Visited);
404 // Now that we have N in, add anything that uses it if all of their operands
406 for (SDNode::use_iterator UI = N->use_begin(), E = N->use_end(); UI != E;++UI)
407 ComputeTopDownOrdering(*UI, Order, Visited);
411 void SelectionDAGLegalize::LegalizeDAG() {
412 // The legalize process is inherently a bottom-up recursive process (users
413 // legalize their uses before themselves). Given infinite stack space, we
414 // could just start legalizing on the root and traverse the whole graph. In
415 // practice however, this causes us to run out of stack space on large basic
416 // blocks. To avoid this problem, compute an ordering of the nodes where each
417 // node is only legalized after all of its operands are legalized.
418 std::map<SDNode*, unsigned> Visited;
419 std::vector<SDNode*> Order;
421 // Compute ordering from all of the leaves in the graphs, those (like the
422 // entry node) that have no operands.
423 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(),
424 E = DAG.allnodes_end(); I != E; ++I) {
425 if (I->getNumOperands() == 0) {
427 ComputeTopDownOrdering(I, Order, Visited);
431 assert(Order.size() == Visited.size() &&
433 (unsigned)std::distance(DAG.allnodes_begin(), DAG.allnodes_end()) &&
434 "Error: DAG is cyclic!");
437 for (unsigned i = 0, e = Order.size(); i != e; ++i) {
438 SDNode *N = Order[i];
439 switch (getTypeAction(N->getValueType(0))) {
440 default: assert(0 && "Bad type action!");
442 LegalizeOp(SDOperand(N, 0));
445 PromoteOp(SDOperand(N, 0));
449 ExpandOp(SDOperand(N, 0), X, Y);
455 // Finally, it's possible the root changed. Get the new root.
456 SDOperand OldRoot = DAG.getRoot();
457 assert(LegalizedNodes.count(OldRoot) && "Root didn't get legalized?");
458 DAG.setRoot(LegalizedNodes[OldRoot]);
460 ExpandedNodes.clear();
461 LegalizedNodes.clear();
462 PromotedNodes.clear();
464 // Remove dead nodes now.
465 DAG.RemoveDeadNodes(OldRoot.Val);
468 SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
469 assert(isTypeLegal(Op.getValueType()) &&
470 "Caller should expand or promote operands that are not legal!");
471 SDNode *Node = Op.Val;
473 // If this operation defines any values that cannot be represented in a
474 // register on this target, make sure to expand or promote them.
475 if (Node->getNumValues() > 1) {
476 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
477 switch (getTypeAction(Node->getValueType(i))) {
478 case Legal: break; // Nothing to do.
481 ExpandOp(Op.getValue(i), T1, T2);
482 assert(LegalizedNodes.count(Op) &&
483 "Expansion didn't add legal operands!");
484 return LegalizedNodes[Op];
487 PromoteOp(Op.getValue(i));
488 assert(LegalizedNodes.count(Op) &&
489 "Expansion didn't add legal operands!");
490 return LegalizedNodes[Op];
494 // Note that LegalizeOp may be reentered even from single-use nodes, which
495 // means that we always must cache transformed nodes.
496 std::map<SDOperand, SDOperand>::iterator I = LegalizedNodes.find(Op);
497 if (I != LegalizedNodes.end()) return I->second;
499 SDOperand Tmp1, Tmp2, Tmp3, Tmp4;
501 SDOperand Result = Op;
503 switch (Node->getOpcode()) {
505 if (Node->getOpcode() >= ISD::BUILTIN_OP_END) {
506 // If this is a target node, legalize it by legalizing the operands then
507 // passing it through.
508 std::vector<SDOperand> Ops;
509 bool Changed = false;
510 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
511 Ops.push_back(LegalizeOp(Node->getOperand(i)));
512 Changed = Changed || Node->getOperand(i) != Ops.back();
515 if (Node->getNumValues() == 1)
516 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Ops);
518 std::vector<MVT::ValueType> VTs(Node->value_begin(),
520 Result = DAG.getNode(Node->getOpcode(), VTs, Ops);
523 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
524 AddLegalizedOperand(Op.getValue(i), Result.getValue(i));
525 return Result.getValue(Op.ResNo);
527 // Otherwise this is an unhandled builtin node. splat.
528 std::cerr << "NODE: "; Node->dump(); std::cerr << "\n";
529 assert(0 && "Do not know how to legalize this operator!");
531 case ISD::EntryToken:
532 case ISD::FrameIndex:
533 case ISD::TargetFrameIndex:
535 case ISD::TargetConstant:
536 case ISD::TargetConstantPool:
537 case ISD::GlobalAddress:
538 case ISD::TargetGlobalAddress:
539 case ISD::ExternalSymbol:
540 case ISD::TargetExternalSymbol:
541 case ISD::ConstantPool: // Nothing to do.
542 case ISD::BasicBlock:
547 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
548 default: assert(0 && "This action is not supported yet!");
549 case TargetLowering::Custom: {
550 SDOperand Tmp = TLI.LowerOperation(Op, DAG);
552 Result = LegalizeOp(Tmp);
555 } // FALLTHROUGH if the target doesn't want to lower this op after all.
556 case TargetLowering::Legal:
557 assert(isTypeLegal(Node->getValueType(0)) && "This must be legal!");
561 case ISD::AssertSext:
562 case ISD::AssertZext:
563 Tmp1 = LegalizeOp(Node->getOperand(0));
564 if (Tmp1 != Node->getOperand(0))
565 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1,
566 Node->getOperand(1));
568 case ISD::MERGE_VALUES:
569 return LegalizeOp(Node->getOperand(Op.ResNo));
570 case ISD::CopyFromReg:
571 Tmp1 = LegalizeOp(Node->getOperand(0));
572 Result = Op.getValue(0);
573 if (Node->getNumValues() == 2) {
574 if (Tmp1 != Node->getOperand(0))
575 Result = DAG.getCopyFromReg(Tmp1,
576 cast<RegisterSDNode>(Node->getOperand(1))->getReg(),
577 Node->getValueType(0));
579 assert(Node->getNumValues() == 3 && "Invalid copyfromreg!");
580 if (Node->getNumOperands() == 3)
581 Tmp2 = LegalizeOp(Node->getOperand(2));
582 if (Tmp1 != Node->getOperand(0) ||
583 (Node->getNumOperands() == 3 && Tmp2 != Node->getOperand(2)))
584 Result = DAG.getCopyFromReg(Tmp1,
585 cast<RegisterSDNode>(Node->getOperand(1))->getReg(),
586 Node->getValueType(0), Tmp2);
587 AddLegalizedOperand(Op.getValue(2), Result.getValue(2));
589 // Since CopyFromReg produces two values, make sure to remember that we
590 // legalized both of them.
591 AddLegalizedOperand(Op.getValue(0), Result);
592 AddLegalizedOperand(Op.getValue(1), Result.getValue(1));
593 return Result.getValue(Op.ResNo);
595 MVT::ValueType VT = Op.getValueType();
596 switch (TLI.getOperationAction(ISD::UNDEF, VT)) {
597 default: assert(0 && "This action is not supported yet!");
598 case TargetLowering::Expand:
599 case TargetLowering::Promote:
600 if (MVT::isInteger(VT))
601 Result = DAG.getConstant(0, VT);
602 else if (MVT::isFloatingPoint(VT))
603 Result = DAG.getConstantFP(0, VT);
605 assert(0 && "Unknown value type!");
607 case TargetLowering::Legal:
614 assert(Node->getNumOperands() == 5 && "Invalid LOCATION node!");
615 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the input chain.
617 switch (TLI.getOperationAction(ISD::LOCATION, MVT::Other)) {
618 case TargetLowering::Promote:
619 default: assert(0 && "This action is not supported yet!");
620 case TargetLowering::Expand: {
621 MachineDebugInfo *DebugInfo = DAG.getMachineDebugInfo();
622 bool useDEBUG_LOC = TLI.isOperationLegal(ISD::DEBUG_LOC, MVT::Other);
623 bool useDEBUG_LABEL = TLI.isOperationLegal(ISD::DEBUG_LABEL, MVT::Other);
625 if (DebugInfo && (useDEBUG_LOC || useDEBUG_LABEL)) {
626 const std::string &FName =
627 cast<StringSDNode>(Node->getOperand(3))->getValue();
628 const std::string &DirName =
629 cast<StringSDNode>(Node->getOperand(4))->getValue();
630 unsigned SrcFile = DebugInfo->RecordSource(DirName, FName);
632 std::vector<SDOperand> Ops;
633 Ops.push_back(Tmp1); // chain
634 SDOperand LineOp = Node->getOperand(1);
635 SDOperand ColOp = Node->getOperand(2);
638 Ops.push_back(LineOp); // line #
639 Ops.push_back(ColOp); // col #
640 Ops.push_back(DAG.getConstant(SrcFile, MVT::i32)); // source file id
641 Result = DAG.getNode(ISD::DEBUG_LOC, MVT::Other, Ops);
643 unsigned Line = dyn_cast<ConstantSDNode>(LineOp)->getValue();
644 unsigned Col = dyn_cast<ConstantSDNode>(ColOp)->getValue();
645 unsigned ID = DebugInfo->RecordLabel(Line, Col, SrcFile);
646 Ops.push_back(DAG.getConstant(ID, MVT::i32));
647 Result = DAG.getNode(ISD::DEBUG_LABEL, MVT::Other, Ops);
650 Result = Tmp1; // chain
652 Result = LegalizeOp(Result); // Relegalize new nodes.
655 case TargetLowering::Legal:
656 if (Tmp1 != Node->getOperand(0) ||
657 getTypeAction(Node->getOperand(1).getValueType()) == Promote) {
658 std::vector<SDOperand> Ops;
660 if (getTypeAction(Node->getOperand(1).getValueType()) == Legal) {
661 Ops.push_back(Node->getOperand(1)); // line # must be legal.
662 Ops.push_back(Node->getOperand(2)); // col # must be legal.
664 // Otherwise promote them.
665 Ops.push_back(PromoteOp(Node->getOperand(1)));
666 Ops.push_back(PromoteOp(Node->getOperand(2)));
668 Ops.push_back(Node->getOperand(3)); // filename must be legal.
669 Ops.push_back(Node->getOperand(4)); // working dir # must be legal.
670 Result = DAG.getNode(ISD::LOCATION, MVT::Other, Ops);
677 assert(Node->getNumOperands() == 4 && "Invalid DEBUG_LOC node!");
678 switch (TLI.getOperationAction(ISD::DEBUG_LOC, MVT::Other)) {
679 case TargetLowering::Promote:
680 case TargetLowering::Expand:
681 default: assert(0 && "This action is not supported yet!");
682 case TargetLowering::Legal:
683 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
684 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the line #.
685 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the col #.
686 Tmp4 = LegalizeOp(Node->getOperand(3)); // Legalize the source file id.
688 if (Tmp1 != Node->getOperand(0) ||
689 Tmp2 != Node->getOperand(1) ||
690 Tmp3 != Node->getOperand(2) ||
691 Tmp4 != Node->getOperand(3)) {
692 Result = DAG.getNode(ISD::DEBUG_LOC,MVT::Other, Tmp1, Tmp2, Tmp3, Tmp4);
698 case ISD::DEBUG_LABEL:
699 assert(Node->getNumOperands() == 2 && "Invalid DEBUG_LABEL node!");
700 switch (TLI.getOperationAction(ISD::DEBUG_LABEL, MVT::Other)) {
701 case TargetLowering::Promote:
702 case TargetLowering::Expand:
703 default: assert(0 && "This action is not supported yet!");
704 case TargetLowering::Legal:
705 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
706 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the label id.
708 if (Tmp1 != Node->getOperand(0) ||
709 Tmp2 != Node->getOperand(1)) {
710 Result = DAG.getNode(ISD::DEBUG_LABEL, MVT::Other, Tmp1, Tmp2);
717 // We know we don't need to expand constants here, constants only have one
718 // value and we check that it is fine above.
720 // FIXME: Maybe we should handle things like targets that don't support full
721 // 32-bit immediates?
723 case ISD::ConstantFP: {
724 // Spill FP immediates to the constant pool if the target cannot directly
725 // codegen them. Targets often have some immediate values that can be
726 // efficiently generated into an FP register without a load. We explicitly
727 // leave these constants as ConstantFP nodes for the target to deal with.
729 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node);
731 // Check to see if this FP immediate is already legal.
732 bool isLegal = false;
733 for (TargetLowering::legal_fpimm_iterator I = TLI.legal_fpimm_begin(),
734 E = TLI.legal_fpimm_end(); I != E; ++I)
735 if (CFP->isExactlyValue(*I)) {
741 // Otherwise we need to spill the constant to memory.
744 // If a FP immediate is precise when represented as a float, we put it
745 // into the constant pool as a float, even if it's is statically typed
747 MVT::ValueType VT = CFP->getValueType(0);
748 bool isDouble = VT == MVT::f64;
749 ConstantFP *LLVMC = ConstantFP::get(isDouble ? Type::DoubleTy :
750 Type::FloatTy, CFP->getValue());
751 if (isDouble && CFP->isExactlyValue((float)CFP->getValue()) &&
752 // Only do this if the target has a native EXTLOAD instruction from
754 TLI.isOperationLegal(ISD::EXTLOAD, MVT::f32)) {
755 LLVMC = cast<ConstantFP>(ConstantExpr::getCast(LLVMC, Type::FloatTy));
761 LegalizeOp(DAG.getConstantPool(LLVMC, TLI.getPointerTy()));
763 Result = DAG.getExtLoad(ISD::EXTLOAD, MVT::f64, DAG.getEntryNode(),
764 CPIdx, DAG.getSrcValue(NULL), MVT::f32);
766 Result = DAG.getLoad(VT, DAG.getEntryNode(), CPIdx,
767 DAG.getSrcValue(NULL));
772 case ISD::ConstantVec: {
773 // We assume that vector constants are not legal, and will be immediately
774 // spilled to the constant pool.
776 // FIXME: revisit this when we have some kind of mechanism by which targets
777 // can decided legality of vector constants, of which there may be very
780 // Create a ConstantPacked, and put it in the constant pool.
781 std::vector<Constant*> CV;
782 MVT::ValueType VT = Node->getValueType(0);
783 for (unsigned I = 0, E = Node->getNumOperands(); I < E; ++I) {
784 SDOperand OpN = Node->getOperand(I);
785 const Type* OpNTy = MVT::getTypeForValueType(OpN.getValueType());
786 if (MVT::isFloatingPoint(VT))
787 CV.push_back(ConstantFP::get(OpNTy,
788 cast<ConstantFPSDNode>(OpN)->getValue()));
790 CV.push_back(ConstantUInt::get(OpNTy,
791 cast<ConstantSDNode>(OpN)->getValue()));
793 Constant *CP = ConstantPacked::get(CV);
794 SDOperand CPIdx = LegalizeOp(DAG.getConstantPool(CP, TLI.getPointerTy()));
795 Result = DAG.getLoad(VT, DAG.getEntryNode(), CPIdx, DAG.getSrcValue(NULL));
798 case ISD::TokenFactor:
799 if (Node->getNumOperands() == 2) {
800 bool Changed = false;
801 SDOperand Op0 = LegalizeOp(Node->getOperand(0));
802 SDOperand Op1 = LegalizeOp(Node->getOperand(1));
803 if (Op0 != Node->getOperand(0) || Op1 != Node->getOperand(1))
804 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, Op0, Op1);
806 std::vector<SDOperand> Ops;
807 bool Changed = false;
808 // Legalize the operands.
809 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
810 SDOperand Op = Node->getOperand(i);
811 Ops.push_back(LegalizeOp(Op));
812 Changed |= Ops[i] != Op;
815 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, Ops);
819 case ISD::CALLSEQ_START:
820 case ISD::CALLSEQ_END:
821 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
822 // Do not try to legalize the target-specific arguments (#1+)
823 Tmp2 = Node->getOperand(0);
825 Node->setAdjCallChain(Tmp1);
827 // If this has a flag input, do legalize it.
828 if (Node->getOperand(Node->getNumOperands()-1).getValueType() == MVT::Flag){
829 Tmp1 = LegalizeOp(Node->getOperand(Node->getNumOperands()-1));
830 if (Tmp1 != Node->getOperand(Node->getNumOperands()-1))
831 Node->setAdjCallFlag(Tmp1);
834 // Note that we do not create new CALLSEQ_DOWN/UP nodes here. These
835 // nodes are treated specially and are mutated in place. This makes the dag
836 // legalization process more efficient and also makes libcall insertion
839 case ISD::DYNAMIC_STACKALLOC: {
840 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
841 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the size.
842 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the alignment.
843 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1) ||
844 Tmp3 != Node->getOperand(2)) {
845 std::vector<MVT::ValueType> VTs(Node->value_begin(), Node->value_end());
846 std::vector<SDOperand> Ops;
847 Ops.push_back(Tmp1); Ops.push_back(Tmp2); Ops.push_back(Tmp3);
848 Result = DAG.getNode(ISD::DYNAMIC_STACKALLOC, VTs, Ops);
850 Result = Op.getValue(0);
853 Tmp2 = Result.getValue(1);
854 switch (TLI.getOperationAction(Node->getOpcode(),
855 Node->getValueType(0))) {
856 default: assert(0 && "This action is not supported yet!");
857 case TargetLowering::Expand: {
858 unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore();
859 assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and"
860 " not tell us which reg is the stack pointer!");
861 SDOperand Chain = Tmp1.getOperand(0);
862 SDOperand Size = Tmp2.getOperand(1);
863 SDOperand SP = DAG.getCopyFromReg(Chain, SPReg, Node->getValueType(0));
864 Tmp1 = DAG.getNode(ISD::SUB, Node->getValueType(0), SP, Size); // Value
865 Tmp2 = DAG.getCopyToReg(SP.getValue(1), SPReg, Tmp1); // Output chain
868 case TargetLowering::Custom:
869 Tmp3 = TLI.LowerOperation(Tmp1, DAG);
871 Tmp1 = LegalizeOp(Tmp3);
872 Tmp2 = LegalizeOp(Tmp3.getValue(1));
875 case TargetLowering::Legal:
878 // Since this op produce two values, make sure to remember that we
879 // legalized both of them.
880 AddLegalizedOperand(SDOperand(Node, 0), Tmp1);
881 AddLegalizedOperand(SDOperand(Node, 1), Tmp2);
882 return Op.ResNo ? Tmp2 : Tmp1;
886 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
887 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the callee.
889 bool Changed = false;
890 std::vector<SDOperand> Ops;
891 for (unsigned i = 2, e = Node->getNumOperands(); i != e; ++i) {
892 Ops.push_back(LegalizeOp(Node->getOperand(i)));
893 Changed |= Ops.back() != Node->getOperand(i);
896 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1) || Changed) {
897 std::vector<MVT::ValueType> RetTyVTs;
898 RetTyVTs.reserve(Node->getNumValues());
899 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
900 RetTyVTs.push_back(Node->getValueType(i));
901 Result = SDOperand(DAG.getCall(RetTyVTs, Tmp1, Tmp2, Ops,
902 Node->getOpcode() == ISD::TAILCALL), 0);
904 Result = Result.getValue(0);
906 // Since calls produce multiple values, make sure to remember that we
907 // legalized all of them.
908 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
909 AddLegalizedOperand(SDOperand(Node, i), Result.getValue(i));
910 return Result.getValue(Op.ResNo);
913 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
914 if (Tmp1 != Node->getOperand(0))
915 Result = DAG.getNode(ISD::BR, MVT::Other, Tmp1, Node->getOperand(1));
919 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
921 switch (getTypeAction(Node->getOperand(1).getValueType())) {
922 case Expand: assert(0 && "It's impossible to expand bools");
924 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the condition.
927 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the condition.
931 switch (TLI.getOperationAction(ISD::BRCOND, MVT::Other)) {
932 default: assert(0 && "This action is not supported yet!");
933 case TargetLowering::Expand:
934 // Expand brcond's setcc into its constituent parts and create a BR_CC
936 if (Tmp2.getOpcode() == ISD::SETCC) {
937 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1, Tmp2.getOperand(2),
938 Tmp2.getOperand(0), Tmp2.getOperand(1),
939 Node->getOperand(2));
941 // Make sure the condition is either zero or one. It may have been
942 // promoted from something else.
943 Tmp2 = DAG.getZeroExtendInReg(Tmp2, MVT::i1);
945 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1,
946 DAG.getCondCode(ISD::SETNE), Tmp2,
947 DAG.getConstant(0, Tmp2.getValueType()),
948 Node->getOperand(2));
950 Result = LegalizeOp(Result); // Relegalize new nodes.
952 case TargetLowering::Custom: {
954 TLI.LowerOperation(DAG.getNode(ISD::BRCOND, Node->getValueType(0),
955 Tmp1, Tmp2, Node->getOperand(2)), DAG);
957 Result = LegalizeOp(Tmp);
960 // FALLTHROUGH if the target thinks it is legal.
962 case TargetLowering::Legal:
963 // Basic block destination (Op#2) is always legal.
964 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1))
965 Result = DAG.getNode(ISD::BRCOND, MVT::Other, Tmp1, Tmp2,
966 Node->getOperand(2));
971 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
972 if (!isTypeLegal(Node->getOperand(2).getValueType())) {
973 Tmp2 = LegalizeOp(DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(),
974 Node->getOperand(2), // LHS
975 Node->getOperand(3), // RHS
976 Node->getOperand(1)));
977 // If we get a SETCC back from legalizing the SETCC node we just
978 // created, then use its LHS, RHS, and CC directly in creating a new
979 // node. Otherwise, select between the true and false value based on
980 // comparing the result of the legalized with zero.
981 if (Tmp2.getOpcode() == ISD::SETCC) {
982 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1, Tmp2.getOperand(2),
983 Tmp2.getOperand(0), Tmp2.getOperand(1),
984 Node->getOperand(4));
986 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1,
987 DAG.getCondCode(ISD::SETNE),
988 Tmp2, DAG.getConstant(0, Tmp2.getValueType()),
989 Node->getOperand(4));
994 Tmp2 = LegalizeOp(Node->getOperand(2)); // LHS
995 Tmp3 = LegalizeOp(Node->getOperand(3)); // RHS
997 switch (TLI.getOperationAction(ISD::BR_CC, Tmp3.getValueType())) {
998 default: assert(0 && "Unexpected action for BR_CC!");
999 case TargetLowering::Custom: {
1000 Tmp4 = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1, Node->getOperand(1),
1001 Tmp2, Tmp3, Node->getOperand(4));
1002 Tmp4 = TLI.LowerOperation(Tmp4, DAG);
1004 Result = LegalizeOp(Tmp4);
1007 } // FALLTHROUGH if the target doesn't want to lower this op after all.
1008 case TargetLowering::Legal:
1009 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(2) ||
1010 Tmp3 != Node->getOperand(3)) {
1011 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1, Node->getOperand(1),
1012 Tmp2, Tmp3, Node->getOperand(4));
1017 case ISD::BRCONDTWOWAY:
1018 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1019 switch (getTypeAction(Node->getOperand(1).getValueType())) {
1020 case Expand: assert(0 && "It's impossible to expand bools");
1022 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the condition.
1025 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the condition.
1028 // If this target does not support BRCONDTWOWAY, lower it to a BRCOND/BR
1030 switch (TLI.getOperationAction(ISD::BRCONDTWOWAY, MVT::Other)) {
1031 case TargetLowering::Promote:
1032 default: assert(0 && "This action is not supported yet!");
1033 case TargetLowering::Legal:
1034 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1)) {
1035 std::vector<SDOperand> Ops;
1036 Ops.push_back(Tmp1);
1037 Ops.push_back(Tmp2);
1038 Ops.push_back(Node->getOperand(2));
1039 Ops.push_back(Node->getOperand(3));
1040 Result = DAG.getNode(ISD::BRCONDTWOWAY, MVT::Other, Ops);
1043 case TargetLowering::Expand:
1044 // If BRTWOWAY_CC is legal for this target, then simply expand this node
1045 // to that. Otherwise, skip BRTWOWAY_CC and expand directly to a
1047 if (TLI.isOperationLegal(ISD::BRTWOWAY_CC, MVT::Other)) {
1048 if (Tmp2.getOpcode() == ISD::SETCC) {
1049 Result = DAG.getBR2Way_CC(Tmp1, Tmp2.getOperand(2),
1050 Tmp2.getOperand(0), Tmp2.getOperand(1),
1051 Node->getOperand(2), Node->getOperand(3));
1053 Result = DAG.getBR2Way_CC(Tmp1, DAG.getCondCode(ISD::SETNE), Tmp2,
1054 DAG.getConstant(0, Tmp2.getValueType()),
1055 Node->getOperand(2), Node->getOperand(3));
1058 Result = DAG.getNode(ISD::BRCOND, MVT::Other, Tmp1, Tmp2,
1059 Node->getOperand(2));
1060 Result = DAG.getNode(ISD::BR, MVT::Other, Result, Node->getOperand(3));
1062 Result = LegalizeOp(Result); // Relegalize new nodes.
1066 case ISD::BRTWOWAY_CC:
1067 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1068 if (isTypeLegal(Node->getOperand(2).getValueType())) {
1069 Tmp2 = LegalizeOp(Node->getOperand(2)); // LHS
1070 Tmp3 = LegalizeOp(Node->getOperand(3)); // RHS
1071 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(2) ||
1072 Tmp3 != Node->getOperand(3)) {
1073 Result = DAG.getBR2Way_CC(Tmp1, Node->getOperand(1), Tmp2, Tmp3,
1074 Node->getOperand(4), Node->getOperand(5));
1078 Tmp2 = LegalizeOp(DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(),
1079 Node->getOperand(2), // LHS
1080 Node->getOperand(3), // RHS
1081 Node->getOperand(1)));
1082 // If this target does not support BRTWOWAY_CC, lower it to a BRCOND/BR
1084 switch (TLI.getOperationAction(ISD::BRTWOWAY_CC, MVT::Other)) {
1085 default: assert(0 && "This action is not supported yet!");
1086 case TargetLowering::Legal:
1087 // If we get a SETCC back from legalizing the SETCC node we just
1088 // created, then use its LHS, RHS, and CC directly in creating a new
1089 // node. Otherwise, select between the true and false value based on
1090 // comparing the result of the legalized with zero.
1091 if (Tmp2.getOpcode() == ISD::SETCC) {
1092 Result = DAG.getBR2Way_CC(Tmp1, Tmp2.getOperand(2),
1093 Tmp2.getOperand(0), Tmp2.getOperand(1),
1094 Node->getOperand(4), Node->getOperand(5));
1096 Result = DAG.getBR2Way_CC(Tmp1, DAG.getCondCode(ISD::SETNE), Tmp2,
1097 DAG.getConstant(0, Tmp2.getValueType()),
1098 Node->getOperand(4), Node->getOperand(5));
1101 case TargetLowering::Expand:
1102 Result = DAG.getNode(ISD::BRCOND, MVT::Other, Tmp1, Tmp2,
1103 Node->getOperand(4));
1104 Result = DAG.getNode(ISD::BR, MVT::Other, Result, Node->getOperand(5));
1107 Result = LegalizeOp(Result); // Relegalize new nodes.
1111 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1112 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
1114 MVT::ValueType VT = Node->getValueType(0);
1115 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
1116 default: assert(0 && "This action is not supported yet!");
1117 case TargetLowering::Custom: {
1118 SDOperand Op = DAG.getLoad(Node->getValueType(0),
1119 Tmp1, Tmp2, Node->getOperand(2));
1120 SDOperand Tmp = TLI.LowerOperation(Op, DAG);
1122 Result = LegalizeOp(Tmp);
1123 // Since loads produce two values, make sure to remember that we legalized
1125 AddLegalizedOperand(SDOperand(Node, 0), Result);
1126 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
1127 return Result.getValue(Op.ResNo);
1129 // FALLTHROUGH if the target thinks it is legal.
1131 case TargetLowering::Legal:
1132 if (Tmp1 != Node->getOperand(0) ||
1133 Tmp2 != Node->getOperand(1))
1134 Result = DAG.getLoad(Node->getValueType(0), Tmp1, Tmp2,
1135 Node->getOperand(2));
1137 Result = SDOperand(Node, 0);
1139 // Since loads produce two values, make sure to remember that we legalized
1141 AddLegalizedOperand(SDOperand(Node, 0), Result);
1142 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
1143 return Result.getValue(Op.ResNo);
1145 assert(0 && "Unreachable");
1149 case ISD::ZEXTLOAD: {
1150 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1151 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
1153 MVT::ValueType SrcVT = cast<VTSDNode>(Node->getOperand(3))->getVT();
1154 switch (TLI.getOperationAction(Node->getOpcode(), SrcVT)) {
1155 default: assert(0 && "This action is not supported yet!");
1156 case TargetLowering::Promote:
1157 assert(SrcVT == MVT::i1 && "Can only promote EXTLOAD from i1 -> i8!");
1158 Result = DAG.getExtLoad(Node->getOpcode(), Node->getValueType(0),
1159 Tmp1, Tmp2, Node->getOperand(2), MVT::i8);
1160 // Since loads produce two values, make sure to remember that we legalized
1162 AddLegalizedOperand(SDOperand(Node, 0), Result);
1163 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
1164 return Result.getValue(Op.ResNo);
1166 case TargetLowering::Custom: {
1167 SDOperand Op = DAG.getExtLoad(Node->getOpcode(), Node->getValueType(0),
1168 Tmp1, Tmp2, Node->getOperand(2),
1170 SDOperand Tmp = TLI.LowerOperation(Op, DAG);
1172 Result = LegalizeOp(Tmp);
1173 // Since loads produce two values, make sure to remember that we legalized
1175 AddLegalizedOperand(SDOperand(Node, 0), Result);
1176 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
1177 return Result.getValue(Op.ResNo);
1179 // FALLTHROUGH if the target thinks it is legal.
1181 case TargetLowering::Legal:
1182 if (Tmp1 != Node->getOperand(0) ||
1183 Tmp2 != Node->getOperand(1))
1184 Result = DAG.getExtLoad(Node->getOpcode(), Node->getValueType(0),
1185 Tmp1, Tmp2, Node->getOperand(2), SrcVT);
1187 Result = SDOperand(Node, 0);
1189 // Since loads produce two values, make sure to remember that we legalized
1191 AddLegalizedOperand(SDOperand(Node, 0), Result);
1192 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
1193 return Result.getValue(Op.ResNo);
1194 case TargetLowering::Expand:
1195 // f64 = EXTLOAD f32 should expand to LOAD, FP_EXTEND
1196 if (SrcVT == MVT::f32 && Node->getValueType(0) == MVT::f64) {
1197 SDOperand Load = DAG.getLoad(SrcVT, Tmp1, Tmp2, Node->getOperand(2));
1198 Result = DAG.getNode(ISD::FP_EXTEND, Node->getValueType(0), Load);
1199 Result = LegalizeOp(Result); // Relegalize new nodes.
1200 Load = LegalizeOp(Load);
1201 AddLegalizedOperand(SDOperand(Node, 0), Result);
1202 AddLegalizedOperand(SDOperand(Node, 1), Load.getValue(1));
1204 return Load.getValue(1);
1207 assert(Node->getOpcode() != ISD::EXTLOAD &&
1208 "EXTLOAD should always be supported!");
1209 // Turn the unsupported load into an EXTLOAD followed by an explicit
1210 // zero/sign extend inreg.
1211 Result = DAG.getExtLoad(ISD::EXTLOAD, Node->getValueType(0),
1212 Tmp1, Tmp2, Node->getOperand(2), SrcVT);
1214 if (Node->getOpcode() == ISD::SEXTLOAD)
1215 ValRes = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(),
1216 Result, DAG.getValueType(SrcVT));
1218 ValRes = DAG.getZeroExtendInReg(Result, SrcVT);
1219 Result = LegalizeOp(Result); // Relegalize new nodes.
1220 ValRes = LegalizeOp(ValRes); // Relegalize new nodes.
1221 AddLegalizedOperand(SDOperand(Node, 0), ValRes);
1222 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
1224 return Result.getValue(1);
1227 assert(0 && "Unreachable");
1229 case ISD::EXTRACT_ELEMENT: {
1230 MVT::ValueType OpTy = Node->getOperand(0).getValueType();
1231 switch (getTypeAction(OpTy)) {
1233 assert(0 && "EXTRACT_ELEMENT action for type unimplemented!");
1236 if (cast<ConstantSDNode>(Node->getOperand(1))->getValue()) {
1238 Result = DAG.getNode(ISD::SRL, OpTy, Node->getOperand(0),
1239 DAG.getConstant(MVT::getSizeInBits(OpTy)/2,
1240 TLI.getShiftAmountTy()));
1241 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), Result);
1244 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0),
1245 Node->getOperand(0));
1247 Result = LegalizeOp(Result);
1250 // Get both the low and high parts.
1251 ExpandOp(Node->getOperand(0), Tmp1, Tmp2);
1252 if (cast<ConstantSDNode>(Node->getOperand(1))->getValue())
1253 Result = Tmp2; // 1 -> Hi
1255 Result = Tmp1; // 0 -> Lo
1261 case ISD::CopyToReg:
1262 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1264 assert(isTypeLegal(Node->getOperand(2).getValueType()) &&
1265 "Register type must be legal!");
1266 // Legalize the incoming value (must be a legal type).
1267 Tmp2 = LegalizeOp(Node->getOperand(2));
1268 if (Node->getNumValues() == 1) {
1269 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(2))
1270 Result = DAG.getNode(ISD::CopyToReg, MVT::Other, Tmp1,
1271 Node->getOperand(1), Tmp2);
1273 assert(Node->getNumValues() == 2 && "Unknown CopyToReg");
1274 if (Node->getNumOperands() == 4)
1275 Tmp3 = LegalizeOp(Node->getOperand(3));
1276 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(2) ||
1277 (Node->getNumOperands() == 4 && Tmp3 != Node->getOperand(3))) {
1278 unsigned Reg = cast<RegisterSDNode>(Node->getOperand(1))->getReg();
1279 Result = DAG.getCopyToReg(Tmp1, Reg, Tmp2, Tmp3);
1282 // Since this produces two values, make sure to remember that we legalized
1284 AddLegalizedOperand(SDOperand(Node, 0), Result);
1285 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
1286 return Result.getValue(Op.ResNo);
1291 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1292 switch (Node->getNumOperands()) {
1294 switch (getTypeAction(Node->getOperand(1).getValueType())) {
1296 Tmp2 = LegalizeOp(Node->getOperand(1));
1297 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1))
1298 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Tmp2);
1302 ExpandOp(Node->getOperand(1), Lo, Hi);
1303 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Hi);
1307 Tmp2 = PromoteOp(Node->getOperand(1));
1308 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Tmp2);
1313 if (Tmp1 != Node->getOperand(0))
1314 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1);
1316 default: { // ret <values>
1317 std::vector<SDOperand> NewValues;
1318 NewValues.push_back(Tmp1);
1319 for (unsigned i = 1, e = Node->getNumOperands(); i != e; ++i)
1320 switch (getTypeAction(Node->getOperand(i).getValueType())) {
1322 NewValues.push_back(LegalizeOp(Node->getOperand(i)));
1326 ExpandOp(Node->getOperand(i), Lo, Hi);
1327 NewValues.push_back(Lo);
1328 NewValues.push_back(Hi);
1332 assert(0 && "Can't promote multiple return value yet!");
1334 Result = DAG.getNode(ISD::RET, MVT::Other, NewValues);
1339 switch (TLI.getOperationAction(Node->getOpcode(),
1340 Node->getValueType(0))) {
1341 default: assert(0 && "This action is not supported yet!");
1342 case TargetLowering::Custom: {
1343 SDOperand Tmp = TLI.LowerOperation(Result, DAG);
1345 Result = LegalizeOp(Tmp);
1348 // FALLTHROUGH if the target thinks it is legal.
1350 case TargetLowering::Legal:
1356 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1357 Tmp2 = LegalizeOp(Node->getOperand(2)); // Legalize the pointer.
1359 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr'
1360 if (ConstantFPSDNode *CFP =dyn_cast<ConstantFPSDNode>(Node->getOperand(1))){
1361 if (CFP->getValueType(0) == MVT::f32) {
1362 Result = DAG.getNode(ISD::STORE, MVT::Other, Tmp1,
1363 DAG.getConstant(FloatToBits(CFP->getValue()),
1366 Node->getOperand(3));
1368 assert(CFP->getValueType(0) == MVT::f64 && "Unknown FP type!");
1369 Result = DAG.getNode(ISD::STORE, MVT::Other, Tmp1,
1370 DAG.getConstant(DoubleToBits(CFP->getValue()),
1373 Node->getOperand(3));
1375 Result = LegalizeOp(Result);
1379 switch (getTypeAction(Node->getOperand(1).getValueType())) {
1381 SDOperand Val = LegalizeOp(Node->getOperand(1));
1382 if (Val != Node->getOperand(1) || Tmp1 != Node->getOperand(0) ||
1383 Tmp2 != Node->getOperand(2))
1384 Result = DAG.getNode(ISD::STORE, MVT::Other, Tmp1, Val, Tmp2,
1385 Node->getOperand(3));
1387 MVT::ValueType VT = Result.Val->getOperand(1).getValueType();
1388 switch (TLI.getOperationAction(Result.Val->getOpcode(), VT)) {
1389 default: assert(0 && "This action is not supported yet!");
1390 case TargetLowering::Custom: {
1391 SDOperand Tmp = TLI.LowerOperation(Result, DAG);
1393 Result = LegalizeOp(Tmp);
1396 // FALLTHROUGH if the target thinks it is legal.
1398 case TargetLowering::Legal:
1405 // Truncate the value and store the result.
1406 Tmp3 = PromoteOp(Node->getOperand(1));
1407 Result = DAG.getNode(ISD::TRUNCSTORE, MVT::Other, Tmp1, Tmp3, Tmp2,
1408 Node->getOperand(3),
1409 DAG.getValueType(Node->getOperand(1).getValueType()));
1414 unsigned IncrementSize;
1415 ExpandOp(Node->getOperand(1), Lo, Hi);
1417 if (!TLI.isLittleEndian())
1420 Lo = DAG.getNode(ISD::STORE, MVT::Other, Tmp1, Lo, Tmp2,
1421 Node->getOperand(3));
1422 // If this is a vector type, then we have to calculate the increment as
1423 // the product of the element size in bytes, and the number of elements
1424 // in the high half of the vector.
1425 if (MVT::Vector == Hi.getValueType()) {
1426 unsigned NumElems = cast<ConstantSDNode>(Hi.getOperand(2))->getValue();
1427 MVT::ValueType EVT = cast<VTSDNode>(Hi.getOperand(3))->getVT();
1428 IncrementSize = NumElems * MVT::getSizeInBits(EVT)/8;
1430 IncrementSize = MVT::getSizeInBits(Hi.getValueType())/8;
1432 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2,
1433 getIntPtrConstant(IncrementSize));
1434 assert(isTypeLegal(Tmp2.getValueType()) &&
1435 "Pointers must be legal!");
1436 //Again, claiming both parts of the store came form the same Instr
1437 Hi = DAG.getNode(ISD::STORE, MVT::Other, Tmp1, Hi, Tmp2,
1438 Node->getOperand(3));
1439 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi);
1445 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1446 if (Tmp1 != Node->getOperand(0))
1447 Result = DAG.getNode(ISD::PCMARKER, MVT::Other, Tmp1,Node->getOperand(1));
1449 case ISD::STACKSAVE:
1450 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1451 if (Tmp1 != Node->getOperand(0)) {
1452 std::vector<MVT::ValueType> VTs;
1453 VTs.push_back(Node->getValueType(0));
1454 VTs.push_back(MVT::Other);
1455 std::vector<SDOperand> Ops;
1456 Ops.push_back(Tmp1);
1457 Result = DAG.getNode(ISD::STACKSAVE, VTs, Ops);
1460 switch (TLI.getOperationAction(ISD::STACKSAVE, MVT::Other)) {
1461 default: assert(0 && "This action is not supported yet!");
1462 case TargetLowering::Custom: {
1463 SDOperand Tmp = TLI.LowerOperation(Result, DAG);
1465 Result = LegalizeOp(Tmp);
1468 // FALLTHROUGH if the target thinks it is legal.
1470 case TargetLowering::Legal:
1471 // Since stacksave produce two values, make sure to remember that we
1472 // legalized both of them.
1473 AddLegalizedOperand(SDOperand(Node, 0), Result);
1474 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
1475 return Result.getValue(Op.ResNo);
1476 case TargetLowering::Expand:
1477 // Expand to CopyFromReg if the target set
1478 // StackPointerRegisterToSaveRestore.
1479 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) {
1480 Tmp1 = DAG.getCopyFromReg(Tmp1, SP,
1481 Node->getValueType(0));
1482 AddLegalizedOperand(SDOperand(Node, 0), Tmp1);
1483 AddLegalizedOperand(SDOperand(Node, 1), Tmp1.getValue(1));
1484 return Tmp1.getValue(Op.ResNo);
1486 Tmp1 = DAG.getNode(ISD::UNDEF, Node->getValueType(0));
1487 AddLegalizedOperand(SDOperand(Node, 0), Tmp1);
1488 AddLegalizedOperand(SDOperand(Node, 1), Node->getOperand(0));
1489 return Op.ResNo ? Node->getOperand(0) : Tmp1;
1493 case ISD::STACKRESTORE:
1494 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1495 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
1496 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1))
1497 Result = DAG.getNode(ISD::STACKRESTORE, MVT::Other, Tmp1, Tmp2);
1499 switch (TLI.getOperationAction(ISD::STACKRESTORE, MVT::Other)) {
1500 default: assert(0 && "This action is not supported yet!");
1501 case TargetLowering::Custom: {
1502 SDOperand Tmp = TLI.LowerOperation(Result, DAG);
1504 Result = LegalizeOp(Tmp);
1507 // FALLTHROUGH if the target thinks it is legal.
1509 case TargetLowering::Legal:
1511 case TargetLowering::Expand:
1512 // Expand to CopyToReg if the target set
1513 // StackPointerRegisterToSaveRestore.
1514 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) {
1515 Result = DAG.getCopyToReg(Tmp1, SP, Tmp2);
1523 case ISD::READCYCLECOUNTER:
1524 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain
1525 if (Tmp1 != Node->getOperand(0)) {
1526 std::vector<MVT::ValueType> rtypes;
1527 std::vector<SDOperand> rvals;
1528 rtypes.push_back(MVT::i64);
1529 rtypes.push_back(MVT::Other);
1530 rvals.push_back(Tmp1);
1531 Result = DAG.getNode(ISD::READCYCLECOUNTER, rtypes, rvals);
1534 // Since rdcc produce two values, make sure to remember that we legalized
1536 AddLegalizedOperand(SDOperand(Node, 0), Result);
1537 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
1538 return Result.getValue(Op.ResNo);
1540 case ISD::TRUNCSTORE: {
1541 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1542 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the pointer.
1544 switch (getTypeAction(Node->getOperand(1).getValueType())) {
1547 assert(0 && "Cannot handle illegal TRUNCSTORE yet!");
1549 Tmp2 = LegalizeOp(Node->getOperand(1));
1551 // The only promote case we handle is TRUNCSTORE:i1 X into
1552 // -> TRUNCSTORE:i8 (and X, 1)
1553 if (cast<VTSDNode>(Node->getOperand(4))->getVT() == MVT::i1 &&
1554 TLI.getOperationAction(ISD::TRUNCSTORE, MVT::i1) ==
1555 TargetLowering::Promote) {
1556 // Promote the bool to a mask then store.
1557 Tmp2 = DAG.getNode(ISD::AND, Tmp2.getValueType(), Tmp2,
1558 DAG.getConstant(1, Tmp2.getValueType()));
1559 Result = DAG.getNode(ISD::TRUNCSTORE, MVT::Other, Tmp1, Tmp2, Tmp3,
1560 Node->getOperand(3), DAG.getValueType(MVT::i8));
1562 } else if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1) ||
1563 Tmp3 != Node->getOperand(2)) {
1564 Result = DAG.getNode(ISD::TRUNCSTORE, MVT::Other, Tmp1, Tmp2, Tmp3,
1565 Node->getOperand(3), Node->getOperand(4));
1568 MVT::ValueType StVT = cast<VTSDNode>(Result.Val->getOperand(4))->getVT();
1569 switch (TLI.getOperationAction(Result.Val->getOpcode(), StVT)) {
1570 default: assert(0 && "This action is not supported yet!");
1571 case TargetLowering::Custom: {
1572 SDOperand Tmp = TLI.LowerOperation(Result, DAG);
1574 Result = LegalizeOp(Tmp);
1577 // FALLTHROUGH if the target thinks it is legal.
1579 case TargetLowering::Legal:
1588 switch (getTypeAction(Node->getOperand(0).getValueType())) {
1589 case Expand: assert(0 && "It's impossible to expand bools");
1591 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the condition.
1594 Tmp1 = PromoteOp(Node->getOperand(0)); // Promote the condition.
1597 Tmp2 = LegalizeOp(Node->getOperand(1)); // TrueVal
1598 Tmp3 = LegalizeOp(Node->getOperand(2)); // FalseVal
1600 switch (TLI.getOperationAction(ISD::SELECT, Tmp2.getValueType())) {
1601 default: assert(0 && "This action is not supported yet!");
1602 case TargetLowering::Expand:
1603 if (Tmp1.getOpcode() == ISD::SETCC) {
1604 Result = DAG.getSelectCC(Tmp1.getOperand(0), Tmp1.getOperand(1),
1606 cast<CondCodeSDNode>(Tmp1.getOperand(2))->get());
1608 // Make sure the condition is either zero or one. It may have been
1609 // promoted from something else.
1610 Tmp1 = DAG.getZeroExtendInReg(Tmp1, MVT::i1);
1611 Result = DAG.getSelectCC(Tmp1,
1612 DAG.getConstant(0, Tmp1.getValueType()),
1613 Tmp2, Tmp3, ISD::SETNE);
1615 Result = LegalizeOp(Result); // Relegalize new nodes.
1617 case TargetLowering::Custom: {
1619 TLI.LowerOperation(DAG.getNode(ISD::SELECT, Node->getValueType(0),
1620 Tmp1, Tmp2, Tmp3), DAG);
1622 Result = LegalizeOp(Tmp);
1625 // FALLTHROUGH if the target thinks it is legal.
1627 case TargetLowering::Legal:
1628 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1) ||
1629 Tmp3 != Node->getOperand(2))
1630 Result = DAG.getNode(ISD::SELECT, Node->getValueType(0),
1633 case TargetLowering::Promote: {
1634 MVT::ValueType NVT =
1635 TLI.getTypeToPromoteTo(ISD::SELECT, Tmp2.getValueType());
1636 unsigned ExtOp, TruncOp;
1637 if (MVT::isInteger(Tmp2.getValueType())) {
1638 ExtOp = ISD::ANY_EXTEND;
1639 TruncOp = ISD::TRUNCATE;
1641 ExtOp = ISD::FP_EXTEND;
1642 TruncOp = ISD::FP_ROUND;
1644 // Promote each of the values to the new type.
1645 Tmp2 = DAG.getNode(ExtOp, NVT, Tmp2);
1646 Tmp3 = DAG.getNode(ExtOp, NVT, Tmp3);
1647 // Perform the larger operation, then round down.
1648 Result = DAG.getNode(ISD::SELECT, NVT, Tmp1, Tmp2,Tmp3);
1649 Result = DAG.getNode(TruncOp, Node->getValueType(0), Result);
1650 Result = LegalizeOp(Result);
1655 case ISD::SELECT_CC:
1656 Tmp3 = LegalizeOp(Node->getOperand(2)); // True
1657 Tmp4 = LegalizeOp(Node->getOperand(3)); // False
1659 if (isTypeLegal(Node->getOperand(0).getValueType())) {
1660 // Everything is legal, see if we should expand this op or something.
1661 switch (TLI.getOperationAction(ISD::SELECT_CC,
1662 Node->getOperand(0).getValueType())) {
1663 default: assert(0 && "This action is not supported yet!");
1664 case TargetLowering::Custom: {
1666 TLI.LowerOperation(DAG.getNode(ISD::SELECT_CC, Node->getValueType(0),
1667 Node->getOperand(0),
1668 Node->getOperand(1), Tmp3, Tmp4,
1669 Node->getOperand(4)), DAG);
1671 Result = LegalizeOp(Tmp);
1674 } // FALLTHROUGH if the target can't lower this operation after all.
1675 case TargetLowering::Legal:
1676 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
1677 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS
1678 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1) ||
1679 Tmp3 != Node->getOperand(2) || Tmp4 != Node->getOperand(3)) {
1680 Result = DAG.getNode(ISD::SELECT_CC, Node->getValueType(0), Tmp1,Tmp2,
1681 Tmp3, Tmp4, Node->getOperand(4));
1687 Tmp1 = LegalizeOp(DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(),
1688 Node->getOperand(0), // LHS
1689 Node->getOperand(1), // RHS
1690 Node->getOperand(4)));
1691 // If we get a SETCC back from legalizing the SETCC node we just
1692 // created, then use its LHS, RHS, and CC directly in creating a new
1693 // node. Otherwise, select between the true and false value based on
1694 // comparing the result of the legalized with zero.
1695 if (Tmp1.getOpcode() == ISD::SETCC) {
1696 Result = DAG.getNode(ISD::SELECT_CC, Tmp3.getValueType(),
1697 Tmp1.getOperand(0), Tmp1.getOperand(1),
1698 Tmp3, Tmp4, Tmp1.getOperand(2));
1700 Result = DAG.getSelectCC(Tmp1,
1701 DAG.getConstant(0, Tmp1.getValueType()),
1702 Tmp3, Tmp4, ISD::SETNE);
1707 switch (getTypeAction(Node->getOperand(0).getValueType())) {
1709 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
1710 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS
1713 Tmp1 = PromoteOp(Node->getOperand(0)); // LHS
1714 Tmp2 = PromoteOp(Node->getOperand(1)); // RHS
1716 // If this is an FP compare, the operands have already been extended.
1717 if (MVT::isInteger(Node->getOperand(0).getValueType())) {
1718 MVT::ValueType VT = Node->getOperand(0).getValueType();
1719 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT);
1721 // Otherwise, we have to insert explicit sign or zero extends. Note
1722 // that we could insert sign extends for ALL conditions, but zero extend
1723 // is cheaper on many machines (an AND instead of two shifts), so prefer
1725 switch (cast<CondCodeSDNode>(Node->getOperand(2))->get()) {
1726 default: assert(0 && "Unknown integer comparison!");
1733 // ALL of these operations will work if we either sign or zero extend
1734 // the operands (including the unsigned comparisons!). Zero extend is
1735 // usually a simpler/cheaper operation, so prefer it.
1736 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT);
1737 Tmp2 = DAG.getZeroExtendInReg(Tmp2, VT);
1743 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1,
1744 DAG.getValueType(VT));
1745 Tmp2 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp2,
1746 DAG.getValueType(VT));
1752 SDOperand LHSLo, LHSHi, RHSLo, RHSHi;
1753 ExpandOp(Node->getOperand(0), LHSLo, LHSHi);
1754 ExpandOp(Node->getOperand(1), RHSLo, RHSHi);
1755 switch (cast<CondCodeSDNode>(Node->getOperand(2))->get()) {
1759 if (ConstantSDNode *RHSCST = dyn_cast<ConstantSDNode>(RHSLo))
1760 if (RHSCST->isAllOnesValue()) {
1761 // Comparison to -1.
1762 Tmp1 = DAG.getNode(ISD::AND, LHSLo.getValueType(), LHSLo, LHSHi);
1767 Tmp1 = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSLo, RHSLo);
1768 Tmp2 = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSHi, RHSHi);
1769 Tmp1 = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp2);
1770 Tmp2 = DAG.getConstant(0, Tmp1.getValueType());
1773 // If this is a comparison of the sign bit, just look at the top part.
1775 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Node->getOperand(1)))
1776 if ((cast<CondCodeSDNode>(Node->getOperand(2))->get() == ISD::SETLT &&
1777 CST->getValue() == 0) || // X < 0
1778 (cast<CondCodeSDNode>(Node->getOperand(2))->get() == ISD::SETGT &&
1779 (CST->isAllOnesValue()))) { // X > -1
1785 // FIXME: This generated code sucks.
1786 ISD::CondCode LowCC;
1787 switch (cast<CondCodeSDNode>(Node->getOperand(2))->get()) {
1788 default: assert(0 && "Unknown integer setcc!");
1790 case ISD::SETULT: LowCC = ISD::SETULT; break;
1792 case ISD::SETUGT: LowCC = ISD::SETUGT; break;
1794 case ISD::SETULE: LowCC = ISD::SETULE; break;
1796 case ISD::SETUGE: LowCC = ISD::SETUGE; break;
1799 // Tmp1 = lo(op1) < lo(op2) // Always unsigned comparison
1800 // Tmp2 = hi(op1) < hi(op2) // Signedness depends on operands
1801 // dest = hi(op1) == hi(op2) ? Tmp1 : Tmp2;
1803 // NOTE: on targets without efficient SELECT of bools, we can always use
1804 // this identity: (B1 ? B2 : B3) --> (B1 & B2)|(!B1&B3)
1805 Tmp1 = DAG.getSetCC(Node->getValueType(0), LHSLo, RHSLo, LowCC);
1806 Tmp2 = DAG.getNode(ISD::SETCC, Node->getValueType(0), LHSHi, RHSHi,
1807 Node->getOperand(2));
1808 Result = DAG.getSetCC(Node->getValueType(0), LHSHi, RHSHi, ISD::SETEQ);
1809 Result = LegalizeOp(DAG.getNode(ISD::SELECT, Tmp1.getValueType(),
1810 Result, Tmp1, Tmp2));
1811 AddLegalizedOperand(SDOperand(Node, 0), Result);
1816 switch(TLI.getOperationAction(ISD::SETCC,
1817 Node->getOperand(0).getValueType())) {
1819 assert(0 && "Cannot handle this action for SETCC yet!");
1821 case TargetLowering::Promote: {
1822 // First step, figure out the appropriate operation to use.
1823 // Allow SETCC to not be supported for all legal data types
1824 // Mostly this targets FP
1825 MVT::ValueType NewInTy = Node->getOperand(0).getValueType();
1826 MVT::ValueType OldVT = NewInTy;
1828 // Scan for the appropriate larger type to use.
1830 NewInTy = (MVT::ValueType)(NewInTy+1);
1832 assert(MVT::isInteger(NewInTy) == MVT::isInteger(OldVT) &&
1833 "Fell off of the edge of the integer world");
1834 assert(MVT::isFloatingPoint(NewInTy) == MVT::isFloatingPoint(OldVT) &&
1835 "Fell off of the edge of the floating point world");
1837 // If the target supports SETCC of this type, use it.
1838 if (TLI.isOperationLegal(ISD::SETCC, NewInTy))
1841 if (MVT::isInteger(NewInTy))
1842 assert(0 && "Cannot promote Legal Integer SETCC yet");
1844 Tmp1 = DAG.getNode(ISD::FP_EXTEND, NewInTy, Tmp1);
1845 Tmp2 = DAG.getNode(ISD::FP_EXTEND, NewInTy, Tmp2);
1848 Result = DAG.getNode(ISD::SETCC, Node->getValueType(0), Tmp1, Tmp2,
1849 Node->getOperand(2));
1850 Result = LegalizeOp(Result);
1853 case TargetLowering::Custom: {
1855 TLI.LowerOperation(DAG.getNode(ISD::SETCC, Node->getValueType(0),
1856 Tmp1, Tmp2, Node->getOperand(2)), DAG);
1858 Result = LegalizeOp(Tmp);
1861 // FALLTHROUGH if the target thinks it is legal.
1863 case TargetLowering::Legal:
1864 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1))
1865 Result = DAG.getNode(ISD::SETCC, Node->getValueType(0), Tmp1, Tmp2,
1866 Node->getOperand(2));
1868 case TargetLowering::Expand:
1869 // Expand a setcc node into a select_cc of the same condition, lhs, and
1870 // rhs that selects between const 1 (true) and const 0 (false).
1871 MVT::ValueType VT = Node->getValueType(0);
1872 Result = DAG.getNode(ISD::SELECT_CC, VT, Tmp1, Tmp2,
1873 DAG.getConstant(1, VT), DAG.getConstant(0, VT),
1874 Node->getOperand(2));
1875 Result = LegalizeOp(Result);
1882 case ISD::MEMMOVE: {
1883 Tmp1 = LegalizeOp(Node->getOperand(0)); // Chain
1884 Tmp2 = LegalizeOp(Node->getOperand(1)); // Pointer
1886 if (Node->getOpcode() == ISD::MEMSET) { // memset = ubyte
1887 switch (getTypeAction(Node->getOperand(2).getValueType())) {
1888 case Expand: assert(0 && "Cannot expand a byte!");
1890 Tmp3 = LegalizeOp(Node->getOperand(2));
1893 Tmp3 = PromoteOp(Node->getOperand(2));
1897 Tmp3 = LegalizeOp(Node->getOperand(2)); // memcpy/move = pointer,
1901 switch (getTypeAction(Node->getOperand(3).getValueType())) {
1903 // Length is too big, just take the lo-part of the length.
1905 ExpandOp(Node->getOperand(3), HiPart, Tmp4);
1909 Tmp4 = LegalizeOp(Node->getOperand(3));
1912 Tmp4 = PromoteOp(Node->getOperand(3));
1917 switch (getTypeAction(Node->getOperand(4).getValueType())) { // uint
1918 case Expand: assert(0 && "Cannot expand this yet!");
1920 Tmp5 = LegalizeOp(Node->getOperand(4));
1923 Tmp5 = PromoteOp(Node->getOperand(4));
1927 switch (TLI.getOperationAction(Node->getOpcode(), MVT::Other)) {
1928 default: assert(0 && "This action not implemented for this operation!");
1929 case TargetLowering::Custom: {
1931 TLI.LowerOperation(DAG.getNode(Node->getOpcode(), MVT::Other, Tmp1,
1932 Tmp2, Tmp3, Tmp4, Tmp5), DAG);
1934 Result = LegalizeOp(Tmp);
1937 // FALLTHROUGH if the target thinks it is legal.
1939 case TargetLowering::Legal:
1940 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1) ||
1941 Tmp3 != Node->getOperand(2) || Tmp4 != Node->getOperand(3) ||
1942 Tmp5 != Node->getOperand(4)) {
1943 std::vector<SDOperand> Ops;
1944 Ops.push_back(Tmp1); Ops.push_back(Tmp2); Ops.push_back(Tmp3);
1945 Ops.push_back(Tmp4); Ops.push_back(Tmp5);
1946 Result = DAG.getNode(Node->getOpcode(), MVT::Other, Ops);
1949 case TargetLowering::Expand: {
1950 // Otherwise, the target does not support this operation. Lower the
1951 // operation to an explicit libcall as appropriate.
1952 MVT::ValueType IntPtr = TLI.getPointerTy();
1953 const Type *IntPtrTy = TLI.getTargetData().getIntPtrType();
1954 std::vector<std::pair<SDOperand, const Type*> > Args;
1956 const char *FnName = 0;
1957 if (Node->getOpcode() == ISD::MEMSET) {
1958 Args.push_back(std::make_pair(Tmp2, IntPtrTy));
1959 // Extend the ubyte argument to be an int value for the call.
1960 Tmp3 = DAG.getNode(ISD::ZERO_EXTEND, MVT::i32, Tmp3);
1961 Args.push_back(std::make_pair(Tmp3, Type::IntTy));
1962 Args.push_back(std::make_pair(Tmp4, IntPtrTy));
1965 } else if (Node->getOpcode() == ISD::MEMCPY ||
1966 Node->getOpcode() == ISD::MEMMOVE) {
1967 Args.push_back(std::make_pair(Tmp2, IntPtrTy));
1968 Args.push_back(std::make_pair(Tmp3, IntPtrTy));
1969 Args.push_back(std::make_pair(Tmp4, IntPtrTy));
1970 FnName = Node->getOpcode() == ISD::MEMMOVE ? "memmove" : "memcpy";
1972 assert(0 && "Unknown op!");
1975 std::pair<SDOperand,SDOperand> CallResult =
1976 TLI.LowerCallTo(Tmp1, Type::VoidTy, false, CallingConv::C, false,
1977 DAG.getExternalSymbol(FnName, IntPtr), Args, DAG);
1978 Result = LegalizeOp(CallResult.second);
1986 Tmp1 = LegalizeOp(Node->getOperand(0));
1987 Tmp2 = LegalizeOp(Node->getOperand(1));
1989 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1)) {
1990 std::vector<MVT::ValueType> VTs(Node->value_begin(), Node->value_end());
1991 std::vector<SDOperand> Ops;
1992 Ops.push_back(Tmp1);
1993 Ops.push_back(Tmp2);
1994 Result = DAG.getNode(ISD::READPORT, VTs, Ops);
1996 Result = SDOperand(Node, 0);
1997 // Since these produce two values, make sure to remember that we legalized
1999 AddLegalizedOperand(SDOperand(Node, 0), Result);
2000 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
2001 return Result.getValue(Op.ResNo);
2002 case ISD::WRITEPORT:
2003 Tmp1 = LegalizeOp(Node->getOperand(0));
2004 Tmp2 = LegalizeOp(Node->getOperand(1));
2005 Tmp3 = LegalizeOp(Node->getOperand(2));
2006 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1) ||
2007 Tmp3 != Node->getOperand(2))
2008 Result = DAG.getNode(Node->getOpcode(), MVT::Other, Tmp1, Tmp2, Tmp3);
2012 Tmp1 = LegalizeOp(Node->getOperand(0));
2013 Tmp2 = LegalizeOp(Node->getOperand(1));
2015 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
2016 case TargetLowering::Custom:
2017 default: assert(0 && "This action not implemented for this operation!");
2018 case TargetLowering::Legal:
2019 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1)) {
2020 std::vector<MVT::ValueType> VTs(Node->value_begin(), Node->value_end());
2021 std::vector<SDOperand> Ops;
2022 Ops.push_back(Tmp1);
2023 Ops.push_back(Tmp2);
2024 Result = DAG.getNode(ISD::READPORT, VTs, Ops);
2026 Result = SDOperand(Node, 0);
2028 case TargetLowering::Expand:
2029 // Replace this with a load from memory.
2030 Result = DAG.getLoad(Node->getValueType(0), Node->getOperand(0),
2031 Node->getOperand(1), DAG.getSrcValue(NULL));
2032 Result = LegalizeOp(Result);
2036 // Since these produce two values, make sure to remember that we legalized
2038 AddLegalizedOperand(SDOperand(Node, 0), Result);
2039 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
2040 return Result.getValue(Op.ResNo);
2043 Tmp1 = LegalizeOp(Node->getOperand(0));
2044 Tmp2 = LegalizeOp(Node->getOperand(1));
2045 Tmp3 = LegalizeOp(Node->getOperand(2));
2047 switch (TLI.getOperationAction(Node->getOpcode(),
2048 Node->getOperand(1).getValueType())) {
2049 case TargetLowering::Custom:
2050 default: assert(0 && "This action not implemented for this operation!");
2051 case TargetLowering::Legal:
2052 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1) ||
2053 Tmp3 != Node->getOperand(2))
2054 Result = DAG.getNode(Node->getOpcode(), MVT::Other, Tmp1, Tmp2, Tmp3);
2056 case TargetLowering::Expand:
2057 // Replace this with a store to memory.
2058 Result = DAG.getNode(ISD::STORE, MVT::Other, Node->getOperand(0),
2059 Node->getOperand(1), Node->getOperand(2),
2060 DAG.getSrcValue(NULL));
2061 Result = LegalizeOp(Result);
2066 case ISD::ADD_PARTS:
2067 case ISD::SUB_PARTS:
2068 case ISD::SHL_PARTS:
2069 case ISD::SRA_PARTS:
2070 case ISD::SRL_PARTS: {
2071 std::vector<SDOperand> Ops;
2072 bool Changed = false;
2073 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
2074 Ops.push_back(LegalizeOp(Node->getOperand(i)));
2075 Changed |= Ops.back() != Node->getOperand(i);
2078 std::vector<MVT::ValueType> VTs(Node->value_begin(), Node->value_end());
2079 Result = DAG.getNode(Node->getOpcode(), VTs, Ops);
2082 switch (TLI.getOperationAction(Node->getOpcode(),
2083 Node->getValueType(0))) {
2084 default: assert(0 && "This action is not supported yet!");
2085 case TargetLowering::Custom: {
2086 SDOperand Tmp = TLI.LowerOperation(Result, DAG);
2088 SDOperand Tmp2, RetVal(0,0);
2089 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) {
2090 Tmp2 = LegalizeOp(Tmp.getValue(i));
2091 AddLegalizedOperand(SDOperand(Node, i), Tmp2);
2095 assert(RetVal.Val && "Illegal result number");
2098 // FALLTHROUGH if the target thinks it is legal.
2100 case TargetLowering::Legal:
2105 // Since these produce multiple values, make sure to remember that we
2106 // legalized all of them.
2107 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
2108 AddLegalizedOperand(SDOperand(Node, i), Result.getValue(i));
2109 return Result.getValue(Op.ResNo);
2130 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
2131 switch (getTypeAction(Node->getOperand(1).getValueType())) {
2132 case Expand: assert(0 && "Not possible");
2134 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the RHS.
2137 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the RHS.
2140 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
2141 case TargetLowering::Custom: {
2142 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1, Tmp2);
2143 SDOperand Tmp = TLI.LowerOperation(Result, DAG);
2145 Tmp = LegalizeOp(Tmp); // Relegalize input.
2146 AddLegalizedOperand(Op, Tmp);
2148 } //else it was considered legal and we fall through
2150 case TargetLowering::Legal:
2151 if (Tmp1 != Node->getOperand(0) ||
2152 Tmp2 != Node->getOperand(1))
2153 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1,Tmp2);
2156 assert(0 && "Operation not supported");
2160 case ISD::BUILD_PAIR: {
2161 MVT::ValueType PairTy = Node->getValueType(0);
2162 // TODO: handle the case where the Lo and Hi operands are not of legal type
2163 Tmp1 = LegalizeOp(Node->getOperand(0)); // Lo
2164 Tmp2 = LegalizeOp(Node->getOperand(1)); // Hi
2165 switch (TLI.getOperationAction(ISD::BUILD_PAIR, PairTy)) {
2166 case TargetLowering::Legal:
2167 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1))
2168 Result = DAG.getNode(ISD::BUILD_PAIR, PairTy, Tmp1, Tmp2);
2170 case TargetLowering::Promote:
2171 case TargetLowering::Custom:
2172 assert(0 && "Cannot promote/custom this yet!");
2173 case TargetLowering::Expand:
2174 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, PairTy, Tmp1);
2175 Tmp2 = DAG.getNode(ISD::ANY_EXTEND, PairTy, Tmp2);
2176 Tmp2 = DAG.getNode(ISD::SHL, PairTy, Tmp2,
2177 DAG.getConstant(MVT::getSizeInBits(PairTy)/2,
2178 TLI.getShiftAmountTy()));
2179 Result = LegalizeOp(DAG.getNode(ISD::OR, PairTy, Tmp1, Tmp2));
2188 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
2189 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS
2190 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
2191 case TargetLowering::Custom: {
2192 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1,Tmp2);
2193 SDOperand Tmp = TLI.LowerOperation(Result, DAG);
2195 Tmp = LegalizeOp(Tmp); // Relegalize input.
2196 AddLegalizedOperand(Op, Tmp);
2198 } //else it was considered legal and we fall through
2200 case TargetLowering::Legal:
2201 if (Tmp1 != Node->getOperand(0) ||
2202 Tmp2 != Node->getOperand(1))
2203 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1,
2206 case TargetLowering::Promote:
2207 assert(0 && "Cannot promote handle this yet!");
2208 case TargetLowering::Expand:
2209 if (MVT::isInteger(Node->getValueType(0))) {
2210 MVT::ValueType VT = Node->getValueType(0);
2211 unsigned Opc = (Node->getOpcode() == ISD::UREM) ? ISD::UDIV : ISD::SDIV;
2212 Result = DAG.getNode(Opc, VT, Tmp1, Tmp2);
2213 Result = DAG.getNode(ISD::MUL, VT, Result, Tmp2);
2214 Result = DAG.getNode(ISD::SUB, VT, Tmp1, Result);
2216 // Floating point mod -> fmod libcall.
2217 const char *FnName = Node->getValueType(0) == MVT::f32 ? "fmodf":"fmod";
2219 Result = ExpandLibCall(FnName, Node, Dummy);
2227 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
2228 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS
2229 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
2230 case TargetLowering::Custom:
2231 case TargetLowering::Promote:
2232 case TargetLowering::Expand:
2233 assert(0 && "Cannot handle this yet!");
2234 case TargetLowering::Legal:
2235 if (Tmp1 != Node->getOperand(0) ||
2236 Tmp2 != Node->getOperand(1))
2237 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1,
2244 Tmp1 = LegalizeOp(Node->getOperand(0)); // Op
2245 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
2246 case TargetLowering::Legal:
2247 if (Tmp1 != Node->getOperand(0))
2248 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1);
2250 case TargetLowering::Promote: {
2251 MVT::ValueType OVT = Tmp1.getValueType();
2252 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
2253 unsigned DiffBits = getSizeInBits(NVT) - getSizeInBits(OVT);
2255 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1);
2256 Tmp1 = DAG.getNode(ISD::BSWAP, NVT, Tmp1);
2257 Result = DAG.getNode(ISD::SRL, NVT, Tmp1,
2258 DAG.getConstant(DiffBits, TLI.getShiftAmountTy()));
2259 Result = LegalizeOp(Result);
2262 case TargetLowering::Custom:
2263 assert(0 && "Cannot custom legalize this yet!");
2264 case TargetLowering::Expand: {
2265 MVT::ValueType VT = Tmp1.getValueType();
2267 default: assert(0 && "Unhandled Expand type in BSWAP!"); abort();
2269 Tmp2 = DAG.getNode(ISD::SHL, VT, Tmp1,
2270 DAG.getConstant(8, TLI.getShiftAmountTy()));
2271 Tmp1 = DAG.getNode(ISD::SRL, VT, Tmp1,
2272 DAG.getConstant(8, TLI.getShiftAmountTy()));
2273 Result = DAG.getNode(ISD::OR, VT, Tmp1, Tmp2);
2276 Tmp4 = DAG.getNode(ISD::SHL, VT, Tmp1,
2277 DAG.getConstant(24, TLI.getShiftAmountTy()));
2278 Tmp3 = DAG.getNode(ISD::SHL, VT, Tmp1,
2279 DAG.getConstant(8, TLI.getShiftAmountTy()));
2280 Tmp2 = DAG.getNode(ISD::SRL, VT, Tmp1,
2281 DAG.getConstant(8, TLI.getShiftAmountTy()));
2282 Tmp1 = DAG.getNode(ISD::SRL, VT, Tmp1,
2283 DAG.getConstant(24, TLI.getShiftAmountTy()));
2284 Tmp3 = DAG.getNode(ISD::AND, VT, Tmp3, DAG.getConstant(0xFF0000, VT));
2285 Tmp2 = DAG.getNode(ISD::AND, VT, Tmp2, DAG.getConstant(0xFF00, VT));
2286 Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp3);
2287 Tmp2 = DAG.getNode(ISD::OR, VT, Tmp2, Tmp1);
2288 Result = DAG.getNode(ISD::OR, VT, Tmp4, Tmp2);
2291 SDOperand Tmp5, Tmp6, Tmp7, Tmp8;
2292 Tmp8 = DAG.getNode(ISD::SHL, VT, Tmp1,
2293 DAG.getConstant(56, TLI.getShiftAmountTy()));
2294 Tmp7 = DAG.getNode(ISD::SHL, VT, Tmp1,
2295 DAG.getConstant(40, TLI.getShiftAmountTy()));
2296 Tmp6 = DAG.getNode(ISD::SHL, VT, Tmp1,
2297 DAG.getConstant(24, TLI.getShiftAmountTy()));
2298 Tmp5 = DAG.getNode(ISD::SHL, VT, Tmp1,
2299 DAG.getConstant(8, TLI.getShiftAmountTy()));
2300 Tmp4 = DAG.getNode(ISD::SRL, VT, Tmp1,
2301 DAG.getConstant(8, TLI.getShiftAmountTy()));
2302 Tmp3 = DAG.getNode(ISD::SRL, VT, Tmp1,
2303 DAG.getConstant(24, TLI.getShiftAmountTy()));
2304 Tmp2 = DAG.getNode(ISD::SRL, VT, Tmp1,
2305 DAG.getConstant(40, TLI.getShiftAmountTy()));
2306 Tmp1 = DAG.getNode(ISD::SRL, VT, Tmp1,
2307 DAG.getConstant(56, TLI.getShiftAmountTy()));
2308 Tmp7 = DAG.getNode(ISD::AND, VT, Tmp7,
2309 DAG.getConstant(0x00FF000000000000ULL, VT));
2310 Tmp6 = DAG.getNode(ISD::AND, VT, Tmp7,
2311 DAG.getConstant(0x0000FF0000000000ULL, VT));
2312 Tmp5 = DAG.getNode(ISD::AND, VT, Tmp7,
2313 DAG.getConstant(0x000000FF00000000ULL, VT));
2314 Tmp4 = DAG.getNode(ISD::AND, VT, Tmp7,
2315 DAG.getConstant(0x00000000FF000000ULL, VT));
2316 Tmp3 = DAG.getNode(ISD::AND, VT, Tmp7,
2317 DAG.getConstant(0x0000000000FF0000ULL, VT));
2318 Tmp2 = DAG.getNode(ISD::AND, VT, Tmp7,
2319 DAG.getConstant(0x000000000000FF00ULL, VT));
2320 Tmp8 = DAG.getNode(ISD::OR, VT, Tmp8, Tmp7);
2321 Tmp6 = DAG.getNode(ISD::OR, VT, Tmp6, Tmp5);
2322 Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp3);
2323 Tmp2 = DAG.getNode(ISD::OR, VT, Tmp2, Tmp1);
2324 Tmp8 = DAG.getNode(ISD::OR, VT, Tmp8, Tmp6);
2325 Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp2);
2326 Result = DAG.getNode(ISD::OR, VT, Tmp8, Tmp4);
2330 Result = LegalizeOp(Result);
2339 Tmp1 = LegalizeOp(Node->getOperand(0)); // Op
2340 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
2341 case TargetLowering::Legal:
2342 if (Tmp1 != Node->getOperand(0))
2343 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1);
2345 case TargetLowering::Promote: {
2346 MVT::ValueType OVT = Tmp1.getValueType();
2347 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
2349 // Zero extend the argument.
2350 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1);
2351 // Perform the larger operation, then subtract if needed.
2352 Tmp1 = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1);
2353 switch(Node->getOpcode())
2359 //if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT)
2360 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), Tmp1,
2361 DAG.getConstant(getSizeInBits(NVT), NVT),
2363 Result = DAG.getNode(ISD::SELECT, NVT, Tmp2,
2364 DAG.getConstant(getSizeInBits(OVT),NVT), Tmp1);
2367 //Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT))
2368 Result = DAG.getNode(ISD::SUB, NVT, Tmp1,
2369 DAG.getConstant(getSizeInBits(NVT) -
2370 getSizeInBits(OVT), NVT));
2373 Result = LegalizeOp(Result);
2376 case TargetLowering::Custom:
2377 assert(0 && "Cannot custom handle this yet!");
2378 case TargetLowering::Expand:
2379 switch(Node->getOpcode())
2382 static const uint64_t mask[6] = {
2383 0x5555555555555555ULL, 0x3333333333333333ULL,
2384 0x0F0F0F0F0F0F0F0FULL, 0x00FF00FF00FF00FFULL,
2385 0x0000FFFF0000FFFFULL, 0x00000000FFFFFFFFULL
2387 MVT::ValueType VT = Tmp1.getValueType();
2388 MVT::ValueType ShVT = TLI.getShiftAmountTy();
2389 unsigned len = getSizeInBits(VT);
2390 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) {
2391 //x = (x & mask[i][len/8]) + (x >> (1 << i) & mask[i][len/8])
2392 Tmp2 = DAG.getConstant(mask[i], VT);
2393 Tmp3 = DAG.getConstant(1ULL << i, ShVT);
2394 Tmp1 = DAG.getNode(ISD::ADD, VT,
2395 DAG.getNode(ISD::AND, VT, Tmp1, Tmp2),
2396 DAG.getNode(ISD::AND, VT,
2397 DAG.getNode(ISD::SRL, VT, Tmp1, Tmp3),
2400 Result = LegalizeOp(Tmp1);
2404 /* for now, we do this:
2409 x = x | (x >>32); // for 64-bit input
2410 return popcount(~x);
2412 but see also: http://www.hackersdelight.org/HDcode/nlz.cc */
2413 MVT::ValueType VT = Tmp1.getValueType();
2414 MVT::ValueType ShVT = TLI.getShiftAmountTy();
2415 unsigned len = getSizeInBits(VT);
2416 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) {
2417 Tmp3 = DAG.getConstant(1ULL << i, ShVT);
2418 Tmp1 = DAG.getNode(ISD::OR, VT, Tmp1,
2419 DAG.getNode(ISD::SRL, VT, Tmp1, Tmp3));
2421 Tmp3 = DAG.getNode(ISD::XOR, VT, Tmp1, DAG.getConstant(~0ULL, VT));
2422 Result = LegalizeOp(DAG.getNode(ISD::CTPOP, VT, Tmp3));
2426 // for now, we use: { return popcount(~x & (x - 1)); }
2427 // unless the target has ctlz but not ctpop, in which case we use:
2428 // { return 32 - nlz(~x & (x-1)); }
2429 // see also http://www.hackersdelight.org/HDcode/ntz.cc
2430 MVT::ValueType VT = Tmp1.getValueType();
2431 Tmp2 = DAG.getConstant(~0ULL, VT);
2432 Tmp3 = DAG.getNode(ISD::AND, VT,
2433 DAG.getNode(ISD::XOR, VT, Tmp1, Tmp2),
2434 DAG.getNode(ISD::SUB, VT, Tmp1,
2435 DAG.getConstant(1, VT)));
2436 // If ISD::CTLZ is legal and CTPOP isn't, then do that instead
2437 if (!TLI.isOperationLegal(ISD::CTPOP, VT) &&
2438 TLI.isOperationLegal(ISD::CTLZ, VT)) {
2439 Result = LegalizeOp(DAG.getNode(ISD::SUB, VT,
2440 DAG.getConstant(getSizeInBits(VT), VT),
2441 DAG.getNode(ISD::CTLZ, VT, Tmp3)));
2443 Result = LegalizeOp(DAG.getNode(ISD::CTPOP, VT, Tmp3));
2448 assert(0 && "Cannot expand this yet!");
2461 Tmp1 = LegalizeOp(Node->getOperand(0));
2462 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
2463 case TargetLowering::Legal:
2464 if (Tmp1 != Node->getOperand(0))
2465 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1);
2467 case TargetLowering::Promote:
2468 case TargetLowering::Custom:
2469 assert(0 && "Cannot promote/custom handle this yet!");
2470 case TargetLowering::Expand:
2471 switch(Node->getOpcode()) {
2473 // Expand Y = FNEG(X) -> Y = SUB -0.0, X
2474 Tmp2 = DAG.getConstantFP(-0.0, Node->getValueType(0));
2475 Result = LegalizeOp(DAG.getNode(ISD::FSUB, Node->getValueType(0),
2480 // Expand Y = FABS(X) -> Y = (X >u 0.0) ? X : fneg(X).
2481 MVT::ValueType VT = Node->getValueType(0);
2482 Tmp2 = DAG.getConstantFP(0.0, VT);
2483 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), Tmp1, Tmp2, ISD::SETUGT);
2484 Tmp3 = DAG.getNode(ISD::FNEG, VT, Tmp1);
2485 Result = DAG.getNode(ISD::SELECT, VT, Tmp2, Tmp1, Tmp3);
2486 Result = LegalizeOp(Result);
2492 MVT::ValueType VT = Node->getValueType(0);
2493 const char *FnName = 0;
2494 switch(Node->getOpcode()) {
2495 case ISD::FSQRT: FnName = VT == MVT::f32 ? "sqrtf" : "sqrt"; break;
2496 case ISD::FSIN: FnName = VT == MVT::f32 ? "sinf" : "sin"; break;
2497 case ISD::FCOS: FnName = VT == MVT::f32 ? "cosf" : "cos"; break;
2498 default: assert(0 && "Unreachable!");
2501 Result = ExpandLibCall(FnName, Node, Dummy);
2505 assert(0 && "Unreachable!");
2511 case ISD::BIT_CONVERT:
2512 if (!isTypeLegal(Node->getOperand(0).getValueType())) {
2513 Result = ExpandBIT_CONVERT(Node->getValueType(0), Node->getOperand(0));
2514 Result = LegalizeOp(Result);
2516 switch (TLI.getOperationAction(ISD::BIT_CONVERT,
2517 Node->getOperand(0).getValueType())) {
2518 default: assert(0 && "Unknown operation action!");
2519 case TargetLowering::Expand:
2520 Result = ExpandBIT_CONVERT(Node->getValueType(0), Node->getOperand(0));
2521 Result = LegalizeOp(Result);
2523 case TargetLowering::Legal:
2524 Tmp1 = LegalizeOp(Node->getOperand(0));
2525 if (Tmp1 != Node->getOperand(0))
2526 Result = DAG.getNode(ISD::BIT_CONVERT, Node->getValueType(0), Tmp1);
2531 // Conversion operators. The source and destination have different types.
2532 case ISD::SINT_TO_FP:
2533 case ISD::UINT_TO_FP: {
2534 bool isSigned = Node->getOpcode() == ISD::SINT_TO_FP;
2535 switch (getTypeAction(Node->getOperand(0).getValueType())) {
2537 switch (TLI.getOperationAction(Node->getOpcode(),
2538 Node->getOperand(0).getValueType())) {
2539 default: assert(0 && "Unknown operation action!");
2540 case TargetLowering::Expand:
2541 Result = ExpandLegalINT_TO_FP(isSigned,
2542 LegalizeOp(Node->getOperand(0)),
2543 Node->getValueType(0));
2544 AddLegalizedOperand(Op, Result);
2546 case TargetLowering::Promote:
2547 Result = PromoteLegalINT_TO_FP(LegalizeOp(Node->getOperand(0)),
2548 Node->getValueType(0),
2550 AddLegalizedOperand(Op, Result);
2552 case TargetLowering::Legal:
2554 case TargetLowering::Custom: {
2555 Tmp1 = LegalizeOp(Node->getOperand(0));
2557 DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1);
2558 Tmp = TLI.LowerOperation(Tmp, DAG);
2560 Tmp = LegalizeOp(Tmp); // Relegalize input.
2561 AddLegalizedOperand(Op, Tmp);
2564 assert(0 && "Target Must Lower this");
2569 Tmp1 = LegalizeOp(Node->getOperand(0));
2570 if (Tmp1 != Node->getOperand(0))
2571 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1);
2574 Result = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP,
2575 Node->getValueType(0), Node->getOperand(0));
2579 Result = PromoteOp(Node->getOperand(0));
2580 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(),
2581 Result, DAG.getValueType(Node->getOperand(0).getValueType()));
2582 Result = DAG.getNode(ISD::SINT_TO_FP, Op.getValueType(), Result);
2584 Result = PromoteOp(Node->getOperand(0));
2585 Result = DAG.getZeroExtendInReg(Result,
2586 Node->getOperand(0).getValueType());
2587 Result = DAG.getNode(ISD::UINT_TO_FP, Op.getValueType(), Result);
2594 switch (getTypeAction(Node->getOperand(0).getValueType())) {
2596 Tmp1 = LegalizeOp(Node->getOperand(0));
2597 if (Tmp1 != Node->getOperand(0))
2598 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1);
2601 ExpandOp(Node->getOperand(0), Tmp1, Tmp2);
2603 // Since the result is legal, we should just be able to truncate the low
2604 // part of the source.
2605 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), Tmp1);
2608 Result = PromoteOp(Node->getOperand(0));
2609 Result = DAG.getNode(ISD::TRUNCATE, Op.getValueType(), Result);
2614 case ISD::FP_TO_SINT:
2615 case ISD::FP_TO_UINT:
2616 switch (getTypeAction(Node->getOperand(0).getValueType())) {
2618 Tmp1 = LegalizeOp(Node->getOperand(0));
2620 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))){
2621 default: assert(0 && "Unknown operation action!");
2622 case TargetLowering::Expand:
2623 if (Node->getOpcode() == ISD::FP_TO_UINT) {
2624 SDOperand True, False;
2625 MVT::ValueType VT = Node->getOperand(0).getValueType();
2626 MVT::ValueType NVT = Node->getValueType(0);
2627 unsigned ShiftAmt = MVT::getSizeInBits(Node->getValueType(0))-1;
2628 Tmp2 = DAG.getConstantFP((double)(1ULL << ShiftAmt), VT);
2629 Tmp3 = DAG.getSetCC(TLI.getSetCCResultTy(),
2630 Node->getOperand(0), Tmp2, ISD::SETLT);
2631 True = DAG.getNode(ISD::FP_TO_SINT, NVT, Node->getOperand(0));
2632 False = DAG.getNode(ISD::FP_TO_SINT, NVT,
2633 DAG.getNode(ISD::FSUB, VT, Node->getOperand(0),
2635 False = DAG.getNode(ISD::XOR, NVT, False,
2636 DAG.getConstant(1ULL << ShiftAmt, NVT));
2637 Result = LegalizeOp(DAG.getNode(ISD::SELECT, NVT, Tmp3, True, False));
2638 AddLegalizedOperand(SDOperand(Node, 0), Result);
2641 assert(0 && "Do not know how to expand FP_TO_SINT yet!");
2644 case TargetLowering::Promote:
2645 Result = PromoteLegalFP_TO_INT(Tmp1, Node->getValueType(0),
2646 Node->getOpcode() == ISD::FP_TO_SINT);
2647 AddLegalizedOperand(Op, Result);
2649 case TargetLowering::Custom: {
2651 DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1);
2652 Tmp = TLI.LowerOperation(Tmp, DAG);
2654 Tmp = LegalizeOp(Tmp);
2655 AddLegalizedOperand(Op, Tmp);
2658 // The target thinks this is legal afterall.
2662 case TargetLowering::Legal:
2666 if (Tmp1 != Node->getOperand(0))
2667 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1);
2670 assert(0 && "Shouldn't need to expand other operators here!");
2672 Result = PromoteOp(Node->getOperand(0));
2673 Result = DAG.getNode(Node->getOpcode(), Op.getValueType(), Result);
2678 case ISD::ANY_EXTEND:
2679 case ISD::ZERO_EXTEND:
2680 case ISD::SIGN_EXTEND:
2681 case ISD::FP_EXTEND:
2683 switch (getTypeAction(Node->getOperand(0).getValueType())) {
2685 Tmp1 = LegalizeOp(Node->getOperand(0));
2686 if (Tmp1 != Node->getOperand(0))
2687 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1);
2690 assert(0 && "Shouldn't need to expand other operators here!");
2693 switch (Node->getOpcode()) {
2694 case ISD::ANY_EXTEND:
2695 Result = PromoteOp(Node->getOperand(0));
2696 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Result);
2698 case ISD::ZERO_EXTEND:
2699 Result = PromoteOp(Node->getOperand(0));
2700 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Result);
2701 Result = DAG.getZeroExtendInReg(Result,
2702 Node->getOperand(0).getValueType());
2704 case ISD::SIGN_EXTEND:
2705 Result = PromoteOp(Node->getOperand(0));
2706 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Result);
2707 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(),
2709 DAG.getValueType(Node->getOperand(0).getValueType()));
2711 case ISD::FP_EXTEND:
2712 Result = PromoteOp(Node->getOperand(0));
2713 if (Result.getValueType() != Op.getValueType())
2714 // Dynamically dead while we have only 2 FP types.
2715 Result = DAG.getNode(ISD::FP_EXTEND, Op.getValueType(), Result);
2718 Result = PromoteOp(Node->getOperand(0));
2719 Result = DAG.getNode(Node->getOpcode(), Op.getValueType(), Result);
2724 case ISD::FP_ROUND_INREG:
2725 case ISD::SIGN_EXTEND_INREG: {
2726 Tmp1 = LegalizeOp(Node->getOperand(0));
2727 MVT::ValueType ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT();
2729 // If this operation is not supported, convert it to a shl/shr or load/store
2731 switch (TLI.getOperationAction(Node->getOpcode(), ExtraVT)) {
2732 default: assert(0 && "This action not supported for this op yet!");
2733 case TargetLowering::Legal:
2734 if (Tmp1 != Node->getOperand(0))
2735 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1,
2736 DAG.getValueType(ExtraVT));
2738 case TargetLowering::Expand:
2739 // If this is an integer extend and shifts are supported, do that.
2740 if (Node->getOpcode() == ISD::SIGN_EXTEND_INREG) {
2741 // NOTE: we could fall back on load/store here too for targets without
2742 // SAR. However, it is doubtful that any exist.
2743 unsigned BitsDiff = MVT::getSizeInBits(Node->getValueType(0)) -
2744 MVT::getSizeInBits(ExtraVT);
2745 SDOperand ShiftCst = DAG.getConstant(BitsDiff, TLI.getShiftAmountTy());
2746 Result = DAG.getNode(ISD::SHL, Node->getValueType(0),
2747 Node->getOperand(0), ShiftCst);
2748 Result = DAG.getNode(ISD::SRA, Node->getValueType(0),
2750 } else if (Node->getOpcode() == ISD::FP_ROUND_INREG) {
2751 // The only way we can lower this is to turn it into a STORETRUNC,
2752 // EXTLOAD pair, targetting a temporary location (a stack slot).
2754 // NOTE: there is a choice here between constantly creating new stack
2755 // slots and always reusing the same one. We currently always create
2756 // new ones, as reuse may inhibit scheduling.
2757 const Type *Ty = MVT::getTypeForValueType(ExtraVT);
2758 unsigned TySize = (unsigned)TLI.getTargetData().getTypeSize(Ty);
2759 unsigned Align = TLI.getTargetData().getTypeAlignment(Ty);
2760 MachineFunction &MF = DAG.getMachineFunction();
2762 MF.getFrameInfo()->CreateStackObject((unsigned)TySize, Align);
2763 SDOperand StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy());
2764 Result = DAG.getNode(ISD::TRUNCSTORE, MVT::Other, DAG.getEntryNode(),
2765 Node->getOperand(0), StackSlot,
2766 DAG.getSrcValue(NULL), DAG.getValueType(ExtraVT));
2767 Result = DAG.getExtLoad(ISD::EXTLOAD, Node->getValueType(0),
2768 Result, StackSlot, DAG.getSrcValue(NULL),
2771 assert(0 && "Unknown op");
2773 Result = LegalizeOp(Result);
2780 // Note that LegalizeOp may be reentered even from single-use nodes, which
2781 // means that we always must cache transformed nodes.
2782 AddLegalizedOperand(Op, Result);
2786 /// PromoteOp - Given an operation that produces a value in an invalid type,
2787 /// promote it to compute the value into a larger type. The produced value will
2788 /// have the correct bits for the low portion of the register, but no guarantee
2789 /// is made about the top bits: it may be zero, sign-extended, or garbage.
2790 SDOperand SelectionDAGLegalize::PromoteOp(SDOperand Op) {
2791 MVT::ValueType VT = Op.getValueType();
2792 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT);
2793 assert(getTypeAction(VT) == Promote &&
2794 "Caller should expand or legalize operands that are not promotable!");
2795 assert(NVT > VT && MVT::isInteger(NVT) == MVT::isInteger(VT) &&
2796 "Cannot promote to smaller type!");
2798 SDOperand Tmp1, Tmp2, Tmp3;
2801 SDNode *Node = Op.Val;
2803 std::map<SDOperand, SDOperand>::iterator I = PromotedNodes.find(Op);
2804 if (I != PromotedNodes.end()) return I->second;
2806 // Promotion needs an optimization step to clean up after it, and is not
2807 // careful to avoid operations the target does not support. Make sure that
2808 // all generated operations are legalized in the next iteration.
2809 NeedsAnotherIteration = true;
2811 switch (Node->getOpcode()) {
2812 case ISD::CopyFromReg:
2813 assert(0 && "CopyFromReg must be legal!");
2815 std::cerr << "NODE: "; Node->dump(); std::cerr << "\n";
2816 assert(0 && "Do not know how to promote this operator!");
2819 Result = DAG.getNode(ISD::UNDEF, NVT);
2823 Result = DAG.getNode(ISD::SIGN_EXTEND, NVT, Op);
2825 Result = DAG.getNode(ISD::ZERO_EXTEND, NVT, Op);
2826 assert(isa<ConstantSDNode>(Result) && "Didn't constant fold zext?");
2828 case ISD::ConstantFP:
2829 Result = DAG.getNode(ISD::FP_EXTEND, NVT, Op);
2830 assert(isa<ConstantFPSDNode>(Result) && "Didn't constant fold fp_extend?");
2834 assert(isTypeLegal(TLI.getSetCCResultTy()) && "SetCC type is not legal??");
2835 Result = DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(),Node->getOperand(0),
2836 Node->getOperand(1), Node->getOperand(2));
2837 Result = LegalizeOp(Result);
2841 switch (getTypeAction(Node->getOperand(0).getValueType())) {
2843 Result = LegalizeOp(Node->getOperand(0));
2844 assert(Result.getValueType() >= NVT &&
2845 "This truncation doesn't make sense!");
2846 if (Result.getValueType() > NVT) // Truncate to NVT instead of VT
2847 Result = DAG.getNode(ISD::TRUNCATE, NVT, Result);
2850 // The truncation is not required, because we don't guarantee anything
2851 // about high bits anyway.
2852 Result = PromoteOp(Node->getOperand(0));
2855 ExpandOp(Node->getOperand(0), Tmp1, Tmp2);
2856 // Truncate the low part of the expanded value to the result type
2857 Result = DAG.getNode(ISD::TRUNCATE, NVT, Tmp1);
2860 case ISD::SIGN_EXTEND:
2861 case ISD::ZERO_EXTEND:
2862 case ISD::ANY_EXTEND:
2863 switch (getTypeAction(Node->getOperand(0).getValueType())) {
2864 case Expand: assert(0 && "BUG: Smaller reg should have been promoted!");
2866 // Input is legal? Just do extend all the way to the larger type.
2867 Result = LegalizeOp(Node->getOperand(0));
2868 Result = DAG.getNode(Node->getOpcode(), NVT, Result);
2871 // Promote the reg if it's smaller.
2872 Result = PromoteOp(Node->getOperand(0));
2873 // The high bits are not guaranteed to be anything. Insert an extend.
2874 if (Node->getOpcode() == ISD::SIGN_EXTEND)
2875 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Result,
2876 DAG.getValueType(Node->getOperand(0).getValueType()));
2877 else if (Node->getOpcode() == ISD::ZERO_EXTEND)
2878 Result = DAG.getZeroExtendInReg(Result,
2879 Node->getOperand(0).getValueType());
2883 case ISD::BIT_CONVERT:
2884 Result = ExpandBIT_CONVERT(Node->getValueType(0), Node->getOperand(0));
2885 Result = PromoteOp(Result);
2888 case ISD::FP_EXTEND:
2889 assert(0 && "Case not implemented. Dynamically dead with 2 FP types!");
2891 switch (getTypeAction(Node->getOperand(0).getValueType())) {
2892 case Expand: assert(0 && "BUG: Cannot expand FP regs!");
2893 case Promote: assert(0 && "Unreachable with 2 FP types!");
2895 // Input is legal? Do an FP_ROUND_INREG.
2896 Result = LegalizeOp(Node->getOperand(0));
2897 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
2898 DAG.getValueType(VT));
2903 case ISD::SINT_TO_FP:
2904 case ISD::UINT_TO_FP:
2905 switch (getTypeAction(Node->getOperand(0).getValueType())) {
2907 Result = LegalizeOp(Node->getOperand(0));
2908 // No extra round required here.
2909 Result = DAG.getNode(Node->getOpcode(), NVT, Result);
2913 Result = PromoteOp(Node->getOperand(0));
2914 if (Node->getOpcode() == ISD::SINT_TO_FP)
2915 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(),
2917 DAG.getValueType(Node->getOperand(0).getValueType()));
2919 Result = DAG.getZeroExtendInReg(Result,
2920 Node->getOperand(0).getValueType());
2921 // No extra round required here.
2922 Result = DAG.getNode(Node->getOpcode(), NVT, Result);
2925 Result = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP, NVT,
2926 Node->getOperand(0));
2927 // Round if we cannot tolerate excess precision.
2928 if (NoExcessFPPrecision)
2929 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
2930 DAG.getValueType(VT));
2935 case ISD::SIGN_EXTEND_INREG:
2936 Result = PromoteOp(Node->getOperand(0));
2937 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Result,
2938 Node->getOperand(1));
2940 case ISD::FP_TO_SINT:
2941 case ISD::FP_TO_UINT:
2942 switch (getTypeAction(Node->getOperand(0).getValueType())) {
2944 Tmp1 = LegalizeOp(Node->getOperand(0));
2947 // The input result is prerounded, so we don't have to do anything
2949 Tmp1 = PromoteOp(Node->getOperand(0));
2952 assert(0 && "not implemented");
2954 // If we're promoting a UINT to a larger size, check to see if the new node
2955 // will be legal. If it isn't, check to see if FP_TO_SINT is legal, since
2956 // we can use that instead. This allows us to generate better code for
2957 // FP_TO_UINT for small destination sizes on targets where FP_TO_UINT is not
2958 // legal, such as PowerPC.
2959 if (Node->getOpcode() == ISD::FP_TO_UINT &&
2960 !TLI.isOperationLegal(ISD::FP_TO_UINT, NVT) &&
2961 (TLI.isOperationLegal(ISD::FP_TO_SINT, NVT) ||
2962 TLI.getOperationAction(ISD::FP_TO_SINT, NVT)==TargetLowering::Custom)){
2963 Result = DAG.getNode(ISD::FP_TO_SINT, NVT, Tmp1);
2965 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
2971 Tmp1 = PromoteOp(Node->getOperand(0));
2972 assert(Tmp1.getValueType() == NVT);
2973 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
2974 // NOTE: we do not have to do any extra rounding here for
2975 // NoExcessFPPrecision, because we know the input will have the appropriate
2976 // precision, and these operations don't modify precision at all.
2982 Tmp1 = PromoteOp(Node->getOperand(0));
2983 assert(Tmp1.getValueType() == NVT);
2984 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
2985 if(NoExcessFPPrecision)
2986 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
2987 DAG.getValueType(VT));
2996 // The input may have strange things in the top bits of the registers, but
2997 // these operations don't care. They may have weird bits going out, but
2998 // that too is okay if they are integer operations.
2999 Tmp1 = PromoteOp(Node->getOperand(0));
3000 Tmp2 = PromoteOp(Node->getOperand(1));
3001 assert(Tmp1.getValueType() == NVT && Tmp2.getValueType() == NVT);
3002 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
3007 // The input may have strange things in the top bits of the registers, but
3008 // these operations don't care.
3009 Tmp1 = PromoteOp(Node->getOperand(0));
3010 Tmp2 = PromoteOp(Node->getOperand(1));
3011 assert(Tmp1.getValueType() == NVT && Tmp2.getValueType() == NVT);
3012 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
3014 // Floating point operations will give excess precision that we may not be
3015 // able to tolerate. If we DO allow excess precision, just leave it,
3016 // otherwise excise it.
3017 // FIXME: Why would we need to round FP ops more than integer ones?
3018 // Is Round(Add(Add(A,B),C)) != Round(Add(Round(Add(A,B)), C))
3019 if (NoExcessFPPrecision)
3020 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
3021 DAG.getValueType(VT));
3026 // These operators require that their input be sign extended.
3027 Tmp1 = PromoteOp(Node->getOperand(0));
3028 Tmp2 = PromoteOp(Node->getOperand(1));
3029 if (MVT::isInteger(NVT)) {
3030 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1,
3031 DAG.getValueType(VT));
3032 Tmp2 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp2,
3033 DAG.getValueType(VT));
3035 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
3037 // Perform FP_ROUND: this is probably overly pessimistic.
3038 if (MVT::isFloatingPoint(NVT) && NoExcessFPPrecision)
3039 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
3040 DAG.getValueType(VT));
3044 // These operators require that their input be fp extended.
3045 Tmp1 = PromoteOp(Node->getOperand(0));
3046 Tmp2 = PromoteOp(Node->getOperand(1));
3047 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
3049 // Perform FP_ROUND: this is probably overly pessimistic.
3050 if (NoExcessFPPrecision)
3051 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
3052 DAG.getValueType(VT));
3057 // These operators require that their input be zero extended.
3058 Tmp1 = PromoteOp(Node->getOperand(0));
3059 Tmp2 = PromoteOp(Node->getOperand(1));
3060 assert(MVT::isInteger(NVT) && "Operators don't apply to FP!");
3061 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT);
3062 Tmp2 = DAG.getZeroExtendInReg(Tmp2, VT);
3063 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
3067 Tmp1 = PromoteOp(Node->getOperand(0));
3068 Tmp2 = LegalizeOp(Node->getOperand(1));
3069 Result = DAG.getNode(ISD::SHL, NVT, Tmp1, Tmp2);
3072 // The input value must be properly sign extended.
3073 Tmp1 = PromoteOp(Node->getOperand(0));
3074 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1,
3075 DAG.getValueType(VT));
3076 Tmp2 = LegalizeOp(Node->getOperand(1));
3077 Result = DAG.getNode(ISD::SRA, NVT, Tmp1, Tmp2);
3080 // The input value must be properly zero extended.
3081 Tmp1 = PromoteOp(Node->getOperand(0));
3082 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT);
3083 Tmp2 = LegalizeOp(Node->getOperand(1));
3084 Result = DAG.getNode(ISD::SRL, NVT, Tmp1, Tmp2);
3088 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
3089 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
3090 Result = DAG.getExtLoad(ISD::EXTLOAD, NVT, Tmp1, Tmp2,
3091 Node->getOperand(2), VT);
3092 // Remember that we legalized the chain.
3093 AddLegalizedOperand(Op.getValue(1), Result.getValue(1));
3098 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
3099 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
3100 Result = DAG.getExtLoad(Node->getOpcode(), NVT, Tmp1, Tmp2,
3101 Node->getOperand(2),
3102 cast<VTSDNode>(Node->getOperand(3))->getVT());
3103 // Remember that we legalized the chain.
3104 AddLegalizedOperand(Op.getValue(1), Result.getValue(1));
3107 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3108 case Expand: assert(0 && "It's impossible to expand bools");
3110 Tmp1 = LegalizeOp(Node->getOperand(0));// Legalize the condition.
3113 Tmp1 = PromoteOp(Node->getOperand(0)); // Promote the condition.
3116 Tmp2 = PromoteOp(Node->getOperand(1)); // Legalize the op0
3117 Tmp3 = PromoteOp(Node->getOperand(2)); // Legalize the op1
3118 Result = DAG.getNode(ISD::SELECT, NVT, Tmp1, Tmp2, Tmp3);
3120 case ISD::SELECT_CC:
3121 Tmp2 = PromoteOp(Node->getOperand(2)); // True
3122 Tmp3 = PromoteOp(Node->getOperand(3)); // False
3123 Result = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0),
3124 Node->getOperand(1), Tmp2, Tmp3,
3125 Node->getOperand(4));
3129 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
3130 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the callee.
3132 std::vector<SDOperand> Ops;
3133 for (unsigned i = 2, e = Node->getNumOperands(); i != e; ++i)
3134 Ops.push_back(LegalizeOp(Node->getOperand(i)));
3136 assert(Node->getNumValues() == 2 && Op.ResNo == 0 &&
3137 "Can only promote single result calls");
3138 std::vector<MVT::ValueType> RetTyVTs;
3139 RetTyVTs.reserve(2);
3140 RetTyVTs.push_back(NVT);
3141 RetTyVTs.push_back(MVT::Other);
3142 SDNode *NC = DAG.getCall(RetTyVTs, Tmp1, Tmp2, Ops,
3143 Node->getOpcode() == ISD::TAILCALL);
3144 Result = SDOperand(NC, 0);
3146 // Insert the new chain mapping.
3147 AddLegalizedOperand(Op.getValue(1), Result.getValue(1));
3151 Tmp1 = Node->getOperand(0);
3152 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1);
3153 Tmp1 = DAG.getNode(ISD::BSWAP, NVT, Tmp1);
3154 Result = DAG.getNode(ISD::SRL, NVT, Tmp1,
3155 DAG.getConstant(getSizeInBits(NVT) - getSizeInBits(VT),
3156 TLI.getShiftAmountTy()));
3161 Tmp1 = Node->getOperand(0);
3162 //Zero extend the argument
3163 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1);
3164 // Perform the larger operation, then subtract if needed.
3165 Tmp1 = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
3166 switch(Node->getOpcode())
3172 //if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT)
3173 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), Tmp1,
3174 DAG.getConstant(getSizeInBits(NVT), NVT), ISD::SETEQ);
3175 Result = DAG.getNode(ISD::SELECT, NVT, Tmp2,
3176 DAG.getConstant(getSizeInBits(VT),NVT), Tmp1);
3179 //Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT))
3180 Result = DAG.getNode(ISD::SUB, NVT, Tmp1,
3181 DAG.getConstant(getSizeInBits(NVT) -
3182 getSizeInBits(VT), NVT));
3188 assert(Result.Val && "Didn't set a result!");
3189 AddPromotedOperand(Op, Result);
3193 /// ExpandBIT_CONVERT - Expand a BIT_CONVERT node into a store/load combination.
3194 /// The resultant code need not be legal. Note that SrcOp is the input operand
3195 /// to the BIT_CONVERT, not the BIT_CONVERT node itself.
3196 SDOperand SelectionDAGLegalize::ExpandBIT_CONVERT(MVT::ValueType DestVT,
3198 // Create the stack frame object.
3199 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo();
3200 unsigned ByteSize = MVT::getSizeInBits(DestVT)/8;
3201 int FrameIdx = FrameInfo->CreateStackObject(ByteSize, ByteSize);
3202 SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, TLI.getPointerTy());
3204 // Emit a store to the stack slot.
3205 SDOperand Store = DAG.getNode(ISD::STORE, MVT::Other, DAG.getEntryNode(),
3206 SrcOp, FIPtr, DAG.getSrcValue(NULL));
3207 // Result is a load from the stack slot.
3208 return DAG.getLoad(DestVT, Store, FIPtr, DAG.getSrcValue(0));
3211 /// ExpandAddSub - Find a clever way to expand this add operation into
3213 void SelectionDAGLegalize::
3214 ExpandByParts(unsigned NodeOp, SDOperand LHS, SDOperand RHS,
3215 SDOperand &Lo, SDOperand &Hi) {
3216 // Expand the subcomponents.
3217 SDOperand LHSL, LHSH, RHSL, RHSH;
3218 ExpandOp(LHS, LHSL, LHSH);
3219 ExpandOp(RHS, RHSL, RHSH);
3221 std::vector<SDOperand> Ops;
3222 Ops.push_back(LHSL);
3223 Ops.push_back(LHSH);
3224 Ops.push_back(RHSL);
3225 Ops.push_back(RHSH);
3226 std::vector<MVT::ValueType> VTs(2, LHSL.getValueType());
3227 Lo = DAG.getNode(NodeOp, VTs, Ops);
3228 Hi = Lo.getValue(1);
3231 void SelectionDAGLegalize::ExpandShiftParts(unsigned NodeOp,
3232 SDOperand Op, SDOperand Amt,
3233 SDOperand &Lo, SDOperand &Hi) {
3234 // Expand the subcomponents.
3235 SDOperand LHSL, LHSH;
3236 ExpandOp(Op, LHSL, LHSH);
3238 std::vector<SDOperand> Ops;
3239 Ops.push_back(LHSL);
3240 Ops.push_back(LHSH);
3242 std::vector<MVT::ValueType> VTs(2, LHSL.getValueType());
3243 Lo = DAG.getNode(NodeOp, VTs, Ops);
3244 Hi = Lo.getValue(1);
3248 /// ExpandShift - Try to find a clever way to expand this shift operation out to
3249 /// smaller elements. If we can't find a way that is more efficient than a
3250 /// libcall on this target, return false. Otherwise, return true with the
3251 /// low-parts expanded into Lo and Hi.
3252 bool SelectionDAGLegalize::ExpandShift(unsigned Opc, SDOperand Op,SDOperand Amt,
3253 SDOperand &Lo, SDOperand &Hi) {
3254 assert((Opc == ISD::SHL || Opc == ISD::SRA || Opc == ISD::SRL) &&
3255 "This is not a shift!");
3257 MVT::ValueType NVT = TLI.getTypeToTransformTo(Op.getValueType());
3258 SDOperand ShAmt = LegalizeOp(Amt);
3259 MVT::ValueType ShTy = ShAmt.getValueType();
3260 unsigned VTBits = MVT::getSizeInBits(Op.getValueType());
3261 unsigned NVTBits = MVT::getSizeInBits(NVT);
3263 // Handle the case when Amt is an immediate. Other cases are currently broken
3264 // and are disabled.
3265 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Amt.Val)) {
3266 unsigned Cst = CN->getValue();
3267 // Expand the incoming operand to be shifted, so that we have its parts
3269 ExpandOp(Op, InL, InH);
3273 Lo = DAG.getConstant(0, NVT);
3274 Hi = DAG.getConstant(0, NVT);
3275 } else if (Cst > NVTBits) {
3276 Lo = DAG.getConstant(0, NVT);
3277 Hi = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Cst-NVTBits,ShTy));
3278 } else if (Cst == NVTBits) {
3279 Lo = DAG.getConstant(0, NVT);
3282 Lo = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Cst, ShTy));
3283 Hi = DAG.getNode(ISD::OR, NVT,
3284 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(Cst, ShTy)),
3285 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(NVTBits-Cst, ShTy)));
3290 Lo = DAG.getConstant(0, NVT);
3291 Hi = DAG.getConstant(0, NVT);
3292 } else if (Cst > NVTBits) {
3293 Lo = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Cst-NVTBits,ShTy));
3294 Hi = DAG.getConstant(0, NVT);
3295 } else if (Cst == NVTBits) {
3297 Hi = DAG.getConstant(0, NVT);
3299 Lo = DAG.getNode(ISD::OR, NVT,
3300 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(Cst, ShTy)),
3301 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(NVTBits-Cst, ShTy)));
3302 Hi = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Cst, ShTy));
3307 Hi = Lo = DAG.getNode(ISD::SRA, NVT, InH,
3308 DAG.getConstant(NVTBits-1, ShTy));
3309 } else if (Cst > NVTBits) {
3310 Lo = DAG.getNode(ISD::SRA, NVT, InH,
3311 DAG.getConstant(Cst-NVTBits, ShTy));
3312 Hi = DAG.getNode(ISD::SRA, NVT, InH,
3313 DAG.getConstant(NVTBits-1, ShTy));
3314 } else if (Cst == NVTBits) {
3316 Hi = DAG.getNode(ISD::SRA, NVT, InH,
3317 DAG.getConstant(NVTBits-1, ShTy));
3319 Lo = DAG.getNode(ISD::OR, NVT,
3320 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(Cst, ShTy)),
3321 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(NVTBits-Cst, ShTy)));
3322 Hi = DAG.getNode(ISD::SRA, NVT, InH, DAG.getConstant(Cst, ShTy));
3327 // FIXME: The following code for expanding shifts using ISD::SELECT is buggy,
3328 // so disable it for now. Currently targets are handling this via SHL_PARTS
3332 // If we have an efficient select operation (or if the selects will all fold
3333 // away), lower to some complex code, otherwise just emit the libcall.
3334 if (!TLI.isOperationLegal(ISD::SELECT, NVT) && !isa<ConstantSDNode>(Amt))
3338 ExpandOp(Op, InL, InH);
3339 SDOperand NAmt = DAG.getNode(ISD::SUB, ShTy, // NAmt = 32-ShAmt
3340 DAG.getConstant(NVTBits, ShTy), ShAmt);
3342 // Compare the unmasked shift amount against 32.
3343 SDOperand Cond = DAG.getSetCC(TLI.getSetCCResultTy(), ShAmt,
3344 DAG.getConstant(NVTBits, ShTy), ISD::SETGE);
3346 if (TLI.getShiftAmountFlavor() != TargetLowering::Mask) {
3347 ShAmt = DAG.getNode(ISD::AND, ShTy, ShAmt, // ShAmt &= 31
3348 DAG.getConstant(NVTBits-1, ShTy));
3349 NAmt = DAG.getNode(ISD::AND, ShTy, NAmt, // NAmt &= 31
3350 DAG.getConstant(NVTBits-1, ShTy));
3353 if (Opc == ISD::SHL) {
3354 SDOperand T1 = DAG.getNode(ISD::OR, NVT,// T1 = (Hi << Amt) | (Lo >> NAmt)
3355 DAG.getNode(ISD::SHL, NVT, InH, ShAmt),
3356 DAG.getNode(ISD::SRL, NVT, InL, NAmt));
3357 SDOperand T2 = DAG.getNode(ISD::SHL, NVT, InL, ShAmt); // T2 = Lo << Amt&31
3359 Hi = DAG.getNode(ISD::SELECT, NVT, Cond, T2, T1);
3360 Lo = DAG.getNode(ISD::SELECT, NVT, Cond, DAG.getConstant(0, NVT), T2);
3362 SDOperand HiLoPart = DAG.getNode(ISD::SELECT, NVT,
3363 DAG.getSetCC(TLI.getSetCCResultTy(), NAmt,
3364 DAG.getConstant(32, ShTy),
3366 DAG.getConstant(0, NVT),
3367 DAG.getNode(ISD::SHL, NVT, InH, NAmt));
3368 SDOperand T1 = DAG.getNode(ISD::OR, NVT,// T1 = (Hi << NAmt) | (Lo >> Amt)
3370 DAG.getNode(ISD::SRL, NVT, InL, ShAmt));
3371 SDOperand T2 = DAG.getNode(Opc, NVT, InH, ShAmt); // T2 = InH >> ShAmt&31
3374 if (Opc == ISD::SRA)
3375 HiPart = DAG.getNode(ISD::SRA, NVT, InH,
3376 DAG.getConstant(NVTBits-1, ShTy));
3378 HiPart = DAG.getConstant(0, NVT);
3379 Lo = DAG.getNode(ISD::SELECT, NVT, Cond, T2, T1);
3380 Hi = DAG.getNode(ISD::SELECT, NVT, Cond, HiPart, T2);
3385 /// FindLatestCallSeqStart - Scan up the dag to find the latest (highest
3386 /// NodeDepth) node that is an CallSeqStart operation and occurs later than
3388 static void FindLatestCallSeqStart(SDNode *Node, SDNode *&Found,
3389 std::set<SDNode*> &Visited) {
3390 if (Node->getNodeDepth() <= Found->getNodeDepth() ||
3391 !Visited.insert(Node).second) return;
3393 // If we found an CALLSEQ_START, we already know this node occurs later
3394 // than the Found node. Just remember this node and return.
3395 if (Node->getOpcode() == ISD::CALLSEQ_START) {
3400 // Otherwise, scan the operands of Node to see if any of them is a call.
3401 assert(Node->getNumOperands() != 0 &&
3402 "All leaves should have depth equal to the entry node!");
3403 for (unsigned i = 0, e = Node->getNumOperands()-1; i != e; ++i)
3404 FindLatestCallSeqStart(Node->getOperand(i).Val, Found, Visited);
3406 // Tail recurse for the last iteration.
3407 FindLatestCallSeqStart(Node->getOperand(Node->getNumOperands()-1).Val,
3412 /// FindEarliestCallSeqEnd - Scan down the dag to find the earliest (lowest
3413 /// NodeDepth) node that is an CallSeqEnd operation and occurs more recent
3415 static void FindEarliestCallSeqEnd(SDNode *Node, SDNode *&Found,
3416 std::set<SDNode*> &Visited) {
3417 if ((Found && Node->getNodeDepth() >= Found->getNodeDepth()) ||
3418 !Visited.insert(Node).second) return;
3420 // If we found an CALLSEQ_END, we already know this node occurs earlier
3421 // than the Found node. Just remember this node and return.
3422 if (Node->getOpcode() == ISD::CALLSEQ_END) {
3427 // Otherwise, scan the operands of Node to see if any of them is a call.
3428 SDNode::use_iterator UI = Node->use_begin(), E = Node->use_end();
3429 if (UI == E) return;
3430 for (--E; UI != E; ++UI)
3431 FindEarliestCallSeqEnd(*UI, Found, Visited);
3433 // Tail recurse for the last iteration.
3434 FindEarliestCallSeqEnd(*UI, Found, Visited);
3437 /// FindCallSeqEnd - Given a chained node that is part of a call sequence,
3438 /// find the CALLSEQ_END node that terminates the call sequence.
3439 static SDNode *FindCallSeqEnd(SDNode *Node) {
3440 if (Node->getOpcode() == ISD::CALLSEQ_END)
3442 if (Node->use_empty())
3443 return 0; // No CallSeqEnd
3445 // The chain is usually at the end.
3446 SDOperand TheChain(Node, Node->getNumValues()-1);
3447 if (TheChain.getValueType() != MVT::Other) {
3448 // Sometimes it's at the beginning.
3449 TheChain = SDOperand(Node, 0);
3450 if (TheChain.getValueType() != MVT::Other) {
3451 // Otherwise, hunt for it.
3452 for (unsigned i = 1, e = Node->getNumValues(); i != e; ++i)
3453 if (Node->getValueType(i) == MVT::Other) {
3454 TheChain = SDOperand(Node, i);
3458 // Otherwise, we walked into a node without a chain.
3459 if (TheChain.getValueType() != MVT::Other)
3464 for (SDNode::use_iterator UI = Node->use_begin(),
3465 E = Node->use_end(); UI != E; ++UI) {
3467 // Make sure to only follow users of our token chain.
3469 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i)
3470 if (User->getOperand(i) == TheChain)
3471 if (SDNode *Result = FindCallSeqEnd(User))
3477 /// FindCallSeqStart - Given a chained node that is part of a call sequence,
3478 /// find the CALLSEQ_START node that initiates the call sequence.
3479 static SDNode *FindCallSeqStart(SDNode *Node) {
3480 assert(Node && "Didn't find callseq_start for a call??");
3481 if (Node->getOpcode() == ISD::CALLSEQ_START) return Node;
3483 assert(Node->getOperand(0).getValueType() == MVT::Other &&
3484 "Node doesn't have a token chain argument!");
3485 return FindCallSeqStart(Node->getOperand(0).Val);
3489 /// FindInputOutputChains - If we are replacing an operation with a call we need
3490 /// to find the call that occurs before and the call that occurs after it to
3491 /// properly serialize the calls in the block. The returned operand is the
3492 /// input chain value for the new call (e.g. the entry node or the previous
3493 /// call), and OutChain is set to be the chain node to update to point to the
3494 /// end of the call chain.
3495 static SDOperand FindInputOutputChains(SDNode *OpNode, SDNode *&OutChain,
3497 SDNode *LatestCallSeqStart = Entry.Val;
3498 SDNode *LatestCallSeqEnd = 0;
3499 std::set<SDNode*> Visited;
3500 FindLatestCallSeqStart(OpNode, LatestCallSeqStart, Visited);
3502 //std::cerr<<"Found node: "; LatestCallSeqStart->dump(); std::cerr <<"\n";
3504 // It is possible that no ISD::CALLSEQ_START was found because there is no
3505 // previous call in the function. LatestCallStackDown may in that case be
3506 // the entry node itself. Do not attempt to find a matching CALLSEQ_END
3507 // unless LatestCallStackDown is an CALLSEQ_START.
3508 if (LatestCallSeqStart->getOpcode() == ISD::CALLSEQ_START) {
3509 LatestCallSeqEnd = FindCallSeqEnd(LatestCallSeqStart);
3510 //std::cerr<<"Found end node: "; LatestCallSeqEnd->dump(); std::cerr <<"\n";
3512 LatestCallSeqEnd = Entry.Val;
3514 assert(LatestCallSeqEnd && "NULL return from FindCallSeqEnd");
3516 // Finally, find the first call that this must come before, first we find the
3517 // CallSeqEnd that ends the call.
3519 FindEarliestCallSeqEnd(OpNode, OutChain, Visited);
3522 // If we found one, translate from the adj up to the callseq_start.
3524 OutChain = FindCallSeqStart(OutChain);
3526 return SDOperand(LatestCallSeqEnd, 0);
3529 /// SpliceCallInto - Given the result chain of a libcall (CallResult), and a
3530 void SelectionDAGLegalize::SpliceCallInto(const SDOperand &CallResult,
3532 // Nothing to splice it into?
3533 if (OutChain == 0) return;
3535 assert(OutChain->getOperand(0).getValueType() == MVT::Other);
3538 // Form a token factor node merging the old inval and the new inval.
3539 SDOperand InToken = DAG.getNode(ISD::TokenFactor, MVT::Other, CallResult,
3540 OutChain->getOperand(0));
3541 // Change the node to refer to the new token.
3542 OutChain->setAdjCallChain(InToken);
3546 // ExpandLibCall - Expand a node into a call to a libcall. If the result value
3547 // does not fit into a register, return the lo part and set the hi part to the
3548 // by-reg argument. If it does fit into a single register, return the result
3549 // and leave the Hi part unset.
3550 SDOperand SelectionDAGLegalize::ExpandLibCall(const char *Name, SDNode *Node,
3553 SDOperand InChain = FindInputOutputChains(Node, OutChain,
3554 DAG.getEntryNode());
3555 if (InChain.Val == 0)
3556 InChain = DAG.getEntryNode();
3558 TargetLowering::ArgListTy Args;
3559 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
3560 MVT::ValueType ArgVT = Node->getOperand(i).getValueType();
3561 const Type *ArgTy = MVT::getTypeForValueType(ArgVT);
3562 Args.push_back(std::make_pair(Node->getOperand(i), ArgTy));
3564 SDOperand Callee = DAG.getExternalSymbol(Name, TLI.getPointerTy());
3566 // Splice the libcall in wherever FindInputOutputChains tells us to.
3567 const Type *RetTy = MVT::getTypeForValueType(Node->getValueType(0));
3568 std::pair<SDOperand,SDOperand> CallInfo =
3569 TLI.LowerCallTo(InChain, RetTy, false, CallingConv::C, false,
3573 switch (getTypeAction(CallInfo.first.getValueType())) {
3574 default: assert(0 && "Unknown thing");
3576 Result = CallInfo.first;
3579 assert(0 && "Cannot promote this yet!");
3581 ExpandOp(CallInfo.first, Result, Hi);
3582 CallInfo.second = LegalizeOp(CallInfo.second);
3586 SpliceCallInto(CallInfo.second, OutChain);
3587 NeedsAnotherIteration = true;
3592 /// ExpandIntToFP - Expand a [US]INT_TO_FP operation, assuming that the
3593 /// destination type is legal.
3594 SDOperand SelectionDAGLegalize::
3595 ExpandIntToFP(bool isSigned, MVT::ValueType DestTy, SDOperand Source) {
3596 assert(isTypeLegal(DestTy) && "Destination type is not legal!");
3597 assert(getTypeAction(Source.getValueType()) == Expand &&
3598 "This is not an expansion!");
3599 assert(Source.getValueType() == MVT::i64 && "Only handle expand from i64!");
3602 assert(Source.getValueType() == MVT::i64 &&
3603 "This only works for 64-bit -> FP");
3604 // The 64-bit value loaded will be incorrectly if the 'sign bit' of the
3605 // incoming integer is set. To handle this, we dynamically test to see if
3606 // it is set, and, if so, add a fudge factor.
3608 ExpandOp(Source, Lo, Hi);
3610 // If this is unsigned, and not supported, first perform the conversion to
3611 // signed, then adjust the result if the sign bit is set.
3612 SDOperand SignedConv = ExpandIntToFP(true, DestTy,
3613 DAG.getNode(ISD::BUILD_PAIR, Source.getValueType(), Lo, Hi));
3615 SDOperand SignSet = DAG.getSetCC(TLI.getSetCCResultTy(), Hi,
3616 DAG.getConstant(0, Hi.getValueType()),
3618 SDOperand Zero = getIntPtrConstant(0), Four = getIntPtrConstant(4);
3619 SDOperand CstOffset = DAG.getNode(ISD::SELECT, Zero.getValueType(),
3620 SignSet, Four, Zero);
3621 uint64_t FF = 0x5f800000ULL;
3622 if (TLI.isLittleEndian()) FF <<= 32;
3623 static Constant *FudgeFactor = ConstantUInt::get(Type::ULongTy, FF);
3625 SDOperand CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy());
3626 CPIdx = DAG.getNode(ISD::ADD, TLI.getPointerTy(), CPIdx, CstOffset);
3627 SDOperand FudgeInReg;
3628 if (DestTy == MVT::f32)
3629 FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx,
3630 DAG.getSrcValue(NULL));
3632 assert(DestTy == MVT::f64 && "Unexpected conversion");
3633 FudgeInReg = DAG.getExtLoad(ISD::EXTLOAD, MVT::f64, DAG.getEntryNode(),
3634 CPIdx, DAG.getSrcValue(NULL), MVT::f32);
3636 return DAG.getNode(ISD::FADD, DestTy, SignedConv, FudgeInReg);
3639 // Check to see if the target has a custom way to lower this. If so, use it.
3640 switch (TLI.getOperationAction(ISD::SINT_TO_FP, Source.getValueType())) {
3641 default: assert(0 && "This action not implemented for this operation!");
3642 case TargetLowering::Legal:
3643 case TargetLowering::Expand:
3644 break; // This case is handled below.
3645 case TargetLowering::Custom: {
3646 SDOperand NV = TLI.LowerOperation(DAG.getNode(ISD::SINT_TO_FP, DestTy,
3649 return LegalizeOp(NV);
3650 break; // The target decided this was legal after all
3654 // Expand the source, then glue it back together for the call. We must expand
3655 // the source in case it is shared (this pass of legalize must traverse it).
3656 SDOperand SrcLo, SrcHi;
3657 ExpandOp(Source, SrcLo, SrcHi);
3658 Source = DAG.getNode(ISD::BUILD_PAIR, Source.getValueType(), SrcLo, SrcHi);
3660 SDNode *OutChain = 0;
3661 SDOperand InChain = FindInputOutputChains(Source.Val, OutChain,
3662 DAG.getEntryNode());
3663 const char *FnName = 0;
3664 if (DestTy == MVT::f32)
3665 FnName = "__floatdisf";
3667 assert(DestTy == MVT::f64 && "Unknown fp value type!");
3668 FnName = "__floatdidf";
3671 SDOperand Callee = DAG.getExternalSymbol(FnName, TLI.getPointerTy());
3673 TargetLowering::ArgListTy Args;
3674 const Type *ArgTy = MVT::getTypeForValueType(Source.getValueType());
3676 Args.push_back(std::make_pair(Source, ArgTy));
3678 // We don't care about token chains for libcalls. We just use the entry
3679 // node as our input and ignore the output chain. This allows us to place
3680 // calls wherever we need them to satisfy data dependences.
3681 const Type *RetTy = MVT::getTypeForValueType(DestTy);
3683 std::pair<SDOperand,SDOperand> CallResult =
3684 TLI.LowerCallTo(InChain, RetTy, false, CallingConv::C, true,
3687 SpliceCallInto(CallResult.second, OutChain);
3688 return CallResult.first;
3693 /// ExpandOp - Expand the specified SDOperand into its two component pieces
3694 /// Lo&Hi. Note that the Op MUST be an expanded type. As a result of this, the
3695 /// LegalizeNodes map is filled in for any results that are not expanded, the
3696 /// ExpandedNodes map is filled in for any results that are expanded, and the
3697 /// Lo/Hi values are returned.
3698 void SelectionDAGLegalize::ExpandOp(SDOperand Op, SDOperand &Lo, SDOperand &Hi){
3699 MVT::ValueType VT = Op.getValueType();
3700 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT);
3701 SDNode *Node = Op.Val;
3702 assert(getTypeAction(VT) == Expand && "Not an expanded type!");
3703 assert((MVT::isInteger(VT) || VT == MVT::Vector) &&
3704 "Cannot expand FP values!");
3705 assert(((MVT::isInteger(NVT) && NVT < VT) || VT == MVT::Vector) &&
3706 "Cannot expand to FP value or to larger int value!");
3708 // See if we already expanded it.
3709 std::map<SDOperand, std::pair<SDOperand, SDOperand> >::iterator I
3710 = ExpandedNodes.find(Op);
3711 if (I != ExpandedNodes.end()) {
3712 Lo = I->second.first;
3713 Hi = I->second.second;
3717 // Expanding to multiple registers needs to perform an optimization step, and
3718 // is not careful to avoid operations the target does not support. Make sure
3719 // that all generated operations are legalized in the next iteration.
3720 NeedsAnotherIteration = true;
3722 switch (Node->getOpcode()) {
3723 case ISD::CopyFromReg:
3724 assert(0 && "CopyFromReg must be legal!");
3726 std::cerr << "NODE: "; Node->dump(); std::cerr << "\n";
3727 assert(0 && "Do not know how to expand this operator!");
3730 Lo = DAG.getNode(ISD::UNDEF, NVT);
3731 Hi = DAG.getNode(ISD::UNDEF, NVT);
3733 case ISD::Constant: {
3734 uint64_t Cst = cast<ConstantSDNode>(Node)->getValue();
3735 Lo = DAG.getConstant(Cst, NVT);
3736 Hi = DAG.getConstant(Cst >> MVT::getSizeInBits(NVT), NVT);
3739 case ISD::ConstantVec: {
3740 unsigned NumElements = Node->getNumOperands();
3741 // If we only have two elements left in the constant vector, just break it
3742 // apart into the two scalar constants it contains. Otherwise, bisect the
3743 // ConstantVec, and return each half as a new ConstantVec.
3744 // FIXME: this is hard coded as big endian, it may have to change to support
3745 // SSE and Alpha MVI
3746 if (NumElements == 2) {
3747 Hi = Node->getOperand(0);
3748 Lo = Node->getOperand(1);
3751 std::vector<SDOperand> LoOps, HiOps;
3752 for (unsigned I = 0, E = NumElements; I < E; ++I) {
3753 HiOps.push_back(Node->getOperand(I));
3754 LoOps.push_back(Node->getOperand(I+NumElements));
3756 Lo = DAG.getNode(ISD::ConstantVec, MVT::Vector, LoOps);
3757 Hi = DAG.getNode(ISD::ConstantVec, MVT::Vector, HiOps);
3762 case ISD::BUILD_PAIR:
3763 // Legalize both operands. FIXME: in the future we should handle the case
3764 // where the two elements are not legal.
3765 assert(isTypeLegal(NVT) && "Cannot expand this multiple times yet!");
3766 Lo = LegalizeOp(Node->getOperand(0));
3767 Hi = LegalizeOp(Node->getOperand(1));
3770 case ISD::SIGN_EXTEND_INREG:
3771 ExpandOp(Node->getOperand(0), Lo, Hi);
3772 // Sign extend the lo-part.
3773 Hi = DAG.getNode(ISD::SRA, NVT, Lo,
3774 DAG.getConstant(MVT::getSizeInBits(NVT)-1,
3775 TLI.getShiftAmountTy()));
3776 // sext_inreg the low part if needed.
3777 Lo = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Lo, Node->getOperand(1));
3781 ExpandOp(Node->getOperand(0), Lo, Hi);
3782 SDOperand TempLo = DAG.getNode(ISD::BSWAP, NVT, Hi);
3783 Hi = DAG.getNode(ISD::BSWAP, NVT, Lo);
3789 ExpandOp(Node->getOperand(0), Lo, Hi);
3790 Lo = DAG.getNode(ISD::ADD, NVT, // ctpop(HL) -> ctpop(H)+ctpop(L)
3791 DAG.getNode(ISD::CTPOP, NVT, Lo),
3792 DAG.getNode(ISD::CTPOP, NVT, Hi));
3793 Hi = DAG.getConstant(0, NVT);
3797 // ctlz (HL) -> ctlz(H) != 32 ? ctlz(H) : (ctlz(L)+32)
3798 ExpandOp(Node->getOperand(0), Lo, Hi);
3799 SDOperand BitsC = DAG.getConstant(MVT::getSizeInBits(NVT), NVT);
3800 SDOperand HLZ = DAG.getNode(ISD::CTLZ, NVT, Hi);
3801 SDOperand TopNotZero = DAG.getSetCC(TLI.getSetCCResultTy(), HLZ, BitsC,
3803 SDOperand LowPart = DAG.getNode(ISD::CTLZ, NVT, Lo);
3804 LowPart = DAG.getNode(ISD::ADD, NVT, LowPart, BitsC);
3806 Lo = DAG.getNode(ISD::SELECT, NVT, TopNotZero, HLZ, LowPart);
3807 Hi = DAG.getConstant(0, NVT);
3812 // cttz (HL) -> cttz(L) != 32 ? cttz(L) : (cttz(H)+32)
3813 ExpandOp(Node->getOperand(0), Lo, Hi);
3814 SDOperand BitsC = DAG.getConstant(MVT::getSizeInBits(NVT), NVT);
3815 SDOperand LTZ = DAG.getNode(ISD::CTTZ, NVT, Lo);
3816 SDOperand BotNotZero = DAG.getSetCC(TLI.getSetCCResultTy(), LTZ, BitsC,
3818 SDOperand HiPart = DAG.getNode(ISD::CTTZ, NVT, Hi);
3819 HiPart = DAG.getNode(ISD::ADD, NVT, HiPart, BitsC);
3821 Lo = DAG.getNode(ISD::SELECT, NVT, BotNotZero, LTZ, HiPart);
3822 Hi = DAG.getConstant(0, NVT);
3827 SDOperand Ch = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
3828 SDOperand Ptr = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
3829 Lo = DAG.getLoad(NVT, Ch, Ptr, Node->getOperand(2));
3831 // Increment the pointer to the other half.
3832 unsigned IncrementSize = MVT::getSizeInBits(Lo.getValueType())/8;
3833 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
3834 getIntPtrConstant(IncrementSize));
3835 //Is this safe? declaring that the two parts of the split load
3836 //are from the same instruction?
3837 Hi = DAG.getLoad(NVT, Ch, Ptr, Node->getOperand(2));
3839 // Build a factor node to remember that this load is independent of the
3841 SDOperand TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
3844 // Remember that we legalized the chain.
3845 AddLegalizedOperand(Op.getValue(1), TF);
3846 if (!TLI.isLittleEndian())
3851 SDOperand Ch = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
3852 SDOperand Ptr = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
3853 unsigned NumElements =cast<ConstantSDNode>(Node->getOperand(2))->getValue();
3854 MVT::ValueType EVT = cast<VTSDNode>(Node->getOperand(3))->getVT();
3856 // If we only have two elements, turn into a pair of scalar loads.
3857 // FIXME: handle case where a vector of two elements is fine, such as
3858 // 2 x double on SSE2.
3859 if (NumElements == 2) {
3860 Lo = DAG.getLoad(EVT, Ch, Ptr, Node->getOperand(4));
3861 // Increment the pointer to the other half.
3862 unsigned IncrementSize = MVT::getSizeInBits(EVT)/8;
3863 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
3864 getIntPtrConstant(IncrementSize));
3865 //Is this safe? declaring that the two parts of the split load
3866 //are from the same instruction?
3867 Hi = DAG.getLoad(EVT, Ch, Ptr, Node->getOperand(4));
3869 NumElements /= 2; // Split the vector in half
3870 Lo = DAG.getVecLoad(NumElements, EVT, Ch, Ptr, Node->getOperand(4));
3871 unsigned IncrementSize = NumElements * MVT::getSizeInBits(EVT)/8;
3872 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
3873 getIntPtrConstant(IncrementSize));
3874 //Is this safe? declaring that the two parts of the split load
3875 //are from the same instruction?
3876 Hi = DAG.getVecLoad(NumElements, EVT, Ch, Ptr, Node->getOperand(4));
3879 // Build a factor node to remember that this load is independent of the
3881 SDOperand TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
3884 // Remember that we legalized the chain.
3885 AddLegalizedOperand(Op.getValue(1), TF);
3886 if (!TLI.isLittleEndian())
3893 unsigned NumElements =cast<ConstantSDNode>(Node->getOperand(2))->getValue();
3894 MVT::ValueType EVT = cast<VTSDNode>(Node->getOperand(3))->getVT();
3895 SDOperand LL, LH, RL, RH;
3897 ExpandOp(Node->getOperand(0), LL, LH);
3898 ExpandOp(Node->getOperand(1), RL, RH);
3900 // If we only have two elements, turn into a pair of scalar loads.
3901 // FIXME: handle case where a vector of two elements is fine, such as
3902 // 2 x double on SSE2.
3903 if (NumElements == 2) {
3904 unsigned Opc = getScalarizedOpcode(Node->getOpcode(), EVT);
3905 Lo = DAG.getNode(Opc, EVT, LL, RL);
3906 Hi = DAG.getNode(Opc, EVT, LH, RH);
3908 Lo = DAG.getNode(Node->getOpcode(), MVT::Vector, LL, RL, LL.getOperand(2),
3910 Hi = DAG.getNode(Node->getOpcode(), MVT::Vector, LH, RH, LH.getOperand(2),
3917 SDOperand Chain = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
3918 SDOperand Callee = LegalizeOp(Node->getOperand(1)); // Legalize the callee.
3920 bool Changed = false;
3921 std::vector<SDOperand> Ops;
3922 for (unsigned i = 2, e = Node->getNumOperands(); i != e; ++i) {
3923 Ops.push_back(LegalizeOp(Node->getOperand(i)));
3924 Changed |= Ops.back() != Node->getOperand(i);
3927 assert(Node->getNumValues() == 2 && Op.ResNo == 0 &&
3928 "Can only expand a call once so far, not i64 -> i16!");
3930 std::vector<MVT::ValueType> RetTyVTs;
3931 RetTyVTs.reserve(3);
3932 RetTyVTs.push_back(NVT);
3933 RetTyVTs.push_back(NVT);
3934 RetTyVTs.push_back(MVT::Other);
3935 SDNode *NC = DAG.getCall(RetTyVTs, Chain, Callee, Ops,
3936 Node->getOpcode() == ISD::TAILCALL);
3937 Lo = SDOperand(NC, 0);
3938 Hi = SDOperand(NC, 1);
3940 // Insert the new chain mapping.
3941 AddLegalizedOperand(Op.getValue(1), Hi.getValue(2));
3946 case ISD::XOR: { // Simple logical operators -> two trivial pieces.
3947 SDOperand LL, LH, RL, RH;
3948 ExpandOp(Node->getOperand(0), LL, LH);
3949 ExpandOp(Node->getOperand(1), RL, RH);
3950 Lo = DAG.getNode(Node->getOpcode(), NVT, LL, RL);
3951 Hi = DAG.getNode(Node->getOpcode(), NVT, LH, RH);
3955 SDOperand C, LL, LH, RL, RH;
3957 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3958 case Expand: assert(0 && "It's impossible to expand bools");
3960 C = LegalizeOp(Node->getOperand(0)); // Legalize the condition.
3963 C = PromoteOp(Node->getOperand(0)); // Promote the condition.
3966 ExpandOp(Node->getOperand(1), LL, LH);
3967 ExpandOp(Node->getOperand(2), RL, RH);
3968 Lo = DAG.getNode(ISD::SELECT, NVT, C, LL, RL);
3969 Hi = DAG.getNode(ISD::SELECT, NVT, C, LH, RH);
3972 case ISD::SELECT_CC: {
3973 SDOperand TL, TH, FL, FH;
3974 ExpandOp(Node->getOperand(2), TL, TH);
3975 ExpandOp(Node->getOperand(3), FL, FH);
3976 Lo = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0),
3977 Node->getOperand(1), TL, FL, Node->getOperand(4));
3978 Hi = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0),
3979 Node->getOperand(1), TH, FH, Node->getOperand(4));
3980 Lo = LegalizeOp(Lo);
3981 Hi = LegalizeOp(Hi);
3984 case ISD::SEXTLOAD: {
3985 SDOperand Chain = LegalizeOp(Node->getOperand(0));
3986 SDOperand Ptr = LegalizeOp(Node->getOperand(1));
3987 MVT::ValueType EVT = cast<VTSDNode>(Node->getOperand(3))->getVT();
3990 Lo = DAG.getLoad(NVT, Chain, Ptr, Node->getOperand(2));
3992 Lo = DAG.getExtLoad(ISD::SEXTLOAD, NVT, Chain, Ptr, Node->getOperand(2),
3995 // Remember that we legalized the chain.
3996 AddLegalizedOperand(SDOperand(Node, 1), Lo.getValue(1));
3998 // The high part is obtained by SRA'ing all but one of the bits of the lo
4000 unsigned LoSize = MVT::getSizeInBits(Lo.getValueType());
4001 Hi = DAG.getNode(ISD::SRA, NVT, Lo, DAG.getConstant(LoSize-1,
4002 TLI.getShiftAmountTy()));
4003 Lo = LegalizeOp(Lo);
4004 Hi = LegalizeOp(Hi);
4007 case ISD::ZEXTLOAD: {
4008 SDOperand Chain = LegalizeOp(Node->getOperand(0));
4009 SDOperand Ptr = LegalizeOp(Node->getOperand(1));
4010 MVT::ValueType EVT = cast<VTSDNode>(Node->getOperand(3))->getVT();
4013 Lo = DAG.getLoad(NVT, Chain, Ptr, Node->getOperand(2));
4015 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, NVT, Chain, Ptr, Node->getOperand(2),
4018 // Remember that we legalized the chain.
4019 AddLegalizedOperand(SDOperand(Node, 1), Lo.getValue(1));
4021 // The high part is just a zero.
4022 Hi = LegalizeOp(DAG.getConstant(0, NVT));
4023 Lo = LegalizeOp(Lo);
4026 case ISD::EXTLOAD: {
4027 SDOperand Chain = LegalizeOp(Node->getOperand(0));
4028 SDOperand Ptr = LegalizeOp(Node->getOperand(1));
4029 MVT::ValueType EVT = cast<VTSDNode>(Node->getOperand(3))->getVT();
4032 Lo = DAG.getLoad(NVT, Chain, Ptr, Node->getOperand(2));
4034 Lo = DAG.getExtLoad(ISD::EXTLOAD, NVT, Chain, Ptr, Node->getOperand(2),
4037 // Remember that we legalized the chain.
4038 AddLegalizedOperand(SDOperand(Node, 1), Lo.getValue(1));
4040 // The high part is undefined.
4041 Hi = LegalizeOp(DAG.getNode(ISD::UNDEF, NVT));
4042 Lo = LegalizeOp(Lo);
4045 case ISD::ANY_EXTEND: {
4047 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4048 case Expand: assert(0 && "expand-expand not implemented yet!");
4049 case Legal: In = LegalizeOp(Node->getOperand(0)); break;
4051 In = PromoteOp(Node->getOperand(0));
4055 // The low part is any extension of the input (which degenerates to a copy).
4056 Lo = DAG.getNode(ISD::ANY_EXTEND, NVT, In);
4057 // The high part is undefined.
4058 Hi = DAG.getNode(ISD::UNDEF, NVT);
4061 case ISD::SIGN_EXTEND: {
4063 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4064 case Expand: assert(0 && "expand-expand not implemented yet!");
4065 case Legal: In = LegalizeOp(Node->getOperand(0)); break;
4067 In = PromoteOp(Node->getOperand(0));
4068 // Emit the appropriate sign_extend_inreg to get the value we want.
4069 In = DAG.getNode(ISD::SIGN_EXTEND_INREG, In.getValueType(), In,
4070 DAG.getValueType(Node->getOperand(0).getValueType()));
4074 // The low part is just a sign extension of the input (which degenerates to
4076 Lo = DAG.getNode(ISD::SIGN_EXTEND, NVT, In);
4078 // The high part is obtained by SRA'ing all but one of the bits of the lo
4080 unsigned LoSize = MVT::getSizeInBits(Lo.getValueType());
4081 Hi = DAG.getNode(ISD::SRA, NVT, Lo, DAG.getConstant(LoSize-1,
4082 TLI.getShiftAmountTy()));
4085 case ISD::ZERO_EXTEND: {
4087 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4088 case Expand: assert(0 && "expand-expand not implemented yet!");
4089 case Legal: In = LegalizeOp(Node->getOperand(0)); break;
4091 In = PromoteOp(Node->getOperand(0));
4092 // Emit the appropriate zero_extend_inreg to get the value we want.
4093 In = DAG.getZeroExtendInReg(In, Node->getOperand(0).getValueType());
4097 // The low part is just a zero extension of the input (which degenerates to
4099 Lo = DAG.getNode(ISD::ZERO_EXTEND, NVT, In);
4101 // The high part is just a zero.
4102 Hi = DAG.getConstant(0, NVT);
4106 case ISD::BIT_CONVERT: {
4107 SDOperand Tmp = ExpandBIT_CONVERT(Node->getValueType(0),
4108 Node->getOperand(0));
4109 ExpandOp(Tmp, Lo, Hi);
4113 case ISD::READCYCLECOUNTER: {
4114 assert(TLI.getOperationAction(ISD::READCYCLECOUNTER, VT) ==
4115 TargetLowering::Custom &&
4116 "Must custom expand ReadCycleCounter");
4117 SDOperand T = TLI.LowerOperation(Op, DAG);
4118 assert(T.Val && "Node must be custom expanded!");
4119 Lo = LegalizeOp(T.getValue(0));
4120 Hi = LegalizeOp(T.getValue(1));
4121 AddLegalizedOperand(SDOperand(Node, 1), // Remember we legalized the chain.
4122 LegalizeOp(T.getValue(2)));
4126 // These operators cannot be expanded directly, emit them as calls to
4127 // library functions.
4128 case ISD::FP_TO_SINT:
4129 if (TLI.getOperationAction(ISD::FP_TO_SINT, VT) == TargetLowering::Custom) {
4131 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4132 case Expand: assert(0 && "cannot expand FP!");
4133 case Legal: Op = LegalizeOp(Node->getOperand(0)); break;
4134 case Promote: Op = PromoteOp(Node->getOperand(0)); break;
4137 Op = TLI.LowerOperation(DAG.getNode(ISD::FP_TO_SINT, VT, Op), DAG);
4139 // Now that the custom expander is done, expand the result, which is still
4142 ExpandOp(Op, Lo, Hi);
4147 if (Node->getOperand(0).getValueType() == MVT::f32)
4148 Lo = ExpandLibCall("__fixsfdi", Node, Hi);
4150 Lo = ExpandLibCall("__fixdfdi", Node, Hi);
4153 case ISD::FP_TO_UINT:
4154 if (TLI.getOperationAction(ISD::FP_TO_UINT, VT) == TargetLowering::Custom) {
4155 SDOperand Op = DAG.getNode(ISD::FP_TO_UINT, VT,
4156 LegalizeOp(Node->getOperand(0)));
4157 // Now that the custom expander is done, expand the result, which is still
4159 Op = TLI.LowerOperation(Op, DAG);
4161 ExpandOp(Op, Lo, Hi);
4166 if (Node->getOperand(0).getValueType() == MVT::f32)
4167 Lo = ExpandLibCall("__fixunssfdi", Node, Hi);
4169 Lo = ExpandLibCall("__fixunsdfdi", Node, Hi);
4173 // If the target wants custom lowering, do so.
4174 SDOperand ShiftAmt = LegalizeOp(Node->getOperand(1));
4175 if (TLI.getOperationAction(ISD::SHL, VT) == TargetLowering::Custom) {
4176 SDOperand Op = DAG.getNode(ISD::SHL, VT, Node->getOperand(0),
4178 Op = TLI.LowerOperation(Op, DAG);
4180 // Now that the custom expander is done, expand the result, which is
4182 ExpandOp(Op, Lo, Hi);
4187 // If we can emit an efficient shift operation, do so now.
4188 if (ExpandShift(ISD::SHL, Node->getOperand(0), ShiftAmt, Lo, Hi))
4191 // If this target supports SHL_PARTS, use it.
4192 TargetLowering::LegalizeAction Action =
4193 TLI.getOperationAction(ISD::SHL_PARTS, NVT);
4194 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) ||
4195 Action == TargetLowering::Custom) {
4196 ExpandShiftParts(ISD::SHL_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi);
4200 // Otherwise, emit a libcall.
4201 Lo = ExpandLibCall("__ashldi3", Node, Hi);
4206 // If the target wants custom lowering, do so.
4207 SDOperand ShiftAmt = LegalizeOp(Node->getOperand(1));
4208 if (TLI.getOperationAction(ISD::SRA, VT) == TargetLowering::Custom) {
4209 SDOperand Op = DAG.getNode(ISD::SRA, VT, Node->getOperand(0),
4211 Op = TLI.LowerOperation(Op, DAG);
4213 // Now that the custom expander is done, expand the result, which is
4215 ExpandOp(Op, Lo, Hi);
4220 // If we can emit an efficient shift operation, do so now.
4221 if (ExpandShift(ISD::SRA, Node->getOperand(0), ShiftAmt, Lo, Hi))
4224 // If this target supports SRA_PARTS, use it.
4225 TargetLowering::LegalizeAction Action =
4226 TLI.getOperationAction(ISD::SRA_PARTS, NVT);
4227 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) ||
4228 Action == TargetLowering::Custom) {
4229 ExpandShiftParts(ISD::SRA_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi);
4233 // Otherwise, emit a libcall.
4234 Lo = ExpandLibCall("__ashrdi3", Node, Hi);
4239 // If the target wants custom lowering, do so.
4240 SDOperand ShiftAmt = LegalizeOp(Node->getOperand(1));
4241 if (TLI.getOperationAction(ISD::SRL, VT) == TargetLowering::Custom) {
4242 SDOperand Op = DAG.getNode(ISD::SRL, VT, Node->getOperand(0),
4244 Op = TLI.LowerOperation(Op, DAG);
4246 // Now that the custom expander is done, expand the result, which is
4248 ExpandOp(Op, Lo, Hi);
4253 // If we can emit an efficient shift operation, do so now.
4254 if (ExpandShift(ISD::SRL, Node->getOperand(0), ShiftAmt, Lo, Hi))
4257 // If this target supports SRL_PARTS, use it.
4258 TargetLowering::LegalizeAction Action =
4259 TLI.getOperationAction(ISD::SRL_PARTS, NVT);
4260 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) ||
4261 Action == TargetLowering::Custom) {
4262 ExpandShiftParts(ISD::SRL_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi);
4266 // Otherwise, emit a libcall.
4267 Lo = ExpandLibCall("__lshrdi3", Node, Hi);
4272 ExpandByParts(ISD::ADD_PARTS, Node->getOperand(0), Node->getOperand(1),
4276 ExpandByParts(ISD::SUB_PARTS, Node->getOperand(0), Node->getOperand(1),
4280 if (TLI.isOperationLegal(ISD::MULHU, NVT)) {
4281 SDOperand LL, LH, RL, RH;
4282 ExpandOp(Node->getOperand(0), LL, LH);
4283 ExpandOp(Node->getOperand(1), RL, RH);
4284 unsigned SH = MVT::getSizeInBits(RH.getValueType())-1;
4285 // MULHS implicitly sign extends its inputs. Check to see if ExpandOp
4286 // extended the sign bit of the low half through the upper half, and if so
4287 // emit a MULHS instead of the alternate sequence that is valid for any
4288 // i64 x i64 multiply.
4289 if (TLI.isOperationLegal(ISD::MULHS, NVT) &&
4290 // is RH an extension of the sign bit of RL?
4291 RH.getOpcode() == ISD::SRA && RH.getOperand(0) == RL &&
4292 RH.getOperand(1).getOpcode() == ISD::Constant &&
4293 cast<ConstantSDNode>(RH.getOperand(1))->getValue() == SH &&
4294 // is LH an extension of the sign bit of LL?
4295 LH.getOpcode() == ISD::SRA && LH.getOperand(0) == LL &&
4296 LH.getOperand(1).getOpcode() == ISD::Constant &&
4297 cast<ConstantSDNode>(LH.getOperand(1))->getValue() == SH) {
4298 Hi = DAG.getNode(ISD::MULHS, NVT, LL, RL);
4300 Hi = DAG.getNode(ISD::MULHU, NVT, LL, RL);
4301 RH = DAG.getNode(ISD::MUL, NVT, LL, RH);
4302 LH = DAG.getNode(ISD::MUL, NVT, LH, RL);
4303 Hi = DAG.getNode(ISD::ADD, NVT, Hi, RH);
4304 Hi = DAG.getNode(ISD::ADD, NVT, Hi, LH);
4306 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL);
4308 Lo = ExpandLibCall("__muldi3" , Node, Hi); break;
4312 case ISD::SDIV: Lo = ExpandLibCall("__divdi3" , Node, Hi); break;
4313 case ISD::UDIV: Lo = ExpandLibCall("__udivdi3", Node, Hi); break;
4314 case ISD::SREM: Lo = ExpandLibCall("__moddi3" , Node, Hi); break;
4315 case ISD::UREM: Lo = ExpandLibCall("__umoddi3", Node, Hi); break;
4318 // Make sure the resultant values have been legalized themselves, unless this
4319 // is a type that requires multi-step expansion.
4320 if (getTypeAction(NVT) != Expand && NVT != MVT::isVoid) {
4321 Lo = LegalizeOp(Lo);
4322 Hi = LegalizeOp(Hi);
4325 // Remember in a map if the values will be reused later.
4327 ExpandedNodes.insert(std::make_pair(Op, std::make_pair(Lo, Hi))).second;
4328 assert(isNew && "Value already expanded?!?");
4332 // SelectionDAG::Legalize - This is the entry point for the file.
4334 void SelectionDAG::Legalize() {
4335 /// run - This is the main entry point to this class.
4337 SelectionDAGLegalize(*this).Run();