1 //===-- LegalizeDAG.cpp - Implement SelectionDAG::Legalize ----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the SelectionDAG::Legalize method.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/CodeGen/SelectionDAG.h"
15 #include "llvm/CodeGen/MachineFunction.h"
16 #include "llvm/CodeGen/MachineFrameInfo.h"
17 #include "llvm/CodeGen/MachineJumpTableInfo.h"
18 #include "llvm/CodeGen/MachineModuleInfo.h"
19 #include "llvm/CodeGen/PseudoSourceValue.h"
20 #include "llvm/Target/TargetFrameInfo.h"
21 #include "llvm/Target/TargetLowering.h"
22 #include "llvm/Target/TargetData.h"
23 #include "llvm/Target/TargetMachine.h"
24 #include "llvm/Target/TargetOptions.h"
25 #include "llvm/Target/TargetSubtarget.h"
26 #include "llvm/CallingConv.h"
27 #include "llvm/Constants.h"
28 #include "llvm/DerivedTypes.h"
29 #include "llvm/Support/CommandLine.h"
30 #include "llvm/Support/Compiler.h"
31 #include "llvm/Support/MathExtras.h"
32 #include "llvm/ADT/DenseMap.h"
33 #include "llvm/ADT/SmallVector.h"
34 #include "llvm/ADT/SmallPtrSet.h"
38 //===----------------------------------------------------------------------===//
39 /// SelectionDAGLegalize - This takes an arbitrary SelectionDAG as input and
40 /// hacks on it until the target machine can handle it. This involves
41 /// eliminating value sizes the machine cannot handle (promoting small sizes to
42 /// large sizes or splitting up large values into small values) as well as
43 /// eliminating operations the machine cannot handle.
45 /// This code also does a small amount of optimization and recognition of idioms
46 /// as part of its processing. For example, if a target does not support a
47 /// 'setcc' instruction efficiently, but does support 'brcc' instruction, this
48 /// will attempt merge setcc and brc instructions into brcc's.
51 class VISIBILITY_HIDDEN SelectionDAGLegalize {
54 bool TypesNeedLegalizing;
56 // Libcall insertion helpers.
58 /// LastCALLSEQ_END - This keeps track of the CALLSEQ_END node that has been
59 /// legalized. We use this to ensure that calls are properly serialized
60 /// against each other, including inserted libcalls.
61 SDValue LastCALLSEQ_END;
63 /// IsLegalizingCall - This member is used *only* for purposes of providing
64 /// helpful assertions that a libcall isn't created while another call is
65 /// being legalized (which could lead to non-serialized call sequences).
66 bool IsLegalizingCall;
69 Legal, // The target natively supports this operation.
70 Promote, // This operation should be executed in a larger type.
71 Expand // Try to expand this to other ops, otherwise use a libcall.
74 /// ValueTypeActions - This is a bitvector that contains two bits for each
75 /// value type, where the two bits correspond to the LegalizeAction enum.
76 /// This can be queried with "getTypeAction(VT)".
77 TargetLowering::ValueTypeActionImpl ValueTypeActions;
79 /// LegalizedNodes - For nodes that are of legal width, and that have more
80 /// than one use, this map indicates what regularized operand to use. This
81 /// allows us to avoid legalizing the same thing more than once.
82 DenseMap<SDValue, SDValue> LegalizedNodes;
84 /// PromotedNodes - For nodes that are below legal width, and that have more
85 /// than one use, this map indicates what promoted value to use. This allows
86 /// us to avoid promoting the same thing more than once.
87 DenseMap<SDValue, SDValue> PromotedNodes;
89 /// ExpandedNodes - For nodes that need to be expanded this map indicates
90 /// which operands are the expanded version of the input. This allows
91 /// us to avoid expanding the same node more than once.
92 DenseMap<SDValue, std::pair<SDValue, SDValue> > ExpandedNodes;
94 /// SplitNodes - For vector nodes that need to be split, this map indicates
95 /// which operands are the split version of the input. This allows us
96 /// to avoid splitting the same node more than once.
97 std::map<SDValue, std::pair<SDValue, SDValue> > SplitNodes;
99 /// ScalarizedNodes - For nodes that need to be converted from vector types to
100 /// scalar types, this contains the mapping of ones we have already
101 /// processed to the result.
102 std::map<SDValue, SDValue> ScalarizedNodes;
104 /// WidenNodes - For nodes that need to be widened from one vector type to
105 /// another, this contains the mapping of those that we have already widen.
106 /// This allows us to avoid widening more than once.
107 std::map<SDValue, SDValue> WidenNodes;
109 void AddLegalizedOperand(SDValue From, SDValue To) {
110 LegalizedNodes.insert(std::make_pair(From, To));
111 // If someone requests legalization of the new node, return itself.
113 LegalizedNodes.insert(std::make_pair(To, To));
115 void AddPromotedOperand(SDValue From, SDValue To) {
116 bool isNew = PromotedNodes.insert(std::make_pair(From, To)).second;
117 assert(isNew && "Got into the map somehow?");
119 // If someone requests legalization of the new node, return itself.
120 LegalizedNodes.insert(std::make_pair(To, To));
122 void AddWidenedOperand(SDValue From, SDValue To) {
123 bool isNew = WidenNodes.insert(std::make_pair(From, To)).second;
124 assert(isNew && "Got into the map somehow?");
126 // If someone requests legalization of the new node, return itself.
127 LegalizedNodes.insert(std::make_pair(To, To));
131 explicit SelectionDAGLegalize(SelectionDAG &DAG, bool TypesNeedLegalizing);
133 /// getTypeAction - Return how we should legalize values of this type, either
134 /// it is already legal or we need to expand it into multiple registers of
135 /// smaller integer type, or we need to promote it to a larger type.
136 LegalizeAction getTypeAction(MVT VT) const {
137 return (LegalizeAction)ValueTypeActions.getTypeAction(VT);
140 /// isTypeLegal - Return true if this type is legal on this target.
142 bool isTypeLegal(MVT VT) const {
143 return getTypeAction(VT) == Legal;
149 /// HandleOp - Legalize, Promote, or Expand the specified operand as
150 /// appropriate for its type.
151 void HandleOp(SDValue Op);
153 /// LegalizeOp - We know that the specified value has a legal type.
154 /// Recursively ensure that the operands have legal types, then return the
156 SDValue LegalizeOp(SDValue O);
158 /// UnrollVectorOp - We know that the given vector has a legal type, however
159 /// the operation it performs is not legal and is an operation that we have
160 /// no way of lowering. "Unroll" the vector, splitting out the scalars and
161 /// operating on each element individually.
162 SDValue UnrollVectorOp(SDValue O);
164 /// PerformInsertVectorEltInMemory - Some target cannot handle a variable
165 /// insertion index for the INSERT_VECTOR_ELT instruction. In this case, it
166 /// is necessary to spill the vector being inserted into to memory, perform
167 /// the insert there, and then read the result back.
168 SDValue PerformInsertVectorEltInMemory(SDValue Vec, SDValue Val,
171 /// PromoteOp - Given an operation that produces a value in an invalid type,
172 /// promote it to compute the value into a larger type. The produced value
173 /// will have the correct bits for the low portion of the register, but no
174 /// guarantee is made about the top bits: it may be zero, sign-extended, or
176 SDValue PromoteOp(SDValue O);
178 /// ExpandOp - Expand the specified SDValue into its two component pieces
179 /// Lo&Hi. Note that the Op MUST be an expanded type. As a result of this,
180 /// the LegalizedNodes map is filled in for any results that are not expanded,
181 /// the ExpandedNodes map is filled in for any results that are expanded, and
182 /// the Lo/Hi values are returned. This applies to integer types and Vector
184 void ExpandOp(SDValue O, SDValue &Lo, SDValue &Hi);
186 /// WidenVectorOp - Widen a vector operation to a wider type given by WidenVT
187 /// (e.g., v3i32 to v4i32). The produced value will have the correct value
188 /// for the existing elements but no guarantee is made about the new elements
189 /// at the end of the vector: it may be zero, ones, or garbage. This is useful
190 /// when we have an instruction operating on an illegal vector type and we
191 /// want to widen it to do the computation on a legal wider vector type.
192 SDValue WidenVectorOp(SDValue Op, MVT WidenVT);
194 /// SplitVectorOp - Given an operand of vector type, break it down into
195 /// two smaller values.
196 void SplitVectorOp(SDValue O, SDValue &Lo, SDValue &Hi);
198 /// ScalarizeVectorOp - Given an operand of single-element vector type
199 /// (e.g. v1f32), convert it into the equivalent operation that returns a
200 /// scalar (e.g. f32) value.
201 SDValue ScalarizeVectorOp(SDValue O);
203 /// Useful 16 element vector type that is used to pass operands for widening.
204 typedef SmallVector<SDValue, 16> SDValueVector;
206 /// LoadWidenVectorOp - Load a vector for a wider type. Returns true if
207 /// the LdChain contains a single load and false if it contains a token
208 /// factor for multiple loads. It takes
209 /// Result: location to return the result
210 /// LdChain: location to return the load chain
211 /// Op: load operation to widen
212 /// NVT: widen vector result type we want for the load
213 bool LoadWidenVectorOp(SDValue& Result, SDValue& LdChain,
214 SDValue Op, MVT NVT);
216 /// Helper genWidenVectorLoads - Helper function to generate a set of
217 /// loads to load a vector with a resulting wider type. It takes
218 /// LdChain: list of chains for the load we have generated
219 /// Chain: incoming chain for the ld vector
220 /// BasePtr: base pointer to load from
221 /// SV: memory disambiguation source value
222 /// SVOffset: memory disambiugation offset
223 /// Alignment: alignment of the memory
224 /// isVolatile: volatile load
225 /// LdWidth: width of memory that we want to load
226 /// ResType: the wider result result type for the resulting loaded vector
227 SDValue genWidenVectorLoads(SDValueVector& LdChain, SDValue Chain,
228 SDValue BasePtr, const Value *SV,
229 int SVOffset, unsigned Alignment,
230 bool isVolatile, unsigned LdWidth,
233 /// StoreWidenVectorOp - Stores a widen vector into non widen memory
234 /// location. It takes
235 /// ST: store node that we want to replace
236 /// Chain: incoming store chain
237 /// BasePtr: base address of where we want to store into
238 SDValue StoreWidenVectorOp(StoreSDNode *ST, SDValue Chain,
241 /// Helper genWidenVectorStores - Helper function to generate a set of
242 /// stores to store a widen vector into non widen memory
244 // StChain: list of chains for the stores we have generated
245 // Chain: incoming chain for the ld vector
246 // BasePtr: base pointer to load from
247 // SV: memory disambiguation source value
248 // SVOffset: memory disambiugation offset
249 // Alignment: alignment of the memory
250 // isVolatile: volatile lod
251 // ValOp: value to store
252 // StWidth: width of memory that we want to store
253 void genWidenVectorStores(SDValueVector& StChain, SDValue Chain,
254 SDValue BasePtr, const Value *SV,
255 int SVOffset, unsigned Alignment,
256 bool isVolatile, SDValue ValOp,
259 /// isShuffleLegal - Return non-null if a vector shuffle is legal with the
260 /// specified mask and type. Targets can specify exactly which masks they
261 /// support and the code generator is tasked with not creating illegal masks.
263 /// Note that this will also return true for shuffles that are promoted to a
266 /// If this is a legal shuffle, this method returns the (possibly promoted)
267 /// build_vector Mask. If it's not a legal shuffle, it returns null.
268 SDNode *isShuffleLegal(MVT VT, SDValue Mask) const;
270 bool LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest,
271 SmallPtrSet<SDNode*, 32> &NodesLeadingTo);
273 void LegalizeSetCCOperands(SDValue &LHS, SDValue &RHS, SDValue &CC);
274 void LegalizeSetCCCondCode(MVT VT, SDValue &LHS, SDValue &RHS, SDValue &CC);
275 void LegalizeSetCC(MVT VT, SDValue &LHS, SDValue &RHS, SDValue &CC) {
276 LegalizeSetCCOperands(LHS, RHS, CC);
277 LegalizeSetCCCondCode(VT, LHS, RHS, CC);
280 SDValue ExpandLibCall(RTLIB::Libcall LC, SDNode *Node, bool isSigned,
282 SDValue ExpandIntToFP(bool isSigned, MVT DestTy, SDValue Source);
284 SDValue EmitStackConvert(SDValue SrcOp, MVT SlotVT, MVT DestVT);
285 SDValue ExpandBUILD_VECTOR(SDNode *Node);
286 SDValue ExpandSCALAR_TO_VECTOR(SDNode *Node);
287 SDValue LegalizeINT_TO_FP(SDValue Result, bool isSigned, MVT DestTy, SDValue Op);
288 SDValue ExpandLegalINT_TO_FP(bool isSigned, SDValue LegalOp, MVT DestVT);
289 SDValue PromoteLegalINT_TO_FP(SDValue LegalOp, MVT DestVT, bool isSigned);
290 SDValue PromoteLegalFP_TO_INT(SDValue LegalOp, MVT DestVT, bool isSigned);
292 SDValue ExpandBSWAP(SDValue Op);
293 SDValue ExpandBitCount(unsigned Opc, SDValue Op);
294 bool ExpandShift(unsigned Opc, SDValue Op, SDValue Amt,
295 SDValue &Lo, SDValue &Hi);
296 void ExpandShiftParts(unsigned NodeOp, SDValue Op, SDValue Amt,
297 SDValue &Lo, SDValue &Hi);
299 SDValue ExpandEXTRACT_SUBVECTOR(SDValue Op);
300 SDValue ExpandEXTRACT_VECTOR_ELT(SDValue Op);
302 // Returns the legalized (truncated or extended) shift amount.
303 SDValue LegalizeShiftAmount(SDValue ShiftAmt);
307 /// isVectorShuffleLegal - Return true if a vector shuffle is legal with the
308 /// specified mask and type. Targets can specify exactly which masks they
309 /// support and the code generator is tasked with not creating illegal masks.
311 /// Note that this will also return true for shuffles that are promoted to a
313 SDNode *SelectionDAGLegalize::isShuffleLegal(MVT VT, SDValue Mask) const {
314 switch (TLI.getOperationAction(ISD::VECTOR_SHUFFLE, VT)) {
316 case TargetLowering::Legal:
317 case TargetLowering::Custom:
319 case TargetLowering::Promote: {
320 // If this is promoted to a different type, convert the shuffle mask and
321 // ask if it is legal in the promoted type!
322 MVT NVT = TLI.getTypeToPromoteTo(ISD::VECTOR_SHUFFLE, VT);
323 MVT EltVT = NVT.getVectorElementType();
325 // If we changed # elements, change the shuffle mask.
326 unsigned NumEltsGrowth =
327 NVT.getVectorNumElements() / VT.getVectorNumElements();
328 assert(NumEltsGrowth && "Cannot promote to vector type with fewer elts!");
329 if (NumEltsGrowth > 1) {
330 // Renumber the elements.
331 SmallVector<SDValue, 8> Ops;
332 for (unsigned i = 0, e = Mask.getNumOperands(); i != e; ++i) {
333 SDValue InOp = Mask.getOperand(i);
334 for (unsigned j = 0; j != NumEltsGrowth; ++j) {
335 if (InOp.getOpcode() == ISD::UNDEF)
336 Ops.push_back(DAG.getNode(ISD::UNDEF, EltVT));
338 unsigned InEltNo = cast<ConstantSDNode>(InOp)->getZExtValue();
339 Ops.push_back(DAG.getConstant(InEltNo*NumEltsGrowth+j, EltVT));
343 Mask = DAG.getNode(ISD::BUILD_VECTOR, NVT, &Ops[0], Ops.size());
349 return TLI.isShuffleMaskLegal(Mask, VT) ? Mask.getNode() : 0;
352 SelectionDAGLegalize::SelectionDAGLegalize(SelectionDAG &dag, bool types)
353 : TLI(dag.getTargetLoweringInfo()), DAG(dag), TypesNeedLegalizing(types),
354 ValueTypeActions(TLI.getValueTypeActions()) {
355 assert(MVT::LAST_VALUETYPE <= 32 &&
356 "Too many value types for ValueTypeActions to hold!");
359 void SelectionDAGLegalize::LegalizeDAG() {
360 LastCALLSEQ_END = DAG.getEntryNode();
361 IsLegalizingCall = false;
363 // The legalize process is inherently a bottom-up recursive process (users
364 // legalize their uses before themselves). Given infinite stack space, we
365 // could just start legalizing on the root and traverse the whole graph. In
366 // practice however, this causes us to run out of stack space on large basic
367 // blocks. To avoid this problem, compute an ordering of the nodes where each
368 // node is only legalized after all of its operands are legalized.
369 DAG.AssignTopologicalOrder();
370 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(),
371 E = prior(DAG.allnodes_end()); I != next(E); ++I)
372 HandleOp(SDValue(I, 0));
374 // Finally, it's possible the root changed. Get the new root.
375 SDValue OldRoot = DAG.getRoot();
376 assert(LegalizedNodes.count(OldRoot) && "Root didn't get legalized?");
377 DAG.setRoot(LegalizedNodes[OldRoot]);
379 ExpandedNodes.clear();
380 LegalizedNodes.clear();
381 PromotedNodes.clear();
383 ScalarizedNodes.clear();
386 // Remove dead nodes now.
387 DAG.RemoveDeadNodes();
391 /// FindCallEndFromCallStart - Given a chained node that is part of a call
392 /// sequence, find the CALLSEQ_END node that terminates the call sequence.
393 static SDNode *FindCallEndFromCallStart(SDNode *Node) {
394 if (Node->getOpcode() == ISD::CALLSEQ_END)
396 if (Node->use_empty())
397 return 0; // No CallSeqEnd
399 // The chain is usually at the end.
400 SDValue TheChain(Node, Node->getNumValues()-1);
401 if (TheChain.getValueType() != MVT::Other) {
402 // Sometimes it's at the beginning.
403 TheChain = SDValue(Node, 0);
404 if (TheChain.getValueType() != MVT::Other) {
405 // Otherwise, hunt for it.
406 for (unsigned i = 1, e = Node->getNumValues(); i != e; ++i)
407 if (Node->getValueType(i) == MVT::Other) {
408 TheChain = SDValue(Node, i);
412 // Otherwise, we walked into a node without a chain.
413 if (TheChain.getValueType() != MVT::Other)
418 for (SDNode::use_iterator UI = Node->use_begin(),
419 E = Node->use_end(); UI != E; ++UI) {
421 // Make sure to only follow users of our token chain.
423 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i)
424 if (User->getOperand(i) == TheChain)
425 if (SDNode *Result = FindCallEndFromCallStart(User))
431 /// FindCallStartFromCallEnd - Given a chained node that is part of a call
432 /// sequence, find the CALLSEQ_START node that initiates the call sequence.
433 static SDNode *FindCallStartFromCallEnd(SDNode *Node) {
434 assert(Node && "Didn't find callseq_start for a call??");
435 if (Node->getOpcode() == ISD::CALLSEQ_START) return Node;
437 assert(Node->getOperand(0).getValueType() == MVT::Other &&
438 "Node doesn't have a token chain argument!");
439 return FindCallStartFromCallEnd(Node->getOperand(0).getNode());
442 /// LegalizeAllNodesNotLeadingTo - Recursively walk the uses of N, looking to
443 /// see if any uses can reach Dest. If no dest operands can get to dest,
444 /// legalize them, legalize ourself, and return false, otherwise, return true.
446 /// Keep track of the nodes we fine that actually do lead to Dest in
447 /// NodesLeadingTo. This avoids retraversing them exponential number of times.
449 bool SelectionDAGLegalize::LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest,
450 SmallPtrSet<SDNode*, 32> &NodesLeadingTo) {
451 if (N == Dest) return true; // N certainly leads to Dest :)
453 // If we've already processed this node and it does lead to Dest, there is no
454 // need to reprocess it.
455 if (NodesLeadingTo.count(N)) return true;
457 // If the first result of this node has been already legalized, then it cannot
459 switch (getTypeAction(N->getValueType(0))) {
461 if (LegalizedNodes.count(SDValue(N, 0))) return false;
464 if (PromotedNodes.count(SDValue(N, 0))) return false;
467 if (ExpandedNodes.count(SDValue(N, 0))) return false;
471 // Okay, this node has not already been legalized. Check and legalize all
472 // operands. If none lead to Dest, then we can legalize this node.
473 bool OperandsLeadToDest = false;
474 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
475 OperandsLeadToDest |= // If an operand leads to Dest, so do we.
476 LegalizeAllNodesNotLeadingTo(N->getOperand(i).getNode(), Dest, NodesLeadingTo);
478 if (OperandsLeadToDest) {
479 NodesLeadingTo.insert(N);
483 // Okay, this node looks safe, legalize it and return false.
484 HandleOp(SDValue(N, 0));
488 /// HandleOp - Legalize, Promote, Widen, or Expand the specified operand as
489 /// appropriate for its type.
490 void SelectionDAGLegalize::HandleOp(SDValue Op) {
491 MVT VT = Op.getValueType();
492 // If the type legalizer was run then we should never see any illegal result
493 // types here except for target constants (the type legalizer does not touch
494 // those) or for build vector used as a mask for a vector shuffle.
495 // FIXME: We can removed the BUILD_VECTOR case when we fix PR2957.
496 assert((TypesNeedLegalizing || getTypeAction(VT) == Legal ||
497 Op.getOpcode() == ISD::TargetConstant ||
498 Op.getOpcode() == ISD::BUILD_VECTOR) &&
499 "Illegal type introduced after type legalization?");
500 switch (getTypeAction(VT)) {
501 default: assert(0 && "Bad type action!");
502 case Legal: (void)LegalizeOp(Op); break;
504 if (!VT.isVector()) {
509 // See if we can widen otherwise use Expand to either scalarize or split
510 MVT WidenVT = TLI.getWidenVectorType(VT);
511 if (WidenVT != MVT::Other) {
512 (void) WidenVectorOp(Op, WidenVT);
515 // else fall thru to expand since we can't widen the vector
518 if (!VT.isVector()) {
519 // If this is an illegal scalar, expand it into its two component
522 if (Op.getOpcode() == ISD::TargetConstant)
523 break; // Allow illegal target nodes.
525 } else if (VT.getVectorNumElements() == 1) {
526 // If this is an illegal single element vector, convert it to a
528 (void)ScalarizeVectorOp(Op);
530 // This is an illegal multiple element vector.
531 // Split it in half and legalize both parts.
533 SplitVectorOp(Op, X, Y);
539 /// ExpandConstantFP - Expands the ConstantFP node to an integer constant or
540 /// a load from the constant pool.
541 static SDValue ExpandConstantFP(ConstantFPSDNode *CFP, bool UseCP,
542 SelectionDAG &DAG, TargetLowering &TLI) {
545 // If a FP immediate is precise when represented as a float and if the
546 // target can do an extending load from float to double, we put it into
547 // the constant pool as a float, even if it's is statically typed as a
548 // double. This shrinks FP constants and canonicalizes them for targets where
549 // an FP extending load is the same cost as a normal load (such as on the x87
550 // fp stack or PPC FP unit).
551 MVT VT = CFP->getValueType(0);
552 ConstantFP *LLVMC = const_cast<ConstantFP*>(CFP->getConstantFPValue());
554 if (VT!=MVT::f64 && VT!=MVT::f32)
555 assert(0 && "Invalid type expansion");
556 return DAG.getConstant(LLVMC->getValueAPF().bitcastToAPInt(),
557 (VT == MVT::f64) ? MVT::i64 : MVT::i32);
562 while (SVT != MVT::f32) {
563 SVT = (MVT::SimpleValueType)(SVT.getSimpleVT() - 1);
564 if (CFP->isValueValidForType(SVT, CFP->getValueAPF()) &&
565 // Only do this if the target has a native EXTLOAD instruction from
567 TLI.isLoadExtLegal(ISD::EXTLOAD, SVT) &&
568 TLI.ShouldShrinkFPConstant(OrigVT)) {
569 const Type *SType = SVT.getTypeForMVT();
570 LLVMC = cast<ConstantFP>(ConstantExpr::getFPTrunc(LLVMC, SType));
576 SDValue CPIdx = DAG.getConstantPool(LLVMC, TLI.getPointerTy());
577 unsigned Alignment = 1 << cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
579 return DAG.getExtLoad(ISD::EXTLOAD, OrigVT, DAG.getEntryNode(),
580 CPIdx, PseudoSourceValue::getConstantPool(),
581 0, VT, false, Alignment);
582 return DAG.getLoad(OrigVT, DAG.getEntryNode(), CPIdx,
583 PseudoSourceValue::getConstantPool(), 0, false, Alignment);
587 /// ExpandFCOPYSIGNToBitwiseOps - Expands fcopysign to a series of bitwise
590 SDValue ExpandFCOPYSIGNToBitwiseOps(SDNode *Node, MVT NVT,
591 SelectionDAG &DAG, TargetLowering &TLI) {
592 MVT VT = Node->getValueType(0);
593 MVT SrcVT = Node->getOperand(1).getValueType();
594 assert((SrcVT == MVT::f32 || SrcVT == MVT::f64) &&
595 "fcopysign expansion only supported for f32 and f64");
596 MVT SrcNVT = (SrcVT == MVT::f64) ? MVT::i64 : MVT::i32;
598 // First get the sign bit of second operand.
599 SDValue Mask1 = (SrcVT == MVT::f64)
600 ? DAG.getConstantFP(BitsToDouble(1ULL << 63), SrcVT)
601 : DAG.getConstantFP(BitsToFloat(1U << 31), SrcVT);
602 Mask1 = DAG.getNode(ISD::BIT_CONVERT, SrcNVT, Mask1);
603 SDValue SignBit= DAG.getNode(ISD::BIT_CONVERT, SrcNVT, Node->getOperand(1));
604 SignBit = DAG.getNode(ISD::AND, SrcNVT, SignBit, Mask1);
605 // Shift right or sign-extend it if the two operands have different types.
606 int SizeDiff = SrcNVT.getSizeInBits() - NVT.getSizeInBits();
608 SignBit = DAG.getNode(ISD::SRL, SrcNVT, SignBit,
609 DAG.getConstant(SizeDiff, TLI.getShiftAmountTy()));
610 SignBit = DAG.getNode(ISD::TRUNCATE, NVT, SignBit);
611 } else if (SizeDiff < 0) {
612 SignBit = DAG.getNode(ISD::ZERO_EXTEND, NVT, SignBit);
613 SignBit = DAG.getNode(ISD::SHL, NVT, SignBit,
614 DAG.getConstant(-SizeDiff, TLI.getShiftAmountTy()));
617 // Clear the sign bit of first operand.
618 SDValue Mask2 = (VT == MVT::f64)
619 ? DAG.getConstantFP(BitsToDouble(~(1ULL << 63)), VT)
620 : DAG.getConstantFP(BitsToFloat(~(1U << 31)), VT);
621 Mask2 = DAG.getNode(ISD::BIT_CONVERT, NVT, Mask2);
622 SDValue Result = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0));
623 Result = DAG.getNode(ISD::AND, NVT, Result, Mask2);
625 // Or the value with the sign bit.
626 Result = DAG.getNode(ISD::OR, NVT, Result, SignBit);
630 /// ExpandUnalignedStore - Expands an unaligned store to 2 half-size stores.
632 SDValue ExpandUnalignedStore(StoreSDNode *ST, SelectionDAG &DAG,
633 TargetLowering &TLI) {
634 SDValue Chain = ST->getChain();
635 SDValue Ptr = ST->getBasePtr();
636 SDValue Val = ST->getValue();
637 MVT VT = Val.getValueType();
638 int Alignment = ST->getAlignment();
639 int SVOffset = ST->getSrcValueOffset();
640 if (ST->getMemoryVT().isFloatingPoint() ||
641 ST->getMemoryVT().isVector()) {
642 MVT intVT = MVT::getIntegerVT(VT.getSizeInBits());
643 if (TLI.isTypeLegal(intVT)) {
644 // Expand to a bitconvert of the value to the integer type of the
645 // same size, then a (misaligned) int store.
646 // FIXME: Does not handle truncating floating point stores!
647 SDValue Result = DAG.getNode(ISD::BIT_CONVERT, intVT, Val);
648 return DAG.getStore(Chain, Result, Ptr, ST->getSrcValue(),
649 SVOffset, ST->isVolatile(), Alignment);
651 // Do a (aligned) store to a stack slot, then copy from the stack slot
652 // to the final destination using (unaligned) integer loads and stores.
653 MVT StoredVT = ST->getMemoryVT();
655 TLI.getRegisterType(MVT::getIntegerVT(StoredVT.getSizeInBits()));
656 unsigned StoredBytes = StoredVT.getSizeInBits() / 8;
657 unsigned RegBytes = RegVT.getSizeInBits() / 8;
658 unsigned NumRegs = (StoredBytes + RegBytes - 1) / RegBytes;
660 // Make sure the stack slot is also aligned for the register type.
661 SDValue StackPtr = DAG.CreateStackTemporary(StoredVT, RegVT);
663 // Perform the original store, only redirected to the stack slot.
664 SDValue Store = DAG.getTruncStore(Chain, Val, StackPtr, NULL, 0,StoredVT);
665 SDValue Increment = DAG.getConstant(RegBytes, TLI.getPointerTy());
666 SmallVector<SDValue, 8> Stores;
669 // Do all but one copies using the full register width.
670 for (unsigned i = 1; i < NumRegs; i++) {
671 // Load one integer register's worth from the stack slot.
672 SDValue Load = DAG.getLoad(RegVT, Store, StackPtr, NULL, 0);
673 // Store it to the final location. Remember the store.
674 Stores.push_back(DAG.getStore(Load.getValue(1), Load, Ptr,
675 ST->getSrcValue(), SVOffset + Offset,
677 MinAlign(ST->getAlignment(), Offset)));
678 // Increment the pointers.
680 StackPtr = DAG.getNode(ISD::ADD, StackPtr.getValueType(), StackPtr,
682 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr, Increment);
685 // The last store may be partial. Do a truncating store. On big-endian
686 // machines this requires an extending load from the stack slot to ensure
687 // that the bits are in the right place.
688 MVT MemVT = MVT::getIntegerVT(8 * (StoredBytes - Offset));
690 // Load from the stack slot.
691 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, RegVT, Store, StackPtr,
694 Stores.push_back(DAG.getTruncStore(Load.getValue(1), Load, Ptr,
695 ST->getSrcValue(), SVOffset + Offset,
696 MemVT, ST->isVolatile(),
697 MinAlign(ST->getAlignment(), Offset)));
698 // The order of the stores doesn't matter - say it with a TokenFactor.
699 return DAG.getNode(ISD::TokenFactor, MVT::Other, &Stores[0],
703 assert(ST->getMemoryVT().isInteger() &&
704 !ST->getMemoryVT().isVector() &&
705 "Unaligned store of unknown type.");
706 // Get the half-size VT
708 (MVT::SimpleValueType)(ST->getMemoryVT().getSimpleVT() - 1);
709 int NumBits = NewStoredVT.getSizeInBits();
710 int IncrementSize = NumBits / 8;
712 // Divide the stored value in two parts.
713 SDValue ShiftAmount = DAG.getConstant(NumBits, TLI.getShiftAmountTy());
715 SDValue Hi = DAG.getNode(ISD::SRL, VT, Val, ShiftAmount);
717 // Store the two parts
718 SDValue Store1, Store2;
719 Store1 = DAG.getTruncStore(Chain, TLI.isLittleEndian()?Lo:Hi, Ptr,
720 ST->getSrcValue(), SVOffset, NewStoredVT,
721 ST->isVolatile(), Alignment);
722 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
723 DAG.getConstant(IncrementSize, TLI.getPointerTy()));
724 Alignment = MinAlign(Alignment, IncrementSize);
725 Store2 = DAG.getTruncStore(Chain, TLI.isLittleEndian()?Hi:Lo, Ptr,
726 ST->getSrcValue(), SVOffset + IncrementSize,
727 NewStoredVT, ST->isVolatile(), Alignment);
729 return DAG.getNode(ISD::TokenFactor, MVT::Other, Store1, Store2);
732 /// ExpandUnalignedLoad - Expands an unaligned load to 2 half-size loads.
734 SDValue ExpandUnalignedLoad(LoadSDNode *LD, SelectionDAG &DAG,
735 TargetLowering &TLI) {
736 int SVOffset = LD->getSrcValueOffset();
737 SDValue Chain = LD->getChain();
738 SDValue Ptr = LD->getBasePtr();
739 MVT VT = LD->getValueType(0);
740 MVT LoadedVT = LD->getMemoryVT();
741 if (VT.isFloatingPoint() || VT.isVector()) {
742 MVT intVT = MVT::getIntegerVT(LoadedVT.getSizeInBits());
743 if (TLI.isTypeLegal(intVT)) {
744 // Expand to a (misaligned) integer load of the same size,
745 // then bitconvert to floating point or vector.
746 SDValue newLoad = DAG.getLoad(intVT, Chain, Ptr, LD->getSrcValue(),
747 SVOffset, LD->isVolatile(),
749 SDValue Result = DAG.getNode(ISD::BIT_CONVERT, LoadedVT, newLoad);
750 if (VT.isFloatingPoint() && LoadedVT != VT)
751 Result = DAG.getNode(ISD::FP_EXTEND, VT, Result);
753 SDValue Ops[] = { Result, Chain };
754 return DAG.getMergeValues(Ops, 2);
756 // Copy the value to a (aligned) stack slot using (unaligned) integer
757 // loads and stores, then do a (aligned) load from the stack slot.
758 MVT RegVT = TLI.getRegisterType(intVT);
759 unsigned LoadedBytes = LoadedVT.getSizeInBits() / 8;
760 unsigned RegBytes = RegVT.getSizeInBits() / 8;
761 unsigned NumRegs = (LoadedBytes + RegBytes - 1) / RegBytes;
763 // Make sure the stack slot is also aligned for the register type.
764 SDValue StackBase = DAG.CreateStackTemporary(LoadedVT, RegVT);
766 SDValue Increment = DAG.getConstant(RegBytes, TLI.getPointerTy());
767 SmallVector<SDValue, 8> Stores;
768 SDValue StackPtr = StackBase;
771 // Do all but one copies using the full register width.
772 for (unsigned i = 1; i < NumRegs; i++) {
773 // Load one integer register's worth from the original location.
774 SDValue Load = DAG.getLoad(RegVT, Chain, Ptr, LD->getSrcValue(),
775 SVOffset + Offset, LD->isVolatile(),
776 MinAlign(LD->getAlignment(), Offset));
777 // Follow the load with a store to the stack slot. Remember the store.
778 Stores.push_back(DAG.getStore(Load.getValue(1), Load, StackPtr,
780 // Increment the pointers.
782 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr, Increment);
783 StackPtr = DAG.getNode(ISD::ADD, StackPtr.getValueType(), StackPtr,
787 // The last copy may be partial. Do an extending load.
788 MVT MemVT = MVT::getIntegerVT(8 * (LoadedBytes - Offset));
789 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, RegVT, Chain, Ptr,
790 LD->getSrcValue(), SVOffset + Offset,
791 MemVT, LD->isVolatile(),
792 MinAlign(LD->getAlignment(), Offset));
793 // Follow the load with a store to the stack slot. Remember the store.
794 // On big-endian machines this requires a truncating store to ensure
795 // that the bits end up in the right place.
796 Stores.push_back(DAG.getTruncStore(Load.getValue(1), Load, StackPtr,
799 // The order of the stores doesn't matter - say it with a TokenFactor.
800 SDValue TF = DAG.getNode(ISD::TokenFactor, MVT::Other, &Stores[0],
803 // Finally, perform the original load only redirected to the stack slot.
804 Load = DAG.getExtLoad(LD->getExtensionType(), VT, TF, StackBase,
807 // Callers expect a MERGE_VALUES node.
808 SDValue Ops[] = { Load, TF };
809 return DAG.getMergeValues(Ops, 2);
812 assert(LoadedVT.isInteger() && !LoadedVT.isVector() &&
813 "Unaligned load of unsupported type.");
815 // Compute the new VT that is half the size of the old one. This is an
817 unsigned NumBits = LoadedVT.getSizeInBits();
819 NewLoadedVT = MVT::getIntegerVT(NumBits/2);
822 unsigned Alignment = LD->getAlignment();
823 unsigned IncrementSize = NumBits / 8;
824 ISD::LoadExtType HiExtType = LD->getExtensionType();
826 // If the original load is NON_EXTLOAD, the hi part load must be ZEXTLOAD.
827 if (HiExtType == ISD::NON_EXTLOAD)
828 HiExtType = ISD::ZEXTLOAD;
830 // Load the value in two parts
832 if (TLI.isLittleEndian()) {
833 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, VT, Chain, Ptr, LD->getSrcValue(),
834 SVOffset, NewLoadedVT, LD->isVolatile(), Alignment);
835 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
836 DAG.getConstant(IncrementSize, TLI.getPointerTy()));
837 Hi = DAG.getExtLoad(HiExtType, VT, Chain, Ptr, LD->getSrcValue(),
838 SVOffset + IncrementSize, NewLoadedVT, LD->isVolatile(),
839 MinAlign(Alignment, IncrementSize));
841 Hi = DAG.getExtLoad(HiExtType, VT, Chain, Ptr, LD->getSrcValue(), SVOffset,
842 NewLoadedVT,LD->isVolatile(), Alignment);
843 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
844 DAG.getConstant(IncrementSize, TLI.getPointerTy()));
845 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, VT, Chain, Ptr, LD->getSrcValue(),
846 SVOffset + IncrementSize, NewLoadedVT, LD->isVolatile(),
847 MinAlign(Alignment, IncrementSize));
850 // aggregate the two parts
851 SDValue ShiftAmount = DAG.getConstant(NumBits, TLI.getShiftAmountTy());
852 SDValue Result = DAG.getNode(ISD::SHL, VT, Hi, ShiftAmount);
853 Result = DAG.getNode(ISD::OR, VT, Result, Lo);
855 SDValue TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
858 SDValue Ops[] = { Result, TF };
859 return DAG.getMergeValues(Ops, 2);
862 /// UnrollVectorOp - We know that the given vector has a legal type, however
863 /// the operation it performs is not legal and is an operation that we have
864 /// no way of lowering. "Unroll" the vector, splitting out the scalars and
865 /// operating on each element individually.
866 SDValue SelectionDAGLegalize::UnrollVectorOp(SDValue Op) {
867 MVT VT = Op.getValueType();
868 assert(isTypeLegal(VT) &&
869 "Caller should expand or promote operands that are not legal!");
870 assert(Op.getNode()->getNumValues() == 1 &&
871 "Can't unroll a vector with multiple results!");
872 unsigned NE = VT.getVectorNumElements();
873 MVT EltVT = VT.getVectorElementType();
875 SmallVector<SDValue, 8> Scalars;
876 SmallVector<SDValue, 4> Operands(Op.getNumOperands());
877 for (unsigned i = 0; i != NE; ++i) {
878 for (unsigned j = 0; j != Op.getNumOperands(); ++j) {
879 SDValue Operand = Op.getOperand(j);
880 MVT OperandVT = Operand.getValueType();
881 if (OperandVT.isVector()) {
882 // A vector operand; extract a single element.
883 MVT OperandEltVT = OperandVT.getVectorElementType();
884 Operands[j] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT,
887 DAG.getConstant(i, MVT::i32));
889 // A scalar operand; just use it as is.
890 Operands[j] = Operand;
894 switch (Op.getOpcode()) {
896 Scalars.push_back(DAG.getNode(Op.getOpcode(), EltVT,
897 &Operands[0], Operands.size()));
902 Scalars.push_back(DAG.getNode(Op.getOpcode(), EltVT, Operands[0],
903 LegalizeShiftAmount(Operands[1])));
908 return DAG.getNode(ISD::BUILD_VECTOR, VT, &Scalars[0], Scalars.size());
911 /// GetFPLibCall - Return the right libcall for the given floating point type.
912 static RTLIB::Libcall GetFPLibCall(MVT VT,
913 RTLIB::Libcall Call_F32,
914 RTLIB::Libcall Call_F64,
915 RTLIB::Libcall Call_F80,
916 RTLIB::Libcall Call_PPCF128) {
918 VT == MVT::f32 ? Call_F32 :
919 VT == MVT::f64 ? Call_F64 :
920 VT == MVT::f80 ? Call_F80 :
921 VT == MVT::ppcf128 ? Call_PPCF128 :
922 RTLIB::UNKNOWN_LIBCALL;
925 /// PerformInsertVectorEltInMemory - Some target cannot handle a variable
926 /// insertion index for the INSERT_VECTOR_ELT instruction. In this case, it
927 /// is necessary to spill the vector being inserted into to memory, perform
928 /// the insert there, and then read the result back.
929 SDValue SelectionDAGLegalize::
930 PerformInsertVectorEltInMemory(SDValue Vec, SDValue Val, SDValue Idx) {
935 // If the target doesn't support this, we have to spill the input vector
936 // to a temporary stack slot, update the element, then reload it. This is
937 // badness. We could also load the value into a vector register (either
938 // with a "move to register" or "extload into register" instruction, then
939 // permute it into place, if the idx is a constant and if the idx is
940 // supported by the target.
941 MVT VT = Tmp1.getValueType();
942 MVT EltVT = VT.getVectorElementType();
943 MVT IdxVT = Tmp3.getValueType();
944 MVT PtrVT = TLI.getPointerTy();
945 SDValue StackPtr = DAG.CreateStackTemporary(VT);
947 int SPFI = cast<FrameIndexSDNode>(StackPtr.getNode())->getIndex();
950 SDValue Ch = DAG.getStore(DAG.getEntryNode(), Tmp1, StackPtr,
951 PseudoSourceValue::getFixedStack(SPFI), 0);
953 // Truncate or zero extend offset to target pointer type.
954 unsigned CastOpc = IdxVT.bitsGT(PtrVT) ? ISD::TRUNCATE : ISD::ZERO_EXTEND;
955 Tmp3 = DAG.getNode(CastOpc, PtrVT, Tmp3);
956 // Add the offset to the index.
957 unsigned EltSize = EltVT.getSizeInBits()/8;
958 Tmp3 = DAG.getNode(ISD::MUL, IdxVT, Tmp3,DAG.getConstant(EltSize, IdxVT));
959 SDValue StackPtr2 = DAG.getNode(ISD::ADD, IdxVT, Tmp3, StackPtr);
960 // Store the scalar value.
961 Ch = DAG.getTruncStore(Ch, Tmp2, StackPtr2,
962 PseudoSourceValue::getFixedStack(SPFI), 0, EltVT);
963 // Load the updated vector.
964 return DAG.getLoad(VT, Ch, StackPtr,
965 PseudoSourceValue::getFixedStack(SPFI), 0);
968 SDValue SelectionDAGLegalize::LegalizeShiftAmount(SDValue ShiftAmt) {
969 if (TLI.getShiftAmountTy().bitsLT(ShiftAmt.getValueType()))
970 return DAG.getNode(ISD::TRUNCATE, TLI.getShiftAmountTy(), ShiftAmt);
972 if (TLI.getShiftAmountTy().bitsGT(ShiftAmt.getValueType()))
973 return DAG.getNode(ISD::ANY_EXTEND, TLI.getShiftAmountTy(), ShiftAmt);
979 /// LegalizeOp - We know that the specified value has a legal type, and
980 /// that its operands are legal. Now ensure that the operation itself
981 /// is legal, recursively ensuring that the operands' operations remain
983 SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
984 if (Op.getOpcode() == ISD::TargetConstant) // Allow illegal target nodes.
987 assert(isTypeLegal(Op.getValueType()) &&
988 "Caller should expand or promote operands that are not legal!");
989 SDNode *Node = Op.getNode();
991 // If this operation defines any values that cannot be represented in a
992 // register on this target, make sure to expand or promote them.
993 if (Node->getNumValues() > 1) {
994 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
995 if (getTypeAction(Node->getValueType(i)) != Legal) {
996 HandleOp(Op.getValue(i));
997 assert(LegalizedNodes.count(Op) &&
998 "Handling didn't add legal operands!");
999 return LegalizedNodes[Op];
1003 // Note that LegalizeOp may be reentered even from single-use nodes, which
1004 // means that we always must cache transformed nodes.
1005 DenseMap<SDValue, SDValue>::iterator I = LegalizedNodes.find(Op);
1006 if (I != LegalizedNodes.end()) return I->second;
1008 SDValue Tmp1, Tmp2, Tmp3, Tmp4;
1009 SDValue Result = Op;
1010 bool isCustom = false;
1012 switch (Node->getOpcode()) {
1013 case ISD::FrameIndex:
1014 case ISD::EntryToken:
1016 case ISD::BasicBlock:
1017 case ISD::TargetFrameIndex:
1018 case ISD::TargetJumpTable:
1019 case ISD::TargetConstant:
1020 case ISD::TargetConstantFP:
1021 case ISD::TargetConstantPool:
1022 case ISD::TargetGlobalAddress:
1023 case ISD::TargetGlobalTLSAddress:
1024 case ISD::TargetExternalSymbol:
1025 case ISD::VALUETYPE:
1027 case ISD::MEMOPERAND:
1029 case ISD::ARG_FLAGS:
1030 // Primitives must all be legal.
1031 assert(TLI.isOperationLegal(Node->getOpcode(), Node->getValueType(0)) &&
1032 "This must be legal!");
1035 if (Node->getOpcode() >= ISD::BUILTIN_OP_END) {
1036 // If this is a target node, legalize it by legalizing the operands then
1037 // passing it through.
1038 SmallVector<SDValue, 8> Ops;
1039 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
1040 Ops.push_back(LegalizeOp(Node->getOperand(i)));
1042 Result = DAG.UpdateNodeOperands(Result.getValue(0), &Ops[0], Ops.size());
1044 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
1045 AddLegalizedOperand(Op.getValue(i), Result.getValue(i));
1046 return Result.getValue(Op.getResNo());
1048 // Otherwise this is an unhandled builtin node. splat.
1050 cerr << "NODE: "; Node->dump(&DAG); cerr << "\n";
1052 assert(0 && "Do not know how to legalize this operator!");
1054 case ISD::GLOBAL_OFFSET_TABLE:
1055 case ISD::GlobalAddress:
1056 case ISD::GlobalTLSAddress:
1057 case ISD::ExternalSymbol:
1058 case ISD::ConstantPool:
1059 case ISD::JumpTable: // Nothing to do.
1060 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
1061 default: assert(0 && "This action is not supported yet!");
1062 case TargetLowering::Custom:
1063 Tmp1 = TLI.LowerOperation(Op, DAG);
1064 if (Tmp1.getNode()) Result = Tmp1;
1065 // FALLTHROUGH if the target doesn't want to lower this op after all.
1066 case TargetLowering::Legal:
1070 case ISD::FRAMEADDR:
1071 case ISD::RETURNADDR:
1072 // The only option for these nodes is to custom lower them. If the target
1073 // does not custom lower them, then return zero.
1074 Tmp1 = TLI.LowerOperation(Op, DAG);
1078 Result = DAG.getConstant(0, TLI.getPointerTy());
1080 case ISD::FRAME_TO_ARGS_OFFSET: {
1081 MVT VT = Node->getValueType(0);
1082 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
1083 default: assert(0 && "This action is not supported yet!");
1084 case TargetLowering::Custom:
1085 Result = TLI.LowerOperation(Op, DAG);
1086 if (Result.getNode()) break;
1088 case TargetLowering::Legal:
1089 Result = DAG.getConstant(0, VT);
1094 case ISD::EXCEPTIONADDR: {
1095 Tmp1 = LegalizeOp(Node->getOperand(0));
1096 MVT VT = Node->getValueType(0);
1097 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
1098 default: assert(0 && "This action is not supported yet!");
1099 case TargetLowering::Expand: {
1100 unsigned Reg = TLI.getExceptionAddressRegister();
1101 Result = DAG.getCopyFromReg(Tmp1, Reg, VT);
1104 case TargetLowering::Custom:
1105 Result = TLI.LowerOperation(Op, DAG);
1106 if (Result.getNode()) break;
1108 case TargetLowering::Legal: {
1109 SDValue Ops[] = { DAG.getConstant(0, VT), Tmp1 };
1110 Result = DAG.getMergeValues(Ops, 2);
1115 if (Result.getNode()->getNumValues() == 1) break;
1117 assert(Result.getNode()->getNumValues() == 2 &&
1118 "Cannot return more than two values!");
1120 // Since we produced two values, make sure to remember that we
1121 // legalized both of them.
1122 Tmp1 = LegalizeOp(Result);
1123 Tmp2 = LegalizeOp(Result.getValue(1));
1124 AddLegalizedOperand(Op.getValue(0), Tmp1);
1125 AddLegalizedOperand(Op.getValue(1), Tmp2);
1126 return Op.getResNo() ? Tmp2 : Tmp1;
1127 case ISD::EHSELECTION: {
1128 Tmp1 = LegalizeOp(Node->getOperand(0));
1129 Tmp2 = LegalizeOp(Node->getOperand(1));
1130 MVT VT = Node->getValueType(0);
1131 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
1132 default: assert(0 && "This action is not supported yet!");
1133 case TargetLowering::Expand: {
1134 unsigned Reg = TLI.getExceptionSelectorRegister();
1135 Result = DAG.getCopyFromReg(Tmp2, Reg, VT);
1138 case TargetLowering::Custom:
1139 Result = TLI.LowerOperation(Op, DAG);
1140 if (Result.getNode()) break;
1142 case TargetLowering::Legal: {
1143 SDValue Ops[] = { DAG.getConstant(0, VT), Tmp2 };
1144 Result = DAG.getMergeValues(Ops, 2);
1149 if (Result.getNode()->getNumValues() == 1) break;
1151 assert(Result.getNode()->getNumValues() == 2 &&
1152 "Cannot return more than two values!");
1154 // Since we produced two values, make sure to remember that we
1155 // legalized both of them.
1156 Tmp1 = LegalizeOp(Result);
1157 Tmp2 = LegalizeOp(Result.getValue(1));
1158 AddLegalizedOperand(Op.getValue(0), Tmp1);
1159 AddLegalizedOperand(Op.getValue(1), Tmp2);
1160 return Op.getResNo() ? Tmp2 : Tmp1;
1161 case ISD::EH_RETURN: {
1162 MVT VT = Node->getValueType(0);
1163 // The only "good" option for this node is to custom lower it.
1164 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
1165 default: assert(0 && "This action is not supported at all!");
1166 case TargetLowering::Custom:
1167 Result = TLI.LowerOperation(Op, DAG);
1168 if (Result.getNode()) break;
1170 case TargetLowering::Legal:
1171 // Target does not know, how to lower this, lower to noop
1172 Result = LegalizeOp(Node->getOperand(0));
1177 case ISD::AssertSext:
1178 case ISD::AssertZext:
1179 Tmp1 = LegalizeOp(Node->getOperand(0));
1180 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
1182 case ISD::MERGE_VALUES:
1183 // Legalize eliminates MERGE_VALUES nodes.
1184 Result = Node->getOperand(Op.getResNo());
1186 case ISD::CopyFromReg:
1187 Tmp1 = LegalizeOp(Node->getOperand(0));
1188 Result = Op.getValue(0);
1189 if (Node->getNumValues() == 2) {
1190 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
1192 assert(Node->getNumValues() == 3 && "Invalid copyfromreg!");
1193 if (Node->getNumOperands() == 3) {
1194 Tmp2 = LegalizeOp(Node->getOperand(2));
1195 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1),Tmp2);
1197 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
1199 AddLegalizedOperand(Op.getValue(2), Result.getValue(2));
1201 // Since CopyFromReg produces two values, make sure to remember that we
1202 // legalized both of them.
1203 AddLegalizedOperand(Op.getValue(0), Result);
1204 AddLegalizedOperand(Op.getValue(1), Result.getValue(1));
1205 return Result.getValue(Op.getResNo());
1207 MVT VT = Op.getValueType();
1208 switch (TLI.getOperationAction(ISD::UNDEF, VT)) {
1209 default: assert(0 && "This action is not supported yet!");
1210 case TargetLowering::Expand:
1212 Result = DAG.getConstant(0, VT);
1213 else if (VT.isFloatingPoint())
1214 Result = DAG.getConstantFP(APFloat(APInt(VT.getSizeInBits(), 0)),
1217 assert(0 && "Unknown value type!");
1219 case TargetLowering::Legal:
1225 case ISD::INTRINSIC_W_CHAIN:
1226 case ISD::INTRINSIC_WO_CHAIN:
1227 case ISD::INTRINSIC_VOID: {
1228 SmallVector<SDValue, 8> Ops;
1229 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
1230 Ops.push_back(LegalizeOp(Node->getOperand(i)));
1231 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1233 // Allow the target to custom lower its intrinsics if it wants to.
1234 if (TLI.getOperationAction(Node->getOpcode(), MVT::Other) ==
1235 TargetLowering::Custom) {
1236 Tmp3 = TLI.LowerOperation(Result, DAG);
1237 if (Tmp3.getNode()) Result = Tmp3;
1240 if (Result.getNode()->getNumValues() == 1) break;
1242 // Must have return value and chain result.
1243 assert(Result.getNode()->getNumValues() == 2 &&
1244 "Cannot return more than two values!");
1246 // Since loads produce two values, make sure to remember that we
1247 // legalized both of them.
1248 AddLegalizedOperand(SDValue(Node, 0), Result.getValue(0));
1249 AddLegalizedOperand(SDValue(Node, 1), Result.getValue(1));
1250 return Result.getValue(Op.getResNo());
1253 case ISD::DBG_STOPPOINT:
1254 assert(Node->getNumOperands() == 1 && "Invalid DBG_STOPPOINT node!");
1255 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the input chain.
1257 switch (TLI.getOperationAction(ISD::DBG_STOPPOINT, MVT::Other)) {
1258 case TargetLowering::Promote:
1259 default: assert(0 && "This action is not supported yet!");
1260 case TargetLowering::Expand: {
1261 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
1262 bool useDEBUG_LOC = TLI.isOperationLegal(ISD::DEBUG_LOC, MVT::Other);
1263 bool useLABEL = TLI.isOperationLegal(ISD::DBG_LABEL, MVT::Other);
1265 const DbgStopPointSDNode *DSP = cast<DbgStopPointSDNode>(Node);
1266 if (MMI && (useDEBUG_LOC || useLABEL)) {
1267 const CompileUnitDesc *CompileUnit = DSP->getCompileUnit();
1268 unsigned SrcFile = MMI->RecordSource(CompileUnit);
1270 unsigned Line = DSP->getLine();
1271 unsigned Col = DSP->getColumn();
1274 SDValue Ops[] = { Tmp1, DAG.getConstant(Line, MVT::i32),
1275 DAG.getConstant(Col, MVT::i32),
1276 DAG.getConstant(SrcFile, MVT::i32) };
1277 Result = DAG.getNode(ISD::DEBUG_LOC, MVT::Other, Ops, 4);
1279 unsigned ID = MMI->RecordSourceLine(Line, Col, SrcFile);
1280 Result = DAG.getLabel(ISD::DBG_LABEL, Tmp1, ID);
1283 Result = Tmp1; // chain
1287 case TargetLowering::Legal: {
1288 LegalizeAction Action = getTypeAction(Node->getOperand(1).getValueType());
1289 if (Action == Legal && Tmp1 == Node->getOperand(0))
1292 SmallVector<SDValue, 8> Ops;
1293 Ops.push_back(Tmp1);
1294 if (Action == Legal) {
1295 Ops.push_back(Node->getOperand(1)); // line # must be legal.
1296 Ops.push_back(Node->getOperand(2)); // col # must be legal.
1298 // Otherwise promote them.
1299 Ops.push_back(PromoteOp(Node->getOperand(1)));
1300 Ops.push_back(PromoteOp(Node->getOperand(2)));
1302 Ops.push_back(Node->getOperand(3)); // filename must be legal.
1303 Ops.push_back(Node->getOperand(4)); // working dir # must be legal.
1304 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1311 assert(Node->getNumOperands() == 3 && "Invalid DECLARE node!");
1312 switch (TLI.getOperationAction(ISD::DECLARE, MVT::Other)) {
1313 default: assert(0 && "This action is not supported yet!");
1314 case TargetLowering::Legal:
1315 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1316 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the address.
1317 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the variable.
1318 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1320 case TargetLowering::Expand:
1321 Result = LegalizeOp(Node->getOperand(0));
1326 case ISD::DEBUG_LOC:
1327 assert(Node->getNumOperands() == 4 && "Invalid DEBUG_LOC node!");
1328 switch (TLI.getOperationAction(ISD::DEBUG_LOC, MVT::Other)) {
1329 default: assert(0 && "This action is not supported yet!");
1330 case TargetLowering::Legal: {
1331 LegalizeAction Action = getTypeAction(Node->getOperand(1).getValueType());
1332 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1333 if (Action == Legal && Tmp1 == Node->getOperand(0))
1335 if (Action == Legal) {
1336 Tmp2 = Node->getOperand(1);
1337 Tmp3 = Node->getOperand(2);
1338 Tmp4 = Node->getOperand(3);
1340 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the line #.
1341 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the col #.
1342 Tmp4 = LegalizeOp(Node->getOperand(3)); // Legalize the source file id.
1344 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4);
1350 case ISD::DBG_LABEL:
1352 assert(Node->getNumOperands() == 1 && "Invalid LABEL node!");
1353 switch (TLI.getOperationAction(Node->getOpcode(), MVT::Other)) {
1354 default: assert(0 && "This action is not supported yet!");
1355 case TargetLowering::Legal:
1356 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1357 Result = DAG.UpdateNodeOperands(Result, Tmp1);
1359 case TargetLowering::Expand:
1360 Result = LegalizeOp(Node->getOperand(0));
1366 assert(Node->getNumOperands() == 4 && "Invalid Prefetch node!");
1367 switch (TLI.getOperationAction(ISD::PREFETCH, MVT::Other)) {
1368 default: assert(0 && "This action is not supported yet!");
1369 case TargetLowering::Legal:
1370 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1371 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the address.
1372 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the rw specifier.
1373 Tmp4 = LegalizeOp(Node->getOperand(3)); // Legalize locality specifier.
1374 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4);
1376 case TargetLowering::Expand:
1378 Result = LegalizeOp(Node->getOperand(0));
1383 case ISD::MEMBARRIER: {
1384 assert(Node->getNumOperands() == 6 && "Invalid MemBarrier node!");
1385 switch (TLI.getOperationAction(ISD::MEMBARRIER, MVT::Other)) {
1386 default: assert(0 && "This action is not supported yet!");
1387 case TargetLowering::Legal: {
1389 Ops[0] = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1390 for (int x = 1; x < 6; ++x) {
1391 Ops[x] = Node->getOperand(x);
1392 if (!isTypeLegal(Ops[x].getValueType()))
1393 Ops[x] = PromoteOp(Ops[x]);
1395 Result = DAG.UpdateNodeOperands(Result, &Ops[0], 6);
1398 case TargetLowering::Expand:
1399 //There is no libgcc call for this op
1400 Result = Node->getOperand(0); // Noop
1406 case ISD::ATOMIC_CMP_SWAP: {
1407 unsigned int num_operands = 4;
1408 assert(Node->getNumOperands() == num_operands && "Invalid Atomic node!");
1410 for (unsigned int x = 0; x < num_operands; ++x)
1411 Ops[x] = LegalizeOp(Node->getOperand(x));
1412 Result = DAG.UpdateNodeOperands(Result, &Ops[0], num_operands);
1414 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
1415 default: assert(0 && "This action is not supported yet!");
1416 case TargetLowering::Custom:
1417 Result = TLI.LowerOperation(Result, DAG);
1419 case TargetLowering::Legal:
1422 AddLegalizedOperand(SDValue(Node, 0), Result.getValue(0));
1423 AddLegalizedOperand(SDValue(Node, 1), Result.getValue(1));
1424 return Result.getValue(Op.getResNo());
1426 case ISD::ATOMIC_LOAD_ADD:
1427 case ISD::ATOMIC_LOAD_SUB:
1428 case ISD::ATOMIC_LOAD_AND:
1429 case ISD::ATOMIC_LOAD_OR:
1430 case ISD::ATOMIC_LOAD_XOR:
1431 case ISD::ATOMIC_LOAD_NAND:
1432 case ISD::ATOMIC_LOAD_MIN:
1433 case ISD::ATOMIC_LOAD_MAX:
1434 case ISD::ATOMIC_LOAD_UMIN:
1435 case ISD::ATOMIC_LOAD_UMAX:
1436 case ISD::ATOMIC_SWAP: {
1437 unsigned int num_operands = 3;
1438 assert(Node->getNumOperands() == num_operands && "Invalid Atomic node!");
1440 for (unsigned int x = 0; x < num_operands; ++x)
1441 Ops[x] = LegalizeOp(Node->getOperand(x));
1442 Result = DAG.UpdateNodeOperands(Result, &Ops[0], num_operands);
1444 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
1445 default: assert(0 && "This action is not supported yet!");
1446 case TargetLowering::Custom:
1447 Result = TLI.LowerOperation(Result, DAG);
1449 case TargetLowering::Legal:
1452 AddLegalizedOperand(SDValue(Node, 0), Result.getValue(0));
1453 AddLegalizedOperand(SDValue(Node, 1), Result.getValue(1));
1454 return Result.getValue(Op.getResNo());
1456 case ISD::Constant: {
1457 ConstantSDNode *CN = cast<ConstantSDNode>(Node);
1459 TLI.getOperationAction(ISD::Constant, CN->getValueType(0));
1461 // We know we don't need to expand constants here, constants only have one
1462 // value and we check that it is fine above.
1464 if (opAction == TargetLowering::Custom) {
1465 Tmp1 = TLI.LowerOperation(Result, DAG);
1471 case ISD::ConstantFP: {
1472 // Spill FP immediates to the constant pool if the target cannot directly
1473 // codegen them. Targets often have some immediate values that can be
1474 // efficiently generated into an FP register without a load. We explicitly
1475 // leave these constants as ConstantFP nodes for the target to deal with.
1476 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node);
1478 switch (TLI.getOperationAction(ISD::ConstantFP, CFP->getValueType(0))) {
1479 default: assert(0 && "This action is not supported yet!");
1480 case TargetLowering::Legal:
1482 case TargetLowering::Custom:
1483 Tmp3 = TLI.LowerOperation(Result, DAG);
1484 if (Tmp3.getNode()) {
1489 case TargetLowering::Expand: {
1490 // Check to see if this FP immediate is already legal.
1491 bool isLegal = false;
1492 for (TargetLowering::legal_fpimm_iterator I = TLI.legal_fpimm_begin(),
1493 E = TLI.legal_fpimm_end(); I != E; ++I) {
1494 if (CFP->isExactlyValue(*I)) {
1499 // If this is a legal constant, turn it into a TargetConstantFP node.
1502 Result = ExpandConstantFP(CFP, true, DAG, TLI);
1507 case ISD::TokenFactor:
1508 if (Node->getNumOperands() == 2) {
1509 Tmp1 = LegalizeOp(Node->getOperand(0));
1510 Tmp2 = LegalizeOp(Node->getOperand(1));
1511 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1512 } else if (Node->getNumOperands() == 3) {
1513 Tmp1 = LegalizeOp(Node->getOperand(0));
1514 Tmp2 = LegalizeOp(Node->getOperand(1));
1515 Tmp3 = LegalizeOp(Node->getOperand(2));
1516 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1518 SmallVector<SDValue, 8> Ops;
1519 // Legalize the operands.
1520 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
1521 Ops.push_back(LegalizeOp(Node->getOperand(i)));
1522 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1526 case ISD::FORMAL_ARGUMENTS:
1528 // The only option for this is to custom lower it.
1529 Tmp3 = TLI.LowerOperation(Result.getValue(0), DAG);
1530 assert(Tmp3.getNode() && "Target didn't custom lower this node!");
1531 // A call within a calling sequence must be legalized to something
1532 // other than the normal CALLSEQ_END. Violating this gets Legalize
1533 // into an infinite loop.
1534 assert ((!IsLegalizingCall ||
1535 Node->getOpcode() != ISD::CALL ||
1536 Tmp3.getNode()->getOpcode() != ISD::CALLSEQ_END) &&
1537 "Nested CALLSEQ_START..CALLSEQ_END not supported.");
1539 // The number of incoming and outgoing values should match; unless the final
1540 // outgoing value is a flag.
1541 assert((Tmp3.getNode()->getNumValues() == Result.getNode()->getNumValues() ||
1542 (Tmp3.getNode()->getNumValues() == Result.getNode()->getNumValues() + 1 &&
1543 Tmp3.getNode()->getValueType(Tmp3.getNode()->getNumValues() - 1) ==
1545 "Lowering call/formal_arguments produced unexpected # results!");
1547 // Since CALL/FORMAL_ARGUMENTS nodes produce multiple values, make sure to
1548 // remember that we legalized all of them, so it doesn't get relegalized.
1549 for (unsigned i = 0, e = Tmp3.getNode()->getNumValues(); i != e; ++i) {
1550 if (Tmp3.getNode()->getValueType(i) == MVT::Flag)
1552 Tmp1 = LegalizeOp(Tmp3.getValue(i));
1553 if (Op.getResNo() == i)
1555 AddLegalizedOperand(SDValue(Node, i), Tmp1);
1558 case ISD::EXTRACT_SUBREG: {
1559 Tmp1 = LegalizeOp(Node->getOperand(0));
1560 ConstantSDNode *idx = dyn_cast<ConstantSDNode>(Node->getOperand(1));
1561 assert(idx && "Operand must be a constant");
1562 Tmp2 = DAG.getTargetConstant(idx->getAPIntValue(), idx->getValueType(0));
1563 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1566 case ISD::INSERT_SUBREG: {
1567 Tmp1 = LegalizeOp(Node->getOperand(0));
1568 Tmp2 = LegalizeOp(Node->getOperand(1));
1569 ConstantSDNode *idx = dyn_cast<ConstantSDNode>(Node->getOperand(2));
1570 assert(idx && "Operand must be a constant");
1571 Tmp3 = DAG.getTargetConstant(idx->getAPIntValue(), idx->getValueType(0));
1572 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1575 case ISD::BUILD_VECTOR:
1576 switch (TLI.getOperationAction(ISD::BUILD_VECTOR, Node->getValueType(0))) {
1577 default: assert(0 && "This action is not supported yet!");
1578 case TargetLowering::Custom:
1579 Tmp3 = TLI.LowerOperation(Result, DAG);
1580 if (Tmp3.getNode()) {
1585 case TargetLowering::Expand:
1586 Result = ExpandBUILD_VECTOR(Result.getNode());
1590 case ISD::INSERT_VECTOR_ELT:
1591 Tmp1 = LegalizeOp(Node->getOperand(0)); // InVec
1592 Tmp3 = LegalizeOp(Node->getOperand(2)); // InEltNo
1594 // The type of the value to insert may not be legal, even though the vector
1595 // type is legal. Legalize/Promote accordingly. We do not handle Expand
1597 switch (getTypeAction(Node->getOperand(1).getValueType())) {
1598 default: assert(0 && "Cannot expand insert element operand");
1599 case Legal: Tmp2 = LegalizeOp(Node->getOperand(1)); break;
1600 case Promote: Tmp2 = PromoteOp(Node->getOperand(1)); break;
1602 // FIXME: An alternative would be to check to see if the target is not
1603 // going to custom lower this operation, we could bitcast to half elt
1604 // width and perform two inserts at that width, if that is legal.
1605 Tmp2 = Node->getOperand(1);
1608 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1610 switch (TLI.getOperationAction(ISD::INSERT_VECTOR_ELT,
1611 Node->getValueType(0))) {
1612 default: assert(0 && "This action is not supported yet!");
1613 case TargetLowering::Legal:
1615 case TargetLowering::Custom:
1616 Tmp4 = TLI.LowerOperation(Result, DAG);
1617 if (Tmp4.getNode()) {
1622 case TargetLowering::Promote:
1623 // Fall thru for vector case
1624 case TargetLowering::Expand: {
1625 // If the insert index is a constant, codegen this as a scalar_to_vector,
1626 // then a shuffle that inserts it into the right position in the vector.
1627 if (ConstantSDNode *InsertPos = dyn_cast<ConstantSDNode>(Tmp3)) {
1628 // SCALAR_TO_VECTOR requires that the type of the value being inserted
1629 // match the element type of the vector being created.
1630 if (Tmp2.getValueType() ==
1631 Op.getValueType().getVectorElementType()) {
1632 SDValue ScVec = DAG.getNode(ISD::SCALAR_TO_VECTOR,
1633 Tmp1.getValueType(), Tmp2);
1635 unsigned NumElts = Tmp1.getValueType().getVectorNumElements();
1637 MVT::getIntVectorWithNumElements(NumElts);
1638 MVT ShufMaskEltVT = ShufMaskVT.getVectorElementType();
1640 // We generate a shuffle of InVec and ScVec, so the shuffle mask
1641 // should be 0,1,2,3,4,5... with the appropriate element replaced with
1642 // elt 0 of the RHS.
1643 SmallVector<SDValue, 8> ShufOps;
1644 for (unsigned i = 0; i != NumElts; ++i) {
1645 if (i != InsertPos->getZExtValue())
1646 ShufOps.push_back(DAG.getConstant(i, ShufMaskEltVT));
1648 ShufOps.push_back(DAG.getConstant(NumElts, ShufMaskEltVT));
1650 SDValue ShufMask = DAG.getNode(ISD::BUILD_VECTOR, ShufMaskVT,
1651 &ShufOps[0], ShufOps.size());
1653 Result = DAG.getNode(ISD::VECTOR_SHUFFLE, Tmp1.getValueType(),
1654 Tmp1, ScVec, ShufMask);
1655 Result = LegalizeOp(Result);
1659 Result = PerformInsertVectorEltInMemory(Tmp1, Tmp2, Tmp3);
1664 case ISD::SCALAR_TO_VECTOR:
1665 if (!TLI.isTypeLegal(Node->getOperand(0).getValueType())) {
1666 Result = LegalizeOp(ExpandSCALAR_TO_VECTOR(Node));
1670 Tmp1 = LegalizeOp(Node->getOperand(0)); // InVal
1671 Result = DAG.UpdateNodeOperands(Result, Tmp1);
1672 switch (TLI.getOperationAction(ISD::SCALAR_TO_VECTOR,
1673 Node->getValueType(0))) {
1674 default: assert(0 && "This action is not supported yet!");
1675 case TargetLowering::Legal:
1677 case TargetLowering::Custom:
1678 Tmp3 = TLI.LowerOperation(Result, DAG);
1679 if (Tmp3.getNode()) {
1684 case TargetLowering::Expand:
1685 Result = LegalizeOp(ExpandSCALAR_TO_VECTOR(Node));
1689 case ISD::VECTOR_SHUFFLE:
1690 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the input vectors,
1691 Tmp2 = LegalizeOp(Node->getOperand(1)); // but not the shuffle mask.
1692 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
1694 // Allow targets to custom lower the SHUFFLEs they support.
1695 switch (TLI.getOperationAction(ISD::VECTOR_SHUFFLE,Result.getValueType())) {
1696 default: assert(0 && "Unknown operation action!");
1697 case TargetLowering::Legal:
1698 assert(isShuffleLegal(Result.getValueType(), Node->getOperand(2)) &&
1699 "vector shuffle should not be created if not legal!");
1701 case TargetLowering::Custom:
1702 Tmp3 = TLI.LowerOperation(Result, DAG);
1703 if (Tmp3.getNode()) {
1708 case TargetLowering::Expand: {
1709 MVT VT = Node->getValueType(0);
1710 MVT EltVT = VT.getVectorElementType();
1711 MVT PtrVT = TLI.getPointerTy();
1712 SDValue Mask = Node->getOperand(2);
1713 unsigned NumElems = Mask.getNumOperands();
1714 SmallVector<SDValue,8> Ops;
1715 for (unsigned i = 0; i != NumElems; ++i) {
1716 SDValue Arg = Mask.getOperand(i);
1717 if (Arg.getOpcode() == ISD::UNDEF) {
1718 Ops.push_back(DAG.getNode(ISD::UNDEF, EltVT));
1720 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
1721 unsigned Idx = cast<ConstantSDNode>(Arg)->getZExtValue();
1723 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, Tmp1,
1724 DAG.getConstant(Idx, PtrVT)));
1726 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, Tmp2,
1727 DAG.getConstant(Idx - NumElems, PtrVT)));
1730 Result = DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size());
1733 case TargetLowering::Promote: {
1734 // Change base type to a different vector type.
1735 MVT OVT = Node->getValueType(0);
1736 MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
1738 // Cast the two input vectors.
1739 Tmp1 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp1);
1740 Tmp2 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp2);
1742 // Convert the shuffle mask to the right # elements.
1743 Tmp3 = SDValue(isShuffleLegal(OVT, Node->getOperand(2)), 0);
1744 assert(Tmp3.getNode() && "Shuffle not legal?");
1745 Result = DAG.getNode(ISD::VECTOR_SHUFFLE, NVT, Tmp1, Tmp2, Tmp3);
1746 Result = DAG.getNode(ISD::BIT_CONVERT, OVT, Result);
1752 case ISD::EXTRACT_VECTOR_ELT:
1753 Tmp1 = Node->getOperand(0);
1754 Tmp2 = LegalizeOp(Node->getOperand(1));
1755 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1756 Result = ExpandEXTRACT_VECTOR_ELT(Result);
1759 case ISD::EXTRACT_SUBVECTOR:
1760 Tmp1 = Node->getOperand(0);
1761 Tmp2 = LegalizeOp(Node->getOperand(1));
1762 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1763 Result = ExpandEXTRACT_SUBVECTOR(Result);
1766 case ISD::CONCAT_VECTORS: {
1767 // Use extract/insert/build vector for now. We might try to be
1768 // more clever later.
1769 MVT PtrVT = TLI.getPointerTy();
1770 SmallVector<SDValue, 8> Ops;
1771 unsigned NumOperands = Node->getNumOperands();
1772 for (unsigned i=0; i < NumOperands; ++i) {
1773 SDValue SubOp = Node->getOperand(i);
1774 MVT VVT = SubOp.getNode()->getValueType(0);
1775 MVT EltVT = VVT.getVectorElementType();
1776 unsigned NumSubElem = VVT.getVectorNumElements();
1777 for (unsigned j=0; j < NumSubElem; ++j) {
1778 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, SubOp,
1779 DAG.getConstant(j, PtrVT)));
1782 return LegalizeOp(DAG.getNode(ISD::BUILD_VECTOR, Node->getValueType(0),
1783 &Ops[0], Ops.size()));
1786 case ISD::CALLSEQ_START: {
1787 SDNode *CallEnd = FindCallEndFromCallStart(Node);
1789 // Recursively Legalize all of the inputs of the call end that do not lead
1790 // to this call start. This ensures that any libcalls that need be inserted
1791 // are inserted *before* the CALLSEQ_START.
1792 {SmallPtrSet<SDNode*, 32> NodesLeadingTo;
1793 for (unsigned i = 0, e = CallEnd->getNumOperands(); i != e; ++i)
1794 LegalizeAllNodesNotLeadingTo(CallEnd->getOperand(i).getNode(), Node,
1798 // Now that we legalized all of the inputs (which may have inserted
1799 // libcalls) create the new CALLSEQ_START node.
1800 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1802 // Merge in the last call, to ensure that this call start after the last
1804 if (LastCALLSEQ_END.getOpcode() != ISD::EntryToken) {
1805 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1806 Tmp1 = LegalizeOp(Tmp1);
1809 // Do not try to legalize the target-specific arguments (#1+).
1810 if (Tmp1 != Node->getOperand(0)) {
1811 SmallVector<SDValue, 8> Ops(Node->op_begin(), Node->op_end());
1813 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1816 // Remember that the CALLSEQ_START is legalized.
1817 AddLegalizedOperand(Op.getValue(0), Result);
1818 if (Node->getNumValues() == 2) // If this has a flag result, remember it.
1819 AddLegalizedOperand(Op.getValue(1), Result.getValue(1));
1821 // Now that the callseq_start and all of the non-call nodes above this call
1822 // sequence have been legalized, legalize the call itself. During this
1823 // process, no libcalls can/will be inserted, guaranteeing that no calls
1825 assert(!IsLegalizingCall && "Inconsistent sequentialization of calls!");
1826 // Note that we are selecting this call!
1827 LastCALLSEQ_END = SDValue(CallEnd, 0);
1828 IsLegalizingCall = true;
1830 // Legalize the call, starting from the CALLSEQ_END.
1831 LegalizeOp(LastCALLSEQ_END);
1832 assert(!IsLegalizingCall && "CALLSEQ_END should have cleared this!");
1835 case ISD::CALLSEQ_END:
1836 // If the CALLSEQ_START node hasn't been legalized first, legalize it. This
1837 // will cause this node to be legalized as well as handling libcalls right.
1838 if (LastCALLSEQ_END.getNode() != Node) {
1839 LegalizeOp(SDValue(FindCallStartFromCallEnd(Node), 0));
1840 DenseMap<SDValue, SDValue>::iterator I = LegalizedNodes.find(Op);
1841 assert(I != LegalizedNodes.end() &&
1842 "Legalizing the call start should have legalized this node!");
1846 // Otherwise, the call start has been legalized and everything is going
1847 // according to plan. Just legalize ourselves normally here.
1848 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1849 // Do not try to legalize the target-specific arguments (#1+), except for
1850 // an optional flag input.
1851 if (Node->getOperand(Node->getNumOperands()-1).getValueType() != MVT::Flag){
1852 if (Tmp1 != Node->getOperand(0)) {
1853 SmallVector<SDValue, 8> Ops(Node->op_begin(), Node->op_end());
1855 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1858 Tmp2 = LegalizeOp(Node->getOperand(Node->getNumOperands()-1));
1859 if (Tmp1 != Node->getOperand(0) ||
1860 Tmp2 != Node->getOperand(Node->getNumOperands()-1)) {
1861 SmallVector<SDValue, 8> Ops(Node->op_begin(), Node->op_end());
1864 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1867 assert(IsLegalizingCall && "Call sequence imbalance between start/end?");
1868 // This finishes up call legalization.
1869 IsLegalizingCall = false;
1871 // If the CALLSEQ_END node has a flag, remember that we legalized it.
1872 AddLegalizedOperand(SDValue(Node, 0), Result.getValue(0));
1873 if (Node->getNumValues() == 2)
1874 AddLegalizedOperand(SDValue(Node, 1), Result.getValue(1));
1875 return Result.getValue(Op.getResNo());
1876 case ISD::DYNAMIC_STACKALLOC: {
1877 MVT VT = Node->getValueType(0);
1878 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1879 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the size.
1880 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the alignment.
1881 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1883 Tmp1 = Result.getValue(0);
1884 Tmp2 = Result.getValue(1);
1885 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
1886 default: assert(0 && "This action is not supported yet!");
1887 case TargetLowering::Expand: {
1888 unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore();
1889 assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and"
1890 " not tell us which reg is the stack pointer!");
1891 SDValue Chain = Tmp1.getOperand(0);
1893 // Chain the dynamic stack allocation so that it doesn't modify the stack
1894 // pointer when other instructions are using the stack.
1895 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(0, true));
1897 SDValue Size = Tmp2.getOperand(1);
1898 SDValue SP = DAG.getCopyFromReg(Chain, SPReg, VT);
1899 Chain = SP.getValue(1);
1900 unsigned Align = cast<ConstantSDNode>(Tmp3)->getZExtValue();
1901 unsigned StackAlign =
1902 TLI.getTargetMachine().getFrameInfo()->getStackAlignment();
1903 if (Align > StackAlign)
1904 SP = DAG.getNode(ISD::AND, VT, SP,
1905 DAG.getConstant(-(uint64_t)Align, VT));
1906 Tmp1 = DAG.getNode(ISD::SUB, VT, SP, Size); // Value
1907 Chain = DAG.getCopyToReg(Chain, SPReg, Tmp1); // Output chain
1909 Tmp2 = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(0, true),
1910 DAG.getIntPtrConstant(0, true), SDValue());
1912 Tmp1 = LegalizeOp(Tmp1);
1913 Tmp2 = LegalizeOp(Tmp2);
1916 case TargetLowering::Custom:
1917 Tmp3 = TLI.LowerOperation(Tmp1, DAG);
1918 if (Tmp3.getNode()) {
1919 Tmp1 = LegalizeOp(Tmp3);
1920 Tmp2 = LegalizeOp(Tmp3.getValue(1));
1923 case TargetLowering::Legal:
1926 // Since this op produce two values, make sure to remember that we
1927 // legalized both of them.
1928 AddLegalizedOperand(SDValue(Node, 0), Tmp1);
1929 AddLegalizedOperand(SDValue(Node, 1), Tmp2);
1930 return Op.getResNo() ? Tmp2 : Tmp1;
1932 case ISD::INLINEASM: {
1933 SmallVector<SDValue, 8> Ops(Node->op_begin(), Node->op_end());
1934 bool Changed = false;
1935 // Legalize all of the operands of the inline asm, in case they are nodes
1936 // that need to be expanded or something. Note we skip the asm string and
1937 // all of the TargetConstant flags.
1938 SDValue Op = LegalizeOp(Ops[0]);
1939 Changed = Op != Ops[0];
1942 bool HasInFlag = Ops.back().getValueType() == MVT::Flag;
1943 for (unsigned i = 2, e = Ops.size()-HasInFlag; i < e; ) {
1944 unsigned NumVals = cast<ConstantSDNode>(Ops[i])->getZExtValue() >> 3;
1945 for (++i; NumVals; ++i, --NumVals) {
1946 SDValue Op = LegalizeOp(Ops[i]);
1955 Op = LegalizeOp(Ops.back());
1956 Changed |= Op != Ops.back();
1961 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1963 // INLINE asm returns a chain and flag, make sure to add both to the map.
1964 AddLegalizedOperand(SDValue(Node, 0), Result.getValue(0));
1965 AddLegalizedOperand(SDValue(Node, 1), Result.getValue(1));
1966 return Result.getValue(Op.getResNo());
1969 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1970 // Ensure that libcalls are emitted before a branch.
1971 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1972 Tmp1 = LegalizeOp(Tmp1);
1973 LastCALLSEQ_END = DAG.getEntryNode();
1975 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
1978 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1979 // Ensure that libcalls are emitted before a branch.
1980 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1981 Tmp1 = LegalizeOp(Tmp1);
1982 LastCALLSEQ_END = DAG.getEntryNode();
1984 switch (getTypeAction(Node->getOperand(1).getValueType())) {
1985 default: assert(0 && "Indirect target must be legal type (pointer)!");
1987 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the condition.
1990 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1993 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1994 // Ensure that libcalls are emitted before a branch.
1995 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1996 Tmp1 = LegalizeOp(Tmp1);
1997 LastCALLSEQ_END = DAG.getEntryNode();
1999 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the jumptable node.
2000 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
2002 switch (TLI.getOperationAction(ISD::BR_JT, MVT::Other)) {
2003 default: assert(0 && "This action is not supported yet!");
2004 case TargetLowering::Legal: break;
2005 case TargetLowering::Custom:
2006 Tmp1 = TLI.LowerOperation(Result, DAG);
2007 if (Tmp1.getNode()) Result = Tmp1;
2009 case TargetLowering::Expand: {
2010 SDValue Chain = Result.getOperand(0);
2011 SDValue Table = Result.getOperand(1);
2012 SDValue Index = Result.getOperand(2);
2014 MVT PTy = TLI.getPointerTy();
2015 MachineFunction &MF = DAG.getMachineFunction();
2016 unsigned EntrySize = MF.getJumpTableInfo()->getEntrySize();
2017 Index= DAG.getNode(ISD::MUL, PTy, Index, DAG.getConstant(EntrySize, PTy));
2018 SDValue Addr = DAG.getNode(ISD::ADD, PTy, Index, Table);
2020 MVT MemVT = MVT::getIntegerVT(EntrySize * 8);
2021 SDValue LD = DAG.getExtLoad(ISD::SEXTLOAD, PTy, Chain, Addr,
2022 PseudoSourceValue::getJumpTable(), 0, MemVT);
2024 if (TLI.getTargetMachine().getRelocationModel() == Reloc::PIC_) {
2025 // For PIC, the sequence is:
2026 // BRIND(load(Jumptable + index) + RelocBase)
2027 // RelocBase can be JumpTable, GOT or some sort of global base.
2028 Addr = DAG.getNode(ISD::ADD, PTy, Addr,
2029 TLI.getPICJumpTableRelocBase(Table, DAG));
2031 Result = DAG.getNode(ISD::BRIND, MVT::Other, LD.getValue(1), Addr);
2036 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2037 // Ensure that libcalls are emitted before a return.
2038 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
2039 Tmp1 = LegalizeOp(Tmp1);
2040 LastCALLSEQ_END = DAG.getEntryNode();
2042 switch (getTypeAction(Node->getOperand(1).getValueType())) {
2043 case Expand: assert(0 && "It's impossible to expand bools");
2045 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the condition.
2048 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the condition.
2050 // The top bits of the promoted condition are not necessarily zero, ensure
2051 // that the value is properly zero extended.
2052 unsigned BitWidth = Tmp2.getValueSizeInBits();
2053 if (!DAG.MaskedValueIsZero(Tmp2,
2054 APInt::getHighBitsSet(BitWidth, BitWidth-1)))
2055 Tmp2 = DAG.getZeroExtendInReg(Tmp2, MVT::i1);
2060 // Basic block destination (Op#2) is always legal.
2061 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
2063 switch (TLI.getOperationAction(ISD::BRCOND, MVT::Other)) {
2064 default: assert(0 && "This action is not supported yet!");
2065 case TargetLowering::Legal: break;
2066 case TargetLowering::Custom:
2067 Tmp1 = TLI.LowerOperation(Result, DAG);
2068 if (Tmp1.getNode()) Result = Tmp1;
2070 case TargetLowering::Expand:
2071 // Expand brcond's setcc into its constituent parts and create a BR_CC
2073 if (Tmp2.getOpcode() == ISD::SETCC) {
2074 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1, Tmp2.getOperand(2),
2075 Tmp2.getOperand(0), Tmp2.getOperand(1),
2076 Node->getOperand(2));
2078 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1,
2079 DAG.getCondCode(ISD::SETNE), Tmp2,
2080 DAG.getConstant(0, Tmp2.getValueType()),
2081 Node->getOperand(2));
2087 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2088 // Ensure that libcalls are emitted before a branch.
2089 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
2090 Tmp1 = LegalizeOp(Tmp1);
2091 Tmp2 = Node->getOperand(2); // LHS
2092 Tmp3 = Node->getOperand(3); // RHS
2093 Tmp4 = Node->getOperand(1); // CC
2095 LegalizeSetCC(TLI.getSetCCResultType(Tmp2), Tmp2, Tmp3, Tmp4);
2096 LastCALLSEQ_END = DAG.getEntryNode();
2098 // If we didn't get both a LHS and RHS back from LegalizeSetCC,
2099 // the LHS is a legal SETCC itself. In this case, we need to compare
2100 // the result against zero to select between true and false values.
2101 if (Tmp3.getNode() == 0) {
2102 Tmp3 = DAG.getConstant(0, Tmp2.getValueType());
2103 Tmp4 = DAG.getCondCode(ISD::SETNE);
2106 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp4, Tmp2, Tmp3,
2107 Node->getOperand(4));
2109 switch (TLI.getOperationAction(ISD::BR_CC, Tmp3.getValueType())) {
2110 default: assert(0 && "Unexpected action for BR_CC!");
2111 case TargetLowering::Legal: break;
2112 case TargetLowering::Custom:
2113 Tmp4 = TLI.LowerOperation(Result, DAG);
2114 if (Tmp4.getNode()) Result = Tmp4;
2119 LoadSDNode *LD = cast<LoadSDNode>(Node);
2120 Tmp1 = LegalizeOp(LD->getChain()); // Legalize the chain.
2121 Tmp2 = LegalizeOp(LD->getBasePtr()); // Legalize the base pointer.
2123 ISD::LoadExtType ExtType = LD->getExtensionType();
2124 if (ExtType == ISD::NON_EXTLOAD) {
2125 MVT VT = Node->getValueType(0);
2126 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, LD->getOffset());
2127 Tmp3 = Result.getValue(0);
2128 Tmp4 = Result.getValue(1);
2130 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
2131 default: assert(0 && "This action is not supported yet!");
2132 case TargetLowering::Legal:
2133 // If this is an unaligned load and the target doesn't support it,
2135 if (!TLI.allowsUnalignedMemoryAccesses()) {
2136 unsigned ABIAlignment = TLI.getTargetData()->
2137 getABITypeAlignment(LD->getMemoryVT().getTypeForMVT());
2138 if (LD->getAlignment() < ABIAlignment){
2139 Result = ExpandUnalignedLoad(cast<LoadSDNode>(Result.getNode()), DAG,
2141 Tmp3 = Result.getOperand(0);
2142 Tmp4 = Result.getOperand(1);
2143 Tmp3 = LegalizeOp(Tmp3);
2144 Tmp4 = LegalizeOp(Tmp4);
2148 case TargetLowering::Custom:
2149 Tmp1 = TLI.LowerOperation(Tmp3, DAG);
2150 if (Tmp1.getNode()) {
2151 Tmp3 = LegalizeOp(Tmp1);
2152 Tmp4 = LegalizeOp(Tmp1.getValue(1));
2155 case TargetLowering::Promote: {
2156 // Only promote a load of vector type to another.
2157 assert(VT.isVector() && "Cannot promote this load!");
2158 // Change base type to a different vector type.
2159 MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), VT);
2161 Tmp1 = DAG.getLoad(NVT, Tmp1, Tmp2, LD->getSrcValue(),
2162 LD->getSrcValueOffset(),
2163 LD->isVolatile(), LD->getAlignment());
2164 Tmp3 = LegalizeOp(DAG.getNode(ISD::BIT_CONVERT, VT, Tmp1));
2165 Tmp4 = LegalizeOp(Tmp1.getValue(1));
2169 // Since loads produce two values, make sure to remember that we
2170 // legalized both of them.
2171 AddLegalizedOperand(SDValue(Node, 0), Tmp3);
2172 AddLegalizedOperand(SDValue(Node, 1), Tmp4);
2173 return Op.getResNo() ? Tmp4 : Tmp3;
2175 MVT SrcVT = LD->getMemoryVT();
2176 unsigned SrcWidth = SrcVT.getSizeInBits();
2177 int SVOffset = LD->getSrcValueOffset();
2178 unsigned Alignment = LD->getAlignment();
2179 bool isVolatile = LD->isVolatile();
2181 if (SrcWidth != SrcVT.getStoreSizeInBits() &&
2182 // Some targets pretend to have an i1 loading operation, and actually
2183 // load an i8. This trick is correct for ZEXTLOAD because the top 7
2184 // bits are guaranteed to be zero; it helps the optimizers understand
2185 // that these bits are zero. It is also useful for EXTLOAD, since it
2186 // tells the optimizers that those bits are undefined. It would be
2187 // nice to have an effective generic way of getting these benefits...
2188 // Until such a way is found, don't insist on promoting i1 here.
2189 (SrcVT != MVT::i1 ||
2190 TLI.getLoadExtAction(ExtType, MVT::i1) == TargetLowering::Promote)) {
2191 // Promote to a byte-sized load if not loading an integral number of
2192 // bytes. For example, promote EXTLOAD:i20 -> EXTLOAD:i24.
2193 unsigned NewWidth = SrcVT.getStoreSizeInBits();
2194 MVT NVT = MVT::getIntegerVT(NewWidth);
2197 // The extra bits are guaranteed to be zero, since we stored them that
2198 // way. A zext load from NVT thus automatically gives zext from SrcVT.
2200 ISD::LoadExtType NewExtType =
2201 ExtType == ISD::ZEXTLOAD ? ISD::ZEXTLOAD : ISD::EXTLOAD;
2203 Result = DAG.getExtLoad(NewExtType, Node->getValueType(0),
2204 Tmp1, Tmp2, LD->getSrcValue(), SVOffset,
2205 NVT, isVolatile, Alignment);
2207 Ch = Result.getValue(1); // The chain.
2209 if (ExtType == ISD::SEXTLOAD)
2210 // Having the top bits zero doesn't help when sign extending.
2211 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(),
2212 Result, DAG.getValueType(SrcVT));
2213 else if (ExtType == ISD::ZEXTLOAD || NVT == Result.getValueType())
2214 // All the top bits are guaranteed to be zero - inform the optimizers.
2215 Result = DAG.getNode(ISD::AssertZext, Result.getValueType(), Result,
2216 DAG.getValueType(SrcVT));
2218 Tmp1 = LegalizeOp(Result);
2219 Tmp2 = LegalizeOp(Ch);
2220 } else if (SrcWidth & (SrcWidth - 1)) {
2221 // If not loading a power-of-2 number of bits, expand as two loads.
2222 assert(SrcVT.isExtended() && !SrcVT.isVector() &&
2223 "Unsupported extload!");
2224 unsigned RoundWidth = 1 << Log2_32(SrcWidth);
2225 assert(RoundWidth < SrcWidth);
2226 unsigned ExtraWidth = SrcWidth - RoundWidth;
2227 assert(ExtraWidth < RoundWidth);
2228 assert(!(RoundWidth % 8) && !(ExtraWidth % 8) &&
2229 "Load size not an integral number of bytes!");
2230 MVT RoundVT = MVT::getIntegerVT(RoundWidth);
2231 MVT ExtraVT = MVT::getIntegerVT(ExtraWidth);
2233 unsigned IncrementSize;
2235 if (TLI.isLittleEndian()) {
2236 // EXTLOAD:i24 -> ZEXTLOAD:i16 | (shl EXTLOAD@+2:i8, 16)
2237 // Load the bottom RoundWidth bits.
2238 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, Node->getValueType(0), Tmp1, Tmp2,
2239 LD->getSrcValue(), SVOffset, RoundVT, isVolatile,
2242 // Load the remaining ExtraWidth bits.
2243 IncrementSize = RoundWidth / 8;
2244 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2,
2245 DAG.getIntPtrConstant(IncrementSize));
2246 Hi = DAG.getExtLoad(ExtType, Node->getValueType(0), Tmp1, Tmp2,
2247 LD->getSrcValue(), SVOffset + IncrementSize,
2248 ExtraVT, isVolatile,
2249 MinAlign(Alignment, IncrementSize));
2251 // Build a factor node to remember that this load is independent of the
2253 Ch = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
2256 // Move the top bits to the right place.
2257 Hi = DAG.getNode(ISD::SHL, Hi.getValueType(), Hi,
2258 DAG.getConstant(RoundWidth, TLI.getShiftAmountTy()));
2260 // Join the hi and lo parts.
2261 Result = DAG.getNode(ISD::OR, Node->getValueType(0), Lo, Hi);
2263 // Big endian - avoid unaligned loads.
2264 // EXTLOAD:i24 -> (shl EXTLOAD:i16, 8) | ZEXTLOAD@+2:i8
2265 // Load the top RoundWidth bits.
2266 Hi = DAG.getExtLoad(ExtType, Node->getValueType(0), Tmp1, Tmp2,
2267 LD->getSrcValue(), SVOffset, RoundVT, isVolatile,
2270 // Load the remaining ExtraWidth bits.
2271 IncrementSize = RoundWidth / 8;
2272 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2,
2273 DAG.getIntPtrConstant(IncrementSize));
2274 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, Node->getValueType(0), Tmp1, Tmp2,
2275 LD->getSrcValue(), SVOffset + IncrementSize,
2276 ExtraVT, isVolatile,
2277 MinAlign(Alignment, IncrementSize));
2279 // Build a factor node to remember that this load is independent of the
2281 Ch = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
2284 // Move the top bits to the right place.
2285 Hi = DAG.getNode(ISD::SHL, Hi.getValueType(), Hi,
2286 DAG.getConstant(ExtraWidth, TLI.getShiftAmountTy()));
2288 // Join the hi and lo parts.
2289 Result = DAG.getNode(ISD::OR, Node->getValueType(0), Lo, Hi);
2292 Tmp1 = LegalizeOp(Result);
2293 Tmp2 = LegalizeOp(Ch);
2295 switch (TLI.getLoadExtAction(ExtType, SrcVT)) {
2296 default: assert(0 && "This action is not supported yet!");
2297 case TargetLowering::Custom:
2300 case TargetLowering::Legal:
2301 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, LD->getOffset());
2302 Tmp1 = Result.getValue(0);
2303 Tmp2 = Result.getValue(1);
2306 Tmp3 = TLI.LowerOperation(Result, DAG);
2307 if (Tmp3.getNode()) {
2308 Tmp1 = LegalizeOp(Tmp3);
2309 Tmp2 = LegalizeOp(Tmp3.getValue(1));
2312 // If this is an unaligned load and the target doesn't support it,
2314 if (!TLI.allowsUnalignedMemoryAccesses()) {
2315 unsigned ABIAlignment = TLI.getTargetData()->
2316 getABITypeAlignment(LD->getMemoryVT().getTypeForMVT());
2317 if (LD->getAlignment() < ABIAlignment){
2318 Result = ExpandUnalignedLoad(cast<LoadSDNode>(Result.getNode()), DAG,
2320 Tmp1 = Result.getOperand(0);
2321 Tmp2 = Result.getOperand(1);
2322 Tmp1 = LegalizeOp(Tmp1);
2323 Tmp2 = LegalizeOp(Tmp2);
2328 case TargetLowering::Expand:
2329 // f64 = EXTLOAD f32 should expand to LOAD, FP_EXTEND
2330 if (SrcVT == MVT::f32 && Node->getValueType(0) == MVT::f64) {
2331 SDValue Load = DAG.getLoad(SrcVT, Tmp1, Tmp2, LD->getSrcValue(),
2332 LD->getSrcValueOffset(),
2333 LD->isVolatile(), LD->getAlignment());
2334 Result = DAG.getNode(ISD::FP_EXTEND, Node->getValueType(0), Load);
2335 Tmp1 = LegalizeOp(Result); // Relegalize new nodes.
2336 Tmp2 = LegalizeOp(Load.getValue(1));
2339 assert(ExtType != ISD::EXTLOAD &&"EXTLOAD should always be supported!");
2340 // Turn the unsupported load into an EXTLOAD followed by an explicit
2341 // zero/sign extend inreg.
2342 Result = DAG.getExtLoad(ISD::EXTLOAD, Node->getValueType(0),
2343 Tmp1, Tmp2, LD->getSrcValue(),
2344 LD->getSrcValueOffset(), SrcVT,
2345 LD->isVolatile(), LD->getAlignment());
2347 if (ExtType == ISD::SEXTLOAD)
2348 ValRes = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(),
2349 Result, DAG.getValueType(SrcVT));
2351 ValRes = DAG.getZeroExtendInReg(Result, SrcVT);
2352 Tmp1 = LegalizeOp(ValRes); // Relegalize new nodes.
2353 Tmp2 = LegalizeOp(Result.getValue(1)); // Relegalize new nodes.
2358 // Since loads produce two values, make sure to remember that we legalized
2360 AddLegalizedOperand(SDValue(Node, 0), Tmp1);
2361 AddLegalizedOperand(SDValue(Node, 1), Tmp2);
2362 return Op.getResNo() ? Tmp2 : Tmp1;
2365 case ISD::EXTRACT_ELEMENT: {
2366 MVT OpTy = Node->getOperand(0).getValueType();
2367 switch (getTypeAction(OpTy)) {
2368 default: assert(0 && "EXTRACT_ELEMENT action for type unimplemented!");
2370 if (cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue()) {
2372 Result = DAG.getNode(ISD::SRL, OpTy, Node->getOperand(0),
2373 DAG.getConstant(OpTy.getSizeInBits()/2,
2374 TLI.getShiftAmountTy()));
2375 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), Result);
2378 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0),
2379 Node->getOperand(0));
2383 // Get both the low and high parts.
2384 ExpandOp(Node->getOperand(0), Tmp1, Tmp2);
2385 if (cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue())
2386 Result = Tmp2; // 1 -> Hi
2388 Result = Tmp1; // 0 -> Lo
2394 case ISD::CopyToReg:
2395 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2397 assert(isTypeLegal(Node->getOperand(2).getValueType()) &&
2398 "Register type must be legal!");
2399 // Legalize the incoming value (must be a legal type).
2400 Tmp2 = LegalizeOp(Node->getOperand(2));
2401 if (Node->getNumValues() == 1) {
2402 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1), Tmp2);
2404 assert(Node->getNumValues() == 2 && "Unknown CopyToReg");
2405 if (Node->getNumOperands() == 4) {
2406 Tmp3 = LegalizeOp(Node->getOperand(3));
2407 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1), Tmp2,
2410 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1),Tmp2);
2413 // Since this produces two values, make sure to remember that we legalized
2415 AddLegalizedOperand(SDValue(Node, 0), Result.getValue(0));
2416 AddLegalizedOperand(SDValue(Node, 1), Result.getValue(1));
2422 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2424 // Ensure that libcalls are emitted before a return.
2425 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
2426 Tmp1 = LegalizeOp(Tmp1);
2427 LastCALLSEQ_END = DAG.getEntryNode();
2429 switch (Node->getNumOperands()) {
2431 Tmp2 = Node->getOperand(1);
2432 Tmp3 = Node->getOperand(2); // Signness
2433 switch (getTypeAction(Tmp2.getValueType())) {
2435 Result = DAG.UpdateNodeOperands(Result, Tmp1, LegalizeOp(Tmp2), Tmp3);
2438 if (!Tmp2.getValueType().isVector()) {
2440 ExpandOp(Tmp2, Lo, Hi);
2442 // Big endian systems want the hi reg first.
2443 if (TLI.isBigEndian())
2447 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Tmp3, Hi,Tmp3);
2449 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Tmp3);
2450 Result = LegalizeOp(Result);
2452 SDNode *InVal = Tmp2.getNode();
2453 int InIx = Tmp2.getResNo();
2454 unsigned NumElems = InVal->getValueType(InIx).getVectorNumElements();
2455 MVT EVT = InVal->getValueType(InIx).getVectorElementType();
2457 // Figure out if there is a simple type corresponding to this Vector
2458 // type. If so, convert to the vector type.
2459 MVT TVT = MVT::getVectorVT(EVT, NumElems);
2460 if (TLI.isTypeLegal(TVT)) {
2461 // Turn this into a return of the vector type.
2462 Tmp2 = LegalizeOp(Tmp2);
2463 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2464 } else if (NumElems == 1) {
2465 // Turn this into a return of the scalar type.
2466 Tmp2 = ScalarizeVectorOp(Tmp2);
2467 Tmp2 = LegalizeOp(Tmp2);
2468 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2470 // FIXME: Returns of gcc generic vectors smaller than a legal type
2471 // should be returned in integer registers!
2473 // The scalarized value type may not be legal, e.g. it might require
2474 // promotion or expansion. Relegalize the return.
2475 Result = LegalizeOp(Result);
2477 // FIXME: Returns of gcc generic vectors larger than a legal vector
2478 // type should be returned by reference!
2480 SplitVectorOp(Tmp2, Lo, Hi);
2481 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Tmp3, Hi,Tmp3);
2482 Result = LegalizeOp(Result);
2487 Tmp2 = PromoteOp(Node->getOperand(1));
2488 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2489 Result = LegalizeOp(Result);
2494 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2496 default: { // ret <values>
2497 SmallVector<SDValue, 8> NewValues;
2498 NewValues.push_back(Tmp1);
2499 for (unsigned i = 1, e = Node->getNumOperands(); i < e; i += 2)
2500 switch (getTypeAction(Node->getOperand(i).getValueType())) {
2502 NewValues.push_back(LegalizeOp(Node->getOperand(i)));
2503 NewValues.push_back(Node->getOperand(i+1));
2507 assert(!Node->getOperand(i).getValueType().isExtended() &&
2508 "FIXME: TODO: implement returning non-legal vector types!");
2509 ExpandOp(Node->getOperand(i), Lo, Hi);
2510 NewValues.push_back(Lo);
2511 NewValues.push_back(Node->getOperand(i+1));
2513 NewValues.push_back(Hi);
2514 NewValues.push_back(Node->getOperand(i+1));
2519 assert(0 && "Can't promote multiple return value yet!");
2522 if (NewValues.size() == Node->getNumOperands())
2523 Result = DAG.UpdateNodeOperands(Result, &NewValues[0],NewValues.size());
2525 Result = DAG.getNode(ISD::RET, MVT::Other,
2526 &NewValues[0], NewValues.size());
2531 if (Result.getOpcode() == ISD::RET) {
2532 switch (TLI.getOperationAction(Result.getOpcode(), MVT::Other)) {
2533 default: assert(0 && "This action is not supported yet!");
2534 case TargetLowering::Legal: break;
2535 case TargetLowering::Custom:
2536 Tmp1 = TLI.LowerOperation(Result, DAG);
2537 if (Tmp1.getNode()) Result = Tmp1;
2543 StoreSDNode *ST = cast<StoreSDNode>(Node);
2544 Tmp1 = LegalizeOp(ST->getChain()); // Legalize the chain.
2545 Tmp2 = LegalizeOp(ST->getBasePtr()); // Legalize the pointer.
2546 int SVOffset = ST->getSrcValueOffset();
2547 unsigned Alignment = ST->getAlignment();
2548 bool isVolatile = ST->isVolatile();
2550 if (!ST->isTruncatingStore()) {
2551 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr'
2552 // FIXME: We shouldn't do this for TargetConstantFP's.
2553 // FIXME: move this to the DAG Combiner! Note that we can't regress due
2554 // to phase ordering between legalized code and the dag combiner. This
2555 // probably means that we need to integrate dag combiner and legalizer
2557 // We generally can't do this one for long doubles.
2558 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(ST->getValue())) {
2559 if (CFP->getValueType(0) == MVT::f32 &&
2560 getTypeAction(MVT::i32) == Legal) {
2561 Tmp3 = DAG.getConstant(CFP->getValueAPF().
2562 bitcastToAPInt().zextOrTrunc(32),
2564 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2565 SVOffset, isVolatile, Alignment);
2567 } else if (CFP->getValueType(0) == MVT::f64) {
2568 // If this target supports 64-bit registers, do a single 64-bit store.
2569 if (getTypeAction(MVT::i64) == Legal) {
2570 Tmp3 = DAG.getConstant(CFP->getValueAPF().bitcastToAPInt().
2571 zextOrTrunc(64), MVT::i64);
2572 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2573 SVOffset, isVolatile, Alignment);
2575 } else if (getTypeAction(MVT::i32) == Legal && !ST->isVolatile()) {
2576 // Otherwise, if the target supports 32-bit registers, use 2 32-bit
2577 // stores. If the target supports neither 32- nor 64-bits, this
2578 // xform is certainly not worth it.
2579 const APInt &IntVal =CFP->getValueAPF().bitcastToAPInt();
2580 SDValue Lo = DAG.getConstant(APInt(IntVal).trunc(32), MVT::i32);
2581 SDValue Hi = DAG.getConstant(IntVal.lshr(32).trunc(32), MVT::i32);
2582 if (TLI.isBigEndian()) std::swap(Lo, Hi);
2584 Lo = DAG.getStore(Tmp1, Lo, Tmp2, ST->getSrcValue(),
2585 SVOffset, isVolatile, Alignment);
2586 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2,
2587 DAG.getIntPtrConstant(4));
2588 Hi = DAG.getStore(Tmp1, Hi, Tmp2, ST->getSrcValue(), SVOffset+4,
2589 isVolatile, MinAlign(Alignment, 4U));
2591 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi);
2597 switch (getTypeAction(ST->getMemoryVT())) {
2599 Tmp3 = LegalizeOp(ST->getValue());
2600 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2,
2603 MVT VT = Tmp3.getValueType();
2604 switch (TLI.getOperationAction(ISD::STORE, VT)) {
2605 default: assert(0 && "This action is not supported yet!");
2606 case TargetLowering::Legal:
2607 // If this is an unaligned store and the target doesn't support it,
2609 if (!TLI.allowsUnalignedMemoryAccesses()) {
2610 unsigned ABIAlignment = TLI.getTargetData()->
2611 getABITypeAlignment(ST->getMemoryVT().getTypeForMVT());
2612 if (ST->getAlignment() < ABIAlignment)
2613 Result = ExpandUnalignedStore(cast<StoreSDNode>(Result.getNode()), DAG,
2617 case TargetLowering::Custom:
2618 Tmp1 = TLI.LowerOperation(Result, DAG);
2619 if (Tmp1.getNode()) Result = Tmp1;
2621 case TargetLowering::Promote:
2622 assert(VT.isVector() && "Unknown legal promote case!");
2623 Tmp3 = DAG.getNode(ISD::BIT_CONVERT,
2624 TLI.getTypeToPromoteTo(ISD::STORE, VT), Tmp3);
2625 Result = DAG.getStore(Tmp1, Tmp3, Tmp2,
2626 ST->getSrcValue(), SVOffset, isVolatile,
2633 if (!ST->getMemoryVT().isVector()) {
2634 // Truncate the value and store the result.
2635 Tmp3 = PromoteOp(ST->getValue());
2636 Result = DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2637 SVOffset, ST->getMemoryVT(),
2638 isVolatile, Alignment);
2641 // Fall thru to expand for vector
2643 unsigned IncrementSize = 0;
2646 // If this is a vector type, then we have to calculate the increment as
2647 // the product of the element size in bytes, and the number of elements
2648 // in the high half of the vector.
2649 if (ST->getValue().getValueType().isVector()) {
2650 SDNode *InVal = ST->getValue().getNode();
2651 int InIx = ST->getValue().getResNo();
2652 MVT InVT = InVal->getValueType(InIx);
2653 unsigned NumElems = InVT.getVectorNumElements();
2654 MVT EVT = InVT.getVectorElementType();
2656 // Figure out if there is a simple type corresponding to this Vector
2657 // type. If so, convert to the vector type.
2658 MVT TVT = MVT::getVectorVT(EVT, NumElems);
2659 if (TLI.isTypeLegal(TVT)) {
2660 // Turn this into a normal store of the vector type.
2661 Tmp3 = LegalizeOp(ST->getValue());
2662 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2663 SVOffset, isVolatile, Alignment);
2664 Result = LegalizeOp(Result);
2666 } else if (NumElems == 1) {
2667 // Turn this into a normal store of the scalar type.
2668 Tmp3 = ScalarizeVectorOp(ST->getValue());
2669 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2670 SVOffset, isVolatile, Alignment);
2671 // The scalarized value type may not be legal, e.g. it might require
2672 // promotion or expansion. Relegalize the scalar store.
2673 Result = LegalizeOp(Result);
2676 // Check if we have widen this node with another value
2677 std::map<SDValue, SDValue>::iterator I =
2678 WidenNodes.find(ST->getValue());
2679 if (I != WidenNodes.end()) {
2680 Result = StoreWidenVectorOp(ST, Tmp1, Tmp2);
2684 SplitVectorOp(ST->getValue(), Lo, Hi);
2685 IncrementSize = Lo.getNode()->getValueType(0).getVectorNumElements() *
2686 EVT.getSizeInBits()/8;
2690 ExpandOp(ST->getValue(), Lo, Hi);
2691 IncrementSize = Hi.getNode() ? Hi.getValueType().getSizeInBits()/8 : 0;
2693 if (Hi.getNode() && TLI.isBigEndian())
2697 Lo = DAG.getStore(Tmp1, Lo, Tmp2, ST->getSrcValue(),
2698 SVOffset, isVolatile, Alignment);
2700 if (Hi.getNode() == NULL) {
2701 // Must be int <-> float one-to-one expansion.
2706 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2,
2707 DAG.getIntPtrConstant(IncrementSize));
2708 assert(isTypeLegal(Tmp2.getValueType()) &&
2709 "Pointers must be legal!");
2710 SVOffset += IncrementSize;
2711 Alignment = MinAlign(Alignment, IncrementSize);
2712 Hi = DAG.getStore(Tmp1, Hi, Tmp2, ST->getSrcValue(),
2713 SVOffset, isVolatile, Alignment);
2714 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi);
2719 switch (getTypeAction(ST->getValue().getValueType())) {
2721 Tmp3 = LegalizeOp(ST->getValue());
2724 if (!ST->getValue().getValueType().isVector()) {
2725 // We can promote the value, the truncstore will still take care of it.
2726 Tmp3 = PromoteOp(ST->getValue());
2729 // Vector case falls through to expand
2731 // Just store the low part. This may become a non-trunc store, so make
2732 // sure to use getTruncStore, not UpdateNodeOperands below.
2733 ExpandOp(ST->getValue(), Tmp3, Tmp4);
2734 return DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2735 SVOffset, MVT::i8, isVolatile, Alignment);
2738 MVT StVT = ST->getMemoryVT();
2739 unsigned StWidth = StVT.getSizeInBits();
2741 if (StWidth != StVT.getStoreSizeInBits()) {
2742 // Promote to a byte-sized store with upper bits zero if not
2743 // storing an integral number of bytes. For example, promote
2744 // TRUNCSTORE:i1 X -> TRUNCSTORE:i8 (and X, 1)
2745 MVT NVT = MVT::getIntegerVT(StVT.getStoreSizeInBits());
2746 Tmp3 = DAG.getZeroExtendInReg(Tmp3, StVT);
2747 Result = DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2748 SVOffset, NVT, isVolatile, Alignment);
2749 } else if (StWidth & (StWidth - 1)) {
2750 // If not storing a power-of-2 number of bits, expand as two stores.
2751 assert(StVT.isExtended() && !StVT.isVector() &&
2752 "Unsupported truncstore!");
2753 unsigned RoundWidth = 1 << Log2_32(StWidth);
2754 assert(RoundWidth < StWidth);
2755 unsigned ExtraWidth = StWidth - RoundWidth;
2756 assert(ExtraWidth < RoundWidth);
2757 assert(!(RoundWidth % 8) && !(ExtraWidth % 8) &&
2758 "Store size not an integral number of bytes!");
2759 MVT RoundVT = MVT::getIntegerVT(RoundWidth);
2760 MVT ExtraVT = MVT::getIntegerVT(ExtraWidth);
2762 unsigned IncrementSize;
2764 if (TLI.isLittleEndian()) {
2765 // TRUNCSTORE:i24 X -> TRUNCSTORE:i16 X, TRUNCSTORE@+2:i8 (srl X, 16)
2766 // Store the bottom RoundWidth bits.
2767 Lo = DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2769 isVolatile, Alignment);
2771 // Store the remaining ExtraWidth bits.
2772 IncrementSize = RoundWidth / 8;
2773 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2,
2774 DAG.getIntPtrConstant(IncrementSize));
2775 Hi = DAG.getNode(ISD::SRL, Tmp3.getValueType(), Tmp3,
2776 DAG.getConstant(RoundWidth, TLI.getShiftAmountTy()));
2777 Hi = DAG.getTruncStore(Tmp1, Hi, Tmp2, ST->getSrcValue(),
2778 SVOffset + IncrementSize, ExtraVT, isVolatile,
2779 MinAlign(Alignment, IncrementSize));
2781 // Big endian - avoid unaligned stores.
2782 // TRUNCSTORE:i24 X -> TRUNCSTORE:i16 (srl X, 8), TRUNCSTORE@+2:i8 X
2783 // Store the top RoundWidth bits.
2784 Hi = DAG.getNode(ISD::SRL, Tmp3.getValueType(), Tmp3,
2785 DAG.getConstant(ExtraWidth, TLI.getShiftAmountTy()));
2786 Hi = DAG.getTruncStore(Tmp1, Hi, Tmp2, ST->getSrcValue(), SVOffset,
2787 RoundVT, isVolatile, Alignment);
2789 // Store the remaining ExtraWidth bits.
2790 IncrementSize = RoundWidth / 8;
2791 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2,
2792 DAG.getIntPtrConstant(IncrementSize));
2793 Lo = DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2794 SVOffset + IncrementSize, ExtraVT, isVolatile,
2795 MinAlign(Alignment, IncrementSize));
2798 // The order of the stores doesn't matter.
2799 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi);
2801 if (Tmp1 != ST->getChain() || Tmp3 != ST->getValue() ||
2802 Tmp2 != ST->getBasePtr())
2803 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2,
2806 switch (TLI.getTruncStoreAction(ST->getValue().getValueType(), StVT)) {
2807 default: assert(0 && "This action is not supported yet!");
2808 case TargetLowering::Legal:
2809 // If this is an unaligned store and the target doesn't support it,
2811 if (!TLI.allowsUnalignedMemoryAccesses()) {
2812 unsigned ABIAlignment = TLI.getTargetData()->
2813 getABITypeAlignment(ST->getMemoryVT().getTypeForMVT());
2814 if (ST->getAlignment() < ABIAlignment)
2815 Result = ExpandUnalignedStore(cast<StoreSDNode>(Result.getNode()), DAG,
2819 case TargetLowering::Custom:
2820 Result = TLI.LowerOperation(Result, DAG);
2823 // TRUNCSTORE:i16 i32 -> STORE i16
2824 assert(isTypeLegal(StVT) && "Do not know how to expand this store!");
2825 Tmp3 = DAG.getNode(ISD::TRUNCATE, StVT, Tmp3);
2826 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(), SVOffset,
2827 isVolatile, Alignment);
2835 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2836 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
2838 case ISD::STACKSAVE:
2839 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2840 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2841 Tmp1 = Result.getValue(0);
2842 Tmp2 = Result.getValue(1);
2844 switch (TLI.getOperationAction(ISD::STACKSAVE, MVT::Other)) {
2845 default: assert(0 && "This action is not supported yet!");
2846 case TargetLowering::Legal: break;
2847 case TargetLowering::Custom:
2848 Tmp3 = TLI.LowerOperation(Result, DAG);
2849 if (Tmp3.getNode()) {
2850 Tmp1 = LegalizeOp(Tmp3);
2851 Tmp2 = LegalizeOp(Tmp3.getValue(1));
2854 case TargetLowering::Expand:
2855 // Expand to CopyFromReg if the target set
2856 // StackPointerRegisterToSaveRestore.
2857 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) {
2858 Tmp1 = DAG.getCopyFromReg(Result.getOperand(0), SP,
2859 Node->getValueType(0));
2860 Tmp2 = Tmp1.getValue(1);
2862 Tmp1 = DAG.getNode(ISD::UNDEF, Node->getValueType(0));
2863 Tmp2 = Node->getOperand(0);
2868 // Since stacksave produce two values, make sure to remember that we
2869 // legalized both of them.
2870 AddLegalizedOperand(SDValue(Node, 0), Tmp1);
2871 AddLegalizedOperand(SDValue(Node, 1), Tmp2);
2872 return Op.getResNo() ? Tmp2 : Tmp1;
2874 case ISD::STACKRESTORE:
2875 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2876 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
2877 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
2879 switch (TLI.getOperationAction(ISD::STACKRESTORE, MVT::Other)) {
2880 default: assert(0 && "This action is not supported yet!");
2881 case TargetLowering::Legal: break;
2882 case TargetLowering::Custom:
2883 Tmp1 = TLI.LowerOperation(Result, DAG);
2884 if (Tmp1.getNode()) Result = Tmp1;
2886 case TargetLowering::Expand:
2887 // Expand to CopyToReg if the target set
2888 // StackPointerRegisterToSaveRestore.
2889 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) {
2890 Result = DAG.getCopyToReg(Tmp1, SP, Tmp2);
2898 case ISD::READCYCLECOUNTER:
2899 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain
2900 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2901 switch (TLI.getOperationAction(ISD::READCYCLECOUNTER,
2902 Node->getValueType(0))) {
2903 default: assert(0 && "This action is not supported yet!");
2904 case TargetLowering::Legal:
2905 Tmp1 = Result.getValue(0);
2906 Tmp2 = Result.getValue(1);
2908 case TargetLowering::Custom:
2909 Result = TLI.LowerOperation(Result, DAG);
2910 Tmp1 = LegalizeOp(Result.getValue(0));
2911 Tmp2 = LegalizeOp(Result.getValue(1));
2915 // Since rdcc produce two values, make sure to remember that we legalized
2917 AddLegalizedOperand(SDValue(Node, 0), Tmp1);
2918 AddLegalizedOperand(SDValue(Node, 1), Tmp2);
2922 switch (getTypeAction(Node->getOperand(0).getValueType())) {
2923 case Expand: assert(0 && "It's impossible to expand bools");
2925 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the condition.
2928 assert(!Node->getOperand(0).getValueType().isVector() && "not possible");
2929 Tmp1 = PromoteOp(Node->getOperand(0)); // Promote the condition.
2930 // Make sure the condition is either zero or one.
2931 unsigned BitWidth = Tmp1.getValueSizeInBits();
2932 if (!DAG.MaskedValueIsZero(Tmp1,
2933 APInt::getHighBitsSet(BitWidth, BitWidth-1)))
2934 Tmp1 = DAG.getZeroExtendInReg(Tmp1, MVT::i1);
2938 Tmp2 = LegalizeOp(Node->getOperand(1)); // TrueVal
2939 Tmp3 = LegalizeOp(Node->getOperand(2)); // FalseVal
2941 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2943 switch (TLI.getOperationAction(ISD::SELECT, Tmp2.getValueType())) {
2944 default: assert(0 && "This action is not supported yet!");
2945 case TargetLowering::Legal: break;
2946 case TargetLowering::Custom: {
2947 Tmp1 = TLI.LowerOperation(Result, DAG);
2948 if (Tmp1.getNode()) Result = Tmp1;
2951 case TargetLowering::Expand:
2952 if (Tmp1.getOpcode() == ISD::SETCC) {
2953 Result = DAG.getSelectCC(Tmp1.getOperand(0), Tmp1.getOperand(1),
2955 cast<CondCodeSDNode>(Tmp1.getOperand(2))->get());
2957 Result = DAG.getSelectCC(Tmp1,
2958 DAG.getConstant(0, Tmp1.getValueType()),
2959 Tmp2, Tmp3, ISD::SETNE);
2962 case TargetLowering::Promote: {
2964 TLI.getTypeToPromoteTo(ISD::SELECT, Tmp2.getValueType());
2965 unsigned ExtOp, TruncOp;
2966 if (Tmp2.getValueType().isVector()) {
2967 ExtOp = ISD::BIT_CONVERT;
2968 TruncOp = ISD::BIT_CONVERT;
2969 } else if (Tmp2.getValueType().isInteger()) {
2970 ExtOp = ISD::ANY_EXTEND;
2971 TruncOp = ISD::TRUNCATE;
2973 ExtOp = ISD::FP_EXTEND;
2974 TruncOp = ISD::FP_ROUND;
2976 // Promote each of the values to the new type.
2977 Tmp2 = DAG.getNode(ExtOp, NVT, Tmp2);
2978 Tmp3 = DAG.getNode(ExtOp, NVT, Tmp3);
2979 // Perform the larger operation, then round down.
2980 Result = DAG.getNode(ISD::SELECT, NVT, Tmp1, Tmp2,Tmp3);
2981 if (TruncOp != ISD::FP_ROUND)
2982 Result = DAG.getNode(TruncOp, Node->getValueType(0), Result);
2984 Result = DAG.getNode(TruncOp, Node->getValueType(0), Result,
2985 DAG.getIntPtrConstant(0));
2990 case ISD::SELECT_CC: {
2991 Tmp1 = Node->getOperand(0); // LHS
2992 Tmp2 = Node->getOperand(1); // RHS
2993 Tmp3 = LegalizeOp(Node->getOperand(2)); // True
2994 Tmp4 = LegalizeOp(Node->getOperand(3)); // False
2995 SDValue CC = Node->getOperand(4);
2997 LegalizeSetCC(TLI.getSetCCResultType(Tmp1), Tmp1, Tmp2, CC);
2999 // If we didn't get both a LHS and RHS back from LegalizeSetCC,
3000 // the LHS is a legal SETCC itself. In this case, we need to compare
3001 // the result against zero to select between true and false values.
3002 if (Tmp2.getNode() == 0) {
3003 Tmp2 = DAG.getConstant(0, Tmp1.getValueType());
3004 CC = DAG.getCondCode(ISD::SETNE);
3006 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4, CC);
3008 // Everything is legal, see if we should expand this op or something.
3009 switch (TLI.getOperationAction(ISD::SELECT_CC, Tmp3.getValueType())) {
3010 default: assert(0 && "This action is not supported yet!");
3011 case TargetLowering::Legal: break;
3012 case TargetLowering::Custom:
3013 Tmp1 = TLI.LowerOperation(Result, DAG);
3014 if (Tmp1.getNode()) Result = Tmp1;
3020 Tmp1 = Node->getOperand(0);
3021 Tmp2 = Node->getOperand(1);
3022 Tmp3 = Node->getOperand(2);
3023 LegalizeSetCC(Node->getValueType(0), Tmp1, Tmp2, Tmp3);
3025 // If we had to Expand the SetCC operands into a SELECT node, then it may
3026 // not always be possible to return a true LHS & RHS. In this case, just
3027 // return the value we legalized, returned in the LHS
3028 if (Tmp2.getNode() == 0) {
3033 switch (TLI.getOperationAction(ISD::SETCC, Tmp1.getValueType())) {
3034 default: assert(0 && "Cannot handle this action for SETCC yet!");
3035 case TargetLowering::Custom:
3038 case TargetLowering::Legal:
3039 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
3041 Tmp4 = TLI.LowerOperation(Result, DAG);
3042 if (Tmp4.getNode()) Result = Tmp4;
3045 case TargetLowering::Promote: {
3046 // First step, figure out the appropriate operation to use.
3047 // Allow SETCC to not be supported for all legal data types
3048 // Mostly this targets FP
3049 MVT NewInTy = Node->getOperand(0).getValueType();
3050 MVT OldVT = NewInTy; OldVT = OldVT;
3052 // Scan for the appropriate larger type to use.
3054 NewInTy = (MVT::SimpleValueType)(NewInTy.getSimpleVT()+1);
3056 assert(NewInTy.isInteger() == OldVT.isInteger() &&
3057 "Fell off of the edge of the integer world");
3058 assert(NewInTy.isFloatingPoint() == OldVT.isFloatingPoint() &&
3059 "Fell off of the edge of the floating point world");
3061 // If the target supports SETCC of this type, use it.
3062 if (TLI.isOperationLegal(ISD::SETCC, NewInTy))
3065 if (NewInTy.isInteger())
3066 assert(0 && "Cannot promote Legal Integer SETCC yet");
3068 Tmp1 = DAG.getNode(ISD::FP_EXTEND, NewInTy, Tmp1);
3069 Tmp2 = DAG.getNode(ISD::FP_EXTEND, NewInTy, Tmp2);
3071 Tmp1 = LegalizeOp(Tmp1);
3072 Tmp2 = LegalizeOp(Tmp2);
3073 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
3074 Result = LegalizeOp(Result);
3077 case TargetLowering::Expand:
3078 // Expand a setcc node into a select_cc of the same condition, lhs, and
3079 // rhs that selects between const 1 (true) and const 0 (false).
3080 MVT VT = Node->getValueType(0);
3081 Result = DAG.getNode(ISD::SELECT_CC, VT, Tmp1, Tmp2,
3082 DAG.getConstant(1, VT), DAG.getConstant(0, VT),
3088 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
3089 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS
3090 SDValue CC = Node->getOperand(2);
3092 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, CC);
3094 // Everything is legal, see if we should expand this op or something.
3095 switch (TLI.getOperationAction(ISD::VSETCC, Tmp1.getValueType())) {
3096 default: assert(0 && "This action is not supported yet!");
3097 case TargetLowering::Legal: break;
3098 case TargetLowering::Custom:
3099 Tmp1 = TLI.LowerOperation(Result, DAG);
3100 if (Tmp1.getNode()) Result = Tmp1;
3102 case TargetLowering::Expand: {
3103 // Unroll into a nasty set of scalar code for now.
3104 MVT VT = Node->getValueType(0);
3105 unsigned NumElems = VT.getVectorNumElements();
3106 MVT EltVT = VT.getVectorElementType();
3107 MVT TmpEltVT = Tmp1.getValueType().getVectorElementType();
3108 SmallVector<SDValue, 8> Ops(NumElems);
3109 for (unsigned i = 0; i < NumElems; ++i) {
3110 SDValue In1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, TmpEltVT,
3111 Tmp1, DAG.getIntPtrConstant(i));
3112 Ops[i] = DAG.getNode(ISD::SETCC, TLI.getSetCCResultType(In1), In1,
3113 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, TmpEltVT,
3114 Tmp2, DAG.getIntPtrConstant(i)),
3116 Ops[i] = DAG.getNode(ISD::SELECT, EltVT, Ops[i],
3117 DAG.getConstant(EltVT.getIntegerVTBitMask(),EltVT),
3118 DAG.getConstant(0, EltVT));
3120 Result = DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], NumElems);
3127 case ISD::SHL_PARTS:
3128 case ISD::SRA_PARTS:
3129 case ISD::SRL_PARTS: {
3130 SmallVector<SDValue, 8> Ops;
3131 bool Changed = false;
3132 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
3133 Ops.push_back(LegalizeOp(Node->getOperand(i)));
3134 Changed |= Ops.back() != Node->getOperand(i);
3137 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
3139 switch (TLI.getOperationAction(Node->getOpcode(),
3140 Node->getValueType(0))) {
3141 default: assert(0 && "This action is not supported yet!");
3142 case TargetLowering::Legal: break;
3143 case TargetLowering::Custom:
3144 Tmp1 = TLI.LowerOperation(Result, DAG);
3145 if (Tmp1.getNode()) {
3146 SDValue Tmp2, RetVal(0, 0);
3147 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) {
3148 Tmp2 = LegalizeOp(Tmp1.getValue(i));
3149 AddLegalizedOperand(SDValue(Node, i), Tmp2);
3150 if (i == Op.getResNo())
3153 assert(RetVal.getNode() && "Illegal result number");
3159 // Since these produce multiple values, make sure to remember that we
3160 // legalized all of them.
3161 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
3162 AddLegalizedOperand(SDValue(Node, i), Result.getValue(i));
3163 return Result.getValue(Op.getResNo());
3185 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
3186 switch (getTypeAction(Node->getOperand(1).getValueType())) {
3187 case Expand: assert(0 && "Not possible");
3189 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the RHS.
3192 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the RHS.
3196 if ((Node->getOpcode() == ISD::SHL ||
3197 Node->getOpcode() == ISD::SRL ||
3198 Node->getOpcode() == ISD::SRA) &&
3199 !Node->getValueType(0).isVector()) {
3200 Tmp2 = LegalizeShiftAmount(Tmp2);
3203 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
3205 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3206 default: assert(0 && "BinOp legalize operation not supported");
3207 case TargetLowering::Legal: break;
3208 case TargetLowering::Custom:
3209 Tmp1 = TLI.LowerOperation(Result, DAG);
3210 if (Tmp1.getNode()) {
3214 // Fall through if the custom lower can't deal with the operation
3215 case TargetLowering::Expand: {
3216 MVT VT = Op.getValueType();
3218 // See if multiply or divide can be lowered using two-result operations.
3219 SDVTList VTs = DAG.getVTList(VT, VT);
3220 if (Node->getOpcode() == ISD::MUL) {
3221 // We just need the low half of the multiply; try both the signed
3222 // and unsigned forms. If the target supports both SMUL_LOHI and
3223 // UMUL_LOHI, form a preference by checking which forms of plain
3224 // MULH it supports.
3225 bool HasSMUL_LOHI = TLI.isOperationLegal(ISD::SMUL_LOHI, VT);
3226 bool HasUMUL_LOHI = TLI.isOperationLegal(ISD::UMUL_LOHI, VT);
3227 bool HasMULHS = TLI.isOperationLegal(ISD::MULHS, VT);
3228 bool HasMULHU = TLI.isOperationLegal(ISD::MULHU, VT);
3229 unsigned OpToUse = 0;
3230 if (HasSMUL_LOHI && !HasMULHS) {
3231 OpToUse = ISD::SMUL_LOHI;
3232 } else if (HasUMUL_LOHI && !HasMULHU) {
3233 OpToUse = ISD::UMUL_LOHI;
3234 } else if (HasSMUL_LOHI) {
3235 OpToUse = ISD::SMUL_LOHI;
3236 } else if (HasUMUL_LOHI) {
3237 OpToUse = ISD::UMUL_LOHI;
3240 Result = SDValue(DAG.getNode(OpToUse, VTs, Tmp1, Tmp2).getNode(), 0);
3244 if (Node->getOpcode() == ISD::MULHS &&
3245 TLI.isOperationLegal(ISD::SMUL_LOHI, VT)) {
3246 Result = SDValue(DAG.getNode(ISD::SMUL_LOHI, VTs, Tmp1, Tmp2).getNode(),
3250 if (Node->getOpcode() == ISD::MULHU &&
3251 TLI.isOperationLegal(ISD::UMUL_LOHI, VT)) {
3252 Result = SDValue(DAG.getNode(ISD::UMUL_LOHI, VTs, Tmp1, Tmp2).getNode(),
3256 if (Node->getOpcode() == ISD::SDIV &&
3257 TLI.isOperationLegal(ISD::SDIVREM, VT)) {
3258 Result = SDValue(DAG.getNode(ISD::SDIVREM, VTs, Tmp1, Tmp2).getNode(),
3262 if (Node->getOpcode() == ISD::UDIV &&
3263 TLI.isOperationLegal(ISD::UDIVREM, VT)) {
3264 Result = SDValue(DAG.getNode(ISD::UDIVREM, VTs, Tmp1, Tmp2).getNode(),
3269 // Check to see if we have a libcall for this operator.
3270 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
3271 bool isSigned = false;
3272 switch (Node->getOpcode()) {
3275 if (VT == MVT::i32) {
3276 LC = Node->getOpcode() == ISD::UDIV
3277 ? RTLIB::UDIV_I32 : RTLIB::SDIV_I32;
3278 isSigned = Node->getOpcode() == ISD::SDIV;
3283 LC = RTLIB::MUL_I32;
3286 LC = GetFPLibCall(VT, RTLIB::POW_F32, RTLIB::POW_F64, RTLIB::POW_F80,
3287 RTLIB::POW_PPCF128);
3291 if (LC != RTLIB::UNKNOWN_LIBCALL) {
3293 Result = ExpandLibCall(LC, Node, isSigned, Dummy);
3297 assert(Node->getValueType(0).isVector() &&
3298 "Cannot expand this binary operator!");
3299 // Expand the operation into a bunch of nasty scalar code.
3300 Result = LegalizeOp(UnrollVectorOp(Op));
3303 case TargetLowering::Promote: {
3304 switch (Node->getOpcode()) {
3305 default: assert(0 && "Do not know how to promote this BinOp!");
3309 MVT OVT = Node->getValueType(0);
3310 MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
3311 assert(OVT.isVector() && "Cannot promote this BinOp!");
3312 // Bit convert each of the values to the new type.
3313 Tmp1 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp1);
3314 Tmp2 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp2);
3315 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
3316 // Bit convert the result back the original type.
3317 Result = DAG.getNode(ISD::BIT_CONVERT, OVT, Result);
3325 case ISD::SMUL_LOHI:
3326 case ISD::UMUL_LOHI:
3329 // These nodes will only be produced by target-specific lowering, so
3330 // they shouldn't be here if they aren't legal.
3331 assert(TLI.isOperationLegal(Node->getOpcode(), Node->getValueType(0)) &&
3332 "This must be legal!");
3334 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
3335 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS
3336 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
3339 case ISD::FCOPYSIGN: // FCOPYSIGN does not require LHS/RHS to match type!
3340 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
3341 switch (getTypeAction(Node->getOperand(1).getValueType())) {
3342 case Expand: assert(0 && "Not possible");
3344 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the RHS.
3347 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the RHS.
3351 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
3353 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3354 default: assert(0 && "Operation not supported");
3355 case TargetLowering::Custom:
3356 Tmp1 = TLI.LowerOperation(Result, DAG);
3357 if (Tmp1.getNode()) Result = Tmp1;
3359 case TargetLowering::Legal: break;
3360 case TargetLowering::Expand: {
3361 // If this target supports fabs/fneg natively and select is cheap,
3362 // do this efficiently.
3363 if (!TLI.isSelectExpensive() &&
3364 TLI.getOperationAction(ISD::FABS, Tmp1.getValueType()) ==
3365 TargetLowering::Legal &&
3366 TLI.getOperationAction(ISD::FNEG, Tmp1.getValueType()) ==
3367 TargetLowering::Legal) {
3368 // Get the sign bit of the RHS.
3370 Tmp2.getValueType() == MVT::f32 ? MVT::i32 : MVT::i64;
3371 SDValue SignBit = DAG.getNode(ISD::BIT_CONVERT, IVT, Tmp2);
3372 SignBit = DAG.getSetCC(TLI.getSetCCResultType(SignBit),
3373 SignBit, DAG.getConstant(0, IVT), ISD::SETLT);
3374 // Get the absolute value of the result.
3375 SDValue AbsVal = DAG.getNode(ISD::FABS, Tmp1.getValueType(), Tmp1);
3376 // Select between the nabs and abs value based on the sign bit of
3378 Result = DAG.getNode(ISD::SELECT, AbsVal.getValueType(), SignBit,
3379 DAG.getNode(ISD::FNEG, AbsVal.getValueType(),
3382 Result = LegalizeOp(Result);
3386 // Otherwise, do bitwise ops!
3388 Node->getValueType(0) == MVT::f32 ? MVT::i32 : MVT::i64;
3389 Result = ExpandFCOPYSIGNToBitwiseOps(Node, NVT, DAG, TLI);
3390 Result = DAG.getNode(ISD::BIT_CONVERT, Node->getValueType(0), Result);
3391 Result = LegalizeOp(Result);
3399 Tmp1 = LegalizeOp(Node->getOperand(0));
3400 Tmp2 = LegalizeOp(Node->getOperand(1));
3401 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
3402 Tmp3 = Result.getValue(0);
3403 Tmp4 = Result.getValue(1);
3405 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3406 default: assert(0 && "This action is not supported yet!");
3407 case TargetLowering::Legal:
3409 case TargetLowering::Custom:
3410 Tmp1 = TLI.LowerOperation(Tmp3, DAG);
3411 if (Tmp1.getNode() != NULL) {
3412 Tmp3 = LegalizeOp(Tmp1);
3413 Tmp4 = LegalizeOp(Tmp1.getValue(1));
3417 // Since this produces two values, make sure to remember that we legalized
3419 AddLegalizedOperand(SDValue(Node, 0), Tmp3);
3420 AddLegalizedOperand(SDValue(Node, 1), Tmp4);
3421 return Op.getResNo() ? Tmp4 : Tmp3;
3425 Tmp1 = LegalizeOp(Node->getOperand(0));
3426 Tmp2 = LegalizeOp(Node->getOperand(1));
3427 Tmp3 = LegalizeOp(Node->getOperand(2));
3428 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
3429 Tmp3 = Result.getValue(0);
3430 Tmp4 = Result.getValue(1);
3432 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3433 default: assert(0 && "This action is not supported yet!");
3434 case TargetLowering::Legal:
3436 case TargetLowering::Custom:
3437 Tmp1 = TLI.LowerOperation(Tmp3, DAG);
3438 if (Tmp1.getNode() != NULL) {
3439 Tmp3 = LegalizeOp(Tmp1);
3440 Tmp4 = LegalizeOp(Tmp1.getValue(1));
3444 // Since this produces two values, make sure to remember that we legalized
3446 AddLegalizedOperand(SDValue(Node, 0), Tmp3);
3447 AddLegalizedOperand(SDValue(Node, 1), Tmp4);
3448 return Op.getResNo() ? Tmp4 : Tmp3;
3450 case ISD::BUILD_PAIR: {
3451 MVT PairTy = Node->getValueType(0);
3452 // TODO: handle the case where the Lo and Hi operands are not of legal type
3453 Tmp1 = LegalizeOp(Node->getOperand(0)); // Lo
3454 Tmp2 = LegalizeOp(Node->getOperand(1)); // Hi
3455 switch (TLI.getOperationAction(ISD::BUILD_PAIR, PairTy)) {
3456 case TargetLowering::Promote:
3457 case TargetLowering::Custom:
3458 assert(0 && "Cannot promote/custom this yet!");
3459 case TargetLowering::Legal:
3460 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1))
3461 Result = DAG.getNode(ISD::BUILD_PAIR, PairTy, Tmp1, Tmp2);
3463 case TargetLowering::Expand:
3464 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, PairTy, Tmp1);
3465 Tmp2 = DAG.getNode(ISD::ANY_EXTEND, PairTy, Tmp2);
3466 Tmp2 = DAG.getNode(ISD::SHL, PairTy, Tmp2,
3467 DAG.getConstant(PairTy.getSizeInBits()/2,
3468 TLI.getShiftAmountTy()));
3469 Result = DAG.getNode(ISD::OR, PairTy, Tmp1, Tmp2);
3478 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
3479 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS
3481 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3482 case TargetLowering::Promote: assert(0 && "Cannot promote this yet!");
3483 case TargetLowering::Custom:
3486 case TargetLowering::Legal:
3487 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
3489 Tmp1 = TLI.LowerOperation(Result, DAG);
3490 if (Tmp1.getNode()) Result = Tmp1;
3493 case TargetLowering::Expand: {
3494 unsigned DivOpc= (Node->getOpcode() == ISD::UREM) ? ISD::UDIV : ISD::SDIV;
3495 bool isSigned = DivOpc == ISD::SDIV;
3496 MVT VT = Node->getValueType(0);
3498 // See if remainder can be lowered using two-result operations.
3499 SDVTList VTs = DAG.getVTList(VT, VT);
3500 if (Node->getOpcode() == ISD::SREM &&
3501 TLI.isOperationLegal(ISD::SDIVREM, VT)) {
3502 Result = SDValue(DAG.getNode(ISD::SDIVREM, VTs, Tmp1, Tmp2).getNode(), 1);
3505 if (Node->getOpcode() == ISD::UREM &&
3506 TLI.isOperationLegal(ISD::UDIVREM, VT)) {
3507 Result = SDValue(DAG.getNode(ISD::UDIVREM, VTs, Tmp1, Tmp2).getNode(), 1);
3511 if (VT.isInteger()) {
3512 if (TLI.getOperationAction(DivOpc, VT) ==
3513 TargetLowering::Legal) {
3515 Result = DAG.getNode(DivOpc, VT, Tmp1, Tmp2);
3516 Result = DAG.getNode(ISD::MUL, VT, Result, Tmp2);
3517 Result = DAG.getNode(ISD::SUB, VT, Tmp1, Result);
3518 } else if (VT.isVector()) {
3519 Result = LegalizeOp(UnrollVectorOp(Op));
3521 assert(VT == MVT::i32 &&
3522 "Cannot expand this binary operator!");
3523 RTLIB::Libcall LC = Node->getOpcode() == ISD::UREM
3524 ? RTLIB::UREM_I32 : RTLIB::SREM_I32;
3526 Result = ExpandLibCall(LC, Node, isSigned, Dummy);
3529 assert(VT.isFloatingPoint() &&
3530 "remainder op must have integer or floating-point type");
3531 if (VT.isVector()) {
3532 Result = LegalizeOp(UnrollVectorOp(Op));
3534 // Floating point mod -> fmod libcall.
3535 RTLIB::Libcall LC = GetFPLibCall(VT, RTLIB::REM_F32, RTLIB::REM_F64,
3536 RTLIB::REM_F80, RTLIB::REM_PPCF128);
3538 Result = ExpandLibCall(LC, Node, false/*sign irrelevant*/, Dummy);
3546 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
3547 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
3549 MVT VT = Node->getValueType(0);
3550 switch (TLI.getOperationAction(Node->getOpcode(), MVT::Other)) {
3551 default: assert(0 && "This action is not supported yet!");
3552 case TargetLowering::Custom:
3555 case TargetLowering::Legal:
3556 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
3557 Result = Result.getValue(0);
3558 Tmp1 = Result.getValue(1);
3561 Tmp2 = TLI.LowerOperation(Result, DAG);
3562 if (Tmp2.getNode()) {
3563 Result = LegalizeOp(Tmp2);
3564 Tmp1 = LegalizeOp(Tmp2.getValue(1));
3568 case TargetLowering::Expand: {
3569 const Value *V = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
3570 SDValue VAList = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp2, V, 0);
3571 // Increment the pointer, VAList, to the next vaarg
3572 Tmp3 = DAG.getNode(ISD::ADD, TLI.getPointerTy(), VAList,
3573 DAG.getConstant(TLI.getTargetData()->getABITypeSize(VT.getTypeForMVT()),
3574 TLI.getPointerTy()));
3575 // Store the incremented VAList to the legalized pointer
3576 Tmp3 = DAG.getStore(VAList.getValue(1), Tmp3, Tmp2, V, 0);
3577 // Load the actual argument out of the pointer VAList
3578 Result = DAG.getLoad(VT, Tmp3, VAList, NULL, 0);
3579 Tmp1 = LegalizeOp(Result.getValue(1));
3580 Result = LegalizeOp(Result);
3584 // Since VAARG produces two values, make sure to remember that we
3585 // legalized both of them.
3586 AddLegalizedOperand(SDValue(Node, 0), Result);
3587 AddLegalizedOperand(SDValue(Node, 1), Tmp1);
3588 return Op.getResNo() ? Tmp1 : Result;
3592 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
3593 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the dest pointer.
3594 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the source pointer.
3596 switch (TLI.getOperationAction(ISD::VACOPY, MVT::Other)) {
3597 default: assert(0 && "This action is not supported yet!");
3598 case TargetLowering::Custom:
3601 case TargetLowering::Legal:
3602 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3,
3603 Node->getOperand(3), Node->getOperand(4));
3605 Tmp1 = TLI.LowerOperation(Result, DAG);
3606 if (Tmp1.getNode()) Result = Tmp1;
3609 case TargetLowering::Expand:
3610 // This defaults to loading a pointer from the input and storing it to the
3611 // output, returning the chain.
3612 const Value *VD = cast<SrcValueSDNode>(Node->getOperand(3))->getValue();
3613 const Value *VS = cast<SrcValueSDNode>(Node->getOperand(4))->getValue();
3614 Tmp4 = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp3, VS, 0);
3615 Result = DAG.getStore(Tmp4.getValue(1), Tmp4, Tmp2, VD, 0);
3621 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
3622 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
3624 switch (TLI.getOperationAction(ISD::VAEND, MVT::Other)) {
3625 default: assert(0 && "This action is not supported yet!");
3626 case TargetLowering::Custom:
3629 case TargetLowering::Legal:
3630 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
3632 Tmp1 = TLI.LowerOperation(Tmp1, DAG);
3633 if (Tmp1.getNode()) Result = Tmp1;
3636 case TargetLowering::Expand:
3637 Result = Tmp1; // Default to a no-op, return the chain
3643 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
3644 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
3646 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
3648 switch (TLI.getOperationAction(ISD::VASTART, MVT::Other)) {
3649 default: assert(0 && "This action is not supported yet!");
3650 case TargetLowering::Legal: break;
3651 case TargetLowering::Custom:
3652 Tmp1 = TLI.LowerOperation(Result, DAG);
3653 if (Tmp1.getNode()) Result = Tmp1;
3660 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
3661 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS
3662 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
3663 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3665 assert(0 && "ROTL/ROTR legalize operation not supported");
3667 case TargetLowering::Legal:
3669 case TargetLowering::Custom:
3670 Tmp1 = TLI.LowerOperation(Result, DAG);
3671 if (Tmp1.getNode()) Result = Tmp1;
3673 case TargetLowering::Promote:
3674 assert(0 && "Do not know how to promote ROTL/ROTR");
3676 case TargetLowering::Expand:
3677 assert(0 && "Do not know how to expand ROTL/ROTR");
3683 Tmp1 = LegalizeOp(Node->getOperand(0)); // Op
3684 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3685 case TargetLowering::Custom:
3686 assert(0 && "Cannot custom legalize this yet!");
3687 case TargetLowering::Legal:
3688 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3690 case TargetLowering::Promote: {
3691 MVT OVT = Tmp1.getValueType();
3692 MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
3693 unsigned DiffBits = NVT.getSizeInBits() - OVT.getSizeInBits();
3695 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1);
3696 Tmp1 = DAG.getNode(ISD::BSWAP, NVT, Tmp1);
3697 Result = DAG.getNode(ISD::SRL, NVT, Tmp1,
3698 DAG.getConstant(DiffBits, TLI.getShiftAmountTy()));
3701 case TargetLowering::Expand:
3702 Result = ExpandBSWAP(Tmp1);
3710 Tmp1 = LegalizeOp(Node->getOperand(0)); // Op
3711 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3712 case TargetLowering::Custom:
3713 case TargetLowering::Legal:
3714 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3715 if (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0)) ==
3716 TargetLowering::Custom) {
3717 Tmp1 = TLI.LowerOperation(Result, DAG);
3718 if (Tmp1.getNode()) {
3723 case TargetLowering::Promote: {
3724 MVT OVT = Tmp1.getValueType();
3725 MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
3727 // Zero extend the argument.
3728 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1);
3729 // Perform the larger operation, then subtract if needed.
3730 Tmp1 = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1);
3731 switch (Node->getOpcode()) {
3736 //if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT)
3737 Tmp2 = DAG.getSetCC(TLI.getSetCCResultType(Tmp1), Tmp1,
3738 DAG.getConstant(NVT.getSizeInBits(), NVT),
3740 Result = DAG.getNode(ISD::SELECT, NVT, Tmp2,
3741 DAG.getConstant(OVT.getSizeInBits(), NVT), Tmp1);
3744 // Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT))
3745 Result = DAG.getNode(ISD::SUB, NVT, Tmp1,
3746 DAG.getConstant(NVT.getSizeInBits() -
3747 OVT.getSizeInBits(), NVT));
3752 case TargetLowering::Expand:
3753 Result = ExpandBitCount(Node->getOpcode(), Tmp1);
3773 case ISD::FNEARBYINT:
3774 Tmp1 = LegalizeOp(Node->getOperand(0));
3775 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3776 case TargetLowering::Promote:
3777 case TargetLowering::Custom:
3780 case TargetLowering::Legal:
3781 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3783 Tmp1 = TLI.LowerOperation(Result, DAG);
3784 if (Tmp1.getNode()) Result = Tmp1;
3787 case TargetLowering::Expand:
3788 switch (Node->getOpcode()) {
3789 default: assert(0 && "Unreachable!");
3791 // Expand Y = FNEG(X) -> Y = SUB -0.0, X
3792 Tmp2 = DAG.getConstantFP(-0.0, Node->getValueType(0));
3793 Result = DAG.getNode(ISD::FSUB, Node->getValueType(0), Tmp2, Tmp1);
3796 // Expand Y = FABS(X) -> Y = (X >u 0.0) ? X : fneg(X).
3797 MVT VT = Node->getValueType(0);
3798 Tmp2 = DAG.getConstantFP(0.0, VT);
3799 Tmp2 = DAG.getSetCC(TLI.getSetCCResultType(Tmp1), Tmp1, Tmp2,
3801 Tmp3 = DAG.getNode(ISD::FNEG, VT, Tmp1);
3802 Result = DAG.getNode(ISD::SELECT, VT, Tmp2, Tmp1, Tmp3);
3817 case ISD::FNEARBYINT: {
3818 MVT VT = Node->getValueType(0);
3820 // Expand unsupported unary vector operators by unrolling them.
3821 if (VT.isVector()) {
3822 Result = LegalizeOp(UnrollVectorOp(Op));
3826 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
3827 switch(Node->getOpcode()) {
3829 LC = GetFPLibCall(VT, RTLIB::SQRT_F32, RTLIB::SQRT_F64,
3830 RTLIB::SQRT_F80, RTLIB::SQRT_PPCF128);
3833 LC = GetFPLibCall(VT, RTLIB::SIN_F32, RTLIB::SIN_F64,
3834 RTLIB::SIN_F80, RTLIB::SIN_PPCF128);
3837 LC = GetFPLibCall(VT, RTLIB::COS_F32, RTLIB::COS_F64,
3838 RTLIB::COS_F80, RTLIB::COS_PPCF128);
3841 LC = GetFPLibCall(VT, RTLIB::LOG_F32, RTLIB::LOG_F64,
3842 RTLIB::LOG_F80, RTLIB::LOG_PPCF128);
3845 LC = GetFPLibCall(VT, RTLIB::LOG2_F32, RTLIB::LOG2_F64,
3846 RTLIB::LOG2_F80, RTLIB::LOG2_PPCF128);
3849 LC = GetFPLibCall(VT, RTLIB::LOG10_F32, RTLIB::LOG10_F64,
3850 RTLIB::LOG10_F80, RTLIB::LOG10_PPCF128);
3853 LC = GetFPLibCall(VT, RTLIB::EXP_F32, RTLIB::EXP_F64,
3854 RTLIB::EXP_F80, RTLIB::EXP_PPCF128);
3857 LC = GetFPLibCall(VT, RTLIB::EXP2_F32, RTLIB::EXP2_F64,
3858 RTLIB::EXP2_F80, RTLIB::EXP2_PPCF128);
3861 LC = GetFPLibCall(VT, RTLIB::TRUNC_F32, RTLIB::TRUNC_F64,
3862 RTLIB::TRUNC_F80, RTLIB::TRUNC_PPCF128);
3865 LC = GetFPLibCall(VT, RTLIB::FLOOR_F32, RTLIB::FLOOR_F64,
3866 RTLIB::FLOOR_F80, RTLIB::FLOOR_PPCF128);
3869 LC = GetFPLibCall(VT, RTLIB::CEIL_F32, RTLIB::CEIL_F64,
3870 RTLIB::CEIL_F80, RTLIB::CEIL_PPCF128);
3873 LC = GetFPLibCall(VT, RTLIB::RINT_F32, RTLIB::RINT_F64,
3874 RTLIB::RINT_F80, RTLIB::RINT_PPCF128);
3876 case ISD::FNEARBYINT:
3877 LC = GetFPLibCall(VT, RTLIB::NEARBYINT_F32, RTLIB::NEARBYINT_F64,
3878 RTLIB::NEARBYINT_F80, RTLIB::NEARBYINT_PPCF128);
3881 default: assert(0 && "Unreachable!");
3884 Result = ExpandLibCall(LC, Node, false/*sign irrelevant*/, Dummy);
3892 MVT VT = Node->getValueType(0);
3894 // Expand unsupported unary vector operators by unrolling them.
3895 if (VT.isVector()) {
3896 Result = LegalizeOp(UnrollVectorOp(Op));
3900 // We always lower FPOWI into a libcall. No target support for it yet.
3901 RTLIB::Libcall LC = GetFPLibCall(VT, RTLIB::POWI_F32, RTLIB::POWI_F64,
3902 RTLIB::POWI_F80, RTLIB::POWI_PPCF128);
3904 Result = ExpandLibCall(LC, Node, false/*sign irrelevant*/, Dummy);
3907 case ISD::BIT_CONVERT:
3908 if (!isTypeLegal(Node->getOperand(0).getValueType())) {
3909 Result = EmitStackConvert(Node->getOperand(0), Node->getValueType(0),
3910 Node->getValueType(0));
3911 } else if (Op.getOperand(0).getValueType().isVector()) {
3912 // The input has to be a vector type, we have to either scalarize it, pack
3913 // it, or convert it based on whether the input vector type is legal.
3914 SDNode *InVal = Node->getOperand(0).getNode();
3915 int InIx = Node->getOperand(0).getResNo();
3916 unsigned NumElems = InVal->getValueType(InIx).getVectorNumElements();
3917 MVT EVT = InVal->getValueType(InIx).getVectorElementType();
3919 // Figure out if there is a simple type corresponding to this Vector
3920 // type. If so, convert to the vector type.
3921 MVT TVT = MVT::getVectorVT(EVT, NumElems);
3922 if (TLI.isTypeLegal(TVT)) {
3923 // Turn this into a bit convert of the vector input.
3924 Result = DAG.getNode(ISD::BIT_CONVERT, Node->getValueType(0),
3925 LegalizeOp(Node->getOperand(0)));
3927 } else if (NumElems == 1) {
3928 // Turn this into a bit convert of the scalar input.
3929 Result = DAG.getNode(ISD::BIT_CONVERT, Node->getValueType(0),
3930 ScalarizeVectorOp(Node->getOperand(0)));
3933 // FIXME: UNIMP! Store then reload
3934 assert(0 && "Cast from unsupported vector type not implemented yet!");
3937 switch (TLI.getOperationAction(ISD::BIT_CONVERT,
3938 Node->getOperand(0).getValueType())) {
3939 default: assert(0 && "Unknown operation action!");
3940 case TargetLowering::Expand:
3941 Result = EmitStackConvert(Node->getOperand(0), Node->getValueType(0),
3942 Node->getValueType(0));
3944 case TargetLowering::Legal:
3945 Tmp1 = LegalizeOp(Node->getOperand(0));
3946 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3951 case ISD::CONVERT_RNDSAT: {
3952 ISD::CvtCode CvtCode = cast<CvtRndSatSDNode>(Node)->getCvtCode();
3954 default: assert(0 && "Unknown cvt code!");
3965 SDValue DTyOp = Node->getOperand(1);
3966 SDValue STyOp = Node->getOperand(2);
3967 SDValue RndOp = Node->getOperand(3);
3968 SDValue SatOp = Node->getOperand(4);
3969 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3970 case Expand: assert(0 && "Shouldn't need to expand other operators here!");
3972 Tmp1 = LegalizeOp(Node->getOperand(0));
3973 Result = DAG.UpdateNodeOperands(Result, Tmp1, DTyOp, STyOp,
3975 if (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0)) ==
3976 TargetLowering::Custom) {
3977 Tmp1 = TLI.LowerOperation(Result, DAG);
3978 if (Tmp1.getNode()) Result = Tmp1;
3982 Result = PromoteOp(Node->getOperand(0));
3983 // For FP, make Op1 a i32
3985 Result = DAG.getConvertRndSat(Op.getValueType(), Result,
3986 DTyOp, STyOp, RndOp, SatOp, CvtCode);
3991 } // end switch CvtCode
3994 // Conversion operators. The source and destination have different types.
3995 case ISD::SINT_TO_FP:
3996 case ISD::UINT_TO_FP: {
3997 bool isSigned = Node->getOpcode() == ISD::SINT_TO_FP;
3998 Result = LegalizeINT_TO_FP(Result, isSigned,
3999 Node->getValueType(0), Node->getOperand(0));
4003 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4005 Tmp1 = LegalizeOp(Node->getOperand(0));
4006 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
4007 default: assert(0 && "Unknown TRUNCATE legalization operation action!");
4008 case TargetLowering::Custom:
4011 case TargetLowering::Legal:
4012 Result = DAG.UpdateNodeOperands(Result, Tmp1);
4014 Tmp1 = TLI.LowerOperation(Result, DAG);
4015 if (Tmp1.getNode()) Result = Tmp1;
4018 case TargetLowering::Expand:
4019 assert(Result.getValueType().isVector() && "must be vector type");
4020 // Unroll the truncate. We should do better.
4021 Result = LegalizeOp(UnrollVectorOp(Result));
4025 ExpandOp(Node->getOperand(0), Tmp1, Tmp2);
4027 // Since the result is legal, we should just be able to truncate the low
4028 // part of the source.
4029 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), Tmp1);
4032 Result = PromoteOp(Node->getOperand(0));
4033 Result = DAG.getNode(ISD::TRUNCATE, Op.getValueType(), Result);
4038 case ISD::FP_TO_SINT:
4039 case ISD::FP_TO_UINT:
4040 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4042 Tmp1 = LegalizeOp(Node->getOperand(0));
4044 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))){
4045 default: assert(0 && "Unknown operation action!");
4046 case TargetLowering::Custom:
4049 case TargetLowering::Legal:
4050 Result = DAG.UpdateNodeOperands(Result, Tmp1);
4052 Tmp1 = TLI.LowerOperation(Result, DAG);
4053 if (Tmp1.getNode()) Result = Tmp1;
4056 case TargetLowering::Promote:
4057 Result = PromoteLegalFP_TO_INT(Tmp1, Node->getValueType(0),
4058 Node->getOpcode() == ISD::FP_TO_SINT);
4060 case TargetLowering::Expand:
4061 if (Node->getOpcode() == ISD::FP_TO_UINT) {
4062 SDValue True, False;
4063 MVT VT = Node->getOperand(0).getValueType();
4064 MVT NVT = Node->getValueType(0);
4065 const uint64_t zero[] = {0, 0};
4066 APFloat apf = APFloat(APInt(VT.getSizeInBits(), 2, zero));
4067 APInt x = APInt::getSignBit(NVT.getSizeInBits());
4068 (void)apf.convertFromAPInt(x, false, APFloat::rmNearestTiesToEven);
4069 Tmp2 = DAG.getConstantFP(apf, VT);
4070 Tmp3 = DAG.getSetCC(TLI.getSetCCResultType(Node->getOperand(0)),
4071 Node->getOperand(0), Tmp2, ISD::SETLT);
4072 True = DAG.getNode(ISD::FP_TO_SINT, NVT, Node->getOperand(0));
4073 False = DAG.getNode(ISD::FP_TO_SINT, NVT,
4074 DAG.getNode(ISD::FSUB, VT, Node->getOperand(0),
4076 False = DAG.getNode(ISD::XOR, NVT, False,
4077 DAG.getConstant(x, NVT));
4078 Result = DAG.getNode(ISD::SELECT, NVT, Tmp3, True, False);
4081 assert(0 && "Do not know how to expand FP_TO_SINT yet!");
4087 MVT VT = Op.getValueType();
4088 MVT OVT = Node->getOperand(0).getValueType();
4089 // Convert ppcf128 to i32
4090 if (OVT == MVT::ppcf128 && VT == MVT::i32) {
4091 if (Node->getOpcode() == ISD::FP_TO_SINT) {
4092 Result = DAG.getNode(ISD::FP_ROUND_INREG, MVT::ppcf128,
4093 Node->getOperand(0), DAG.getValueType(MVT::f64));
4094 Result = DAG.getNode(ISD::FP_ROUND, MVT::f64, Result,
4095 DAG.getIntPtrConstant(1));
4096 Result = DAG.getNode(ISD::FP_TO_SINT, VT, Result);
4098 const uint64_t TwoE31[] = {0x41e0000000000000LL, 0};
4099 APFloat apf = APFloat(APInt(128, 2, TwoE31));
4100 Tmp2 = DAG.getConstantFP(apf, OVT);
4101 // X>=2^31 ? (int)(X-2^31)+0x80000000 : (int)X
4102 // FIXME: generated code sucks.
4103 Result = DAG.getNode(ISD::SELECT_CC, VT, Node->getOperand(0), Tmp2,
4104 DAG.getNode(ISD::ADD, MVT::i32,
4105 DAG.getNode(ISD::FP_TO_SINT, VT,
4106 DAG.getNode(ISD::FSUB, OVT,
4107 Node->getOperand(0), Tmp2)),
4108 DAG.getConstant(0x80000000, MVT::i32)),
4109 DAG.getNode(ISD::FP_TO_SINT, VT,
4110 Node->getOperand(0)),
4111 DAG.getCondCode(ISD::SETGE));
4115 // Convert f32 / f64 to i32 / i64 / i128.
4116 RTLIB::Libcall LC = (Node->getOpcode() == ISD::FP_TO_SINT) ?
4117 RTLIB::getFPTOSINT(OVT, VT) : RTLIB::getFPTOUINT(OVT, VT);
4118 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpectd fp-to-int conversion!");
4120 Result = ExpandLibCall(LC, Node, false/*sign irrelevant*/, Dummy);
4124 Tmp1 = PromoteOp(Node->getOperand(0));
4125 Result = DAG.UpdateNodeOperands(Result, LegalizeOp(Tmp1));
4126 Result = LegalizeOp(Result);
4131 case ISD::FP_EXTEND: {
4132 MVT DstVT = Op.getValueType();
4133 MVT SrcVT = Op.getOperand(0).getValueType();
4134 if (TLI.getConvertAction(SrcVT, DstVT) == TargetLowering::Expand) {
4135 // The only other way we can lower this is to turn it into a STORE,
4136 // LOAD pair, targetting a temporary location (a stack slot).
4137 Result = EmitStackConvert(Node->getOperand(0), SrcVT, DstVT);
4140 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4141 case Expand: assert(0 && "Shouldn't need to expand other operators here!");
4143 Tmp1 = LegalizeOp(Node->getOperand(0));
4144 Result = DAG.UpdateNodeOperands(Result, Tmp1);
4147 Tmp1 = PromoteOp(Node->getOperand(0));
4148 Result = DAG.getNode(ISD::FP_EXTEND, Op.getValueType(), Tmp1);
4153 case ISD::FP_ROUND: {
4154 MVT DstVT = Op.getValueType();
4155 MVT SrcVT = Op.getOperand(0).getValueType();
4156 if (TLI.getConvertAction(SrcVT, DstVT) == TargetLowering::Expand) {
4157 if (SrcVT == MVT::ppcf128) {
4159 ExpandOp(Node->getOperand(0), Lo, Result);
4160 // Round it the rest of the way (e.g. to f32) if needed.
4161 if (DstVT!=MVT::f64)
4162 Result = DAG.getNode(ISD::FP_ROUND, DstVT, Result, Op.getOperand(1));
4165 // The only other way we can lower this is to turn it into a STORE,
4166 // LOAD pair, targetting a temporary location (a stack slot).
4167 Result = EmitStackConvert(Node->getOperand(0), DstVT, DstVT);
4170 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4171 case Expand: assert(0 && "Shouldn't need to expand other operators here!");
4173 Tmp1 = LegalizeOp(Node->getOperand(0));
4174 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
4177 Tmp1 = PromoteOp(Node->getOperand(0));
4178 Result = DAG.getNode(ISD::FP_ROUND, Op.getValueType(), Tmp1,
4179 Node->getOperand(1));
4184 case ISD::ANY_EXTEND:
4185 case ISD::ZERO_EXTEND:
4186 case ISD::SIGN_EXTEND:
4187 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4188 case Expand: assert(0 && "Shouldn't need to expand other operators here!");
4190 Tmp1 = LegalizeOp(Node->getOperand(0));
4191 Result = DAG.UpdateNodeOperands(Result, Tmp1);
4192 if (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0)) ==
4193 TargetLowering::Custom) {
4194 Tmp1 = TLI.LowerOperation(Result, DAG);
4195 if (Tmp1.getNode()) Result = Tmp1;
4199 switch (Node->getOpcode()) {
4200 case ISD::ANY_EXTEND:
4201 Tmp1 = PromoteOp(Node->getOperand(0));
4202 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Tmp1);
4204 case ISD::ZERO_EXTEND:
4205 Result = PromoteOp(Node->getOperand(0));
4206 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Result);
4207 Result = DAG.getZeroExtendInReg(Result,
4208 Node->getOperand(0).getValueType());
4210 case ISD::SIGN_EXTEND:
4211 Result = PromoteOp(Node->getOperand(0));
4212 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Result);
4213 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(),
4215 DAG.getValueType(Node->getOperand(0).getValueType()));
4220 case ISD::FP_ROUND_INREG:
4221 case ISD::SIGN_EXTEND_INREG: {
4222 Tmp1 = LegalizeOp(Node->getOperand(0));
4223 MVT ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT();
4225 // If this operation is not supported, convert it to a shl/shr or load/store
4227 switch (TLI.getOperationAction(Node->getOpcode(), ExtraVT)) {
4228 default: assert(0 && "This action not supported for this op yet!");
4229 case TargetLowering::Legal:
4230 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
4232 case TargetLowering::Expand:
4233 // If this is an integer extend and shifts are supported, do that.
4234 if (Node->getOpcode() == ISD::SIGN_EXTEND_INREG) {
4235 // NOTE: we could fall back on load/store here too for targets without
4236 // SAR. However, it is doubtful that any exist.
4237 unsigned BitsDiff = Node->getValueType(0).getSizeInBits() -
4238 ExtraVT.getSizeInBits();
4239 SDValue ShiftCst = DAG.getConstant(BitsDiff, TLI.getShiftAmountTy());
4240 Result = DAG.getNode(ISD::SHL, Node->getValueType(0),
4241 Node->getOperand(0), ShiftCst);
4242 Result = DAG.getNode(ISD::SRA, Node->getValueType(0),
4244 } else if (Node->getOpcode() == ISD::FP_ROUND_INREG) {
4245 // The only way we can lower this is to turn it into a TRUNCSTORE,
4246 // EXTLOAD pair, targetting a temporary location (a stack slot).
4248 // NOTE: there is a choice here between constantly creating new stack
4249 // slots and always reusing the same one. We currently always create
4250 // new ones, as reuse may inhibit scheduling.
4251 Result = EmitStackConvert(Node->getOperand(0), ExtraVT,
4252 Node->getValueType(0));
4254 assert(0 && "Unknown op");
4260 case ISD::TRAMPOLINE: {
4262 for (unsigned i = 0; i != 6; ++i)
4263 Ops[i] = LegalizeOp(Node->getOperand(i));
4264 Result = DAG.UpdateNodeOperands(Result, Ops, 6);
4265 // The only option for this node is to custom lower it.
4266 Result = TLI.LowerOperation(Result, DAG);
4267 assert(Result.getNode() && "Should always custom lower!");
4269 // Since trampoline produces two values, make sure to remember that we
4270 // legalized both of them.
4271 Tmp1 = LegalizeOp(Result.getValue(1));
4272 Result = LegalizeOp(Result);
4273 AddLegalizedOperand(SDValue(Node, 0), Result);
4274 AddLegalizedOperand(SDValue(Node, 1), Tmp1);
4275 return Op.getResNo() ? Tmp1 : Result;
4277 case ISD::FLT_ROUNDS_: {
4278 MVT VT = Node->getValueType(0);
4279 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
4280 default: assert(0 && "This action not supported for this op yet!");
4281 case TargetLowering::Custom:
4282 Result = TLI.LowerOperation(Op, DAG);
4283 if (Result.getNode()) break;
4285 case TargetLowering::Legal:
4286 // If this operation is not supported, lower it to constant 1
4287 Result = DAG.getConstant(1, VT);
4293 MVT VT = Node->getValueType(0);
4294 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
4295 default: assert(0 && "This action not supported for this op yet!");
4296 case TargetLowering::Legal:
4297 Tmp1 = LegalizeOp(Node->getOperand(0));
4298 Result = DAG.UpdateNodeOperands(Result, Tmp1);
4300 case TargetLowering::Custom:
4301 Result = TLI.LowerOperation(Op, DAG);
4302 if (Result.getNode()) break;
4304 case TargetLowering::Expand:
4305 // If this operation is not supported, lower it to 'abort()' call
4306 Tmp1 = LegalizeOp(Node->getOperand(0));
4307 TargetLowering::ArgListTy Args;
4308 std::pair<SDValue,SDValue> CallResult =
4309 TLI.LowerCallTo(Tmp1, Type::VoidTy,
4310 false, false, false, false, CallingConv::C, false,
4311 DAG.getExternalSymbol("abort", TLI.getPointerTy()),
4313 Result = CallResult.second;
4321 MVT VT = Node->getValueType(0);
4322 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
4323 default: assert(0 && "This action not supported for this op yet!");
4324 case TargetLowering::Custom:
4325 Result = TLI.LowerOperation(Op, DAG);
4326 if (Result.getNode()) break;
4328 case TargetLowering::Legal: {
4329 SDValue LHS = LegalizeOp(Node->getOperand(0));
4330 SDValue RHS = LegalizeOp(Node->getOperand(1));
4332 SDValue Sum = DAG.getNode(Node->getOpcode() == ISD::SADDO ?
4333 ISD::ADD : ISD::SUB, LHS.getValueType(),
4335 MVT OType = Node->getValueType(1);
4337 SDValue Zero = DAG.getConstant(0, LHS.getValueType());
4339 // LHSSign -> LHS >= 0
4340 // RHSSign -> RHS >= 0
4341 // SumSign -> Sum >= 0
4344 // Overflow -> (LHSSign == RHSSign) && (LHSSign != SumSign)
4346 // Overflow -> (LHSSign != RHSSign) && (LHSSign != SumSign)
4348 SDValue LHSSign = DAG.getSetCC(OType, LHS, Zero, ISD::SETGE);
4349 SDValue RHSSign = DAG.getSetCC(OType, RHS, Zero, ISD::SETGE);
4350 SDValue SignsMatch = DAG.getSetCC(OType, LHSSign, RHSSign,
4351 Node->getOpcode() == ISD::SADDO ?
4352 ISD::SETEQ : ISD::SETNE);
4354 SDValue SumSign = DAG.getSetCC(OType, Sum, Zero, ISD::SETGE);
4355 SDValue SumSignNE = DAG.getSetCC(OType, LHSSign, SumSign, ISD::SETNE);
4357 SDValue Cmp = DAG.getNode(ISD::AND, OType, SignsMatch, SumSignNE);
4359 MVT ValueVTs[] = { LHS.getValueType(), OType };
4360 SDValue Ops[] = { Sum, Cmp };
4362 Result = DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(&ValueVTs[0], 2),
4364 SDNode *RNode = Result.getNode();
4365 DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 0), SDValue(RNode, 0));
4366 DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 1), SDValue(RNode, 1));
4375 MVT VT = Node->getValueType(0);
4376 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
4377 default: assert(0 && "This action not supported for this op yet!");
4378 case TargetLowering::Custom:
4379 Result = TLI.LowerOperation(Op, DAG);
4380 if (Result.getNode()) break;
4382 case TargetLowering::Legal: {
4383 SDValue LHS = LegalizeOp(Node->getOperand(0));
4384 SDValue RHS = LegalizeOp(Node->getOperand(1));
4386 SDValue Sum = DAG.getNode(Node->getOpcode() == ISD::UADDO ?
4387 ISD::ADD : ISD::SUB, LHS.getValueType(),
4389 MVT OType = Node->getValueType(1);
4390 SDValue Cmp = DAG.getSetCC(OType, Sum, LHS,
4391 Node->getOpcode () == ISD::UADDO ?
4392 ISD::SETULT : ISD::SETUGT);
4394 MVT ValueVTs[] = { LHS.getValueType(), OType };
4395 SDValue Ops[] = { Sum, Cmp };
4397 Result = DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(&ValueVTs[0], 2),
4399 SDNode *RNode = Result.getNode();
4400 DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 0), SDValue(RNode, 0));
4401 DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 1), SDValue(RNode, 1));
4410 MVT VT = Node->getValueType(0);
4411 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
4412 default: assert(0 && "This action is not supported at all!");
4413 case TargetLowering::Custom:
4414 Result = TLI.LowerOperation(Op, DAG);
4415 if (Result.getNode()) break;
4417 case TargetLowering::Legal:
4418 // FIXME: According to Hacker's Delight, this can be implemented in
4419 // target independent lowering, but it would be inefficient, since it
4420 // requires a division + a branch.
4421 assert(0 && "Target independent lowering is not supported for SMULO/UMULO!");
4429 assert(Result.getValueType() == Op.getValueType() &&
4430 "Bad legalization!");
4432 // Make sure that the generated code is itself legal.
4434 Result = LegalizeOp(Result);
4436 // Note that LegalizeOp may be reentered even from single-use nodes, which
4437 // means that we always must cache transformed nodes.
4438 AddLegalizedOperand(Op, Result);
4442 /// PromoteOp - Given an operation that produces a value in an invalid type,
4443 /// promote it to compute the value into a larger type. The produced value will
4444 /// have the correct bits for the low portion of the register, but no guarantee
4445 /// is made about the top bits: it may be zero, sign-extended, or garbage.
4446 SDValue SelectionDAGLegalize::PromoteOp(SDValue Op) {
4447 MVT VT = Op.getValueType();
4448 MVT NVT = TLI.getTypeToTransformTo(VT);
4449 assert(getTypeAction(VT) == Promote &&
4450 "Caller should expand or legalize operands that are not promotable!");
4451 assert(NVT.bitsGT(VT) && NVT.isInteger() == VT.isInteger() &&
4452 "Cannot promote to smaller type!");
4454 SDValue Tmp1, Tmp2, Tmp3;
4456 SDNode *Node = Op.getNode();
4458 DenseMap<SDValue, SDValue>::iterator I = PromotedNodes.find(Op);
4459 if (I != PromotedNodes.end()) return I->second;
4461 switch (Node->getOpcode()) {
4462 case ISD::CopyFromReg:
4463 assert(0 && "CopyFromReg must be legal!");
4466 cerr << "NODE: "; Node->dump(&DAG); cerr << "\n";
4468 assert(0 && "Do not know how to promote this operator!");
4471 Result = DAG.getNode(ISD::UNDEF, NVT);
4475 Result = DAG.getNode(ISD::SIGN_EXTEND, NVT, Op);
4477 Result = DAG.getNode(ISD::ZERO_EXTEND, NVT, Op);
4478 assert(isa<ConstantSDNode>(Result) && "Didn't constant fold zext?");
4480 case ISD::ConstantFP:
4481 Result = DAG.getNode(ISD::FP_EXTEND, NVT, Op);
4482 assert(isa<ConstantFPSDNode>(Result) && "Didn't constant fold fp_extend?");
4486 assert(isTypeLegal(TLI.getSetCCResultType(Node->getOperand(0)))
4487 && "SetCC type is not legal??");
4488 Result = DAG.getNode(ISD::SETCC,
4489 TLI.getSetCCResultType(Node->getOperand(0)),
4490 Node->getOperand(0), Node->getOperand(1),
4491 Node->getOperand(2));
4495 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4497 Result = LegalizeOp(Node->getOperand(0));
4498 assert(Result.getValueType().bitsGE(NVT) &&
4499 "This truncation doesn't make sense!");
4500 if (Result.getValueType().bitsGT(NVT)) // Truncate to NVT instead of VT
4501 Result = DAG.getNode(ISD::TRUNCATE, NVT, Result);
4504 // The truncation is not required, because we don't guarantee anything
4505 // about high bits anyway.
4506 Result = PromoteOp(Node->getOperand(0));
4509 ExpandOp(Node->getOperand(0), Tmp1, Tmp2);
4510 // Truncate the low part of the expanded value to the result type
4511 Result = DAG.getNode(ISD::TRUNCATE, NVT, Tmp1);
4514 case ISD::SIGN_EXTEND:
4515 case ISD::ZERO_EXTEND:
4516 case ISD::ANY_EXTEND:
4517 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4518 case Expand: assert(0 && "BUG: Smaller reg should have been promoted!");
4520 // Input is legal? Just do extend all the way to the larger type.
4521 Result = DAG.getNode(Node->getOpcode(), NVT, Node->getOperand(0));
4524 // Promote the reg if it's smaller.
4525 Result = PromoteOp(Node->getOperand(0));
4526 // The high bits are not guaranteed to be anything. Insert an extend.
4527 if (Node->getOpcode() == ISD::SIGN_EXTEND)
4528 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Result,
4529 DAG.getValueType(Node->getOperand(0).getValueType()));
4530 else if (Node->getOpcode() == ISD::ZERO_EXTEND)
4531 Result = DAG.getZeroExtendInReg(Result,
4532 Node->getOperand(0).getValueType());
4536 case ISD::CONVERT_RNDSAT: {
4537 ISD::CvtCode CvtCode = cast<CvtRndSatSDNode>(Node)->getCvtCode();
4538 assert ((CvtCode == ISD::CVT_SS || CvtCode == ISD::CVT_SU ||
4539 CvtCode == ISD::CVT_US || CvtCode == ISD::CVT_UU ||
4540 CvtCode == ISD::CVT_SF || CvtCode == ISD::CVT_UF) &&
4541 "can only promote integers");
4542 Result = DAG.getConvertRndSat(NVT, Node->getOperand(0),
4543 Node->getOperand(1), Node->getOperand(2),
4544 Node->getOperand(3), Node->getOperand(4),
4549 case ISD::BIT_CONVERT:
4550 Result = EmitStackConvert(Node->getOperand(0), Node->getValueType(0),
4551 Node->getValueType(0));
4552 Result = PromoteOp(Result);
4555 case ISD::FP_EXTEND:
4556 assert(0 && "Case not implemented. Dynamically dead with 2 FP types!");
4558 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4559 case Expand: assert(0 && "BUG: Cannot expand FP regs!");
4560 case Promote: assert(0 && "Unreachable with 2 FP types!");
4562 if (Node->getConstantOperandVal(1) == 0) {
4563 // Input is legal? Do an FP_ROUND_INREG.
4564 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Node->getOperand(0),
4565 DAG.getValueType(VT));
4567 // Just remove the truncate, it isn't affecting the value.
4568 Result = DAG.getNode(ISD::FP_ROUND, NVT, Node->getOperand(0),
4569 Node->getOperand(1));
4574 case ISD::SINT_TO_FP:
4575 case ISD::UINT_TO_FP:
4576 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4578 // No extra round required here.
4579 Result = DAG.getNode(Node->getOpcode(), NVT, Node->getOperand(0));
4583 Result = PromoteOp(Node->getOperand(0));
4584 if (Node->getOpcode() == ISD::SINT_TO_FP)
4585 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(),
4587 DAG.getValueType(Node->getOperand(0).getValueType()));
4589 Result = DAG.getZeroExtendInReg(Result,
4590 Node->getOperand(0).getValueType());
4591 // No extra round required here.
4592 Result = DAG.getNode(Node->getOpcode(), NVT, Result);
4595 Result = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP, NVT,
4596 Node->getOperand(0));
4597 // Round if we cannot tolerate excess precision.
4598 if (NoExcessFPPrecision)
4599 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
4600 DAG.getValueType(VT));
4605 case ISD::SIGN_EXTEND_INREG:
4606 Result = PromoteOp(Node->getOperand(0));
4607 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Result,
4608 Node->getOperand(1));
4610 case ISD::FP_TO_SINT:
4611 case ISD::FP_TO_UINT:
4612 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4615 Tmp1 = Node->getOperand(0);
4618 // The input result is prerounded, so we don't have to do anything
4620 Tmp1 = PromoteOp(Node->getOperand(0));
4623 // If we're promoting a UINT to a larger size, check to see if the new node
4624 // will be legal. If it isn't, check to see if FP_TO_SINT is legal, since
4625 // we can use that instead. This allows us to generate better code for
4626 // FP_TO_UINT for small destination sizes on targets where FP_TO_UINT is not
4627 // legal, such as PowerPC.
4628 if (Node->getOpcode() == ISD::FP_TO_UINT &&
4629 !TLI.isOperationLegal(ISD::FP_TO_UINT, NVT) &&
4630 (TLI.isOperationLegal(ISD::FP_TO_SINT, NVT) ||
4631 TLI.getOperationAction(ISD::FP_TO_SINT, NVT)==TargetLowering::Custom)){
4632 Result = DAG.getNode(ISD::FP_TO_SINT, NVT, Tmp1);
4634 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
4640 Tmp1 = PromoteOp(Node->getOperand(0));
4641 assert(Tmp1.getValueType() == NVT);
4642 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
4643 // NOTE: we do not have to do any extra rounding here for
4644 // NoExcessFPPrecision, because we know the input will have the appropriate
4645 // precision, and these operations don't modify precision at all.
4660 case ISD::FNEARBYINT:
4661 Tmp1 = PromoteOp(Node->getOperand(0));
4662 assert(Tmp1.getValueType() == NVT);
4663 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
4664 if (NoExcessFPPrecision)
4665 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
4666 DAG.getValueType(VT));
4671 // Promote f32 pow(i) to f64 pow(i). Note that this could insert a libcall
4672 // directly as well, which may be better.
4673 Tmp1 = PromoteOp(Node->getOperand(0));
4674 Tmp2 = Node->getOperand(1);
4675 if (Node->getOpcode() == ISD::FPOW)
4676 Tmp2 = PromoteOp(Tmp2);
4677 assert(Tmp1.getValueType() == NVT);
4678 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
4679 if (NoExcessFPPrecision)
4680 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
4681 DAG.getValueType(VT));
4685 case ISD::ATOMIC_CMP_SWAP: {
4686 AtomicSDNode* AtomNode = cast<AtomicSDNode>(Node);
4687 Tmp2 = PromoteOp(Node->getOperand(2));
4688 Tmp3 = PromoteOp(Node->getOperand(3));
4689 Result = DAG.getAtomic(Node->getOpcode(), AtomNode->getMemoryVT(),
4690 AtomNode->getChain(),
4691 AtomNode->getBasePtr(), Tmp2, Tmp3,
4692 AtomNode->getSrcValue(),
4693 AtomNode->getAlignment());
4694 // Remember that we legalized the chain.
4695 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
4698 case ISD::ATOMIC_LOAD_ADD:
4699 case ISD::ATOMIC_LOAD_SUB:
4700 case ISD::ATOMIC_LOAD_AND:
4701 case ISD::ATOMIC_LOAD_OR:
4702 case ISD::ATOMIC_LOAD_XOR:
4703 case ISD::ATOMIC_LOAD_NAND:
4704 case ISD::ATOMIC_LOAD_MIN:
4705 case ISD::ATOMIC_LOAD_MAX:
4706 case ISD::ATOMIC_LOAD_UMIN:
4707 case ISD::ATOMIC_LOAD_UMAX:
4708 case ISD::ATOMIC_SWAP: {
4709 AtomicSDNode* AtomNode = cast<AtomicSDNode>(Node);
4710 Tmp2 = PromoteOp(Node->getOperand(2));
4711 Result = DAG.getAtomic(Node->getOpcode(), AtomNode->getMemoryVT(),
4712 AtomNode->getChain(),
4713 AtomNode->getBasePtr(), Tmp2,
4714 AtomNode->getSrcValue(),
4715 AtomNode->getAlignment());
4716 // Remember that we legalized the chain.
4717 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
4727 // The input may have strange things in the top bits of the registers, but
4728 // these operations don't care. They may have weird bits going out, but
4729 // that too is okay if they are integer operations.
4730 Tmp1 = PromoteOp(Node->getOperand(0));
4731 Tmp2 = PromoteOp(Node->getOperand(1));
4732 assert(Tmp1.getValueType() == NVT && Tmp2.getValueType() == NVT);
4733 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
4738 Tmp1 = PromoteOp(Node->getOperand(0));
4739 Tmp2 = PromoteOp(Node->getOperand(1));
4740 assert(Tmp1.getValueType() == NVT && Tmp2.getValueType() == NVT);
4741 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
4743 // Floating point operations will give excess precision that we may not be
4744 // able to tolerate. If we DO allow excess precision, just leave it,
4745 // otherwise excise it.
4746 // FIXME: Why would we need to round FP ops more than integer ones?
4747 // Is Round(Add(Add(A,B),C)) != Round(Add(Round(Add(A,B)), C))
4748 if (NoExcessFPPrecision)
4749 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
4750 DAG.getValueType(VT));
4755 // These operators require that their input be sign extended.
4756 Tmp1 = PromoteOp(Node->getOperand(0));
4757 Tmp2 = PromoteOp(Node->getOperand(1));
4758 if (NVT.isInteger()) {
4759 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1,
4760 DAG.getValueType(VT));
4761 Tmp2 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp2,
4762 DAG.getValueType(VT));
4764 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
4766 // Perform FP_ROUND: this is probably overly pessimistic.
4767 if (NVT.isFloatingPoint() && NoExcessFPPrecision)
4768 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
4769 DAG.getValueType(VT));
4773 case ISD::FCOPYSIGN:
4774 // These operators require that their input be fp extended.
4775 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4776 case Expand: assert(0 && "not implemented");
4777 case Legal: Tmp1 = LegalizeOp(Node->getOperand(0)); break;
4778 case Promote: Tmp1 = PromoteOp(Node->getOperand(0)); break;
4780 switch (getTypeAction(Node->getOperand(1).getValueType())) {
4781 case Expand: assert(0 && "not implemented");
4782 case Legal: Tmp2 = LegalizeOp(Node->getOperand(1)); break;
4783 case Promote: Tmp2 = PromoteOp(Node->getOperand(1)); break;
4785 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
4787 // Perform FP_ROUND: this is probably overly pessimistic.
4788 if (NoExcessFPPrecision && Node->getOpcode() != ISD::FCOPYSIGN)
4789 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
4790 DAG.getValueType(VT));
4795 // These operators require that their input be zero extended.
4796 Tmp1 = PromoteOp(Node->getOperand(0));
4797 Tmp2 = PromoteOp(Node->getOperand(1));
4798 assert(NVT.isInteger() && "Operators don't apply to FP!");
4799 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT);
4800 Tmp2 = DAG.getZeroExtendInReg(Tmp2, VT);
4801 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
4805 Tmp1 = PromoteOp(Node->getOperand(0));
4806 Result = DAG.getNode(ISD::SHL, NVT, Tmp1, Node->getOperand(1));
4809 // The input value must be properly sign extended.
4810 Tmp1 = PromoteOp(Node->getOperand(0));
4811 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1,
4812 DAG.getValueType(VT));
4813 Result = DAG.getNode(ISD::SRA, NVT, Tmp1, Node->getOperand(1));
4816 // The input value must be properly zero extended.
4817 Tmp1 = PromoteOp(Node->getOperand(0));
4818 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT);
4819 Result = DAG.getNode(ISD::SRL, NVT, Tmp1, Node->getOperand(1));
4823 Tmp1 = Node->getOperand(0); // Get the chain.
4824 Tmp2 = Node->getOperand(1); // Get the pointer.
4825 if (TLI.getOperationAction(ISD::VAARG, VT) == TargetLowering::Custom) {
4826 Tmp3 = DAG.getVAArg(VT, Tmp1, Tmp2, Node->getOperand(2));
4827 Result = TLI.LowerOperation(Tmp3, DAG);
4829 const Value *V = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
4830 SDValue VAList = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp2, V, 0);
4831 // Increment the pointer, VAList, to the next vaarg
4832 Tmp3 = DAG.getNode(ISD::ADD, TLI.getPointerTy(), VAList,
4833 DAG.getConstant(VT.getSizeInBits()/8,
4834 TLI.getPointerTy()));
4835 // Store the incremented VAList to the legalized pointer
4836 Tmp3 = DAG.getStore(VAList.getValue(1), Tmp3, Tmp2, V, 0);
4837 // Load the actual argument out of the pointer VAList
4838 Result = DAG.getExtLoad(ISD::EXTLOAD, NVT, Tmp3, VAList, NULL, 0, VT);
4840 // Remember that we legalized the chain.
4841 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
4845 LoadSDNode *LD = cast<LoadSDNode>(Node);
4846 ISD::LoadExtType ExtType = ISD::isNON_EXTLoad(Node)
4847 ? ISD::EXTLOAD : LD->getExtensionType();
4848 Result = DAG.getExtLoad(ExtType, NVT,
4849 LD->getChain(), LD->getBasePtr(),
4850 LD->getSrcValue(), LD->getSrcValueOffset(),
4853 LD->getAlignment());
4854 // Remember that we legalized the chain.
4855 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
4859 Tmp2 = PromoteOp(Node->getOperand(1)); // Legalize the op0
4860 Tmp3 = PromoteOp(Node->getOperand(2)); // Legalize the op1
4862 MVT VT2 = Tmp2.getValueType();
4863 assert(VT2 == Tmp3.getValueType()
4864 && "PromoteOp SELECT: Operands 2 and 3 ValueTypes don't match");
4865 // Ensure that the resulting node is at least the same size as the operands'
4866 // value types, because we cannot assume that TLI.getSetCCValueType() is
4868 Result = DAG.getNode(ISD::SELECT, VT2, Node->getOperand(0), Tmp2, Tmp3);
4871 case ISD::SELECT_CC:
4872 Tmp2 = PromoteOp(Node->getOperand(2)); // True
4873 Tmp3 = PromoteOp(Node->getOperand(3)); // False
4874 Result = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0),
4875 Node->getOperand(1), Tmp2, Tmp3, Node->getOperand(4));
4878 Tmp1 = Node->getOperand(0);
4879 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1);
4880 Tmp1 = DAG.getNode(ISD::BSWAP, NVT, Tmp1);
4881 Result = DAG.getNode(ISD::SRL, NVT, Tmp1,
4882 DAG.getConstant(NVT.getSizeInBits() -
4884 TLI.getShiftAmountTy()));
4889 // Zero extend the argument
4890 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Node->getOperand(0));
4891 // Perform the larger operation, then subtract if needed.
4892 Tmp1 = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
4893 switch(Node->getOpcode()) {
4898 // if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT)
4899 Tmp2 = DAG.getSetCC(TLI.getSetCCResultType(Tmp1), Tmp1,
4900 DAG.getConstant(NVT.getSizeInBits(), NVT),
4902 Result = DAG.getNode(ISD::SELECT, NVT, Tmp2,
4903 DAG.getConstant(VT.getSizeInBits(), NVT), Tmp1);
4906 //Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT))
4907 Result = DAG.getNode(ISD::SUB, NVT, Tmp1,
4908 DAG.getConstant(NVT.getSizeInBits() -
4909 VT.getSizeInBits(), NVT));
4913 case ISD::EXTRACT_SUBVECTOR:
4914 Result = PromoteOp(ExpandEXTRACT_SUBVECTOR(Op));
4916 case ISD::EXTRACT_VECTOR_ELT:
4917 Result = PromoteOp(ExpandEXTRACT_VECTOR_ELT(Op));
4921 assert(Result.getNode() && "Didn't set a result!");
4923 // Make sure the result is itself legal.
4924 Result = LegalizeOp(Result);
4926 // Remember that we promoted this!
4927 AddPromotedOperand(Op, Result);
4931 /// ExpandEXTRACT_VECTOR_ELT - Expand an EXTRACT_VECTOR_ELT operation into
4932 /// a legal EXTRACT_VECTOR_ELT operation, scalar code, or memory traffic,
4933 /// based on the vector type. The return type of this matches the element type
4934 /// of the vector, which may not be legal for the target.
4935 SDValue SelectionDAGLegalize::ExpandEXTRACT_VECTOR_ELT(SDValue Op) {
4936 // We know that operand #0 is the Vec vector. If the index is a constant
4937 // or if the invec is a supported hardware type, we can use it. Otherwise,
4938 // lower to a store then an indexed load.
4939 SDValue Vec = Op.getOperand(0);
4940 SDValue Idx = Op.getOperand(1);
4942 MVT TVT = Vec.getValueType();
4943 unsigned NumElems = TVT.getVectorNumElements();
4945 switch (TLI.getOperationAction(ISD::EXTRACT_VECTOR_ELT, TVT)) {
4946 default: assert(0 && "This action is not supported yet!");
4947 case TargetLowering::Custom: {
4948 Vec = LegalizeOp(Vec);
4949 Op = DAG.UpdateNodeOperands(Op, Vec, Idx);
4950 SDValue Tmp3 = TLI.LowerOperation(Op, DAG);
4955 case TargetLowering::Legal:
4956 if (isTypeLegal(TVT)) {
4957 Vec = LegalizeOp(Vec);
4958 Op = DAG.UpdateNodeOperands(Op, Vec, Idx);
4962 case TargetLowering::Promote:
4963 assert(TVT.isVector() && "not vector type");
4964 // fall thru to expand since vectors are by default are promote
4965 case TargetLowering::Expand:
4969 if (NumElems == 1) {
4970 // This must be an access of the only element. Return it.
4971 Op = ScalarizeVectorOp(Vec);
4972 } else if (!TLI.isTypeLegal(TVT) && isa<ConstantSDNode>(Idx)) {
4973 unsigned NumLoElts = 1 << Log2_32(NumElems-1);
4974 ConstantSDNode *CIdx = cast<ConstantSDNode>(Idx);
4976 SplitVectorOp(Vec, Lo, Hi);
4977 if (CIdx->getZExtValue() < NumLoElts) {
4981 Idx = DAG.getConstant(CIdx->getZExtValue() - NumLoElts,
4982 Idx.getValueType());
4985 // It's now an extract from the appropriate high or low part. Recurse.
4986 Op = DAG.UpdateNodeOperands(Op, Vec, Idx);
4987 Op = ExpandEXTRACT_VECTOR_ELT(Op);
4989 // Store the value to a temporary stack slot, then LOAD the scalar
4990 // element back out.
4991 SDValue StackPtr = DAG.CreateStackTemporary(Vec.getValueType());
4992 SDValue Ch = DAG.getStore(DAG.getEntryNode(), Vec, StackPtr, NULL, 0);
4994 // Add the offset to the index.
4995 unsigned EltSize = Op.getValueType().getSizeInBits()/8;
4996 Idx = DAG.getNode(ISD::MUL, Idx.getValueType(), Idx,
4997 DAG.getConstant(EltSize, Idx.getValueType()));
4999 if (Idx.getValueType().bitsGT(TLI.getPointerTy()))
5000 Idx = DAG.getNode(ISD::TRUNCATE, TLI.getPointerTy(), Idx);
5002 Idx = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(), Idx);
5004 StackPtr = DAG.getNode(ISD::ADD, Idx.getValueType(), Idx, StackPtr);
5006 Op = DAG.getLoad(Op.getValueType(), Ch, StackPtr, NULL, 0);
5011 /// ExpandEXTRACT_SUBVECTOR - Expand a EXTRACT_SUBVECTOR operation. For now
5012 /// we assume the operation can be split if it is not already legal.
5013 SDValue SelectionDAGLegalize::ExpandEXTRACT_SUBVECTOR(SDValue Op) {
5014 // We know that operand #0 is the Vec vector. For now we assume the index
5015 // is a constant and that the extracted result is a supported hardware type.
5016 SDValue Vec = Op.getOperand(0);
5017 SDValue Idx = LegalizeOp(Op.getOperand(1));
5019 unsigned NumElems = Vec.getValueType().getVectorNumElements();
5021 if (NumElems == Op.getValueType().getVectorNumElements()) {
5022 // This must be an access of the desired vector length. Return it.
5026 ConstantSDNode *CIdx = cast<ConstantSDNode>(Idx);
5028 SplitVectorOp(Vec, Lo, Hi);
5029 if (CIdx->getZExtValue() < NumElems/2) {
5033 Idx = DAG.getConstant(CIdx->getZExtValue() - NumElems/2,
5034 Idx.getValueType());
5037 // It's now an extract from the appropriate high or low part. Recurse.
5038 Op = DAG.UpdateNodeOperands(Op, Vec, Idx);
5039 return ExpandEXTRACT_SUBVECTOR(Op);
5042 /// LegalizeSetCCOperands - Attempts to create a legal LHS and RHS for a SETCC
5043 /// with condition CC on the current target. This usually involves legalizing
5044 /// or promoting the arguments. In the case where LHS and RHS must be expanded,
5045 /// there may be no choice but to create a new SetCC node to represent the
5046 /// legalized value of setcc lhs, rhs. In this case, the value is returned in
5047 /// LHS, and the SDValue returned in RHS has a nil SDNode value.
5048 void SelectionDAGLegalize::LegalizeSetCCOperands(SDValue &LHS,
5051 SDValue Tmp1, Tmp2, Tmp3, Result;
5053 switch (getTypeAction(LHS.getValueType())) {
5055 Tmp1 = LegalizeOp(LHS); // LHS
5056 Tmp2 = LegalizeOp(RHS); // RHS
5059 Tmp1 = PromoteOp(LHS); // LHS
5060 Tmp2 = PromoteOp(RHS); // RHS
5062 // If this is an FP compare, the operands have already been extended.
5063 if (LHS.getValueType().isInteger()) {
5064 MVT VT = LHS.getValueType();
5065 MVT NVT = TLI.getTypeToTransformTo(VT);
5067 // Otherwise, we have to insert explicit sign or zero extends. Note
5068 // that we could insert sign extends for ALL conditions, but zero extend
5069 // is cheaper on many machines (an AND instead of two shifts), so prefer
5071 switch (cast<CondCodeSDNode>(CC)->get()) {
5072 default: assert(0 && "Unknown integer comparison!");
5079 // ALL of these operations will work if we either sign or zero extend
5080 // the operands (including the unsigned comparisons!). Zero extend is
5081 // usually a simpler/cheaper operation, so prefer it.
5082 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT);
5083 Tmp2 = DAG.getZeroExtendInReg(Tmp2, VT);
5089 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1,
5090 DAG.getValueType(VT));
5091 Tmp2 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp2,
5092 DAG.getValueType(VT));
5093 Tmp1 = LegalizeOp(Tmp1); // Relegalize new nodes.
5094 Tmp2 = LegalizeOp(Tmp2); // Relegalize new nodes.
5100 MVT VT = LHS.getValueType();
5101 if (VT == MVT::f32 || VT == MVT::f64) {
5102 // Expand into one or more soft-fp libcall(s).
5103 RTLIB::Libcall LC1 = RTLIB::UNKNOWN_LIBCALL, LC2 = RTLIB::UNKNOWN_LIBCALL;
5104 switch (cast<CondCodeSDNode>(CC)->get()) {
5107 LC1 = (VT == MVT::f32) ? RTLIB::OEQ_F32 : RTLIB::OEQ_F64;
5111 LC1 = (VT == MVT::f32) ? RTLIB::UNE_F32 : RTLIB::UNE_F64;
5115 LC1 = (VT == MVT::f32) ? RTLIB::OGE_F32 : RTLIB::OGE_F64;
5119 LC1 = (VT == MVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64;
5123 LC1 = (VT == MVT::f32) ? RTLIB::OLE_F32 : RTLIB::OLE_F64;
5127 LC1 = (VT == MVT::f32) ? RTLIB::OGT_F32 : RTLIB::OGT_F64;
5130 LC1 = (VT == MVT::f32) ? RTLIB::UO_F32 : RTLIB::UO_F64;
5133 LC1 = (VT == MVT::f32) ? RTLIB::O_F32 : RTLIB::O_F64;
5136 LC1 = (VT == MVT::f32) ? RTLIB::UO_F32 : RTLIB::UO_F64;
5137 switch (cast<CondCodeSDNode>(CC)->get()) {
5139 // SETONE = SETOLT | SETOGT
5140 LC1 = (VT == MVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64;
5143 LC2 = (VT == MVT::f32) ? RTLIB::OGT_F32 : RTLIB::OGT_F64;
5146 LC2 = (VT == MVT::f32) ? RTLIB::OGE_F32 : RTLIB::OGE_F64;
5149 LC2 = (VT == MVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64;
5152 LC2 = (VT == MVT::f32) ? RTLIB::OLE_F32 : RTLIB::OLE_F64;
5155 LC2 = (VT == MVT::f32) ? RTLIB::OEQ_F32 : RTLIB::OEQ_F64;
5157 default: assert(0 && "Unsupported FP setcc!");
5162 SDValue Ops[2] = { LHS, RHS };
5163 Tmp1 = ExpandLibCall(LC1, DAG.getMergeValues(Ops, 2).getNode(),
5164 false /*sign irrelevant*/, Dummy);
5165 Tmp2 = DAG.getConstant(0, MVT::i32);
5166 CC = DAG.getCondCode(TLI.getCmpLibcallCC(LC1));
5167 if (LC2 != RTLIB::UNKNOWN_LIBCALL) {
5168 Tmp1 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultType(Tmp1), Tmp1, Tmp2,
5170 LHS = ExpandLibCall(LC2, DAG.getMergeValues(Ops, 2).getNode(),
5171 false /*sign irrelevant*/, Dummy);
5172 Tmp2 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultType(LHS), LHS, Tmp2,
5173 DAG.getCondCode(TLI.getCmpLibcallCC(LC2)));
5174 Tmp1 = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp2);
5177 LHS = LegalizeOp(Tmp1);
5182 SDValue LHSLo, LHSHi, RHSLo, RHSHi;
5183 ExpandOp(LHS, LHSLo, LHSHi);
5184 ExpandOp(RHS, RHSLo, RHSHi);
5185 ISD::CondCode CCCode = cast<CondCodeSDNode>(CC)->get();
5187 if (VT==MVT::ppcf128) {
5188 // FIXME: This generated code sucks. We want to generate
5189 // FCMPU crN, hi1, hi2
5191 // FCMPU crN, lo1, lo2
5192 // The following can be improved, but not that much.
5193 Tmp1 = DAG.getSetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi,
5195 Tmp2 = DAG.getSetCC(TLI.getSetCCResultType(LHSLo), LHSLo, RHSLo, CCCode);
5196 Tmp3 = DAG.getNode(ISD::AND, Tmp1.getValueType(), Tmp1, Tmp2);
5197 Tmp1 = DAG.getSetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi,
5199 Tmp2 = DAG.getSetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi, CCCode);
5200 Tmp1 = DAG.getNode(ISD::AND, Tmp1.getValueType(), Tmp1, Tmp2);
5201 Tmp1 = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp3);
5210 if (ConstantSDNode *RHSCST = dyn_cast<ConstantSDNode>(RHSLo))
5211 if (RHSCST->isAllOnesValue()) {
5212 // Comparison to -1.
5213 Tmp1 = DAG.getNode(ISD::AND, LHSLo.getValueType(), LHSLo, LHSHi);
5218 Tmp1 = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSLo, RHSLo);
5219 Tmp2 = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSHi, RHSHi);
5220 Tmp1 = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp2);
5221 Tmp2 = DAG.getConstant(0, Tmp1.getValueType());
5224 // If this is a comparison of the sign bit, just look at the top part.
5226 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(RHS))
5227 if ((cast<CondCodeSDNode>(CC)->get() == ISD::SETLT &&
5228 CST->isNullValue()) || // X < 0
5229 (cast<CondCodeSDNode>(CC)->get() == ISD::SETGT &&
5230 CST->isAllOnesValue())) { // X > -1
5236 // FIXME: This generated code sucks.
5237 ISD::CondCode LowCC;
5239 default: assert(0 && "Unknown integer setcc!");
5241 case ISD::SETULT: LowCC = ISD::SETULT; break;
5243 case ISD::SETUGT: LowCC = ISD::SETUGT; break;
5245 case ISD::SETULE: LowCC = ISD::SETULE; break;
5247 case ISD::SETUGE: LowCC = ISD::SETUGE; break;
5250 // Tmp1 = lo(op1) < lo(op2) // Always unsigned comparison
5251 // Tmp2 = hi(op1) < hi(op2) // Signedness depends on operands
5252 // dest = hi(op1) == hi(op2) ? Tmp1 : Tmp2;
5254 // NOTE: on targets without efficient SELECT of bools, we can always use
5255 // this identity: (B1 ? B2 : B3) --> (B1 & B2)|(!B1&B3)
5256 TargetLowering::DAGCombinerInfo DagCombineInfo(DAG, false, true, NULL);
5257 Tmp1 = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSLo), LHSLo, RHSLo,
5258 LowCC, false, DagCombineInfo);
5259 if (!Tmp1.getNode())
5260 Tmp1 = DAG.getSetCC(TLI.getSetCCResultType(LHSLo), LHSLo, RHSLo, LowCC);
5261 Tmp2 = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi,
5262 CCCode, false, DagCombineInfo);
5263 if (!Tmp2.getNode())
5264 Tmp2 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultType(LHSHi), LHSHi,
5267 ConstantSDNode *Tmp1C = dyn_cast<ConstantSDNode>(Tmp1.getNode());
5268 ConstantSDNode *Tmp2C = dyn_cast<ConstantSDNode>(Tmp2.getNode());
5269 if ((Tmp1C && Tmp1C->isNullValue()) ||
5270 (Tmp2C && Tmp2C->isNullValue() &&
5271 (CCCode == ISD::SETLE || CCCode == ISD::SETGE ||
5272 CCCode == ISD::SETUGE || CCCode == ISD::SETULE)) ||
5273 (Tmp2C && Tmp2C->getAPIntValue() == 1 &&
5274 (CCCode == ISD::SETLT || CCCode == ISD::SETGT ||
5275 CCCode == ISD::SETUGT || CCCode == ISD::SETULT))) {
5276 // low part is known false, returns high part.
5277 // For LE / GE, if high part is known false, ignore the low part.
5278 // For LT / GT, if high part is known true, ignore the low part.
5282 Result = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi,
5283 ISD::SETEQ, false, DagCombineInfo);
5284 if (!Result.getNode())
5285 Result=DAG.getSetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi,
5287 Result = LegalizeOp(DAG.getNode(ISD::SELECT, Tmp1.getValueType(),
5288 Result, Tmp1, Tmp2));
5299 /// LegalizeSetCCCondCode - Legalize a SETCC with given LHS and RHS and
5300 /// condition code CC on the current target. This routine assumes LHS and rHS
5301 /// have already been legalized by LegalizeSetCCOperands. It expands SETCC with
5302 /// illegal condition code into AND / OR of multiple SETCC values.
5303 void SelectionDAGLegalize::LegalizeSetCCCondCode(MVT VT,
5304 SDValue &LHS, SDValue &RHS,
5306 MVT OpVT = LHS.getValueType();
5307 ISD::CondCode CCCode = cast<CondCodeSDNode>(CC)->get();
5308 switch (TLI.getCondCodeAction(CCCode, OpVT)) {
5309 default: assert(0 && "Unknown condition code action!");
5310 case TargetLowering::Legal:
5313 case TargetLowering::Expand: {
5314 ISD::CondCode CC1 = ISD::SETCC_INVALID, CC2 = ISD::SETCC_INVALID;
5317 default: assert(0 && "Don't know how to expand this condition!"); abort();
5318 case ISD::SETOEQ: CC1 = ISD::SETEQ; CC2 = ISD::SETO; Opc = ISD::AND; break;
5319 case ISD::SETOGT: CC1 = ISD::SETGT; CC2 = ISD::SETO; Opc = ISD::AND; break;
5320 case ISD::SETOGE: CC1 = ISD::SETGE; CC2 = ISD::SETO; Opc = ISD::AND; break;
5321 case ISD::SETOLT: CC1 = ISD::SETLT; CC2 = ISD::SETO; Opc = ISD::AND; break;
5322 case ISD::SETOLE: CC1 = ISD::SETLE; CC2 = ISD::SETO; Opc = ISD::AND; break;
5323 case ISD::SETONE: CC1 = ISD::SETNE; CC2 = ISD::SETO; Opc = ISD::AND; break;
5324 case ISD::SETUEQ: CC1 = ISD::SETEQ; CC2 = ISD::SETUO; Opc = ISD::OR; break;
5325 case ISD::SETUGT: CC1 = ISD::SETGT; CC2 = ISD::SETUO; Opc = ISD::OR; break;
5326 case ISD::SETUGE: CC1 = ISD::SETGE; CC2 = ISD::SETUO; Opc = ISD::OR; break;
5327 case ISD::SETULT: CC1 = ISD::SETLT; CC2 = ISD::SETUO; Opc = ISD::OR; break;
5328 case ISD::SETULE: CC1 = ISD::SETLE; CC2 = ISD::SETUO; Opc = ISD::OR; break;
5329 case ISD::SETUNE: CC1 = ISD::SETNE; CC2 = ISD::SETUO; Opc = ISD::OR; break;
5330 // FIXME: Implement more expansions.
5333 SDValue SetCC1 = DAG.getSetCC(VT, LHS, RHS, CC1);
5334 SDValue SetCC2 = DAG.getSetCC(VT, LHS, RHS, CC2);
5335 LHS = DAG.getNode(Opc, VT, SetCC1, SetCC2);
5343 /// EmitStackConvert - Emit a store/load combination to the stack. This stores
5344 /// SrcOp to a stack slot of type SlotVT, truncating it if needed. It then does
5345 /// a load from the stack slot to DestVT, extending it if needed.
5346 /// The resultant code need not be legal.
5347 SDValue SelectionDAGLegalize::EmitStackConvert(SDValue SrcOp,
5350 // Create the stack frame object.
5351 unsigned SrcAlign = TLI.getTargetData()->getPrefTypeAlignment(
5352 SrcOp.getValueType().getTypeForMVT());
5353 SDValue FIPtr = DAG.CreateStackTemporary(SlotVT, SrcAlign);
5355 FrameIndexSDNode *StackPtrFI = cast<FrameIndexSDNode>(FIPtr);
5356 int SPFI = StackPtrFI->getIndex();
5358 unsigned SrcSize = SrcOp.getValueType().getSizeInBits();
5359 unsigned SlotSize = SlotVT.getSizeInBits();
5360 unsigned DestSize = DestVT.getSizeInBits();
5361 unsigned DestAlign = TLI.getTargetData()->getPrefTypeAlignment(
5362 DestVT.getTypeForMVT());
5364 // Emit a store to the stack slot. Use a truncstore if the input value is
5365 // later than DestVT.
5368 if (SrcSize > SlotSize)
5369 Store = DAG.getTruncStore(DAG.getEntryNode(), SrcOp, FIPtr,
5370 PseudoSourceValue::getFixedStack(SPFI), 0,
5371 SlotVT, false, SrcAlign);
5373 assert(SrcSize == SlotSize && "Invalid store");
5374 Store = DAG.getStore(DAG.getEntryNode(), SrcOp, FIPtr,
5375 PseudoSourceValue::getFixedStack(SPFI), 0,
5379 // Result is a load from the stack slot.
5380 if (SlotSize == DestSize)
5381 return DAG.getLoad(DestVT, Store, FIPtr, NULL, 0, false, DestAlign);
5383 assert(SlotSize < DestSize && "Unknown extension!");
5384 return DAG.getExtLoad(ISD::EXTLOAD, DestVT, Store, FIPtr, NULL, 0, SlotVT,
5388 SDValue SelectionDAGLegalize::ExpandSCALAR_TO_VECTOR(SDNode *Node) {
5389 // Create a vector sized/aligned stack slot, store the value to element #0,
5390 // then load the whole vector back out.
5391 SDValue StackPtr = DAG.CreateStackTemporary(Node->getValueType(0));
5393 FrameIndexSDNode *StackPtrFI = cast<FrameIndexSDNode>(StackPtr);
5394 int SPFI = StackPtrFI->getIndex();
5396 SDValue Ch = DAG.getStore(DAG.getEntryNode(), Node->getOperand(0), StackPtr,
5397 PseudoSourceValue::getFixedStack(SPFI), 0);
5398 return DAG.getLoad(Node->getValueType(0), Ch, StackPtr,
5399 PseudoSourceValue::getFixedStack(SPFI), 0);
5403 /// ExpandBUILD_VECTOR - Expand a BUILD_VECTOR node on targets that don't
5404 /// support the operation, but do support the resultant vector type.
5405 SDValue SelectionDAGLegalize::ExpandBUILD_VECTOR(SDNode *Node) {
5407 // If the only non-undef value is the low element, turn this into a
5408 // SCALAR_TO_VECTOR node. If this is { X, X, X, X }, determine X.
5409 unsigned NumElems = Node->getNumOperands();
5410 bool isOnlyLowElement = true;
5411 SDValue SplatValue = Node->getOperand(0);
5413 // FIXME: it would be far nicer to change this into map<SDValue,uint64_t>
5414 // and use a bitmask instead of a list of elements.
5415 std::map<SDValue, std::vector<unsigned> > Values;
5416 Values[SplatValue].push_back(0);
5417 bool isConstant = true;
5418 if (!isa<ConstantFPSDNode>(SplatValue) && !isa<ConstantSDNode>(SplatValue) &&
5419 SplatValue.getOpcode() != ISD::UNDEF)
5422 for (unsigned i = 1; i < NumElems; ++i) {
5423 SDValue V = Node->getOperand(i);
5424 Values[V].push_back(i);
5425 if (V.getOpcode() != ISD::UNDEF)
5426 isOnlyLowElement = false;
5427 if (SplatValue != V)
5428 SplatValue = SDValue(0,0);
5430 // If this isn't a constant element or an undef, we can't use a constant
5432 if (!isa<ConstantFPSDNode>(V) && !isa<ConstantSDNode>(V) &&
5433 V.getOpcode() != ISD::UNDEF)
5437 if (isOnlyLowElement) {
5438 // If the low element is an undef too, then this whole things is an undef.
5439 if (Node->getOperand(0).getOpcode() == ISD::UNDEF)
5440 return DAG.getNode(ISD::UNDEF, Node->getValueType(0));
5441 // Otherwise, turn this into a scalar_to_vector node.
5442 return DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0),
5443 Node->getOperand(0));
5446 // If all elements are constants, create a load from the constant pool.
5448 MVT VT = Node->getValueType(0);
5449 std::vector<Constant*> CV;
5450 for (unsigned i = 0, e = NumElems; i != e; ++i) {
5451 if (ConstantFPSDNode *V =
5452 dyn_cast<ConstantFPSDNode>(Node->getOperand(i))) {
5453 CV.push_back(const_cast<ConstantFP *>(V->getConstantFPValue()));
5454 } else if (ConstantSDNode *V =
5455 dyn_cast<ConstantSDNode>(Node->getOperand(i))) {
5456 CV.push_back(const_cast<ConstantInt *>(V->getConstantIntValue()));
5458 assert(Node->getOperand(i).getOpcode() == ISD::UNDEF);
5460 Node->getOperand(0).getValueType().getTypeForMVT();
5461 CV.push_back(UndefValue::get(OpNTy));
5464 Constant *CP = ConstantVector::get(CV);
5465 SDValue CPIdx = DAG.getConstantPool(CP, TLI.getPointerTy());
5466 unsigned Alignment = 1 << cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
5467 return DAG.getLoad(VT, DAG.getEntryNode(), CPIdx,
5468 PseudoSourceValue::getConstantPool(), 0,
5472 if (SplatValue.getNode()) { // Splat of one value?
5473 // Build the shuffle constant vector: <0, 0, 0, 0>
5474 MVT MaskVT = MVT::getIntVectorWithNumElements(NumElems);
5475 SDValue Zero = DAG.getConstant(0, MaskVT.getVectorElementType());
5476 std::vector<SDValue> ZeroVec(NumElems, Zero);
5477 SDValue SplatMask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
5478 &ZeroVec[0], ZeroVec.size());
5480 // If the target supports VECTOR_SHUFFLE and this shuffle mask, use it.
5481 if (isShuffleLegal(Node->getValueType(0), SplatMask)) {
5482 // Get the splatted value into the low element of a vector register.
5484 DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0), SplatValue);
5486 // Return shuffle(LowValVec, undef, <0,0,0,0>)
5487 return DAG.getNode(ISD::VECTOR_SHUFFLE, Node->getValueType(0), LowValVec,
5488 DAG.getNode(ISD::UNDEF, Node->getValueType(0)),
5493 // If there are only two unique elements, we may be able to turn this into a
5495 if (Values.size() == 2) {
5496 // Get the two values in deterministic order.
5497 SDValue Val1 = Node->getOperand(1);
5499 std::map<SDValue, std::vector<unsigned> >::iterator MI = Values.begin();
5500 if (MI->first != Val1)
5503 Val2 = (++MI)->first;
5505 // If Val1 is an undef, make sure end ends up as Val2, to ensure that our
5506 // vector shuffle has the undef vector on the RHS.
5507 if (Val1.getOpcode() == ISD::UNDEF)
5508 std::swap(Val1, Val2);
5510 // Build the shuffle constant vector: e.g. <0, 4, 0, 4>
5511 MVT MaskVT = MVT::getIntVectorWithNumElements(NumElems);
5512 MVT MaskEltVT = MaskVT.getVectorElementType();
5513 std::vector<SDValue> MaskVec(NumElems);
5515 // Set elements of the shuffle mask for Val1.
5516 std::vector<unsigned> &Val1Elts = Values[Val1];
5517 for (unsigned i = 0, e = Val1Elts.size(); i != e; ++i)
5518 MaskVec[Val1Elts[i]] = DAG.getConstant(0, MaskEltVT);
5520 // Set elements of the shuffle mask for Val2.
5521 std::vector<unsigned> &Val2Elts = Values[Val2];
5522 for (unsigned i = 0, e = Val2Elts.size(); i != e; ++i)
5523 if (Val2.getOpcode() != ISD::UNDEF)
5524 MaskVec[Val2Elts[i]] = DAG.getConstant(NumElems, MaskEltVT);
5526 MaskVec[Val2Elts[i]] = DAG.getNode(ISD::UNDEF, MaskEltVT);
5528 SDValue ShuffleMask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
5529 &MaskVec[0], MaskVec.size());
5531 // If the target supports SCALAR_TO_VECTOR and this shuffle mask, use it.
5532 if (TLI.isOperationLegal(ISD::SCALAR_TO_VECTOR, Node->getValueType(0)) &&
5533 isShuffleLegal(Node->getValueType(0), ShuffleMask)) {
5534 Val1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0), Val1);
5535 Val2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0), Val2);
5536 SDValue Ops[] = { Val1, Val2, ShuffleMask };
5538 // Return shuffle(LoValVec, HiValVec, <0,1,0,1>)
5539 return DAG.getNode(ISD::VECTOR_SHUFFLE, Node->getValueType(0), Ops, 3);
5543 // Otherwise, we can't handle this case efficiently. Allocate a sufficiently
5544 // aligned object on the stack, store each element into it, then load
5545 // the result as a vector.
5546 MVT VT = Node->getValueType(0);
5547 // Create the stack frame object.
5548 SDValue FIPtr = DAG.CreateStackTemporary(VT);
5550 // Emit a store of each element to the stack slot.
5551 SmallVector<SDValue, 8> Stores;
5552 unsigned TypeByteSize = Node->getOperand(0).getValueType().getSizeInBits()/8;
5553 // Store (in the right endianness) the elements to memory.
5554 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
5555 // Ignore undef elements.
5556 if (Node->getOperand(i).getOpcode() == ISD::UNDEF) continue;
5558 unsigned Offset = TypeByteSize*i;
5560 SDValue Idx = DAG.getConstant(Offset, FIPtr.getValueType());
5561 Idx = DAG.getNode(ISD::ADD, FIPtr.getValueType(), FIPtr, Idx);
5563 Stores.push_back(DAG.getStore(DAG.getEntryNode(), Node->getOperand(i), Idx,
5568 if (!Stores.empty()) // Not all undef elements?
5569 StoreChain = DAG.getNode(ISD::TokenFactor, MVT::Other,
5570 &Stores[0], Stores.size());
5572 StoreChain = DAG.getEntryNode();
5574 // Result is a load from the stack slot.
5575 return DAG.getLoad(VT, StoreChain, FIPtr, NULL, 0);
5578 void SelectionDAGLegalize::ExpandShiftParts(unsigned NodeOp,
5579 SDValue Op, SDValue Amt,
5580 SDValue &Lo, SDValue &Hi) {
5581 // Expand the subcomponents.
5583 ExpandOp(Op, LHSL, LHSH);
5585 SDValue Ops[] = { LHSL, LHSH, Amt };
5586 MVT VT = LHSL.getValueType();
5587 Lo = DAG.getNode(NodeOp, DAG.getNodeValueTypes(VT, VT), 2, Ops, 3);
5588 Hi = Lo.getValue(1);
5592 /// ExpandShift - Try to find a clever way to expand this shift operation out to
5593 /// smaller elements. If we can't find a way that is more efficient than a
5594 /// libcall on this target, return false. Otherwise, return true with the
5595 /// low-parts expanded into Lo and Hi.
5596 bool SelectionDAGLegalize::ExpandShift(unsigned Opc, SDValue Op,SDValue Amt,
5597 SDValue &Lo, SDValue &Hi) {
5598 assert((Opc == ISD::SHL || Opc == ISD::SRA || Opc == ISD::SRL) &&
5599 "This is not a shift!");
5601 MVT NVT = TLI.getTypeToTransformTo(Op.getValueType());
5602 SDValue ShAmt = LegalizeOp(Amt);
5603 MVT ShTy = ShAmt.getValueType();
5604 unsigned ShBits = ShTy.getSizeInBits();
5605 unsigned VTBits = Op.getValueType().getSizeInBits();
5606 unsigned NVTBits = NVT.getSizeInBits();
5608 // Handle the case when Amt is an immediate.
5609 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Amt.getNode())) {
5610 unsigned Cst = CN->getZExtValue();
5611 // Expand the incoming operand to be shifted, so that we have its parts
5613 ExpandOp(Op, InL, InH);
5617 Lo = DAG.getConstant(0, NVT);
5618 Hi = DAG.getConstant(0, NVT);
5619 } else if (Cst > NVTBits) {
5620 Lo = DAG.getConstant(0, NVT);
5621 Hi = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Cst-NVTBits,ShTy));
5622 } else if (Cst == NVTBits) {
5623 Lo = DAG.getConstant(0, NVT);
5626 Lo = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Cst, ShTy));
5627 Hi = DAG.getNode(ISD::OR, NVT,
5628 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(Cst, ShTy)),
5629 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(NVTBits-Cst, ShTy)));
5634 Lo = DAG.getConstant(0, NVT);
5635 Hi = DAG.getConstant(0, NVT);
5636 } else if (Cst > NVTBits) {
5637 Lo = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Cst-NVTBits,ShTy));
5638 Hi = DAG.getConstant(0, NVT);
5639 } else if (Cst == NVTBits) {
5641 Hi = DAG.getConstant(0, NVT);
5643 Lo = DAG.getNode(ISD::OR, NVT,
5644 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(Cst, ShTy)),
5645 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(NVTBits-Cst, ShTy)));
5646 Hi = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Cst, ShTy));
5651 Hi = Lo = DAG.getNode(ISD::SRA, NVT, InH,
5652 DAG.getConstant(NVTBits-1, ShTy));
5653 } else if (Cst > NVTBits) {
5654 Lo = DAG.getNode(ISD::SRA, NVT, InH,
5655 DAG.getConstant(Cst-NVTBits, ShTy));
5656 Hi = DAG.getNode(ISD::SRA, NVT, InH,
5657 DAG.getConstant(NVTBits-1, ShTy));
5658 } else if (Cst == NVTBits) {
5660 Hi = DAG.getNode(ISD::SRA, NVT, InH,
5661 DAG.getConstant(NVTBits-1, ShTy));
5663 Lo = DAG.getNode(ISD::OR, NVT,
5664 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(Cst, ShTy)),
5665 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(NVTBits-Cst, ShTy)));
5666 Hi = DAG.getNode(ISD::SRA, NVT, InH, DAG.getConstant(Cst, ShTy));
5672 // Okay, the shift amount isn't constant. However, if we can tell that it is
5673 // >= 32 or < 32, we can still simplify it, without knowing the actual value.
5674 APInt Mask = APInt::getHighBitsSet(ShBits, ShBits - Log2_32(NVTBits));
5675 APInt KnownZero, KnownOne;
5676 DAG.ComputeMaskedBits(Amt, Mask, KnownZero, KnownOne);
5678 // If we know that if any of the high bits of the shift amount are one, then
5679 // we can do this as a couple of simple shifts.
5680 if (KnownOne.intersects(Mask)) {
5681 // Mask out the high bit, which we know is set.
5682 Amt = DAG.getNode(ISD::AND, Amt.getValueType(), Amt,
5683 DAG.getConstant(~Mask, Amt.getValueType()));
5685 // Expand the incoming operand to be shifted, so that we have its parts
5687 ExpandOp(Op, InL, InH);
5690 Lo = DAG.getConstant(0, NVT); // Low part is zero.
5691 Hi = DAG.getNode(ISD::SHL, NVT, InL, Amt); // High part from Lo part.
5694 Hi = DAG.getConstant(0, NVT); // Hi part is zero.
5695 Lo = DAG.getNode(ISD::SRL, NVT, InH, Amt); // Lo part from Hi part.
5698 Hi = DAG.getNode(ISD::SRA, NVT, InH, // Sign extend high part.
5699 DAG.getConstant(NVTBits-1, Amt.getValueType()));
5700 Lo = DAG.getNode(ISD::SRA, NVT, InH, Amt); // Lo part from Hi part.
5705 // If we know that the high bits of the shift amount are all zero, then we can
5706 // do this as a couple of simple shifts.
5707 if ((KnownZero & Mask) == Mask) {
5709 SDValue Amt2 = DAG.getNode(ISD::SUB, Amt.getValueType(),
5710 DAG.getConstant(NVTBits, Amt.getValueType()),
5713 // Expand the incoming operand to be shifted, so that we have its parts
5715 ExpandOp(Op, InL, InH);
5718 Lo = DAG.getNode(ISD::SHL, NVT, InL, Amt);
5719 Hi = DAG.getNode(ISD::OR, NVT,
5720 DAG.getNode(ISD::SHL, NVT, InH, Amt),
5721 DAG.getNode(ISD::SRL, NVT, InL, Amt2));
5724 Hi = DAG.getNode(ISD::SRL, NVT, InH, Amt);
5725 Lo = DAG.getNode(ISD::OR, NVT,
5726 DAG.getNode(ISD::SRL, NVT, InL, Amt),
5727 DAG.getNode(ISD::SHL, NVT, InH, Amt2));
5730 Hi = DAG.getNode(ISD::SRA, NVT, InH, Amt);
5731 Lo = DAG.getNode(ISD::OR, NVT,
5732 DAG.getNode(ISD::SRL, NVT, InL, Amt),
5733 DAG.getNode(ISD::SHL, NVT, InH, Amt2));
5742 // ExpandLibCall - Expand a node into a call to a libcall. If the result value
5743 // does not fit into a register, return the lo part and set the hi part to the
5744 // by-reg argument. If it does fit into a single register, return the result
5745 // and leave the Hi part unset.
5746 SDValue SelectionDAGLegalize::ExpandLibCall(RTLIB::Libcall LC, SDNode *Node,
5747 bool isSigned, SDValue &Hi) {
5748 assert(!IsLegalizingCall && "Cannot overlap legalization of calls!");
5749 // The input chain to this libcall is the entry node of the function.
5750 // Legalizing the call will automatically add the previous call to the
5752 SDValue InChain = DAG.getEntryNode();
5754 TargetLowering::ArgListTy Args;
5755 TargetLowering::ArgListEntry Entry;
5756 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
5757 MVT ArgVT = Node->getOperand(i).getValueType();
5758 const Type *ArgTy = ArgVT.getTypeForMVT();
5759 Entry.Node = Node->getOperand(i); Entry.Ty = ArgTy;
5760 Entry.isSExt = isSigned;
5761 Entry.isZExt = !isSigned;
5762 Args.push_back(Entry);
5764 SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC),
5765 TLI.getPointerTy());
5767 // Splice the libcall in wherever FindInputOutputChains tells us to.
5768 const Type *RetTy = Node->getValueType(0).getTypeForMVT();
5769 std::pair<SDValue,SDValue> CallInfo =
5770 TLI.LowerCallTo(InChain, RetTy, isSigned, !isSigned, false, false,
5771 CallingConv::C, false, Callee, Args, DAG);
5773 // Legalize the call sequence, starting with the chain. This will advance
5774 // the LastCALLSEQ_END to the legalized version of the CALLSEQ_END node that
5775 // was added by LowerCallTo (guaranteeing proper serialization of calls).
5776 LegalizeOp(CallInfo.second);
5778 switch (getTypeAction(CallInfo.first.getValueType())) {
5779 default: assert(0 && "Unknown thing");
5781 Result = CallInfo.first;
5784 ExpandOp(CallInfo.first, Result, Hi);
5790 /// LegalizeINT_TO_FP - Legalize a [US]INT_TO_FP operation.
5792 SDValue SelectionDAGLegalize::
5793 LegalizeINT_TO_FP(SDValue Result, bool isSigned, MVT DestTy, SDValue Op) {
5794 bool isCustom = false;
5796 switch (getTypeAction(Op.getValueType())) {
5798 switch (TLI.getOperationAction(isSigned ? ISD::SINT_TO_FP : ISD::UINT_TO_FP,
5799 Op.getValueType())) {
5800 default: assert(0 && "Unknown operation action!");
5801 case TargetLowering::Custom:
5804 case TargetLowering::Legal:
5805 Tmp1 = LegalizeOp(Op);
5806 if (Result.getNode())
5807 Result = DAG.UpdateNodeOperands(Result, Tmp1);
5809 Result = DAG.getNode(isSigned ? ISD::SINT_TO_FP : ISD::UINT_TO_FP,
5812 Tmp1 = TLI.LowerOperation(Result, DAG);
5813 if (Tmp1.getNode()) Result = Tmp1;
5816 case TargetLowering::Expand:
5817 Result = ExpandLegalINT_TO_FP(isSigned, LegalizeOp(Op), DestTy);
5819 case TargetLowering::Promote:
5820 Result = PromoteLegalINT_TO_FP(LegalizeOp(Op), DestTy, isSigned);
5825 Result = ExpandIntToFP(isSigned, DestTy, Op);
5828 Tmp1 = PromoteOp(Op);
5830 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, Tmp1.getValueType(),
5831 Tmp1, DAG.getValueType(Op.getValueType()));
5833 Tmp1 = DAG.getZeroExtendInReg(Tmp1,
5836 if (Result.getNode())
5837 Result = DAG.UpdateNodeOperands(Result, Tmp1);
5839 Result = DAG.getNode(isSigned ? ISD::SINT_TO_FP : ISD::UINT_TO_FP,
5841 Result = LegalizeOp(Result); // The 'op' is not necessarily legal!
5847 /// ExpandIntToFP - Expand a [US]INT_TO_FP operation.
5849 SDValue SelectionDAGLegalize::
5850 ExpandIntToFP(bool isSigned, MVT DestTy, SDValue Source) {
5851 MVT SourceVT = Source.getValueType();
5852 bool ExpandSource = getTypeAction(SourceVT) == Expand;
5854 // Expand unsupported int-to-fp vector casts by unrolling them.
5855 if (DestTy.isVector()) {
5857 return LegalizeOp(UnrollVectorOp(Source));
5858 MVT DestEltTy = DestTy.getVectorElementType();
5859 if (DestTy.getVectorNumElements() == 1) {
5860 SDValue Scalar = ScalarizeVectorOp(Source);
5861 SDValue Result = LegalizeINT_TO_FP(SDValue(), isSigned,
5863 return DAG.getNode(ISD::BUILD_VECTOR, DestTy, Result);
5866 SplitVectorOp(Source, Lo, Hi);
5867 MVT SplitDestTy = MVT::getVectorVT(DestEltTy,
5868 DestTy.getVectorNumElements() / 2);
5869 SDValue LoResult = LegalizeINT_TO_FP(SDValue(), isSigned, SplitDestTy, Lo);
5870 SDValue HiResult = LegalizeINT_TO_FP(SDValue(), isSigned, SplitDestTy, Hi);
5871 return LegalizeOp(DAG.getNode(ISD::CONCAT_VECTORS, DestTy, LoResult,
5875 // Special case for i32 source to take advantage of UINTTOFP_I32_F32, etc.
5876 if (!isSigned && SourceVT != MVT::i32) {
5877 // The integer value loaded will be incorrectly if the 'sign bit' of the
5878 // incoming integer is set. To handle this, we dynamically test to see if
5879 // it is set, and, if so, add a fudge factor.
5883 ExpandOp(Source, Lo, Hi);
5884 Source = DAG.getNode(ISD::BUILD_PAIR, SourceVT, Lo, Hi);
5886 // The comparison for the sign bit will use the entire operand.
5890 // Check to see if the target has a custom way to lower this. If so, use
5891 // it. (Note we've already expanded the operand in this case.)
5892 switch (TLI.getOperationAction(ISD::UINT_TO_FP, SourceVT)) {
5893 default: assert(0 && "This action not implemented for this operation!");
5894 case TargetLowering::Legal:
5895 case TargetLowering::Expand:
5896 break; // This case is handled below.
5897 case TargetLowering::Custom: {
5898 SDValue NV = TLI.LowerOperation(DAG.getNode(ISD::UINT_TO_FP, DestTy,
5901 return LegalizeOp(NV);
5902 break; // The target decided this was legal after all
5906 // If this is unsigned, and not supported, first perform the conversion to
5907 // signed, then adjust the result if the sign bit is set.
5908 SDValue SignedConv = ExpandIntToFP(true, DestTy, Source);
5910 SDValue SignSet = DAG.getSetCC(TLI.getSetCCResultType(Hi), Hi,
5911 DAG.getConstant(0, Hi.getValueType()),
5913 SDValue Zero = DAG.getIntPtrConstant(0), Four = DAG.getIntPtrConstant(4);
5914 SDValue CstOffset = DAG.getNode(ISD::SELECT, Zero.getValueType(),
5915 SignSet, Four, Zero);
5916 uint64_t FF = 0x5f800000ULL;
5917 if (TLI.isLittleEndian()) FF <<= 32;
5918 static Constant *FudgeFactor = ConstantInt::get(Type::Int64Ty, FF);
5920 SDValue CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy());
5921 unsigned Alignment = 1 << cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
5922 CPIdx = DAG.getNode(ISD::ADD, TLI.getPointerTy(), CPIdx, CstOffset);
5923 Alignment = std::min(Alignment, 4u);
5925 if (DestTy == MVT::f32)
5926 FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx,
5927 PseudoSourceValue::getConstantPool(), 0,
5929 else if (DestTy.bitsGT(MVT::f32))
5930 // FIXME: Avoid the extend by construction the right constantpool?
5931 FudgeInReg = DAG.getExtLoad(ISD::EXTLOAD, DestTy, DAG.getEntryNode(),
5933 PseudoSourceValue::getConstantPool(), 0,
5934 MVT::f32, false, Alignment);
5936 assert(0 && "Unexpected conversion");
5938 MVT SCVT = SignedConv.getValueType();
5939 if (SCVT != DestTy) {
5940 // Destination type needs to be expanded as well. The FADD now we are
5941 // constructing will be expanded into a libcall.
5942 if (SCVT.getSizeInBits() != DestTy.getSizeInBits()) {
5943 assert(SCVT.getSizeInBits() * 2 == DestTy.getSizeInBits());
5944 SignedConv = DAG.getNode(ISD::BUILD_PAIR, DestTy,
5945 SignedConv, SignedConv.getValue(1));
5947 SignedConv = DAG.getNode(ISD::BIT_CONVERT, DestTy, SignedConv);
5949 return DAG.getNode(ISD::FADD, DestTy, SignedConv, FudgeInReg);
5952 // Check to see if the target has a custom way to lower this. If so, use it.
5953 switch (TLI.getOperationAction(ISD::SINT_TO_FP, SourceVT)) {
5954 default: assert(0 && "This action not implemented for this operation!");
5955 case TargetLowering::Legal:
5956 case TargetLowering::Expand:
5957 break; // This case is handled below.
5958 case TargetLowering::Custom: {
5959 SDValue NV = TLI.LowerOperation(DAG.getNode(ISD::SINT_TO_FP, DestTy,
5962 return LegalizeOp(NV);
5963 break; // The target decided this was legal after all
5967 // Expand the source, then glue it back together for the call. We must expand
5968 // the source in case it is shared (this pass of legalize must traverse it).
5970 SDValue SrcLo, SrcHi;
5971 ExpandOp(Source, SrcLo, SrcHi);
5972 Source = DAG.getNode(ISD::BUILD_PAIR, SourceVT, SrcLo, SrcHi);
5975 RTLIB::Libcall LC = isSigned ?
5976 RTLIB::getSINTTOFP(SourceVT, DestTy) :
5977 RTLIB::getUINTTOFP(SourceVT, DestTy);
5978 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unknown int value type");
5980 Source = DAG.getNode(ISD::SINT_TO_FP, DestTy, Source);
5982 SDValue Result = ExpandLibCall(LC, Source.getNode(), isSigned, HiPart);
5983 if (Result.getValueType() != DestTy && HiPart.getNode())
5984 Result = DAG.getNode(ISD::BUILD_PAIR, DestTy, Result, HiPart);
5988 /// ExpandLegalINT_TO_FP - This function is responsible for legalizing a
5989 /// INT_TO_FP operation of the specified operand when the target requests that
5990 /// we expand it. At this point, we know that the result and operand types are
5991 /// legal for the target.
5992 SDValue SelectionDAGLegalize::ExpandLegalINT_TO_FP(bool isSigned,
5995 if (Op0.getValueType() == MVT::i32) {
5996 // simple 32-bit [signed|unsigned] integer to float/double expansion
5998 // Get the stack frame index of a 8 byte buffer.
5999 SDValue StackSlot = DAG.CreateStackTemporary(MVT::f64);
6001 // word offset constant for Hi/Lo address computation
6002 SDValue WordOff = DAG.getConstant(sizeof(int), TLI.getPointerTy());
6003 // set up Hi and Lo (into buffer) address based on endian
6004 SDValue Hi = StackSlot;
6005 SDValue Lo = DAG.getNode(ISD::ADD, TLI.getPointerTy(), StackSlot,WordOff);
6006 if (TLI.isLittleEndian())
6009 // if signed map to unsigned space
6012 // constant used to invert sign bit (signed to unsigned mapping)
6013 SDValue SignBit = DAG.getConstant(0x80000000u, MVT::i32);
6014 Op0Mapped = DAG.getNode(ISD::XOR, MVT::i32, Op0, SignBit);
6018 // store the lo of the constructed double - based on integer input
6019 SDValue Store1 = DAG.getStore(DAG.getEntryNode(),
6020 Op0Mapped, Lo, NULL, 0);
6021 // initial hi portion of constructed double
6022 SDValue InitialHi = DAG.getConstant(0x43300000u, MVT::i32);
6023 // store the hi of the constructed double - biased exponent
6024 SDValue Store2=DAG.getStore(Store1, InitialHi, Hi, NULL, 0);
6025 // load the constructed double
6026 SDValue Load = DAG.getLoad(MVT::f64, Store2, StackSlot, NULL, 0);
6027 // FP constant to bias correct the final result
6028 SDValue Bias = DAG.getConstantFP(isSigned ?
6029 BitsToDouble(0x4330000080000000ULL)
6030 : BitsToDouble(0x4330000000000000ULL),
6032 // subtract the bias
6033 SDValue Sub = DAG.getNode(ISD::FSUB, MVT::f64, Load, Bias);
6036 // handle final rounding
6037 if (DestVT == MVT::f64) {
6040 } else if (DestVT.bitsLT(MVT::f64)) {
6041 Result = DAG.getNode(ISD::FP_ROUND, DestVT, Sub,
6042 DAG.getIntPtrConstant(0));
6043 } else if (DestVT.bitsGT(MVT::f64)) {
6044 Result = DAG.getNode(ISD::FP_EXTEND, DestVT, Sub);
6048 assert(!isSigned && "Legalize cannot Expand SINT_TO_FP for i64 yet");
6049 SDValue Tmp1 = DAG.getNode(ISD::SINT_TO_FP, DestVT, Op0);
6051 SDValue SignSet = DAG.getSetCC(TLI.getSetCCResultType(Op0), Op0,
6052 DAG.getConstant(0, Op0.getValueType()),
6054 SDValue Zero = DAG.getIntPtrConstant(0), Four = DAG.getIntPtrConstant(4);
6055 SDValue CstOffset = DAG.getNode(ISD::SELECT, Zero.getValueType(),
6056 SignSet, Four, Zero);
6058 // If the sign bit of the integer is set, the large number will be treated
6059 // as a negative number. To counteract this, the dynamic code adds an
6060 // offset depending on the data type.
6062 switch (Op0.getValueType().getSimpleVT()) {
6063 default: assert(0 && "Unsupported integer type!");
6064 case MVT::i8 : FF = 0x43800000ULL; break; // 2^8 (as a float)
6065 case MVT::i16: FF = 0x47800000ULL; break; // 2^16 (as a float)
6066 case MVT::i32: FF = 0x4F800000ULL; break; // 2^32 (as a float)
6067 case MVT::i64: FF = 0x5F800000ULL; break; // 2^64 (as a float)
6069 if (TLI.isLittleEndian()) FF <<= 32;
6070 static Constant *FudgeFactor = ConstantInt::get(Type::Int64Ty, FF);
6072 SDValue CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy());
6073 unsigned Alignment = 1 << cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
6074 CPIdx = DAG.getNode(ISD::ADD, TLI.getPointerTy(), CPIdx, CstOffset);
6075 Alignment = std::min(Alignment, 4u);
6077 if (DestVT == MVT::f32)
6078 FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx,
6079 PseudoSourceValue::getConstantPool(), 0,
6083 LegalizeOp(DAG.getExtLoad(ISD::EXTLOAD, DestVT,
6084 DAG.getEntryNode(), CPIdx,
6085 PseudoSourceValue::getConstantPool(), 0,
6086 MVT::f32, false, Alignment));
6089 return DAG.getNode(ISD::FADD, DestVT, Tmp1, FudgeInReg);
6092 /// PromoteLegalINT_TO_FP - This function is responsible for legalizing a
6093 /// *INT_TO_FP operation of the specified operand when the target requests that
6094 /// we promote it. At this point, we know that the result and operand types are
6095 /// legal for the target, and that there is a legal UINT_TO_FP or SINT_TO_FP
6096 /// operation that takes a larger input.
6097 SDValue SelectionDAGLegalize::PromoteLegalINT_TO_FP(SDValue LegalOp,
6100 // First step, figure out the appropriate *INT_TO_FP operation to use.
6101 MVT NewInTy = LegalOp.getValueType();
6103 unsigned OpToUse = 0;
6105 // Scan for the appropriate larger type to use.
6107 NewInTy = (MVT::SimpleValueType)(NewInTy.getSimpleVT()+1);
6108 assert(NewInTy.isInteger() && "Ran out of possibilities!");
6110 // If the target supports SINT_TO_FP of this type, use it.
6111 switch (TLI.getOperationAction(ISD::SINT_TO_FP, NewInTy)) {
6113 case TargetLowering::Legal:
6114 if (!TLI.isTypeLegal(NewInTy))
6115 break; // Can't use this datatype.
6117 case TargetLowering::Custom:
6118 OpToUse = ISD::SINT_TO_FP;
6122 if (isSigned) continue;
6124 // If the target supports UINT_TO_FP of this type, use it.
6125 switch (TLI.getOperationAction(ISD::UINT_TO_FP, NewInTy)) {
6127 case TargetLowering::Legal:
6128 if (!TLI.isTypeLegal(NewInTy))
6129 break; // Can't use this datatype.
6131 case TargetLowering::Custom:
6132 OpToUse = ISD::UINT_TO_FP;
6137 // Otherwise, try a larger type.
6140 // Okay, we found the operation and type to use. Zero extend our input to the
6141 // desired type then run the operation on it.
6142 return DAG.getNode(OpToUse, DestVT,
6143 DAG.getNode(isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND,
6147 /// PromoteLegalFP_TO_INT - This function is responsible for legalizing a
6148 /// FP_TO_*INT operation of the specified operand when the target requests that
6149 /// we promote it. At this point, we know that the result and operand types are
6150 /// legal for the target, and that there is a legal FP_TO_UINT or FP_TO_SINT
6151 /// operation that returns a larger result.
6152 SDValue SelectionDAGLegalize::PromoteLegalFP_TO_INT(SDValue LegalOp,
6155 // First step, figure out the appropriate FP_TO*INT operation to use.
6156 MVT NewOutTy = DestVT;
6158 unsigned OpToUse = 0;
6160 // Scan for the appropriate larger type to use.
6162 NewOutTy = (MVT::SimpleValueType)(NewOutTy.getSimpleVT()+1);
6163 assert(NewOutTy.isInteger() && "Ran out of possibilities!");
6165 // If the target supports FP_TO_SINT returning this type, use it.
6166 switch (TLI.getOperationAction(ISD::FP_TO_SINT, NewOutTy)) {
6168 case TargetLowering::Legal:
6169 if (!TLI.isTypeLegal(NewOutTy))
6170 break; // Can't use this datatype.
6172 case TargetLowering::Custom:
6173 OpToUse = ISD::FP_TO_SINT;
6178 // If the target supports FP_TO_UINT of this type, use it.
6179 switch (TLI.getOperationAction(ISD::FP_TO_UINT, NewOutTy)) {
6181 case TargetLowering::Legal:
6182 if (!TLI.isTypeLegal(NewOutTy))
6183 break; // Can't use this datatype.
6185 case TargetLowering::Custom:
6186 OpToUse = ISD::FP_TO_UINT;
6191 // Otherwise, try a larger type.
6195 // Okay, we found the operation and type to use.
6196 SDValue Operation = DAG.getNode(OpToUse, NewOutTy, LegalOp);
6198 // If the operation produces an invalid type, it must be custom lowered. Use
6199 // the target lowering hooks to expand it. Just keep the low part of the
6200 // expanded operation, we know that we're truncating anyway.
6201 if (getTypeAction(NewOutTy) == Expand) {
6202 SmallVector<SDValue, 2> Results;
6203 TLI.ReplaceNodeResults(Operation.getNode(), Results, DAG);
6204 assert(Results.size() == 1 && "Incorrect FP_TO_XINT lowering!");
6205 Operation = Results[0];
6208 // Truncate the result of the extended FP_TO_*INT operation to the desired
6210 return DAG.getNode(ISD::TRUNCATE, DestVT, Operation);
6213 /// ExpandBSWAP - Open code the operations for BSWAP of the specified operation.
6215 SDValue SelectionDAGLegalize::ExpandBSWAP(SDValue Op) {
6216 MVT VT = Op.getValueType();
6217 MVT SHVT = TLI.getShiftAmountTy();
6218 SDValue Tmp1, Tmp2, Tmp3, Tmp4, Tmp5, Tmp6, Tmp7, Tmp8;
6219 switch (VT.getSimpleVT()) {
6220 default: assert(0 && "Unhandled Expand type in BSWAP!"); abort();
6222 Tmp2 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT));
6223 Tmp1 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(8, SHVT));
6224 return DAG.getNode(ISD::OR, VT, Tmp1, Tmp2);
6226 Tmp4 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(24, SHVT));
6227 Tmp3 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT));
6228 Tmp2 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(8, SHVT));
6229 Tmp1 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(24, SHVT));
6230 Tmp3 = DAG.getNode(ISD::AND, VT, Tmp3, DAG.getConstant(0xFF0000, VT));
6231 Tmp2 = DAG.getNode(ISD::AND, VT, Tmp2, DAG.getConstant(0xFF00, VT));
6232 Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp3);
6233 Tmp2 = DAG.getNode(ISD::OR, VT, Tmp2, Tmp1);
6234 return DAG.getNode(ISD::OR, VT, Tmp4, Tmp2);
6236 Tmp8 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(56, SHVT));
6237 Tmp7 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(40, SHVT));
6238 Tmp6 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(24, SHVT));
6239 Tmp5 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT));
6240 Tmp4 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(8, SHVT));
6241 Tmp3 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(24, SHVT));
6242 Tmp2 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(40, SHVT));
6243 Tmp1 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(56, SHVT));
6244 Tmp7 = DAG.getNode(ISD::AND, VT, Tmp7, DAG.getConstant(255ULL<<48, VT));
6245 Tmp6 = DAG.getNode(ISD::AND, VT, Tmp6, DAG.getConstant(255ULL<<40, VT));
6246 Tmp5 = DAG.getNode(ISD::AND, VT, Tmp5, DAG.getConstant(255ULL<<32, VT));
6247 Tmp4 = DAG.getNode(ISD::AND, VT, Tmp4, DAG.getConstant(255ULL<<24, VT));
6248 Tmp3 = DAG.getNode(ISD::AND, VT, Tmp3, DAG.getConstant(255ULL<<16, VT));
6249 Tmp2 = DAG.getNode(ISD::AND, VT, Tmp2, DAG.getConstant(255ULL<<8 , VT));
6250 Tmp8 = DAG.getNode(ISD::OR, VT, Tmp8, Tmp7);
6251 Tmp6 = DAG.getNode(ISD::OR, VT, Tmp6, Tmp5);
6252 Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp3);
6253 Tmp2 = DAG.getNode(ISD::OR, VT, Tmp2, Tmp1);
6254 Tmp8 = DAG.getNode(ISD::OR, VT, Tmp8, Tmp6);
6255 Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp2);
6256 return DAG.getNode(ISD::OR, VT, Tmp8, Tmp4);
6260 /// ExpandBitCount - Expand the specified bitcount instruction into operations.
6262 SDValue SelectionDAGLegalize::ExpandBitCount(unsigned Opc, SDValue Op) {
6264 default: assert(0 && "Cannot expand this yet!");
6266 static const uint64_t mask[6] = {
6267 0x5555555555555555ULL, 0x3333333333333333ULL,
6268 0x0F0F0F0F0F0F0F0FULL, 0x00FF00FF00FF00FFULL,
6269 0x0000FFFF0000FFFFULL, 0x00000000FFFFFFFFULL
6271 MVT VT = Op.getValueType();
6272 MVT ShVT = TLI.getShiftAmountTy();
6273 unsigned len = VT.getSizeInBits();
6274 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) {
6275 //x = (x & mask[i][len/8]) + (x >> (1 << i) & mask[i][len/8])
6276 SDValue Tmp2 = DAG.getConstant(mask[i], VT);
6277 SDValue Tmp3 = DAG.getConstant(1ULL << i, ShVT);
6278 Op = DAG.getNode(ISD::ADD, VT, DAG.getNode(ISD::AND, VT, Op, Tmp2),
6279 DAG.getNode(ISD::AND, VT,
6280 DAG.getNode(ISD::SRL, VT, Op, Tmp3),Tmp2));
6285 // for now, we do this:
6286 // x = x | (x >> 1);
6287 // x = x | (x >> 2);
6289 // x = x | (x >>16);
6290 // x = x | (x >>32); // for 64-bit input
6291 // return popcount(~x);
6293 // but see also: http://www.hackersdelight.org/HDcode/nlz.cc
6294 MVT VT = Op.getValueType();
6295 MVT ShVT = TLI.getShiftAmountTy();
6296 unsigned len = VT.getSizeInBits();
6297 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) {
6298 SDValue Tmp3 = DAG.getConstant(1ULL << i, ShVT);
6299 Op = DAG.getNode(ISD::OR, VT, Op, DAG.getNode(ISD::SRL, VT, Op, Tmp3));
6301 Op = DAG.getNode(ISD::XOR, VT, Op, DAG.getConstant(~0ULL, VT));
6302 return DAG.getNode(ISD::CTPOP, VT, Op);
6305 // for now, we use: { return popcount(~x & (x - 1)); }
6306 // unless the target has ctlz but not ctpop, in which case we use:
6307 // { return 32 - nlz(~x & (x-1)); }
6308 // see also http://www.hackersdelight.org/HDcode/ntz.cc
6309 MVT VT = Op.getValueType();
6310 SDValue Tmp2 = DAG.getConstant(~0ULL, VT);
6311 SDValue Tmp3 = DAG.getNode(ISD::AND, VT,
6312 DAG.getNode(ISD::XOR, VT, Op, Tmp2),
6313 DAG.getNode(ISD::SUB, VT, Op, DAG.getConstant(1, VT)));
6314 // If ISD::CTLZ is legal and CTPOP isn't, then do that instead.
6315 if (!TLI.isOperationLegal(ISD::CTPOP, VT) &&
6316 TLI.isOperationLegal(ISD::CTLZ, VT))
6317 return DAG.getNode(ISD::SUB, VT,
6318 DAG.getConstant(VT.getSizeInBits(), VT),
6319 DAG.getNode(ISD::CTLZ, VT, Tmp3));
6320 return DAG.getNode(ISD::CTPOP, VT, Tmp3);
6325 /// ExpandOp - Expand the specified SDValue into its two component pieces
6326 /// Lo&Hi. Note that the Op MUST be an expanded type. As a result of this, the
6327 /// LegalizedNodes map is filled in for any results that are not expanded, the
6328 /// ExpandedNodes map is filled in for any results that are expanded, and the
6329 /// Lo/Hi values are returned.
6330 void SelectionDAGLegalize::ExpandOp(SDValue Op, SDValue &Lo, SDValue &Hi){
6331 MVT VT = Op.getValueType();
6332 MVT NVT = TLI.getTypeToTransformTo(VT);
6333 SDNode *Node = Op.getNode();
6334 assert(getTypeAction(VT) == Expand && "Not an expanded type!");
6335 assert(((NVT.isInteger() && NVT.bitsLT(VT)) || VT.isFloatingPoint() ||
6336 VT.isVector()) && "Cannot expand to FP value or to larger int value!");
6338 // See if we already expanded it.
6339 DenseMap<SDValue, std::pair<SDValue, SDValue> >::iterator I
6340 = ExpandedNodes.find(Op);
6341 if (I != ExpandedNodes.end()) {
6342 Lo = I->second.first;
6343 Hi = I->second.second;
6347 switch (Node->getOpcode()) {
6348 case ISD::CopyFromReg:
6349 assert(0 && "CopyFromReg must be legal!");
6350 case ISD::FP_ROUND_INREG:
6351 if (VT == MVT::ppcf128 &&
6352 TLI.getOperationAction(ISD::FP_ROUND_INREG, VT) ==
6353 TargetLowering::Custom) {
6354 SDValue SrcLo, SrcHi, Src;
6355 ExpandOp(Op.getOperand(0), SrcLo, SrcHi);
6356 Src = DAG.getNode(ISD::BUILD_PAIR, VT, SrcLo, SrcHi);
6357 SDValue Result = TLI.LowerOperation(
6358 DAG.getNode(ISD::FP_ROUND_INREG, VT, Src, Op.getOperand(1)), DAG);
6359 assert(Result.getNode()->getOpcode() == ISD::BUILD_PAIR);
6360 Lo = Result.getNode()->getOperand(0);
6361 Hi = Result.getNode()->getOperand(1);
6367 cerr << "NODE: "; Node->dump(&DAG); cerr << "\n";
6369 assert(0 && "Do not know how to expand this operator!");
6371 case ISD::EXTRACT_ELEMENT:
6372 ExpandOp(Node->getOperand(0), Lo, Hi);
6373 if (cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue())
6374 return ExpandOp(Hi, Lo, Hi);
6375 return ExpandOp(Lo, Lo, Hi);
6376 case ISD::EXTRACT_VECTOR_ELT:
6377 // ExpandEXTRACT_VECTOR_ELT tolerates invalid result types.
6378 Lo = ExpandEXTRACT_VECTOR_ELT(Op);
6379 return ExpandOp(Lo, Lo, Hi);
6381 Lo = DAG.getNode(ISD::UNDEF, NVT);
6382 Hi = DAG.getNode(ISD::UNDEF, NVT);
6384 case ISD::Constant: {
6385 unsigned NVTBits = NVT.getSizeInBits();
6386 const APInt &Cst = cast<ConstantSDNode>(Node)->getAPIntValue();
6387 Lo = DAG.getConstant(APInt(Cst).trunc(NVTBits), NVT);
6388 Hi = DAG.getConstant(Cst.lshr(NVTBits).trunc(NVTBits), NVT);
6391 case ISD::ConstantFP: {
6392 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node);
6393 if (CFP->getValueType(0) == MVT::ppcf128) {
6394 APInt api = CFP->getValueAPF().bitcastToAPInt();
6395 Lo = DAG.getConstantFP(APFloat(APInt(64, 1, &api.getRawData()[1])),
6397 Hi = DAG.getConstantFP(APFloat(APInt(64, 1, &api.getRawData()[0])),
6401 Lo = ExpandConstantFP(CFP, false, DAG, TLI);
6402 if (getTypeAction(Lo.getValueType()) == Expand)
6403 ExpandOp(Lo, Lo, Hi);
6406 case ISD::BUILD_PAIR:
6407 // Return the operands.
6408 Lo = Node->getOperand(0);
6409 Hi = Node->getOperand(1);
6412 case ISD::MERGE_VALUES:
6413 if (Node->getNumValues() == 1) {
6414 ExpandOp(Op.getOperand(0), Lo, Hi);
6417 // FIXME: For now only expand i64,chain = MERGE_VALUES (x, y)
6418 assert(Op.getResNo() == 0 && Node->getNumValues() == 2 &&
6419 Op.getValue(1).getValueType() == MVT::Other &&
6420 "unhandled MERGE_VALUES");
6421 ExpandOp(Op.getOperand(0), Lo, Hi);
6422 // Remember that we legalized the chain.
6423 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Op.getOperand(1)));
6426 case ISD::SIGN_EXTEND_INREG:
6427 ExpandOp(Node->getOperand(0), Lo, Hi);
6428 // sext_inreg the low part if needed.
6429 Lo = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Lo, Node->getOperand(1));
6431 // The high part gets the sign extension from the lo-part. This handles
6432 // things like sextinreg V:i64 from i8.
6433 Hi = DAG.getNode(ISD::SRA, NVT, Lo,
6434 DAG.getConstant(NVT.getSizeInBits()-1,
6435 TLI.getShiftAmountTy()));
6439 ExpandOp(Node->getOperand(0), Lo, Hi);
6440 SDValue TempLo = DAG.getNode(ISD::BSWAP, NVT, Hi);
6441 Hi = DAG.getNode(ISD::BSWAP, NVT, Lo);
6447 ExpandOp(Node->getOperand(0), Lo, Hi);
6448 Lo = DAG.getNode(ISD::ADD, NVT, // ctpop(HL) -> ctpop(H)+ctpop(L)
6449 DAG.getNode(ISD::CTPOP, NVT, Lo),
6450 DAG.getNode(ISD::CTPOP, NVT, Hi));
6451 Hi = DAG.getConstant(0, NVT);
6455 // ctlz (HL) -> ctlz(H) != 32 ? ctlz(H) : (ctlz(L)+32)
6456 ExpandOp(Node->getOperand(0), Lo, Hi);
6457 SDValue BitsC = DAG.getConstant(NVT.getSizeInBits(), NVT);
6458 SDValue HLZ = DAG.getNode(ISD::CTLZ, NVT, Hi);
6459 SDValue TopNotZero = DAG.getSetCC(TLI.getSetCCResultType(HLZ), HLZ, BitsC,
6461 SDValue LowPart = DAG.getNode(ISD::CTLZ, NVT, Lo);
6462 LowPart = DAG.getNode(ISD::ADD, NVT, LowPart, BitsC);
6464 Lo = DAG.getNode(ISD::SELECT, NVT, TopNotZero, HLZ, LowPart);
6465 Hi = DAG.getConstant(0, NVT);
6470 // cttz (HL) -> cttz(L) != 32 ? cttz(L) : (cttz(H)+32)
6471 ExpandOp(Node->getOperand(0), Lo, Hi);
6472 SDValue BitsC = DAG.getConstant(NVT.getSizeInBits(), NVT);
6473 SDValue LTZ = DAG.getNode(ISD::CTTZ, NVT, Lo);
6474 SDValue BotNotZero = DAG.getSetCC(TLI.getSetCCResultType(LTZ), LTZ, BitsC,
6476 SDValue HiPart = DAG.getNode(ISD::CTTZ, NVT, Hi);
6477 HiPart = DAG.getNode(ISD::ADD, NVT, HiPart, BitsC);
6479 Lo = DAG.getNode(ISD::SELECT, NVT, BotNotZero, LTZ, HiPart);
6480 Hi = DAG.getConstant(0, NVT);
6485 SDValue Ch = Node->getOperand(0); // Legalize the chain.
6486 SDValue Ptr = Node->getOperand(1); // Legalize the pointer.
6487 Lo = DAG.getVAArg(NVT, Ch, Ptr, Node->getOperand(2));
6488 Hi = DAG.getVAArg(NVT, Lo.getValue(1), Ptr, Node->getOperand(2));
6490 // Remember that we legalized the chain.
6491 Hi = LegalizeOp(Hi);
6492 AddLegalizedOperand(Op.getValue(1), Hi.getValue(1));
6493 if (TLI.isBigEndian())
6499 LoadSDNode *LD = cast<LoadSDNode>(Node);
6500 SDValue Ch = LD->getChain(); // Legalize the chain.
6501 SDValue Ptr = LD->getBasePtr(); // Legalize the pointer.
6502 ISD::LoadExtType ExtType = LD->getExtensionType();
6503 const Value *SV = LD->getSrcValue();
6504 int SVOffset = LD->getSrcValueOffset();
6505 unsigned Alignment = LD->getAlignment();
6506 bool isVolatile = LD->isVolatile();
6508 if (ExtType == ISD::NON_EXTLOAD) {
6509 Lo = DAG.getLoad(NVT, Ch, Ptr, SV, SVOffset,
6510 isVolatile, Alignment);
6511 if (VT == MVT::f32 || VT == MVT::f64) {
6512 // f32->i32 or f64->i64 one to one expansion.
6513 // Remember that we legalized the chain.
6514 AddLegalizedOperand(SDValue(Node, 1), LegalizeOp(Lo.getValue(1)));
6515 // Recursively expand the new load.
6516 if (getTypeAction(NVT) == Expand)
6517 ExpandOp(Lo, Lo, Hi);
6521 // Increment the pointer to the other half.
6522 unsigned IncrementSize = Lo.getValueType().getSizeInBits()/8;
6523 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
6524 DAG.getIntPtrConstant(IncrementSize));
6525 SVOffset += IncrementSize;
6526 Alignment = MinAlign(Alignment, IncrementSize);
6527 Hi = DAG.getLoad(NVT, Ch, Ptr, SV, SVOffset,
6528 isVolatile, Alignment);
6530 // Build a factor node to remember that this load is independent of the
6532 SDValue TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
6535 // Remember that we legalized the chain.
6536 AddLegalizedOperand(Op.getValue(1), LegalizeOp(TF));
6537 if (TLI.isBigEndian())
6540 MVT EVT = LD->getMemoryVT();
6542 if ((VT == MVT::f64 && EVT == MVT::f32) ||
6543 (VT == MVT::ppcf128 && (EVT==MVT::f64 || EVT==MVT::f32))) {
6544 // f64 = EXTLOAD f32 should expand to LOAD, FP_EXTEND
6545 SDValue Load = DAG.getLoad(EVT, Ch, Ptr, SV,
6546 SVOffset, isVolatile, Alignment);
6547 // Remember that we legalized the chain.
6548 AddLegalizedOperand(SDValue(Node, 1), LegalizeOp(Load.getValue(1)));
6549 ExpandOp(DAG.getNode(ISD::FP_EXTEND, VT, Load), Lo, Hi);
6554 Lo = DAG.getLoad(NVT, Ch, Ptr, SV,
6555 SVOffset, isVolatile, Alignment);
6557 Lo = DAG.getExtLoad(ExtType, NVT, Ch, Ptr, SV,
6558 SVOffset, EVT, isVolatile,
6561 // Remember that we legalized the chain.
6562 AddLegalizedOperand(SDValue(Node, 1), LegalizeOp(Lo.getValue(1)));
6564 if (ExtType == ISD::SEXTLOAD) {
6565 // The high part is obtained by SRA'ing all but one of the bits of the
6567 unsigned LoSize = Lo.getValueType().getSizeInBits();
6568 Hi = DAG.getNode(ISD::SRA, NVT, Lo,
6569 DAG.getConstant(LoSize-1, TLI.getShiftAmountTy()));
6570 } else if (ExtType == ISD::ZEXTLOAD) {
6571 // The high part is just a zero.
6572 Hi = DAG.getConstant(0, NVT);
6573 } else /* if (ExtType == ISD::EXTLOAD) */ {
6574 // The high part is undefined.
6575 Hi = DAG.getNode(ISD::UNDEF, NVT);
6582 case ISD::XOR: { // Simple logical operators -> two trivial pieces.
6583 SDValue LL, LH, RL, RH;
6584 ExpandOp(Node->getOperand(0), LL, LH);
6585 ExpandOp(Node->getOperand(1), RL, RH);
6586 Lo = DAG.getNode(Node->getOpcode(), NVT, LL, RL);
6587 Hi = DAG.getNode(Node->getOpcode(), NVT, LH, RH);
6591 SDValue LL, LH, RL, RH;
6592 ExpandOp(Node->getOperand(1), LL, LH);
6593 ExpandOp(Node->getOperand(2), RL, RH);
6594 if (getTypeAction(NVT) == Expand)
6595 NVT = TLI.getTypeToExpandTo(NVT);
6596 Lo = DAG.getNode(ISD::SELECT, NVT, Node->getOperand(0), LL, RL);
6598 Hi = DAG.getNode(ISD::SELECT, NVT, Node->getOperand(0), LH, RH);
6601 case ISD::SELECT_CC: {
6602 SDValue TL, TH, FL, FH;
6603 ExpandOp(Node->getOperand(2), TL, TH);
6604 ExpandOp(Node->getOperand(3), FL, FH);
6605 if (getTypeAction(NVT) == Expand)
6606 NVT = TLI.getTypeToExpandTo(NVT);
6607 Lo = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0),
6608 Node->getOperand(1), TL, FL, Node->getOperand(4));
6610 Hi = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0),
6611 Node->getOperand(1), TH, FH, Node->getOperand(4));
6614 case ISD::ANY_EXTEND:
6615 // The low part is any extension of the input (which degenerates to a copy).
6616 Lo = DAG.getNode(ISD::ANY_EXTEND, NVT, Node->getOperand(0));
6617 // The high part is undefined.
6618 Hi = DAG.getNode(ISD::UNDEF, NVT);
6620 case ISD::SIGN_EXTEND: {
6621 // The low part is just a sign extension of the input (which degenerates to
6623 Lo = DAG.getNode(ISD::SIGN_EXTEND, NVT, Node->getOperand(0));
6625 // The high part is obtained by SRA'ing all but one of the bits of the lo
6627 unsigned LoSize = Lo.getValueType().getSizeInBits();
6628 Hi = DAG.getNode(ISD::SRA, NVT, Lo,
6629 DAG.getConstant(LoSize-1, TLI.getShiftAmountTy()));
6632 case ISD::ZERO_EXTEND:
6633 // The low part is just a zero extension of the input (which degenerates to
6635 Lo = DAG.getNode(ISD::ZERO_EXTEND, NVT, Node->getOperand(0));
6637 // The high part is just a zero.
6638 Hi = DAG.getConstant(0, NVT);
6641 case ISD::TRUNCATE: {
6642 // The input value must be larger than this value. Expand *it*.
6644 ExpandOp(Node->getOperand(0), NewLo, Hi);
6646 // The low part is now either the right size, or it is closer. If not the
6647 // right size, make an illegal truncate so we recursively expand it.
6648 if (NewLo.getValueType() != Node->getValueType(0))
6649 NewLo = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), NewLo);
6650 ExpandOp(NewLo, Lo, Hi);
6654 case ISD::BIT_CONVERT: {
6656 if (TLI.getOperationAction(ISD::BIT_CONVERT, VT) == TargetLowering::Custom){
6657 // If the target wants to, allow it to lower this itself.
6658 switch (getTypeAction(Node->getOperand(0).getValueType())) {
6659 case Expand: assert(0 && "cannot expand FP!");
6660 case Legal: Tmp = LegalizeOp(Node->getOperand(0)); break;
6661 case Promote: Tmp = PromoteOp (Node->getOperand(0)); break;
6663 Tmp = TLI.LowerOperation(DAG.getNode(ISD::BIT_CONVERT, VT, Tmp), DAG);
6666 // f32 / f64 must be expanded to i32 / i64.
6667 if (VT == MVT::f32 || VT == MVT::f64) {
6668 Lo = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0));
6669 if (getTypeAction(NVT) == Expand)
6670 ExpandOp(Lo, Lo, Hi);
6674 // If source operand will be expanded to the same type as VT, i.e.
6675 // i64 <- f64, i32 <- f32, expand the source operand instead.
6676 MVT VT0 = Node->getOperand(0).getValueType();
6677 if (getTypeAction(VT0) == Expand && TLI.getTypeToTransformTo(VT0) == VT) {
6678 ExpandOp(Node->getOperand(0), Lo, Hi);
6682 // Turn this into a load/store pair by default.
6683 if (Tmp.getNode() == 0)
6684 Tmp = EmitStackConvert(Node->getOperand(0), VT, VT);
6686 ExpandOp(Tmp, Lo, Hi);
6690 case ISD::READCYCLECOUNTER: {
6691 assert(TLI.getOperationAction(ISD::READCYCLECOUNTER, VT) ==
6692 TargetLowering::Custom &&
6693 "Must custom expand ReadCycleCounter");
6694 SDValue Tmp = TLI.LowerOperation(Op, DAG);
6695 assert(Tmp.getNode() && "Node must be custom expanded!");
6696 ExpandOp(Tmp.getValue(0), Lo, Hi);
6697 AddLegalizedOperand(SDValue(Node, 1), // Remember we legalized the chain.
6698 LegalizeOp(Tmp.getValue(1)));
6702 case ISD::ATOMIC_CMP_SWAP: {
6703 // This operation does not need a loop.
6704 SDValue Tmp = TLI.LowerOperation(Op, DAG);
6705 assert(Tmp.getNode() && "Node must be custom expanded!");
6706 ExpandOp(Tmp.getValue(0), Lo, Hi);
6707 AddLegalizedOperand(SDValue(Node, 1), // Remember we legalized the chain.
6708 LegalizeOp(Tmp.getValue(1)));
6712 case ISD::ATOMIC_LOAD_ADD:
6713 case ISD::ATOMIC_LOAD_SUB:
6714 case ISD::ATOMIC_LOAD_AND:
6715 case ISD::ATOMIC_LOAD_OR:
6716 case ISD::ATOMIC_LOAD_XOR:
6717 case ISD::ATOMIC_LOAD_NAND:
6718 case ISD::ATOMIC_SWAP: {
6719 // These operations require a loop to be generated. We can't do that yet,
6720 // so substitute a target-dependent pseudo and expand that later.
6721 SDValue In2Lo, In2Hi, In2;
6722 ExpandOp(Op.getOperand(2), In2Lo, In2Hi);
6723 In2 = DAG.getNode(ISD::BUILD_PAIR, VT, In2Lo, In2Hi);
6724 AtomicSDNode* Anode = cast<AtomicSDNode>(Node);
6726 DAG.getAtomic(Op.getOpcode(), Anode->getMemoryVT(),
6727 Op.getOperand(0), Op.getOperand(1), In2,
6728 Anode->getSrcValue(), Anode->getAlignment());
6729 SDValue Result = TLI.LowerOperation(Replace, DAG);
6730 ExpandOp(Result.getValue(0), Lo, Hi);
6731 // Remember that we legalized the chain.
6732 AddLegalizedOperand(SDValue(Node,1), LegalizeOp(Result.getValue(1)));
6736 // These operators cannot be expanded directly, emit them as calls to
6737 // library functions.
6738 case ISD::FP_TO_SINT: {
6739 if (TLI.getOperationAction(ISD::FP_TO_SINT, VT) == TargetLowering::Custom) {
6741 switch (getTypeAction(Node->getOperand(0).getValueType())) {
6742 case Expand: assert(0 && "cannot expand FP!");
6743 case Legal: Op = LegalizeOp(Node->getOperand(0)); break;
6744 case Promote: Op = PromoteOp (Node->getOperand(0)); break;
6747 Op = TLI.LowerOperation(DAG.getNode(ISD::FP_TO_SINT, VT, Op), DAG);
6749 // Now that the custom expander is done, expand the result, which is still
6752 ExpandOp(Op, Lo, Hi);
6757 RTLIB::Libcall LC = RTLIB::getFPTOSINT(Node->getOperand(0).getValueType(),
6759 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected uint-to-fp conversion!");
6760 Lo = ExpandLibCall(LC, Node, false/*sign irrelevant*/, Hi);
6764 case ISD::FP_TO_UINT: {
6765 if (TLI.getOperationAction(ISD::FP_TO_UINT, VT) == TargetLowering::Custom) {
6767 switch (getTypeAction(Node->getOperand(0).getValueType())) {
6768 case Expand: assert(0 && "cannot expand FP!");
6769 case Legal: Op = LegalizeOp(Node->getOperand(0)); break;
6770 case Promote: Op = PromoteOp (Node->getOperand(0)); break;
6773 Op = TLI.LowerOperation(DAG.getNode(ISD::FP_TO_UINT, VT, Op), DAG);
6775 // Now that the custom expander is done, expand the result.
6777 ExpandOp(Op, Lo, Hi);
6782 RTLIB::Libcall LC = RTLIB::getFPTOUINT(Node->getOperand(0).getValueType(),
6784 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected fp-to-uint conversion!");
6785 Lo = ExpandLibCall(LC, Node, false/*sign irrelevant*/, Hi);
6790 // If the target wants custom lowering, do so.
6791 SDValue ShiftAmt = LegalizeOp(Node->getOperand(1));
6792 if (TLI.getOperationAction(ISD::SHL, VT) == TargetLowering::Custom) {
6793 SDValue Op = DAG.getNode(ISD::SHL, VT, Node->getOperand(0), ShiftAmt);
6794 Op = TLI.LowerOperation(Op, DAG);
6796 // Now that the custom expander is done, expand the result, which is
6798 ExpandOp(Op, Lo, Hi);
6803 // If ADDC/ADDE are supported and if the shift amount is a constant 1, emit
6804 // this X << 1 as X+X.
6805 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(ShiftAmt)) {
6806 if (ShAmt->getAPIntValue() == 1 && TLI.isOperationLegal(ISD::ADDC, NVT) &&
6807 TLI.isOperationLegal(ISD::ADDE, NVT)) {
6808 SDValue LoOps[2], HiOps[3];
6809 ExpandOp(Node->getOperand(0), LoOps[0], HiOps[0]);
6810 SDVTList VTList = DAG.getVTList(LoOps[0].getValueType(), MVT::Flag);
6811 LoOps[1] = LoOps[0];
6812 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2);
6814 HiOps[1] = HiOps[0];
6815 HiOps[2] = Lo.getValue(1);
6816 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3);
6821 // If we can emit an efficient shift operation, do so now.
6822 if (ExpandShift(ISD::SHL, Node->getOperand(0), ShiftAmt, Lo, Hi))
6825 // If this target supports SHL_PARTS, use it.
6826 TargetLowering::LegalizeAction Action =
6827 TLI.getOperationAction(ISD::SHL_PARTS, NVT);
6828 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) ||
6829 Action == TargetLowering::Custom) {
6830 ExpandShiftParts(ISD::SHL_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi);
6834 // Otherwise, emit a libcall.
6835 Lo = ExpandLibCall(RTLIB::SHL_I64, Node, false/*left shift=unsigned*/, Hi);
6840 // If the target wants custom lowering, do so.
6841 SDValue ShiftAmt = LegalizeOp(Node->getOperand(1));
6842 if (TLI.getOperationAction(ISD::SRA, VT) == TargetLowering::Custom) {
6843 SDValue Op = DAG.getNode(ISD::SRA, VT, Node->getOperand(0), ShiftAmt);
6844 Op = TLI.LowerOperation(Op, DAG);
6846 // Now that the custom expander is done, expand the result, which is
6848 ExpandOp(Op, Lo, Hi);
6853 // If we can emit an efficient shift operation, do so now.
6854 if (ExpandShift(ISD::SRA, Node->getOperand(0), ShiftAmt, Lo, Hi))
6857 // If this target supports SRA_PARTS, use it.
6858 TargetLowering::LegalizeAction Action =
6859 TLI.getOperationAction(ISD::SRA_PARTS, NVT);
6860 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) ||
6861 Action == TargetLowering::Custom) {
6862 ExpandShiftParts(ISD::SRA_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi);
6866 // Otherwise, emit a libcall.
6867 Lo = ExpandLibCall(RTLIB::SRA_I64, Node, true/*ashr is signed*/, Hi);
6872 // If the target wants custom lowering, do so.
6873 SDValue ShiftAmt = LegalizeOp(Node->getOperand(1));
6874 if (TLI.getOperationAction(ISD::SRL, VT) == TargetLowering::Custom) {
6875 SDValue Op = DAG.getNode(ISD::SRL, VT, Node->getOperand(0), ShiftAmt);
6876 Op = TLI.LowerOperation(Op, DAG);
6878 // Now that the custom expander is done, expand the result, which is
6880 ExpandOp(Op, Lo, Hi);
6885 // If we can emit an efficient shift operation, do so now.
6886 if (ExpandShift(ISD::SRL, Node->getOperand(0), ShiftAmt, Lo, Hi))
6889 // If this target supports SRL_PARTS, use it.
6890 TargetLowering::LegalizeAction Action =
6891 TLI.getOperationAction(ISD::SRL_PARTS, NVT);
6892 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) ||
6893 Action == TargetLowering::Custom) {
6894 ExpandShiftParts(ISD::SRL_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi);
6898 // Otherwise, emit a libcall.
6899 Lo = ExpandLibCall(RTLIB::SRL_I64, Node, false/*lshr is unsigned*/, Hi);
6905 // If the target wants to custom expand this, let them.
6906 if (TLI.getOperationAction(Node->getOpcode(), VT) ==
6907 TargetLowering::Custom) {
6908 SDValue Result = TLI.LowerOperation(Op, DAG);
6909 if (Result.getNode()) {
6910 ExpandOp(Result, Lo, Hi);
6914 // Expand the subcomponents.
6915 SDValue LHSL, LHSH, RHSL, RHSH;
6916 ExpandOp(Node->getOperand(0), LHSL, LHSH);
6917 ExpandOp(Node->getOperand(1), RHSL, RHSH);
6918 SDValue LoOps[2], HiOps[3];
6924 //cascaded check to see if any smaller size has a a carry flag.
6925 unsigned OpV = Node->getOpcode() == ISD::ADD ? ISD::ADDC : ISD::SUBC;
6926 bool hasCarry = false;
6927 for (unsigned BitSize = NVT.getSizeInBits(); BitSize != 0; BitSize /= 2) {
6928 MVT AVT = MVT::getIntegerVT(BitSize);
6929 if (TLI.isOperationLegal(OpV, AVT)) {
6936 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag);
6937 if (Node->getOpcode() == ISD::ADD) {
6938 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2);
6939 HiOps[2] = Lo.getValue(1);
6940 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3);
6942 Lo = DAG.getNode(ISD::SUBC, VTList, LoOps, 2);
6943 HiOps[2] = Lo.getValue(1);
6944 Hi = DAG.getNode(ISD::SUBE, VTList, HiOps, 3);
6948 if (Node->getOpcode() == ISD::ADD) {
6949 Lo = DAG.getNode(ISD::ADD, NVT, LoOps, 2);
6950 Hi = DAG.getNode(ISD::ADD, NVT, HiOps, 2);
6951 SDValue Cmp1 = DAG.getSetCC(TLI.getSetCCResultType(Lo),
6952 Lo, LoOps[0], ISD::SETULT);
6953 SDValue Carry1 = DAG.getNode(ISD::SELECT, NVT, Cmp1,
6954 DAG.getConstant(1, NVT),
6955 DAG.getConstant(0, NVT));
6956 SDValue Cmp2 = DAG.getSetCC(TLI.getSetCCResultType(Lo),
6957 Lo, LoOps[1], ISD::SETULT);
6958 SDValue Carry2 = DAG.getNode(ISD::SELECT, NVT, Cmp2,
6959 DAG.getConstant(1, NVT),
6961 Hi = DAG.getNode(ISD::ADD, NVT, Hi, Carry2);
6963 Lo = DAG.getNode(ISD::SUB, NVT, LoOps, 2);
6964 Hi = DAG.getNode(ISD::SUB, NVT, HiOps, 2);
6965 SDValue Cmp = DAG.getSetCC(NVT, LoOps[0], LoOps[1], ISD::SETULT);
6966 SDValue Borrow = DAG.getNode(ISD::SELECT, NVT, Cmp,
6967 DAG.getConstant(1, NVT),
6968 DAG.getConstant(0, NVT));
6969 Hi = DAG.getNode(ISD::SUB, NVT, Hi, Borrow);
6977 // Expand the subcomponents.
6978 SDValue LHSL, LHSH, RHSL, RHSH;
6979 ExpandOp(Node->getOperand(0), LHSL, LHSH);
6980 ExpandOp(Node->getOperand(1), RHSL, RHSH);
6981 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag);
6982 SDValue LoOps[2] = { LHSL, RHSL };
6983 SDValue HiOps[3] = { LHSH, RHSH };
6985 if (Node->getOpcode() == ISD::ADDC) {
6986 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2);
6987 HiOps[2] = Lo.getValue(1);
6988 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3);
6990 Lo = DAG.getNode(ISD::SUBC, VTList, LoOps, 2);
6991 HiOps[2] = Lo.getValue(1);
6992 Hi = DAG.getNode(ISD::SUBE, VTList, HiOps, 3);
6994 // Remember that we legalized the flag.
6995 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Hi.getValue(1)));
7000 // Expand the subcomponents.
7001 SDValue LHSL, LHSH, RHSL, RHSH;
7002 ExpandOp(Node->getOperand(0), LHSL, LHSH);
7003 ExpandOp(Node->getOperand(1), RHSL, RHSH);
7004 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag);
7005 SDValue LoOps[3] = { LHSL, RHSL, Node->getOperand(2) };
7006 SDValue HiOps[3] = { LHSH, RHSH };
7008 Lo = DAG.getNode(Node->getOpcode(), VTList, LoOps, 3);
7009 HiOps[2] = Lo.getValue(1);
7010 Hi = DAG.getNode(Node->getOpcode(), VTList, HiOps, 3);
7012 // Remember that we legalized the flag.
7013 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Hi.getValue(1)));
7017 // If the target wants to custom expand this, let them.
7018 if (TLI.getOperationAction(ISD::MUL, VT) == TargetLowering::Custom) {
7019 SDValue New = TLI.LowerOperation(Op, DAG);
7020 if (New.getNode()) {
7021 ExpandOp(New, Lo, Hi);
7026 bool HasMULHS = TLI.isOperationLegal(ISD::MULHS, NVT);
7027 bool HasMULHU = TLI.isOperationLegal(ISD::MULHU, NVT);
7028 bool HasSMUL_LOHI = TLI.isOperationLegal(ISD::SMUL_LOHI, NVT);
7029 bool HasUMUL_LOHI = TLI.isOperationLegal(ISD::UMUL_LOHI, NVT);
7030 if (HasMULHU || HasMULHS || HasUMUL_LOHI || HasSMUL_LOHI) {
7031 SDValue LL, LH, RL, RH;
7032 ExpandOp(Node->getOperand(0), LL, LH);
7033 ExpandOp(Node->getOperand(1), RL, RH);
7034 unsigned OuterBitSize = Op.getValueSizeInBits();
7035 unsigned InnerBitSize = RH.getValueSizeInBits();
7036 unsigned LHSSB = DAG.ComputeNumSignBits(Op.getOperand(0));
7037 unsigned RHSSB = DAG.ComputeNumSignBits(Op.getOperand(1));
7038 APInt HighMask = APInt::getHighBitsSet(OuterBitSize, InnerBitSize);
7039 if (DAG.MaskedValueIsZero(Node->getOperand(0), HighMask) &&
7040 DAG.MaskedValueIsZero(Node->getOperand(1), HighMask)) {
7041 // The inputs are both zero-extended.
7043 // We can emit a umul_lohi.
7044 Lo = DAG.getNode(ISD::UMUL_LOHI, DAG.getVTList(NVT, NVT), LL, RL);
7045 Hi = SDValue(Lo.getNode(), 1);
7049 // We can emit a mulhu+mul.
7050 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL);
7051 Hi = DAG.getNode(ISD::MULHU, NVT, LL, RL);
7055 if (LHSSB > InnerBitSize && RHSSB > InnerBitSize) {
7056 // The input values are both sign-extended.
7058 // We can emit a smul_lohi.
7059 Lo = DAG.getNode(ISD::SMUL_LOHI, DAG.getVTList(NVT, NVT), LL, RL);
7060 Hi = SDValue(Lo.getNode(), 1);
7064 // We can emit a mulhs+mul.
7065 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL);
7066 Hi = DAG.getNode(ISD::MULHS, NVT, LL, RL);
7071 // Lo,Hi = umul LHS, RHS.
7072 SDValue UMulLOHI = DAG.getNode(ISD::UMUL_LOHI,
7073 DAG.getVTList(NVT, NVT), LL, RL);
7075 Hi = UMulLOHI.getValue(1);
7076 RH = DAG.getNode(ISD::MUL, NVT, LL, RH);
7077 LH = DAG.getNode(ISD::MUL, NVT, LH, RL);
7078 Hi = DAG.getNode(ISD::ADD, NVT, Hi, RH);
7079 Hi = DAG.getNode(ISD::ADD, NVT, Hi, LH);
7083 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL);
7084 Hi = DAG.getNode(ISD::MULHU, NVT, LL, RL);
7085 RH = DAG.getNode(ISD::MUL, NVT, LL, RH);
7086 LH = DAG.getNode(ISD::MUL, NVT, LH, RL);
7087 Hi = DAG.getNode(ISD::ADD, NVT, Hi, RH);
7088 Hi = DAG.getNode(ISD::ADD, NVT, Hi, LH);
7093 // If nothing else, we can make a libcall.
7094 Lo = ExpandLibCall(RTLIB::MUL_I64, Node, false/*sign irrelevant*/, Hi);
7098 Lo = ExpandLibCall(RTLIB::SDIV_I64, Node, true, Hi);
7101 Lo = ExpandLibCall(RTLIB::UDIV_I64, Node, true, Hi);
7104 Lo = ExpandLibCall(RTLIB::SREM_I64, Node, true, Hi);
7107 Lo = ExpandLibCall(RTLIB::UREM_I64, Node, true, Hi);
7111 Lo = ExpandLibCall(GetFPLibCall(VT, RTLIB::ADD_F32,
7114 RTLIB::ADD_PPCF128),
7118 Lo = ExpandLibCall(GetFPLibCall(VT, RTLIB::SUB_F32,
7121 RTLIB::SUB_PPCF128),
7125 Lo = ExpandLibCall(GetFPLibCall(VT, RTLIB::MUL_F32,
7128 RTLIB::MUL_PPCF128),
7132 Lo = ExpandLibCall(GetFPLibCall(VT, RTLIB::DIV_F32,
7135 RTLIB::DIV_PPCF128),
7138 case ISD::FP_EXTEND: {
7139 if (VT == MVT::ppcf128) {
7140 assert(Node->getOperand(0).getValueType()==MVT::f32 ||
7141 Node->getOperand(0).getValueType()==MVT::f64);
7142 const uint64_t zero = 0;
7143 if (Node->getOperand(0).getValueType()==MVT::f32)
7144 Hi = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Node->getOperand(0));
7146 Hi = Node->getOperand(0);
7147 Lo = DAG.getConstantFP(APFloat(APInt(64, 1, &zero)), MVT::f64);
7150 RTLIB::Libcall LC = RTLIB::getFPEXT(Node->getOperand(0).getValueType(), VT);
7151 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported FP_EXTEND!");
7152 Lo = ExpandLibCall(LC, Node, true, Hi);
7155 case ISD::FP_ROUND: {
7156 RTLIB::Libcall LC = RTLIB::getFPROUND(Node->getOperand(0).getValueType(),
7158 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported FP_ROUND!");
7159 Lo = ExpandLibCall(LC, Node, true, Hi);
7174 case ISD::FNEARBYINT:
7177 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
7178 switch(Node->getOpcode()) {
7180 LC = GetFPLibCall(VT, RTLIB::SQRT_F32, RTLIB::SQRT_F64,
7181 RTLIB::SQRT_F80, RTLIB::SQRT_PPCF128);
7184 LC = GetFPLibCall(VT, RTLIB::SIN_F32, RTLIB::SIN_F64,
7185 RTLIB::SIN_F80, RTLIB::SIN_PPCF128);
7188 LC = GetFPLibCall(VT, RTLIB::COS_F32, RTLIB::COS_F64,
7189 RTLIB::COS_F80, RTLIB::COS_PPCF128);
7192 LC = GetFPLibCall(VT, RTLIB::LOG_F32, RTLIB::LOG_F64,
7193 RTLIB::LOG_F80, RTLIB::LOG_PPCF128);
7196 LC = GetFPLibCall(VT, RTLIB::LOG2_F32, RTLIB::LOG2_F64,
7197 RTLIB::LOG2_F80, RTLIB::LOG2_PPCF128);
7200 LC = GetFPLibCall(VT, RTLIB::LOG10_F32, RTLIB::LOG10_F64,
7201 RTLIB::LOG10_F80, RTLIB::LOG10_PPCF128);
7204 LC = GetFPLibCall(VT, RTLIB::EXP_F32, RTLIB::EXP_F64,
7205 RTLIB::EXP_F80, RTLIB::EXP_PPCF128);
7208 LC = GetFPLibCall(VT, RTLIB::EXP2_F32, RTLIB::EXP2_F64,
7209 RTLIB::EXP2_F80, RTLIB::EXP2_PPCF128);
7212 LC = GetFPLibCall(VT, RTLIB::TRUNC_F32, RTLIB::TRUNC_F64,
7213 RTLIB::TRUNC_F80, RTLIB::TRUNC_PPCF128);
7216 LC = GetFPLibCall(VT, RTLIB::FLOOR_F32, RTLIB::FLOOR_F64,
7217 RTLIB::FLOOR_F80, RTLIB::FLOOR_PPCF128);
7220 LC = GetFPLibCall(VT, RTLIB::CEIL_F32, RTLIB::CEIL_F64,
7221 RTLIB::CEIL_F80, RTLIB::CEIL_PPCF128);
7224 LC = GetFPLibCall(VT, RTLIB::RINT_F32, RTLIB::RINT_F64,
7225 RTLIB::RINT_F80, RTLIB::RINT_PPCF128);
7227 case ISD::FNEARBYINT:
7228 LC = GetFPLibCall(VT, RTLIB::NEARBYINT_F32, RTLIB::NEARBYINT_F64,
7229 RTLIB::NEARBYINT_F80, RTLIB::NEARBYINT_PPCF128);
7232 LC = GetFPLibCall(VT, RTLIB::POW_F32, RTLIB::POW_F64, RTLIB::POW_F80,
7233 RTLIB::POW_PPCF128);
7236 LC = GetFPLibCall(VT, RTLIB::POWI_F32, RTLIB::POWI_F64, RTLIB::POWI_F80,
7237 RTLIB::POWI_PPCF128);
7239 default: assert(0 && "Unreachable!");
7241 Lo = ExpandLibCall(LC, Node, false, Hi);
7245 if (VT == MVT::ppcf128) {
7247 ExpandOp(Node->getOperand(0), Lo, Tmp);
7248 Hi = DAG.getNode(ISD::FABS, NVT, Tmp);
7249 // lo = hi==fabs(hi) ? lo : -lo;
7250 Lo = DAG.getNode(ISD::SELECT_CC, NVT, Hi, Tmp,
7251 Lo, DAG.getNode(ISD::FNEG, NVT, Lo),
7252 DAG.getCondCode(ISD::SETEQ));
7255 SDValue Mask = (VT == MVT::f64)
7256 ? DAG.getConstantFP(BitsToDouble(~(1ULL << 63)), VT)
7257 : DAG.getConstantFP(BitsToFloat(~(1U << 31)), VT);
7258 Mask = DAG.getNode(ISD::BIT_CONVERT, NVT, Mask);
7259 Lo = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0));
7260 Lo = DAG.getNode(ISD::AND, NVT, Lo, Mask);
7261 if (getTypeAction(NVT) == Expand)
7262 ExpandOp(Lo, Lo, Hi);
7266 if (VT == MVT::ppcf128) {
7267 ExpandOp(Node->getOperand(0), Lo, Hi);
7268 Lo = DAG.getNode(ISD::FNEG, MVT::f64, Lo);
7269 Hi = DAG.getNode(ISD::FNEG, MVT::f64, Hi);
7272 SDValue Mask = (VT == MVT::f64)
7273 ? DAG.getConstantFP(BitsToDouble(1ULL << 63), VT)
7274 : DAG.getConstantFP(BitsToFloat(1U << 31), VT);
7275 Mask = DAG.getNode(ISD::BIT_CONVERT, NVT, Mask);
7276 Lo = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0));
7277 Lo = DAG.getNode(ISD::XOR, NVT, Lo, Mask);
7278 if (getTypeAction(NVT) == Expand)
7279 ExpandOp(Lo, Lo, Hi);
7282 case ISD::FCOPYSIGN: {
7283 Lo = ExpandFCOPYSIGNToBitwiseOps(Node, NVT, DAG, TLI);
7284 if (getTypeAction(NVT) == Expand)
7285 ExpandOp(Lo, Lo, Hi);
7288 case ISD::SINT_TO_FP:
7289 case ISD::UINT_TO_FP: {
7290 bool isSigned = Node->getOpcode() == ISD::SINT_TO_FP;
7291 MVT SrcVT = Node->getOperand(0).getValueType();
7293 // Promote the operand if needed. Do this before checking for
7294 // ppcf128 so conversions of i16 and i8 work.
7295 if (getTypeAction(SrcVT) == Promote) {
7296 SDValue Tmp = PromoteOp(Node->getOperand(0));
7298 ? DAG.getNode(ISD::SIGN_EXTEND_INREG, Tmp.getValueType(), Tmp,
7299 DAG.getValueType(SrcVT))
7300 : DAG.getZeroExtendInReg(Tmp, SrcVT);
7301 Node = DAG.UpdateNodeOperands(Op, Tmp).getNode();
7302 SrcVT = Node->getOperand(0).getValueType();
7305 if (VT == MVT::ppcf128 && SrcVT == MVT::i32) {
7306 static const uint64_t zero = 0;
7308 Hi = LegalizeOp(DAG.getNode(ISD::SINT_TO_FP, MVT::f64,
7309 Node->getOperand(0)));
7310 Lo = DAG.getConstantFP(APFloat(APInt(64, 1, &zero)), MVT::f64);
7312 static const uint64_t TwoE32[] = { 0x41f0000000000000LL, 0 };
7313 Hi = LegalizeOp(DAG.getNode(ISD::SINT_TO_FP, MVT::f64,
7314 Node->getOperand(0)));
7315 Lo = DAG.getConstantFP(APFloat(APInt(64, 1, &zero)), MVT::f64);
7316 Hi = DAG.getNode(ISD::BUILD_PAIR, VT, Lo, Hi);
7317 // X>=0 ? {(f64)x, 0} : {(f64)x, 0} + 2^32
7318 ExpandOp(DAG.getNode(ISD::SELECT_CC, MVT::ppcf128, Node->getOperand(0),
7319 DAG.getConstant(0, MVT::i32),
7320 DAG.getNode(ISD::FADD, MVT::ppcf128, Hi,
7322 APFloat(APInt(128, 2, TwoE32)),
7325 DAG.getCondCode(ISD::SETLT)),
7330 if (VT == MVT::ppcf128 && SrcVT == MVT::i64 && !isSigned) {
7331 // si64->ppcf128 done by libcall, below
7332 static const uint64_t TwoE64[] = { 0x43f0000000000000LL, 0 };
7333 ExpandOp(DAG.getNode(ISD::SINT_TO_FP, MVT::ppcf128, Node->getOperand(0)),
7335 Hi = DAG.getNode(ISD::BUILD_PAIR, VT, Lo, Hi);
7336 // x>=0 ? (ppcf128)(i64)x : (ppcf128)(i64)x + 2^64
7337 ExpandOp(DAG.getNode(ISD::SELECT_CC, MVT::ppcf128, Node->getOperand(0),
7338 DAG.getConstant(0, MVT::i64),
7339 DAG.getNode(ISD::FADD, MVT::ppcf128, Hi,
7341 APFloat(APInt(128, 2, TwoE64)),
7344 DAG.getCondCode(ISD::SETLT)),
7349 Lo = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP, VT,
7350 Node->getOperand(0));
7351 if (getTypeAction(Lo.getValueType()) == Expand)
7352 // float to i32 etc. can be 'expanded' to a single node.
7353 ExpandOp(Lo, Lo, Hi);
7358 // Make sure the resultant values have been legalized themselves, unless this
7359 // is a type that requires multi-step expansion.
7360 if (getTypeAction(NVT) != Expand && NVT != MVT::isVoid) {
7361 Lo = LegalizeOp(Lo);
7363 // Don't legalize the high part if it is expanded to a single node.
7364 Hi = LegalizeOp(Hi);
7367 // Remember in a map if the values will be reused later.
7369 ExpandedNodes.insert(std::make_pair(Op, std::make_pair(Lo, Hi))).second;
7370 assert(isNew && "Value already expanded?!?");
7374 /// SplitVectorOp - Given an operand of vector type, break it down into
7375 /// two smaller values, still of vector type.
7376 void SelectionDAGLegalize::SplitVectorOp(SDValue Op, SDValue &Lo,
7378 assert(Op.getValueType().isVector() && "Cannot split non-vector type!");
7379 SDNode *Node = Op.getNode();
7380 unsigned NumElements = Op.getValueType().getVectorNumElements();
7381 assert(NumElements > 1 && "Cannot split a single element vector!");
7383 MVT NewEltVT = Op.getValueType().getVectorElementType();
7385 unsigned NewNumElts_Lo = 1 << Log2_32(NumElements-1);
7386 unsigned NewNumElts_Hi = NumElements - NewNumElts_Lo;
7388 MVT NewVT_Lo = MVT::getVectorVT(NewEltVT, NewNumElts_Lo);
7389 MVT NewVT_Hi = MVT::getVectorVT(NewEltVT, NewNumElts_Hi);
7391 // See if we already split it.
7392 std::map<SDValue, std::pair<SDValue, SDValue> >::iterator I
7393 = SplitNodes.find(Op);
7394 if (I != SplitNodes.end()) {
7395 Lo = I->second.first;
7396 Hi = I->second.second;
7400 switch (Node->getOpcode()) {
7405 assert(0 && "Unhandled operation in SplitVectorOp!");
7407 Lo = DAG.getNode(ISD::UNDEF, NewVT_Lo);
7408 Hi = DAG.getNode(ISD::UNDEF, NewVT_Hi);
7410 case ISD::BUILD_PAIR:
7411 Lo = Node->getOperand(0);
7412 Hi = Node->getOperand(1);
7414 case ISD::INSERT_VECTOR_ELT: {
7415 if (ConstantSDNode *Idx = dyn_cast<ConstantSDNode>(Node->getOperand(2))) {
7416 SplitVectorOp(Node->getOperand(0), Lo, Hi);
7417 unsigned Index = Idx->getZExtValue();
7418 SDValue ScalarOp = Node->getOperand(1);
7419 if (Index < NewNumElts_Lo)
7420 Lo = DAG.getNode(ISD::INSERT_VECTOR_ELT, NewVT_Lo, Lo, ScalarOp,
7421 DAG.getIntPtrConstant(Index));
7423 Hi = DAG.getNode(ISD::INSERT_VECTOR_ELT, NewVT_Hi, Hi, ScalarOp,
7424 DAG.getIntPtrConstant(Index - NewNumElts_Lo));
7427 SDValue Tmp = PerformInsertVectorEltInMemory(Node->getOperand(0),
7428 Node->getOperand(1),
7429 Node->getOperand(2));
7430 SplitVectorOp(Tmp, Lo, Hi);
7433 case ISD::VECTOR_SHUFFLE: {
7434 // Build the low part.
7435 SDValue Mask = Node->getOperand(2);
7436 SmallVector<SDValue, 8> Ops;
7437 MVT PtrVT = TLI.getPointerTy();
7439 // Insert all of the elements from the input that are needed. We use
7440 // buildvector of extractelement here because the input vectors will have
7441 // to be legalized, so this makes the code simpler.
7442 for (unsigned i = 0; i != NewNumElts_Lo; ++i) {
7443 SDValue IdxNode = Mask.getOperand(i);
7444 if (IdxNode.getOpcode() == ISD::UNDEF) {
7445 Ops.push_back(DAG.getNode(ISD::UNDEF, NewEltVT));
7448 unsigned Idx = cast<ConstantSDNode>(IdxNode)->getZExtValue();
7449 SDValue InVec = Node->getOperand(0);
7450 if (Idx >= NumElements) {
7451 InVec = Node->getOperand(1);
7454 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, NewEltVT, InVec,
7455 DAG.getConstant(Idx, PtrVT)));
7457 Lo = DAG.getNode(ISD::BUILD_VECTOR, NewVT_Lo, &Ops[0], Ops.size());
7460 for (unsigned i = NewNumElts_Lo; i != NumElements; ++i) {
7461 SDValue IdxNode = Mask.getOperand(i);
7462 if (IdxNode.getOpcode() == ISD::UNDEF) {
7463 Ops.push_back(DAG.getNode(ISD::UNDEF, NewEltVT));
7466 unsigned Idx = cast<ConstantSDNode>(IdxNode)->getZExtValue();
7467 SDValue InVec = Node->getOperand(0);
7468 if (Idx >= NumElements) {
7469 InVec = Node->getOperand(1);
7472 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, NewEltVT, InVec,
7473 DAG.getConstant(Idx, PtrVT)));
7475 Hi = DAG.getNode(ISD::BUILD_VECTOR, NewVT_Hi, &Ops[0], Ops.size());
7478 case ISD::BUILD_VECTOR: {
7479 SmallVector<SDValue, 8> LoOps(Node->op_begin(),
7480 Node->op_begin()+NewNumElts_Lo);
7481 Lo = DAG.getNode(ISD::BUILD_VECTOR, NewVT_Lo, &LoOps[0], LoOps.size());
7483 SmallVector<SDValue, 8> HiOps(Node->op_begin()+NewNumElts_Lo,
7485 Hi = DAG.getNode(ISD::BUILD_VECTOR, NewVT_Hi, &HiOps[0], HiOps.size());
7488 case ISD::CONCAT_VECTORS: {
7489 // FIXME: Handle non-power-of-two vectors?
7490 unsigned NewNumSubvectors = Node->getNumOperands() / 2;
7491 if (NewNumSubvectors == 1) {
7492 Lo = Node->getOperand(0);
7493 Hi = Node->getOperand(1);
7495 SmallVector<SDValue, 8> LoOps(Node->op_begin(),
7496 Node->op_begin()+NewNumSubvectors);
7497 Lo = DAG.getNode(ISD::CONCAT_VECTORS, NewVT_Lo, &LoOps[0], LoOps.size());
7499 SmallVector<SDValue, 8> HiOps(Node->op_begin()+NewNumSubvectors,
7501 Hi = DAG.getNode(ISD::CONCAT_VECTORS, NewVT_Hi, &HiOps[0], HiOps.size());
7505 case ISD::EXTRACT_SUBVECTOR: {
7506 SDValue Vec = Op.getOperand(0);
7507 SDValue Idx = Op.getOperand(1);
7508 MVT IdxVT = Idx.getValueType();
7510 Lo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, NewVT_Lo, Vec, Idx);
7511 ConstantSDNode *CIdx = dyn_cast<ConstantSDNode>(Idx);
7513 Hi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, NewVT_Hi, Vec,
7514 DAG.getConstant(CIdx->getZExtValue() + NewNumElts_Lo,
7517 Idx = DAG.getNode(ISD::ADD, IdxVT, Idx,
7518 DAG.getConstant(NewNumElts_Lo, IdxVT));
7519 Hi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, NewVT_Hi, Vec, Idx);
7524 SDValue Cond = Node->getOperand(0);
7526 SDValue LL, LH, RL, RH;
7527 SplitVectorOp(Node->getOperand(1), LL, LH);
7528 SplitVectorOp(Node->getOperand(2), RL, RH);
7530 if (Cond.getValueType().isVector()) {
7531 // Handle a vector merge.
7533 SplitVectorOp(Cond, CL, CH);
7534 Lo = DAG.getNode(Node->getOpcode(), NewVT_Lo, CL, LL, RL);
7535 Hi = DAG.getNode(Node->getOpcode(), NewVT_Hi, CH, LH, RH);
7537 // Handle a simple select with vector operands.
7538 Lo = DAG.getNode(Node->getOpcode(), NewVT_Lo, Cond, LL, RL);
7539 Hi = DAG.getNode(Node->getOpcode(), NewVT_Hi, Cond, LH, RH);
7543 case ISD::SELECT_CC: {
7544 SDValue CondLHS = Node->getOperand(0);
7545 SDValue CondRHS = Node->getOperand(1);
7546 SDValue CondCode = Node->getOperand(4);
7548 SDValue LL, LH, RL, RH;
7549 SplitVectorOp(Node->getOperand(2), LL, LH);
7550 SplitVectorOp(Node->getOperand(3), RL, RH);
7552 // Handle a simple select with vector operands.
7553 Lo = DAG.getNode(ISD::SELECT_CC, NewVT_Lo, CondLHS, CondRHS,
7555 Hi = DAG.getNode(ISD::SELECT_CC, NewVT_Hi, CondLHS, CondRHS,
7560 SDValue LL, LH, RL, RH;
7561 SplitVectorOp(Node->getOperand(0), LL, LH);
7562 SplitVectorOp(Node->getOperand(1), RL, RH);
7563 Lo = DAG.getNode(ISD::VSETCC, NewVT_Lo, LL, RL, Node->getOperand(2));
7564 Hi = DAG.getNode(ISD::VSETCC, NewVT_Hi, LH, RH, Node->getOperand(2));
7586 SDValue LL, LH, RL, RH;
7587 SplitVectorOp(Node->getOperand(0), LL, LH);
7588 SplitVectorOp(Node->getOperand(1), RL, RH);
7590 Lo = DAG.getNode(Node->getOpcode(), NewVT_Lo, LL, RL);
7591 Hi = DAG.getNode(Node->getOpcode(), NewVT_Hi, LH, RH);
7597 SplitVectorOp(Node->getOperand(0), L, H);
7599 Lo = DAG.getNode(Node->getOpcode(), NewVT_Lo, L, Node->getOperand(1));
7600 Hi = DAG.getNode(Node->getOpcode(), NewVT_Hi, H, Node->getOperand(1));
7616 case ISD::FP_TO_SINT:
7617 case ISD::FP_TO_UINT:
7618 case ISD::SINT_TO_FP:
7619 case ISD::UINT_TO_FP:
7621 case ISD::ANY_EXTEND:
7622 case ISD::SIGN_EXTEND:
7623 case ISD::ZERO_EXTEND:
7624 case ISD::FP_EXTEND: {
7626 SplitVectorOp(Node->getOperand(0), L, H);
7628 Lo = DAG.getNode(Node->getOpcode(), NewVT_Lo, L);
7629 Hi = DAG.getNode(Node->getOpcode(), NewVT_Hi, H);
7632 case ISD::CONVERT_RNDSAT: {
7633 ISD::CvtCode CvtCode = cast<CvtRndSatSDNode>(Node)->getCvtCode();
7635 SplitVectorOp(Node->getOperand(0), L, H);
7636 SDValue DTyOpL = DAG.getValueType(NewVT_Lo);
7637 SDValue DTyOpH = DAG.getValueType(NewVT_Hi);
7638 SDValue STyOpL = DAG.getValueType(L.getValueType());
7639 SDValue STyOpH = DAG.getValueType(H.getValueType());
7641 SDValue RndOp = Node->getOperand(3);
7642 SDValue SatOp = Node->getOperand(4);
7644 Lo = DAG.getConvertRndSat(NewVT_Lo, L, DTyOpL, STyOpL,
7645 RndOp, SatOp, CvtCode);
7646 Hi = DAG.getConvertRndSat(NewVT_Hi, H, DTyOpH, STyOpH,
7647 RndOp, SatOp, CvtCode);
7651 LoadSDNode *LD = cast<LoadSDNode>(Node);
7652 SDValue Ch = LD->getChain();
7653 SDValue Ptr = LD->getBasePtr();
7654 ISD::LoadExtType ExtType = LD->getExtensionType();
7655 const Value *SV = LD->getSrcValue();
7656 int SVOffset = LD->getSrcValueOffset();
7657 MVT MemoryVT = LD->getMemoryVT();
7658 unsigned Alignment = LD->getAlignment();
7659 bool isVolatile = LD->isVolatile();
7661 assert(LD->isUnindexed() && "Indexed vector loads are not supported yet!");
7662 SDValue Offset = DAG.getNode(ISD::UNDEF, Ptr.getValueType());
7664 MVT MemNewEltVT = MemoryVT.getVectorElementType();
7665 MVT MemNewVT_Lo = MVT::getVectorVT(MemNewEltVT, NewNumElts_Lo);
7666 MVT MemNewVT_Hi = MVT::getVectorVT(MemNewEltVT, NewNumElts_Hi);
7668 Lo = DAG.getLoad(ISD::UNINDEXED, ExtType,
7669 NewVT_Lo, Ch, Ptr, Offset,
7670 SV, SVOffset, MemNewVT_Lo, isVolatile, Alignment);
7671 unsigned IncrementSize = NewNumElts_Lo * MemNewEltVT.getSizeInBits()/8;
7672 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
7673 DAG.getIntPtrConstant(IncrementSize));
7674 SVOffset += IncrementSize;
7675 Alignment = MinAlign(Alignment, IncrementSize);
7676 Hi = DAG.getLoad(ISD::UNINDEXED, ExtType,
7677 NewVT_Hi, Ch, Ptr, Offset,
7678 SV, SVOffset, MemNewVT_Hi, isVolatile, Alignment);
7680 // Build a factor node to remember that this load is independent of the
7682 SDValue TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
7685 // Remember that we legalized the chain.
7686 AddLegalizedOperand(Op.getValue(1), LegalizeOp(TF));
7689 case ISD::BIT_CONVERT: {
7690 // We know the result is a vector. The input may be either a vector or a
7692 SDValue InOp = Node->getOperand(0);
7693 if (!InOp.getValueType().isVector() ||
7694 InOp.getValueType().getVectorNumElements() == 1) {
7695 // The input is a scalar or single-element vector.
7696 // Lower to a store/load so that it can be split.
7697 // FIXME: this could be improved probably.
7698 unsigned LdAlign = TLI.getTargetData()->getPrefTypeAlignment(
7699 Op.getValueType().getTypeForMVT());
7700 SDValue Ptr = DAG.CreateStackTemporary(InOp.getValueType(), LdAlign);
7701 int FI = cast<FrameIndexSDNode>(Ptr.getNode())->getIndex();
7703 SDValue St = DAG.getStore(DAG.getEntryNode(),
7705 PseudoSourceValue::getFixedStack(FI), 0);
7706 InOp = DAG.getLoad(Op.getValueType(), St, Ptr,
7707 PseudoSourceValue::getFixedStack(FI), 0);
7709 // Split the vector and convert each of the pieces now.
7710 SplitVectorOp(InOp, Lo, Hi);
7711 Lo = DAG.getNode(ISD::BIT_CONVERT, NewVT_Lo, Lo);
7712 Hi = DAG.getNode(ISD::BIT_CONVERT, NewVT_Hi, Hi);
7717 // Remember in a map if the values will be reused later.
7719 SplitNodes.insert(std::make_pair(Op, std::make_pair(Lo, Hi))).second;
7720 assert(isNew && "Value already split?!?");
7725 /// ScalarizeVectorOp - Given an operand of single-element vector type
7726 /// (e.g. v1f32), convert it into the equivalent operation that returns a
7727 /// scalar (e.g. f32) value.
7728 SDValue SelectionDAGLegalize::ScalarizeVectorOp(SDValue Op) {
7729 assert(Op.getValueType().isVector() && "Bad ScalarizeVectorOp invocation!");
7730 SDNode *Node = Op.getNode();
7731 MVT NewVT = Op.getValueType().getVectorElementType();
7732 assert(Op.getValueType().getVectorNumElements() == 1);
7734 // See if we already scalarized it.
7735 std::map<SDValue, SDValue>::iterator I = ScalarizedNodes.find(Op);
7736 if (I != ScalarizedNodes.end()) return I->second;
7739 switch (Node->getOpcode()) {
7742 Node->dump(&DAG); cerr << "\n";
7744 assert(0 && "Unknown vector operation in ScalarizeVectorOp!");
7761 Result = DAG.getNode(Node->getOpcode(),
7763 ScalarizeVectorOp(Node->getOperand(0)),
7764 ScalarizeVectorOp(Node->getOperand(1)));
7776 case ISD::FP_TO_SINT:
7777 case ISD::FP_TO_UINT:
7778 case ISD::SINT_TO_FP:
7779 case ISD::UINT_TO_FP:
7780 case ISD::SIGN_EXTEND:
7781 case ISD::ZERO_EXTEND:
7782 case ISD::ANY_EXTEND:
7784 case ISD::FP_EXTEND:
7785 Result = DAG.getNode(Node->getOpcode(),
7787 ScalarizeVectorOp(Node->getOperand(0)));
7789 case ISD::CONVERT_RNDSAT: {
7790 SDValue Op0 = ScalarizeVectorOp(Node->getOperand(0));
7791 Result = DAG.getConvertRndSat(NewVT, Op0,
7792 DAG.getValueType(NewVT),
7793 DAG.getValueType(Op0.getValueType()),
7794 Node->getOperand(3),
7795 Node->getOperand(4),
7796 cast<CvtRndSatSDNode>(Node)->getCvtCode());
7801 Result = DAG.getNode(Node->getOpcode(),
7803 ScalarizeVectorOp(Node->getOperand(0)),
7804 Node->getOperand(1));
7807 LoadSDNode *LD = cast<LoadSDNode>(Node);
7808 SDValue Ch = LegalizeOp(LD->getChain()); // Legalize the chain.
7809 SDValue Ptr = LegalizeOp(LD->getBasePtr()); // Legalize the pointer.
7810 ISD::LoadExtType ExtType = LD->getExtensionType();
7811 const Value *SV = LD->getSrcValue();
7812 int SVOffset = LD->getSrcValueOffset();
7813 MVT MemoryVT = LD->getMemoryVT();
7814 unsigned Alignment = LD->getAlignment();
7815 bool isVolatile = LD->isVolatile();
7817 assert(LD->isUnindexed() && "Indexed vector loads are not supported yet!");
7818 SDValue Offset = DAG.getNode(ISD::UNDEF, Ptr.getValueType());
7820 Result = DAG.getLoad(ISD::UNINDEXED, ExtType,
7821 NewVT, Ch, Ptr, Offset, SV, SVOffset,
7822 MemoryVT.getVectorElementType(),
7823 isVolatile, Alignment);
7825 // Remember that we legalized the chain.
7826 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
7829 case ISD::BUILD_VECTOR:
7830 Result = Node->getOperand(0);
7832 case ISD::INSERT_VECTOR_ELT:
7833 // Returning the inserted scalar element.
7834 Result = Node->getOperand(1);
7836 case ISD::CONCAT_VECTORS:
7837 assert(Node->getOperand(0).getValueType() == NewVT &&
7838 "Concat of non-legal vectors not yet supported!");
7839 Result = Node->getOperand(0);
7841 case ISD::VECTOR_SHUFFLE: {
7842 // Figure out if the scalar is the LHS or RHS and return it.
7843 SDValue EltNum = Node->getOperand(2).getOperand(0);
7844 if (cast<ConstantSDNode>(EltNum)->getZExtValue())
7845 Result = ScalarizeVectorOp(Node->getOperand(1));
7847 Result = ScalarizeVectorOp(Node->getOperand(0));
7850 case ISD::EXTRACT_SUBVECTOR:
7851 Result = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, NewVT, Node->getOperand(0),
7852 Node->getOperand(1));
7854 case ISD::BIT_CONVERT: {
7855 SDValue Op0 = Op.getOperand(0);
7856 if (Op0.getValueType().getVectorNumElements() == 1)
7857 Op0 = ScalarizeVectorOp(Op0);
7858 Result = DAG.getNode(ISD::BIT_CONVERT, NewVT, Op0);
7862 Result = DAG.getNode(ISD::SELECT, NewVT, Op.getOperand(0),
7863 ScalarizeVectorOp(Op.getOperand(1)),
7864 ScalarizeVectorOp(Op.getOperand(2)));
7866 case ISD::SELECT_CC:
7867 Result = DAG.getNode(ISD::SELECT_CC, NewVT, Node->getOperand(0),
7868 Node->getOperand(1),
7869 ScalarizeVectorOp(Op.getOperand(2)),
7870 ScalarizeVectorOp(Op.getOperand(3)),
7871 Node->getOperand(4));
7874 SDValue Op0 = ScalarizeVectorOp(Op.getOperand(0));
7875 SDValue Op1 = ScalarizeVectorOp(Op.getOperand(1));
7876 Result = DAG.getNode(ISD::SETCC, TLI.getSetCCResultType(Op0), Op0, Op1,
7878 Result = DAG.getNode(ISD::SELECT, NewVT, Result,
7879 DAG.getConstant(-1ULL, NewVT),
7880 DAG.getConstant(0ULL, NewVT));
7885 if (TLI.isTypeLegal(NewVT))
7886 Result = LegalizeOp(Result);
7887 bool isNew = ScalarizedNodes.insert(std::make_pair(Op, Result)).second;
7888 assert(isNew && "Value already scalarized?");
7894 SDValue SelectionDAGLegalize::WidenVectorOp(SDValue Op, MVT WidenVT) {
7895 std::map<SDValue, SDValue>::iterator I = WidenNodes.find(Op);
7896 if (I != WidenNodes.end()) return I->second;
7898 MVT VT = Op.getValueType();
7899 assert(VT.isVector() && "Cannot widen non-vector type!");
7902 SDNode *Node = Op.getNode();
7903 MVT EVT = VT.getVectorElementType();
7905 unsigned NumElts = VT.getVectorNumElements();
7906 unsigned NewNumElts = WidenVT.getVectorNumElements();
7907 assert(NewNumElts > NumElts && "Cannot widen to smaller type!");
7908 assert(NewNumElts < 17);
7910 // When widen is called, it is assumed that it is more efficient to use a
7911 // wide type. The default action is to widen to operation to a wider legal
7912 // vector type and then do the operation if it is legal by calling LegalizeOp
7913 // again. If there is no vector equivalent, we will unroll the operation, do
7914 // it, and rebuild the vector. If most of the operations are vectorizible to
7915 // the legal type, the resulting code will be more efficient. If this is not
7916 // the case, the resulting code will preform badly as we end up generating
7917 // code to pack/unpack the results. It is the function that calls widen
7918 // that is responsible for seeing this doesn't happen.
7919 switch (Node->getOpcode()) {
7924 assert(0 && "Unexpected operation in WidenVectorOp!");
7926 case ISD::CopyFromReg:
7927 assert(0 && "CopyFromReg doesn't need widening!");
7929 case ISD::ConstantFP:
7930 // To build a vector of these elements, clients should call BuildVector
7931 // and with each element instead of creating a node with a vector type
7932 assert(0 && "Unexpected operation in WidenVectorOp!");
7934 // Variable Arguments with vector types doesn't make any sense to me
7935 assert(0 && "Unexpected operation in WidenVectorOp!");
7938 Result = DAG.getNode(ISD::UNDEF, WidenVT);
7940 case ISD::BUILD_VECTOR: {
7941 // Build a vector with undefined for the new nodes
7942 SDValueVector NewOps(Node->op_begin(), Node->op_end());
7943 for (unsigned i = NumElts; i < NewNumElts; ++i) {
7944 NewOps.push_back(DAG.getNode(ISD::UNDEF,EVT));
7946 Result = DAG.getNode(ISD::BUILD_VECTOR, WidenVT, &NewOps[0], NewOps.size());
7949 case ISD::INSERT_VECTOR_ELT: {
7950 SDValue Tmp1 = WidenVectorOp(Node->getOperand(0), WidenVT);
7951 Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, WidenVT, Tmp1,
7952 Node->getOperand(1), Node->getOperand(2));
7955 case ISD::VECTOR_SHUFFLE: {
7956 SDValue Tmp1 = WidenVectorOp(Node->getOperand(0), WidenVT);
7957 SDValue Tmp2 = WidenVectorOp(Node->getOperand(1), WidenVT);
7958 // VECTOR_SHUFFLE 3rd operand must be a constant build vector that is
7959 // used as permutation array. We build the vector here instead of widening
7960 // because we don't want to legalize and have it turned to something else.
7961 SDValue PermOp = Node->getOperand(2);
7962 SDValueVector NewOps;
7963 MVT PVT = PermOp.getValueType().getVectorElementType();
7964 for (unsigned i = 0; i < NumElts; ++i) {
7965 if (PermOp.getOperand(i).getOpcode() == ISD::UNDEF) {
7966 NewOps.push_back(PermOp.getOperand(i));
7969 cast<ConstantSDNode>(PermOp.getOperand(i))->getZExtValue();
7970 if (Idx < NumElts) {
7971 NewOps.push_back(PermOp.getOperand(i));
7974 NewOps.push_back(DAG.getConstant(Idx + NewNumElts - NumElts,
7975 PermOp.getOperand(i).getValueType()));
7979 for (unsigned i = NumElts; i < NewNumElts; ++i) {
7980 NewOps.push_back(DAG.getNode(ISD::UNDEF,PVT));
7983 SDValue Tmp3 = DAG.getNode(ISD::BUILD_VECTOR,
7984 MVT::getVectorVT(PVT, NewOps.size()),
7985 &NewOps[0], NewOps.size());
7987 Result = DAG.getNode(ISD::VECTOR_SHUFFLE, WidenVT, Tmp1, Tmp2, Tmp3);
7991 // If the load widen returns true, we can use a single load for the
7992 // vector. Otherwise, it is returning a token factor for multiple
7995 if (LoadWidenVectorOp(Result, TFOp, Op, WidenVT))
7996 AddLegalizedOperand(Op.getValue(1), LegalizeOp(TFOp.getValue(1)));
7998 AddLegalizedOperand(Op.getValue(1), LegalizeOp(TFOp.getValue(0)));
8002 case ISD::BIT_CONVERT: {
8003 SDValue Tmp1 = Node->getOperand(0);
8004 // Converts between two different types so we need to determine
8005 // the correct widen type for the input operand.
8006 MVT InVT = Tmp1.getValueType();
8007 unsigned WidenSize = WidenVT.getSizeInBits();
8008 if (InVT.isVector()) {
8009 MVT InEltVT = InVT.getVectorElementType();
8010 unsigned InEltSize = InEltVT.getSizeInBits();
8011 assert(WidenSize % InEltSize == 0 &&
8012 "can not widen bit convert that are not multiple of element type");
8013 MVT NewInWidenVT = MVT::getVectorVT(InEltVT, WidenSize / InEltSize);
8014 Tmp1 = WidenVectorOp(Tmp1, NewInWidenVT);
8015 assert(Tmp1.getValueType().getSizeInBits() == WidenVT.getSizeInBits());
8016 Result = DAG.getNode(ISD::BIT_CONVERT, WidenVT, Tmp1);
8018 // If the result size is a multiple of the input size, widen the input
8019 // and then convert.
8020 unsigned InSize = InVT.getSizeInBits();
8021 assert(WidenSize % InSize == 0 &&
8022 "can not widen bit convert that are not multiple of element type");
8023 unsigned NewNumElts = WidenSize / InSize;
8024 SmallVector<SDValue, 16> Ops(NewNumElts);
8025 SDValue UndefVal = DAG.getNode(ISD::UNDEF, InVT);
8027 for (unsigned i = 1; i < NewNumElts; ++i)
8030 MVT NewInVT = MVT::getVectorVT(InVT, NewNumElts);
8031 Result = DAG.getNode(ISD::BUILD_VECTOR, NewInVT, &Ops[0], NewNumElts);
8032 Result = DAG.getNode(ISD::BIT_CONVERT, WidenVT, Result);
8037 case ISD::SINT_TO_FP:
8038 case ISD::UINT_TO_FP:
8039 case ISD::FP_TO_SINT:
8040 case ISD::FP_TO_UINT:
8041 case ISD::FP_ROUND: {
8042 SDValue Tmp1 = Node->getOperand(0);
8043 // Converts between two different types so we need to determine
8044 // the correct widen type for the input operand.
8045 MVT TVT = Tmp1.getValueType();
8046 assert(TVT.isVector() && "can not widen non vector type");
8047 MVT TEVT = TVT.getVectorElementType();
8048 MVT TWidenVT = MVT::getVectorVT(TEVT, NewNumElts);
8049 Tmp1 = WidenVectorOp(Tmp1, TWidenVT);
8050 assert(Tmp1.getValueType().getVectorNumElements() == NewNumElts);
8051 Result = DAG.getNode(Node->getOpcode(), WidenVT, Tmp1);
8055 case ISD::FP_EXTEND:
8056 assert(0 && "Case not implemented. Dynamically dead with 2 FP types!");
8058 case ISD::SIGN_EXTEND:
8059 case ISD::ZERO_EXTEND:
8060 case ISD::ANY_EXTEND:
8061 case ISD::SIGN_EXTEND_INREG:
8070 // Unary op widening
8072 Tmp1 = WidenVectorOp(Node->getOperand(0), WidenVT);
8073 assert(Tmp1.getValueType() == WidenVT);
8074 Result = DAG.getNode(Node->getOpcode(), WidenVT, Tmp1);
8077 case ISD::CONVERT_RNDSAT: {
8078 SDValue RndOp = Node->getOperand(3);
8079 SDValue SatOp = Node->getOperand(4);
8080 SDValue SrcOp = Node->getOperand(0);
8082 // Converts between two different types so we need to determine
8083 // the correct widen type for the input operand.
8084 MVT SVT = SrcOp.getValueType();
8085 assert(SVT.isVector() && "can not widen non vector type");
8086 MVT SEVT = SVT.getVectorElementType();
8087 MVT SWidenVT = MVT::getVectorVT(SEVT, NewNumElts);
8089 SrcOp = WidenVectorOp(SrcOp, SWidenVT);
8090 assert(SrcOp.getValueType() == WidenVT);
8091 SDValue DTyOp = DAG.getValueType(WidenVT);
8092 SDValue STyOp = DAG.getValueType(SrcOp.getValueType());
8093 ISD::CvtCode CvtCode = cast<CvtRndSatSDNode>(Node)->getCvtCode();
8095 Result = DAG.getConvertRndSat(WidenVT, SrcOp, DTyOp, STyOp,
8096 RndOp, SatOp, CvtCode);
8116 case ISD::FCOPYSIGN:
8120 // Binary op widening
8121 SDValue Tmp1 = WidenVectorOp(Node->getOperand(0), WidenVT);
8122 SDValue Tmp2 = WidenVectorOp(Node->getOperand(1), WidenVT);
8123 assert(Tmp1.getValueType() == WidenVT && Tmp2.getValueType() == WidenVT);
8124 Result = DAG.getNode(Node->getOpcode(), WidenVT, Tmp1, Tmp2);
8131 SDValue Tmp1 = WidenVectorOp(Node->getOperand(0), WidenVT);
8132 assert(Tmp1.getValueType() == WidenVT);
8133 SDValue ShOp = Node->getOperand(1);
8134 MVT ShVT = ShOp.getValueType();
8135 MVT NewShVT = MVT::getVectorVT(ShVT.getVectorElementType(),
8136 WidenVT.getVectorNumElements());
8137 ShOp = WidenVectorOp(ShOp, NewShVT);
8138 assert(ShOp.getValueType() == NewShVT);
8139 Result = DAG.getNode(Node->getOpcode(), WidenVT, Tmp1, ShOp);
8143 case ISD::EXTRACT_VECTOR_ELT: {
8144 SDValue Tmp1 = WidenVectorOp(Node->getOperand(0), WidenVT);
8145 assert(Tmp1.getValueType() == WidenVT);
8146 Result = DAG.getNode(Node->getOpcode(), EVT, Tmp1, Node->getOperand(1));
8149 case ISD::CONCAT_VECTORS: {
8150 // We concurrently support only widen on a multiple of the incoming vector.
8151 // We could widen on a multiple of the incoming operand if necessary.
8152 unsigned NumConcat = NewNumElts / NumElts;
8153 assert(NewNumElts % NumElts == 0 && "Can widen only a multiple of vector");
8154 SDValue UndefVal = DAG.getNode(ISD::UNDEF, VT);
8155 SmallVector<SDValue, 8> MOps;
8157 for (unsigned i = 1; i != NumConcat; ++i) {
8158 MOps.push_back(UndefVal);
8160 Result = LegalizeOp(DAG.getNode(ISD::CONCAT_VECTORS, WidenVT,
8161 &MOps[0], MOps.size()));
8164 case ISD::EXTRACT_SUBVECTOR: {
8165 SDValue Tmp1 = Node->getOperand(0);
8166 SDValue Idx = Node->getOperand(1);
8167 ConstantSDNode *CIdx = dyn_cast<ConstantSDNode>(Idx);
8168 if (CIdx && CIdx->getZExtValue() == 0) {
8169 // Since we are access the start of the vector, the incoming
8170 // vector type might be the proper.
8171 MVT Tmp1VT = Tmp1.getValueType();
8172 if (Tmp1VT == WidenVT)
8175 unsigned Tmp1VTNumElts = Tmp1VT.getVectorNumElements();
8176 if (Tmp1VTNumElts < NewNumElts)
8177 Result = WidenVectorOp(Tmp1, WidenVT);
8179 Result = DAG.getNode(ISD::EXTRACT_SUBVECTOR, WidenVT, Tmp1, Idx);
8181 } else if (NewNumElts % NumElts == 0) {
8182 // Widen the extracted subvector.
8183 unsigned NumConcat = NewNumElts / NumElts;
8184 SDValue UndefVal = DAG.getNode(ISD::UNDEF, VT);
8185 SmallVector<SDValue, 8> MOps;
8187 for (unsigned i = 1; i != NumConcat; ++i) {
8188 MOps.push_back(UndefVal);
8190 Result = LegalizeOp(DAG.getNode(ISD::CONCAT_VECTORS, WidenVT,
8191 &MOps[0], MOps.size()));
8193 assert(0 && "can not widen extract subvector");
8194 // This could be implemented using insert and build vector but I would
8195 // like to see when this happens.
8201 // Determine new condition widen type and widen
8202 SDValue Cond1 = Node->getOperand(0);
8203 MVT CondVT = Cond1.getValueType();
8204 assert(CondVT.isVector() && "can not widen non vector type");
8205 MVT CondEVT = CondVT.getVectorElementType();
8206 MVT CondWidenVT = MVT::getVectorVT(CondEVT, NewNumElts);
8207 Cond1 = WidenVectorOp(Cond1, CondWidenVT);
8208 assert(Cond1.getValueType() == CondWidenVT && "Condition not widen");
8210 SDValue Tmp1 = WidenVectorOp(Node->getOperand(1), WidenVT);
8211 SDValue Tmp2 = WidenVectorOp(Node->getOperand(2), WidenVT);
8212 assert(Tmp1.getValueType() == WidenVT && Tmp2.getValueType() == WidenVT);
8213 Result = DAG.getNode(Node->getOpcode(), WidenVT, Cond1, Tmp1, Tmp2);
8217 case ISD::SELECT_CC: {
8218 // Determine new condition widen type and widen
8219 SDValue Cond1 = Node->getOperand(0);
8220 SDValue Cond2 = Node->getOperand(1);
8221 MVT CondVT = Cond1.getValueType();
8222 assert(CondVT.isVector() && "can not widen non vector type");
8223 assert(CondVT == Cond2.getValueType() && "mismatch lhs/rhs");
8224 MVT CondEVT = CondVT.getVectorElementType();
8225 MVT CondWidenVT = MVT::getVectorVT(CondEVT, NewNumElts);
8226 Cond1 = WidenVectorOp(Cond1, CondWidenVT);
8227 Cond2 = WidenVectorOp(Cond2, CondWidenVT);
8228 assert(Cond1.getValueType() == CondWidenVT &&
8229 Cond2.getValueType() == CondWidenVT && "condition not widen");
8231 SDValue Tmp1 = WidenVectorOp(Node->getOperand(2), WidenVT);
8232 SDValue Tmp2 = WidenVectorOp(Node->getOperand(3), WidenVT);
8233 assert(Tmp1.getValueType() == WidenVT && Tmp2.getValueType() == WidenVT &&
8234 "operands not widen");
8235 Result = DAG.getNode(Node->getOpcode(), WidenVT, Cond1, Cond2, Tmp1,
8236 Tmp2, Node->getOperand(4));
8240 // Determine widen for the operand
8241 SDValue Tmp1 = Node->getOperand(0);
8242 MVT TmpVT = Tmp1.getValueType();
8243 assert(TmpVT.isVector() && "can not widen non vector type");
8244 MVT TmpEVT = TmpVT.getVectorElementType();
8245 MVT TmpWidenVT = MVT::getVectorVT(TmpEVT, NewNumElts);
8246 Tmp1 = WidenVectorOp(Tmp1, TmpWidenVT);
8247 SDValue Tmp2 = WidenVectorOp(Node->getOperand(1), TmpWidenVT);
8248 Result = DAG.getNode(Node->getOpcode(), WidenVT, Tmp1, Tmp2,
8249 Node->getOperand(2));
8252 case ISD::ATOMIC_CMP_SWAP:
8253 case ISD::ATOMIC_LOAD_ADD:
8254 case ISD::ATOMIC_LOAD_SUB:
8255 case ISD::ATOMIC_LOAD_AND:
8256 case ISD::ATOMIC_LOAD_OR:
8257 case ISD::ATOMIC_LOAD_XOR:
8258 case ISD::ATOMIC_LOAD_NAND:
8259 case ISD::ATOMIC_LOAD_MIN:
8260 case ISD::ATOMIC_LOAD_MAX:
8261 case ISD::ATOMIC_LOAD_UMIN:
8262 case ISD::ATOMIC_LOAD_UMAX:
8263 case ISD::ATOMIC_SWAP: {
8264 // For now, we assume that using vectors for these operations don't make
8265 // much sense so we just split it. We return an empty result
8267 SplitVectorOp(Op, X, Y);
8272 } // end switch (Node->getOpcode())
8274 assert(Result.getNode() && "Didn't set a result!");
8276 Result = LegalizeOp(Result);
8278 AddWidenedOperand(Op, Result);
8282 // Utility function to find a legal vector type and its associated element
8283 // type from a preferred width and whose vector type must be the same size
8285 // TLI: Target lowering used to determine legal types
8286 // Width: Preferred width of element type
8287 // VVT: Vector value type whose size we must match.
8288 // Returns VecEVT and EVT - the vector type and its associated element type
8289 static void FindWidenVecType(TargetLowering &TLI, unsigned Width, MVT VVT,
8290 MVT& EVT, MVT& VecEVT) {
8291 // We start with the preferred width, make it a power of 2 and see if
8292 // we can find a vector type of that width. If not, we reduce it by
8293 // another power of 2. If we have widen the type, a vector of bytes should
8295 assert(TLI.isTypeLegal(VVT));
8296 unsigned EWidth = Width + 1;
8299 EWidth = (1 << Log2_32(EWidth-1));
8300 EVT = MVT::getIntegerVT(EWidth);
8301 unsigned NumEVT = VVT.getSizeInBits()/EWidth;
8302 VecEVT = MVT::getVectorVT(EVT, NumEVT);
8303 } while (!TLI.isTypeLegal(VecEVT) ||
8304 VVT.getSizeInBits() != VecEVT.getSizeInBits());
8307 SDValue SelectionDAGLegalize::genWidenVectorLoads(SDValueVector& LdChain,
8316 // We assume that we have good rules to handle loading power of two loads so
8317 // we break down the operations to power of 2 loads. The strategy is to
8318 // load the largest power of 2 that we can easily transform to a legal vector
8319 // and then insert into that vector, and the cast the result into the legal
8320 // vector that we want. This avoids unnecessary stack converts.
8321 // TODO: If the Ldwidth is legal, alignment is the same as the LdWidth, and
8322 // the load is nonvolatile, we an use a wider load for the value.
8323 // Find a vector length we can load a large chunk
8326 FindWidenVecType(TLI, LdWidth, ResType, EVT, VecEVT);
8327 EVTWidth = EVT.getSizeInBits();
8329 SDValue LdOp = DAG.getLoad(EVT, Chain, BasePtr, SV, SVOffset,
8330 isVolatile, Alignment);
8331 SDValue VecOp = DAG.getNode(ISD::SCALAR_TO_VECTOR, VecEVT, LdOp);
8332 LdChain.push_back(LdOp.getValue(1));
8334 // Check if we can load the element with one instruction
8335 if (LdWidth == EVTWidth) {
8336 return DAG.getNode(ISD::BIT_CONVERT, ResType, VecOp);
8339 // The vector element order is endianness dependent.
8341 LdWidth -= EVTWidth;
8342 unsigned Offset = 0;
8344 while (LdWidth > 0) {
8345 unsigned Increment = EVTWidth / 8;
8346 Offset += Increment;
8347 BasePtr = DAG.getNode(ISD::ADD, BasePtr.getValueType(), BasePtr,
8348 DAG.getIntPtrConstant(Increment));
8350 if (LdWidth < EVTWidth) {
8351 // Our current type we are using is too large, use a smaller size by
8352 // using a smaller power of 2
8353 unsigned oEVTWidth = EVTWidth;
8354 FindWidenVecType(TLI, LdWidth, ResType, EVT, VecEVT);
8355 EVTWidth = EVT.getSizeInBits();
8356 // Readjust position and vector position based on new load type
8357 Idx = Idx * (oEVTWidth/EVTWidth);
8358 VecOp = DAG.getNode(ISD::BIT_CONVERT, VecEVT, VecOp);
8361 SDValue LdOp = DAG.getLoad(EVT, Chain, BasePtr, SV,
8362 SVOffset+Offset, isVolatile,
8363 MinAlign(Alignment, Offset));
8364 LdChain.push_back(LdOp.getValue(1));
8365 VecOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, VecEVT, VecOp, LdOp,
8366 DAG.getIntPtrConstant(Idx++));
8368 LdWidth -= EVTWidth;
8371 return DAG.getNode(ISD::BIT_CONVERT, ResType, VecOp);
8374 bool SelectionDAGLegalize::LoadWidenVectorOp(SDValue& Result,
8378 // TODO: Add support for ConcatVec and the ability to load many vector
8379 // types (e.g., v4i8). This will not work when a vector register
8380 // to memory mapping is strange (e.g., vector elements are not
8381 // stored in some sequential order).
8383 // It must be true that the widen vector type is bigger than where
8384 // we need to load from.
8385 LoadSDNode *LD = cast<LoadSDNode>(Op.getNode());
8386 MVT LdVT = LD->getMemoryVT();
8387 assert(LdVT.isVector() && NVT.isVector());
8388 assert(LdVT.getVectorElementType() == NVT.getVectorElementType());
8391 SDValue Chain = LD->getChain();
8392 SDValue BasePtr = LD->getBasePtr();
8393 int SVOffset = LD->getSrcValueOffset();
8394 unsigned Alignment = LD->getAlignment();
8395 bool isVolatile = LD->isVolatile();
8396 const Value *SV = LD->getSrcValue();
8397 unsigned int LdWidth = LdVT.getSizeInBits();
8399 // Load value as a large register
8400 SDValueVector LdChain;
8401 Result = genWidenVectorLoads(LdChain, Chain, BasePtr, SV, SVOffset,
8402 Alignment, isVolatile, LdWidth, NVT);
8404 if (LdChain.size() == 1) {
8409 TFOp=DAG.getNode(ISD::TokenFactor, MVT::Other, &LdChain[0], LdChain.size());
8415 void SelectionDAGLegalize::genWidenVectorStores(SDValueVector& StChain,
8424 // Breaks the stores into a series of power of 2 width stores. For any
8425 // width, we convert the vector to the vector of element size that we
8426 // want to store. This avoids requiring a stack convert.
8428 // Find a width of the element type we can store with
8429 MVT VVT = ValOp.getValueType();
8432 FindWidenVecType(TLI, StWidth, VVT, EVT, VecEVT);
8433 EVTWidth = EVT.getSizeInBits();
8435 SDValue VecOp = DAG.getNode(ISD::BIT_CONVERT, VecEVT, ValOp);
8436 SDValue EOp = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EVT, VecOp,
8437 DAG.getIntPtrConstant(0));
8438 SDValue StOp = DAG.getStore(Chain, EOp, BasePtr, SV, SVOffset,
8439 isVolatile, Alignment);
8440 StChain.push_back(StOp);
8442 // Check if we are done
8443 if (StWidth == EVTWidth) {
8448 StWidth -= EVTWidth;
8449 unsigned Offset = 0;
8451 while (StWidth > 0) {
8452 unsigned Increment = EVTWidth / 8;
8453 Offset += Increment;
8454 BasePtr = DAG.getNode(ISD::ADD, BasePtr.getValueType(), BasePtr,
8455 DAG.getIntPtrConstant(Increment));
8457 if (StWidth < EVTWidth) {
8458 // Our current type we are using is too large, use a smaller size by
8459 // using a smaller power of 2
8460 unsigned oEVTWidth = EVTWidth;
8461 FindWidenVecType(TLI, StWidth, VVT, EVT, VecEVT);
8462 EVTWidth = EVT.getSizeInBits();
8463 // Readjust position and vector position based on new load type
8464 Idx = Idx * (oEVTWidth/EVTWidth);
8465 VecOp = DAG.getNode(ISD::BIT_CONVERT, VecEVT, VecOp);
8468 EOp = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EVT, VecOp,
8469 DAG.getIntPtrConstant(Idx++));
8470 StChain.push_back(DAG.getStore(Chain, EOp, BasePtr, SV,
8471 SVOffset + Offset, isVolatile,
8472 MinAlign(Alignment, Offset)));
8473 StWidth -= EVTWidth;
8478 SDValue SelectionDAGLegalize::StoreWidenVectorOp(StoreSDNode *ST,
8481 // TODO: It might be cleaner if we can use SplitVector and have more legal
8482 // vector types that can be stored into memory (e.g., v4xi8 can
8483 // be stored as a word). This will not work when a vector register
8484 // to memory mapping is strange (e.g., vector elements are not
8485 // stored in some sequential order).
8487 MVT StVT = ST->getMemoryVT();
8488 SDValue ValOp = ST->getValue();
8490 // Check if we have widen this node with another value
8491 std::map<SDValue, SDValue>::iterator I = WidenNodes.find(ValOp);
8492 if (I != WidenNodes.end())
8495 MVT VVT = ValOp.getValueType();
8497 // It must be true that we the widen vector type is bigger than where
8498 // we need to store.
8499 assert(StVT.isVector() && VVT.isVector());
8500 assert(StVT.getSizeInBits() < VVT.getSizeInBits());
8501 assert(StVT.getVectorElementType() == VVT.getVectorElementType());
8504 SDValueVector StChain;
8505 genWidenVectorStores(StChain, Chain, BasePtr, ST->getSrcValue(),
8506 ST->getSrcValueOffset(), ST->getAlignment(),
8507 ST->isVolatile(), ValOp, StVT.getSizeInBits());
8508 if (StChain.size() == 1)
8511 return DAG.getNode(ISD::TokenFactor, MVT::Other,&StChain[0],StChain.size());
8515 // SelectionDAG::Legalize - This is the entry point for the file.
8517 void SelectionDAG::Legalize(bool TypesNeedLegalizing) {
8518 /// run - This is the main entry point to this class.
8520 SelectionDAGLegalize(*this, TypesNeedLegalizing).LegalizeDAG();