1 //===-- LegalizeDAG.cpp - Implement SelectionDAG::Legalize ----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the SelectionDAG::Legalize method.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/CodeGen/SelectionDAG.h"
15 #include "llvm/CodeGen/MachineFunction.h"
16 #include "llvm/CodeGen/MachineFrameInfo.h"
17 #include "llvm/CodeGen/MachineJumpTableInfo.h"
18 #include "llvm/Target/TargetFrameInfo.h"
19 #include "llvm/Target/TargetLowering.h"
20 #include "llvm/Target/TargetData.h"
21 #include "llvm/Target/TargetMachine.h"
22 #include "llvm/Target/TargetOptions.h"
23 #include "llvm/CallingConv.h"
24 #include "llvm/Constants.h"
25 #include "llvm/DerivedTypes.h"
26 #include "llvm/Support/CommandLine.h"
27 #include "llvm/Support/Compiler.h"
28 #include "llvm/Support/MathExtras.h"
29 #include "llvm/ADT/DenseMap.h"
30 #include "llvm/ADT/SmallVector.h"
31 #include "llvm/ADT/SmallPtrSet.h"
37 ViewLegalizeDAGs("view-legalize-dags", cl::Hidden,
38 cl::desc("Pop up a window to show dags before legalize"));
40 static const bool ViewLegalizeDAGs = 0;
43 //===----------------------------------------------------------------------===//
44 /// SelectionDAGLegalize - This takes an arbitrary SelectionDAG as input and
45 /// hacks on it until the target machine can handle it. This involves
46 /// eliminating value sizes the machine cannot handle (promoting small sizes to
47 /// large sizes or splitting up large values into small values) as well as
48 /// eliminating operations the machine cannot handle.
50 /// This code also does a small amount of optimization and recognition of idioms
51 /// as part of its processing. For example, if a target does not support a
52 /// 'setcc' instruction efficiently, but does support 'brcc' instruction, this
53 /// will attempt merge setcc and brc instructions into brcc's.
56 class VISIBILITY_HIDDEN SelectionDAGLegalize {
60 // Libcall insertion helpers.
62 /// LastCALLSEQ_END - This keeps track of the CALLSEQ_END node that has been
63 /// legalized. We use this to ensure that calls are properly serialized
64 /// against each other, including inserted libcalls.
65 SDOperand LastCALLSEQ_END;
67 /// IsLegalizingCall - This member is used *only* for purposes of providing
68 /// helpful assertions that a libcall isn't created while another call is
69 /// being legalized (which could lead to non-serialized call sequences).
70 bool IsLegalizingCall;
73 Legal, // The target natively supports this operation.
74 Promote, // This operation should be executed in a larger type.
75 Expand // Try to expand this to other ops, otherwise use a libcall.
78 /// ValueTypeActions - This is a bitvector that contains two bits for each
79 /// value type, where the two bits correspond to the LegalizeAction enum.
80 /// This can be queried with "getTypeAction(VT)".
81 TargetLowering::ValueTypeActionImpl ValueTypeActions;
83 /// LegalizedNodes - For nodes that are of legal width, and that have more
84 /// than one use, this map indicates what regularized operand to use. This
85 /// allows us to avoid legalizing the same thing more than once.
86 DenseMap<SDOperand, SDOperand> LegalizedNodes;
88 /// PromotedNodes - For nodes that are below legal width, and that have more
89 /// than one use, this map indicates what promoted value to use. This allows
90 /// us to avoid promoting the same thing more than once.
91 DenseMap<SDOperand, SDOperand> PromotedNodes;
93 /// ExpandedNodes - For nodes that need to be expanded this map indicates
94 /// which which operands are the expanded version of the input. This allows
95 /// us to avoid expanding the same node more than once.
96 DenseMap<SDOperand, std::pair<SDOperand, SDOperand> > ExpandedNodes;
98 /// SplitNodes - For vector nodes that need to be split, this map indicates
99 /// which which operands are the split version of the input. This allows us
100 /// to avoid splitting the same node more than once.
101 std::map<SDOperand, std::pair<SDOperand, SDOperand> > SplitNodes;
103 /// ScalarizedNodes - For nodes that need to be converted from vector types to
104 /// scalar types, this contains the mapping of ones we have already
105 /// processed to the result.
106 std::map<SDOperand, SDOperand> ScalarizedNodes;
108 void AddLegalizedOperand(SDOperand From, SDOperand To) {
109 LegalizedNodes.insert(std::make_pair(From, To));
110 // If someone requests legalization of the new node, return itself.
112 LegalizedNodes.insert(std::make_pair(To, To));
114 void AddPromotedOperand(SDOperand From, SDOperand To) {
115 bool isNew = PromotedNodes.insert(std::make_pair(From, To));
116 assert(isNew && "Got into the map somehow?");
117 // If someone requests legalization of the new node, return itself.
118 LegalizedNodes.insert(std::make_pair(To, To));
123 SelectionDAGLegalize(SelectionDAG &DAG);
125 /// getTypeAction - Return how we should legalize values of this type, either
126 /// it is already legal or we need to expand it into multiple registers of
127 /// smaller integer type, or we need to promote it to a larger type.
128 LegalizeAction getTypeAction(MVT::ValueType VT) const {
129 return (LegalizeAction)ValueTypeActions.getTypeAction(VT);
132 /// isTypeLegal - Return true if this type is legal on this target.
134 bool isTypeLegal(MVT::ValueType VT) const {
135 return getTypeAction(VT) == Legal;
141 /// HandleOp - Legalize, Promote, or Expand the specified operand as
142 /// appropriate for its type.
143 void HandleOp(SDOperand Op);
145 /// LegalizeOp - We know that the specified value has a legal type.
146 /// Recursively ensure that the operands have legal types, then return the
148 SDOperand LegalizeOp(SDOperand O);
150 /// UnrollVectorOp - We know that the given vector has a legal type, however
151 /// the operation it performs is not legal and is an operation that we have
152 /// no way of lowering. "Unroll" the vector, splitting out the scalars and
153 /// operating on each element individually.
154 SDOperand UnrollVectorOp(SDOperand O);
156 /// PromoteOp - Given an operation that produces a value in an invalid type,
157 /// promote it to compute the value into a larger type. The produced value
158 /// will have the correct bits for the low portion of the register, but no
159 /// guarantee is made about the top bits: it may be zero, sign-extended, or
161 SDOperand PromoteOp(SDOperand O);
163 /// ExpandOp - Expand the specified SDOperand into its two component pieces
164 /// Lo&Hi. Note that the Op MUST be an expanded type. As a result of this,
165 /// the LegalizeNodes map is filled in for any results that are not expanded,
166 /// the ExpandedNodes map is filled in for any results that are expanded, and
167 /// the Lo/Hi values are returned. This applies to integer types and Vector
169 void ExpandOp(SDOperand O, SDOperand &Lo, SDOperand &Hi);
171 /// SplitVectorOp - Given an operand of vector type, break it down into
172 /// two smaller values.
173 void SplitVectorOp(SDOperand O, SDOperand &Lo, SDOperand &Hi);
175 /// ScalarizeVectorOp - Given an operand of single-element vector type
176 /// (e.g. v1f32), convert it into the equivalent operation that returns a
177 /// scalar (e.g. f32) value.
178 SDOperand ScalarizeVectorOp(SDOperand O);
180 /// isShuffleLegal - Return true if a vector shuffle is legal with the
181 /// specified mask and type. Targets can specify exactly which masks they
182 /// support and the code generator is tasked with not creating illegal masks.
184 /// Note that this will also return true for shuffles that are promoted to a
187 /// If this is a legal shuffle, this method returns the (possibly promoted)
188 /// build_vector Mask. If it's not a legal shuffle, it returns null.
189 SDNode *isShuffleLegal(MVT::ValueType VT, SDOperand Mask) const;
191 bool LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest,
192 SmallPtrSet<SDNode*, 32> &NodesLeadingTo);
194 void LegalizeSetCCOperands(SDOperand &LHS, SDOperand &RHS, SDOperand &CC);
196 SDOperand ExpandLibCall(const char *Name, SDNode *Node, bool isSigned,
198 SDOperand ExpandIntToFP(bool isSigned, MVT::ValueType DestTy,
201 SDOperand ExpandBIT_CONVERT(MVT::ValueType DestVT, SDOperand SrcOp);
202 SDOperand ExpandBUILD_VECTOR(SDNode *Node);
203 SDOperand ExpandSCALAR_TO_VECTOR(SDNode *Node);
204 SDOperand ExpandLegalINT_TO_FP(bool isSigned,
206 MVT::ValueType DestVT);
207 SDOperand PromoteLegalINT_TO_FP(SDOperand LegalOp, MVT::ValueType DestVT,
209 SDOperand PromoteLegalFP_TO_INT(SDOperand LegalOp, MVT::ValueType DestVT,
212 SDOperand ExpandBSWAP(SDOperand Op);
213 SDOperand ExpandBitCount(unsigned Opc, SDOperand Op);
214 bool ExpandShift(unsigned Opc, SDOperand Op, SDOperand Amt,
215 SDOperand &Lo, SDOperand &Hi);
216 void ExpandShiftParts(unsigned NodeOp, SDOperand Op, SDOperand Amt,
217 SDOperand &Lo, SDOperand &Hi);
219 SDOperand ExpandEXTRACT_SUBVECTOR(SDOperand Op);
220 SDOperand ExpandEXTRACT_VECTOR_ELT(SDOperand Op);
222 SDOperand getIntPtrConstant(uint64_t Val) {
223 return DAG.getConstant(Val, TLI.getPointerTy());
228 /// isVectorShuffleLegal - Return true if a vector shuffle is legal with the
229 /// specified mask and type. Targets can specify exactly which masks they
230 /// support and the code generator is tasked with not creating illegal masks.
232 /// Note that this will also return true for shuffles that are promoted to a
234 SDNode *SelectionDAGLegalize::isShuffleLegal(MVT::ValueType VT,
235 SDOperand Mask) const {
236 switch (TLI.getOperationAction(ISD::VECTOR_SHUFFLE, VT)) {
238 case TargetLowering::Legal:
239 case TargetLowering::Custom:
241 case TargetLowering::Promote: {
242 // If this is promoted to a different type, convert the shuffle mask and
243 // ask if it is legal in the promoted type!
244 MVT::ValueType NVT = TLI.getTypeToPromoteTo(ISD::VECTOR_SHUFFLE, VT);
246 // If we changed # elements, change the shuffle mask.
247 unsigned NumEltsGrowth =
248 MVT::getVectorNumElements(NVT) / MVT::getVectorNumElements(VT);
249 assert(NumEltsGrowth && "Cannot promote to vector type with fewer elts!");
250 if (NumEltsGrowth > 1) {
251 // Renumber the elements.
252 SmallVector<SDOperand, 8> Ops;
253 for (unsigned i = 0, e = Mask.getNumOperands(); i != e; ++i) {
254 SDOperand InOp = Mask.getOperand(i);
255 for (unsigned j = 0; j != NumEltsGrowth; ++j) {
256 if (InOp.getOpcode() == ISD::UNDEF)
257 Ops.push_back(DAG.getNode(ISD::UNDEF, MVT::i32));
259 unsigned InEltNo = cast<ConstantSDNode>(InOp)->getValue();
260 Ops.push_back(DAG.getConstant(InEltNo*NumEltsGrowth+j, MVT::i32));
264 Mask = DAG.getNode(ISD::BUILD_VECTOR, NVT, &Ops[0], Ops.size());
270 return TLI.isShuffleMaskLegal(Mask, VT) ? Mask.Val : 0;
273 SelectionDAGLegalize::SelectionDAGLegalize(SelectionDAG &dag)
274 : TLI(dag.getTargetLoweringInfo()), DAG(dag),
275 ValueTypeActions(TLI.getValueTypeActions()) {
276 assert(MVT::LAST_VALUETYPE <= 32 &&
277 "Too many value types for ValueTypeActions to hold!");
280 /// ComputeTopDownOrdering - Compute a top-down ordering of the dag, where Order
281 /// contains all of a nodes operands before it contains the node.
282 static void ComputeTopDownOrdering(SelectionDAG &DAG,
283 SmallVector<SDNode*, 64> &Order) {
285 DenseMap<SDNode*, unsigned> Visited;
286 std::vector<SDNode*> Worklist;
287 Worklist.reserve(128);
289 // Compute ordering from all of the leaves in the graphs, those (like the
290 // entry node) that have no operands.
291 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(),
292 E = DAG.allnodes_end(); I != E; ++I) {
293 if (I->getNumOperands() == 0) {
295 Worklist.push_back(I);
299 while (!Worklist.empty()) {
300 SDNode *N = Worklist.back();
303 if (++Visited[N] != N->getNumOperands())
304 continue; // Haven't visited all operands yet
308 // Now that we have N in, add anything that uses it if all of their operands
310 for (SDNode::use_iterator UI = N->use_begin(), E = N->use_end();
312 Worklist.push_back(*UI);
315 assert(Order.size() == Visited.size() &&
317 (unsigned)std::distance(DAG.allnodes_begin(), DAG.allnodes_end()) &&
318 "Error: DAG is cyclic!");
322 void SelectionDAGLegalize::LegalizeDAG() {
323 LastCALLSEQ_END = DAG.getEntryNode();
324 IsLegalizingCall = false;
326 // The legalize process is inherently a bottom-up recursive process (users
327 // legalize their uses before themselves). Given infinite stack space, we
328 // could just start legalizing on the root and traverse the whole graph. In
329 // practice however, this causes us to run out of stack space on large basic
330 // blocks. To avoid this problem, compute an ordering of the nodes where each
331 // node is only legalized after all of its operands are legalized.
332 SmallVector<SDNode*, 64> Order;
333 ComputeTopDownOrdering(DAG, Order);
335 for (unsigned i = 0, e = Order.size(); i != e; ++i)
336 HandleOp(SDOperand(Order[i], 0));
338 // Finally, it's possible the root changed. Get the new root.
339 SDOperand OldRoot = DAG.getRoot();
340 assert(LegalizedNodes.count(OldRoot) && "Root didn't get legalized?");
341 DAG.setRoot(LegalizedNodes[OldRoot]);
343 ExpandedNodes.clear();
344 LegalizedNodes.clear();
345 PromotedNodes.clear();
347 ScalarizedNodes.clear();
349 // Remove dead nodes now.
350 DAG.RemoveDeadNodes();
354 /// FindCallEndFromCallStart - Given a chained node that is part of a call
355 /// sequence, find the CALLSEQ_END node that terminates the call sequence.
356 static SDNode *FindCallEndFromCallStart(SDNode *Node) {
357 if (Node->getOpcode() == ISD::CALLSEQ_END)
359 if (Node->use_empty())
360 return 0; // No CallSeqEnd
362 // The chain is usually at the end.
363 SDOperand TheChain(Node, Node->getNumValues()-1);
364 if (TheChain.getValueType() != MVT::Other) {
365 // Sometimes it's at the beginning.
366 TheChain = SDOperand(Node, 0);
367 if (TheChain.getValueType() != MVT::Other) {
368 // Otherwise, hunt for it.
369 for (unsigned i = 1, e = Node->getNumValues(); i != e; ++i)
370 if (Node->getValueType(i) == MVT::Other) {
371 TheChain = SDOperand(Node, i);
375 // Otherwise, we walked into a node without a chain.
376 if (TheChain.getValueType() != MVT::Other)
381 for (SDNode::use_iterator UI = Node->use_begin(),
382 E = Node->use_end(); UI != E; ++UI) {
384 // Make sure to only follow users of our token chain.
386 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i)
387 if (User->getOperand(i) == TheChain)
388 if (SDNode *Result = FindCallEndFromCallStart(User))
394 /// FindCallStartFromCallEnd - Given a chained node that is part of a call
395 /// sequence, find the CALLSEQ_START node that initiates the call sequence.
396 static SDNode *FindCallStartFromCallEnd(SDNode *Node) {
397 assert(Node && "Didn't find callseq_start for a call??");
398 if (Node->getOpcode() == ISD::CALLSEQ_START) return Node;
400 assert(Node->getOperand(0).getValueType() == MVT::Other &&
401 "Node doesn't have a token chain argument!");
402 return FindCallStartFromCallEnd(Node->getOperand(0).Val);
405 /// LegalizeAllNodesNotLeadingTo - Recursively walk the uses of N, looking to
406 /// see if any uses can reach Dest. If no dest operands can get to dest,
407 /// legalize them, legalize ourself, and return false, otherwise, return true.
409 /// Keep track of the nodes we fine that actually do lead to Dest in
410 /// NodesLeadingTo. This avoids retraversing them exponential number of times.
412 bool SelectionDAGLegalize::LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest,
413 SmallPtrSet<SDNode*, 32> &NodesLeadingTo) {
414 if (N == Dest) return true; // N certainly leads to Dest :)
416 // If we've already processed this node and it does lead to Dest, there is no
417 // need to reprocess it.
418 if (NodesLeadingTo.count(N)) return true;
420 // If the first result of this node has been already legalized, then it cannot
422 switch (getTypeAction(N->getValueType(0))) {
424 if (LegalizedNodes.count(SDOperand(N, 0))) return false;
427 if (PromotedNodes.count(SDOperand(N, 0))) return false;
430 if (ExpandedNodes.count(SDOperand(N, 0))) return false;
434 // Okay, this node has not already been legalized. Check and legalize all
435 // operands. If none lead to Dest, then we can legalize this node.
436 bool OperandsLeadToDest = false;
437 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
438 OperandsLeadToDest |= // If an operand leads to Dest, so do we.
439 LegalizeAllNodesNotLeadingTo(N->getOperand(i).Val, Dest, NodesLeadingTo);
441 if (OperandsLeadToDest) {
442 NodesLeadingTo.insert(N);
446 // Okay, this node looks safe, legalize it and return false.
447 HandleOp(SDOperand(N, 0));
451 /// HandleOp - Legalize, Promote, or Expand the specified operand as
452 /// appropriate for its type.
453 void SelectionDAGLegalize::HandleOp(SDOperand Op) {
454 MVT::ValueType VT = Op.getValueType();
455 switch (getTypeAction(VT)) {
456 default: assert(0 && "Bad type action!");
457 case Legal: (void)LegalizeOp(Op); break;
458 case Promote: (void)PromoteOp(Op); break;
460 if (!MVT::isVector(VT)) {
461 // If this is an illegal scalar, expand it into its two component
464 if (Op.getOpcode() == ISD::TargetConstant)
465 break; // Allow illegal target nodes.
467 } else if (MVT::getVectorNumElements(VT) == 1) {
468 // If this is an illegal single element vector, convert it to a
470 (void)ScalarizeVectorOp(Op);
472 // Otherwise, this is an illegal multiple element vector.
473 // Split it in half and legalize both parts.
475 SplitVectorOp(Op, X, Y);
481 /// ExpandConstantFP - Expands the ConstantFP node to an integer constant or
482 /// a load from the constant pool.
483 static SDOperand ExpandConstantFP(ConstantFPSDNode *CFP, bool UseCP,
484 SelectionDAG &DAG, TargetLowering &TLI) {
487 // If a FP immediate is precise when represented as a float and if the
488 // target can do an extending load from float to double, we put it into
489 // the constant pool as a float, even if it's is statically typed as a
491 MVT::ValueType VT = CFP->getValueType(0);
492 bool isDouble = VT == MVT::f64;
493 ConstantFP *LLVMC = ConstantFP::get(MVT::getTypeForValueType(VT),
496 if (VT!=MVT::f64 && VT!=MVT::f32)
497 assert(0 && "Invalid type expansion");
498 return DAG.getConstant(LLVMC->getValueAPF().convertToAPInt().getZExtValue(),
499 isDouble ? MVT::i64 : MVT::i32);
502 if (isDouble && CFP->isValueValidForType(MVT::f32, CFP->getValueAPF()) &&
503 // Only do this if the target has a native EXTLOAD instruction from f32.
504 // Do not try to be clever about long doubles (so far)
505 TLI.isLoadXLegal(ISD::EXTLOAD, MVT::f32)) {
506 LLVMC = cast<ConstantFP>(ConstantExpr::getFPTrunc(LLVMC,Type::FloatTy));
511 SDOperand CPIdx = DAG.getConstantPool(LLVMC, TLI.getPointerTy());
513 return DAG.getExtLoad(ISD::EXTLOAD, MVT::f64, DAG.getEntryNode(),
514 CPIdx, NULL, 0, MVT::f32);
516 return DAG.getLoad(VT, DAG.getEntryNode(), CPIdx, NULL, 0);
521 /// ExpandFCOPYSIGNToBitwiseOps - Expands fcopysign to a series of bitwise
524 SDOperand ExpandFCOPYSIGNToBitwiseOps(SDNode *Node, MVT::ValueType NVT,
525 SelectionDAG &DAG, TargetLowering &TLI) {
526 MVT::ValueType VT = Node->getValueType(0);
527 MVT::ValueType SrcVT = Node->getOperand(1).getValueType();
528 assert((SrcVT == MVT::f32 || SrcVT == MVT::f64) &&
529 "fcopysign expansion only supported for f32 and f64");
530 MVT::ValueType SrcNVT = (SrcVT == MVT::f64) ? MVT::i64 : MVT::i32;
532 // First get the sign bit of second operand.
533 SDOperand Mask1 = (SrcVT == MVT::f64)
534 ? DAG.getConstantFP(BitsToDouble(1ULL << 63), SrcVT)
535 : DAG.getConstantFP(BitsToFloat(1U << 31), SrcVT);
536 Mask1 = DAG.getNode(ISD::BIT_CONVERT, SrcNVT, Mask1);
537 SDOperand SignBit= DAG.getNode(ISD::BIT_CONVERT, SrcNVT, Node->getOperand(1));
538 SignBit = DAG.getNode(ISD::AND, SrcNVT, SignBit, Mask1);
539 // Shift right or sign-extend it if the two operands have different types.
540 int SizeDiff = MVT::getSizeInBits(SrcNVT) - MVT::getSizeInBits(NVT);
542 SignBit = DAG.getNode(ISD::SRL, SrcNVT, SignBit,
543 DAG.getConstant(SizeDiff, TLI.getShiftAmountTy()));
544 SignBit = DAG.getNode(ISD::TRUNCATE, NVT, SignBit);
545 } else if (SizeDiff < 0)
546 SignBit = DAG.getNode(ISD::SIGN_EXTEND, NVT, SignBit);
548 // Clear the sign bit of first operand.
549 SDOperand Mask2 = (VT == MVT::f64)
550 ? DAG.getConstantFP(BitsToDouble(~(1ULL << 63)), VT)
551 : DAG.getConstantFP(BitsToFloat(~(1U << 31)), VT);
552 Mask2 = DAG.getNode(ISD::BIT_CONVERT, NVT, Mask2);
553 SDOperand Result = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0));
554 Result = DAG.getNode(ISD::AND, NVT, Result, Mask2);
556 // Or the value with the sign bit.
557 Result = DAG.getNode(ISD::OR, NVT, Result, SignBit);
561 /// ExpandUnalignedStore - Expands an unaligned store to 2 half-size stores.
563 SDOperand ExpandUnalignedStore(StoreSDNode *ST, SelectionDAG &DAG,
564 TargetLowering &TLI) {
565 SDOperand Chain = ST->getChain();
566 SDOperand Ptr = ST->getBasePtr();
567 SDOperand Val = ST->getValue();
568 MVT::ValueType VT = Val.getValueType();
569 int Alignment = ST->getAlignment();
570 int SVOffset = ST->getSrcValueOffset();
571 if (MVT::isFloatingPoint(ST->getStoredVT())) {
572 // Expand to a bitconvert of the value to the integer type of the
573 // same size, then a (misaligned) int store.
574 MVT::ValueType intVT;
577 else if (VT==MVT::f32)
580 assert(0 && "Unaligned load of unsupported floating point type");
582 SDOperand Result = DAG.getNode(ISD::BIT_CONVERT, intVT, Val);
583 return DAG.getStore(Chain, Result, Ptr, ST->getSrcValue(),
584 SVOffset, ST->isVolatile(), Alignment);
586 assert(MVT::isInteger(ST->getStoredVT()) &&
587 "Unaligned store of unknown type.");
588 // Get the half-size VT
589 MVT::ValueType NewStoredVT = ST->getStoredVT() - 1;
590 int NumBits = MVT::getSizeInBits(NewStoredVT);
591 int IncrementSize = NumBits / 8;
593 // Divide the stored value in two parts.
594 SDOperand ShiftAmount = DAG.getConstant(NumBits, TLI.getShiftAmountTy());
596 SDOperand Hi = DAG.getNode(ISD::SRL, VT, Val, ShiftAmount);
598 // Store the two parts
599 SDOperand Store1, Store2;
600 Store1 = DAG.getTruncStore(Chain, TLI.isLittleEndian()?Lo:Hi, Ptr,
601 ST->getSrcValue(), SVOffset, NewStoredVT,
602 ST->isVolatile(), Alignment);
603 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
604 DAG.getConstant(IncrementSize, TLI.getPointerTy()));
605 Alignment = MinAlign(Alignment, IncrementSize);
606 Store2 = DAG.getTruncStore(Chain, TLI.isLittleEndian()?Hi:Lo, Ptr,
607 ST->getSrcValue(), SVOffset + IncrementSize,
608 NewStoredVT, ST->isVolatile(), Alignment);
610 return DAG.getNode(ISD::TokenFactor, MVT::Other, Store1, Store2);
613 /// ExpandUnalignedLoad - Expands an unaligned load to 2 half-size loads.
615 SDOperand ExpandUnalignedLoad(LoadSDNode *LD, SelectionDAG &DAG,
616 TargetLowering &TLI) {
617 int SVOffset = LD->getSrcValueOffset();
618 SDOperand Chain = LD->getChain();
619 SDOperand Ptr = LD->getBasePtr();
620 MVT::ValueType VT = LD->getValueType(0);
621 MVT::ValueType LoadedVT = LD->getLoadedVT();
622 if (MVT::isFloatingPoint(VT)) {
623 // Expand to a (misaligned) integer load of the same size,
624 // then bitconvert to floating point.
625 MVT::ValueType intVT;
626 if (LoadedVT==MVT::f64)
628 else if (LoadedVT==MVT::f32)
631 assert(0 && "Unaligned load of unsupported floating point type");
633 SDOperand newLoad = DAG.getLoad(intVT, Chain, Ptr, LD->getSrcValue(),
634 SVOffset, LD->isVolatile(),
636 SDOperand Result = DAG.getNode(ISD::BIT_CONVERT, LoadedVT, newLoad);
638 Result = DAG.getNode(ISD::FP_EXTEND, VT, Result);
640 SDOperand Ops[] = { Result, Chain };
641 return DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(VT, MVT::Other),
644 assert(MVT::isInteger(LoadedVT) && "Unaligned load of unsupported type.");
645 MVT::ValueType NewLoadedVT = LoadedVT - 1;
646 int NumBits = MVT::getSizeInBits(NewLoadedVT);
647 int Alignment = LD->getAlignment();
648 int IncrementSize = NumBits / 8;
649 ISD::LoadExtType HiExtType = LD->getExtensionType();
651 // If the original load is NON_EXTLOAD, the hi part load must be ZEXTLOAD.
652 if (HiExtType == ISD::NON_EXTLOAD)
653 HiExtType = ISD::ZEXTLOAD;
655 // Load the value in two parts
657 if (TLI.isLittleEndian()) {
658 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, VT, Chain, Ptr, LD->getSrcValue(),
659 SVOffset, NewLoadedVT, LD->isVolatile(), Alignment);
660 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
661 DAG.getConstant(IncrementSize, TLI.getPointerTy()));
662 Hi = DAG.getExtLoad(HiExtType, VT, Chain, Ptr, LD->getSrcValue(),
663 SVOffset + IncrementSize, NewLoadedVT, LD->isVolatile(),
664 MinAlign(Alignment, IncrementSize));
666 Hi = DAG.getExtLoad(HiExtType, VT, Chain, Ptr, LD->getSrcValue(), SVOffset,
667 NewLoadedVT,LD->isVolatile(), Alignment);
668 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
669 DAG.getConstant(IncrementSize, TLI.getPointerTy()));
670 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, VT, Chain, Ptr, LD->getSrcValue(),
671 SVOffset + IncrementSize, NewLoadedVT, LD->isVolatile(),
672 MinAlign(Alignment, IncrementSize));
675 // aggregate the two parts
676 SDOperand ShiftAmount = DAG.getConstant(NumBits, TLI.getShiftAmountTy());
677 SDOperand Result = DAG.getNode(ISD::SHL, VT, Hi, ShiftAmount);
678 Result = DAG.getNode(ISD::OR, VT, Result, Lo);
680 SDOperand TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
683 SDOperand Ops[] = { Result, TF };
684 return DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(VT, MVT::Other), Ops, 2);
687 /// UnrollVectorOp - We know that the given vector has a legal type, however
688 /// the operation it performs is not legal and is an operation that we have
689 /// no way of lowering. "Unroll" the vector, splitting out the scalars and
690 /// operating on each element individually.
691 SDOperand SelectionDAGLegalize::UnrollVectorOp(SDOperand Op) {
692 MVT::ValueType VT = Op.getValueType();
693 assert(isTypeLegal(VT) &&
694 "Caller should expand or promote operands that are not legal!");
695 assert(Op.Val->getNumValues() == 1 &&
696 "Can't unroll a vector with multiple results!");
697 unsigned NE = MVT::getVectorNumElements(VT);
698 MVT::ValueType EltVT = MVT::getVectorElementType(VT);
700 SmallVector<SDOperand, 8> Scalars;
701 SmallVector<SDOperand, 4> Operands(Op.getNumOperands());
702 for (unsigned i = 0; i != NE; ++i) {
703 for (unsigned j = 0; j != Op.getNumOperands(); ++j) {
704 SDOperand Operand = Op.getOperand(j);
705 MVT::ValueType OperandVT = Operand.getValueType();
706 if (MVT::isVector(OperandVT)) {
707 // A vector operand; extract a single element.
708 MVT::ValueType OperandEltVT = MVT::getVectorElementType(OperandVT);
709 Operands[j] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT,
712 DAG.getConstant(i, MVT::i32));
714 // A scalar operand; just use it as is.
715 Operands[j] = Operand;
718 Scalars.push_back(DAG.getNode(Op.getOpcode(), EltVT,
719 &Operands[0], Operands.size()));
722 return DAG.getNode(ISD::BUILD_VECTOR, VT, &Scalars[0], Scalars.size());
725 /// LegalizeOp - We know that the specified value has a legal type, and
726 /// that its operands are legal. Now ensure that the operation itself
727 /// is legal, recursively ensuring that the operands' operations remain
729 SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
730 if (Op.getOpcode() == ISD::TargetConstant) // Allow illegal target nodes.
733 assert(isTypeLegal(Op.getValueType()) &&
734 "Caller should expand or promote operands that are not legal!");
735 SDNode *Node = Op.Val;
737 // If this operation defines any values that cannot be represented in a
738 // register on this target, make sure to expand or promote them.
739 if (Node->getNumValues() > 1) {
740 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
741 if (getTypeAction(Node->getValueType(i)) != Legal) {
742 HandleOp(Op.getValue(i));
743 assert(LegalizedNodes.count(Op) &&
744 "Handling didn't add legal operands!");
745 return LegalizedNodes[Op];
749 // Note that LegalizeOp may be reentered even from single-use nodes, which
750 // means that we always must cache transformed nodes.
751 DenseMap<SDOperand, SDOperand>::iterator I = LegalizedNodes.find(Op);
752 if (I != LegalizedNodes.end()) return I->second;
754 SDOperand Tmp1, Tmp2, Tmp3, Tmp4;
755 SDOperand Result = Op;
756 bool isCustom = false;
758 switch (Node->getOpcode()) {
759 case ISD::FrameIndex:
760 case ISD::EntryToken:
762 case ISD::BasicBlock:
763 case ISD::TargetFrameIndex:
764 case ISD::TargetJumpTable:
765 case ISD::TargetConstant:
766 case ISD::TargetConstantFP:
767 case ISD::TargetConstantPool:
768 case ISD::TargetGlobalAddress:
769 case ISD::TargetGlobalTLSAddress:
770 case ISD::TargetExternalSymbol:
775 // Primitives must all be legal.
776 assert(TLI.isOperationLegal(Node->getOpcode(), Node->getValueType(0)) &&
777 "This must be legal!");
780 if (Node->getOpcode() >= ISD::BUILTIN_OP_END) {
781 // If this is a target node, legalize it by legalizing the operands then
782 // passing it through.
783 SmallVector<SDOperand, 8> Ops;
784 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
785 Ops.push_back(LegalizeOp(Node->getOperand(i)));
787 Result = DAG.UpdateNodeOperands(Result.getValue(0), &Ops[0], Ops.size());
789 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
790 AddLegalizedOperand(Op.getValue(i), Result.getValue(i));
791 return Result.getValue(Op.ResNo);
793 // Otherwise this is an unhandled builtin node. splat.
795 cerr << "NODE: "; Node->dump(&DAG); cerr << "\n";
797 assert(0 && "Do not know how to legalize this operator!");
799 case ISD::GLOBAL_OFFSET_TABLE:
800 case ISD::GlobalAddress:
801 case ISD::GlobalTLSAddress:
802 case ISD::ExternalSymbol:
803 case ISD::ConstantPool:
804 case ISD::JumpTable: // Nothing to do.
805 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
806 default: assert(0 && "This action is not supported yet!");
807 case TargetLowering::Custom:
808 Tmp1 = TLI.LowerOperation(Op, DAG);
809 if (Tmp1.Val) Result = Tmp1;
810 // FALLTHROUGH if the target doesn't want to lower this op after all.
811 case TargetLowering::Legal:
816 case ISD::RETURNADDR:
817 // The only option for these nodes is to custom lower them. If the target
818 // does not custom lower them, then return zero.
819 Tmp1 = TLI.LowerOperation(Op, DAG);
823 Result = DAG.getConstant(0, TLI.getPointerTy());
825 case ISD::FRAME_TO_ARGS_OFFSET: {
826 MVT::ValueType VT = Node->getValueType(0);
827 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
828 default: assert(0 && "This action is not supported yet!");
829 case TargetLowering::Custom:
830 Result = TLI.LowerOperation(Op, DAG);
831 if (Result.Val) break;
833 case TargetLowering::Legal:
834 Result = DAG.getConstant(0, VT);
839 case ISD::EXCEPTIONADDR: {
840 Tmp1 = LegalizeOp(Node->getOperand(0));
841 MVT::ValueType VT = Node->getValueType(0);
842 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
843 default: assert(0 && "This action is not supported yet!");
844 case TargetLowering::Expand: {
845 unsigned Reg = TLI.getExceptionAddressRegister();
846 Result = DAG.getCopyFromReg(Tmp1, Reg, VT).getValue(Op.ResNo);
849 case TargetLowering::Custom:
850 Result = TLI.LowerOperation(Op, DAG);
851 if (Result.Val) break;
853 case TargetLowering::Legal: {
854 SDOperand Ops[] = { DAG.getConstant(0, VT), Tmp1 };
855 Result = DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(VT, MVT::Other),
856 Ops, 2).getValue(Op.ResNo);
862 case ISD::EHSELECTION: {
863 Tmp1 = LegalizeOp(Node->getOperand(0));
864 Tmp2 = LegalizeOp(Node->getOperand(1));
865 MVT::ValueType VT = Node->getValueType(0);
866 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
867 default: assert(0 && "This action is not supported yet!");
868 case TargetLowering::Expand: {
869 unsigned Reg = TLI.getExceptionSelectorRegister();
870 Result = DAG.getCopyFromReg(Tmp2, Reg, VT).getValue(Op.ResNo);
873 case TargetLowering::Custom:
874 Result = TLI.LowerOperation(Op, DAG);
875 if (Result.Val) break;
877 case TargetLowering::Legal: {
878 SDOperand Ops[] = { DAG.getConstant(0, VT), Tmp2 };
879 Result = DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(VT, MVT::Other),
880 Ops, 2).getValue(Op.ResNo);
886 case ISD::EH_RETURN: {
887 MVT::ValueType VT = Node->getValueType(0);
888 // The only "good" option for this node is to custom lower it.
889 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
890 default: assert(0 && "This action is not supported at all!");
891 case TargetLowering::Custom:
892 Result = TLI.LowerOperation(Op, DAG);
893 if (Result.Val) break;
895 case TargetLowering::Legal:
896 // Target does not know, how to lower this, lower to noop
897 Result = LegalizeOp(Node->getOperand(0));
902 case ISD::AssertSext:
903 case ISD::AssertZext:
904 Tmp1 = LegalizeOp(Node->getOperand(0));
905 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
907 case ISD::MERGE_VALUES:
908 // Legalize eliminates MERGE_VALUES nodes.
909 Result = Node->getOperand(Op.ResNo);
911 case ISD::CopyFromReg:
912 Tmp1 = LegalizeOp(Node->getOperand(0));
913 Result = Op.getValue(0);
914 if (Node->getNumValues() == 2) {
915 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
917 assert(Node->getNumValues() == 3 && "Invalid copyfromreg!");
918 if (Node->getNumOperands() == 3) {
919 Tmp2 = LegalizeOp(Node->getOperand(2));
920 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1),Tmp2);
922 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
924 AddLegalizedOperand(Op.getValue(2), Result.getValue(2));
926 // Since CopyFromReg produces two values, make sure to remember that we
927 // legalized both of them.
928 AddLegalizedOperand(Op.getValue(0), Result);
929 AddLegalizedOperand(Op.getValue(1), Result.getValue(1));
930 return Result.getValue(Op.ResNo);
932 MVT::ValueType VT = Op.getValueType();
933 switch (TLI.getOperationAction(ISD::UNDEF, VT)) {
934 default: assert(0 && "This action is not supported yet!");
935 case TargetLowering::Expand:
936 if (MVT::isInteger(VT))
937 Result = DAG.getConstant(0, VT);
938 else if (MVT::isFloatingPoint(VT))
939 Result = DAG.getConstantFP(APFloat(APInt(MVT::getSizeInBits(VT), 0)),
942 assert(0 && "Unknown value type!");
944 case TargetLowering::Legal:
950 case ISD::INTRINSIC_W_CHAIN:
951 case ISD::INTRINSIC_WO_CHAIN:
952 case ISD::INTRINSIC_VOID: {
953 SmallVector<SDOperand, 8> Ops;
954 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
955 Ops.push_back(LegalizeOp(Node->getOperand(i)));
956 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
958 // Allow the target to custom lower its intrinsics if it wants to.
959 if (TLI.getOperationAction(Node->getOpcode(), MVT::Other) ==
960 TargetLowering::Custom) {
961 Tmp3 = TLI.LowerOperation(Result, DAG);
962 if (Tmp3.Val) Result = Tmp3;
965 if (Result.Val->getNumValues() == 1) break;
967 // Must have return value and chain result.
968 assert(Result.Val->getNumValues() == 2 &&
969 "Cannot return more than two values!");
971 // Since loads produce two values, make sure to remember that we
972 // legalized both of them.
973 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
974 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
975 return Result.getValue(Op.ResNo);
979 assert(Node->getNumOperands() == 5 && "Invalid LOCATION node!");
980 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the input chain.
982 switch (TLI.getOperationAction(ISD::LOCATION, MVT::Other)) {
983 case TargetLowering::Promote:
984 default: assert(0 && "This action is not supported yet!");
985 case TargetLowering::Expand: {
986 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
987 bool useDEBUG_LOC = TLI.isOperationLegal(ISD::DEBUG_LOC, MVT::Other);
988 bool useLABEL = TLI.isOperationLegal(ISD::LABEL, MVT::Other);
990 if (MMI && (useDEBUG_LOC || useLABEL)) {
991 const std::string &FName =
992 cast<StringSDNode>(Node->getOperand(3))->getValue();
993 const std::string &DirName =
994 cast<StringSDNode>(Node->getOperand(4))->getValue();
995 unsigned SrcFile = MMI->RecordSource(DirName, FName);
997 SmallVector<SDOperand, 8> Ops;
998 Ops.push_back(Tmp1); // chain
999 SDOperand LineOp = Node->getOperand(1);
1000 SDOperand ColOp = Node->getOperand(2);
1003 Ops.push_back(LineOp); // line #
1004 Ops.push_back(ColOp); // col #
1005 Ops.push_back(DAG.getConstant(SrcFile, MVT::i32)); // source file id
1006 Result = DAG.getNode(ISD::DEBUG_LOC, MVT::Other, &Ops[0], Ops.size());
1008 unsigned Line = cast<ConstantSDNode>(LineOp)->getValue();
1009 unsigned Col = cast<ConstantSDNode>(ColOp)->getValue();
1010 unsigned ID = MMI->RecordLabel(Line, Col, SrcFile);
1011 Ops.push_back(DAG.getConstant(ID, MVT::i32));
1012 Result = DAG.getNode(ISD::LABEL, MVT::Other,&Ops[0],Ops.size());
1015 Result = Tmp1; // chain
1019 case TargetLowering::Legal:
1020 if (Tmp1 != Node->getOperand(0) ||
1021 getTypeAction(Node->getOperand(1).getValueType()) == Promote) {
1022 SmallVector<SDOperand, 8> Ops;
1023 Ops.push_back(Tmp1);
1024 if (getTypeAction(Node->getOperand(1).getValueType()) == Legal) {
1025 Ops.push_back(Node->getOperand(1)); // line # must be legal.
1026 Ops.push_back(Node->getOperand(2)); // col # must be legal.
1028 // Otherwise promote them.
1029 Ops.push_back(PromoteOp(Node->getOperand(1)));
1030 Ops.push_back(PromoteOp(Node->getOperand(2)));
1032 Ops.push_back(Node->getOperand(3)); // filename must be legal.
1033 Ops.push_back(Node->getOperand(4)); // working dir # must be legal.
1034 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1040 case ISD::DEBUG_LOC:
1041 assert(Node->getNumOperands() == 4 && "Invalid DEBUG_LOC node!");
1042 switch (TLI.getOperationAction(ISD::DEBUG_LOC, MVT::Other)) {
1043 default: assert(0 && "This action is not supported yet!");
1044 case TargetLowering::Legal:
1045 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1046 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the line #.
1047 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the col #.
1048 Tmp4 = LegalizeOp(Node->getOperand(3)); // Legalize the source file id.
1049 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4);
1055 assert(Node->getNumOperands() == 2 && "Invalid LABEL node!");
1056 switch (TLI.getOperationAction(ISD::LABEL, MVT::Other)) {
1057 default: assert(0 && "This action is not supported yet!");
1058 case TargetLowering::Legal:
1059 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1060 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the label id.
1061 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1063 case TargetLowering::Expand:
1064 Result = LegalizeOp(Node->getOperand(0));
1069 case ISD::Constant: {
1070 ConstantSDNode *CN = cast<ConstantSDNode>(Node);
1072 TLI.getOperationAction(ISD::Constant, CN->getValueType(0));
1074 // We know we don't need to expand constants here, constants only have one
1075 // value and we check that it is fine above.
1077 if (opAction == TargetLowering::Custom) {
1078 Tmp1 = TLI.LowerOperation(Result, DAG);
1084 case ISD::ConstantFP: {
1085 // Spill FP immediates to the constant pool if the target cannot directly
1086 // codegen them. Targets often have some immediate values that can be
1087 // efficiently generated into an FP register without a load. We explicitly
1088 // leave these constants as ConstantFP nodes for the target to deal with.
1089 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node);
1091 // Check to see if this FP immediate is already legal.
1092 bool isLegal = false;
1093 for (TargetLowering::legal_fpimm_iterator I = TLI.legal_fpimm_begin(),
1094 E = TLI.legal_fpimm_end(); I != E; ++I)
1095 if (CFP->isExactlyValue(*I)) {
1100 // If this is a legal constant, turn it into a TargetConstantFP node.
1102 Result = DAG.getTargetConstantFP(CFP->getValueAPF(),
1103 CFP->getValueType(0));
1107 switch (TLI.getOperationAction(ISD::ConstantFP, CFP->getValueType(0))) {
1108 default: assert(0 && "This action is not supported yet!");
1109 case TargetLowering::Custom:
1110 Tmp3 = TLI.LowerOperation(Result, DAG);
1116 case TargetLowering::Expand:
1117 Result = ExpandConstantFP(CFP, true, DAG, TLI);
1121 case ISD::TokenFactor:
1122 if (Node->getNumOperands() == 2) {
1123 Tmp1 = LegalizeOp(Node->getOperand(0));
1124 Tmp2 = LegalizeOp(Node->getOperand(1));
1125 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1126 } else if (Node->getNumOperands() == 3) {
1127 Tmp1 = LegalizeOp(Node->getOperand(0));
1128 Tmp2 = LegalizeOp(Node->getOperand(1));
1129 Tmp3 = LegalizeOp(Node->getOperand(2));
1130 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1132 SmallVector<SDOperand, 8> Ops;
1133 // Legalize the operands.
1134 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
1135 Ops.push_back(LegalizeOp(Node->getOperand(i)));
1136 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1140 case ISD::FORMAL_ARGUMENTS:
1142 // The only option for this is to custom lower it.
1143 Tmp3 = TLI.LowerOperation(Result.getValue(0), DAG);
1144 assert(Tmp3.Val && "Target didn't custom lower this node!");
1146 // The number of incoming and outgoing values should match; unless the final
1147 // outgoing value is a flag.
1148 assert((Tmp3.Val->getNumValues() == Result.Val->getNumValues() ||
1149 (Tmp3.Val->getNumValues() == Result.Val->getNumValues() + 1 &&
1150 Tmp3.Val->getValueType(Tmp3.Val->getNumValues() - 1) ==
1152 "Lowering call/formal_arguments produced unexpected # results!");
1154 // Since CALL/FORMAL_ARGUMENTS nodes produce multiple values, make sure to
1155 // remember that we legalized all of them, so it doesn't get relegalized.
1156 for (unsigned i = 0, e = Tmp3.Val->getNumValues(); i != e; ++i) {
1157 if (Tmp3.Val->getValueType(i) == MVT::Flag)
1159 Tmp1 = LegalizeOp(Tmp3.getValue(i));
1162 AddLegalizedOperand(SDOperand(Node, i), Tmp1);
1165 case ISD::EXTRACT_SUBREG: {
1166 Tmp1 = LegalizeOp(Node->getOperand(0));
1167 ConstantSDNode *idx = dyn_cast<ConstantSDNode>(Node->getOperand(1));
1168 assert(idx && "Operand must be a constant");
1169 Tmp2 = DAG.getTargetConstant(idx->getValue(), idx->getValueType(0));
1170 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1173 case ISD::INSERT_SUBREG: {
1174 Tmp1 = LegalizeOp(Node->getOperand(0));
1175 Tmp2 = LegalizeOp(Node->getOperand(1));
1176 ConstantSDNode *idx = dyn_cast<ConstantSDNode>(Node->getOperand(2));
1177 assert(idx && "Operand must be a constant");
1178 Tmp3 = DAG.getTargetConstant(idx->getValue(), idx->getValueType(0));
1179 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1182 case ISD::BUILD_VECTOR:
1183 switch (TLI.getOperationAction(ISD::BUILD_VECTOR, Node->getValueType(0))) {
1184 default: assert(0 && "This action is not supported yet!");
1185 case TargetLowering::Custom:
1186 Tmp3 = TLI.LowerOperation(Result, DAG);
1192 case TargetLowering::Expand:
1193 Result = ExpandBUILD_VECTOR(Result.Val);
1197 case ISD::INSERT_VECTOR_ELT:
1198 Tmp1 = LegalizeOp(Node->getOperand(0)); // InVec
1199 Tmp2 = LegalizeOp(Node->getOperand(1)); // InVal
1200 Tmp3 = LegalizeOp(Node->getOperand(2)); // InEltNo
1201 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1203 switch (TLI.getOperationAction(ISD::INSERT_VECTOR_ELT,
1204 Node->getValueType(0))) {
1205 default: assert(0 && "This action is not supported yet!");
1206 case TargetLowering::Legal:
1208 case TargetLowering::Custom:
1209 Tmp3 = TLI.LowerOperation(Result, DAG);
1215 case TargetLowering::Expand: {
1216 // If the insert index is a constant, codegen this as a scalar_to_vector,
1217 // then a shuffle that inserts it into the right position in the vector.
1218 if (ConstantSDNode *InsertPos = dyn_cast<ConstantSDNode>(Tmp3)) {
1219 SDOperand ScVec = DAG.getNode(ISD::SCALAR_TO_VECTOR,
1220 Tmp1.getValueType(), Tmp2);
1222 unsigned NumElts = MVT::getVectorNumElements(Tmp1.getValueType());
1223 MVT::ValueType ShufMaskVT = MVT::getIntVectorWithNumElements(NumElts);
1224 MVT::ValueType ShufMaskEltVT = MVT::getVectorElementType(ShufMaskVT);
1226 // We generate a shuffle of InVec and ScVec, so the shuffle mask should
1227 // be 0,1,2,3,4,5... with the appropriate element replaced with elt 0 of
1229 SmallVector<SDOperand, 8> ShufOps;
1230 for (unsigned i = 0; i != NumElts; ++i) {
1231 if (i != InsertPos->getValue())
1232 ShufOps.push_back(DAG.getConstant(i, ShufMaskEltVT));
1234 ShufOps.push_back(DAG.getConstant(NumElts, ShufMaskEltVT));
1236 SDOperand ShufMask = DAG.getNode(ISD::BUILD_VECTOR, ShufMaskVT,
1237 &ShufOps[0], ShufOps.size());
1239 Result = DAG.getNode(ISD::VECTOR_SHUFFLE, Tmp1.getValueType(),
1240 Tmp1, ScVec, ShufMask);
1241 Result = LegalizeOp(Result);
1245 // If the target doesn't support this, we have to spill the input vector
1246 // to a temporary stack slot, update the element, then reload it. This is
1247 // badness. We could also load the value into a vector register (either
1248 // with a "move to register" or "extload into register" instruction, then
1249 // permute it into place, if the idx is a constant and if the idx is
1250 // supported by the target.
1251 MVT::ValueType VT = Tmp1.getValueType();
1252 MVT::ValueType EltVT = Tmp2.getValueType();
1253 MVT::ValueType IdxVT = Tmp3.getValueType();
1254 MVT::ValueType PtrVT = TLI.getPointerTy();
1255 SDOperand StackPtr = DAG.CreateStackTemporary(VT);
1256 // Store the vector.
1257 SDOperand Ch = DAG.getStore(DAG.getEntryNode(), Tmp1, StackPtr, NULL, 0);
1259 // Truncate or zero extend offset to target pointer type.
1260 unsigned CastOpc = (IdxVT > PtrVT) ? ISD::TRUNCATE : ISD::ZERO_EXTEND;
1261 Tmp3 = DAG.getNode(CastOpc, PtrVT, Tmp3);
1262 // Add the offset to the index.
1263 unsigned EltSize = MVT::getSizeInBits(EltVT)/8;
1264 Tmp3 = DAG.getNode(ISD::MUL, IdxVT, Tmp3,DAG.getConstant(EltSize, IdxVT));
1265 SDOperand StackPtr2 = DAG.getNode(ISD::ADD, IdxVT, Tmp3, StackPtr);
1266 // Store the scalar value.
1267 Ch = DAG.getStore(Ch, Tmp2, StackPtr2, NULL, 0);
1268 // Load the updated vector.
1269 Result = DAG.getLoad(VT, Ch, StackPtr, NULL, 0);
1274 case ISD::SCALAR_TO_VECTOR:
1275 if (!TLI.isTypeLegal(Node->getOperand(0).getValueType())) {
1276 Result = LegalizeOp(ExpandSCALAR_TO_VECTOR(Node));
1280 Tmp1 = LegalizeOp(Node->getOperand(0)); // InVal
1281 Result = DAG.UpdateNodeOperands(Result, Tmp1);
1282 switch (TLI.getOperationAction(ISD::SCALAR_TO_VECTOR,
1283 Node->getValueType(0))) {
1284 default: assert(0 && "This action is not supported yet!");
1285 case TargetLowering::Legal:
1287 case TargetLowering::Custom:
1288 Tmp3 = TLI.LowerOperation(Result, DAG);
1294 case TargetLowering::Expand:
1295 Result = LegalizeOp(ExpandSCALAR_TO_VECTOR(Node));
1299 case ISD::VECTOR_SHUFFLE:
1300 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the input vectors,
1301 Tmp2 = LegalizeOp(Node->getOperand(1)); // but not the shuffle mask.
1302 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
1304 // Allow targets to custom lower the SHUFFLEs they support.
1305 switch (TLI.getOperationAction(ISD::VECTOR_SHUFFLE,Result.getValueType())) {
1306 default: assert(0 && "Unknown operation action!");
1307 case TargetLowering::Legal:
1308 assert(isShuffleLegal(Result.getValueType(), Node->getOperand(2)) &&
1309 "vector shuffle should not be created if not legal!");
1311 case TargetLowering::Custom:
1312 Tmp3 = TLI.LowerOperation(Result, DAG);
1318 case TargetLowering::Expand: {
1319 MVT::ValueType VT = Node->getValueType(0);
1320 MVT::ValueType EltVT = MVT::getVectorElementType(VT);
1321 MVT::ValueType PtrVT = TLI.getPointerTy();
1322 SDOperand Mask = Node->getOperand(2);
1323 unsigned NumElems = Mask.getNumOperands();
1324 SmallVector<SDOperand,8> Ops;
1325 for (unsigned i = 0; i != NumElems; ++i) {
1326 SDOperand Arg = Mask.getOperand(i);
1327 if (Arg.getOpcode() == ISD::UNDEF) {
1328 Ops.push_back(DAG.getNode(ISD::UNDEF, EltVT));
1330 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
1331 unsigned Idx = cast<ConstantSDNode>(Arg)->getValue();
1333 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, Tmp1,
1334 DAG.getConstant(Idx, PtrVT)));
1336 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, Tmp2,
1337 DAG.getConstant(Idx - NumElems, PtrVT)));
1340 Result = DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size());
1343 case TargetLowering::Promote: {
1344 // Change base type to a different vector type.
1345 MVT::ValueType OVT = Node->getValueType(0);
1346 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
1348 // Cast the two input vectors.
1349 Tmp1 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp1);
1350 Tmp2 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp2);
1352 // Convert the shuffle mask to the right # elements.
1353 Tmp3 = SDOperand(isShuffleLegal(OVT, Node->getOperand(2)), 0);
1354 assert(Tmp3.Val && "Shuffle not legal?");
1355 Result = DAG.getNode(ISD::VECTOR_SHUFFLE, NVT, Tmp1, Tmp2, Tmp3);
1356 Result = DAG.getNode(ISD::BIT_CONVERT, OVT, Result);
1362 case ISD::EXTRACT_VECTOR_ELT:
1363 Tmp1 = Node->getOperand(0);
1364 Tmp2 = LegalizeOp(Node->getOperand(1));
1365 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1366 Result = ExpandEXTRACT_VECTOR_ELT(Result);
1369 case ISD::EXTRACT_SUBVECTOR:
1370 Tmp1 = Node->getOperand(0);
1371 Tmp2 = LegalizeOp(Node->getOperand(1));
1372 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1373 Result = ExpandEXTRACT_SUBVECTOR(Result);
1376 case ISD::CALLSEQ_START: {
1377 SDNode *CallEnd = FindCallEndFromCallStart(Node);
1379 // Recursively Legalize all of the inputs of the call end that do not lead
1380 // to this call start. This ensures that any libcalls that need be inserted
1381 // are inserted *before* the CALLSEQ_START.
1382 {SmallPtrSet<SDNode*, 32> NodesLeadingTo;
1383 for (unsigned i = 0, e = CallEnd->getNumOperands(); i != e; ++i)
1384 LegalizeAllNodesNotLeadingTo(CallEnd->getOperand(i).Val, Node,
1388 // Now that we legalized all of the inputs (which may have inserted
1389 // libcalls) create the new CALLSEQ_START node.
1390 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1392 // Merge in the last call, to ensure that this call start after the last
1394 if (LastCALLSEQ_END.getOpcode() != ISD::EntryToken) {
1395 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1396 Tmp1 = LegalizeOp(Tmp1);
1399 // Do not try to legalize the target-specific arguments (#1+).
1400 if (Tmp1 != Node->getOperand(0)) {
1401 SmallVector<SDOperand, 8> Ops(Node->op_begin(), Node->op_end());
1403 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1406 // Remember that the CALLSEQ_START is legalized.
1407 AddLegalizedOperand(Op.getValue(0), Result);
1408 if (Node->getNumValues() == 2) // If this has a flag result, remember it.
1409 AddLegalizedOperand(Op.getValue(1), Result.getValue(1));
1411 // Now that the callseq_start and all of the non-call nodes above this call
1412 // sequence have been legalized, legalize the call itself. During this
1413 // process, no libcalls can/will be inserted, guaranteeing that no calls
1415 assert(!IsLegalizingCall && "Inconsistent sequentialization of calls!");
1416 SDOperand InCallSEQ = LastCALLSEQ_END;
1417 // Note that we are selecting this call!
1418 LastCALLSEQ_END = SDOperand(CallEnd, 0);
1419 IsLegalizingCall = true;
1421 // Legalize the call, starting from the CALLSEQ_END.
1422 LegalizeOp(LastCALLSEQ_END);
1423 assert(!IsLegalizingCall && "CALLSEQ_END should have cleared this!");
1426 case ISD::CALLSEQ_END:
1427 // If the CALLSEQ_START node hasn't been legalized first, legalize it. This
1428 // will cause this node to be legalized as well as handling libcalls right.
1429 if (LastCALLSEQ_END.Val != Node) {
1430 LegalizeOp(SDOperand(FindCallStartFromCallEnd(Node), 0));
1431 DenseMap<SDOperand, SDOperand>::iterator I = LegalizedNodes.find(Op);
1432 assert(I != LegalizedNodes.end() &&
1433 "Legalizing the call start should have legalized this node!");
1437 // Otherwise, the call start has been legalized and everything is going
1438 // according to plan. Just legalize ourselves normally here.
1439 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1440 // Do not try to legalize the target-specific arguments (#1+), except for
1441 // an optional flag input.
1442 if (Node->getOperand(Node->getNumOperands()-1).getValueType() != MVT::Flag){
1443 if (Tmp1 != Node->getOperand(0)) {
1444 SmallVector<SDOperand, 8> Ops(Node->op_begin(), Node->op_end());
1446 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1449 Tmp2 = LegalizeOp(Node->getOperand(Node->getNumOperands()-1));
1450 if (Tmp1 != Node->getOperand(0) ||
1451 Tmp2 != Node->getOperand(Node->getNumOperands()-1)) {
1452 SmallVector<SDOperand, 8> Ops(Node->op_begin(), Node->op_end());
1455 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1458 assert(IsLegalizingCall && "Call sequence imbalance between start/end?");
1459 // This finishes up call legalization.
1460 IsLegalizingCall = false;
1462 // If the CALLSEQ_END node has a flag, remember that we legalized it.
1463 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
1464 if (Node->getNumValues() == 2)
1465 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
1466 return Result.getValue(Op.ResNo);
1467 case ISD::DYNAMIC_STACKALLOC: {
1468 MVT::ValueType VT = Node->getValueType(0);
1469 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1470 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the size.
1471 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the alignment.
1472 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1474 Tmp1 = Result.getValue(0);
1475 Tmp2 = Result.getValue(1);
1476 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
1477 default: assert(0 && "This action is not supported yet!");
1478 case TargetLowering::Expand: {
1479 unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore();
1480 assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and"
1481 " not tell us which reg is the stack pointer!");
1482 SDOperand Chain = Tmp1.getOperand(0);
1484 // Chain the dynamic stack allocation so that it doesn't modify the stack
1485 // pointer when other instructions are using the stack.
1486 Chain = DAG.getCALLSEQ_START(Chain,
1487 DAG.getConstant(0, TLI.getPointerTy()));
1489 SDOperand Size = Tmp2.getOperand(1);
1490 SDOperand SP = DAG.getCopyFromReg(Chain, SPReg, VT);
1491 Chain = SP.getValue(1);
1492 unsigned Align = cast<ConstantSDNode>(Tmp3)->getValue();
1493 unsigned StackAlign =
1494 TLI.getTargetMachine().getFrameInfo()->getStackAlignment();
1495 if (Align > StackAlign)
1496 SP = DAG.getNode(ISD::AND, VT, SP,
1497 DAG.getConstant(-(uint64_t)Align, VT));
1498 Tmp1 = DAG.getNode(ISD::SUB, VT, SP, Size); // Value
1499 Chain = DAG.getCopyToReg(Chain, SPReg, Tmp1); // Output chain
1502 DAG.getCALLSEQ_END(Chain,
1503 DAG.getConstant(0, TLI.getPointerTy()),
1504 DAG.getConstant(0, TLI.getPointerTy()),
1507 Tmp1 = LegalizeOp(Tmp1);
1508 Tmp2 = LegalizeOp(Tmp2);
1511 case TargetLowering::Custom:
1512 Tmp3 = TLI.LowerOperation(Tmp1, DAG);
1514 Tmp1 = LegalizeOp(Tmp3);
1515 Tmp2 = LegalizeOp(Tmp3.getValue(1));
1518 case TargetLowering::Legal:
1521 // Since this op produce two values, make sure to remember that we
1522 // legalized both of them.
1523 AddLegalizedOperand(SDOperand(Node, 0), Tmp1);
1524 AddLegalizedOperand(SDOperand(Node, 1), Tmp2);
1525 return Op.ResNo ? Tmp2 : Tmp1;
1527 case ISD::INLINEASM: {
1528 SmallVector<SDOperand, 8> Ops(Node->op_begin(), Node->op_end());
1529 bool Changed = false;
1530 // Legalize all of the operands of the inline asm, in case they are nodes
1531 // that need to be expanded or something. Note we skip the asm string and
1532 // all of the TargetConstant flags.
1533 SDOperand Op = LegalizeOp(Ops[0]);
1534 Changed = Op != Ops[0];
1537 bool HasInFlag = Ops.back().getValueType() == MVT::Flag;
1538 for (unsigned i = 2, e = Ops.size()-HasInFlag; i < e; ) {
1539 unsigned NumVals = cast<ConstantSDNode>(Ops[i])->getValue() >> 3;
1540 for (++i; NumVals; ++i, --NumVals) {
1541 SDOperand Op = LegalizeOp(Ops[i]);
1550 Op = LegalizeOp(Ops.back());
1551 Changed |= Op != Ops.back();
1556 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1558 // INLINE asm returns a chain and flag, make sure to add both to the map.
1559 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
1560 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
1561 return Result.getValue(Op.ResNo);
1564 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1565 // Ensure that libcalls are emitted before a branch.
1566 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1567 Tmp1 = LegalizeOp(Tmp1);
1568 LastCALLSEQ_END = DAG.getEntryNode();
1570 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
1573 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1574 // Ensure that libcalls are emitted before a branch.
1575 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1576 Tmp1 = LegalizeOp(Tmp1);
1577 LastCALLSEQ_END = DAG.getEntryNode();
1579 switch (getTypeAction(Node->getOperand(1).getValueType())) {
1580 default: assert(0 && "Indirect target must be legal type (pointer)!");
1582 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the condition.
1585 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1588 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1589 // Ensure that libcalls are emitted before a branch.
1590 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1591 Tmp1 = LegalizeOp(Tmp1);
1592 LastCALLSEQ_END = DAG.getEntryNode();
1594 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the jumptable node.
1595 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
1597 switch (TLI.getOperationAction(ISD::BR_JT, MVT::Other)) {
1598 default: assert(0 && "This action is not supported yet!");
1599 case TargetLowering::Legal: break;
1600 case TargetLowering::Custom:
1601 Tmp1 = TLI.LowerOperation(Result, DAG);
1602 if (Tmp1.Val) Result = Tmp1;
1604 case TargetLowering::Expand: {
1605 SDOperand Chain = Result.getOperand(0);
1606 SDOperand Table = Result.getOperand(1);
1607 SDOperand Index = Result.getOperand(2);
1609 MVT::ValueType PTy = TLI.getPointerTy();
1610 MachineFunction &MF = DAG.getMachineFunction();
1611 unsigned EntrySize = MF.getJumpTableInfo()->getEntrySize();
1612 Index= DAG.getNode(ISD::MUL, PTy, Index, DAG.getConstant(EntrySize, PTy));
1613 SDOperand Addr = DAG.getNode(ISD::ADD, PTy, Index, Table);
1616 switch (EntrySize) {
1617 default: assert(0 && "Size of jump table not supported yet."); break;
1618 case 4: LD = DAG.getLoad(MVT::i32, Chain, Addr, NULL, 0); break;
1619 case 8: LD = DAG.getLoad(MVT::i64, Chain, Addr, NULL, 0); break;
1623 if (TLI.getTargetMachine().getRelocationModel() == Reloc::PIC_) {
1624 // For PIC, the sequence is:
1625 // BRIND(load(Jumptable + index) + RelocBase)
1626 // RelocBase can be JumpTable, GOT or some sort of global base.
1627 if (PTy != MVT::i32)
1628 Addr = DAG.getNode(ISD::SIGN_EXTEND, PTy, Addr);
1629 Addr = DAG.getNode(ISD::ADD, PTy, Addr,
1630 TLI.getPICJumpTableRelocBase(Table, DAG));
1632 Result = DAG.getNode(ISD::BRIND, MVT::Other, LD.getValue(1), Addr);
1637 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1638 // Ensure that libcalls are emitted before a return.
1639 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1640 Tmp1 = LegalizeOp(Tmp1);
1641 LastCALLSEQ_END = DAG.getEntryNode();
1643 switch (getTypeAction(Node->getOperand(1).getValueType())) {
1644 case Expand: assert(0 && "It's impossible to expand bools");
1646 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the condition.
1649 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the condition.
1651 // The top bits of the promoted condition are not necessarily zero, ensure
1652 // that the value is properly zero extended.
1653 if (!DAG.MaskedValueIsZero(Tmp2,
1654 MVT::getIntVTBitMask(Tmp2.getValueType())^1))
1655 Tmp2 = DAG.getZeroExtendInReg(Tmp2, MVT::i1);
1659 // Basic block destination (Op#2) is always legal.
1660 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
1662 switch (TLI.getOperationAction(ISD::BRCOND, MVT::Other)) {
1663 default: assert(0 && "This action is not supported yet!");
1664 case TargetLowering::Legal: break;
1665 case TargetLowering::Custom:
1666 Tmp1 = TLI.LowerOperation(Result, DAG);
1667 if (Tmp1.Val) Result = Tmp1;
1669 case TargetLowering::Expand:
1670 // Expand brcond's setcc into its constituent parts and create a BR_CC
1672 if (Tmp2.getOpcode() == ISD::SETCC) {
1673 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1, Tmp2.getOperand(2),
1674 Tmp2.getOperand(0), Tmp2.getOperand(1),
1675 Node->getOperand(2));
1677 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1,
1678 DAG.getCondCode(ISD::SETNE), Tmp2,
1679 DAG.getConstant(0, Tmp2.getValueType()),
1680 Node->getOperand(2));
1686 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1687 // Ensure that libcalls are emitted before a branch.
1688 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1689 Tmp1 = LegalizeOp(Tmp1);
1690 Tmp2 = Node->getOperand(2); // LHS
1691 Tmp3 = Node->getOperand(3); // RHS
1692 Tmp4 = Node->getOperand(1); // CC
1694 LegalizeSetCCOperands(Tmp2, Tmp3, Tmp4);
1695 LastCALLSEQ_END = DAG.getEntryNode();
1697 // If we didn't get both a LHS and RHS back from LegalizeSetCCOperands,
1698 // the LHS is a legal SETCC itself. In this case, we need to compare
1699 // the result against zero to select between true and false values.
1700 if (Tmp3.Val == 0) {
1701 Tmp3 = DAG.getConstant(0, Tmp2.getValueType());
1702 Tmp4 = DAG.getCondCode(ISD::SETNE);
1705 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp4, Tmp2, Tmp3,
1706 Node->getOperand(4));
1708 switch (TLI.getOperationAction(ISD::BR_CC, Tmp3.getValueType())) {
1709 default: assert(0 && "Unexpected action for BR_CC!");
1710 case TargetLowering::Legal: break;
1711 case TargetLowering::Custom:
1712 Tmp4 = TLI.LowerOperation(Result, DAG);
1713 if (Tmp4.Val) Result = Tmp4;
1718 LoadSDNode *LD = cast<LoadSDNode>(Node);
1719 Tmp1 = LegalizeOp(LD->getChain()); // Legalize the chain.
1720 Tmp2 = LegalizeOp(LD->getBasePtr()); // Legalize the base pointer.
1722 ISD::LoadExtType ExtType = LD->getExtensionType();
1723 if (ExtType == ISD::NON_EXTLOAD) {
1724 MVT::ValueType VT = Node->getValueType(0);
1725 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, LD->getOffset());
1726 Tmp3 = Result.getValue(0);
1727 Tmp4 = Result.getValue(1);
1729 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
1730 default: assert(0 && "This action is not supported yet!");
1731 case TargetLowering::Legal:
1732 // If this is an unaligned load and the target doesn't support it,
1734 if (!TLI.allowsUnalignedMemoryAccesses()) {
1735 unsigned ABIAlignment = TLI.getTargetData()->
1736 getABITypeAlignment(MVT::getTypeForValueType(LD->getLoadedVT()));
1737 if (LD->getAlignment() < ABIAlignment){
1738 Result = ExpandUnalignedLoad(cast<LoadSDNode>(Result.Val), DAG,
1740 Tmp3 = Result.getOperand(0);
1741 Tmp4 = Result.getOperand(1);
1742 Tmp3 = LegalizeOp(Tmp3);
1743 Tmp4 = LegalizeOp(Tmp4);
1747 case TargetLowering::Custom:
1748 Tmp1 = TLI.LowerOperation(Tmp3, DAG);
1750 Tmp3 = LegalizeOp(Tmp1);
1751 Tmp4 = LegalizeOp(Tmp1.getValue(1));
1754 case TargetLowering::Promote: {
1755 // Only promote a load of vector type to another.
1756 assert(MVT::isVector(VT) && "Cannot promote this load!");
1757 // Change base type to a different vector type.
1758 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), VT);
1760 Tmp1 = DAG.getLoad(NVT, Tmp1, Tmp2, LD->getSrcValue(),
1761 LD->getSrcValueOffset(),
1762 LD->isVolatile(), LD->getAlignment());
1763 Tmp3 = LegalizeOp(DAG.getNode(ISD::BIT_CONVERT, VT, Tmp1));
1764 Tmp4 = LegalizeOp(Tmp1.getValue(1));
1768 // Since loads produce two values, make sure to remember that we
1769 // legalized both of them.
1770 AddLegalizedOperand(SDOperand(Node, 0), Tmp3);
1771 AddLegalizedOperand(SDOperand(Node, 1), Tmp4);
1772 return Op.ResNo ? Tmp4 : Tmp3;
1774 MVT::ValueType SrcVT = LD->getLoadedVT();
1775 switch (TLI.getLoadXAction(ExtType, SrcVT)) {
1776 default: assert(0 && "This action is not supported yet!");
1777 case TargetLowering::Promote:
1778 assert(SrcVT == MVT::i1 &&
1779 "Can only promote extending LOAD from i1 -> i8!");
1780 Result = DAG.getExtLoad(ExtType, Node->getValueType(0), Tmp1, Tmp2,
1781 LD->getSrcValue(), LD->getSrcValueOffset(),
1782 MVT::i8, LD->isVolatile(), LD->getAlignment());
1783 Tmp1 = Result.getValue(0);
1784 Tmp2 = Result.getValue(1);
1786 case TargetLowering::Custom:
1789 case TargetLowering::Legal:
1790 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, LD->getOffset());
1791 Tmp1 = Result.getValue(0);
1792 Tmp2 = Result.getValue(1);
1795 Tmp3 = TLI.LowerOperation(Result, DAG);
1797 Tmp1 = LegalizeOp(Tmp3);
1798 Tmp2 = LegalizeOp(Tmp3.getValue(1));
1801 // If this is an unaligned load and the target doesn't support it,
1803 if (!TLI.allowsUnalignedMemoryAccesses()) {
1804 unsigned ABIAlignment = TLI.getTargetData()->
1805 getABITypeAlignment(MVT::getTypeForValueType(LD->getLoadedVT()));
1806 if (LD->getAlignment() < ABIAlignment){
1807 Result = ExpandUnalignedLoad(cast<LoadSDNode>(Result.Val), DAG,
1809 Tmp1 = Result.getOperand(0);
1810 Tmp2 = Result.getOperand(1);
1811 Tmp1 = LegalizeOp(Tmp1);
1812 Tmp2 = LegalizeOp(Tmp2);
1817 case TargetLowering::Expand:
1818 // f64 = EXTLOAD f32 should expand to LOAD, FP_EXTEND
1819 if (SrcVT == MVT::f32 && Node->getValueType(0) == MVT::f64) {
1820 SDOperand Load = DAG.getLoad(SrcVT, Tmp1, Tmp2, LD->getSrcValue(),
1821 LD->getSrcValueOffset(),
1822 LD->isVolatile(), LD->getAlignment());
1823 Result = DAG.getNode(ISD::FP_EXTEND, Node->getValueType(0), Load);
1824 Tmp1 = LegalizeOp(Result); // Relegalize new nodes.
1825 Tmp2 = LegalizeOp(Load.getValue(1));
1828 assert(ExtType != ISD::EXTLOAD &&"EXTLOAD should always be supported!");
1829 // Turn the unsupported load into an EXTLOAD followed by an explicit
1830 // zero/sign extend inreg.
1831 Result = DAG.getExtLoad(ISD::EXTLOAD, Node->getValueType(0),
1832 Tmp1, Tmp2, LD->getSrcValue(),
1833 LD->getSrcValueOffset(), SrcVT,
1834 LD->isVolatile(), LD->getAlignment());
1836 if (ExtType == ISD::SEXTLOAD)
1837 ValRes = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(),
1838 Result, DAG.getValueType(SrcVT));
1840 ValRes = DAG.getZeroExtendInReg(Result, SrcVT);
1841 Tmp1 = LegalizeOp(ValRes); // Relegalize new nodes.
1842 Tmp2 = LegalizeOp(Result.getValue(1)); // Relegalize new nodes.
1845 // Since loads produce two values, make sure to remember that we legalized
1847 AddLegalizedOperand(SDOperand(Node, 0), Tmp1);
1848 AddLegalizedOperand(SDOperand(Node, 1), Tmp2);
1849 return Op.ResNo ? Tmp2 : Tmp1;
1852 case ISD::EXTRACT_ELEMENT: {
1853 MVT::ValueType OpTy = Node->getOperand(0).getValueType();
1854 switch (getTypeAction(OpTy)) {
1855 default: assert(0 && "EXTRACT_ELEMENT action for type unimplemented!");
1857 if (cast<ConstantSDNode>(Node->getOperand(1))->getValue()) {
1859 Result = DAG.getNode(ISD::SRL, OpTy, Node->getOperand(0),
1860 DAG.getConstant(MVT::getSizeInBits(OpTy)/2,
1861 TLI.getShiftAmountTy()));
1862 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), Result);
1865 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0),
1866 Node->getOperand(0));
1870 // Get both the low and high parts.
1871 ExpandOp(Node->getOperand(0), Tmp1, Tmp2);
1872 if (cast<ConstantSDNode>(Node->getOperand(1))->getValue())
1873 Result = Tmp2; // 1 -> Hi
1875 Result = Tmp1; // 0 -> Lo
1881 case ISD::CopyToReg:
1882 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1884 assert(isTypeLegal(Node->getOperand(2).getValueType()) &&
1885 "Register type must be legal!");
1886 // Legalize the incoming value (must be a legal type).
1887 Tmp2 = LegalizeOp(Node->getOperand(2));
1888 if (Node->getNumValues() == 1) {
1889 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1), Tmp2);
1891 assert(Node->getNumValues() == 2 && "Unknown CopyToReg");
1892 if (Node->getNumOperands() == 4) {
1893 Tmp3 = LegalizeOp(Node->getOperand(3));
1894 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1), Tmp2,
1897 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1),Tmp2);
1900 // Since this produces two values, make sure to remember that we legalized
1902 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
1903 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
1909 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1911 // Ensure that libcalls are emitted before a return.
1912 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1913 Tmp1 = LegalizeOp(Tmp1);
1914 LastCALLSEQ_END = DAG.getEntryNode();
1916 switch (Node->getNumOperands()) {
1918 Tmp2 = Node->getOperand(1);
1919 Tmp3 = Node->getOperand(2); // Signness
1920 switch (getTypeAction(Tmp2.getValueType())) {
1922 Result = DAG.UpdateNodeOperands(Result, Tmp1, LegalizeOp(Tmp2), Tmp3);
1925 if (!MVT::isVector(Tmp2.getValueType())) {
1927 ExpandOp(Tmp2, Lo, Hi);
1929 // Big endian systems want the hi reg first.
1930 if (!TLI.isLittleEndian())
1934 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Tmp3, Hi,Tmp3);
1936 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Tmp3);
1937 Result = LegalizeOp(Result);
1939 SDNode *InVal = Tmp2.Val;
1940 int InIx = Tmp2.ResNo;
1941 unsigned NumElems = MVT::getVectorNumElements(InVal->getValueType(InIx));
1942 MVT::ValueType EVT = MVT::getVectorElementType(InVal->getValueType(InIx));
1944 // Figure out if there is a simple type corresponding to this Vector
1945 // type. If so, convert to the vector type.
1946 MVT::ValueType TVT = MVT::getVectorType(EVT, NumElems);
1947 if (TLI.isTypeLegal(TVT)) {
1948 // Turn this into a return of the vector type.
1949 Tmp2 = LegalizeOp(Tmp2);
1950 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1951 } else if (NumElems == 1) {
1952 // Turn this into a return of the scalar type.
1953 Tmp2 = ScalarizeVectorOp(Tmp2);
1954 Tmp2 = LegalizeOp(Tmp2);
1955 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1957 // FIXME: Returns of gcc generic vectors smaller than a legal type
1958 // should be returned in integer registers!
1960 // The scalarized value type may not be legal, e.g. it might require
1961 // promotion or expansion. Relegalize the return.
1962 Result = LegalizeOp(Result);
1964 // FIXME: Returns of gcc generic vectors larger than a legal vector
1965 // type should be returned by reference!
1967 SplitVectorOp(Tmp2, Lo, Hi);
1968 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Tmp3, Hi,Tmp3);
1969 Result = LegalizeOp(Result);
1974 Tmp2 = PromoteOp(Node->getOperand(1));
1975 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1976 Result = LegalizeOp(Result);
1981 Result = DAG.UpdateNodeOperands(Result, Tmp1);
1983 default: { // ret <values>
1984 SmallVector<SDOperand, 8> NewValues;
1985 NewValues.push_back(Tmp1);
1986 for (unsigned i = 1, e = Node->getNumOperands(); i < e; i += 2)
1987 switch (getTypeAction(Node->getOperand(i).getValueType())) {
1989 NewValues.push_back(LegalizeOp(Node->getOperand(i)));
1990 NewValues.push_back(Node->getOperand(i+1));
1994 assert(!MVT::isExtendedVT(Node->getOperand(i).getValueType()) &&
1995 "FIXME: TODO: implement returning non-legal vector types!");
1996 ExpandOp(Node->getOperand(i), Lo, Hi);
1997 NewValues.push_back(Lo);
1998 NewValues.push_back(Node->getOperand(i+1));
2000 NewValues.push_back(Hi);
2001 NewValues.push_back(Node->getOperand(i+1));
2006 assert(0 && "Can't promote multiple return value yet!");
2009 if (NewValues.size() == Node->getNumOperands())
2010 Result = DAG.UpdateNodeOperands(Result, &NewValues[0],NewValues.size());
2012 Result = DAG.getNode(ISD::RET, MVT::Other,
2013 &NewValues[0], NewValues.size());
2018 if (Result.getOpcode() == ISD::RET) {
2019 switch (TLI.getOperationAction(Result.getOpcode(), MVT::Other)) {
2020 default: assert(0 && "This action is not supported yet!");
2021 case TargetLowering::Legal: break;
2022 case TargetLowering::Custom:
2023 Tmp1 = TLI.LowerOperation(Result, DAG);
2024 if (Tmp1.Val) Result = Tmp1;
2030 StoreSDNode *ST = cast<StoreSDNode>(Node);
2031 Tmp1 = LegalizeOp(ST->getChain()); // Legalize the chain.
2032 Tmp2 = LegalizeOp(ST->getBasePtr()); // Legalize the pointer.
2033 int SVOffset = ST->getSrcValueOffset();
2034 unsigned Alignment = ST->getAlignment();
2035 bool isVolatile = ST->isVolatile();
2037 if (!ST->isTruncatingStore()) {
2038 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr'
2039 // FIXME: We shouldn't do this for TargetConstantFP's.
2040 // FIXME: move this to the DAG Combiner! Note that we can't regress due
2041 // to phase ordering between legalized code and the dag combiner. This
2042 // probably means that we need to integrate dag combiner and legalizer
2044 // We generally can't do this one for long doubles.
2045 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(ST->getValue())) {
2046 if (CFP->getValueType(0) == MVT::f32 &&
2047 getTypeAction(MVT::i32) == Legal) {
2048 Tmp3 = DAG.getConstant((uint32_t)CFP->getValueAPF().
2049 convertToAPInt().getZExtValue(),
2051 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2052 SVOffset, isVolatile, Alignment);
2054 } else if (CFP->getValueType(0) == MVT::f64) {
2055 // If this target supports 64-bit registers, do a single 64-bit store.
2056 if (getTypeAction(MVT::i64) == Legal) {
2057 Tmp3 = DAG.getConstant(CFP->getValueAPF().convertToAPInt().
2058 getZExtValue(), MVT::i64);
2059 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2060 SVOffset, isVolatile, Alignment);
2062 } else if (getTypeAction(MVT::i32) == Legal) {
2063 // Otherwise, if the target supports 32-bit registers, use 2 32-bit
2064 // stores. If the target supports neither 32- nor 64-bits, this
2065 // xform is certainly not worth it.
2066 uint64_t IntVal =CFP->getValueAPF().convertToAPInt().getZExtValue();
2067 SDOperand Lo = DAG.getConstant(uint32_t(IntVal), MVT::i32);
2068 SDOperand Hi = DAG.getConstant(uint32_t(IntVal >>32), MVT::i32);
2069 if (!TLI.isLittleEndian()) std::swap(Lo, Hi);
2071 Lo = DAG.getStore(Tmp1, Lo, Tmp2, ST->getSrcValue(),
2072 SVOffset, isVolatile, Alignment);
2073 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2,
2074 getIntPtrConstant(4));
2075 Hi = DAG.getStore(Tmp1, Hi, Tmp2, ST->getSrcValue(), SVOffset+4,
2076 isVolatile, MinAlign(Alignment, 4U));
2078 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi);
2084 switch (getTypeAction(ST->getStoredVT())) {
2086 Tmp3 = LegalizeOp(ST->getValue());
2087 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2,
2090 MVT::ValueType VT = Tmp3.getValueType();
2091 switch (TLI.getOperationAction(ISD::STORE, VT)) {
2092 default: assert(0 && "This action is not supported yet!");
2093 case TargetLowering::Legal:
2094 // If this is an unaligned store and the target doesn't support it,
2096 if (!TLI.allowsUnalignedMemoryAccesses()) {
2097 unsigned ABIAlignment = TLI.getTargetData()->
2098 getABITypeAlignment(MVT::getTypeForValueType(ST->getStoredVT()));
2099 if (ST->getAlignment() < ABIAlignment)
2100 Result = ExpandUnalignedStore(cast<StoreSDNode>(Result.Val), DAG,
2104 case TargetLowering::Custom:
2105 Tmp1 = TLI.LowerOperation(Result, DAG);
2106 if (Tmp1.Val) Result = Tmp1;
2108 case TargetLowering::Promote:
2109 assert(MVT::isVector(VT) && "Unknown legal promote case!");
2110 Tmp3 = DAG.getNode(ISD::BIT_CONVERT,
2111 TLI.getTypeToPromoteTo(ISD::STORE, VT), Tmp3);
2112 Result = DAG.getStore(Tmp1, Tmp3, Tmp2,
2113 ST->getSrcValue(), SVOffset, isVolatile,
2120 // Truncate the value and store the result.
2121 Tmp3 = PromoteOp(ST->getValue());
2122 Result = DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2123 SVOffset, ST->getStoredVT(),
2124 isVolatile, Alignment);
2128 unsigned IncrementSize = 0;
2131 // If this is a vector type, then we have to calculate the increment as
2132 // the product of the element size in bytes, and the number of elements
2133 // in the high half of the vector.
2134 if (MVT::isVector(ST->getValue().getValueType())) {
2135 SDNode *InVal = ST->getValue().Val;
2136 int InIx = ST->getValue().ResNo;
2137 unsigned NumElems = MVT::getVectorNumElements(InVal->getValueType(InIx));
2138 MVT::ValueType EVT = MVT::getVectorElementType(InVal->getValueType(InIx));
2140 // Figure out if there is a simple type corresponding to this Vector
2141 // type. If so, convert to the vector type.
2142 MVT::ValueType TVT = MVT::getVectorType(EVT, NumElems);
2143 if (TLI.isTypeLegal(TVT)) {
2144 // Turn this into a normal store of the vector type.
2145 Tmp3 = LegalizeOp(Node->getOperand(1));
2146 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2147 SVOffset, isVolatile, Alignment);
2148 Result = LegalizeOp(Result);
2150 } else if (NumElems == 1) {
2151 // Turn this into a normal store of the scalar type.
2152 Tmp3 = ScalarizeVectorOp(Node->getOperand(1));
2153 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2154 SVOffset, isVolatile, Alignment);
2155 // The scalarized value type may not be legal, e.g. it might require
2156 // promotion or expansion. Relegalize the scalar store.
2157 Result = LegalizeOp(Result);
2160 SplitVectorOp(Node->getOperand(1), Lo, Hi);
2161 IncrementSize = MVT::getVectorNumElements(Lo.Val->getValueType(0)) *
2162 MVT::getSizeInBits(EVT)/8;
2165 ExpandOp(Node->getOperand(1), Lo, Hi);
2166 IncrementSize = Hi.Val ? MVT::getSizeInBits(Hi.getValueType())/8 : 0;
2168 if (!TLI.isLittleEndian())
2172 Lo = DAG.getStore(Tmp1, Lo, Tmp2, ST->getSrcValue(),
2173 SVOffset, isVolatile, Alignment);
2175 if (Hi.Val == NULL) {
2176 // Must be int <-> float one-to-one expansion.
2181 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2,
2182 getIntPtrConstant(IncrementSize));
2183 assert(isTypeLegal(Tmp2.getValueType()) &&
2184 "Pointers must be legal!");
2185 SVOffset += IncrementSize;
2186 Alignment = MinAlign(Alignment, IncrementSize);
2187 Hi = DAG.getStore(Tmp1, Hi, Tmp2, ST->getSrcValue(),
2188 SVOffset, isVolatile, Alignment);
2189 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi);
2194 assert(isTypeLegal(ST->getValue().getValueType()) &&
2195 "Cannot handle illegal TRUNCSTORE yet!");
2196 Tmp3 = LegalizeOp(ST->getValue());
2198 // The only promote case we handle is TRUNCSTORE:i1 X into
2199 // -> TRUNCSTORE:i8 (and X, 1)
2200 if (ST->getStoredVT() == MVT::i1 &&
2201 TLI.getStoreXAction(MVT::i1) == TargetLowering::Promote) {
2202 // Promote the bool to a mask then store.
2203 Tmp3 = DAG.getNode(ISD::AND, Tmp3.getValueType(), Tmp3,
2204 DAG.getConstant(1, Tmp3.getValueType()));
2205 Result = DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2207 isVolatile, Alignment);
2208 } else if (Tmp1 != ST->getChain() || Tmp3 != ST->getValue() ||
2209 Tmp2 != ST->getBasePtr()) {
2210 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2,
2214 MVT::ValueType StVT = cast<StoreSDNode>(Result.Val)->getStoredVT();
2215 switch (TLI.getStoreXAction(StVT)) {
2216 default: assert(0 && "This action is not supported yet!");
2217 case TargetLowering::Legal:
2218 // If this is an unaligned store and the target doesn't support it,
2220 if (!TLI.allowsUnalignedMemoryAccesses()) {
2221 unsigned ABIAlignment = TLI.getTargetData()->
2222 getABITypeAlignment(MVT::getTypeForValueType(ST->getStoredVT()));
2223 if (ST->getAlignment() < ABIAlignment)
2224 Result = ExpandUnalignedStore(cast<StoreSDNode>(Result.Val), DAG,
2228 case TargetLowering::Custom:
2229 Tmp1 = TLI.LowerOperation(Result, DAG);
2230 if (Tmp1.Val) Result = Tmp1;
2237 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2238 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
2240 case ISD::STACKSAVE:
2241 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2242 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2243 Tmp1 = Result.getValue(0);
2244 Tmp2 = Result.getValue(1);
2246 switch (TLI.getOperationAction(ISD::STACKSAVE, MVT::Other)) {
2247 default: assert(0 && "This action is not supported yet!");
2248 case TargetLowering::Legal: break;
2249 case TargetLowering::Custom:
2250 Tmp3 = TLI.LowerOperation(Result, DAG);
2252 Tmp1 = LegalizeOp(Tmp3);
2253 Tmp2 = LegalizeOp(Tmp3.getValue(1));
2256 case TargetLowering::Expand:
2257 // Expand to CopyFromReg if the target set
2258 // StackPointerRegisterToSaveRestore.
2259 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) {
2260 Tmp1 = DAG.getCopyFromReg(Result.getOperand(0), SP,
2261 Node->getValueType(0));
2262 Tmp2 = Tmp1.getValue(1);
2264 Tmp1 = DAG.getNode(ISD::UNDEF, Node->getValueType(0));
2265 Tmp2 = Node->getOperand(0);
2270 // Since stacksave produce two values, make sure to remember that we
2271 // legalized both of them.
2272 AddLegalizedOperand(SDOperand(Node, 0), Tmp1);
2273 AddLegalizedOperand(SDOperand(Node, 1), Tmp2);
2274 return Op.ResNo ? Tmp2 : Tmp1;
2276 case ISD::STACKRESTORE:
2277 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2278 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
2279 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
2281 switch (TLI.getOperationAction(ISD::STACKRESTORE, MVT::Other)) {
2282 default: assert(0 && "This action is not supported yet!");
2283 case TargetLowering::Legal: break;
2284 case TargetLowering::Custom:
2285 Tmp1 = TLI.LowerOperation(Result, DAG);
2286 if (Tmp1.Val) Result = Tmp1;
2288 case TargetLowering::Expand:
2289 // Expand to CopyToReg if the target set
2290 // StackPointerRegisterToSaveRestore.
2291 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) {
2292 Result = DAG.getCopyToReg(Tmp1, SP, Tmp2);
2300 case ISD::READCYCLECOUNTER:
2301 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain
2302 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2303 switch (TLI.getOperationAction(ISD::READCYCLECOUNTER,
2304 Node->getValueType(0))) {
2305 default: assert(0 && "This action is not supported yet!");
2306 case TargetLowering::Legal:
2307 Tmp1 = Result.getValue(0);
2308 Tmp2 = Result.getValue(1);
2310 case TargetLowering::Custom:
2311 Result = TLI.LowerOperation(Result, DAG);
2312 Tmp1 = LegalizeOp(Result.getValue(0));
2313 Tmp2 = LegalizeOp(Result.getValue(1));
2317 // Since rdcc produce two values, make sure to remember that we legalized
2319 AddLegalizedOperand(SDOperand(Node, 0), Tmp1);
2320 AddLegalizedOperand(SDOperand(Node, 1), Tmp2);
2324 switch (getTypeAction(Node->getOperand(0).getValueType())) {
2325 case Expand: assert(0 && "It's impossible to expand bools");
2327 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the condition.
2330 Tmp1 = PromoteOp(Node->getOperand(0)); // Promote the condition.
2331 // Make sure the condition is either zero or one.
2332 if (!DAG.MaskedValueIsZero(Tmp1,
2333 MVT::getIntVTBitMask(Tmp1.getValueType())^1))
2334 Tmp1 = DAG.getZeroExtendInReg(Tmp1, MVT::i1);
2337 Tmp2 = LegalizeOp(Node->getOperand(1)); // TrueVal
2338 Tmp3 = LegalizeOp(Node->getOperand(2)); // FalseVal
2340 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2342 switch (TLI.getOperationAction(ISD::SELECT, Tmp2.getValueType())) {
2343 default: assert(0 && "This action is not supported yet!");
2344 case TargetLowering::Legal: break;
2345 case TargetLowering::Custom: {
2346 Tmp1 = TLI.LowerOperation(Result, DAG);
2347 if (Tmp1.Val) Result = Tmp1;
2350 case TargetLowering::Expand:
2351 if (Tmp1.getOpcode() == ISD::SETCC) {
2352 Result = DAG.getSelectCC(Tmp1.getOperand(0), Tmp1.getOperand(1),
2354 cast<CondCodeSDNode>(Tmp1.getOperand(2))->get());
2356 Result = DAG.getSelectCC(Tmp1,
2357 DAG.getConstant(0, Tmp1.getValueType()),
2358 Tmp2, Tmp3, ISD::SETNE);
2361 case TargetLowering::Promote: {
2362 MVT::ValueType NVT =
2363 TLI.getTypeToPromoteTo(ISD::SELECT, Tmp2.getValueType());
2364 unsigned ExtOp, TruncOp;
2365 if (MVT::isVector(Tmp2.getValueType())) {
2366 ExtOp = ISD::BIT_CONVERT;
2367 TruncOp = ISD::BIT_CONVERT;
2368 } else if (MVT::isInteger(Tmp2.getValueType())) {
2369 ExtOp = ISD::ANY_EXTEND;
2370 TruncOp = ISD::TRUNCATE;
2372 ExtOp = ISD::FP_EXTEND;
2373 TruncOp = ISD::FP_ROUND;
2375 // Promote each of the values to the new type.
2376 Tmp2 = DAG.getNode(ExtOp, NVT, Tmp2);
2377 Tmp3 = DAG.getNode(ExtOp, NVT, Tmp3);
2378 // Perform the larger operation, then round down.
2379 Result = DAG.getNode(ISD::SELECT, NVT, Tmp1, Tmp2,Tmp3);
2380 Result = DAG.getNode(TruncOp, Node->getValueType(0), Result);
2385 case ISD::SELECT_CC: {
2386 Tmp1 = Node->getOperand(0); // LHS
2387 Tmp2 = Node->getOperand(1); // RHS
2388 Tmp3 = LegalizeOp(Node->getOperand(2)); // True
2389 Tmp4 = LegalizeOp(Node->getOperand(3)); // False
2390 SDOperand CC = Node->getOperand(4);
2392 LegalizeSetCCOperands(Tmp1, Tmp2, CC);
2394 // If we didn't get both a LHS and RHS back from LegalizeSetCCOperands,
2395 // the LHS is a legal SETCC itself. In this case, we need to compare
2396 // the result against zero to select between true and false values.
2397 if (Tmp2.Val == 0) {
2398 Tmp2 = DAG.getConstant(0, Tmp1.getValueType());
2399 CC = DAG.getCondCode(ISD::SETNE);
2401 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4, CC);
2403 // Everything is legal, see if we should expand this op or something.
2404 switch (TLI.getOperationAction(ISD::SELECT_CC, Tmp3.getValueType())) {
2405 default: assert(0 && "This action is not supported yet!");
2406 case TargetLowering::Legal: break;
2407 case TargetLowering::Custom:
2408 Tmp1 = TLI.LowerOperation(Result, DAG);
2409 if (Tmp1.Val) Result = Tmp1;
2415 Tmp1 = Node->getOperand(0);
2416 Tmp2 = Node->getOperand(1);
2417 Tmp3 = Node->getOperand(2);
2418 LegalizeSetCCOperands(Tmp1, Tmp2, Tmp3);
2420 // If we had to Expand the SetCC operands into a SELECT node, then it may
2421 // not always be possible to return a true LHS & RHS. In this case, just
2422 // return the value we legalized, returned in the LHS
2423 if (Tmp2.Val == 0) {
2428 switch (TLI.getOperationAction(ISD::SETCC, Tmp1.getValueType())) {
2429 default: assert(0 && "Cannot handle this action for SETCC yet!");
2430 case TargetLowering::Custom:
2433 case TargetLowering::Legal:
2434 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2436 Tmp4 = TLI.LowerOperation(Result, DAG);
2437 if (Tmp4.Val) Result = Tmp4;
2440 case TargetLowering::Promote: {
2441 // First step, figure out the appropriate operation to use.
2442 // Allow SETCC to not be supported for all legal data types
2443 // Mostly this targets FP
2444 MVT::ValueType NewInTy = Node->getOperand(0).getValueType();
2445 MVT::ValueType OldVT = NewInTy; OldVT = OldVT;
2447 // Scan for the appropriate larger type to use.
2449 NewInTy = (MVT::ValueType)(NewInTy+1);
2451 assert(MVT::isInteger(NewInTy) == MVT::isInteger(OldVT) &&
2452 "Fell off of the edge of the integer world");
2453 assert(MVT::isFloatingPoint(NewInTy) == MVT::isFloatingPoint(OldVT) &&
2454 "Fell off of the edge of the floating point world");
2456 // If the target supports SETCC of this type, use it.
2457 if (TLI.isOperationLegal(ISD::SETCC, NewInTy))
2460 if (MVT::isInteger(NewInTy))
2461 assert(0 && "Cannot promote Legal Integer SETCC yet");
2463 Tmp1 = DAG.getNode(ISD::FP_EXTEND, NewInTy, Tmp1);
2464 Tmp2 = DAG.getNode(ISD::FP_EXTEND, NewInTy, Tmp2);
2466 Tmp1 = LegalizeOp(Tmp1);
2467 Tmp2 = LegalizeOp(Tmp2);
2468 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2469 Result = LegalizeOp(Result);
2472 case TargetLowering::Expand:
2473 // Expand a setcc node into a select_cc of the same condition, lhs, and
2474 // rhs that selects between const 1 (true) and const 0 (false).
2475 MVT::ValueType VT = Node->getValueType(0);
2476 Result = DAG.getNode(ISD::SELECT_CC, VT, Tmp1, Tmp2,
2477 DAG.getConstant(1, VT), DAG.getConstant(0, VT),
2484 case ISD::MEMMOVE: {
2485 Tmp1 = LegalizeOp(Node->getOperand(0)); // Chain
2486 Tmp2 = LegalizeOp(Node->getOperand(1)); // Pointer
2488 if (Node->getOpcode() == ISD::MEMSET) { // memset = ubyte
2489 switch (getTypeAction(Node->getOperand(2).getValueType())) {
2490 case Expand: assert(0 && "Cannot expand a byte!");
2492 Tmp3 = LegalizeOp(Node->getOperand(2));
2495 Tmp3 = PromoteOp(Node->getOperand(2));
2499 Tmp3 = LegalizeOp(Node->getOperand(2)); // memcpy/move = pointer,
2503 switch (getTypeAction(Node->getOperand(3).getValueType())) {
2505 // Length is too big, just take the lo-part of the length.
2507 ExpandOp(Node->getOperand(3), Tmp4, HiPart);
2511 Tmp4 = LegalizeOp(Node->getOperand(3));
2514 Tmp4 = PromoteOp(Node->getOperand(3));
2519 switch (getTypeAction(Node->getOperand(4).getValueType())) { // uint
2520 case Expand: assert(0 && "Cannot expand this yet!");
2522 Tmp5 = LegalizeOp(Node->getOperand(4));
2525 Tmp5 = PromoteOp(Node->getOperand(4));
2530 switch (getTypeAction(Node->getOperand(5).getValueType())) { // bool
2531 case Expand: assert(0 && "Cannot expand this yet!");
2533 Tmp6 = LegalizeOp(Node->getOperand(5));
2536 Tmp6 = PromoteOp(Node->getOperand(5));
2540 switch (TLI.getOperationAction(Node->getOpcode(), MVT::Other)) {
2541 default: assert(0 && "This action not implemented for this operation!");
2542 case TargetLowering::Custom:
2545 case TargetLowering::Legal: {
2546 SDOperand Ops[] = { Tmp1, Tmp2, Tmp3, Tmp4, Tmp5, Tmp6 };
2547 Result = DAG.UpdateNodeOperands(Result, Ops, 6);
2549 Tmp1 = TLI.LowerOperation(Result, DAG);
2550 if (Tmp1.Val) Result = Tmp1;
2554 case TargetLowering::Expand: {
2555 // Otherwise, the target does not support this operation. Lower the
2556 // operation to an explicit libcall as appropriate.
2557 MVT::ValueType IntPtr = TLI.getPointerTy();
2558 const Type *IntPtrTy = TLI.getTargetData()->getIntPtrType();
2559 TargetLowering::ArgListTy Args;
2560 TargetLowering::ArgListEntry Entry;
2562 const char *FnName = 0;
2563 if (Node->getOpcode() == ISD::MEMSET) {
2564 Entry.Node = Tmp2; Entry.Ty = IntPtrTy;
2565 Args.push_back(Entry);
2566 // Extend the (previously legalized) ubyte argument to be an int value
2568 if (Tmp3.getValueType() > MVT::i32)
2569 Tmp3 = DAG.getNode(ISD::TRUNCATE, MVT::i32, Tmp3);
2571 Tmp3 = DAG.getNode(ISD::ZERO_EXTEND, MVT::i32, Tmp3);
2572 Entry.Node = Tmp3; Entry.Ty = Type::Int32Ty; Entry.isSExt = true;
2573 Args.push_back(Entry);
2574 Entry.Node = Tmp4; Entry.Ty = IntPtrTy; Entry.isSExt = false;
2575 Args.push_back(Entry);
2578 } else if (Node->getOpcode() == ISD::MEMCPY ||
2579 Node->getOpcode() == ISD::MEMMOVE) {
2580 Entry.Ty = IntPtrTy;
2581 Entry.Node = Tmp2; Args.push_back(Entry);
2582 Entry.Node = Tmp3; Args.push_back(Entry);
2583 Entry.Node = Tmp4; Args.push_back(Entry);
2584 FnName = Node->getOpcode() == ISD::MEMMOVE ? "memmove" : "memcpy";
2586 assert(0 && "Unknown op!");
2589 std::pair<SDOperand,SDOperand> CallResult =
2590 TLI.LowerCallTo(Tmp1, Type::VoidTy, false, false, CallingConv::C, false,
2591 DAG.getExternalSymbol(FnName, IntPtr), Args, DAG);
2592 Result = CallResult.second;
2599 case ISD::SHL_PARTS:
2600 case ISD::SRA_PARTS:
2601 case ISD::SRL_PARTS: {
2602 SmallVector<SDOperand, 8> Ops;
2603 bool Changed = false;
2604 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
2605 Ops.push_back(LegalizeOp(Node->getOperand(i)));
2606 Changed |= Ops.back() != Node->getOperand(i);
2609 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
2611 switch (TLI.getOperationAction(Node->getOpcode(),
2612 Node->getValueType(0))) {
2613 default: assert(0 && "This action is not supported yet!");
2614 case TargetLowering::Legal: break;
2615 case TargetLowering::Custom:
2616 Tmp1 = TLI.LowerOperation(Result, DAG);
2618 SDOperand Tmp2, RetVal(0, 0);
2619 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) {
2620 Tmp2 = LegalizeOp(Tmp1.getValue(i));
2621 AddLegalizedOperand(SDOperand(Node, i), Tmp2);
2625 assert(RetVal.Val && "Illegal result number");
2631 // Since these produce multiple values, make sure to remember that we
2632 // legalized all of them.
2633 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
2634 AddLegalizedOperand(SDOperand(Node, i), Result.getValue(i));
2635 return Result.getValue(Op.ResNo);
2657 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
2658 switch (getTypeAction(Node->getOperand(1).getValueType())) {
2659 case Expand: assert(0 && "Not possible");
2661 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the RHS.
2664 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the RHS.
2668 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
2670 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
2671 default: assert(0 && "BinOp legalize operation not supported");
2672 case TargetLowering::Legal: break;
2673 case TargetLowering::Custom:
2674 Tmp1 = TLI.LowerOperation(Result, DAG);
2675 if (Tmp1.Val) Result = Tmp1;
2677 case TargetLowering::Expand: {
2678 MVT::ValueType VT = Op.getValueType();
2680 // See if multiply or divide can be lowered using two-result operations.
2681 SDVTList VTs = DAG.getVTList(VT, VT);
2682 if (Node->getOpcode() == ISD::MUL) {
2683 // We just need the low half of the multiply; try both the signed
2684 // and unsigned forms. If the target supports both SMUL_LOHI and
2685 // UMUL_LOHI, form a preference by checking which forms of plain
2686 // MULH it supports.
2687 bool HasSMUL_LOHI = TLI.isOperationLegal(ISD::SMUL_LOHI, VT);
2688 bool HasUMUL_LOHI = TLI.isOperationLegal(ISD::UMUL_LOHI, VT);
2689 bool HasMULHS = TLI.isOperationLegal(ISD::MULHS, VT);
2690 bool HasMULHU = TLI.isOperationLegal(ISD::MULHU, VT);
2691 unsigned OpToUse = 0;
2692 if (HasSMUL_LOHI && !HasMULHS) {
2693 OpToUse = ISD::SMUL_LOHI;
2694 } else if (HasUMUL_LOHI && !HasMULHU) {
2695 OpToUse = ISD::UMUL_LOHI;
2696 } else if (HasSMUL_LOHI) {
2697 OpToUse = ISD::SMUL_LOHI;
2698 } else if (HasUMUL_LOHI) {
2699 OpToUse = ISD::UMUL_LOHI;
2702 Result = SDOperand(DAG.getNode(OpToUse, VTs, Tmp1, Tmp2).Val, 0);
2706 if (Node->getOpcode() == ISD::MULHS &&
2707 TLI.isOperationLegal(ISD::SMUL_LOHI, VT)) {
2708 Result = SDOperand(DAG.getNode(ISD::SMUL_LOHI, VTs, Tmp1, Tmp2).Val, 1);
2711 if (Node->getOpcode() == ISD::MULHU &&
2712 TLI.isOperationLegal(ISD::UMUL_LOHI, VT)) {
2713 Result = SDOperand(DAG.getNode(ISD::UMUL_LOHI, VTs, Tmp1, Tmp2).Val, 1);
2716 if (Node->getOpcode() == ISD::SDIV &&
2717 TLI.isOperationLegal(ISD::SDIVREM, VT)) {
2718 Result = SDOperand(DAG.getNode(ISD::SDIVREM, VTs, Tmp1, Tmp2).Val, 0);
2721 if (Node->getOpcode() == ISD::UDIV &&
2722 TLI.isOperationLegal(ISD::UDIVREM, VT)) {
2723 Result = SDOperand(DAG.getNode(ISD::UDIVREM, VTs, Tmp1, Tmp2).Val, 0);
2727 // Check to see if we have a libcall for this operator.
2728 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
2729 bool isSigned = false;
2730 switch (Node->getOpcode()) {
2733 if (VT == MVT::i32) {
2734 LC = Node->getOpcode() == ISD::UDIV
2735 ? RTLIB::UDIV_I32 : RTLIB::SDIV_I32;
2736 isSigned = Node->getOpcode() == ISD::SDIV;
2740 LC = VT == MVT::f32 ? RTLIB::POW_F32 :
2741 VT == MVT::f64 ? RTLIB::POW_F64 :
2742 VT == MVT::f80 ? RTLIB::POW_F80 :
2743 VT == MVT::ppcf128 ? RTLIB::POW_PPCF128 :
2744 RTLIB::UNKNOWN_LIBCALL;
2748 if (LC != RTLIB::UNKNOWN_LIBCALL) {
2750 Result = ExpandLibCall(TLI.getLibcallName(LC), Node, isSigned, Dummy);
2754 assert(MVT::isVector(Node->getValueType(0)) &&
2755 "Cannot expand this binary operator!");
2756 // Expand the operation into a bunch of nasty scalar code.
2757 Result = LegalizeOp(UnrollVectorOp(Op));
2760 case TargetLowering::Promote: {
2761 switch (Node->getOpcode()) {
2762 default: assert(0 && "Do not know how to promote this BinOp!");
2766 MVT::ValueType OVT = Node->getValueType(0);
2767 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
2768 assert(MVT::isVector(OVT) && "Cannot promote this BinOp!");
2769 // Bit convert each of the values to the new type.
2770 Tmp1 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp1);
2771 Tmp2 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp2);
2772 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
2773 // Bit convert the result back the original type.
2774 Result = DAG.getNode(ISD::BIT_CONVERT, OVT, Result);
2782 case ISD::SMUL_LOHI:
2783 case ISD::UMUL_LOHI:
2786 // These nodes will only be produced by target-specific lowering, so
2787 // they shouldn't be here if they aren't legal.
2788 assert(TLI.isOperationLegal(Node->getOpcode(), Node->getValueType(0)) &&
2789 "This must be legal!");
2791 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
2792 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS
2793 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
2796 case ISD::FCOPYSIGN: // FCOPYSIGN does not require LHS/RHS to match type!
2797 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
2798 switch (getTypeAction(Node->getOperand(1).getValueType())) {
2799 case Expand: assert(0 && "Not possible");
2801 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the RHS.
2804 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the RHS.
2808 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
2810 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
2811 default: assert(0 && "Operation not supported");
2812 case TargetLowering::Custom:
2813 Tmp1 = TLI.LowerOperation(Result, DAG);
2814 if (Tmp1.Val) Result = Tmp1;
2816 case TargetLowering::Legal: break;
2817 case TargetLowering::Expand: {
2818 // If this target supports fabs/fneg natively and select is cheap,
2819 // do this efficiently.
2820 if (!TLI.isSelectExpensive() &&
2821 TLI.getOperationAction(ISD::FABS, Tmp1.getValueType()) ==
2822 TargetLowering::Legal &&
2823 TLI.getOperationAction(ISD::FNEG, Tmp1.getValueType()) ==
2824 TargetLowering::Legal) {
2825 // Get the sign bit of the RHS.
2826 MVT::ValueType IVT =
2827 Tmp2.getValueType() == MVT::f32 ? MVT::i32 : MVT::i64;
2828 SDOperand SignBit = DAG.getNode(ISD::BIT_CONVERT, IVT, Tmp2);
2829 SignBit = DAG.getSetCC(TLI.getSetCCResultTy(),
2830 SignBit, DAG.getConstant(0, IVT), ISD::SETLT);
2831 // Get the absolute value of the result.
2832 SDOperand AbsVal = DAG.getNode(ISD::FABS, Tmp1.getValueType(), Tmp1);
2833 // Select between the nabs and abs value based on the sign bit of
2835 Result = DAG.getNode(ISD::SELECT, AbsVal.getValueType(), SignBit,
2836 DAG.getNode(ISD::FNEG, AbsVal.getValueType(),
2839 Result = LegalizeOp(Result);
2843 // Otherwise, do bitwise ops!
2844 MVT::ValueType NVT =
2845 Node->getValueType(0) == MVT::f32 ? MVT::i32 : MVT::i64;
2846 Result = ExpandFCOPYSIGNToBitwiseOps(Node, NVT, DAG, TLI);
2847 Result = DAG.getNode(ISD::BIT_CONVERT, Node->getValueType(0), Result);
2848 Result = LegalizeOp(Result);
2856 Tmp1 = LegalizeOp(Node->getOperand(0));
2857 Tmp2 = LegalizeOp(Node->getOperand(1));
2858 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
2859 // Since this produces two values, make sure to remember that we legalized
2861 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
2862 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
2867 Tmp1 = LegalizeOp(Node->getOperand(0));
2868 Tmp2 = LegalizeOp(Node->getOperand(1));
2869 Tmp3 = LegalizeOp(Node->getOperand(2));
2870 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2871 // Since this produces two values, make sure to remember that we legalized
2873 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
2874 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
2877 case ISD::BUILD_PAIR: {
2878 MVT::ValueType PairTy = Node->getValueType(0);
2879 // TODO: handle the case where the Lo and Hi operands are not of legal type
2880 Tmp1 = LegalizeOp(Node->getOperand(0)); // Lo
2881 Tmp2 = LegalizeOp(Node->getOperand(1)); // Hi
2882 switch (TLI.getOperationAction(ISD::BUILD_PAIR, PairTy)) {
2883 case TargetLowering::Promote:
2884 case TargetLowering::Custom:
2885 assert(0 && "Cannot promote/custom this yet!");
2886 case TargetLowering::Legal:
2887 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1))
2888 Result = DAG.getNode(ISD::BUILD_PAIR, PairTy, Tmp1, Tmp2);
2890 case TargetLowering::Expand:
2891 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, PairTy, Tmp1);
2892 Tmp2 = DAG.getNode(ISD::ANY_EXTEND, PairTy, Tmp2);
2893 Tmp2 = DAG.getNode(ISD::SHL, PairTy, Tmp2,
2894 DAG.getConstant(MVT::getSizeInBits(PairTy)/2,
2895 TLI.getShiftAmountTy()));
2896 Result = DAG.getNode(ISD::OR, PairTy, Tmp1, Tmp2);
2905 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
2906 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS
2908 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
2909 case TargetLowering::Promote: assert(0 && "Cannot promote this yet!");
2910 case TargetLowering::Custom:
2913 case TargetLowering::Legal:
2914 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
2916 Tmp1 = TLI.LowerOperation(Result, DAG);
2917 if (Tmp1.Val) Result = Tmp1;
2920 case TargetLowering::Expand: {
2921 unsigned DivOpc= (Node->getOpcode() == ISD::UREM) ? ISD::UDIV : ISD::SDIV;
2922 bool isSigned = DivOpc == ISD::SDIV;
2923 MVT::ValueType VT = Node->getValueType(0);
2925 // See if remainder can be lowered using two-result operations.
2926 SDVTList VTs = DAG.getVTList(VT, VT);
2927 if (Node->getOpcode() == ISD::SREM &&
2928 TLI.isOperationLegal(ISD::SDIVREM, VT)) {
2929 Result = SDOperand(DAG.getNode(ISD::SDIVREM, VTs, Tmp1, Tmp2).Val, 1);
2932 if (Node->getOpcode() == ISD::UREM &&
2933 TLI.isOperationLegal(ISD::UDIVREM, VT)) {
2934 Result = SDOperand(DAG.getNode(ISD::UDIVREM, VTs, Tmp1, Tmp2).Val, 1);
2938 if (MVT::isInteger(VT)) {
2939 if (TLI.getOperationAction(DivOpc, VT) ==
2940 TargetLowering::Legal) {
2942 Result = DAG.getNode(DivOpc, VT, Tmp1, Tmp2);
2943 Result = DAG.getNode(ISD::MUL, VT, Result, Tmp2);
2944 Result = DAG.getNode(ISD::SUB, VT, Tmp1, Result);
2945 } else if (MVT::isVector(VT)) {
2946 Result = LegalizeOp(UnrollVectorOp(Op));
2948 assert(VT == MVT::i32 &&
2949 "Cannot expand this binary operator!");
2950 RTLIB::Libcall LC = Node->getOpcode() == ISD::UREM
2951 ? RTLIB::UREM_I32 : RTLIB::SREM_I32;
2953 Result = ExpandLibCall(TLI.getLibcallName(LC), Node, isSigned, Dummy);
2956 assert(MVT::isFloatingPoint(VT) &&
2957 "remainder op must have integer or floating-point type");
2958 if (MVT::isVector(VT)) {
2959 Result = LegalizeOp(UnrollVectorOp(Op));
2961 // Floating point mod -> fmod libcall.
2962 RTLIB::Libcall LC = VT == MVT::f32
2963 ? RTLIB::REM_F32 : RTLIB::REM_F64;
2965 Result = ExpandLibCall(TLI.getLibcallName(LC), Node,
2966 false/*sign irrelevant*/, Dummy);
2974 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2975 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
2977 MVT::ValueType VT = Node->getValueType(0);
2978 switch (TLI.getOperationAction(Node->getOpcode(), MVT::Other)) {
2979 default: assert(0 && "This action is not supported yet!");
2980 case TargetLowering::Custom:
2983 case TargetLowering::Legal:
2984 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
2985 Result = Result.getValue(0);
2986 Tmp1 = Result.getValue(1);
2989 Tmp2 = TLI.LowerOperation(Result, DAG);
2991 Result = LegalizeOp(Tmp2);
2992 Tmp1 = LegalizeOp(Tmp2.getValue(1));
2996 case TargetLowering::Expand: {
2997 SrcValueSDNode *SV = cast<SrcValueSDNode>(Node->getOperand(2));
2998 SDOperand VAList = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp2,
2999 SV->getValue(), SV->getOffset());
3000 // Increment the pointer, VAList, to the next vaarg
3001 Tmp3 = DAG.getNode(ISD::ADD, TLI.getPointerTy(), VAList,
3002 DAG.getConstant(MVT::getSizeInBits(VT)/8,
3003 TLI.getPointerTy()));
3004 // Store the incremented VAList to the legalized pointer
3005 Tmp3 = DAG.getStore(VAList.getValue(1), Tmp3, Tmp2, SV->getValue(),
3007 // Load the actual argument out of the pointer VAList
3008 Result = DAG.getLoad(VT, Tmp3, VAList, NULL, 0);
3009 Tmp1 = LegalizeOp(Result.getValue(1));
3010 Result = LegalizeOp(Result);
3014 // Since VAARG produces two values, make sure to remember that we
3015 // legalized both of them.
3016 AddLegalizedOperand(SDOperand(Node, 0), Result);
3017 AddLegalizedOperand(SDOperand(Node, 1), Tmp1);
3018 return Op.ResNo ? Tmp1 : Result;
3022 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
3023 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the dest pointer.
3024 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the source pointer.
3026 switch (TLI.getOperationAction(ISD::VACOPY, MVT::Other)) {
3027 default: assert(0 && "This action is not supported yet!");
3028 case TargetLowering::Custom:
3031 case TargetLowering::Legal:
3032 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3,
3033 Node->getOperand(3), Node->getOperand(4));
3035 Tmp1 = TLI.LowerOperation(Result, DAG);
3036 if (Tmp1.Val) Result = Tmp1;
3039 case TargetLowering::Expand:
3040 // This defaults to loading a pointer from the input and storing it to the
3041 // output, returning the chain.
3042 SrcValueSDNode *SVD = cast<SrcValueSDNode>(Node->getOperand(3));
3043 SrcValueSDNode *SVS = cast<SrcValueSDNode>(Node->getOperand(4));
3044 Tmp4 = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp3, SVD->getValue(),
3046 Result = DAG.getStore(Tmp4.getValue(1), Tmp4, Tmp2, SVS->getValue(),
3053 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
3054 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
3056 switch (TLI.getOperationAction(ISD::VAEND, MVT::Other)) {
3057 default: assert(0 && "This action is not supported yet!");
3058 case TargetLowering::Custom:
3061 case TargetLowering::Legal:
3062 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
3064 Tmp1 = TLI.LowerOperation(Tmp1, DAG);
3065 if (Tmp1.Val) Result = Tmp1;
3068 case TargetLowering::Expand:
3069 Result = Tmp1; // Default to a no-op, return the chain
3075 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
3076 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
3078 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
3080 switch (TLI.getOperationAction(ISD::VASTART, MVT::Other)) {
3081 default: assert(0 && "This action is not supported yet!");
3082 case TargetLowering::Legal: break;
3083 case TargetLowering::Custom:
3084 Tmp1 = TLI.LowerOperation(Result, DAG);
3085 if (Tmp1.Val) Result = Tmp1;
3092 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
3093 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS
3094 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
3095 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3097 assert(0 && "ROTL/ROTR legalize operation not supported");
3099 case TargetLowering::Legal:
3101 case TargetLowering::Custom:
3102 Tmp1 = TLI.LowerOperation(Result, DAG);
3103 if (Tmp1.Val) Result = Tmp1;
3105 case TargetLowering::Promote:
3106 assert(0 && "Do not know how to promote ROTL/ROTR");
3108 case TargetLowering::Expand:
3109 assert(0 && "Do not know how to expand ROTL/ROTR");
3115 Tmp1 = LegalizeOp(Node->getOperand(0)); // Op
3116 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3117 case TargetLowering::Custom:
3118 assert(0 && "Cannot custom legalize this yet!");
3119 case TargetLowering::Legal:
3120 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3122 case TargetLowering::Promote: {
3123 MVT::ValueType OVT = Tmp1.getValueType();
3124 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
3125 unsigned DiffBits = MVT::getSizeInBits(NVT) - MVT::getSizeInBits(OVT);
3127 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1);
3128 Tmp1 = DAG.getNode(ISD::BSWAP, NVT, Tmp1);
3129 Result = DAG.getNode(ISD::SRL, NVT, Tmp1,
3130 DAG.getConstant(DiffBits, TLI.getShiftAmountTy()));
3133 case TargetLowering::Expand:
3134 Result = ExpandBSWAP(Tmp1);
3142 Tmp1 = LegalizeOp(Node->getOperand(0)); // Op
3143 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3144 case TargetLowering::Custom:
3145 case TargetLowering::Legal:
3146 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3147 if (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0)) ==
3148 TargetLowering::Custom) {
3149 Tmp1 = TLI.LowerOperation(Result, DAG);
3155 case TargetLowering::Promote: {
3156 MVT::ValueType OVT = Tmp1.getValueType();
3157 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
3159 // Zero extend the argument.
3160 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1);
3161 // Perform the larger operation, then subtract if needed.
3162 Tmp1 = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1);
3163 switch (Node->getOpcode()) {
3168 //if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT)
3169 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), Tmp1,
3170 DAG.getConstant(MVT::getSizeInBits(NVT), NVT),
3172 Result = DAG.getNode(ISD::SELECT, NVT, Tmp2,
3173 DAG.getConstant(MVT::getSizeInBits(OVT),NVT), Tmp1);
3176 // Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT))
3177 Result = DAG.getNode(ISD::SUB, NVT, Tmp1,
3178 DAG.getConstant(MVT::getSizeInBits(NVT) -
3179 MVT::getSizeInBits(OVT), NVT));
3184 case TargetLowering::Expand:
3185 Result = ExpandBitCount(Node->getOpcode(), Tmp1);
3196 Tmp1 = LegalizeOp(Node->getOperand(0));
3197 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3198 case TargetLowering::Promote:
3199 case TargetLowering::Custom:
3202 case TargetLowering::Legal:
3203 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3205 Tmp1 = TLI.LowerOperation(Result, DAG);
3206 if (Tmp1.Val) Result = Tmp1;
3209 case TargetLowering::Expand:
3210 switch (Node->getOpcode()) {
3211 default: assert(0 && "Unreachable!");
3213 // Expand Y = FNEG(X) -> Y = SUB -0.0, X
3214 Tmp2 = DAG.getConstantFP(-0.0, Node->getValueType(0));
3215 Result = DAG.getNode(ISD::FSUB, Node->getValueType(0), Tmp2, Tmp1);
3218 // Expand Y = FABS(X) -> Y = (X >u 0.0) ? X : fneg(X).
3219 MVT::ValueType VT = Node->getValueType(0);
3220 Tmp2 = DAG.getConstantFP(0.0, VT);
3221 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), Tmp1, Tmp2, ISD::SETUGT);
3222 Tmp3 = DAG.getNode(ISD::FNEG, VT, Tmp1);
3223 Result = DAG.getNode(ISD::SELECT, VT, Tmp2, Tmp1, Tmp3);
3229 MVT::ValueType VT = Node->getValueType(0);
3231 // Expand unsupported unary vector operators by unrolling them.
3232 if (MVT::isVector(VT)) {
3233 Result = LegalizeOp(UnrollVectorOp(Op));
3237 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
3238 switch(Node->getOpcode()) {
3240 LC = VT == MVT::f32 ? RTLIB::SQRT_F32 :
3241 VT == MVT::f64 ? RTLIB::SQRT_F64 :
3242 VT == MVT::f80 ? RTLIB::SQRT_F80 :
3243 VT == MVT::ppcf128 ? RTLIB::SQRT_PPCF128 :
3244 RTLIB::UNKNOWN_LIBCALL;
3247 LC = VT == MVT::f32 ? RTLIB::SIN_F32 : RTLIB::SIN_F64;
3250 LC = VT == MVT::f32 ? RTLIB::COS_F32 : RTLIB::COS_F64;
3252 default: assert(0 && "Unreachable!");
3255 Result = ExpandLibCall(TLI.getLibcallName(LC), Node,
3256 false/*sign irrelevant*/, Dummy);
3264 MVT::ValueType VT = Node->getValueType(0);
3266 // Expand unsupported unary vector operators by unrolling them.
3267 if (MVT::isVector(VT)) {
3268 Result = LegalizeOp(UnrollVectorOp(Op));
3272 // We always lower FPOWI into a libcall. No target support for it yet.
3274 VT == MVT::f32 ? RTLIB::POWI_F32 :
3275 VT == MVT::f64 ? RTLIB::POWI_F64 :
3276 VT == MVT::f80 ? RTLIB::POWI_F80 :
3277 VT == MVT::ppcf128 ? RTLIB::POWI_PPCF128 :
3278 RTLIB::UNKNOWN_LIBCALL;
3280 Result = ExpandLibCall(TLI.getLibcallName(LC), Node,
3281 false/*sign irrelevant*/, Dummy);
3284 case ISD::BIT_CONVERT:
3285 if (!isTypeLegal(Node->getOperand(0).getValueType())) {
3286 Result = ExpandBIT_CONVERT(Node->getValueType(0), Node->getOperand(0));
3287 } else if (MVT::isVector(Op.getOperand(0).getValueType())) {
3288 // The input has to be a vector type, we have to either scalarize it, pack
3289 // it, or convert it based on whether the input vector type is legal.
3290 SDNode *InVal = Node->getOperand(0).Val;
3291 int InIx = Node->getOperand(0).ResNo;
3292 unsigned NumElems = MVT::getVectorNumElements(InVal->getValueType(InIx));
3293 MVT::ValueType EVT = MVT::getVectorElementType(InVal->getValueType(InIx));
3295 // Figure out if there is a simple type corresponding to this Vector
3296 // type. If so, convert to the vector type.
3297 MVT::ValueType TVT = MVT::getVectorType(EVT, NumElems);
3298 if (TLI.isTypeLegal(TVT)) {
3299 // Turn this into a bit convert of the vector input.
3300 Result = DAG.getNode(ISD::BIT_CONVERT, Node->getValueType(0),
3301 LegalizeOp(Node->getOperand(0)));
3303 } else if (NumElems == 1) {
3304 // Turn this into a bit convert of the scalar input.
3305 Result = DAG.getNode(ISD::BIT_CONVERT, Node->getValueType(0),
3306 ScalarizeVectorOp(Node->getOperand(0)));
3309 // FIXME: UNIMP! Store then reload
3310 assert(0 && "Cast from unsupported vector type not implemented yet!");
3313 switch (TLI.getOperationAction(ISD::BIT_CONVERT,
3314 Node->getOperand(0).getValueType())) {
3315 default: assert(0 && "Unknown operation action!");
3316 case TargetLowering::Expand:
3317 Result = ExpandBIT_CONVERT(Node->getValueType(0), Node->getOperand(0));
3319 case TargetLowering::Legal:
3320 Tmp1 = LegalizeOp(Node->getOperand(0));
3321 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3327 // Conversion operators. The source and destination have different types.
3328 case ISD::SINT_TO_FP:
3329 case ISD::UINT_TO_FP: {
3330 bool isSigned = Node->getOpcode() == ISD::SINT_TO_FP;
3331 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3333 switch (TLI.getOperationAction(Node->getOpcode(),
3334 Node->getOperand(0).getValueType())) {
3335 default: assert(0 && "Unknown operation action!");
3336 case TargetLowering::Custom:
3339 case TargetLowering::Legal:
3340 Tmp1 = LegalizeOp(Node->getOperand(0));
3341 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3343 Tmp1 = TLI.LowerOperation(Result, DAG);
3344 if (Tmp1.Val) Result = Tmp1;
3347 case TargetLowering::Expand:
3348 Result = ExpandLegalINT_TO_FP(isSigned,
3349 LegalizeOp(Node->getOperand(0)),
3350 Node->getValueType(0));
3352 case TargetLowering::Promote:
3353 Result = PromoteLegalINT_TO_FP(LegalizeOp(Node->getOperand(0)),
3354 Node->getValueType(0),
3360 Result = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP,
3361 Node->getValueType(0), Node->getOperand(0));
3364 Tmp1 = PromoteOp(Node->getOperand(0));
3366 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, Tmp1.getValueType(),
3367 Tmp1, DAG.getValueType(Node->getOperand(0).getValueType()));
3369 Tmp1 = DAG.getZeroExtendInReg(Tmp1,
3370 Node->getOperand(0).getValueType());
3372 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3373 Result = LegalizeOp(Result); // The 'op' is not necessarily legal!
3379 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3381 Tmp1 = LegalizeOp(Node->getOperand(0));
3382 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3385 ExpandOp(Node->getOperand(0), Tmp1, Tmp2);
3387 // Since the result is legal, we should just be able to truncate the low
3388 // part of the source.
3389 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), Tmp1);
3392 Result = PromoteOp(Node->getOperand(0));
3393 Result = DAG.getNode(ISD::TRUNCATE, Op.getValueType(), Result);
3398 case ISD::FP_TO_SINT:
3399 case ISD::FP_TO_UINT:
3400 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3402 Tmp1 = LegalizeOp(Node->getOperand(0));
3404 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))){
3405 default: assert(0 && "Unknown operation action!");
3406 case TargetLowering::Custom:
3409 case TargetLowering::Legal:
3410 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3412 Tmp1 = TLI.LowerOperation(Result, DAG);
3413 if (Tmp1.Val) Result = Tmp1;
3416 case TargetLowering::Promote:
3417 Result = PromoteLegalFP_TO_INT(Tmp1, Node->getValueType(0),
3418 Node->getOpcode() == ISD::FP_TO_SINT);
3420 case TargetLowering::Expand:
3421 if (Node->getOpcode() == ISD::FP_TO_UINT) {
3422 SDOperand True, False;
3423 MVT::ValueType VT = Node->getOperand(0).getValueType();
3424 MVT::ValueType NVT = Node->getValueType(0);
3425 unsigned ShiftAmt = MVT::getSizeInBits(NVT)-1;
3426 const uint64_t zero[] = {0, 0};
3427 APFloat apf = APFloat(APInt(MVT::getSizeInBits(VT), 2, zero));
3428 uint64_t x = 1ULL << ShiftAmt;
3429 (void)apf.convertFromZeroExtendedInteger
3430 (&x, MVT::getSizeInBits(NVT), false, APFloat::rmNearestTiesToEven);
3431 Tmp2 = DAG.getConstantFP(apf, VT);
3432 Tmp3 = DAG.getSetCC(TLI.getSetCCResultTy(),
3433 Node->getOperand(0), Tmp2, ISD::SETLT);
3434 True = DAG.getNode(ISD::FP_TO_SINT, NVT, Node->getOperand(0));
3435 False = DAG.getNode(ISD::FP_TO_SINT, NVT,
3436 DAG.getNode(ISD::FSUB, VT, Node->getOperand(0),
3438 False = DAG.getNode(ISD::XOR, NVT, False,
3439 DAG.getConstant(1ULL << ShiftAmt, NVT));
3440 Result = DAG.getNode(ISD::SELECT, NVT, Tmp3, True, False);
3443 assert(0 && "Do not know how to expand FP_TO_SINT yet!");
3449 MVT::ValueType VT = Op.getValueType();
3450 MVT::ValueType OVT = Node->getOperand(0).getValueType();
3451 // Convert ppcf128 to i32
3452 if (OVT == MVT::ppcf128 && VT == MVT::i32) {
3453 if (Node->getOpcode()==ISD::FP_TO_SINT)
3454 Result = DAG.getNode(ISD::FP_TO_SINT, VT,
3455 DAG.getNode(ISD::FP_ROUND, MVT::f64,
3456 (DAG.getNode(ISD::FP_ROUND_INREG,
3457 MVT::ppcf128, Node->getOperand(0),
3458 DAG.getValueType(MVT::f64)))));
3460 const uint64_t TwoE31[] = {0x41e0000000000000LL, 0};
3461 APFloat apf = APFloat(APInt(128, 2, TwoE31));
3462 Tmp2 = DAG.getConstantFP(apf, OVT);
3463 // X>=2^31 ? (int)(X-2^31)+0x80000000 : (int)X
3464 // FIXME: generated code sucks.
3465 Result = DAG.getNode(ISD::SELECT_CC, VT, Node->getOperand(0), Tmp2,
3466 DAG.getNode(ISD::ADD, MVT::i32,
3467 DAG.getNode(ISD::FP_TO_SINT, VT,
3468 DAG.getNode(ISD::FSUB, OVT,
3469 Node->getOperand(0), Tmp2)),
3470 DAG.getConstant(0x80000000, MVT::i32)),
3471 DAG.getNode(ISD::FP_TO_SINT, VT,
3472 Node->getOperand(0)),
3473 DAG.getCondCode(ISD::SETGE));
3477 // Convert f32 / f64 to i32 / i64.
3478 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
3479 switch (Node->getOpcode()) {
3480 case ISD::FP_TO_SINT: {
3481 if (OVT == MVT::f32)
3482 LC = (VT == MVT::i32)
3483 ? RTLIB::FPTOSINT_F32_I32 : RTLIB::FPTOSINT_F32_I64;
3484 else if (OVT == MVT::f64)
3485 LC = (VT == MVT::i32)
3486 ? RTLIB::FPTOSINT_F64_I32 : RTLIB::FPTOSINT_F64_I64;
3487 else if (OVT == MVT::f80) {
3488 assert(VT == MVT::i64);
3489 LC = RTLIB::FPTOSINT_F80_I64;
3491 else if (OVT == MVT::ppcf128) {
3492 assert(VT == MVT::i64);
3493 LC = RTLIB::FPTOSINT_PPCF128_I64;
3497 case ISD::FP_TO_UINT: {
3498 if (OVT == MVT::f32)
3499 LC = (VT == MVT::i32)
3500 ? RTLIB::FPTOUINT_F32_I32 : RTLIB::FPTOSINT_F32_I64;
3501 else if (OVT == MVT::f64)
3502 LC = (VT == MVT::i32)
3503 ? RTLIB::FPTOUINT_F64_I32 : RTLIB::FPTOSINT_F64_I64;
3504 else if (OVT == MVT::f80) {
3505 LC = (VT == MVT::i32)
3506 ? RTLIB::FPTOUINT_F80_I32 : RTLIB::FPTOUINT_F80_I64;
3508 else if (OVT == MVT::ppcf128) {
3509 assert(VT == MVT::i64);
3510 LC = RTLIB::FPTOUINT_PPCF128_I64;
3514 default: assert(0 && "Unreachable!");
3517 Result = ExpandLibCall(TLI.getLibcallName(LC), Node,
3518 false/*sign irrelevant*/, Dummy);
3522 Tmp1 = PromoteOp(Node->getOperand(0));
3523 Result = DAG.UpdateNodeOperands(Result, LegalizeOp(Tmp1));
3524 Result = LegalizeOp(Result);
3529 case ISD::FP_EXTEND:
3530 case ISD::FP_ROUND: {
3531 MVT::ValueType newVT = Op.getValueType();
3532 MVT::ValueType oldVT = Op.getOperand(0).getValueType();
3533 if (TLI.getConvertAction(oldVT, newVT) == TargetLowering::Expand) {
3534 if (Node->getOpcode() == ISD::FP_ROUND && oldVT == MVT::ppcf128) {
3536 ExpandOp(Node->getOperand(0), Lo, Hi);
3537 if (newVT == MVT::f64)
3540 Result = DAG.getNode(ISD::FP_ROUND, newVT, Hi);
3543 // The only other way we can lower this is to turn it into a STORE,
3544 // LOAD pair, targetting a temporary location (a stack slot).
3546 // NOTE: there is a choice here between constantly creating new stack
3547 // slots and always reusing the same one. We currently always create
3548 // new ones, as reuse may inhibit scheduling.
3549 MVT::ValueType slotVT =
3550 (Node->getOpcode() == ISD::FP_EXTEND) ? oldVT : newVT;
3551 const Type *Ty = MVT::getTypeForValueType(slotVT);
3552 uint64_t TySize = TLI.getTargetData()->getABITypeSize(Ty);
3553 unsigned Align = TLI.getTargetData()->getPrefTypeAlignment(Ty);
3554 MachineFunction &MF = DAG.getMachineFunction();
3556 MF.getFrameInfo()->CreateStackObject(TySize, Align);
3557 SDOperand StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy());
3558 if (Node->getOpcode() == ISD::FP_EXTEND) {
3559 Result = DAG.getStore(DAG.getEntryNode(), Node->getOperand(0),
3560 StackSlot, NULL, 0);
3561 Result = DAG.getExtLoad(ISD::EXTLOAD, newVT,
3562 Result, StackSlot, NULL, 0, oldVT);
3564 Result = DAG.getTruncStore(DAG.getEntryNode(), Node->getOperand(0),
3565 StackSlot, NULL, 0, newVT);
3566 Result = DAG.getLoad(newVT, Result, StackSlot, NULL, 0);
3573 case ISD::ANY_EXTEND:
3574 case ISD::ZERO_EXTEND:
3575 case ISD::SIGN_EXTEND:
3576 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3577 case Expand: assert(0 && "Shouldn't need to expand other operators here!");
3579 Tmp1 = LegalizeOp(Node->getOperand(0));
3580 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3583 switch (Node->getOpcode()) {
3584 case ISD::ANY_EXTEND:
3585 Tmp1 = PromoteOp(Node->getOperand(0));
3586 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Tmp1);
3588 case ISD::ZERO_EXTEND:
3589 Result = PromoteOp(Node->getOperand(0));
3590 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Result);
3591 Result = DAG.getZeroExtendInReg(Result,
3592 Node->getOperand(0).getValueType());
3594 case ISD::SIGN_EXTEND:
3595 Result = PromoteOp(Node->getOperand(0));
3596 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Result);
3597 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(),
3599 DAG.getValueType(Node->getOperand(0).getValueType()));
3601 case ISD::FP_EXTEND:
3602 Result = PromoteOp(Node->getOperand(0));
3603 if (Result.getValueType() != Op.getValueType())
3604 // Dynamically dead while we have only 2 FP types.
3605 Result = DAG.getNode(ISD::FP_EXTEND, Op.getValueType(), Result);
3608 Result = PromoteOp(Node->getOperand(0));
3609 Result = DAG.getNode(Node->getOpcode(), Op.getValueType(), Result);
3614 case ISD::FP_ROUND_INREG:
3615 case ISD::SIGN_EXTEND_INREG: {
3616 Tmp1 = LegalizeOp(Node->getOperand(0));
3617 MVT::ValueType ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT();
3619 // If this operation is not supported, convert it to a shl/shr or load/store
3621 switch (TLI.getOperationAction(Node->getOpcode(), ExtraVT)) {
3622 default: assert(0 && "This action not supported for this op yet!");
3623 case TargetLowering::Legal:
3624 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
3626 case TargetLowering::Expand:
3627 // If this is an integer extend and shifts are supported, do that.
3628 if (Node->getOpcode() == ISD::SIGN_EXTEND_INREG) {
3629 // NOTE: we could fall back on load/store here too for targets without
3630 // SAR. However, it is doubtful that any exist.
3631 unsigned BitsDiff = MVT::getSizeInBits(Node->getValueType(0)) -
3632 MVT::getSizeInBits(ExtraVT);
3633 SDOperand ShiftCst = DAG.getConstant(BitsDiff, TLI.getShiftAmountTy());
3634 Result = DAG.getNode(ISD::SHL, Node->getValueType(0),
3635 Node->getOperand(0), ShiftCst);
3636 Result = DAG.getNode(ISD::SRA, Node->getValueType(0),
3638 } else if (Node->getOpcode() == ISD::FP_ROUND_INREG) {
3639 // The only way we can lower this is to turn it into a TRUNCSTORE,
3640 // EXTLOAD pair, targetting a temporary location (a stack slot).
3642 // NOTE: there is a choice here between constantly creating new stack
3643 // slots and always reusing the same one. We currently always create
3644 // new ones, as reuse may inhibit scheduling.
3645 const Type *Ty = MVT::getTypeForValueType(ExtraVT);
3646 uint64_t TySize = TLI.getTargetData()->getABITypeSize(Ty);
3647 unsigned Align = TLI.getTargetData()->getPrefTypeAlignment(Ty);
3648 MachineFunction &MF = DAG.getMachineFunction();
3650 MF.getFrameInfo()->CreateStackObject(TySize, Align);
3651 SDOperand StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy());
3652 Result = DAG.getTruncStore(DAG.getEntryNode(), Node->getOperand(0),
3653 StackSlot, NULL, 0, ExtraVT);
3654 Result = DAG.getExtLoad(ISD::EXTLOAD, Node->getValueType(0),
3655 Result, StackSlot, NULL, 0, ExtraVT);
3657 assert(0 && "Unknown op");
3663 case ISD::TRAMPOLINE: {
3665 for (unsigned i = 0; i != 6; ++i)
3666 Ops[i] = LegalizeOp(Node->getOperand(i));
3667 Result = DAG.UpdateNodeOperands(Result, Ops, 6);
3668 // The only option for this node is to custom lower it.
3669 Result = TLI.LowerOperation(Result, DAG);
3670 assert(Result.Val && "Should always custom lower!");
3672 // Since trampoline produces two values, make sure to remember that we
3673 // legalized both of them.
3674 Tmp1 = LegalizeOp(Result.getValue(1));
3675 Result = LegalizeOp(Result);
3676 AddLegalizedOperand(SDOperand(Node, 0), Result);
3677 AddLegalizedOperand(SDOperand(Node, 1), Tmp1);
3678 return Op.ResNo ? Tmp1 : Result;
3680 case ISD::FLT_ROUNDS: {
3681 MVT::ValueType VT = Node->getValueType(0);
3682 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
3683 default: assert(0 && "This action not supported for this op yet!");
3684 case TargetLowering::Custom:
3685 Result = TLI.LowerOperation(Op, DAG);
3686 if (Result.Val) break;
3688 case TargetLowering::Legal:
3689 // If this operation is not supported, lower it to constant 1
3690 Result = DAG.getConstant(1, VT);
3696 assert(Result.getValueType() == Op.getValueType() &&
3697 "Bad legalization!");
3699 // Make sure that the generated code is itself legal.
3701 Result = LegalizeOp(Result);
3703 // Note that LegalizeOp may be reentered even from single-use nodes, which
3704 // means that we always must cache transformed nodes.
3705 AddLegalizedOperand(Op, Result);
3709 /// PromoteOp - Given an operation that produces a value in an invalid type,
3710 /// promote it to compute the value into a larger type. The produced value will
3711 /// have the correct bits for the low portion of the register, but no guarantee
3712 /// is made about the top bits: it may be zero, sign-extended, or garbage.
3713 SDOperand SelectionDAGLegalize::PromoteOp(SDOperand Op) {
3714 MVT::ValueType VT = Op.getValueType();
3715 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT);
3716 assert(getTypeAction(VT) == Promote &&
3717 "Caller should expand or legalize operands that are not promotable!");
3718 assert(NVT > VT && MVT::isInteger(NVT) == MVT::isInteger(VT) &&
3719 "Cannot promote to smaller type!");
3721 SDOperand Tmp1, Tmp2, Tmp3;
3723 SDNode *Node = Op.Val;
3725 DenseMap<SDOperand, SDOperand>::iterator I = PromotedNodes.find(Op);
3726 if (I != PromotedNodes.end()) return I->second;
3728 switch (Node->getOpcode()) {
3729 case ISD::CopyFromReg:
3730 assert(0 && "CopyFromReg must be legal!");
3733 cerr << "NODE: "; Node->dump(&DAG); cerr << "\n";
3735 assert(0 && "Do not know how to promote this operator!");
3738 Result = DAG.getNode(ISD::UNDEF, NVT);
3742 Result = DAG.getNode(ISD::SIGN_EXTEND, NVT, Op);
3744 Result = DAG.getNode(ISD::ZERO_EXTEND, NVT, Op);
3745 assert(isa<ConstantSDNode>(Result) && "Didn't constant fold zext?");
3747 case ISD::ConstantFP:
3748 Result = DAG.getNode(ISD::FP_EXTEND, NVT, Op);
3749 assert(isa<ConstantFPSDNode>(Result) && "Didn't constant fold fp_extend?");
3753 assert(isTypeLegal(TLI.getSetCCResultTy()) && "SetCC type is not legal??");
3754 Result = DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(),Node->getOperand(0),
3755 Node->getOperand(1), Node->getOperand(2));
3759 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3761 Result = LegalizeOp(Node->getOperand(0));
3762 assert(Result.getValueType() >= NVT &&
3763 "This truncation doesn't make sense!");
3764 if (Result.getValueType() > NVT) // Truncate to NVT instead of VT
3765 Result = DAG.getNode(ISD::TRUNCATE, NVT, Result);
3768 // The truncation is not required, because we don't guarantee anything
3769 // about high bits anyway.
3770 Result = PromoteOp(Node->getOperand(0));
3773 ExpandOp(Node->getOperand(0), Tmp1, Tmp2);
3774 // Truncate the low part of the expanded value to the result type
3775 Result = DAG.getNode(ISD::TRUNCATE, NVT, Tmp1);
3778 case ISD::SIGN_EXTEND:
3779 case ISD::ZERO_EXTEND:
3780 case ISD::ANY_EXTEND:
3781 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3782 case Expand: assert(0 && "BUG: Smaller reg should have been promoted!");
3784 // Input is legal? Just do extend all the way to the larger type.
3785 Result = DAG.getNode(Node->getOpcode(), NVT, Node->getOperand(0));
3788 // Promote the reg if it's smaller.
3789 Result = PromoteOp(Node->getOperand(0));
3790 // The high bits are not guaranteed to be anything. Insert an extend.
3791 if (Node->getOpcode() == ISD::SIGN_EXTEND)
3792 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Result,
3793 DAG.getValueType(Node->getOperand(0).getValueType()));
3794 else if (Node->getOpcode() == ISD::ZERO_EXTEND)
3795 Result = DAG.getZeroExtendInReg(Result,
3796 Node->getOperand(0).getValueType());
3800 case ISD::BIT_CONVERT:
3801 Result = ExpandBIT_CONVERT(Node->getValueType(0), Node->getOperand(0));
3802 Result = PromoteOp(Result);
3805 case ISD::FP_EXTEND:
3806 assert(0 && "Case not implemented. Dynamically dead with 2 FP types!");
3808 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3809 case Expand: assert(0 && "BUG: Cannot expand FP regs!");
3810 case Promote: assert(0 && "Unreachable with 2 FP types!");
3812 // Input is legal? Do an FP_ROUND_INREG.
3813 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Node->getOperand(0),
3814 DAG.getValueType(VT));
3819 case ISD::SINT_TO_FP:
3820 case ISD::UINT_TO_FP:
3821 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3823 // No extra round required here.
3824 Result = DAG.getNode(Node->getOpcode(), NVT, Node->getOperand(0));
3828 Result = PromoteOp(Node->getOperand(0));
3829 if (Node->getOpcode() == ISD::SINT_TO_FP)
3830 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(),
3832 DAG.getValueType(Node->getOperand(0).getValueType()));
3834 Result = DAG.getZeroExtendInReg(Result,
3835 Node->getOperand(0).getValueType());
3836 // No extra round required here.
3837 Result = DAG.getNode(Node->getOpcode(), NVT, Result);
3840 Result = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP, NVT,
3841 Node->getOperand(0));
3842 // Round if we cannot tolerate excess precision.
3843 if (NoExcessFPPrecision)
3844 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
3845 DAG.getValueType(VT));
3850 case ISD::SIGN_EXTEND_INREG:
3851 Result = PromoteOp(Node->getOperand(0));
3852 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Result,
3853 Node->getOperand(1));
3855 case ISD::FP_TO_SINT:
3856 case ISD::FP_TO_UINT:
3857 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3860 Tmp1 = Node->getOperand(0);
3863 // The input result is prerounded, so we don't have to do anything
3865 Tmp1 = PromoteOp(Node->getOperand(0));
3868 // If we're promoting a UINT to a larger size, check to see if the new node
3869 // will be legal. If it isn't, check to see if FP_TO_SINT is legal, since
3870 // we can use that instead. This allows us to generate better code for
3871 // FP_TO_UINT for small destination sizes on targets where FP_TO_UINT is not
3872 // legal, such as PowerPC.
3873 if (Node->getOpcode() == ISD::FP_TO_UINT &&
3874 !TLI.isOperationLegal(ISD::FP_TO_UINT, NVT) &&
3875 (TLI.isOperationLegal(ISD::FP_TO_SINT, NVT) ||
3876 TLI.getOperationAction(ISD::FP_TO_SINT, NVT)==TargetLowering::Custom)){
3877 Result = DAG.getNode(ISD::FP_TO_SINT, NVT, Tmp1);
3879 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
3885 Tmp1 = PromoteOp(Node->getOperand(0));
3886 assert(Tmp1.getValueType() == NVT);
3887 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
3888 // NOTE: we do not have to do any extra rounding here for
3889 // NoExcessFPPrecision, because we know the input will have the appropriate
3890 // precision, and these operations don't modify precision at all.
3896 Tmp1 = PromoteOp(Node->getOperand(0));
3897 assert(Tmp1.getValueType() == NVT);
3898 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
3899 if (NoExcessFPPrecision)
3900 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
3901 DAG.getValueType(VT));
3905 // Promote f32 powi to f64 powi. Note that this could insert a libcall
3906 // directly as well, which may be better.
3907 Tmp1 = PromoteOp(Node->getOperand(0));
3908 assert(Tmp1.getValueType() == NVT);
3909 Result = DAG.getNode(ISD::FPOWI, NVT, Tmp1, Node->getOperand(1));
3910 if (NoExcessFPPrecision)
3911 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
3912 DAG.getValueType(VT));
3922 // The input may have strange things in the top bits of the registers, but
3923 // these operations don't care. They may have weird bits going out, but
3924 // that too is okay if they are integer operations.
3925 Tmp1 = PromoteOp(Node->getOperand(0));
3926 Tmp2 = PromoteOp(Node->getOperand(1));
3927 assert(Tmp1.getValueType() == NVT && Tmp2.getValueType() == NVT);
3928 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
3933 Tmp1 = PromoteOp(Node->getOperand(0));
3934 Tmp2 = PromoteOp(Node->getOperand(1));
3935 assert(Tmp1.getValueType() == NVT && Tmp2.getValueType() == NVT);
3936 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
3938 // Floating point operations will give excess precision that we may not be
3939 // able to tolerate. If we DO allow excess precision, just leave it,
3940 // otherwise excise it.
3941 // FIXME: Why would we need to round FP ops more than integer ones?
3942 // Is Round(Add(Add(A,B),C)) != Round(Add(Round(Add(A,B)), C))
3943 if (NoExcessFPPrecision)
3944 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
3945 DAG.getValueType(VT));
3950 // These operators require that their input be sign extended.
3951 Tmp1 = PromoteOp(Node->getOperand(0));
3952 Tmp2 = PromoteOp(Node->getOperand(1));
3953 if (MVT::isInteger(NVT)) {
3954 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1,
3955 DAG.getValueType(VT));
3956 Tmp2 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp2,
3957 DAG.getValueType(VT));
3959 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
3961 // Perform FP_ROUND: this is probably overly pessimistic.
3962 if (MVT::isFloatingPoint(NVT) && NoExcessFPPrecision)
3963 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
3964 DAG.getValueType(VT));
3968 case ISD::FCOPYSIGN:
3969 // These operators require that their input be fp extended.
3970 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3972 Tmp1 = LegalizeOp(Node->getOperand(0));
3975 Tmp1 = PromoteOp(Node->getOperand(0));
3978 assert(0 && "not implemented");
3980 switch (getTypeAction(Node->getOperand(1).getValueType())) {
3982 Tmp2 = LegalizeOp(Node->getOperand(1));
3985 Tmp2 = PromoteOp(Node->getOperand(1));
3988 assert(0 && "not implemented");
3990 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
3992 // Perform FP_ROUND: this is probably overly pessimistic.
3993 if (NoExcessFPPrecision && Node->getOpcode() != ISD::FCOPYSIGN)
3994 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
3995 DAG.getValueType(VT));
4000 // These operators require that their input be zero extended.
4001 Tmp1 = PromoteOp(Node->getOperand(0));
4002 Tmp2 = PromoteOp(Node->getOperand(1));
4003 assert(MVT::isInteger(NVT) && "Operators don't apply to FP!");
4004 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT);
4005 Tmp2 = DAG.getZeroExtendInReg(Tmp2, VT);
4006 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
4010 Tmp1 = PromoteOp(Node->getOperand(0));
4011 Result = DAG.getNode(ISD::SHL, NVT, Tmp1, Node->getOperand(1));
4014 // The input value must be properly sign extended.
4015 Tmp1 = PromoteOp(Node->getOperand(0));
4016 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1,
4017 DAG.getValueType(VT));
4018 Result = DAG.getNode(ISD::SRA, NVT, Tmp1, Node->getOperand(1));
4021 // The input value must be properly zero extended.
4022 Tmp1 = PromoteOp(Node->getOperand(0));
4023 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT);
4024 Result = DAG.getNode(ISD::SRL, NVT, Tmp1, Node->getOperand(1));
4028 Tmp1 = Node->getOperand(0); // Get the chain.
4029 Tmp2 = Node->getOperand(1); // Get the pointer.
4030 if (TLI.getOperationAction(ISD::VAARG, VT) == TargetLowering::Custom) {
4031 Tmp3 = DAG.getVAArg(VT, Tmp1, Tmp2, Node->getOperand(2));
4032 Result = TLI.CustomPromoteOperation(Tmp3, DAG);
4034 SrcValueSDNode *SV = cast<SrcValueSDNode>(Node->getOperand(2));
4035 SDOperand VAList = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp2,
4036 SV->getValue(), SV->getOffset());
4037 // Increment the pointer, VAList, to the next vaarg
4038 Tmp3 = DAG.getNode(ISD::ADD, TLI.getPointerTy(), VAList,
4039 DAG.getConstant(MVT::getSizeInBits(VT)/8,
4040 TLI.getPointerTy()));
4041 // Store the incremented VAList to the legalized pointer
4042 Tmp3 = DAG.getStore(VAList.getValue(1), Tmp3, Tmp2, SV->getValue(),
4044 // Load the actual argument out of the pointer VAList
4045 Result = DAG.getExtLoad(ISD::EXTLOAD, NVT, Tmp3, VAList, NULL, 0, VT);
4047 // Remember that we legalized the chain.
4048 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
4052 LoadSDNode *LD = cast<LoadSDNode>(Node);
4053 ISD::LoadExtType ExtType = ISD::isNON_EXTLoad(Node)
4054 ? ISD::EXTLOAD : LD->getExtensionType();
4055 Result = DAG.getExtLoad(ExtType, NVT,
4056 LD->getChain(), LD->getBasePtr(),
4057 LD->getSrcValue(), LD->getSrcValueOffset(),
4060 LD->getAlignment());
4061 // Remember that we legalized the chain.
4062 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
4066 Tmp2 = PromoteOp(Node->getOperand(1)); // Legalize the op0
4067 Tmp3 = PromoteOp(Node->getOperand(2)); // Legalize the op1
4068 Result = DAG.getNode(ISD::SELECT, NVT, Node->getOperand(0), Tmp2, Tmp3);
4070 case ISD::SELECT_CC:
4071 Tmp2 = PromoteOp(Node->getOperand(2)); // True
4072 Tmp3 = PromoteOp(Node->getOperand(3)); // False
4073 Result = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0),
4074 Node->getOperand(1), Tmp2, Tmp3, Node->getOperand(4));
4077 Tmp1 = Node->getOperand(0);
4078 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1);
4079 Tmp1 = DAG.getNode(ISD::BSWAP, NVT, Tmp1);
4080 Result = DAG.getNode(ISD::SRL, NVT, Tmp1,
4081 DAG.getConstant(MVT::getSizeInBits(NVT) -
4082 MVT::getSizeInBits(VT),
4083 TLI.getShiftAmountTy()));
4088 // Zero extend the argument
4089 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Node->getOperand(0));
4090 // Perform the larger operation, then subtract if needed.
4091 Tmp1 = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
4092 switch(Node->getOpcode()) {
4097 // if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT)
4098 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), Tmp1,
4099 DAG.getConstant(MVT::getSizeInBits(NVT), NVT),
4101 Result = DAG.getNode(ISD::SELECT, NVT, Tmp2,
4102 DAG.getConstant(MVT::getSizeInBits(VT), NVT), Tmp1);
4105 //Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT))
4106 Result = DAG.getNode(ISD::SUB, NVT, Tmp1,
4107 DAG.getConstant(MVT::getSizeInBits(NVT) -
4108 MVT::getSizeInBits(VT), NVT));
4112 case ISD::EXTRACT_SUBVECTOR:
4113 Result = PromoteOp(ExpandEXTRACT_SUBVECTOR(Op));
4115 case ISD::EXTRACT_VECTOR_ELT:
4116 Result = PromoteOp(ExpandEXTRACT_VECTOR_ELT(Op));
4120 assert(Result.Val && "Didn't set a result!");
4122 // Make sure the result is itself legal.
4123 Result = LegalizeOp(Result);
4125 // Remember that we promoted this!
4126 AddPromotedOperand(Op, Result);
4130 /// ExpandEXTRACT_VECTOR_ELT - Expand an EXTRACT_VECTOR_ELT operation into
4131 /// a legal EXTRACT_VECTOR_ELT operation, scalar code, or memory traffic,
4132 /// based on the vector type. The return type of this matches the element type
4133 /// of the vector, which may not be legal for the target.
4134 SDOperand SelectionDAGLegalize::ExpandEXTRACT_VECTOR_ELT(SDOperand Op) {
4135 // We know that operand #0 is the Vec vector. If the index is a constant
4136 // or if the invec is a supported hardware type, we can use it. Otherwise,
4137 // lower to a store then an indexed load.
4138 SDOperand Vec = Op.getOperand(0);
4139 SDOperand Idx = Op.getOperand(1);
4141 MVT::ValueType TVT = Vec.getValueType();
4142 unsigned NumElems = MVT::getVectorNumElements(TVT);
4144 switch (TLI.getOperationAction(ISD::EXTRACT_VECTOR_ELT, TVT)) {
4145 default: assert(0 && "This action is not supported yet!");
4146 case TargetLowering::Custom: {
4147 Vec = LegalizeOp(Vec);
4148 Op = DAG.UpdateNodeOperands(Op, Vec, Idx);
4149 SDOperand Tmp3 = TLI.LowerOperation(Op, DAG);
4154 case TargetLowering::Legal:
4155 if (isTypeLegal(TVT)) {
4156 Vec = LegalizeOp(Vec);
4157 Op = DAG.UpdateNodeOperands(Op, Vec, Idx);
4161 case TargetLowering::Expand:
4165 if (NumElems == 1) {
4166 // This must be an access of the only element. Return it.
4167 Op = ScalarizeVectorOp(Vec);
4168 } else if (!TLI.isTypeLegal(TVT) && isa<ConstantSDNode>(Idx)) {
4169 ConstantSDNode *CIdx = cast<ConstantSDNode>(Idx);
4171 SplitVectorOp(Vec, Lo, Hi);
4172 if (CIdx->getValue() < NumElems/2) {
4176 Idx = DAG.getConstant(CIdx->getValue() - NumElems/2,
4177 Idx.getValueType());
4180 // It's now an extract from the appropriate high or low part. Recurse.
4181 Op = DAG.UpdateNodeOperands(Op, Vec, Idx);
4182 Op = ExpandEXTRACT_VECTOR_ELT(Op);
4184 // Store the value to a temporary stack slot, then LOAD the scalar
4185 // element back out.
4186 SDOperand StackPtr = DAG.CreateStackTemporary(Vec.getValueType());
4187 SDOperand Ch = DAG.getStore(DAG.getEntryNode(), Vec, StackPtr, NULL, 0);
4189 // Add the offset to the index.
4190 unsigned EltSize = MVT::getSizeInBits(Op.getValueType())/8;
4191 Idx = DAG.getNode(ISD::MUL, Idx.getValueType(), Idx,
4192 DAG.getConstant(EltSize, Idx.getValueType()));
4194 if (MVT::getSizeInBits(Idx.getValueType()) >
4195 MVT::getSizeInBits(TLI.getPointerTy()))
4196 Idx = DAG.getNode(ISD::TRUNCATE, TLI.getPointerTy(), Idx);
4198 Idx = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(), Idx);
4200 StackPtr = DAG.getNode(ISD::ADD, Idx.getValueType(), Idx, StackPtr);
4202 Op = DAG.getLoad(Op.getValueType(), Ch, StackPtr, NULL, 0);
4207 /// ExpandEXTRACT_SUBVECTOR - Expand a EXTRACT_SUBVECTOR operation. For now
4208 /// we assume the operation can be split if it is not already legal.
4209 SDOperand SelectionDAGLegalize::ExpandEXTRACT_SUBVECTOR(SDOperand Op) {
4210 // We know that operand #0 is the Vec vector. For now we assume the index
4211 // is a constant and that the extracted result is a supported hardware type.
4212 SDOperand Vec = Op.getOperand(0);
4213 SDOperand Idx = LegalizeOp(Op.getOperand(1));
4215 unsigned NumElems = MVT::getVectorNumElements(Vec.getValueType());
4217 if (NumElems == MVT::getVectorNumElements(Op.getValueType())) {
4218 // This must be an access of the desired vector length. Return it.
4222 ConstantSDNode *CIdx = cast<ConstantSDNode>(Idx);
4224 SplitVectorOp(Vec, Lo, Hi);
4225 if (CIdx->getValue() < NumElems/2) {
4229 Idx = DAG.getConstant(CIdx->getValue() - NumElems/2, Idx.getValueType());
4232 // It's now an extract from the appropriate high or low part. Recurse.
4233 Op = DAG.UpdateNodeOperands(Op, Vec, Idx);
4234 return ExpandEXTRACT_SUBVECTOR(Op);
4237 /// LegalizeSetCCOperands - Attempts to create a legal LHS and RHS for a SETCC
4238 /// with condition CC on the current target. This usually involves legalizing
4239 /// or promoting the arguments. In the case where LHS and RHS must be expanded,
4240 /// there may be no choice but to create a new SetCC node to represent the
4241 /// legalized value of setcc lhs, rhs. In this case, the value is returned in
4242 /// LHS, and the SDOperand returned in RHS has a nil SDNode value.
4243 void SelectionDAGLegalize::LegalizeSetCCOperands(SDOperand &LHS,
4246 SDOperand Tmp1, Tmp2, Tmp3, Result;
4248 switch (getTypeAction(LHS.getValueType())) {
4250 Tmp1 = LegalizeOp(LHS); // LHS
4251 Tmp2 = LegalizeOp(RHS); // RHS
4254 Tmp1 = PromoteOp(LHS); // LHS
4255 Tmp2 = PromoteOp(RHS); // RHS
4257 // If this is an FP compare, the operands have already been extended.
4258 if (MVT::isInteger(LHS.getValueType())) {
4259 MVT::ValueType VT = LHS.getValueType();
4260 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT);
4262 // Otherwise, we have to insert explicit sign or zero extends. Note
4263 // that we could insert sign extends for ALL conditions, but zero extend
4264 // is cheaper on many machines (an AND instead of two shifts), so prefer
4266 switch (cast<CondCodeSDNode>(CC)->get()) {
4267 default: assert(0 && "Unknown integer comparison!");
4274 // ALL of these operations will work if we either sign or zero extend
4275 // the operands (including the unsigned comparisons!). Zero extend is
4276 // usually a simpler/cheaper operation, so prefer it.
4277 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT);
4278 Tmp2 = DAG.getZeroExtendInReg(Tmp2, VT);
4284 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1,
4285 DAG.getValueType(VT));
4286 Tmp2 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp2,
4287 DAG.getValueType(VT));
4293 MVT::ValueType VT = LHS.getValueType();
4294 if (VT == MVT::f32 || VT == MVT::f64) {
4295 // Expand into one or more soft-fp libcall(s).
4296 RTLIB::Libcall LC1, LC2 = RTLIB::UNKNOWN_LIBCALL;
4297 switch (cast<CondCodeSDNode>(CC)->get()) {
4300 LC1 = (VT == MVT::f32) ? RTLIB::OEQ_F32 : RTLIB::OEQ_F64;
4304 LC1 = (VT == MVT::f32) ? RTLIB::UNE_F32 : RTLIB::UNE_F64;
4308 LC1 = (VT == MVT::f32) ? RTLIB::OGE_F32 : RTLIB::OGE_F64;
4312 LC1 = (VT == MVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64;
4316 LC1 = (VT == MVT::f32) ? RTLIB::OLE_F32 : RTLIB::OLE_F64;
4320 LC1 = (VT == MVT::f32) ? RTLIB::OGT_F32 : RTLIB::OGT_F64;
4323 LC1 = (VT == MVT::f32) ? RTLIB::UO_F32 : RTLIB::UO_F64;
4326 LC1 = (VT == MVT::f32) ? RTLIB::O_F32 : RTLIB::O_F64;
4329 LC1 = (VT == MVT::f32) ? RTLIB::UO_F32 : RTLIB::UO_F64;
4330 switch (cast<CondCodeSDNode>(CC)->get()) {
4332 // SETONE = SETOLT | SETOGT
4333 LC1 = (VT == MVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64;
4336 LC2 = (VT == MVT::f32) ? RTLIB::OGT_F32 : RTLIB::OGT_F64;
4339 LC2 = (VT == MVT::f32) ? RTLIB::OGE_F32 : RTLIB::OGE_F64;
4342 LC2 = (VT == MVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64;
4345 LC2 = (VT == MVT::f32) ? RTLIB::OLE_F32 : RTLIB::OLE_F64;
4348 LC2 = (VT == MVT::f32) ? RTLIB::OEQ_F32 : RTLIB::OEQ_F64;
4350 default: assert(0 && "Unsupported FP setcc!");
4355 Tmp1 = ExpandLibCall(TLI.getLibcallName(LC1),
4356 DAG.getNode(ISD::MERGE_VALUES, VT, LHS, RHS).Val,
4357 false /*sign irrelevant*/, Dummy);
4358 Tmp2 = DAG.getConstant(0, MVT::i32);
4359 CC = DAG.getCondCode(TLI.getCmpLibcallCC(LC1));
4360 if (LC2 != RTLIB::UNKNOWN_LIBCALL) {
4361 Tmp1 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(), Tmp1, Tmp2, CC);
4362 LHS = ExpandLibCall(TLI.getLibcallName(LC2),
4363 DAG.getNode(ISD::MERGE_VALUES, VT, LHS, RHS).Val,
4364 false /*sign irrelevant*/, Dummy);
4365 Tmp2 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(), LHS, Tmp2,
4366 DAG.getCondCode(TLI.getCmpLibcallCC(LC2)));
4367 Tmp1 = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp2);
4375 SDOperand LHSLo, LHSHi, RHSLo, RHSHi;
4376 ExpandOp(LHS, LHSLo, LHSHi);
4377 ExpandOp(RHS, RHSLo, RHSHi);
4378 ISD::CondCode CCCode = cast<CondCodeSDNode>(CC)->get();
4380 if (VT==MVT::ppcf128) {
4381 // FIXME: This generated code sucks. We want to generate
4382 // FCMP crN, hi1, hi2
4384 // FCMP crN, lo1, lo2
4385 // The following can be improved, but not that much.
4386 Tmp1 = DAG.getSetCC(TLI.getSetCCResultTy(), LHSHi, RHSHi, ISD::SETEQ);
4387 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), LHSLo, RHSLo, CCCode);
4388 Tmp3 = DAG.getNode(ISD::AND, Tmp1.getValueType(), Tmp1, Tmp2);
4389 Tmp1 = DAG.getSetCC(TLI.getSetCCResultTy(), LHSHi, RHSHi, ISD::SETNE);
4390 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), LHSHi, RHSHi, CCCode);
4391 Tmp1 = DAG.getNode(ISD::AND, Tmp1.getValueType(), Tmp1, Tmp2);
4392 Tmp1 = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp3);
4401 if (ConstantSDNode *RHSCST = dyn_cast<ConstantSDNode>(RHSLo))
4402 if (RHSCST->isAllOnesValue()) {
4403 // Comparison to -1.
4404 Tmp1 = DAG.getNode(ISD::AND, LHSLo.getValueType(), LHSLo, LHSHi);
4409 Tmp1 = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSLo, RHSLo);
4410 Tmp2 = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSHi, RHSHi);
4411 Tmp1 = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp2);
4412 Tmp2 = DAG.getConstant(0, Tmp1.getValueType());
4415 // If this is a comparison of the sign bit, just look at the top part.
4417 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(RHS))
4418 if ((cast<CondCodeSDNode>(CC)->get() == ISD::SETLT &&
4419 CST->getValue() == 0) || // X < 0
4420 (cast<CondCodeSDNode>(CC)->get() == ISD::SETGT &&
4421 CST->isAllOnesValue())) { // X > -1
4427 // FIXME: This generated code sucks.
4428 ISD::CondCode LowCC;
4430 default: assert(0 && "Unknown integer setcc!");
4432 case ISD::SETULT: LowCC = ISD::SETULT; break;
4434 case ISD::SETUGT: LowCC = ISD::SETUGT; break;
4436 case ISD::SETULE: LowCC = ISD::SETULE; break;
4438 case ISD::SETUGE: LowCC = ISD::SETUGE; break;
4441 // Tmp1 = lo(op1) < lo(op2) // Always unsigned comparison
4442 // Tmp2 = hi(op1) < hi(op2) // Signedness depends on operands
4443 // dest = hi(op1) == hi(op2) ? Tmp1 : Tmp2;
4445 // NOTE: on targets without efficient SELECT of bools, we can always use
4446 // this identity: (B1 ? B2 : B3) --> (B1 & B2)|(!B1&B3)
4447 TargetLowering::DAGCombinerInfo DagCombineInfo(DAG, false, true, NULL);
4448 Tmp1 = TLI.SimplifySetCC(TLI.getSetCCResultTy(), LHSLo, RHSLo, LowCC,
4449 false, DagCombineInfo);
4451 Tmp1 = DAG.getSetCC(TLI.getSetCCResultTy(), LHSLo, RHSLo, LowCC);
4452 Tmp2 = TLI.SimplifySetCC(TLI.getSetCCResultTy(), LHSHi, RHSHi,
4453 CCCode, false, DagCombineInfo);
4455 Tmp2 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(), LHSHi, RHSHi,CC);
4457 ConstantSDNode *Tmp1C = dyn_cast<ConstantSDNode>(Tmp1.Val);
4458 ConstantSDNode *Tmp2C = dyn_cast<ConstantSDNode>(Tmp2.Val);
4459 if ((Tmp1C && Tmp1C->getValue() == 0) ||
4460 (Tmp2C && Tmp2C->getValue() == 0 &&
4461 (CCCode == ISD::SETLE || CCCode == ISD::SETGE ||
4462 CCCode == ISD::SETUGE || CCCode == ISD::SETULE)) ||
4463 (Tmp2C && Tmp2C->getValue() == 1 &&
4464 (CCCode == ISD::SETLT || CCCode == ISD::SETGT ||
4465 CCCode == ISD::SETUGT || CCCode == ISD::SETULT))) {
4466 // low part is known false, returns high part.
4467 // For LE / GE, if high part is known false, ignore the low part.
4468 // For LT / GT, if high part is known true, ignore the low part.
4472 Result = TLI.SimplifySetCC(TLI.getSetCCResultTy(), LHSHi, RHSHi,
4473 ISD::SETEQ, false, DagCombineInfo);
4475 Result=DAG.getSetCC(TLI.getSetCCResultTy(), LHSHi, RHSHi, ISD::SETEQ);
4476 Result = LegalizeOp(DAG.getNode(ISD::SELECT, Tmp1.getValueType(),
4477 Result, Tmp1, Tmp2));
4488 /// ExpandBIT_CONVERT - Expand a BIT_CONVERT node into a store/load combination.
4489 /// The resultant code need not be legal. Note that SrcOp is the input operand
4490 /// to the BIT_CONVERT, not the BIT_CONVERT node itself.
4491 SDOperand SelectionDAGLegalize::ExpandBIT_CONVERT(MVT::ValueType DestVT,
4493 // Create the stack frame object.
4494 SDOperand FIPtr = DAG.CreateStackTemporary(DestVT);
4496 // Emit a store to the stack slot.
4497 SDOperand Store = DAG.getStore(DAG.getEntryNode(), SrcOp, FIPtr, NULL, 0);
4498 // Result is a load from the stack slot.
4499 return DAG.getLoad(DestVT, Store, FIPtr, NULL, 0);
4502 SDOperand SelectionDAGLegalize::ExpandSCALAR_TO_VECTOR(SDNode *Node) {
4503 // Create a vector sized/aligned stack slot, store the value to element #0,
4504 // then load the whole vector back out.
4505 SDOperand StackPtr = DAG.CreateStackTemporary(Node->getValueType(0));
4506 SDOperand Ch = DAG.getStore(DAG.getEntryNode(), Node->getOperand(0), StackPtr,
4508 return DAG.getLoad(Node->getValueType(0), Ch, StackPtr, NULL, 0);
4512 /// ExpandBUILD_VECTOR - Expand a BUILD_VECTOR node on targets that don't
4513 /// support the operation, but do support the resultant vector type.
4514 SDOperand SelectionDAGLegalize::ExpandBUILD_VECTOR(SDNode *Node) {
4516 // If the only non-undef value is the low element, turn this into a
4517 // SCALAR_TO_VECTOR node. If this is { X, X, X, X }, determine X.
4518 unsigned NumElems = Node->getNumOperands();
4519 bool isOnlyLowElement = true;
4520 SDOperand SplatValue = Node->getOperand(0);
4521 std::map<SDOperand, std::vector<unsigned> > Values;
4522 Values[SplatValue].push_back(0);
4523 bool isConstant = true;
4524 if (!isa<ConstantFPSDNode>(SplatValue) && !isa<ConstantSDNode>(SplatValue) &&
4525 SplatValue.getOpcode() != ISD::UNDEF)
4528 for (unsigned i = 1; i < NumElems; ++i) {
4529 SDOperand V = Node->getOperand(i);
4530 Values[V].push_back(i);
4531 if (V.getOpcode() != ISD::UNDEF)
4532 isOnlyLowElement = false;
4533 if (SplatValue != V)
4534 SplatValue = SDOperand(0,0);
4536 // If this isn't a constant element or an undef, we can't use a constant
4538 if (!isa<ConstantFPSDNode>(V) && !isa<ConstantSDNode>(V) &&
4539 V.getOpcode() != ISD::UNDEF)
4543 if (isOnlyLowElement) {
4544 // If the low element is an undef too, then this whole things is an undef.
4545 if (Node->getOperand(0).getOpcode() == ISD::UNDEF)
4546 return DAG.getNode(ISD::UNDEF, Node->getValueType(0));
4547 // Otherwise, turn this into a scalar_to_vector node.
4548 return DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0),
4549 Node->getOperand(0));
4552 // If all elements are constants, create a load from the constant pool.
4554 MVT::ValueType VT = Node->getValueType(0);
4556 MVT::getTypeForValueType(Node->getOperand(0).getValueType());
4557 std::vector<Constant*> CV;
4558 for (unsigned i = 0, e = NumElems; i != e; ++i) {
4559 if (ConstantFPSDNode *V =
4560 dyn_cast<ConstantFPSDNode>(Node->getOperand(i))) {
4561 CV.push_back(ConstantFP::get(OpNTy, V->getValueAPF()));
4562 } else if (ConstantSDNode *V =
4563 dyn_cast<ConstantSDNode>(Node->getOperand(i))) {
4564 CV.push_back(ConstantInt::get(OpNTy, V->getValue()));
4566 assert(Node->getOperand(i).getOpcode() == ISD::UNDEF);
4567 CV.push_back(UndefValue::get(OpNTy));
4570 Constant *CP = ConstantVector::get(CV);
4571 SDOperand CPIdx = DAG.getConstantPool(CP, TLI.getPointerTy());
4572 return DAG.getLoad(VT, DAG.getEntryNode(), CPIdx, NULL, 0);
4575 if (SplatValue.Val) { // Splat of one value?
4576 // Build the shuffle constant vector: <0, 0, 0, 0>
4577 MVT::ValueType MaskVT =
4578 MVT::getIntVectorWithNumElements(NumElems);
4579 SDOperand Zero = DAG.getConstant(0, MVT::getVectorElementType(MaskVT));
4580 std::vector<SDOperand> ZeroVec(NumElems, Zero);
4581 SDOperand SplatMask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
4582 &ZeroVec[0], ZeroVec.size());
4584 // If the target supports VECTOR_SHUFFLE and this shuffle mask, use it.
4585 if (isShuffleLegal(Node->getValueType(0), SplatMask)) {
4586 // Get the splatted value into the low element of a vector register.
4587 SDOperand LowValVec =
4588 DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0), SplatValue);
4590 // Return shuffle(LowValVec, undef, <0,0,0,0>)
4591 return DAG.getNode(ISD::VECTOR_SHUFFLE, Node->getValueType(0), LowValVec,
4592 DAG.getNode(ISD::UNDEF, Node->getValueType(0)),
4597 // If there are only two unique elements, we may be able to turn this into a
4599 if (Values.size() == 2) {
4600 // Build the shuffle constant vector: e.g. <0, 4, 0, 4>
4601 MVT::ValueType MaskVT =
4602 MVT::getIntVectorWithNumElements(NumElems);
4603 std::vector<SDOperand> MaskVec(NumElems);
4605 for (std::map<SDOperand,std::vector<unsigned> >::iterator I=Values.begin(),
4606 E = Values.end(); I != E; ++I) {
4607 for (std::vector<unsigned>::iterator II = I->second.begin(),
4608 EE = I->second.end(); II != EE; ++II)
4609 MaskVec[*II] = DAG.getConstant(i, MVT::getVectorElementType(MaskVT));
4612 SDOperand ShuffleMask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
4613 &MaskVec[0], MaskVec.size());
4615 // If the target supports VECTOR_SHUFFLE and this shuffle mask, use it.
4616 if (TLI.isOperationLegal(ISD::SCALAR_TO_VECTOR, Node->getValueType(0)) &&
4617 isShuffleLegal(Node->getValueType(0), ShuffleMask)) {
4618 SmallVector<SDOperand, 8> Ops;
4619 for(std::map<SDOperand,std::vector<unsigned> >::iterator I=Values.begin(),
4620 E = Values.end(); I != E; ++I) {
4621 SDOperand Op = DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0),
4625 Ops.push_back(ShuffleMask);
4627 // Return shuffle(LoValVec, HiValVec, <0,1,0,1>)
4628 return DAG.getNode(ISD::VECTOR_SHUFFLE, Node->getValueType(0),
4629 &Ops[0], Ops.size());
4633 // Otherwise, we can't handle this case efficiently. Allocate a sufficiently
4634 // aligned object on the stack, store each element into it, then load
4635 // the result as a vector.
4636 MVT::ValueType VT = Node->getValueType(0);
4637 // Create the stack frame object.
4638 SDOperand FIPtr = DAG.CreateStackTemporary(VT);
4640 // Emit a store of each element to the stack slot.
4641 SmallVector<SDOperand, 8> Stores;
4642 unsigned TypeByteSize =
4643 MVT::getSizeInBits(Node->getOperand(0).getValueType())/8;
4644 // Store (in the right endianness) the elements to memory.
4645 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
4646 // Ignore undef elements.
4647 if (Node->getOperand(i).getOpcode() == ISD::UNDEF) continue;
4649 unsigned Offset = TypeByteSize*i;
4651 SDOperand Idx = DAG.getConstant(Offset, FIPtr.getValueType());
4652 Idx = DAG.getNode(ISD::ADD, FIPtr.getValueType(), FIPtr, Idx);
4654 Stores.push_back(DAG.getStore(DAG.getEntryNode(), Node->getOperand(i), Idx,
4658 SDOperand StoreChain;
4659 if (!Stores.empty()) // Not all undef elements?
4660 StoreChain = DAG.getNode(ISD::TokenFactor, MVT::Other,
4661 &Stores[0], Stores.size());
4663 StoreChain = DAG.getEntryNode();
4665 // Result is a load from the stack slot.
4666 return DAG.getLoad(VT, StoreChain, FIPtr, NULL, 0);
4669 void SelectionDAGLegalize::ExpandShiftParts(unsigned NodeOp,
4670 SDOperand Op, SDOperand Amt,
4671 SDOperand &Lo, SDOperand &Hi) {
4672 // Expand the subcomponents.
4673 SDOperand LHSL, LHSH;
4674 ExpandOp(Op, LHSL, LHSH);
4676 SDOperand Ops[] = { LHSL, LHSH, Amt };
4677 MVT::ValueType VT = LHSL.getValueType();
4678 Lo = DAG.getNode(NodeOp, DAG.getNodeValueTypes(VT, VT), 2, Ops, 3);
4679 Hi = Lo.getValue(1);
4683 /// ExpandShift - Try to find a clever way to expand this shift operation out to
4684 /// smaller elements. If we can't find a way that is more efficient than a
4685 /// libcall on this target, return false. Otherwise, return true with the
4686 /// low-parts expanded into Lo and Hi.
4687 bool SelectionDAGLegalize::ExpandShift(unsigned Opc, SDOperand Op,SDOperand Amt,
4688 SDOperand &Lo, SDOperand &Hi) {
4689 assert((Opc == ISD::SHL || Opc == ISD::SRA || Opc == ISD::SRL) &&
4690 "This is not a shift!");
4692 MVT::ValueType NVT = TLI.getTypeToTransformTo(Op.getValueType());
4693 SDOperand ShAmt = LegalizeOp(Amt);
4694 MVT::ValueType ShTy = ShAmt.getValueType();
4695 unsigned VTBits = MVT::getSizeInBits(Op.getValueType());
4696 unsigned NVTBits = MVT::getSizeInBits(NVT);
4698 // Handle the case when Amt is an immediate.
4699 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Amt.Val)) {
4700 unsigned Cst = CN->getValue();
4701 // Expand the incoming operand to be shifted, so that we have its parts
4703 ExpandOp(Op, InL, InH);
4707 Lo = DAG.getConstant(0, NVT);
4708 Hi = DAG.getConstant(0, NVT);
4709 } else if (Cst > NVTBits) {
4710 Lo = DAG.getConstant(0, NVT);
4711 Hi = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Cst-NVTBits,ShTy));
4712 } else if (Cst == NVTBits) {
4713 Lo = DAG.getConstant(0, NVT);
4716 Lo = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Cst, ShTy));
4717 Hi = DAG.getNode(ISD::OR, NVT,
4718 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(Cst, ShTy)),
4719 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(NVTBits-Cst, ShTy)));
4724 Lo = DAG.getConstant(0, NVT);
4725 Hi = DAG.getConstant(0, NVT);
4726 } else if (Cst > NVTBits) {
4727 Lo = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Cst-NVTBits,ShTy));
4728 Hi = DAG.getConstant(0, NVT);
4729 } else if (Cst == NVTBits) {
4731 Hi = DAG.getConstant(0, NVT);
4733 Lo = DAG.getNode(ISD::OR, NVT,
4734 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(Cst, ShTy)),
4735 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(NVTBits-Cst, ShTy)));
4736 Hi = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Cst, ShTy));
4741 Hi = Lo = DAG.getNode(ISD::SRA, NVT, InH,
4742 DAG.getConstant(NVTBits-1, ShTy));
4743 } else if (Cst > NVTBits) {
4744 Lo = DAG.getNode(ISD::SRA, NVT, InH,
4745 DAG.getConstant(Cst-NVTBits, ShTy));
4746 Hi = DAG.getNode(ISD::SRA, NVT, InH,
4747 DAG.getConstant(NVTBits-1, ShTy));
4748 } else if (Cst == NVTBits) {
4750 Hi = DAG.getNode(ISD::SRA, NVT, InH,
4751 DAG.getConstant(NVTBits-1, ShTy));
4753 Lo = DAG.getNode(ISD::OR, NVT,
4754 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(Cst, ShTy)),
4755 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(NVTBits-Cst, ShTy)));
4756 Hi = DAG.getNode(ISD::SRA, NVT, InH, DAG.getConstant(Cst, ShTy));
4762 // Okay, the shift amount isn't constant. However, if we can tell that it is
4763 // >= 32 or < 32, we can still simplify it, without knowing the actual value.
4764 uint64_t Mask = NVTBits, KnownZero, KnownOne;
4765 DAG.ComputeMaskedBits(Amt, Mask, KnownZero, KnownOne);
4767 // If we know that the high bit of the shift amount is one, then we can do
4768 // this as a couple of simple shifts.
4769 if (KnownOne & Mask) {
4770 // Mask out the high bit, which we know is set.
4771 Amt = DAG.getNode(ISD::AND, Amt.getValueType(), Amt,
4772 DAG.getConstant(NVTBits-1, Amt.getValueType()));
4774 // Expand the incoming operand to be shifted, so that we have its parts
4776 ExpandOp(Op, InL, InH);
4779 Lo = DAG.getConstant(0, NVT); // Low part is zero.
4780 Hi = DAG.getNode(ISD::SHL, NVT, InL, Amt); // High part from Lo part.
4783 Hi = DAG.getConstant(0, NVT); // Hi part is zero.
4784 Lo = DAG.getNode(ISD::SRL, NVT, InH, Amt); // Lo part from Hi part.
4787 Hi = DAG.getNode(ISD::SRA, NVT, InH, // Sign extend high part.
4788 DAG.getConstant(NVTBits-1, Amt.getValueType()));
4789 Lo = DAG.getNode(ISD::SRA, NVT, InH, Amt); // Lo part from Hi part.
4794 // If we know that the high bit of the shift amount is zero, then we can do
4795 // this as a couple of simple shifts.
4796 if (KnownZero & Mask) {
4798 SDOperand Amt2 = DAG.getNode(ISD::SUB, Amt.getValueType(),
4799 DAG.getConstant(NVTBits, Amt.getValueType()),
4802 // Expand the incoming operand to be shifted, so that we have its parts
4804 ExpandOp(Op, InL, InH);
4807 Lo = DAG.getNode(ISD::SHL, NVT, InL, Amt);
4808 Hi = DAG.getNode(ISD::OR, NVT,
4809 DAG.getNode(ISD::SHL, NVT, InH, Amt),
4810 DAG.getNode(ISD::SRL, NVT, InL, Amt2));
4813 Hi = DAG.getNode(ISD::SRL, NVT, InH, Amt);
4814 Lo = DAG.getNode(ISD::OR, NVT,
4815 DAG.getNode(ISD::SRL, NVT, InL, Amt),
4816 DAG.getNode(ISD::SHL, NVT, InH, Amt2));
4819 Hi = DAG.getNode(ISD::SRA, NVT, InH, Amt);
4820 Lo = DAG.getNode(ISD::OR, NVT,
4821 DAG.getNode(ISD::SRL, NVT, InL, Amt),
4822 DAG.getNode(ISD::SHL, NVT, InH, Amt2));
4831 // ExpandLibCall - Expand a node into a call to a libcall. If the result value
4832 // does not fit into a register, return the lo part and set the hi part to the
4833 // by-reg argument. If it does fit into a single register, return the result
4834 // and leave the Hi part unset.
4835 SDOperand SelectionDAGLegalize::ExpandLibCall(const char *Name, SDNode *Node,
4836 bool isSigned, SDOperand &Hi) {
4837 assert(!IsLegalizingCall && "Cannot overlap legalization of calls!");
4838 // The input chain to this libcall is the entry node of the function.
4839 // Legalizing the call will automatically add the previous call to the
4841 SDOperand InChain = DAG.getEntryNode();
4843 TargetLowering::ArgListTy Args;
4844 TargetLowering::ArgListEntry Entry;
4845 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
4846 MVT::ValueType ArgVT = Node->getOperand(i).getValueType();
4847 const Type *ArgTy = MVT::getTypeForValueType(ArgVT);
4848 Entry.Node = Node->getOperand(i); Entry.Ty = ArgTy;
4849 Entry.isSExt = isSigned;
4850 Args.push_back(Entry);
4852 SDOperand Callee = DAG.getExternalSymbol(Name, TLI.getPointerTy());
4854 // Splice the libcall in wherever FindInputOutputChains tells us to.
4855 const Type *RetTy = MVT::getTypeForValueType(Node->getValueType(0));
4856 std::pair<SDOperand,SDOperand> CallInfo =
4857 TLI.LowerCallTo(InChain, RetTy, isSigned, false, CallingConv::C, false,
4860 // Legalize the call sequence, starting with the chain. This will advance
4861 // the LastCALLSEQ_END to the legalized version of the CALLSEQ_END node that
4862 // was added by LowerCallTo (guaranteeing proper serialization of calls).
4863 LegalizeOp(CallInfo.second);
4865 switch (getTypeAction(CallInfo.first.getValueType())) {
4866 default: assert(0 && "Unknown thing");
4868 Result = CallInfo.first;
4871 ExpandOp(CallInfo.first, Result, Hi);
4878 /// ExpandIntToFP - Expand a [US]INT_TO_FP operation.
4880 SDOperand SelectionDAGLegalize::
4881 ExpandIntToFP(bool isSigned, MVT::ValueType DestTy, SDOperand Source) {
4882 assert(getTypeAction(Source.getValueType()) == Expand &&
4883 "This is not an expansion!");
4884 assert(Source.getValueType() == MVT::i64 && "Only handle expand from i64!");
4887 assert(Source.getValueType() == MVT::i64 &&
4888 "This only works for 64-bit -> FP");
4889 // The 64-bit value loaded will be incorrectly if the 'sign bit' of the
4890 // incoming integer is set. To handle this, we dynamically test to see if
4891 // it is set, and, if so, add a fudge factor.
4893 ExpandOp(Source, Lo, Hi);
4895 // If this is unsigned, and not supported, first perform the conversion to
4896 // signed, then adjust the result if the sign bit is set.
4897 SDOperand SignedConv = ExpandIntToFP(true, DestTy,
4898 DAG.getNode(ISD::BUILD_PAIR, Source.getValueType(), Lo, Hi));
4900 SDOperand SignSet = DAG.getSetCC(TLI.getSetCCResultTy(), Hi,
4901 DAG.getConstant(0, Hi.getValueType()),
4903 SDOperand Zero = getIntPtrConstant(0), Four = getIntPtrConstant(4);
4904 SDOperand CstOffset = DAG.getNode(ISD::SELECT, Zero.getValueType(),
4905 SignSet, Four, Zero);
4906 uint64_t FF = 0x5f800000ULL;
4907 if (TLI.isLittleEndian()) FF <<= 32;
4908 static Constant *FudgeFactor = ConstantInt::get(Type::Int64Ty, FF);
4910 SDOperand CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy());
4911 CPIdx = DAG.getNode(ISD::ADD, TLI.getPointerTy(), CPIdx, CstOffset);
4912 SDOperand FudgeInReg;
4913 if (DestTy == MVT::f32)
4914 FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx, NULL, 0);
4915 else if (MVT::getSizeInBits(DestTy) > MVT::getSizeInBits(MVT::f32))
4916 // FIXME: Avoid the extend by construction the right constantpool?
4917 FudgeInReg = DAG.getExtLoad(ISD::EXTLOAD, DestTy, DAG.getEntryNode(),
4918 CPIdx, NULL, 0, MVT::f32);
4920 assert(0 && "Unexpected conversion");
4922 MVT::ValueType SCVT = SignedConv.getValueType();
4923 if (SCVT != DestTy) {
4924 // Destination type needs to be expanded as well. The FADD now we are
4925 // constructing will be expanded into a libcall.
4926 if (MVT::getSizeInBits(SCVT) != MVT::getSizeInBits(DestTy)) {
4927 assert(SCVT == MVT::i32 && DestTy == MVT::f64);
4928 SignedConv = DAG.getNode(ISD::BUILD_PAIR, MVT::i64,
4929 SignedConv, SignedConv.getValue(1));
4931 SignedConv = DAG.getNode(ISD::BIT_CONVERT, DestTy, SignedConv);
4933 return DAG.getNode(ISD::FADD, DestTy, SignedConv, FudgeInReg);
4936 // Check to see if the target has a custom way to lower this. If so, use it.
4937 switch (TLI.getOperationAction(ISD::SINT_TO_FP, Source.getValueType())) {
4938 default: assert(0 && "This action not implemented for this operation!");
4939 case TargetLowering::Legal:
4940 case TargetLowering::Expand:
4941 break; // This case is handled below.
4942 case TargetLowering::Custom: {
4943 SDOperand NV = TLI.LowerOperation(DAG.getNode(ISD::SINT_TO_FP, DestTy,
4946 return LegalizeOp(NV);
4947 break; // The target decided this was legal after all
4951 // Expand the source, then glue it back together for the call. We must expand
4952 // the source in case it is shared (this pass of legalize must traverse it).
4953 SDOperand SrcLo, SrcHi;
4954 ExpandOp(Source, SrcLo, SrcHi);
4955 Source = DAG.getNode(ISD::BUILD_PAIR, Source.getValueType(), SrcLo, SrcHi);
4958 if (DestTy == MVT::f32)
4959 LC = RTLIB::SINTTOFP_I64_F32;
4961 assert(DestTy == MVT::f64 && "Unknown fp value type!");
4962 LC = RTLIB::SINTTOFP_I64_F64;
4965 assert(TLI.getLibcallName(LC) && "Don't know how to expand this SINT_TO_FP!");
4966 Source = DAG.getNode(ISD::SINT_TO_FP, DestTy, Source);
4967 SDOperand UnusedHiPart;
4968 return ExpandLibCall(TLI.getLibcallName(LC), Source.Val, isSigned,
4972 /// ExpandLegalINT_TO_FP - This function is responsible for legalizing a
4973 /// INT_TO_FP operation of the specified operand when the target requests that
4974 /// we expand it. At this point, we know that the result and operand types are
4975 /// legal for the target.
4976 SDOperand SelectionDAGLegalize::ExpandLegalINT_TO_FP(bool isSigned,
4978 MVT::ValueType DestVT) {
4979 if (Op0.getValueType() == MVT::i32) {
4980 // simple 32-bit [signed|unsigned] integer to float/double expansion
4982 // get the stack frame index of a 8 byte buffer, pessimistically aligned
4983 MachineFunction &MF = DAG.getMachineFunction();
4984 const Type *F64Type = MVT::getTypeForValueType(MVT::f64);
4985 unsigned StackAlign =
4986 (unsigned)TLI.getTargetData()->getPrefTypeAlignment(F64Type);
4987 int SSFI = MF.getFrameInfo()->CreateStackObject(8, StackAlign);
4988 // get address of 8 byte buffer
4989 SDOperand StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy());
4990 // word offset constant for Hi/Lo address computation
4991 SDOperand WordOff = DAG.getConstant(sizeof(int), TLI.getPointerTy());
4992 // set up Hi and Lo (into buffer) address based on endian
4993 SDOperand Hi = StackSlot;
4994 SDOperand Lo = DAG.getNode(ISD::ADD, TLI.getPointerTy(), StackSlot,WordOff);
4995 if (TLI.isLittleEndian())
4998 // if signed map to unsigned space
4999 SDOperand Op0Mapped;
5001 // constant used to invert sign bit (signed to unsigned mapping)
5002 SDOperand SignBit = DAG.getConstant(0x80000000u, MVT::i32);
5003 Op0Mapped = DAG.getNode(ISD::XOR, MVT::i32, Op0, SignBit);
5007 // store the lo of the constructed double - based on integer input
5008 SDOperand Store1 = DAG.getStore(DAG.getEntryNode(),
5009 Op0Mapped, Lo, NULL, 0);
5010 // initial hi portion of constructed double
5011 SDOperand InitialHi = DAG.getConstant(0x43300000u, MVT::i32);
5012 // store the hi of the constructed double - biased exponent
5013 SDOperand Store2=DAG.getStore(Store1, InitialHi, Hi, NULL, 0);
5014 // load the constructed double
5015 SDOperand Load = DAG.getLoad(MVT::f64, Store2, StackSlot, NULL, 0);
5016 // FP constant to bias correct the final result
5017 SDOperand Bias = DAG.getConstantFP(isSigned ?
5018 BitsToDouble(0x4330000080000000ULL)
5019 : BitsToDouble(0x4330000000000000ULL),
5021 // subtract the bias
5022 SDOperand Sub = DAG.getNode(ISD::FSUB, MVT::f64, Load, Bias);
5025 // handle final rounding
5026 if (DestVT == MVT::f64) {
5029 } else if (MVT::getSizeInBits(DestVT) < MVT::getSizeInBits(MVT::f64)) {
5030 Result = DAG.getNode(ISD::FP_ROUND, DestVT, Sub);
5031 } else if (MVT::getSizeInBits(DestVT) > MVT::getSizeInBits(MVT::f64)) {
5032 Result = DAG.getNode(ISD::FP_EXTEND, DestVT, Sub);
5036 assert(!isSigned && "Legalize cannot Expand SINT_TO_FP for i64 yet");
5037 SDOperand Tmp1 = DAG.getNode(ISD::SINT_TO_FP, DestVT, Op0);
5039 SDOperand SignSet = DAG.getSetCC(TLI.getSetCCResultTy(), Op0,
5040 DAG.getConstant(0, Op0.getValueType()),
5042 SDOperand Zero = getIntPtrConstant(0), Four = getIntPtrConstant(4);
5043 SDOperand CstOffset = DAG.getNode(ISD::SELECT, Zero.getValueType(),
5044 SignSet, Four, Zero);
5046 // If the sign bit of the integer is set, the large number will be treated
5047 // as a negative number. To counteract this, the dynamic code adds an
5048 // offset depending on the data type.
5050 switch (Op0.getValueType()) {
5051 default: assert(0 && "Unsupported integer type!");
5052 case MVT::i8 : FF = 0x43800000ULL; break; // 2^8 (as a float)
5053 case MVT::i16: FF = 0x47800000ULL; break; // 2^16 (as a float)
5054 case MVT::i32: FF = 0x4F800000ULL; break; // 2^32 (as a float)
5055 case MVT::i64: FF = 0x5F800000ULL; break; // 2^64 (as a float)
5057 if (TLI.isLittleEndian()) FF <<= 32;
5058 static Constant *FudgeFactor = ConstantInt::get(Type::Int64Ty, FF);
5060 SDOperand CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy());
5061 CPIdx = DAG.getNode(ISD::ADD, TLI.getPointerTy(), CPIdx, CstOffset);
5062 SDOperand FudgeInReg;
5063 if (DestVT == MVT::f32)
5064 FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx, NULL, 0);
5066 FudgeInReg = LegalizeOp(DAG.getExtLoad(ISD::EXTLOAD, DestVT,
5067 DAG.getEntryNode(), CPIdx,
5068 NULL, 0, MVT::f32));
5071 return DAG.getNode(ISD::FADD, DestVT, Tmp1, FudgeInReg);
5074 /// PromoteLegalINT_TO_FP - This function is responsible for legalizing a
5075 /// *INT_TO_FP operation of the specified operand when the target requests that
5076 /// we promote it. At this point, we know that the result and operand types are
5077 /// legal for the target, and that there is a legal UINT_TO_FP or SINT_TO_FP
5078 /// operation that takes a larger input.
5079 SDOperand SelectionDAGLegalize::PromoteLegalINT_TO_FP(SDOperand LegalOp,
5080 MVT::ValueType DestVT,
5082 // First step, figure out the appropriate *INT_TO_FP operation to use.
5083 MVT::ValueType NewInTy = LegalOp.getValueType();
5085 unsigned OpToUse = 0;
5087 // Scan for the appropriate larger type to use.
5089 NewInTy = (MVT::ValueType)(NewInTy+1);
5090 assert(MVT::isInteger(NewInTy) && "Ran out of possibilities!");
5092 // If the target supports SINT_TO_FP of this type, use it.
5093 switch (TLI.getOperationAction(ISD::SINT_TO_FP, NewInTy)) {
5095 case TargetLowering::Legal:
5096 if (!TLI.isTypeLegal(NewInTy))
5097 break; // Can't use this datatype.
5099 case TargetLowering::Custom:
5100 OpToUse = ISD::SINT_TO_FP;
5104 if (isSigned) continue;
5106 // If the target supports UINT_TO_FP of this type, use it.
5107 switch (TLI.getOperationAction(ISD::UINT_TO_FP, NewInTy)) {
5109 case TargetLowering::Legal:
5110 if (!TLI.isTypeLegal(NewInTy))
5111 break; // Can't use this datatype.
5113 case TargetLowering::Custom:
5114 OpToUse = ISD::UINT_TO_FP;
5119 // Otherwise, try a larger type.
5122 // Okay, we found the operation and type to use. Zero extend our input to the
5123 // desired type then run the operation on it.
5124 return DAG.getNode(OpToUse, DestVT,
5125 DAG.getNode(isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND,
5129 /// PromoteLegalFP_TO_INT - This function is responsible for legalizing a
5130 /// FP_TO_*INT operation of the specified operand when the target requests that
5131 /// we promote it. At this point, we know that the result and operand types are
5132 /// legal for the target, and that there is a legal FP_TO_UINT or FP_TO_SINT
5133 /// operation that returns a larger result.
5134 SDOperand SelectionDAGLegalize::PromoteLegalFP_TO_INT(SDOperand LegalOp,
5135 MVT::ValueType DestVT,
5137 // First step, figure out the appropriate FP_TO*INT operation to use.
5138 MVT::ValueType NewOutTy = DestVT;
5140 unsigned OpToUse = 0;
5142 // Scan for the appropriate larger type to use.
5144 NewOutTy = (MVT::ValueType)(NewOutTy+1);
5145 assert(MVT::isInteger(NewOutTy) && "Ran out of possibilities!");
5147 // If the target supports FP_TO_SINT returning this type, use it.
5148 switch (TLI.getOperationAction(ISD::FP_TO_SINT, NewOutTy)) {
5150 case TargetLowering::Legal:
5151 if (!TLI.isTypeLegal(NewOutTy))
5152 break; // Can't use this datatype.
5154 case TargetLowering::Custom:
5155 OpToUse = ISD::FP_TO_SINT;
5160 // If the target supports FP_TO_UINT of this type, use it.
5161 switch (TLI.getOperationAction(ISD::FP_TO_UINT, NewOutTy)) {
5163 case TargetLowering::Legal:
5164 if (!TLI.isTypeLegal(NewOutTy))
5165 break; // Can't use this datatype.
5167 case TargetLowering::Custom:
5168 OpToUse = ISD::FP_TO_UINT;
5173 // Otherwise, try a larger type.
5176 // Okay, we found the operation and type to use. Truncate the result of the
5177 // extended FP_TO_*INT operation to the desired size.
5178 return DAG.getNode(ISD::TRUNCATE, DestVT,
5179 DAG.getNode(OpToUse, NewOutTy, LegalOp));
5182 /// ExpandBSWAP - Open code the operations for BSWAP of the specified operation.
5184 SDOperand SelectionDAGLegalize::ExpandBSWAP(SDOperand Op) {
5185 MVT::ValueType VT = Op.getValueType();
5186 MVT::ValueType SHVT = TLI.getShiftAmountTy();
5187 SDOperand Tmp1, Tmp2, Tmp3, Tmp4, Tmp5, Tmp6, Tmp7, Tmp8;
5189 default: assert(0 && "Unhandled Expand type in BSWAP!"); abort();
5191 Tmp2 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT));
5192 Tmp1 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(8, SHVT));
5193 return DAG.getNode(ISD::OR, VT, Tmp1, Tmp2);
5195 Tmp4 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(24, SHVT));
5196 Tmp3 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT));
5197 Tmp2 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(8, SHVT));
5198 Tmp1 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(24, SHVT));
5199 Tmp3 = DAG.getNode(ISD::AND, VT, Tmp3, DAG.getConstant(0xFF0000, VT));
5200 Tmp2 = DAG.getNode(ISD::AND, VT, Tmp2, DAG.getConstant(0xFF00, VT));
5201 Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp3);
5202 Tmp2 = DAG.getNode(ISD::OR, VT, Tmp2, Tmp1);
5203 return DAG.getNode(ISD::OR, VT, Tmp4, Tmp2);
5205 Tmp8 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(56, SHVT));
5206 Tmp7 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(40, SHVT));
5207 Tmp6 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(24, SHVT));
5208 Tmp5 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT));
5209 Tmp4 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(8, SHVT));
5210 Tmp3 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(24, SHVT));
5211 Tmp2 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(40, SHVT));
5212 Tmp1 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(56, SHVT));
5213 Tmp7 = DAG.getNode(ISD::AND, VT, Tmp7, DAG.getConstant(255ULL<<48, VT));
5214 Tmp6 = DAG.getNode(ISD::AND, VT, Tmp6, DAG.getConstant(255ULL<<40, VT));
5215 Tmp5 = DAG.getNode(ISD::AND, VT, Tmp5, DAG.getConstant(255ULL<<32, VT));
5216 Tmp4 = DAG.getNode(ISD::AND, VT, Tmp4, DAG.getConstant(255ULL<<24, VT));
5217 Tmp3 = DAG.getNode(ISD::AND, VT, Tmp3, DAG.getConstant(255ULL<<16, VT));
5218 Tmp2 = DAG.getNode(ISD::AND, VT, Tmp2, DAG.getConstant(255ULL<<8 , VT));
5219 Tmp8 = DAG.getNode(ISD::OR, VT, Tmp8, Tmp7);
5220 Tmp6 = DAG.getNode(ISD::OR, VT, Tmp6, Tmp5);
5221 Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp3);
5222 Tmp2 = DAG.getNode(ISD::OR, VT, Tmp2, Tmp1);
5223 Tmp8 = DAG.getNode(ISD::OR, VT, Tmp8, Tmp6);
5224 Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp2);
5225 return DAG.getNode(ISD::OR, VT, Tmp8, Tmp4);
5229 /// ExpandBitCount - Expand the specified bitcount instruction into operations.
5231 SDOperand SelectionDAGLegalize::ExpandBitCount(unsigned Opc, SDOperand Op) {
5233 default: assert(0 && "Cannot expand this yet!");
5235 static const uint64_t mask[6] = {
5236 0x5555555555555555ULL, 0x3333333333333333ULL,
5237 0x0F0F0F0F0F0F0F0FULL, 0x00FF00FF00FF00FFULL,
5238 0x0000FFFF0000FFFFULL, 0x00000000FFFFFFFFULL
5240 MVT::ValueType VT = Op.getValueType();
5241 MVT::ValueType ShVT = TLI.getShiftAmountTy();
5242 unsigned len = MVT::getSizeInBits(VT);
5243 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) {
5244 //x = (x & mask[i][len/8]) + (x >> (1 << i) & mask[i][len/8])
5245 SDOperand Tmp2 = DAG.getConstant(mask[i], VT);
5246 SDOperand Tmp3 = DAG.getConstant(1ULL << i, ShVT);
5247 Op = DAG.getNode(ISD::ADD, VT, DAG.getNode(ISD::AND, VT, Op, Tmp2),
5248 DAG.getNode(ISD::AND, VT,
5249 DAG.getNode(ISD::SRL, VT, Op, Tmp3),Tmp2));
5254 // for now, we do this:
5255 // x = x | (x >> 1);
5256 // x = x | (x >> 2);
5258 // x = x | (x >>16);
5259 // x = x | (x >>32); // for 64-bit input
5260 // return popcount(~x);
5262 // but see also: http://www.hackersdelight.org/HDcode/nlz.cc
5263 MVT::ValueType VT = Op.getValueType();
5264 MVT::ValueType ShVT = TLI.getShiftAmountTy();
5265 unsigned len = MVT::getSizeInBits(VT);
5266 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) {
5267 SDOperand Tmp3 = DAG.getConstant(1ULL << i, ShVT);
5268 Op = DAG.getNode(ISD::OR, VT, Op, DAG.getNode(ISD::SRL, VT, Op, Tmp3));
5270 Op = DAG.getNode(ISD::XOR, VT, Op, DAG.getConstant(~0ULL, VT));
5271 return DAG.getNode(ISD::CTPOP, VT, Op);
5274 // for now, we use: { return popcount(~x & (x - 1)); }
5275 // unless the target has ctlz but not ctpop, in which case we use:
5276 // { return 32 - nlz(~x & (x-1)); }
5277 // see also http://www.hackersdelight.org/HDcode/ntz.cc
5278 MVT::ValueType VT = Op.getValueType();
5279 SDOperand Tmp2 = DAG.getConstant(~0ULL, VT);
5280 SDOperand Tmp3 = DAG.getNode(ISD::AND, VT,
5281 DAG.getNode(ISD::XOR, VT, Op, Tmp2),
5282 DAG.getNode(ISD::SUB, VT, Op, DAG.getConstant(1, VT)));
5283 // If ISD::CTLZ is legal and CTPOP isn't, then do that instead.
5284 if (!TLI.isOperationLegal(ISD::CTPOP, VT) &&
5285 TLI.isOperationLegal(ISD::CTLZ, VT))
5286 return DAG.getNode(ISD::SUB, VT,
5287 DAG.getConstant(MVT::getSizeInBits(VT), VT),
5288 DAG.getNode(ISD::CTLZ, VT, Tmp3));
5289 return DAG.getNode(ISD::CTPOP, VT, Tmp3);
5294 /// ExpandOp - Expand the specified SDOperand into its two component pieces
5295 /// Lo&Hi. Note that the Op MUST be an expanded type. As a result of this, the
5296 /// LegalizeNodes map is filled in for any results that are not expanded, the
5297 /// ExpandedNodes map is filled in for any results that are expanded, and the
5298 /// Lo/Hi values are returned.
5299 void SelectionDAGLegalize::ExpandOp(SDOperand Op, SDOperand &Lo, SDOperand &Hi){
5300 MVT::ValueType VT = Op.getValueType();
5301 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT);
5302 SDNode *Node = Op.Val;
5303 assert(getTypeAction(VT) == Expand && "Not an expanded type!");
5304 assert(((MVT::isInteger(NVT) && NVT < VT) || MVT::isFloatingPoint(VT) ||
5305 MVT::isVector(VT)) &&
5306 "Cannot expand to FP value or to larger int value!");
5308 // See if we already expanded it.
5309 DenseMap<SDOperand, std::pair<SDOperand, SDOperand> >::iterator I
5310 = ExpandedNodes.find(Op);
5311 if (I != ExpandedNodes.end()) {
5312 Lo = I->second.first;
5313 Hi = I->second.second;
5317 switch (Node->getOpcode()) {
5318 case ISD::CopyFromReg:
5319 assert(0 && "CopyFromReg must be legal!");
5320 case ISD::FP_ROUND_INREG:
5321 if (VT == MVT::ppcf128 &&
5322 TLI.getOperationAction(ISD::FP_ROUND_INREG, VT) ==
5323 TargetLowering::Custom) {
5324 SDOperand SrcLo, SrcHi, Src;
5325 ExpandOp(Op.getOperand(0), SrcLo, SrcHi);
5326 Src = DAG.getNode(ISD::BUILD_PAIR, VT, SrcLo, SrcHi);
5327 SDOperand Result = TLI.LowerOperation(
5328 DAG.getNode(ISD::FP_ROUND_INREG, VT, Src, Op.getOperand(1)), DAG);
5329 assert(Result.Val->getOpcode() == ISD::BUILD_PAIR);
5330 Lo = Result.Val->getOperand(0);
5331 Hi = Result.Val->getOperand(1);
5337 cerr << "NODE: "; Node->dump(&DAG); cerr << "\n";
5339 assert(0 && "Do not know how to expand this operator!");
5341 case ISD::EXTRACT_VECTOR_ELT:
5342 assert(VT==MVT::i64 && "Do not know how to expand this operator!");
5343 // ExpandEXTRACT_VECTOR_ELT tolerates invalid result types.
5344 Lo = ExpandEXTRACT_VECTOR_ELT(Op);
5345 return ExpandOp(Lo, Lo, Hi);
5347 NVT = TLI.getTypeToExpandTo(VT);
5348 Lo = DAG.getNode(ISD::UNDEF, NVT);
5349 Hi = DAG.getNode(ISD::UNDEF, NVT);
5351 case ISD::Constant: {
5352 uint64_t Cst = cast<ConstantSDNode>(Node)->getValue();
5353 Lo = DAG.getConstant(Cst, NVT);
5354 Hi = DAG.getConstant(Cst >> MVT::getSizeInBits(NVT), NVT);
5357 case ISD::ConstantFP: {
5358 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node);
5359 if (CFP->getValueType(0) == MVT::ppcf128) {
5360 APInt api = CFP->getValueAPF().convertToAPInt();
5361 Lo = DAG.getConstantFP(APFloat(APInt(64, 1, &api.getRawData()[1])),
5363 Hi = DAG.getConstantFP(APFloat(APInt(64, 1, &api.getRawData()[0])),
5367 Lo = ExpandConstantFP(CFP, false, DAG, TLI);
5368 if (getTypeAction(Lo.getValueType()) == Expand)
5369 ExpandOp(Lo, Lo, Hi);
5372 case ISD::BUILD_PAIR:
5373 // Return the operands.
5374 Lo = Node->getOperand(0);
5375 Hi = Node->getOperand(1);
5378 case ISD::SIGN_EXTEND_INREG:
5379 ExpandOp(Node->getOperand(0), Lo, Hi);
5380 // sext_inreg the low part if needed.
5381 Lo = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Lo, Node->getOperand(1));
5383 // The high part gets the sign extension from the lo-part. This handles
5384 // things like sextinreg V:i64 from i8.
5385 Hi = DAG.getNode(ISD::SRA, NVT, Lo,
5386 DAG.getConstant(MVT::getSizeInBits(NVT)-1,
5387 TLI.getShiftAmountTy()));
5391 ExpandOp(Node->getOperand(0), Lo, Hi);
5392 SDOperand TempLo = DAG.getNode(ISD::BSWAP, NVT, Hi);
5393 Hi = DAG.getNode(ISD::BSWAP, NVT, Lo);
5399 ExpandOp(Node->getOperand(0), Lo, Hi);
5400 Lo = DAG.getNode(ISD::ADD, NVT, // ctpop(HL) -> ctpop(H)+ctpop(L)
5401 DAG.getNode(ISD::CTPOP, NVT, Lo),
5402 DAG.getNode(ISD::CTPOP, NVT, Hi));
5403 Hi = DAG.getConstant(0, NVT);
5407 // ctlz (HL) -> ctlz(H) != 32 ? ctlz(H) : (ctlz(L)+32)
5408 ExpandOp(Node->getOperand(0), Lo, Hi);
5409 SDOperand BitsC = DAG.getConstant(MVT::getSizeInBits(NVT), NVT);
5410 SDOperand HLZ = DAG.getNode(ISD::CTLZ, NVT, Hi);
5411 SDOperand TopNotZero = DAG.getSetCC(TLI.getSetCCResultTy(), HLZ, BitsC,
5413 SDOperand LowPart = DAG.getNode(ISD::CTLZ, NVT, Lo);
5414 LowPart = DAG.getNode(ISD::ADD, NVT, LowPart, BitsC);
5416 Lo = DAG.getNode(ISD::SELECT, NVT, TopNotZero, HLZ, LowPart);
5417 Hi = DAG.getConstant(0, NVT);
5422 // cttz (HL) -> cttz(L) != 32 ? cttz(L) : (cttz(H)+32)
5423 ExpandOp(Node->getOperand(0), Lo, Hi);
5424 SDOperand BitsC = DAG.getConstant(MVT::getSizeInBits(NVT), NVT);
5425 SDOperand LTZ = DAG.getNode(ISD::CTTZ, NVT, Lo);
5426 SDOperand BotNotZero = DAG.getSetCC(TLI.getSetCCResultTy(), LTZ, BitsC,
5428 SDOperand HiPart = DAG.getNode(ISD::CTTZ, NVT, Hi);
5429 HiPart = DAG.getNode(ISD::ADD, NVT, HiPart, BitsC);
5431 Lo = DAG.getNode(ISD::SELECT, NVT, BotNotZero, LTZ, HiPart);
5432 Hi = DAG.getConstant(0, NVT);
5437 SDOperand Ch = Node->getOperand(0); // Legalize the chain.
5438 SDOperand Ptr = Node->getOperand(1); // Legalize the pointer.
5439 Lo = DAG.getVAArg(NVT, Ch, Ptr, Node->getOperand(2));
5440 Hi = DAG.getVAArg(NVT, Lo.getValue(1), Ptr, Node->getOperand(2));
5442 // Remember that we legalized the chain.
5443 Hi = LegalizeOp(Hi);
5444 AddLegalizedOperand(Op.getValue(1), Hi.getValue(1));
5445 if (!TLI.isLittleEndian())
5451 LoadSDNode *LD = cast<LoadSDNode>(Node);
5452 SDOperand Ch = LD->getChain(); // Legalize the chain.
5453 SDOperand Ptr = LD->getBasePtr(); // Legalize the pointer.
5454 ISD::LoadExtType ExtType = LD->getExtensionType();
5455 int SVOffset = LD->getSrcValueOffset();
5456 unsigned Alignment = LD->getAlignment();
5457 bool isVolatile = LD->isVolatile();
5459 if (ExtType == ISD::NON_EXTLOAD) {
5460 Lo = DAG.getLoad(NVT, Ch, Ptr, LD->getSrcValue(), SVOffset,
5461 isVolatile, Alignment);
5462 if (VT == MVT::f32 || VT == MVT::f64) {
5463 // f32->i32 or f64->i64 one to one expansion.
5464 // Remember that we legalized the chain.
5465 AddLegalizedOperand(SDOperand(Node, 1), LegalizeOp(Lo.getValue(1)));
5466 // Recursively expand the new load.
5467 if (getTypeAction(NVT) == Expand)
5468 ExpandOp(Lo, Lo, Hi);
5472 // Increment the pointer to the other half.
5473 unsigned IncrementSize = MVT::getSizeInBits(Lo.getValueType())/8;
5474 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
5475 getIntPtrConstant(IncrementSize));
5476 SVOffset += IncrementSize;
5477 Alignment = MinAlign(Alignment, IncrementSize);
5478 Hi = DAG.getLoad(NVT, Ch, Ptr, LD->getSrcValue(), SVOffset,
5479 isVolatile, Alignment);
5481 // Build a factor node to remember that this load is independent of the
5483 SDOperand TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
5486 // Remember that we legalized the chain.
5487 AddLegalizedOperand(Op.getValue(1), LegalizeOp(TF));
5488 if (!TLI.isLittleEndian())
5491 MVT::ValueType EVT = LD->getLoadedVT();
5493 if ((VT == MVT::f64 && EVT == MVT::f32) ||
5494 (VT == MVT::ppcf128 && (EVT==MVT::f64 || EVT==MVT::f32))) {
5495 // f64 = EXTLOAD f32 should expand to LOAD, FP_EXTEND
5496 SDOperand Load = DAG.getLoad(EVT, Ch, Ptr, LD->getSrcValue(),
5497 SVOffset, isVolatile, Alignment);
5498 // Remember that we legalized the chain.
5499 AddLegalizedOperand(SDOperand(Node, 1), LegalizeOp(Load.getValue(1)));
5500 ExpandOp(DAG.getNode(ISD::FP_EXTEND, VT, Load), Lo, Hi);
5505 Lo = DAG.getLoad(NVT, Ch, Ptr, LD->getSrcValue(),
5506 SVOffset, isVolatile, Alignment);
5508 Lo = DAG.getExtLoad(ExtType, NVT, Ch, Ptr, LD->getSrcValue(),
5509 SVOffset, EVT, isVolatile,
5512 // Remember that we legalized the chain.
5513 AddLegalizedOperand(SDOperand(Node, 1), LegalizeOp(Lo.getValue(1)));
5515 if (ExtType == ISD::SEXTLOAD) {
5516 // The high part is obtained by SRA'ing all but one of the bits of the
5518 unsigned LoSize = MVT::getSizeInBits(Lo.getValueType());
5519 Hi = DAG.getNode(ISD::SRA, NVT, Lo,
5520 DAG.getConstant(LoSize-1, TLI.getShiftAmountTy()));
5521 } else if (ExtType == ISD::ZEXTLOAD) {
5522 // The high part is just a zero.
5523 Hi = DAG.getConstant(0, NVT);
5524 } else /* if (ExtType == ISD::EXTLOAD) */ {
5525 // The high part is undefined.
5526 Hi = DAG.getNode(ISD::UNDEF, NVT);
5533 case ISD::XOR: { // Simple logical operators -> two trivial pieces.
5534 SDOperand LL, LH, RL, RH;
5535 ExpandOp(Node->getOperand(0), LL, LH);
5536 ExpandOp(Node->getOperand(1), RL, RH);
5537 Lo = DAG.getNode(Node->getOpcode(), NVT, LL, RL);
5538 Hi = DAG.getNode(Node->getOpcode(), NVT, LH, RH);
5542 SDOperand LL, LH, RL, RH;
5543 ExpandOp(Node->getOperand(1), LL, LH);
5544 ExpandOp(Node->getOperand(2), RL, RH);
5545 if (getTypeAction(NVT) == Expand)
5546 NVT = TLI.getTypeToExpandTo(NVT);
5547 Lo = DAG.getNode(ISD::SELECT, NVT, Node->getOperand(0), LL, RL);
5549 Hi = DAG.getNode(ISD::SELECT, NVT, Node->getOperand(0), LH, RH);
5552 case ISD::SELECT_CC: {
5553 SDOperand TL, TH, FL, FH;
5554 ExpandOp(Node->getOperand(2), TL, TH);
5555 ExpandOp(Node->getOperand(3), FL, FH);
5556 if (getTypeAction(NVT) == Expand)
5557 NVT = TLI.getTypeToExpandTo(NVT);
5558 Lo = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0),
5559 Node->getOperand(1), TL, FL, Node->getOperand(4));
5561 Hi = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0),
5562 Node->getOperand(1), TH, FH, Node->getOperand(4));
5565 case ISD::ANY_EXTEND:
5566 // The low part is any extension of the input (which degenerates to a copy).
5567 Lo = DAG.getNode(ISD::ANY_EXTEND, NVT, Node->getOperand(0));
5568 // The high part is undefined.
5569 Hi = DAG.getNode(ISD::UNDEF, NVT);
5571 case ISD::SIGN_EXTEND: {
5572 // The low part is just a sign extension of the input (which degenerates to
5574 Lo = DAG.getNode(ISD::SIGN_EXTEND, NVT, Node->getOperand(0));
5576 // The high part is obtained by SRA'ing all but one of the bits of the lo
5578 unsigned LoSize = MVT::getSizeInBits(Lo.getValueType());
5579 Hi = DAG.getNode(ISD::SRA, NVT, Lo,
5580 DAG.getConstant(LoSize-1, TLI.getShiftAmountTy()));
5583 case ISD::ZERO_EXTEND:
5584 // The low part is just a zero extension of the input (which degenerates to
5586 Lo = DAG.getNode(ISD::ZERO_EXTEND, NVT, Node->getOperand(0));
5588 // The high part is just a zero.
5589 Hi = DAG.getConstant(0, NVT);
5592 case ISD::TRUNCATE: {
5593 // The input value must be larger than this value. Expand *it*.
5595 ExpandOp(Node->getOperand(0), NewLo, Hi);
5597 // The low part is now either the right size, or it is closer. If not the
5598 // right size, make an illegal truncate so we recursively expand it.
5599 if (NewLo.getValueType() != Node->getValueType(0))
5600 NewLo = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), NewLo);
5601 ExpandOp(NewLo, Lo, Hi);
5605 case ISD::BIT_CONVERT: {
5607 if (TLI.getOperationAction(ISD::BIT_CONVERT, VT) == TargetLowering::Custom){
5608 // If the target wants to, allow it to lower this itself.
5609 switch (getTypeAction(Node->getOperand(0).getValueType())) {
5610 case Expand: assert(0 && "cannot expand FP!");
5611 case Legal: Tmp = LegalizeOp(Node->getOperand(0)); break;
5612 case Promote: Tmp = PromoteOp (Node->getOperand(0)); break;
5614 Tmp = TLI.LowerOperation(DAG.getNode(ISD::BIT_CONVERT, VT, Tmp), DAG);
5617 // f32 / f64 must be expanded to i32 / i64.
5618 if (VT == MVT::f32 || VT == MVT::f64) {
5619 Lo = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0));
5620 if (getTypeAction(NVT) == Expand)
5621 ExpandOp(Lo, Lo, Hi);
5625 // If source operand will be expanded to the same type as VT, i.e.
5626 // i64 <- f64, i32 <- f32, expand the source operand instead.
5627 MVT::ValueType VT0 = Node->getOperand(0).getValueType();
5628 if (getTypeAction(VT0) == Expand && TLI.getTypeToTransformTo(VT0) == VT) {
5629 ExpandOp(Node->getOperand(0), Lo, Hi);
5633 // Turn this into a load/store pair by default.
5635 Tmp = ExpandBIT_CONVERT(VT, Node->getOperand(0));
5637 ExpandOp(Tmp, Lo, Hi);
5641 case ISD::READCYCLECOUNTER:
5642 assert(TLI.getOperationAction(ISD::READCYCLECOUNTER, VT) ==
5643 TargetLowering::Custom &&
5644 "Must custom expand ReadCycleCounter");
5645 Lo = TLI.LowerOperation(Op, DAG);
5646 assert(Lo.Val && "Node must be custom expanded!");
5647 Hi = Lo.getValue(1);
5648 AddLegalizedOperand(SDOperand(Node, 1), // Remember we legalized the chain.
5649 LegalizeOp(Lo.getValue(2)));
5652 // These operators cannot be expanded directly, emit them as calls to
5653 // library functions.
5654 case ISD::FP_TO_SINT: {
5655 if (TLI.getOperationAction(ISD::FP_TO_SINT, VT) == TargetLowering::Custom) {
5657 switch (getTypeAction(Node->getOperand(0).getValueType())) {
5658 case Expand: assert(0 && "cannot expand FP!");
5659 case Legal: Op = LegalizeOp(Node->getOperand(0)); break;
5660 case Promote: Op = PromoteOp (Node->getOperand(0)); break;
5663 Op = TLI.LowerOperation(DAG.getNode(ISD::FP_TO_SINT, VT, Op), DAG);
5665 // Now that the custom expander is done, expand the result, which is still
5668 ExpandOp(Op, Lo, Hi);
5673 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
5674 if (Node->getOperand(0).getValueType() == MVT::f32)
5675 LC = RTLIB::FPTOSINT_F32_I64;
5676 else if (Node->getOperand(0).getValueType() == MVT::f64)
5677 LC = RTLIB::FPTOSINT_F64_I64;
5678 else if (Node->getOperand(0).getValueType() == MVT::f80)
5679 LC = RTLIB::FPTOSINT_F80_I64;
5680 else if (Node->getOperand(0).getValueType() == MVT::ppcf128)
5681 LC = RTLIB::FPTOSINT_PPCF128_I64;
5682 Lo = ExpandLibCall(TLI.getLibcallName(LC), Node,
5683 false/*sign irrelevant*/, Hi);
5687 case ISD::FP_TO_UINT: {
5688 if (TLI.getOperationAction(ISD::FP_TO_UINT, VT) == TargetLowering::Custom) {
5690 switch (getTypeAction(Node->getOperand(0).getValueType())) {
5691 case Expand: assert(0 && "cannot expand FP!");
5692 case Legal: Op = LegalizeOp(Node->getOperand(0)); break;
5693 case Promote: Op = PromoteOp (Node->getOperand(0)); break;
5696 Op = TLI.LowerOperation(DAG.getNode(ISD::FP_TO_UINT, VT, Op), DAG);
5698 // Now that the custom expander is done, expand the result.
5700 ExpandOp(Op, Lo, Hi);
5705 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
5706 if (Node->getOperand(0).getValueType() == MVT::f32)
5707 LC = RTLIB::FPTOUINT_F32_I64;
5708 else if (Node->getOperand(0).getValueType() == MVT::f64)
5709 LC = RTLIB::FPTOUINT_F64_I64;
5710 else if (Node->getOperand(0).getValueType() == MVT::f80)
5711 LC = RTLIB::FPTOUINT_F80_I64;
5712 else if (Node->getOperand(0).getValueType() == MVT::ppcf128)
5713 LC = RTLIB::FPTOUINT_PPCF128_I64;
5714 Lo = ExpandLibCall(TLI.getLibcallName(LC), Node,
5715 false/*sign irrelevant*/, Hi);
5720 // If the target wants custom lowering, do so.
5721 SDOperand ShiftAmt = LegalizeOp(Node->getOperand(1));
5722 if (TLI.getOperationAction(ISD::SHL, VT) == TargetLowering::Custom) {
5723 SDOperand Op = DAG.getNode(ISD::SHL, VT, Node->getOperand(0), ShiftAmt);
5724 Op = TLI.LowerOperation(Op, DAG);
5726 // Now that the custom expander is done, expand the result, which is
5728 ExpandOp(Op, Lo, Hi);
5733 // If ADDC/ADDE are supported and if the shift amount is a constant 1, emit
5734 // this X << 1 as X+X.
5735 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(ShiftAmt)) {
5736 if (ShAmt->getValue() == 1 && TLI.isOperationLegal(ISD::ADDC, NVT) &&
5737 TLI.isOperationLegal(ISD::ADDE, NVT)) {
5738 SDOperand LoOps[2], HiOps[3];
5739 ExpandOp(Node->getOperand(0), LoOps[0], HiOps[0]);
5740 SDVTList VTList = DAG.getVTList(LoOps[0].getValueType(), MVT::Flag);
5741 LoOps[1] = LoOps[0];
5742 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2);
5744 HiOps[1] = HiOps[0];
5745 HiOps[2] = Lo.getValue(1);
5746 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3);
5751 // If we can emit an efficient shift operation, do so now.
5752 if (ExpandShift(ISD::SHL, Node->getOperand(0), ShiftAmt, Lo, Hi))
5755 // If this target supports SHL_PARTS, use it.
5756 TargetLowering::LegalizeAction Action =
5757 TLI.getOperationAction(ISD::SHL_PARTS, NVT);
5758 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) ||
5759 Action == TargetLowering::Custom) {
5760 ExpandShiftParts(ISD::SHL_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi);
5764 // Otherwise, emit a libcall.
5765 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::SHL_I64), Node,
5766 false/*left shift=unsigned*/, Hi);
5771 // If the target wants custom lowering, do so.
5772 SDOperand ShiftAmt = LegalizeOp(Node->getOperand(1));
5773 if (TLI.getOperationAction(ISD::SRA, VT) == TargetLowering::Custom) {
5774 SDOperand Op = DAG.getNode(ISD::SRA, VT, Node->getOperand(0), ShiftAmt);
5775 Op = TLI.LowerOperation(Op, DAG);
5777 // Now that the custom expander is done, expand the result, which is
5779 ExpandOp(Op, Lo, Hi);
5784 // If we can emit an efficient shift operation, do so now.
5785 if (ExpandShift(ISD::SRA, Node->getOperand(0), ShiftAmt, Lo, Hi))
5788 // If this target supports SRA_PARTS, use it.
5789 TargetLowering::LegalizeAction Action =
5790 TLI.getOperationAction(ISD::SRA_PARTS, NVT);
5791 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) ||
5792 Action == TargetLowering::Custom) {
5793 ExpandShiftParts(ISD::SRA_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi);
5797 // Otherwise, emit a libcall.
5798 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::SRA_I64), Node,
5799 true/*ashr is signed*/, Hi);
5804 // If the target wants custom lowering, do so.
5805 SDOperand ShiftAmt = LegalizeOp(Node->getOperand(1));
5806 if (TLI.getOperationAction(ISD::SRL, VT) == TargetLowering::Custom) {
5807 SDOperand Op = DAG.getNode(ISD::SRL, VT, Node->getOperand(0), ShiftAmt);
5808 Op = TLI.LowerOperation(Op, DAG);
5810 // Now that the custom expander is done, expand the result, which is
5812 ExpandOp(Op, Lo, Hi);
5817 // If we can emit an efficient shift operation, do so now.
5818 if (ExpandShift(ISD::SRL, Node->getOperand(0), ShiftAmt, Lo, Hi))
5821 // If this target supports SRL_PARTS, use it.
5822 TargetLowering::LegalizeAction Action =
5823 TLI.getOperationAction(ISD::SRL_PARTS, NVT);
5824 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) ||
5825 Action == TargetLowering::Custom) {
5826 ExpandShiftParts(ISD::SRL_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi);
5830 // Otherwise, emit a libcall.
5831 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::SRL_I64), Node,
5832 false/*lshr is unsigned*/, Hi);
5838 // If the target wants to custom expand this, let them.
5839 if (TLI.getOperationAction(Node->getOpcode(), VT) ==
5840 TargetLowering::Custom) {
5841 Op = TLI.LowerOperation(Op, DAG);
5843 ExpandOp(Op, Lo, Hi);
5848 // Expand the subcomponents.
5849 SDOperand LHSL, LHSH, RHSL, RHSH;
5850 ExpandOp(Node->getOperand(0), LHSL, LHSH);
5851 ExpandOp(Node->getOperand(1), RHSL, RHSH);
5852 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag);
5853 SDOperand LoOps[2], HiOps[3];
5858 if (Node->getOpcode() == ISD::ADD) {
5859 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2);
5860 HiOps[2] = Lo.getValue(1);
5861 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3);
5863 Lo = DAG.getNode(ISD::SUBC, VTList, LoOps, 2);
5864 HiOps[2] = Lo.getValue(1);
5865 Hi = DAG.getNode(ISD::SUBE, VTList, HiOps, 3);
5872 // Expand the subcomponents.
5873 SDOperand LHSL, LHSH, RHSL, RHSH;
5874 ExpandOp(Node->getOperand(0), LHSL, LHSH);
5875 ExpandOp(Node->getOperand(1), RHSL, RHSH);
5876 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag);
5877 SDOperand LoOps[2] = { LHSL, RHSL };
5878 SDOperand HiOps[3] = { LHSH, RHSH };
5880 if (Node->getOpcode() == ISD::ADDC) {
5881 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2);
5882 HiOps[2] = Lo.getValue(1);
5883 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3);
5885 Lo = DAG.getNode(ISD::SUBC, VTList, LoOps, 2);
5886 HiOps[2] = Lo.getValue(1);
5887 Hi = DAG.getNode(ISD::SUBE, VTList, HiOps, 3);
5889 // Remember that we legalized the flag.
5890 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Hi.getValue(1)));
5895 // Expand the subcomponents.
5896 SDOperand LHSL, LHSH, RHSL, RHSH;
5897 ExpandOp(Node->getOperand(0), LHSL, LHSH);
5898 ExpandOp(Node->getOperand(1), RHSL, RHSH);
5899 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag);
5900 SDOperand LoOps[3] = { LHSL, RHSL, Node->getOperand(2) };
5901 SDOperand HiOps[3] = { LHSH, RHSH };
5903 Lo = DAG.getNode(Node->getOpcode(), VTList, LoOps, 3);
5904 HiOps[2] = Lo.getValue(1);
5905 Hi = DAG.getNode(Node->getOpcode(), VTList, HiOps, 3);
5907 // Remember that we legalized the flag.
5908 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Hi.getValue(1)));
5912 // If the target wants to custom expand this, let them.
5913 if (TLI.getOperationAction(ISD::MUL, VT) == TargetLowering::Custom) {
5914 SDOperand New = TLI.LowerOperation(Op, DAG);
5916 ExpandOp(New, Lo, Hi);
5921 bool HasMULHS = TLI.isOperationLegal(ISD::MULHS, NVT);
5922 bool HasMULHU = TLI.isOperationLegal(ISD::MULHU, NVT);
5923 bool HasSMUL_LOHI = TLI.isOperationLegal(ISD::SMUL_LOHI, NVT);
5924 bool HasUMUL_LOHI = TLI.isOperationLegal(ISD::UMUL_LOHI, NVT);
5925 if (HasMULHU || HasMULHS || HasUMUL_LOHI || HasSMUL_LOHI) {
5926 SDOperand LL, LH, RL, RH;
5927 ExpandOp(Node->getOperand(0), LL, LH);
5928 ExpandOp(Node->getOperand(1), RL, RH);
5929 unsigned BitSize = MVT::getSizeInBits(RH.getValueType());
5930 unsigned LHSSB = DAG.ComputeNumSignBits(Op.getOperand(0));
5931 unsigned RHSSB = DAG.ComputeNumSignBits(Op.getOperand(1));
5932 // FIXME: generalize this to handle other bit sizes
5933 if (LHSSB == 32 && RHSSB == 32 &&
5934 DAG.MaskedValueIsZero(Op.getOperand(0), 0xFFFFFFFF00000000ULL) &&
5935 DAG.MaskedValueIsZero(Op.getOperand(1), 0xFFFFFFFF00000000ULL)) {
5936 // The inputs are both zero-extended.
5938 // We can emit a umul_lohi.
5939 Lo = DAG.getNode(ISD::UMUL_LOHI, DAG.getVTList(NVT, NVT), LL, RL);
5940 Hi = SDOperand(Lo.Val, 1);
5944 // We can emit a mulhu+mul.
5945 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL);
5946 Hi = DAG.getNode(ISD::MULHU, NVT, LL, RL);
5950 if (LHSSB > BitSize && RHSSB > BitSize) {
5951 // The input values are both sign-extended.
5953 // We can emit a smul_lohi.
5954 Lo = DAG.getNode(ISD::SMUL_LOHI, DAG.getVTList(NVT, NVT), LL, RL);
5955 Hi = SDOperand(Lo.Val, 1);
5959 // We can emit a mulhs+mul.
5960 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL);
5961 Hi = DAG.getNode(ISD::MULHS, NVT, LL, RL);
5966 // Lo,Hi = umul LHS, RHS.
5967 SDOperand UMulLOHI = DAG.getNode(ISD::UMUL_LOHI,
5968 DAG.getVTList(NVT, NVT), LL, RL);
5970 Hi = UMulLOHI.getValue(1);
5971 RH = DAG.getNode(ISD::MUL, NVT, LL, RH);
5972 LH = DAG.getNode(ISD::MUL, NVT, LH, RL);
5973 Hi = DAG.getNode(ISD::ADD, NVT, Hi, RH);
5974 Hi = DAG.getNode(ISD::ADD, NVT, Hi, LH);
5978 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL);
5979 Hi = DAG.getNode(ISD::MULHU, NVT, LL, RL);
5980 RH = DAG.getNode(ISD::MUL, NVT, LL, RH);
5981 LH = DAG.getNode(ISD::MUL, NVT, LH, RL);
5982 Hi = DAG.getNode(ISD::ADD, NVT, Hi, RH);
5983 Hi = DAG.getNode(ISD::ADD, NVT, Hi, LH);
5988 // If nothing else, we can make a libcall.
5989 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::MUL_I64), Node,
5990 false/*sign irrelevant*/, Hi);
5994 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::SDIV_I64), Node, true, Hi);
5997 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::UDIV_I64), Node, true, Hi);
6000 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::SREM_I64), Node, true, Hi);
6003 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::UREM_I64), Node, true, Hi);
6007 Lo = ExpandLibCall(TLI.getLibcallName(VT == MVT::f32 ? RTLIB::ADD_F32 :
6008 VT == MVT::f64 ? RTLIB::ADD_F64 :
6009 VT == MVT::ppcf128 ?
6010 RTLIB::ADD_PPCF128 :
6011 RTLIB::UNKNOWN_LIBCALL),
6015 Lo = ExpandLibCall(TLI.getLibcallName(VT == MVT::f32 ? RTLIB::SUB_F32 :
6016 VT == MVT::f64 ? RTLIB::SUB_F64 :
6017 VT == MVT::ppcf128 ?
6018 RTLIB::SUB_PPCF128 :
6019 RTLIB::UNKNOWN_LIBCALL),
6023 Lo = ExpandLibCall(TLI.getLibcallName(VT == MVT::f32 ? RTLIB::MUL_F32 :
6024 VT == MVT::f64 ? RTLIB::MUL_F64 :
6025 VT == MVT::ppcf128 ?
6026 RTLIB::MUL_PPCF128 :
6027 RTLIB::UNKNOWN_LIBCALL),
6031 Lo = ExpandLibCall(TLI.getLibcallName(VT == MVT::f32 ? RTLIB::DIV_F32 :
6032 VT == MVT::f64 ? RTLIB::DIV_F64 :
6033 VT == MVT::ppcf128 ?
6034 RTLIB::DIV_PPCF128 :
6035 RTLIB::UNKNOWN_LIBCALL),
6038 case ISD::FP_EXTEND:
6039 if (VT == MVT::ppcf128) {
6040 assert(Node->getOperand(0).getValueType()==MVT::f32 ||
6041 Node->getOperand(0).getValueType()==MVT::f64);
6042 const uint64_t zero = 0;
6043 if (Node->getOperand(0).getValueType()==MVT::f32)
6044 Hi = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Node->getOperand(0));
6046 Hi = Node->getOperand(0);
6047 Lo = DAG.getConstantFP(APFloat(APInt(64, 1, &zero)), MVT::f64);
6050 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::FPEXT_F32_F64), Node, true,Hi);
6053 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::FPROUND_F64_F32),Node,true,Hi);
6056 Lo = ExpandLibCall(TLI.getLibcallName((VT == MVT::f32) ? RTLIB::POWI_F32 :
6057 (VT == MVT::f64) ? RTLIB::POWI_F64 :
6058 (VT == MVT::f80) ? RTLIB::POWI_F80 :
6059 (VT == MVT::ppcf128) ?
6060 RTLIB::POWI_PPCF128 :
6061 RTLIB::UNKNOWN_LIBCALL),
6067 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
6068 switch(Node->getOpcode()) {
6070 LC = (VT == MVT::f32) ? RTLIB::SQRT_F32 :
6071 (VT == MVT::f64) ? RTLIB::SQRT_F64 :
6072 (VT == MVT::f80) ? RTLIB::SQRT_F80 :
6073 (VT == MVT::ppcf128) ? RTLIB::SQRT_PPCF128 :
6074 RTLIB::UNKNOWN_LIBCALL;
6077 LC = (VT == MVT::f32) ? RTLIB::SIN_F32 : RTLIB::SIN_F64;
6080 LC = (VT == MVT::f32) ? RTLIB::COS_F32 : RTLIB::COS_F64;
6082 default: assert(0 && "Unreachable!");
6084 Lo = ExpandLibCall(TLI.getLibcallName(LC), Node, false, Hi);
6088 if (VT == MVT::ppcf128) {
6090 ExpandOp(Node->getOperand(0), Lo, Tmp);
6091 Hi = DAG.getNode(ISD::FABS, NVT, Tmp);
6092 // lo = hi==fabs(hi) ? lo : -lo;
6093 Lo = DAG.getNode(ISD::SELECT_CC, NVT, Hi, Tmp,
6094 Lo, DAG.getNode(ISD::FNEG, NVT, Lo),
6095 DAG.getCondCode(ISD::SETEQ));
6098 SDOperand Mask = (VT == MVT::f64)
6099 ? DAG.getConstantFP(BitsToDouble(~(1ULL << 63)), VT)
6100 : DAG.getConstantFP(BitsToFloat(~(1U << 31)), VT);
6101 Mask = DAG.getNode(ISD::BIT_CONVERT, NVT, Mask);
6102 Lo = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0));
6103 Lo = DAG.getNode(ISD::AND, NVT, Lo, Mask);
6104 if (getTypeAction(NVT) == Expand)
6105 ExpandOp(Lo, Lo, Hi);
6109 if (VT == MVT::ppcf128) {
6110 ExpandOp(Node->getOperand(0), Lo, Hi);
6111 Lo = DAG.getNode(ISD::FNEG, MVT::f64, Lo);
6112 Hi = DAG.getNode(ISD::FNEG, MVT::f64, Hi);
6115 SDOperand Mask = (VT == MVT::f64)
6116 ? DAG.getConstantFP(BitsToDouble(1ULL << 63), VT)
6117 : DAG.getConstantFP(BitsToFloat(1U << 31), VT);
6118 Mask = DAG.getNode(ISD::BIT_CONVERT, NVT, Mask);
6119 Lo = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0));
6120 Lo = DAG.getNode(ISD::XOR, NVT, Lo, Mask);
6121 if (getTypeAction(NVT) == Expand)
6122 ExpandOp(Lo, Lo, Hi);
6125 case ISD::FCOPYSIGN: {
6126 Lo = ExpandFCOPYSIGNToBitwiseOps(Node, NVT, DAG, TLI);
6127 if (getTypeAction(NVT) == Expand)
6128 ExpandOp(Lo, Lo, Hi);
6131 case ISD::SINT_TO_FP:
6132 case ISD::UINT_TO_FP: {
6133 bool isSigned = Node->getOpcode() == ISD::SINT_TO_FP;
6134 MVT::ValueType SrcVT = Node->getOperand(0).getValueType();
6135 if (VT == MVT::ppcf128 && SrcVT != MVT::i64) {
6136 static uint64_t zero = 0;
6138 Hi = LegalizeOp(DAG.getNode(ISD::SINT_TO_FP, MVT::f64,
6139 Node->getOperand(0)));
6140 Lo = DAG.getConstantFP(APFloat(APInt(64, 1, &zero)), MVT::f64);
6142 static uint64_t TwoE32[] = { 0x41f0000000000000LL, 0 };
6143 Hi = LegalizeOp(DAG.getNode(ISD::SINT_TO_FP, MVT::f64,
6144 Node->getOperand(0)));
6145 Lo = DAG.getConstantFP(APFloat(APInt(64, 1, &zero)), MVT::f64);
6146 Hi = DAG.getNode(ISD::BUILD_PAIR, VT, Lo, Hi);
6147 // X>=0 ? {(f64)x, 0} : {(f64)x, 0} + 2^32
6148 ExpandOp(DAG.getNode(ISD::SELECT_CC, MVT::ppcf128, Node->getOperand(0),
6149 DAG.getConstant(0, MVT::i32),
6150 DAG.getNode(ISD::FADD, MVT::ppcf128, Hi,
6152 APFloat(APInt(128, 2, TwoE32)),
6155 DAG.getCondCode(ISD::SETLT)),
6160 if (VT == MVT::ppcf128 && SrcVT == MVT::i64 && !isSigned) {
6161 // si64->ppcf128 done by libcall, below
6162 static uint64_t TwoE64[] = { 0x43f0000000000000LL, 0 };
6163 ExpandOp(DAG.getNode(ISD::SINT_TO_FP, MVT::ppcf128, Node->getOperand(0)),
6165 Hi = DAG.getNode(ISD::BUILD_PAIR, VT, Lo, Hi);
6166 // x>=0 ? (ppcf128)(i64)x : (ppcf128)(i64)x + 2^64
6167 ExpandOp(DAG.getNode(ISD::SELECT_CC, MVT::ppcf128, Node->getOperand(0),
6168 DAG.getConstant(0, MVT::i64),
6169 DAG.getNode(ISD::FADD, MVT::ppcf128, Hi,
6171 APFloat(APInt(128, 2, TwoE64)),
6174 DAG.getCondCode(ISD::SETLT)),
6178 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
6179 if (Node->getOperand(0).getValueType() == MVT::i64) {
6181 LC = isSigned ? RTLIB::SINTTOFP_I64_F32 : RTLIB::UINTTOFP_I64_F32;
6182 else if (VT == MVT::f64)
6183 LC = isSigned ? RTLIB::SINTTOFP_I64_F64 : RTLIB::UINTTOFP_I64_F64;
6184 else if (VT == MVT::f80) {
6186 LC = RTLIB::SINTTOFP_I64_F80;
6188 else if (VT == MVT::ppcf128) {
6190 LC = RTLIB::SINTTOFP_I64_PPCF128;
6194 LC = isSigned ? RTLIB::SINTTOFP_I32_F32 : RTLIB::UINTTOFP_I32_F32;
6196 LC = isSigned ? RTLIB::SINTTOFP_I32_F64 : RTLIB::UINTTOFP_I32_F64;
6199 // Promote the operand if needed.
6200 if (getTypeAction(SrcVT) == Promote) {
6201 SDOperand Tmp = PromoteOp(Node->getOperand(0));
6203 ? DAG.getNode(ISD::SIGN_EXTEND_INREG, Tmp.getValueType(), Tmp,
6204 DAG.getValueType(SrcVT))
6205 : DAG.getZeroExtendInReg(Tmp, SrcVT);
6206 Node = DAG.UpdateNodeOperands(Op, Tmp).Val;
6209 const char *LibCall = TLI.getLibcallName(LC);
6211 Lo = ExpandLibCall(TLI.getLibcallName(LC), Node, isSigned, Hi);
6213 Lo = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP, VT,
6214 Node->getOperand(0));
6215 if (getTypeAction(Lo.getValueType()) == Expand)
6216 ExpandOp(Lo, Lo, Hi);
6222 // Make sure the resultant values have been legalized themselves, unless this
6223 // is a type that requires multi-step expansion.
6224 if (getTypeAction(NVT) != Expand && NVT != MVT::isVoid) {
6225 Lo = LegalizeOp(Lo);
6227 // Don't legalize the high part if it is expanded to a single node.
6228 Hi = LegalizeOp(Hi);
6231 // Remember in a map if the values will be reused later.
6232 bool isNew = ExpandedNodes.insert(std::make_pair(Op, std::make_pair(Lo, Hi)));
6233 assert(isNew && "Value already expanded?!?");
6236 /// SplitVectorOp - Given an operand of vector type, break it down into
6237 /// two smaller values, still of vector type.
6238 void SelectionDAGLegalize::SplitVectorOp(SDOperand Op, SDOperand &Lo,
6240 assert(MVT::isVector(Op.getValueType()) && "Cannot split non-vector type!");
6241 SDNode *Node = Op.Val;
6242 unsigned NumElements = MVT::getVectorNumElements(Op.getValueType());
6243 assert(NumElements > 1 && "Cannot split a single element vector!");
6245 MVT::ValueType NewEltVT = MVT::getVectorElementType(Op.getValueType());
6247 unsigned NewNumElts_Lo = 1 << Log2_32(NumElements-1);
6248 unsigned NewNumElts_Hi = NumElements - NewNumElts_Lo;
6250 MVT::ValueType NewVT_Lo = MVT::getVectorType(NewEltVT, NewNumElts_Lo);
6251 MVT::ValueType NewVT_Hi = MVT::getVectorType(NewEltVT, NewNumElts_Hi);
6253 // See if we already split it.
6254 std::map<SDOperand, std::pair<SDOperand, SDOperand> >::iterator I
6255 = SplitNodes.find(Op);
6256 if (I != SplitNodes.end()) {
6257 Lo = I->second.first;
6258 Hi = I->second.second;
6262 switch (Node->getOpcode()) {
6267 assert(0 && "Unhandled operation in SplitVectorOp!");
6268 case ISD::BUILD_PAIR:
6269 Lo = Node->getOperand(0);
6270 Hi = Node->getOperand(1);
6272 case ISD::INSERT_VECTOR_ELT: {
6273 SplitVectorOp(Node->getOperand(0), Lo, Hi);
6274 unsigned Index = cast<ConstantSDNode>(Node->getOperand(2))->getValue();
6275 SDOperand ScalarOp = Node->getOperand(1);
6276 if (Index < NewNumElts_Lo)
6277 Lo = DAG.getNode(ISD::INSERT_VECTOR_ELT, NewVT_Lo, Lo, ScalarOp,
6278 DAG.getConstant(Index, TLI.getPointerTy()));
6280 Hi = DAG.getNode(ISD::INSERT_VECTOR_ELT, NewVT_Hi, Hi, ScalarOp,
6281 DAG.getConstant(Index - NewNumElts_Lo,
6282 TLI.getPointerTy()));
6285 case ISD::BUILD_VECTOR: {
6286 SmallVector<SDOperand, 8> LoOps(Node->op_begin(),
6287 Node->op_begin()+NewNumElts_Lo);
6288 Lo = DAG.getNode(ISD::BUILD_VECTOR, NewVT_Lo, &LoOps[0], LoOps.size());
6290 SmallVector<SDOperand, 8> HiOps(Node->op_begin()+NewNumElts_Lo,
6292 Hi = DAG.getNode(ISD::BUILD_VECTOR, NewVT_Hi, &HiOps[0], HiOps.size());
6295 case ISD::CONCAT_VECTORS: {
6296 // FIXME: Handle non-power-of-two vectors?
6297 unsigned NewNumSubvectors = Node->getNumOperands() / 2;
6298 if (NewNumSubvectors == 1) {
6299 Lo = Node->getOperand(0);
6300 Hi = Node->getOperand(1);
6302 SmallVector<SDOperand, 8> LoOps(Node->op_begin(),
6303 Node->op_begin()+NewNumSubvectors);
6304 Lo = DAG.getNode(ISD::CONCAT_VECTORS, NewVT_Lo, &LoOps[0], LoOps.size());
6306 SmallVector<SDOperand, 8> HiOps(Node->op_begin()+NewNumSubvectors,
6308 Hi = DAG.getNode(ISD::CONCAT_VECTORS, NewVT_Hi, &HiOps[0], HiOps.size());
6313 SDOperand Cond = Node->getOperand(0);
6315 SDOperand LL, LH, RL, RH;
6316 SplitVectorOp(Node->getOperand(1), LL, LH);
6317 SplitVectorOp(Node->getOperand(2), RL, RH);
6319 if (MVT::isVector(Cond.getValueType())) {
6320 // Handle a vector merge.
6322 SplitVectorOp(Cond, CL, CH);
6323 Lo = DAG.getNode(Node->getOpcode(), NewVT_Lo, CL, LL, RL);
6324 Hi = DAG.getNode(Node->getOpcode(), NewVT_Hi, CH, LH, RH);
6326 // Handle a simple select with vector operands.
6327 Lo = DAG.getNode(Node->getOpcode(), NewVT_Lo, Cond, LL, RL);
6328 Hi = DAG.getNode(Node->getOpcode(), NewVT_Hi, Cond, LH, RH);
6348 SDOperand LL, LH, RL, RH;
6349 SplitVectorOp(Node->getOperand(0), LL, LH);
6350 SplitVectorOp(Node->getOperand(1), RL, RH);
6352 Lo = DAG.getNode(Node->getOpcode(), NewVT_Lo, LL, RL);
6353 Hi = DAG.getNode(Node->getOpcode(), NewVT_Hi, LH, RH);
6358 SplitVectorOp(Node->getOperand(0), L, H);
6360 Lo = DAG.getNode(Node->getOpcode(), NewVT_Lo, L, Node->getOperand(1));
6361 Hi = DAG.getNode(Node->getOpcode(), NewVT_Hi, H, Node->getOperand(1));
6372 case ISD::FP_TO_SINT:
6373 case ISD::FP_TO_UINT:
6374 case ISD::SINT_TO_FP:
6375 case ISD::UINT_TO_FP: {
6377 SplitVectorOp(Node->getOperand(0), L, H);
6379 Lo = DAG.getNode(Node->getOpcode(), NewVT_Lo, L);
6380 Hi = DAG.getNode(Node->getOpcode(), NewVT_Hi, H);
6384 LoadSDNode *LD = cast<LoadSDNode>(Node);
6385 SDOperand Ch = LD->getChain();
6386 SDOperand Ptr = LD->getBasePtr();
6387 const Value *SV = LD->getSrcValue();
6388 int SVOffset = LD->getSrcValueOffset();
6389 unsigned Alignment = LD->getAlignment();
6390 bool isVolatile = LD->isVolatile();
6392 Lo = DAG.getLoad(NewVT_Lo, Ch, Ptr, SV, SVOffset, isVolatile, Alignment);
6393 unsigned IncrementSize = NewNumElts_Lo * MVT::getSizeInBits(NewEltVT)/8;
6394 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
6395 getIntPtrConstant(IncrementSize));
6396 SVOffset += IncrementSize;
6397 Alignment = MinAlign(Alignment, IncrementSize);
6398 Hi = DAG.getLoad(NewVT_Hi, Ch, Ptr, SV, SVOffset, isVolatile, Alignment);
6400 // Build a factor node to remember that this load is independent of the
6402 SDOperand TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
6405 // Remember that we legalized the chain.
6406 AddLegalizedOperand(Op.getValue(1), LegalizeOp(TF));
6409 case ISD::BIT_CONVERT: {
6410 // We know the result is a vector. The input may be either a vector or a
6412 SDOperand InOp = Node->getOperand(0);
6413 if (!MVT::isVector(InOp.getValueType()) ||
6414 MVT::getVectorNumElements(InOp.getValueType()) == 1) {
6415 // The input is a scalar or single-element vector.
6416 // Lower to a store/load so that it can be split.
6417 // FIXME: this could be improved probably.
6418 SDOperand Ptr = DAG.CreateStackTemporary(InOp.getValueType());
6420 SDOperand St = DAG.getStore(DAG.getEntryNode(),
6421 InOp, Ptr, NULL, 0);
6422 InOp = DAG.getLoad(Op.getValueType(), St, Ptr, NULL, 0);
6424 // Split the vector and convert each of the pieces now.
6425 SplitVectorOp(InOp, Lo, Hi);
6426 Lo = DAG.getNode(ISD::BIT_CONVERT, NewVT_Lo, Lo);
6427 Hi = DAG.getNode(ISD::BIT_CONVERT, NewVT_Hi, Hi);
6432 // Remember in a map if the values will be reused later.
6434 SplitNodes.insert(std::make_pair(Op, std::make_pair(Lo, Hi))).second;
6435 assert(isNew && "Value already split?!?");
6439 /// ScalarizeVectorOp - Given an operand of single-element vector type
6440 /// (e.g. v1f32), convert it into the equivalent operation that returns a
6441 /// scalar (e.g. f32) value.
6442 SDOperand SelectionDAGLegalize::ScalarizeVectorOp(SDOperand Op) {
6443 assert(MVT::isVector(Op.getValueType()) &&
6444 "Bad ScalarizeVectorOp invocation!");
6445 SDNode *Node = Op.Val;
6446 MVT::ValueType NewVT = MVT::getVectorElementType(Op.getValueType());
6447 assert(MVT::getVectorNumElements(Op.getValueType()) == 1);
6449 // See if we already scalarized it.
6450 std::map<SDOperand, SDOperand>::iterator I = ScalarizedNodes.find(Op);
6451 if (I != ScalarizedNodes.end()) return I->second;
6454 switch (Node->getOpcode()) {
6457 Node->dump(&DAG); cerr << "\n";
6459 assert(0 && "Unknown vector operation in ScalarizeVectorOp!");
6476 Result = DAG.getNode(Node->getOpcode(),
6478 ScalarizeVectorOp(Node->getOperand(0)),
6479 ScalarizeVectorOp(Node->getOperand(1)));
6486 Result = DAG.getNode(Node->getOpcode(),
6488 ScalarizeVectorOp(Node->getOperand(0)));
6491 Result = DAG.getNode(Node->getOpcode(),
6493 ScalarizeVectorOp(Node->getOperand(0)),
6494 Node->getOperand(1));
6497 LoadSDNode *LD = cast<LoadSDNode>(Node);
6498 SDOperand Ch = LegalizeOp(LD->getChain()); // Legalize the chain.
6499 SDOperand Ptr = LegalizeOp(LD->getBasePtr()); // Legalize the pointer.
6501 const Value *SV = LD->getSrcValue();
6502 int SVOffset = LD->getSrcValueOffset();
6503 Result = DAG.getLoad(NewVT, Ch, Ptr, SV, SVOffset,
6504 LD->isVolatile(), LD->getAlignment());
6506 // Remember that we legalized the chain.
6507 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
6510 case ISD::BUILD_VECTOR:
6511 Result = Node->getOperand(0);
6513 case ISD::INSERT_VECTOR_ELT:
6514 // Returning the inserted scalar element.
6515 Result = Node->getOperand(1);
6517 case ISD::CONCAT_VECTORS:
6518 assert(Node->getOperand(0).getValueType() == NewVT &&
6519 "Concat of non-legal vectors not yet supported!");
6520 Result = Node->getOperand(0);
6522 case ISD::VECTOR_SHUFFLE: {
6523 // Figure out if the scalar is the LHS or RHS and return it.
6524 SDOperand EltNum = Node->getOperand(2).getOperand(0);
6525 if (cast<ConstantSDNode>(EltNum)->getValue())
6526 Result = ScalarizeVectorOp(Node->getOperand(1));
6528 Result = ScalarizeVectorOp(Node->getOperand(0));
6531 case ISD::EXTRACT_SUBVECTOR:
6532 Result = Node->getOperand(0);
6533 assert(Result.getValueType() == NewVT);
6535 case ISD::BIT_CONVERT:
6536 Result = DAG.getNode(ISD::BIT_CONVERT, NewVT, Op.getOperand(0));
6539 Result = DAG.getNode(ISD::SELECT, NewVT, Op.getOperand(0),
6540 ScalarizeVectorOp(Op.getOperand(1)),
6541 ScalarizeVectorOp(Op.getOperand(2)));
6545 if (TLI.isTypeLegal(NewVT))
6546 Result = LegalizeOp(Result);
6547 bool isNew = ScalarizedNodes.insert(std::make_pair(Op, Result)).second;
6548 assert(isNew && "Value already scalarized?");
6553 // SelectionDAG::Legalize - This is the entry point for the file.
6555 void SelectionDAG::Legalize() {
6556 if (ViewLegalizeDAGs) viewGraph();
6558 /// run - This is the main entry point to this class.
6560 SelectionDAGLegalize(*this).LegalizeDAG();