1 //===-- LegalizeDAG.cpp - Implement SelectionDAG::Legalize ----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the SelectionDAG::Legalize method.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/CodeGen/SelectionDAG.h"
15 #include "llvm/CodeGen/MachineFunction.h"
16 #include "llvm/CodeGen/MachineFrameInfo.h"
17 #include "llvm/Target/TargetLowering.h"
18 #include "llvm/Target/TargetData.h"
19 #include "llvm/Target/TargetMachine.h"
20 #include "llvm/Target/TargetOptions.h"
21 #include "llvm/CallingConv.h"
22 #include "llvm/Constants.h"
23 #include "llvm/Support/MathExtras.h"
24 #include "llvm/Support/CommandLine.h"
25 #include "llvm/Support/Compiler.h"
26 #include "llvm/ADT/SmallVector.h"
32 ViewLegalizeDAGs("view-legalize-dags", cl::Hidden,
33 cl::desc("Pop up a window to show dags before legalize"));
35 static const bool ViewLegalizeDAGs = 0;
38 //===----------------------------------------------------------------------===//
39 /// SelectionDAGLegalize - This takes an arbitrary SelectionDAG as input and
40 /// hacks on it until the target machine can handle it. This involves
41 /// eliminating value sizes the machine cannot handle (promoting small sizes to
42 /// large sizes or splitting up large values into small values) as well as
43 /// eliminating operations the machine cannot handle.
45 /// This code also does a small amount of optimization and recognition of idioms
46 /// as part of its processing. For example, if a target does not support a
47 /// 'setcc' instruction efficiently, but does support 'brcc' instruction, this
48 /// will attempt merge setcc and brc instructions into brcc's.
51 class VISIBILITY_HIDDEN SelectionDAGLegalize {
55 // Libcall insertion helpers.
57 /// LastCALLSEQ_END - This keeps track of the CALLSEQ_END node that has been
58 /// legalized. We use this to ensure that calls are properly serialized
59 /// against each other, including inserted libcalls.
60 SDOperand LastCALLSEQ_END;
62 /// IsLegalizingCall - This member is used *only* for purposes of providing
63 /// helpful assertions that a libcall isn't created while another call is
64 /// being legalized (which could lead to non-serialized call sequences).
65 bool IsLegalizingCall;
68 Legal, // The target natively supports this operation.
69 Promote, // This operation should be executed in a larger type.
70 Expand // Try to expand this to other ops, otherwise use a libcall.
73 /// ValueTypeActions - This is a bitvector that contains two bits for each
74 /// value type, where the two bits correspond to the LegalizeAction enum.
75 /// This can be queried with "getTypeAction(VT)".
76 TargetLowering::ValueTypeActionImpl ValueTypeActions;
78 /// LegalizedNodes - For nodes that are of legal width, and that have more
79 /// than one use, this map indicates what regularized operand to use. This
80 /// allows us to avoid legalizing the same thing more than once.
81 std::map<SDOperand, SDOperand> LegalizedNodes;
83 /// PromotedNodes - For nodes that are below legal width, and that have more
84 /// than one use, this map indicates what promoted value to use. This allows
85 /// us to avoid promoting the same thing more than once.
86 std::map<SDOperand, SDOperand> PromotedNodes;
88 /// ExpandedNodes - For nodes that need to be expanded this map indicates
89 /// which which operands are the expanded version of the input. This allows
90 /// us to avoid expanding the same node more than once.
91 std::map<SDOperand, std::pair<SDOperand, SDOperand> > ExpandedNodes;
93 /// SplitNodes - For vector nodes that need to be split, this map indicates
94 /// which which operands are the split version of the input. This allows us
95 /// to avoid splitting the same node more than once.
96 std::map<SDOperand, std::pair<SDOperand, SDOperand> > SplitNodes;
98 /// PackedNodes - For nodes that need to be packed from MVT::Vector types to
99 /// concrete packed types, this contains the mapping of ones we have already
100 /// processed to the result.
101 std::map<SDOperand, SDOperand> PackedNodes;
103 void AddLegalizedOperand(SDOperand From, SDOperand To) {
104 LegalizedNodes.insert(std::make_pair(From, To));
105 // If someone requests legalization of the new node, return itself.
107 LegalizedNodes.insert(std::make_pair(To, To));
109 void AddPromotedOperand(SDOperand From, SDOperand To) {
110 bool isNew = PromotedNodes.insert(std::make_pair(From, To)).second;
111 assert(isNew && "Got into the map somehow?");
112 // If someone requests legalization of the new node, return itself.
113 LegalizedNodes.insert(std::make_pair(To, To));
118 SelectionDAGLegalize(SelectionDAG &DAG);
120 /// getTypeAction - Return how we should legalize values of this type, either
121 /// it is already legal or we need to expand it into multiple registers of
122 /// smaller integer type, or we need to promote it to a larger type.
123 LegalizeAction getTypeAction(MVT::ValueType VT) const {
124 return (LegalizeAction)ValueTypeActions.getTypeAction(VT);
127 /// isTypeLegal - Return true if this type is legal on this target.
129 bool isTypeLegal(MVT::ValueType VT) const {
130 return getTypeAction(VT) == Legal;
136 /// HandleOp - Legalize, Promote, Expand or Pack the specified operand as
137 /// appropriate for its type.
138 void HandleOp(SDOperand Op);
140 /// LegalizeOp - We know that the specified value has a legal type.
141 /// Recursively ensure that the operands have legal types, then return the
143 SDOperand LegalizeOp(SDOperand O);
145 /// PromoteOp - Given an operation that produces a value in an invalid type,
146 /// promote it to compute the value into a larger type. The produced value
147 /// will have the correct bits for the low portion of the register, but no
148 /// guarantee is made about the top bits: it may be zero, sign-extended, or
150 SDOperand PromoteOp(SDOperand O);
152 /// ExpandOp - Expand the specified SDOperand into its two component pieces
153 /// Lo&Hi. Note that the Op MUST be an expanded type. As a result of this,
154 /// the LegalizeNodes map is filled in for any results that are not expanded,
155 /// the ExpandedNodes map is filled in for any results that are expanded, and
156 /// the Lo/Hi values are returned. This applies to integer types and Vector
158 void ExpandOp(SDOperand O, SDOperand &Lo, SDOperand &Hi);
160 /// SplitVectorOp - Given an operand of MVT::Vector type, break it down into
161 /// two smaller values of MVT::Vector type.
162 void SplitVectorOp(SDOperand O, SDOperand &Lo, SDOperand &Hi);
164 /// PackVectorOp - Given an operand of MVT::Vector type, convert it into the
165 /// equivalent operation that returns a packed value (e.g. MVT::V4F32). When
166 /// this is called, we know that PackedVT is the right type for the result and
167 /// we know that this type is legal for the target.
168 SDOperand PackVectorOp(SDOperand O, MVT::ValueType PackedVT);
170 /// isShuffleLegal - Return true if a vector shuffle is legal with the
171 /// specified mask and type. Targets can specify exactly which masks they
172 /// support and the code generator is tasked with not creating illegal masks.
174 /// Note that this will also return true for shuffles that are promoted to a
177 /// If this is a legal shuffle, this method returns the (possibly promoted)
178 /// build_vector Mask. If it's not a legal shuffle, it returns null.
179 SDNode *isShuffleLegal(MVT::ValueType VT, SDOperand Mask) const;
181 bool LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest,
182 std::set<SDNode*> &NodesLeadingTo);
184 void LegalizeSetCCOperands(SDOperand &LHS, SDOperand &RHS, SDOperand &CC);
186 SDOperand CreateStackTemporary(MVT::ValueType VT);
188 SDOperand ExpandLibCall(const char *Name, SDNode *Node,
190 SDOperand ExpandIntToFP(bool isSigned, MVT::ValueType DestTy,
193 SDOperand ExpandBIT_CONVERT(MVT::ValueType DestVT, SDOperand SrcOp);
194 SDOperand ExpandBUILD_VECTOR(SDNode *Node);
195 SDOperand ExpandSCALAR_TO_VECTOR(SDNode *Node);
196 SDOperand ExpandLegalINT_TO_FP(bool isSigned,
198 MVT::ValueType DestVT);
199 SDOperand PromoteLegalINT_TO_FP(SDOperand LegalOp, MVT::ValueType DestVT,
201 SDOperand PromoteLegalFP_TO_INT(SDOperand LegalOp, MVT::ValueType DestVT,
204 SDOperand ExpandBSWAP(SDOperand Op);
205 SDOperand ExpandBitCount(unsigned Opc, SDOperand Op);
206 bool ExpandShift(unsigned Opc, SDOperand Op, SDOperand Amt,
207 SDOperand &Lo, SDOperand &Hi);
208 void ExpandShiftParts(unsigned NodeOp, SDOperand Op, SDOperand Amt,
209 SDOperand &Lo, SDOperand &Hi);
211 SDOperand LowerVEXTRACT_VECTOR_ELT(SDOperand Op);
212 SDOperand ExpandEXTRACT_VECTOR_ELT(SDOperand Op);
214 SDOperand getIntPtrConstant(uint64_t Val) {
215 return DAG.getConstant(Val, TLI.getPointerTy());
220 /// isVectorShuffleLegal - Return true if a vector shuffle is legal with the
221 /// specified mask and type. Targets can specify exactly which masks they
222 /// support and the code generator is tasked with not creating illegal masks.
224 /// Note that this will also return true for shuffles that are promoted to a
226 SDNode *SelectionDAGLegalize::isShuffleLegal(MVT::ValueType VT,
227 SDOperand Mask) const {
228 switch (TLI.getOperationAction(ISD::VECTOR_SHUFFLE, VT)) {
230 case TargetLowering::Legal:
231 case TargetLowering::Custom:
233 case TargetLowering::Promote: {
234 // If this is promoted to a different type, convert the shuffle mask and
235 // ask if it is legal in the promoted type!
236 MVT::ValueType NVT = TLI.getTypeToPromoteTo(ISD::VECTOR_SHUFFLE, VT);
238 // If we changed # elements, change the shuffle mask.
239 unsigned NumEltsGrowth =
240 MVT::getVectorNumElements(NVT) / MVT::getVectorNumElements(VT);
241 assert(NumEltsGrowth && "Cannot promote to vector type with fewer elts!");
242 if (NumEltsGrowth > 1) {
243 // Renumber the elements.
244 SmallVector<SDOperand, 8> Ops;
245 for (unsigned i = 0, e = Mask.getNumOperands(); i != e; ++i) {
246 SDOperand InOp = Mask.getOperand(i);
247 for (unsigned j = 0; j != NumEltsGrowth; ++j) {
248 if (InOp.getOpcode() == ISD::UNDEF)
249 Ops.push_back(DAG.getNode(ISD::UNDEF, MVT::i32));
251 unsigned InEltNo = cast<ConstantSDNode>(InOp)->getValue();
252 Ops.push_back(DAG.getConstant(InEltNo*NumEltsGrowth+j, MVT::i32));
256 Mask = DAG.getNode(ISD::BUILD_VECTOR, NVT, &Ops[0], Ops.size());
262 return TLI.isShuffleMaskLegal(Mask, VT) ? Mask.Val : 0;
265 /// getScalarizedOpcode - Return the scalar opcode that corresponds to the
266 /// specified vector opcode.
267 static unsigned getScalarizedOpcode(unsigned VecOp, MVT::ValueType VT) {
269 default: assert(0 && "Don't know how to scalarize this opcode!");
270 case ISD::VADD: return MVT::isInteger(VT) ? ISD::ADD : ISD::FADD;
271 case ISD::VSUB: return MVT::isInteger(VT) ? ISD::SUB : ISD::FSUB;
272 case ISD::VMUL: return MVT::isInteger(VT) ? ISD::MUL : ISD::FMUL;
273 case ISD::VSDIV: return MVT::isInteger(VT) ? ISD::SDIV: ISD::FDIV;
274 case ISD::VUDIV: return MVT::isInteger(VT) ? ISD::UDIV: ISD::FDIV;
275 case ISD::VAND: return MVT::isInteger(VT) ? ISD::AND : 0;
276 case ISD::VOR: return MVT::isInteger(VT) ? ISD::OR : 0;
277 case ISD::VXOR: return MVT::isInteger(VT) ? ISD::XOR : 0;
281 SelectionDAGLegalize::SelectionDAGLegalize(SelectionDAG &dag)
282 : TLI(dag.getTargetLoweringInfo()), DAG(dag),
283 ValueTypeActions(TLI.getValueTypeActions()) {
284 assert(MVT::LAST_VALUETYPE <= 32 &&
285 "Too many value types for ValueTypeActions to hold!");
288 /// ComputeTopDownOrdering - Add the specified node to the Order list if it has
289 /// not been visited yet and if all of its operands have already been visited.
290 static void ComputeTopDownOrdering(SDNode *N, std::vector<SDNode*> &Order,
291 std::map<SDNode*, unsigned> &Visited) {
292 if (++Visited[N] != N->getNumOperands())
293 return; // Haven't visited all operands yet
297 if (N->hasOneUse()) { // Tail recurse in common case.
298 ComputeTopDownOrdering(*N->use_begin(), Order, Visited);
302 // Now that we have N in, add anything that uses it if all of their operands
304 for (SDNode::use_iterator UI = N->use_begin(), E = N->use_end(); UI != E;++UI)
305 ComputeTopDownOrdering(*UI, Order, Visited);
309 void SelectionDAGLegalize::LegalizeDAG() {
310 LastCALLSEQ_END = DAG.getEntryNode();
311 IsLegalizingCall = false;
313 // The legalize process is inherently a bottom-up recursive process (users
314 // legalize their uses before themselves). Given infinite stack space, we
315 // could just start legalizing on the root and traverse the whole graph. In
316 // practice however, this causes us to run out of stack space on large basic
317 // blocks. To avoid this problem, compute an ordering of the nodes where each
318 // node is only legalized after all of its operands are legalized.
319 std::map<SDNode*, unsigned> Visited;
320 std::vector<SDNode*> Order;
322 // Compute ordering from all of the leaves in the graphs, those (like the
323 // entry node) that have no operands.
324 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(),
325 E = DAG.allnodes_end(); I != E; ++I) {
326 if (I->getNumOperands() == 0) {
328 ComputeTopDownOrdering(I, Order, Visited);
332 assert(Order.size() == Visited.size() &&
334 (unsigned)std::distance(DAG.allnodes_begin(), DAG.allnodes_end()) &&
335 "Error: DAG is cyclic!");
338 for (unsigned i = 0, e = Order.size(); i != e; ++i)
339 HandleOp(SDOperand(Order[i], 0));
341 // Finally, it's possible the root changed. Get the new root.
342 SDOperand OldRoot = DAG.getRoot();
343 assert(LegalizedNodes.count(OldRoot) && "Root didn't get legalized?");
344 DAG.setRoot(LegalizedNodes[OldRoot]);
346 ExpandedNodes.clear();
347 LegalizedNodes.clear();
348 PromotedNodes.clear();
352 // Remove dead nodes now.
353 DAG.RemoveDeadNodes();
357 /// FindCallEndFromCallStart - Given a chained node that is part of a call
358 /// sequence, find the CALLSEQ_END node that terminates the call sequence.
359 static SDNode *FindCallEndFromCallStart(SDNode *Node) {
360 if (Node->getOpcode() == ISD::CALLSEQ_END)
362 if (Node->use_empty())
363 return 0; // No CallSeqEnd
365 // The chain is usually at the end.
366 SDOperand TheChain(Node, Node->getNumValues()-1);
367 if (TheChain.getValueType() != MVT::Other) {
368 // Sometimes it's at the beginning.
369 TheChain = SDOperand(Node, 0);
370 if (TheChain.getValueType() != MVT::Other) {
371 // Otherwise, hunt for it.
372 for (unsigned i = 1, e = Node->getNumValues(); i != e; ++i)
373 if (Node->getValueType(i) == MVT::Other) {
374 TheChain = SDOperand(Node, i);
378 // Otherwise, we walked into a node without a chain.
379 if (TheChain.getValueType() != MVT::Other)
384 for (SDNode::use_iterator UI = Node->use_begin(),
385 E = Node->use_end(); UI != E; ++UI) {
387 // Make sure to only follow users of our token chain.
389 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i)
390 if (User->getOperand(i) == TheChain)
391 if (SDNode *Result = FindCallEndFromCallStart(User))
397 /// FindCallStartFromCallEnd - Given a chained node that is part of a call
398 /// sequence, find the CALLSEQ_START node that initiates the call sequence.
399 static SDNode *FindCallStartFromCallEnd(SDNode *Node) {
400 assert(Node && "Didn't find callseq_start for a call??");
401 if (Node->getOpcode() == ISD::CALLSEQ_START) return Node;
403 assert(Node->getOperand(0).getValueType() == MVT::Other &&
404 "Node doesn't have a token chain argument!");
405 return FindCallStartFromCallEnd(Node->getOperand(0).Val);
408 /// LegalizeAllNodesNotLeadingTo - Recursively walk the uses of N, looking to
409 /// see if any uses can reach Dest. If no dest operands can get to dest,
410 /// legalize them, legalize ourself, and return false, otherwise, return true.
412 /// Keep track of the nodes we fine that actually do lead to Dest in
413 /// NodesLeadingTo. This avoids retraversing them exponential number of times.
415 bool SelectionDAGLegalize::LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest,
416 std::set<SDNode*> &NodesLeadingTo) {
417 if (N == Dest) return true; // N certainly leads to Dest :)
419 // If we've already processed this node and it does lead to Dest, there is no
420 // need to reprocess it.
421 if (NodesLeadingTo.count(N)) return true;
423 // If the first result of this node has been already legalized, then it cannot
425 switch (getTypeAction(N->getValueType(0))) {
427 if (LegalizedNodes.count(SDOperand(N, 0))) return false;
430 if (PromotedNodes.count(SDOperand(N, 0))) return false;
433 if (ExpandedNodes.count(SDOperand(N, 0))) return false;
437 // Okay, this node has not already been legalized. Check and legalize all
438 // operands. If none lead to Dest, then we can legalize this node.
439 bool OperandsLeadToDest = false;
440 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
441 OperandsLeadToDest |= // If an operand leads to Dest, so do we.
442 LegalizeAllNodesNotLeadingTo(N->getOperand(i).Val, Dest, NodesLeadingTo);
444 if (OperandsLeadToDest) {
445 NodesLeadingTo.insert(N);
449 // Okay, this node looks safe, legalize it and return false.
450 HandleOp(SDOperand(N, 0));
454 /// HandleOp - Legalize, Promote, Expand or Pack the specified operand as
455 /// appropriate for its type.
456 void SelectionDAGLegalize::HandleOp(SDOperand Op) {
457 switch (getTypeAction(Op.getValueType())) {
458 default: assert(0 && "Bad type action!");
459 case Legal: LegalizeOp(Op); break;
460 case Promote: PromoteOp(Op); break;
462 if (Op.getValueType() != MVT::Vector) {
467 unsigned NumOps = N->getNumOperands();
468 unsigned NumElements =
469 cast<ConstantSDNode>(N->getOperand(NumOps-2))->getValue();
470 MVT::ValueType EVT = cast<VTSDNode>(N->getOperand(NumOps-1))->getVT();
471 MVT::ValueType PackedVT = getVectorType(EVT, NumElements);
472 if (PackedVT != MVT::Other && TLI.isTypeLegal(PackedVT)) {
473 // In the common case, this is a legal vector type, convert it to the
474 // packed operation and type now.
475 PackVectorOp(Op, PackedVT);
476 } else if (NumElements == 1) {
477 // Otherwise, if this is a single element vector, convert it to a
479 PackVectorOp(Op, EVT);
481 // Otherwise, this is a multiple element vector that isn't supported.
482 // Split it in half and legalize both parts.
484 SplitVectorOp(Op, X, Y);
492 /// LegalizeOp - We know that the specified value has a legal type.
493 /// Recursively ensure that the operands have legal types, then return the
495 SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
496 assert(isTypeLegal(Op.getValueType()) &&
497 "Caller should expand or promote operands that are not legal!");
498 SDNode *Node = Op.Val;
500 // If this operation defines any values that cannot be represented in a
501 // register on this target, make sure to expand or promote them.
502 if (Node->getNumValues() > 1) {
503 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
504 if (getTypeAction(Node->getValueType(i)) != Legal) {
505 HandleOp(Op.getValue(i));
506 assert(LegalizedNodes.count(Op) &&
507 "Handling didn't add legal operands!");
508 return LegalizedNodes[Op];
512 // Note that LegalizeOp may be reentered even from single-use nodes, which
513 // means that we always must cache transformed nodes.
514 std::map<SDOperand, SDOperand>::iterator I = LegalizedNodes.find(Op);
515 if (I != LegalizedNodes.end()) return I->second;
517 SDOperand Tmp1, Tmp2, Tmp3, Tmp4;
518 SDOperand Result = Op;
519 bool isCustom = false;
521 switch (Node->getOpcode()) {
522 case ISD::FrameIndex:
523 case ISD::EntryToken:
525 case ISD::BasicBlock:
526 case ISD::TargetFrameIndex:
527 case ISD::TargetJumpTable:
528 case ISD::TargetConstant:
529 case ISD::TargetConstantFP:
530 case ISD::TargetConstantPool:
531 case ISD::TargetGlobalAddress:
532 case ISD::TargetExternalSymbol:
537 case ISD::GLOBAL_OFFSET_TABLE:
538 // Primitives must all be legal.
539 assert(TLI.isOperationLegal(Node->getValueType(0), Node->getValueType(0)) &&
540 "This must be legal!");
543 if (Node->getOpcode() >= ISD::BUILTIN_OP_END) {
544 // If this is a target node, legalize it by legalizing the operands then
545 // passing it through.
546 SmallVector<SDOperand, 8> Ops;
547 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
548 Ops.push_back(LegalizeOp(Node->getOperand(i)));
550 Result = DAG.UpdateNodeOperands(Result.getValue(0), &Ops[0], Ops.size());
552 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
553 AddLegalizedOperand(Op.getValue(i), Result.getValue(i));
554 return Result.getValue(Op.ResNo);
556 // Otherwise this is an unhandled builtin node. splat.
558 cerr << "NODE: "; Node->dump(); cerr << "\n";
560 assert(0 && "Do not know how to legalize this operator!");
562 case ISD::GlobalAddress:
563 case ISD::ExternalSymbol:
564 case ISD::ConstantPool:
565 case ISD::JumpTable: // Nothing to do.
566 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
567 default: assert(0 && "This action is not supported yet!");
568 case TargetLowering::Custom:
569 Tmp1 = TLI.LowerOperation(Op, DAG);
570 if (Tmp1.Val) Result = Tmp1;
571 // FALLTHROUGH if the target doesn't want to lower this op after all.
572 case TargetLowering::Legal:
576 case ISD::AssertSext:
577 case ISD::AssertZext:
578 Tmp1 = LegalizeOp(Node->getOperand(0));
579 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
581 case ISD::MERGE_VALUES:
582 // Legalize eliminates MERGE_VALUES nodes.
583 Result = Node->getOperand(Op.ResNo);
585 case ISD::CopyFromReg:
586 Tmp1 = LegalizeOp(Node->getOperand(0));
587 Result = Op.getValue(0);
588 if (Node->getNumValues() == 2) {
589 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
591 assert(Node->getNumValues() == 3 && "Invalid copyfromreg!");
592 if (Node->getNumOperands() == 3) {
593 Tmp2 = LegalizeOp(Node->getOperand(2));
594 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1),Tmp2);
596 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
598 AddLegalizedOperand(Op.getValue(2), Result.getValue(2));
600 // Since CopyFromReg produces two values, make sure to remember that we
601 // legalized both of them.
602 AddLegalizedOperand(Op.getValue(0), Result);
603 AddLegalizedOperand(Op.getValue(1), Result.getValue(1));
604 return Result.getValue(Op.ResNo);
606 MVT::ValueType VT = Op.getValueType();
607 switch (TLI.getOperationAction(ISD::UNDEF, VT)) {
608 default: assert(0 && "This action is not supported yet!");
609 case TargetLowering::Expand:
610 if (MVT::isInteger(VT))
611 Result = DAG.getConstant(0, VT);
612 else if (MVT::isFloatingPoint(VT))
613 Result = DAG.getConstantFP(0, VT);
615 assert(0 && "Unknown value type!");
617 case TargetLowering::Legal:
623 case ISD::INTRINSIC_W_CHAIN:
624 case ISD::INTRINSIC_WO_CHAIN:
625 case ISD::INTRINSIC_VOID: {
626 SmallVector<SDOperand, 8> Ops;
627 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
628 Ops.push_back(LegalizeOp(Node->getOperand(i)));
629 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
631 // Allow the target to custom lower its intrinsics if it wants to.
632 if (TLI.getOperationAction(Node->getOpcode(), MVT::Other) ==
633 TargetLowering::Custom) {
634 Tmp3 = TLI.LowerOperation(Result, DAG);
635 if (Tmp3.Val) Result = Tmp3;
638 if (Result.Val->getNumValues() == 1) break;
640 // Must have return value and chain result.
641 assert(Result.Val->getNumValues() == 2 &&
642 "Cannot return more than two values!");
644 // Since loads produce two values, make sure to remember that we
645 // legalized both of them.
646 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
647 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
648 return Result.getValue(Op.ResNo);
652 assert(Node->getNumOperands() == 5 && "Invalid LOCATION node!");
653 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the input chain.
655 switch (TLI.getOperationAction(ISD::LOCATION, MVT::Other)) {
656 case TargetLowering::Promote:
657 default: assert(0 && "This action is not supported yet!");
658 case TargetLowering::Expand: {
659 MachineDebugInfo *DebugInfo = DAG.getMachineDebugInfo();
660 bool useDEBUG_LOC = TLI.isOperationLegal(ISD::DEBUG_LOC, MVT::Other);
661 bool useDEBUG_LABEL = TLI.isOperationLegal(ISD::DEBUG_LABEL, MVT::Other);
663 if (DebugInfo && (useDEBUG_LOC || useDEBUG_LABEL)) {
664 const std::string &FName =
665 cast<StringSDNode>(Node->getOperand(3))->getValue();
666 const std::string &DirName =
667 cast<StringSDNode>(Node->getOperand(4))->getValue();
668 unsigned SrcFile = DebugInfo->RecordSource(DirName, FName);
670 SmallVector<SDOperand, 8> Ops;
671 Ops.push_back(Tmp1); // chain
672 SDOperand LineOp = Node->getOperand(1);
673 SDOperand ColOp = Node->getOperand(2);
676 Ops.push_back(LineOp); // line #
677 Ops.push_back(ColOp); // col #
678 Ops.push_back(DAG.getConstant(SrcFile, MVT::i32)); // source file id
679 Result = DAG.getNode(ISD::DEBUG_LOC, MVT::Other, &Ops[0], Ops.size());
681 unsigned Line = cast<ConstantSDNode>(LineOp)->getValue();
682 unsigned Col = cast<ConstantSDNode>(ColOp)->getValue();
683 unsigned ID = DebugInfo->RecordLabel(Line, Col, SrcFile);
684 Ops.push_back(DAG.getConstant(ID, MVT::i32));
685 Result = DAG.getNode(ISD::DEBUG_LABEL, MVT::Other,&Ops[0],Ops.size());
688 Result = Tmp1; // chain
692 case TargetLowering::Legal:
693 if (Tmp1 != Node->getOperand(0) ||
694 getTypeAction(Node->getOperand(1).getValueType()) == Promote) {
695 SmallVector<SDOperand, 8> Ops;
697 if (getTypeAction(Node->getOperand(1).getValueType()) == Legal) {
698 Ops.push_back(Node->getOperand(1)); // line # must be legal.
699 Ops.push_back(Node->getOperand(2)); // col # must be legal.
701 // Otherwise promote them.
702 Ops.push_back(PromoteOp(Node->getOperand(1)));
703 Ops.push_back(PromoteOp(Node->getOperand(2)));
705 Ops.push_back(Node->getOperand(3)); // filename must be legal.
706 Ops.push_back(Node->getOperand(4)); // working dir # must be legal.
707 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
714 assert(Node->getNumOperands() == 4 && "Invalid DEBUG_LOC node!");
715 switch (TLI.getOperationAction(ISD::DEBUG_LOC, MVT::Other)) {
716 default: assert(0 && "This action is not supported yet!");
717 case TargetLowering::Legal:
718 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
719 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the line #.
720 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the col #.
721 Tmp4 = LegalizeOp(Node->getOperand(3)); // Legalize the source file id.
722 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4);
727 case ISD::DEBUG_LABEL:
728 assert(Node->getNumOperands() == 2 && "Invalid DEBUG_LABEL node!");
729 switch (TLI.getOperationAction(ISD::DEBUG_LABEL, MVT::Other)) {
730 default: assert(0 && "This action is not supported yet!");
731 case TargetLowering::Legal:
732 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
733 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the label id.
734 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
740 // We know we don't need to expand constants here, constants only have one
741 // value and we check that it is fine above.
743 // FIXME: Maybe we should handle things like targets that don't support full
744 // 32-bit immediates?
746 case ISD::ConstantFP: {
747 // Spill FP immediates to the constant pool if the target cannot directly
748 // codegen them. Targets often have some immediate values that can be
749 // efficiently generated into an FP register without a load. We explicitly
750 // leave these constants as ConstantFP nodes for the target to deal with.
751 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node);
753 // Check to see if this FP immediate is already legal.
754 bool isLegal = false;
755 for (TargetLowering::legal_fpimm_iterator I = TLI.legal_fpimm_begin(),
756 E = TLI.legal_fpimm_end(); I != E; ++I)
757 if (CFP->isExactlyValue(*I)) {
762 // If this is a legal constant, turn it into a TargetConstantFP node.
764 Result = DAG.getTargetConstantFP(CFP->getValue(), CFP->getValueType(0));
768 switch (TLI.getOperationAction(ISD::ConstantFP, CFP->getValueType(0))) {
769 default: assert(0 && "This action is not supported yet!");
770 case TargetLowering::Custom:
771 Tmp3 = TLI.LowerOperation(Result, DAG);
777 case TargetLowering::Expand:
778 // Otherwise we need to spill the constant to memory.
781 // If a FP immediate is precise when represented as a float and if the
782 // target can do an extending load from float to double, we put it into
783 // the constant pool as a float, even if it's is statically typed as a
785 MVT::ValueType VT = CFP->getValueType(0);
786 bool isDouble = VT == MVT::f64;
787 ConstantFP *LLVMC = ConstantFP::get(isDouble ? Type::DoubleTy :
788 Type::FloatTy, CFP->getValue());
789 if (isDouble && CFP->isExactlyValue((float)CFP->getValue()) &&
790 // Only do this if the target has a native EXTLOAD instruction from
792 TLI.isLoadXLegal(ISD::EXTLOAD, MVT::f32)) {
793 LLVMC = cast<ConstantFP>(ConstantExpr::getFPTrunc(LLVMC,Type::FloatTy));
798 SDOperand CPIdx = DAG.getConstantPool(LLVMC, TLI.getPointerTy());
800 Result = DAG.getExtLoad(ISD::EXTLOAD, MVT::f64, DAG.getEntryNode(),
801 CPIdx, NULL, 0, MVT::f32);
803 Result = DAG.getLoad(VT, DAG.getEntryNode(), CPIdx, NULL, 0);
808 case ISD::TokenFactor:
809 if (Node->getNumOperands() == 2) {
810 Tmp1 = LegalizeOp(Node->getOperand(0));
811 Tmp2 = LegalizeOp(Node->getOperand(1));
812 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
813 } else if (Node->getNumOperands() == 3) {
814 Tmp1 = LegalizeOp(Node->getOperand(0));
815 Tmp2 = LegalizeOp(Node->getOperand(1));
816 Tmp3 = LegalizeOp(Node->getOperand(2));
817 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
819 SmallVector<SDOperand, 8> Ops;
820 // Legalize the operands.
821 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
822 Ops.push_back(LegalizeOp(Node->getOperand(i)));
823 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
827 case ISD::FORMAL_ARGUMENTS:
829 // The only option for this is to custom lower it.
830 Tmp3 = TLI.LowerOperation(Result.getValue(0), DAG);
831 assert(Tmp3.Val && "Target didn't custom lower this node!");
832 assert(Tmp3.Val->getNumValues() == Result.Val->getNumValues() &&
833 "Lowering call/formal_arguments produced unexpected # results!");
835 // Since CALL/FORMAL_ARGUMENTS nodes produce multiple values, make sure to
836 // remember that we legalized all of them, so it doesn't get relegalized.
837 for (unsigned i = 0, e = Tmp3.Val->getNumValues(); i != e; ++i) {
838 Tmp1 = LegalizeOp(Tmp3.getValue(i));
841 AddLegalizedOperand(SDOperand(Node, i), Tmp1);
845 case ISD::BUILD_VECTOR:
846 switch (TLI.getOperationAction(ISD::BUILD_VECTOR, Node->getValueType(0))) {
847 default: assert(0 && "This action is not supported yet!");
848 case TargetLowering::Custom:
849 Tmp3 = TLI.LowerOperation(Result, DAG);
855 case TargetLowering::Expand:
856 Result = ExpandBUILD_VECTOR(Result.Val);
860 case ISD::INSERT_VECTOR_ELT:
861 Tmp1 = LegalizeOp(Node->getOperand(0)); // InVec
862 Tmp2 = LegalizeOp(Node->getOperand(1)); // InVal
863 Tmp3 = LegalizeOp(Node->getOperand(2)); // InEltNo
864 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
866 switch (TLI.getOperationAction(ISD::INSERT_VECTOR_ELT,
867 Node->getValueType(0))) {
868 default: assert(0 && "This action is not supported yet!");
869 case TargetLowering::Legal:
871 case TargetLowering::Custom:
872 Tmp3 = TLI.LowerOperation(Result, DAG);
878 case TargetLowering::Expand: {
879 // If the insert index is a constant, codegen this as a scalar_to_vector,
880 // then a shuffle that inserts it into the right position in the vector.
881 if (ConstantSDNode *InsertPos = dyn_cast<ConstantSDNode>(Tmp3)) {
882 SDOperand ScVec = DAG.getNode(ISD::SCALAR_TO_VECTOR,
883 Tmp1.getValueType(), Tmp2);
885 unsigned NumElts = MVT::getVectorNumElements(Tmp1.getValueType());
886 MVT::ValueType ShufMaskVT = MVT::getIntVectorWithNumElements(NumElts);
887 MVT::ValueType ShufMaskEltVT = MVT::getVectorBaseType(ShufMaskVT);
889 // We generate a shuffle of InVec and ScVec, so the shuffle mask should
890 // be 0,1,2,3,4,5... with the appropriate element replaced with elt 0 of
892 SmallVector<SDOperand, 8> ShufOps;
893 for (unsigned i = 0; i != NumElts; ++i) {
894 if (i != InsertPos->getValue())
895 ShufOps.push_back(DAG.getConstant(i, ShufMaskEltVT));
897 ShufOps.push_back(DAG.getConstant(NumElts, ShufMaskEltVT));
899 SDOperand ShufMask = DAG.getNode(ISD::BUILD_VECTOR, ShufMaskVT,
900 &ShufOps[0], ShufOps.size());
902 Result = DAG.getNode(ISD::VECTOR_SHUFFLE, Tmp1.getValueType(),
903 Tmp1, ScVec, ShufMask);
904 Result = LegalizeOp(Result);
908 // If the target doesn't support this, we have to spill the input vector
909 // to a temporary stack slot, update the element, then reload it. This is
910 // badness. We could also load the value into a vector register (either
911 // with a "move to register" or "extload into register" instruction, then
912 // permute it into place, if the idx is a constant and if the idx is
913 // supported by the target.
914 MVT::ValueType VT = Tmp1.getValueType();
915 MVT::ValueType EltVT = Tmp2.getValueType();
916 MVT::ValueType IdxVT = Tmp3.getValueType();
917 MVT::ValueType PtrVT = TLI.getPointerTy();
918 SDOperand StackPtr = CreateStackTemporary(VT);
920 SDOperand Ch = DAG.getStore(DAG.getEntryNode(), Tmp1, StackPtr, NULL, 0);
922 // Truncate or zero extend offset to target pointer type.
923 unsigned CastOpc = (IdxVT > PtrVT) ? ISD::TRUNCATE : ISD::ZERO_EXTEND;
924 Tmp3 = DAG.getNode(CastOpc, PtrVT, Tmp3);
925 // Add the offset to the index.
926 unsigned EltSize = MVT::getSizeInBits(EltVT)/8;
927 Tmp3 = DAG.getNode(ISD::MUL, IdxVT, Tmp3,DAG.getConstant(EltSize, IdxVT));
928 SDOperand StackPtr2 = DAG.getNode(ISD::ADD, IdxVT, Tmp3, StackPtr);
929 // Store the scalar value.
930 Ch = DAG.getStore(Ch, Tmp2, StackPtr2, NULL, 0);
931 // Load the updated vector.
932 Result = DAG.getLoad(VT, Ch, StackPtr, NULL, 0);
937 case ISD::SCALAR_TO_VECTOR:
938 if (!TLI.isTypeLegal(Node->getOperand(0).getValueType())) {
939 Result = LegalizeOp(ExpandSCALAR_TO_VECTOR(Node));
943 Tmp1 = LegalizeOp(Node->getOperand(0)); // InVal
944 Result = DAG.UpdateNodeOperands(Result, Tmp1);
945 switch (TLI.getOperationAction(ISD::SCALAR_TO_VECTOR,
946 Node->getValueType(0))) {
947 default: assert(0 && "This action is not supported yet!");
948 case TargetLowering::Legal:
950 case TargetLowering::Custom:
951 Tmp3 = TLI.LowerOperation(Result, DAG);
957 case TargetLowering::Expand:
958 Result = LegalizeOp(ExpandSCALAR_TO_VECTOR(Node));
962 case ISD::VECTOR_SHUFFLE:
963 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the input vectors,
964 Tmp2 = LegalizeOp(Node->getOperand(1)); // but not the shuffle mask.
965 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
967 // Allow targets to custom lower the SHUFFLEs they support.
968 switch (TLI.getOperationAction(ISD::VECTOR_SHUFFLE,Result.getValueType())) {
969 default: assert(0 && "Unknown operation action!");
970 case TargetLowering::Legal:
971 assert(isShuffleLegal(Result.getValueType(), Node->getOperand(2)) &&
972 "vector shuffle should not be created if not legal!");
974 case TargetLowering::Custom:
975 Tmp3 = TLI.LowerOperation(Result, DAG);
981 case TargetLowering::Expand: {
982 MVT::ValueType VT = Node->getValueType(0);
983 MVT::ValueType EltVT = MVT::getVectorBaseType(VT);
984 MVT::ValueType PtrVT = TLI.getPointerTy();
985 SDOperand Mask = Node->getOperand(2);
986 unsigned NumElems = Mask.getNumOperands();
987 SmallVector<SDOperand,8> Ops;
988 for (unsigned i = 0; i != NumElems; ++i) {
989 SDOperand Arg = Mask.getOperand(i);
990 if (Arg.getOpcode() == ISD::UNDEF) {
991 Ops.push_back(DAG.getNode(ISD::UNDEF, EltVT));
993 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
994 unsigned Idx = cast<ConstantSDNode>(Arg)->getValue();
996 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, Tmp1,
997 DAG.getConstant(Idx, PtrVT)));
999 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, Tmp2,
1000 DAG.getConstant(Idx - NumElems, PtrVT)));
1003 Result = DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size());
1006 case TargetLowering::Promote: {
1007 // Change base type to a different vector type.
1008 MVT::ValueType OVT = Node->getValueType(0);
1009 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
1011 // Cast the two input vectors.
1012 Tmp1 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp1);
1013 Tmp2 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp2);
1015 // Convert the shuffle mask to the right # elements.
1016 Tmp3 = SDOperand(isShuffleLegal(OVT, Node->getOperand(2)), 0);
1017 assert(Tmp3.Val && "Shuffle not legal?");
1018 Result = DAG.getNode(ISD::VECTOR_SHUFFLE, NVT, Tmp1, Tmp2, Tmp3);
1019 Result = DAG.getNode(ISD::BIT_CONVERT, OVT, Result);
1025 case ISD::EXTRACT_VECTOR_ELT:
1026 Tmp1 = LegalizeOp(Node->getOperand(0));
1027 Tmp2 = LegalizeOp(Node->getOperand(1));
1028 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1030 switch (TLI.getOperationAction(ISD::EXTRACT_VECTOR_ELT,
1031 Tmp1.getValueType())) {
1032 default: assert(0 && "This action is not supported yet!");
1033 case TargetLowering::Legal:
1035 case TargetLowering::Custom:
1036 Tmp3 = TLI.LowerOperation(Result, DAG);
1042 case TargetLowering::Expand:
1043 Result = ExpandEXTRACT_VECTOR_ELT(Result);
1048 case ISD::VEXTRACT_VECTOR_ELT:
1049 Result = LegalizeOp(LowerVEXTRACT_VECTOR_ELT(Op));
1052 case ISD::CALLSEQ_START: {
1053 SDNode *CallEnd = FindCallEndFromCallStart(Node);
1055 // Recursively Legalize all of the inputs of the call end that do not lead
1056 // to this call start. This ensures that any libcalls that need be inserted
1057 // are inserted *before* the CALLSEQ_START.
1058 {std::set<SDNode*> NodesLeadingTo;
1059 for (unsigned i = 0, e = CallEnd->getNumOperands(); i != e; ++i)
1060 LegalizeAllNodesNotLeadingTo(CallEnd->getOperand(i).Val, Node,
1064 // Now that we legalized all of the inputs (which may have inserted
1065 // libcalls) create the new CALLSEQ_START node.
1066 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1068 // Merge in the last call, to ensure that this call start after the last
1070 if (LastCALLSEQ_END.getOpcode() != ISD::EntryToken) {
1071 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1072 Tmp1 = LegalizeOp(Tmp1);
1075 // Do not try to legalize the target-specific arguments (#1+).
1076 if (Tmp1 != Node->getOperand(0)) {
1077 SmallVector<SDOperand, 8> Ops(Node->op_begin(), Node->op_end());
1079 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1082 // Remember that the CALLSEQ_START is legalized.
1083 AddLegalizedOperand(Op.getValue(0), Result);
1084 if (Node->getNumValues() == 2) // If this has a flag result, remember it.
1085 AddLegalizedOperand(Op.getValue(1), Result.getValue(1));
1087 // Now that the callseq_start and all of the non-call nodes above this call
1088 // sequence have been legalized, legalize the call itself. During this
1089 // process, no libcalls can/will be inserted, guaranteeing that no calls
1091 assert(!IsLegalizingCall && "Inconsistent sequentialization of calls!");
1092 SDOperand InCallSEQ = LastCALLSEQ_END;
1093 // Note that we are selecting this call!
1094 LastCALLSEQ_END = SDOperand(CallEnd, 0);
1095 IsLegalizingCall = true;
1097 // Legalize the call, starting from the CALLSEQ_END.
1098 LegalizeOp(LastCALLSEQ_END);
1099 assert(!IsLegalizingCall && "CALLSEQ_END should have cleared this!");
1102 case ISD::CALLSEQ_END:
1103 // If the CALLSEQ_START node hasn't been legalized first, legalize it. This
1104 // will cause this node to be legalized as well as handling libcalls right.
1105 if (LastCALLSEQ_END.Val != Node) {
1106 LegalizeOp(SDOperand(FindCallStartFromCallEnd(Node), 0));
1107 std::map<SDOperand, SDOperand>::iterator I = LegalizedNodes.find(Op);
1108 assert(I != LegalizedNodes.end() &&
1109 "Legalizing the call start should have legalized this node!");
1113 // Otherwise, the call start has been legalized and everything is going
1114 // according to plan. Just legalize ourselves normally here.
1115 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1116 // Do not try to legalize the target-specific arguments (#1+), except for
1117 // an optional flag input.
1118 if (Node->getOperand(Node->getNumOperands()-1).getValueType() != MVT::Flag){
1119 if (Tmp1 != Node->getOperand(0)) {
1120 SmallVector<SDOperand, 8> Ops(Node->op_begin(), Node->op_end());
1122 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1125 Tmp2 = LegalizeOp(Node->getOperand(Node->getNumOperands()-1));
1126 if (Tmp1 != Node->getOperand(0) ||
1127 Tmp2 != Node->getOperand(Node->getNumOperands()-1)) {
1128 SmallVector<SDOperand, 8> Ops(Node->op_begin(), Node->op_end());
1131 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1134 assert(IsLegalizingCall && "Call sequence imbalance between start/end?");
1135 // This finishes up call legalization.
1136 IsLegalizingCall = false;
1138 // If the CALLSEQ_END node has a flag, remember that we legalized it.
1139 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
1140 if (Node->getNumValues() == 2)
1141 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
1142 return Result.getValue(Op.ResNo);
1143 case ISD::DYNAMIC_STACKALLOC: {
1144 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1145 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the size.
1146 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the alignment.
1147 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1149 Tmp1 = Result.getValue(0);
1150 Tmp2 = Result.getValue(1);
1151 switch (TLI.getOperationAction(Node->getOpcode(),
1152 Node->getValueType(0))) {
1153 default: assert(0 && "This action is not supported yet!");
1154 case TargetLowering::Expand: {
1155 unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore();
1156 assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and"
1157 " not tell us which reg is the stack pointer!");
1158 SDOperand Chain = Tmp1.getOperand(0);
1159 SDOperand Size = Tmp2.getOperand(1);
1160 SDOperand SP = DAG.getCopyFromReg(Chain, SPReg, Node->getValueType(0));
1161 Tmp1 = DAG.getNode(ISD::SUB, Node->getValueType(0), SP, Size); // Value
1162 Tmp2 = DAG.getCopyToReg(SP.getValue(1), SPReg, Tmp1); // Output chain
1163 Tmp1 = LegalizeOp(Tmp1);
1164 Tmp2 = LegalizeOp(Tmp2);
1167 case TargetLowering::Custom:
1168 Tmp3 = TLI.LowerOperation(Tmp1, DAG);
1170 Tmp1 = LegalizeOp(Tmp3);
1171 Tmp2 = LegalizeOp(Tmp3.getValue(1));
1174 case TargetLowering::Legal:
1177 // Since this op produce two values, make sure to remember that we
1178 // legalized both of them.
1179 AddLegalizedOperand(SDOperand(Node, 0), Tmp1);
1180 AddLegalizedOperand(SDOperand(Node, 1), Tmp2);
1181 return Op.ResNo ? Tmp2 : Tmp1;
1183 case ISD::INLINEASM: {
1184 SmallVector<SDOperand, 8> Ops(Node->op_begin(), Node->op_end());
1185 bool Changed = false;
1186 // Legalize all of the operands of the inline asm, in case they are nodes
1187 // that need to be expanded or something. Note we skip the asm string and
1188 // all of the TargetConstant flags.
1189 SDOperand Op = LegalizeOp(Ops[0]);
1190 Changed = Op != Ops[0];
1193 bool HasInFlag = Ops.back().getValueType() == MVT::Flag;
1194 for (unsigned i = 2, e = Ops.size()-HasInFlag; i < e; ) {
1195 unsigned NumVals = cast<ConstantSDNode>(Ops[i])->getValue() >> 3;
1196 for (++i; NumVals; ++i, --NumVals) {
1197 SDOperand Op = LegalizeOp(Ops[i]);
1206 Op = LegalizeOp(Ops.back());
1207 Changed |= Op != Ops.back();
1212 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1214 // INLINE asm returns a chain and flag, make sure to add both to the map.
1215 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
1216 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
1217 return Result.getValue(Op.ResNo);
1220 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1221 // Ensure that libcalls are emitted before a branch.
1222 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1223 Tmp1 = LegalizeOp(Tmp1);
1224 LastCALLSEQ_END = DAG.getEntryNode();
1226 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
1229 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1230 // Ensure that libcalls are emitted before a branch.
1231 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1232 Tmp1 = LegalizeOp(Tmp1);
1233 LastCALLSEQ_END = DAG.getEntryNode();
1235 switch (getTypeAction(Node->getOperand(1).getValueType())) {
1236 default: assert(0 && "Indirect target must be legal type (pointer)!");
1238 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the condition.
1241 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1244 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1245 // Ensure that libcalls are emitted before a branch.
1246 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1247 Tmp1 = LegalizeOp(Tmp1);
1248 LastCALLSEQ_END = DAG.getEntryNode();
1250 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the jumptable node.
1251 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
1253 switch (TLI.getOperationAction(ISD::BR_JT, MVT::Other)) {
1254 default: assert(0 && "This action is not supported yet!");
1255 case TargetLowering::Legal: break;
1256 case TargetLowering::Custom:
1257 Tmp1 = TLI.LowerOperation(Result, DAG);
1258 if (Tmp1.Val) Result = Tmp1;
1260 case TargetLowering::Expand: {
1261 SDOperand Chain = Result.getOperand(0);
1262 SDOperand Table = Result.getOperand(1);
1263 SDOperand Index = Result.getOperand(2);
1265 MVT::ValueType PTy = TLI.getPointerTy();
1266 bool isPIC = TLI.getTargetMachine().getRelocationModel() == Reloc::PIC_;
1267 // PIC jump table entries are 32-bit values.
1268 unsigned EntrySize = isPIC ? 4 : MVT::getSizeInBits(PTy)/8;
1269 Index= DAG.getNode(ISD::MUL, PTy, Index, DAG.getConstant(EntrySize, PTy));
1270 SDOperand Addr = DAG.getNode(ISD::ADD, PTy, Index, Table);
1271 SDOperand LD = DAG.getLoad(isPIC ? MVT::i32 : PTy, Chain, Addr, NULL, 0);
1273 // For PIC, the sequence is:
1274 // BRIND(load(Jumptable + index) + RelocBase)
1275 // RelocBase is the JumpTable on PPC and X86, GOT on Alpha
1277 if (TLI.usesGlobalOffsetTable())
1278 Reloc = DAG.getNode(ISD::GLOBAL_OFFSET_TABLE, PTy);
1281 Addr = (PTy != MVT::i32) ? DAG.getNode(ISD::SIGN_EXTEND, PTy, LD) : LD;
1282 Addr = DAG.getNode(ISD::ADD, PTy, Addr, Reloc);
1283 Result = DAG.getNode(ISD::BRIND, MVT::Other, LD.getValue(1), Addr);
1285 Result = DAG.getNode(ISD::BRIND, MVT::Other, LD.getValue(1), LD);
1291 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1292 // Ensure that libcalls are emitted before a return.
1293 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1294 Tmp1 = LegalizeOp(Tmp1);
1295 LastCALLSEQ_END = DAG.getEntryNode();
1297 switch (getTypeAction(Node->getOperand(1).getValueType())) {
1298 case Expand: assert(0 && "It's impossible to expand bools");
1300 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the condition.
1303 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the condition.
1305 // The top bits of the promoted condition are not necessarily zero, ensure
1306 // that the value is properly zero extended.
1307 if (!TLI.MaskedValueIsZero(Tmp2,
1308 MVT::getIntVTBitMask(Tmp2.getValueType())^1))
1309 Tmp2 = DAG.getZeroExtendInReg(Tmp2, MVT::i1);
1313 // Basic block destination (Op#2) is always legal.
1314 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
1316 switch (TLI.getOperationAction(ISD::BRCOND, MVT::Other)) {
1317 default: assert(0 && "This action is not supported yet!");
1318 case TargetLowering::Legal: break;
1319 case TargetLowering::Custom:
1320 Tmp1 = TLI.LowerOperation(Result, DAG);
1321 if (Tmp1.Val) Result = Tmp1;
1323 case TargetLowering::Expand:
1324 // Expand brcond's setcc into its constituent parts and create a BR_CC
1326 if (Tmp2.getOpcode() == ISD::SETCC) {
1327 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1, Tmp2.getOperand(2),
1328 Tmp2.getOperand(0), Tmp2.getOperand(1),
1329 Node->getOperand(2));
1331 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1,
1332 DAG.getCondCode(ISD::SETNE), Tmp2,
1333 DAG.getConstant(0, Tmp2.getValueType()),
1334 Node->getOperand(2));
1340 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1341 // Ensure that libcalls are emitted before a branch.
1342 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1343 Tmp1 = LegalizeOp(Tmp1);
1344 LastCALLSEQ_END = DAG.getEntryNode();
1346 Tmp2 = Node->getOperand(2); // LHS
1347 Tmp3 = Node->getOperand(3); // RHS
1348 Tmp4 = Node->getOperand(1); // CC
1350 LegalizeSetCCOperands(Tmp2, Tmp3, Tmp4);
1352 // If we didn't get both a LHS and RHS back from LegalizeSetCCOperands,
1353 // the LHS is a legal SETCC itself. In this case, we need to compare
1354 // the result against zero to select between true and false values.
1355 if (Tmp3.Val == 0) {
1356 Tmp3 = DAG.getConstant(0, Tmp2.getValueType());
1357 Tmp4 = DAG.getCondCode(ISD::SETNE);
1360 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp4, Tmp2, Tmp3,
1361 Node->getOperand(4));
1363 switch (TLI.getOperationAction(ISD::BR_CC, Tmp3.getValueType())) {
1364 default: assert(0 && "Unexpected action for BR_CC!");
1365 case TargetLowering::Legal: break;
1366 case TargetLowering::Custom:
1367 Tmp4 = TLI.LowerOperation(Result, DAG);
1368 if (Tmp4.Val) Result = Tmp4;
1373 LoadSDNode *LD = cast<LoadSDNode>(Node);
1374 Tmp1 = LegalizeOp(LD->getChain()); // Legalize the chain.
1375 Tmp2 = LegalizeOp(LD->getBasePtr()); // Legalize the base pointer.
1377 ISD::LoadExtType ExtType = LD->getExtensionType();
1378 if (ExtType == ISD::NON_EXTLOAD) {
1379 MVT::ValueType VT = Node->getValueType(0);
1380 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, LD->getOffset());
1381 Tmp3 = Result.getValue(0);
1382 Tmp4 = Result.getValue(1);
1384 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
1385 default: assert(0 && "This action is not supported yet!");
1386 case TargetLowering::Legal: break;
1387 case TargetLowering::Custom:
1388 Tmp1 = TLI.LowerOperation(Tmp3, DAG);
1390 Tmp3 = LegalizeOp(Tmp1);
1391 Tmp4 = LegalizeOp(Tmp1.getValue(1));
1394 case TargetLowering::Promote: {
1395 // Only promote a load of vector type to another.
1396 assert(MVT::isVector(VT) && "Cannot promote this load!");
1397 // Change base type to a different vector type.
1398 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), VT);
1400 Tmp1 = DAG.getLoad(NVT, Tmp1, Tmp2, LD->getSrcValue(),
1401 LD->getSrcValueOffset());
1402 Tmp3 = LegalizeOp(DAG.getNode(ISD::BIT_CONVERT, VT, Tmp1));
1403 Tmp4 = LegalizeOp(Tmp1.getValue(1));
1407 // Since loads produce two values, make sure to remember that we
1408 // legalized both of them.
1409 AddLegalizedOperand(SDOperand(Node, 0), Tmp3);
1410 AddLegalizedOperand(SDOperand(Node, 1), Tmp4);
1411 return Op.ResNo ? Tmp4 : Tmp3;
1413 MVT::ValueType SrcVT = LD->getLoadedVT();
1414 switch (TLI.getLoadXAction(ExtType, SrcVT)) {
1415 default: assert(0 && "This action is not supported yet!");
1416 case TargetLowering::Promote:
1417 assert(SrcVT == MVT::i1 &&
1418 "Can only promote extending LOAD from i1 -> i8!");
1419 Result = DAG.getExtLoad(ExtType, Node->getValueType(0), Tmp1, Tmp2,
1420 LD->getSrcValue(), LD->getSrcValueOffset(),
1422 Tmp1 = Result.getValue(0);
1423 Tmp2 = Result.getValue(1);
1425 case TargetLowering::Custom:
1428 case TargetLowering::Legal:
1429 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, LD->getOffset());
1430 Tmp1 = Result.getValue(0);
1431 Tmp2 = Result.getValue(1);
1434 Tmp3 = TLI.LowerOperation(Result, DAG);
1436 Tmp1 = LegalizeOp(Tmp3);
1437 Tmp2 = LegalizeOp(Tmp3.getValue(1));
1441 case TargetLowering::Expand:
1442 // f64 = EXTLOAD f32 should expand to LOAD, FP_EXTEND
1443 if (SrcVT == MVT::f32 && Node->getValueType(0) == MVT::f64) {
1444 SDOperand Load = DAG.getLoad(SrcVT, Tmp1, Tmp2, LD->getSrcValue(),
1445 LD->getSrcValueOffset());
1446 Result = DAG.getNode(ISD::FP_EXTEND, Node->getValueType(0), Load);
1447 Tmp1 = LegalizeOp(Result); // Relegalize new nodes.
1448 Tmp2 = LegalizeOp(Load.getValue(1));
1451 assert(ExtType != ISD::EXTLOAD && "EXTLOAD should always be supported!");
1452 // Turn the unsupported load into an EXTLOAD followed by an explicit
1453 // zero/sign extend inreg.
1454 Result = DAG.getExtLoad(ISD::EXTLOAD, Node->getValueType(0),
1455 Tmp1, Tmp2, LD->getSrcValue(),
1456 LD->getSrcValueOffset(), SrcVT);
1458 if (ExtType == ISD::SEXTLOAD)
1459 ValRes = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(),
1460 Result, DAG.getValueType(SrcVT));
1462 ValRes = DAG.getZeroExtendInReg(Result, SrcVT);
1463 Tmp1 = LegalizeOp(ValRes); // Relegalize new nodes.
1464 Tmp2 = LegalizeOp(Result.getValue(1)); // Relegalize new nodes.
1467 // Since loads produce two values, make sure to remember that we legalized
1469 AddLegalizedOperand(SDOperand(Node, 0), Tmp1);
1470 AddLegalizedOperand(SDOperand(Node, 1), Tmp2);
1471 return Op.ResNo ? Tmp2 : Tmp1;
1474 case ISD::EXTRACT_ELEMENT: {
1475 MVT::ValueType OpTy = Node->getOperand(0).getValueType();
1476 switch (getTypeAction(OpTy)) {
1477 default: assert(0 && "EXTRACT_ELEMENT action for type unimplemented!");
1479 if (cast<ConstantSDNode>(Node->getOperand(1))->getValue()) {
1481 Result = DAG.getNode(ISD::SRL, OpTy, Node->getOperand(0),
1482 DAG.getConstant(MVT::getSizeInBits(OpTy)/2,
1483 TLI.getShiftAmountTy()));
1484 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), Result);
1487 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0),
1488 Node->getOperand(0));
1492 // Get both the low and high parts.
1493 ExpandOp(Node->getOperand(0), Tmp1, Tmp2);
1494 if (cast<ConstantSDNode>(Node->getOperand(1))->getValue())
1495 Result = Tmp2; // 1 -> Hi
1497 Result = Tmp1; // 0 -> Lo
1503 case ISD::CopyToReg:
1504 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1506 assert(isTypeLegal(Node->getOperand(2).getValueType()) &&
1507 "Register type must be legal!");
1508 // Legalize the incoming value (must be a legal type).
1509 Tmp2 = LegalizeOp(Node->getOperand(2));
1510 if (Node->getNumValues() == 1) {
1511 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1), Tmp2);
1513 assert(Node->getNumValues() == 2 && "Unknown CopyToReg");
1514 if (Node->getNumOperands() == 4) {
1515 Tmp3 = LegalizeOp(Node->getOperand(3));
1516 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1), Tmp2,
1519 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1),Tmp2);
1522 // Since this produces two values, make sure to remember that we legalized
1524 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
1525 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
1531 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1533 // Ensure that libcalls are emitted before a return.
1534 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1535 Tmp1 = LegalizeOp(Tmp1);
1536 LastCALLSEQ_END = DAG.getEntryNode();
1538 switch (Node->getNumOperands()) {
1540 Tmp2 = Node->getOperand(1);
1541 Tmp3 = Node->getOperand(2); // Signness
1542 switch (getTypeAction(Tmp2.getValueType())) {
1544 Result = DAG.UpdateNodeOperands(Result, Tmp1, LegalizeOp(Tmp2), Tmp3);
1547 if (Tmp2.getValueType() != MVT::Vector) {
1549 ExpandOp(Tmp2, Lo, Hi);
1551 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Tmp3, Hi,Tmp3);
1553 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Tmp3);
1554 Result = LegalizeOp(Result);
1556 SDNode *InVal = Tmp2.Val;
1558 cast<ConstantSDNode>(*(InVal->op_end()-2))->getValue();
1559 MVT::ValueType EVT = cast<VTSDNode>(*(InVal->op_end()-1))->getVT();
1561 // Figure out if there is a Packed type corresponding to this Vector
1562 // type. If so, convert to the packed type.
1563 MVT::ValueType TVT = MVT::getVectorType(EVT, NumElems);
1564 if (TVT != MVT::Other && TLI.isTypeLegal(TVT)) {
1565 // Turn this into a return of the packed type.
1566 Tmp2 = PackVectorOp(Tmp2, TVT);
1567 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1568 } else if (NumElems == 1) {
1569 // Turn this into a return of the scalar type.
1570 Tmp2 = PackVectorOp(Tmp2, EVT);
1571 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1573 // FIXME: Returns of gcc generic vectors smaller than a legal type
1574 // should be returned in integer registers!
1576 // The scalarized value type may not be legal, e.g. it might require
1577 // promotion or expansion. Relegalize the return.
1578 Result = LegalizeOp(Result);
1580 // FIXME: Returns of gcc generic vectors larger than a legal vector
1581 // type should be returned by reference!
1583 SplitVectorOp(Tmp2, Lo, Hi);
1584 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Tmp3, Hi, Tmp3);
1585 Result = LegalizeOp(Result);
1590 Tmp2 = PromoteOp(Node->getOperand(1));
1591 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1592 Result = LegalizeOp(Result);
1597 Result = DAG.UpdateNodeOperands(Result, Tmp1);
1599 default: { // ret <values>
1600 SmallVector<SDOperand, 8> NewValues;
1601 NewValues.push_back(Tmp1);
1602 for (unsigned i = 1, e = Node->getNumOperands(); i < e; i += 2)
1603 switch (getTypeAction(Node->getOperand(i).getValueType())) {
1605 NewValues.push_back(LegalizeOp(Node->getOperand(i)));
1606 NewValues.push_back(Node->getOperand(i+1));
1610 assert(Node->getOperand(i).getValueType() != MVT::Vector &&
1611 "FIXME: TODO: implement returning non-legal vector types!");
1612 ExpandOp(Node->getOperand(i), Lo, Hi);
1613 NewValues.push_back(Lo);
1614 NewValues.push_back(Node->getOperand(i+1));
1616 NewValues.push_back(Hi);
1617 NewValues.push_back(Node->getOperand(i+1));
1622 assert(0 && "Can't promote multiple return value yet!");
1625 if (NewValues.size() == Node->getNumOperands())
1626 Result = DAG.UpdateNodeOperands(Result, &NewValues[0],NewValues.size());
1628 Result = DAG.getNode(ISD::RET, MVT::Other,
1629 &NewValues[0], NewValues.size());
1634 if (Result.getOpcode() == ISD::RET) {
1635 switch (TLI.getOperationAction(Result.getOpcode(), MVT::Other)) {
1636 default: assert(0 && "This action is not supported yet!");
1637 case TargetLowering::Legal: break;
1638 case TargetLowering::Custom:
1639 Tmp1 = TLI.LowerOperation(Result, DAG);
1640 if (Tmp1.Val) Result = Tmp1;
1646 StoreSDNode *ST = cast<StoreSDNode>(Node);
1647 Tmp1 = LegalizeOp(ST->getChain()); // Legalize the chain.
1648 Tmp2 = LegalizeOp(ST->getBasePtr()); // Legalize the pointer.
1650 if (!ST->isTruncatingStore()) {
1651 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr'
1652 // FIXME: We shouldn't do this for TargetConstantFP's.
1653 // FIXME: move this to the DAG Combiner! Note that we can't regress due
1654 // to phase ordering between legalized code and the dag combiner. This
1655 // probably means that we need to integrate dag combiner and legalizer
1657 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(ST->getValue())) {
1658 if (CFP->getValueType(0) == MVT::f32) {
1659 Tmp3 = DAG.getConstant(FloatToBits(CFP->getValue()), MVT::i32);
1661 assert(CFP->getValueType(0) == MVT::f64 && "Unknown FP type!");
1662 Tmp3 = DAG.getConstant(DoubleToBits(CFP->getValue()), MVT::i64);
1664 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
1665 ST->getSrcValueOffset());
1669 switch (getTypeAction(ST->getStoredVT())) {
1671 Tmp3 = LegalizeOp(ST->getValue());
1672 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2,
1675 MVT::ValueType VT = Tmp3.getValueType();
1676 switch (TLI.getOperationAction(ISD::STORE, VT)) {
1677 default: assert(0 && "This action is not supported yet!");
1678 case TargetLowering::Legal: break;
1679 case TargetLowering::Custom:
1680 Tmp1 = TLI.LowerOperation(Result, DAG);
1681 if (Tmp1.Val) Result = Tmp1;
1683 case TargetLowering::Promote:
1684 assert(MVT::isVector(VT) && "Unknown legal promote case!");
1685 Tmp3 = DAG.getNode(ISD::BIT_CONVERT,
1686 TLI.getTypeToPromoteTo(ISD::STORE, VT), Tmp3);
1687 Result = DAG.getStore(Tmp1, Tmp3, Tmp2,
1688 ST->getSrcValue(), ST->getSrcValueOffset());
1694 // Truncate the value and store the result.
1695 Tmp3 = PromoteOp(ST->getValue());
1696 Result = DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
1697 ST->getSrcValueOffset(), ST->getStoredVT());
1701 unsigned IncrementSize = 0;
1704 // If this is a vector type, then we have to calculate the increment as
1705 // the product of the element size in bytes, and the number of elements
1706 // in the high half of the vector.
1707 if (ST->getValue().getValueType() == MVT::Vector) {
1708 SDNode *InVal = ST->getValue().Val;
1710 cast<ConstantSDNode>(*(InVal->op_end()-2))->getValue();
1711 MVT::ValueType EVT = cast<VTSDNode>(*(InVal->op_end()-1))->getVT();
1713 // Figure out if there is a Packed type corresponding to this Vector
1714 // type. If so, convert to the packed type.
1715 MVT::ValueType TVT = MVT::getVectorType(EVT, NumElems);
1716 if (TVT != MVT::Other && TLI.isTypeLegal(TVT)) {
1717 // Turn this into a normal store of the packed type.
1718 Tmp3 = PackVectorOp(Node->getOperand(1), TVT);
1719 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
1720 ST->getSrcValueOffset());
1721 Result = LegalizeOp(Result);
1723 } else if (NumElems == 1) {
1724 // Turn this into a normal store of the scalar type.
1725 Tmp3 = PackVectorOp(Node->getOperand(1), EVT);
1726 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
1727 ST->getSrcValueOffset());
1728 // The scalarized value type may not be legal, e.g. it might require
1729 // promotion or expansion. Relegalize the scalar store.
1730 Result = LegalizeOp(Result);
1733 SplitVectorOp(Node->getOperand(1), Lo, Hi);
1734 IncrementSize = NumElems/2 * MVT::getSizeInBits(EVT)/8;
1737 ExpandOp(Node->getOperand(1), Lo, Hi);
1738 IncrementSize = Hi.Val ? MVT::getSizeInBits(Hi.getValueType())/8 : 0;
1740 if (!TLI.isLittleEndian())
1744 Lo = DAG.getStore(Tmp1, Lo, Tmp2, ST->getSrcValue(),
1745 ST->getSrcValueOffset());
1747 if (Hi.Val == NULL) {
1748 // Must be int <-> float one-to-one expansion.
1753 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2,
1754 getIntPtrConstant(IncrementSize));
1755 assert(isTypeLegal(Tmp2.getValueType()) &&
1756 "Pointers must be legal!");
1757 // FIXME: This sets the srcvalue of both halves to be the same, which is
1759 Hi = DAG.getStore(Tmp1, Hi, Tmp2, ST->getSrcValue(),
1760 ST->getSrcValueOffset());
1761 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi);
1766 assert(isTypeLegal(ST->getValue().getValueType()) &&
1767 "Cannot handle illegal TRUNCSTORE yet!");
1768 Tmp3 = LegalizeOp(ST->getValue());
1770 // The only promote case we handle is TRUNCSTORE:i1 X into
1771 // -> TRUNCSTORE:i8 (and X, 1)
1772 if (ST->getStoredVT() == MVT::i1 &&
1773 TLI.getStoreXAction(MVT::i1) == TargetLowering::Promote) {
1774 // Promote the bool to a mask then store.
1775 Tmp3 = DAG.getNode(ISD::AND, Tmp3.getValueType(), Tmp3,
1776 DAG.getConstant(1, Tmp3.getValueType()));
1777 Result = DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
1778 ST->getSrcValueOffset(), MVT::i8);
1779 } else if (Tmp1 != ST->getChain() || Tmp3 != ST->getValue() ||
1780 Tmp2 != ST->getBasePtr()) {
1781 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2,
1785 MVT::ValueType StVT = cast<StoreSDNode>(Result.Val)->getStoredVT();
1786 switch (TLI.getStoreXAction(StVT)) {
1787 default: assert(0 && "This action is not supported yet!");
1788 case TargetLowering::Legal: break;
1789 case TargetLowering::Custom:
1790 Tmp1 = TLI.LowerOperation(Result, DAG);
1791 if (Tmp1.Val) Result = Tmp1;
1798 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1799 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
1801 case ISD::STACKSAVE:
1802 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1803 Result = DAG.UpdateNodeOperands(Result, Tmp1);
1804 Tmp1 = Result.getValue(0);
1805 Tmp2 = Result.getValue(1);
1807 switch (TLI.getOperationAction(ISD::STACKSAVE, MVT::Other)) {
1808 default: assert(0 && "This action is not supported yet!");
1809 case TargetLowering::Legal: break;
1810 case TargetLowering::Custom:
1811 Tmp3 = TLI.LowerOperation(Result, DAG);
1813 Tmp1 = LegalizeOp(Tmp3);
1814 Tmp2 = LegalizeOp(Tmp3.getValue(1));
1817 case TargetLowering::Expand:
1818 // Expand to CopyFromReg if the target set
1819 // StackPointerRegisterToSaveRestore.
1820 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) {
1821 Tmp1 = DAG.getCopyFromReg(Result.getOperand(0), SP,
1822 Node->getValueType(0));
1823 Tmp2 = Tmp1.getValue(1);
1825 Tmp1 = DAG.getNode(ISD::UNDEF, Node->getValueType(0));
1826 Tmp2 = Node->getOperand(0);
1831 // Since stacksave produce two values, make sure to remember that we
1832 // legalized both of them.
1833 AddLegalizedOperand(SDOperand(Node, 0), Tmp1);
1834 AddLegalizedOperand(SDOperand(Node, 1), Tmp2);
1835 return Op.ResNo ? Tmp2 : Tmp1;
1837 case ISD::STACKRESTORE:
1838 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1839 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
1840 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1842 switch (TLI.getOperationAction(ISD::STACKRESTORE, MVT::Other)) {
1843 default: assert(0 && "This action is not supported yet!");
1844 case TargetLowering::Legal: break;
1845 case TargetLowering::Custom:
1846 Tmp1 = TLI.LowerOperation(Result, DAG);
1847 if (Tmp1.Val) Result = Tmp1;
1849 case TargetLowering::Expand:
1850 // Expand to CopyToReg if the target set
1851 // StackPointerRegisterToSaveRestore.
1852 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) {
1853 Result = DAG.getCopyToReg(Tmp1, SP, Tmp2);
1861 case ISD::READCYCLECOUNTER:
1862 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain
1863 Result = DAG.UpdateNodeOperands(Result, Tmp1);
1864 switch (TLI.getOperationAction(ISD::READCYCLECOUNTER,
1865 Node->getValueType(0))) {
1866 default: assert(0 && "This action is not supported yet!");
1867 case TargetLowering::Legal:
1868 Tmp1 = Result.getValue(0);
1869 Tmp2 = Result.getValue(1);
1871 case TargetLowering::Custom:
1872 Result = TLI.LowerOperation(Result, DAG);
1873 Tmp1 = LegalizeOp(Result.getValue(0));
1874 Tmp2 = LegalizeOp(Result.getValue(1));
1878 // Since rdcc produce two values, make sure to remember that we legalized
1880 AddLegalizedOperand(SDOperand(Node, 0), Tmp1);
1881 AddLegalizedOperand(SDOperand(Node, 1), Tmp2);
1885 switch (getTypeAction(Node->getOperand(0).getValueType())) {
1886 case Expand: assert(0 && "It's impossible to expand bools");
1888 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the condition.
1891 Tmp1 = PromoteOp(Node->getOperand(0)); // Promote the condition.
1892 // Make sure the condition is either zero or one.
1893 if (!TLI.MaskedValueIsZero(Tmp1,
1894 MVT::getIntVTBitMask(Tmp1.getValueType())^1))
1895 Tmp1 = DAG.getZeroExtendInReg(Tmp1, MVT::i1);
1898 Tmp2 = LegalizeOp(Node->getOperand(1)); // TrueVal
1899 Tmp3 = LegalizeOp(Node->getOperand(2)); // FalseVal
1901 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1903 switch (TLI.getOperationAction(ISD::SELECT, Tmp2.getValueType())) {
1904 default: assert(0 && "This action is not supported yet!");
1905 case TargetLowering::Legal: break;
1906 case TargetLowering::Custom: {
1907 Tmp1 = TLI.LowerOperation(Result, DAG);
1908 if (Tmp1.Val) Result = Tmp1;
1911 case TargetLowering::Expand:
1912 if (Tmp1.getOpcode() == ISD::SETCC) {
1913 Result = DAG.getSelectCC(Tmp1.getOperand(0), Tmp1.getOperand(1),
1915 cast<CondCodeSDNode>(Tmp1.getOperand(2))->get());
1917 Result = DAG.getSelectCC(Tmp1,
1918 DAG.getConstant(0, Tmp1.getValueType()),
1919 Tmp2, Tmp3, ISD::SETNE);
1922 case TargetLowering::Promote: {
1923 MVT::ValueType NVT =
1924 TLI.getTypeToPromoteTo(ISD::SELECT, Tmp2.getValueType());
1925 unsigned ExtOp, TruncOp;
1926 if (MVT::isVector(Tmp2.getValueType())) {
1927 ExtOp = ISD::BIT_CONVERT;
1928 TruncOp = ISD::BIT_CONVERT;
1929 } else if (MVT::isInteger(Tmp2.getValueType())) {
1930 ExtOp = ISD::ANY_EXTEND;
1931 TruncOp = ISD::TRUNCATE;
1933 ExtOp = ISD::FP_EXTEND;
1934 TruncOp = ISD::FP_ROUND;
1936 // Promote each of the values to the new type.
1937 Tmp2 = DAG.getNode(ExtOp, NVT, Tmp2);
1938 Tmp3 = DAG.getNode(ExtOp, NVT, Tmp3);
1939 // Perform the larger operation, then round down.
1940 Result = DAG.getNode(ISD::SELECT, NVT, Tmp1, Tmp2,Tmp3);
1941 Result = DAG.getNode(TruncOp, Node->getValueType(0), Result);
1946 case ISD::SELECT_CC: {
1947 Tmp1 = Node->getOperand(0); // LHS
1948 Tmp2 = Node->getOperand(1); // RHS
1949 Tmp3 = LegalizeOp(Node->getOperand(2)); // True
1950 Tmp4 = LegalizeOp(Node->getOperand(3)); // False
1951 SDOperand CC = Node->getOperand(4);
1953 LegalizeSetCCOperands(Tmp1, Tmp2, CC);
1955 // If we didn't get both a LHS and RHS back from LegalizeSetCCOperands,
1956 // the LHS is a legal SETCC itself. In this case, we need to compare
1957 // the result against zero to select between true and false values.
1958 if (Tmp2.Val == 0) {
1959 Tmp2 = DAG.getConstant(0, Tmp1.getValueType());
1960 CC = DAG.getCondCode(ISD::SETNE);
1962 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4, CC);
1964 // Everything is legal, see if we should expand this op or something.
1965 switch (TLI.getOperationAction(ISD::SELECT_CC, Tmp3.getValueType())) {
1966 default: assert(0 && "This action is not supported yet!");
1967 case TargetLowering::Legal: break;
1968 case TargetLowering::Custom:
1969 Tmp1 = TLI.LowerOperation(Result, DAG);
1970 if (Tmp1.Val) Result = Tmp1;
1976 Tmp1 = Node->getOperand(0);
1977 Tmp2 = Node->getOperand(1);
1978 Tmp3 = Node->getOperand(2);
1979 LegalizeSetCCOperands(Tmp1, Tmp2, Tmp3);
1981 // If we had to Expand the SetCC operands into a SELECT node, then it may
1982 // not always be possible to return a true LHS & RHS. In this case, just
1983 // return the value we legalized, returned in the LHS
1984 if (Tmp2.Val == 0) {
1989 switch (TLI.getOperationAction(ISD::SETCC, Tmp1.getValueType())) {
1990 default: assert(0 && "Cannot handle this action for SETCC yet!");
1991 case TargetLowering::Custom:
1994 case TargetLowering::Legal:
1995 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
1997 Tmp3 = TLI.LowerOperation(Result, DAG);
1998 if (Tmp3.Val) Result = Tmp3;
2001 case TargetLowering::Promote: {
2002 // First step, figure out the appropriate operation to use.
2003 // Allow SETCC to not be supported for all legal data types
2004 // Mostly this targets FP
2005 MVT::ValueType NewInTy = Node->getOperand(0).getValueType();
2006 MVT::ValueType OldVT = NewInTy;
2008 // Scan for the appropriate larger type to use.
2010 NewInTy = (MVT::ValueType)(NewInTy+1);
2012 assert(MVT::isInteger(NewInTy) == MVT::isInteger(OldVT) &&
2013 "Fell off of the edge of the integer world");
2014 assert(MVT::isFloatingPoint(NewInTy) == MVT::isFloatingPoint(OldVT) &&
2015 "Fell off of the edge of the floating point world");
2017 // If the target supports SETCC of this type, use it.
2018 if (TLI.isOperationLegal(ISD::SETCC, NewInTy))
2021 if (MVT::isInteger(NewInTy))
2022 assert(0 && "Cannot promote Legal Integer SETCC yet");
2024 Tmp1 = DAG.getNode(ISD::FP_EXTEND, NewInTy, Tmp1);
2025 Tmp2 = DAG.getNode(ISD::FP_EXTEND, NewInTy, Tmp2);
2027 Tmp1 = LegalizeOp(Tmp1);
2028 Tmp2 = LegalizeOp(Tmp2);
2029 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
2030 Result = LegalizeOp(Result);
2033 case TargetLowering::Expand:
2034 // Expand a setcc node into a select_cc of the same condition, lhs, and
2035 // rhs that selects between const 1 (true) and const 0 (false).
2036 MVT::ValueType VT = Node->getValueType(0);
2037 Result = DAG.getNode(ISD::SELECT_CC, VT, Tmp1, Tmp2,
2038 DAG.getConstant(1, VT), DAG.getConstant(0, VT),
2039 Node->getOperand(2));
2045 case ISD::MEMMOVE: {
2046 Tmp1 = LegalizeOp(Node->getOperand(0)); // Chain
2047 Tmp2 = LegalizeOp(Node->getOperand(1)); // Pointer
2049 if (Node->getOpcode() == ISD::MEMSET) { // memset = ubyte
2050 switch (getTypeAction(Node->getOperand(2).getValueType())) {
2051 case Expand: assert(0 && "Cannot expand a byte!");
2053 Tmp3 = LegalizeOp(Node->getOperand(2));
2056 Tmp3 = PromoteOp(Node->getOperand(2));
2060 Tmp3 = LegalizeOp(Node->getOperand(2)); // memcpy/move = pointer,
2064 switch (getTypeAction(Node->getOperand(3).getValueType())) {
2066 // Length is too big, just take the lo-part of the length.
2068 ExpandOp(Node->getOperand(3), Tmp4, HiPart);
2072 Tmp4 = LegalizeOp(Node->getOperand(3));
2075 Tmp4 = PromoteOp(Node->getOperand(3));
2080 switch (getTypeAction(Node->getOperand(4).getValueType())) { // uint
2081 case Expand: assert(0 && "Cannot expand this yet!");
2083 Tmp5 = LegalizeOp(Node->getOperand(4));
2086 Tmp5 = PromoteOp(Node->getOperand(4));
2090 switch (TLI.getOperationAction(Node->getOpcode(), MVT::Other)) {
2091 default: assert(0 && "This action not implemented for this operation!");
2092 case TargetLowering::Custom:
2095 case TargetLowering::Legal:
2096 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4, Tmp5);
2098 Tmp1 = TLI.LowerOperation(Result, DAG);
2099 if (Tmp1.Val) Result = Tmp1;
2102 case TargetLowering::Expand: {
2103 // Otherwise, the target does not support this operation. Lower the
2104 // operation to an explicit libcall as appropriate.
2105 MVT::ValueType IntPtr = TLI.getPointerTy();
2106 const Type *IntPtrTy = TLI.getTargetData()->getIntPtrType();
2107 std::vector<std::pair<SDOperand, const Type*> > Args;
2109 const char *FnName = 0;
2110 if (Node->getOpcode() == ISD::MEMSET) {
2111 Args.push_back(std::make_pair(Tmp2, IntPtrTy));
2112 // Extend the (previously legalized) ubyte argument to be an int value
2114 if (Tmp3.getValueType() > MVT::i32)
2115 Tmp3 = DAG.getNode(ISD::TRUNCATE, MVT::i32, Tmp3);
2117 Tmp3 = DAG.getNode(ISD::ZERO_EXTEND, MVT::i32, Tmp3);
2118 Args.push_back(std::make_pair(Tmp3, Type::IntTy));
2119 Args.push_back(std::make_pair(Tmp4, IntPtrTy));
2122 } else if (Node->getOpcode() == ISD::MEMCPY ||
2123 Node->getOpcode() == ISD::MEMMOVE) {
2124 Args.push_back(std::make_pair(Tmp2, IntPtrTy));
2125 Args.push_back(std::make_pair(Tmp3, IntPtrTy));
2126 Args.push_back(std::make_pair(Tmp4, IntPtrTy));
2127 FnName = Node->getOpcode() == ISD::MEMMOVE ? "memmove" : "memcpy";
2129 assert(0 && "Unknown op!");
2132 std::pair<SDOperand,SDOperand> CallResult =
2133 TLI.LowerCallTo(Tmp1, Type::VoidTy, false, CallingConv::C, false,
2134 DAG.getExternalSymbol(FnName, IntPtr), Args, DAG);
2135 Result = CallResult.second;
2142 case ISD::SHL_PARTS:
2143 case ISD::SRA_PARTS:
2144 case ISD::SRL_PARTS: {
2145 SmallVector<SDOperand, 8> Ops;
2146 bool Changed = false;
2147 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
2148 Ops.push_back(LegalizeOp(Node->getOperand(i)));
2149 Changed |= Ops.back() != Node->getOperand(i);
2152 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
2154 switch (TLI.getOperationAction(Node->getOpcode(),
2155 Node->getValueType(0))) {
2156 default: assert(0 && "This action is not supported yet!");
2157 case TargetLowering::Legal: break;
2158 case TargetLowering::Custom:
2159 Tmp1 = TLI.LowerOperation(Result, DAG);
2161 SDOperand Tmp2, RetVal(0, 0);
2162 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) {
2163 Tmp2 = LegalizeOp(Tmp1.getValue(i));
2164 AddLegalizedOperand(SDOperand(Node, i), Tmp2);
2168 assert(RetVal.Val && "Illegal result number");
2174 // Since these produce multiple values, make sure to remember that we
2175 // legalized all of them.
2176 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
2177 AddLegalizedOperand(SDOperand(Node, i), Result.getValue(i));
2178 return Result.getValue(Op.ResNo);
2199 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
2200 switch (getTypeAction(Node->getOperand(1).getValueType())) {
2201 case Expand: assert(0 && "Not possible");
2203 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the RHS.
2206 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the RHS.
2210 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
2212 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
2213 default: assert(0 && "BinOp legalize operation not supported");
2214 case TargetLowering::Legal: break;
2215 case TargetLowering::Custom:
2216 Tmp1 = TLI.LowerOperation(Result, DAG);
2217 if (Tmp1.Val) Result = Tmp1;
2219 case TargetLowering::Expand: {
2220 if (Node->getValueType(0) == MVT::i32) {
2221 switch (Node->getOpcode()) {
2222 default: assert(0 && "Do not know how to expand this integer BinOp!");
2225 const char *FnName = Node->getOpcode() == ISD::UDIV
2226 ? "__udivsi3" : "__divsi3";
2228 Result = ExpandLibCall(FnName, Node, Dummy);
2233 assert(MVT::isVector(Node->getValueType(0)) &&
2234 "Cannot expand this binary operator!");
2235 // Expand the operation into a bunch of nasty scalar code.
2236 SmallVector<SDOperand, 8> Ops;
2237 MVT::ValueType EltVT = MVT::getVectorBaseType(Node->getValueType(0));
2238 MVT::ValueType PtrVT = TLI.getPointerTy();
2239 for (unsigned i = 0, e = MVT::getVectorNumElements(Node->getValueType(0));
2241 SDOperand Idx = DAG.getConstant(i, PtrVT);
2242 SDOperand LHS = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, Tmp1, Idx);
2243 SDOperand RHS = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, Tmp2, Idx);
2244 Ops.push_back(DAG.getNode(Node->getOpcode(), EltVT, LHS, RHS));
2246 Result = DAG.getNode(ISD::BUILD_VECTOR, Node->getValueType(0),
2247 &Ops[0], Ops.size());
2250 case TargetLowering::Promote: {
2251 switch (Node->getOpcode()) {
2252 default: assert(0 && "Do not know how to promote this BinOp!");
2256 MVT::ValueType OVT = Node->getValueType(0);
2257 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
2258 assert(MVT::isVector(OVT) && "Cannot promote this BinOp!");
2259 // Bit convert each of the values to the new type.
2260 Tmp1 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp1);
2261 Tmp2 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp2);
2262 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
2263 // Bit convert the result back the original type.
2264 Result = DAG.getNode(ISD::BIT_CONVERT, OVT, Result);
2272 case ISD::FCOPYSIGN: // FCOPYSIGN does not require LHS/RHS to match type!
2273 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
2274 switch (getTypeAction(Node->getOperand(1).getValueType())) {
2275 case Expand: assert(0 && "Not possible");
2277 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the RHS.
2280 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the RHS.
2284 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
2286 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
2287 default: assert(0 && "Operation not supported");
2288 case TargetLowering::Custom:
2289 Tmp1 = TLI.LowerOperation(Result, DAG);
2290 if (Tmp1.Val) Result = Tmp1;
2292 case TargetLowering::Legal: break;
2293 case TargetLowering::Expand:
2294 // If this target supports fabs/fneg natively, do this efficiently.
2295 if (TLI.isOperationLegal(ISD::FABS, Tmp1.getValueType()) &&
2296 TLI.isOperationLegal(ISD::FNEG, Tmp1.getValueType())) {
2297 // Get the sign bit of the RHS.
2298 MVT::ValueType IVT =
2299 Tmp2.getValueType() == MVT::f32 ? MVT::i32 : MVT::i64;
2300 SDOperand SignBit = DAG.getNode(ISD::BIT_CONVERT, IVT, Tmp2);
2301 SignBit = DAG.getSetCC(TLI.getSetCCResultTy(),
2302 SignBit, DAG.getConstant(0, IVT), ISD::SETLT);
2303 // Get the absolute value of the result.
2304 SDOperand AbsVal = DAG.getNode(ISD::FABS, Tmp1.getValueType(), Tmp1);
2305 // Select between the nabs and abs value based on the sign bit of
2307 Result = DAG.getNode(ISD::SELECT, AbsVal.getValueType(), SignBit,
2308 DAG.getNode(ISD::FNEG, AbsVal.getValueType(),
2311 Result = LegalizeOp(Result);
2315 // Otherwise, do bitwise ops!
2317 // copysign -> copysignf/copysign libcall.
2319 if (Node->getValueType(0) == MVT::f32) {
2320 FnName = "copysignf";
2321 if (Tmp2.getValueType() != MVT::f32) // Force operands to match type.
2322 Result = DAG.UpdateNodeOperands(Result, Tmp1,
2323 DAG.getNode(ISD::FP_ROUND, MVT::f32, Tmp2));
2325 FnName = "copysign";
2326 if (Tmp2.getValueType() != MVT::f64) // Force operands to match type.
2327 Result = DAG.UpdateNodeOperands(Result, Tmp1,
2328 DAG.getNode(ISD::FP_EXTEND, MVT::f64, Tmp2));
2331 Result = ExpandLibCall(FnName, Node, Dummy);
2338 Tmp1 = LegalizeOp(Node->getOperand(0));
2339 Tmp2 = LegalizeOp(Node->getOperand(1));
2340 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
2341 // Since this produces two values, make sure to remember that we legalized
2343 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
2344 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
2349 Tmp1 = LegalizeOp(Node->getOperand(0));
2350 Tmp2 = LegalizeOp(Node->getOperand(1));
2351 Tmp3 = LegalizeOp(Node->getOperand(2));
2352 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2353 // Since this produces two values, make sure to remember that we legalized
2355 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
2356 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
2359 case ISD::BUILD_PAIR: {
2360 MVT::ValueType PairTy = Node->getValueType(0);
2361 // TODO: handle the case where the Lo and Hi operands are not of legal type
2362 Tmp1 = LegalizeOp(Node->getOperand(0)); // Lo
2363 Tmp2 = LegalizeOp(Node->getOperand(1)); // Hi
2364 switch (TLI.getOperationAction(ISD::BUILD_PAIR, PairTy)) {
2365 case TargetLowering::Promote:
2366 case TargetLowering::Custom:
2367 assert(0 && "Cannot promote/custom this yet!");
2368 case TargetLowering::Legal:
2369 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1))
2370 Result = DAG.getNode(ISD::BUILD_PAIR, PairTy, Tmp1, Tmp2);
2372 case TargetLowering::Expand:
2373 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, PairTy, Tmp1);
2374 Tmp2 = DAG.getNode(ISD::ANY_EXTEND, PairTy, Tmp2);
2375 Tmp2 = DAG.getNode(ISD::SHL, PairTy, Tmp2,
2376 DAG.getConstant(MVT::getSizeInBits(PairTy)/2,
2377 TLI.getShiftAmountTy()));
2378 Result = DAG.getNode(ISD::OR, PairTy, Tmp1, Tmp2);
2387 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
2388 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS
2390 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
2391 case TargetLowering::Promote: assert(0 && "Cannot promote this yet!");
2392 case TargetLowering::Custom:
2395 case TargetLowering::Legal:
2396 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
2398 Tmp1 = TLI.LowerOperation(Result, DAG);
2399 if (Tmp1.Val) Result = Tmp1;
2402 case TargetLowering::Expand:
2403 unsigned DivOpc= (Node->getOpcode() == ISD::UREM) ? ISD::UDIV : ISD::SDIV;
2404 if (MVT::isInteger(Node->getValueType(0))) {
2405 if (TLI.getOperationAction(DivOpc, Node->getValueType(0)) ==
2406 TargetLowering::Legal) {
2408 MVT::ValueType VT = Node->getValueType(0);
2409 Result = DAG.getNode(DivOpc, VT, Tmp1, Tmp2);
2410 Result = DAG.getNode(ISD::MUL, VT, Result, Tmp2);
2411 Result = DAG.getNode(ISD::SUB, VT, Tmp1, Result);
2413 assert(Node->getValueType(0) == MVT::i32 &&
2414 "Cannot expand this binary operator!");
2415 const char *FnName = Node->getOpcode() == ISD::UREM
2416 ? "__umodsi3" : "__modsi3";
2418 Result = ExpandLibCall(FnName, Node, Dummy);
2421 // Floating point mod -> fmod libcall.
2422 const char *FnName = Node->getValueType(0) == MVT::f32 ? "fmodf":"fmod";
2424 Result = ExpandLibCall(FnName, Node, Dummy);
2430 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2431 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
2433 MVT::ValueType VT = Node->getValueType(0);
2434 switch (TLI.getOperationAction(Node->getOpcode(), MVT::Other)) {
2435 default: assert(0 && "This action is not supported yet!");
2436 case TargetLowering::Custom:
2439 case TargetLowering::Legal:
2440 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
2441 Result = Result.getValue(0);
2442 Tmp1 = Result.getValue(1);
2445 Tmp2 = TLI.LowerOperation(Result, DAG);
2447 Result = LegalizeOp(Tmp2);
2448 Tmp1 = LegalizeOp(Tmp2.getValue(1));
2452 case TargetLowering::Expand: {
2453 SrcValueSDNode *SV = cast<SrcValueSDNode>(Node->getOperand(2));
2454 SDOperand VAList = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp2,
2455 SV->getValue(), SV->getOffset());
2456 // Increment the pointer, VAList, to the next vaarg
2457 Tmp3 = DAG.getNode(ISD::ADD, TLI.getPointerTy(), VAList,
2458 DAG.getConstant(MVT::getSizeInBits(VT)/8,
2459 TLI.getPointerTy()));
2460 // Store the incremented VAList to the legalized pointer
2461 Tmp3 = DAG.getStore(VAList.getValue(1), Tmp3, Tmp2, SV->getValue(),
2463 // Load the actual argument out of the pointer VAList
2464 Result = DAG.getLoad(VT, Tmp3, VAList, NULL, 0);
2465 Tmp1 = LegalizeOp(Result.getValue(1));
2466 Result = LegalizeOp(Result);
2470 // Since VAARG produces two values, make sure to remember that we
2471 // legalized both of them.
2472 AddLegalizedOperand(SDOperand(Node, 0), Result);
2473 AddLegalizedOperand(SDOperand(Node, 1), Tmp1);
2474 return Op.ResNo ? Tmp1 : Result;
2478 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2479 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the dest pointer.
2480 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the source pointer.
2482 switch (TLI.getOperationAction(ISD::VACOPY, MVT::Other)) {
2483 default: assert(0 && "This action is not supported yet!");
2484 case TargetLowering::Custom:
2487 case TargetLowering::Legal:
2488 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3,
2489 Node->getOperand(3), Node->getOperand(4));
2491 Tmp1 = TLI.LowerOperation(Result, DAG);
2492 if (Tmp1.Val) Result = Tmp1;
2495 case TargetLowering::Expand:
2496 // This defaults to loading a pointer from the input and storing it to the
2497 // output, returning the chain.
2498 SrcValueSDNode *SVD = cast<SrcValueSDNode>(Node->getOperand(3));
2499 SrcValueSDNode *SVS = cast<SrcValueSDNode>(Node->getOperand(4));
2500 Tmp4 = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp3, SVD->getValue(),
2502 Result = DAG.getStore(Tmp4.getValue(1), Tmp4, Tmp2, SVS->getValue(),
2509 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2510 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
2512 switch (TLI.getOperationAction(ISD::VAEND, MVT::Other)) {
2513 default: assert(0 && "This action is not supported yet!");
2514 case TargetLowering::Custom:
2517 case TargetLowering::Legal:
2518 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
2520 Tmp1 = TLI.LowerOperation(Tmp1, DAG);
2521 if (Tmp1.Val) Result = Tmp1;
2524 case TargetLowering::Expand:
2525 Result = Tmp1; // Default to a no-op, return the chain
2531 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2532 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
2534 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
2536 switch (TLI.getOperationAction(ISD::VASTART, MVT::Other)) {
2537 default: assert(0 && "This action is not supported yet!");
2538 case TargetLowering::Legal: break;
2539 case TargetLowering::Custom:
2540 Tmp1 = TLI.LowerOperation(Result, DAG);
2541 if (Tmp1.Val) Result = Tmp1;
2548 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
2549 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS
2551 assert(TLI.isOperationLegal(Node->getOpcode(), Node->getValueType(0)) &&
2552 "Cannot handle this yet!");
2553 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
2557 Tmp1 = LegalizeOp(Node->getOperand(0)); // Op
2558 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
2559 case TargetLowering::Custom:
2560 assert(0 && "Cannot custom legalize this yet!");
2561 case TargetLowering::Legal:
2562 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2564 case TargetLowering::Promote: {
2565 MVT::ValueType OVT = Tmp1.getValueType();
2566 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
2567 unsigned DiffBits = getSizeInBits(NVT) - getSizeInBits(OVT);
2569 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1);
2570 Tmp1 = DAG.getNode(ISD::BSWAP, NVT, Tmp1);
2571 Result = DAG.getNode(ISD::SRL, NVT, Tmp1,
2572 DAG.getConstant(DiffBits, TLI.getShiftAmountTy()));
2575 case TargetLowering::Expand:
2576 Result = ExpandBSWAP(Tmp1);
2584 Tmp1 = LegalizeOp(Node->getOperand(0)); // Op
2585 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
2586 case TargetLowering::Custom: assert(0 && "Cannot custom handle this yet!");
2587 case TargetLowering::Legal:
2588 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2590 case TargetLowering::Promote: {
2591 MVT::ValueType OVT = Tmp1.getValueType();
2592 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
2594 // Zero extend the argument.
2595 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1);
2596 // Perform the larger operation, then subtract if needed.
2597 Tmp1 = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1);
2598 switch (Node->getOpcode()) {
2603 //if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT)
2604 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), Tmp1,
2605 DAG.getConstant(getSizeInBits(NVT), NVT),
2607 Result = DAG.getNode(ISD::SELECT, NVT, Tmp2,
2608 DAG.getConstant(getSizeInBits(OVT),NVT), Tmp1);
2611 // Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT))
2612 Result = DAG.getNode(ISD::SUB, NVT, Tmp1,
2613 DAG.getConstant(getSizeInBits(NVT) -
2614 getSizeInBits(OVT), NVT));
2619 case TargetLowering::Expand:
2620 Result = ExpandBitCount(Node->getOpcode(), Tmp1);
2631 Tmp1 = LegalizeOp(Node->getOperand(0));
2632 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
2633 case TargetLowering::Promote:
2634 case TargetLowering::Custom:
2637 case TargetLowering::Legal:
2638 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2640 Tmp1 = TLI.LowerOperation(Result, DAG);
2641 if (Tmp1.Val) Result = Tmp1;
2644 case TargetLowering::Expand:
2645 switch (Node->getOpcode()) {
2646 default: assert(0 && "Unreachable!");
2648 // Expand Y = FNEG(X) -> Y = SUB -0.0, X
2649 Tmp2 = DAG.getConstantFP(-0.0, Node->getValueType(0));
2650 Result = DAG.getNode(ISD::FSUB, Node->getValueType(0), Tmp2, Tmp1);
2653 // Expand Y = FABS(X) -> Y = (X >u 0.0) ? X : fneg(X).
2654 MVT::ValueType VT = Node->getValueType(0);
2655 Tmp2 = DAG.getConstantFP(0.0, VT);
2656 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), Tmp1, Tmp2, ISD::SETUGT);
2657 Tmp3 = DAG.getNode(ISD::FNEG, VT, Tmp1);
2658 Result = DAG.getNode(ISD::SELECT, VT, Tmp2, Tmp1, Tmp3);
2664 MVT::ValueType VT = Node->getValueType(0);
2665 const char *FnName = 0;
2666 switch(Node->getOpcode()) {
2667 case ISD::FSQRT: FnName = VT == MVT::f32 ? "sqrtf" : "sqrt"; break;
2668 case ISD::FSIN: FnName = VT == MVT::f32 ? "sinf" : "sin"; break;
2669 case ISD::FCOS: FnName = VT == MVT::f32 ? "cosf" : "cos"; break;
2670 default: assert(0 && "Unreachable!");
2673 Result = ExpandLibCall(FnName, Node, Dummy);
2681 // We always lower FPOWI into a libcall. No target support it yet.
2682 const char *FnName = Node->getValueType(0) == MVT::f32
2683 ? "__powisf2" : "__powidf2";
2685 Result = ExpandLibCall(FnName, Node, Dummy);
2688 case ISD::BIT_CONVERT:
2689 if (!isTypeLegal(Node->getOperand(0).getValueType())) {
2690 Result = ExpandBIT_CONVERT(Node->getValueType(0), Node->getOperand(0));
2692 switch (TLI.getOperationAction(ISD::BIT_CONVERT,
2693 Node->getOperand(0).getValueType())) {
2694 default: assert(0 && "Unknown operation action!");
2695 case TargetLowering::Expand:
2696 Result = ExpandBIT_CONVERT(Node->getValueType(0), Node->getOperand(0));
2698 case TargetLowering::Legal:
2699 Tmp1 = LegalizeOp(Node->getOperand(0));
2700 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2705 case ISD::VBIT_CONVERT: {
2706 assert(Op.getOperand(0).getValueType() == MVT::Vector &&
2707 "Can only have VBIT_CONVERT where input or output is MVT::Vector!");
2709 // The input has to be a vector type, we have to either scalarize it, pack
2710 // it, or convert it based on whether the input vector type is legal.
2711 SDNode *InVal = Node->getOperand(0).Val;
2713 cast<ConstantSDNode>(*(InVal->op_end()-2))->getValue();
2714 MVT::ValueType EVT = cast<VTSDNode>(*(InVal->op_end()-1))->getVT();
2716 // Figure out if there is a Packed type corresponding to this Vector
2717 // type. If so, convert to the packed type.
2718 MVT::ValueType TVT = MVT::getVectorType(EVT, NumElems);
2719 if (TVT != MVT::Other && TLI.isTypeLegal(TVT)) {
2720 // Turn this into a bit convert of the packed input.
2721 Result = DAG.getNode(ISD::BIT_CONVERT, Node->getValueType(0),
2722 PackVectorOp(Node->getOperand(0), TVT));
2724 } else if (NumElems == 1) {
2725 // Turn this into a bit convert of the scalar input.
2726 Result = DAG.getNode(ISD::BIT_CONVERT, Node->getValueType(0),
2727 PackVectorOp(Node->getOperand(0), EVT));
2730 // FIXME: UNIMP! Store then reload
2731 assert(0 && "Cast from unsupported vector type not implemented yet!");
2735 // Conversion operators. The source and destination have different types.
2736 case ISD::SINT_TO_FP:
2737 case ISD::UINT_TO_FP: {
2738 bool isSigned = Node->getOpcode() == ISD::SINT_TO_FP;
2739 switch (getTypeAction(Node->getOperand(0).getValueType())) {
2741 switch (TLI.getOperationAction(Node->getOpcode(),
2742 Node->getOperand(0).getValueType())) {
2743 default: assert(0 && "Unknown operation action!");
2744 case TargetLowering::Custom:
2747 case TargetLowering::Legal:
2748 Tmp1 = LegalizeOp(Node->getOperand(0));
2749 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2751 Tmp1 = TLI.LowerOperation(Result, DAG);
2752 if (Tmp1.Val) Result = Tmp1;
2755 case TargetLowering::Expand:
2756 Result = ExpandLegalINT_TO_FP(isSigned,
2757 LegalizeOp(Node->getOperand(0)),
2758 Node->getValueType(0));
2760 case TargetLowering::Promote:
2761 Result = PromoteLegalINT_TO_FP(LegalizeOp(Node->getOperand(0)),
2762 Node->getValueType(0),
2768 Result = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP,
2769 Node->getValueType(0), Node->getOperand(0));
2772 Tmp1 = PromoteOp(Node->getOperand(0));
2774 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, Tmp1.getValueType(),
2775 Tmp1, DAG.getValueType(Node->getOperand(0).getValueType()));
2777 Tmp1 = DAG.getZeroExtendInReg(Tmp1,
2778 Node->getOperand(0).getValueType());
2780 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2781 Result = LegalizeOp(Result); // The 'op' is not necessarily legal!
2787 switch (getTypeAction(Node->getOperand(0).getValueType())) {
2789 Tmp1 = LegalizeOp(Node->getOperand(0));
2790 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2793 ExpandOp(Node->getOperand(0), Tmp1, Tmp2);
2795 // Since the result is legal, we should just be able to truncate the low
2796 // part of the source.
2797 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), Tmp1);
2800 Result = PromoteOp(Node->getOperand(0));
2801 Result = DAG.getNode(ISD::TRUNCATE, Op.getValueType(), Result);
2806 case ISD::FP_TO_SINT:
2807 case ISD::FP_TO_UINT:
2808 switch (getTypeAction(Node->getOperand(0).getValueType())) {
2810 Tmp1 = LegalizeOp(Node->getOperand(0));
2812 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))){
2813 default: assert(0 && "Unknown operation action!");
2814 case TargetLowering::Custom:
2817 case TargetLowering::Legal:
2818 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2820 Tmp1 = TLI.LowerOperation(Result, DAG);
2821 if (Tmp1.Val) Result = Tmp1;
2824 case TargetLowering::Promote:
2825 Result = PromoteLegalFP_TO_INT(Tmp1, Node->getValueType(0),
2826 Node->getOpcode() == ISD::FP_TO_SINT);
2828 case TargetLowering::Expand:
2829 if (Node->getOpcode() == ISD::FP_TO_UINT) {
2830 SDOperand True, False;
2831 MVT::ValueType VT = Node->getOperand(0).getValueType();
2832 MVT::ValueType NVT = Node->getValueType(0);
2833 unsigned ShiftAmt = MVT::getSizeInBits(Node->getValueType(0))-1;
2834 Tmp2 = DAG.getConstantFP((double)(1ULL << ShiftAmt), VT);
2835 Tmp3 = DAG.getSetCC(TLI.getSetCCResultTy(),
2836 Node->getOperand(0), Tmp2, ISD::SETLT);
2837 True = DAG.getNode(ISD::FP_TO_SINT, NVT, Node->getOperand(0));
2838 False = DAG.getNode(ISD::FP_TO_SINT, NVT,
2839 DAG.getNode(ISD::FSUB, VT, Node->getOperand(0),
2841 False = DAG.getNode(ISD::XOR, NVT, False,
2842 DAG.getConstant(1ULL << ShiftAmt, NVT));
2843 Result = DAG.getNode(ISD::SELECT, NVT, Tmp3, True, False);
2846 assert(0 && "Do not know how to expand FP_TO_SINT yet!");
2852 assert(0 && "Shouldn't need to expand other operators here!");
2854 Tmp1 = PromoteOp(Node->getOperand(0));
2855 Result = DAG.UpdateNodeOperands(Result, LegalizeOp(Tmp1));
2856 Result = LegalizeOp(Result);
2861 case ISD::ANY_EXTEND:
2862 case ISD::ZERO_EXTEND:
2863 case ISD::SIGN_EXTEND:
2864 case ISD::FP_EXTEND:
2866 switch (getTypeAction(Node->getOperand(0).getValueType())) {
2867 case Expand: assert(0 && "Shouldn't need to expand other operators here!");
2869 Tmp1 = LegalizeOp(Node->getOperand(0));
2870 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2873 switch (Node->getOpcode()) {
2874 case ISD::ANY_EXTEND:
2875 Tmp1 = PromoteOp(Node->getOperand(0));
2876 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Tmp1);
2878 case ISD::ZERO_EXTEND:
2879 Result = PromoteOp(Node->getOperand(0));
2880 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Result);
2881 Result = DAG.getZeroExtendInReg(Result,
2882 Node->getOperand(0).getValueType());
2884 case ISD::SIGN_EXTEND:
2885 Result = PromoteOp(Node->getOperand(0));
2886 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Result);
2887 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(),
2889 DAG.getValueType(Node->getOperand(0).getValueType()));
2891 case ISD::FP_EXTEND:
2892 Result = PromoteOp(Node->getOperand(0));
2893 if (Result.getValueType() != Op.getValueType())
2894 // Dynamically dead while we have only 2 FP types.
2895 Result = DAG.getNode(ISD::FP_EXTEND, Op.getValueType(), Result);
2898 Result = PromoteOp(Node->getOperand(0));
2899 Result = DAG.getNode(Node->getOpcode(), Op.getValueType(), Result);
2904 case ISD::FP_ROUND_INREG:
2905 case ISD::SIGN_EXTEND_INREG: {
2906 Tmp1 = LegalizeOp(Node->getOperand(0));
2907 MVT::ValueType ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT();
2909 // If this operation is not supported, convert it to a shl/shr or load/store
2911 switch (TLI.getOperationAction(Node->getOpcode(), ExtraVT)) {
2912 default: assert(0 && "This action not supported for this op yet!");
2913 case TargetLowering::Legal:
2914 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
2916 case TargetLowering::Expand:
2917 // If this is an integer extend and shifts are supported, do that.
2918 if (Node->getOpcode() == ISD::SIGN_EXTEND_INREG) {
2919 // NOTE: we could fall back on load/store here too for targets without
2920 // SAR. However, it is doubtful that any exist.
2921 unsigned BitsDiff = MVT::getSizeInBits(Node->getValueType(0)) -
2922 MVT::getSizeInBits(ExtraVT);
2923 SDOperand ShiftCst = DAG.getConstant(BitsDiff, TLI.getShiftAmountTy());
2924 Result = DAG.getNode(ISD::SHL, Node->getValueType(0),
2925 Node->getOperand(0), ShiftCst);
2926 Result = DAG.getNode(ISD::SRA, Node->getValueType(0),
2928 } else if (Node->getOpcode() == ISD::FP_ROUND_INREG) {
2929 // The only way we can lower this is to turn it into a TRUNCSTORE,
2930 // EXTLOAD pair, targetting a temporary location (a stack slot).
2932 // NOTE: there is a choice here between constantly creating new stack
2933 // slots and always reusing the same one. We currently always create
2934 // new ones, as reuse may inhibit scheduling.
2935 const Type *Ty = MVT::getTypeForValueType(ExtraVT);
2936 unsigned TySize = (unsigned)TLI.getTargetData()->getTypeSize(Ty);
2937 unsigned Align = TLI.getTargetData()->getTypeAlignment(Ty);
2938 MachineFunction &MF = DAG.getMachineFunction();
2940 MF.getFrameInfo()->CreateStackObject((unsigned)TySize, Align);
2941 SDOperand StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy());
2942 Result = DAG.getTruncStore(DAG.getEntryNode(), Node->getOperand(0),
2943 StackSlot, NULL, 0, ExtraVT);
2944 Result = DAG.getExtLoad(ISD::EXTLOAD, Node->getValueType(0),
2945 Result, StackSlot, NULL, 0, ExtraVT);
2947 assert(0 && "Unknown op");
2955 assert(Result.getValueType() == Op.getValueType() &&
2956 "Bad legalization!");
2958 // Make sure that the generated code is itself legal.
2960 Result = LegalizeOp(Result);
2962 // Note that LegalizeOp may be reentered even from single-use nodes, which
2963 // means that we always must cache transformed nodes.
2964 AddLegalizedOperand(Op, Result);
2968 /// PromoteOp - Given an operation that produces a value in an invalid type,
2969 /// promote it to compute the value into a larger type. The produced value will
2970 /// have the correct bits for the low portion of the register, but no guarantee
2971 /// is made about the top bits: it may be zero, sign-extended, or garbage.
2972 SDOperand SelectionDAGLegalize::PromoteOp(SDOperand Op) {
2973 MVT::ValueType VT = Op.getValueType();
2974 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT);
2975 assert(getTypeAction(VT) == Promote &&
2976 "Caller should expand or legalize operands that are not promotable!");
2977 assert(NVT > VT && MVT::isInteger(NVT) == MVT::isInteger(VT) &&
2978 "Cannot promote to smaller type!");
2980 SDOperand Tmp1, Tmp2, Tmp3;
2982 SDNode *Node = Op.Val;
2984 std::map<SDOperand, SDOperand>::iterator I = PromotedNodes.find(Op);
2985 if (I != PromotedNodes.end()) return I->second;
2987 switch (Node->getOpcode()) {
2988 case ISD::CopyFromReg:
2989 assert(0 && "CopyFromReg must be legal!");
2992 cerr << "NODE: "; Node->dump(); cerr << "\n";
2994 assert(0 && "Do not know how to promote this operator!");
2997 Result = DAG.getNode(ISD::UNDEF, NVT);
3001 Result = DAG.getNode(ISD::SIGN_EXTEND, NVT, Op);
3003 Result = DAG.getNode(ISD::ZERO_EXTEND, NVT, Op);
3004 assert(isa<ConstantSDNode>(Result) && "Didn't constant fold zext?");
3006 case ISD::ConstantFP:
3007 Result = DAG.getNode(ISD::FP_EXTEND, NVT, Op);
3008 assert(isa<ConstantFPSDNode>(Result) && "Didn't constant fold fp_extend?");
3012 assert(isTypeLegal(TLI.getSetCCResultTy()) && "SetCC type is not legal??");
3013 Result = DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(),Node->getOperand(0),
3014 Node->getOperand(1), Node->getOperand(2));
3018 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3020 Result = LegalizeOp(Node->getOperand(0));
3021 assert(Result.getValueType() >= NVT &&
3022 "This truncation doesn't make sense!");
3023 if (Result.getValueType() > NVT) // Truncate to NVT instead of VT
3024 Result = DAG.getNode(ISD::TRUNCATE, NVT, Result);
3027 // The truncation is not required, because we don't guarantee anything
3028 // about high bits anyway.
3029 Result = PromoteOp(Node->getOperand(0));
3032 ExpandOp(Node->getOperand(0), Tmp1, Tmp2);
3033 // Truncate the low part of the expanded value to the result type
3034 Result = DAG.getNode(ISD::TRUNCATE, NVT, Tmp1);
3037 case ISD::SIGN_EXTEND:
3038 case ISD::ZERO_EXTEND:
3039 case ISD::ANY_EXTEND:
3040 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3041 case Expand: assert(0 && "BUG: Smaller reg should have been promoted!");
3043 // Input is legal? Just do extend all the way to the larger type.
3044 Result = DAG.getNode(Node->getOpcode(), NVT, Node->getOperand(0));
3047 // Promote the reg if it's smaller.
3048 Result = PromoteOp(Node->getOperand(0));
3049 // The high bits are not guaranteed to be anything. Insert an extend.
3050 if (Node->getOpcode() == ISD::SIGN_EXTEND)
3051 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Result,
3052 DAG.getValueType(Node->getOperand(0).getValueType()));
3053 else if (Node->getOpcode() == ISD::ZERO_EXTEND)
3054 Result = DAG.getZeroExtendInReg(Result,
3055 Node->getOperand(0).getValueType());
3059 case ISD::BIT_CONVERT:
3060 Result = ExpandBIT_CONVERT(Node->getValueType(0), Node->getOperand(0));
3061 Result = PromoteOp(Result);
3064 case ISD::FP_EXTEND:
3065 assert(0 && "Case not implemented. Dynamically dead with 2 FP types!");
3067 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3068 case Expand: assert(0 && "BUG: Cannot expand FP regs!");
3069 case Promote: assert(0 && "Unreachable with 2 FP types!");
3071 // Input is legal? Do an FP_ROUND_INREG.
3072 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Node->getOperand(0),
3073 DAG.getValueType(VT));
3078 case ISD::SINT_TO_FP:
3079 case ISD::UINT_TO_FP:
3080 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3082 // No extra round required here.
3083 Result = DAG.getNode(Node->getOpcode(), NVT, Node->getOperand(0));
3087 Result = PromoteOp(Node->getOperand(0));
3088 if (Node->getOpcode() == ISD::SINT_TO_FP)
3089 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(),
3091 DAG.getValueType(Node->getOperand(0).getValueType()));
3093 Result = DAG.getZeroExtendInReg(Result,
3094 Node->getOperand(0).getValueType());
3095 // No extra round required here.
3096 Result = DAG.getNode(Node->getOpcode(), NVT, Result);
3099 Result = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP, NVT,
3100 Node->getOperand(0));
3101 // Round if we cannot tolerate excess precision.
3102 if (NoExcessFPPrecision)
3103 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
3104 DAG.getValueType(VT));
3109 case ISD::SIGN_EXTEND_INREG:
3110 Result = PromoteOp(Node->getOperand(0));
3111 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Result,
3112 Node->getOperand(1));
3114 case ISD::FP_TO_SINT:
3115 case ISD::FP_TO_UINT:
3116 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3118 Tmp1 = Node->getOperand(0);
3121 // The input result is prerounded, so we don't have to do anything
3123 Tmp1 = PromoteOp(Node->getOperand(0));
3126 assert(0 && "not implemented");
3128 // If we're promoting a UINT to a larger size, check to see if the new node
3129 // will be legal. If it isn't, check to see if FP_TO_SINT is legal, since
3130 // we can use that instead. This allows us to generate better code for
3131 // FP_TO_UINT for small destination sizes on targets where FP_TO_UINT is not
3132 // legal, such as PowerPC.
3133 if (Node->getOpcode() == ISD::FP_TO_UINT &&
3134 !TLI.isOperationLegal(ISD::FP_TO_UINT, NVT) &&
3135 (TLI.isOperationLegal(ISD::FP_TO_SINT, NVT) ||
3136 TLI.getOperationAction(ISD::FP_TO_SINT, NVT)==TargetLowering::Custom)){
3137 Result = DAG.getNode(ISD::FP_TO_SINT, NVT, Tmp1);
3139 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
3145 Tmp1 = PromoteOp(Node->getOperand(0));
3146 assert(Tmp1.getValueType() == NVT);
3147 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
3148 // NOTE: we do not have to do any extra rounding here for
3149 // NoExcessFPPrecision, because we know the input will have the appropriate
3150 // precision, and these operations don't modify precision at all.
3156 Tmp1 = PromoteOp(Node->getOperand(0));
3157 assert(Tmp1.getValueType() == NVT);
3158 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
3159 if (NoExcessFPPrecision)
3160 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
3161 DAG.getValueType(VT));
3170 // The input may have strange things in the top bits of the registers, but
3171 // these operations don't care. They may have weird bits going out, but
3172 // that too is okay if they are integer operations.
3173 Tmp1 = PromoteOp(Node->getOperand(0));
3174 Tmp2 = PromoteOp(Node->getOperand(1));
3175 assert(Tmp1.getValueType() == NVT && Tmp2.getValueType() == NVT);
3176 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
3181 Tmp1 = PromoteOp(Node->getOperand(0));
3182 Tmp2 = PromoteOp(Node->getOperand(1));
3183 assert(Tmp1.getValueType() == NVT && Tmp2.getValueType() == NVT);
3184 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
3186 // Floating point operations will give excess precision that we may not be
3187 // able to tolerate. If we DO allow excess precision, just leave it,
3188 // otherwise excise it.
3189 // FIXME: Why would we need to round FP ops more than integer ones?
3190 // Is Round(Add(Add(A,B),C)) != Round(Add(Round(Add(A,B)), C))
3191 if (NoExcessFPPrecision)
3192 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
3193 DAG.getValueType(VT));
3198 // These operators require that their input be sign extended.
3199 Tmp1 = PromoteOp(Node->getOperand(0));
3200 Tmp2 = PromoteOp(Node->getOperand(1));
3201 if (MVT::isInteger(NVT)) {
3202 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1,
3203 DAG.getValueType(VT));
3204 Tmp2 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp2,
3205 DAG.getValueType(VT));
3207 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
3209 // Perform FP_ROUND: this is probably overly pessimistic.
3210 if (MVT::isFloatingPoint(NVT) && NoExcessFPPrecision)
3211 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
3212 DAG.getValueType(VT));
3216 case ISD::FCOPYSIGN:
3217 // These operators require that their input be fp extended.
3218 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3220 Tmp1 = LegalizeOp(Node->getOperand(0));
3223 Tmp1 = PromoteOp(Node->getOperand(0));
3226 assert(0 && "not implemented");
3228 switch (getTypeAction(Node->getOperand(1).getValueType())) {
3230 Tmp2 = LegalizeOp(Node->getOperand(1));
3233 Tmp2 = PromoteOp(Node->getOperand(1));
3236 assert(0 && "not implemented");
3238 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
3240 // Perform FP_ROUND: this is probably overly pessimistic.
3241 if (NoExcessFPPrecision && Node->getOpcode() != ISD::FCOPYSIGN)
3242 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
3243 DAG.getValueType(VT));
3248 // These operators require that their input be zero extended.
3249 Tmp1 = PromoteOp(Node->getOperand(0));
3250 Tmp2 = PromoteOp(Node->getOperand(1));
3251 assert(MVT::isInteger(NVT) && "Operators don't apply to FP!");
3252 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT);
3253 Tmp2 = DAG.getZeroExtendInReg(Tmp2, VT);
3254 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
3258 Tmp1 = PromoteOp(Node->getOperand(0));
3259 Result = DAG.getNode(ISD::SHL, NVT, Tmp1, Node->getOperand(1));
3262 // The input value must be properly sign extended.
3263 Tmp1 = PromoteOp(Node->getOperand(0));
3264 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1,
3265 DAG.getValueType(VT));
3266 Result = DAG.getNode(ISD::SRA, NVT, Tmp1, Node->getOperand(1));
3269 // The input value must be properly zero extended.
3270 Tmp1 = PromoteOp(Node->getOperand(0));
3271 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT);
3272 Result = DAG.getNode(ISD::SRL, NVT, Tmp1, Node->getOperand(1));
3276 Tmp1 = Node->getOperand(0); // Get the chain.
3277 Tmp2 = Node->getOperand(1); // Get the pointer.
3278 if (TLI.getOperationAction(ISD::VAARG, VT) == TargetLowering::Custom) {
3279 Tmp3 = DAG.getVAArg(VT, Tmp1, Tmp2, Node->getOperand(2));
3280 Result = TLI.CustomPromoteOperation(Tmp3, DAG);
3282 SrcValueSDNode *SV = cast<SrcValueSDNode>(Node->getOperand(2));
3283 SDOperand VAList = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp2,
3284 SV->getValue(), SV->getOffset());
3285 // Increment the pointer, VAList, to the next vaarg
3286 Tmp3 = DAG.getNode(ISD::ADD, TLI.getPointerTy(), VAList,
3287 DAG.getConstant(MVT::getSizeInBits(VT)/8,
3288 TLI.getPointerTy()));
3289 // Store the incremented VAList to the legalized pointer
3290 Tmp3 = DAG.getStore(VAList.getValue(1), Tmp3, Tmp2, SV->getValue(),
3292 // Load the actual argument out of the pointer VAList
3293 Result = DAG.getExtLoad(ISD::EXTLOAD, NVT, Tmp3, VAList, NULL, 0, VT);
3295 // Remember that we legalized the chain.
3296 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
3300 LoadSDNode *LD = cast<LoadSDNode>(Node);
3301 ISD::LoadExtType ExtType = ISD::isNON_EXTLoad(Node)
3302 ? ISD::EXTLOAD : LD->getExtensionType();
3303 Result = DAG.getExtLoad(ExtType, NVT,
3304 LD->getChain(), LD->getBasePtr(),
3305 LD->getSrcValue(), LD->getSrcValueOffset(),
3307 // Remember that we legalized the chain.
3308 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
3312 Tmp2 = PromoteOp(Node->getOperand(1)); // Legalize the op0
3313 Tmp3 = PromoteOp(Node->getOperand(2)); // Legalize the op1
3314 Result = DAG.getNode(ISD::SELECT, NVT, Node->getOperand(0), Tmp2, Tmp3);
3316 case ISD::SELECT_CC:
3317 Tmp2 = PromoteOp(Node->getOperand(2)); // True
3318 Tmp3 = PromoteOp(Node->getOperand(3)); // False
3319 Result = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0),
3320 Node->getOperand(1), Tmp2, Tmp3, Node->getOperand(4));
3323 Tmp1 = Node->getOperand(0);
3324 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1);
3325 Tmp1 = DAG.getNode(ISD::BSWAP, NVT, Tmp1);
3326 Result = DAG.getNode(ISD::SRL, NVT, Tmp1,
3327 DAG.getConstant(getSizeInBits(NVT) - getSizeInBits(VT),
3328 TLI.getShiftAmountTy()));
3333 // Zero extend the argument
3334 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Node->getOperand(0));
3335 // Perform the larger operation, then subtract if needed.
3336 Tmp1 = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
3337 switch(Node->getOpcode()) {
3342 // if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT)
3343 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), Tmp1,
3344 DAG.getConstant(getSizeInBits(NVT), NVT), ISD::SETEQ);
3345 Result = DAG.getNode(ISD::SELECT, NVT, Tmp2,
3346 DAG.getConstant(getSizeInBits(VT), NVT), Tmp1);
3349 //Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT))
3350 Result = DAG.getNode(ISD::SUB, NVT, Tmp1,
3351 DAG.getConstant(getSizeInBits(NVT) -
3352 getSizeInBits(VT), NVT));
3356 case ISD::VEXTRACT_VECTOR_ELT:
3357 Result = PromoteOp(LowerVEXTRACT_VECTOR_ELT(Op));
3359 case ISD::EXTRACT_VECTOR_ELT:
3360 Result = PromoteOp(ExpandEXTRACT_VECTOR_ELT(Op));
3364 assert(Result.Val && "Didn't set a result!");
3366 // Make sure the result is itself legal.
3367 Result = LegalizeOp(Result);
3369 // Remember that we promoted this!
3370 AddPromotedOperand(Op, Result);
3374 /// LowerVEXTRACT_VECTOR_ELT - Lower a VEXTRACT_VECTOR_ELT operation into a
3375 /// EXTRACT_VECTOR_ELT operation, to memory operations, or to scalar code based
3376 /// on the vector type. The return type of this matches the element type of the
3377 /// vector, which may not be legal for the target.
3378 SDOperand SelectionDAGLegalize::LowerVEXTRACT_VECTOR_ELT(SDOperand Op) {
3379 // We know that operand #0 is the Vec vector. If the index is a constant
3380 // or if the invec is a supported hardware type, we can use it. Otherwise,
3381 // lower to a store then an indexed load.
3382 SDOperand Vec = Op.getOperand(0);
3383 SDOperand Idx = LegalizeOp(Op.getOperand(1));
3385 SDNode *InVal = Vec.Val;
3386 unsigned NumElems = cast<ConstantSDNode>(*(InVal->op_end()-2))->getValue();
3387 MVT::ValueType EVT = cast<VTSDNode>(*(InVal->op_end()-1))->getVT();
3389 // Figure out if there is a Packed type corresponding to this Vector
3390 // type. If so, convert to the packed type.
3391 MVT::ValueType TVT = MVT::getVectorType(EVT, NumElems);
3392 if (TVT != MVT::Other && TLI.isTypeLegal(TVT)) {
3393 // Turn this into a packed extract_vector_elt operation.
3394 Vec = PackVectorOp(Vec, TVT);
3395 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, Op.getValueType(), Vec, Idx);
3396 } else if (NumElems == 1) {
3397 // This must be an access of the only element. Return it.
3398 return PackVectorOp(Vec, EVT);
3399 } else if (ConstantSDNode *CIdx = dyn_cast<ConstantSDNode>(Idx)) {
3401 SplitVectorOp(Vec, Lo, Hi);
3402 if (CIdx->getValue() < NumElems/2) {
3406 Idx = DAG.getConstant(CIdx->getValue() - NumElems/2, Idx.getValueType());
3409 // It's now an extract from the appropriate high or low part. Recurse.
3410 Op = DAG.UpdateNodeOperands(Op, Vec, Idx);
3411 return LowerVEXTRACT_VECTOR_ELT(Op);
3413 // Variable index case for extract element.
3414 // FIXME: IMPLEMENT STORE/LOAD lowering. Need alignment of stack slot!!
3415 assert(0 && "unimp!");
3420 /// ExpandEXTRACT_VECTOR_ELT - Expand an EXTRACT_VECTOR_ELT operation into
3422 SDOperand SelectionDAGLegalize::ExpandEXTRACT_VECTOR_ELT(SDOperand Op) {
3423 SDOperand Vector = Op.getOperand(0);
3424 SDOperand Idx = Op.getOperand(1);
3426 // If the target doesn't support this, store the value to a temporary
3427 // stack slot, then LOAD the scalar element back out.
3428 SDOperand StackPtr = CreateStackTemporary(Vector.getValueType());
3429 SDOperand Ch = DAG.getStore(DAG.getEntryNode(), Vector, StackPtr, NULL, 0);
3431 // Add the offset to the index.
3432 unsigned EltSize = MVT::getSizeInBits(Op.getValueType())/8;
3433 Idx = DAG.getNode(ISD::MUL, Idx.getValueType(), Idx,
3434 DAG.getConstant(EltSize, Idx.getValueType()));
3435 StackPtr = DAG.getNode(ISD::ADD, Idx.getValueType(), Idx, StackPtr);
3437 return DAG.getLoad(Op.getValueType(), Ch, StackPtr, NULL, 0);
3441 /// LegalizeSetCCOperands - Attempts to create a legal LHS and RHS for a SETCC
3442 /// with condition CC on the current target. This usually involves legalizing
3443 /// or promoting the arguments. In the case where LHS and RHS must be expanded,
3444 /// there may be no choice but to create a new SetCC node to represent the
3445 /// legalized value of setcc lhs, rhs. In this case, the value is returned in
3446 /// LHS, and the SDOperand returned in RHS has a nil SDNode value.
3447 void SelectionDAGLegalize::LegalizeSetCCOperands(SDOperand &LHS,
3450 SDOperand Tmp1, Tmp2, Result;
3452 switch (getTypeAction(LHS.getValueType())) {
3454 Tmp1 = LegalizeOp(LHS); // LHS
3455 Tmp2 = LegalizeOp(RHS); // RHS
3458 Tmp1 = PromoteOp(LHS); // LHS
3459 Tmp2 = PromoteOp(RHS); // RHS
3461 // If this is an FP compare, the operands have already been extended.
3462 if (MVT::isInteger(LHS.getValueType())) {
3463 MVT::ValueType VT = LHS.getValueType();
3464 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT);
3466 // Otherwise, we have to insert explicit sign or zero extends. Note
3467 // that we could insert sign extends for ALL conditions, but zero extend
3468 // is cheaper on many machines (an AND instead of two shifts), so prefer
3470 switch (cast<CondCodeSDNode>(CC)->get()) {
3471 default: assert(0 && "Unknown integer comparison!");
3478 // ALL of these operations will work if we either sign or zero extend
3479 // the operands (including the unsigned comparisons!). Zero extend is
3480 // usually a simpler/cheaper operation, so prefer it.
3481 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT);
3482 Tmp2 = DAG.getZeroExtendInReg(Tmp2, VT);
3488 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1,
3489 DAG.getValueType(VT));
3490 Tmp2 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp2,
3491 DAG.getValueType(VT));
3497 SDOperand LHSLo, LHSHi, RHSLo, RHSHi;
3498 ExpandOp(LHS, LHSLo, LHSHi);
3499 ExpandOp(RHS, RHSLo, RHSHi);
3500 switch (cast<CondCodeSDNode>(CC)->get()) {
3504 if (ConstantSDNode *RHSCST = dyn_cast<ConstantSDNode>(RHSLo))
3505 if (RHSCST->isAllOnesValue()) {
3506 // Comparison to -1.
3507 Tmp1 = DAG.getNode(ISD::AND, LHSLo.getValueType(), LHSLo, LHSHi);
3512 Tmp1 = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSLo, RHSLo);
3513 Tmp2 = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSHi, RHSHi);
3514 Tmp1 = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp2);
3515 Tmp2 = DAG.getConstant(0, Tmp1.getValueType());
3518 // If this is a comparison of the sign bit, just look at the top part.
3520 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(RHS))
3521 if ((cast<CondCodeSDNode>(CC)->get() == ISD::SETLT &&
3522 CST->getValue() == 0) || // X < 0
3523 (cast<CondCodeSDNode>(CC)->get() == ISD::SETGT &&
3524 CST->isAllOnesValue())) { // X > -1
3530 // FIXME: This generated code sucks.
3531 ISD::CondCode LowCC;
3532 switch (cast<CondCodeSDNode>(CC)->get()) {
3533 default: assert(0 && "Unknown integer setcc!");
3535 case ISD::SETULT: LowCC = ISD::SETULT; break;
3537 case ISD::SETUGT: LowCC = ISD::SETUGT; break;
3539 case ISD::SETULE: LowCC = ISD::SETULE; break;
3541 case ISD::SETUGE: LowCC = ISD::SETUGE; break;
3544 // Tmp1 = lo(op1) < lo(op2) // Always unsigned comparison
3545 // Tmp2 = hi(op1) < hi(op2) // Signedness depends on operands
3546 // dest = hi(op1) == hi(op2) ? Tmp1 : Tmp2;
3548 // NOTE: on targets without efficient SELECT of bools, we can always use
3549 // this identity: (B1 ? B2 : B3) --> (B1 & B2)|(!B1&B3)
3550 Tmp1 = DAG.getSetCC(TLI.getSetCCResultTy(), LHSLo, RHSLo, LowCC);
3551 Tmp2 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(), LHSHi, RHSHi, CC);
3552 Result = DAG.getSetCC(TLI.getSetCCResultTy(), LHSHi, RHSHi, ISD::SETEQ);
3553 Result = LegalizeOp(DAG.getNode(ISD::SELECT, Tmp1.getValueType(),
3554 Result, Tmp1, Tmp2));
3563 /// ExpandBIT_CONVERT - Expand a BIT_CONVERT node into a store/load combination.
3564 /// The resultant code need not be legal. Note that SrcOp is the input operand
3565 /// to the BIT_CONVERT, not the BIT_CONVERT node itself.
3566 SDOperand SelectionDAGLegalize::ExpandBIT_CONVERT(MVT::ValueType DestVT,
3568 // Create the stack frame object.
3569 SDOperand FIPtr = CreateStackTemporary(DestVT);
3571 // Emit a store to the stack slot.
3572 SDOperand Store = DAG.getStore(DAG.getEntryNode(), SrcOp, FIPtr, NULL, 0);
3573 // Result is a load from the stack slot.
3574 return DAG.getLoad(DestVT, Store, FIPtr, NULL, 0);
3577 SDOperand SelectionDAGLegalize::ExpandSCALAR_TO_VECTOR(SDNode *Node) {
3578 // Create a vector sized/aligned stack slot, store the value to element #0,
3579 // then load the whole vector back out.
3580 SDOperand StackPtr = CreateStackTemporary(Node->getValueType(0));
3581 SDOperand Ch = DAG.getStore(DAG.getEntryNode(), Node->getOperand(0), StackPtr,
3583 return DAG.getLoad(Node->getValueType(0), Ch, StackPtr, NULL, 0);
3587 /// ExpandBUILD_VECTOR - Expand a BUILD_VECTOR node on targets that don't
3588 /// support the operation, but do support the resultant packed vector type.
3589 SDOperand SelectionDAGLegalize::ExpandBUILD_VECTOR(SDNode *Node) {
3591 // If the only non-undef value is the low element, turn this into a
3592 // SCALAR_TO_VECTOR node. If this is { X, X, X, X }, determine X.
3593 unsigned NumElems = Node->getNumOperands();
3594 bool isOnlyLowElement = true;
3595 SDOperand SplatValue = Node->getOperand(0);
3596 std::map<SDOperand, std::vector<unsigned> > Values;
3597 Values[SplatValue].push_back(0);
3598 bool isConstant = true;
3599 if (!isa<ConstantFPSDNode>(SplatValue) && !isa<ConstantSDNode>(SplatValue) &&
3600 SplatValue.getOpcode() != ISD::UNDEF)
3603 for (unsigned i = 1; i < NumElems; ++i) {
3604 SDOperand V = Node->getOperand(i);
3605 Values[V].push_back(i);
3606 if (V.getOpcode() != ISD::UNDEF)
3607 isOnlyLowElement = false;
3608 if (SplatValue != V)
3609 SplatValue = SDOperand(0,0);
3611 // If this isn't a constant element or an undef, we can't use a constant
3613 if (!isa<ConstantFPSDNode>(V) && !isa<ConstantSDNode>(V) &&
3614 V.getOpcode() != ISD::UNDEF)
3618 if (isOnlyLowElement) {
3619 // If the low element is an undef too, then this whole things is an undef.
3620 if (Node->getOperand(0).getOpcode() == ISD::UNDEF)
3621 return DAG.getNode(ISD::UNDEF, Node->getValueType(0));
3622 // Otherwise, turn this into a scalar_to_vector node.
3623 return DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0),
3624 Node->getOperand(0));
3627 // If all elements are constants, create a load from the constant pool.
3629 MVT::ValueType VT = Node->getValueType(0);
3631 MVT::getTypeForValueType(Node->getOperand(0).getValueType());
3632 std::vector<Constant*> CV;
3633 for (unsigned i = 0, e = NumElems; i != e; ++i) {
3634 if (ConstantFPSDNode *V =
3635 dyn_cast<ConstantFPSDNode>(Node->getOperand(i))) {
3636 CV.push_back(ConstantFP::get(OpNTy, V->getValue()));
3637 } else if (ConstantSDNode *V =
3638 dyn_cast<ConstantSDNode>(Node->getOperand(i))) {
3639 CV.push_back(ConstantInt::get(OpNTy, V->getValue()));
3641 assert(Node->getOperand(i).getOpcode() == ISD::UNDEF);
3642 CV.push_back(UndefValue::get(OpNTy));
3645 Constant *CP = ConstantPacked::get(CV);
3646 SDOperand CPIdx = DAG.getConstantPool(CP, TLI.getPointerTy());
3647 return DAG.getLoad(VT, DAG.getEntryNode(), CPIdx, NULL, 0);
3650 if (SplatValue.Val) { // Splat of one value?
3651 // Build the shuffle constant vector: <0, 0, 0, 0>
3652 MVT::ValueType MaskVT =
3653 MVT::getIntVectorWithNumElements(NumElems);
3654 SDOperand Zero = DAG.getConstant(0, MVT::getVectorBaseType(MaskVT));
3655 std::vector<SDOperand> ZeroVec(NumElems, Zero);
3656 SDOperand SplatMask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
3657 &ZeroVec[0], ZeroVec.size());
3659 // If the target supports VECTOR_SHUFFLE and this shuffle mask, use it.
3660 if (isShuffleLegal(Node->getValueType(0), SplatMask)) {
3661 // Get the splatted value into the low element of a vector register.
3662 SDOperand LowValVec =
3663 DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0), SplatValue);
3665 // Return shuffle(LowValVec, undef, <0,0,0,0>)
3666 return DAG.getNode(ISD::VECTOR_SHUFFLE, Node->getValueType(0), LowValVec,
3667 DAG.getNode(ISD::UNDEF, Node->getValueType(0)),
3672 // If there are only two unique elements, we may be able to turn this into a
3674 if (Values.size() == 2) {
3675 // Build the shuffle constant vector: e.g. <0, 4, 0, 4>
3676 MVT::ValueType MaskVT =
3677 MVT::getIntVectorWithNumElements(NumElems);
3678 std::vector<SDOperand> MaskVec(NumElems);
3680 for (std::map<SDOperand,std::vector<unsigned> >::iterator I=Values.begin(),
3681 E = Values.end(); I != E; ++I) {
3682 for (std::vector<unsigned>::iterator II = I->second.begin(),
3683 EE = I->second.end(); II != EE; ++II)
3684 MaskVec[*II] = DAG.getConstant(i, MVT::getVectorBaseType(MaskVT));
3687 SDOperand ShuffleMask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
3688 &MaskVec[0], MaskVec.size());
3690 // If the target supports VECTOR_SHUFFLE and this shuffle mask, use it.
3691 if (TLI.isOperationLegal(ISD::SCALAR_TO_VECTOR, Node->getValueType(0)) &&
3692 isShuffleLegal(Node->getValueType(0), ShuffleMask)) {
3693 SmallVector<SDOperand, 8> Ops;
3694 for(std::map<SDOperand,std::vector<unsigned> >::iterator I=Values.begin(),
3695 E = Values.end(); I != E; ++I) {
3696 SDOperand Op = DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0),
3700 Ops.push_back(ShuffleMask);
3702 // Return shuffle(LoValVec, HiValVec, <0,1,0,1>)
3703 return DAG.getNode(ISD::VECTOR_SHUFFLE, Node->getValueType(0),
3704 &Ops[0], Ops.size());
3708 // Otherwise, we can't handle this case efficiently. Allocate a sufficiently
3709 // aligned object on the stack, store each element into it, then load
3710 // the result as a vector.
3711 MVT::ValueType VT = Node->getValueType(0);
3712 // Create the stack frame object.
3713 SDOperand FIPtr = CreateStackTemporary(VT);
3715 // Emit a store of each element to the stack slot.
3716 SmallVector<SDOperand, 8> Stores;
3717 unsigned TypeByteSize =
3718 MVT::getSizeInBits(Node->getOperand(0).getValueType())/8;
3719 // Store (in the right endianness) the elements to memory.
3720 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
3721 // Ignore undef elements.
3722 if (Node->getOperand(i).getOpcode() == ISD::UNDEF) continue;
3724 unsigned Offset = TypeByteSize*i;
3726 SDOperand Idx = DAG.getConstant(Offset, FIPtr.getValueType());
3727 Idx = DAG.getNode(ISD::ADD, FIPtr.getValueType(), FIPtr, Idx);
3729 Stores.push_back(DAG.getStore(DAG.getEntryNode(), Node->getOperand(i), Idx,
3733 SDOperand StoreChain;
3734 if (!Stores.empty()) // Not all undef elements?
3735 StoreChain = DAG.getNode(ISD::TokenFactor, MVT::Other,
3736 &Stores[0], Stores.size());
3738 StoreChain = DAG.getEntryNode();
3740 // Result is a load from the stack slot.
3741 return DAG.getLoad(VT, StoreChain, FIPtr, NULL, 0);
3744 /// CreateStackTemporary - Create a stack temporary, suitable for holding the
3745 /// specified value type.
3746 SDOperand SelectionDAGLegalize::CreateStackTemporary(MVT::ValueType VT) {
3747 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo();
3748 unsigned ByteSize = MVT::getSizeInBits(VT)/8;
3749 int FrameIdx = FrameInfo->CreateStackObject(ByteSize, ByteSize);
3750 return DAG.getFrameIndex(FrameIdx, TLI.getPointerTy());
3753 void SelectionDAGLegalize::ExpandShiftParts(unsigned NodeOp,
3754 SDOperand Op, SDOperand Amt,
3755 SDOperand &Lo, SDOperand &Hi) {
3756 // Expand the subcomponents.
3757 SDOperand LHSL, LHSH;
3758 ExpandOp(Op, LHSL, LHSH);
3760 SDOperand Ops[] = { LHSL, LHSH, Amt };
3761 MVT::ValueType VT = LHSL.getValueType();
3762 Lo = DAG.getNode(NodeOp, DAG.getNodeValueTypes(VT, VT), 2, Ops, 3);
3763 Hi = Lo.getValue(1);
3767 /// ExpandShift - Try to find a clever way to expand this shift operation out to
3768 /// smaller elements. If we can't find a way that is more efficient than a
3769 /// libcall on this target, return false. Otherwise, return true with the
3770 /// low-parts expanded into Lo and Hi.
3771 bool SelectionDAGLegalize::ExpandShift(unsigned Opc, SDOperand Op,SDOperand Amt,
3772 SDOperand &Lo, SDOperand &Hi) {
3773 assert((Opc == ISD::SHL || Opc == ISD::SRA || Opc == ISD::SRL) &&
3774 "This is not a shift!");
3776 MVT::ValueType NVT = TLI.getTypeToTransformTo(Op.getValueType());
3777 SDOperand ShAmt = LegalizeOp(Amt);
3778 MVT::ValueType ShTy = ShAmt.getValueType();
3779 unsigned VTBits = MVT::getSizeInBits(Op.getValueType());
3780 unsigned NVTBits = MVT::getSizeInBits(NVT);
3782 // Handle the case when Amt is an immediate. Other cases are currently broken
3783 // and are disabled.
3784 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Amt.Val)) {
3785 unsigned Cst = CN->getValue();
3786 // Expand the incoming operand to be shifted, so that we have its parts
3788 ExpandOp(Op, InL, InH);
3792 Lo = DAG.getConstant(0, NVT);
3793 Hi = DAG.getConstant(0, NVT);
3794 } else if (Cst > NVTBits) {
3795 Lo = DAG.getConstant(0, NVT);
3796 Hi = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Cst-NVTBits,ShTy));
3797 } else if (Cst == NVTBits) {
3798 Lo = DAG.getConstant(0, NVT);
3801 Lo = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Cst, ShTy));
3802 Hi = DAG.getNode(ISD::OR, NVT,
3803 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(Cst, ShTy)),
3804 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(NVTBits-Cst, ShTy)));
3809 Lo = DAG.getConstant(0, NVT);
3810 Hi = DAG.getConstant(0, NVT);
3811 } else if (Cst > NVTBits) {
3812 Lo = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Cst-NVTBits,ShTy));
3813 Hi = DAG.getConstant(0, NVT);
3814 } else if (Cst == NVTBits) {
3816 Hi = DAG.getConstant(0, NVT);
3818 Lo = DAG.getNode(ISD::OR, NVT,
3819 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(Cst, ShTy)),
3820 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(NVTBits-Cst, ShTy)));
3821 Hi = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Cst, ShTy));
3826 Hi = Lo = DAG.getNode(ISD::SRA, NVT, InH,
3827 DAG.getConstant(NVTBits-1, ShTy));
3828 } else if (Cst > NVTBits) {
3829 Lo = DAG.getNode(ISD::SRA, NVT, InH,
3830 DAG.getConstant(Cst-NVTBits, ShTy));
3831 Hi = DAG.getNode(ISD::SRA, NVT, InH,
3832 DAG.getConstant(NVTBits-1, ShTy));
3833 } else if (Cst == NVTBits) {
3835 Hi = DAG.getNode(ISD::SRA, NVT, InH,
3836 DAG.getConstant(NVTBits-1, ShTy));
3838 Lo = DAG.getNode(ISD::OR, NVT,
3839 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(Cst, ShTy)),
3840 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(NVTBits-Cst, ShTy)));
3841 Hi = DAG.getNode(ISD::SRA, NVT, InH, DAG.getConstant(Cst, ShTy));
3847 // Okay, the shift amount isn't constant. However, if we can tell that it is
3848 // >= 32 or < 32, we can still simplify it, without knowing the actual value.
3849 uint64_t Mask = NVTBits, KnownZero, KnownOne;
3850 TLI.ComputeMaskedBits(Amt, Mask, KnownZero, KnownOne);
3852 // If we know that the high bit of the shift amount is one, then we can do
3853 // this as a couple of simple shifts.
3854 if (KnownOne & Mask) {
3855 // Mask out the high bit, which we know is set.
3856 Amt = DAG.getNode(ISD::AND, Amt.getValueType(), Amt,
3857 DAG.getConstant(NVTBits-1, Amt.getValueType()));
3859 // Expand the incoming operand to be shifted, so that we have its parts
3861 ExpandOp(Op, InL, InH);
3864 Lo = DAG.getConstant(0, NVT); // Low part is zero.
3865 Hi = DAG.getNode(ISD::SHL, NVT, InL, Amt); // High part from Lo part.
3868 Hi = DAG.getConstant(0, NVT); // Hi part is zero.
3869 Lo = DAG.getNode(ISD::SRL, NVT, InH, Amt); // Lo part from Hi part.
3872 Hi = DAG.getNode(ISD::SRA, NVT, InH, // Sign extend high part.
3873 DAG.getConstant(NVTBits-1, Amt.getValueType()));
3874 Lo = DAG.getNode(ISD::SRA, NVT, InH, Amt); // Lo part from Hi part.
3879 // If we know that the high bit of the shift amount is zero, then we can do
3880 // this as a couple of simple shifts.
3881 if (KnownZero & Mask) {
3883 SDOperand Amt2 = DAG.getNode(ISD::SUB, Amt.getValueType(),
3884 DAG.getConstant(NVTBits, Amt.getValueType()),
3887 // Expand the incoming operand to be shifted, so that we have its parts
3889 ExpandOp(Op, InL, InH);
3892 Lo = DAG.getNode(ISD::SHL, NVT, InL, Amt);
3893 Hi = DAG.getNode(ISD::OR, NVT,
3894 DAG.getNode(ISD::SHL, NVT, InH, Amt),
3895 DAG.getNode(ISD::SRL, NVT, InL, Amt2));
3898 Hi = DAG.getNode(ISD::SRL, NVT, InH, Amt);
3899 Lo = DAG.getNode(ISD::OR, NVT,
3900 DAG.getNode(ISD::SRL, NVT, InL, Amt),
3901 DAG.getNode(ISD::SHL, NVT, InH, Amt2));
3904 Hi = DAG.getNode(ISD::SRA, NVT, InH, Amt);
3905 Lo = DAG.getNode(ISD::OR, NVT,
3906 DAG.getNode(ISD::SRL, NVT, InL, Amt),
3907 DAG.getNode(ISD::SHL, NVT, InH, Amt2));
3916 // ExpandLibCall - Expand a node into a call to a libcall. If the result value
3917 // does not fit into a register, return the lo part and set the hi part to the
3918 // by-reg argument. If it does fit into a single register, return the result
3919 // and leave the Hi part unset.
3920 SDOperand SelectionDAGLegalize::ExpandLibCall(const char *Name, SDNode *Node,
3922 assert(!IsLegalizingCall && "Cannot overlap legalization of calls!");
3923 // The input chain to this libcall is the entry node of the function.
3924 // Legalizing the call will automatically add the previous call to the
3926 SDOperand InChain = DAG.getEntryNode();
3928 TargetLowering::ArgListTy Args;
3929 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
3930 MVT::ValueType ArgVT = Node->getOperand(i).getValueType();
3931 const Type *ArgTy = MVT::getTypeForValueType(ArgVT);
3932 Args.push_back(std::make_pair(Node->getOperand(i), ArgTy));
3934 SDOperand Callee = DAG.getExternalSymbol(Name, TLI.getPointerTy());
3936 // Splice the libcall in wherever FindInputOutputChains tells us to.
3937 const Type *RetTy = MVT::getTypeForValueType(Node->getValueType(0));
3938 std::pair<SDOperand,SDOperand> CallInfo =
3939 TLI.LowerCallTo(InChain, RetTy, false, CallingConv::C, false,
3942 // Legalize the call sequence, starting with the chain. This will advance
3943 // the LastCALLSEQ_END to the legalized version of the CALLSEQ_END node that
3944 // was added by LowerCallTo (guaranteeing proper serialization of calls).
3945 LegalizeOp(CallInfo.second);
3947 switch (getTypeAction(CallInfo.first.getValueType())) {
3948 default: assert(0 && "Unknown thing");
3950 Result = CallInfo.first;
3953 ExpandOp(CallInfo.first, Result, Hi);
3960 /// ExpandIntToFP - Expand a [US]INT_TO_FP operation, assuming that the
3961 /// destination type is legal.
3962 SDOperand SelectionDAGLegalize::
3963 ExpandIntToFP(bool isSigned, MVT::ValueType DestTy, SDOperand Source) {
3964 assert(isTypeLegal(DestTy) && "Destination type is not legal!");
3965 assert(getTypeAction(Source.getValueType()) == Expand &&
3966 "This is not an expansion!");
3967 assert(Source.getValueType() == MVT::i64 && "Only handle expand from i64!");
3970 assert(Source.getValueType() == MVT::i64 &&
3971 "This only works for 64-bit -> FP");
3972 // The 64-bit value loaded will be incorrectly if the 'sign bit' of the
3973 // incoming integer is set. To handle this, we dynamically test to see if
3974 // it is set, and, if so, add a fudge factor.
3976 ExpandOp(Source, Lo, Hi);
3978 // If this is unsigned, and not supported, first perform the conversion to
3979 // signed, then adjust the result if the sign bit is set.
3980 SDOperand SignedConv = ExpandIntToFP(true, DestTy,
3981 DAG.getNode(ISD::BUILD_PAIR, Source.getValueType(), Lo, Hi));
3983 SDOperand SignSet = DAG.getSetCC(TLI.getSetCCResultTy(), Hi,
3984 DAG.getConstant(0, Hi.getValueType()),
3986 SDOperand Zero = getIntPtrConstant(0), Four = getIntPtrConstant(4);
3987 SDOperand CstOffset = DAG.getNode(ISD::SELECT, Zero.getValueType(),
3988 SignSet, Four, Zero);
3989 uint64_t FF = 0x5f800000ULL;
3990 if (TLI.isLittleEndian()) FF <<= 32;
3991 static Constant *FudgeFactor = ConstantInt::get(Type::ULongTy, FF);
3993 SDOperand CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy());
3994 CPIdx = DAG.getNode(ISD::ADD, TLI.getPointerTy(), CPIdx, CstOffset);
3995 SDOperand FudgeInReg;
3996 if (DestTy == MVT::f32)
3997 FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx, NULL, 0);
3999 assert(DestTy == MVT::f64 && "Unexpected conversion");
4000 FudgeInReg = DAG.getExtLoad(ISD::EXTLOAD, MVT::f64, DAG.getEntryNode(),
4001 CPIdx, NULL, 0, MVT::f32);
4003 return DAG.getNode(ISD::FADD, DestTy, SignedConv, FudgeInReg);
4006 // Check to see if the target has a custom way to lower this. If so, use it.
4007 switch (TLI.getOperationAction(ISD::SINT_TO_FP, Source.getValueType())) {
4008 default: assert(0 && "This action not implemented for this operation!");
4009 case TargetLowering::Legal:
4010 case TargetLowering::Expand:
4011 break; // This case is handled below.
4012 case TargetLowering::Custom: {
4013 SDOperand NV = TLI.LowerOperation(DAG.getNode(ISD::SINT_TO_FP, DestTy,
4016 return LegalizeOp(NV);
4017 break; // The target decided this was legal after all
4021 // Expand the source, then glue it back together for the call. We must expand
4022 // the source in case it is shared (this pass of legalize must traverse it).
4023 SDOperand SrcLo, SrcHi;
4024 ExpandOp(Source, SrcLo, SrcHi);
4025 Source = DAG.getNode(ISD::BUILD_PAIR, Source.getValueType(), SrcLo, SrcHi);
4027 const char *FnName = 0;
4028 if (DestTy == MVT::f32)
4029 FnName = "__floatdisf";
4031 assert(DestTy == MVT::f64 && "Unknown fp value type!");
4032 FnName = "__floatdidf";
4035 Source = DAG.getNode(ISD::SINT_TO_FP, DestTy, Source);
4036 SDOperand UnusedHiPart;
4037 return ExpandLibCall(FnName, Source.Val, UnusedHiPart);
4040 /// ExpandLegalINT_TO_FP - This function is responsible for legalizing a
4041 /// INT_TO_FP operation of the specified operand when the target requests that
4042 /// we expand it. At this point, we know that the result and operand types are
4043 /// legal for the target.
4044 SDOperand SelectionDAGLegalize::ExpandLegalINT_TO_FP(bool isSigned,
4046 MVT::ValueType DestVT) {
4047 if (Op0.getValueType() == MVT::i32) {
4048 // simple 32-bit [signed|unsigned] integer to float/double expansion
4050 // get the stack frame index of a 8 byte buffer
4051 MachineFunction &MF = DAG.getMachineFunction();
4052 int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8);
4053 // get address of 8 byte buffer
4054 SDOperand StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy());
4055 // word offset constant for Hi/Lo address computation
4056 SDOperand WordOff = DAG.getConstant(sizeof(int), TLI.getPointerTy());
4057 // set up Hi and Lo (into buffer) address based on endian
4058 SDOperand Hi = StackSlot;
4059 SDOperand Lo = DAG.getNode(ISD::ADD, TLI.getPointerTy(), StackSlot,WordOff);
4060 if (TLI.isLittleEndian())
4063 // if signed map to unsigned space
4064 SDOperand Op0Mapped;
4066 // constant used to invert sign bit (signed to unsigned mapping)
4067 SDOperand SignBit = DAG.getConstant(0x80000000u, MVT::i32);
4068 Op0Mapped = DAG.getNode(ISD::XOR, MVT::i32, Op0, SignBit);
4072 // store the lo of the constructed double - based on integer input
4073 SDOperand Store1 = DAG.getStore(DAG.getEntryNode(),
4074 Op0Mapped, Lo, NULL, 0);
4075 // initial hi portion of constructed double
4076 SDOperand InitialHi = DAG.getConstant(0x43300000u, MVT::i32);
4077 // store the hi of the constructed double - biased exponent
4078 SDOperand Store2=DAG.getStore(Store1, InitialHi, Hi, NULL, 0);
4079 // load the constructed double
4080 SDOperand Load = DAG.getLoad(MVT::f64, Store2, StackSlot, NULL, 0);
4081 // FP constant to bias correct the final result
4082 SDOperand Bias = DAG.getConstantFP(isSigned ?
4083 BitsToDouble(0x4330000080000000ULL)
4084 : BitsToDouble(0x4330000000000000ULL),
4086 // subtract the bias
4087 SDOperand Sub = DAG.getNode(ISD::FSUB, MVT::f64, Load, Bias);
4090 // handle final rounding
4091 if (DestVT == MVT::f64) {
4095 // if f32 then cast to f32
4096 Result = DAG.getNode(ISD::FP_ROUND, MVT::f32, Sub);
4100 assert(!isSigned && "Legalize cannot Expand SINT_TO_FP for i64 yet");
4101 SDOperand Tmp1 = DAG.getNode(ISD::SINT_TO_FP, DestVT, Op0);
4103 SDOperand SignSet = DAG.getSetCC(TLI.getSetCCResultTy(), Op0,
4104 DAG.getConstant(0, Op0.getValueType()),
4106 SDOperand Zero = getIntPtrConstant(0), Four = getIntPtrConstant(4);
4107 SDOperand CstOffset = DAG.getNode(ISD::SELECT, Zero.getValueType(),
4108 SignSet, Four, Zero);
4110 // If the sign bit of the integer is set, the large number will be treated
4111 // as a negative number. To counteract this, the dynamic code adds an
4112 // offset depending on the data type.
4114 switch (Op0.getValueType()) {
4115 default: assert(0 && "Unsupported integer type!");
4116 case MVT::i8 : FF = 0x43800000ULL; break; // 2^8 (as a float)
4117 case MVT::i16: FF = 0x47800000ULL; break; // 2^16 (as a float)
4118 case MVT::i32: FF = 0x4F800000ULL; break; // 2^32 (as a float)
4119 case MVT::i64: FF = 0x5F800000ULL; break; // 2^64 (as a float)
4121 if (TLI.isLittleEndian()) FF <<= 32;
4122 static Constant *FudgeFactor = ConstantInt::get(Type::ULongTy, FF);
4124 SDOperand CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy());
4125 CPIdx = DAG.getNode(ISD::ADD, TLI.getPointerTy(), CPIdx, CstOffset);
4126 SDOperand FudgeInReg;
4127 if (DestVT == MVT::f32)
4128 FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx, NULL, 0);
4130 assert(DestVT == MVT::f64 && "Unexpected conversion");
4131 FudgeInReg = LegalizeOp(DAG.getExtLoad(ISD::EXTLOAD, MVT::f64,
4132 DAG.getEntryNode(), CPIdx,
4133 NULL, 0, MVT::f32));
4136 return DAG.getNode(ISD::FADD, DestVT, Tmp1, FudgeInReg);
4139 /// PromoteLegalINT_TO_FP - This function is responsible for legalizing a
4140 /// *INT_TO_FP operation of the specified operand when the target requests that
4141 /// we promote it. At this point, we know that the result and operand types are
4142 /// legal for the target, and that there is a legal UINT_TO_FP or SINT_TO_FP
4143 /// operation that takes a larger input.
4144 SDOperand SelectionDAGLegalize::PromoteLegalINT_TO_FP(SDOperand LegalOp,
4145 MVT::ValueType DestVT,
4147 // First step, figure out the appropriate *INT_TO_FP operation to use.
4148 MVT::ValueType NewInTy = LegalOp.getValueType();
4150 unsigned OpToUse = 0;
4152 // Scan for the appropriate larger type to use.
4154 NewInTy = (MVT::ValueType)(NewInTy+1);
4155 assert(MVT::isInteger(NewInTy) && "Ran out of possibilities!");
4157 // If the target supports SINT_TO_FP of this type, use it.
4158 switch (TLI.getOperationAction(ISD::SINT_TO_FP, NewInTy)) {
4160 case TargetLowering::Legal:
4161 if (!TLI.isTypeLegal(NewInTy))
4162 break; // Can't use this datatype.
4164 case TargetLowering::Custom:
4165 OpToUse = ISD::SINT_TO_FP;
4169 if (isSigned) continue;
4171 // If the target supports UINT_TO_FP of this type, use it.
4172 switch (TLI.getOperationAction(ISD::UINT_TO_FP, NewInTy)) {
4174 case TargetLowering::Legal:
4175 if (!TLI.isTypeLegal(NewInTy))
4176 break; // Can't use this datatype.
4178 case TargetLowering::Custom:
4179 OpToUse = ISD::UINT_TO_FP;
4184 // Otherwise, try a larger type.
4187 // Okay, we found the operation and type to use. Zero extend our input to the
4188 // desired type then run the operation on it.
4189 return DAG.getNode(OpToUse, DestVT,
4190 DAG.getNode(isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND,
4194 /// PromoteLegalFP_TO_INT - This function is responsible for legalizing a
4195 /// FP_TO_*INT operation of the specified operand when the target requests that
4196 /// we promote it. At this point, we know that the result and operand types are
4197 /// legal for the target, and that there is a legal FP_TO_UINT or FP_TO_SINT
4198 /// operation that returns a larger result.
4199 SDOperand SelectionDAGLegalize::PromoteLegalFP_TO_INT(SDOperand LegalOp,
4200 MVT::ValueType DestVT,
4202 // First step, figure out the appropriate FP_TO*INT operation to use.
4203 MVT::ValueType NewOutTy = DestVT;
4205 unsigned OpToUse = 0;
4207 // Scan for the appropriate larger type to use.
4209 NewOutTy = (MVT::ValueType)(NewOutTy+1);
4210 assert(MVT::isInteger(NewOutTy) && "Ran out of possibilities!");
4212 // If the target supports FP_TO_SINT returning this type, use it.
4213 switch (TLI.getOperationAction(ISD::FP_TO_SINT, NewOutTy)) {
4215 case TargetLowering::Legal:
4216 if (!TLI.isTypeLegal(NewOutTy))
4217 break; // Can't use this datatype.
4219 case TargetLowering::Custom:
4220 OpToUse = ISD::FP_TO_SINT;
4225 // If the target supports FP_TO_UINT of this type, use it.
4226 switch (TLI.getOperationAction(ISD::FP_TO_UINT, NewOutTy)) {
4228 case TargetLowering::Legal:
4229 if (!TLI.isTypeLegal(NewOutTy))
4230 break; // Can't use this datatype.
4232 case TargetLowering::Custom:
4233 OpToUse = ISD::FP_TO_UINT;
4238 // Otherwise, try a larger type.
4241 // Okay, we found the operation and type to use. Truncate the result of the
4242 // extended FP_TO_*INT operation to the desired size.
4243 return DAG.getNode(ISD::TRUNCATE, DestVT,
4244 DAG.getNode(OpToUse, NewOutTy, LegalOp));
4247 /// ExpandBSWAP - Open code the operations for BSWAP of the specified operation.
4249 SDOperand SelectionDAGLegalize::ExpandBSWAP(SDOperand Op) {
4250 MVT::ValueType VT = Op.getValueType();
4251 MVT::ValueType SHVT = TLI.getShiftAmountTy();
4252 SDOperand Tmp1, Tmp2, Tmp3, Tmp4, Tmp5, Tmp6, Tmp7, Tmp8;
4254 default: assert(0 && "Unhandled Expand type in BSWAP!"); abort();
4256 Tmp2 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT));
4257 Tmp1 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(8, SHVT));
4258 return DAG.getNode(ISD::OR, VT, Tmp1, Tmp2);
4260 Tmp4 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(24, SHVT));
4261 Tmp3 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT));
4262 Tmp2 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(8, SHVT));
4263 Tmp1 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(24, SHVT));
4264 Tmp3 = DAG.getNode(ISD::AND, VT, Tmp3, DAG.getConstant(0xFF0000, VT));
4265 Tmp2 = DAG.getNode(ISD::AND, VT, Tmp2, DAG.getConstant(0xFF00, VT));
4266 Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp3);
4267 Tmp2 = DAG.getNode(ISD::OR, VT, Tmp2, Tmp1);
4268 return DAG.getNode(ISD::OR, VT, Tmp4, Tmp2);
4270 Tmp8 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(56, SHVT));
4271 Tmp7 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(40, SHVT));
4272 Tmp6 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(24, SHVT));
4273 Tmp5 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT));
4274 Tmp4 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(8, SHVT));
4275 Tmp3 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(24, SHVT));
4276 Tmp2 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(40, SHVT));
4277 Tmp1 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(56, SHVT));
4278 Tmp7 = DAG.getNode(ISD::AND, VT, Tmp7, DAG.getConstant(255ULL<<48, VT));
4279 Tmp6 = DAG.getNode(ISD::AND, VT, Tmp6, DAG.getConstant(255ULL<<40, VT));
4280 Tmp5 = DAG.getNode(ISD::AND, VT, Tmp5, DAG.getConstant(255ULL<<32, VT));
4281 Tmp4 = DAG.getNode(ISD::AND, VT, Tmp4, DAG.getConstant(255ULL<<24, VT));
4282 Tmp3 = DAG.getNode(ISD::AND, VT, Tmp3, DAG.getConstant(255ULL<<16, VT));
4283 Tmp2 = DAG.getNode(ISD::AND, VT, Tmp2, DAG.getConstant(255ULL<<8 , VT));
4284 Tmp8 = DAG.getNode(ISD::OR, VT, Tmp8, Tmp7);
4285 Tmp6 = DAG.getNode(ISD::OR, VT, Tmp6, Tmp5);
4286 Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp3);
4287 Tmp2 = DAG.getNode(ISD::OR, VT, Tmp2, Tmp1);
4288 Tmp8 = DAG.getNode(ISD::OR, VT, Tmp8, Tmp6);
4289 Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp2);
4290 return DAG.getNode(ISD::OR, VT, Tmp8, Tmp4);
4294 /// ExpandBitCount - Expand the specified bitcount instruction into operations.
4296 SDOperand SelectionDAGLegalize::ExpandBitCount(unsigned Opc, SDOperand Op) {
4298 default: assert(0 && "Cannot expand this yet!");
4300 static const uint64_t mask[6] = {
4301 0x5555555555555555ULL, 0x3333333333333333ULL,
4302 0x0F0F0F0F0F0F0F0FULL, 0x00FF00FF00FF00FFULL,
4303 0x0000FFFF0000FFFFULL, 0x00000000FFFFFFFFULL
4305 MVT::ValueType VT = Op.getValueType();
4306 MVT::ValueType ShVT = TLI.getShiftAmountTy();
4307 unsigned len = getSizeInBits(VT);
4308 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) {
4309 //x = (x & mask[i][len/8]) + (x >> (1 << i) & mask[i][len/8])
4310 SDOperand Tmp2 = DAG.getConstant(mask[i], VT);
4311 SDOperand Tmp3 = DAG.getConstant(1ULL << i, ShVT);
4312 Op = DAG.getNode(ISD::ADD, VT, DAG.getNode(ISD::AND, VT, Op, Tmp2),
4313 DAG.getNode(ISD::AND, VT,
4314 DAG.getNode(ISD::SRL, VT, Op, Tmp3),Tmp2));
4319 // for now, we do this:
4320 // x = x | (x >> 1);
4321 // x = x | (x >> 2);
4323 // x = x | (x >>16);
4324 // x = x | (x >>32); // for 64-bit input
4325 // return popcount(~x);
4327 // but see also: http://www.hackersdelight.org/HDcode/nlz.cc
4328 MVT::ValueType VT = Op.getValueType();
4329 MVT::ValueType ShVT = TLI.getShiftAmountTy();
4330 unsigned len = getSizeInBits(VT);
4331 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) {
4332 SDOperand Tmp3 = DAG.getConstant(1ULL << i, ShVT);
4333 Op = DAG.getNode(ISD::OR, VT, Op, DAG.getNode(ISD::SRL, VT, Op, Tmp3));
4335 Op = DAG.getNode(ISD::XOR, VT, Op, DAG.getConstant(~0ULL, VT));
4336 return DAG.getNode(ISD::CTPOP, VT, Op);
4339 // for now, we use: { return popcount(~x & (x - 1)); }
4340 // unless the target has ctlz but not ctpop, in which case we use:
4341 // { return 32 - nlz(~x & (x-1)); }
4342 // see also http://www.hackersdelight.org/HDcode/ntz.cc
4343 MVT::ValueType VT = Op.getValueType();
4344 SDOperand Tmp2 = DAG.getConstant(~0ULL, VT);
4345 SDOperand Tmp3 = DAG.getNode(ISD::AND, VT,
4346 DAG.getNode(ISD::XOR, VT, Op, Tmp2),
4347 DAG.getNode(ISD::SUB, VT, Op, DAG.getConstant(1, VT)));
4348 // If ISD::CTLZ is legal and CTPOP isn't, then do that instead.
4349 if (!TLI.isOperationLegal(ISD::CTPOP, VT) &&
4350 TLI.isOperationLegal(ISD::CTLZ, VT))
4351 return DAG.getNode(ISD::SUB, VT,
4352 DAG.getConstant(getSizeInBits(VT), VT),
4353 DAG.getNode(ISD::CTLZ, VT, Tmp3));
4354 return DAG.getNode(ISD::CTPOP, VT, Tmp3);
4359 /// ExpandOp - Expand the specified SDOperand into its two component pieces
4360 /// Lo&Hi. Note that the Op MUST be an expanded type. As a result of this, the
4361 /// LegalizeNodes map is filled in for any results that are not expanded, the
4362 /// ExpandedNodes map is filled in for any results that are expanded, and the
4363 /// Lo/Hi values are returned.
4364 void SelectionDAGLegalize::ExpandOp(SDOperand Op, SDOperand &Lo, SDOperand &Hi){
4365 MVT::ValueType VT = Op.getValueType();
4366 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT);
4367 SDNode *Node = Op.Val;
4368 assert(getTypeAction(VT) == Expand && "Not an expanded type!");
4369 assert(((MVT::isInteger(NVT) && NVT < VT) || MVT::isFloatingPoint(VT) ||
4370 VT == MVT::Vector) &&
4371 "Cannot expand to FP value or to larger int value!");
4373 // See if we already expanded it.
4374 std::map<SDOperand, std::pair<SDOperand, SDOperand> >::iterator I
4375 = ExpandedNodes.find(Op);
4376 if (I != ExpandedNodes.end()) {
4377 Lo = I->second.first;
4378 Hi = I->second.second;
4382 switch (Node->getOpcode()) {
4383 case ISD::CopyFromReg:
4384 assert(0 && "CopyFromReg must be legal!");
4387 cerr << "NODE: "; Node->dump(); cerr << "\n";
4389 assert(0 && "Do not know how to expand this operator!");
4392 Lo = DAG.getNode(ISD::UNDEF, NVT);
4393 Hi = DAG.getNode(ISD::UNDEF, NVT);
4395 case ISD::Constant: {
4396 uint64_t Cst = cast<ConstantSDNode>(Node)->getValue();
4397 Lo = DAG.getConstant(Cst, NVT);
4398 Hi = DAG.getConstant(Cst >> MVT::getSizeInBits(NVT), NVT);
4401 case ISD::BUILD_PAIR:
4402 // Return the operands.
4403 Lo = Node->getOperand(0);
4404 Hi = Node->getOperand(1);
4407 case ISD::SIGN_EXTEND_INREG:
4408 ExpandOp(Node->getOperand(0), Lo, Hi);
4409 // sext_inreg the low part if needed.
4410 Lo = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Lo, Node->getOperand(1));
4412 // The high part gets the sign extension from the lo-part. This handles
4413 // things like sextinreg V:i64 from i8.
4414 Hi = DAG.getNode(ISD::SRA, NVT, Lo,
4415 DAG.getConstant(MVT::getSizeInBits(NVT)-1,
4416 TLI.getShiftAmountTy()));
4420 ExpandOp(Node->getOperand(0), Lo, Hi);
4421 SDOperand TempLo = DAG.getNode(ISD::BSWAP, NVT, Hi);
4422 Hi = DAG.getNode(ISD::BSWAP, NVT, Lo);
4428 ExpandOp(Node->getOperand(0), Lo, Hi);
4429 Lo = DAG.getNode(ISD::ADD, NVT, // ctpop(HL) -> ctpop(H)+ctpop(L)
4430 DAG.getNode(ISD::CTPOP, NVT, Lo),
4431 DAG.getNode(ISD::CTPOP, NVT, Hi));
4432 Hi = DAG.getConstant(0, NVT);
4436 // ctlz (HL) -> ctlz(H) != 32 ? ctlz(H) : (ctlz(L)+32)
4437 ExpandOp(Node->getOperand(0), Lo, Hi);
4438 SDOperand BitsC = DAG.getConstant(MVT::getSizeInBits(NVT), NVT);
4439 SDOperand HLZ = DAG.getNode(ISD::CTLZ, NVT, Hi);
4440 SDOperand TopNotZero = DAG.getSetCC(TLI.getSetCCResultTy(), HLZ, BitsC,
4442 SDOperand LowPart = DAG.getNode(ISD::CTLZ, NVT, Lo);
4443 LowPart = DAG.getNode(ISD::ADD, NVT, LowPart, BitsC);
4445 Lo = DAG.getNode(ISD::SELECT, NVT, TopNotZero, HLZ, LowPart);
4446 Hi = DAG.getConstant(0, NVT);
4451 // cttz (HL) -> cttz(L) != 32 ? cttz(L) : (cttz(H)+32)
4452 ExpandOp(Node->getOperand(0), Lo, Hi);
4453 SDOperand BitsC = DAG.getConstant(MVT::getSizeInBits(NVT), NVT);
4454 SDOperand LTZ = DAG.getNode(ISD::CTTZ, NVT, Lo);
4455 SDOperand BotNotZero = DAG.getSetCC(TLI.getSetCCResultTy(), LTZ, BitsC,
4457 SDOperand HiPart = DAG.getNode(ISD::CTTZ, NVT, Hi);
4458 HiPart = DAG.getNode(ISD::ADD, NVT, HiPart, BitsC);
4460 Lo = DAG.getNode(ISD::SELECT, NVT, BotNotZero, LTZ, HiPart);
4461 Hi = DAG.getConstant(0, NVT);
4466 SDOperand Ch = Node->getOperand(0); // Legalize the chain.
4467 SDOperand Ptr = Node->getOperand(1); // Legalize the pointer.
4468 Lo = DAG.getVAArg(NVT, Ch, Ptr, Node->getOperand(2));
4469 Hi = DAG.getVAArg(NVT, Lo.getValue(1), Ptr, Node->getOperand(2));
4471 // Remember that we legalized the chain.
4472 Hi = LegalizeOp(Hi);
4473 AddLegalizedOperand(Op.getValue(1), Hi.getValue(1));
4474 if (!TLI.isLittleEndian())
4480 LoadSDNode *LD = cast<LoadSDNode>(Node);
4481 SDOperand Ch = LD->getChain(); // Legalize the chain.
4482 SDOperand Ptr = LD->getBasePtr(); // Legalize the pointer.
4483 ISD::LoadExtType ExtType = LD->getExtensionType();
4485 if (ExtType == ISD::NON_EXTLOAD) {
4486 Lo = DAG.getLoad(NVT, Ch, Ptr, LD->getSrcValue(), LD->getSrcValueOffset());
4488 // Increment the pointer to the other half.
4489 unsigned IncrementSize = MVT::getSizeInBits(Lo.getValueType())/8;
4490 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
4491 getIntPtrConstant(IncrementSize));
4492 // FIXME: This creates a bogus srcvalue!
4493 Hi = DAG.getLoad(NVT, Ch, Ptr, LD->getSrcValue(), LD->getSrcValueOffset());
4495 // Build a factor node to remember that this load is independent of the
4497 SDOperand TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
4500 // Remember that we legalized the chain.
4501 AddLegalizedOperand(Op.getValue(1), LegalizeOp(TF));
4502 if (!TLI.isLittleEndian())
4505 MVT::ValueType EVT = LD->getLoadedVT();
4508 Lo = DAG.getLoad(NVT, Ch, Ptr, LD->getSrcValue(),
4509 LD->getSrcValueOffset());
4511 Lo = DAG.getExtLoad(ExtType, NVT, Ch, Ptr, LD->getSrcValue(),
4512 LD->getSrcValueOffset(), EVT);
4514 // Remember that we legalized the chain.
4515 AddLegalizedOperand(SDOperand(Node, 1), LegalizeOp(Lo.getValue(1)));
4517 if (ExtType == ISD::SEXTLOAD) {
4518 // The high part is obtained by SRA'ing all but one of the bits of the
4520 unsigned LoSize = MVT::getSizeInBits(Lo.getValueType());
4521 Hi = DAG.getNode(ISD::SRA, NVT, Lo,
4522 DAG.getConstant(LoSize-1, TLI.getShiftAmountTy()));
4523 } else if (ExtType == ISD::ZEXTLOAD) {
4524 // The high part is just a zero.
4525 Hi = DAG.getConstant(0, NVT);
4526 } else /* if (ExtType == ISD::EXTLOAD) */ {
4527 // The high part is undefined.
4528 Hi = DAG.getNode(ISD::UNDEF, NVT);
4535 case ISD::XOR: { // Simple logical operators -> two trivial pieces.
4536 SDOperand LL, LH, RL, RH;
4537 ExpandOp(Node->getOperand(0), LL, LH);
4538 ExpandOp(Node->getOperand(1), RL, RH);
4539 Lo = DAG.getNode(Node->getOpcode(), NVT, LL, RL);
4540 Hi = DAG.getNode(Node->getOpcode(), NVT, LH, RH);
4544 SDOperand LL, LH, RL, RH;
4545 ExpandOp(Node->getOperand(1), LL, LH);
4546 ExpandOp(Node->getOperand(2), RL, RH);
4547 Lo = DAG.getNode(ISD::SELECT, NVT, Node->getOperand(0), LL, RL);
4548 Hi = DAG.getNode(ISD::SELECT, NVT, Node->getOperand(0), LH, RH);
4551 case ISD::SELECT_CC: {
4552 SDOperand TL, TH, FL, FH;
4553 ExpandOp(Node->getOperand(2), TL, TH);
4554 ExpandOp(Node->getOperand(3), FL, FH);
4555 Lo = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0),
4556 Node->getOperand(1), TL, FL, Node->getOperand(4));
4557 Hi = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0),
4558 Node->getOperand(1), TH, FH, Node->getOperand(4));
4561 case ISD::ANY_EXTEND:
4562 // The low part is any extension of the input (which degenerates to a copy).
4563 Lo = DAG.getNode(ISD::ANY_EXTEND, NVT, Node->getOperand(0));
4564 // The high part is undefined.
4565 Hi = DAG.getNode(ISD::UNDEF, NVT);
4567 case ISD::SIGN_EXTEND: {
4568 // The low part is just a sign extension of the input (which degenerates to
4570 Lo = DAG.getNode(ISD::SIGN_EXTEND, NVT, Node->getOperand(0));
4572 // The high part is obtained by SRA'ing all but one of the bits of the lo
4574 unsigned LoSize = MVT::getSizeInBits(Lo.getValueType());
4575 Hi = DAG.getNode(ISD::SRA, NVT, Lo,
4576 DAG.getConstant(LoSize-1, TLI.getShiftAmountTy()));
4579 case ISD::ZERO_EXTEND:
4580 // The low part is just a zero extension of the input (which degenerates to
4582 Lo = DAG.getNode(ISD::ZERO_EXTEND, NVT, Node->getOperand(0));
4584 // The high part is just a zero.
4585 Hi = DAG.getConstant(0, NVT);
4588 case ISD::BIT_CONVERT: {
4590 if (TLI.getOperationAction(ISD::BIT_CONVERT, VT) == TargetLowering::Custom){
4591 // If the target wants to, allow it to lower this itself.
4592 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4593 case Expand: assert(0 && "cannot expand FP!");
4594 case Legal: Tmp = LegalizeOp(Node->getOperand(0)); break;
4595 case Promote: Tmp = PromoteOp (Node->getOperand(0)); break;
4597 Tmp = TLI.LowerOperation(DAG.getNode(ISD::BIT_CONVERT, VT, Tmp), DAG);
4600 // f32 / f64 must be expanded to i32 / i64.
4601 if (VT == MVT::f32 || VT == MVT::f64) {
4602 Lo = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0));
4606 // If source operand will be expanded to the same type as VT, i.e.
4607 // i64 <- f64, i32 <- f32, expand the source operand instead.
4608 MVT::ValueType VT0 = Node->getOperand(0).getValueType();
4609 if (getTypeAction(VT0) == Expand && TLI.getTypeToTransformTo(VT0) == VT) {
4610 ExpandOp(Node->getOperand(0), Lo, Hi);
4614 // Turn this into a load/store pair by default.
4616 Tmp = ExpandBIT_CONVERT(VT, Node->getOperand(0));
4618 ExpandOp(Tmp, Lo, Hi);
4622 case ISD::READCYCLECOUNTER:
4623 assert(TLI.getOperationAction(ISD::READCYCLECOUNTER, VT) ==
4624 TargetLowering::Custom &&
4625 "Must custom expand ReadCycleCounter");
4626 Lo = TLI.LowerOperation(Op, DAG);
4627 assert(Lo.Val && "Node must be custom expanded!");
4628 Hi = Lo.getValue(1);
4629 AddLegalizedOperand(SDOperand(Node, 1), // Remember we legalized the chain.
4630 LegalizeOp(Lo.getValue(2)));
4633 // These operators cannot be expanded directly, emit them as calls to
4634 // library functions.
4635 case ISD::FP_TO_SINT:
4636 if (TLI.getOperationAction(ISD::FP_TO_SINT, VT) == TargetLowering::Custom) {
4638 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4639 case Expand: assert(0 && "cannot expand FP!");
4640 case Legal: Op = LegalizeOp(Node->getOperand(0)); break;
4641 case Promote: Op = PromoteOp (Node->getOperand(0)); break;
4644 Op = TLI.LowerOperation(DAG.getNode(ISD::FP_TO_SINT, VT, Op), DAG);
4646 // Now that the custom expander is done, expand the result, which is still
4649 ExpandOp(Op, Lo, Hi);
4654 if (Node->getOperand(0).getValueType() == MVT::f32)
4655 Lo = ExpandLibCall("__fixsfdi", Node, Hi);
4657 Lo = ExpandLibCall("__fixdfdi", Node, Hi);
4660 case ISD::FP_TO_UINT:
4661 if (TLI.getOperationAction(ISD::FP_TO_UINT, VT) == TargetLowering::Custom) {
4663 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4664 case Expand: assert(0 && "cannot expand FP!");
4665 case Legal: Op = LegalizeOp(Node->getOperand(0)); break;
4666 case Promote: Op = PromoteOp (Node->getOperand(0)); break;
4669 Op = TLI.LowerOperation(DAG.getNode(ISD::FP_TO_UINT, VT, Op), DAG);
4671 // Now that the custom expander is done, expand the result.
4673 ExpandOp(Op, Lo, Hi);
4678 if (Node->getOperand(0).getValueType() == MVT::f32)
4679 Lo = ExpandLibCall("__fixunssfdi", Node, Hi);
4681 Lo = ExpandLibCall("__fixunsdfdi", Node, Hi);
4685 // If the target wants custom lowering, do so.
4686 SDOperand ShiftAmt = LegalizeOp(Node->getOperand(1));
4687 if (TLI.getOperationAction(ISD::SHL, VT) == TargetLowering::Custom) {
4688 SDOperand Op = DAG.getNode(ISD::SHL, VT, Node->getOperand(0), ShiftAmt);
4689 Op = TLI.LowerOperation(Op, DAG);
4691 // Now that the custom expander is done, expand the result, which is
4693 ExpandOp(Op, Lo, Hi);
4698 // If ADDC/ADDE are supported and if the shift amount is a constant 1, emit
4699 // this X << 1 as X+X.
4700 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(ShiftAmt)) {
4701 if (ShAmt->getValue() == 1 && TLI.isOperationLegal(ISD::ADDC, NVT) &&
4702 TLI.isOperationLegal(ISD::ADDE, NVT)) {
4703 SDOperand LoOps[2], HiOps[3];
4704 ExpandOp(Node->getOperand(0), LoOps[0], HiOps[0]);
4705 SDVTList VTList = DAG.getVTList(LoOps[0].getValueType(), MVT::Flag);
4706 LoOps[1] = LoOps[0];
4707 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2);
4709 HiOps[1] = HiOps[0];
4710 HiOps[2] = Lo.getValue(1);
4711 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3);
4716 // If we can emit an efficient shift operation, do so now.
4717 if (ExpandShift(ISD::SHL, Node->getOperand(0), ShiftAmt, Lo, Hi))
4720 // If this target supports SHL_PARTS, use it.
4721 TargetLowering::LegalizeAction Action =
4722 TLI.getOperationAction(ISD::SHL_PARTS, NVT);
4723 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) ||
4724 Action == TargetLowering::Custom) {
4725 ExpandShiftParts(ISD::SHL_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi);
4729 // Otherwise, emit a libcall.
4730 Lo = ExpandLibCall("__ashldi3", Node, Hi);
4735 // If the target wants custom lowering, do so.
4736 SDOperand ShiftAmt = LegalizeOp(Node->getOperand(1));
4737 if (TLI.getOperationAction(ISD::SRA, VT) == TargetLowering::Custom) {
4738 SDOperand Op = DAG.getNode(ISD::SRA, VT, Node->getOperand(0), ShiftAmt);
4739 Op = TLI.LowerOperation(Op, DAG);
4741 // Now that the custom expander is done, expand the result, which is
4743 ExpandOp(Op, Lo, Hi);
4748 // If we can emit an efficient shift operation, do so now.
4749 if (ExpandShift(ISD::SRA, Node->getOperand(0), ShiftAmt, Lo, Hi))
4752 // If this target supports SRA_PARTS, use it.
4753 TargetLowering::LegalizeAction Action =
4754 TLI.getOperationAction(ISD::SRA_PARTS, NVT);
4755 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) ||
4756 Action == TargetLowering::Custom) {
4757 ExpandShiftParts(ISD::SRA_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi);
4761 // Otherwise, emit a libcall.
4762 Lo = ExpandLibCall("__ashrdi3", Node, Hi);
4767 // If the target wants custom lowering, do so.
4768 SDOperand ShiftAmt = LegalizeOp(Node->getOperand(1));
4769 if (TLI.getOperationAction(ISD::SRL, VT) == TargetLowering::Custom) {
4770 SDOperand Op = DAG.getNode(ISD::SRL, VT, Node->getOperand(0), ShiftAmt);
4771 Op = TLI.LowerOperation(Op, DAG);
4773 // Now that the custom expander is done, expand the result, which is
4775 ExpandOp(Op, Lo, Hi);
4780 // If we can emit an efficient shift operation, do so now.
4781 if (ExpandShift(ISD::SRL, Node->getOperand(0), ShiftAmt, Lo, Hi))
4784 // If this target supports SRL_PARTS, use it.
4785 TargetLowering::LegalizeAction Action =
4786 TLI.getOperationAction(ISD::SRL_PARTS, NVT);
4787 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) ||
4788 Action == TargetLowering::Custom) {
4789 ExpandShiftParts(ISD::SRL_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi);
4793 // Otherwise, emit a libcall.
4794 Lo = ExpandLibCall("__lshrdi3", Node, Hi);
4800 // If the target wants to custom expand this, let them.
4801 if (TLI.getOperationAction(Node->getOpcode(), VT) ==
4802 TargetLowering::Custom) {
4803 Op = TLI.LowerOperation(Op, DAG);
4805 ExpandOp(Op, Lo, Hi);
4810 // Expand the subcomponents.
4811 SDOperand LHSL, LHSH, RHSL, RHSH;
4812 ExpandOp(Node->getOperand(0), LHSL, LHSH);
4813 ExpandOp(Node->getOperand(1), RHSL, RHSH);
4814 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag);
4815 SDOperand LoOps[2], HiOps[3];
4820 if (Node->getOpcode() == ISD::ADD) {
4821 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2);
4822 HiOps[2] = Lo.getValue(1);
4823 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3);
4825 Lo = DAG.getNode(ISD::SUBC, VTList, LoOps, 2);
4826 HiOps[2] = Lo.getValue(1);
4827 Hi = DAG.getNode(ISD::SUBE, VTList, HiOps, 3);
4832 // If the target wants to custom expand this, let them.
4833 if (TLI.getOperationAction(ISD::MUL, VT) == TargetLowering::Custom) {
4834 SDOperand New = TLI.LowerOperation(Op, DAG);
4836 ExpandOp(New, Lo, Hi);
4841 bool HasMULHS = TLI.isOperationLegal(ISD::MULHS, NVT);
4842 bool HasMULHU = TLI.isOperationLegal(ISD::MULHU, NVT);
4843 if (HasMULHS || HasMULHU) {
4844 SDOperand LL, LH, RL, RH;
4845 ExpandOp(Node->getOperand(0), LL, LH);
4846 ExpandOp(Node->getOperand(1), RL, RH);
4847 unsigned SH = MVT::getSizeInBits(RH.getValueType())-1;
4848 // FIXME: Move this to the dag combiner.
4849 // MULHS implicitly sign extends its inputs. Check to see if ExpandOp
4850 // extended the sign bit of the low half through the upper half, and if so
4851 // emit a MULHS instead of the alternate sequence that is valid for any
4852 // i64 x i64 multiply.
4854 // is RH an extension of the sign bit of RL?
4855 RH.getOpcode() == ISD::SRA && RH.getOperand(0) == RL &&
4856 RH.getOperand(1).getOpcode() == ISD::Constant &&
4857 cast<ConstantSDNode>(RH.getOperand(1))->getValue() == SH &&
4858 // is LH an extension of the sign bit of LL?
4859 LH.getOpcode() == ISD::SRA && LH.getOperand(0) == LL &&
4860 LH.getOperand(1).getOpcode() == ISD::Constant &&
4861 cast<ConstantSDNode>(LH.getOperand(1))->getValue() == SH) {
4863 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL);
4865 Hi = DAG.getNode(ISD::MULHS, NVT, LL, RL);
4867 } else if (HasMULHU) {
4869 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL);
4872 Hi = DAG.getNode(ISD::MULHU, NVT, LL, RL);
4873 RH = DAG.getNode(ISD::MUL, NVT, LL, RH);
4874 LH = DAG.getNode(ISD::MUL, NVT, LH, RL);
4875 Hi = DAG.getNode(ISD::ADD, NVT, Hi, RH);
4876 Hi = DAG.getNode(ISD::ADD, NVT, Hi, LH);
4881 Lo = ExpandLibCall("__muldi3" , Node, Hi);
4884 case ISD::SDIV: Lo = ExpandLibCall("__divdi3" , Node, Hi); break;
4885 case ISD::UDIV: Lo = ExpandLibCall("__udivdi3", Node, Hi); break;
4886 case ISD::SREM: Lo = ExpandLibCall("__moddi3" , Node, Hi); break;
4887 case ISD::UREM: Lo = ExpandLibCall("__umoddi3", Node, Hi); break;
4890 Lo = ExpandLibCall(((VT == MVT::f32) ? "__addsf3" : "__adddf3"), Node, Hi);
4893 Lo = ExpandLibCall(((VT == MVT::f32) ? "__subsf3" : "__subdf3"), Node, Hi);
4896 Lo = ExpandLibCall(((VT == MVT::f32) ? "__mulsf3" : "__muldf3"), Node, Hi);
4899 Lo = ExpandLibCall(((VT == MVT::f32) ? "__divsf3" : "__divdf3"), Node, Hi);
4901 case ISD::FP_EXTEND:
4902 Lo = ExpandLibCall("__extendsfdf2", Node, Hi);
4905 Lo = ExpandLibCall("__truncdfsf2", Node, Hi);
4909 // Make sure the resultant values have been legalized themselves, unless this
4910 // is a type that requires multi-step expansion.
4911 if (getTypeAction(NVT) != Expand && NVT != MVT::isVoid) {
4912 Lo = LegalizeOp(Lo);
4914 // Don't legalize the high part if it is expanded to a single node.
4915 Hi = LegalizeOp(Hi);
4918 // Remember in a map if the values will be reused later.
4920 ExpandedNodes.insert(std::make_pair(Op, std::make_pair(Lo, Hi))).second;
4921 assert(isNew && "Value already expanded?!?");
4924 /// SplitVectorOp - Given an operand of MVT::Vector type, break it down into
4925 /// two smaller values of MVT::Vector type.
4926 void SelectionDAGLegalize::SplitVectorOp(SDOperand Op, SDOperand &Lo,
4928 assert(Op.getValueType() == MVT::Vector && "Cannot split non-vector type!");
4929 SDNode *Node = Op.Val;
4930 unsigned NumElements = cast<ConstantSDNode>(*(Node->op_end()-2))->getValue();
4931 assert(NumElements > 1 && "Cannot split a single element vector!");
4932 unsigned NewNumElts = NumElements/2;
4933 SDOperand NewNumEltsNode = DAG.getConstant(NewNumElts, MVT::i32);
4934 SDOperand TypeNode = *(Node->op_end()-1);
4936 // See if we already split it.
4937 std::map<SDOperand, std::pair<SDOperand, SDOperand> >::iterator I
4938 = SplitNodes.find(Op);
4939 if (I != SplitNodes.end()) {
4940 Lo = I->second.first;
4941 Hi = I->second.second;
4945 switch (Node->getOpcode()) {
4950 assert(0 && "Unhandled operation in SplitVectorOp!");
4951 case ISD::VBUILD_VECTOR: {
4952 SmallVector<SDOperand, 8> LoOps(Node->op_begin(),
4953 Node->op_begin()+NewNumElts);
4954 LoOps.push_back(NewNumEltsNode);
4955 LoOps.push_back(TypeNode);
4956 Lo = DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, &LoOps[0], LoOps.size());
4958 SmallVector<SDOperand, 8> HiOps(Node->op_begin()+NewNumElts,
4960 HiOps.push_back(NewNumEltsNode);
4961 HiOps.push_back(TypeNode);
4962 Hi = DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, &HiOps[0], HiOps.size());
4973 SDOperand LL, LH, RL, RH;
4974 SplitVectorOp(Node->getOperand(0), LL, LH);
4975 SplitVectorOp(Node->getOperand(1), RL, RH);
4977 Lo = DAG.getNode(Node->getOpcode(), MVT::Vector, LL, RL,
4978 NewNumEltsNode, TypeNode);
4979 Hi = DAG.getNode(Node->getOpcode(), MVT::Vector, LH, RH,
4980 NewNumEltsNode, TypeNode);
4984 SDOperand Ch = Node->getOperand(0); // Legalize the chain.
4985 SDOperand Ptr = Node->getOperand(1); // Legalize the pointer.
4986 MVT::ValueType EVT = cast<VTSDNode>(TypeNode)->getVT();
4988 Lo = DAG.getVecLoad(NewNumElts, EVT, Ch, Ptr, Node->getOperand(2));
4989 unsigned IncrementSize = NewNumElts * MVT::getSizeInBits(EVT)/8;
4990 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
4991 getIntPtrConstant(IncrementSize));
4992 // FIXME: This creates a bogus srcvalue!
4993 Hi = DAG.getVecLoad(NewNumElts, EVT, Ch, Ptr, Node->getOperand(2));
4995 // Build a factor node to remember that this load is independent of the
4997 SDOperand TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
5000 // Remember that we legalized the chain.
5001 AddLegalizedOperand(Op.getValue(1), LegalizeOp(TF));
5004 case ISD::VBIT_CONVERT: {
5005 // We know the result is a vector. The input may be either a vector or a
5007 if (Op.getOperand(0).getValueType() != MVT::Vector) {
5008 // Lower to a store/load. FIXME: this could be improved probably.
5009 SDOperand Ptr = CreateStackTemporary(Op.getOperand(0).getValueType());
5011 SDOperand St = DAG.getStore(DAG.getEntryNode(),
5012 Op.getOperand(0), Ptr, NULL, 0);
5013 MVT::ValueType EVT = cast<VTSDNode>(TypeNode)->getVT();
5014 St = DAG.getVecLoad(NumElements, EVT, St, Ptr, DAG.getSrcValue(0));
5015 SplitVectorOp(St, Lo, Hi);
5017 // If the input is a vector type, we have to either scalarize it, pack it
5018 // or convert it based on whether the input vector type is legal.
5019 SDNode *InVal = Node->getOperand(0).Val;
5021 cast<ConstantSDNode>(*(InVal->op_end()-2))->getValue();
5022 MVT::ValueType EVT = cast<VTSDNode>(*(InVal->op_end()-1))->getVT();
5024 // If the input is from a single element vector, scalarize the vector,
5025 // then treat like a scalar.
5026 if (NumElems == 1) {
5027 SDOperand Scalar = PackVectorOp(Op.getOperand(0), EVT);
5028 Scalar = DAG.getNode(ISD::VBIT_CONVERT, MVT::Vector, Scalar,
5029 Op.getOperand(1), Op.getOperand(2));
5030 SplitVectorOp(Scalar, Lo, Hi);
5032 // Split the input vector.
5033 SplitVectorOp(Op.getOperand(0), Lo, Hi);
5035 // Convert each of the pieces now.
5036 Lo = DAG.getNode(ISD::VBIT_CONVERT, MVT::Vector, Lo,
5037 NewNumEltsNode, TypeNode);
5038 Hi = DAG.getNode(ISD::VBIT_CONVERT, MVT::Vector, Hi,
5039 NewNumEltsNode, TypeNode);
5046 // Remember in a map if the values will be reused later.
5048 SplitNodes.insert(std::make_pair(Op, std::make_pair(Lo, Hi))).second;
5049 assert(isNew && "Value already expanded?!?");
5053 /// PackVectorOp - Given an operand of MVT::Vector type, convert it into the
5054 /// equivalent operation that returns a scalar (e.g. F32) or packed value
5055 /// (e.g. MVT::V4F32). When this is called, we know that PackedVT is the right
5056 /// type for the result.
5057 SDOperand SelectionDAGLegalize::PackVectorOp(SDOperand Op,
5058 MVT::ValueType NewVT) {
5059 assert(Op.getValueType() == MVT::Vector && "Bad PackVectorOp invocation!");
5060 SDNode *Node = Op.Val;
5062 // See if we already packed it.
5063 std::map<SDOperand, SDOperand>::iterator I = PackedNodes.find(Op);
5064 if (I != PackedNodes.end()) return I->second;
5067 switch (Node->getOpcode()) {
5070 Node->dump(); cerr << "\n";
5072 assert(0 && "Unknown vector operation in PackVectorOp!");
5081 Result = DAG.getNode(getScalarizedOpcode(Node->getOpcode(), NewVT),
5083 PackVectorOp(Node->getOperand(0), NewVT),
5084 PackVectorOp(Node->getOperand(1), NewVT));
5087 SDOperand Ch = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
5088 SDOperand Ptr = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
5090 SrcValueSDNode *SV = cast<SrcValueSDNode>(Node->getOperand(2));
5091 Result = DAG.getLoad(NewVT, Ch, Ptr, SV->getValue(), SV->getOffset());
5093 // Remember that we legalized the chain.
5094 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
5097 case ISD::VBUILD_VECTOR:
5098 if (Node->getOperand(0).getValueType() == NewVT) {
5099 // Returning a scalar?
5100 Result = Node->getOperand(0);
5102 // Returning a BUILD_VECTOR?
5104 // If all elements of the build_vector are undefs, return an undef.
5105 bool AllUndef = true;
5106 for (unsigned i = 0, e = Node->getNumOperands()-2; i != e; ++i)
5107 if (Node->getOperand(i).getOpcode() != ISD::UNDEF) {
5112 Result = DAG.getNode(ISD::UNDEF, NewVT);
5114 Result = DAG.getNode(ISD::BUILD_VECTOR, NewVT, Node->op_begin(),
5115 Node->getNumOperands()-2);
5119 case ISD::VINSERT_VECTOR_ELT:
5120 if (!MVT::isVector(NewVT)) {
5121 // Returning a scalar? Must be the inserted element.
5122 Result = Node->getOperand(1);
5124 Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, NewVT,
5125 PackVectorOp(Node->getOperand(0), NewVT),
5126 Node->getOperand(1), Node->getOperand(2));
5129 case ISD::VVECTOR_SHUFFLE:
5130 if (!MVT::isVector(NewVT)) {
5131 // Returning a scalar? Figure out if it is the LHS or RHS and return it.
5132 SDOperand EltNum = Node->getOperand(2).getOperand(0);
5133 if (cast<ConstantSDNode>(EltNum)->getValue())
5134 Result = PackVectorOp(Node->getOperand(1), NewVT);
5136 Result = PackVectorOp(Node->getOperand(0), NewVT);
5138 // Otherwise, return a VECTOR_SHUFFLE node. First convert the index
5139 // vector from a VBUILD_VECTOR to a BUILD_VECTOR.
5140 std::vector<SDOperand> BuildVecIdx(Node->getOperand(2).Val->op_begin(),
5141 Node->getOperand(2).Val->op_end()-2);
5142 MVT::ValueType BVT = MVT::getIntVectorWithNumElements(BuildVecIdx.size());
5143 SDOperand BV = DAG.getNode(ISD::BUILD_VECTOR, BVT,
5144 Node->getOperand(2).Val->op_begin(),
5145 Node->getOperand(2).Val->getNumOperands()-2);
5147 Result = DAG.getNode(ISD::VECTOR_SHUFFLE, NewVT,
5148 PackVectorOp(Node->getOperand(0), NewVT),
5149 PackVectorOp(Node->getOperand(1), NewVT), BV);
5152 case ISD::VBIT_CONVERT:
5153 if (Op.getOperand(0).getValueType() != MVT::Vector)
5154 Result = DAG.getNode(ISD::BIT_CONVERT, NewVT, Op.getOperand(0));
5156 // If the input is a vector type, we have to either scalarize it, pack it
5157 // or convert it based on whether the input vector type is legal.
5158 SDNode *InVal = Node->getOperand(0).Val;
5160 cast<ConstantSDNode>(*(InVal->op_end()-2))->getValue();
5161 MVT::ValueType EVT = cast<VTSDNode>(*(InVal->op_end()-1))->getVT();
5163 // Figure out if there is a Packed type corresponding to this Vector
5164 // type. If so, convert to the packed type.
5165 MVT::ValueType TVT = MVT::getVectorType(EVT, NumElems);
5166 if (TVT != MVT::Other && TLI.isTypeLegal(TVT)) {
5167 // Turn this into a bit convert of the packed input.
5168 Result = DAG.getNode(ISD::BIT_CONVERT, NewVT,
5169 PackVectorOp(Node->getOperand(0), TVT));
5171 } else if (NumElems == 1) {
5172 // Turn this into a bit convert of the scalar input.
5173 Result = DAG.getNode(ISD::BIT_CONVERT, NewVT,
5174 PackVectorOp(Node->getOperand(0), EVT));
5178 assert(0 && "Cast from unsupported vector type not implemented yet!");
5183 Result = DAG.getNode(ISD::SELECT, NewVT, Op.getOperand(0),
5184 PackVectorOp(Op.getOperand(1), NewVT),
5185 PackVectorOp(Op.getOperand(2), NewVT));
5189 if (TLI.isTypeLegal(NewVT))
5190 Result = LegalizeOp(Result);
5191 bool isNew = PackedNodes.insert(std::make_pair(Op, Result)).second;
5192 assert(isNew && "Value already packed?");
5197 // SelectionDAG::Legalize - This is the entry point for the file.
5199 void SelectionDAG::Legalize() {
5200 if (ViewLegalizeDAGs) viewGraph();
5202 /// run - This is the main entry point to this class.
5204 SelectionDAGLegalize(*this).LegalizeDAG();