1 //===-- LegalizeDAG.cpp - Implement SelectionDAG::Legalize ----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the SelectionDAG::Legalize method.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/CodeGen/SelectionDAG.h"
15 #include "llvm/CodeGen/MachineFunction.h"
16 #include "llvm/CodeGen/MachineFrameInfo.h"
17 #include "llvm/CodeGen/MachineJumpTableInfo.h"
18 #include "llvm/CodeGen/MachineModuleInfo.h"
19 #include "llvm/CodeGen/PseudoSourceValue.h"
20 #include "llvm/Target/TargetFrameInfo.h"
21 #include "llvm/Target/TargetLowering.h"
22 #include "llvm/Target/TargetData.h"
23 #include "llvm/Target/TargetMachine.h"
24 #include "llvm/Target/TargetOptions.h"
25 #include "llvm/Target/TargetSubtarget.h"
26 #include "llvm/CallingConv.h"
27 #include "llvm/Constants.h"
28 #include "llvm/DerivedTypes.h"
29 #include "llvm/Support/CommandLine.h"
30 #include "llvm/Support/Compiler.h"
31 #include "llvm/Support/MathExtras.h"
32 #include "llvm/ADT/DenseMap.h"
33 #include "llvm/ADT/SmallVector.h"
34 #include "llvm/ADT/SmallPtrSet.h"
38 //===----------------------------------------------------------------------===//
39 /// SelectionDAGLegalize - This takes an arbitrary SelectionDAG as input and
40 /// hacks on it until the target machine can handle it. This involves
41 /// eliminating value sizes the machine cannot handle (promoting small sizes to
42 /// large sizes or splitting up large values into small values) as well as
43 /// eliminating operations the machine cannot handle.
45 /// This code also does a small amount of optimization and recognition of idioms
46 /// as part of its processing. For example, if a target does not support a
47 /// 'setcc' instruction efficiently, but does support 'brcc' instruction, this
48 /// will attempt merge setcc and brc instructions into brcc's.
51 class VISIBILITY_HIDDEN SelectionDAGLegalize {
55 // Libcall insertion helpers.
57 /// LastCALLSEQ_END - This keeps track of the CALLSEQ_END node that has been
58 /// legalized. We use this to ensure that calls are properly serialized
59 /// against each other, including inserted libcalls.
60 SDValue LastCALLSEQ_END;
62 /// IsLegalizingCall - This member is used *only* for purposes of providing
63 /// helpful assertions that a libcall isn't created while another call is
64 /// being legalized (which could lead to non-serialized call sequences).
65 bool IsLegalizingCall;
68 Legal, // The target natively supports this operation.
69 Promote, // This operation should be executed in a larger type.
70 Expand // Try to expand this to other ops, otherwise use a libcall.
73 /// ValueTypeActions - This is a bitvector that contains two bits for each
74 /// value type, where the two bits correspond to the LegalizeAction enum.
75 /// This can be queried with "getTypeAction(VT)".
76 TargetLowering::ValueTypeActionImpl ValueTypeActions;
78 /// LegalizedNodes - For nodes that are of legal width, and that have more
79 /// than one use, this map indicates what regularized operand to use. This
80 /// allows us to avoid legalizing the same thing more than once.
81 DenseMap<SDValue, SDValue> LegalizedNodes;
83 /// PromotedNodes - For nodes that are below legal width, and that have more
84 /// than one use, this map indicates what promoted value to use. This allows
85 /// us to avoid promoting the same thing more than once.
86 DenseMap<SDValue, SDValue> PromotedNodes;
88 /// ExpandedNodes - For nodes that need to be expanded this map indicates
89 /// which which operands are the expanded version of the input. This allows
90 /// us to avoid expanding the same node more than once.
91 DenseMap<SDValue, std::pair<SDValue, SDValue> > ExpandedNodes;
93 /// SplitNodes - For vector nodes that need to be split, this map indicates
94 /// which which operands are the split version of the input. This allows us
95 /// to avoid splitting the same node more than once.
96 std::map<SDValue, std::pair<SDValue, SDValue> > SplitNodes;
98 /// ScalarizedNodes - For nodes that need to be converted from vector types to
99 /// scalar types, this contains the mapping of ones we have already
100 /// processed to the result.
101 std::map<SDValue, SDValue> ScalarizedNodes;
103 void AddLegalizedOperand(SDValue From, SDValue To) {
104 LegalizedNodes.insert(std::make_pair(From, To));
105 // If someone requests legalization of the new node, return itself.
107 LegalizedNodes.insert(std::make_pair(To, To));
109 void AddPromotedOperand(SDValue From, SDValue To) {
110 bool isNew = PromotedNodes.insert(std::make_pair(From, To)).second;
111 assert(isNew && "Got into the map somehow?");
112 // If someone requests legalization of the new node, return itself.
113 LegalizedNodes.insert(std::make_pair(To, To));
117 explicit SelectionDAGLegalize(SelectionDAG &DAG);
119 /// getTypeAction - Return how we should legalize values of this type, either
120 /// it is already legal or we need to expand it into multiple registers of
121 /// smaller integer type, or we need to promote it to a larger type.
122 LegalizeAction getTypeAction(MVT VT) const {
123 return (LegalizeAction)ValueTypeActions.getTypeAction(VT);
126 /// isTypeLegal - Return true if this type is legal on this target.
128 bool isTypeLegal(MVT VT) const {
129 return getTypeAction(VT) == Legal;
135 /// HandleOp - Legalize, Promote, or Expand the specified operand as
136 /// appropriate for its type.
137 void HandleOp(SDValue Op);
139 /// LegalizeOp - We know that the specified value has a legal type.
140 /// Recursively ensure that the operands have legal types, then return the
142 SDValue LegalizeOp(SDValue O);
144 /// UnrollVectorOp - We know that the given vector has a legal type, however
145 /// the operation it performs is not legal and is an operation that we have
146 /// no way of lowering. "Unroll" the vector, splitting out the scalars and
147 /// operating on each element individually.
148 SDValue UnrollVectorOp(SDValue O);
150 /// PerformInsertVectorEltInMemory - Some target cannot handle a variable
151 /// insertion index for the INSERT_VECTOR_ELT instruction. In this case, it
152 /// is necessary to spill the vector being inserted into to memory, perform
153 /// the insert there, and then read the result back.
154 SDValue PerformInsertVectorEltInMemory(SDValue Vec, SDValue Val,
157 /// PromoteOp - Given an operation that produces a value in an invalid type,
158 /// promote it to compute the value into a larger type. The produced value
159 /// will have the correct bits for the low portion of the register, but no
160 /// guarantee is made about the top bits: it may be zero, sign-extended, or
162 SDValue PromoteOp(SDValue O);
164 /// ExpandOp - Expand the specified SDValue into its two component pieces
165 /// Lo&Hi. Note that the Op MUST be an expanded type. As a result of this,
166 /// the LegalizedNodes map is filled in for any results that are not expanded,
167 /// the ExpandedNodes map is filled in for any results that are expanded, and
168 /// the Lo/Hi values are returned. This applies to integer types and Vector
170 void ExpandOp(SDValue O, SDValue &Lo, SDValue &Hi);
172 /// SplitVectorOp - Given an operand of vector type, break it down into
173 /// two smaller values.
174 void SplitVectorOp(SDValue O, SDValue &Lo, SDValue &Hi);
176 /// ScalarizeVectorOp - Given an operand of single-element vector type
177 /// (e.g. v1f32), convert it into the equivalent operation that returns a
178 /// scalar (e.g. f32) value.
179 SDValue ScalarizeVectorOp(SDValue O);
181 /// isShuffleLegal - Return non-null if a vector shuffle is legal with the
182 /// specified mask and type. Targets can specify exactly which masks they
183 /// support and the code generator is tasked with not creating illegal masks.
185 /// Note that this will also return true for shuffles that are promoted to a
188 /// If this is a legal shuffle, this method returns the (possibly promoted)
189 /// build_vector Mask. If it's not a legal shuffle, it returns null.
190 SDNode *isShuffleLegal(MVT VT, SDValue Mask) const;
192 bool LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest,
193 SmallPtrSet<SDNode*, 32> &NodesLeadingTo);
195 void LegalizeSetCCOperands(SDValue &LHS, SDValue &RHS, SDValue &CC);
197 SDValue ExpandLibCall(RTLIB::Libcall LC, SDNode *Node, bool isSigned,
199 SDValue ExpandIntToFP(bool isSigned, MVT DestTy, SDValue Source);
201 SDValue EmitStackConvert(SDValue SrcOp, MVT SlotVT, MVT DestVT);
202 SDValue ExpandBUILD_VECTOR(SDNode *Node);
203 SDValue ExpandSCALAR_TO_VECTOR(SDNode *Node);
204 SDValue LegalizeINT_TO_FP(SDValue Result, bool isSigned, MVT DestTy, SDValue Op);
205 SDValue ExpandLegalINT_TO_FP(bool isSigned, SDValue LegalOp, MVT DestVT);
206 SDValue PromoteLegalINT_TO_FP(SDValue LegalOp, MVT DestVT, bool isSigned);
207 SDValue PromoteLegalFP_TO_INT(SDValue LegalOp, MVT DestVT, bool isSigned);
209 SDValue ExpandBSWAP(SDValue Op);
210 SDValue ExpandBitCount(unsigned Opc, SDValue Op);
211 bool ExpandShift(unsigned Opc, SDValue Op, SDValue Amt,
212 SDValue &Lo, SDValue &Hi);
213 void ExpandShiftParts(unsigned NodeOp, SDValue Op, SDValue Amt,
214 SDValue &Lo, SDValue &Hi);
216 SDValue ExpandEXTRACT_SUBVECTOR(SDValue Op);
217 SDValue ExpandEXTRACT_VECTOR_ELT(SDValue Op);
221 /// isVectorShuffleLegal - Return true if a vector shuffle is legal with the
222 /// specified mask and type. Targets can specify exactly which masks they
223 /// support and the code generator is tasked with not creating illegal masks.
225 /// Note that this will also return true for shuffles that are promoted to a
227 SDNode *SelectionDAGLegalize::isShuffleLegal(MVT VT, SDValue Mask) const {
228 switch (TLI.getOperationAction(ISD::VECTOR_SHUFFLE, VT)) {
230 case TargetLowering::Legal:
231 case TargetLowering::Custom:
233 case TargetLowering::Promote: {
234 // If this is promoted to a different type, convert the shuffle mask and
235 // ask if it is legal in the promoted type!
236 MVT NVT = TLI.getTypeToPromoteTo(ISD::VECTOR_SHUFFLE, VT);
237 MVT EltVT = NVT.getVectorElementType();
239 // If we changed # elements, change the shuffle mask.
240 unsigned NumEltsGrowth =
241 NVT.getVectorNumElements() / VT.getVectorNumElements();
242 assert(NumEltsGrowth && "Cannot promote to vector type with fewer elts!");
243 if (NumEltsGrowth > 1) {
244 // Renumber the elements.
245 SmallVector<SDValue, 8> Ops;
246 for (unsigned i = 0, e = Mask.getNumOperands(); i != e; ++i) {
247 SDValue InOp = Mask.getOperand(i);
248 for (unsigned j = 0; j != NumEltsGrowth; ++j) {
249 if (InOp.getOpcode() == ISD::UNDEF)
250 Ops.push_back(DAG.getNode(ISD::UNDEF, EltVT));
252 unsigned InEltNo = cast<ConstantSDNode>(InOp)->getZExtValue();
253 Ops.push_back(DAG.getConstant(InEltNo*NumEltsGrowth+j, EltVT));
257 Mask = DAG.getNode(ISD::BUILD_VECTOR, NVT, &Ops[0], Ops.size());
263 return TLI.isShuffleMaskLegal(Mask, VT) ? Mask.getNode() : 0;
266 SelectionDAGLegalize::SelectionDAGLegalize(SelectionDAG &dag)
267 : TLI(dag.getTargetLoweringInfo()), DAG(dag),
268 ValueTypeActions(TLI.getValueTypeActions()) {
269 assert(MVT::LAST_VALUETYPE <= 32 &&
270 "Too many value types for ValueTypeActions to hold!");
273 void SelectionDAGLegalize::LegalizeDAG() {
274 LastCALLSEQ_END = DAG.getEntryNode();
275 IsLegalizingCall = false;
277 // The legalize process is inherently a bottom-up recursive process (users
278 // legalize their uses before themselves). Given infinite stack space, we
279 // could just start legalizing on the root and traverse the whole graph. In
280 // practice however, this causes us to run out of stack space on large basic
281 // blocks. To avoid this problem, compute an ordering of the nodes where each
282 // node is only legalized after all of its operands are legalized.
283 DAG.AssignTopologicalOrder();
284 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(),
285 E = prior(DAG.allnodes_end()); I != next(E); ++I)
286 HandleOp(SDValue(I, 0));
288 // Finally, it's possible the root changed. Get the new root.
289 SDValue OldRoot = DAG.getRoot();
290 assert(LegalizedNodes.count(OldRoot) && "Root didn't get legalized?");
291 DAG.setRoot(LegalizedNodes[OldRoot]);
293 ExpandedNodes.clear();
294 LegalizedNodes.clear();
295 PromotedNodes.clear();
297 ScalarizedNodes.clear();
299 // Remove dead nodes now.
300 DAG.RemoveDeadNodes();
304 /// FindCallEndFromCallStart - Given a chained node that is part of a call
305 /// sequence, find the CALLSEQ_END node that terminates the call sequence.
306 static SDNode *FindCallEndFromCallStart(SDNode *Node) {
307 if (Node->getOpcode() == ISD::CALLSEQ_END)
309 if (Node->use_empty())
310 return 0; // No CallSeqEnd
312 // The chain is usually at the end.
313 SDValue TheChain(Node, Node->getNumValues()-1);
314 if (TheChain.getValueType() != MVT::Other) {
315 // Sometimes it's at the beginning.
316 TheChain = SDValue(Node, 0);
317 if (TheChain.getValueType() != MVT::Other) {
318 // Otherwise, hunt for it.
319 for (unsigned i = 1, e = Node->getNumValues(); i != e; ++i)
320 if (Node->getValueType(i) == MVT::Other) {
321 TheChain = SDValue(Node, i);
325 // Otherwise, we walked into a node without a chain.
326 if (TheChain.getValueType() != MVT::Other)
331 for (SDNode::use_iterator UI = Node->use_begin(),
332 E = Node->use_end(); UI != E; ++UI) {
334 // Make sure to only follow users of our token chain.
336 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i)
337 if (User->getOperand(i) == TheChain)
338 if (SDNode *Result = FindCallEndFromCallStart(User))
344 /// FindCallStartFromCallEnd - Given a chained node that is part of a call
345 /// sequence, find the CALLSEQ_START node that initiates the call sequence.
346 static SDNode *FindCallStartFromCallEnd(SDNode *Node) {
347 assert(Node && "Didn't find callseq_start for a call??");
348 if (Node->getOpcode() == ISD::CALLSEQ_START) return Node;
350 assert(Node->getOperand(0).getValueType() == MVT::Other &&
351 "Node doesn't have a token chain argument!");
352 return FindCallStartFromCallEnd(Node->getOperand(0).getNode());
355 /// LegalizeAllNodesNotLeadingTo - Recursively walk the uses of N, looking to
356 /// see if any uses can reach Dest. If no dest operands can get to dest,
357 /// legalize them, legalize ourself, and return false, otherwise, return true.
359 /// Keep track of the nodes we fine that actually do lead to Dest in
360 /// NodesLeadingTo. This avoids retraversing them exponential number of times.
362 bool SelectionDAGLegalize::LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest,
363 SmallPtrSet<SDNode*, 32> &NodesLeadingTo) {
364 if (N == Dest) return true; // N certainly leads to Dest :)
366 // If we've already processed this node and it does lead to Dest, there is no
367 // need to reprocess it.
368 if (NodesLeadingTo.count(N)) return true;
370 // If the first result of this node has been already legalized, then it cannot
372 switch (getTypeAction(N->getValueType(0))) {
374 if (LegalizedNodes.count(SDValue(N, 0))) return false;
377 if (PromotedNodes.count(SDValue(N, 0))) return false;
380 if (ExpandedNodes.count(SDValue(N, 0))) return false;
384 // Okay, this node has not already been legalized. Check and legalize all
385 // operands. If none lead to Dest, then we can legalize this node.
386 bool OperandsLeadToDest = false;
387 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
388 OperandsLeadToDest |= // If an operand leads to Dest, so do we.
389 LegalizeAllNodesNotLeadingTo(N->getOperand(i).getNode(), Dest, NodesLeadingTo);
391 if (OperandsLeadToDest) {
392 NodesLeadingTo.insert(N);
396 // Okay, this node looks safe, legalize it and return false.
397 HandleOp(SDValue(N, 0));
401 /// HandleOp - Legalize, Promote, or Expand the specified operand as
402 /// appropriate for its type.
403 void SelectionDAGLegalize::HandleOp(SDValue Op) {
404 MVT VT = Op.getValueType();
405 switch (getTypeAction(VT)) {
406 default: assert(0 && "Bad type action!");
407 case Legal: (void)LegalizeOp(Op); break;
408 case Promote: (void)PromoteOp(Op); break;
410 if (!VT.isVector()) {
411 // If this is an illegal scalar, expand it into its two component
414 if (Op.getOpcode() == ISD::TargetConstant)
415 break; // Allow illegal target nodes.
417 } else if (VT.getVectorNumElements() == 1) {
418 // If this is an illegal single element vector, convert it to a
420 (void)ScalarizeVectorOp(Op);
422 // Otherwise, this is an illegal multiple element vector.
423 // Split it in half and legalize both parts.
425 SplitVectorOp(Op, X, Y);
431 /// ExpandConstantFP - Expands the ConstantFP node to an integer constant or
432 /// a load from the constant pool.
433 static SDValue ExpandConstantFP(ConstantFPSDNode *CFP, bool UseCP,
434 SelectionDAG &DAG, TargetLowering &TLI) {
437 // If a FP immediate is precise when represented as a float and if the
438 // target can do an extending load from float to double, we put it into
439 // the constant pool as a float, even if it's is statically typed as a
440 // double. This shrinks FP constants and canonicalizes them for targets where
441 // an FP extending load is the same cost as a normal load (such as on the x87
442 // fp stack or PPC FP unit).
443 MVT VT = CFP->getValueType(0);
444 ConstantFP *LLVMC = const_cast<ConstantFP*>(CFP->getConstantFPValue());
446 if (VT!=MVT::f64 && VT!=MVT::f32)
447 assert(0 && "Invalid type expansion");
448 return DAG.getConstant(LLVMC->getValueAPF().convertToAPInt(),
449 (VT == MVT::f64) ? MVT::i64 : MVT::i32);
454 while (SVT != MVT::f32) {
455 SVT = (MVT::SimpleValueType)(SVT.getSimpleVT() - 1);
456 if (CFP->isValueValidForType(SVT, CFP->getValueAPF()) &&
457 // Only do this if the target has a native EXTLOAD instruction from
459 TLI.isLoadXLegal(ISD::EXTLOAD, SVT) &&
460 TLI.ShouldShrinkFPConstant(OrigVT)) {
461 const Type *SType = SVT.getTypeForMVT();
462 LLVMC = cast<ConstantFP>(ConstantExpr::getFPTrunc(LLVMC, SType));
468 SDValue CPIdx = DAG.getConstantPool(LLVMC, TLI.getPointerTy());
469 unsigned Alignment = 1 << cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
471 return DAG.getExtLoad(ISD::EXTLOAD, OrigVT, DAG.getEntryNode(),
472 CPIdx, PseudoSourceValue::getConstantPool(),
473 0, VT, false, Alignment);
474 return DAG.getLoad(OrigVT, DAG.getEntryNode(), CPIdx,
475 PseudoSourceValue::getConstantPool(), 0, false, Alignment);
479 /// ExpandFCOPYSIGNToBitwiseOps - Expands fcopysign to a series of bitwise
482 SDValue ExpandFCOPYSIGNToBitwiseOps(SDNode *Node, MVT NVT,
483 SelectionDAG &DAG, TargetLowering &TLI) {
484 MVT VT = Node->getValueType(0);
485 MVT SrcVT = Node->getOperand(1).getValueType();
486 assert((SrcVT == MVT::f32 || SrcVT == MVT::f64) &&
487 "fcopysign expansion only supported for f32 and f64");
488 MVT SrcNVT = (SrcVT == MVT::f64) ? MVT::i64 : MVT::i32;
490 // First get the sign bit of second operand.
491 SDValue Mask1 = (SrcVT == MVT::f64)
492 ? DAG.getConstantFP(BitsToDouble(1ULL << 63), SrcVT)
493 : DAG.getConstantFP(BitsToFloat(1U << 31), SrcVT);
494 Mask1 = DAG.getNode(ISD::BIT_CONVERT, SrcNVT, Mask1);
495 SDValue SignBit= DAG.getNode(ISD::BIT_CONVERT, SrcNVT, Node->getOperand(1));
496 SignBit = DAG.getNode(ISD::AND, SrcNVT, SignBit, Mask1);
497 // Shift right or sign-extend it if the two operands have different types.
498 int SizeDiff = SrcNVT.getSizeInBits() - NVT.getSizeInBits();
500 SignBit = DAG.getNode(ISD::SRL, SrcNVT, SignBit,
501 DAG.getConstant(SizeDiff, TLI.getShiftAmountTy()));
502 SignBit = DAG.getNode(ISD::TRUNCATE, NVT, SignBit);
503 } else if (SizeDiff < 0) {
504 SignBit = DAG.getNode(ISD::ZERO_EXTEND, NVT, SignBit);
505 SignBit = DAG.getNode(ISD::SHL, NVT, SignBit,
506 DAG.getConstant(-SizeDiff, TLI.getShiftAmountTy()));
509 // Clear the sign bit of first operand.
510 SDValue Mask2 = (VT == MVT::f64)
511 ? DAG.getConstantFP(BitsToDouble(~(1ULL << 63)), VT)
512 : DAG.getConstantFP(BitsToFloat(~(1U << 31)), VT);
513 Mask2 = DAG.getNode(ISD::BIT_CONVERT, NVT, Mask2);
514 SDValue Result = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0));
515 Result = DAG.getNode(ISD::AND, NVT, Result, Mask2);
517 // Or the value with the sign bit.
518 Result = DAG.getNode(ISD::OR, NVT, Result, SignBit);
522 /// ExpandUnalignedStore - Expands an unaligned store to 2 half-size stores.
524 SDValue ExpandUnalignedStore(StoreSDNode *ST, SelectionDAG &DAG,
525 TargetLowering &TLI) {
526 SDValue Chain = ST->getChain();
527 SDValue Ptr = ST->getBasePtr();
528 SDValue Val = ST->getValue();
529 MVT VT = Val.getValueType();
530 int Alignment = ST->getAlignment();
531 int SVOffset = ST->getSrcValueOffset();
532 if (ST->getMemoryVT().isFloatingPoint() ||
533 ST->getMemoryVT().isVector()) {
534 // Expand to a bitconvert of the value to the integer type of the
535 // same size, then a (misaligned) int store.
537 if (VT.is128BitVector() || VT == MVT::ppcf128 || VT == MVT::f128)
539 else if (VT.is64BitVector() || VT==MVT::f64)
541 else if (VT==MVT::f32)
544 assert(0 && "Unaligned store of unsupported type");
546 SDValue Result = DAG.getNode(ISD::BIT_CONVERT, intVT, Val);
547 return DAG.getStore(Chain, Result, Ptr, ST->getSrcValue(),
548 SVOffset, ST->isVolatile(), Alignment);
550 assert(ST->getMemoryVT().isInteger() &&
551 !ST->getMemoryVT().isVector() &&
552 "Unaligned store of unknown type.");
553 // Get the half-size VT
555 (MVT::SimpleValueType)(ST->getMemoryVT().getSimpleVT() - 1);
556 int NumBits = NewStoredVT.getSizeInBits();
557 int IncrementSize = NumBits / 8;
559 // Divide the stored value in two parts.
560 SDValue ShiftAmount = DAG.getConstant(NumBits, TLI.getShiftAmountTy());
562 SDValue Hi = DAG.getNode(ISD::SRL, VT, Val, ShiftAmount);
564 // Store the two parts
565 SDValue Store1, Store2;
566 Store1 = DAG.getTruncStore(Chain, TLI.isLittleEndian()?Lo:Hi, Ptr,
567 ST->getSrcValue(), SVOffset, NewStoredVT,
568 ST->isVolatile(), Alignment);
569 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
570 DAG.getConstant(IncrementSize, TLI.getPointerTy()));
571 Alignment = MinAlign(Alignment, IncrementSize);
572 Store2 = DAG.getTruncStore(Chain, TLI.isLittleEndian()?Hi:Lo, Ptr,
573 ST->getSrcValue(), SVOffset + IncrementSize,
574 NewStoredVT, ST->isVolatile(), Alignment);
576 return DAG.getNode(ISD::TokenFactor, MVT::Other, Store1, Store2);
579 /// ExpandUnalignedLoad - Expands an unaligned load to 2 half-size loads.
581 SDValue ExpandUnalignedLoad(LoadSDNode *LD, SelectionDAG &DAG,
582 TargetLowering &TLI) {
583 int SVOffset = LD->getSrcValueOffset();
584 SDValue Chain = LD->getChain();
585 SDValue Ptr = LD->getBasePtr();
586 MVT VT = LD->getValueType(0);
587 MVT LoadedVT = LD->getMemoryVT();
588 if (VT.isFloatingPoint() || VT.isVector()) {
589 // Expand to a (misaligned) integer load of the same size,
590 // then bitconvert to floating point or vector.
592 if (LoadedVT.is128BitVector() ||
593 LoadedVT == MVT::ppcf128 || LoadedVT == MVT::f128)
595 else if (LoadedVT.is64BitVector() || LoadedVT == MVT::f64)
597 else if (LoadedVT == MVT::f32)
600 assert(0 && "Unaligned load of unsupported type");
602 SDValue newLoad = DAG.getLoad(intVT, Chain, Ptr, LD->getSrcValue(),
603 SVOffset, LD->isVolatile(),
605 SDValue Result = DAG.getNode(ISD::BIT_CONVERT, LoadedVT, newLoad);
606 if (VT.isFloatingPoint() && LoadedVT != VT)
607 Result = DAG.getNode(ISD::FP_EXTEND, VT, Result);
609 SDValue Ops[] = { Result, Chain };
610 return DAG.getMergeValues(Ops, 2);
612 assert(LoadedVT.isInteger() && !LoadedVT.isVector() &&
613 "Unaligned load of unsupported type.");
615 // Compute the new VT that is half the size of the old one. This is an
617 unsigned NumBits = LoadedVT.getSizeInBits();
619 NewLoadedVT = MVT::getIntegerVT(NumBits/2);
622 unsigned Alignment = LD->getAlignment();
623 unsigned IncrementSize = NumBits / 8;
624 ISD::LoadExtType HiExtType = LD->getExtensionType();
626 // If the original load is NON_EXTLOAD, the hi part load must be ZEXTLOAD.
627 if (HiExtType == ISD::NON_EXTLOAD)
628 HiExtType = ISD::ZEXTLOAD;
630 // Load the value in two parts
632 if (TLI.isLittleEndian()) {
633 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, VT, Chain, Ptr, LD->getSrcValue(),
634 SVOffset, NewLoadedVT, LD->isVolatile(), Alignment);
635 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
636 DAG.getConstant(IncrementSize, TLI.getPointerTy()));
637 Hi = DAG.getExtLoad(HiExtType, VT, Chain, Ptr, LD->getSrcValue(),
638 SVOffset + IncrementSize, NewLoadedVT, LD->isVolatile(),
639 MinAlign(Alignment, IncrementSize));
641 Hi = DAG.getExtLoad(HiExtType, VT, Chain, Ptr, LD->getSrcValue(), SVOffset,
642 NewLoadedVT,LD->isVolatile(), Alignment);
643 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
644 DAG.getConstant(IncrementSize, TLI.getPointerTy()));
645 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, VT, Chain, Ptr, LD->getSrcValue(),
646 SVOffset + IncrementSize, NewLoadedVT, LD->isVolatile(),
647 MinAlign(Alignment, IncrementSize));
650 // aggregate the two parts
651 SDValue ShiftAmount = DAG.getConstant(NumBits, TLI.getShiftAmountTy());
652 SDValue Result = DAG.getNode(ISD::SHL, VT, Hi, ShiftAmount);
653 Result = DAG.getNode(ISD::OR, VT, Result, Lo);
655 SDValue TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
658 SDValue Ops[] = { Result, TF };
659 return DAG.getMergeValues(Ops, 2);
662 /// UnrollVectorOp - We know that the given vector has a legal type, however
663 /// the operation it performs is not legal and is an operation that we have
664 /// no way of lowering. "Unroll" the vector, splitting out the scalars and
665 /// operating on each element individually.
666 SDValue SelectionDAGLegalize::UnrollVectorOp(SDValue Op) {
667 MVT VT = Op.getValueType();
668 assert(isTypeLegal(VT) &&
669 "Caller should expand or promote operands that are not legal!");
670 assert(Op.getNode()->getNumValues() == 1 &&
671 "Can't unroll a vector with multiple results!");
672 unsigned NE = VT.getVectorNumElements();
673 MVT EltVT = VT.getVectorElementType();
675 SmallVector<SDValue, 8> Scalars;
676 SmallVector<SDValue, 4> Operands(Op.getNumOperands());
677 for (unsigned i = 0; i != NE; ++i) {
678 for (unsigned j = 0; j != Op.getNumOperands(); ++j) {
679 SDValue Operand = Op.getOperand(j);
680 MVT OperandVT = Operand.getValueType();
681 if (OperandVT.isVector()) {
682 // A vector operand; extract a single element.
683 MVT OperandEltVT = OperandVT.getVectorElementType();
684 Operands[j] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT,
687 DAG.getConstant(i, MVT::i32));
689 // A scalar operand; just use it as is.
690 Operands[j] = Operand;
693 Scalars.push_back(DAG.getNode(Op.getOpcode(), EltVT,
694 &Operands[0], Operands.size()));
697 return DAG.getNode(ISD::BUILD_VECTOR, VT, &Scalars[0], Scalars.size());
700 /// GetFPLibCall - Return the right libcall for the given floating point type.
701 static RTLIB::Libcall GetFPLibCall(MVT VT,
702 RTLIB::Libcall Call_F32,
703 RTLIB::Libcall Call_F64,
704 RTLIB::Libcall Call_F80,
705 RTLIB::Libcall Call_PPCF128) {
707 VT == MVT::f32 ? Call_F32 :
708 VT == MVT::f64 ? Call_F64 :
709 VT == MVT::f80 ? Call_F80 :
710 VT == MVT::ppcf128 ? Call_PPCF128 :
711 RTLIB::UNKNOWN_LIBCALL;
714 /// PerformInsertVectorEltInMemory - Some target cannot handle a variable
715 /// insertion index for the INSERT_VECTOR_ELT instruction. In this case, it
716 /// is necessary to spill the vector being inserted into to memory, perform
717 /// the insert there, and then read the result back.
718 SDValue SelectionDAGLegalize::
719 PerformInsertVectorEltInMemory(SDValue Vec, SDValue Val, SDValue Idx) {
724 // If the target doesn't support this, we have to spill the input vector
725 // to a temporary stack slot, update the element, then reload it. This is
726 // badness. We could also load the value into a vector register (either
727 // with a "move to register" or "extload into register" instruction, then
728 // permute it into place, if the idx is a constant and if the idx is
729 // supported by the target.
730 MVT VT = Tmp1.getValueType();
731 MVT EltVT = VT.getVectorElementType();
732 MVT IdxVT = Tmp3.getValueType();
733 MVT PtrVT = TLI.getPointerTy();
734 SDValue StackPtr = DAG.CreateStackTemporary(VT);
736 int SPFI = cast<FrameIndexSDNode>(StackPtr.getNode())->getIndex();
739 SDValue Ch = DAG.getStore(DAG.getEntryNode(), Tmp1, StackPtr,
740 PseudoSourceValue::getFixedStack(SPFI), 0);
742 // Truncate or zero extend offset to target pointer type.
743 unsigned CastOpc = IdxVT.bitsGT(PtrVT) ? ISD::TRUNCATE : ISD::ZERO_EXTEND;
744 Tmp3 = DAG.getNode(CastOpc, PtrVT, Tmp3);
745 // Add the offset to the index.
746 unsigned EltSize = EltVT.getSizeInBits()/8;
747 Tmp3 = DAG.getNode(ISD::MUL, IdxVT, Tmp3,DAG.getConstant(EltSize, IdxVT));
748 SDValue StackPtr2 = DAG.getNode(ISD::ADD, IdxVT, Tmp3, StackPtr);
749 // Store the scalar value.
750 Ch = DAG.getTruncStore(Ch, Tmp2, StackPtr2,
751 PseudoSourceValue::getFixedStack(SPFI), 0, EltVT);
752 // Load the updated vector.
753 return DAG.getLoad(VT, Ch, StackPtr,
754 PseudoSourceValue::getFixedStack(SPFI), 0);
757 /// LegalizeOp - We know that the specified value has a legal type, and
758 /// that its operands are legal. Now ensure that the operation itself
759 /// is legal, recursively ensuring that the operands' operations remain
761 SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
762 if (Op.getOpcode() == ISD::TargetConstant) // Allow illegal target nodes.
765 assert(isTypeLegal(Op.getValueType()) &&
766 "Caller should expand or promote operands that are not legal!");
767 SDNode *Node = Op.getNode();
769 // If this operation defines any values that cannot be represented in a
770 // register on this target, make sure to expand or promote them.
771 if (Node->getNumValues() > 1) {
772 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
773 if (getTypeAction(Node->getValueType(i)) != Legal) {
774 HandleOp(Op.getValue(i));
775 assert(LegalizedNodes.count(Op) &&
776 "Handling didn't add legal operands!");
777 return LegalizedNodes[Op];
781 // Note that LegalizeOp may be reentered even from single-use nodes, which
782 // means that we always must cache transformed nodes.
783 DenseMap<SDValue, SDValue>::iterator I = LegalizedNodes.find(Op);
784 if (I != LegalizedNodes.end()) return I->second;
786 SDValue Tmp1, Tmp2, Tmp3, Tmp4;
788 bool isCustom = false;
790 switch (Node->getOpcode()) {
791 case ISD::FrameIndex:
792 case ISD::EntryToken:
794 case ISD::BasicBlock:
795 case ISD::TargetFrameIndex:
796 case ISD::TargetJumpTable:
797 case ISD::TargetConstant:
798 case ISD::TargetConstantFP:
799 case ISD::TargetConstantPool:
800 case ISD::TargetGlobalAddress:
801 case ISD::TargetGlobalTLSAddress:
802 case ISD::TargetExternalSymbol:
805 case ISD::MEMOPERAND:
808 // Primitives must all be legal.
809 assert(TLI.isOperationLegal(Node->getOpcode(), Node->getValueType(0)) &&
810 "This must be legal!");
813 if (Node->getOpcode() >= ISD::BUILTIN_OP_END) {
814 // If this is a target node, legalize it by legalizing the operands then
815 // passing it through.
816 SmallVector<SDValue, 8> Ops;
817 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
818 Ops.push_back(LegalizeOp(Node->getOperand(i)));
820 Result = DAG.UpdateNodeOperands(Result.getValue(0), &Ops[0], Ops.size());
822 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
823 AddLegalizedOperand(Op.getValue(i), Result.getValue(i));
824 return Result.getValue(Op.getResNo());
826 // Otherwise this is an unhandled builtin node. splat.
828 cerr << "NODE: "; Node->dump(&DAG); cerr << "\n";
830 assert(0 && "Do not know how to legalize this operator!");
832 case ISD::GLOBAL_OFFSET_TABLE:
833 case ISD::GlobalAddress:
834 case ISD::GlobalTLSAddress:
835 case ISD::ExternalSymbol:
836 case ISD::ConstantPool:
837 case ISD::JumpTable: // Nothing to do.
838 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
839 default: assert(0 && "This action is not supported yet!");
840 case TargetLowering::Custom:
841 Tmp1 = TLI.LowerOperation(Op, DAG);
842 if (Tmp1.getNode()) Result = Tmp1;
843 // FALLTHROUGH if the target doesn't want to lower this op after all.
844 case TargetLowering::Legal:
849 case ISD::RETURNADDR:
850 // The only option for these nodes is to custom lower them. If the target
851 // does not custom lower them, then return zero.
852 Tmp1 = TLI.LowerOperation(Op, DAG);
856 Result = DAG.getConstant(0, TLI.getPointerTy());
858 case ISD::FRAME_TO_ARGS_OFFSET: {
859 MVT VT = Node->getValueType(0);
860 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
861 default: assert(0 && "This action is not supported yet!");
862 case TargetLowering::Custom:
863 Result = TLI.LowerOperation(Op, DAG);
864 if (Result.getNode()) break;
866 case TargetLowering::Legal:
867 Result = DAG.getConstant(0, VT);
872 case ISD::EXCEPTIONADDR: {
873 Tmp1 = LegalizeOp(Node->getOperand(0));
874 MVT VT = Node->getValueType(0);
875 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
876 default: assert(0 && "This action is not supported yet!");
877 case TargetLowering::Expand: {
878 unsigned Reg = TLI.getExceptionAddressRegister();
879 Result = DAG.getCopyFromReg(Tmp1, Reg, VT);
882 case TargetLowering::Custom:
883 Result = TLI.LowerOperation(Op, DAG);
884 if (Result.getNode()) break;
886 case TargetLowering::Legal: {
887 SDValue Ops[] = { DAG.getConstant(0, VT), Tmp1 };
888 Result = DAG.getMergeValues(Ops, 2);
893 if (Result.getNode()->getNumValues() == 1) break;
895 assert(Result.getNode()->getNumValues() == 2 &&
896 "Cannot return more than two values!");
898 // Since we produced two values, make sure to remember that we
899 // legalized both of them.
900 Tmp1 = LegalizeOp(Result);
901 Tmp2 = LegalizeOp(Result.getValue(1));
902 AddLegalizedOperand(Op.getValue(0), Tmp1);
903 AddLegalizedOperand(Op.getValue(1), Tmp2);
904 return Op.getResNo() ? Tmp2 : Tmp1;
905 case ISD::EHSELECTION: {
906 Tmp1 = LegalizeOp(Node->getOperand(0));
907 Tmp2 = LegalizeOp(Node->getOperand(1));
908 MVT VT = Node->getValueType(0);
909 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
910 default: assert(0 && "This action is not supported yet!");
911 case TargetLowering::Expand: {
912 unsigned Reg = TLI.getExceptionSelectorRegister();
913 Result = DAG.getCopyFromReg(Tmp2, Reg, VT);
916 case TargetLowering::Custom:
917 Result = TLI.LowerOperation(Op, DAG);
918 if (Result.getNode()) break;
920 case TargetLowering::Legal: {
921 SDValue Ops[] = { DAG.getConstant(0, VT), Tmp2 };
922 Result = DAG.getMergeValues(Ops, 2);
927 if (Result.getNode()->getNumValues() == 1) break;
929 assert(Result.getNode()->getNumValues() == 2 &&
930 "Cannot return more than two values!");
932 // Since we produced two values, make sure to remember that we
933 // legalized both of them.
934 Tmp1 = LegalizeOp(Result);
935 Tmp2 = LegalizeOp(Result.getValue(1));
936 AddLegalizedOperand(Op.getValue(0), Tmp1);
937 AddLegalizedOperand(Op.getValue(1), Tmp2);
938 return Op.getResNo() ? Tmp2 : Tmp1;
939 case ISD::EH_RETURN: {
940 MVT VT = Node->getValueType(0);
941 // The only "good" option for this node is to custom lower it.
942 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
943 default: assert(0 && "This action is not supported at all!");
944 case TargetLowering::Custom:
945 Result = TLI.LowerOperation(Op, DAG);
946 if (Result.getNode()) break;
948 case TargetLowering::Legal:
949 // Target does not know, how to lower this, lower to noop
950 Result = LegalizeOp(Node->getOperand(0));
955 case ISD::AssertSext:
956 case ISD::AssertZext:
957 Tmp1 = LegalizeOp(Node->getOperand(0));
958 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
960 case ISD::MERGE_VALUES:
961 // Legalize eliminates MERGE_VALUES nodes.
962 Result = Node->getOperand(Op.getResNo());
964 case ISD::CopyFromReg:
965 Tmp1 = LegalizeOp(Node->getOperand(0));
966 Result = Op.getValue(0);
967 if (Node->getNumValues() == 2) {
968 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
970 assert(Node->getNumValues() == 3 && "Invalid copyfromreg!");
971 if (Node->getNumOperands() == 3) {
972 Tmp2 = LegalizeOp(Node->getOperand(2));
973 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1),Tmp2);
975 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
977 AddLegalizedOperand(Op.getValue(2), Result.getValue(2));
979 // Since CopyFromReg produces two values, make sure to remember that we
980 // legalized both of them.
981 AddLegalizedOperand(Op.getValue(0), Result);
982 AddLegalizedOperand(Op.getValue(1), Result.getValue(1));
983 return Result.getValue(Op.getResNo());
985 MVT VT = Op.getValueType();
986 switch (TLI.getOperationAction(ISD::UNDEF, VT)) {
987 default: assert(0 && "This action is not supported yet!");
988 case TargetLowering::Expand:
990 Result = DAG.getConstant(0, VT);
991 else if (VT.isFloatingPoint())
992 Result = DAG.getConstantFP(APFloat(APInt(VT.getSizeInBits(), 0)),
995 assert(0 && "Unknown value type!");
997 case TargetLowering::Legal:
1003 case ISD::INTRINSIC_W_CHAIN:
1004 case ISD::INTRINSIC_WO_CHAIN:
1005 case ISD::INTRINSIC_VOID: {
1006 SmallVector<SDValue, 8> Ops;
1007 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
1008 Ops.push_back(LegalizeOp(Node->getOperand(i)));
1009 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1011 // Allow the target to custom lower its intrinsics if it wants to.
1012 if (TLI.getOperationAction(Node->getOpcode(), MVT::Other) ==
1013 TargetLowering::Custom) {
1014 Tmp3 = TLI.LowerOperation(Result, DAG);
1015 if (Tmp3.getNode()) Result = Tmp3;
1018 if (Result.getNode()->getNumValues() == 1) break;
1020 // Must have return value and chain result.
1021 assert(Result.getNode()->getNumValues() == 2 &&
1022 "Cannot return more than two values!");
1024 // Since loads produce two values, make sure to remember that we
1025 // legalized both of them.
1026 AddLegalizedOperand(SDValue(Node, 0), Result.getValue(0));
1027 AddLegalizedOperand(SDValue(Node, 1), Result.getValue(1));
1028 return Result.getValue(Op.getResNo());
1031 case ISD::DBG_STOPPOINT:
1032 assert(Node->getNumOperands() == 1 && "Invalid DBG_STOPPOINT node!");
1033 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the input chain.
1035 switch (TLI.getOperationAction(ISD::DBG_STOPPOINT, MVT::Other)) {
1036 case TargetLowering::Promote:
1037 default: assert(0 && "This action is not supported yet!");
1038 case TargetLowering::Expand: {
1039 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
1040 bool useDEBUG_LOC = TLI.isOperationLegal(ISD::DEBUG_LOC, MVT::Other);
1041 bool useLABEL = TLI.isOperationLegal(ISD::DBG_LABEL, MVT::Other);
1043 const DbgStopPointSDNode *DSP = cast<DbgStopPointSDNode>(Node);
1044 if (MMI && (useDEBUG_LOC || useLABEL)) {
1045 const CompileUnitDesc *CompileUnit = DSP->getCompileUnit();
1046 unsigned SrcFile = MMI->RecordSource(CompileUnit);
1048 unsigned Line = DSP->getLine();
1049 unsigned Col = DSP->getColumn();
1052 SDValue Ops[] = { Tmp1, DAG.getConstant(Line, MVT::i32),
1053 DAG.getConstant(Col, MVT::i32),
1054 DAG.getConstant(SrcFile, MVT::i32) };
1055 Result = DAG.getNode(ISD::DEBUG_LOC, MVT::Other, Ops, 4);
1057 unsigned ID = MMI->RecordSourceLine(Line, Col, SrcFile);
1058 Result = DAG.getLabel(ISD::DBG_LABEL, Tmp1, ID);
1061 Result = Tmp1; // chain
1065 case TargetLowering::Legal: {
1066 LegalizeAction Action = getTypeAction(Node->getOperand(1).getValueType());
1067 if (Action == Legal && Tmp1 == Node->getOperand(0))
1070 SmallVector<SDValue, 8> Ops;
1071 Ops.push_back(Tmp1);
1072 if (Action == Legal) {
1073 Ops.push_back(Node->getOperand(1)); // line # must be legal.
1074 Ops.push_back(Node->getOperand(2)); // col # must be legal.
1076 // Otherwise promote them.
1077 Ops.push_back(PromoteOp(Node->getOperand(1)));
1078 Ops.push_back(PromoteOp(Node->getOperand(2)));
1080 Ops.push_back(Node->getOperand(3)); // filename must be legal.
1081 Ops.push_back(Node->getOperand(4)); // working dir # must be legal.
1082 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1089 assert(Node->getNumOperands() == 3 && "Invalid DECLARE node!");
1090 switch (TLI.getOperationAction(ISD::DECLARE, MVT::Other)) {
1091 default: assert(0 && "This action is not supported yet!");
1092 case TargetLowering::Legal:
1093 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1094 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the address.
1095 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the variable.
1096 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1098 case TargetLowering::Expand:
1099 Result = LegalizeOp(Node->getOperand(0));
1104 case ISD::DEBUG_LOC:
1105 assert(Node->getNumOperands() == 4 && "Invalid DEBUG_LOC node!");
1106 switch (TLI.getOperationAction(ISD::DEBUG_LOC, MVT::Other)) {
1107 default: assert(0 && "This action is not supported yet!");
1108 case TargetLowering::Legal: {
1109 LegalizeAction Action = getTypeAction(Node->getOperand(1).getValueType());
1110 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1111 if (Action == Legal && Tmp1 == Node->getOperand(0))
1113 if (Action == Legal) {
1114 Tmp2 = Node->getOperand(1);
1115 Tmp3 = Node->getOperand(2);
1116 Tmp4 = Node->getOperand(3);
1118 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the line #.
1119 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the col #.
1120 Tmp4 = LegalizeOp(Node->getOperand(3)); // Legalize the source file id.
1122 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4);
1128 case ISD::DBG_LABEL:
1130 assert(Node->getNumOperands() == 1 && "Invalid LABEL node!");
1131 switch (TLI.getOperationAction(Node->getOpcode(), MVT::Other)) {
1132 default: assert(0 && "This action is not supported yet!");
1133 case TargetLowering::Legal:
1134 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1135 Result = DAG.UpdateNodeOperands(Result, Tmp1);
1137 case TargetLowering::Expand:
1138 Result = LegalizeOp(Node->getOperand(0));
1144 assert(Node->getNumOperands() == 4 && "Invalid Prefetch node!");
1145 switch (TLI.getOperationAction(ISD::PREFETCH, MVT::Other)) {
1146 default: assert(0 && "This action is not supported yet!");
1147 case TargetLowering::Legal:
1148 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1149 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the address.
1150 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the rw specifier.
1151 Tmp4 = LegalizeOp(Node->getOperand(3)); // Legalize locality specifier.
1152 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4);
1154 case TargetLowering::Expand:
1156 Result = LegalizeOp(Node->getOperand(0));
1161 case ISD::MEMBARRIER: {
1162 assert(Node->getNumOperands() == 6 && "Invalid MemBarrier node!");
1163 switch (TLI.getOperationAction(ISD::MEMBARRIER, MVT::Other)) {
1164 default: assert(0 && "This action is not supported yet!");
1165 case TargetLowering::Legal: {
1167 Ops[0] = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1168 for (int x = 1; x < 6; ++x) {
1169 Ops[x] = Node->getOperand(x);
1170 if (!isTypeLegal(Ops[x].getValueType()))
1171 Ops[x] = PromoteOp(Ops[x]);
1173 Result = DAG.UpdateNodeOperands(Result, &Ops[0], 6);
1176 case TargetLowering::Expand:
1177 //There is no libgcc call for this op
1178 Result = Node->getOperand(0); // Noop
1184 case ISD::ATOMIC_CMP_SWAP_8:
1185 case ISD::ATOMIC_CMP_SWAP_16:
1186 case ISD::ATOMIC_CMP_SWAP_32:
1187 case ISD::ATOMIC_CMP_SWAP_64: {
1188 unsigned int num_operands = 4;
1189 assert(Node->getNumOperands() == num_operands && "Invalid Atomic node!");
1191 for (unsigned int x = 0; x < num_operands; ++x)
1192 Ops[x] = LegalizeOp(Node->getOperand(x));
1193 Result = DAG.UpdateNodeOperands(Result, &Ops[0], num_operands);
1195 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
1196 default: assert(0 && "This action is not supported yet!");
1197 case TargetLowering::Custom:
1198 Result = TLI.LowerOperation(Result, DAG);
1200 case TargetLowering::Legal:
1203 AddLegalizedOperand(SDValue(Node, 0), Result.getValue(0));
1204 AddLegalizedOperand(SDValue(Node, 1), Result.getValue(1));
1205 return Result.getValue(Op.getResNo());
1207 case ISD::ATOMIC_LOAD_ADD_8:
1208 case ISD::ATOMIC_LOAD_SUB_8:
1209 case ISD::ATOMIC_LOAD_AND_8:
1210 case ISD::ATOMIC_LOAD_OR_8:
1211 case ISD::ATOMIC_LOAD_XOR_8:
1212 case ISD::ATOMIC_LOAD_NAND_8:
1213 case ISD::ATOMIC_LOAD_MIN_8:
1214 case ISD::ATOMIC_LOAD_MAX_8:
1215 case ISD::ATOMIC_LOAD_UMIN_8:
1216 case ISD::ATOMIC_LOAD_UMAX_8:
1217 case ISD::ATOMIC_SWAP_8:
1218 case ISD::ATOMIC_LOAD_ADD_16:
1219 case ISD::ATOMIC_LOAD_SUB_16:
1220 case ISD::ATOMIC_LOAD_AND_16:
1221 case ISD::ATOMIC_LOAD_OR_16:
1222 case ISD::ATOMIC_LOAD_XOR_16:
1223 case ISD::ATOMIC_LOAD_NAND_16:
1224 case ISD::ATOMIC_LOAD_MIN_16:
1225 case ISD::ATOMIC_LOAD_MAX_16:
1226 case ISD::ATOMIC_LOAD_UMIN_16:
1227 case ISD::ATOMIC_LOAD_UMAX_16:
1228 case ISD::ATOMIC_SWAP_16:
1229 case ISD::ATOMIC_LOAD_ADD_32:
1230 case ISD::ATOMIC_LOAD_SUB_32:
1231 case ISD::ATOMIC_LOAD_AND_32:
1232 case ISD::ATOMIC_LOAD_OR_32:
1233 case ISD::ATOMIC_LOAD_XOR_32:
1234 case ISD::ATOMIC_LOAD_NAND_32:
1235 case ISD::ATOMIC_LOAD_MIN_32:
1236 case ISD::ATOMIC_LOAD_MAX_32:
1237 case ISD::ATOMIC_LOAD_UMIN_32:
1238 case ISD::ATOMIC_LOAD_UMAX_32:
1239 case ISD::ATOMIC_SWAP_32:
1240 case ISD::ATOMIC_LOAD_ADD_64:
1241 case ISD::ATOMIC_LOAD_SUB_64:
1242 case ISD::ATOMIC_LOAD_AND_64:
1243 case ISD::ATOMIC_LOAD_OR_64:
1244 case ISD::ATOMIC_LOAD_XOR_64:
1245 case ISD::ATOMIC_LOAD_NAND_64:
1246 case ISD::ATOMIC_LOAD_MIN_64:
1247 case ISD::ATOMIC_LOAD_MAX_64:
1248 case ISD::ATOMIC_LOAD_UMIN_64:
1249 case ISD::ATOMIC_LOAD_UMAX_64:
1250 case ISD::ATOMIC_SWAP_64: {
1251 unsigned int num_operands = 3;
1252 assert(Node->getNumOperands() == num_operands && "Invalid Atomic node!");
1254 for (unsigned int x = 0; x < num_operands; ++x)
1255 Ops[x] = LegalizeOp(Node->getOperand(x));
1256 Result = DAG.UpdateNodeOperands(Result, &Ops[0], num_operands);
1258 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
1259 default: assert(0 && "This action is not supported yet!");
1260 case TargetLowering::Custom:
1261 Result = TLI.LowerOperation(Result, DAG);
1263 case TargetLowering::Legal:
1266 AddLegalizedOperand(SDValue(Node, 0), Result.getValue(0));
1267 AddLegalizedOperand(SDValue(Node, 1), Result.getValue(1));
1268 return Result.getValue(Op.getResNo());
1270 case ISD::Constant: {
1271 ConstantSDNode *CN = cast<ConstantSDNode>(Node);
1273 TLI.getOperationAction(ISD::Constant, CN->getValueType(0));
1275 // We know we don't need to expand constants here, constants only have one
1276 // value and we check that it is fine above.
1278 if (opAction == TargetLowering::Custom) {
1279 Tmp1 = TLI.LowerOperation(Result, DAG);
1285 case ISD::ConstantFP: {
1286 // Spill FP immediates to the constant pool if the target cannot directly
1287 // codegen them. Targets often have some immediate values that can be
1288 // efficiently generated into an FP register without a load. We explicitly
1289 // leave these constants as ConstantFP nodes for the target to deal with.
1290 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node);
1292 switch (TLI.getOperationAction(ISD::ConstantFP, CFP->getValueType(0))) {
1293 default: assert(0 && "This action is not supported yet!");
1294 case TargetLowering::Legal:
1296 case TargetLowering::Custom:
1297 Tmp3 = TLI.LowerOperation(Result, DAG);
1298 if (Tmp3.getNode()) {
1303 case TargetLowering::Expand: {
1304 // Check to see if this FP immediate is already legal.
1305 bool isLegal = false;
1306 for (TargetLowering::legal_fpimm_iterator I = TLI.legal_fpimm_begin(),
1307 E = TLI.legal_fpimm_end(); I != E; ++I) {
1308 if (CFP->isExactlyValue(*I)) {
1313 // If this is a legal constant, turn it into a TargetConstantFP node.
1316 Result = ExpandConstantFP(CFP, true, DAG, TLI);
1321 case ISD::TokenFactor:
1322 if (Node->getNumOperands() == 2) {
1323 Tmp1 = LegalizeOp(Node->getOperand(0));
1324 Tmp2 = LegalizeOp(Node->getOperand(1));
1325 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1326 } else if (Node->getNumOperands() == 3) {
1327 Tmp1 = LegalizeOp(Node->getOperand(0));
1328 Tmp2 = LegalizeOp(Node->getOperand(1));
1329 Tmp3 = LegalizeOp(Node->getOperand(2));
1330 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1332 SmallVector<SDValue, 8> Ops;
1333 // Legalize the operands.
1334 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
1335 Ops.push_back(LegalizeOp(Node->getOperand(i)));
1336 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1340 case ISD::FORMAL_ARGUMENTS:
1342 // The only option for this is to custom lower it.
1343 Tmp3 = TLI.LowerOperation(Result.getValue(0), DAG);
1344 assert(Tmp3.getNode() && "Target didn't custom lower this node!");
1345 // A call within a calling sequence must be legalized to something
1346 // other than the normal CALLSEQ_END. Violating this gets Legalize
1347 // into an infinite loop.
1348 assert ((!IsLegalizingCall ||
1349 Node->getOpcode() != ISD::CALL ||
1350 Tmp3.getNode()->getOpcode() != ISD::CALLSEQ_END) &&
1351 "Nested CALLSEQ_START..CALLSEQ_END not supported.");
1353 // The number of incoming and outgoing values should match; unless the final
1354 // outgoing value is a flag.
1355 assert((Tmp3.getNode()->getNumValues() == Result.getNode()->getNumValues() ||
1356 (Tmp3.getNode()->getNumValues() == Result.getNode()->getNumValues() + 1 &&
1357 Tmp3.getNode()->getValueType(Tmp3.getNode()->getNumValues() - 1) ==
1359 "Lowering call/formal_arguments produced unexpected # results!");
1361 // Since CALL/FORMAL_ARGUMENTS nodes produce multiple values, make sure to
1362 // remember that we legalized all of them, so it doesn't get relegalized.
1363 for (unsigned i = 0, e = Tmp3.getNode()->getNumValues(); i != e; ++i) {
1364 if (Tmp3.getNode()->getValueType(i) == MVT::Flag)
1366 Tmp1 = LegalizeOp(Tmp3.getValue(i));
1367 if (Op.getResNo() == i)
1369 AddLegalizedOperand(SDValue(Node, i), Tmp1);
1372 case ISD::EXTRACT_SUBREG: {
1373 Tmp1 = LegalizeOp(Node->getOperand(0));
1374 ConstantSDNode *idx = dyn_cast<ConstantSDNode>(Node->getOperand(1));
1375 assert(idx && "Operand must be a constant");
1376 Tmp2 = DAG.getTargetConstant(idx->getAPIntValue(), idx->getValueType(0));
1377 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1380 case ISD::INSERT_SUBREG: {
1381 Tmp1 = LegalizeOp(Node->getOperand(0));
1382 Tmp2 = LegalizeOp(Node->getOperand(1));
1383 ConstantSDNode *idx = dyn_cast<ConstantSDNode>(Node->getOperand(2));
1384 assert(idx && "Operand must be a constant");
1385 Tmp3 = DAG.getTargetConstant(idx->getAPIntValue(), idx->getValueType(0));
1386 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1389 case ISD::BUILD_VECTOR:
1390 switch (TLI.getOperationAction(ISD::BUILD_VECTOR, Node->getValueType(0))) {
1391 default: assert(0 && "This action is not supported yet!");
1392 case TargetLowering::Custom:
1393 Tmp3 = TLI.LowerOperation(Result, DAG);
1394 if (Tmp3.getNode()) {
1399 case TargetLowering::Expand:
1400 Result = ExpandBUILD_VECTOR(Result.getNode());
1404 case ISD::INSERT_VECTOR_ELT:
1405 Tmp1 = LegalizeOp(Node->getOperand(0)); // InVec
1406 Tmp3 = LegalizeOp(Node->getOperand(2)); // InEltNo
1408 // The type of the value to insert may not be legal, even though the vector
1409 // type is legal. Legalize/Promote accordingly. We do not handle Expand
1411 switch (getTypeAction(Node->getOperand(1).getValueType())) {
1412 default: assert(0 && "Cannot expand insert element operand");
1413 case Legal: Tmp2 = LegalizeOp(Node->getOperand(1)); break;
1414 case Promote: Tmp2 = PromoteOp(Node->getOperand(1)); break;
1416 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1418 switch (TLI.getOperationAction(ISD::INSERT_VECTOR_ELT,
1419 Node->getValueType(0))) {
1420 default: assert(0 && "This action is not supported yet!");
1421 case TargetLowering::Legal:
1423 case TargetLowering::Custom:
1424 Tmp4 = TLI.LowerOperation(Result, DAG);
1425 if (Tmp4.getNode()) {
1430 case TargetLowering::Expand: {
1431 // If the insert index is a constant, codegen this as a scalar_to_vector,
1432 // then a shuffle that inserts it into the right position in the vector.
1433 if (ConstantSDNode *InsertPos = dyn_cast<ConstantSDNode>(Tmp3)) {
1434 // SCALAR_TO_VECTOR requires that the type of the value being inserted
1435 // match the element type of the vector being created.
1436 if (Tmp2.getValueType() ==
1437 Op.getValueType().getVectorElementType()) {
1438 SDValue ScVec = DAG.getNode(ISD::SCALAR_TO_VECTOR,
1439 Tmp1.getValueType(), Tmp2);
1441 unsigned NumElts = Tmp1.getValueType().getVectorNumElements();
1443 MVT::getIntVectorWithNumElements(NumElts);
1444 MVT ShufMaskEltVT = ShufMaskVT.getVectorElementType();
1446 // We generate a shuffle of InVec and ScVec, so the shuffle mask
1447 // should be 0,1,2,3,4,5... with the appropriate element replaced with
1448 // elt 0 of the RHS.
1449 SmallVector<SDValue, 8> ShufOps;
1450 for (unsigned i = 0; i != NumElts; ++i) {
1451 if (i != InsertPos->getZExtValue())
1452 ShufOps.push_back(DAG.getConstant(i, ShufMaskEltVT));
1454 ShufOps.push_back(DAG.getConstant(NumElts, ShufMaskEltVT));
1456 SDValue ShufMask = DAG.getNode(ISD::BUILD_VECTOR, ShufMaskVT,
1457 &ShufOps[0], ShufOps.size());
1459 Result = DAG.getNode(ISD::VECTOR_SHUFFLE, Tmp1.getValueType(),
1460 Tmp1, ScVec, ShufMask);
1461 Result = LegalizeOp(Result);
1465 Result = PerformInsertVectorEltInMemory(Tmp1, Tmp2, Tmp3);
1470 case ISD::SCALAR_TO_VECTOR:
1471 if (!TLI.isTypeLegal(Node->getOperand(0).getValueType())) {
1472 Result = LegalizeOp(ExpandSCALAR_TO_VECTOR(Node));
1476 Tmp1 = LegalizeOp(Node->getOperand(0)); // InVal
1477 Result = DAG.UpdateNodeOperands(Result, Tmp1);
1478 switch (TLI.getOperationAction(ISD::SCALAR_TO_VECTOR,
1479 Node->getValueType(0))) {
1480 default: assert(0 && "This action is not supported yet!");
1481 case TargetLowering::Legal:
1483 case TargetLowering::Custom:
1484 Tmp3 = TLI.LowerOperation(Result, DAG);
1485 if (Tmp3.getNode()) {
1490 case TargetLowering::Expand:
1491 Result = LegalizeOp(ExpandSCALAR_TO_VECTOR(Node));
1495 case ISD::VECTOR_SHUFFLE:
1496 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the input vectors,
1497 Tmp2 = LegalizeOp(Node->getOperand(1)); // but not the shuffle mask.
1498 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
1500 // Allow targets to custom lower the SHUFFLEs they support.
1501 switch (TLI.getOperationAction(ISD::VECTOR_SHUFFLE,Result.getValueType())) {
1502 default: assert(0 && "Unknown operation action!");
1503 case TargetLowering::Legal:
1504 assert(isShuffleLegal(Result.getValueType(), Node->getOperand(2)) &&
1505 "vector shuffle should not be created if not legal!");
1507 case TargetLowering::Custom:
1508 Tmp3 = TLI.LowerOperation(Result, DAG);
1509 if (Tmp3.getNode()) {
1514 case TargetLowering::Expand: {
1515 MVT VT = Node->getValueType(0);
1516 MVT EltVT = VT.getVectorElementType();
1517 MVT PtrVT = TLI.getPointerTy();
1518 SDValue Mask = Node->getOperand(2);
1519 unsigned NumElems = Mask.getNumOperands();
1520 SmallVector<SDValue,8> Ops;
1521 for (unsigned i = 0; i != NumElems; ++i) {
1522 SDValue Arg = Mask.getOperand(i);
1523 if (Arg.getOpcode() == ISD::UNDEF) {
1524 Ops.push_back(DAG.getNode(ISD::UNDEF, EltVT));
1526 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
1527 unsigned Idx = cast<ConstantSDNode>(Arg)->getZExtValue();
1529 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, Tmp1,
1530 DAG.getConstant(Idx, PtrVT)));
1532 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, Tmp2,
1533 DAG.getConstant(Idx - NumElems, PtrVT)));
1536 Result = DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size());
1539 case TargetLowering::Promote: {
1540 // Change base type to a different vector type.
1541 MVT OVT = Node->getValueType(0);
1542 MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
1544 // Cast the two input vectors.
1545 Tmp1 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp1);
1546 Tmp2 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp2);
1548 // Convert the shuffle mask to the right # elements.
1549 Tmp3 = SDValue(isShuffleLegal(OVT, Node->getOperand(2)), 0);
1550 assert(Tmp3.getNode() && "Shuffle not legal?");
1551 Result = DAG.getNode(ISD::VECTOR_SHUFFLE, NVT, Tmp1, Tmp2, Tmp3);
1552 Result = DAG.getNode(ISD::BIT_CONVERT, OVT, Result);
1558 case ISD::EXTRACT_VECTOR_ELT:
1559 Tmp1 = Node->getOperand(0);
1560 Tmp2 = LegalizeOp(Node->getOperand(1));
1561 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1562 Result = ExpandEXTRACT_VECTOR_ELT(Result);
1565 case ISD::EXTRACT_SUBVECTOR:
1566 Tmp1 = Node->getOperand(0);
1567 Tmp2 = LegalizeOp(Node->getOperand(1));
1568 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1569 Result = ExpandEXTRACT_SUBVECTOR(Result);
1572 case ISD::CALLSEQ_START: {
1573 SDNode *CallEnd = FindCallEndFromCallStart(Node);
1575 // Recursively Legalize all of the inputs of the call end that do not lead
1576 // to this call start. This ensures that any libcalls that need be inserted
1577 // are inserted *before* the CALLSEQ_START.
1578 {SmallPtrSet<SDNode*, 32> NodesLeadingTo;
1579 for (unsigned i = 0, e = CallEnd->getNumOperands(); i != e; ++i)
1580 LegalizeAllNodesNotLeadingTo(CallEnd->getOperand(i).getNode(), Node,
1584 // Now that we legalized all of the inputs (which may have inserted
1585 // libcalls) create the new CALLSEQ_START node.
1586 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1588 // Merge in the last call, to ensure that this call start after the last
1590 if (LastCALLSEQ_END.getOpcode() != ISD::EntryToken) {
1591 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1592 Tmp1 = LegalizeOp(Tmp1);
1595 // Do not try to legalize the target-specific arguments (#1+).
1596 if (Tmp1 != Node->getOperand(0)) {
1597 SmallVector<SDValue, 8> Ops(Node->op_begin(), Node->op_end());
1599 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1602 // Remember that the CALLSEQ_START is legalized.
1603 AddLegalizedOperand(Op.getValue(0), Result);
1604 if (Node->getNumValues() == 2) // If this has a flag result, remember it.
1605 AddLegalizedOperand(Op.getValue(1), Result.getValue(1));
1607 // Now that the callseq_start and all of the non-call nodes above this call
1608 // sequence have been legalized, legalize the call itself. During this
1609 // process, no libcalls can/will be inserted, guaranteeing that no calls
1611 assert(!IsLegalizingCall && "Inconsistent sequentialization of calls!");
1612 // Note that we are selecting this call!
1613 LastCALLSEQ_END = SDValue(CallEnd, 0);
1614 IsLegalizingCall = true;
1616 // Legalize the call, starting from the CALLSEQ_END.
1617 LegalizeOp(LastCALLSEQ_END);
1618 assert(!IsLegalizingCall && "CALLSEQ_END should have cleared this!");
1621 case ISD::CALLSEQ_END:
1622 // If the CALLSEQ_START node hasn't been legalized first, legalize it. This
1623 // will cause this node to be legalized as well as handling libcalls right.
1624 if (LastCALLSEQ_END.getNode() != Node) {
1625 LegalizeOp(SDValue(FindCallStartFromCallEnd(Node), 0));
1626 DenseMap<SDValue, SDValue>::iterator I = LegalizedNodes.find(Op);
1627 assert(I != LegalizedNodes.end() &&
1628 "Legalizing the call start should have legalized this node!");
1632 // Otherwise, the call start has been legalized and everything is going
1633 // according to plan. Just legalize ourselves normally here.
1634 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1635 // Do not try to legalize the target-specific arguments (#1+), except for
1636 // an optional flag input.
1637 if (Node->getOperand(Node->getNumOperands()-1).getValueType() != MVT::Flag){
1638 if (Tmp1 != Node->getOperand(0)) {
1639 SmallVector<SDValue, 8> Ops(Node->op_begin(), Node->op_end());
1641 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1644 Tmp2 = LegalizeOp(Node->getOperand(Node->getNumOperands()-1));
1645 if (Tmp1 != Node->getOperand(0) ||
1646 Tmp2 != Node->getOperand(Node->getNumOperands()-1)) {
1647 SmallVector<SDValue, 8> Ops(Node->op_begin(), Node->op_end());
1650 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1653 assert(IsLegalizingCall && "Call sequence imbalance between start/end?");
1654 // This finishes up call legalization.
1655 IsLegalizingCall = false;
1657 // If the CALLSEQ_END node has a flag, remember that we legalized it.
1658 AddLegalizedOperand(SDValue(Node, 0), Result.getValue(0));
1659 if (Node->getNumValues() == 2)
1660 AddLegalizedOperand(SDValue(Node, 1), Result.getValue(1));
1661 return Result.getValue(Op.getResNo());
1662 case ISD::DYNAMIC_STACKALLOC: {
1663 MVT VT = Node->getValueType(0);
1664 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1665 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the size.
1666 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the alignment.
1667 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1669 Tmp1 = Result.getValue(0);
1670 Tmp2 = Result.getValue(1);
1671 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
1672 default: assert(0 && "This action is not supported yet!");
1673 case TargetLowering::Expand: {
1674 unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore();
1675 assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and"
1676 " not tell us which reg is the stack pointer!");
1677 SDValue Chain = Tmp1.getOperand(0);
1679 // Chain the dynamic stack allocation so that it doesn't modify the stack
1680 // pointer when other instructions are using the stack.
1681 Chain = DAG.getCALLSEQ_START(Chain,
1682 DAG.getConstant(0, TLI.getPointerTy()));
1684 SDValue Size = Tmp2.getOperand(1);
1685 SDValue SP = DAG.getCopyFromReg(Chain, SPReg, VT);
1686 Chain = SP.getValue(1);
1687 unsigned Align = cast<ConstantSDNode>(Tmp3)->getZExtValue();
1688 unsigned StackAlign =
1689 TLI.getTargetMachine().getFrameInfo()->getStackAlignment();
1690 if (Align > StackAlign)
1691 SP = DAG.getNode(ISD::AND, VT, SP,
1692 DAG.getConstant(-(uint64_t)Align, VT));
1693 Tmp1 = DAG.getNode(ISD::SUB, VT, SP, Size); // Value
1694 Chain = DAG.getCopyToReg(Chain, SPReg, Tmp1); // Output chain
1697 DAG.getCALLSEQ_END(Chain,
1698 DAG.getConstant(0, TLI.getPointerTy()),
1699 DAG.getConstant(0, TLI.getPointerTy()),
1702 Tmp1 = LegalizeOp(Tmp1);
1703 Tmp2 = LegalizeOp(Tmp2);
1706 case TargetLowering::Custom:
1707 Tmp3 = TLI.LowerOperation(Tmp1, DAG);
1708 if (Tmp3.getNode()) {
1709 Tmp1 = LegalizeOp(Tmp3);
1710 Tmp2 = LegalizeOp(Tmp3.getValue(1));
1713 case TargetLowering::Legal:
1716 // Since this op produce two values, make sure to remember that we
1717 // legalized both of them.
1718 AddLegalizedOperand(SDValue(Node, 0), Tmp1);
1719 AddLegalizedOperand(SDValue(Node, 1), Tmp2);
1720 return Op.getResNo() ? Tmp2 : Tmp1;
1722 case ISD::INLINEASM: {
1723 SmallVector<SDValue, 8> Ops(Node->op_begin(), Node->op_end());
1724 bool Changed = false;
1725 // Legalize all of the operands of the inline asm, in case they are nodes
1726 // that need to be expanded or something. Note we skip the asm string and
1727 // all of the TargetConstant flags.
1728 SDValue Op = LegalizeOp(Ops[0]);
1729 Changed = Op != Ops[0];
1732 bool HasInFlag = Ops.back().getValueType() == MVT::Flag;
1733 for (unsigned i = 2, e = Ops.size()-HasInFlag; i < e; ) {
1734 unsigned NumVals = cast<ConstantSDNode>(Ops[i])->getZExtValue() >> 3;
1735 for (++i; NumVals; ++i, --NumVals) {
1736 SDValue Op = LegalizeOp(Ops[i]);
1745 Op = LegalizeOp(Ops.back());
1746 Changed |= Op != Ops.back();
1751 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1753 // INLINE asm returns a chain and flag, make sure to add both to the map.
1754 AddLegalizedOperand(SDValue(Node, 0), Result.getValue(0));
1755 AddLegalizedOperand(SDValue(Node, 1), Result.getValue(1));
1756 return Result.getValue(Op.getResNo());
1759 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1760 // Ensure that libcalls are emitted before a branch.
1761 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1762 Tmp1 = LegalizeOp(Tmp1);
1763 LastCALLSEQ_END = DAG.getEntryNode();
1765 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
1768 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1769 // Ensure that libcalls are emitted before a branch.
1770 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1771 Tmp1 = LegalizeOp(Tmp1);
1772 LastCALLSEQ_END = DAG.getEntryNode();
1774 switch (getTypeAction(Node->getOperand(1).getValueType())) {
1775 default: assert(0 && "Indirect target must be legal type (pointer)!");
1777 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the condition.
1780 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1783 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1784 // Ensure that libcalls are emitted before a branch.
1785 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1786 Tmp1 = LegalizeOp(Tmp1);
1787 LastCALLSEQ_END = DAG.getEntryNode();
1789 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the jumptable node.
1790 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
1792 switch (TLI.getOperationAction(ISD::BR_JT, MVT::Other)) {
1793 default: assert(0 && "This action is not supported yet!");
1794 case TargetLowering::Legal: break;
1795 case TargetLowering::Custom:
1796 Tmp1 = TLI.LowerOperation(Result, DAG);
1797 if (Tmp1.getNode()) Result = Tmp1;
1799 case TargetLowering::Expand: {
1800 SDValue Chain = Result.getOperand(0);
1801 SDValue Table = Result.getOperand(1);
1802 SDValue Index = Result.getOperand(2);
1804 MVT PTy = TLI.getPointerTy();
1805 MachineFunction &MF = DAG.getMachineFunction();
1806 unsigned EntrySize = MF.getJumpTableInfo()->getEntrySize();
1807 Index= DAG.getNode(ISD::MUL, PTy, Index, DAG.getConstant(EntrySize, PTy));
1808 SDValue Addr = DAG.getNode(ISD::ADD, PTy, Index, Table);
1811 switch (EntrySize) {
1812 default: assert(0 && "Size of jump table not supported yet."); break;
1813 case 4: LD = DAG.getLoad(MVT::i32, Chain, Addr,
1814 PseudoSourceValue::getJumpTable(), 0); break;
1815 case 8: LD = DAG.getLoad(MVT::i64, Chain, Addr,
1816 PseudoSourceValue::getJumpTable(), 0); break;
1820 if (TLI.getTargetMachine().getRelocationModel() == Reloc::PIC_) {
1821 // For PIC, the sequence is:
1822 // BRIND(load(Jumptable + index) + RelocBase)
1823 // RelocBase can be JumpTable, GOT or some sort of global base.
1824 if (PTy != MVT::i32)
1825 Addr = DAG.getNode(ISD::SIGN_EXTEND, PTy, Addr);
1826 Addr = DAG.getNode(ISD::ADD, PTy, Addr,
1827 TLI.getPICJumpTableRelocBase(Table, DAG));
1829 Result = DAG.getNode(ISD::BRIND, MVT::Other, LD.getValue(1), Addr);
1834 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1835 // Ensure that libcalls are emitted before a return.
1836 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1837 Tmp1 = LegalizeOp(Tmp1);
1838 LastCALLSEQ_END = DAG.getEntryNode();
1840 switch (getTypeAction(Node->getOperand(1).getValueType())) {
1841 case Expand: assert(0 && "It's impossible to expand bools");
1843 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the condition.
1846 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the condition.
1848 // The top bits of the promoted condition are not necessarily zero, ensure
1849 // that the value is properly zero extended.
1850 unsigned BitWidth = Tmp2.getValueSizeInBits();
1851 if (!DAG.MaskedValueIsZero(Tmp2,
1852 APInt::getHighBitsSet(BitWidth, BitWidth-1)))
1853 Tmp2 = DAG.getZeroExtendInReg(Tmp2, MVT::i1);
1858 // Basic block destination (Op#2) is always legal.
1859 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
1861 switch (TLI.getOperationAction(ISD::BRCOND, MVT::Other)) {
1862 default: assert(0 && "This action is not supported yet!");
1863 case TargetLowering::Legal: break;
1864 case TargetLowering::Custom:
1865 Tmp1 = TLI.LowerOperation(Result, DAG);
1866 if (Tmp1.getNode()) Result = Tmp1;
1868 case TargetLowering::Expand:
1869 // Expand brcond's setcc into its constituent parts and create a BR_CC
1871 if (Tmp2.getOpcode() == ISD::SETCC) {
1872 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1, Tmp2.getOperand(2),
1873 Tmp2.getOperand(0), Tmp2.getOperand(1),
1874 Node->getOperand(2));
1876 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1,
1877 DAG.getCondCode(ISD::SETNE), Tmp2,
1878 DAG.getConstant(0, Tmp2.getValueType()),
1879 Node->getOperand(2));
1885 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1886 // Ensure that libcalls are emitted before a branch.
1887 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1888 Tmp1 = LegalizeOp(Tmp1);
1889 Tmp2 = Node->getOperand(2); // LHS
1890 Tmp3 = Node->getOperand(3); // RHS
1891 Tmp4 = Node->getOperand(1); // CC
1893 LegalizeSetCCOperands(Tmp2, Tmp3, Tmp4);
1894 LastCALLSEQ_END = DAG.getEntryNode();
1896 // If we didn't get both a LHS and RHS back from LegalizeSetCCOperands,
1897 // the LHS is a legal SETCC itself. In this case, we need to compare
1898 // the result against zero to select between true and false values.
1899 if (Tmp3.getNode() == 0) {
1900 Tmp3 = DAG.getConstant(0, Tmp2.getValueType());
1901 Tmp4 = DAG.getCondCode(ISD::SETNE);
1904 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp4, Tmp2, Tmp3,
1905 Node->getOperand(4));
1907 switch (TLI.getOperationAction(ISD::BR_CC, Tmp3.getValueType())) {
1908 default: assert(0 && "Unexpected action for BR_CC!");
1909 case TargetLowering::Legal: break;
1910 case TargetLowering::Custom:
1911 Tmp4 = TLI.LowerOperation(Result, DAG);
1912 if (Tmp4.getNode()) Result = Tmp4;
1917 LoadSDNode *LD = cast<LoadSDNode>(Node);
1918 Tmp1 = LegalizeOp(LD->getChain()); // Legalize the chain.
1919 Tmp2 = LegalizeOp(LD->getBasePtr()); // Legalize the base pointer.
1921 ISD::LoadExtType ExtType = LD->getExtensionType();
1922 if (ExtType == ISD::NON_EXTLOAD) {
1923 MVT VT = Node->getValueType(0);
1924 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, LD->getOffset());
1925 Tmp3 = Result.getValue(0);
1926 Tmp4 = Result.getValue(1);
1928 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
1929 default: assert(0 && "This action is not supported yet!");
1930 case TargetLowering::Legal:
1931 // If this is an unaligned load and the target doesn't support it,
1933 if (!TLI.allowsUnalignedMemoryAccesses()) {
1934 unsigned ABIAlignment = TLI.getTargetData()->
1935 getABITypeAlignment(LD->getMemoryVT().getTypeForMVT());
1936 if (LD->getAlignment() < ABIAlignment){
1937 Result = ExpandUnalignedLoad(cast<LoadSDNode>(Result.getNode()), DAG,
1939 Tmp3 = Result.getOperand(0);
1940 Tmp4 = Result.getOperand(1);
1941 Tmp3 = LegalizeOp(Tmp3);
1942 Tmp4 = LegalizeOp(Tmp4);
1946 case TargetLowering::Custom:
1947 Tmp1 = TLI.LowerOperation(Tmp3, DAG);
1948 if (Tmp1.getNode()) {
1949 Tmp3 = LegalizeOp(Tmp1);
1950 Tmp4 = LegalizeOp(Tmp1.getValue(1));
1953 case TargetLowering::Promote: {
1954 // Only promote a load of vector type to another.
1955 assert(VT.isVector() && "Cannot promote this load!");
1956 // Change base type to a different vector type.
1957 MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), VT);
1959 Tmp1 = DAG.getLoad(NVT, Tmp1, Tmp2, LD->getSrcValue(),
1960 LD->getSrcValueOffset(),
1961 LD->isVolatile(), LD->getAlignment());
1962 Tmp3 = LegalizeOp(DAG.getNode(ISD::BIT_CONVERT, VT, Tmp1));
1963 Tmp4 = LegalizeOp(Tmp1.getValue(1));
1967 // Since loads produce two values, make sure to remember that we
1968 // legalized both of them.
1969 AddLegalizedOperand(SDValue(Node, 0), Tmp3);
1970 AddLegalizedOperand(SDValue(Node, 1), Tmp4);
1971 return Op.getResNo() ? Tmp4 : Tmp3;
1973 MVT SrcVT = LD->getMemoryVT();
1974 unsigned SrcWidth = SrcVT.getSizeInBits();
1975 int SVOffset = LD->getSrcValueOffset();
1976 unsigned Alignment = LD->getAlignment();
1977 bool isVolatile = LD->isVolatile();
1979 if (SrcWidth != SrcVT.getStoreSizeInBits() &&
1980 // Some targets pretend to have an i1 loading operation, and actually
1981 // load an i8. This trick is correct for ZEXTLOAD because the top 7
1982 // bits are guaranteed to be zero; it helps the optimizers understand
1983 // that these bits are zero. It is also useful for EXTLOAD, since it
1984 // tells the optimizers that those bits are undefined. It would be
1985 // nice to have an effective generic way of getting these benefits...
1986 // Until such a way is found, don't insist on promoting i1 here.
1987 (SrcVT != MVT::i1 ||
1988 TLI.getLoadXAction(ExtType, MVT::i1) == TargetLowering::Promote)) {
1989 // Promote to a byte-sized load if not loading an integral number of
1990 // bytes. For example, promote EXTLOAD:i20 -> EXTLOAD:i24.
1991 unsigned NewWidth = SrcVT.getStoreSizeInBits();
1992 MVT NVT = MVT::getIntegerVT(NewWidth);
1995 // The extra bits are guaranteed to be zero, since we stored them that
1996 // way. A zext load from NVT thus automatically gives zext from SrcVT.
1998 ISD::LoadExtType NewExtType =
1999 ExtType == ISD::ZEXTLOAD ? ISD::ZEXTLOAD : ISD::EXTLOAD;
2001 Result = DAG.getExtLoad(NewExtType, Node->getValueType(0),
2002 Tmp1, Tmp2, LD->getSrcValue(), SVOffset,
2003 NVT, isVolatile, Alignment);
2005 Ch = Result.getValue(1); // The chain.
2007 if (ExtType == ISD::SEXTLOAD)
2008 // Having the top bits zero doesn't help when sign extending.
2009 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(),
2010 Result, DAG.getValueType(SrcVT));
2011 else if (ExtType == ISD::ZEXTLOAD || NVT == Result.getValueType())
2012 // All the top bits are guaranteed to be zero - inform the optimizers.
2013 Result = DAG.getNode(ISD::AssertZext, Result.getValueType(), Result,
2014 DAG.getValueType(SrcVT));
2016 Tmp1 = LegalizeOp(Result);
2017 Tmp2 = LegalizeOp(Ch);
2018 } else if (SrcWidth & (SrcWidth - 1)) {
2019 // If not loading a power-of-2 number of bits, expand as two loads.
2020 assert(SrcVT.isExtended() && !SrcVT.isVector() &&
2021 "Unsupported extload!");
2022 unsigned RoundWidth = 1 << Log2_32(SrcWidth);
2023 assert(RoundWidth < SrcWidth);
2024 unsigned ExtraWidth = SrcWidth - RoundWidth;
2025 assert(ExtraWidth < RoundWidth);
2026 assert(!(RoundWidth % 8) && !(ExtraWidth % 8) &&
2027 "Load size not an integral number of bytes!");
2028 MVT RoundVT = MVT::getIntegerVT(RoundWidth);
2029 MVT ExtraVT = MVT::getIntegerVT(ExtraWidth);
2031 unsigned IncrementSize;
2033 if (TLI.isLittleEndian()) {
2034 // EXTLOAD:i24 -> ZEXTLOAD:i16 | (shl EXTLOAD@+2:i8, 16)
2035 // Load the bottom RoundWidth bits.
2036 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, Node->getValueType(0), Tmp1, Tmp2,
2037 LD->getSrcValue(), SVOffset, RoundVT, isVolatile,
2040 // Load the remaining ExtraWidth bits.
2041 IncrementSize = RoundWidth / 8;
2042 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2,
2043 DAG.getIntPtrConstant(IncrementSize));
2044 Hi = DAG.getExtLoad(ExtType, Node->getValueType(0), Tmp1, Tmp2,
2045 LD->getSrcValue(), SVOffset + IncrementSize,
2046 ExtraVT, isVolatile,
2047 MinAlign(Alignment, IncrementSize));
2049 // Build a factor node to remember that this load is independent of the
2051 Ch = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
2054 // Move the top bits to the right place.
2055 Hi = DAG.getNode(ISD::SHL, Hi.getValueType(), Hi,
2056 DAG.getConstant(RoundWidth, TLI.getShiftAmountTy()));
2058 // Join the hi and lo parts.
2059 Result = DAG.getNode(ISD::OR, Node->getValueType(0), Lo, Hi);
2061 // Big endian - avoid unaligned loads.
2062 // EXTLOAD:i24 -> (shl EXTLOAD:i16, 8) | ZEXTLOAD@+2:i8
2063 // Load the top RoundWidth bits.
2064 Hi = DAG.getExtLoad(ExtType, Node->getValueType(0), Tmp1, Tmp2,
2065 LD->getSrcValue(), SVOffset, RoundVT, isVolatile,
2068 // Load the remaining ExtraWidth bits.
2069 IncrementSize = RoundWidth / 8;
2070 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2,
2071 DAG.getIntPtrConstant(IncrementSize));
2072 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, Node->getValueType(0), Tmp1, Tmp2,
2073 LD->getSrcValue(), SVOffset + IncrementSize,
2074 ExtraVT, isVolatile,
2075 MinAlign(Alignment, IncrementSize));
2077 // Build a factor node to remember that this load is independent of the
2079 Ch = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
2082 // Move the top bits to the right place.
2083 Hi = DAG.getNode(ISD::SHL, Hi.getValueType(), Hi,
2084 DAG.getConstant(ExtraWidth, TLI.getShiftAmountTy()));
2086 // Join the hi and lo parts.
2087 Result = DAG.getNode(ISD::OR, Node->getValueType(0), Lo, Hi);
2090 Tmp1 = LegalizeOp(Result);
2091 Tmp2 = LegalizeOp(Ch);
2093 switch (TLI.getLoadXAction(ExtType, SrcVT)) {
2094 default: assert(0 && "This action is not supported yet!");
2095 case TargetLowering::Custom:
2098 case TargetLowering::Legal:
2099 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, LD->getOffset());
2100 Tmp1 = Result.getValue(0);
2101 Tmp2 = Result.getValue(1);
2104 Tmp3 = TLI.LowerOperation(Result, DAG);
2105 if (Tmp3.getNode()) {
2106 Tmp1 = LegalizeOp(Tmp3);
2107 Tmp2 = LegalizeOp(Tmp3.getValue(1));
2110 // If this is an unaligned load and the target doesn't support it,
2112 if (!TLI.allowsUnalignedMemoryAccesses()) {
2113 unsigned ABIAlignment = TLI.getTargetData()->
2114 getABITypeAlignment(LD->getMemoryVT().getTypeForMVT());
2115 if (LD->getAlignment() < ABIAlignment){
2116 Result = ExpandUnalignedLoad(cast<LoadSDNode>(Result.getNode()), DAG,
2118 Tmp1 = Result.getOperand(0);
2119 Tmp2 = Result.getOperand(1);
2120 Tmp1 = LegalizeOp(Tmp1);
2121 Tmp2 = LegalizeOp(Tmp2);
2126 case TargetLowering::Expand:
2127 // f64 = EXTLOAD f32 should expand to LOAD, FP_EXTEND
2128 if (SrcVT == MVT::f32 && Node->getValueType(0) == MVT::f64) {
2129 SDValue Load = DAG.getLoad(SrcVT, Tmp1, Tmp2, LD->getSrcValue(),
2130 LD->getSrcValueOffset(),
2131 LD->isVolatile(), LD->getAlignment());
2132 Result = DAG.getNode(ISD::FP_EXTEND, Node->getValueType(0), Load);
2133 Tmp1 = LegalizeOp(Result); // Relegalize new nodes.
2134 Tmp2 = LegalizeOp(Load.getValue(1));
2137 assert(ExtType != ISD::EXTLOAD &&"EXTLOAD should always be supported!");
2138 // Turn the unsupported load into an EXTLOAD followed by an explicit
2139 // zero/sign extend inreg.
2140 Result = DAG.getExtLoad(ISD::EXTLOAD, Node->getValueType(0),
2141 Tmp1, Tmp2, LD->getSrcValue(),
2142 LD->getSrcValueOffset(), SrcVT,
2143 LD->isVolatile(), LD->getAlignment());
2145 if (ExtType == ISD::SEXTLOAD)
2146 ValRes = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(),
2147 Result, DAG.getValueType(SrcVT));
2149 ValRes = DAG.getZeroExtendInReg(Result, SrcVT);
2150 Tmp1 = LegalizeOp(ValRes); // Relegalize new nodes.
2151 Tmp2 = LegalizeOp(Result.getValue(1)); // Relegalize new nodes.
2156 // Since loads produce two values, make sure to remember that we legalized
2158 AddLegalizedOperand(SDValue(Node, 0), Tmp1);
2159 AddLegalizedOperand(SDValue(Node, 1), Tmp2);
2160 return Op.getResNo() ? Tmp2 : Tmp1;
2163 case ISD::EXTRACT_ELEMENT: {
2164 MVT OpTy = Node->getOperand(0).getValueType();
2165 switch (getTypeAction(OpTy)) {
2166 default: assert(0 && "EXTRACT_ELEMENT action for type unimplemented!");
2168 if (cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue()) {
2170 Result = DAG.getNode(ISD::SRL, OpTy, Node->getOperand(0),
2171 DAG.getConstant(OpTy.getSizeInBits()/2,
2172 TLI.getShiftAmountTy()));
2173 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), Result);
2176 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0),
2177 Node->getOperand(0));
2181 // Get both the low and high parts.
2182 ExpandOp(Node->getOperand(0), Tmp1, Tmp2);
2183 if (cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue())
2184 Result = Tmp2; // 1 -> Hi
2186 Result = Tmp1; // 0 -> Lo
2192 case ISD::CopyToReg:
2193 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2195 assert(isTypeLegal(Node->getOperand(2).getValueType()) &&
2196 "Register type must be legal!");
2197 // Legalize the incoming value (must be a legal type).
2198 Tmp2 = LegalizeOp(Node->getOperand(2));
2199 if (Node->getNumValues() == 1) {
2200 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1), Tmp2);
2202 assert(Node->getNumValues() == 2 && "Unknown CopyToReg");
2203 if (Node->getNumOperands() == 4) {
2204 Tmp3 = LegalizeOp(Node->getOperand(3));
2205 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1), Tmp2,
2208 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1),Tmp2);
2211 // Since this produces two values, make sure to remember that we legalized
2213 AddLegalizedOperand(SDValue(Node, 0), Result.getValue(0));
2214 AddLegalizedOperand(SDValue(Node, 1), Result.getValue(1));
2220 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2222 // Ensure that libcalls are emitted before a return.
2223 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
2224 Tmp1 = LegalizeOp(Tmp1);
2225 LastCALLSEQ_END = DAG.getEntryNode();
2227 switch (Node->getNumOperands()) {
2229 Tmp2 = Node->getOperand(1);
2230 Tmp3 = Node->getOperand(2); // Signness
2231 switch (getTypeAction(Tmp2.getValueType())) {
2233 Result = DAG.UpdateNodeOperands(Result, Tmp1, LegalizeOp(Tmp2), Tmp3);
2236 if (!Tmp2.getValueType().isVector()) {
2238 ExpandOp(Tmp2, Lo, Hi);
2240 // Big endian systems want the hi reg first.
2241 if (TLI.isBigEndian())
2245 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Tmp3, Hi,Tmp3);
2247 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Tmp3);
2248 Result = LegalizeOp(Result);
2250 SDNode *InVal = Tmp2.getNode();
2251 int InIx = Tmp2.getResNo();
2252 unsigned NumElems = InVal->getValueType(InIx).getVectorNumElements();
2253 MVT EVT = InVal->getValueType(InIx).getVectorElementType();
2255 // Figure out if there is a simple type corresponding to this Vector
2256 // type. If so, convert to the vector type.
2257 MVT TVT = MVT::getVectorVT(EVT, NumElems);
2258 if (TLI.isTypeLegal(TVT)) {
2259 // Turn this into a return of the vector type.
2260 Tmp2 = LegalizeOp(Tmp2);
2261 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2262 } else if (NumElems == 1) {
2263 // Turn this into a return of the scalar type.
2264 Tmp2 = ScalarizeVectorOp(Tmp2);
2265 Tmp2 = LegalizeOp(Tmp2);
2266 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2268 // FIXME: Returns of gcc generic vectors smaller than a legal type
2269 // should be returned in integer registers!
2271 // The scalarized value type may not be legal, e.g. it might require
2272 // promotion or expansion. Relegalize the return.
2273 Result = LegalizeOp(Result);
2275 // FIXME: Returns of gcc generic vectors larger than a legal vector
2276 // type should be returned by reference!
2278 SplitVectorOp(Tmp2, Lo, Hi);
2279 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Tmp3, Hi,Tmp3);
2280 Result = LegalizeOp(Result);
2285 Tmp2 = PromoteOp(Node->getOperand(1));
2286 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2287 Result = LegalizeOp(Result);
2292 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2294 default: { // ret <values>
2295 SmallVector<SDValue, 8> NewValues;
2296 NewValues.push_back(Tmp1);
2297 for (unsigned i = 1, e = Node->getNumOperands(); i < e; i += 2)
2298 switch (getTypeAction(Node->getOperand(i).getValueType())) {
2300 NewValues.push_back(LegalizeOp(Node->getOperand(i)));
2301 NewValues.push_back(Node->getOperand(i+1));
2305 assert(!Node->getOperand(i).getValueType().isExtended() &&
2306 "FIXME: TODO: implement returning non-legal vector types!");
2307 ExpandOp(Node->getOperand(i), Lo, Hi);
2308 NewValues.push_back(Lo);
2309 NewValues.push_back(Node->getOperand(i+1));
2311 NewValues.push_back(Hi);
2312 NewValues.push_back(Node->getOperand(i+1));
2317 assert(0 && "Can't promote multiple return value yet!");
2320 if (NewValues.size() == Node->getNumOperands())
2321 Result = DAG.UpdateNodeOperands(Result, &NewValues[0],NewValues.size());
2323 Result = DAG.getNode(ISD::RET, MVT::Other,
2324 &NewValues[0], NewValues.size());
2329 if (Result.getOpcode() == ISD::RET) {
2330 switch (TLI.getOperationAction(Result.getOpcode(), MVT::Other)) {
2331 default: assert(0 && "This action is not supported yet!");
2332 case TargetLowering::Legal: break;
2333 case TargetLowering::Custom:
2334 Tmp1 = TLI.LowerOperation(Result, DAG);
2335 if (Tmp1.getNode()) Result = Tmp1;
2341 StoreSDNode *ST = cast<StoreSDNode>(Node);
2342 Tmp1 = LegalizeOp(ST->getChain()); // Legalize the chain.
2343 Tmp2 = LegalizeOp(ST->getBasePtr()); // Legalize the pointer.
2344 int SVOffset = ST->getSrcValueOffset();
2345 unsigned Alignment = ST->getAlignment();
2346 bool isVolatile = ST->isVolatile();
2348 if (!ST->isTruncatingStore()) {
2349 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr'
2350 // FIXME: We shouldn't do this for TargetConstantFP's.
2351 // FIXME: move this to the DAG Combiner! Note that we can't regress due
2352 // to phase ordering between legalized code and the dag combiner. This
2353 // probably means that we need to integrate dag combiner and legalizer
2355 // We generally can't do this one for long doubles.
2356 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(ST->getValue())) {
2357 if (CFP->getValueType(0) == MVT::f32 &&
2358 getTypeAction(MVT::i32) == Legal) {
2359 Tmp3 = DAG.getConstant(CFP->getValueAPF().
2360 convertToAPInt().zextOrTrunc(32),
2362 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2363 SVOffset, isVolatile, Alignment);
2365 } else if (CFP->getValueType(0) == MVT::f64) {
2366 // If this target supports 64-bit registers, do a single 64-bit store.
2367 if (getTypeAction(MVT::i64) == Legal) {
2368 Tmp3 = DAG.getConstant(CFP->getValueAPF().convertToAPInt().
2369 zextOrTrunc(64), MVT::i64);
2370 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2371 SVOffset, isVolatile, Alignment);
2373 } else if (getTypeAction(MVT::i32) == Legal && !ST->isVolatile()) {
2374 // Otherwise, if the target supports 32-bit registers, use 2 32-bit
2375 // stores. If the target supports neither 32- nor 64-bits, this
2376 // xform is certainly not worth it.
2377 const APInt &IntVal =CFP->getValueAPF().convertToAPInt();
2378 SDValue Lo = DAG.getConstant(APInt(IntVal).trunc(32), MVT::i32);
2379 SDValue Hi = DAG.getConstant(IntVal.lshr(32).trunc(32), MVT::i32);
2380 if (TLI.isBigEndian()) std::swap(Lo, Hi);
2382 Lo = DAG.getStore(Tmp1, Lo, Tmp2, ST->getSrcValue(),
2383 SVOffset, isVolatile, Alignment);
2384 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2,
2385 DAG.getIntPtrConstant(4));
2386 Hi = DAG.getStore(Tmp1, Hi, Tmp2, ST->getSrcValue(), SVOffset+4,
2387 isVolatile, MinAlign(Alignment, 4U));
2389 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi);
2395 switch (getTypeAction(ST->getMemoryVT())) {
2397 Tmp3 = LegalizeOp(ST->getValue());
2398 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2,
2401 MVT VT = Tmp3.getValueType();
2402 switch (TLI.getOperationAction(ISD::STORE, VT)) {
2403 default: assert(0 && "This action is not supported yet!");
2404 case TargetLowering::Legal:
2405 // If this is an unaligned store and the target doesn't support it,
2407 if (!TLI.allowsUnalignedMemoryAccesses()) {
2408 unsigned ABIAlignment = TLI.getTargetData()->
2409 getABITypeAlignment(ST->getMemoryVT().getTypeForMVT());
2410 if (ST->getAlignment() < ABIAlignment)
2411 Result = ExpandUnalignedStore(cast<StoreSDNode>(Result.getNode()), DAG,
2415 case TargetLowering::Custom:
2416 Tmp1 = TLI.LowerOperation(Result, DAG);
2417 if (Tmp1.getNode()) Result = Tmp1;
2419 case TargetLowering::Promote:
2420 assert(VT.isVector() && "Unknown legal promote case!");
2421 Tmp3 = DAG.getNode(ISD::BIT_CONVERT,
2422 TLI.getTypeToPromoteTo(ISD::STORE, VT), Tmp3);
2423 Result = DAG.getStore(Tmp1, Tmp3, Tmp2,
2424 ST->getSrcValue(), SVOffset, isVolatile,
2431 // Truncate the value and store the result.
2432 Tmp3 = PromoteOp(ST->getValue());
2433 Result = DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2434 SVOffset, ST->getMemoryVT(),
2435 isVolatile, Alignment);
2439 unsigned IncrementSize = 0;
2442 // If this is a vector type, then we have to calculate the increment as
2443 // the product of the element size in bytes, and the number of elements
2444 // in the high half of the vector.
2445 if (ST->getValue().getValueType().isVector()) {
2446 SDNode *InVal = ST->getValue().getNode();
2447 int InIx = ST->getValue().getResNo();
2448 MVT InVT = InVal->getValueType(InIx);
2449 unsigned NumElems = InVT.getVectorNumElements();
2450 MVT EVT = InVT.getVectorElementType();
2452 // Figure out if there is a simple type corresponding to this Vector
2453 // type. If so, convert to the vector type.
2454 MVT TVT = MVT::getVectorVT(EVT, NumElems);
2455 if (TLI.isTypeLegal(TVT)) {
2456 // Turn this into a normal store of the vector type.
2457 Tmp3 = LegalizeOp(ST->getValue());
2458 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2459 SVOffset, isVolatile, Alignment);
2460 Result = LegalizeOp(Result);
2462 } else if (NumElems == 1) {
2463 // Turn this into a normal store of the scalar type.
2464 Tmp3 = ScalarizeVectorOp(ST->getValue());
2465 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2466 SVOffset, isVolatile, Alignment);
2467 // The scalarized value type may not be legal, e.g. it might require
2468 // promotion or expansion. Relegalize the scalar store.
2469 Result = LegalizeOp(Result);
2472 SplitVectorOp(ST->getValue(), Lo, Hi);
2473 IncrementSize = Lo.getNode()->getValueType(0).getVectorNumElements() *
2474 EVT.getSizeInBits()/8;
2477 ExpandOp(ST->getValue(), Lo, Hi);
2478 IncrementSize = Hi.getNode() ? Hi.getValueType().getSizeInBits()/8 : 0;
2480 if (Hi.getNode() && TLI.isBigEndian())
2484 Lo = DAG.getStore(Tmp1, Lo, Tmp2, ST->getSrcValue(),
2485 SVOffset, isVolatile, Alignment);
2487 if (Hi.getNode() == NULL) {
2488 // Must be int <-> float one-to-one expansion.
2493 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2,
2494 DAG.getIntPtrConstant(IncrementSize));
2495 assert(isTypeLegal(Tmp2.getValueType()) &&
2496 "Pointers must be legal!");
2497 SVOffset += IncrementSize;
2498 Alignment = MinAlign(Alignment, IncrementSize);
2499 Hi = DAG.getStore(Tmp1, Hi, Tmp2, ST->getSrcValue(),
2500 SVOffset, isVolatile, Alignment);
2501 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi);
2505 switch (getTypeAction(ST->getValue().getValueType())) {
2507 Tmp3 = LegalizeOp(ST->getValue());
2510 // We can promote the value, the truncstore will still take care of it.
2511 Tmp3 = PromoteOp(ST->getValue());
2514 // Just store the low part. This may become a non-trunc store, so make
2515 // sure to use getTruncStore, not UpdateNodeOperands below.
2516 ExpandOp(ST->getValue(), Tmp3, Tmp4);
2517 return DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2518 SVOffset, MVT::i8, isVolatile, Alignment);
2521 MVT StVT = ST->getMemoryVT();
2522 unsigned StWidth = StVT.getSizeInBits();
2524 if (StWidth != StVT.getStoreSizeInBits()) {
2525 // Promote to a byte-sized store with upper bits zero if not
2526 // storing an integral number of bytes. For example, promote
2527 // TRUNCSTORE:i1 X -> TRUNCSTORE:i8 (and X, 1)
2528 MVT NVT = MVT::getIntegerVT(StVT.getStoreSizeInBits());
2529 Tmp3 = DAG.getZeroExtendInReg(Tmp3, StVT);
2530 Result = DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2531 SVOffset, NVT, isVolatile, Alignment);
2532 } else if (StWidth & (StWidth - 1)) {
2533 // If not storing a power-of-2 number of bits, expand as two stores.
2534 assert(StVT.isExtended() && !StVT.isVector() &&
2535 "Unsupported truncstore!");
2536 unsigned RoundWidth = 1 << Log2_32(StWidth);
2537 assert(RoundWidth < StWidth);
2538 unsigned ExtraWidth = StWidth - RoundWidth;
2539 assert(ExtraWidth < RoundWidth);
2540 assert(!(RoundWidth % 8) && !(ExtraWidth % 8) &&
2541 "Store size not an integral number of bytes!");
2542 MVT RoundVT = MVT::getIntegerVT(RoundWidth);
2543 MVT ExtraVT = MVT::getIntegerVT(ExtraWidth);
2545 unsigned IncrementSize;
2547 if (TLI.isLittleEndian()) {
2548 // TRUNCSTORE:i24 X -> TRUNCSTORE:i16 X, TRUNCSTORE@+2:i8 (srl X, 16)
2549 // Store the bottom RoundWidth bits.
2550 Lo = DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2552 isVolatile, Alignment);
2554 // Store the remaining ExtraWidth bits.
2555 IncrementSize = RoundWidth / 8;
2556 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2,
2557 DAG.getIntPtrConstant(IncrementSize));
2558 Hi = DAG.getNode(ISD::SRL, Tmp3.getValueType(), Tmp3,
2559 DAG.getConstant(RoundWidth, TLI.getShiftAmountTy()));
2560 Hi = DAG.getTruncStore(Tmp1, Hi, Tmp2, ST->getSrcValue(),
2561 SVOffset + IncrementSize, ExtraVT, isVolatile,
2562 MinAlign(Alignment, IncrementSize));
2564 // Big endian - avoid unaligned stores.
2565 // TRUNCSTORE:i24 X -> TRUNCSTORE:i16 (srl X, 8), TRUNCSTORE@+2:i8 X
2566 // Store the top RoundWidth bits.
2567 Hi = DAG.getNode(ISD::SRL, Tmp3.getValueType(), Tmp3,
2568 DAG.getConstant(ExtraWidth, TLI.getShiftAmountTy()));
2569 Hi = DAG.getTruncStore(Tmp1, Hi, Tmp2, ST->getSrcValue(), SVOffset,
2570 RoundVT, isVolatile, Alignment);
2572 // Store the remaining ExtraWidth bits.
2573 IncrementSize = RoundWidth / 8;
2574 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2,
2575 DAG.getIntPtrConstant(IncrementSize));
2576 Lo = DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2577 SVOffset + IncrementSize, ExtraVT, isVolatile,
2578 MinAlign(Alignment, IncrementSize));
2581 // The order of the stores doesn't matter.
2582 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi);
2584 if (Tmp1 != ST->getChain() || Tmp3 != ST->getValue() ||
2585 Tmp2 != ST->getBasePtr())
2586 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2,
2589 switch (TLI.getTruncStoreAction(ST->getValue().getValueType(), StVT)) {
2590 default: assert(0 && "This action is not supported yet!");
2591 case TargetLowering::Legal:
2592 // If this is an unaligned store and the target doesn't support it,
2594 if (!TLI.allowsUnalignedMemoryAccesses()) {
2595 unsigned ABIAlignment = TLI.getTargetData()->
2596 getABITypeAlignment(ST->getMemoryVT().getTypeForMVT());
2597 if (ST->getAlignment() < ABIAlignment)
2598 Result = ExpandUnalignedStore(cast<StoreSDNode>(Result.getNode()), DAG,
2602 case TargetLowering::Custom:
2603 Result = TLI.LowerOperation(Result, DAG);
2606 // TRUNCSTORE:i16 i32 -> STORE i16
2607 assert(isTypeLegal(StVT) && "Do not know how to expand this store!");
2608 Tmp3 = DAG.getNode(ISD::TRUNCATE, StVT, Tmp3);
2609 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(), SVOffset,
2610 isVolatile, Alignment);
2618 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2619 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
2621 case ISD::STACKSAVE:
2622 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2623 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2624 Tmp1 = Result.getValue(0);
2625 Tmp2 = Result.getValue(1);
2627 switch (TLI.getOperationAction(ISD::STACKSAVE, MVT::Other)) {
2628 default: assert(0 && "This action is not supported yet!");
2629 case TargetLowering::Legal: break;
2630 case TargetLowering::Custom:
2631 Tmp3 = TLI.LowerOperation(Result, DAG);
2632 if (Tmp3.getNode()) {
2633 Tmp1 = LegalizeOp(Tmp3);
2634 Tmp2 = LegalizeOp(Tmp3.getValue(1));
2637 case TargetLowering::Expand:
2638 // Expand to CopyFromReg if the target set
2639 // StackPointerRegisterToSaveRestore.
2640 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) {
2641 Tmp1 = DAG.getCopyFromReg(Result.getOperand(0), SP,
2642 Node->getValueType(0));
2643 Tmp2 = Tmp1.getValue(1);
2645 Tmp1 = DAG.getNode(ISD::UNDEF, Node->getValueType(0));
2646 Tmp2 = Node->getOperand(0);
2651 // Since stacksave produce two values, make sure to remember that we
2652 // legalized both of them.
2653 AddLegalizedOperand(SDValue(Node, 0), Tmp1);
2654 AddLegalizedOperand(SDValue(Node, 1), Tmp2);
2655 return Op.getResNo() ? Tmp2 : Tmp1;
2657 case ISD::STACKRESTORE:
2658 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2659 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
2660 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
2662 switch (TLI.getOperationAction(ISD::STACKRESTORE, MVT::Other)) {
2663 default: assert(0 && "This action is not supported yet!");
2664 case TargetLowering::Legal: break;
2665 case TargetLowering::Custom:
2666 Tmp1 = TLI.LowerOperation(Result, DAG);
2667 if (Tmp1.getNode()) Result = Tmp1;
2669 case TargetLowering::Expand:
2670 // Expand to CopyToReg if the target set
2671 // StackPointerRegisterToSaveRestore.
2672 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) {
2673 Result = DAG.getCopyToReg(Tmp1, SP, Tmp2);
2681 case ISD::READCYCLECOUNTER:
2682 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain
2683 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2684 switch (TLI.getOperationAction(ISD::READCYCLECOUNTER,
2685 Node->getValueType(0))) {
2686 default: assert(0 && "This action is not supported yet!");
2687 case TargetLowering::Legal:
2688 Tmp1 = Result.getValue(0);
2689 Tmp2 = Result.getValue(1);
2691 case TargetLowering::Custom:
2692 Result = TLI.LowerOperation(Result, DAG);
2693 Tmp1 = LegalizeOp(Result.getValue(0));
2694 Tmp2 = LegalizeOp(Result.getValue(1));
2698 // Since rdcc produce two values, make sure to remember that we legalized
2700 AddLegalizedOperand(SDValue(Node, 0), Tmp1);
2701 AddLegalizedOperand(SDValue(Node, 1), Tmp2);
2705 switch (getTypeAction(Node->getOperand(0).getValueType())) {
2706 case Expand: assert(0 && "It's impossible to expand bools");
2708 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the condition.
2711 Tmp1 = PromoteOp(Node->getOperand(0)); // Promote the condition.
2712 // Make sure the condition is either zero or one.
2713 unsigned BitWidth = Tmp1.getValueSizeInBits();
2714 if (!DAG.MaskedValueIsZero(Tmp1,
2715 APInt::getHighBitsSet(BitWidth, BitWidth-1)))
2716 Tmp1 = DAG.getZeroExtendInReg(Tmp1, MVT::i1);
2720 Tmp2 = LegalizeOp(Node->getOperand(1)); // TrueVal
2721 Tmp3 = LegalizeOp(Node->getOperand(2)); // FalseVal
2723 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2725 switch (TLI.getOperationAction(ISD::SELECT, Tmp2.getValueType())) {
2726 default: assert(0 && "This action is not supported yet!");
2727 case TargetLowering::Legal: break;
2728 case TargetLowering::Custom: {
2729 Tmp1 = TLI.LowerOperation(Result, DAG);
2730 if (Tmp1.getNode()) Result = Tmp1;
2733 case TargetLowering::Expand:
2734 if (Tmp1.getOpcode() == ISD::SETCC) {
2735 Result = DAG.getSelectCC(Tmp1.getOperand(0), Tmp1.getOperand(1),
2737 cast<CondCodeSDNode>(Tmp1.getOperand(2))->get());
2739 Result = DAG.getSelectCC(Tmp1,
2740 DAG.getConstant(0, Tmp1.getValueType()),
2741 Tmp2, Tmp3, ISD::SETNE);
2744 case TargetLowering::Promote: {
2746 TLI.getTypeToPromoteTo(ISD::SELECT, Tmp2.getValueType());
2747 unsigned ExtOp, TruncOp;
2748 if (Tmp2.getValueType().isVector()) {
2749 ExtOp = ISD::BIT_CONVERT;
2750 TruncOp = ISD::BIT_CONVERT;
2751 } else if (Tmp2.getValueType().isInteger()) {
2752 ExtOp = ISD::ANY_EXTEND;
2753 TruncOp = ISD::TRUNCATE;
2755 ExtOp = ISD::FP_EXTEND;
2756 TruncOp = ISD::FP_ROUND;
2758 // Promote each of the values to the new type.
2759 Tmp2 = DAG.getNode(ExtOp, NVT, Tmp2);
2760 Tmp3 = DAG.getNode(ExtOp, NVT, Tmp3);
2761 // Perform the larger operation, then round down.
2762 Result = DAG.getNode(ISD::SELECT, NVT, Tmp1, Tmp2,Tmp3);
2763 if (TruncOp != ISD::FP_ROUND)
2764 Result = DAG.getNode(TruncOp, Node->getValueType(0), Result);
2766 Result = DAG.getNode(TruncOp, Node->getValueType(0), Result,
2767 DAG.getIntPtrConstant(0));
2772 case ISD::SELECT_CC: {
2773 Tmp1 = Node->getOperand(0); // LHS
2774 Tmp2 = Node->getOperand(1); // RHS
2775 Tmp3 = LegalizeOp(Node->getOperand(2)); // True
2776 Tmp4 = LegalizeOp(Node->getOperand(3)); // False
2777 SDValue CC = Node->getOperand(4);
2779 LegalizeSetCCOperands(Tmp1, Tmp2, CC);
2781 // If we didn't get both a LHS and RHS back from LegalizeSetCCOperands,
2782 // the LHS is a legal SETCC itself. In this case, we need to compare
2783 // the result against zero to select between true and false values.
2784 if (Tmp2.getNode() == 0) {
2785 Tmp2 = DAG.getConstant(0, Tmp1.getValueType());
2786 CC = DAG.getCondCode(ISD::SETNE);
2788 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4, CC);
2790 // Everything is legal, see if we should expand this op or something.
2791 switch (TLI.getOperationAction(ISD::SELECT_CC, Tmp3.getValueType())) {
2792 default: assert(0 && "This action is not supported yet!");
2793 case TargetLowering::Legal: break;
2794 case TargetLowering::Custom:
2795 Tmp1 = TLI.LowerOperation(Result, DAG);
2796 if (Tmp1.getNode()) Result = Tmp1;
2802 Tmp1 = Node->getOperand(0);
2803 Tmp2 = Node->getOperand(1);
2804 Tmp3 = Node->getOperand(2);
2805 LegalizeSetCCOperands(Tmp1, Tmp2, Tmp3);
2807 // If we had to Expand the SetCC operands into a SELECT node, then it may
2808 // not always be possible to return a true LHS & RHS. In this case, just
2809 // return the value we legalized, returned in the LHS
2810 if (Tmp2.getNode() == 0) {
2815 switch (TLI.getOperationAction(ISD::SETCC, Tmp1.getValueType())) {
2816 default: assert(0 && "Cannot handle this action for SETCC yet!");
2817 case TargetLowering::Custom:
2820 case TargetLowering::Legal:
2821 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2823 Tmp4 = TLI.LowerOperation(Result, DAG);
2824 if (Tmp4.getNode()) Result = Tmp4;
2827 case TargetLowering::Promote: {
2828 // First step, figure out the appropriate operation to use.
2829 // Allow SETCC to not be supported for all legal data types
2830 // Mostly this targets FP
2831 MVT NewInTy = Node->getOperand(0).getValueType();
2832 MVT OldVT = NewInTy; OldVT = OldVT;
2834 // Scan for the appropriate larger type to use.
2836 NewInTy = (MVT::SimpleValueType)(NewInTy.getSimpleVT()+1);
2838 assert(NewInTy.isInteger() == OldVT.isInteger() &&
2839 "Fell off of the edge of the integer world");
2840 assert(NewInTy.isFloatingPoint() == OldVT.isFloatingPoint() &&
2841 "Fell off of the edge of the floating point world");
2843 // If the target supports SETCC of this type, use it.
2844 if (TLI.isOperationLegal(ISD::SETCC, NewInTy))
2847 if (NewInTy.isInteger())
2848 assert(0 && "Cannot promote Legal Integer SETCC yet");
2850 Tmp1 = DAG.getNode(ISD::FP_EXTEND, NewInTy, Tmp1);
2851 Tmp2 = DAG.getNode(ISD::FP_EXTEND, NewInTy, Tmp2);
2853 Tmp1 = LegalizeOp(Tmp1);
2854 Tmp2 = LegalizeOp(Tmp2);
2855 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2856 Result = LegalizeOp(Result);
2859 case TargetLowering::Expand:
2860 // Expand a setcc node into a select_cc of the same condition, lhs, and
2861 // rhs that selects between const 1 (true) and const 0 (false).
2862 MVT VT = Node->getValueType(0);
2863 Result = DAG.getNode(ISD::SELECT_CC, VT, Tmp1, Tmp2,
2864 DAG.getConstant(1, VT), DAG.getConstant(0, VT),
2870 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
2871 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS
2872 SDValue CC = Node->getOperand(2);
2874 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, CC);
2876 // Everything is legal, see if we should expand this op or something.
2877 switch (TLI.getOperationAction(ISD::VSETCC, Tmp1.getValueType())) {
2878 default: assert(0 && "This action is not supported yet!");
2879 case TargetLowering::Legal: break;
2880 case TargetLowering::Custom:
2881 Tmp1 = TLI.LowerOperation(Result, DAG);
2882 if (Tmp1.getNode()) Result = Tmp1;
2888 case ISD::SHL_PARTS:
2889 case ISD::SRA_PARTS:
2890 case ISD::SRL_PARTS: {
2891 SmallVector<SDValue, 8> Ops;
2892 bool Changed = false;
2893 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
2894 Ops.push_back(LegalizeOp(Node->getOperand(i)));
2895 Changed |= Ops.back() != Node->getOperand(i);
2898 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
2900 switch (TLI.getOperationAction(Node->getOpcode(),
2901 Node->getValueType(0))) {
2902 default: assert(0 && "This action is not supported yet!");
2903 case TargetLowering::Legal: break;
2904 case TargetLowering::Custom:
2905 Tmp1 = TLI.LowerOperation(Result, DAG);
2906 if (Tmp1.getNode()) {
2907 SDValue Tmp2, RetVal(0, 0);
2908 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) {
2909 Tmp2 = LegalizeOp(Tmp1.getValue(i));
2910 AddLegalizedOperand(SDValue(Node, i), Tmp2);
2911 if (i == Op.getResNo())
2914 assert(RetVal.getNode() && "Illegal result number");
2920 // Since these produce multiple values, make sure to remember that we
2921 // legalized all of them.
2922 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
2923 AddLegalizedOperand(SDValue(Node, i), Result.getValue(i));
2924 return Result.getValue(Op.getResNo());
2946 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
2947 switch (getTypeAction(Node->getOperand(1).getValueType())) {
2948 case Expand: assert(0 && "Not possible");
2950 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the RHS.
2953 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the RHS.
2957 if ((Node->getOpcode() == ISD::SHL ||
2958 Node->getOpcode() == ISD::SRL ||
2959 Node->getOpcode() == ISD::SRA) &&
2960 !Node->getValueType(0).isVector()) {
2961 if (TLI.getShiftAmountTy().bitsLT(Tmp2.getValueType()))
2962 Tmp2 = DAG.getNode(ISD::TRUNCATE, TLI.getShiftAmountTy(), Tmp2);
2963 else if (TLI.getShiftAmountTy().bitsGT(Tmp2.getValueType()))
2964 Tmp2 = DAG.getNode(ISD::ANY_EXTEND, TLI.getShiftAmountTy(), Tmp2);
2967 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
2969 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
2970 default: assert(0 && "BinOp legalize operation not supported");
2971 case TargetLowering::Legal: break;
2972 case TargetLowering::Custom:
2973 Tmp1 = TLI.LowerOperation(Result, DAG);
2974 if (Tmp1.getNode()) {
2978 // Fall through if the custom lower can't deal with the operation
2979 case TargetLowering::Expand: {
2980 MVT VT = Op.getValueType();
2982 // See if multiply or divide can be lowered using two-result operations.
2983 SDVTList VTs = DAG.getVTList(VT, VT);
2984 if (Node->getOpcode() == ISD::MUL) {
2985 // We just need the low half of the multiply; try both the signed
2986 // and unsigned forms. If the target supports both SMUL_LOHI and
2987 // UMUL_LOHI, form a preference by checking which forms of plain
2988 // MULH it supports.
2989 bool HasSMUL_LOHI = TLI.isOperationLegal(ISD::SMUL_LOHI, VT);
2990 bool HasUMUL_LOHI = TLI.isOperationLegal(ISD::UMUL_LOHI, VT);
2991 bool HasMULHS = TLI.isOperationLegal(ISD::MULHS, VT);
2992 bool HasMULHU = TLI.isOperationLegal(ISD::MULHU, VT);
2993 unsigned OpToUse = 0;
2994 if (HasSMUL_LOHI && !HasMULHS) {
2995 OpToUse = ISD::SMUL_LOHI;
2996 } else if (HasUMUL_LOHI && !HasMULHU) {
2997 OpToUse = ISD::UMUL_LOHI;
2998 } else if (HasSMUL_LOHI) {
2999 OpToUse = ISD::SMUL_LOHI;
3000 } else if (HasUMUL_LOHI) {
3001 OpToUse = ISD::UMUL_LOHI;
3004 Result = SDValue(DAG.getNode(OpToUse, VTs, Tmp1, Tmp2).getNode(), 0);
3008 if (Node->getOpcode() == ISD::MULHS &&
3009 TLI.isOperationLegal(ISD::SMUL_LOHI, VT)) {
3010 Result = SDValue(DAG.getNode(ISD::SMUL_LOHI, VTs, Tmp1, Tmp2).getNode(),
3014 if (Node->getOpcode() == ISD::MULHU &&
3015 TLI.isOperationLegal(ISD::UMUL_LOHI, VT)) {
3016 Result = SDValue(DAG.getNode(ISD::UMUL_LOHI, VTs, Tmp1, Tmp2).getNode(),
3020 if (Node->getOpcode() == ISD::SDIV &&
3021 TLI.isOperationLegal(ISD::SDIVREM, VT)) {
3022 Result = SDValue(DAG.getNode(ISD::SDIVREM, VTs, Tmp1, Tmp2).getNode(),
3026 if (Node->getOpcode() == ISD::UDIV &&
3027 TLI.isOperationLegal(ISD::UDIVREM, VT)) {
3028 Result = SDValue(DAG.getNode(ISD::UDIVREM, VTs, Tmp1, Tmp2).getNode(),
3033 // Check to see if we have a libcall for this operator.
3034 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
3035 bool isSigned = false;
3036 switch (Node->getOpcode()) {
3039 if (VT == MVT::i32) {
3040 LC = Node->getOpcode() == ISD::UDIV
3041 ? RTLIB::UDIV_I32 : RTLIB::SDIV_I32;
3042 isSigned = Node->getOpcode() == ISD::SDIV;
3047 LC = RTLIB::MUL_I32;
3050 LC = GetFPLibCall(VT, RTLIB::POW_F32, RTLIB::POW_F64, RTLIB::POW_F80,
3051 RTLIB::POW_PPCF128);
3055 if (LC != RTLIB::UNKNOWN_LIBCALL) {
3057 Result = ExpandLibCall(LC, Node, isSigned, Dummy);
3061 assert(Node->getValueType(0).isVector() &&
3062 "Cannot expand this binary operator!");
3063 // Expand the operation into a bunch of nasty scalar code.
3064 Result = LegalizeOp(UnrollVectorOp(Op));
3067 case TargetLowering::Promote: {
3068 switch (Node->getOpcode()) {
3069 default: assert(0 && "Do not know how to promote this BinOp!");
3073 MVT OVT = Node->getValueType(0);
3074 MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
3075 assert(OVT.isVector() && "Cannot promote this BinOp!");
3076 // Bit convert each of the values to the new type.
3077 Tmp1 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp1);
3078 Tmp2 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp2);
3079 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
3080 // Bit convert the result back the original type.
3081 Result = DAG.getNode(ISD::BIT_CONVERT, OVT, Result);
3089 case ISD::SMUL_LOHI:
3090 case ISD::UMUL_LOHI:
3093 // These nodes will only be produced by target-specific lowering, so
3094 // they shouldn't be here if they aren't legal.
3095 assert(TLI.isOperationLegal(Node->getOpcode(), Node->getValueType(0)) &&
3096 "This must be legal!");
3098 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
3099 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS
3100 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
3103 case ISD::FCOPYSIGN: // FCOPYSIGN does not require LHS/RHS to match type!
3104 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
3105 switch (getTypeAction(Node->getOperand(1).getValueType())) {
3106 case Expand: assert(0 && "Not possible");
3108 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the RHS.
3111 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the RHS.
3115 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
3117 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3118 default: assert(0 && "Operation not supported");
3119 case TargetLowering::Custom:
3120 Tmp1 = TLI.LowerOperation(Result, DAG);
3121 if (Tmp1.getNode()) Result = Tmp1;
3123 case TargetLowering::Legal: break;
3124 case TargetLowering::Expand: {
3125 // If this target supports fabs/fneg natively and select is cheap,
3126 // do this efficiently.
3127 if (!TLI.isSelectExpensive() &&
3128 TLI.getOperationAction(ISD::FABS, Tmp1.getValueType()) ==
3129 TargetLowering::Legal &&
3130 TLI.getOperationAction(ISD::FNEG, Tmp1.getValueType()) ==
3131 TargetLowering::Legal) {
3132 // Get the sign bit of the RHS.
3134 Tmp2.getValueType() == MVT::f32 ? MVT::i32 : MVT::i64;
3135 SDValue SignBit = DAG.getNode(ISD::BIT_CONVERT, IVT, Tmp2);
3136 SignBit = DAG.getSetCC(TLI.getSetCCResultType(SignBit),
3137 SignBit, DAG.getConstant(0, IVT), ISD::SETLT);
3138 // Get the absolute value of the result.
3139 SDValue AbsVal = DAG.getNode(ISD::FABS, Tmp1.getValueType(), Tmp1);
3140 // Select between the nabs and abs value based on the sign bit of
3142 Result = DAG.getNode(ISD::SELECT, AbsVal.getValueType(), SignBit,
3143 DAG.getNode(ISD::FNEG, AbsVal.getValueType(),
3146 Result = LegalizeOp(Result);
3150 // Otherwise, do bitwise ops!
3152 Node->getValueType(0) == MVT::f32 ? MVT::i32 : MVT::i64;
3153 Result = ExpandFCOPYSIGNToBitwiseOps(Node, NVT, DAG, TLI);
3154 Result = DAG.getNode(ISD::BIT_CONVERT, Node->getValueType(0), Result);
3155 Result = LegalizeOp(Result);
3163 Tmp1 = LegalizeOp(Node->getOperand(0));
3164 Tmp2 = LegalizeOp(Node->getOperand(1));
3165 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
3166 // Since this produces two values, make sure to remember that we legalized
3168 AddLegalizedOperand(SDValue(Node, 0), Result.getValue(0));
3169 AddLegalizedOperand(SDValue(Node, 1), Result.getValue(1));
3174 Tmp1 = LegalizeOp(Node->getOperand(0));
3175 Tmp2 = LegalizeOp(Node->getOperand(1));
3176 Tmp3 = LegalizeOp(Node->getOperand(2));
3177 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
3178 // Since this produces two values, make sure to remember that we legalized
3180 AddLegalizedOperand(SDValue(Node, 0), Result.getValue(0));
3181 AddLegalizedOperand(SDValue(Node, 1), Result.getValue(1));
3184 case ISD::BUILD_PAIR: {
3185 MVT PairTy = Node->getValueType(0);
3186 // TODO: handle the case where the Lo and Hi operands are not of legal type
3187 Tmp1 = LegalizeOp(Node->getOperand(0)); // Lo
3188 Tmp2 = LegalizeOp(Node->getOperand(1)); // Hi
3189 switch (TLI.getOperationAction(ISD::BUILD_PAIR, PairTy)) {
3190 case TargetLowering::Promote:
3191 case TargetLowering::Custom:
3192 assert(0 && "Cannot promote/custom this yet!");
3193 case TargetLowering::Legal:
3194 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1))
3195 Result = DAG.getNode(ISD::BUILD_PAIR, PairTy, Tmp1, Tmp2);
3197 case TargetLowering::Expand:
3198 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, PairTy, Tmp1);
3199 Tmp2 = DAG.getNode(ISD::ANY_EXTEND, PairTy, Tmp2);
3200 Tmp2 = DAG.getNode(ISD::SHL, PairTy, Tmp2,
3201 DAG.getConstant(PairTy.getSizeInBits()/2,
3202 TLI.getShiftAmountTy()));
3203 Result = DAG.getNode(ISD::OR, PairTy, Tmp1, Tmp2);
3212 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
3213 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS
3215 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3216 case TargetLowering::Promote: assert(0 && "Cannot promote this yet!");
3217 case TargetLowering::Custom:
3220 case TargetLowering::Legal:
3221 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
3223 Tmp1 = TLI.LowerOperation(Result, DAG);
3224 if (Tmp1.getNode()) Result = Tmp1;
3227 case TargetLowering::Expand: {
3228 unsigned DivOpc= (Node->getOpcode() == ISD::UREM) ? ISD::UDIV : ISD::SDIV;
3229 bool isSigned = DivOpc == ISD::SDIV;
3230 MVT VT = Node->getValueType(0);
3232 // See if remainder can be lowered using two-result operations.
3233 SDVTList VTs = DAG.getVTList(VT, VT);
3234 if (Node->getOpcode() == ISD::SREM &&
3235 TLI.isOperationLegal(ISD::SDIVREM, VT)) {
3236 Result = SDValue(DAG.getNode(ISD::SDIVREM, VTs, Tmp1, Tmp2).getNode(), 1);
3239 if (Node->getOpcode() == ISD::UREM &&
3240 TLI.isOperationLegal(ISD::UDIVREM, VT)) {
3241 Result = SDValue(DAG.getNode(ISD::UDIVREM, VTs, Tmp1, Tmp2).getNode(), 1);
3245 if (VT.isInteger()) {
3246 if (TLI.getOperationAction(DivOpc, VT) ==
3247 TargetLowering::Legal) {
3249 Result = DAG.getNode(DivOpc, VT, Tmp1, Tmp2);
3250 Result = DAG.getNode(ISD::MUL, VT, Result, Tmp2);
3251 Result = DAG.getNode(ISD::SUB, VT, Tmp1, Result);
3252 } else if (VT.isVector()) {
3253 Result = LegalizeOp(UnrollVectorOp(Op));
3255 assert(VT == MVT::i32 &&
3256 "Cannot expand this binary operator!");
3257 RTLIB::Libcall LC = Node->getOpcode() == ISD::UREM
3258 ? RTLIB::UREM_I32 : RTLIB::SREM_I32;
3260 Result = ExpandLibCall(LC, Node, isSigned, Dummy);
3263 assert(VT.isFloatingPoint() &&
3264 "remainder op must have integer or floating-point type");
3265 if (VT.isVector()) {
3266 Result = LegalizeOp(UnrollVectorOp(Op));
3268 // Floating point mod -> fmod libcall.
3269 RTLIB::Libcall LC = GetFPLibCall(VT, RTLIB::REM_F32, RTLIB::REM_F64,
3270 RTLIB::REM_F80, RTLIB::REM_PPCF128);
3272 Result = ExpandLibCall(LC, Node, false/*sign irrelevant*/, Dummy);
3280 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
3281 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
3283 MVT VT = Node->getValueType(0);
3284 switch (TLI.getOperationAction(Node->getOpcode(), MVT::Other)) {
3285 default: assert(0 && "This action is not supported yet!");
3286 case TargetLowering::Custom:
3289 case TargetLowering::Legal:
3290 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
3291 Result = Result.getValue(0);
3292 Tmp1 = Result.getValue(1);
3295 Tmp2 = TLI.LowerOperation(Result, DAG);
3296 if (Tmp2.getNode()) {
3297 Result = LegalizeOp(Tmp2);
3298 Tmp1 = LegalizeOp(Tmp2.getValue(1));
3302 case TargetLowering::Expand: {
3303 const Value *V = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
3304 SDValue VAList = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp2, V, 0);
3305 // Increment the pointer, VAList, to the next vaarg
3306 Tmp3 = DAG.getNode(ISD::ADD, TLI.getPointerTy(), VAList,
3307 DAG.getConstant(VT.getSizeInBits()/8,
3308 TLI.getPointerTy()));
3309 // Store the incremented VAList to the legalized pointer
3310 Tmp3 = DAG.getStore(VAList.getValue(1), Tmp3, Tmp2, V, 0);
3311 // Load the actual argument out of the pointer VAList
3312 Result = DAG.getLoad(VT, Tmp3, VAList, NULL, 0);
3313 Tmp1 = LegalizeOp(Result.getValue(1));
3314 Result = LegalizeOp(Result);
3318 // Since VAARG produces two values, make sure to remember that we
3319 // legalized both of them.
3320 AddLegalizedOperand(SDValue(Node, 0), Result);
3321 AddLegalizedOperand(SDValue(Node, 1), Tmp1);
3322 return Op.getResNo() ? Tmp1 : Result;
3326 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
3327 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the dest pointer.
3328 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the source pointer.
3330 switch (TLI.getOperationAction(ISD::VACOPY, MVT::Other)) {
3331 default: assert(0 && "This action is not supported yet!");
3332 case TargetLowering::Custom:
3335 case TargetLowering::Legal:
3336 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3,
3337 Node->getOperand(3), Node->getOperand(4));
3339 Tmp1 = TLI.LowerOperation(Result, DAG);
3340 if (Tmp1.getNode()) Result = Tmp1;
3343 case TargetLowering::Expand:
3344 // This defaults to loading a pointer from the input and storing it to the
3345 // output, returning the chain.
3346 const Value *VD = cast<SrcValueSDNode>(Node->getOperand(3))->getValue();
3347 const Value *VS = cast<SrcValueSDNode>(Node->getOperand(4))->getValue();
3348 Tmp4 = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp3, VS, 0);
3349 Result = DAG.getStore(Tmp4.getValue(1), Tmp4, Tmp2, VD, 0);
3355 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
3356 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
3358 switch (TLI.getOperationAction(ISD::VAEND, MVT::Other)) {
3359 default: assert(0 && "This action is not supported yet!");
3360 case TargetLowering::Custom:
3363 case TargetLowering::Legal:
3364 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
3366 Tmp1 = TLI.LowerOperation(Tmp1, DAG);
3367 if (Tmp1.getNode()) Result = Tmp1;
3370 case TargetLowering::Expand:
3371 Result = Tmp1; // Default to a no-op, return the chain
3377 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
3378 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
3380 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
3382 switch (TLI.getOperationAction(ISD::VASTART, MVT::Other)) {
3383 default: assert(0 && "This action is not supported yet!");
3384 case TargetLowering::Legal: break;
3385 case TargetLowering::Custom:
3386 Tmp1 = TLI.LowerOperation(Result, DAG);
3387 if (Tmp1.getNode()) Result = Tmp1;
3394 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
3395 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS
3396 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
3397 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3399 assert(0 && "ROTL/ROTR legalize operation not supported");
3401 case TargetLowering::Legal:
3403 case TargetLowering::Custom:
3404 Tmp1 = TLI.LowerOperation(Result, DAG);
3405 if (Tmp1.getNode()) Result = Tmp1;
3407 case TargetLowering::Promote:
3408 assert(0 && "Do not know how to promote ROTL/ROTR");
3410 case TargetLowering::Expand:
3411 assert(0 && "Do not know how to expand ROTL/ROTR");
3417 Tmp1 = LegalizeOp(Node->getOperand(0)); // Op
3418 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3419 case TargetLowering::Custom:
3420 assert(0 && "Cannot custom legalize this yet!");
3421 case TargetLowering::Legal:
3422 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3424 case TargetLowering::Promote: {
3425 MVT OVT = Tmp1.getValueType();
3426 MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
3427 unsigned DiffBits = NVT.getSizeInBits() - OVT.getSizeInBits();
3429 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1);
3430 Tmp1 = DAG.getNode(ISD::BSWAP, NVT, Tmp1);
3431 Result = DAG.getNode(ISD::SRL, NVT, Tmp1,
3432 DAG.getConstant(DiffBits, TLI.getShiftAmountTy()));
3435 case TargetLowering::Expand:
3436 Result = ExpandBSWAP(Tmp1);
3444 Tmp1 = LegalizeOp(Node->getOperand(0)); // Op
3445 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3446 case TargetLowering::Custom:
3447 case TargetLowering::Legal:
3448 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3449 if (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0)) ==
3450 TargetLowering::Custom) {
3451 Tmp1 = TLI.LowerOperation(Result, DAG);
3452 if (Tmp1.getNode()) {
3457 case TargetLowering::Promote: {
3458 MVT OVT = Tmp1.getValueType();
3459 MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
3461 // Zero extend the argument.
3462 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1);
3463 // Perform the larger operation, then subtract if needed.
3464 Tmp1 = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1);
3465 switch (Node->getOpcode()) {
3470 //if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT)
3471 Tmp2 = DAG.getSetCC(TLI.getSetCCResultType(Tmp1), Tmp1,
3472 DAG.getConstant(NVT.getSizeInBits(), NVT),
3474 Result = DAG.getNode(ISD::SELECT, NVT, Tmp2,
3475 DAG.getConstant(OVT.getSizeInBits(), NVT), Tmp1);
3478 // Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT))
3479 Result = DAG.getNode(ISD::SUB, NVT, Tmp1,
3480 DAG.getConstant(NVT.getSizeInBits() -
3481 OVT.getSizeInBits(), NVT));
3486 case TargetLowering::Expand:
3487 Result = ExpandBitCount(Node->getOpcode(), Tmp1);
3507 case ISD::FNEARBYINT:
3508 Tmp1 = LegalizeOp(Node->getOperand(0));
3509 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3510 case TargetLowering::Promote:
3511 case TargetLowering::Custom:
3514 case TargetLowering::Legal:
3515 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3517 Tmp1 = TLI.LowerOperation(Result, DAG);
3518 if (Tmp1.getNode()) Result = Tmp1;
3521 case TargetLowering::Expand:
3522 switch (Node->getOpcode()) {
3523 default: assert(0 && "Unreachable!");
3525 // Expand Y = FNEG(X) -> Y = SUB -0.0, X
3526 Tmp2 = DAG.getConstantFP(-0.0, Node->getValueType(0));
3527 Result = DAG.getNode(ISD::FSUB, Node->getValueType(0), Tmp2, Tmp1);
3530 // Expand Y = FABS(X) -> Y = (X >u 0.0) ? X : fneg(X).
3531 MVT VT = Node->getValueType(0);
3532 Tmp2 = DAG.getConstantFP(0.0, VT);
3533 Tmp2 = DAG.getSetCC(TLI.getSetCCResultType(Tmp1), Tmp1, Tmp2,
3535 Tmp3 = DAG.getNode(ISD::FNEG, VT, Tmp1);
3536 Result = DAG.getNode(ISD::SELECT, VT, Tmp2, Tmp1, Tmp3);
3551 case ISD::FNEARBYINT: {
3552 MVT VT = Node->getValueType(0);
3554 // Expand unsupported unary vector operators by unrolling them.
3555 if (VT.isVector()) {
3556 Result = LegalizeOp(UnrollVectorOp(Op));
3560 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
3561 switch(Node->getOpcode()) {
3563 LC = GetFPLibCall(VT, RTLIB::SQRT_F32, RTLIB::SQRT_F64,
3564 RTLIB::SQRT_F80, RTLIB::SQRT_PPCF128);
3567 LC = GetFPLibCall(VT, RTLIB::SIN_F32, RTLIB::SIN_F64,
3568 RTLIB::SIN_F80, RTLIB::SIN_PPCF128);
3571 LC = GetFPLibCall(VT, RTLIB::COS_F32, RTLIB::COS_F64,
3572 RTLIB::COS_F80, RTLIB::COS_PPCF128);
3575 LC = GetFPLibCall(VT, RTLIB::LOG_F32, RTLIB::LOG_F64,
3576 RTLIB::LOG_F80, RTLIB::LOG_PPCF128);
3579 LC = GetFPLibCall(VT, RTLIB::LOG2_F32, RTLIB::LOG2_F64,
3580 RTLIB::LOG2_F80, RTLIB::LOG2_PPCF128);
3583 LC = GetFPLibCall(VT, RTLIB::LOG10_F32, RTLIB::LOG10_F64,
3584 RTLIB::LOG10_F80, RTLIB::LOG10_PPCF128);
3587 LC = GetFPLibCall(VT, RTLIB::EXP_F32, RTLIB::EXP_F64,
3588 RTLIB::EXP_F80, RTLIB::EXP_PPCF128);
3591 LC = GetFPLibCall(VT, RTLIB::EXP2_F32, RTLIB::EXP2_F64,
3592 RTLIB::EXP2_F80, RTLIB::EXP2_PPCF128);
3595 LC = GetFPLibCall(VT, RTLIB::TRUNC_F32, RTLIB::TRUNC_F64,
3596 RTLIB::TRUNC_F80, RTLIB::TRUNC_PPCF128);
3599 LC = GetFPLibCall(VT, RTLIB::FLOOR_F32, RTLIB::FLOOR_F64,
3600 RTLIB::FLOOR_F80, RTLIB::FLOOR_PPCF128);
3603 LC = GetFPLibCall(VT, RTLIB::CEIL_F32, RTLIB::CEIL_F64,
3604 RTLIB::CEIL_F80, RTLIB::CEIL_PPCF128);
3607 LC = GetFPLibCall(VT, RTLIB::RINT_F32, RTLIB::RINT_F64,
3608 RTLIB::RINT_F80, RTLIB::RINT_PPCF128);
3610 case ISD::FNEARBYINT:
3611 LC = GetFPLibCall(VT, RTLIB::NEARBYINT_F32, RTLIB::NEARBYINT_F64,
3612 RTLIB::NEARBYINT_F80, RTLIB::NEARBYINT_PPCF128);
3615 default: assert(0 && "Unreachable!");
3618 Result = ExpandLibCall(LC, Node, false/*sign irrelevant*/, Dummy);
3626 MVT VT = Node->getValueType(0);
3628 // Expand unsupported unary vector operators by unrolling them.
3629 if (VT.isVector()) {
3630 Result = LegalizeOp(UnrollVectorOp(Op));
3634 // We always lower FPOWI into a libcall. No target support for it yet.
3635 RTLIB::Libcall LC = GetFPLibCall(VT, RTLIB::POWI_F32, RTLIB::POWI_F64,
3636 RTLIB::POWI_F80, RTLIB::POWI_PPCF128);
3638 Result = ExpandLibCall(LC, Node, false/*sign irrelevant*/, Dummy);
3641 case ISD::BIT_CONVERT:
3642 if (!isTypeLegal(Node->getOperand(0).getValueType())) {
3643 Result = EmitStackConvert(Node->getOperand(0), Node->getValueType(0),
3644 Node->getValueType(0));
3645 } else if (Op.getOperand(0).getValueType().isVector()) {
3646 // The input has to be a vector type, we have to either scalarize it, pack
3647 // it, or convert it based on whether the input vector type is legal.
3648 SDNode *InVal = Node->getOperand(0).getNode();
3649 int InIx = Node->getOperand(0).getResNo();
3650 unsigned NumElems = InVal->getValueType(InIx).getVectorNumElements();
3651 MVT EVT = InVal->getValueType(InIx).getVectorElementType();
3653 // Figure out if there is a simple type corresponding to this Vector
3654 // type. If so, convert to the vector type.
3655 MVT TVT = MVT::getVectorVT(EVT, NumElems);
3656 if (TLI.isTypeLegal(TVT)) {
3657 // Turn this into a bit convert of the vector input.
3658 Result = DAG.getNode(ISD::BIT_CONVERT, Node->getValueType(0),
3659 LegalizeOp(Node->getOperand(0)));
3661 } else if (NumElems == 1) {
3662 // Turn this into a bit convert of the scalar input.
3663 Result = DAG.getNode(ISD::BIT_CONVERT, Node->getValueType(0),
3664 ScalarizeVectorOp(Node->getOperand(0)));
3667 // FIXME: UNIMP! Store then reload
3668 assert(0 && "Cast from unsupported vector type not implemented yet!");
3671 switch (TLI.getOperationAction(ISD::BIT_CONVERT,
3672 Node->getOperand(0).getValueType())) {
3673 default: assert(0 && "Unknown operation action!");
3674 case TargetLowering::Expand:
3675 Result = EmitStackConvert(Node->getOperand(0), Node->getValueType(0),
3676 Node->getValueType(0));
3678 case TargetLowering::Legal:
3679 Tmp1 = LegalizeOp(Node->getOperand(0));
3680 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3686 // Conversion operators. The source and destination have different types.
3687 case ISD::SINT_TO_FP:
3688 case ISD::UINT_TO_FP: {
3689 bool isSigned = Node->getOpcode() == ISD::SINT_TO_FP;
3690 Result = LegalizeINT_TO_FP(Result, isSigned,
3691 Node->getValueType(0), Node->getOperand(0));
3695 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3697 Tmp1 = LegalizeOp(Node->getOperand(0));
3698 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3701 ExpandOp(Node->getOperand(0), Tmp1, Tmp2);
3703 // Since the result is legal, we should just be able to truncate the low
3704 // part of the source.
3705 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), Tmp1);
3708 Result = PromoteOp(Node->getOperand(0));
3709 Result = DAG.getNode(ISD::TRUNCATE, Op.getValueType(), Result);
3714 case ISD::FP_TO_SINT:
3715 case ISD::FP_TO_UINT:
3716 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3718 Tmp1 = LegalizeOp(Node->getOperand(0));
3720 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))){
3721 default: assert(0 && "Unknown operation action!");
3722 case TargetLowering::Custom:
3725 case TargetLowering::Legal:
3726 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3728 Tmp1 = TLI.LowerOperation(Result, DAG);
3729 if (Tmp1.getNode()) Result = Tmp1;
3732 case TargetLowering::Promote:
3733 Result = PromoteLegalFP_TO_INT(Tmp1, Node->getValueType(0),
3734 Node->getOpcode() == ISD::FP_TO_SINT);
3736 case TargetLowering::Expand:
3737 if (Node->getOpcode() == ISD::FP_TO_UINT) {
3738 SDValue True, False;
3739 MVT VT = Node->getOperand(0).getValueType();
3740 MVT NVT = Node->getValueType(0);
3741 const uint64_t zero[] = {0, 0};
3742 APFloat apf = APFloat(APInt(VT.getSizeInBits(), 2, zero));
3743 APInt x = APInt::getSignBit(NVT.getSizeInBits());
3744 (void)apf.convertFromAPInt(x, false, APFloat::rmNearestTiesToEven);
3745 Tmp2 = DAG.getConstantFP(apf, VT);
3746 Tmp3 = DAG.getSetCC(TLI.getSetCCResultType(Node->getOperand(0)),
3747 Node->getOperand(0), Tmp2, ISD::SETLT);
3748 True = DAG.getNode(ISD::FP_TO_SINT, NVT, Node->getOperand(0));
3749 False = DAG.getNode(ISD::FP_TO_SINT, NVT,
3750 DAG.getNode(ISD::FSUB, VT, Node->getOperand(0),
3752 False = DAG.getNode(ISD::XOR, NVT, False,
3753 DAG.getConstant(x, NVT));
3754 Result = DAG.getNode(ISD::SELECT, NVT, Tmp3, True, False);
3757 assert(0 && "Do not know how to expand FP_TO_SINT yet!");
3763 MVT VT = Op.getValueType();
3764 MVT OVT = Node->getOperand(0).getValueType();
3765 // Convert ppcf128 to i32
3766 if (OVT == MVT::ppcf128 && VT == MVT::i32) {
3767 if (Node->getOpcode() == ISD::FP_TO_SINT) {
3768 Result = DAG.getNode(ISD::FP_ROUND_INREG, MVT::ppcf128,
3769 Node->getOperand(0), DAG.getValueType(MVT::f64));
3770 Result = DAG.getNode(ISD::FP_ROUND, MVT::f64, Result,
3771 DAG.getIntPtrConstant(1));
3772 Result = DAG.getNode(ISD::FP_TO_SINT, VT, Result);
3774 const uint64_t TwoE31[] = {0x41e0000000000000LL, 0};
3775 APFloat apf = APFloat(APInt(128, 2, TwoE31));
3776 Tmp2 = DAG.getConstantFP(apf, OVT);
3777 // X>=2^31 ? (int)(X-2^31)+0x80000000 : (int)X
3778 // FIXME: generated code sucks.
3779 Result = DAG.getNode(ISD::SELECT_CC, VT, Node->getOperand(0), Tmp2,
3780 DAG.getNode(ISD::ADD, MVT::i32,
3781 DAG.getNode(ISD::FP_TO_SINT, VT,
3782 DAG.getNode(ISD::FSUB, OVT,
3783 Node->getOperand(0), Tmp2)),
3784 DAG.getConstant(0x80000000, MVT::i32)),
3785 DAG.getNode(ISD::FP_TO_SINT, VT,
3786 Node->getOperand(0)),
3787 DAG.getCondCode(ISD::SETGE));
3791 // Convert f32 / f64 to i32 / i64 / i128.
3792 RTLIB::Libcall LC = (Node->getOpcode() == ISD::FP_TO_SINT) ?
3793 RTLIB::getFPTOSINT(OVT, VT) : RTLIB::getFPTOUINT(OVT, VT);
3794 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpectd fp-to-int conversion!");
3796 Result = ExpandLibCall(LC, Node, false/*sign irrelevant*/, Dummy);
3800 Tmp1 = PromoteOp(Node->getOperand(0));
3801 Result = DAG.UpdateNodeOperands(Result, LegalizeOp(Tmp1));
3802 Result = LegalizeOp(Result);
3807 case ISD::FP_EXTEND: {
3808 MVT DstVT = Op.getValueType();
3809 MVT SrcVT = Op.getOperand(0).getValueType();
3810 if (TLI.getConvertAction(SrcVT, DstVT) == TargetLowering::Expand) {
3811 // The only other way we can lower this is to turn it into a STORE,
3812 // LOAD pair, targetting a temporary location (a stack slot).
3813 Result = EmitStackConvert(Node->getOperand(0), SrcVT, DstVT);
3816 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3817 case Expand: assert(0 && "Shouldn't need to expand other operators here!");
3819 Tmp1 = LegalizeOp(Node->getOperand(0));
3820 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3823 Tmp1 = PromoteOp(Node->getOperand(0));
3824 Result = DAG.getNode(ISD::FP_EXTEND, Op.getValueType(), Tmp1);
3829 case ISD::FP_ROUND: {
3830 MVT DstVT = Op.getValueType();
3831 MVT SrcVT = Op.getOperand(0).getValueType();
3832 if (TLI.getConvertAction(SrcVT, DstVT) == TargetLowering::Expand) {
3833 if (SrcVT == MVT::ppcf128) {
3835 ExpandOp(Node->getOperand(0), Lo, Result);
3836 // Round it the rest of the way (e.g. to f32) if needed.
3837 if (DstVT!=MVT::f64)
3838 Result = DAG.getNode(ISD::FP_ROUND, DstVT, Result, Op.getOperand(1));
3841 // The only other way we can lower this is to turn it into a STORE,
3842 // LOAD pair, targetting a temporary location (a stack slot).
3843 Result = EmitStackConvert(Node->getOperand(0), DstVT, DstVT);
3846 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3847 case Expand: assert(0 && "Shouldn't need to expand other operators here!");
3849 Tmp1 = LegalizeOp(Node->getOperand(0));
3850 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
3853 Tmp1 = PromoteOp(Node->getOperand(0));
3854 Result = DAG.getNode(ISD::FP_ROUND, Op.getValueType(), Tmp1,
3855 Node->getOperand(1));
3860 case ISD::ANY_EXTEND:
3861 case ISD::ZERO_EXTEND:
3862 case ISD::SIGN_EXTEND:
3863 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3864 case Expand: assert(0 && "Shouldn't need to expand other operators here!");
3866 Tmp1 = LegalizeOp(Node->getOperand(0));
3867 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3868 if (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0)) ==
3869 TargetLowering::Custom) {
3870 Tmp1 = TLI.LowerOperation(Result, DAG);
3871 if (Tmp1.getNode()) Result = Tmp1;
3875 switch (Node->getOpcode()) {
3876 case ISD::ANY_EXTEND:
3877 Tmp1 = PromoteOp(Node->getOperand(0));
3878 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Tmp1);
3880 case ISD::ZERO_EXTEND:
3881 Result = PromoteOp(Node->getOperand(0));
3882 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Result);
3883 Result = DAG.getZeroExtendInReg(Result,
3884 Node->getOperand(0).getValueType());
3886 case ISD::SIGN_EXTEND:
3887 Result = PromoteOp(Node->getOperand(0));
3888 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Result);
3889 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(),
3891 DAG.getValueType(Node->getOperand(0).getValueType()));
3896 case ISD::FP_ROUND_INREG:
3897 case ISD::SIGN_EXTEND_INREG: {
3898 Tmp1 = LegalizeOp(Node->getOperand(0));
3899 MVT ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT();
3901 // If this operation is not supported, convert it to a shl/shr or load/store
3903 switch (TLI.getOperationAction(Node->getOpcode(), ExtraVT)) {
3904 default: assert(0 && "This action not supported for this op yet!");
3905 case TargetLowering::Legal:
3906 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
3908 case TargetLowering::Expand:
3909 // If this is an integer extend and shifts are supported, do that.
3910 if (Node->getOpcode() == ISD::SIGN_EXTEND_INREG) {
3911 // NOTE: we could fall back on load/store here too for targets without
3912 // SAR. However, it is doubtful that any exist.
3913 unsigned BitsDiff = Node->getValueType(0).getSizeInBits() -
3914 ExtraVT.getSizeInBits();
3915 SDValue ShiftCst = DAG.getConstant(BitsDiff, TLI.getShiftAmountTy());
3916 Result = DAG.getNode(ISD::SHL, Node->getValueType(0),
3917 Node->getOperand(0), ShiftCst);
3918 Result = DAG.getNode(ISD::SRA, Node->getValueType(0),
3920 } else if (Node->getOpcode() == ISD::FP_ROUND_INREG) {
3921 // The only way we can lower this is to turn it into a TRUNCSTORE,
3922 // EXTLOAD pair, targetting a temporary location (a stack slot).
3924 // NOTE: there is a choice here between constantly creating new stack
3925 // slots and always reusing the same one. We currently always create
3926 // new ones, as reuse may inhibit scheduling.
3927 Result = EmitStackConvert(Node->getOperand(0), ExtraVT,
3928 Node->getValueType(0));
3930 assert(0 && "Unknown op");
3936 case ISD::TRAMPOLINE: {
3938 for (unsigned i = 0; i != 6; ++i)
3939 Ops[i] = LegalizeOp(Node->getOperand(i));
3940 Result = DAG.UpdateNodeOperands(Result, Ops, 6);
3941 // The only option for this node is to custom lower it.
3942 Result = TLI.LowerOperation(Result, DAG);
3943 assert(Result.getNode() && "Should always custom lower!");
3945 // Since trampoline produces two values, make sure to remember that we
3946 // legalized both of them.
3947 Tmp1 = LegalizeOp(Result.getValue(1));
3948 Result = LegalizeOp(Result);
3949 AddLegalizedOperand(SDValue(Node, 0), Result);
3950 AddLegalizedOperand(SDValue(Node, 1), Tmp1);
3951 return Op.getResNo() ? Tmp1 : Result;
3953 case ISD::FLT_ROUNDS_: {
3954 MVT VT = Node->getValueType(0);
3955 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
3956 default: assert(0 && "This action not supported for this op yet!");
3957 case TargetLowering::Custom:
3958 Result = TLI.LowerOperation(Op, DAG);
3959 if (Result.getNode()) break;
3961 case TargetLowering::Legal:
3962 // If this operation is not supported, lower it to constant 1
3963 Result = DAG.getConstant(1, VT);
3969 MVT VT = Node->getValueType(0);
3970 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
3971 default: assert(0 && "This action not supported for this op yet!");
3972 case TargetLowering::Legal:
3973 Tmp1 = LegalizeOp(Node->getOperand(0));
3974 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3976 case TargetLowering::Custom:
3977 Result = TLI.LowerOperation(Op, DAG);
3978 if (Result.getNode()) break;
3980 case TargetLowering::Expand:
3981 // If this operation is not supported, lower it to 'abort()' call
3982 Tmp1 = LegalizeOp(Node->getOperand(0));
3983 TargetLowering::ArgListTy Args;
3984 std::pair<SDValue,SDValue> CallResult =
3985 TLI.LowerCallTo(Tmp1, Type::VoidTy,
3986 false, false, false, false, CallingConv::C, false,
3987 DAG.getExternalSymbol("abort", TLI.getPointerTy()),
3989 Result = CallResult.second;
3996 assert(Result.getValueType() == Op.getValueType() &&
3997 "Bad legalization!");
3999 // Make sure that the generated code is itself legal.
4001 Result = LegalizeOp(Result);
4003 // Note that LegalizeOp may be reentered even from single-use nodes, which
4004 // means that we always must cache transformed nodes.
4005 AddLegalizedOperand(Op, Result);
4009 /// PromoteOp - Given an operation that produces a value in an invalid type,
4010 /// promote it to compute the value into a larger type. The produced value will
4011 /// have the correct bits for the low portion of the register, but no guarantee
4012 /// is made about the top bits: it may be zero, sign-extended, or garbage.
4013 SDValue SelectionDAGLegalize::PromoteOp(SDValue Op) {
4014 MVT VT = Op.getValueType();
4015 MVT NVT = TLI.getTypeToTransformTo(VT);
4016 assert(getTypeAction(VT) == Promote &&
4017 "Caller should expand or legalize operands that are not promotable!");
4018 assert(NVT.bitsGT(VT) && NVT.isInteger() == VT.isInteger() &&
4019 "Cannot promote to smaller type!");
4021 SDValue Tmp1, Tmp2, Tmp3;
4023 SDNode *Node = Op.getNode();
4025 DenseMap<SDValue, SDValue>::iterator I = PromotedNodes.find(Op);
4026 if (I != PromotedNodes.end()) return I->second;
4028 switch (Node->getOpcode()) {
4029 case ISD::CopyFromReg:
4030 assert(0 && "CopyFromReg must be legal!");
4033 cerr << "NODE: "; Node->dump(&DAG); cerr << "\n";
4035 assert(0 && "Do not know how to promote this operator!");
4038 Result = DAG.getNode(ISD::UNDEF, NVT);
4042 Result = DAG.getNode(ISD::SIGN_EXTEND, NVT, Op);
4044 Result = DAG.getNode(ISD::ZERO_EXTEND, NVT, Op);
4045 assert(isa<ConstantSDNode>(Result) && "Didn't constant fold zext?");
4047 case ISD::ConstantFP:
4048 Result = DAG.getNode(ISD::FP_EXTEND, NVT, Op);
4049 assert(isa<ConstantFPSDNode>(Result) && "Didn't constant fold fp_extend?");
4053 assert(isTypeLegal(TLI.getSetCCResultType(Node->getOperand(0)))
4054 && "SetCC type is not legal??");
4055 Result = DAG.getNode(ISD::SETCC,
4056 TLI.getSetCCResultType(Node->getOperand(0)),
4057 Node->getOperand(0), Node->getOperand(1),
4058 Node->getOperand(2));
4062 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4064 Result = LegalizeOp(Node->getOperand(0));
4065 assert(Result.getValueType().bitsGE(NVT) &&
4066 "This truncation doesn't make sense!");
4067 if (Result.getValueType().bitsGT(NVT)) // Truncate to NVT instead of VT
4068 Result = DAG.getNode(ISD::TRUNCATE, NVT, Result);
4071 // The truncation is not required, because we don't guarantee anything
4072 // about high bits anyway.
4073 Result = PromoteOp(Node->getOperand(0));
4076 ExpandOp(Node->getOperand(0), Tmp1, Tmp2);
4077 // Truncate the low part of the expanded value to the result type
4078 Result = DAG.getNode(ISD::TRUNCATE, NVT, Tmp1);
4081 case ISD::SIGN_EXTEND:
4082 case ISD::ZERO_EXTEND:
4083 case ISD::ANY_EXTEND:
4084 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4085 case Expand: assert(0 && "BUG: Smaller reg should have been promoted!");
4087 // Input is legal? Just do extend all the way to the larger type.
4088 Result = DAG.getNode(Node->getOpcode(), NVT, Node->getOperand(0));
4091 // Promote the reg if it's smaller.
4092 Result = PromoteOp(Node->getOperand(0));
4093 // The high bits are not guaranteed to be anything. Insert an extend.
4094 if (Node->getOpcode() == ISD::SIGN_EXTEND)
4095 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Result,
4096 DAG.getValueType(Node->getOperand(0).getValueType()));
4097 else if (Node->getOpcode() == ISD::ZERO_EXTEND)
4098 Result = DAG.getZeroExtendInReg(Result,
4099 Node->getOperand(0).getValueType());
4103 case ISD::BIT_CONVERT:
4104 Result = EmitStackConvert(Node->getOperand(0), Node->getValueType(0),
4105 Node->getValueType(0));
4106 Result = PromoteOp(Result);
4109 case ISD::FP_EXTEND:
4110 assert(0 && "Case not implemented. Dynamically dead with 2 FP types!");
4112 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4113 case Expand: assert(0 && "BUG: Cannot expand FP regs!");
4114 case Promote: assert(0 && "Unreachable with 2 FP types!");
4116 if (Node->getConstantOperandVal(1) == 0) {
4117 // Input is legal? Do an FP_ROUND_INREG.
4118 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Node->getOperand(0),
4119 DAG.getValueType(VT));
4121 // Just remove the truncate, it isn't affecting the value.
4122 Result = DAG.getNode(ISD::FP_ROUND, NVT, Node->getOperand(0),
4123 Node->getOperand(1));
4128 case ISD::SINT_TO_FP:
4129 case ISD::UINT_TO_FP:
4130 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4132 // No extra round required here.
4133 Result = DAG.getNode(Node->getOpcode(), NVT, Node->getOperand(0));
4137 Result = PromoteOp(Node->getOperand(0));
4138 if (Node->getOpcode() == ISD::SINT_TO_FP)
4139 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(),
4141 DAG.getValueType(Node->getOperand(0).getValueType()));
4143 Result = DAG.getZeroExtendInReg(Result,
4144 Node->getOperand(0).getValueType());
4145 // No extra round required here.
4146 Result = DAG.getNode(Node->getOpcode(), NVT, Result);
4149 Result = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP, NVT,
4150 Node->getOperand(0));
4151 // Round if we cannot tolerate excess precision.
4152 if (NoExcessFPPrecision)
4153 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
4154 DAG.getValueType(VT));
4159 case ISD::SIGN_EXTEND_INREG:
4160 Result = PromoteOp(Node->getOperand(0));
4161 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Result,
4162 Node->getOperand(1));
4164 case ISD::FP_TO_SINT:
4165 case ISD::FP_TO_UINT:
4166 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4169 Tmp1 = Node->getOperand(0);
4172 // The input result is prerounded, so we don't have to do anything
4174 Tmp1 = PromoteOp(Node->getOperand(0));
4177 // If we're promoting a UINT to a larger size, check to see if the new node
4178 // will be legal. If it isn't, check to see if FP_TO_SINT is legal, since
4179 // we can use that instead. This allows us to generate better code for
4180 // FP_TO_UINT for small destination sizes on targets where FP_TO_UINT is not
4181 // legal, such as PowerPC.
4182 if (Node->getOpcode() == ISD::FP_TO_UINT &&
4183 !TLI.isOperationLegal(ISD::FP_TO_UINT, NVT) &&
4184 (TLI.isOperationLegal(ISD::FP_TO_SINT, NVT) ||
4185 TLI.getOperationAction(ISD::FP_TO_SINT, NVT)==TargetLowering::Custom)){
4186 Result = DAG.getNode(ISD::FP_TO_SINT, NVT, Tmp1);
4188 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
4194 Tmp1 = PromoteOp(Node->getOperand(0));
4195 assert(Tmp1.getValueType() == NVT);
4196 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
4197 // NOTE: we do not have to do any extra rounding here for
4198 // NoExcessFPPrecision, because we know the input will have the appropriate
4199 // precision, and these operations don't modify precision at all.
4214 case ISD::FNEARBYINT:
4215 Tmp1 = PromoteOp(Node->getOperand(0));
4216 assert(Tmp1.getValueType() == NVT);
4217 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
4218 if (NoExcessFPPrecision)
4219 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
4220 DAG.getValueType(VT));
4225 // Promote f32 pow(i) to f64 pow(i). Note that this could insert a libcall
4226 // directly as well, which may be better.
4227 Tmp1 = PromoteOp(Node->getOperand(0));
4228 Tmp2 = Node->getOperand(1);
4229 if (Node->getOpcode() == ISD::FPOW)
4230 Tmp2 = PromoteOp(Tmp2);
4231 assert(Tmp1.getValueType() == NVT);
4232 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
4233 if (NoExcessFPPrecision)
4234 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
4235 DAG.getValueType(VT));
4239 case ISD::ATOMIC_CMP_SWAP_8:
4240 case ISD::ATOMIC_CMP_SWAP_16:
4241 case ISD::ATOMIC_CMP_SWAP_32:
4242 case ISD::ATOMIC_CMP_SWAP_64: {
4243 AtomicSDNode* AtomNode = cast<AtomicSDNode>(Node);
4244 Tmp2 = PromoteOp(Node->getOperand(2));
4245 Tmp3 = PromoteOp(Node->getOperand(3));
4246 Result = DAG.getAtomic(Node->getOpcode(), AtomNode->getChain(),
4247 AtomNode->getBasePtr(), Tmp2, Tmp3,
4248 AtomNode->getSrcValue(),
4249 AtomNode->getAlignment());
4250 // Remember that we legalized the chain.
4251 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
4254 case ISD::ATOMIC_LOAD_ADD_8:
4255 case ISD::ATOMIC_LOAD_SUB_8:
4256 case ISD::ATOMIC_LOAD_AND_8:
4257 case ISD::ATOMIC_LOAD_OR_8:
4258 case ISD::ATOMIC_LOAD_XOR_8:
4259 case ISD::ATOMIC_LOAD_NAND_8:
4260 case ISD::ATOMIC_LOAD_MIN_8:
4261 case ISD::ATOMIC_LOAD_MAX_8:
4262 case ISD::ATOMIC_LOAD_UMIN_8:
4263 case ISD::ATOMIC_LOAD_UMAX_8:
4264 case ISD::ATOMIC_SWAP_8:
4265 case ISD::ATOMIC_LOAD_ADD_16:
4266 case ISD::ATOMIC_LOAD_SUB_16:
4267 case ISD::ATOMIC_LOAD_AND_16:
4268 case ISD::ATOMIC_LOAD_OR_16:
4269 case ISD::ATOMIC_LOAD_XOR_16:
4270 case ISD::ATOMIC_LOAD_NAND_16:
4271 case ISD::ATOMIC_LOAD_MIN_16:
4272 case ISD::ATOMIC_LOAD_MAX_16:
4273 case ISD::ATOMIC_LOAD_UMIN_16:
4274 case ISD::ATOMIC_LOAD_UMAX_16:
4275 case ISD::ATOMIC_SWAP_16:
4276 case ISD::ATOMIC_LOAD_ADD_32:
4277 case ISD::ATOMIC_LOAD_SUB_32:
4278 case ISD::ATOMIC_LOAD_AND_32:
4279 case ISD::ATOMIC_LOAD_OR_32:
4280 case ISD::ATOMIC_LOAD_XOR_32:
4281 case ISD::ATOMIC_LOAD_NAND_32:
4282 case ISD::ATOMIC_LOAD_MIN_32:
4283 case ISD::ATOMIC_LOAD_MAX_32:
4284 case ISD::ATOMIC_LOAD_UMIN_32:
4285 case ISD::ATOMIC_LOAD_UMAX_32:
4286 case ISD::ATOMIC_SWAP_32:
4287 case ISD::ATOMIC_LOAD_ADD_64:
4288 case ISD::ATOMIC_LOAD_SUB_64:
4289 case ISD::ATOMIC_LOAD_AND_64:
4290 case ISD::ATOMIC_LOAD_OR_64:
4291 case ISD::ATOMIC_LOAD_XOR_64:
4292 case ISD::ATOMIC_LOAD_NAND_64:
4293 case ISD::ATOMIC_LOAD_MIN_64:
4294 case ISD::ATOMIC_LOAD_MAX_64:
4295 case ISD::ATOMIC_LOAD_UMIN_64:
4296 case ISD::ATOMIC_LOAD_UMAX_64:
4297 case ISD::ATOMIC_SWAP_64: {
4298 AtomicSDNode* AtomNode = cast<AtomicSDNode>(Node);
4299 Tmp2 = PromoteOp(Node->getOperand(2));
4300 Result = DAG.getAtomic(Node->getOpcode(), AtomNode->getChain(),
4301 AtomNode->getBasePtr(), Tmp2,
4302 AtomNode->getSrcValue(),
4303 AtomNode->getAlignment());
4304 // Remember that we legalized the chain.
4305 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
4315 // The input may have strange things in the top bits of the registers, but
4316 // these operations don't care. They may have weird bits going out, but
4317 // that too is okay if they are integer operations.
4318 Tmp1 = PromoteOp(Node->getOperand(0));
4319 Tmp2 = PromoteOp(Node->getOperand(1));
4320 assert(Tmp1.getValueType() == NVT && Tmp2.getValueType() == NVT);
4321 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
4326 Tmp1 = PromoteOp(Node->getOperand(0));
4327 Tmp2 = PromoteOp(Node->getOperand(1));
4328 assert(Tmp1.getValueType() == NVT && Tmp2.getValueType() == NVT);
4329 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
4331 // Floating point operations will give excess precision that we may not be
4332 // able to tolerate. If we DO allow excess precision, just leave it,
4333 // otherwise excise it.
4334 // FIXME: Why would we need to round FP ops more than integer ones?
4335 // Is Round(Add(Add(A,B),C)) != Round(Add(Round(Add(A,B)), C))
4336 if (NoExcessFPPrecision)
4337 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
4338 DAG.getValueType(VT));
4343 // These operators require that their input be sign extended.
4344 Tmp1 = PromoteOp(Node->getOperand(0));
4345 Tmp2 = PromoteOp(Node->getOperand(1));
4346 if (NVT.isInteger()) {
4347 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1,
4348 DAG.getValueType(VT));
4349 Tmp2 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp2,
4350 DAG.getValueType(VT));
4352 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
4354 // Perform FP_ROUND: this is probably overly pessimistic.
4355 if (NVT.isFloatingPoint() && NoExcessFPPrecision)
4356 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
4357 DAG.getValueType(VT));
4361 case ISD::FCOPYSIGN:
4362 // These operators require that their input be fp extended.
4363 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4364 case Expand: assert(0 && "not implemented");
4365 case Legal: Tmp1 = LegalizeOp(Node->getOperand(0)); break;
4366 case Promote: Tmp1 = PromoteOp(Node->getOperand(0)); break;
4368 switch (getTypeAction(Node->getOperand(1).getValueType())) {
4369 case Expand: assert(0 && "not implemented");
4370 case Legal: Tmp2 = LegalizeOp(Node->getOperand(1)); break;
4371 case Promote: Tmp2 = PromoteOp(Node->getOperand(1)); break;
4373 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
4375 // Perform FP_ROUND: this is probably overly pessimistic.
4376 if (NoExcessFPPrecision && Node->getOpcode() != ISD::FCOPYSIGN)
4377 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
4378 DAG.getValueType(VT));
4383 // These operators require that their input be zero extended.
4384 Tmp1 = PromoteOp(Node->getOperand(0));
4385 Tmp2 = PromoteOp(Node->getOperand(1));
4386 assert(NVT.isInteger() && "Operators don't apply to FP!");
4387 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT);
4388 Tmp2 = DAG.getZeroExtendInReg(Tmp2, VT);
4389 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
4393 Tmp1 = PromoteOp(Node->getOperand(0));
4394 Result = DAG.getNode(ISD::SHL, NVT, Tmp1, Node->getOperand(1));
4397 // The input value must be properly sign extended.
4398 Tmp1 = PromoteOp(Node->getOperand(0));
4399 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1,
4400 DAG.getValueType(VT));
4401 Result = DAG.getNode(ISD::SRA, NVT, Tmp1, Node->getOperand(1));
4404 // The input value must be properly zero extended.
4405 Tmp1 = PromoteOp(Node->getOperand(0));
4406 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT);
4407 Result = DAG.getNode(ISD::SRL, NVT, Tmp1, Node->getOperand(1));
4411 Tmp1 = Node->getOperand(0); // Get the chain.
4412 Tmp2 = Node->getOperand(1); // Get the pointer.
4413 if (TLI.getOperationAction(ISD::VAARG, VT) == TargetLowering::Custom) {
4414 Tmp3 = DAG.getVAArg(VT, Tmp1, Tmp2, Node->getOperand(2));
4415 Result = TLI.LowerOperation(Tmp3, DAG);
4417 const Value *V = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
4418 SDValue VAList = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp2, V, 0);
4419 // Increment the pointer, VAList, to the next vaarg
4420 Tmp3 = DAG.getNode(ISD::ADD, TLI.getPointerTy(), VAList,
4421 DAG.getConstant(VT.getSizeInBits()/8,
4422 TLI.getPointerTy()));
4423 // Store the incremented VAList to the legalized pointer
4424 Tmp3 = DAG.getStore(VAList.getValue(1), Tmp3, Tmp2, V, 0);
4425 // Load the actual argument out of the pointer VAList
4426 Result = DAG.getExtLoad(ISD::EXTLOAD, NVT, Tmp3, VAList, NULL, 0, VT);
4428 // Remember that we legalized the chain.
4429 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
4433 LoadSDNode *LD = cast<LoadSDNode>(Node);
4434 ISD::LoadExtType ExtType = ISD::isNON_EXTLoad(Node)
4435 ? ISD::EXTLOAD : LD->getExtensionType();
4436 Result = DAG.getExtLoad(ExtType, NVT,
4437 LD->getChain(), LD->getBasePtr(),
4438 LD->getSrcValue(), LD->getSrcValueOffset(),
4441 LD->getAlignment());
4442 // Remember that we legalized the chain.
4443 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
4447 Tmp2 = PromoteOp(Node->getOperand(1)); // Legalize the op0
4448 Tmp3 = PromoteOp(Node->getOperand(2)); // Legalize the op1
4450 MVT VT2 = Tmp2.getValueType();
4451 assert(VT2 == Tmp3.getValueType()
4452 && "PromoteOp SELECT: Operands 2 and 3 ValueTypes don't match");
4453 // Ensure that the resulting node is at least the same size as the operands'
4454 // value types, because we cannot assume that TLI.getSetCCValueType() is
4456 Result = DAG.getNode(ISD::SELECT, VT2, Node->getOperand(0), Tmp2, Tmp3);
4459 case ISD::SELECT_CC:
4460 Tmp2 = PromoteOp(Node->getOperand(2)); // True
4461 Tmp3 = PromoteOp(Node->getOperand(3)); // False
4462 Result = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0),
4463 Node->getOperand(1), Tmp2, Tmp3, Node->getOperand(4));
4466 Tmp1 = Node->getOperand(0);
4467 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1);
4468 Tmp1 = DAG.getNode(ISD::BSWAP, NVT, Tmp1);
4469 Result = DAG.getNode(ISD::SRL, NVT, Tmp1,
4470 DAG.getConstant(NVT.getSizeInBits() -
4472 TLI.getShiftAmountTy()));
4477 // Zero extend the argument
4478 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Node->getOperand(0));
4479 // Perform the larger operation, then subtract if needed.
4480 Tmp1 = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
4481 switch(Node->getOpcode()) {
4486 // if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT)
4487 Tmp2 = DAG.getSetCC(TLI.getSetCCResultType(Tmp1), Tmp1,
4488 DAG.getConstant(NVT.getSizeInBits(), NVT),
4490 Result = DAG.getNode(ISD::SELECT, NVT, Tmp2,
4491 DAG.getConstant(VT.getSizeInBits(), NVT), Tmp1);
4494 //Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT))
4495 Result = DAG.getNode(ISD::SUB, NVT, Tmp1,
4496 DAG.getConstant(NVT.getSizeInBits() -
4497 VT.getSizeInBits(), NVT));
4501 case ISD::EXTRACT_SUBVECTOR:
4502 Result = PromoteOp(ExpandEXTRACT_SUBVECTOR(Op));
4504 case ISD::EXTRACT_VECTOR_ELT:
4505 Result = PromoteOp(ExpandEXTRACT_VECTOR_ELT(Op));
4509 assert(Result.getNode() && "Didn't set a result!");
4511 // Make sure the result is itself legal.
4512 Result = LegalizeOp(Result);
4514 // Remember that we promoted this!
4515 AddPromotedOperand(Op, Result);
4519 /// ExpandEXTRACT_VECTOR_ELT - Expand an EXTRACT_VECTOR_ELT operation into
4520 /// a legal EXTRACT_VECTOR_ELT operation, scalar code, or memory traffic,
4521 /// based on the vector type. The return type of this matches the element type
4522 /// of the vector, which may not be legal for the target.
4523 SDValue SelectionDAGLegalize::ExpandEXTRACT_VECTOR_ELT(SDValue Op) {
4524 // We know that operand #0 is the Vec vector. If the index is a constant
4525 // or if the invec is a supported hardware type, we can use it. Otherwise,
4526 // lower to a store then an indexed load.
4527 SDValue Vec = Op.getOperand(0);
4528 SDValue Idx = Op.getOperand(1);
4530 MVT TVT = Vec.getValueType();
4531 unsigned NumElems = TVT.getVectorNumElements();
4533 switch (TLI.getOperationAction(ISD::EXTRACT_VECTOR_ELT, TVT)) {
4534 default: assert(0 && "This action is not supported yet!");
4535 case TargetLowering::Custom: {
4536 Vec = LegalizeOp(Vec);
4537 Op = DAG.UpdateNodeOperands(Op, Vec, Idx);
4538 SDValue Tmp3 = TLI.LowerOperation(Op, DAG);
4543 case TargetLowering::Legal:
4544 if (isTypeLegal(TVT)) {
4545 Vec = LegalizeOp(Vec);
4546 Op = DAG.UpdateNodeOperands(Op, Vec, Idx);
4550 case TargetLowering::Expand:
4554 if (NumElems == 1) {
4555 // This must be an access of the only element. Return it.
4556 Op = ScalarizeVectorOp(Vec);
4557 } else if (!TLI.isTypeLegal(TVT) && isa<ConstantSDNode>(Idx)) {
4558 unsigned NumLoElts = 1 << Log2_32(NumElems-1);
4559 ConstantSDNode *CIdx = cast<ConstantSDNode>(Idx);
4561 SplitVectorOp(Vec, Lo, Hi);
4562 if (CIdx->getZExtValue() < NumLoElts) {
4566 Idx = DAG.getConstant(CIdx->getZExtValue() - NumLoElts,
4567 Idx.getValueType());
4570 // It's now an extract from the appropriate high or low part. Recurse.
4571 Op = DAG.UpdateNodeOperands(Op, Vec, Idx);
4572 Op = ExpandEXTRACT_VECTOR_ELT(Op);
4574 // Store the value to a temporary stack slot, then LOAD the scalar
4575 // element back out.
4576 SDValue StackPtr = DAG.CreateStackTemporary(Vec.getValueType());
4577 SDValue Ch = DAG.getStore(DAG.getEntryNode(), Vec, StackPtr, NULL, 0);
4579 // Add the offset to the index.
4580 unsigned EltSize = Op.getValueType().getSizeInBits()/8;
4581 Idx = DAG.getNode(ISD::MUL, Idx.getValueType(), Idx,
4582 DAG.getConstant(EltSize, Idx.getValueType()));
4584 if (Idx.getValueType().bitsGT(TLI.getPointerTy()))
4585 Idx = DAG.getNode(ISD::TRUNCATE, TLI.getPointerTy(), Idx);
4587 Idx = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(), Idx);
4589 StackPtr = DAG.getNode(ISD::ADD, Idx.getValueType(), Idx, StackPtr);
4591 Op = DAG.getLoad(Op.getValueType(), Ch, StackPtr, NULL, 0);
4596 /// ExpandEXTRACT_SUBVECTOR - Expand a EXTRACT_SUBVECTOR operation. For now
4597 /// we assume the operation can be split if it is not already legal.
4598 SDValue SelectionDAGLegalize::ExpandEXTRACT_SUBVECTOR(SDValue Op) {
4599 // We know that operand #0 is the Vec vector. For now we assume the index
4600 // is a constant and that the extracted result is a supported hardware type.
4601 SDValue Vec = Op.getOperand(0);
4602 SDValue Idx = LegalizeOp(Op.getOperand(1));
4604 unsigned NumElems = Vec.getValueType().getVectorNumElements();
4606 if (NumElems == Op.getValueType().getVectorNumElements()) {
4607 // This must be an access of the desired vector length. Return it.
4611 ConstantSDNode *CIdx = cast<ConstantSDNode>(Idx);
4613 SplitVectorOp(Vec, Lo, Hi);
4614 if (CIdx->getZExtValue() < NumElems/2) {
4618 Idx = DAG.getConstant(CIdx->getZExtValue() - NumElems/2,
4619 Idx.getValueType());
4622 // It's now an extract from the appropriate high or low part. Recurse.
4623 Op = DAG.UpdateNodeOperands(Op, Vec, Idx);
4624 return ExpandEXTRACT_SUBVECTOR(Op);
4627 /// LegalizeSetCCOperands - Attempts to create a legal LHS and RHS for a SETCC
4628 /// with condition CC on the current target. This usually involves legalizing
4629 /// or promoting the arguments. In the case where LHS and RHS must be expanded,
4630 /// there may be no choice but to create a new SetCC node to represent the
4631 /// legalized value of setcc lhs, rhs. In this case, the value is returned in
4632 /// LHS, and the SDValue returned in RHS has a nil SDNode value.
4633 void SelectionDAGLegalize::LegalizeSetCCOperands(SDValue &LHS,
4636 SDValue Tmp1, Tmp2, Tmp3, Result;
4638 switch (getTypeAction(LHS.getValueType())) {
4640 Tmp1 = LegalizeOp(LHS); // LHS
4641 Tmp2 = LegalizeOp(RHS); // RHS
4644 Tmp1 = PromoteOp(LHS); // LHS
4645 Tmp2 = PromoteOp(RHS); // RHS
4647 // If this is an FP compare, the operands have already been extended.
4648 if (LHS.getValueType().isInteger()) {
4649 MVT VT = LHS.getValueType();
4650 MVT NVT = TLI.getTypeToTransformTo(VT);
4652 // Otherwise, we have to insert explicit sign or zero extends. Note
4653 // that we could insert sign extends for ALL conditions, but zero extend
4654 // is cheaper on many machines (an AND instead of two shifts), so prefer
4656 switch (cast<CondCodeSDNode>(CC)->get()) {
4657 default: assert(0 && "Unknown integer comparison!");
4664 // ALL of these operations will work if we either sign or zero extend
4665 // the operands (including the unsigned comparisons!). Zero extend is
4666 // usually a simpler/cheaper operation, so prefer it.
4667 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT);
4668 Tmp2 = DAG.getZeroExtendInReg(Tmp2, VT);
4674 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1,
4675 DAG.getValueType(VT));
4676 Tmp2 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp2,
4677 DAG.getValueType(VT));
4683 MVT VT = LHS.getValueType();
4684 if (VT == MVT::f32 || VT == MVT::f64) {
4685 // Expand into one or more soft-fp libcall(s).
4686 RTLIB::Libcall LC1 = RTLIB::UNKNOWN_LIBCALL, LC2 = RTLIB::UNKNOWN_LIBCALL;
4687 switch (cast<CondCodeSDNode>(CC)->get()) {
4690 LC1 = (VT == MVT::f32) ? RTLIB::OEQ_F32 : RTLIB::OEQ_F64;
4694 LC1 = (VT == MVT::f32) ? RTLIB::UNE_F32 : RTLIB::UNE_F64;
4698 LC1 = (VT == MVT::f32) ? RTLIB::OGE_F32 : RTLIB::OGE_F64;
4702 LC1 = (VT == MVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64;
4706 LC1 = (VT == MVT::f32) ? RTLIB::OLE_F32 : RTLIB::OLE_F64;
4710 LC1 = (VT == MVT::f32) ? RTLIB::OGT_F32 : RTLIB::OGT_F64;
4713 LC1 = (VT == MVT::f32) ? RTLIB::UO_F32 : RTLIB::UO_F64;
4716 LC1 = (VT == MVT::f32) ? RTLIB::O_F32 : RTLIB::O_F64;
4719 LC1 = (VT == MVT::f32) ? RTLIB::UO_F32 : RTLIB::UO_F64;
4720 switch (cast<CondCodeSDNode>(CC)->get()) {
4722 // SETONE = SETOLT | SETOGT
4723 LC1 = (VT == MVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64;
4726 LC2 = (VT == MVT::f32) ? RTLIB::OGT_F32 : RTLIB::OGT_F64;
4729 LC2 = (VT == MVT::f32) ? RTLIB::OGE_F32 : RTLIB::OGE_F64;
4732 LC2 = (VT == MVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64;
4735 LC2 = (VT == MVT::f32) ? RTLIB::OLE_F32 : RTLIB::OLE_F64;
4738 LC2 = (VT == MVT::f32) ? RTLIB::OEQ_F32 : RTLIB::OEQ_F64;
4740 default: assert(0 && "Unsupported FP setcc!");
4745 SDValue Ops[2] = { LHS, RHS };
4746 Tmp1 = ExpandLibCall(LC1, DAG.getMergeValues(Ops, 2).getNode(),
4747 false /*sign irrelevant*/, Dummy);
4748 Tmp2 = DAG.getConstant(0, MVT::i32);
4749 CC = DAG.getCondCode(TLI.getCmpLibcallCC(LC1));
4750 if (LC2 != RTLIB::UNKNOWN_LIBCALL) {
4751 Tmp1 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultType(Tmp1), Tmp1, Tmp2,
4753 LHS = ExpandLibCall(LC2, DAG.getMergeValues(Ops, 2).getNode(),
4754 false /*sign irrelevant*/, Dummy);
4755 Tmp2 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultType(LHS), LHS, Tmp2,
4756 DAG.getCondCode(TLI.getCmpLibcallCC(LC2)));
4757 Tmp1 = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp2);
4760 LHS = LegalizeOp(Tmp1);
4765 SDValue LHSLo, LHSHi, RHSLo, RHSHi;
4766 ExpandOp(LHS, LHSLo, LHSHi);
4767 ExpandOp(RHS, RHSLo, RHSHi);
4768 ISD::CondCode CCCode = cast<CondCodeSDNode>(CC)->get();
4770 if (VT==MVT::ppcf128) {
4771 // FIXME: This generated code sucks. We want to generate
4772 // FCMPU crN, hi1, hi2
4774 // FCMPU crN, lo1, lo2
4775 // The following can be improved, but not that much.
4776 Tmp1 = DAG.getSetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi,
4778 Tmp2 = DAG.getSetCC(TLI.getSetCCResultType(LHSLo), LHSLo, RHSLo, CCCode);
4779 Tmp3 = DAG.getNode(ISD::AND, Tmp1.getValueType(), Tmp1, Tmp2);
4780 Tmp1 = DAG.getSetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi,
4782 Tmp2 = DAG.getSetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi, CCCode);
4783 Tmp1 = DAG.getNode(ISD::AND, Tmp1.getValueType(), Tmp1, Tmp2);
4784 Tmp1 = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp3);
4793 if (ConstantSDNode *RHSCST = dyn_cast<ConstantSDNode>(RHSLo))
4794 if (RHSCST->isAllOnesValue()) {
4795 // Comparison to -1.
4796 Tmp1 = DAG.getNode(ISD::AND, LHSLo.getValueType(), LHSLo, LHSHi);
4801 Tmp1 = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSLo, RHSLo);
4802 Tmp2 = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSHi, RHSHi);
4803 Tmp1 = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp2);
4804 Tmp2 = DAG.getConstant(0, Tmp1.getValueType());
4807 // If this is a comparison of the sign bit, just look at the top part.
4809 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(RHS))
4810 if ((cast<CondCodeSDNode>(CC)->get() == ISD::SETLT &&
4811 CST->isNullValue()) || // X < 0
4812 (cast<CondCodeSDNode>(CC)->get() == ISD::SETGT &&
4813 CST->isAllOnesValue())) { // X > -1
4819 // FIXME: This generated code sucks.
4820 ISD::CondCode LowCC;
4822 default: assert(0 && "Unknown integer setcc!");
4824 case ISD::SETULT: LowCC = ISD::SETULT; break;
4826 case ISD::SETUGT: LowCC = ISD::SETUGT; break;
4828 case ISD::SETULE: LowCC = ISD::SETULE; break;
4830 case ISD::SETUGE: LowCC = ISD::SETUGE; break;
4833 // Tmp1 = lo(op1) < lo(op2) // Always unsigned comparison
4834 // Tmp2 = hi(op1) < hi(op2) // Signedness depends on operands
4835 // dest = hi(op1) == hi(op2) ? Tmp1 : Tmp2;
4837 // NOTE: on targets without efficient SELECT of bools, we can always use
4838 // this identity: (B1 ? B2 : B3) --> (B1 & B2)|(!B1&B3)
4839 TargetLowering::DAGCombinerInfo DagCombineInfo(DAG, false, true, NULL);
4840 Tmp1 = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSLo), LHSLo, RHSLo,
4841 LowCC, false, DagCombineInfo);
4842 if (!Tmp1.getNode())
4843 Tmp1 = DAG.getSetCC(TLI.getSetCCResultType(LHSLo), LHSLo, RHSLo, LowCC);
4844 Tmp2 = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi,
4845 CCCode, false, DagCombineInfo);
4846 if (!Tmp2.getNode())
4847 Tmp2 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultType(LHSHi), LHSHi,
4850 ConstantSDNode *Tmp1C = dyn_cast<ConstantSDNode>(Tmp1.getNode());
4851 ConstantSDNode *Tmp2C = dyn_cast<ConstantSDNode>(Tmp2.getNode());
4852 if ((Tmp1C && Tmp1C->isNullValue()) ||
4853 (Tmp2C && Tmp2C->isNullValue() &&
4854 (CCCode == ISD::SETLE || CCCode == ISD::SETGE ||
4855 CCCode == ISD::SETUGE || CCCode == ISD::SETULE)) ||
4856 (Tmp2C && Tmp2C->getAPIntValue() == 1 &&
4857 (CCCode == ISD::SETLT || CCCode == ISD::SETGT ||
4858 CCCode == ISD::SETUGT || CCCode == ISD::SETULT))) {
4859 // low part is known false, returns high part.
4860 // For LE / GE, if high part is known false, ignore the low part.
4861 // For LT / GT, if high part is known true, ignore the low part.
4865 Result = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi,
4866 ISD::SETEQ, false, DagCombineInfo);
4867 if (!Result.getNode())
4868 Result=DAG.getSetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi,
4870 Result = LegalizeOp(DAG.getNode(ISD::SELECT, Tmp1.getValueType(),
4871 Result, Tmp1, Tmp2));
4882 /// EmitStackConvert - Emit a store/load combination to the stack. This stores
4883 /// SrcOp to a stack slot of type SlotVT, truncating it if needed. It then does
4884 /// a load from the stack slot to DestVT, extending it if needed.
4885 /// The resultant code need not be legal.
4886 SDValue SelectionDAGLegalize::EmitStackConvert(SDValue SrcOp,
4889 // Create the stack frame object.
4890 unsigned SrcAlign = TLI.getTargetData()->getPrefTypeAlignment(
4891 SrcOp.getValueType().getTypeForMVT());
4892 SDValue FIPtr = DAG.CreateStackTemporary(SlotVT, SrcAlign);
4894 FrameIndexSDNode *StackPtrFI = cast<FrameIndexSDNode>(FIPtr);
4895 int SPFI = StackPtrFI->getIndex();
4897 unsigned SrcSize = SrcOp.getValueType().getSizeInBits();
4898 unsigned SlotSize = SlotVT.getSizeInBits();
4899 unsigned DestSize = DestVT.getSizeInBits();
4900 unsigned DestAlign = TLI.getTargetData()->getPrefTypeAlignment(
4901 DestVT.getTypeForMVT());
4903 // Emit a store to the stack slot. Use a truncstore if the input value is
4904 // later than DestVT.
4907 if (SrcSize > SlotSize)
4908 Store = DAG.getTruncStore(DAG.getEntryNode(), SrcOp, FIPtr,
4909 PseudoSourceValue::getFixedStack(SPFI), 0,
4910 SlotVT, false, SrcAlign);
4912 assert(SrcSize == SlotSize && "Invalid store");
4913 Store = DAG.getStore(DAG.getEntryNode(), SrcOp, FIPtr,
4914 PseudoSourceValue::getFixedStack(SPFI), 0,
4918 // Result is a load from the stack slot.
4919 if (SlotSize == DestSize)
4920 return DAG.getLoad(DestVT, Store, FIPtr, NULL, 0, false, DestAlign);
4922 assert(SlotSize < DestSize && "Unknown extension!");
4923 return DAG.getExtLoad(ISD::EXTLOAD, DestVT, Store, FIPtr, NULL, 0, SlotVT,
4927 SDValue SelectionDAGLegalize::ExpandSCALAR_TO_VECTOR(SDNode *Node) {
4928 // Create a vector sized/aligned stack slot, store the value to element #0,
4929 // then load the whole vector back out.
4930 SDValue StackPtr = DAG.CreateStackTemporary(Node->getValueType(0));
4932 FrameIndexSDNode *StackPtrFI = cast<FrameIndexSDNode>(StackPtr);
4933 int SPFI = StackPtrFI->getIndex();
4935 SDValue Ch = DAG.getStore(DAG.getEntryNode(), Node->getOperand(0), StackPtr,
4936 PseudoSourceValue::getFixedStack(SPFI), 0);
4937 return DAG.getLoad(Node->getValueType(0), Ch, StackPtr,
4938 PseudoSourceValue::getFixedStack(SPFI), 0);
4942 /// ExpandBUILD_VECTOR - Expand a BUILD_VECTOR node on targets that don't
4943 /// support the operation, but do support the resultant vector type.
4944 SDValue SelectionDAGLegalize::ExpandBUILD_VECTOR(SDNode *Node) {
4946 // If the only non-undef value is the low element, turn this into a
4947 // SCALAR_TO_VECTOR node. If this is { X, X, X, X }, determine X.
4948 unsigned NumElems = Node->getNumOperands();
4949 bool isOnlyLowElement = true;
4950 SDValue SplatValue = Node->getOperand(0);
4952 // FIXME: it would be far nicer to change this into map<SDValue,uint64_t>
4953 // and use a bitmask instead of a list of elements.
4954 std::map<SDValue, std::vector<unsigned> > Values;
4955 Values[SplatValue].push_back(0);
4956 bool isConstant = true;
4957 if (!isa<ConstantFPSDNode>(SplatValue) && !isa<ConstantSDNode>(SplatValue) &&
4958 SplatValue.getOpcode() != ISD::UNDEF)
4961 for (unsigned i = 1; i < NumElems; ++i) {
4962 SDValue V = Node->getOperand(i);
4963 Values[V].push_back(i);
4964 if (V.getOpcode() != ISD::UNDEF)
4965 isOnlyLowElement = false;
4966 if (SplatValue != V)
4967 SplatValue = SDValue(0,0);
4969 // If this isn't a constant element or an undef, we can't use a constant
4971 if (!isa<ConstantFPSDNode>(V) && !isa<ConstantSDNode>(V) &&
4972 V.getOpcode() != ISD::UNDEF)
4976 if (isOnlyLowElement) {
4977 // If the low element is an undef too, then this whole things is an undef.
4978 if (Node->getOperand(0).getOpcode() == ISD::UNDEF)
4979 return DAG.getNode(ISD::UNDEF, Node->getValueType(0));
4980 // Otherwise, turn this into a scalar_to_vector node.
4981 return DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0),
4982 Node->getOperand(0));
4985 // If all elements are constants, create a load from the constant pool.
4987 MVT VT = Node->getValueType(0);
4988 std::vector<Constant*> CV;
4989 for (unsigned i = 0, e = NumElems; i != e; ++i) {
4990 if (ConstantFPSDNode *V =
4991 dyn_cast<ConstantFPSDNode>(Node->getOperand(i))) {
4992 CV.push_back(const_cast<ConstantFP *>(V->getConstantFPValue()));
4993 } else if (ConstantSDNode *V =
4994 dyn_cast<ConstantSDNode>(Node->getOperand(i))) {
4995 CV.push_back(const_cast<ConstantInt *>(V->getConstantIntValue()));
4997 assert(Node->getOperand(i).getOpcode() == ISD::UNDEF);
4999 Node->getOperand(0).getValueType().getTypeForMVT();
5000 CV.push_back(UndefValue::get(OpNTy));
5003 Constant *CP = ConstantVector::get(CV);
5004 SDValue CPIdx = DAG.getConstantPool(CP, TLI.getPointerTy());
5005 unsigned Alignment = 1 << cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
5006 return DAG.getLoad(VT, DAG.getEntryNode(), CPIdx,
5007 PseudoSourceValue::getConstantPool(), 0,
5011 if (SplatValue.getNode()) { // Splat of one value?
5012 // Build the shuffle constant vector: <0, 0, 0, 0>
5013 MVT MaskVT = MVT::getIntVectorWithNumElements(NumElems);
5014 SDValue Zero = DAG.getConstant(0, MaskVT.getVectorElementType());
5015 std::vector<SDValue> ZeroVec(NumElems, Zero);
5016 SDValue SplatMask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
5017 &ZeroVec[0], ZeroVec.size());
5019 // If the target supports VECTOR_SHUFFLE and this shuffle mask, use it.
5020 if (isShuffleLegal(Node->getValueType(0), SplatMask)) {
5021 // Get the splatted value into the low element of a vector register.
5023 DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0), SplatValue);
5025 // Return shuffle(LowValVec, undef, <0,0,0,0>)
5026 return DAG.getNode(ISD::VECTOR_SHUFFLE, Node->getValueType(0), LowValVec,
5027 DAG.getNode(ISD::UNDEF, Node->getValueType(0)),
5032 // If there are only two unique elements, we may be able to turn this into a
5034 if (Values.size() == 2) {
5035 // Get the two values in deterministic order.
5036 SDValue Val1 = Node->getOperand(1);
5038 std::map<SDValue, std::vector<unsigned> >::iterator MI = Values.begin();
5039 if (MI->first != Val1)
5042 Val2 = (++MI)->first;
5044 // If Val1 is an undef, make sure end ends up as Val2, to ensure that our
5045 // vector shuffle has the undef vector on the RHS.
5046 if (Val1.getOpcode() == ISD::UNDEF)
5047 std::swap(Val1, Val2);
5049 // Build the shuffle constant vector: e.g. <0, 4, 0, 4>
5050 MVT MaskVT = MVT::getIntVectorWithNumElements(NumElems);
5051 MVT MaskEltVT = MaskVT.getVectorElementType();
5052 std::vector<SDValue> MaskVec(NumElems);
5054 // Set elements of the shuffle mask for Val1.
5055 std::vector<unsigned> &Val1Elts = Values[Val1];
5056 for (unsigned i = 0, e = Val1Elts.size(); i != e; ++i)
5057 MaskVec[Val1Elts[i]] = DAG.getConstant(0, MaskEltVT);
5059 // Set elements of the shuffle mask for Val2.
5060 std::vector<unsigned> &Val2Elts = Values[Val2];
5061 for (unsigned i = 0, e = Val2Elts.size(); i != e; ++i)
5062 if (Val2.getOpcode() != ISD::UNDEF)
5063 MaskVec[Val2Elts[i]] = DAG.getConstant(NumElems, MaskEltVT);
5065 MaskVec[Val2Elts[i]] = DAG.getNode(ISD::UNDEF, MaskEltVT);
5067 SDValue ShuffleMask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
5068 &MaskVec[0], MaskVec.size());
5070 // If the target supports SCALAR_TO_VECTOR and this shuffle mask, use it.
5071 if (TLI.isOperationLegal(ISD::SCALAR_TO_VECTOR, Node->getValueType(0)) &&
5072 isShuffleLegal(Node->getValueType(0), ShuffleMask)) {
5073 Val1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0), Val1);
5074 Val2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0), Val2);
5075 SDValue Ops[] = { Val1, Val2, ShuffleMask };
5077 // Return shuffle(LoValVec, HiValVec, <0,1,0,1>)
5078 return DAG.getNode(ISD::VECTOR_SHUFFLE, Node->getValueType(0), Ops, 3);
5082 // Otherwise, we can't handle this case efficiently. Allocate a sufficiently
5083 // aligned object on the stack, store each element into it, then load
5084 // the result as a vector.
5085 MVT VT = Node->getValueType(0);
5086 // Create the stack frame object.
5087 SDValue FIPtr = DAG.CreateStackTemporary(VT);
5089 // Emit a store of each element to the stack slot.
5090 SmallVector<SDValue, 8> Stores;
5091 unsigned TypeByteSize = Node->getOperand(0).getValueType().getSizeInBits()/8;
5092 // Store (in the right endianness) the elements to memory.
5093 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
5094 // Ignore undef elements.
5095 if (Node->getOperand(i).getOpcode() == ISD::UNDEF) continue;
5097 unsigned Offset = TypeByteSize*i;
5099 SDValue Idx = DAG.getConstant(Offset, FIPtr.getValueType());
5100 Idx = DAG.getNode(ISD::ADD, FIPtr.getValueType(), FIPtr, Idx);
5102 Stores.push_back(DAG.getStore(DAG.getEntryNode(), Node->getOperand(i), Idx,
5107 if (!Stores.empty()) // Not all undef elements?
5108 StoreChain = DAG.getNode(ISD::TokenFactor, MVT::Other,
5109 &Stores[0], Stores.size());
5111 StoreChain = DAG.getEntryNode();
5113 // Result is a load from the stack slot.
5114 return DAG.getLoad(VT, StoreChain, FIPtr, NULL, 0);
5117 void SelectionDAGLegalize::ExpandShiftParts(unsigned NodeOp,
5118 SDValue Op, SDValue Amt,
5119 SDValue &Lo, SDValue &Hi) {
5120 // Expand the subcomponents.
5122 ExpandOp(Op, LHSL, LHSH);
5124 SDValue Ops[] = { LHSL, LHSH, Amt };
5125 MVT VT = LHSL.getValueType();
5126 Lo = DAG.getNode(NodeOp, DAG.getNodeValueTypes(VT, VT), 2, Ops, 3);
5127 Hi = Lo.getValue(1);
5131 /// ExpandShift - Try to find a clever way to expand this shift operation out to
5132 /// smaller elements. If we can't find a way that is more efficient than a
5133 /// libcall on this target, return false. Otherwise, return true with the
5134 /// low-parts expanded into Lo and Hi.
5135 bool SelectionDAGLegalize::ExpandShift(unsigned Opc, SDValue Op,SDValue Amt,
5136 SDValue &Lo, SDValue &Hi) {
5137 assert((Opc == ISD::SHL || Opc == ISD::SRA || Opc == ISD::SRL) &&
5138 "This is not a shift!");
5140 MVT NVT = TLI.getTypeToTransformTo(Op.getValueType());
5141 SDValue ShAmt = LegalizeOp(Amt);
5142 MVT ShTy = ShAmt.getValueType();
5143 unsigned ShBits = ShTy.getSizeInBits();
5144 unsigned VTBits = Op.getValueType().getSizeInBits();
5145 unsigned NVTBits = NVT.getSizeInBits();
5147 // Handle the case when Amt is an immediate.
5148 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Amt.getNode())) {
5149 unsigned Cst = CN->getZExtValue();
5150 // Expand the incoming operand to be shifted, so that we have its parts
5152 ExpandOp(Op, InL, InH);
5156 Lo = DAG.getConstant(0, NVT);
5157 Hi = DAG.getConstant(0, NVT);
5158 } else if (Cst > NVTBits) {
5159 Lo = DAG.getConstant(0, NVT);
5160 Hi = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Cst-NVTBits,ShTy));
5161 } else if (Cst == NVTBits) {
5162 Lo = DAG.getConstant(0, NVT);
5165 Lo = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Cst, ShTy));
5166 Hi = DAG.getNode(ISD::OR, NVT,
5167 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(Cst, ShTy)),
5168 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(NVTBits-Cst, ShTy)));
5173 Lo = DAG.getConstant(0, NVT);
5174 Hi = DAG.getConstant(0, NVT);
5175 } else if (Cst > NVTBits) {
5176 Lo = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Cst-NVTBits,ShTy));
5177 Hi = DAG.getConstant(0, NVT);
5178 } else if (Cst == NVTBits) {
5180 Hi = DAG.getConstant(0, NVT);
5182 Lo = DAG.getNode(ISD::OR, NVT,
5183 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(Cst, ShTy)),
5184 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(NVTBits-Cst, ShTy)));
5185 Hi = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Cst, ShTy));
5190 Hi = Lo = DAG.getNode(ISD::SRA, NVT, InH,
5191 DAG.getConstant(NVTBits-1, ShTy));
5192 } else if (Cst > NVTBits) {
5193 Lo = DAG.getNode(ISD::SRA, NVT, InH,
5194 DAG.getConstant(Cst-NVTBits, ShTy));
5195 Hi = DAG.getNode(ISD::SRA, NVT, InH,
5196 DAG.getConstant(NVTBits-1, ShTy));
5197 } else if (Cst == NVTBits) {
5199 Hi = DAG.getNode(ISD::SRA, NVT, InH,
5200 DAG.getConstant(NVTBits-1, ShTy));
5202 Lo = DAG.getNode(ISD::OR, NVT,
5203 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(Cst, ShTy)),
5204 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(NVTBits-Cst, ShTy)));
5205 Hi = DAG.getNode(ISD::SRA, NVT, InH, DAG.getConstant(Cst, ShTy));
5211 // Okay, the shift amount isn't constant. However, if we can tell that it is
5212 // >= 32 or < 32, we can still simplify it, without knowing the actual value.
5213 APInt Mask = APInt::getHighBitsSet(ShBits, ShBits - Log2_32(NVTBits));
5214 APInt KnownZero, KnownOne;
5215 DAG.ComputeMaskedBits(Amt, Mask, KnownZero, KnownOne);
5217 // If we know that if any of the high bits of the shift amount are one, then
5218 // we can do this as a couple of simple shifts.
5219 if (KnownOne.intersects(Mask)) {
5220 // Mask out the high bit, which we know is set.
5221 Amt = DAG.getNode(ISD::AND, Amt.getValueType(), Amt,
5222 DAG.getConstant(~Mask, Amt.getValueType()));
5224 // Expand the incoming operand to be shifted, so that we have its parts
5226 ExpandOp(Op, InL, InH);
5229 Lo = DAG.getConstant(0, NVT); // Low part is zero.
5230 Hi = DAG.getNode(ISD::SHL, NVT, InL, Amt); // High part from Lo part.
5233 Hi = DAG.getConstant(0, NVT); // Hi part is zero.
5234 Lo = DAG.getNode(ISD::SRL, NVT, InH, Amt); // Lo part from Hi part.
5237 Hi = DAG.getNode(ISD::SRA, NVT, InH, // Sign extend high part.
5238 DAG.getConstant(NVTBits-1, Amt.getValueType()));
5239 Lo = DAG.getNode(ISD::SRA, NVT, InH, Amt); // Lo part from Hi part.
5244 // If we know that the high bits of the shift amount are all zero, then we can
5245 // do this as a couple of simple shifts.
5246 if ((KnownZero & Mask) == Mask) {
5248 SDValue Amt2 = DAG.getNode(ISD::SUB, Amt.getValueType(),
5249 DAG.getConstant(NVTBits, Amt.getValueType()),
5252 // Expand the incoming operand to be shifted, so that we have its parts
5254 ExpandOp(Op, InL, InH);
5257 Lo = DAG.getNode(ISD::SHL, NVT, InL, Amt);
5258 Hi = DAG.getNode(ISD::OR, NVT,
5259 DAG.getNode(ISD::SHL, NVT, InH, Amt),
5260 DAG.getNode(ISD::SRL, NVT, InL, Amt2));
5263 Hi = DAG.getNode(ISD::SRL, NVT, InH, Amt);
5264 Lo = DAG.getNode(ISD::OR, NVT,
5265 DAG.getNode(ISD::SRL, NVT, InL, Amt),
5266 DAG.getNode(ISD::SHL, NVT, InH, Amt2));
5269 Hi = DAG.getNode(ISD::SRA, NVT, InH, Amt);
5270 Lo = DAG.getNode(ISD::OR, NVT,
5271 DAG.getNode(ISD::SRL, NVT, InL, Amt),
5272 DAG.getNode(ISD::SHL, NVT, InH, Amt2));
5281 // ExpandLibCall - Expand a node into a call to a libcall. If the result value
5282 // does not fit into a register, return the lo part and set the hi part to the
5283 // by-reg argument. If it does fit into a single register, return the result
5284 // and leave the Hi part unset.
5285 SDValue SelectionDAGLegalize::ExpandLibCall(RTLIB::Libcall LC, SDNode *Node,
5286 bool isSigned, SDValue &Hi) {
5287 assert(!IsLegalizingCall && "Cannot overlap legalization of calls!");
5288 // The input chain to this libcall is the entry node of the function.
5289 // Legalizing the call will automatically add the previous call to the
5291 SDValue InChain = DAG.getEntryNode();
5293 TargetLowering::ArgListTy Args;
5294 TargetLowering::ArgListEntry Entry;
5295 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
5296 MVT ArgVT = Node->getOperand(i).getValueType();
5297 const Type *ArgTy = ArgVT.getTypeForMVT();
5298 Entry.Node = Node->getOperand(i); Entry.Ty = ArgTy;
5299 Entry.isSExt = isSigned;
5300 Entry.isZExt = !isSigned;
5301 Args.push_back(Entry);
5303 SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC),
5304 TLI.getPointerTy());
5306 // Splice the libcall in wherever FindInputOutputChains tells us to.
5307 const Type *RetTy = Node->getValueType(0).getTypeForMVT();
5308 std::pair<SDValue,SDValue> CallInfo =
5309 TLI.LowerCallTo(InChain, RetTy, isSigned, !isSigned, false, false,
5310 CallingConv::C, false, Callee, Args, DAG);
5312 // Legalize the call sequence, starting with the chain. This will advance
5313 // the LastCALLSEQ_END to the legalized version of the CALLSEQ_END node that
5314 // was added by LowerCallTo (guaranteeing proper serialization of calls).
5315 LegalizeOp(CallInfo.second);
5317 switch (getTypeAction(CallInfo.first.getValueType())) {
5318 default: assert(0 && "Unknown thing");
5320 Result = CallInfo.first;
5323 ExpandOp(CallInfo.first, Result, Hi);
5329 /// LegalizeINT_TO_FP - Legalize a [US]INT_TO_FP operation.
5331 SDValue SelectionDAGLegalize::
5332 LegalizeINT_TO_FP(SDValue Result, bool isSigned, MVT DestTy, SDValue Op) {
5333 bool isCustom = false;
5335 switch (getTypeAction(Op.getValueType())) {
5337 switch (TLI.getOperationAction(isSigned ? ISD::SINT_TO_FP : ISD::UINT_TO_FP,
5338 Op.getValueType())) {
5339 default: assert(0 && "Unknown operation action!");
5340 case TargetLowering::Custom:
5343 case TargetLowering::Legal:
5344 Tmp1 = LegalizeOp(Op);
5345 if (Result.getNode())
5346 Result = DAG.UpdateNodeOperands(Result, Tmp1);
5348 Result = DAG.getNode(isSigned ? ISD::SINT_TO_FP : ISD::UINT_TO_FP,
5351 Tmp1 = TLI.LowerOperation(Result, DAG);
5352 if (Tmp1.getNode()) Result = Tmp1;
5355 case TargetLowering::Expand:
5356 Result = ExpandLegalINT_TO_FP(isSigned, LegalizeOp(Op), DestTy);
5358 case TargetLowering::Promote:
5359 Result = PromoteLegalINT_TO_FP(LegalizeOp(Op), DestTy, isSigned);
5364 Result = ExpandIntToFP(isSigned, DestTy, Op);
5367 Tmp1 = PromoteOp(Op);
5369 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, Tmp1.getValueType(),
5370 Tmp1, DAG.getValueType(Op.getValueType()));
5372 Tmp1 = DAG.getZeroExtendInReg(Tmp1,
5375 if (Result.getNode())
5376 Result = DAG.UpdateNodeOperands(Result, Tmp1);
5378 Result = DAG.getNode(isSigned ? ISD::SINT_TO_FP : ISD::UINT_TO_FP,
5380 Result = LegalizeOp(Result); // The 'op' is not necessarily legal!
5386 /// ExpandIntToFP - Expand a [US]INT_TO_FP operation.
5388 SDValue SelectionDAGLegalize::
5389 ExpandIntToFP(bool isSigned, MVT DestTy, SDValue Source) {
5390 MVT SourceVT = Source.getValueType();
5391 bool ExpandSource = getTypeAction(SourceVT) == Expand;
5393 // Expand unsupported int-to-fp vector casts by unrolling them.
5394 if (DestTy.isVector()) {
5396 return LegalizeOp(UnrollVectorOp(Source));
5397 MVT DestEltTy = DestTy.getVectorElementType();
5398 if (DestTy.getVectorNumElements() == 1) {
5399 SDValue Scalar = ScalarizeVectorOp(Source);
5400 SDValue Result = LegalizeINT_TO_FP(SDValue(), isSigned,
5402 return DAG.getNode(ISD::BUILD_VECTOR, DestTy, Result);
5405 SplitVectorOp(Source, Lo, Hi);
5406 MVT SplitDestTy = MVT::getVectorVT(DestEltTy,
5407 DestTy.getVectorNumElements() / 2);
5408 SDValue LoResult = LegalizeINT_TO_FP(SDValue(), isSigned, SplitDestTy, Lo);
5409 SDValue HiResult = LegalizeINT_TO_FP(SDValue(), isSigned, SplitDestTy, Hi);
5410 return LegalizeOp(DAG.getNode(ISD::CONCAT_VECTORS, DestTy, LoResult, HiResult));
5413 // Special case for i32 source to take advantage of UINTTOFP_I32_F32, etc.
5414 if (!isSigned && SourceVT != MVT::i32) {
5415 // The integer value loaded will be incorrectly if the 'sign bit' of the
5416 // incoming integer is set. To handle this, we dynamically test to see if
5417 // it is set, and, if so, add a fudge factor.
5421 ExpandOp(Source, Lo, Hi);
5422 Source = DAG.getNode(ISD::BUILD_PAIR, SourceVT, Lo, Hi);
5424 // The comparison for the sign bit will use the entire operand.
5428 // If this is unsigned, and not supported, first perform the conversion to
5429 // signed, then adjust the result if the sign bit is set.
5430 SDValue SignedConv = ExpandIntToFP(true, DestTy, Source);
5432 SDValue SignSet = DAG.getSetCC(TLI.getSetCCResultType(Hi), Hi,
5433 DAG.getConstant(0, Hi.getValueType()),
5435 SDValue Zero = DAG.getIntPtrConstant(0), Four = DAG.getIntPtrConstant(4);
5436 SDValue CstOffset = DAG.getNode(ISD::SELECT, Zero.getValueType(),
5437 SignSet, Four, Zero);
5438 uint64_t FF = 0x5f800000ULL;
5439 if (TLI.isLittleEndian()) FF <<= 32;
5440 static Constant *FudgeFactor = ConstantInt::get(Type::Int64Ty, FF);
5442 SDValue CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy());
5443 unsigned Alignment = 1 << cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
5444 CPIdx = DAG.getNode(ISD::ADD, TLI.getPointerTy(), CPIdx, CstOffset);
5445 Alignment = std::min(Alignment, 4u);
5447 if (DestTy == MVT::f32)
5448 FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx,
5449 PseudoSourceValue::getConstantPool(), 0,
5451 else if (DestTy.bitsGT(MVT::f32))
5452 // FIXME: Avoid the extend by construction the right constantpool?
5453 FudgeInReg = DAG.getExtLoad(ISD::EXTLOAD, DestTy, DAG.getEntryNode(),
5455 PseudoSourceValue::getConstantPool(), 0,
5456 MVT::f32, false, Alignment);
5458 assert(0 && "Unexpected conversion");
5460 MVT SCVT = SignedConv.getValueType();
5461 if (SCVT != DestTy) {
5462 // Destination type needs to be expanded as well. The FADD now we are
5463 // constructing will be expanded into a libcall.
5464 if (SCVT.getSizeInBits() != DestTy.getSizeInBits()) {
5465 assert(SCVT.getSizeInBits() * 2 == DestTy.getSizeInBits());
5466 SignedConv = DAG.getNode(ISD::BUILD_PAIR, DestTy,
5467 SignedConv, SignedConv.getValue(1));
5469 SignedConv = DAG.getNode(ISD::BIT_CONVERT, DestTy, SignedConv);
5471 return DAG.getNode(ISD::FADD, DestTy, SignedConv, FudgeInReg);
5474 // Check to see if the target has a custom way to lower this. If so, use it.
5475 switch (TLI.getOperationAction(ISD::SINT_TO_FP, SourceVT)) {
5476 default: assert(0 && "This action not implemented for this operation!");
5477 case TargetLowering::Legal:
5478 case TargetLowering::Expand:
5479 break; // This case is handled below.
5480 case TargetLowering::Custom: {
5481 SDValue NV = TLI.LowerOperation(DAG.getNode(ISD::SINT_TO_FP, DestTy,
5484 return LegalizeOp(NV);
5485 break; // The target decided this was legal after all
5489 // Expand the source, then glue it back together for the call. We must expand
5490 // the source in case it is shared (this pass of legalize must traverse it).
5492 SDValue SrcLo, SrcHi;
5493 ExpandOp(Source, SrcLo, SrcHi);
5494 Source = DAG.getNode(ISD::BUILD_PAIR, SourceVT, SrcLo, SrcHi);
5497 RTLIB::Libcall LC = isSigned ?
5498 RTLIB::getSINTTOFP(SourceVT, DestTy) :
5499 RTLIB::getUINTTOFP(SourceVT, DestTy);
5500 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unknown int value type");
5502 Source = DAG.getNode(ISD::SINT_TO_FP, DestTy, Source);
5504 SDValue Result = ExpandLibCall(LC, Source.getNode(), isSigned, HiPart);
5505 if (Result.getValueType() != DestTy && HiPart.getNode())
5506 Result = DAG.getNode(ISD::BUILD_PAIR, DestTy, Result, HiPart);
5510 /// ExpandLegalINT_TO_FP - This function is responsible for legalizing a
5511 /// INT_TO_FP operation of the specified operand when the target requests that
5512 /// we expand it. At this point, we know that the result and operand types are
5513 /// legal for the target.
5514 SDValue SelectionDAGLegalize::ExpandLegalINT_TO_FP(bool isSigned,
5517 if (Op0.getValueType() == MVT::i32) {
5518 // simple 32-bit [signed|unsigned] integer to float/double expansion
5520 // Get the stack frame index of a 8 byte buffer.
5521 SDValue StackSlot = DAG.CreateStackTemporary(MVT::f64);
5523 // word offset constant for Hi/Lo address computation
5524 SDValue WordOff = DAG.getConstant(sizeof(int), TLI.getPointerTy());
5525 // set up Hi and Lo (into buffer) address based on endian
5526 SDValue Hi = StackSlot;
5527 SDValue Lo = DAG.getNode(ISD::ADD, TLI.getPointerTy(), StackSlot,WordOff);
5528 if (TLI.isLittleEndian())
5531 // if signed map to unsigned space
5534 // constant used to invert sign bit (signed to unsigned mapping)
5535 SDValue SignBit = DAG.getConstant(0x80000000u, MVT::i32);
5536 Op0Mapped = DAG.getNode(ISD::XOR, MVT::i32, Op0, SignBit);
5540 // store the lo of the constructed double - based on integer input
5541 SDValue Store1 = DAG.getStore(DAG.getEntryNode(),
5542 Op0Mapped, Lo, NULL, 0);
5543 // initial hi portion of constructed double
5544 SDValue InitialHi = DAG.getConstant(0x43300000u, MVT::i32);
5545 // store the hi of the constructed double - biased exponent
5546 SDValue Store2=DAG.getStore(Store1, InitialHi, Hi, NULL, 0);
5547 // load the constructed double
5548 SDValue Load = DAG.getLoad(MVT::f64, Store2, StackSlot, NULL, 0);
5549 // FP constant to bias correct the final result
5550 SDValue Bias = DAG.getConstantFP(isSigned ?
5551 BitsToDouble(0x4330000080000000ULL)
5552 : BitsToDouble(0x4330000000000000ULL),
5554 // subtract the bias
5555 SDValue Sub = DAG.getNode(ISD::FSUB, MVT::f64, Load, Bias);
5558 // handle final rounding
5559 if (DestVT == MVT::f64) {
5562 } else if (DestVT.bitsLT(MVT::f64)) {
5563 Result = DAG.getNode(ISD::FP_ROUND, DestVT, Sub,
5564 DAG.getIntPtrConstant(0));
5565 } else if (DestVT.bitsGT(MVT::f64)) {
5566 Result = DAG.getNode(ISD::FP_EXTEND, DestVT, Sub);
5570 assert(!isSigned && "Legalize cannot Expand SINT_TO_FP for i64 yet");
5571 SDValue Tmp1 = DAG.getNode(ISD::SINT_TO_FP, DestVT, Op0);
5573 SDValue SignSet = DAG.getSetCC(TLI.getSetCCResultType(Op0), Op0,
5574 DAG.getConstant(0, Op0.getValueType()),
5576 SDValue Zero = DAG.getIntPtrConstant(0), Four = DAG.getIntPtrConstant(4);
5577 SDValue CstOffset = DAG.getNode(ISD::SELECT, Zero.getValueType(),
5578 SignSet, Four, Zero);
5580 // If the sign bit of the integer is set, the large number will be treated
5581 // as a negative number. To counteract this, the dynamic code adds an
5582 // offset depending on the data type.
5584 switch (Op0.getValueType().getSimpleVT()) {
5585 default: assert(0 && "Unsupported integer type!");
5586 case MVT::i8 : FF = 0x43800000ULL; break; // 2^8 (as a float)
5587 case MVT::i16: FF = 0x47800000ULL; break; // 2^16 (as a float)
5588 case MVT::i32: FF = 0x4F800000ULL; break; // 2^32 (as a float)
5589 case MVT::i64: FF = 0x5F800000ULL; break; // 2^64 (as a float)
5591 if (TLI.isLittleEndian()) FF <<= 32;
5592 static Constant *FudgeFactor = ConstantInt::get(Type::Int64Ty, FF);
5594 SDValue CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy());
5595 unsigned Alignment = 1 << cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
5596 CPIdx = DAG.getNode(ISD::ADD, TLI.getPointerTy(), CPIdx, CstOffset);
5597 Alignment = std::min(Alignment, 4u);
5599 if (DestVT == MVT::f32)
5600 FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx,
5601 PseudoSourceValue::getConstantPool(), 0,
5605 LegalizeOp(DAG.getExtLoad(ISD::EXTLOAD, DestVT,
5606 DAG.getEntryNode(), CPIdx,
5607 PseudoSourceValue::getConstantPool(), 0,
5608 MVT::f32, false, Alignment));
5611 return DAG.getNode(ISD::FADD, DestVT, Tmp1, FudgeInReg);
5614 /// PromoteLegalINT_TO_FP - This function is responsible for legalizing a
5615 /// *INT_TO_FP operation of the specified operand when the target requests that
5616 /// we promote it. At this point, we know that the result and operand types are
5617 /// legal for the target, and that there is a legal UINT_TO_FP or SINT_TO_FP
5618 /// operation that takes a larger input.
5619 SDValue SelectionDAGLegalize::PromoteLegalINT_TO_FP(SDValue LegalOp,
5622 // First step, figure out the appropriate *INT_TO_FP operation to use.
5623 MVT NewInTy = LegalOp.getValueType();
5625 unsigned OpToUse = 0;
5627 // Scan for the appropriate larger type to use.
5629 NewInTy = (MVT::SimpleValueType)(NewInTy.getSimpleVT()+1);
5630 assert(NewInTy.isInteger() && "Ran out of possibilities!");
5632 // If the target supports SINT_TO_FP of this type, use it.
5633 switch (TLI.getOperationAction(ISD::SINT_TO_FP, NewInTy)) {
5635 case TargetLowering::Legal:
5636 if (!TLI.isTypeLegal(NewInTy))
5637 break; // Can't use this datatype.
5639 case TargetLowering::Custom:
5640 OpToUse = ISD::SINT_TO_FP;
5644 if (isSigned) continue;
5646 // If the target supports UINT_TO_FP of this type, use it.
5647 switch (TLI.getOperationAction(ISD::UINT_TO_FP, NewInTy)) {
5649 case TargetLowering::Legal:
5650 if (!TLI.isTypeLegal(NewInTy))
5651 break; // Can't use this datatype.
5653 case TargetLowering::Custom:
5654 OpToUse = ISD::UINT_TO_FP;
5659 // Otherwise, try a larger type.
5662 // Okay, we found the operation and type to use. Zero extend our input to the
5663 // desired type then run the operation on it.
5664 return DAG.getNode(OpToUse, DestVT,
5665 DAG.getNode(isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND,
5669 /// PromoteLegalFP_TO_INT - This function is responsible for legalizing a
5670 /// FP_TO_*INT operation of the specified operand when the target requests that
5671 /// we promote it. At this point, we know that the result and operand types are
5672 /// legal for the target, and that there is a legal FP_TO_UINT or FP_TO_SINT
5673 /// operation that returns a larger result.
5674 SDValue SelectionDAGLegalize::PromoteLegalFP_TO_INT(SDValue LegalOp,
5677 // First step, figure out the appropriate FP_TO*INT operation to use.
5678 MVT NewOutTy = DestVT;
5680 unsigned OpToUse = 0;
5682 // Scan for the appropriate larger type to use.
5684 NewOutTy = (MVT::SimpleValueType)(NewOutTy.getSimpleVT()+1);
5685 assert(NewOutTy.isInteger() && "Ran out of possibilities!");
5687 // If the target supports FP_TO_SINT returning this type, use it.
5688 switch (TLI.getOperationAction(ISD::FP_TO_SINT, NewOutTy)) {
5690 case TargetLowering::Legal:
5691 if (!TLI.isTypeLegal(NewOutTy))
5692 break; // Can't use this datatype.
5694 case TargetLowering::Custom:
5695 OpToUse = ISD::FP_TO_SINT;
5700 // If the target supports FP_TO_UINT of this type, use it.
5701 switch (TLI.getOperationAction(ISD::FP_TO_UINT, NewOutTy)) {
5703 case TargetLowering::Legal:
5704 if (!TLI.isTypeLegal(NewOutTy))
5705 break; // Can't use this datatype.
5707 case TargetLowering::Custom:
5708 OpToUse = ISD::FP_TO_UINT;
5713 // Otherwise, try a larger type.
5717 // Okay, we found the operation and type to use.
5718 SDValue Operation = DAG.getNode(OpToUse, NewOutTy, LegalOp);
5720 // If the operation produces an invalid type, it must be custom lowered. Use
5721 // the target lowering hooks to expand it. Just keep the low part of the
5722 // expanded operation, we know that we're truncating anyway.
5723 if (getTypeAction(NewOutTy) == Expand) {
5724 Operation = SDValue(TLI.ReplaceNodeResults(Operation.getNode(), DAG), 0);
5725 assert(Operation.getNode() && "Didn't return anything");
5728 // Truncate the result of the extended FP_TO_*INT operation to the desired
5730 return DAG.getNode(ISD::TRUNCATE, DestVT, Operation);
5733 /// ExpandBSWAP - Open code the operations for BSWAP of the specified operation.
5735 SDValue SelectionDAGLegalize::ExpandBSWAP(SDValue Op) {
5736 MVT VT = Op.getValueType();
5737 MVT SHVT = TLI.getShiftAmountTy();
5738 SDValue Tmp1, Tmp2, Tmp3, Tmp4, Tmp5, Tmp6, Tmp7, Tmp8;
5739 switch (VT.getSimpleVT()) {
5740 default: assert(0 && "Unhandled Expand type in BSWAP!"); abort();
5742 Tmp2 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT));
5743 Tmp1 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(8, SHVT));
5744 return DAG.getNode(ISD::OR, VT, Tmp1, Tmp2);
5746 Tmp4 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(24, SHVT));
5747 Tmp3 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT));
5748 Tmp2 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(8, SHVT));
5749 Tmp1 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(24, SHVT));
5750 Tmp3 = DAG.getNode(ISD::AND, VT, Tmp3, DAG.getConstant(0xFF0000, VT));
5751 Tmp2 = DAG.getNode(ISD::AND, VT, Tmp2, DAG.getConstant(0xFF00, VT));
5752 Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp3);
5753 Tmp2 = DAG.getNode(ISD::OR, VT, Tmp2, Tmp1);
5754 return DAG.getNode(ISD::OR, VT, Tmp4, Tmp2);
5756 Tmp8 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(56, SHVT));
5757 Tmp7 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(40, SHVT));
5758 Tmp6 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(24, SHVT));
5759 Tmp5 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT));
5760 Tmp4 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(8, SHVT));
5761 Tmp3 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(24, SHVT));
5762 Tmp2 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(40, SHVT));
5763 Tmp1 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(56, SHVT));
5764 Tmp7 = DAG.getNode(ISD::AND, VT, Tmp7, DAG.getConstant(255ULL<<48, VT));
5765 Tmp6 = DAG.getNode(ISD::AND, VT, Tmp6, DAG.getConstant(255ULL<<40, VT));
5766 Tmp5 = DAG.getNode(ISD::AND, VT, Tmp5, DAG.getConstant(255ULL<<32, VT));
5767 Tmp4 = DAG.getNode(ISD::AND, VT, Tmp4, DAG.getConstant(255ULL<<24, VT));
5768 Tmp3 = DAG.getNode(ISD::AND, VT, Tmp3, DAG.getConstant(255ULL<<16, VT));
5769 Tmp2 = DAG.getNode(ISD::AND, VT, Tmp2, DAG.getConstant(255ULL<<8 , VT));
5770 Tmp8 = DAG.getNode(ISD::OR, VT, Tmp8, Tmp7);
5771 Tmp6 = DAG.getNode(ISD::OR, VT, Tmp6, Tmp5);
5772 Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp3);
5773 Tmp2 = DAG.getNode(ISD::OR, VT, Tmp2, Tmp1);
5774 Tmp8 = DAG.getNode(ISD::OR, VT, Tmp8, Tmp6);
5775 Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp2);
5776 return DAG.getNode(ISD::OR, VT, Tmp8, Tmp4);
5780 /// ExpandBitCount - Expand the specified bitcount instruction into operations.
5782 SDValue SelectionDAGLegalize::ExpandBitCount(unsigned Opc, SDValue Op) {
5784 default: assert(0 && "Cannot expand this yet!");
5786 static const uint64_t mask[6] = {
5787 0x5555555555555555ULL, 0x3333333333333333ULL,
5788 0x0F0F0F0F0F0F0F0FULL, 0x00FF00FF00FF00FFULL,
5789 0x0000FFFF0000FFFFULL, 0x00000000FFFFFFFFULL
5791 MVT VT = Op.getValueType();
5792 MVT ShVT = TLI.getShiftAmountTy();
5793 unsigned len = VT.getSizeInBits();
5794 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) {
5795 //x = (x & mask[i][len/8]) + (x >> (1 << i) & mask[i][len/8])
5796 SDValue Tmp2 = DAG.getConstant(mask[i], VT);
5797 SDValue Tmp3 = DAG.getConstant(1ULL << i, ShVT);
5798 Op = DAG.getNode(ISD::ADD, VT, DAG.getNode(ISD::AND, VT, Op, Tmp2),
5799 DAG.getNode(ISD::AND, VT,
5800 DAG.getNode(ISD::SRL, VT, Op, Tmp3),Tmp2));
5805 // for now, we do this:
5806 // x = x | (x >> 1);
5807 // x = x | (x >> 2);
5809 // x = x | (x >>16);
5810 // x = x | (x >>32); // for 64-bit input
5811 // return popcount(~x);
5813 // but see also: http://www.hackersdelight.org/HDcode/nlz.cc
5814 MVT VT = Op.getValueType();
5815 MVT ShVT = TLI.getShiftAmountTy();
5816 unsigned len = VT.getSizeInBits();
5817 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) {
5818 SDValue Tmp3 = DAG.getConstant(1ULL << i, ShVT);
5819 Op = DAG.getNode(ISD::OR, VT, Op, DAG.getNode(ISD::SRL, VT, Op, Tmp3));
5821 Op = DAG.getNode(ISD::XOR, VT, Op, DAG.getConstant(~0ULL, VT));
5822 return DAG.getNode(ISD::CTPOP, VT, Op);
5825 // for now, we use: { return popcount(~x & (x - 1)); }
5826 // unless the target has ctlz but not ctpop, in which case we use:
5827 // { return 32 - nlz(~x & (x-1)); }
5828 // see also http://www.hackersdelight.org/HDcode/ntz.cc
5829 MVT VT = Op.getValueType();
5830 SDValue Tmp2 = DAG.getConstant(~0ULL, VT);
5831 SDValue Tmp3 = DAG.getNode(ISD::AND, VT,
5832 DAG.getNode(ISD::XOR, VT, Op, Tmp2),
5833 DAG.getNode(ISD::SUB, VT, Op, DAG.getConstant(1, VT)));
5834 // If ISD::CTLZ is legal and CTPOP isn't, then do that instead.
5835 if (!TLI.isOperationLegal(ISD::CTPOP, VT) &&
5836 TLI.isOperationLegal(ISD::CTLZ, VT))
5837 return DAG.getNode(ISD::SUB, VT,
5838 DAG.getConstant(VT.getSizeInBits(), VT),
5839 DAG.getNode(ISD::CTLZ, VT, Tmp3));
5840 return DAG.getNode(ISD::CTPOP, VT, Tmp3);
5845 /// ExpandOp - Expand the specified SDValue into its two component pieces
5846 /// Lo&Hi. Note that the Op MUST be an expanded type. As a result of this, the
5847 /// LegalizedNodes map is filled in for any results that are not expanded, the
5848 /// ExpandedNodes map is filled in for any results that are expanded, and the
5849 /// Lo/Hi values are returned.
5850 void SelectionDAGLegalize::ExpandOp(SDValue Op, SDValue &Lo, SDValue &Hi){
5851 MVT VT = Op.getValueType();
5852 MVT NVT = TLI.getTypeToTransformTo(VT);
5853 SDNode *Node = Op.getNode();
5854 assert(getTypeAction(VT) == Expand && "Not an expanded type!");
5855 assert(((NVT.isInteger() && NVT.bitsLT(VT)) || VT.isFloatingPoint() ||
5856 VT.isVector()) && "Cannot expand to FP value or to larger int value!");
5858 // See if we already expanded it.
5859 DenseMap<SDValue, std::pair<SDValue, SDValue> >::iterator I
5860 = ExpandedNodes.find(Op);
5861 if (I != ExpandedNodes.end()) {
5862 Lo = I->second.first;
5863 Hi = I->second.second;
5867 switch (Node->getOpcode()) {
5868 case ISD::CopyFromReg:
5869 assert(0 && "CopyFromReg must be legal!");
5870 case ISD::FP_ROUND_INREG:
5871 if (VT == MVT::ppcf128 &&
5872 TLI.getOperationAction(ISD::FP_ROUND_INREG, VT) ==
5873 TargetLowering::Custom) {
5874 SDValue SrcLo, SrcHi, Src;
5875 ExpandOp(Op.getOperand(0), SrcLo, SrcHi);
5876 Src = DAG.getNode(ISD::BUILD_PAIR, VT, SrcLo, SrcHi);
5877 SDValue Result = TLI.LowerOperation(
5878 DAG.getNode(ISD::FP_ROUND_INREG, VT, Src, Op.getOperand(1)), DAG);
5879 assert(Result.getNode()->getOpcode() == ISD::BUILD_PAIR);
5880 Lo = Result.getNode()->getOperand(0);
5881 Hi = Result.getNode()->getOperand(1);
5887 cerr << "NODE: "; Node->dump(&DAG); cerr << "\n";
5889 assert(0 && "Do not know how to expand this operator!");
5891 case ISD::EXTRACT_ELEMENT:
5892 ExpandOp(Node->getOperand(0), Lo, Hi);
5893 if (cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue())
5894 return ExpandOp(Hi, Lo, Hi);
5895 return ExpandOp(Lo, Lo, Hi);
5896 case ISD::EXTRACT_VECTOR_ELT:
5897 assert(VT==MVT::i64 && "Do not know how to expand this operator!");
5898 // ExpandEXTRACT_VECTOR_ELT tolerates invalid result types.
5899 Lo = ExpandEXTRACT_VECTOR_ELT(Op);
5900 return ExpandOp(Lo, Lo, Hi);
5902 Lo = DAG.getNode(ISD::UNDEF, NVT);
5903 Hi = DAG.getNode(ISD::UNDEF, NVT);
5905 case ISD::Constant: {
5906 unsigned NVTBits = NVT.getSizeInBits();
5907 const APInt &Cst = cast<ConstantSDNode>(Node)->getAPIntValue();
5908 Lo = DAG.getConstant(APInt(Cst).trunc(NVTBits), NVT);
5909 Hi = DAG.getConstant(Cst.lshr(NVTBits).trunc(NVTBits), NVT);
5912 case ISD::ConstantFP: {
5913 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node);
5914 if (CFP->getValueType(0) == MVT::ppcf128) {
5915 APInt api = CFP->getValueAPF().convertToAPInt();
5916 Lo = DAG.getConstantFP(APFloat(APInt(64, 1, &api.getRawData()[1])),
5918 Hi = DAG.getConstantFP(APFloat(APInt(64, 1, &api.getRawData()[0])),
5922 Lo = ExpandConstantFP(CFP, false, DAG, TLI);
5923 if (getTypeAction(Lo.getValueType()) == Expand)
5924 ExpandOp(Lo, Lo, Hi);
5927 case ISD::BUILD_PAIR:
5928 // Return the operands.
5929 Lo = Node->getOperand(0);
5930 Hi = Node->getOperand(1);
5933 case ISD::MERGE_VALUES:
5934 if (Node->getNumValues() == 1) {
5935 ExpandOp(Op.getOperand(0), Lo, Hi);
5938 // FIXME: For now only expand i64,chain = MERGE_VALUES (x, y)
5939 assert(Op.getResNo() == 0 && Node->getNumValues() == 2 &&
5940 Op.getValue(1).getValueType() == MVT::Other &&
5941 "unhandled MERGE_VALUES");
5942 ExpandOp(Op.getOperand(0), Lo, Hi);
5943 // Remember that we legalized the chain.
5944 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Op.getOperand(1)));
5947 case ISD::SIGN_EXTEND_INREG:
5948 ExpandOp(Node->getOperand(0), Lo, Hi);
5949 // sext_inreg the low part if needed.
5950 Lo = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Lo, Node->getOperand(1));
5952 // The high part gets the sign extension from the lo-part. This handles
5953 // things like sextinreg V:i64 from i8.
5954 Hi = DAG.getNode(ISD::SRA, NVT, Lo,
5955 DAG.getConstant(NVT.getSizeInBits()-1,
5956 TLI.getShiftAmountTy()));
5960 ExpandOp(Node->getOperand(0), Lo, Hi);
5961 SDValue TempLo = DAG.getNode(ISD::BSWAP, NVT, Hi);
5962 Hi = DAG.getNode(ISD::BSWAP, NVT, Lo);
5968 ExpandOp(Node->getOperand(0), Lo, Hi);
5969 Lo = DAG.getNode(ISD::ADD, NVT, // ctpop(HL) -> ctpop(H)+ctpop(L)
5970 DAG.getNode(ISD::CTPOP, NVT, Lo),
5971 DAG.getNode(ISD::CTPOP, NVT, Hi));
5972 Hi = DAG.getConstant(0, NVT);
5976 // ctlz (HL) -> ctlz(H) != 32 ? ctlz(H) : (ctlz(L)+32)
5977 ExpandOp(Node->getOperand(0), Lo, Hi);
5978 SDValue BitsC = DAG.getConstant(NVT.getSizeInBits(), NVT);
5979 SDValue HLZ = DAG.getNode(ISD::CTLZ, NVT, Hi);
5980 SDValue TopNotZero = DAG.getSetCC(TLI.getSetCCResultType(HLZ), HLZ, BitsC,
5982 SDValue LowPart = DAG.getNode(ISD::CTLZ, NVT, Lo);
5983 LowPart = DAG.getNode(ISD::ADD, NVT, LowPart, BitsC);
5985 Lo = DAG.getNode(ISD::SELECT, NVT, TopNotZero, HLZ, LowPart);
5986 Hi = DAG.getConstant(0, NVT);
5991 // cttz (HL) -> cttz(L) != 32 ? cttz(L) : (cttz(H)+32)
5992 ExpandOp(Node->getOperand(0), Lo, Hi);
5993 SDValue BitsC = DAG.getConstant(NVT.getSizeInBits(), NVT);
5994 SDValue LTZ = DAG.getNode(ISD::CTTZ, NVT, Lo);
5995 SDValue BotNotZero = DAG.getSetCC(TLI.getSetCCResultType(LTZ), LTZ, BitsC,
5997 SDValue HiPart = DAG.getNode(ISD::CTTZ, NVT, Hi);
5998 HiPart = DAG.getNode(ISD::ADD, NVT, HiPart, BitsC);
6000 Lo = DAG.getNode(ISD::SELECT, NVT, BotNotZero, LTZ, HiPart);
6001 Hi = DAG.getConstant(0, NVT);
6006 SDValue Ch = Node->getOperand(0); // Legalize the chain.
6007 SDValue Ptr = Node->getOperand(1); // Legalize the pointer.
6008 Lo = DAG.getVAArg(NVT, Ch, Ptr, Node->getOperand(2));
6009 Hi = DAG.getVAArg(NVT, Lo.getValue(1), Ptr, Node->getOperand(2));
6011 // Remember that we legalized the chain.
6012 Hi = LegalizeOp(Hi);
6013 AddLegalizedOperand(Op.getValue(1), Hi.getValue(1));
6014 if (TLI.isBigEndian())
6020 LoadSDNode *LD = cast<LoadSDNode>(Node);
6021 SDValue Ch = LD->getChain(); // Legalize the chain.
6022 SDValue Ptr = LD->getBasePtr(); // Legalize the pointer.
6023 ISD::LoadExtType ExtType = LD->getExtensionType();
6024 const Value *SV = LD->getSrcValue();
6025 int SVOffset = LD->getSrcValueOffset();
6026 unsigned Alignment = LD->getAlignment();
6027 bool isVolatile = LD->isVolatile();
6029 if (ExtType == ISD::NON_EXTLOAD) {
6030 Lo = DAG.getLoad(NVT, Ch, Ptr, SV, SVOffset,
6031 isVolatile, Alignment);
6032 if (VT == MVT::f32 || VT == MVT::f64) {
6033 // f32->i32 or f64->i64 one to one expansion.
6034 // Remember that we legalized the chain.
6035 AddLegalizedOperand(SDValue(Node, 1), LegalizeOp(Lo.getValue(1)));
6036 // Recursively expand the new load.
6037 if (getTypeAction(NVT) == Expand)
6038 ExpandOp(Lo, Lo, Hi);
6042 // Increment the pointer to the other half.
6043 unsigned IncrementSize = Lo.getValueType().getSizeInBits()/8;
6044 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
6045 DAG.getIntPtrConstant(IncrementSize));
6046 SVOffset += IncrementSize;
6047 Alignment = MinAlign(Alignment, IncrementSize);
6048 Hi = DAG.getLoad(NVT, Ch, Ptr, SV, SVOffset,
6049 isVolatile, Alignment);
6051 // Build a factor node to remember that this load is independent of the
6053 SDValue TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
6056 // Remember that we legalized the chain.
6057 AddLegalizedOperand(Op.getValue(1), LegalizeOp(TF));
6058 if (TLI.isBigEndian())
6061 MVT EVT = LD->getMemoryVT();
6063 if ((VT == MVT::f64 && EVT == MVT::f32) ||
6064 (VT == MVT::ppcf128 && (EVT==MVT::f64 || EVT==MVT::f32))) {
6065 // f64 = EXTLOAD f32 should expand to LOAD, FP_EXTEND
6066 SDValue Load = DAG.getLoad(EVT, Ch, Ptr, SV,
6067 SVOffset, isVolatile, Alignment);
6068 // Remember that we legalized the chain.
6069 AddLegalizedOperand(SDValue(Node, 1), LegalizeOp(Load.getValue(1)));
6070 ExpandOp(DAG.getNode(ISD::FP_EXTEND, VT, Load), Lo, Hi);
6075 Lo = DAG.getLoad(NVT, Ch, Ptr, SV,
6076 SVOffset, isVolatile, Alignment);
6078 Lo = DAG.getExtLoad(ExtType, NVT, Ch, Ptr, SV,
6079 SVOffset, EVT, isVolatile,
6082 // Remember that we legalized the chain.
6083 AddLegalizedOperand(SDValue(Node, 1), LegalizeOp(Lo.getValue(1)));
6085 if (ExtType == ISD::SEXTLOAD) {
6086 // The high part is obtained by SRA'ing all but one of the bits of the
6088 unsigned LoSize = Lo.getValueType().getSizeInBits();
6089 Hi = DAG.getNode(ISD::SRA, NVT, Lo,
6090 DAG.getConstant(LoSize-1, TLI.getShiftAmountTy()));
6091 } else if (ExtType == ISD::ZEXTLOAD) {
6092 // The high part is just a zero.
6093 Hi = DAG.getConstant(0, NVT);
6094 } else /* if (ExtType == ISD::EXTLOAD) */ {
6095 // The high part is undefined.
6096 Hi = DAG.getNode(ISD::UNDEF, NVT);
6103 case ISD::XOR: { // Simple logical operators -> two trivial pieces.
6104 SDValue LL, LH, RL, RH;
6105 ExpandOp(Node->getOperand(0), LL, LH);
6106 ExpandOp(Node->getOperand(1), RL, RH);
6107 Lo = DAG.getNode(Node->getOpcode(), NVT, LL, RL);
6108 Hi = DAG.getNode(Node->getOpcode(), NVT, LH, RH);
6112 SDValue LL, LH, RL, RH;
6113 ExpandOp(Node->getOperand(1), LL, LH);
6114 ExpandOp(Node->getOperand(2), RL, RH);
6115 if (getTypeAction(NVT) == Expand)
6116 NVT = TLI.getTypeToExpandTo(NVT);
6117 Lo = DAG.getNode(ISD::SELECT, NVT, Node->getOperand(0), LL, RL);
6119 Hi = DAG.getNode(ISD::SELECT, NVT, Node->getOperand(0), LH, RH);
6122 case ISD::SELECT_CC: {
6123 SDValue TL, TH, FL, FH;
6124 ExpandOp(Node->getOperand(2), TL, TH);
6125 ExpandOp(Node->getOperand(3), FL, FH);
6126 if (getTypeAction(NVT) == Expand)
6127 NVT = TLI.getTypeToExpandTo(NVT);
6128 Lo = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0),
6129 Node->getOperand(1), TL, FL, Node->getOperand(4));
6131 Hi = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0),
6132 Node->getOperand(1), TH, FH, Node->getOperand(4));
6135 case ISD::ANY_EXTEND:
6136 // The low part is any extension of the input (which degenerates to a copy).
6137 Lo = DAG.getNode(ISD::ANY_EXTEND, NVT, Node->getOperand(0));
6138 // The high part is undefined.
6139 Hi = DAG.getNode(ISD::UNDEF, NVT);
6141 case ISD::SIGN_EXTEND: {
6142 // The low part is just a sign extension of the input (which degenerates to
6144 Lo = DAG.getNode(ISD::SIGN_EXTEND, NVT, Node->getOperand(0));
6146 // The high part is obtained by SRA'ing all but one of the bits of the lo
6148 unsigned LoSize = Lo.getValueType().getSizeInBits();
6149 Hi = DAG.getNode(ISD::SRA, NVT, Lo,
6150 DAG.getConstant(LoSize-1, TLI.getShiftAmountTy()));
6153 case ISD::ZERO_EXTEND:
6154 // The low part is just a zero extension of the input (which degenerates to
6156 Lo = DAG.getNode(ISD::ZERO_EXTEND, NVT, Node->getOperand(0));
6158 // The high part is just a zero.
6159 Hi = DAG.getConstant(0, NVT);
6162 case ISD::TRUNCATE: {
6163 // The input value must be larger than this value. Expand *it*.
6165 ExpandOp(Node->getOperand(0), NewLo, Hi);
6167 // The low part is now either the right size, or it is closer. If not the
6168 // right size, make an illegal truncate so we recursively expand it.
6169 if (NewLo.getValueType() != Node->getValueType(0))
6170 NewLo = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), NewLo);
6171 ExpandOp(NewLo, Lo, Hi);
6175 case ISD::BIT_CONVERT: {
6177 if (TLI.getOperationAction(ISD::BIT_CONVERT, VT) == TargetLowering::Custom){
6178 // If the target wants to, allow it to lower this itself.
6179 switch (getTypeAction(Node->getOperand(0).getValueType())) {
6180 case Expand: assert(0 && "cannot expand FP!");
6181 case Legal: Tmp = LegalizeOp(Node->getOperand(0)); break;
6182 case Promote: Tmp = PromoteOp (Node->getOperand(0)); break;
6184 Tmp = TLI.LowerOperation(DAG.getNode(ISD::BIT_CONVERT, VT, Tmp), DAG);
6187 // f32 / f64 must be expanded to i32 / i64.
6188 if (VT == MVT::f32 || VT == MVT::f64) {
6189 Lo = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0));
6190 if (getTypeAction(NVT) == Expand)
6191 ExpandOp(Lo, Lo, Hi);
6195 // If source operand will be expanded to the same type as VT, i.e.
6196 // i64 <- f64, i32 <- f32, expand the source operand instead.
6197 MVT VT0 = Node->getOperand(0).getValueType();
6198 if (getTypeAction(VT0) == Expand && TLI.getTypeToTransformTo(VT0) == VT) {
6199 ExpandOp(Node->getOperand(0), Lo, Hi);
6203 // Turn this into a load/store pair by default.
6204 if (Tmp.getNode() == 0)
6205 Tmp = EmitStackConvert(Node->getOperand(0), VT, VT);
6207 ExpandOp(Tmp, Lo, Hi);
6211 case ISD::READCYCLECOUNTER: {
6212 assert(TLI.getOperationAction(ISD::READCYCLECOUNTER, VT) ==
6213 TargetLowering::Custom &&
6214 "Must custom expand ReadCycleCounter");
6215 SDValue Tmp = TLI.LowerOperation(Op, DAG);
6216 assert(Tmp.getNode() && "Node must be custom expanded!");
6217 ExpandOp(Tmp.getValue(0), Lo, Hi);
6218 AddLegalizedOperand(SDValue(Node, 1), // Remember we legalized the chain.
6219 LegalizeOp(Tmp.getValue(1)));
6223 case ISD::ATOMIC_CMP_SWAP_64: {
6224 // This operation does not need a loop.
6225 SDValue Tmp = TLI.LowerOperation(Op, DAG);
6226 assert(Tmp.getNode() && "Node must be custom expanded!");
6227 ExpandOp(Tmp.getValue(0), Lo, Hi);
6228 AddLegalizedOperand(SDValue(Node, 1), // Remember we legalized the chain.
6229 LegalizeOp(Tmp.getValue(1)));
6233 case ISD::ATOMIC_LOAD_ADD_64:
6234 case ISD::ATOMIC_LOAD_SUB_64:
6235 case ISD::ATOMIC_LOAD_AND_64:
6236 case ISD::ATOMIC_LOAD_OR_64:
6237 case ISD::ATOMIC_LOAD_XOR_64:
6238 case ISD::ATOMIC_LOAD_NAND_64:
6239 case ISD::ATOMIC_SWAP_64: {
6240 // These operations require a loop to be generated. We can't do that yet,
6241 // so substitute a target-dependent pseudo and expand that later.
6242 SDValue In2Lo, In2Hi, In2;
6243 ExpandOp(Op.getOperand(2), In2Lo, In2Hi);
6244 In2 = DAG.getNode(ISD::BUILD_PAIR, VT, In2Lo, In2Hi);
6245 AtomicSDNode* Anode = cast<AtomicSDNode>(Node);
6247 DAG.getAtomic(Op.getOpcode(), Op.getOperand(0), Op.getOperand(1), In2,
6248 Anode->getSrcValue(), Anode->getAlignment());
6249 SDValue Result = TLI.LowerOperation(Replace, DAG);
6250 ExpandOp(Result.getValue(0), Lo, Hi);
6251 // Remember that we legalized the chain.
6252 AddLegalizedOperand(SDValue(Node,1), LegalizeOp(Result.getValue(1)));
6256 // These operators cannot be expanded directly, emit them as calls to
6257 // library functions.
6258 case ISD::FP_TO_SINT: {
6259 if (TLI.getOperationAction(ISD::FP_TO_SINT, VT) == TargetLowering::Custom) {
6261 switch (getTypeAction(Node->getOperand(0).getValueType())) {
6262 case Expand: assert(0 && "cannot expand FP!");
6263 case Legal: Op = LegalizeOp(Node->getOperand(0)); break;
6264 case Promote: Op = PromoteOp (Node->getOperand(0)); break;
6267 Op = TLI.LowerOperation(DAG.getNode(ISD::FP_TO_SINT, VT, Op), DAG);
6269 // Now that the custom expander is done, expand the result, which is still
6272 ExpandOp(Op, Lo, Hi);
6277 RTLIB::Libcall LC = RTLIB::getFPTOSINT(Node->getOperand(0).getValueType(),
6279 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected uint-to-fp conversion!");
6280 Lo = ExpandLibCall(LC, Node, false/*sign irrelevant*/, Hi);
6284 case ISD::FP_TO_UINT: {
6285 if (TLI.getOperationAction(ISD::FP_TO_UINT, VT) == TargetLowering::Custom) {
6287 switch (getTypeAction(Node->getOperand(0).getValueType())) {
6288 case Expand: assert(0 && "cannot expand FP!");
6289 case Legal: Op = LegalizeOp(Node->getOperand(0)); break;
6290 case Promote: Op = PromoteOp (Node->getOperand(0)); break;
6293 Op = TLI.LowerOperation(DAG.getNode(ISD::FP_TO_UINT, VT, Op), DAG);
6295 // Now that the custom expander is done, expand the result.
6297 ExpandOp(Op, Lo, Hi);
6302 RTLIB::Libcall LC = RTLIB::getFPTOUINT(Node->getOperand(0).getValueType(),
6304 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected fp-to-uint conversion!");
6305 Lo = ExpandLibCall(LC, Node, false/*sign irrelevant*/, Hi);
6310 // If the target wants custom lowering, do so.
6311 SDValue ShiftAmt = LegalizeOp(Node->getOperand(1));
6312 if (TLI.getOperationAction(ISD::SHL, VT) == TargetLowering::Custom) {
6313 SDValue Op = DAG.getNode(ISD::SHL, VT, Node->getOperand(0), ShiftAmt);
6314 Op = TLI.LowerOperation(Op, DAG);
6316 // Now that the custom expander is done, expand the result, which is
6318 ExpandOp(Op, Lo, Hi);
6323 // If ADDC/ADDE are supported and if the shift amount is a constant 1, emit
6324 // this X << 1 as X+X.
6325 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(ShiftAmt)) {
6326 if (ShAmt->getAPIntValue() == 1 && TLI.isOperationLegal(ISD::ADDC, NVT) &&
6327 TLI.isOperationLegal(ISD::ADDE, NVT)) {
6328 SDValue LoOps[2], HiOps[3];
6329 ExpandOp(Node->getOperand(0), LoOps[0], HiOps[0]);
6330 SDVTList VTList = DAG.getVTList(LoOps[0].getValueType(), MVT::Flag);
6331 LoOps[1] = LoOps[0];
6332 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2);
6334 HiOps[1] = HiOps[0];
6335 HiOps[2] = Lo.getValue(1);
6336 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3);
6341 // If we can emit an efficient shift operation, do so now.
6342 if (ExpandShift(ISD::SHL, Node->getOperand(0), ShiftAmt, Lo, Hi))
6345 // If this target supports SHL_PARTS, use it.
6346 TargetLowering::LegalizeAction Action =
6347 TLI.getOperationAction(ISD::SHL_PARTS, NVT);
6348 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) ||
6349 Action == TargetLowering::Custom) {
6350 ExpandShiftParts(ISD::SHL_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi);
6354 // Otherwise, emit a libcall.
6355 Lo = ExpandLibCall(RTLIB::SHL_I64, Node, false/*left shift=unsigned*/, Hi);
6360 // If the target wants custom lowering, do so.
6361 SDValue ShiftAmt = LegalizeOp(Node->getOperand(1));
6362 if (TLI.getOperationAction(ISD::SRA, VT) == TargetLowering::Custom) {
6363 SDValue Op = DAG.getNode(ISD::SRA, VT, Node->getOperand(0), ShiftAmt);
6364 Op = TLI.LowerOperation(Op, DAG);
6366 // Now that the custom expander is done, expand the result, which is
6368 ExpandOp(Op, Lo, Hi);
6373 // If we can emit an efficient shift operation, do so now.
6374 if (ExpandShift(ISD::SRA, Node->getOperand(0), ShiftAmt, Lo, Hi))
6377 // If this target supports SRA_PARTS, use it.
6378 TargetLowering::LegalizeAction Action =
6379 TLI.getOperationAction(ISD::SRA_PARTS, NVT);
6380 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) ||
6381 Action == TargetLowering::Custom) {
6382 ExpandShiftParts(ISD::SRA_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi);
6386 // Otherwise, emit a libcall.
6387 Lo = ExpandLibCall(RTLIB::SRA_I64, Node, true/*ashr is signed*/, Hi);
6392 // If the target wants custom lowering, do so.
6393 SDValue ShiftAmt = LegalizeOp(Node->getOperand(1));
6394 if (TLI.getOperationAction(ISD::SRL, VT) == TargetLowering::Custom) {
6395 SDValue Op = DAG.getNode(ISD::SRL, VT, Node->getOperand(0), ShiftAmt);
6396 Op = TLI.LowerOperation(Op, DAG);
6398 // Now that the custom expander is done, expand the result, which is
6400 ExpandOp(Op, Lo, Hi);
6405 // If we can emit an efficient shift operation, do so now.
6406 if (ExpandShift(ISD::SRL, Node->getOperand(0), ShiftAmt, Lo, Hi))
6409 // If this target supports SRL_PARTS, use it.
6410 TargetLowering::LegalizeAction Action =
6411 TLI.getOperationAction(ISD::SRL_PARTS, NVT);
6412 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) ||
6413 Action == TargetLowering::Custom) {
6414 ExpandShiftParts(ISD::SRL_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi);
6418 // Otherwise, emit a libcall.
6419 Lo = ExpandLibCall(RTLIB::SRL_I64, Node, false/*lshr is unsigned*/, Hi);
6425 // If the target wants to custom expand this, let them.
6426 if (TLI.getOperationAction(Node->getOpcode(), VT) ==
6427 TargetLowering::Custom) {
6428 SDValue Result = TLI.LowerOperation(Op, DAG);
6429 if (Result.getNode()) {
6430 ExpandOp(Result, Lo, Hi);
6434 // Expand the subcomponents.
6435 SDValue LHSL, LHSH, RHSL, RHSH;
6436 ExpandOp(Node->getOperand(0), LHSL, LHSH);
6437 ExpandOp(Node->getOperand(1), RHSL, RHSH);
6438 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag);
6439 SDValue LoOps[2], HiOps[3];
6445 //cascaded check to see if any smaller size has a a carry flag.
6446 unsigned OpV = Node->getOpcode() == ISD::ADD ? ISD::ADDC : ISD::SUBC;
6447 bool hasCarry = false;
6448 for (unsigned BitSize = NVT.getSizeInBits(); BitSize != 0; BitSize /= 2) {
6449 MVT AVT = MVT::getIntegerVT(BitSize);
6450 if (TLI.isOperationLegal(OpV, AVT)) {
6457 if (Node->getOpcode() == ISD::ADD) {
6458 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2);
6459 HiOps[2] = Lo.getValue(1);
6460 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3);
6462 Lo = DAG.getNode(ISD::SUBC, VTList, LoOps, 2);
6463 HiOps[2] = Lo.getValue(1);
6464 Hi = DAG.getNode(ISD::SUBE, VTList, HiOps, 3);
6468 if (Node->getOpcode() == ISD::ADD) {
6469 Lo = DAG.getNode(ISD::ADD, VTList, LoOps, 2);
6470 Hi = DAG.getNode(ISD::ADD, VTList, HiOps, 2);
6471 SDValue Cmp1 = DAG.getSetCC(TLI.getSetCCResultType(Lo),
6472 Lo, LoOps[0], ISD::SETULT);
6473 SDValue Carry1 = DAG.getNode(ISD::SELECT, NVT, Cmp1,
6474 DAG.getConstant(1, NVT),
6475 DAG.getConstant(0, NVT));
6476 SDValue Cmp2 = DAG.getSetCC(TLI.getSetCCResultType(Lo),
6477 Lo, LoOps[1], ISD::SETULT);
6478 SDValue Carry2 = DAG.getNode(ISD::SELECT, NVT, Cmp2,
6479 DAG.getConstant(1, NVT),
6481 Hi = DAG.getNode(ISD::ADD, NVT, Hi, Carry2);
6483 Lo = DAG.getNode(ISD::SUB, VTList, LoOps, 2);
6484 Hi = DAG.getNode(ISD::SUB, VTList, HiOps, 2);
6485 SDValue Cmp = DAG.getSetCC(NVT, LoOps[0], LoOps[1], ISD::SETULT);
6486 SDValue Borrow = DAG.getNode(ISD::SELECT, NVT, Cmp,
6487 DAG.getConstant(1, NVT),
6488 DAG.getConstant(0, NVT));
6489 Hi = DAG.getNode(ISD::SUB, NVT, Hi, Borrow);
6497 // Expand the subcomponents.
6498 SDValue LHSL, LHSH, RHSL, RHSH;
6499 ExpandOp(Node->getOperand(0), LHSL, LHSH);
6500 ExpandOp(Node->getOperand(1), RHSL, RHSH);
6501 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag);
6502 SDValue LoOps[2] = { LHSL, RHSL };
6503 SDValue HiOps[3] = { LHSH, RHSH };
6505 if (Node->getOpcode() == ISD::ADDC) {
6506 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2);
6507 HiOps[2] = Lo.getValue(1);
6508 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3);
6510 Lo = DAG.getNode(ISD::SUBC, VTList, LoOps, 2);
6511 HiOps[2] = Lo.getValue(1);
6512 Hi = DAG.getNode(ISD::SUBE, VTList, HiOps, 3);
6514 // Remember that we legalized the flag.
6515 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Hi.getValue(1)));
6520 // Expand the subcomponents.
6521 SDValue LHSL, LHSH, RHSL, RHSH;
6522 ExpandOp(Node->getOperand(0), LHSL, LHSH);
6523 ExpandOp(Node->getOperand(1), RHSL, RHSH);
6524 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag);
6525 SDValue LoOps[3] = { LHSL, RHSL, Node->getOperand(2) };
6526 SDValue HiOps[3] = { LHSH, RHSH };
6528 Lo = DAG.getNode(Node->getOpcode(), VTList, LoOps, 3);
6529 HiOps[2] = Lo.getValue(1);
6530 Hi = DAG.getNode(Node->getOpcode(), VTList, HiOps, 3);
6532 // Remember that we legalized the flag.
6533 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Hi.getValue(1)));
6537 // If the target wants to custom expand this, let them.
6538 if (TLI.getOperationAction(ISD::MUL, VT) == TargetLowering::Custom) {
6539 SDValue New = TLI.LowerOperation(Op, DAG);
6540 if (New.getNode()) {
6541 ExpandOp(New, Lo, Hi);
6546 bool HasMULHS = TLI.isOperationLegal(ISD::MULHS, NVT);
6547 bool HasMULHU = TLI.isOperationLegal(ISD::MULHU, NVT);
6548 bool HasSMUL_LOHI = TLI.isOperationLegal(ISD::SMUL_LOHI, NVT);
6549 bool HasUMUL_LOHI = TLI.isOperationLegal(ISD::UMUL_LOHI, NVT);
6550 if (HasMULHU || HasMULHS || HasUMUL_LOHI || HasSMUL_LOHI) {
6551 SDValue LL, LH, RL, RH;
6552 ExpandOp(Node->getOperand(0), LL, LH);
6553 ExpandOp(Node->getOperand(1), RL, RH);
6554 unsigned OuterBitSize = Op.getValueSizeInBits();
6555 unsigned InnerBitSize = RH.getValueSizeInBits();
6556 unsigned LHSSB = DAG.ComputeNumSignBits(Op.getOperand(0));
6557 unsigned RHSSB = DAG.ComputeNumSignBits(Op.getOperand(1));
6558 APInt HighMask = APInt::getHighBitsSet(OuterBitSize, InnerBitSize);
6559 if (DAG.MaskedValueIsZero(Node->getOperand(0), HighMask) &&
6560 DAG.MaskedValueIsZero(Node->getOperand(1), HighMask)) {
6561 // The inputs are both zero-extended.
6563 // We can emit a umul_lohi.
6564 Lo = DAG.getNode(ISD::UMUL_LOHI, DAG.getVTList(NVT, NVT), LL, RL);
6565 Hi = SDValue(Lo.getNode(), 1);
6569 // We can emit a mulhu+mul.
6570 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL);
6571 Hi = DAG.getNode(ISD::MULHU, NVT, LL, RL);
6575 if (LHSSB > InnerBitSize && RHSSB > InnerBitSize) {
6576 // The input values are both sign-extended.
6578 // We can emit a smul_lohi.
6579 Lo = DAG.getNode(ISD::SMUL_LOHI, DAG.getVTList(NVT, NVT), LL, RL);
6580 Hi = SDValue(Lo.getNode(), 1);
6584 // We can emit a mulhs+mul.
6585 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL);
6586 Hi = DAG.getNode(ISD::MULHS, NVT, LL, RL);
6591 // Lo,Hi = umul LHS, RHS.
6592 SDValue UMulLOHI = DAG.getNode(ISD::UMUL_LOHI,
6593 DAG.getVTList(NVT, NVT), LL, RL);
6595 Hi = UMulLOHI.getValue(1);
6596 RH = DAG.getNode(ISD::MUL, NVT, LL, RH);
6597 LH = DAG.getNode(ISD::MUL, NVT, LH, RL);
6598 Hi = DAG.getNode(ISD::ADD, NVT, Hi, RH);
6599 Hi = DAG.getNode(ISD::ADD, NVT, Hi, LH);
6603 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL);
6604 Hi = DAG.getNode(ISD::MULHU, NVT, LL, RL);
6605 RH = DAG.getNode(ISD::MUL, NVT, LL, RH);
6606 LH = DAG.getNode(ISD::MUL, NVT, LH, RL);
6607 Hi = DAG.getNode(ISD::ADD, NVT, Hi, RH);
6608 Hi = DAG.getNode(ISD::ADD, NVT, Hi, LH);
6613 // If nothing else, we can make a libcall.
6614 Lo = ExpandLibCall(RTLIB::MUL_I64, Node, false/*sign irrelevant*/, Hi);
6618 Lo = ExpandLibCall(RTLIB::SDIV_I64, Node, true, Hi);
6621 Lo = ExpandLibCall(RTLIB::UDIV_I64, Node, true, Hi);
6624 Lo = ExpandLibCall(RTLIB::SREM_I64, Node, true, Hi);
6627 Lo = ExpandLibCall(RTLIB::UREM_I64, Node, true, Hi);
6631 Lo = ExpandLibCall(GetFPLibCall(VT, RTLIB::ADD_F32,
6634 RTLIB::ADD_PPCF128),
6638 Lo = ExpandLibCall(GetFPLibCall(VT, RTLIB::SUB_F32,
6641 RTLIB::SUB_PPCF128),
6645 Lo = ExpandLibCall(GetFPLibCall(VT, RTLIB::MUL_F32,
6648 RTLIB::MUL_PPCF128),
6652 Lo = ExpandLibCall(GetFPLibCall(VT, RTLIB::DIV_F32,
6655 RTLIB::DIV_PPCF128),
6658 case ISD::FP_EXTEND: {
6659 if (VT == MVT::ppcf128) {
6660 assert(Node->getOperand(0).getValueType()==MVT::f32 ||
6661 Node->getOperand(0).getValueType()==MVT::f64);
6662 const uint64_t zero = 0;
6663 if (Node->getOperand(0).getValueType()==MVT::f32)
6664 Hi = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Node->getOperand(0));
6666 Hi = Node->getOperand(0);
6667 Lo = DAG.getConstantFP(APFloat(APInt(64, 1, &zero)), MVT::f64);
6670 RTLIB::Libcall LC = RTLIB::getFPEXT(Node->getOperand(0).getValueType(), VT);
6671 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported FP_EXTEND!");
6672 Lo = ExpandLibCall(LC, Node, true, Hi);
6675 case ISD::FP_ROUND: {
6676 RTLIB::Libcall LC = RTLIB::getFPROUND(Node->getOperand(0).getValueType(),
6678 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported FP_ROUND!");
6679 Lo = ExpandLibCall(LC, Node, true, Hi);
6694 case ISD::FNEARBYINT:
6697 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
6698 switch(Node->getOpcode()) {
6700 LC = GetFPLibCall(VT, RTLIB::SQRT_F32, RTLIB::SQRT_F64,
6701 RTLIB::SQRT_F80, RTLIB::SQRT_PPCF128);
6704 LC = GetFPLibCall(VT, RTLIB::SIN_F32, RTLIB::SIN_F64,
6705 RTLIB::SIN_F80, RTLIB::SIN_PPCF128);
6708 LC = GetFPLibCall(VT, RTLIB::COS_F32, RTLIB::COS_F64,
6709 RTLIB::COS_F80, RTLIB::COS_PPCF128);
6712 LC = GetFPLibCall(VT, RTLIB::LOG_F32, RTLIB::LOG_F64,
6713 RTLIB::LOG_F80, RTLIB::LOG_PPCF128);
6716 LC = GetFPLibCall(VT, RTLIB::LOG2_F32, RTLIB::LOG2_F64,
6717 RTLIB::LOG2_F80, RTLIB::LOG2_PPCF128);
6720 LC = GetFPLibCall(VT, RTLIB::LOG10_F32, RTLIB::LOG10_F64,
6721 RTLIB::LOG10_F80, RTLIB::LOG10_PPCF128);
6724 LC = GetFPLibCall(VT, RTLIB::EXP_F32, RTLIB::EXP_F64,
6725 RTLIB::EXP_F80, RTLIB::EXP_PPCF128);
6728 LC = GetFPLibCall(VT, RTLIB::EXP2_F32, RTLIB::EXP2_F64,
6729 RTLIB::EXP2_F80, RTLIB::EXP2_PPCF128);
6732 LC = GetFPLibCall(VT, RTLIB::TRUNC_F32, RTLIB::TRUNC_F64,
6733 RTLIB::TRUNC_F80, RTLIB::TRUNC_PPCF128);
6736 LC = GetFPLibCall(VT, RTLIB::FLOOR_F32, RTLIB::FLOOR_F64,
6737 RTLIB::FLOOR_F80, RTLIB::FLOOR_PPCF128);
6740 LC = GetFPLibCall(VT, RTLIB::CEIL_F32, RTLIB::CEIL_F64,
6741 RTLIB::CEIL_F80, RTLIB::CEIL_PPCF128);
6744 LC = GetFPLibCall(VT, RTLIB::RINT_F32, RTLIB::RINT_F64,
6745 RTLIB::RINT_F80, RTLIB::RINT_PPCF128);
6747 case ISD::FNEARBYINT:
6748 LC = GetFPLibCall(VT, RTLIB::NEARBYINT_F32, RTLIB::NEARBYINT_F64,
6749 RTLIB::NEARBYINT_F80, RTLIB::NEARBYINT_PPCF128);
6752 LC = GetFPLibCall(VT, RTLIB::POW_F32, RTLIB::POW_F64, RTLIB::POW_F80,
6753 RTLIB::POW_PPCF128);
6756 LC = GetFPLibCall(VT, RTLIB::POWI_F32, RTLIB::POWI_F64, RTLIB::POWI_F80,
6757 RTLIB::POWI_PPCF128);
6759 default: assert(0 && "Unreachable!");
6761 Lo = ExpandLibCall(LC, Node, false, Hi);
6765 if (VT == MVT::ppcf128) {
6767 ExpandOp(Node->getOperand(0), Lo, Tmp);
6768 Hi = DAG.getNode(ISD::FABS, NVT, Tmp);
6769 // lo = hi==fabs(hi) ? lo : -lo;
6770 Lo = DAG.getNode(ISD::SELECT_CC, NVT, Hi, Tmp,
6771 Lo, DAG.getNode(ISD::FNEG, NVT, Lo),
6772 DAG.getCondCode(ISD::SETEQ));
6775 SDValue Mask = (VT == MVT::f64)
6776 ? DAG.getConstantFP(BitsToDouble(~(1ULL << 63)), VT)
6777 : DAG.getConstantFP(BitsToFloat(~(1U << 31)), VT);
6778 Mask = DAG.getNode(ISD::BIT_CONVERT, NVT, Mask);
6779 Lo = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0));
6780 Lo = DAG.getNode(ISD::AND, NVT, Lo, Mask);
6781 if (getTypeAction(NVT) == Expand)
6782 ExpandOp(Lo, Lo, Hi);
6786 if (VT == MVT::ppcf128) {
6787 ExpandOp(Node->getOperand(0), Lo, Hi);
6788 Lo = DAG.getNode(ISD::FNEG, MVT::f64, Lo);
6789 Hi = DAG.getNode(ISD::FNEG, MVT::f64, Hi);
6792 SDValue Mask = (VT == MVT::f64)
6793 ? DAG.getConstantFP(BitsToDouble(1ULL << 63), VT)
6794 : DAG.getConstantFP(BitsToFloat(1U << 31), VT);
6795 Mask = DAG.getNode(ISD::BIT_CONVERT, NVT, Mask);
6796 Lo = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0));
6797 Lo = DAG.getNode(ISD::XOR, NVT, Lo, Mask);
6798 if (getTypeAction(NVT) == Expand)
6799 ExpandOp(Lo, Lo, Hi);
6802 case ISD::FCOPYSIGN: {
6803 Lo = ExpandFCOPYSIGNToBitwiseOps(Node, NVT, DAG, TLI);
6804 if (getTypeAction(NVT) == Expand)
6805 ExpandOp(Lo, Lo, Hi);
6808 case ISD::SINT_TO_FP:
6809 case ISD::UINT_TO_FP: {
6810 bool isSigned = Node->getOpcode() == ISD::SINT_TO_FP;
6811 MVT SrcVT = Node->getOperand(0).getValueType();
6813 // Promote the operand if needed. Do this before checking for
6814 // ppcf128 so conversions of i16 and i8 work.
6815 if (getTypeAction(SrcVT) == Promote) {
6816 SDValue Tmp = PromoteOp(Node->getOperand(0));
6818 ? DAG.getNode(ISD::SIGN_EXTEND_INREG, Tmp.getValueType(), Tmp,
6819 DAG.getValueType(SrcVT))
6820 : DAG.getZeroExtendInReg(Tmp, SrcVT);
6821 Node = DAG.UpdateNodeOperands(Op, Tmp).getNode();
6822 SrcVT = Node->getOperand(0).getValueType();
6825 if (VT == MVT::ppcf128 && SrcVT == MVT::i32) {
6826 static const uint64_t zero = 0;
6828 Hi = LegalizeOp(DAG.getNode(ISD::SINT_TO_FP, MVT::f64,
6829 Node->getOperand(0)));
6830 Lo = DAG.getConstantFP(APFloat(APInt(64, 1, &zero)), MVT::f64);
6832 static const uint64_t TwoE32[] = { 0x41f0000000000000LL, 0 };
6833 Hi = LegalizeOp(DAG.getNode(ISD::SINT_TO_FP, MVT::f64,
6834 Node->getOperand(0)));
6835 Lo = DAG.getConstantFP(APFloat(APInt(64, 1, &zero)), MVT::f64);
6836 Hi = DAG.getNode(ISD::BUILD_PAIR, VT, Lo, Hi);
6837 // X>=0 ? {(f64)x, 0} : {(f64)x, 0} + 2^32
6838 ExpandOp(DAG.getNode(ISD::SELECT_CC, MVT::ppcf128, Node->getOperand(0),
6839 DAG.getConstant(0, MVT::i32),
6840 DAG.getNode(ISD::FADD, MVT::ppcf128, Hi,
6842 APFloat(APInt(128, 2, TwoE32)),
6845 DAG.getCondCode(ISD::SETLT)),
6850 if (VT == MVT::ppcf128 && SrcVT == MVT::i64 && !isSigned) {
6851 // si64->ppcf128 done by libcall, below
6852 static const uint64_t TwoE64[] = { 0x43f0000000000000LL, 0 };
6853 ExpandOp(DAG.getNode(ISD::SINT_TO_FP, MVT::ppcf128, Node->getOperand(0)),
6855 Hi = DAG.getNode(ISD::BUILD_PAIR, VT, Lo, Hi);
6856 // x>=0 ? (ppcf128)(i64)x : (ppcf128)(i64)x + 2^64
6857 ExpandOp(DAG.getNode(ISD::SELECT_CC, MVT::ppcf128, Node->getOperand(0),
6858 DAG.getConstant(0, MVT::i64),
6859 DAG.getNode(ISD::FADD, MVT::ppcf128, Hi,
6861 APFloat(APInt(128, 2, TwoE64)),
6864 DAG.getCondCode(ISD::SETLT)),
6869 Lo = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP, VT,
6870 Node->getOperand(0));
6871 if (getTypeAction(Lo.getValueType()) == Expand)
6872 // float to i32 etc. can be 'expanded' to a single node.
6873 ExpandOp(Lo, Lo, Hi);
6878 // Make sure the resultant values have been legalized themselves, unless this
6879 // is a type that requires multi-step expansion.
6880 if (getTypeAction(NVT) != Expand && NVT != MVT::isVoid) {
6881 Lo = LegalizeOp(Lo);
6883 // Don't legalize the high part if it is expanded to a single node.
6884 Hi = LegalizeOp(Hi);
6887 // Remember in a map if the values will be reused later.
6889 ExpandedNodes.insert(std::make_pair(Op, std::make_pair(Lo, Hi))).second;
6890 assert(isNew && "Value already expanded?!?");
6893 /// SplitVectorOp - Given an operand of vector type, break it down into
6894 /// two smaller values, still of vector type.
6895 void SelectionDAGLegalize::SplitVectorOp(SDValue Op, SDValue &Lo,
6897 assert(Op.getValueType().isVector() && "Cannot split non-vector type!");
6898 SDNode *Node = Op.getNode();
6899 unsigned NumElements = Op.getValueType().getVectorNumElements();
6900 assert(NumElements > 1 && "Cannot split a single element vector!");
6902 MVT NewEltVT = Op.getValueType().getVectorElementType();
6904 unsigned NewNumElts_Lo = 1 << Log2_32(NumElements-1);
6905 unsigned NewNumElts_Hi = NumElements - NewNumElts_Lo;
6907 MVT NewVT_Lo = MVT::getVectorVT(NewEltVT, NewNumElts_Lo);
6908 MVT NewVT_Hi = MVT::getVectorVT(NewEltVT, NewNumElts_Hi);
6910 // See if we already split it.
6911 std::map<SDValue, std::pair<SDValue, SDValue> >::iterator I
6912 = SplitNodes.find(Op);
6913 if (I != SplitNodes.end()) {
6914 Lo = I->second.first;
6915 Hi = I->second.second;
6919 switch (Node->getOpcode()) {
6924 assert(0 && "Unhandled operation in SplitVectorOp!");
6926 Lo = DAG.getNode(ISD::UNDEF, NewVT_Lo);
6927 Hi = DAG.getNode(ISD::UNDEF, NewVT_Hi);
6929 case ISD::BUILD_PAIR:
6930 Lo = Node->getOperand(0);
6931 Hi = Node->getOperand(1);
6933 case ISD::INSERT_VECTOR_ELT: {
6934 if (ConstantSDNode *Idx = dyn_cast<ConstantSDNode>(Node->getOperand(2))) {
6935 SplitVectorOp(Node->getOperand(0), Lo, Hi);
6936 unsigned Index = Idx->getZExtValue();
6937 SDValue ScalarOp = Node->getOperand(1);
6938 if (Index < NewNumElts_Lo)
6939 Lo = DAG.getNode(ISD::INSERT_VECTOR_ELT, NewVT_Lo, Lo, ScalarOp,
6940 DAG.getIntPtrConstant(Index));
6942 Hi = DAG.getNode(ISD::INSERT_VECTOR_ELT, NewVT_Hi, Hi, ScalarOp,
6943 DAG.getIntPtrConstant(Index - NewNumElts_Lo));
6946 SDValue Tmp = PerformInsertVectorEltInMemory(Node->getOperand(0),
6947 Node->getOperand(1),
6948 Node->getOperand(2));
6949 SplitVectorOp(Tmp, Lo, Hi);
6952 case ISD::VECTOR_SHUFFLE: {
6953 // Build the low part.
6954 SDValue Mask = Node->getOperand(2);
6955 SmallVector<SDValue, 8> Ops;
6956 MVT PtrVT = TLI.getPointerTy();
6958 // Insert all of the elements from the input that are needed. We use
6959 // buildvector of extractelement here because the input vectors will have
6960 // to be legalized, so this makes the code simpler.
6961 for (unsigned i = 0; i != NewNumElts_Lo; ++i) {
6962 SDValue IdxNode = Mask.getOperand(i);
6963 if (IdxNode.getOpcode() == ISD::UNDEF) {
6964 Ops.push_back(DAG.getNode(ISD::UNDEF, NewEltVT));
6967 unsigned Idx = cast<ConstantSDNode>(IdxNode)->getZExtValue();
6968 SDValue InVec = Node->getOperand(0);
6969 if (Idx >= NumElements) {
6970 InVec = Node->getOperand(1);
6973 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, NewEltVT, InVec,
6974 DAG.getConstant(Idx, PtrVT)));
6976 Lo = DAG.getNode(ISD::BUILD_VECTOR, NewVT_Lo, &Ops[0], Ops.size());
6979 for (unsigned i = NewNumElts_Lo; i != NumElements; ++i) {
6980 SDValue IdxNode = Mask.getOperand(i);
6981 if (IdxNode.getOpcode() == ISD::UNDEF) {
6982 Ops.push_back(DAG.getNode(ISD::UNDEF, NewEltVT));
6985 unsigned Idx = cast<ConstantSDNode>(IdxNode)->getZExtValue();
6986 SDValue InVec = Node->getOperand(0);
6987 if (Idx >= NumElements) {
6988 InVec = Node->getOperand(1);
6991 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, NewEltVT, InVec,
6992 DAG.getConstant(Idx, PtrVT)));
6994 Hi = DAG.getNode(ISD::BUILD_VECTOR, NewVT_Hi, &Ops[0], Ops.size());
6997 case ISD::BUILD_VECTOR: {
6998 SmallVector<SDValue, 8> LoOps(Node->op_begin(),
6999 Node->op_begin()+NewNumElts_Lo);
7000 Lo = DAG.getNode(ISD::BUILD_VECTOR, NewVT_Lo, &LoOps[0], LoOps.size());
7002 SmallVector<SDValue, 8> HiOps(Node->op_begin()+NewNumElts_Lo,
7004 Hi = DAG.getNode(ISD::BUILD_VECTOR, NewVT_Hi, &HiOps[0], HiOps.size());
7007 case ISD::CONCAT_VECTORS: {
7008 // FIXME: Handle non-power-of-two vectors?
7009 unsigned NewNumSubvectors = Node->getNumOperands() / 2;
7010 if (NewNumSubvectors == 1) {
7011 Lo = Node->getOperand(0);
7012 Hi = Node->getOperand(1);
7014 SmallVector<SDValue, 8> LoOps(Node->op_begin(),
7015 Node->op_begin()+NewNumSubvectors);
7016 Lo = DAG.getNode(ISD::CONCAT_VECTORS, NewVT_Lo, &LoOps[0], LoOps.size());
7018 SmallVector<SDValue, 8> HiOps(Node->op_begin()+NewNumSubvectors,
7020 Hi = DAG.getNode(ISD::CONCAT_VECTORS, NewVT_Hi, &HiOps[0], HiOps.size());
7025 SDValue Cond = Node->getOperand(0);
7027 SDValue LL, LH, RL, RH;
7028 SplitVectorOp(Node->getOperand(1), LL, LH);
7029 SplitVectorOp(Node->getOperand(2), RL, RH);
7031 if (Cond.getValueType().isVector()) {
7032 // Handle a vector merge.
7034 SplitVectorOp(Cond, CL, CH);
7035 Lo = DAG.getNode(Node->getOpcode(), NewVT_Lo, CL, LL, RL);
7036 Hi = DAG.getNode(Node->getOpcode(), NewVT_Hi, CH, LH, RH);
7038 // Handle a simple select with vector operands.
7039 Lo = DAG.getNode(Node->getOpcode(), NewVT_Lo, Cond, LL, RL);
7040 Hi = DAG.getNode(Node->getOpcode(), NewVT_Hi, Cond, LH, RH);
7044 case ISD::SELECT_CC: {
7045 SDValue CondLHS = Node->getOperand(0);
7046 SDValue CondRHS = Node->getOperand(1);
7047 SDValue CondCode = Node->getOperand(4);
7049 SDValue LL, LH, RL, RH;
7050 SplitVectorOp(Node->getOperand(2), LL, LH);
7051 SplitVectorOp(Node->getOperand(3), RL, RH);
7053 // Handle a simple select with vector operands.
7054 Lo = DAG.getNode(ISD::SELECT_CC, NewVT_Lo, CondLHS, CondRHS,
7056 Hi = DAG.getNode(ISD::SELECT_CC, NewVT_Hi, CondLHS, CondRHS,
7061 SDValue LL, LH, RL, RH;
7062 SplitVectorOp(Node->getOperand(0), LL, LH);
7063 SplitVectorOp(Node->getOperand(1), RL, RH);
7064 Lo = DAG.getNode(ISD::VSETCC, NewVT_Lo, LL, RL, Node->getOperand(2));
7065 Hi = DAG.getNode(ISD::VSETCC, NewVT_Hi, LH, RH, Node->getOperand(2));
7084 SDValue LL, LH, RL, RH;
7085 SplitVectorOp(Node->getOperand(0), LL, LH);
7086 SplitVectorOp(Node->getOperand(1), RL, RH);
7088 Lo = DAG.getNode(Node->getOpcode(), NewVT_Lo, LL, RL);
7089 Hi = DAG.getNode(Node->getOpcode(), NewVT_Hi, LH, RH);
7095 SplitVectorOp(Node->getOperand(0), L, H);
7097 Lo = DAG.getNode(Node->getOpcode(), NewVT_Lo, L, Node->getOperand(1));
7098 Hi = DAG.getNode(Node->getOpcode(), NewVT_Hi, H, Node->getOperand(1));
7114 case ISD::FP_TO_SINT:
7115 case ISD::FP_TO_UINT:
7116 case ISD::SINT_TO_FP:
7117 case ISD::UINT_TO_FP:
7119 case ISD::ANY_EXTEND:
7120 case ISD::SIGN_EXTEND:
7121 case ISD::ZERO_EXTEND:
7122 case ISD::FP_EXTEND: {
7124 SplitVectorOp(Node->getOperand(0), L, H);
7126 Lo = DAG.getNode(Node->getOpcode(), NewVT_Lo, L);
7127 Hi = DAG.getNode(Node->getOpcode(), NewVT_Hi, H);
7131 LoadSDNode *LD = cast<LoadSDNode>(Node);
7132 SDValue Ch = LD->getChain();
7133 SDValue Ptr = LD->getBasePtr();
7134 ISD::LoadExtType ExtType = LD->getExtensionType();
7135 const Value *SV = LD->getSrcValue();
7136 int SVOffset = LD->getSrcValueOffset();
7137 MVT MemoryVT = LD->getMemoryVT();
7138 unsigned Alignment = LD->getAlignment();
7139 bool isVolatile = LD->isVolatile();
7141 assert(LD->isUnindexed() && "Indexed vector loads are not supported yet!");
7142 SDValue Offset = DAG.getNode(ISD::UNDEF, Ptr.getValueType());
7144 MVT MemNewEltVT = MemoryVT.getVectorElementType();
7145 MVT MemNewVT_Lo = MVT::getVectorVT(MemNewEltVT, NewNumElts_Lo);
7146 MVT MemNewVT_Hi = MVT::getVectorVT(MemNewEltVT, NewNumElts_Hi);
7148 Lo = DAG.getLoad(ISD::UNINDEXED, ExtType,
7149 NewVT_Lo, Ch, Ptr, Offset,
7150 SV, SVOffset, MemNewVT_Lo, isVolatile, Alignment);
7151 unsigned IncrementSize = NewNumElts_Lo * MemNewEltVT.getSizeInBits()/8;
7152 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
7153 DAG.getIntPtrConstant(IncrementSize));
7154 SVOffset += IncrementSize;
7155 Alignment = MinAlign(Alignment, IncrementSize);
7156 Hi = DAG.getLoad(ISD::UNINDEXED, ExtType,
7157 NewVT_Hi, Ch, Ptr, Offset,
7158 SV, SVOffset, MemNewVT_Hi, isVolatile, Alignment);
7160 // Build a factor node to remember that this load is independent of the
7162 SDValue TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
7165 // Remember that we legalized the chain.
7166 AddLegalizedOperand(Op.getValue(1), LegalizeOp(TF));
7169 case ISD::BIT_CONVERT: {
7170 // We know the result is a vector. The input may be either a vector or a
7172 SDValue InOp = Node->getOperand(0);
7173 if (!InOp.getValueType().isVector() ||
7174 InOp.getValueType().getVectorNumElements() == 1) {
7175 // The input is a scalar or single-element vector.
7176 // Lower to a store/load so that it can be split.
7177 // FIXME: this could be improved probably.
7178 unsigned LdAlign = TLI.getTargetData()->getPrefTypeAlignment(
7179 Op.getValueType().getTypeForMVT());
7180 SDValue Ptr = DAG.CreateStackTemporary(InOp.getValueType(), LdAlign);
7181 int FI = cast<FrameIndexSDNode>(Ptr.getNode())->getIndex();
7183 SDValue St = DAG.getStore(DAG.getEntryNode(),
7185 PseudoSourceValue::getFixedStack(FI), 0);
7186 InOp = DAG.getLoad(Op.getValueType(), St, Ptr,
7187 PseudoSourceValue::getFixedStack(FI), 0);
7189 // Split the vector and convert each of the pieces now.
7190 SplitVectorOp(InOp, Lo, Hi);
7191 Lo = DAG.getNode(ISD::BIT_CONVERT, NewVT_Lo, Lo);
7192 Hi = DAG.getNode(ISD::BIT_CONVERT, NewVT_Hi, Hi);
7197 // Remember in a map if the values will be reused later.
7199 SplitNodes.insert(std::make_pair(Op, std::make_pair(Lo, Hi))).second;
7200 assert(isNew && "Value already split?!?");
7204 /// ScalarizeVectorOp - Given an operand of single-element vector type
7205 /// (e.g. v1f32), convert it into the equivalent operation that returns a
7206 /// scalar (e.g. f32) value.
7207 SDValue SelectionDAGLegalize::ScalarizeVectorOp(SDValue Op) {
7208 assert(Op.getValueType().isVector() && "Bad ScalarizeVectorOp invocation!");
7209 SDNode *Node = Op.getNode();
7210 MVT NewVT = Op.getValueType().getVectorElementType();
7211 assert(Op.getValueType().getVectorNumElements() == 1);
7213 // See if we already scalarized it.
7214 std::map<SDValue, SDValue>::iterator I = ScalarizedNodes.find(Op);
7215 if (I != ScalarizedNodes.end()) return I->second;
7218 switch (Node->getOpcode()) {
7221 Node->dump(&DAG); cerr << "\n";
7223 assert(0 && "Unknown vector operation in ScalarizeVectorOp!");
7240 Result = DAG.getNode(Node->getOpcode(),
7242 ScalarizeVectorOp(Node->getOperand(0)),
7243 ScalarizeVectorOp(Node->getOperand(1)));
7255 case ISD::FP_TO_SINT:
7256 case ISD::FP_TO_UINT:
7257 case ISD::SINT_TO_FP:
7258 case ISD::UINT_TO_FP:
7259 case ISD::SIGN_EXTEND:
7260 case ISD::ZERO_EXTEND:
7261 case ISD::ANY_EXTEND:
7263 case ISD::FP_EXTEND:
7264 Result = DAG.getNode(Node->getOpcode(),
7266 ScalarizeVectorOp(Node->getOperand(0)));
7270 Result = DAG.getNode(Node->getOpcode(),
7272 ScalarizeVectorOp(Node->getOperand(0)),
7273 Node->getOperand(1));
7276 LoadSDNode *LD = cast<LoadSDNode>(Node);
7277 SDValue Ch = LegalizeOp(LD->getChain()); // Legalize the chain.
7278 SDValue Ptr = LegalizeOp(LD->getBasePtr()); // Legalize the pointer.
7279 ISD::LoadExtType ExtType = LD->getExtensionType();
7280 const Value *SV = LD->getSrcValue();
7281 int SVOffset = LD->getSrcValueOffset();
7282 MVT MemoryVT = LD->getMemoryVT();
7283 unsigned Alignment = LD->getAlignment();
7284 bool isVolatile = LD->isVolatile();
7286 assert(LD->isUnindexed() && "Indexed vector loads are not supported yet!");
7287 SDValue Offset = DAG.getNode(ISD::UNDEF, Ptr.getValueType());
7289 Result = DAG.getLoad(ISD::UNINDEXED, ExtType,
7290 NewVT, Ch, Ptr, Offset, SV, SVOffset,
7291 MemoryVT.getVectorElementType(),
7292 isVolatile, Alignment);
7294 // Remember that we legalized the chain.
7295 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
7298 case ISD::BUILD_VECTOR:
7299 Result = Node->getOperand(0);
7301 case ISD::INSERT_VECTOR_ELT:
7302 // Returning the inserted scalar element.
7303 Result = Node->getOperand(1);
7305 case ISD::CONCAT_VECTORS:
7306 assert(Node->getOperand(0).getValueType() == NewVT &&
7307 "Concat of non-legal vectors not yet supported!");
7308 Result = Node->getOperand(0);
7310 case ISD::VECTOR_SHUFFLE: {
7311 // Figure out if the scalar is the LHS or RHS and return it.
7312 SDValue EltNum = Node->getOperand(2).getOperand(0);
7313 if (cast<ConstantSDNode>(EltNum)->getZExtValue())
7314 Result = ScalarizeVectorOp(Node->getOperand(1));
7316 Result = ScalarizeVectorOp(Node->getOperand(0));
7319 case ISD::EXTRACT_SUBVECTOR:
7320 Result = Node->getOperand(0);
7321 assert(Result.getValueType() == NewVT);
7323 case ISD::BIT_CONVERT: {
7324 SDValue Op0 = Op.getOperand(0);
7325 if (Op0.getValueType().getVectorNumElements() == 1)
7326 Op0 = ScalarizeVectorOp(Op0);
7327 Result = DAG.getNode(ISD::BIT_CONVERT, NewVT, Op0);
7331 Result = DAG.getNode(ISD::SELECT, NewVT, Op.getOperand(0),
7332 ScalarizeVectorOp(Op.getOperand(1)),
7333 ScalarizeVectorOp(Op.getOperand(2)));
7335 case ISD::SELECT_CC:
7336 Result = DAG.getNode(ISD::SELECT_CC, NewVT, Node->getOperand(0),
7337 Node->getOperand(1),
7338 ScalarizeVectorOp(Op.getOperand(2)),
7339 ScalarizeVectorOp(Op.getOperand(3)),
7340 Node->getOperand(4));
7343 SDValue Op0 = ScalarizeVectorOp(Op.getOperand(0));
7344 SDValue Op1 = ScalarizeVectorOp(Op.getOperand(1));
7345 Result = DAG.getNode(ISD::SETCC, TLI.getSetCCResultType(Op0), Op0, Op1,
7347 Result = DAG.getNode(ISD::SELECT, NewVT, Result,
7348 DAG.getConstant(-1ULL, NewVT),
7349 DAG.getConstant(0ULL, NewVT));
7354 if (TLI.isTypeLegal(NewVT))
7355 Result = LegalizeOp(Result);
7356 bool isNew = ScalarizedNodes.insert(std::make_pair(Op, Result)).second;
7357 assert(isNew && "Value already scalarized?");
7362 // SelectionDAG::Legalize - This is the entry point for the file.
7364 void SelectionDAG::Legalize() {
7365 /// run - This is the main entry point to this class.
7367 SelectionDAGLegalize(*this).LegalizeDAG();