1 //===-- LegalizeDAG.cpp - Implement SelectionDAG::Legalize ----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the SelectionDAG::Legalize method.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/CallingConv.h"
15 #include "llvm/Constants.h"
16 #include "llvm/DebugInfo.h"
17 #include "llvm/DerivedTypes.h"
18 #include "llvm/LLVMContext.h"
19 #include "llvm/CodeGen/Analysis.h"
20 #include "llvm/CodeGen/MachineFunction.h"
21 #include "llvm/CodeGen/MachineJumpTableInfo.h"
22 #include "llvm/CodeGen/SelectionDAG.h"
23 #include "llvm/Target/TargetFrameLowering.h"
24 #include "llvm/Target/TargetLowering.h"
25 #include "llvm/DataLayout.h"
26 #include "llvm/Target/TargetMachine.h"
27 #include "llvm/Support/Debug.h"
28 #include "llvm/Support/ErrorHandling.h"
29 #include "llvm/Support/MathExtras.h"
30 #include "llvm/Support/raw_ostream.h"
31 #include "llvm/ADT/DenseMap.h"
32 #include "llvm/ADT/SmallVector.h"
33 #include "llvm/ADT/SmallPtrSet.h"
36 //===----------------------------------------------------------------------===//
37 /// SelectionDAGLegalize - This takes an arbitrary SelectionDAG as input and
38 /// hacks on it until the target machine can handle it. This involves
39 /// eliminating value sizes the machine cannot handle (promoting small sizes to
40 /// large sizes or splitting up large values into small values) as well as
41 /// eliminating operations the machine cannot handle.
43 /// This code also does a small amount of optimization and recognition of idioms
44 /// as part of its processing. For example, if a target does not support a
45 /// 'setcc' instruction efficiently, but does support 'brcc' instruction, this
46 /// will attempt merge setcc and brc instructions into brcc's.
49 class SelectionDAGLegalize : public SelectionDAG::DAGUpdateListener {
50 const TargetMachine &TM;
51 const TargetLowering &TLI;
54 /// LegalizePosition - The iterator for walking through the node list.
55 SelectionDAG::allnodes_iterator LegalizePosition;
57 /// LegalizedNodes - The set of nodes which have already been legalized.
58 SmallPtrSet<SDNode *, 16> LegalizedNodes;
60 // Libcall insertion helpers.
63 explicit SelectionDAGLegalize(SelectionDAG &DAG);
68 /// LegalizeOp - Legalizes the given operation.
69 void LegalizeOp(SDNode *Node);
71 SDValue OptimizeFloatStore(StoreSDNode *ST);
73 void LegalizeLoadOps(SDNode *Node);
74 void LegalizeStoreOps(SDNode *Node);
76 /// PerformInsertVectorEltInMemory - Some target cannot handle a variable
77 /// insertion index for the INSERT_VECTOR_ELT instruction. In this case, it
78 /// is necessary to spill the vector being inserted into to memory, perform
79 /// the insert there, and then read the result back.
80 SDValue PerformInsertVectorEltInMemory(SDValue Vec, SDValue Val,
81 SDValue Idx, DebugLoc dl);
82 SDValue ExpandINSERT_VECTOR_ELT(SDValue Vec, SDValue Val,
83 SDValue Idx, DebugLoc dl);
85 /// ShuffleWithNarrowerEltType - Return a vector shuffle operation which
86 /// performs the same shuffe in terms of order or result bytes, but on a type
87 /// whose vector element type is narrower than the original shuffle type.
88 /// e.g. <v4i32> <0, 1, 0, 1> -> v8i16 <0, 1, 2, 3, 0, 1, 2, 3>
89 SDValue ShuffleWithNarrowerEltType(EVT NVT, EVT VT, DebugLoc dl,
90 SDValue N1, SDValue N2,
91 ArrayRef<int> Mask) const;
93 void LegalizeSetCCCondCode(EVT VT, SDValue &LHS, SDValue &RHS, SDValue &CC,
96 SDValue ExpandLibCall(RTLIB::Libcall LC, SDNode *Node, bool isSigned);
97 SDValue ExpandLibCall(RTLIB::Libcall LC, EVT RetVT, const SDValue *Ops,
98 unsigned NumOps, bool isSigned, DebugLoc dl);
100 std::pair<SDValue, SDValue> ExpandChainLibCall(RTLIB::Libcall LC,
101 SDNode *Node, bool isSigned);
102 SDValue ExpandFPLibCall(SDNode *Node, RTLIB::Libcall Call_F32,
103 RTLIB::Libcall Call_F64, RTLIB::Libcall Call_F80,
104 RTLIB::Libcall Call_PPCF128);
105 SDValue ExpandIntLibCall(SDNode *Node, bool isSigned,
106 RTLIB::Libcall Call_I8,
107 RTLIB::Libcall Call_I16,
108 RTLIB::Libcall Call_I32,
109 RTLIB::Libcall Call_I64,
110 RTLIB::Libcall Call_I128);
111 void ExpandDivRemLibCall(SDNode *Node, SmallVectorImpl<SDValue> &Results);
113 SDValue EmitStackConvert(SDValue SrcOp, EVT SlotVT, EVT DestVT, DebugLoc dl);
114 SDValue ExpandBUILD_VECTOR(SDNode *Node);
115 SDValue ExpandSCALAR_TO_VECTOR(SDNode *Node);
116 void ExpandDYNAMIC_STACKALLOC(SDNode *Node,
117 SmallVectorImpl<SDValue> &Results);
118 SDValue ExpandFCOPYSIGN(SDNode *Node);
119 SDValue ExpandLegalINT_TO_FP(bool isSigned, SDValue LegalOp, EVT DestVT,
121 SDValue PromoteLegalINT_TO_FP(SDValue LegalOp, EVT DestVT, bool isSigned,
123 SDValue PromoteLegalFP_TO_INT(SDValue LegalOp, EVT DestVT, bool isSigned,
126 SDValue ExpandBSWAP(SDValue Op, DebugLoc dl);
127 SDValue ExpandBitCount(unsigned Opc, SDValue Op, DebugLoc dl);
129 SDValue ExpandExtractFromVectorThroughStack(SDValue Op);
130 SDValue ExpandInsertToVectorThroughStack(SDValue Op);
131 SDValue ExpandVectorBuildThroughStack(SDNode* Node);
133 SDValue ExpandConstantFP(ConstantFPSDNode *CFP, bool UseCP);
135 std::pair<SDValue, SDValue> ExpandAtomic(SDNode *Node);
137 void ExpandNode(SDNode *Node);
138 void PromoteNode(SDNode *Node);
140 void ForgetNode(SDNode *N) {
141 LegalizedNodes.erase(N);
142 if (LegalizePosition == SelectionDAG::allnodes_iterator(N))
147 // DAGUpdateListener implementation.
148 virtual void NodeDeleted(SDNode *N, SDNode *E) {
151 virtual void NodeUpdated(SDNode *N) {}
153 // Node replacement helpers
154 void ReplacedNode(SDNode *N) {
155 if (N->use_empty()) {
156 DAG.RemoveDeadNode(N);
161 void ReplaceNode(SDNode *Old, SDNode *New) {
162 DAG.ReplaceAllUsesWith(Old, New);
165 void ReplaceNode(SDValue Old, SDValue New) {
166 DAG.ReplaceAllUsesWith(Old, New);
167 ReplacedNode(Old.getNode());
169 void ReplaceNode(SDNode *Old, const SDValue *New) {
170 DAG.ReplaceAllUsesWith(Old, New);
176 /// ShuffleWithNarrowerEltType - Return a vector shuffle operation which
177 /// performs the same shuffe in terms of order or result bytes, but on a type
178 /// whose vector element type is narrower than the original shuffle type.
179 /// e.g. <v4i32> <0, 1, 0, 1> -> v8i16 <0, 1, 2, 3, 0, 1, 2, 3>
181 SelectionDAGLegalize::ShuffleWithNarrowerEltType(EVT NVT, EVT VT, DebugLoc dl,
182 SDValue N1, SDValue N2,
183 ArrayRef<int> Mask) const {
184 unsigned NumMaskElts = VT.getVectorNumElements();
185 unsigned NumDestElts = NVT.getVectorNumElements();
186 unsigned NumEltsGrowth = NumDestElts / NumMaskElts;
188 assert(NumEltsGrowth && "Cannot promote to vector type with fewer elts!");
190 if (NumEltsGrowth == 1)
191 return DAG.getVectorShuffle(NVT, dl, N1, N2, &Mask[0]);
193 SmallVector<int, 8> NewMask;
194 for (unsigned i = 0; i != NumMaskElts; ++i) {
196 for (unsigned j = 0; j != NumEltsGrowth; ++j) {
198 NewMask.push_back(-1);
200 NewMask.push_back(Idx * NumEltsGrowth + j);
203 assert(NewMask.size() == NumDestElts && "Non-integer NumEltsGrowth?");
204 assert(TLI.isShuffleMaskLegal(NewMask, NVT) && "Shuffle not legal?");
205 return DAG.getVectorShuffle(NVT, dl, N1, N2, &NewMask[0]);
208 SelectionDAGLegalize::SelectionDAGLegalize(SelectionDAG &dag)
209 : SelectionDAG::DAGUpdateListener(dag),
210 TM(dag.getTarget()), TLI(dag.getTargetLoweringInfo()),
214 void SelectionDAGLegalize::LegalizeDAG() {
215 DAG.AssignTopologicalOrder();
217 // Visit all the nodes. We start in topological order, so that we see
218 // nodes with their original operands intact. Legalization can produce
219 // new nodes which may themselves need to be legalized. Iterate until all
220 // nodes have been legalized.
222 bool AnyLegalized = false;
223 for (LegalizePosition = DAG.allnodes_end();
224 LegalizePosition != DAG.allnodes_begin(); ) {
227 SDNode *N = LegalizePosition;
228 if (LegalizedNodes.insert(N)) {
238 // Remove dead nodes now.
239 DAG.RemoveDeadNodes();
242 /// ExpandConstantFP - Expands the ConstantFP node to an integer constant or
243 /// a load from the constant pool.
245 SelectionDAGLegalize::ExpandConstantFP(ConstantFPSDNode *CFP, bool UseCP) {
247 DebugLoc dl = CFP->getDebugLoc();
249 // If a FP immediate is precise when represented as a float and if the
250 // target can do an extending load from float to double, we put it into
251 // the constant pool as a float, even if it's is statically typed as a
252 // double. This shrinks FP constants and canonicalizes them for targets where
253 // an FP extending load is the same cost as a normal load (such as on the x87
254 // fp stack or PPC FP unit).
255 EVT VT = CFP->getValueType(0);
256 ConstantFP *LLVMC = const_cast<ConstantFP*>(CFP->getConstantFPValue());
258 assert((VT == MVT::f64 || VT == MVT::f32) && "Invalid type expansion");
259 return DAG.getConstant(LLVMC->getValueAPF().bitcastToAPInt(),
260 (VT == MVT::f64) ? MVT::i64 : MVT::i32);
265 while (SVT != MVT::f32) {
266 SVT = (MVT::SimpleValueType)(SVT.getSimpleVT().SimpleTy - 1);
267 if (ConstantFPSDNode::isValueValidForType(SVT, CFP->getValueAPF()) &&
268 // Only do this if the target has a native EXTLOAD instruction from
270 TLI.isLoadExtLegal(ISD::EXTLOAD, SVT) &&
271 TLI.ShouldShrinkFPConstant(OrigVT)) {
272 Type *SType = SVT.getTypeForEVT(*DAG.getContext());
273 LLVMC = cast<ConstantFP>(ConstantExpr::getFPTrunc(LLVMC, SType));
279 SDValue CPIdx = DAG.getConstantPool(LLVMC, TLI.getPointerTy());
280 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
283 DAG.getExtLoad(ISD::EXTLOAD, dl, OrigVT,
285 CPIdx, MachinePointerInfo::getConstantPool(),
286 VT, false, false, Alignment);
290 DAG.getLoad(OrigVT, dl, DAG.getEntryNode(), CPIdx,
291 MachinePointerInfo::getConstantPool(), false, false, false,
296 /// ExpandUnalignedStore - Expands an unaligned store to 2 half-size stores.
297 static void ExpandUnalignedStore(StoreSDNode *ST, SelectionDAG &DAG,
298 const TargetLowering &TLI,
299 SelectionDAGLegalize *DAGLegalize) {
300 assert(ST->getAddressingMode() == ISD::UNINDEXED &&
301 "unaligned indexed stores not implemented!");
302 SDValue Chain = ST->getChain();
303 SDValue Ptr = ST->getBasePtr();
304 SDValue Val = ST->getValue();
305 EVT VT = Val.getValueType();
306 int Alignment = ST->getAlignment();
307 DebugLoc dl = ST->getDebugLoc();
308 if (ST->getMemoryVT().isFloatingPoint() ||
309 ST->getMemoryVT().isVector()) {
310 EVT intVT = EVT::getIntegerVT(*DAG.getContext(), VT.getSizeInBits());
311 if (TLI.isTypeLegal(intVT)) {
312 // Expand to a bitconvert of the value to the integer type of the
313 // same size, then a (misaligned) int store.
314 // FIXME: Does not handle truncating floating point stores!
315 SDValue Result = DAG.getNode(ISD::BITCAST, dl, intVT, Val);
316 Result = DAG.getStore(Chain, dl, Result, Ptr, ST->getPointerInfo(),
317 ST->isVolatile(), ST->isNonTemporal(), Alignment);
318 DAGLegalize->ReplaceNode(SDValue(ST, 0), Result);
321 // Do a (aligned) store to a stack slot, then copy from the stack slot
322 // to the final destination using (unaligned) integer loads and stores.
323 EVT StoredVT = ST->getMemoryVT();
325 TLI.getRegisterType(*DAG.getContext(),
326 EVT::getIntegerVT(*DAG.getContext(),
327 StoredVT.getSizeInBits()));
328 unsigned StoredBytes = StoredVT.getSizeInBits() / 8;
329 unsigned RegBytes = RegVT.getSizeInBits() / 8;
330 unsigned NumRegs = (StoredBytes + RegBytes - 1) / RegBytes;
332 // Make sure the stack slot is also aligned for the register type.
333 SDValue StackPtr = DAG.CreateStackTemporary(StoredVT, RegVT);
335 // Perform the original store, only redirected to the stack slot.
336 SDValue Store = DAG.getTruncStore(Chain, dl,
337 Val, StackPtr, MachinePointerInfo(),
338 StoredVT, false, false, 0);
339 SDValue Increment = DAG.getConstant(RegBytes, TLI.getPointerTy());
340 SmallVector<SDValue, 8> Stores;
343 // Do all but one copies using the full register width.
344 for (unsigned i = 1; i < NumRegs; i++) {
345 // Load one integer register's worth from the stack slot.
346 SDValue Load = DAG.getLoad(RegVT, dl, Store, StackPtr,
347 MachinePointerInfo(),
348 false, false, false, 0);
349 // Store it to the final location. Remember the store.
350 Stores.push_back(DAG.getStore(Load.getValue(1), dl, Load, Ptr,
351 ST->getPointerInfo().getWithOffset(Offset),
352 ST->isVolatile(), ST->isNonTemporal(),
353 MinAlign(ST->getAlignment(), Offset)));
354 // Increment the pointers.
356 StackPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr,
358 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
361 // The last store may be partial. Do a truncating store. On big-endian
362 // machines this requires an extending load from the stack slot to ensure
363 // that the bits are in the right place.
364 EVT MemVT = EVT::getIntegerVT(*DAG.getContext(),
365 8 * (StoredBytes - Offset));
367 // Load from the stack slot.
368 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, RegVT, Store, StackPtr,
369 MachinePointerInfo(),
370 MemVT, false, false, 0);
372 Stores.push_back(DAG.getTruncStore(Load.getValue(1), dl, Load, Ptr,
374 .getWithOffset(Offset),
375 MemVT, ST->isVolatile(),
377 MinAlign(ST->getAlignment(), Offset)));
378 // The order of the stores doesn't matter - say it with a TokenFactor.
380 DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Stores[0],
382 DAGLegalize->ReplaceNode(SDValue(ST, 0), Result);
385 assert(ST->getMemoryVT().isInteger() &&
386 !ST->getMemoryVT().isVector() &&
387 "Unaligned store of unknown type.");
388 // Get the half-size VT
389 EVT NewStoredVT = ST->getMemoryVT().getHalfSizedIntegerVT(*DAG.getContext());
390 int NumBits = NewStoredVT.getSizeInBits();
391 int IncrementSize = NumBits / 8;
393 // Divide the stored value in two parts.
394 SDValue ShiftAmount = DAG.getConstant(NumBits,
395 TLI.getShiftAmountTy(Val.getValueType()));
397 SDValue Hi = DAG.getNode(ISD::SRL, dl, VT, Val, ShiftAmount);
399 // Store the two parts
400 SDValue Store1, Store2;
401 Store1 = DAG.getTruncStore(Chain, dl, TLI.isLittleEndian()?Lo:Hi, Ptr,
402 ST->getPointerInfo(), NewStoredVT,
403 ST->isVolatile(), ST->isNonTemporal(), Alignment);
404 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
405 DAG.getConstant(IncrementSize, TLI.getPointerTy()));
406 Alignment = MinAlign(Alignment, IncrementSize);
407 Store2 = DAG.getTruncStore(Chain, dl, TLI.isLittleEndian()?Hi:Lo, Ptr,
408 ST->getPointerInfo().getWithOffset(IncrementSize),
409 NewStoredVT, ST->isVolatile(), ST->isNonTemporal(),
413 DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Store1, Store2);
414 DAGLegalize->ReplaceNode(SDValue(ST, 0), Result);
417 /// ExpandUnalignedLoad - Expands an unaligned load to 2 half-size loads.
419 ExpandUnalignedLoad(LoadSDNode *LD, SelectionDAG &DAG,
420 const TargetLowering &TLI,
421 SDValue &ValResult, SDValue &ChainResult) {
422 assert(LD->getAddressingMode() == ISD::UNINDEXED &&
423 "unaligned indexed loads not implemented!");
424 SDValue Chain = LD->getChain();
425 SDValue Ptr = LD->getBasePtr();
426 EVT VT = LD->getValueType(0);
427 EVT LoadedVT = LD->getMemoryVT();
428 DebugLoc dl = LD->getDebugLoc();
429 if (VT.isFloatingPoint() || VT.isVector()) {
430 EVT intVT = EVT::getIntegerVT(*DAG.getContext(), LoadedVT.getSizeInBits());
431 if (TLI.isTypeLegal(intVT) && TLI.isTypeLegal(LoadedVT)) {
432 // Expand to a (misaligned) integer load of the same size,
433 // then bitconvert to floating point or vector.
434 SDValue newLoad = DAG.getLoad(intVT, dl, Chain, Ptr, LD->getPointerInfo(),
437 LD->isInvariant(), LD->getAlignment());
438 SDValue Result = DAG.getNode(ISD::BITCAST, dl, LoadedVT, newLoad);
440 Result = DAG.getNode(VT.isFloatingPoint() ? ISD::FP_EXTEND :
441 ISD::ANY_EXTEND, dl, VT, Result);
448 // Copy the value to a (aligned) stack slot using (unaligned) integer
449 // loads and stores, then do a (aligned) load from the stack slot.
450 EVT RegVT = TLI.getRegisterType(*DAG.getContext(), intVT);
451 unsigned LoadedBytes = LoadedVT.getSizeInBits() / 8;
452 unsigned RegBytes = RegVT.getSizeInBits() / 8;
453 unsigned NumRegs = (LoadedBytes + RegBytes - 1) / RegBytes;
455 // Make sure the stack slot is also aligned for the register type.
456 SDValue StackBase = DAG.CreateStackTemporary(LoadedVT, RegVT);
458 SDValue Increment = DAG.getConstant(RegBytes, TLI.getPointerTy());
459 SmallVector<SDValue, 8> Stores;
460 SDValue StackPtr = StackBase;
463 // Do all but one copies using the full register width.
464 for (unsigned i = 1; i < NumRegs; i++) {
465 // Load one integer register's worth from the original location.
466 SDValue Load = DAG.getLoad(RegVT, dl, Chain, Ptr,
467 LD->getPointerInfo().getWithOffset(Offset),
468 LD->isVolatile(), LD->isNonTemporal(),
470 MinAlign(LD->getAlignment(), Offset));
471 // Follow the load with a store to the stack slot. Remember the store.
472 Stores.push_back(DAG.getStore(Load.getValue(1), dl, Load, StackPtr,
473 MachinePointerInfo(), false, false, 0));
474 // Increment the pointers.
476 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
477 StackPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr,
481 // The last copy may be partial. Do an extending load.
482 EVT MemVT = EVT::getIntegerVT(*DAG.getContext(),
483 8 * (LoadedBytes - Offset));
484 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, RegVT, Chain, Ptr,
485 LD->getPointerInfo().getWithOffset(Offset),
486 MemVT, LD->isVolatile(),
488 MinAlign(LD->getAlignment(), Offset));
489 // Follow the load with a store to the stack slot. Remember the store.
490 // On big-endian machines this requires a truncating store to ensure
491 // that the bits end up in the right place.
492 Stores.push_back(DAG.getTruncStore(Load.getValue(1), dl, Load, StackPtr,
493 MachinePointerInfo(), MemVT,
496 // The order of the stores doesn't matter - say it with a TokenFactor.
497 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Stores[0],
500 // Finally, perform the original load only redirected to the stack slot.
501 Load = DAG.getExtLoad(LD->getExtensionType(), dl, VT, TF, StackBase,
502 MachinePointerInfo(), LoadedVT, false, false, 0);
504 // Callers expect a MERGE_VALUES node.
509 assert(LoadedVT.isInteger() && !LoadedVT.isVector() &&
510 "Unaligned load of unsupported type.");
512 // Compute the new VT that is half the size of the old one. This is an
514 unsigned NumBits = LoadedVT.getSizeInBits();
516 NewLoadedVT = EVT::getIntegerVT(*DAG.getContext(), NumBits/2);
519 unsigned Alignment = LD->getAlignment();
520 unsigned IncrementSize = NumBits / 8;
521 ISD::LoadExtType HiExtType = LD->getExtensionType();
523 // If the original load is NON_EXTLOAD, the hi part load must be ZEXTLOAD.
524 if (HiExtType == ISD::NON_EXTLOAD)
525 HiExtType = ISD::ZEXTLOAD;
527 // Load the value in two parts
529 if (TLI.isLittleEndian()) {
530 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, VT, Chain, Ptr, LD->getPointerInfo(),
531 NewLoadedVT, LD->isVolatile(),
532 LD->isNonTemporal(), Alignment);
533 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
534 DAG.getConstant(IncrementSize, TLI.getPointerTy()));
535 Hi = DAG.getExtLoad(HiExtType, dl, VT, Chain, Ptr,
536 LD->getPointerInfo().getWithOffset(IncrementSize),
537 NewLoadedVT, LD->isVolatile(),
538 LD->isNonTemporal(), MinAlign(Alignment,IncrementSize));
540 Hi = DAG.getExtLoad(HiExtType, dl, VT, Chain, Ptr, LD->getPointerInfo(),
541 NewLoadedVT, LD->isVolatile(),
542 LD->isNonTemporal(), Alignment);
543 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
544 DAG.getConstant(IncrementSize, TLI.getPointerTy()));
545 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, VT, Chain, Ptr,
546 LD->getPointerInfo().getWithOffset(IncrementSize),
547 NewLoadedVT, LD->isVolatile(),
548 LD->isNonTemporal(), MinAlign(Alignment,IncrementSize));
551 // aggregate the two parts
552 SDValue ShiftAmount = DAG.getConstant(NumBits,
553 TLI.getShiftAmountTy(Hi.getValueType()));
554 SDValue Result = DAG.getNode(ISD::SHL, dl, VT, Hi, ShiftAmount);
555 Result = DAG.getNode(ISD::OR, dl, VT, Result, Lo);
557 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
564 /// PerformInsertVectorEltInMemory - Some target cannot handle a variable
565 /// insertion index for the INSERT_VECTOR_ELT instruction. In this case, it
566 /// is necessary to spill the vector being inserted into to memory, perform
567 /// the insert there, and then read the result back.
568 SDValue SelectionDAGLegalize::
569 PerformInsertVectorEltInMemory(SDValue Vec, SDValue Val, SDValue Idx,
575 // If the target doesn't support this, we have to spill the input vector
576 // to a temporary stack slot, update the element, then reload it. This is
577 // badness. We could also load the value into a vector register (either
578 // with a "move to register" or "extload into register" instruction, then
579 // permute it into place, if the idx is a constant and if the idx is
580 // supported by the target.
581 EVT VT = Tmp1.getValueType();
582 EVT EltVT = VT.getVectorElementType();
583 EVT IdxVT = Tmp3.getValueType();
584 EVT PtrVT = TLI.getPointerTy();
585 SDValue StackPtr = DAG.CreateStackTemporary(VT);
587 int SPFI = cast<FrameIndexSDNode>(StackPtr.getNode())->getIndex();
590 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, Tmp1, StackPtr,
591 MachinePointerInfo::getFixedStack(SPFI),
594 // Truncate or zero extend offset to target pointer type.
595 unsigned CastOpc = IdxVT.bitsGT(PtrVT) ? ISD::TRUNCATE : ISD::ZERO_EXTEND;
596 Tmp3 = DAG.getNode(CastOpc, dl, PtrVT, Tmp3);
597 // Add the offset to the index.
598 unsigned EltSize = EltVT.getSizeInBits()/8;
599 Tmp3 = DAG.getNode(ISD::MUL, dl, IdxVT, Tmp3,DAG.getConstant(EltSize, IdxVT));
600 SDValue StackPtr2 = DAG.getNode(ISD::ADD, dl, IdxVT, Tmp3, StackPtr);
601 // Store the scalar value.
602 Ch = DAG.getTruncStore(Ch, dl, Tmp2, StackPtr2, MachinePointerInfo(), EltVT,
604 // Load the updated vector.
605 return DAG.getLoad(VT, dl, Ch, StackPtr,
606 MachinePointerInfo::getFixedStack(SPFI), false, false,
611 SDValue SelectionDAGLegalize::
612 ExpandINSERT_VECTOR_ELT(SDValue Vec, SDValue Val, SDValue Idx, DebugLoc dl) {
613 if (ConstantSDNode *InsertPos = dyn_cast<ConstantSDNode>(Idx)) {
614 // SCALAR_TO_VECTOR requires that the type of the value being inserted
615 // match the element type of the vector being created, except for
616 // integers in which case the inserted value can be over width.
617 EVT EltVT = Vec.getValueType().getVectorElementType();
618 if (Val.getValueType() == EltVT ||
619 (EltVT.isInteger() && Val.getValueType().bitsGE(EltVT))) {
620 SDValue ScVec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
621 Vec.getValueType(), Val);
623 unsigned NumElts = Vec.getValueType().getVectorNumElements();
624 // We generate a shuffle of InVec and ScVec, so the shuffle mask
625 // should be 0,1,2,3,4,5... with the appropriate element replaced with
627 SmallVector<int, 8> ShufOps;
628 for (unsigned i = 0; i != NumElts; ++i)
629 ShufOps.push_back(i != InsertPos->getZExtValue() ? i : NumElts);
631 return DAG.getVectorShuffle(Vec.getValueType(), dl, Vec, ScVec,
635 return PerformInsertVectorEltInMemory(Vec, Val, Idx, dl);
638 SDValue SelectionDAGLegalize::OptimizeFloatStore(StoreSDNode* ST) {
639 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr'
640 // FIXME: We shouldn't do this for TargetConstantFP's.
641 // FIXME: move this to the DAG Combiner! Note that we can't regress due
642 // to phase ordering between legalized code and the dag combiner. This
643 // probably means that we need to integrate dag combiner and legalizer
645 // We generally can't do this one for long doubles.
646 SDValue Chain = ST->getChain();
647 SDValue Ptr = ST->getBasePtr();
648 unsigned Alignment = ST->getAlignment();
649 bool isVolatile = ST->isVolatile();
650 bool isNonTemporal = ST->isNonTemporal();
651 DebugLoc dl = ST->getDebugLoc();
652 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(ST->getValue())) {
653 if (CFP->getValueType(0) == MVT::f32 &&
654 TLI.isTypeLegal(MVT::i32)) {
655 SDValue Con = DAG.getConstant(CFP->getValueAPF().
656 bitcastToAPInt().zextOrTrunc(32),
658 return DAG.getStore(Chain, dl, Con, Ptr, ST->getPointerInfo(),
659 isVolatile, isNonTemporal, Alignment);
662 if (CFP->getValueType(0) == MVT::f64) {
663 // If this target supports 64-bit registers, do a single 64-bit store.
664 if (TLI.isTypeLegal(MVT::i64)) {
665 SDValue Con = DAG.getConstant(CFP->getValueAPF().bitcastToAPInt().
666 zextOrTrunc(64), MVT::i64);
667 return DAG.getStore(Chain, dl, Con, Ptr, ST->getPointerInfo(),
668 isVolatile, isNonTemporal, Alignment);
671 if (TLI.isTypeLegal(MVT::i32) && !ST->isVolatile()) {
672 // Otherwise, if the target supports 32-bit registers, use 2 32-bit
673 // stores. If the target supports neither 32- nor 64-bits, this
674 // xform is certainly not worth it.
675 const APInt &IntVal =CFP->getValueAPF().bitcastToAPInt();
676 SDValue Lo = DAG.getConstant(IntVal.trunc(32), MVT::i32);
677 SDValue Hi = DAG.getConstant(IntVal.lshr(32).trunc(32), MVT::i32);
678 if (TLI.isBigEndian()) std::swap(Lo, Hi);
680 Lo = DAG.getStore(Chain, dl, Lo, Ptr, ST->getPointerInfo(), isVolatile,
681 isNonTemporal, Alignment);
682 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
683 DAG.getIntPtrConstant(4));
684 Hi = DAG.getStore(Chain, dl, Hi, Ptr,
685 ST->getPointerInfo().getWithOffset(4),
686 isVolatile, isNonTemporal, MinAlign(Alignment, 4U));
688 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi);
692 return SDValue(0, 0);
695 void SelectionDAGLegalize::LegalizeStoreOps(SDNode *Node) {
696 StoreSDNode *ST = cast<StoreSDNode>(Node);
697 SDValue Chain = ST->getChain();
698 SDValue Ptr = ST->getBasePtr();
699 DebugLoc dl = Node->getDebugLoc();
701 unsigned Alignment = ST->getAlignment();
702 bool isVolatile = ST->isVolatile();
703 bool isNonTemporal = ST->isNonTemporal();
705 if (!ST->isTruncatingStore()) {
706 if (SDNode *OptStore = OptimizeFloatStore(ST).getNode()) {
707 ReplaceNode(ST, OptStore);
712 SDValue Value = ST->getValue();
713 EVT VT = Value.getValueType();
714 switch (TLI.getOperationAction(ISD::STORE, VT)) {
715 default: llvm_unreachable("This action is not supported yet!");
716 case TargetLowering::Legal:
717 // If this is an unaligned store and the target doesn't support it,
719 if (!TLI.allowsUnalignedMemoryAccesses(ST->getMemoryVT())) {
720 Type *Ty = ST->getMemoryVT().getTypeForEVT(*DAG.getContext());
721 unsigned ABIAlignment= TLI.getDataLayout()->getABITypeAlignment(Ty);
722 if (ST->getAlignment() < ABIAlignment)
723 ExpandUnalignedStore(cast<StoreSDNode>(Node),
727 case TargetLowering::Custom: {
728 SDValue Res = TLI.LowerOperation(SDValue(Node, 0), DAG);
730 ReplaceNode(SDValue(Node, 0), Res);
733 case TargetLowering::Promote: {
734 assert(VT.isVector() && "Unknown legal promote case!");
735 Value = DAG.getNode(ISD::BITCAST, dl,
736 TLI.getTypeToPromoteTo(ISD::STORE, VT), Value);
738 DAG.getStore(Chain, dl, Value, Ptr,
739 ST->getPointerInfo(), isVolatile,
740 isNonTemporal, Alignment);
741 ReplaceNode(SDValue(Node, 0), Result);
748 SDValue Value = ST->getValue();
750 EVT StVT = ST->getMemoryVT();
751 unsigned StWidth = StVT.getSizeInBits();
753 if (StWidth != StVT.getStoreSizeInBits()) {
754 // Promote to a byte-sized store with upper bits zero if not
755 // storing an integral number of bytes. For example, promote
756 // TRUNCSTORE:i1 X -> TRUNCSTORE:i8 (and X, 1)
757 EVT NVT = EVT::getIntegerVT(*DAG.getContext(),
758 StVT.getStoreSizeInBits());
759 Value = DAG.getZeroExtendInReg(Value, dl, StVT);
761 DAG.getTruncStore(Chain, dl, Value, Ptr, ST->getPointerInfo(),
762 NVT, isVolatile, isNonTemporal, Alignment);
763 ReplaceNode(SDValue(Node, 0), Result);
764 } else if (StWidth & (StWidth - 1)) {
765 // If not storing a power-of-2 number of bits, expand as two stores.
766 assert(!StVT.isVector() && "Unsupported truncstore!");
767 unsigned RoundWidth = 1 << Log2_32(StWidth);
768 assert(RoundWidth < StWidth);
769 unsigned ExtraWidth = StWidth - RoundWidth;
770 assert(ExtraWidth < RoundWidth);
771 assert(!(RoundWidth % 8) && !(ExtraWidth % 8) &&
772 "Store size not an integral number of bytes!");
773 EVT RoundVT = EVT::getIntegerVT(*DAG.getContext(), RoundWidth);
774 EVT ExtraVT = EVT::getIntegerVT(*DAG.getContext(), ExtraWidth);
776 unsigned IncrementSize;
778 if (TLI.isLittleEndian()) {
779 // TRUNCSTORE:i24 X -> TRUNCSTORE:i16 X, TRUNCSTORE@+2:i8 (srl X, 16)
780 // Store the bottom RoundWidth bits.
781 Lo = DAG.getTruncStore(Chain, dl, Value, Ptr, ST->getPointerInfo(),
783 isVolatile, isNonTemporal, Alignment);
785 // Store the remaining ExtraWidth bits.
786 IncrementSize = RoundWidth / 8;
787 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
788 DAG.getIntPtrConstant(IncrementSize));
789 Hi = DAG.getNode(ISD::SRL, dl, Value.getValueType(), Value,
790 DAG.getConstant(RoundWidth,
791 TLI.getShiftAmountTy(Value.getValueType())));
792 Hi = DAG.getTruncStore(Chain, dl, Hi, Ptr,
793 ST->getPointerInfo().getWithOffset(IncrementSize),
794 ExtraVT, isVolatile, isNonTemporal,
795 MinAlign(Alignment, IncrementSize));
797 // Big endian - avoid unaligned stores.
798 // TRUNCSTORE:i24 X -> TRUNCSTORE:i16 (srl X, 8), TRUNCSTORE@+2:i8 X
799 // Store the top RoundWidth bits.
800 Hi = DAG.getNode(ISD::SRL, dl, Value.getValueType(), Value,
801 DAG.getConstant(ExtraWidth,
802 TLI.getShiftAmountTy(Value.getValueType())));
803 Hi = DAG.getTruncStore(Chain, dl, Hi, Ptr, ST->getPointerInfo(),
804 RoundVT, isVolatile, isNonTemporal, Alignment);
806 // Store the remaining ExtraWidth bits.
807 IncrementSize = RoundWidth / 8;
808 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
809 DAG.getIntPtrConstant(IncrementSize));
810 Lo = DAG.getTruncStore(Chain, dl, Value, Ptr,
811 ST->getPointerInfo().getWithOffset(IncrementSize),
812 ExtraVT, isVolatile, isNonTemporal,
813 MinAlign(Alignment, IncrementSize));
816 // The order of the stores doesn't matter.
817 SDValue Result = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi);
818 ReplaceNode(SDValue(Node, 0), Result);
820 switch (TLI.getTruncStoreAction(ST->getValue().getValueType(), StVT)) {
821 default: llvm_unreachable("This action is not supported yet!");
822 case TargetLowering::Legal:
823 // If this is an unaligned store and the target doesn't support it,
825 if (!TLI.allowsUnalignedMemoryAccesses(ST->getMemoryVT())) {
826 Type *Ty = ST->getMemoryVT().getTypeForEVT(*DAG.getContext());
827 unsigned ABIAlignment= TLI.getDataLayout()->getABITypeAlignment(Ty);
828 if (ST->getAlignment() < ABIAlignment)
829 ExpandUnalignedStore(cast<StoreSDNode>(Node), DAG, TLI, this);
832 case TargetLowering::Custom: {
833 SDValue Res = TLI.LowerOperation(SDValue(Node, 0), DAG);
835 ReplaceNode(SDValue(Node, 0), Res);
838 case TargetLowering::Expand:
839 assert(!StVT.isVector() &&
840 "Vector Stores are handled in LegalizeVectorOps");
842 // TRUNCSTORE:i16 i32 -> STORE i16
843 assert(TLI.isTypeLegal(StVT) &&
844 "Do not know how to expand this store!");
845 Value = DAG.getNode(ISD::TRUNCATE, dl, StVT, Value);
847 DAG.getStore(Chain, dl, Value, Ptr, ST->getPointerInfo(),
848 isVolatile, isNonTemporal, Alignment);
849 ReplaceNode(SDValue(Node, 0), Result);
856 void SelectionDAGLegalize::LegalizeLoadOps(SDNode *Node) {
857 LoadSDNode *LD = cast<LoadSDNode>(Node);
858 SDValue Chain = LD->getChain(); // The chain.
859 SDValue Ptr = LD->getBasePtr(); // The base pointer.
860 SDValue Value; // The value returned by the load op.
861 DebugLoc dl = Node->getDebugLoc();
863 ISD::LoadExtType ExtType = LD->getExtensionType();
864 if (ExtType == ISD::NON_EXTLOAD) {
865 EVT VT = Node->getValueType(0);
866 SDValue RVal = SDValue(Node, 0);
867 SDValue RChain = SDValue(Node, 1);
869 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
870 default: llvm_unreachable("This action is not supported yet!");
871 case TargetLowering::Legal:
872 // If this is an unaligned load and the target doesn't support it,
874 if (!TLI.allowsUnalignedMemoryAccesses(LD->getMemoryVT())) {
875 Type *Ty = LD->getMemoryVT().getTypeForEVT(*DAG.getContext());
876 unsigned ABIAlignment =
877 TLI.getDataLayout()->getABITypeAlignment(Ty);
878 if (LD->getAlignment() < ABIAlignment){
879 ExpandUnalignedLoad(cast<LoadSDNode>(Node), DAG, TLI, RVal, RChain);
883 case TargetLowering::Custom: {
884 SDValue Res = TLI.LowerOperation(RVal, DAG);
887 RChain = Res.getValue(1);
891 case TargetLowering::Promote: {
892 // Only promote a load of vector type to another.
893 assert(VT.isVector() && "Cannot promote this load!");
894 // Change base type to a different vector type.
895 EVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), VT);
897 SDValue Res = DAG.getLoad(NVT, dl, Chain, Ptr, LD->getPointerInfo(),
898 LD->isVolatile(), LD->isNonTemporal(),
899 LD->isInvariant(), LD->getAlignment());
900 RVal = DAG.getNode(ISD::BITCAST, dl, VT, Res);
901 RChain = Res.getValue(1);
905 if (RChain.getNode() != Node) {
906 assert(RVal.getNode() != Node && "Load must be completely replaced");
907 DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 0), RVal);
908 DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 1), RChain);
914 EVT SrcVT = LD->getMemoryVT();
915 unsigned SrcWidth = SrcVT.getSizeInBits();
916 unsigned Alignment = LD->getAlignment();
917 bool isVolatile = LD->isVolatile();
918 bool isNonTemporal = LD->isNonTemporal();
920 if (SrcWidth != SrcVT.getStoreSizeInBits() &&
921 // Some targets pretend to have an i1 loading operation, and actually
922 // load an i8. This trick is correct for ZEXTLOAD because the top 7
923 // bits are guaranteed to be zero; it helps the optimizers understand
924 // that these bits are zero. It is also useful for EXTLOAD, since it
925 // tells the optimizers that those bits are undefined. It would be
926 // nice to have an effective generic way of getting these benefits...
927 // Until such a way is found, don't insist on promoting i1 here.
929 TLI.getLoadExtAction(ExtType, MVT::i1) == TargetLowering::Promote)) {
930 // Promote to a byte-sized load if not loading an integral number of
931 // bytes. For example, promote EXTLOAD:i20 -> EXTLOAD:i24.
932 unsigned NewWidth = SrcVT.getStoreSizeInBits();
933 EVT NVT = EVT::getIntegerVT(*DAG.getContext(), NewWidth);
936 // The extra bits are guaranteed to be zero, since we stored them that
937 // way. A zext load from NVT thus automatically gives zext from SrcVT.
939 ISD::LoadExtType NewExtType =
940 ExtType == ISD::ZEXTLOAD ? ISD::ZEXTLOAD : ISD::EXTLOAD;
943 DAG.getExtLoad(NewExtType, dl, Node->getValueType(0),
944 Chain, Ptr, LD->getPointerInfo(),
945 NVT, isVolatile, isNonTemporal, Alignment);
947 Ch = Result.getValue(1); // The chain.
949 if (ExtType == ISD::SEXTLOAD)
950 // Having the top bits zero doesn't help when sign extending.
951 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl,
952 Result.getValueType(),
953 Result, DAG.getValueType(SrcVT));
954 else if (ExtType == ISD::ZEXTLOAD || NVT == Result.getValueType())
955 // All the top bits are guaranteed to be zero - inform the optimizers.
956 Result = DAG.getNode(ISD::AssertZext, dl,
957 Result.getValueType(), Result,
958 DAG.getValueType(SrcVT));
962 } else if (SrcWidth & (SrcWidth - 1)) {
963 // If not loading a power-of-2 number of bits, expand as two loads.
964 assert(!SrcVT.isVector() && "Unsupported extload!");
965 unsigned RoundWidth = 1 << Log2_32(SrcWidth);
966 assert(RoundWidth < SrcWidth);
967 unsigned ExtraWidth = SrcWidth - RoundWidth;
968 assert(ExtraWidth < RoundWidth);
969 assert(!(RoundWidth % 8) && !(ExtraWidth % 8) &&
970 "Load size not an integral number of bytes!");
971 EVT RoundVT = EVT::getIntegerVT(*DAG.getContext(), RoundWidth);
972 EVT ExtraVT = EVT::getIntegerVT(*DAG.getContext(), ExtraWidth);
974 unsigned IncrementSize;
976 if (TLI.isLittleEndian()) {
977 // EXTLOAD:i24 -> ZEXTLOAD:i16 | (shl EXTLOAD@+2:i8, 16)
978 // Load the bottom RoundWidth bits.
979 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, Node->getValueType(0),
981 LD->getPointerInfo(), RoundVT, isVolatile,
982 isNonTemporal, Alignment);
984 // Load the remaining ExtraWidth bits.
985 IncrementSize = RoundWidth / 8;
986 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
987 DAG.getIntPtrConstant(IncrementSize));
988 Hi = DAG.getExtLoad(ExtType, dl, Node->getValueType(0), Chain, Ptr,
989 LD->getPointerInfo().getWithOffset(IncrementSize),
990 ExtraVT, isVolatile, isNonTemporal,
991 MinAlign(Alignment, IncrementSize));
993 // Build a factor node to remember that this load is independent of
995 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
998 // Move the top bits to the right place.
999 Hi = DAG.getNode(ISD::SHL, dl, Hi.getValueType(), Hi,
1000 DAG.getConstant(RoundWidth,
1001 TLI.getShiftAmountTy(Hi.getValueType())));
1003 // Join the hi and lo parts.
1004 Value = DAG.getNode(ISD::OR, dl, Node->getValueType(0), Lo, Hi);
1006 // Big endian - avoid unaligned loads.
1007 // EXTLOAD:i24 -> (shl EXTLOAD:i16, 8) | ZEXTLOAD@+2:i8
1008 // Load the top RoundWidth bits.
1009 Hi = DAG.getExtLoad(ExtType, dl, Node->getValueType(0), Chain, Ptr,
1010 LD->getPointerInfo(), RoundVT, isVolatile,
1011 isNonTemporal, Alignment);
1013 // Load the remaining ExtraWidth bits.
1014 IncrementSize = RoundWidth / 8;
1015 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
1016 DAG.getIntPtrConstant(IncrementSize));
1017 Lo = DAG.getExtLoad(ISD::ZEXTLOAD,
1018 dl, Node->getValueType(0), Chain, Ptr,
1019 LD->getPointerInfo().getWithOffset(IncrementSize),
1020 ExtraVT, isVolatile, isNonTemporal,
1021 MinAlign(Alignment, IncrementSize));
1023 // Build a factor node to remember that this load is independent of
1025 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
1028 // Move the top bits to the right place.
1029 Hi = DAG.getNode(ISD::SHL, dl, Hi.getValueType(), Hi,
1030 DAG.getConstant(ExtraWidth,
1031 TLI.getShiftAmountTy(Hi.getValueType())));
1033 // Join the hi and lo parts.
1034 Value = DAG.getNode(ISD::OR, dl, Node->getValueType(0), Lo, Hi);
1039 bool isCustom = false;
1040 switch (TLI.getLoadExtAction(ExtType, SrcVT)) {
1041 default: llvm_unreachable("This action is not supported yet!");
1042 case TargetLowering::Custom:
1045 case TargetLowering::Legal: {
1046 Value = SDValue(Node, 0);
1047 Chain = SDValue(Node, 1);
1050 SDValue Res = TLI.LowerOperation(SDValue(Node, 0), DAG);
1051 if (Res.getNode()) {
1053 Chain = Res.getValue(1);
1056 // If this is an unaligned load and the target doesn't support it,
1058 if (!TLI.allowsUnalignedMemoryAccesses(LD->getMemoryVT())) {
1060 LD->getMemoryVT().getTypeForEVT(*DAG.getContext());
1061 unsigned ABIAlignment =
1062 TLI.getDataLayout()->getABITypeAlignment(Ty);
1063 if (LD->getAlignment() < ABIAlignment){
1064 ExpandUnalignedLoad(cast<LoadSDNode>(Node),
1065 DAG, TLI, Value, Chain);
1071 case TargetLowering::Expand:
1072 if (!TLI.isLoadExtLegal(ISD::EXTLOAD, SrcVT) && TLI.isTypeLegal(SrcVT)) {
1073 SDValue Load = DAG.getLoad(SrcVT, dl, Chain, Ptr,
1074 LD->getPointerInfo(),
1075 LD->isVolatile(), LD->isNonTemporal(),
1076 LD->isInvariant(), LD->getAlignment());
1080 ExtendOp = (SrcVT.isFloatingPoint() ?
1081 ISD::FP_EXTEND : ISD::ANY_EXTEND);
1083 case ISD::SEXTLOAD: ExtendOp = ISD::SIGN_EXTEND; break;
1084 case ISD::ZEXTLOAD: ExtendOp = ISD::ZERO_EXTEND; break;
1085 default: llvm_unreachable("Unexpected extend load type!");
1087 Value = DAG.getNode(ExtendOp, dl, Node->getValueType(0), Load);
1088 Chain = Load.getValue(1);
1092 assert(!SrcVT.isVector() &&
1093 "Vector Loads are handled in LegalizeVectorOps");
1095 // FIXME: This does not work for vectors on most targets. Sign- and
1096 // zero-extend operations are currently folded into extending loads,
1097 // whether they are legal or not, and then we end up here without any
1098 // support for legalizing them.
1099 assert(ExtType != ISD::EXTLOAD &&
1100 "EXTLOAD should always be supported!");
1101 // Turn the unsupported load into an EXTLOAD followed by an explicit
1102 // zero/sign extend inreg.
1103 SDValue Result = DAG.getExtLoad(ISD::EXTLOAD, dl, Node->getValueType(0),
1104 Chain, Ptr, LD->getPointerInfo(), SrcVT,
1105 LD->isVolatile(), LD->isNonTemporal(),
1106 LD->getAlignment());
1108 if (ExtType == ISD::SEXTLOAD)
1109 ValRes = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl,
1110 Result.getValueType(),
1111 Result, DAG.getValueType(SrcVT));
1113 ValRes = DAG.getZeroExtendInReg(Result, dl, SrcVT.getScalarType());
1115 Chain = Result.getValue(1);
1120 // Since loads produce two values, make sure to remember that we legalized
1122 if (Chain.getNode() != Node) {
1123 assert(Value.getNode() != Node && "Load must be completely replaced");
1124 DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 0), Value);
1125 DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 1), Chain);
1130 /// LegalizeOp - Return a legal replacement for the given operation, with
1131 /// all legal operands.
1132 void SelectionDAGLegalize::LegalizeOp(SDNode *Node) {
1133 if (Node->getOpcode() == ISD::TargetConstant) // Allow illegal target nodes.
1136 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
1137 assert(TLI.getTypeAction(*DAG.getContext(), Node->getValueType(i)) ==
1138 TargetLowering::TypeLegal &&
1139 "Unexpected illegal type!");
1141 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
1142 assert((TLI.getTypeAction(*DAG.getContext(),
1143 Node->getOperand(i).getValueType()) ==
1144 TargetLowering::TypeLegal ||
1145 Node->getOperand(i).getOpcode() == ISD::TargetConstant) &&
1146 "Unexpected illegal type!");
1148 // Figure out the correct action; the way to query this varies by opcode
1149 TargetLowering::LegalizeAction Action = TargetLowering::Legal;
1150 bool SimpleFinishLegalizing = true;
1151 switch (Node->getOpcode()) {
1152 case ISD::INTRINSIC_W_CHAIN:
1153 case ISD::INTRINSIC_WO_CHAIN:
1154 case ISD::INTRINSIC_VOID:
1155 case ISD::STACKSAVE:
1156 Action = TLI.getOperationAction(Node->getOpcode(), MVT::Other);
1159 Action = TLI.getOperationAction(Node->getOpcode(),
1160 Node->getValueType(0));
1161 if (Action != TargetLowering::Promote)
1162 Action = TLI.getOperationAction(Node->getOpcode(), MVT::Other);
1164 case ISD::SINT_TO_FP:
1165 case ISD::UINT_TO_FP:
1166 case ISD::EXTRACT_VECTOR_ELT:
1167 Action = TLI.getOperationAction(Node->getOpcode(),
1168 Node->getOperand(0).getValueType());
1170 case ISD::FP_ROUND_INREG:
1171 case ISD::SIGN_EXTEND_INREG: {
1172 EVT InnerType = cast<VTSDNode>(Node->getOperand(1))->getVT();
1173 Action = TLI.getOperationAction(Node->getOpcode(), InnerType);
1176 case ISD::ATOMIC_STORE: {
1177 Action = TLI.getOperationAction(Node->getOpcode(),
1178 Node->getOperand(2).getValueType());
1181 case ISD::SELECT_CC:
1184 unsigned CCOperand = Node->getOpcode() == ISD::SELECT_CC ? 4 :
1185 Node->getOpcode() == ISD::SETCC ? 2 : 1;
1186 unsigned CompareOperand = Node->getOpcode() == ISD::BR_CC ? 2 : 0;
1187 EVT OpVT = Node->getOperand(CompareOperand).getValueType();
1188 ISD::CondCode CCCode =
1189 cast<CondCodeSDNode>(Node->getOperand(CCOperand))->get();
1190 Action = TLI.getCondCodeAction(CCCode, OpVT);
1191 if (Action == TargetLowering::Legal) {
1192 if (Node->getOpcode() == ISD::SELECT_CC)
1193 Action = TLI.getOperationAction(Node->getOpcode(),
1194 Node->getValueType(0));
1196 Action = TLI.getOperationAction(Node->getOpcode(), OpVT);
1202 // FIXME: Model these properly. LOAD and STORE are complicated, and
1203 // STORE expects the unlegalized operand in some cases.
1204 SimpleFinishLegalizing = false;
1206 case ISD::CALLSEQ_START:
1207 case ISD::CALLSEQ_END:
1208 // FIXME: This shouldn't be necessary. These nodes have special properties
1209 // dealing with the recursive nature of legalization. Removing this
1210 // special case should be done as part of making LegalizeDAG non-recursive.
1211 SimpleFinishLegalizing = false;
1213 case ISD::EXTRACT_ELEMENT:
1214 case ISD::FLT_ROUNDS_:
1222 case ISD::MERGE_VALUES:
1223 case ISD::EH_RETURN:
1224 case ISD::FRAME_TO_ARGS_OFFSET:
1225 case ISD::EH_SJLJ_SETJMP:
1226 case ISD::EH_SJLJ_LONGJMP:
1227 // These operations lie about being legal: when they claim to be legal,
1228 // they should actually be expanded.
1229 Action = TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0));
1230 if (Action == TargetLowering::Legal)
1231 Action = TargetLowering::Expand;
1233 case ISD::INIT_TRAMPOLINE:
1234 case ISD::ADJUST_TRAMPOLINE:
1235 case ISD::FRAMEADDR:
1236 case ISD::RETURNADDR:
1237 // These operations lie about being legal: when they claim to be legal,
1238 // they should actually be custom-lowered.
1239 Action = TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0));
1240 if (Action == TargetLowering::Legal)
1241 Action = TargetLowering::Custom;
1244 if (Node->getOpcode() >= ISD::BUILTIN_OP_END) {
1245 Action = TargetLowering::Legal;
1247 Action = TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0));
1252 if (SimpleFinishLegalizing) {
1253 SDNode *NewNode = Node;
1254 switch (Node->getOpcode()) {
1261 // Legalizing shifts/rotates requires adjusting the shift amount
1262 // to the appropriate width.
1263 if (!Node->getOperand(1).getValueType().isVector()) {
1265 DAG.getShiftAmountOperand(Node->getOperand(0).getValueType(),
1266 Node->getOperand(1));
1267 HandleSDNode Handle(SAO);
1268 LegalizeOp(SAO.getNode());
1269 NewNode = DAG.UpdateNodeOperands(Node, Node->getOperand(0),
1273 case ISD::SRL_PARTS:
1274 case ISD::SRA_PARTS:
1275 case ISD::SHL_PARTS:
1276 // Legalizing shifts/rotates requires adjusting the shift amount
1277 // to the appropriate width.
1278 if (!Node->getOperand(2).getValueType().isVector()) {
1280 DAG.getShiftAmountOperand(Node->getOperand(0).getValueType(),
1281 Node->getOperand(2));
1282 HandleSDNode Handle(SAO);
1283 LegalizeOp(SAO.getNode());
1284 NewNode = DAG.UpdateNodeOperands(Node, Node->getOperand(0),
1285 Node->getOperand(1),
1291 if (NewNode != Node) {
1292 DAG.ReplaceAllUsesWith(Node, NewNode);
1293 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
1294 DAG.TransferDbgValues(SDValue(Node, i), SDValue(NewNode, i));
1299 case TargetLowering::Legal:
1301 case TargetLowering::Custom: {
1302 // FIXME: The handling for custom lowering with multiple results is
1304 SDValue Res = TLI.LowerOperation(SDValue(Node, 0), DAG);
1305 if (Res.getNode()) {
1306 SmallVector<SDValue, 8> ResultVals;
1307 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) {
1309 ResultVals.push_back(Res);
1311 ResultVals.push_back(Res.getValue(i));
1313 if (Res.getNode() != Node || Res.getResNo() != 0) {
1314 DAG.ReplaceAllUsesWith(Node, ResultVals.data());
1315 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
1316 DAG.TransferDbgValues(SDValue(Node, i), ResultVals[i]);
1323 case TargetLowering::Expand:
1326 case TargetLowering::Promote:
1332 switch (Node->getOpcode()) {
1339 llvm_unreachable("Do not know how to legalize this operator!");
1341 case ISD::CALLSEQ_START:
1342 case ISD::CALLSEQ_END:
1345 return LegalizeLoadOps(Node);
1348 return LegalizeStoreOps(Node);
1353 SDValue SelectionDAGLegalize::ExpandExtractFromVectorThroughStack(SDValue Op) {
1354 SDValue Vec = Op.getOperand(0);
1355 SDValue Idx = Op.getOperand(1);
1356 DebugLoc dl = Op.getDebugLoc();
1357 // Store the value to a temporary stack slot, then LOAD the returned part.
1358 SDValue StackPtr = DAG.CreateStackTemporary(Vec.getValueType());
1359 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, Vec, StackPtr,
1360 MachinePointerInfo(), false, false, 0);
1362 // Add the offset to the index.
1364 Vec.getValueType().getVectorElementType().getSizeInBits()/8;
1365 Idx = DAG.getNode(ISD::MUL, dl, Idx.getValueType(), Idx,
1366 DAG.getConstant(EltSize, Idx.getValueType()));
1368 if (Idx.getValueType().bitsGT(TLI.getPointerTy()))
1369 Idx = DAG.getNode(ISD::TRUNCATE, dl, TLI.getPointerTy(), Idx);
1371 Idx = DAG.getNode(ISD::ZERO_EXTEND, dl, TLI.getPointerTy(), Idx);
1373 StackPtr = DAG.getNode(ISD::ADD, dl, Idx.getValueType(), Idx, StackPtr);
1375 if (Op.getValueType().isVector())
1376 return DAG.getLoad(Op.getValueType(), dl, Ch, StackPtr,MachinePointerInfo(),
1377 false, false, false, 0);
1378 return DAG.getExtLoad(ISD::EXTLOAD, dl, Op.getValueType(), Ch, StackPtr,
1379 MachinePointerInfo(),
1380 Vec.getValueType().getVectorElementType(),
1384 SDValue SelectionDAGLegalize::ExpandInsertToVectorThroughStack(SDValue Op) {
1385 assert(Op.getValueType().isVector() && "Non-vector insert subvector!");
1387 SDValue Vec = Op.getOperand(0);
1388 SDValue Part = Op.getOperand(1);
1389 SDValue Idx = Op.getOperand(2);
1390 DebugLoc dl = Op.getDebugLoc();
1392 // Store the value to a temporary stack slot, then LOAD the returned part.
1394 SDValue StackPtr = DAG.CreateStackTemporary(Vec.getValueType());
1395 int FI = cast<FrameIndexSDNode>(StackPtr.getNode())->getIndex();
1396 MachinePointerInfo PtrInfo = MachinePointerInfo::getFixedStack(FI);
1398 // First store the whole vector.
1399 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, Vec, StackPtr, PtrInfo,
1402 // Then store the inserted part.
1404 // Add the offset to the index.
1406 Vec.getValueType().getVectorElementType().getSizeInBits()/8;
1408 Idx = DAG.getNode(ISD::MUL, dl, Idx.getValueType(), Idx,
1409 DAG.getConstant(EltSize, Idx.getValueType()));
1411 if (Idx.getValueType().bitsGT(TLI.getPointerTy()))
1412 Idx = DAG.getNode(ISD::TRUNCATE, dl, TLI.getPointerTy(), Idx);
1414 Idx = DAG.getNode(ISD::ZERO_EXTEND, dl, TLI.getPointerTy(), Idx);
1416 SDValue SubStackPtr = DAG.getNode(ISD::ADD, dl, Idx.getValueType(), Idx,
1419 // Store the subvector.
1420 Ch = DAG.getStore(DAG.getEntryNode(), dl, Part, SubStackPtr,
1421 MachinePointerInfo(), false, false, 0);
1423 // Finally, load the updated vector.
1424 return DAG.getLoad(Op.getValueType(), dl, Ch, StackPtr, PtrInfo,
1425 false, false, false, 0);
1428 SDValue SelectionDAGLegalize::ExpandVectorBuildThroughStack(SDNode* Node) {
1429 // We can't handle this case efficiently. Allocate a sufficiently
1430 // aligned object on the stack, store each element into it, then load
1431 // the result as a vector.
1432 // Create the stack frame object.
1433 EVT VT = Node->getValueType(0);
1434 EVT EltVT = VT.getVectorElementType();
1435 DebugLoc dl = Node->getDebugLoc();
1436 SDValue FIPtr = DAG.CreateStackTemporary(VT);
1437 int FI = cast<FrameIndexSDNode>(FIPtr.getNode())->getIndex();
1438 MachinePointerInfo PtrInfo = MachinePointerInfo::getFixedStack(FI);
1440 // Emit a store of each element to the stack slot.
1441 SmallVector<SDValue, 8> Stores;
1442 unsigned TypeByteSize = EltVT.getSizeInBits() / 8;
1443 // Store (in the right endianness) the elements to memory.
1444 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
1445 // Ignore undef elements.
1446 if (Node->getOperand(i).getOpcode() == ISD::UNDEF) continue;
1448 unsigned Offset = TypeByteSize*i;
1450 SDValue Idx = DAG.getConstant(Offset, FIPtr.getValueType());
1451 Idx = DAG.getNode(ISD::ADD, dl, FIPtr.getValueType(), FIPtr, Idx);
1453 // If the destination vector element type is narrower than the source
1454 // element type, only store the bits necessary.
1455 if (EltVT.bitsLT(Node->getOperand(i).getValueType().getScalarType())) {
1456 Stores.push_back(DAG.getTruncStore(DAG.getEntryNode(), dl,
1457 Node->getOperand(i), Idx,
1458 PtrInfo.getWithOffset(Offset),
1459 EltVT, false, false, 0));
1461 Stores.push_back(DAG.getStore(DAG.getEntryNode(), dl,
1462 Node->getOperand(i), Idx,
1463 PtrInfo.getWithOffset(Offset),
1468 if (!Stores.empty()) // Not all undef elements?
1469 StoreChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
1470 &Stores[0], Stores.size());
1472 StoreChain = DAG.getEntryNode();
1474 // Result is a load from the stack slot.
1475 return DAG.getLoad(VT, dl, StoreChain, FIPtr, PtrInfo,
1476 false, false, false, 0);
1479 SDValue SelectionDAGLegalize::ExpandFCOPYSIGN(SDNode* Node) {
1480 DebugLoc dl = Node->getDebugLoc();
1481 SDValue Tmp1 = Node->getOperand(0);
1482 SDValue Tmp2 = Node->getOperand(1);
1484 // Get the sign bit of the RHS. First obtain a value that has the same
1485 // sign as the sign bit, i.e. negative if and only if the sign bit is 1.
1487 EVT FloatVT = Tmp2.getValueType();
1488 EVT IVT = EVT::getIntegerVT(*DAG.getContext(), FloatVT.getSizeInBits());
1489 if (TLI.isTypeLegal(IVT)) {
1490 // Convert to an integer with the same sign bit.
1491 SignBit = DAG.getNode(ISD::BITCAST, dl, IVT, Tmp2);
1493 // Store the float to memory, then load the sign part out as an integer.
1494 MVT LoadTy = TLI.getPointerTy();
1495 // First create a temporary that is aligned for both the load and store.
1496 SDValue StackPtr = DAG.CreateStackTemporary(FloatVT, LoadTy);
1497 // Then store the float to it.
1499 DAG.getStore(DAG.getEntryNode(), dl, Tmp2, StackPtr, MachinePointerInfo(),
1501 if (TLI.isBigEndian()) {
1502 assert(FloatVT.isByteSized() && "Unsupported floating point type!");
1503 // Load out a legal integer with the same sign bit as the float.
1504 SignBit = DAG.getLoad(LoadTy, dl, Ch, StackPtr, MachinePointerInfo(),
1505 false, false, false, 0);
1506 } else { // Little endian
1507 SDValue LoadPtr = StackPtr;
1508 // The float may be wider than the integer we are going to load. Advance
1509 // the pointer so that the loaded integer will contain the sign bit.
1510 unsigned Strides = (FloatVT.getSizeInBits()-1)/LoadTy.getSizeInBits();
1511 unsigned ByteOffset = (Strides * LoadTy.getSizeInBits()) / 8;
1512 LoadPtr = DAG.getNode(ISD::ADD, dl, LoadPtr.getValueType(),
1513 LoadPtr, DAG.getIntPtrConstant(ByteOffset));
1514 // Load a legal integer containing the sign bit.
1515 SignBit = DAG.getLoad(LoadTy, dl, Ch, LoadPtr, MachinePointerInfo(),
1516 false, false, false, 0);
1517 // Move the sign bit to the top bit of the loaded integer.
1518 unsigned BitShift = LoadTy.getSizeInBits() -
1519 (FloatVT.getSizeInBits() - 8 * ByteOffset);
1520 assert(BitShift < LoadTy.getSizeInBits() && "Pointer advanced wrong?");
1522 SignBit = DAG.getNode(ISD::SHL, dl, LoadTy, SignBit,
1523 DAG.getConstant(BitShift,
1524 TLI.getShiftAmountTy(SignBit.getValueType())));
1527 // Now get the sign bit proper, by seeing whether the value is negative.
1528 SignBit = DAG.getSetCC(dl, TLI.getSetCCResultType(SignBit.getValueType()),
1529 SignBit, DAG.getConstant(0, SignBit.getValueType()),
1531 // Get the absolute value of the result.
1532 SDValue AbsVal = DAG.getNode(ISD::FABS, dl, Tmp1.getValueType(), Tmp1);
1533 // Select between the nabs and abs value based on the sign bit of
1535 return DAG.getNode(ISD::SELECT, dl, AbsVal.getValueType(), SignBit,
1536 DAG.getNode(ISD::FNEG, dl, AbsVal.getValueType(), AbsVal),
1540 void SelectionDAGLegalize::ExpandDYNAMIC_STACKALLOC(SDNode* Node,
1541 SmallVectorImpl<SDValue> &Results) {
1542 unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore();
1543 assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and"
1544 " not tell us which reg is the stack pointer!");
1545 DebugLoc dl = Node->getDebugLoc();
1546 EVT VT = Node->getValueType(0);
1547 SDValue Tmp1 = SDValue(Node, 0);
1548 SDValue Tmp2 = SDValue(Node, 1);
1549 SDValue Tmp3 = Node->getOperand(2);
1550 SDValue Chain = Tmp1.getOperand(0);
1552 // Chain the dynamic stack allocation so that it doesn't modify the stack
1553 // pointer when other instructions are using the stack.
1554 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(0, true));
1556 SDValue Size = Tmp2.getOperand(1);
1557 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, VT);
1558 Chain = SP.getValue(1);
1559 unsigned Align = cast<ConstantSDNode>(Tmp3)->getZExtValue();
1560 unsigned StackAlign = TM.getFrameLowering()->getStackAlignment();
1561 if (Align > StackAlign)
1562 SP = DAG.getNode(ISD::AND, dl, VT, SP,
1563 DAG.getConstant(-(uint64_t)Align, VT));
1564 Tmp1 = DAG.getNode(ISD::SUB, dl, VT, SP, Size); // Value
1565 Chain = DAG.getCopyToReg(Chain, dl, SPReg, Tmp1); // Output chain
1567 Tmp2 = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(0, true),
1568 DAG.getIntPtrConstant(0, true), SDValue());
1570 Results.push_back(Tmp1);
1571 Results.push_back(Tmp2);
1574 /// LegalizeSetCCCondCode - Legalize a SETCC with given LHS and RHS and
1575 /// condition code CC on the current target. This routine expands SETCC with
1576 /// illegal condition code into AND / OR of multiple SETCC values.
1577 void SelectionDAGLegalize::LegalizeSetCCCondCode(EVT VT,
1578 SDValue &LHS, SDValue &RHS,
1581 EVT OpVT = LHS.getValueType();
1582 ISD::CondCode CCCode = cast<CondCodeSDNode>(CC)->get();
1583 switch (TLI.getCondCodeAction(CCCode, OpVT)) {
1584 default: llvm_unreachable("Unknown condition code action!");
1585 case TargetLowering::Legal:
1588 case TargetLowering::Expand: {
1589 ISD::CondCode CC1 = ISD::SETCC_INVALID, CC2 = ISD::SETCC_INVALID;
1592 default: llvm_unreachable("Don't know how to expand this condition!");
1593 case ISD::SETOEQ: CC1 = ISD::SETEQ; CC2 = ISD::SETO; Opc = ISD::AND; break;
1594 case ISD::SETOGT: CC1 = ISD::SETGT; CC2 = ISD::SETO; Opc = ISD::AND; break;
1595 case ISD::SETOGE: CC1 = ISD::SETGE; CC2 = ISD::SETO; Opc = ISD::AND; break;
1596 case ISD::SETOLT: CC1 = ISD::SETLT; CC2 = ISD::SETO; Opc = ISD::AND; break;
1597 case ISD::SETOLE: CC1 = ISD::SETLE; CC2 = ISD::SETO; Opc = ISD::AND; break;
1598 case ISD::SETONE: CC1 = ISD::SETNE; CC2 = ISD::SETO; Opc = ISD::AND; break;
1599 case ISD::SETUEQ: CC1 = ISD::SETEQ; CC2 = ISD::SETUO; Opc = ISD::OR; break;
1600 case ISD::SETUGT: CC1 = ISD::SETGT; CC2 = ISD::SETUO; Opc = ISD::OR; break;
1601 case ISD::SETUGE: CC1 = ISD::SETGE; CC2 = ISD::SETUO; Opc = ISD::OR; break;
1602 case ISD::SETULT: CC1 = ISD::SETLT; CC2 = ISD::SETUO; Opc = ISD::OR; break;
1603 case ISD::SETULE: CC1 = ISD::SETLE; CC2 = ISD::SETUO; Opc = ISD::OR; break;
1604 case ISD::SETUNE: CC1 = ISD::SETNE; CC2 = ISD::SETUO; Opc = ISD::OR; break;
1605 // FIXME: Implement more expansions.
1608 SDValue SetCC1 = DAG.getSetCC(dl, VT, LHS, RHS, CC1);
1609 SDValue SetCC2 = DAG.getSetCC(dl, VT, LHS, RHS, CC2);
1610 LHS = DAG.getNode(Opc, dl, VT, SetCC1, SetCC2);
1618 /// EmitStackConvert - Emit a store/load combination to the stack. This stores
1619 /// SrcOp to a stack slot of type SlotVT, truncating it if needed. It then does
1620 /// a load from the stack slot to DestVT, extending it if needed.
1621 /// The resultant code need not be legal.
1622 SDValue SelectionDAGLegalize::EmitStackConvert(SDValue SrcOp,
1626 // Create the stack frame object.
1628 TLI.getDataLayout()->getPrefTypeAlignment(SrcOp.getValueType().
1629 getTypeForEVT(*DAG.getContext()));
1630 SDValue FIPtr = DAG.CreateStackTemporary(SlotVT, SrcAlign);
1632 FrameIndexSDNode *StackPtrFI = cast<FrameIndexSDNode>(FIPtr);
1633 int SPFI = StackPtrFI->getIndex();
1634 MachinePointerInfo PtrInfo = MachinePointerInfo::getFixedStack(SPFI);
1636 unsigned SrcSize = SrcOp.getValueType().getSizeInBits();
1637 unsigned SlotSize = SlotVT.getSizeInBits();
1638 unsigned DestSize = DestVT.getSizeInBits();
1639 Type *DestType = DestVT.getTypeForEVT(*DAG.getContext());
1640 unsigned DestAlign = TLI.getDataLayout()->getPrefTypeAlignment(DestType);
1642 // Emit a store to the stack slot. Use a truncstore if the input value is
1643 // later than DestVT.
1646 if (SrcSize > SlotSize)
1647 Store = DAG.getTruncStore(DAG.getEntryNode(), dl, SrcOp, FIPtr,
1648 PtrInfo, SlotVT, false, false, SrcAlign);
1650 assert(SrcSize == SlotSize && "Invalid store");
1651 Store = DAG.getStore(DAG.getEntryNode(), dl, SrcOp, FIPtr,
1652 PtrInfo, false, false, SrcAlign);
1655 // Result is a load from the stack slot.
1656 if (SlotSize == DestSize)
1657 return DAG.getLoad(DestVT, dl, Store, FIPtr, PtrInfo,
1658 false, false, false, DestAlign);
1660 assert(SlotSize < DestSize && "Unknown extension!");
1661 return DAG.getExtLoad(ISD::EXTLOAD, dl, DestVT, Store, FIPtr,
1662 PtrInfo, SlotVT, false, false, DestAlign);
1665 SDValue SelectionDAGLegalize::ExpandSCALAR_TO_VECTOR(SDNode *Node) {
1666 DebugLoc dl = Node->getDebugLoc();
1667 // Create a vector sized/aligned stack slot, store the value to element #0,
1668 // then load the whole vector back out.
1669 SDValue StackPtr = DAG.CreateStackTemporary(Node->getValueType(0));
1671 FrameIndexSDNode *StackPtrFI = cast<FrameIndexSDNode>(StackPtr);
1672 int SPFI = StackPtrFI->getIndex();
1674 SDValue Ch = DAG.getTruncStore(DAG.getEntryNode(), dl, Node->getOperand(0),
1676 MachinePointerInfo::getFixedStack(SPFI),
1677 Node->getValueType(0).getVectorElementType(),
1679 return DAG.getLoad(Node->getValueType(0), dl, Ch, StackPtr,
1680 MachinePointerInfo::getFixedStack(SPFI),
1681 false, false, false, 0);
1685 /// ExpandBUILD_VECTOR - Expand a BUILD_VECTOR node on targets that don't
1686 /// support the operation, but do support the resultant vector type.
1687 SDValue SelectionDAGLegalize::ExpandBUILD_VECTOR(SDNode *Node) {
1688 unsigned NumElems = Node->getNumOperands();
1689 SDValue Value1, Value2;
1690 DebugLoc dl = Node->getDebugLoc();
1691 EVT VT = Node->getValueType(0);
1692 EVT OpVT = Node->getOperand(0).getValueType();
1693 EVT EltVT = VT.getVectorElementType();
1695 // If the only non-undef value is the low element, turn this into a
1696 // SCALAR_TO_VECTOR node. If this is { X, X, X, X }, determine X.
1697 bool isOnlyLowElement = true;
1698 bool MoreThanTwoValues = false;
1699 bool isConstant = true;
1700 for (unsigned i = 0; i < NumElems; ++i) {
1701 SDValue V = Node->getOperand(i);
1702 if (V.getOpcode() == ISD::UNDEF)
1705 isOnlyLowElement = false;
1706 if (!isa<ConstantFPSDNode>(V) && !isa<ConstantSDNode>(V))
1709 if (!Value1.getNode()) {
1711 } else if (!Value2.getNode()) {
1714 } else if (V != Value1 && V != Value2) {
1715 MoreThanTwoValues = true;
1719 if (!Value1.getNode())
1720 return DAG.getUNDEF(VT);
1722 if (isOnlyLowElement)
1723 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Node->getOperand(0));
1725 // If all elements are constants, create a load from the constant pool.
1727 SmallVector<Constant*, 16> CV;
1728 for (unsigned i = 0, e = NumElems; i != e; ++i) {
1729 if (ConstantFPSDNode *V =
1730 dyn_cast<ConstantFPSDNode>(Node->getOperand(i))) {
1731 CV.push_back(const_cast<ConstantFP *>(V->getConstantFPValue()));
1732 } else if (ConstantSDNode *V =
1733 dyn_cast<ConstantSDNode>(Node->getOperand(i))) {
1735 CV.push_back(const_cast<ConstantInt *>(V->getConstantIntValue()));
1737 // If OpVT and EltVT don't match, EltVT is not legal and the
1738 // element values have been promoted/truncated earlier. Undo this;
1739 // we don't want a v16i8 to become a v16i32 for example.
1740 const ConstantInt *CI = V->getConstantIntValue();
1741 CV.push_back(ConstantInt::get(EltVT.getTypeForEVT(*DAG.getContext()),
1742 CI->getZExtValue()));
1745 assert(Node->getOperand(i).getOpcode() == ISD::UNDEF);
1746 Type *OpNTy = EltVT.getTypeForEVT(*DAG.getContext());
1747 CV.push_back(UndefValue::get(OpNTy));
1750 Constant *CP = ConstantVector::get(CV);
1751 SDValue CPIdx = DAG.getConstantPool(CP, TLI.getPointerTy());
1752 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
1753 return DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
1754 MachinePointerInfo::getConstantPool(),
1755 false, false, false, Alignment);
1758 if (!MoreThanTwoValues) {
1759 SmallVector<int, 8> ShuffleVec(NumElems, -1);
1760 for (unsigned i = 0; i < NumElems; ++i) {
1761 SDValue V = Node->getOperand(i);
1762 if (V.getOpcode() == ISD::UNDEF)
1764 ShuffleVec[i] = V == Value1 ? 0 : NumElems;
1766 if (TLI.isShuffleMaskLegal(ShuffleVec, Node->getValueType(0))) {
1767 // Get the splatted value into the low element of a vector register.
1768 SDValue Vec1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Value1);
1770 if (Value2.getNode())
1771 Vec2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Value2);
1773 Vec2 = DAG.getUNDEF(VT);
1775 // Return shuffle(LowValVec, undef, <0,0,0,0>)
1776 return DAG.getVectorShuffle(VT, dl, Vec1, Vec2, ShuffleVec.data());
1780 // Otherwise, we can't handle this case efficiently.
1781 return ExpandVectorBuildThroughStack(Node);
1784 // ExpandLibCall - Expand a node into a call to a libcall. If the result value
1785 // does not fit into a register, return the lo part and set the hi part to the
1786 // by-reg argument. If it does fit into a single register, return the result
1787 // and leave the Hi part unset.
1788 SDValue SelectionDAGLegalize::ExpandLibCall(RTLIB::Libcall LC, SDNode *Node,
1790 TargetLowering::ArgListTy Args;
1791 TargetLowering::ArgListEntry Entry;
1792 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
1793 EVT ArgVT = Node->getOperand(i).getValueType();
1794 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
1795 Entry.Node = Node->getOperand(i); Entry.Ty = ArgTy;
1796 Entry.isSExt = isSigned;
1797 Entry.isZExt = !isSigned;
1798 Args.push_back(Entry);
1800 SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC),
1801 TLI.getPointerTy());
1803 Type *RetTy = Node->getValueType(0).getTypeForEVT(*DAG.getContext());
1805 // By default, the input chain to this libcall is the entry node of the
1806 // function. If the libcall is going to be emitted as a tail call then
1807 // TLI.isUsedByReturnOnly will change it to the right chain if the return
1808 // node which is being folded has a non-entry input chain.
1809 SDValue InChain = DAG.getEntryNode();
1811 // isTailCall may be true since the callee does not reference caller stack
1812 // frame. Check if it's in the right position.
1813 SDValue TCChain = InChain;
1814 bool isTailCall = isInTailCallPosition(DAG, Node, TCChain, TLI);
1819 CallLoweringInfo CLI(InChain, RetTy, isSigned, !isSigned, false, false,
1820 0, TLI.getLibcallCallingConv(LC), isTailCall,
1821 /*doesNotReturn=*/false, /*isReturnValueUsed=*/true,
1822 Callee, Args, DAG, Node->getDebugLoc());
1823 std::pair<SDValue, SDValue> CallInfo = TLI.LowerCallTo(CLI);
1826 if (!CallInfo.second.getNode())
1827 // It's a tailcall, return the chain (which is the DAG root).
1828 return DAG.getRoot();
1830 return CallInfo.first;
1833 /// ExpandLibCall - Generate a libcall taking the given operands as arguments
1834 /// and returning a result of type RetVT.
1835 SDValue SelectionDAGLegalize::ExpandLibCall(RTLIB::Libcall LC, EVT RetVT,
1836 const SDValue *Ops, unsigned NumOps,
1837 bool isSigned, DebugLoc dl) {
1838 TargetLowering::ArgListTy Args;
1839 Args.reserve(NumOps);
1841 TargetLowering::ArgListEntry Entry;
1842 for (unsigned i = 0; i != NumOps; ++i) {
1843 Entry.Node = Ops[i];
1844 Entry.Ty = Entry.Node.getValueType().getTypeForEVT(*DAG.getContext());
1845 Entry.isSExt = isSigned;
1846 Entry.isZExt = !isSigned;
1847 Args.push_back(Entry);
1849 SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC),
1850 TLI.getPointerTy());
1852 Type *RetTy = RetVT.getTypeForEVT(*DAG.getContext());
1854 CallLoweringInfo CLI(DAG.getEntryNode(), RetTy, isSigned, !isSigned, false,
1855 false, 0, TLI.getLibcallCallingConv(LC),
1856 /*isTailCall=*/false,
1857 /*doesNotReturn=*/false, /*isReturnValueUsed=*/true,
1858 Callee, Args, DAG, dl);
1859 std::pair<SDValue,SDValue> CallInfo = TLI.LowerCallTo(CLI);
1861 return CallInfo.first;
1864 // ExpandChainLibCall - Expand a node into a call to a libcall. Similar to
1865 // ExpandLibCall except that the first operand is the in-chain.
1866 std::pair<SDValue, SDValue>
1867 SelectionDAGLegalize::ExpandChainLibCall(RTLIB::Libcall LC,
1870 SDValue InChain = Node->getOperand(0);
1872 TargetLowering::ArgListTy Args;
1873 TargetLowering::ArgListEntry Entry;
1874 for (unsigned i = 1, e = Node->getNumOperands(); i != e; ++i) {
1875 EVT ArgVT = Node->getOperand(i).getValueType();
1876 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
1877 Entry.Node = Node->getOperand(i);
1879 Entry.isSExt = isSigned;
1880 Entry.isZExt = !isSigned;
1881 Args.push_back(Entry);
1883 SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC),
1884 TLI.getPointerTy());
1886 Type *RetTy = Node->getValueType(0).getTypeForEVT(*DAG.getContext());
1888 CallLoweringInfo CLI(InChain, RetTy, isSigned, !isSigned, false, false,
1889 0, TLI.getLibcallCallingConv(LC), /*isTailCall=*/false,
1890 /*doesNotReturn=*/false, /*isReturnValueUsed=*/true,
1891 Callee, Args, DAG, Node->getDebugLoc());
1892 std::pair<SDValue, SDValue> CallInfo = TLI.LowerCallTo(CLI);
1897 SDValue SelectionDAGLegalize::ExpandFPLibCall(SDNode* Node,
1898 RTLIB::Libcall Call_F32,
1899 RTLIB::Libcall Call_F64,
1900 RTLIB::Libcall Call_F80,
1901 RTLIB::Libcall Call_PPCF128) {
1903 switch (Node->getValueType(0).getSimpleVT().SimpleTy) {
1904 default: llvm_unreachable("Unexpected request for libcall!");
1905 case MVT::f32: LC = Call_F32; break;
1906 case MVT::f64: LC = Call_F64; break;
1907 case MVT::f80: LC = Call_F80; break;
1908 case MVT::ppcf128: LC = Call_PPCF128; break;
1910 return ExpandLibCall(LC, Node, false);
1913 SDValue SelectionDAGLegalize::ExpandIntLibCall(SDNode* Node, bool isSigned,
1914 RTLIB::Libcall Call_I8,
1915 RTLIB::Libcall Call_I16,
1916 RTLIB::Libcall Call_I32,
1917 RTLIB::Libcall Call_I64,
1918 RTLIB::Libcall Call_I128) {
1920 switch (Node->getValueType(0).getSimpleVT().SimpleTy) {
1921 default: llvm_unreachable("Unexpected request for libcall!");
1922 case MVT::i8: LC = Call_I8; break;
1923 case MVT::i16: LC = Call_I16; break;
1924 case MVT::i32: LC = Call_I32; break;
1925 case MVT::i64: LC = Call_I64; break;
1926 case MVT::i128: LC = Call_I128; break;
1928 return ExpandLibCall(LC, Node, isSigned);
1931 /// isDivRemLibcallAvailable - Return true if divmod libcall is available.
1932 static bool isDivRemLibcallAvailable(SDNode *Node, bool isSigned,
1933 const TargetLowering &TLI) {
1935 switch (Node->getValueType(0).getSimpleVT().SimpleTy) {
1936 default: llvm_unreachable("Unexpected request for libcall!");
1937 case MVT::i8: LC= isSigned ? RTLIB::SDIVREM_I8 : RTLIB::UDIVREM_I8; break;
1938 case MVT::i16: LC= isSigned ? RTLIB::SDIVREM_I16 : RTLIB::UDIVREM_I16; break;
1939 case MVT::i32: LC= isSigned ? RTLIB::SDIVREM_I32 : RTLIB::UDIVREM_I32; break;
1940 case MVT::i64: LC= isSigned ? RTLIB::SDIVREM_I64 : RTLIB::UDIVREM_I64; break;
1941 case MVT::i128: LC= isSigned ? RTLIB::SDIVREM_I128:RTLIB::UDIVREM_I128; break;
1944 return TLI.getLibcallName(LC) != 0;
1947 /// useDivRem - Only issue divrem libcall if both quotient and remainder are
1949 static bool useDivRem(SDNode *Node, bool isSigned, bool isDIV) {
1950 // The other use might have been replaced with a divrem already.
1951 unsigned DivRemOpc = isSigned ? ISD::SDIVREM : ISD::UDIVREM;
1952 unsigned OtherOpcode = 0;
1954 OtherOpcode = isDIV ? ISD::SREM : ISD::SDIV;
1956 OtherOpcode = isDIV ? ISD::UREM : ISD::UDIV;
1958 SDValue Op0 = Node->getOperand(0);
1959 SDValue Op1 = Node->getOperand(1);
1960 for (SDNode::use_iterator UI = Op0.getNode()->use_begin(),
1961 UE = Op0.getNode()->use_end(); UI != UE; ++UI) {
1965 if ((User->getOpcode() == OtherOpcode || User->getOpcode() == DivRemOpc) &&
1966 User->getOperand(0) == Op0 &&
1967 User->getOperand(1) == Op1)
1973 /// ExpandDivRemLibCall - Issue libcalls to __{u}divmod to compute div / rem
1976 SelectionDAGLegalize::ExpandDivRemLibCall(SDNode *Node,
1977 SmallVectorImpl<SDValue> &Results) {
1978 unsigned Opcode = Node->getOpcode();
1979 bool isSigned = Opcode == ISD::SDIVREM;
1982 switch (Node->getValueType(0).getSimpleVT().SimpleTy) {
1983 default: llvm_unreachable("Unexpected request for libcall!");
1984 case MVT::i8: LC= isSigned ? RTLIB::SDIVREM_I8 : RTLIB::UDIVREM_I8; break;
1985 case MVT::i16: LC= isSigned ? RTLIB::SDIVREM_I16 : RTLIB::UDIVREM_I16; break;
1986 case MVT::i32: LC= isSigned ? RTLIB::SDIVREM_I32 : RTLIB::UDIVREM_I32; break;
1987 case MVT::i64: LC= isSigned ? RTLIB::SDIVREM_I64 : RTLIB::UDIVREM_I64; break;
1988 case MVT::i128: LC= isSigned ? RTLIB::SDIVREM_I128:RTLIB::UDIVREM_I128; break;
1991 // The input chain to this libcall is the entry node of the function.
1992 // Legalizing the call will automatically add the previous call to the
1994 SDValue InChain = DAG.getEntryNode();
1996 EVT RetVT = Node->getValueType(0);
1997 Type *RetTy = RetVT.getTypeForEVT(*DAG.getContext());
1999 TargetLowering::ArgListTy Args;
2000 TargetLowering::ArgListEntry Entry;
2001 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
2002 EVT ArgVT = Node->getOperand(i).getValueType();
2003 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
2004 Entry.Node = Node->getOperand(i); Entry.Ty = ArgTy;
2005 Entry.isSExt = isSigned;
2006 Entry.isZExt = !isSigned;
2007 Args.push_back(Entry);
2010 // Also pass the return address of the remainder.
2011 SDValue FIPtr = DAG.CreateStackTemporary(RetVT);
2013 Entry.Ty = RetTy->getPointerTo();
2014 Entry.isSExt = isSigned;
2015 Entry.isZExt = !isSigned;
2016 Args.push_back(Entry);
2018 SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC),
2019 TLI.getPointerTy());
2021 DebugLoc dl = Node->getDebugLoc();
2023 CallLoweringInfo CLI(InChain, RetTy, isSigned, !isSigned, false, false,
2024 0, TLI.getLibcallCallingConv(LC), /*isTailCall=*/false,
2025 /*doesNotReturn=*/false, /*isReturnValueUsed=*/true,
2026 Callee, Args, DAG, dl);
2027 std::pair<SDValue, SDValue> CallInfo = TLI.LowerCallTo(CLI);
2029 // Remainder is loaded back from the stack frame.
2030 SDValue Rem = DAG.getLoad(RetVT, dl, CallInfo.second, FIPtr,
2031 MachinePointerInfo(), false, false, false, 0);
2032 Results.push_back(CallInfo.first);
2033 Results.push_back(Rem);
2036 /// ExpandLegalINT_TO_FP - This function is responsible for legalizing a
2037 /// INT_TO_FP operation of the specified operand when the target requests that
2038 /// we expand it. At this point, we know that the result and operand types are
2039 /// legal for the target.
2040 SDValue SelectionDAGLegalize::ExpandLegalINT_TO_FP(bool isSigned,
2044 if (Op0.getValueType() == MVT::i32 && TLI.isTypeLegal(MVT::f64)) {
2045 // simple 32-bit [signed|unsigned] integer to float/double expansion
2047 // Get the stack frame index of a 8 byte buffer.
2048 SDValue StackSlot = DAG.CreateStackTemporary(MVT::f64);
2050 // word offset constant for Hi/Lo address computation
2051 SDValue WordOff = DAG.getConstant(sizeof(int), TLI.getPointerTy());
2052 // set up Hi and Lo (into buffer) address based on endian
2053 SDValue Hi = StackSlot;
2054 SDValue Lo = DAG.getNode(ISD::ADD, dl,
2055 TLI.getPointerTy(), StackSlot, WordOff);
2056 if (TLI.isLittleEndian())
2059 // if signed map to unsigned space
2062 // constant used to invert sign bit (signed to unsigned mapping)
2063 SDValue SignBit = DAG.getConstant(0x80000000u, MVT::i32);
2064 Op0Mapped = DAG.getNode(ISD::XOR, dl, MVT::i32, Op0, SignBit);
2068 // store the lo of the constructed double - based on integer input
2069 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl,
2070 Op0Mapped, Lo, MachinePointerInfo(),
2072 // initial hi portion of constructed double
2073 SDValue InitialHi = DAG.getConstant(0x43300000u, MVT::i32);
2074 // store the hi of the constructed double - biased exponent
2075 SDValue Store2 = DAG.getStore(Store1, dl, InitialHi, Hi,
2076 MachinePointerInfo(),
2078 // load the constructed double
2079 SDValue Load = DAG.getLoad(MVT::f64, dl, Store2, StackSlot,
2080 MachinePointerInfo(), false, false, false, 0);
2081 // FP constant to bias correct the final result
2082 SDValue Bias = DAG.getConstantFP(isSigned ?
2083 BitsToDouble(0x4330000080000000ULL) :
2084 BitsToDouble(0x4330000000000000ULL),
2086 // subtract the bias
2087 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Load, Bias);
2090 // handle final rounding
2091 if (DestVT == MVT::f64) {
2094 } else if (DestVT.bitsLT(MVT::f64)) {
2095 Result = DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub,
2096 DAG.getIntPtrConstant(0));
2097 } else if (DestVT.bitsGT(MVT::f64)) {
2098 Result = DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub);
2102 assert(!isSigned && "Legalize cannot Expand SINT_TO_FP for i64 yet");
2103 // Code below here assumes !isSigned without checking again.
2105 // Implementation of unsigned i64 to f64 following the algorithm in
2106 // __floatundidf in compiler_rt. This implementation has the advantage
2107 // of performing rounding correctly, both in the default rounding mode
2108 // and in all alternate rounding modes.
2109 // TODO: Generalize this for use with other types.
2110 if (Op0.getValueType() == MVT::i64 && DestVT == MVT::f64) {
2112 DAG.getConstant(UINT64_C(0x4330000000000000), MVT::i64);
2113 SDValue TwoP84PlusTwoP52 =
2114 DAG.getConstantFP(BitsToDouble(UINT64_C(0x4530000000100000)), MVT::f64);
2116 DAG.getConstant(UINT64_C(0x4530000000000000), MVT::i64);
2118 SDValue Lo = DAG.getZeroExtendInReg(Op0, dl, MVT::i32);
2119 SDValue Hi = DAG.getNode(ISD::SRL, dl, MVT::i64, Op0,
2120 DAG.getConstant(32, MVT::i64));
2121 SDValue LoOr = DAG.getNode(ISD::OR, dl, MVT::i64, Lo, TwoP52);
2122 SDValue HiOr = DAG.getNode(ISD::OR, dl, MVT::i64, Hi, TwoP84);
2123 SDValue LoFlt = DAG.getNode(ISD::BITCAST, dl, MVT::f64, LoOr);
2124 SDValue HiFlt = DAG.getNode(ISD::BITCAST, dl, MVT::f64, HiOr);
2125 SDValue HiSub = DAG.getNode(ISD::FSUB, dl, MVT::f64, HiFlt,
2127 return DAG.getNode(ISD::FADD, dl, MVT::f64, LoFlt, HiSub);
2130 // Implementation of unsigned i64 to f32.
2131 // TODO: Generalize this for use with other types.
2132 if (Op0.getValueType() == MVT::i64 && DestVT == MVT::f32) {
2133 // For unsigned conversions, convert them to signed conversions using the
2134 // algorithm from the x86_64 __floatundidf in compiler_rt.
2136 SDValue Fast = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, Op0);
2138 SDValue ShiftConst =
2139 DAG.getConstant(1, TLI.getShiftAmountTy(Op0.getValueType()));
2140 SDValue Shr = DAG.getNode(ISD::SRL, dl, MVT::i64, Op0, ShiftConst);
2141 SDValue AndConst = DAG.getConstant(1, MVT::i64);
2142 SDValue And = DAG.getNode(ISD::AND, dl, MVT::i64, Op0, AndConst);
2143 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::i64, And, Shr);
2145 SDValue SignCvt = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, Or);
2146 SDValue Slow = DAG.getNode(ISD::FADD, dl, MVT::f32, SignCvt, SignCvt);
2148 // TODO: This really should be implemented using a branch rather than a
2149 // select. We happen to get lucky and machinesink does the right
2150 // thing most of the time. This would be a good candidate for a
2151 //pseudo-op, or, even better, for whole-function isel.
2152 SDValue SignBitTest = DAG.getSetCC(dl, TLI.getSetCCResultType(MVT::i64),
2153 Op0, DAG.getConstant(0, MVT::i64), ISD::SETLT);
2154 return DAG.getNode(ISD::SELECT, dl, MVT::f32, SignBitTest, Slow, Fast);
2157 // Otherwise, implement the fully general conversion.
2159 SDValue And = DAG.getNode(ISD::AND, dl, MVT::i64, Op0,
2160 DAG.getConstant(UINT64_C(0xfffffffffffff800), MVT::i64));
2161 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::i64, And,
2162 DAG.getConstant(UINT64_C(0x800), MVT::i64));
2163 SDValue And2 = DAG.getNode(ISD::AND, dl, MVT::i64, Op0,
2164 DAG.getConstant(UINT64_C(0x7ff), MVT::i64));
2165 SDValue Ne = DAG.getSetCC(dl, TLI.getSetCCResultType(MVT::i64),
2166 And2, DAG.getConstant(UINT64_C(0), MVT::i64), ISD::SETNE);
2167 SDValue Sel = DAG.getNode(ISD::SELECT, dl, MVT::i64, Ne, Or, Op0);
2168 SDValue Ge = DAG.getSetCC(dl, TLI.getSetCCResultType(MVT::i64),
2169 Op0, DAG.getConstant(UINT64_C(0x0020000000000000), MVT::i64),
2171 SDValue Sel2 = DAG.getNode(ISD::SELECT, dl, MVT::i64, Ge, Sel, Op0);
2172 EVT SHVT = TLI.getShiftAmountTy(Sel2.getValueType());
2174 SDValue Sh = DAG.getNode(ISD::SRL, dl, MVT::i64, Sel2,
2175 DAG.getConstant(32, SHVT));
2176 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Sh);
2177 SDValue Fcvt = DAG.getNode(ISD::UINT_TO_FP, dl, MVT::f64, Trunc);
2179 DAG.getConstantFP(BitsToDouble(UINT64_C(0x41f0000000000000)), MVT::f64);
2180 SDValue Fmul = DAG.getNode(ISD::FMUL, dl, MVT::f64, TwoP32, Fcvt);
2181 SDValue Lo = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Sel2);
2182 SDValue Fcvt2 = DAG.getNode(ISD::UINT_TO_FP, dl, MVT::f64, Lo);
2183 SDValue Fadd = DAG.getNode(ISD::FADD, dl, MVT::f64, Fmul, Fcvt2);
2184 return DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, Fadd,
2185 DAG.getIntPtrConstant(0));
2188 SDValue Tmp1 = DAG.getNode(ISD::SINT_TO_FP, dl, DestVT, Op0);
2190 SDValue SignSet = DAG.getSetCC(dl, TLI.getSetCCResultType(Op0.getValueType()),
2191 Op0, DAG.getConstant(0, Op0.getValueType()),
2193 SDValue Zero = DAG.getIntPtrConstant(0), Four = DAG.getIntPtrConstant(4);
2194 SDValue CstOffset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(),
2195 SignSet, Four, Zero);
2197 // If the sign bit of the integer is set, the large number will be treated
2198 // as a negative number. To counteract this, the dynamic code adds an
2199 // offset depending on the data type.
2201 switch (Op0.getValueType().getSimpleVT().SimpleTy) {
2202 default: llvm_unreachable("Unsupported integer type!");
2203 case MVT::i8 : FF = 0x43800000ULL; break; // 2^8 (as a float)
2204 case MVT::i16: FF = 0x47800000ULL; break; // 2^16 (as a float)
2205 case MVT::i32: FF = 0x4F800000ULL; break; // 2^32 (as a float)
2206 case MVT::i64: FF = 0x5F800000ULL; break; // 2^64 (as a float)
2208 if (TLI.isLittleEndian()) FF <<= 32;
2209 Constant *FudgeFactor = ConstantInt::get(
2210 Type::getInt64Ty(*DAG.getContext()), FF);
2212 SDValue CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy());
2213 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
2214 CPIdx = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(), CPIdx, CstOffset);
2215 Alignment = std::min(Alignment, 4u);
2217 if (DestVT == MVT::f32)
2218 FudgeInReg = DAG.getLoad(MVT::f32, dl, DAG.getEntryNode(), CPIdx,
2219 MachinePointerInfo::getConstantPool(),
2220 false, false, false, Alignment);
2222 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, DestVT,
2223 DAG.getEntryNode(), CPIdx,
2224 MachinePointerInfo::getConstantPool(),
2225 MVT::f32, false, false, Alignment);
2226 HandleSDNode Handle(Load);
2227 LegalizeOp(Load.getNode());
2228 FudgeInReg = Handle.getValue();
2231 return DAG.getNode(ISD::FADD, dl, DestVT, Tmp1, FudgeInReg);
2234 /// PromoteLegalINT_TO_FP - This function is responsible for legalizing a
2235 /// *INT_TO_FP operation of the specified operand when the target requests that
2236 /// we promote it. At this point, we know that the result and operand types are
2237 /// legal for the target, and that there is a legal UINT_TO_FP or SINT_TO_FP
2238 /// operation that takes a larger input.
2239 SDValue SelectionDAGLegalize::PromoteLegalINT_TO_FP(SDValue LegalOp,
2243 // First step, figure out the appropriate *INT_TO_FP operation to use.
2244 EVT NewInTy = LegalOp.getValueType();
2246 unsigned OpToUse = 0;
2248 // Scan for the appropriate larger type to use.
2250 NewInTy = (MVT::SimpleValueType)(NewInTy.getSimpleVT().SimpleTy+1);
2251 assert(NewInTy.isInteger() && "Ran out of possibilities!");
2253 // If the target supports SINT_TO_FP of this type, use it.
2254 if (TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, NewInTy)) {
2255 OpToUse = ISD::SINT_TO_FP;
2258 if (isSigned) continue;
2260 // If the target supports UINT_TO_FP of this type, use it.
2261 if (TLI.isOperationLegalOrCustom(ISD::UINT_TO_FP, NewInTy)) {
2262 OpToUse = ISD::UINT_TO_FP;
2266 // Otherwise, try a larger type.
2269 // Okay, we found the operation and type to use. Zero extend our input to the
2270 // desired type then run the operation on it.
2271 return DAG.getNode(OpToUse, dl, DestVT,
2272 DAG.getNode(isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND,
2273 dl, NewInTy, LegalOp));
2276 /// PromoteLegalFP_TO_INT - This function is responsible for legalizing a
2277 /// FP_TO_*INT operation of the specified operand when the target requests that
2278 /// we promote it. At this point, we know that the result and operand types are
2279 /// legal for the target, and that there is a legal FP_TO_UINT or FP_TO_SINT
2280 /// operation that returns a larger result.
2281 SDValue SelectionDAGLegalize::PromoteLegalFP_TO_INT(SDValue LegalOp,
2285 // First step, figure out the appropriate FP_TO*INT operation to use.
2286 EVT NewOutTy = DestVT;
2288 unsigned OpToUse = 0;
2290 // Scan for the appropriate larger type to use.
2292 NewOutTy = (MVT::SimpleValueType)(NewOutTy.getSimpleVT().SimpleTy+1);
2293 assert(NewOutTy.isInteger() && "Ran out of possibilities!");
2295 if (TLI.isOperationLegalOrCustom(ISD::FP_TO_SINT, NewOutTy)) {
2296 OpToUse = ISD::FP_TO_SINT;
2300 if (TLI.isOperationLegalOrCustom(ISD::FP_TO_UINT, NewOutTy)) {
2301 OpToUse = ISD::FP_TO_UINT;
2305 // Otherwise, try a larger type.
2309 // Okay, we found the operation and type to use.
2310 SDValue Operation = DAG.getNode(OpToUse, dl, NewOutTy, LegalOp);
2312 // Truncate the result of the extended FP_TO_*INT operation to the desired
2314 return DAG.getNode(ISD::TRUNCATE, dl, DestVT, Operation);
2317 /// ExpandBSWAP - Open code the operations for BSWAP of the specified operation.
2319 SDValue SelectionDAGLegalize::ExpandBSWAP(SDValue Op, DebugLoc dl) {
2320 EVT VT = Op.getValueType();
2321 EVT SHVT = TLI.getShiftAmountTy(VT);
2322 SDValue Tmp1, Tmp2, Tmp3, Tmp4, Tmp5, Tmp6, Tmp7, Tmp8;
2323 switch (VT.getSimpleVT().SimpleTy) {
2324 default: llvm_unreachable("Unhandled Expand type in BSWAP!");
2326 Tmp2 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, SHVT));
2327 Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, SHVT));
2328 return DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);
2330 Tmp4 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(24, SHVT));
2331 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, SHVT));
2332 Tmp2 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, SHVT));
2333 Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(24, SHVT));
2334 Tmp3 = DAG.getNode(ISD::AND, dl, VT, Tmp3, DAG.getConstant(0xFF0000, VT));
2335 Tmp2 = DAG.getNode(ISD::AND, dl, VT, Tmp2, DAG.getConstant(0xFF00, VT));
2336 Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp3);
2337 Tmp2 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp1);
2338 return DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp2);
2340 Tmp8 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(56, SHVT));
2341 Tmp7 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(40, SHVT));
2342 Tmp6 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(24, SHVT));
2343 Tmp5 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, SHVT));
2344 Tmp4 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, SHVT));
2345 Tmp3 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(24, SHVT));
2346 Tmp2 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(40, SHVT));
2347 Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(56, SHVT));
2348 Tmp7 = DAG.getNode(ISD::AND, dl, VT, Tmp7, DAG.getConstant(255ULL<<48, VT));
2349 Tmp6 = DAG.getNode(ISD::AND, dl, VT, Tmp6, DAG.getConstant(255ULL<<40, VT));
2350 Tmp5 = DAG.getNode(ISD::AND, dl, VT, Tmp5, DAG.getConstant(255ULL<<32, VT));
2351 Tmp4 = DAG.getNode(ISD::AND, dl, VT, Tmp4, DAG.getConstant(255ULL<<24, VT));
2352 Tmp3 = DAG.getNode(ISD::AND, dl, VT, Tmp3, DAG.getConstant(255ULL<<16, VT));
2353 Tmp2 = DAG.getNode(ISD::AND, dl, VT, Tmp2, DAG.getConstant(255ULL<<8 , VT));
2354 Tmp8 = DAG.getNode(ISD::OR, dl, VT, Tmp8, Tmp7);
2355 Tmp6 = DAG.getNode(ISD::OR, dl, VT, Tmp6, Tmp5);
2356 Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp3);
2357 Tmp2 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp1);
2358 Tmp8 = DAG.getNode(ISD::OR, dl, VT, Tmp8, Tmp6);
2359 Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp2);
2360 return DAG.getNode(ISD::OR, dl, VT, Tmp8, Tmp4);
2364 /// SplatByte - Distribute ByteVal over NumBits bits.
2365 // FIXME: Move this helper to a common place.
2366 static APInt SplatByte(unsigned NumBits, uint8_t ByteVal) {
2367 APInt Val = APInt(NumBits, ByteVal);
2369 for (unsigned i = NumBits; i > 8; i >>= 1) {
2370 Val = (Val << Shift) | Val;
2376 /// ExpandBitCount - Expand the specified bitcount instruction into operations.
2378 SDValue SelectionDAGLegalize::ExpandBitCount(unsigned Opc, SDValue Op,
2381 default: llvm_unreachable("Cannot expand this yet!");
2383 EVT VT = Op.getValueType();
2384 EVT ShVT = TLI.getShiftAmountTy(VT);
2385 unsigned Len = VT.getSizeInBits();
2387 assert(VT.isInteger() && Len <= 128 && Len % 8 == 0 &&
2388 "CTPOP not implemented for this type.");
2390 // This is the "best" algorithm from
2391 // http://graphics.stanford.edu/~seander/bithacks.html#CountBitsSetParallel
2393 SDValue Mask55 = DAG.getConstant(SplatByte(Len, 0x55), VT);
2394 SDValue Mask33 = DAG.getConstant(SplatByte(Len, 0x33), VT);
2395 SDValue Mask0F = DAG.getConstant(SplatByte(Len, 0x0F), VT);
2396 SDValue Mask01 = DAG.getConstant(SplatByte(Len, 0x01), VT);
2398 // v = v - ((v >> 1) & 0x55555555...)
2399 Op = DAG.getNode(ISD::SUB, dl, VT, Op,
2400 DAG.getNode(ISD::AND, dl, VT,
2401 DAG.getNode(ISD::SRL, dl, VT, Op,
2402 DAG.getConstant(1, ShVT)),
2404 // v = (v & 0x33333333...) + ((v >> 2) & 0x33333333...)
2405 Op = DAG.getNode(ISD::ADD, dl, VT,
2406 DAG.getNode(ISD::AND, dl, VT, Op, Mask33),
2407 DAG.getNode(ISD::AND, dl, VT,
2408 DAG.getNode(ISD::SRL, dl, VT, Op,
2409 DAG.getConstant(2, ShVT)),
2411 // v = (v + (v >> 4)) & 0x0F0F0F0F...
2412 Op = DAG.getNode(ISD::AND, dl, VT,
2413 DAG.getNode(ISD::ADD, dl, VT, Op,
2414 DAG.getNode(ISD::SRL, dl, VT, Op,
2415 DAG.getConstant(4, ShVT))),
2417 // v = (v * 0x01010101...) >> (Len - 8)
2418 Op = DAG.getNode(ISD::SRL, dl, VT,
2419 DAG.getNode(ISD::MUL, dl, VT, Op, Mask01),
2420 DAG.getConstant(Len - 8, ShVT));
2424 case ISD::CTLZ_ZERO_UNDEF:
2425 // This trivially expands to CTLZ.
2426 return DAG.getNode(ISD::CTLZ, dl, Op.getValueType(), Op);
2428 // for now, we do this:
2429 // x = x | (x >> 1);
2430 // x = x | (x >> 2);
2432 // x = x | (x >>16);
2433 // x = x | (x >>32); // for 64-bit input
2434 // return popcount(~x);
2436 // but see also: http://www.hackersdelight.org/HDcode/nlz.cc
2437 EVT VT = Op.getValueType();
2438 EVT ShVT = TLI.getShiftAmountTy(VT);
2439 unsigned len = VT.getSizeInBits();
2440 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) {
2441 SDValue Tmp3 = DAG.getConstant(1ULL << i, ShVT);
2442 Op = DAG.getNode(ISD::OR, dl, VT, Op,
2443 DAG.getNode(ISD::SRL, dl, VT, Op, Tmp3));
2445 Op = DAG.getNOT(dl, Op, VT);
2446 return DAG.getNode(ISD::CTPOP, dl, VT, Op);
2448 case ISD::CTTZ_ZERO_UNDEF:
2449 // This trivially expands to CTTZ.
2450 return DAG.getNode(ISD::CTTZ, dl, Op.getValueType(), Op);
2452 // for now, we use: { return popcount(~x & (x - 1)); }
2453 // unless the target has ctlz but not ctpop, in which case we use:
2454 // { return 32 - nlz(~x & (x-1)); }
2455 // see also http://www.hackersdelight.org/HDcode/ntz.cc
2456 EVT VT = Op.getValueType();
2457 SDValue Tmp3 = DAG.getNode(ISD::AND, dl, VT,
2458 DAG.getNOT(dl, Op, VT),
2459 DAG.getNode(ISD::SUB, dl, VT, Op,
2460 DAG.getConstant(1, VT)));
2461 // If ISD::CTLZ is legal and CTPOP isn't, then do that instead.
2462 if (!TLI.isOperationLegalOrCustom(ISD::CTPOP, VT) &&
2463 TLI.isOperationLegalOrCustom(ISD::CTLZ, VT))
2464 return DAG.getNode(ISD::SUB, dl, VT,
2465 DAG.getConstant(VT.getSizeInBits(), VT),
2466 DAG.getNode(ISD::CTLZ, dl, VT, Tmp3));
2467 return DAG.getNode(ISD::CTPOP, dl, VT, Tmp3);
2472 std::pair <SDValue, SDValue> SelectionDAGLegalize::ExpandAtomic(SDNode *Node) {
2473 unsigned Opc = Node->getOpcode();
2474 MVT VT = cast<AtomicSDNode>(Node)->getMemoryVT().getSimpleVT();
2479 llvm_unreachable("Unhandled atomic intrinsic Expand!");
2480 case ISD::ATOMIC_SWAP:
2481 switch (VT.SimpleTy) {
2482 default: llvm_unreachable("Unexpected value type for atomic!");
2483 case MVT::i8: LC = RTLIB::SYNC_LOCK_TEST_AND_SET_1; break;
2484 case MVT::i16: LC = RTLIB::SYNC_LOCK_TEST_AND_SET_2; break;
2485 case MVT::i32: LC = RTLIB::SYNC_LOCK_TEST_AND_SET_4; break;
2486 case MVT::i64: LC = RTLIB::SYNC_LOCK_TEST_AND_SET_8; break;
2489 case ISD::ATOMIC_CMP_SWAP:
2490 switch (VT.SimpleTy) {
2491 default: llvm_unreachable("Unexpected value type for atomic!");
2492 case MVT::i8: LC = RTLIB::SYNC_VAL_COMPARE_AND_SWAP_1; break;
2493 case MVT::i16: LC = RTLIB::SYNC_VAL_COMPARE_AND_SWAP_2; break;
2494 case MVT::i32: LC = RTLIB::SYNC_VAL_COMPARE_AND_SWAP_4; break;
2495 case MVT::i64: LC = RTLIB::SYNC_VAL_COMPARE_AND_SWAP_8; break;
2498 case ISD::ATOMIC_LOAD_ADD:
2499 switch (VT.SimpleTy) {
2500 default: llvm_unreachable("Unexpected value type for atomic!");
2501 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_ADD_1; break;
2502 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_ADD_2; break;
2503 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_ADD_4; break;
2504 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_ADD_8; break;
2507 case ISD::ATOMIC_LOAD_SUB:
2508 switch (VT.SimpleTy) {
2509 default: llvm_unreachable("Unexpected value type for atomic!");
2510 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_SUB_1; break;
2511 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_SUB_2; break;
2512 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_SUB_4; break;
2513 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_SUB_8; break;
2516 case ISD::ATOMIC_LOAD_AND:
2517 switch (VT.SimpleTy) {
2518 default: llvm_unreachable("Unexpected value type for atomic!");
2519 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_AND_1; break;
2520 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_AND_2; break;
2521 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_AND_4; break;
2522 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_AND_8; break;
2525 case ISD::ATOMIC_LOAD_OR:
2526 switch (VT.SimpleTy) {
2527 default: llvm_unreachable("Unexpected value type for atomic!");
2528 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_OR_1; break;
2529 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_OR_2; break;
2530 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_OR_4; break;
2531 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_OR_8; break;
2534 case ISD::ATOMIC_LOAD_XOR:
2535 switch (VT.SimpleTy) {
2536 default: llvm_unreachable("Unexpected value type for atomic!");
2537 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_XOR_1; break;
2538 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_XOR_2; break;
2539 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_XOR_4; break;
2540 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_XOR_8; break;
2543 case ISD::ATOMIC_LOAD_NAND:
2544 switch (VT.SimpleTy) {
2545 default: llvm_unreachable("Unexpected value type for atomic!");
2546 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_NAND_1; break;
2547 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_NAND_2; break;
2548 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_NAND_4; break;
2549 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_NAND_8; break;
2554 return ExpandChainLibCall(LC, Node, false);
2557 void SelectionDAGLegalize::ExpandNode(SDNode *Node) {
2558 SmallVector<SDValue, 8> Results;
2559 DebugLoc dl = Node->getDebugLoc();
2560 SDValue Tmp1, Tmp2, Tmp3, Tmp4;
2561 switch (Node->getOpcode()) {
2564 case ISD::CTLZ_ZERO_UNDEF:
2566 case ISD::CTTZ_ZERO_UNDEF:
2567 Tmp1 = ExpandBitCount(Node->getOpcode(), Node->getOperand(0), dl);
2568 Results.push_back(Tmp1);
2571 Results.push_back(ExpandBSWAP(Node->getOperand(0), dl));
2573 case ISD::FRAMEADDR:
2574 case ISD::RETURNADDR:
2575 case ISD::FRAME_TO_ARGS_OFFSET:
2576 Results.push_back(DAG.getConstant(0, Node->getValueType(0)));
2578 case ISD::FLT_ROUNDS_:
2579 Results.push_back(DAG.getConstant(1, Node->getValueType(0)));
2581 case ISD::EH_RETURN:
2585 case ISD::EH_SJLJ_LONGJMP:
2586 // If the target didn't expand these, there's nothing to do, so just
2587 // preserve the chain and be done.
2588 Results.push_back(Node->getOperand(0));
2590 case ISD::EH_SJLJ_SETJMP:
2591 // If the target didn't expand this, just return 'zero' and preserve the
2593 Results.push_back(DAG.getConstant(0, MVT::i32));
2594 Results.push_back(Node->getOperand(0));
2596 case ISD::ATOMIC_FENCE:
2597 case ISD::MEMBARRIER: {
2598 // If the target didn't lower this, lower it to '__sync_synchronize()' call
2599 // FIXME: handle "fence singlethread" more efficiently.
2600 TargetLowering::ArgListTy Args;
2602 CallLoweringInfo CLI(Node->getOperand(0),
2603 Type::getVoidTy(*DAG.getContext()),
2604 false, false, false, false, 0, CallingConv::C,
2605 /*isTailCall=*/false,
2606 /*doesNotReturn=*/false, /*isReturnValueUsed=*/true,
2607 DAG.getExternalSymbol("__sync_synchronize",
2608 TLI.getPointerTy()),
2610 std::pair<SDValue, SDValue> CallResult = TLI.LowerCallTo(CLI);
2612 Results.push_back(CallResult.second);
2615 case ISD::ATOMIC_LOAD: {
2616 // There is no libcall for atomic load; fake it with ATOMIC_CMP_SWAP.
2617 SDValue Zero = DAG.getConstant(0, Node->getValueType(0));
2618 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_CMP_SWAP, dl,
2619 cast<AtomicSDNode>(Node)->getMemoryVT(),
2620 Node->getOperand(0),
2621 Node->getOperand(1), Zero, Zero,
2622 cast<AtomicSDNode>(Node)->getMemOperand(),
2623 cast<AtomicSDNode>(Node)->getOrdering(),
2624 cast<AtomicSDNode>(Node)->getSynchScope());
2625 Results.push_back(Swap.getValue(0));
2626 Results.push_back(Swap.getValue(1));
2629 case ISD::ATOMIC_STORE: {
2630 // There is no libcall for atomic store; fake it with ATOMIC_SWAP.
2631 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_SWAP, dl,
2632 cast<AtomicSDNode>(Node)->getMemoryVT(),
2633 Node->getOperand(0),
2634 Node->getOperand(1), Node->getOperand(2),
2635 cast<AtomicSDNode>(Node)->getMemOperand(),
2636 cast<AtomicSDNode>(Node)->getOrdering(),
2637 cast<AtomicSDNode>(Node)->getSynchScope());
2638 Results.push_back(Swap.getValue(1));
2641 // By default, atomic intrinsics are marked Legal and lowered. Targets
2642 // which don't support them directly, however, may want libcalls, in which
2643 // case they mark them Expand, and we get here.
2644 case ISD::ATOMIC_SWAP:
2645 case ISD::ATOMIC_LOAD_ADD:
2646 case ISD::ATOMIC_LOAD_SUB:
2647 case ISD::ATOMIC_LOAD_AND:
2648 case ISD::ATOMIC_LOAD_OR:
2649 case ISD::ATOMIC_LOAD_XOR:
2650 case ISD::ATOMIC_LOAD_NAND:
2651 case ISD::ATOMIC_LOAD_MIN:
2652 case ISD::ATOMIC_LOAD_MAX:
2653 case ISD::ATOMIC_LOAD_UMIN:
2654 case ISD::ATOMIC_LOAD_UMAX:
2655 case ISD::ATOMIC_CMP_SWAP: {
2656 std::pair<SDValue, SDValue> Tmp = ExpandAtomic(Node);
2657 Results.push_back(Tmp.first);
2658 Results.push_back(Tmp.second);
2661 case ISD::DYNAMIC_STACKALLOC:
2662 ExpandDYNAMIC_STACKALLOC(Node, Results);
2664 case ISD::MERGE_VALUES:
2665 for (unsigned i = 0; i < Node->getNumValues(); i++)
2666 Results.push_back(Node->getOperand(i));
2669 EVT VT = Node->getValueType(0);
2671 Results.push_back(DAG.getConstant(0, VT));
2673 assert(VT.isFloatingPoint() && "Unknown value type!");
2674 Results.push_back(DAG.getConstantFP(0, VT));
2679 // If this operation is not supported, lower it to 'abort()' call
2680 TargetLowering::ArgListTy Args;
2682 CallLoweringInfo CLI(Node->getOperand(0),
2683 Type::getVoidTy(*DAG.getContext()),
2684 false, false, false, false, 0, CallingConv::C,
2685 /*isTailCall=*/false,
2686 /*doesNotReturn=*/false, /*isReturnValueUsed=*/true,
2687 DAG.getExternalSymbol("abort", TLI.getPointerTy()),
2689 std::pair<SDValue, SDValue> CallResult = TLI.LowerCallTo(CLI);
2691 Results.push_back(CallResult.second);
2696 Tmp1 = EmitStackConvert(Node->getOperand(0), Node->getValueType(0),
2697 Node->getValueType(0), dl);
2698 Results.push_back(Tmp1);
2700 case ISD::FP_EXTEND:
2701 Tmp1 = EmitStackConvert(Node->getOperand(0),
2702 Node->getOperand(0).getValueType(),
2703 Node->getValueType(0), dl);
2704 Results.push_back(Tmp1);
2706 case ISD::SIGN_EXTEND_INREG: {
2707 // NOTE: we could fall back on load/store here too for targets without
2708 // SAR. However, it is doubtful that any exist.
2709 EVT ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT();
2710 EVT VT = Node->getValueType(0);
2711 EVT ShiftAmountTy = TLI.getShiftAmountTy(VT);
2714 unsigned BitsDiff = VT.getScalarType().getSizeInBits() -
2715 ExtraVT.getScalarType().getSizeInBits();
2716 SDValue ShiftCst = DAG.getConstant(BitsDiff, ShiftAmountTy);
2717 Tmp1 = DAG.getNode(ISD::SHL, dl, Node->getValueType(0),
2718 Node->getOperand(0), ShiftCst);
2719 Tmp1 = DAG.getNode(ISD::SRA, dl, Node->getValueType(0), Tmp1, ShiftCst);
2720 Results.push_back(Tmp1);
2723 case ISD::FP_ROUND_INREG: {
2724 // The only way we can lower this is to turn it into a TRUNCSTORE,
2725 // EXTLOAD pair, targeting a temporary location (a stack slot).
2727 // NOTE: there is a choice here between constantly creating new stack
2728 // slots and always reusing the same one. We currently always create
2729 // new ones, as reuse may inhibit scheduling.
2730 EVT ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT();
2731 Tmp1 = EmitStackConvert(Node->getOperand(0), ExtraVT,
2732 Node->getValueType(0), dl);
2733 Results.push_back(Tmp1);
2736 case ISD::SINT_TO_FP:
2737 case ISD::UINT_TO_FP:
2738 Tmp1 = ExpandLegalINT_TO_FP(Node->getOpcode() == ISD::SINT_TO_FP,
2739 Node->getOperand(0), Node->getValueType(0), dl);
2740 Results.push_back(Tmp1);
2742 case ISD::FP_TO_UINT: {
2743 SDValue True, False;
2744 EVT VT = Node->getOperand(0).getValueType();
2745 EVT NVT = Node->getValueType(0);
2746 APFloat apf(APInt::getNullValue(VT.getSizeInBits()));
2747 APInt x = APInt::getSignBit(NVT.getSizeInBits());
2748 (void)apf.convertFromAPInt(x, false, APFloat::rmNearestTiesToEven);
2749 Tmp1 = DAG.getConstantFP(apf, VT);
2750 Tmp2 = DAG.getSetCC(dl, TLI.getSetCCResultType(VT),
2751 Node->getOperand(0),
2753 True = DAG.getNode(ISD::FP_TO_SINT, dl, NVT, Node->getOperand(0));
2754 False = DAG.getNode(ISD::FP_TO_SINT, dl, NVT,
2755 DAG.getNode(ISD::FSUB, dl, VT,
2756 Node->getOperand(0), Tmp1));
2757 False = DAG.getNode(ISD::XOR, dl, NVT, False,
2758 DAG.getConstant(x, NVT));
2759 Tmp1 = DAG.getNode(ISD::SELECT, dl, NVT, Tmp2, True, False);
2760 Results.push_back(Tmp1);
2764 const Value *V = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
2765 EVT VT = Node->getValueType(0);
2766 Tmp1 = Node->getOperand(0);
2767 Tmp2 = Node->getOperand(1);
2768 unsigned Align = Node->getConstantOperandVal(3);
2770 SDValue VAListLoad = DAG.getLoad(TLI.getPointerTy(), dl, Tmp1, Tmp2,
2771 MachinePointerInfo(V),
2772 false, false, false, 0);
2773 SDValue VAList = VAListLoad;
2775 if (Align > TLI.getMinStackArgumentAlignment()) {
2776 assert(((Align & (Align-1)) == 0) && "Expected Align to be a power of 2");
2778 VAList = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(), VAList,
2779 DAG.getConstant(Align - 1,
2780 TLI.getPointerTy()));
2782 VAList = DAG.getNode(ISD::AND, dl, TLI.getPointerTy(), VAList,
2783 DAG.getConstant(-(int64_t)Align,
2784 TLI.getPointerTy()));
2787 // Increment the pointer, VAList, to the next vaarg
2788 Tmp3 = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(), VAList,
2789 DAG.getConstant(TLI.getDataLayout()->
2790 getTypeAllocSize(VT.getTypeForEVT(*DAG.getContext())),
2791 TLI.getPointerTy()));
2792 // Store the incremented VAList to the legalized pointer
2793 Tmp3 = DAG.getStore(VAListLoad.getValue(1), dl, Tmp3, Tmp2,
2794 MachinePointerInfo(V), false, false, 0);
2795 // Load the actual argument out of the pointer VAList
2796 Results.push_back(DAG.getLoad(VT, dl, Tmp3, VAList, MachinePointerInfo(),
2797 false, false, false, 0));
2798 Results.push_back(Results[0].getValue(1));
2802 // This defaults to loading a pointer from the input and storing it to the
2803 // output, returning the chain.
2804 const Value *VD = cast<SrcValueSDNode>(Node->getOperand(3))->getValue();
2805 const Value *VS = cast<SrcValueSDNode>(Node->getOperand(4))->getValue();
2806 Tmp1 = DAG.getLoad(TLI.getPointerTy(), dl, Node->getOperand(0),
2807 Node->getOperand(2), MachinePointerInfo(VS),
2808 false, false, false, 0);
2809 Tmp1 = DAG.getStore(Tmp1.getValue(1), dl, Tmp1, Node->getOperand(1),
2810 MachinePointerInfo(VD), false, false, 0);
2811 Results.push_back(Tmp1);
2814 case ISD::EXTRACT_VECTOR_ELT:
2815 if (Node->getOperand(0).getValueType().getVectorNumElements() == 1)
2816 // This must be an access of the only element. Return it.
2817 Tmp1 = DAG.getNode(ISD::BITCAST, dl, Node->getValueType(0),
2818 Node->getOperand(0));
2820 Tmp1 = ExpandExtractFromVectorThroughStack(SDValue(Node, 0));
2821 Results.push_back(Tmp1);
2823 case ISD::EXTRACT_SUBVECTOR:
2824 Results.push_back(ExpandExtractFromVectorThroughStack(SDValue(Node, 0)));
2826 case ISD::INSERT_SUBVECTOR:
2827 Results.push_back(ExpandInsertToVectorThroughStack(SDValue(Node, 0)));
2829 case ISD::CONCAT_VECTORS: {
2830 Results.push_back(ExpandVectorBuildThroughStack(Node));
2833 case ISD::SCALAR_TO_VECTOR:
2834 Results.push_back(ExpandSCALAR_TO_VECTOR(Node));
2836 case ISD::INSERT_VECTOR_ELT:
2837 Results.push_back(ExpandINSERT_VECTOR_ELT(Node->getOperand(0),
2838 Node->getOperand(1),
2839 Node->getOperand(2), dl));
2841 case ISD::VECTOR_SHUFFLE: {
2842 SmallVector<int, 32> NewMask;
2843 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(Node)->getMask();
2845 EVT VT = Node->getValueType(0);
2846 EVT EltVT = VT.getVectorElementType();
2847 SDValue Op0 = Node->getOperand(0);
2848 SDValue Op1 = Node->getOperand(1);
2849 if (!TLI.isTypeLegal(EltVT)) {
2851 EVT NewEltVT = TLI.getTypeToTransformTo(*DAG.getContext(), EltVT);
2853 // BUILD_VECTOR operands are allowed to be wider than the element type.
2854 // But if NewEltVT is smaller that EltVT the BUILD_VECTOR does not accept it
2855 if (NewEltVT.bitsLT(EltVT)) {
2857 // Convert shuffle node.
2858 // If original node was v4i64 and the new EltVT is i32,
2859 // cast operands to v8i32 and re-build the mask.
2861 // Calculate new VT, the size of the new VT should be equal to original.
2862 EVT NewVT = EVT::getVectorVT(*DAG.getContext(), NewEltVT,
2863 VT.getSizeInBits()/NewEltVT.getSizeInBits());
2864 assert(NewVT.bitsEq(VT));
2866 // cast operands to new VT
2867 Op0 = DAG.getNode(ISD::BITCAST, dl, NewVT, Op0);
2868 Op1 = DAG.getNode(ISD::BITCAST, dl, NewVT, Op1);
2870 // Convert the shuffle mask
2871 unsigned int factor = NewVT.getVectorNumElements()/VT.getVectorNumElements();
2873 // EltVT gets smaller
2876 for (unsigned i = 0; i < VT.getVectorNumElements(); ++i) {
2878 for (unsigned fi = 0; fi < factor; ++fi)
2879 NewMask.push_back(Mask[i]);
2882 for (unsigned fi = 0; fi < factor; ++fi)
2883 NewMask.push_back(Mask[i]*factor+fi);
2891 unsigned NumElems = VT.getVectorNumElements();
2892 SmallVector<SDValue, 16> Ops;
2893 for (unsigned i = 0; i != NumElems; ++i) {
2895 Ops.push_back(DAG.getUNDEF(EltVT));
2898 unsigned Idx = Mask[i];
2900 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT,
2902 DAG.getIntPtrConstant(Idx)));
2904 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT,
2906 DAG.getIntPtrConstant(Idx - NumElems)));
2909 Tmp1 = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &Ops[0], Ops.size());
2910 // We may have changed the BUILD_VECTOR type. Cast it back to the Node type.
2911 Tmp1 = DAG.getNode(ISD::BITCAST, dl, Node->getValueType(0), Tmp1);
2912 Results.push_back(Tmp1);
2915 case ISD::EXTRACT_ELEMENT: {
2916 EVT OpTy = Node->getOperand(0).getValueType();
2917 if (cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue()) {
2919 Tmp1 = DAG.getNode(ISD::SRL, dl, OpTy, Node->getOperand(0),
2920 DAG.getConstant(OpTy.getSizeInBits()/2,
2921 TLI.getShiftAmountTy(Node->getOperand(0).getValueType())));
2922 Tmp1 = DAG.getNode(ISD::TRUNCATE, dl, Node->getValueType(0), Tmp1);
2925 Tmp1 = DAG.getNode(ISD::TRUNCATE, dl, Node->getValueType(0),
2926 Node->getOperand(0));
2928 Results.push_back(Tmp1);
2931 case ISD::STACKSAVE:
2932 // Expand to CopyFromReg if the target set
2933 // StackPointerRegisterToSaveRestore.
2934 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) {
2935 Results.push_back(DAG.getCopyFromReg(Node->getOperand(0), dl, SP,
2936 Node->getValueType(0)));
2937 Results.push_back(Results[0].getValue(1));
2939 Results.push_back(DAG.getUNDEF(Node->getValueType(0)));
2940 Results.push_back(Node->getOperand(0));
2943 case ISD::STACKRESTORE:
2944 // Expand to CopyToReg if the target set
2945 // StackPointerRegisterToSaveRestore.
2946 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) {
2947 Results.push_back(DAG.getCopyToReg(Node->getOperand(0), dl, SP,
2948 Node->getOperand(1)));
2950 Results.push_back(Node->getOperand(0));
2953 case ISD::FCOPYSIGN:
2954 Results.push_back(ExpandFCOPYSIGN(Node));
2957 // Expand Y = FNEG(X) -> Y = SUB -0.0, X
2958 Tmp1 = DAG.getConstantFP(-0.0, Node->getValueType(0));
2959 Tmp1 = DAG.getNode(ISD::FSUB, dl, Node->getValueType(0), Tmp1,
2960 Node->getOperand(0));
2961 Results.push_back(Tmp1);
2964 // Expand Y = FABS(X) -> Y = (X >u 0.0) ? X : fneg(X).
2965 EVT VT = Node->getValueType(0);
2966 Tmp1 = Node->getOperand(0);
2967 Tmp2 = DAG.getConstantFP(0.0, VT);
2968 Tmp2 = DAG.getSetCC(dl, TLI.getSetCCResultType(Tmp1.getValueType()),
2969 Tmp1, Tmp2, ISD::SETUGT);
2970 Tmp3 = DAG.getNode(ISD::FNEG, dl, VT, Tmp1);
2971 Tmp1 = DAG.getNode(ISD::SELECT, dl, VT, Tmp2, Tmp1, Tmp3);
2972 Results.push_back(Tmp1);
2976 Results.push_back(ExpandFPLibCall(Node, RTLIB::SQRT_F32, RTLIB::SQRT_F64,
2977 RTLIB::SQRT_F80, RTLIB::SQRT_PPCF128));
2980 Results.push_back(ExpandFPLibCall(Node, RTLIB::SIN_F32, RTLIB::SIN_F64,
2981 RTLIB::SIN_F80, RTLIB::SIN_PPCF128));
2984 Results.push_back(ExpandFPLibCall(Node, RTLIB::COS_F32, RTLIB::COS_F64,
2985 RTLIB::COS_F80, RTLIB::COS_PPCF128));
2988 Results.push_back(ExpandFPLibCall(Node, RTLIB::LOG_F32, RTLIB::LOG_F64,
2989 RTLIB::LOG_F80, RTLIB::LOG_PPCF128));
2992 Results.push_back(ExpandFPLibCall(Node, RTLIB::LOG2_F32, RTLIB::LOG2_F64,
2993 RTLIB::LOG2_F80, RTLIB::LOG2_PPCF128));
2996 Results.push_back(ExpandFPLibCall(Node, RTLIB::LOG10_F32, RTLIB::LOG10_F64,
2997 RTLIB::LOG10_F80, RTLIB::LOG10_PPCF128));
3000 Results.push_back(ExpandFPLibCall(Node, RTLIB::EXP_F32, RTLIB::EXP_F64,
3001 RTLIB::EXP_F80, RTLIB::EXP_PPCF128));
3004 Results.push_back(ExpandFPLibCall(Node, RTLIB::EXP2_F32, RTLIB::EXP2_F64,
3005 RTLIB::EXP2_F80, RTLIB::EXP2_PPCF128));
3008 Results.push_back(ExpandFPLibCall(Node, RTLIB::TRUNC_F32, RTLIB::TRUNC_F64,
3009 RTLIB::TRUNC_F80, RTLIB::TRUNC_PPCF128));
3012 Results.push_back(ExpandFPLibCall(Node, RTLIB::FLOOR_F32, RTLIB::FLOOR_F64,
3013 RTLIB::FLOOR_F80, RTLIB::FLOOR_PPCF128));
3016 Results.push_back(ExpandFPLibCall(Node, RTLIB::CEIL_F32, RTLIB::CEIL_F64,
3017 RTLIB::CEIL_F80, RTLIB::CEIL_PPCF128));
3020 Results.push_back(ExpandFPLibCall(Node, RTLIB::RINT_F32, RTLIB::RINT_F64,
3021 RTLIB::RINT_F80, RTLIB::RINT_PPCF128));
3023 case ISD::FNEARBYINT:
3024 Results.push_back(ExpandFPLibCall(Node, RTLIB::NEARBYINT_F32,
3025 RTLIB::NEARBYINT_F64,
3026 RTLIB::NEARBYINT_F80,
3027 RTLIB::NEARBYINT_PPCF128));
3030 Results.push_back(ExpandFPLibCall(Node, RTLIB::POWI_F32, RTLIB::POWI_F64,
3031 RTLIB::POWI_F80, RTLIB::POWI_PPCF128));
3034 Results.push_back(ExpandFPLibCall(Node, RTLIB::POW_F32, RTLIB::POW_F64,
3035 RTLIB::POW_F80, RTLIB::POW_PPCF128));
3038 Results.push_back(ExpandFPLibCall(Node, RTLIB::DIV_F32, RTLIB::DIV_F64,
3039 RTLIB::DIV_F80, RTLIB::DIV_PPCF128));
3042 Results.push_back(ExpandFPLibCall(Node, RTLIB::REM_F32, RTLIB::REM_F64,
3043 RTLIB::REM_F80, RTLIB::REM_PPCF128));
3046 Results.push_back(ExpandFPLibCall(Node, RTLIB::FMA_F32, RTLIB::FMA_F64,
3047 RTLIB::FMA_F80, RTLIB::FMA_PPCF128));
3049 case ISD::FP16_TO_FP32:
3050 Results.push_back(ExpandLibCall(RTLIB::FPEXT_F16_F32, Node, false));
3052 case ISD::FP32_TO_FP16:
3053 Results.push_back(ExpandLibCall(RTLIB::FPROUND_F32_F16, Node, false));
3055 case ISD::ConstantFP: {
3056 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node);
3057 // Check to see if this FP immediate is already legal.
3058 // If this is a legal constant, turn it into a TargetConstantFP node.
3059 if (!TLI.isFPImmLegal(CFP->getValueAPF(), Node->getValueType(0)))
3060 Results.push_back(ExpandConstantFP(CFP, true));
3063 case ISD::EHSELECTION: {
3064 unsigned Reg = TLI.getExceptionSelectorRegister();
3065 assert(Reg && "Can't expand to unknown register!");
3066 Results.push_back(DAG.getCopyFromReg(Node->getOperand(1), dl, Reg,
3067 Node->getValueType(0)));
3068 Results.push_back(Results[0].getValue(1));
3071 case ISD::EXCEPTIONADDR: {
3072 unsigned Reg = TLI.getExceptionPointerRegister();
3073 assert(Reg && "Can't expand to unknown register!");
3074 Results.push_back(DAG.getCopyFromReg(Node->getOperand(0), dl, Reg,
3075 Node->getValueType(0)));
3076 Results.push_back(Results[0].getValue(1));
3080 EVT VT = Node->getValueType(0);
3081 assert(TLI.isOperationLegalOrCustom(ISD::FADD, VT) &&
3082 TLI.isOperationLegalOrCustom(ISD::FNEG, VT) &&
3083 "Don't know how to expand this FP subtraction!");
3084 Tmp1 = DAG.getNode(ISD::FNEG, dl, VT, Node->getOperand(1));
3085 Tmp1 = DAG.getNode(ISD::FADD, dl, VT, Node->getOperand(0), Tmp1);
3086 Results.push_back(Tmp1);
3090 EVT VT = Node->getValueType(0);
3091 assert(TLI.isOperationLegalOrCustom(ISD::ADD, VT) &&
3092 TLI.isOperationLegalOrCustom(ISD::XOR, VT) &&
3093 "Don't know how to expand this subtraction!");
3094 Tmp1 = DAG.getNode(ISD::XOR, dl, VT, Node->getOperand(1),
3095 DAG.getConstant(APInt::getAllOnesValue(VT.getSizeInBits()), VT));
3096 Tmp1 = DAG.getNode(ISD::ADD, dl, VT, Tmp1, DAG.getConstant(1, VT));
3097 Results.push_back(DAG.getNode(ISD::ADD, dl, VT, Node->getOperand(0), Tmp1));
3102 EVT VT = Node->getValueType(0);
3103 SDVTList VTs = DAG.getVTList(VT, VT);
3104 bool isSigned = Node->getOpcode() == ISD::SREM;
3105 unsigned DivOpc = isSigned ? ISD::SDIV : ISD::UDIV;
3106 unsigned DivRemOpc = isSigned ? ISD::SDIVREM : ISD::UDIVREM;
3107 Tmp2 = Node->getOperand(0);
3108 Tmp3 = Node->getOperand(1);
3109 if (TLI.isOperationLegalOrCustom(DivRemOpc, VT) ||
3110 (isDivRemLibcallAvailable(Node, isSigned, TLI) &&
3111 useDivRem(Node, isSigned, false))) {
3112 Tmp1 = DAG.getNode(DivRemOpc, dl, VTs, Tmp2, Tmp3).getValue(1);
3113 } else if (TLI.isOperationLegalOrCustom(DivOpc, VT)) {
3115 Tmp1 = DAG.getNode(DivOpc, dl, VT, Tmp2, Tmp3);
3116 Tmp1 = DAG.getNode(ISD::MUL, dl, VT, Tmp1, Tmp3);
3117 Tmp1 = DAG.getNode(ISD::SUB, dl, VT, Tmp2, Tmp1);
3118 } else if (isSigned)
3119 Tmp1 = ExpandIntLibCall(Node, true,
3121 RTLIB::SREM_I16, RTLIB::SREM_I32,
3122 RTLIB::SREM_I64, RTLIB::SREM_I128);
3124 Tmp1 = ExpandIntLibCall(Node, false,
3126 RTLIB::UREM_I16, RTLIB::UREM_I32,
3127 RTLIB::UREM_I64, RTLIB::UREM_I128);
3128 Results.push_back(Tmp1);
3133 bool isSigned = Node->getOpcode() == ISD::SDIV;
3134 unsigned DivRemOpc = isSigned ? ISD::SDIVREM : ISD::UDIVREM;
3135 EVT VT = Node->getValueType(0);
3136 SDVTList VTs = DAG.getVTList(VT, VT);
3137 if (TLI.isOperationLegalOrCustom(DivRemOpc, VT) ||
3138 (isDivRemLibcallAvailable(Node, isSigned, TLI) &&
3139 useDivRem(Node, isSigned, true)))
3140 Tmp1 = DAG.getNode(DivRemOpc, dl, VTs, Node->getOperand(0),
3141 Node->getOperand(1));
3143 Tmp1 = ExpandIntLibCall(Node, true,
3145 RTLIB::SDIV_I16, RTLIB::SDIV_I32,
3146 RTLIB::SDIV_I64, RTLIB::SDIV_I128);
3148 Tmp1 = ExpandIntLibCall(Node, false,
3150 RTLIB::UDIV_I16, RTLIB::UDIV_I32,
3151 RTLIB::UDIV_I64, RTLIB::UDIV_I128);
3152 Results.push_back(Tmp1);
3157 unsigned ExpandOpcode = Node->getOpcode() == ISD::MULHU ? ISD::UMUL_LOHI :
3159 EVT VT = Node->getValueType(0);
3160 SDVTList VTs = DAG.getVTList(VT, VT);
3161 assert(TLI.isOperationLegalOrCustom(ExpandOpcode, VT) &&
3162 "If this wasn't legal, it shouldn't have been created!");
3163 Tmp1 = DAG.getNode(ExpandOpcode, dl, VTs, Node->getOperand(0),
3164 Node->getOperand(1));
3165 Results.push_back(Tmp1.getValue(1));
3170 // Expand into divrem libcall
3171 ExpandDivRemLibCall(Node, Results);
3174 EVT VT = Node->getValueType(0);
3175 SDVTList VTs = DAG.getVTList(VT, VT);
3176 // See if multiply or divide can be lowered using two-result operations.
3177 // We just need the low half of the multiply; try both the signed
3178 // and unsigned forms. If the target supports both SMUL_LOHI and
3179 // UMUL_LOHI, form a preference by checking which forms of plain
3180 // MULH it supports.
3181 bool HasSMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::SMUL_LOHI, VT);
3182 bool HasUMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::UMUL_LOHI, VT);
3183 bool HasMULHS = TLI.isOperationLegalOrCustom(ISD::MULHS, VT);
3184 bool HasMULHU = TLI.isOperationLegalOrCustom(ISD::MULHU, VT);
3185 unsigned OpToUse = 0;
3186 if (HasSMUL_LOHI && !HasMULHS) {
3187 OpToUse = ISD::SMUL_LOHI;
3188 } else if (HasUMUL_LOHI && !HasMULHU) {
3189 OpToUse = ISD::UMUL_LOHI;
3190 } else if (HasSMUL_LOHI) {
3191 OpToUse = ISD::SMUL_LOHI;
3192 } else if (HasUMUL_LOHI) {
3193 OpToUse = ISD::UMUL_LOHI;
3196 Results.push_back(DAG.getNode(OpToUse, dl, VTs, Node->getOperand(0),
3197 Node->getOperand(1)));
3200 Tmp1 = ExpandIntLibCall(Node, false,
3202 RTLIB::MUL_I16, RTLIB::MUL_I32,
3203 RTLIB::MUL_I64, RTLIB::MUL_I128);
3204 Results.push_back(Tmp1);
3209 SDValue LHS = Node->getOperand(0);
3210 SDValue RHS = Node->getOperand(1);
3211 SDValue Sum = DAG.getNode(Node->getOpcode() == ISD::SADDO ?
3212 ISD::ADD : ISD::SUB, dl, LHS.getValueType(),
3214 Results.push_back(Sum);
3215 EVT OType = Node->getValueType(1);
3217 SDValue Zero = DAG.getConstant(0, LHS.getValueType());
3219 // LHSSign -> LHS >= 0
3220 // RHSSign -> RHS >= 0
3221 // SumSign -> Sum >= 0
3224 // Overflow -> (LHSSign == RHSSign) && (LHSSign != SumSign)
3226 // Overflow -> (LHSSign != RHSSign) && (LHSSign != SumSign)
3228 SDValue LHSSign = DAG.getSetCC(dl, OType, LHS, Zero, ISD::SETGE);
3229 SDValue RHSSign = DAG.getSetCC(dl, OType, RHS, Zero, ISD::SETGE);
3230 SDValue SignsMatch = DAG.getSetCC(dl, OType, LHSSign, RHSSign,
3231 Node->getOpcode() == ISD::SADDO ?
3232 ISD::SETEQ : ISD::SETNE);
3234 SDValue SumSign = DAG.getSetCC(dl, OType, Sum, Zero, ISD::SETGE);
3235 SDValue SumSignNE = DAG.getSetCC(dl, OType, LHSSign, SumSign, ISD::SETNE);
3237 SDValue Cmp = DAG.getNode(ISD::AND, dl, OType, SignsMatch, SumSignNE);
3238 Results.push_back(Cmp);
3243 SDValue LHS = Node->getOperand(0);
3244 SDValue RHS = Node->getOperand(1);
3245 SDValue Sum = DAG.getNode(Node->getOpcode() == ISD::UADDO ?
3246 ISD::ADD : ISD::SUB, dl, LHS.getValueType(),
3248 Results.push_back(Sum);
3249 Results.push_back(DAG.getSetCC(dl, Node->getValueType(1), Sum, LHS,
3250 Node->getOpcode () == ISD::UADDO ?
3251 ISD::SETULT : ISD::SETUGT));
3256 EVT VT = Node->getValueType(0);
3257 EVT WideVT = EVT::getIntegerVT(*DAG.getContext(), VT.getSizeInBits() * 2);
3258 SDValue LHS = Node->getOperand(0);
3259 SDValue RHS = Node->getOperand(1);
3262 static const unsigned Ops[2][3] =
3263 { { ISD::MULHU, ISD::UMUL_LOHI, ISD::ZERO_EXTEND },
3264 { ISD::MULHS, ISD::SMUL_LOHI, ISD::SIGN_EXTEND }};
3265 bool isSigned = Node->getOpcode() == ISD::SMULO;
3266 if (TLI.isOperationLegalOrCustom(Ops[isSigned][0], VT)) {
3267 BottomHalf = DAG.getNode(ISD::MUL, dl, VT, LHS, RHS);
3268 TopHalf = DAG.getNode(Ops[isSigned][0], dl, VT, LHS, RHS);
3269 } else if (TLI.isOperationLegalOrCustom(Ops[isSigned][1], VT)) {
3270 BottomHalf = DAG.getNode(Ops[isSigned][1], dl, DAG.getVTList(VT, VT), LHS,
3272 TopHalf = BottomHalf.getValue(1);
3273 } else if (TLI.isTypeLegal(EVT::getIntegerVT(*DAG.getContext(),
3274 VT.getSizeInBits() * 2))) {
3275 LHS = DAG.getNode(Ops[isSigned][2], dl, WideVT, LHS);
3276 RHS = DAG.getNode(Ops[isSigned][2], dl, WideVT, RHS);
3277 Tmp1 = DAG.getNode(ISD::MUL, dl, WideVT, LHS, RHS);
3278 BottomHalf = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VT, Tmp1,
3279 DAG.getIntPtrConstant(0));
3280 TopHalf = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VT, Tmp1,
3281 DAG.getIntPtrConstant(1));
3283 // We can fall back to a libcall with an illegal type for the MUL if we
3284 // have a libcall big enough.
3285 // Also, we can fall back to a division in some cases, but that's a big
3286 // performance hit in the general case.
3287 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
3288 if (WideVT == MVT::i16)
3289 LC = RTLIB::MUL_I16;
3290 else if (WideVT == MVT::i32)
3291 LC = RTLIB::MUL_I32;
3292 else if (WideVT == MVT::i64)
3293 LC = RTLIB::MUL_I64;
3294 else if (WideVT == MVT::i128)
3295 LC = RTLIB::MUL_I128;
3296 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Cannot expand this operation!");
3298 // The high part is obtained by SRA'ing all but one of the bits of low
3300 unsigned LoSize = VT.getSizeInBits();
3301 SDValue HiLHS = DAG.getNode(ISD::SRA, dl, VT, RHS,
3302 DAG.getConstant(LoSize-1, TLI.getPointerTy()));
3303 SDValue HiRHS = DAG.getNode(ISD::SRA, dl, VT, LHS,
3304 DAG.getConstant(LoSize-1, TLI.getPointerTy()));
3306 // Here we're passing the 2 arguments explicitly as 4 arguments that are
3307 // pre-lowered to the correct types. This all depends upon WideVT not
3308 // being a legal type for the architecture and thus has to be split to
3310 SDValue Args[] = { LHS, HiLHS, RHS, HiRHS };
3311 SDValue Ret = ExpandLibCall(LC, WideVT, Args, 4, isSigned, dl);
3312 BottomHalf = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VT, Ret,
3313 DAG.getIntPtrConstant(0));
3314 TopHalf = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VT, Ret,
3315 DAG.getIntPtrConstant(1));
3316 // Ret is a node with an illegal type. Because such things are not
3317 // generally permitted during this phase of legalization, delete the
3318 // node. The above EXTRACT_ELEMENT nodes should have been folded.
3319 DAG.DeleteNode(Ret.getNode());
3323 Tmp1 = DAG.getConstant(VT.getSizeInBits() - 1,
3324 TLI.getShiftAmountTy(BottomHalf.getValueType()));
3325 Tmp1 = DAG.getNode(ISD::SRA, dl, VT, BottomHalf, Tmp1);
3326 TopHalf = DAG.getSetCC(dl, TLI.getSetCCResultType(VT), TopHalf, Tmp1,
3329 TopHalf = DAG.getSetCC(dl, TLI.getSetCCResultType(VT), TopHalf,
3330 DAG.getConstant(0, VT), ISD::SETNE);
3332 Results.push_back(BottomHalf);
3333 Results.push_back(TopHalf);
3336 case ISD::BUILD_PAIR: {
3337 EVT PairTy = Node->getValueType(0);
3338 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, PairTy, Node->getOperand(0));
3339 Tmp2 = DAG.getNode(ISD::ANY_EXTEND, dl, PairTy, Node->getOperand(1));
3340 Tmp2 = DAG.getNode(ISD::SHL, dl, PairTy, Tmp2,
3341 DAG.getConstant(PairTy.getSizeInBits()/2,
3342 TLI.getShiftAmountTy(PairTy)));
3343 Results.push_back(DAG.getNode(ISD::OR, dl, PairTy, Tmp1, Tmp2));
3347 Tmp1 = Node->getOperand(0);
3348 Tmp2 = Node->getOperand(1);
3349 Tmp3 = Node->getOperand(2);
3350 if (Tmp1.getOpcode() == ISD::SETCC) {
3351 Tmp1 = DAG.getSelectCC(dl, Tmp1.getOperand(0), Tmp1.getOperand(1),
3353 cast<CondCodeSDNode>(Tmp1.getOperand(2))->get());
3355 Tmp1 = DAG.getSelectCC(dl, Tmp1,
3356 DAG.getConstant(0, Tmp1.getValueType()),
3357 Tmp2, Tmp3, ISD::SETNE);
3359 Results.push_back(Tmp1);
3362 SDValue Chain = Node->getOperand(0);
3363 SDValue Table = Node->getOperand(1);
3364 SDValue Index = Node->getOperand(2);
3366 EVT PTy = TLI.getPointerTy();
3368 const DataLayout &TD = *TLI.getDataLayout();
3369 unsigned EntrySize =
3370 DAG.getMachineFunction().getJumpTableInfo()->getEntrySize(TD);
3372 Index = DAG.getNode(ISD::MUL, dl, PTy,
3373 Index, DAG.getConstant(EntrySize, PTy));
3374 SDValue Addr = DAG.getNode(ISD::ADD, dl, PTy, Index, Table);
3376 EVT MemVT = EVT::getIntegerVT(*DAG.getContext(), EntrySize * 8);
3377 SDValue LD = DAG.getExtLoad(ISD::SEXTLOAD, dl, PTy, Chain, Addr,
3378 MachinePointerInfo::getJumpTable(), MemVT,
3381 if (TM.getRelocationModel() == Reloc::PIC_) {
3382 // For PIC, the sequence is:
3383 // BRIND(load(Jumptable + index) + RelocBase)
3384 // RelocBase can be JumpTable, GOT or some sort of global base.
3385 Addr = DAG.getNode(ISD::ADD, dl, PTy, Addr,
3386 TLI.getPICJumpTableRelocBase(Table, DAG));
3388 Tmp1 = DAG.getNode(ISD::BRIND, dl, MVT::Other, LD.getValue(1), Addr);
3389 Results.push_back(Tmp1);
3393 // Expand brcond's setcc into its constituent parts and create a BR_CC
3395 Tmp1 = Node->getOperand(0);
3396 Tmp2 = Node->getOperand(1);
3397 if (Tmp2.getOpcode() == ISD::SETCC) {
3398 Tmp1 = DAG.getNode(ISD::BR_CC, dl, MVT::Other,
3399 Tmp1, Tmp2.getOperand(2),
3400 Tmp2.getOperand(0), Tmp2.getOperand(1),
3401 Node->getOperand(2));
3403 // We test only the i1 bit. Skip the AND if UNDEF.
3404 Tmp3 = (Tmp2.getOpcode() == ISD::UNDEF) ? Tmp2 :
3405 DAG.getNode(ISD::AND, dl, Tmp2.getValueType(), Tmp2,
3406 DAG.getConstant(1, Tmp2.getValueType()));
3407 Tmp1 = DAG.getNode(ISD::BR_CC, dl, MVT::Other, Tmp1,
3408 DAG.getCondCode(ISD::SETNE), Tmp3,
3409 DAG.getConstant(0, Tmp3.getValueType()),
3410 Node->getOperand(2));
3412 Results.push_back(Tmp1);
3415 Tmp1 = Node->getOperand(0);
3416 Tmp2 = Node->getOperand(1);
3417 Tmp3 = Node->getOperand(2);
3418 LegalizeSetCCCondCode(Node->getValueType(0), Tmp1, Tmp2, Tmp3, dl);
3420 // If we expanded the SETCC into an AND/OR, return the new node
3421 if (Tmp2.getNode() == 0) {
3422 Results.push_back(Tmp1);
3426 // Otherwise, SETCC for the given comparison type must be completely
3427 // illegal; expand it into a SELECT_CC.
3428 EVT VT = Node->getValueType(0);
3429 Tmp1 = DAG.getNode(ISD::SELECT_CC, dl, VT, Tmp1, Tmp2,
3430 DAG.getConstant(1, VT), DAG.getConstant(0, VT), Tmp3);
3431 Results.push_back(Tmp1);
3434 case ISD::SELECT_CC: {
3435 Tmp1 = Node->getOperand(0); // LHS
3436 Tmp2 = Node->getOperand(1); // RHS
3437 Tmp3 = Node->getOperand(2); // True
3438 Tmp4 = Node->getOperand(3); // False
3439 SDValue CC = Node->getOperand(4);
3441 LegalizeSetCCCondCode(TLI.getSetCCResultType(Tmp1.getValueType()),
3442 Tmp1, Tmp2, CC, dl);
3444 assert(!Tmp2.getNode() && "Can't legalize SELECT_CC with legal condition!");
3445 Tmp2 = DAG.getConstant(0, Tmp1.getValueType());
3446 CC = DAG.getCondCode(ISD::SETNE);
3447 Tmp1 = DAG.getNode(ISD::SELECT_CC, dl, Node->getValueType(0), Tmp1, Tmp2,
3449 Results.push_back(Tmp1);
3453 Tmp1 = Node->getOperand(0); // Chain
3454 Tmp2 = Node->getOperand(2); // LHS
3455 Tmp3 = Node->getOperand(3); // RHS
3456 Tmp4 = Node->getOperand(1); // CC
3458 LegalizeSetCCCondCode(TLI.getSetCCResultType(Tmp2.getValueType()),
3459 Tmp2, Tmp3, Tmp4, dl);
3461 assert(!Tmp3.getNode() && "Can't legalize BR_CC with legal condition!");
3462 Tmp3 = DAG.getConstant(0, Tmp2.getValueType());
3463 Tmp4 = DAG.getCondCode(ISD::SETNE);
3464 Tmp1 = DAG.getNode(ISD::BR_CC, dl, Node->getValueType(0), Tmp1, Tmp4, Tmp2,
3465 Tmp3, Node->getOperand(4));
3466 Results.push_back(Tmp1);
3469 case ISD::BUILD_VECTOR:
3470 Results.push_back(ExpandBUILD_VECTOR(Node));
3475 // Scalarize vector SRA/SRL/SHL.
3476 EVT VT = Node->getValueType(0);
3477 assert(VT.isVector() && "Unable to legalize non-vector shift");
3478 assert(TLI.isTypeLegal(VT.getScalarType())&& "Element type must be legal");
3479 unsigned NumElem = VT.getVectorNumElements();
3481 SmallVector<SDValue, 8> Scalars;
3482 for (unsigned Idx = 0; Idx < NumElem; Idx++) {
3483 SDValue Ex = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
3485 Node->getOperand(0), DAG.getIntPtrConstant(Idx));
3486 SDValue Sh = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
3488 Node->getOperand(1), DAG.getIntPtrConstant(Idx));
3489 Scalars.push_back(DAG.getNode(Node->getOpcode(), dl,
3490 VT.getScalarType(), Ex, Sh));
3493 DAG.getNode(ISD::BUILD_VECTOR, dl, Node->getValueType(0),
3494 &Scalars[0], Scalars.size());
3495 ReplaceNode(SDValue(Node, 0), Result);
3498 case ISD::GLOBAL_OFFSET_TABLE:
3499 case ISD::GlobalAddress:
3500 case ISD::GlobalTLSAddress:
3501 case ISD::ExternalSymbol:
3502 case ISD::ConstantPool:
3503 case ISD::JumpTable:
3504 case ISD::INTRINSIC_W_CHAIN:
3505 case ISD::INTRINSIC_WO_CHAIN:
3506 case ISD::INTRINSIC_VOID:
3507 // FIXME: Custom lowering for these operations shouldn't return null!
3511 // Replace the original node with the legalized result.
3512 if (!Results.empty())
3513 ReplaceNode(Node, Results.data());
3516 void SelectionDAGLegalize::PromoteNode(SDNode *Node) {
3517 SmallVector<SDValue, 8> Results;
3518 EVT OVT = Node->getValueType(0);
3519 if (Node->getOpcode() == ISD::UINT_TO_FP ||
3520 Node->getOpcode() == ISD::SINT_TO_FP ||
3521 Node->getOpcode() == ISD::SETCC) {
3522 OVT = Node->getOperand(0).getValueType();
3524 EVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
3525 DebugLoc dl = Node->getDebugLoc();
3526 SDValue Tmp1, Tmp2, Tmp3;
3527 switch (Node->getOpcode()) {
3529 case ISD::CTTZ_ZERO_UNDEF:
3531 case ISD::CTLZ_ZERO_UNDEF:
3533 // Zero extend the argument.
3534 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Node->getOperand(0));
3535 // Perform the larger operation. For CTPOP and CTTZ_ZERO_UNDEF, this is
3536 // already the correct result.
3537 Tmp1 = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1);
3538 if (Node->getOpcode() == ISD::CTTZ) {
3539 // FIXME: This should set a bit in the zero extended value instead.
3540 Tmp2 = DAG.getSetCC(dl, TLI.getSetCCResultType(NVT),
3541 Tmp1, DAG.getConstant(NVT.getSizeInBits(), NVT),
3543 Tmp1 = DAG.getNode(ISD::SELECT, dl, NVT, Tmp2,
3544 DAG.getConstant(OVT.getSizeInBits(), NVT), Tmp1);
3545 } else if (Node->getOpcode() == ISD::CTLZ ||
3546 Node->getOpcode() == ISD::CTLZ_ZERO_UNDEF) {
3547 // Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT))
3548 Tmp1 = DAG.getNode(ISD::SUB, dl, NVT, Tmp1,
3549 DAG.getConstant(NVT.getSizeInBits() -
3550 OVT.getSizeInBits(), NVT));
3552 Results.push_back(DAG.getNode(ISD::TRUNCATE, dl, OVT, Tmp1));
3555 unsigned DiffBits = NVT.getSizeInBits() - OVT.getSizeInBits();
3556 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Node->getOperand(0));
3557 Tmp1 = DAG.getNode(ISD::BSWAP, dl, NVT, Tmp1);
3558 Tmp1 = DAG.getNode(ISD::SRL, dl, NVT, Tmp1,
3559 DAG.getConstant(DiffBits, TLI.getShiftAmountTy(NVT)));
3560 Results.push_back(Tmp1);
3563 case ISD::FP_TO_UINT:
3564 case ISD::FP_TO_SINT:
3565 Tmp1 = PromoteLegalFP_TO_INT(Node->getOperand(0), Node->getValueType(0),
3566 Node->getOpcode() == ISD::FP_TO_SINT, dl);
3567 Results.push_back(Tmp1);
3569 case ISD::UINT_TO_FP:
3570 case ISD::SINT_TO_FP:
3571 Tmp1 = PromoteLegalINT_TO_FP(Node->getOperand(0), Node->getValueType(0),
3572 Node->getOpcode() == ISD::SINT_TO_FP, dl);
3573 Results.push_back(Tmp1);
3576 SDValue Chain = Node->getOperand(0); // Get the chain.
3577 SDValue Ptr = Node->getOperand(1); // Get the pointer.
3580 if (OVT.isVector()) {
3581 TruncOp = ISD::BITCAST;
3583 assert(OVT.isInteger()
3584 && "VAARG promotion is supported only for vectors or integer types");
3585 TruncOp = ISD::TRUNCATE;
3588 // Perform the larger operation, then convert back
3589 Tmp1 = DAG.getVAArg(NVT, dl, Chain, Ptr, Node->getOperand(2),
3590 Node->getConstantOperandVal(3));
3591 Chain = Tmp1.getValue(1);
3593 Tmp2 = DAG.getNode(TruncOp, dl, OVT, Tmp1);
3595 // Modified the chain result - switch anything that used the old chain to
3597 DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 0), Tmp2);
3598 DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 1), Chain);
3605 unsigned ExtOp, TruncOp;
3606 if (OVT.isVector()) {
3607 ExtOp = ISD::BITCAST;
3608 TruncOp = ISD::BITCAST;
3610 assert(OVT.isInteger() && "Cannot promote logic operation");
3611 ExtOp = ISD::ANY_EXTEND;
3612 TruncOp = ISD::TRUNCATE;
3614 // Promote each of the values to the new type.
3615 Tmp1 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(0));
3616 Tmp2 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(1));
3617 // Perform the larger operation, then convert back
3618 Tmp1 = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1, Tmp2);
3619 Results.push_back(DAG.getNode(TruncOp, dl, OVT, Tmp1));
3623 unsigned ExtOp, TruncOp;
3624 if (Node->getValueType(0).isVector()) {
3625 ExtOp = ISD::BITCAST;
3626 TruncOp = ISD::BITCAST;
3627 } else if (Node->getValueType(0).isInteger()) {
3628 ExtOp = ISD::ANY_EXTEND;
3629 TruncOp = ISD::TRUNCATE;
3631 ExtOp = ISD::FP_EXTEND;
3632 TruncOp = ISD::FP_ROUND;
3634 Tmp1 = Node->getOperand(0);
3635 // Promote each of the values to the new type.
3636 Tmp2 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(1));
3637 Tmp3 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(2));
3638 // Perform the larger operation, then round down.
3639 Tmp1 = DAG.getNode(ISD::SELECT, dl, NVT, Tmp1, Tmp2, Tmp3);
3640 if (TruncOp != ISD::FP_ROUND)
3641 Tmp1 = DAG.getNode(TruncOp, dl, Node->getValueType(0), Tmp1);
3643 Tmp1 = DAG.getNode(TruncOp, dl, Node->getValueType(0), Tmp1,
3644 DAG.getIntPtrConstant(0));
3645 Results.push_back(Tmp1);
3648 case ISD::VECTOR_SHUFFLE: {
3649 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(Node)->getMask();
3651 // Cast the two input vectors.
3652 Tmp1 = DAG.getNode(ISD::BITCAST, dl, NVT, Node->getOperand(0));
3653 Tmp2 = DAG.getNode(ISD::BITCAST, dl, NVT, Node->getOperand(1));
3655 // Convert the shuffle mask to the right # elements.
3656 Tmp1 = ShuffleWithNarrowerEltType(NVT, OVT, dl, Tmp1, Tmp2, Mask);
3657 Tmp1 = DAG.getNode(ISD::BITCAST, dl, OVT, Tmp1);
3658 Results.push_back(Tmp1);
3662 unsigned ExtOp = ISD::FP_EXTEND;
3663 if (NVT.isInteger()) {
3664 ISD::CondCode CCCode =
3665 cast<CondCodeSDNode>(Node->getOperand(2))->get();
3666 ExtOp = isSignedIntSetCC(CCCode) ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
3668 Tmp1 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(0));
3669 Tmp2 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(1));
3670 Results.push_back(DAG.getNode(ISD::SETCC, dl, Node->getValueType(0),
3671 Tmp1, Tmp2, Node->getOperand(2)));
3677 Tmp1 = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Node->getOperand(0));
3678 Tmp2 = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Node->getOperand(1));
3679 Tmp3 = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1, Tmp2);
3680 Results.push_back(DAG.getNode(ISD::FP_ROUND, dl, OVT,
3681 Tmp3, DAG.getIntPtrConstant(0)));
3688 Tmp1 = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Node->getOperand(0));
3689 Tmp2 = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1);
3690 Results.push_back(DAG.getNode(ISD::FP_ROUND, dl, OVT,
3691 Tmp2, DAG.getIntPtrConstant(0)));
3696 // Replace the original node with the legalized result.
3697 if (!Results.empty())
3698 ReplaceNode(Node, Results.data());
3701 // SelectionDAG::Legalize - This is the entry point for the file.
3703 void SelectionDAG::Legalize() {
3704 /// run - This is the main entry point to this class.
3706 SelectionDAGLegalize(*this).LegalizeDAG();