1 //===-- LegalizeDAG.cpp - Implement SelectionDAG::Legalize ----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the SelectionDAG::Legalize method.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/CodeGen/SelectionDAG.h"
15 #include "llvm/CodeGen/MachineFunction.h"
16 #include "llvm/CodeGen/MachineFrameInfo.h"
17 #include "llvm/CodeGen/MachineJumpTableInfo.h"
18 #include "llvm/CodeGen/MachineModuleInfo.h"
19 #include "llvm/CodeGen/PseudoSourceValue.h"
20 #include "llvm/Target/TargetFrameInfo.h"
21 #include "llvm/Target/TargetLowering.h"
22 #include "llvm/Target/TargetData.h"
23 #include "llvm/Target/TargetMachine.h"
24 #include "llvm/Target/TargetOptions.h"
25 #include "llvm/CallingConv.h"
26 #include "llvm/Constants.h"
27 #include "llvm/DerivedTypes.h"
28 #include "llvm/Support/CommandLine.h"
29 #include "llvm/Support/Compiler.h"
30 #include "llvm/Support/MathExtras.h"
31 #include "llvm/ADT/DenseMap.h"
32 #include "llvm/ADT/SmallVector.h"
33 #include "llvm/ADT/SmallPtrSet.h"
39 ViewLegalizeDAGs("view-legalize-dags", cl::Hidden,
40 cl::desc("Pop up a window to show dags before legalize"));
42 static const bool ViewLegalizeDAGs = 0;
45 //===----------------------------------------------------------------------===//
46 /// SelectionDAGLegalize - This takes an arbitrary SelectionDAG as input and
47 /// hacks on it until the target machine can handle it. This involves
48 /// eliminating value sizes the machine cannot handle (promoting small sizes to
49 /// large sizes or splitting up large values into small values) as well as
50 /// eliminating operations the machine cannot handle.
52 /// This code also does a small amount of optimization and recognition of idioms
53 /// as part of its processing. For example, if a target does not support a
54 /// 'setcc' instruction efficiently, but does support 'brcc' instruction, this
55 /// will attempt merge setcc and brc instructions into brcc's.
58 class VISIBILITY_HIDDEN SelectionDAGLegalize {
62 // Libcall insertion helpers.
64 /// LastCALLSEQ_END - This keeps track of the CALLSEQ_END node that has been
65 /// legalized. We use this to ensure that calls are properly serialized
66 /// against each other, including inserted libcalls.
67 SDOperand LastCALLSEQ_END;
69 /// IsLegalizingCall - This member is used *only* for purposes of providing
70 /// helpful assertions that a libcall isn't created while another call is
71 /// being legalized (which could lead to non-serialized call sequences).
72 bool IsLegalizingCall;
75 Legal, // The target natively supports this operation.
76 Promote, // This operation should be executed in a larger type.
77 Expand // Try to expand this to other ops, otherwise use a libcall.
80 /// ValueTypeActions - This is a bitvector that contains two bits for each
81 /// value type, where the two bits correspond to the LegalizeAction enum.
82 /// This can be queried with "getTypeAction(VT)".
83 TargetLowering::ValueTypeActionImpl ValueTypeActions;
85 /// LegalizedNodes - For nodes that are of legal width, and that have more
86 /// than one use, this map indicates what regularized operand to use. This
87 /// allows us to avoid legalizing the same thing more than once.
88 DenseMap<SDOperand, SDOperand> LegalizedNodes;
90 /// PromotedNodes - For nodes that are below legal width, and that have more
91 /// than one use, this map indicates what promoted value to use. This allows
92 /// us to avoid promoting the same thing more than once.
93 DenseMap<SDOperand, SDOperand> PromotedNodes;
95 /// ExpandedNodes - For nodes that need to be expanded this map indicates
96 /// which which operands are the expanded version of the input. This allows
97 /// us to avoid expanding the same node more than once.
98 DenseMap<SDOperand, std::pair<SDOperand, SDOperand> > ExpandedNodes;
100 /// SplitNodes - For vector nodes that need to be split, this map indicates
101 /// which which operands are the split version of the input. This allows us
102 /// to avoid splitting the same node more than once.
103 std::map<SDOperand, std::pair<SDOperand, SDOperand> > SplitNodes;
105 /// ScalarizedNodes - For nodes that need to be converted from vector types to
106 /// scalar types, this contains the mapping of ones we have already
107 /// processed to the result.
108 std::map<SDOperand, SDOperand> ScalarizedNodes;
110 void AddLegalizedOperand(SDOperand From, SDOperand To) {
111 LegalizedNodes.insert(std::make_pair(From, To));
112 // If someone requests legalization of the new node, return itself.
114 LegalizedNodes.insert(std::make_pair(To, To));
116 void AddPromotedOperand(SDOperand From, SDOperand To) {
117 bool isNew = PromotedNodes.insert(std::make_pair(From, To));
118 assert(isNew && "Got into the map somehow?");
119 // If someone requests legalization of the new node, return itself.
120 LegalizedNodes.insert(std::make_pair(To, To));
125 SelectionDAGLegalize(SelectionDAG &DAG);
127 /// getTypeAction - Return how we should legalize values of this type, either
128 /// it is already legal or we need to expand it into multiple registers of
129 /// smaller integer type, or we need to promote it to a larger type.
130 LegalizeAction getTypeAction(MVT::ValueType VT) const {
131 return (LegalizeAction)ValueTypeActions.getTypeAction(VT);
134 /// isTypeLegal - Return true if this type is legal on this target.
136 bool isTypeLegal(MVT::ValueType VT) const {
137 return getTypeAction(VT) == Legal;
143 /// HandleOp - Legalize, Promote, or Expand the specified operand as
144 /// appropriate for its type.
145 void HandleOp(SDOperand Op);
147 /// LegalizeOp - We know that the specified value has a legal type.
148 /// Recursively ensure that the operands have legal types, then return the
150 SDOperand LegalizeOp(SDOperand O);
152 /// UnrollVectorOp - We know that the given vector has a legal type, however
153 /// the operation it performs is not legal and is an operation that we have
154 /// no way of lowering. "Unroll" the vector, splitting out the scalars and
155 /// operating on each element individually.
156 SDOperand UnrollVectorOp(SDOperand O);
158 /// PromoteOp - Given an operation that produces a value in an invalid type,
159 /// promote it to compute the value into a larger type. The produced value
160 /// will have the correct bits for the low portion of the register, but no
161 /// guarantee is made about the top bits: it may be zero, sign-extended, or
163 SDOperand PromoteOp(SDOperand O);
165 /// ExpandOp - Expand the specified SDOperand into its two component pieces
166 /// Lo&Hi. Note that the Op MUST be an expanded type. As a result of this,
167 /// the LegalizeNodes map is filled in for any results that are not expanded,
168 /// the ExpandedNodes map is filled in for any results that are expanded, and
169 /// the Lo/Hi values are returned. This applies to integer types and Vector
171 void ExpandOp(SDOperand O, SDOperand &Lo, SDOperand &Hi);
173 /// SplitVectorOp - Given an operand of vector type, break it down into
174 /// two smaller values.
175 void SplitVectorOp(SDOperand O, SDOperand &Lo, SDOperand &Hi);
177 /// ScalarizeVectorOp - Given an operand of single-element vector type
178 /// (e.g. v1f32), convert it into the equivalent operation that returns a
179 /// scalar (e.g. f32) value.
180 SDOperand ScalarizeVectorOp(SDOperand O);
182 /// isShuffleLegal - Return true if a vector shuffle is legal with the
183 /// specified mask and type. Targets can specify exactly which masks they
184 /// support and the code generator is tasked with not creating illegal masks.
186 /// Note that this will also return true for shuffles that are promoted to a
189 /// If this is a legal shuffle, this method returns the (possibly promoted)
190 /// build_vector Mask. If it's not a legal shuffle, it returns null.
191 SDNode *isShuffleLegal(MVT::ValueType VT, SDOperand Mask) const;
193 bool LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest,
194 SmallPtrSet<SDNode*, 32> &NodesLeadingTo);
196 void LegalizeSetCCOperands(SDOperand &LHS, SDOperand &RHS, SDOperand &CC);
198 SDOperand ExpandLibCall(const char *Name, SDNode *Node, bool isSigned,
200 SDOperand ExpandIntToFP(bool isSigned, MVT::ValueType DestTy,
203 SDOperand EmitStackConvert(SDOperand SrcOp, MVT::ValueType SlotVT,
204 MVT::ValueType DestVT);
205 SDOperand ExpandBUILD_VECTOR(SDNode *Node);
206 SDOperand ExpandSCALAR_TO_VECTOR(SDNode *Node);
207 SDOperand ExpandLegalINT_TO_FP(bool isSigned,
209 MVT::ValueType DestVT);
210 SDOperand PromoteLegalINT_TO_FP(SDOperand LegalOp, MVT::ValueType DestVT,
212 SDOperand PromoteLegalFP_TO_INT(SDOperand LegalOp, MVT::ValueType DestVT,
215 SDOperand ExpandBSWAP(SDOperand Op);
216 SDOperand ExpandBitCount(unsigned Opc, SDOperand Op);
217 bool ExpandShift(unsigned Opc, SDOperand Op, SDOperand Amt,
218 SDOperand &Lo, SDOperand &Hi);
219 void ExpandShiftParts(unsigned NodeOp, SDOperand Op, SDOperand Amt,
220 SDOperand &Lo, SDOperand &Hi);
222 SDOperand ExpandEXTRACT_SUBVECTOR(SDOperand Op);
223 SDOperand ExpandEXTRACT_VECTOR_ELT(SDOperand Op);
227 /// isVectorShuffleLegal - Return true if a vector shuffle is legal with the
228 /// specified mask and type. Targets can specify exactly which masks they
229 /// support and the code generator is tasked with not creating illegal masks.
231 /// Note that this will also return true for shuffles that are promoted to a
233 SDNode *SelectionDAGLegalize::isShuffleLegal(MVT::ValueType VT,
234 SDOperand Mask) const {
235 switch (TLI.getOperationAction(ISD::VECTOR_SHUFFLE, VT)) {
237 case TargetLowering::Legal:
238 case TargetLowering::Custom:
240 case TargetLowering::Promote: {
241 // If this is promoted to a different type, convert the shuffle mask and
242 // ask if it is legal in the promoted type!
243 MVT::ValueType NVT = TLI.getTypeToPromoteTo(ISD::VECTOR_SHUFFLE, VT);
245 // If we changed # elements, change the shuffle mask.
246 unsigned NumEltsGrowth =
247 MVT::getVectorNumElements(NVT) / MVT::getVectorNumElements(VT);
248 assert(NumEltsGrowth && "Cannot promote to vector type with fewer elts!");
249 if (NumEltsGrowth > 1) {
250 // Renumber the elements.
251 SmallVector<SDOperand, 8> Ops;
252 for (unsigned i = 0, e = Mask.getNumOperands(); i != e; ++i) {
253 SDOperand InOp = Mask.getOperand(i);
254 for (unsigned j = 0; j != NumEltsGrowth; ++j) {
255 if (InOp.getOpcode() == ISD::UNDEF)
256 Ops.push_back(DAG.getNode(ISD::UNDEF, MVT::i32));
258 unsigned InEltNo = cast<ConstantSDNode>(InOp)->getValue();
259 Ops.push_back(DAG.getConstant(InEltNo*NumEltsGrowth+j, MVT::i32));
263 Mask = DAG.getNode(ISD::BUILD_VECTOR, NVT, &Ops[0], Ops.size());
269 return TLI.isShuffleMaskLegal(Mask, VT) ? Mask.Val : 0;
272 SelectionDAGLegalize::SelectionDAGLegalize(SelectionDAG &dag)
273 : TLI(dag.getTargetLoweringInfo()), DAG(dag),
274 ValueTypeActions(TLI.getValueTypeActions()) {
275 assert(MVT::LAST_VALUETYPE <= 32 &&
276 "Too many value types for ValueTypeActions to hold!");
279 /// ComputeTopDownOrdering - Compute a top-down ordering of the dag, where Order
280 /// contains all of a nodes operands before it contains the node.
281 static void ComputeTopDownOrdering(SelectionDAG &DAG,
282 SmallVector<SDNode*, 64> &Order) {
284 DenseMap<SDNode*, unsigned> Visited;
285 std::vector<SDNode*> Worklist;
286 Worklist.reserve(128);
288 // Compute ordering from all of the leaves in the graphs, those (like the
289 // entry node) that have no operands.
290 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(),
291 E = DAG.allnodes_end(); I != E; ++I) {
292 if (I->getNumOperands() == 0) {
294 Worklist.push_back(I);
298 while (!Worklist.empty()) {
299 SDNode *N = Worklist.back();
302 if (++Visited[N] != N->getNumOperands())
303 continue; // Haven't visited all operands yet
307 // Now that we have N in, add anything that uses it if all of their operands
309 for (SDNode::use_iterator UI = N->use_begin(), E = N->use_end();
311 Worklist.push_back(*UI);
314 assert(Order.size() == Visited.size() &&
316 (unsigned)std::distance(DAG.allnodes_begin(), DAG.allnodes_end()) &&
317 "Error: DAG is cyclic!");
321 void SelectionDAGLegalize::LegalizeDAG() {
322 LastCALLSEQ_END = DAG.getEntryNode();
323 IsLegalizingCall = false;
325 // The legalize process is inherently a bottom-up recursive process (users
326 // legalize their uses before themselves). Given infinite stack space, we
327 // could just start legalizing on the root and traverse the whole graph. In
328 // practice however, this causes us to run out of stack space on large basic
329 // blocks. To avoid this problem, compute an ordering of the nodes where each
330 // node is only legalized after all of its operands are legalized.
331 SmallVector<SDNode*, 64> Order;
332 ComputeTopDownOrdering(DAG, Order);
334 for (unsigned i = 0, e = Order.size(); i != e; ++i)
335 HandleOp(SDOperand(Order[i], 0));
337 // Finally, it's possible the root changed. Get the new root.
338 SDOperand OldRoot = DAG.getRoot();
339 assert(LegalizedNodes.count(OldRoot) && "Root didn't get legalized?");
340 DAG.setRoot(LegalizedNodes[OldRoot]);
342 ExpandedNodes.clear();
343 LegalizedNodes.clear();
344 PromotedNodes.clear();
346 ScalarizedNodes.clear();
348 // Remove dead nodes now.
349 DAG.RemoveDeadNodes();
353 /// FindCallEndFromCallStart - Given a chained node that is part of a call
354 /// sequence, find the CALLSEQ_END node that terminates the call sequence.
355 static SDNode *FindCallEndFromCallStart(SDNode *Node) {
356 if (Node->getOpcode() == ISD::CALLSEQ_END)
358 if (Node->use_empty())
359 return 0; // No CallSeqEnd
361 // The chain is usually at the end.
362 SDOperand TheChain(Node, Node->getNumValues()-1);
363 if (TheChain.getValueType() != MVT::Other) {
364 // Sometimes it's at the beginning.
365 TheChain = SDOperand(Node, 0);
366 if (TheChain.getValueType() != MVT::Other) {
367 // Otherwise, hunt for it.
368 for (unsigned i = 1, e = Node->getNumValues(); i != e; ++i)
369 if (Node->getValueType(i) == MVT::Other) {
370 TheChain = SDOperand(Node, i);
374 // Otherwise, we walked into a node without a chain.
375 if (TheChain.getValueType() != MVT::Other)
380 for (SDNode::use_iterator UI = Node->use_begin(),
381 E = Node->use_end(); UI != E; ++UI) {
383 // Make sure to only follow users of our token chain.
385 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i)
386 if (User->getOperand(i) == TheChain)
387 if (SDNode *Result = FindCallEndFromCallStart(User))
393 /// FindCallStartFromCallEnd - Given a chained node that is part of a call
394 /// sequence, find the CALLSEQ_START node that initiates the call sequence.
395 static SDNode *FindCallStartFromCallEnd(SDNode *Node) {
396 assert(Node && "Didn't find callseq_start for a call??");
397 if (Node->getOpcode() == ISD::CALLSEQ_START) return Node;
399 assert(Node->getOperand(0).getValueType() == MVT::Other &&
400 "Node doesn't have a token chain argument!");
401 return FindCallStartFromCallEnd(Node->getOperand(0).Val);
404 /// LegalizeAllNodesNotLeadingTo - Recursively walk the uses of N, looking to
405 /// see if any uses can reach Dest. If no dest operands can get to dest,
406 /// legalize them, legalize ourself, and return false, otherwise, return true.
408 /// Keep track of the nodes we fine that actually do lead to Dest in
409 /// NodesLeadingTo. This avoids retraversing them exponential number of times.
411 bool SelectionDAGLegalize::LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest,
412 SmallPtrSet<SDNode*, 32> &NodesLeadingTo) {
413 if (N == Dest) return true; // N certainly leads to Dest :)
415 // If we've already processed this node and it does lead to Dest, there is no
416 // need to reprocess it.
417 if (NodesLeadingTo.count(N)) return true;
419 // If the first result of this node has been already legalized, then it cannot
421 switch (getTypeAction(N->getValueType(0))) {
423 if (LegalizedNodes.count(SDOperand(N, 0))) return false;
426 if (PromotedNodes.count(SDOperand(N, 0))) return false;
429 if (ExpandedNodes.count(SDOperand(N, 0))) return false;
433 // Okay, this node has not already been legalized. Check and legalize all
434 // operands. If none lead to Dest, then we can legalize this node.
435 bool OperandsLeadToDest = false;
436 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
437 OperandsLeadToDest |= // If an operand leads to Dest, so do we.
438 LegalizeAllNodesNotLeadingTo(N->getOperand(i).Val, Dest, NodesLeadingTo);
440 if (OperandsLeadToDest) {
441 NodesLeadingTo.insert(N);
445 // Okay, this node looks safe, legalize it and return false.
446 HandleOp(SDOperand(N, 0));
450 /// HandleOp - Legalize, Promote, or Expand the specified operand as
451 /// appropriate for its type.
452 void SelectionDAGLegalize::HandleOp(SDOperand Op) {
453 MVT::ValueType VT = Op.getValueType();
454 switch (getTypeAction(VT)) {
455 default: assert(0 && "Bad type action!");
456 case Legal: (void)LegalizeOp(Op); break;
457 case Promote: (void)PromoteOp(Op); break;
459 if (!MVT::isVector(VT)) {
460 // If this is an illegal scalar, expand it into its two component
463 if (Op.getOpcode() == ISD::TargetConstant)
464 break; // Allow illegal target nodes.
466 } else if (MVT::getVectorNumElements(VT) == 1) {
467 // If this is an illegal single element vector, convert it to a
469 (void)ScalarizeVectorOp(Op);
471 // Otherwise, this is an illegal multiple element vector.
472 // Split it in half and legalize both parts.
474 SplitVectorOp(Op, X, Y);
480 /// ExpandConstantFP - Expands the ConstantFP node to an integer constant or
481 /// a load from the constant pool.
482 static SDOperand ExpandConstantFP(ConstantFPSDNode *CFP, bool UseCP,
483 SelectionDAG &DAG, TargetLowering &TLI) {
486 // If a FP immediate is precise when represented as a float and if the
487 // target can do an extending load from float to double, we put it into
488 // the constant pool as a float, even if it's is statically typed as a
490 MVT::ValueType VT = CFP->getValueType(0);
491 bool isDouble = VT == MVT::f64;
492 ConstantFP *LLVMC = ConstantFP::get(MVT::getTypeForValueType(VT),
495 if (VT!=MVT::f64 && VT!=MVT::f32)
496 assert(0 && "Invalid type expansion");
497 return DAG.getConstant(LLVMC->getValueAPF().convertToAPInt().getZExtValue(),
498 isDouble ? MVT::i64 : MVT::i32);
501 if (isDouble && CFP->isValueValidForType(MVT::f32, CFP->getValueAPF()) &&
502 // Only do this if the target has a native EXTLOAD instruction from f32.
503 // Do not try to be clever about long doubles (so far)
504 TLI.isLoadXLegal(ISD::EXTLOAD, MVT::f32)) {
505 LLVMC = cast<ConstantFP>(ConstantExpr::getFPTrunc(LLVMC,Type::FloatTy));
510 SDOperand CPIdx = DAG.getConstantPool(LLVMC, TLI.getPointerTy());
512 return DAG.getExtLoad(ISD::EXTLOAD, MVT::f64, DAG.getEntryNode(),
513 CPIdx, PseudoSourceValue::getConstantPool(),
516 return DAG.getLoad(VT, DAG.getEntryNode(), CPIdx,
517 PseudoSourceValue::getConstantPool(), 0);
522 /// ExpandFCOPYSIGNToBitwiseOps - Expands fcopysign to a series of bitwise
525 SDOperand ExpandFCOPYSIGNToBitwiseOps(SDNode *Node, MVT::ValueType NVT,
526 SelectionDAG &DAG, TargetLowering &TLI) {
527 MVT::ValueType VT = Node->getValueType(0);
528 MVT::ValueType SrcVT = Node->getOperand(1).getValueType();
529 assert((SrcVT == MVT::f32 || SrcVT == MVT::f64) &&
530 "fcopysign expansion only supported for f32 and f64");
531 MVT::ValueType SrcNVT = (SrcVT == MVT::f64) ? MVT::i64 : MVT::i32;
533 // First get the sign bit of second operand.
534 SDOperand Mask1 = (SrcVT == MVT::f64)
535 ? DAG.getConstantFP(BitsToDouble(1ULL << 63), SrcVT)
536 : DAG.getConstantFP(BitsToFloat(1U << 31), SrcVT);
537 Mask1 = DAG.getNode(ISD::BIT_CONVERT, SrcNVT, Mask1);
538 SDOperand SignBit= DAG.getNode(ISD::BIT_CONVERT, SrcNVT, Node->getOperand(1));
539 SignBit = DAG.getNode(ISD::AND, SrcNVT, SignBit, Mask1);
540 // Shift right or sign-extend it if the two operands have different types.
541 int SizeDiff = MVT::getSizeInBits(SrcNVT) - MVT::getSizeInBits(NVT);
543 SignBit = DAG.getNode(ISD::SRL, SrcNVT, SignBit,
544 DAG.getConstant(SizeDiff, TLI.getShiftAmountTy()));
545 SignBit = DAG.getNode(ISD::TRUNCATE, NVT, SignBit);
546 } else if (SizeDiff < 0)
547 SignBit = DAG.getNode(ISD::SIGN_EXTEND, NVT, SignBit);
549 // Clear the sign bit of first operand.
550 SDOperand Mask2 = (VT == MVT::f64)
551 ? DAG.getConstantFP(BitsToDouble(~(1ULL << 63)), VT)
552 : DAG.getConstantFP(BitsToFloat(~(1U << 31)), VT);
553 Mask2 = DAG.getNode(ISD::BIT_CONVERT, NVT, Mask2);
554 SDOperand Result = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0));
555 Result = DAG.getNode(ISD::AND, NVT, Result, Mask2);
557 // Or the value with the sign bit.
558 Result = DAG.getNode(ISD::OR, NVT, Result, SignBit);
562 /// ExpandUnalignedStore - Expands an unaligned store to 2 half-size stores.
564 SDOperand ExpandUnalignedStore(StoreSDNode *ST, SelectionDAG &DAG,
565 TargetLowering &TLI) {
566 SDOperand Chain = ST->getChain();
567 SDOperand Ptr = ST->getBasePtr();
568 SDOperand Val = ST->getValue();
569 MVT::ValueType VT = Val.getValueType();
570 int Alignment = ST->getAlignment();
571 int SVOffset = ST->getSrcValueOffset();
572 if (MVT::isFloatingPoint(ST->getMemoryVT())) {
573 // Expand to a bitconvert of the value to the integer type of the
574 // same size, then a (misaligned) int store.
575 MVT::ValueType intVT;
578 else if (VT==MVT::f32)
581 assert(0 && "Unaligned load of unsupported floating point type");
583 SDOperand Result = DAG.getNode(ISD::BIT_CONVERT, intVT, Val);
584 return DAG.getStore(Chain, Result, Ptr, ST->getSrcValue(),
585 SVOffset, ST->isVolatile(), Alignment);
587 assert(MVT::isInteger(ST->getMemoryVT()) &&
588 "Unaligned store of unknown type.");
589 // Get the half-size VT
590 MVT::ValueType NewStoredVT = ST->getMemoryVT() - 1;
591 int NumBits = MVT::getSizeInBits(NewStoredVT);
592 int IncrementSize = NumBits / 8;
594 // Divide the stored value in two parts.
595 SDOperand ShiftAmount = DAG.getConstant(NumBits, TLI.getShiftAmountTy());
597 SDOperand Hi = DAG.getNode(ISD::SRL, VT, Val, ShiftAmount);
599 // Store the two parts
600 SDOperand Store1, Store2;
601 Store1 = DAG.getTruncStore(Chain, TLI.isLittleEndian()?Lo:Hi, Ptr,
602 ST->getSrcValue(), SVOffset, NewStoredVT,
603 ST->isVolatile(), Alignment);
604 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
605 DAG.getConstant(IncrementSize, TLI.getPointerTy()));
606 Alignment = MinAlign(Alignment, IncrementSize);
607 Store2 = DAG.getTruncStore(Chain, TLI.isLittleEndian()?Hi:Lo, Ptr,
608 ST->getSrcValue(), SVOffset + IncrementSize,
609 NewStoredVT, ST->isVolatile(), Alignment);
611 return DAG.getNode(ISD::TokenFactor, MVT::Other, Store1, Store2);
614 /// ExpandUnalignedLoad - Expands an unaligned load to 2 half-size loads.
616 SDOperand ExpandUnalignedLoad(LoadSDNode *LD, SelectionDAG &DAG,
617 TargetLowering &TLI) {
618 int SVOffset = LD->getSrcValueOffset();
619 SDOperand Chain = LD->getChain();
620 SDOperand Ptr = LD->getBasePtr();
621 MVT::ValueType VT = LD->getValueType(0);
622 MVT::ValueType LoadedVT = LD->getMemoryVT();
623 if (MVT::isFloatingPoint(VT) && !MVT::isVector(VT)) {
624 // Expand to a (misaligned) integer load of the same size,
625 // then bitconvert to floating point.
626 MVT::ValueType intVT;
627 if (LoadedVT == MVT::f64)
629 else if (LoadedVT == MVT::f32)
632 assert(0 && "Unaligned load of unsupported floating point type");
634 SDOperand newLoad = DAG.getLoad(intVT, Chain, Ptr, LD->getSrcValue(),
635 SVOffset, LD->isVolatile(),
637 SDOperand Result = DAG.getNode(ISD::BIT_CONVERT, LoadedVT, newLoad);
639 Result = DAG.getNode(ISD::FP_EXTEND, VT, Result);
641 SDOperand Ops[] = { Result, Chain };
642 return DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(VT, MVT::Other),
645 assert((MVT::isInteger(LoadedVT) || MVT::isVector(LoadedVT)) &&
646 "Unaligned load of unsupported type.");
648 // Compute the new VT that is half the size of the old one. We either have an
649 // integer MVT or we have a vector MVT.
650 unsigned NumBits = MVT::getSizeInBits(LoadedVT);
651 MVT::ValueType NewLoadedVT;
652 if (!MVT::isVector(LoadedVT)) {
653 NewLoadedVT = MVT::getIntegerType(NumBits/2);
655 // FIXME: This is not right for <1 x anything> it is also not right for
656 // non-power-of-two vectors.
657 NewLoadedVT = MVT::getVectorType(MVT::getVectorElementType(LoadedVT),
658 MVT::getVectorNumElements(LoadedVT)/2);
662 unsigned Alignment = LD->getAlignment();
663 unsigned IncrementSize = NumBits / 8;
664 ISD::LoadExtType HiExtType = LD->getExtensionType();
666 // If the original load is NON_EXTLOAD, the hi part load must be ZEXTLOAD.
667 if (HiExtType == ISD::NON_EXTLOAD)
668 HiExtType = ISD::ZEXTLOAD;
670 // Load the value in two parts
672 if (TLI.isLittleEndian()) {
673 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, VT, Chain, Ptr, LD->getSrcValue(),
674 SVOffset, NewLoadedVT, LD->isVolatile(), Alignment);
675 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
676 DAG.getConstant(IncrementSize, TLI.getPointerTy()));
677 Hi = DAG.getExtLoad(HiExtType, VT, Chain, Ptr, LD->getSrcValue(),
678 SVOffset + IncrementSize, NewLoadedVT, LD->isVolatile(),
679 MinAlign(Alignment, IncrementSize));
681 Hi = DAG.getExtLoad(HiExtType, VT, Chain, Ptr, LD->getSrcValue(), SVOffset,
682 NewLoadedVT,LD->isVolatile(), Alignment);
683 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
684 DAG.getConstant(IncrementSize, TLI.getPointerTy()));
685 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, VT, Chain, Ptr, LD->getSrcValue(),
686 SVOffset + IncrementSize, NewLoadedVT, LD->isVolatile(),
687 MinAlign(Alignment, IncrementSize));
690 // aggregate the two parts
691 SDOperand ShiftAmount = DAG.getConstant(NumBits, TLI.getShiftAmountTy());
692 SDOperand Result = DAG.getNode(ISD::SHL, VT, Hi, ShiftAmount);
693 Result = DAG.getNode(ISD::OR, VT, Result, Lo);
695 SDOperand TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
698 SDOperand Ops[] = { Result, TF };
699 return DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(VT, MVT::Other), Ops, 2);
702 /// UnrollVectorOp - We know that the given vector has a legal type, however
703 /// the operation it performs is not legal and is an operation that we have
704 /// no way of lowering. "Unroll" the vector, splitting out the scalars and
705 /// operating on each element individually.
706 SDOperand SelectionDAGLegalize::UnrollVectorOp(SDOperand Op) {
707 MVT::ValueType VT = Op.getValueType();
708 assert(isTypeLegal(VT) &&
709 "Caller should expand or promote operands that are not legal!");
710 assert(Op.Val->getNumValues() == 1 &&
711 "Can't unroll a vector with multiple results!");
712 unsigned NE = MVT::getVectorNumElements(VT);
713 MVT::ValueType EltVT = MVT::getVectorElementType(VT);
715 SmallVector<SDOperand, 8> Scalars;
716 SmallVector<SDOperand, 4> Operands(Op.getNumOperands());
717 for (unsigned i = 0; i != NE; ++i) {
718 for (unsigned j = 0; j != Op.getNumOperands(); ++j) {
719 SDOperand Operand = Op.getOperand(j);
720 MVT::ValueType OperandVT = Operand.getValueType();
721 if (MVT::isVector(OperandVT)) {
722 // A vector operand; extract a single element.
723 MVT::ValueType OperandEltVT = MVT::getVectorElementType(OperandVT);
724 Operands[j] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT,
727 DAG.getConstant(i, MVT::i32));
729 // A scalar operand; just use it as is.
730 Operands[j] = Operand;
733 Scalars.push_back(DAG.getNode(Op.getOpcode(), EltVT,
734 &Operands[0], Operands.size()));
737 return DAG.getNode(ISD::BUILD_VECTOR, VT, &Scalars[0], Scalars.size());
740 /// GetFPLibCall - Return the right libcall for the given floating point type.
741 static RTLIB::Libcall GetFPLibCall(MVT::ValueType VT,
742 RTLIB::Libcall Call_F32,
743 RTLIB::Libcall Call_F64,
744 RTLIB::Libcall Call_F80,
745 RTLIB::Libcall Call_PPCF128) {
747 VT == MVT::f32 ? Call_F32 :
748 VT == MVT::f64 ? Call_F64 :
749 VT == MVT::f80 ? Call_F80 :
750 VT == MVT::ppcf128 ? Call_PPCF128 :
751 RTLIB::UNKNOWN_LIBCALL;
754 /// LegalizeOp - We know that the specified value has a legal type, and
755 /// that its operands are legal. Now ensure that the operation itself
756 /// is legal, recursively ensuring that the operands' operations remain
758 SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
759 if (Op.getOpcode() == ISD::TargetConstant) // Allow illegal target nodes.
762 assert(isTypeLegal(Op.getValueType()) &&
763 "Caller should expand or promote operands that are not legal!");
764 SDNode *Node = Op.Val;
766 // If this operation defines any values that cannot be represented in a
767 // register on this target, make sure to expand or promote them.
768 if (Node->getNumValues() > 1) {
769 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
770 if (getTypeAction(Node->getValueType(i)) != Legal) {
771 HandleOp(Op.getValue(i));
772 assert(LegalizedNodes.count(Op) &&
773 "Handling didn't add legal operands!");
774 return LegalizedNodes[Op];
778 // Note that LegalizeOp may be reentered even from single-use nodes, which
779 // means that we always must cache transformed nodes.
780 DenseMap<SDOperand, SDOperand>::iterator I = LegalizedNodes.find(Op);
781 if (I != LegalizedNodes.end()) return I->second;
783 SDOperand Tmp1, Tmp2, Tmp3, Tmp4;
784 SDOperand Result = Op;
785 bool isCustom = false;
787 switch (Node->getOpcode()) {
788 case ISD::FrameIndex:
789 case ISD::EntryToken:
791 case ISD::BasicBlock:
792 case ISD::TargetFrameIndex:
793 case ISD::TargetJumpTable:
794 case ISD::TargetConstant:
795 case ISD::TargetConstantFP:
796 case ISD::TargetConstantPool:
797 case ISD::TargetGlobalAddress:
798 case ISD::TargetGlobalTLSAddress:
799 case ISD::TargetExternalSymbol:
802 case ISD::MEMOPERAND:
805 // Primitives must all be legal.
806 assert(TLI.isOperationLegal(Node->getOpcode(), Node->getValueType(0)) &&
807 "This must be legal!");
810 if (Node->getOpcode() >= ISD::BUILTIN_OP_END) {
811 // If this is a target node, legalize it by legalizing the operands then
812 // passing it through.
813 SmallVector<SDOperand, 8> Ops;
814 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
815 Ops.push_back(LegalizeOp(Node->getOperand(i)));
817 Result = DAG.UpdateNodeOperands(Result.getValue(0), &Ops[0], Ops.size());
819 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
820 AddLegalizedOperand(Op.getValue(i), Result.getValue(i));
821 return Result.getValue(Op.ResNo);
823 // Otherwise this is an unhandled builtin node. splat.
825 cerr << "NODE: "; Node->dump(&DAG); cerr << "\n";
827 assert(0 && "Do not know how to legalize this operator!");
829 case ISD::GLOBAL_OFFSET_TABLE:
830 case ISD::GlobalAddress:
831 case ISD::GlobalTLSAddress:
832 case ISD::ExternalSymbol:
833 case ISD::ConstantPool:
834 case ISD::JumpTable: // Nothing to do.
835 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
836 default: assert(0 && "This action is not supported yet!");
837 case TargetLowering::Custom:
838 Tmp1 = TLI.LowerOperation(Op, DAG);
839 if (Tmp1.Val) Result = Tmp1;
840 // FALLTHROUGH if the target doesn't want to lower this op after all.
841 case TargetLowering::Legal:
846 case ISD::RETURNADDR:
847 // The only option for these nodes is to custom lower them. If the target
848 // does not custom lower them, then return zero.
849 Tmp1 = TLI.LowerOperation(Op, DAG);
853 Result = DAG.getConstant(0, TLI.getPointerTy());
855 case ISD::FRAME_TO_ARGS_OFFSET: {
856 MVT::ValueType VT = Node->getValueType(0);
857 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
858 default: assert(0 && "This action is not supported yet!");
859 case TargetLowering::Custom:
860 Result = TLI.LowerOperation(Op, DAG);
861 if (Result.Val) break;
863 case TargetLowering::Legal:
864 Result = DAG.getConstant(0, VT);
869 case ISD::EXCEPTIONADDR: {
870 Tmp1 = LegalizeOp(Node->getOperand(0));
871 MVT::ValueType VT = Node->getValueType(0);
872 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
873 default: assert(0 && "This action is not supported yet!");
874 case TargetLowering::Expand: {
875 unsigned Reg = TLI.getExceptionAddressRegister();
876 Result = DAG.getCopyFromReg(Tmp1, Reg, VT);
879 case TargetLowering::Custom:
880 Result = TLI.LowerOperation(Op, DAG);
881 if (Result.Val) break;
883 case TargetLowering::Legal: {
884 SDOperand Ops[] = { DAG.getConstant(0, VT), Tmp1 };
885 Result = DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(VT, MVT::Other),
891 if (Result.Val->getNumValues() == 1) break;
893 assert(Result.Val->getNumValues() == 2 &&
894 "Cannot return more than two values!");
896 // Since we produced two values, make sure to remember that we
897 // legalized both of them.
898 Tmp1 = LegalizeOp(Result);
899 Tmp2 = LegalizeOp(Result.getValue(1));
900 AddLegalizedOperand(Op.getValue(0), Tmp1);
901 AddLegalizedOperand(Op.getValue(1), Tmp2);
902 return Op.ResNo ? Tmp2 : Tmp1;
903 case ISD::EHSELECTION: {
904 Tmp1 = LegalizeOp(Node->getOperand(0));
905 Tmp2 = LegalizeOp(Node->getOperand(1));
906 MVT::ValueType VT = Node->getValueType(0);
907 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
908 default: assert(0 && "This action is not supported yet!");
909 case TargetLowering::Expand: {
910 unsigned Reg = TLI.getExceptionSelectorRegister();
911 Result = DAG.getCopyFromReg(Tmp2, Reg, VT);
914 case TargetLowering::Custom:
915 Result = TLI.LowerOperation(Op, DAG);
916 if (Result.Val) break;
918 case TargetLowering::Legal: {
919 SDOperand Ops[] = { DAG.getConstant(0, VT), Tmp2 };
920 Result = DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(VT, MVT::Other),
926 if (Result.Val->getNumValues() == 1) break;
928 assert(Result.Val->getNumValues() == 2 &&
929 "Cannot return more than two values!");
931 // Since we produced two values, make sure to remember that we
932 // legalized both of them.
933 Tmp1 = LegalizeOp(Result);
934 Tmp2 = LegalizeOp(Result.getValue(1));
935 AddLegalizedOperand(Op.getValue(0), Tmp1);
936 AddLegalizedOperand(Op.getValue(1), Tmp2);
937 return Op.ResNo ? Tmp2 : Tmp1;
938 case ISD::EH_RETURN: {
939 MVT::ValueType VT = Node->getValueType(0);
940 // The only "good" option for this node is to custom lower it.
941 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
942 default: assert(0 && "This action is not supported at all!");
943 case TargetLowering::Custom:
944 Result = TLI.LowerOperation(Op, DAG);
945 if (Result.Val) break;
947 case TargetLowering::Legal:
948 // Target does not know, how to lower this, lower to noop
949 Result = LegalizeOp(Node->getOperand(0));
954 case ISD::AssertSext:
955 case ISD::AssertZext:
956 Tmp1 = LegalizeOp(Node->getOperand(0));
957 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
959 case ISD::MERGE_VALUES:
960 // Legalize eliminates MERGE_VALUES nodes.
961 Result = Node->getOperand(Op.ResNo);
963 case ISD::CopyFromReg:
964 Tmp1 = LegalizeOp(Node->getOperand(0));
965 Result = Op.getValue(0);
966 if (Node->getNumValues() == 2) {
967 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
969 assert(Node->getNumValues() == 3 && "Invalid copyfromreg!");
970 if (Node->getNumOperands() == 3) {
971 Tmp2 = LegalizeOp(Node->getOperand(2));
972 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1),Tmp2);
974 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
976 AddLegalizedOperand(Op.getValue(2), Result.getValue(2));
978 // Since CopyFromReg produces two values, make sure to remember that we
979 // legalized both of them.
980 AddLegalizedOperand(Op.getValue(0), Result);
981 AddLegalizedOperand(Op.getValue(1), Result.getValue(1));
982 return Result.getValue(Op.ResNo);
984 MVT::ValueType VT = Op.getValueType();
985 switch (TLI.getOperationAction(ISD::UNDEF, VT)) {
986 default: assert(0 && "This action is not supported yet!");
987 case TargetLowering::Expand:
988 if (MVT::isInteger(VT))
989 Result = DAG.getConstant(0, VT);
990 else if (MVT::isFloatingPoint(VT))
991 Result = DAG.getConstantFP(APFloat(APInt(MVT::getSizeInBits(VT), 0)),
994 assert(0 && "Unknown value type!");
996 case TargetLowering::Legal:
1002 case ISD::INTRINSIC_W_CHAIN:
1003 case ISD::INTRINSIC_WO_CHAIN:
1004 case ISD::INTRINSIC_VOID: {
1005 SmallVector<SDOperand, 8> Ops;
1006 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
1007 Ops.push_back(LegalizeOp(Node->getOperand(i)));
1008 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1010 // Allow the target to custom lower its intrinsics if it wants to.
1011 if (TLI.getOperationAction(Node->getOpcode(), MVT::Other) ==
1012 TargetLowering::Custom) {
1013 Tmp3 = TLI.LowerOperation(Result, DAG);
1014 if (Tmp3.Val) Result = Tmp3;
1017 if (Result.Val->getNumValues() == 1) break;
1019 // Must have return value and chain result.
1020 assert(Result.Val->getNumValues() == 2 &&
1021 "Cannot return more than two values!");
1023 // Since loads produce two values, make sure to remember that we
1024 // legalized both of them.
1025 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
1026 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
1027 return Result.getValue(Op.ResNo);
1031 assert(Node->getNumOperands() == 5 && "Invalid LOCATION node!");
1032 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the input chain.
1034 switch (TLI.getOperationAction(ISD::LOCATION, MVT::Other)) {
1035 case TargetLowering::Promote:
1036 default: assert(0 && "This action is not supported yet!");
1037 case TargetLowering::Expand: {
1038 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
1039 bool useDEBUG_LOC = TLI.isOperationLegal(ISD::DEBUG_LOC, MVT::Other);
1040 bool useLABEL = TLI.isOperationLegal(ISD::LABEL, MVT::Other);
1042 if (MMI && (useDEBUG_LOC || useLABEL)) {
1043 const std::string &FName =
1044 cast<StringSDNode>(Node->getOperand(3))->getValue();
1045 const std::string &DirName =
1046 cast<StringSDNode>(Node->getOperand(4))->getValue();
1047 unsigned SrcFile = MMI->RecordSource(DirName, FName);
1049 SmallVector<SDOperand, 8> Ops;
1050 Ops.push_back(Tmp1); // chain
1051 SDOperand LineOp = Node->getOperand(1);
1052 SDOperand ColOp = Node->getOperand(2);
1055 Ops.push_back(LineOp); // line #
1056 Ops.push_back(ColOp); // col #
1057 Ops.push_back(DAG.getConstant(SrcFile, MVT::i32)); // source file id
1058 Result = DAG.getNode(ISD::DEBUG_LOC, MVT::Other, &Ops[0], Ops.size());
1060 unsigned Line = cast<ConstantSDNode>(LineOp)->getValue();
1061 unsigned Col = cast<ConstantSDNode>(ColOp)->getValue();
1062 unsigned ID = MMI->RecordSourceLine(Line, Col, SrcFile);
1063 Ops.push_back(DAG.getConstant(ID, MVT::i32));
1064 Ops.push_back(DAG.getConstant(0, MVT::i32)); // a debug label
1065 Result = DAG.getNode(ISD::LABEL, MVT::Other, &Ops[0], Ops.size());
1068 Result = Tmp1; // chain
1072 case TargetLowering::Legal:
1073 if (Tmp1 != Node->getOperand(0) ||
1074 getTypeAction(Node->getOperand(1).getValueType()) == Promote) {
1075 SmallVector<SDOperand, 8> Ops;
1076 Ops.push_back(Tmp1);
1077 if (getTypeAction(Node->getOperand(1).getValueType()) == Legal) {
1078 Ops.push_back(Node->getOperand(1)); // line # must be legal.
1079 Ops.push_back(Node->getOperand(2)); // col # must be legal.
1081 // Otherwise promote them.
1082 Ops.push_back(PromoteOp(Node->getOperand(1)));
1083 Ops.push_back(PromoteOp(Node->getOperand(2)));
1085 Ops.push_back(Node->getOperand(3)); // filename must be legal.
1086 Ops.push_back(Node->getOperand(4)); // working dir # must be legal.
1087 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1094 assert(Node->getNumOperands() == 3 && "Invalid DECLARE node!");
1095 switch (TLI.getOperationAction(ISD::DECLARE, MVT::Other)) {
1096 default: assert(0 && "This action is not supported yet!");
1097 case TargetLowering::Legal:
1098 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1099 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the address.
1100 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the variable.
1101 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1106 case ISD::DEBUG_LOC:
1107 assert(Node->getNumOperands() == 4 && "Invalid DEBUG_LOC node!");
1108 switch (TLI.getOperationAction(ISD::DEBUG_LOC, MVT::Other)) {
1109 default: assert(0 && "This action is not supported yet!");
1110 case TargetLowering::Legal:
1111 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1112 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the line #.
1113 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the col #.
1114 Tmp4 = LegalizeOp(Node->getOperand(3)); // Legalize the source file id.
1115 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4);
1121 assert(Node->getNumOperands() == 3 && "Invalid LABEL node!");
1122 switch (TLI.getOperationAction(ISD::LABEL, MVT::Other)) {
1123 default: assert(0 && "This action is not supported yet!");
1124 case TargetLowering::Legal:
1125 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1126 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the label id.
1127 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the "flavor" operand.
1128 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1130 case TargetLowering::Expand:
1131 Result = LegalizeOp(Node->getOperand(0));
1136 case ISD::MEMBARRIER: {
1137 assert(Node->getNumOperands() == 6 && "Invalid MemBarrier node!");
1138 switch (TLI.getOperationAction(ISD::MEMBARRIER, MVT::Other)) {
1139 default: assert(0 && "This action is not supported yet!");
1140 case TargetLowering::Legal: {
1142 Ops[0] = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1143 for (int x = 1; x < 6; ++x) {
1144 Ops[x] = Node->getOperand(x);
1145 if (!isTypeLegal(Ops[x].getValueType()))
1146 Ops[x] = PromoteOp(Ops[x]);
1148 Result = DAG.UpdateNodeOperands(Result, &Ops[0], 6);
1151 case TargetLowering::Expand:
1152 //There is no libgcc call for this op
1153 Result = Node->getOperand(0); // Noop
1159 case ISD::ATOMIC_LCS:
1160 case ISD::ATOMIC_LAS:
1161 case ISD::ATOMIC_SWAP: {
1162 assert(((Node->getNumOperands() == 4 && Node->getOpcode() == ISD::ATOMIC_LCS) ||
1163 (Node->getNumOperands() == 3 && Node->getOpcode() == ISD::ATOMIC_LAS) ||
1164 (Node->getNumOperands() == 3 && Node->getOpcode() == ISD::ATOMIC_SWAP)) &&
1165 "Invalid MemBarrier node!");
1166 int num = Node->getOpcode() == ISD::ATOMIC_LCS ? 4 : 3;
1167 MVT::ValueType VT = Node->getValueType(0);
1168 switch (TLI.getOperationAction(ISD::ATOMIC_LCS, VT)) {
1169 default: assert(0 && "This action is not supported yet!");
1170 case TargetLowering::Legal: {
1172 for (int x = 0; x < num; ++x)
1173 Ops[x] = LegalizeOp(Node->getOperand(x));
1174 Result = DAG.UpdateNodeOperands(Result, &Ops[0], num);
1175 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
1176 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
1177 return Result.getValue(Op.ResNo);
1184 case ISD::Constant: {
1185 ConstantSDNode *CN = cast<ConstantSDNode>(Node);
1187 TLI.getOperationAction(ISD::Constant, CN->getValueType(0));
1189 // We know we don't need to expand constants here, constants only have one
1190 // value and we check that it is fine above.
1192 if (opAction == TargetLowering::Custom) {
1193 Tmp1 = TLI.LowerOperation(Result, DAG);
1199 case ISD::ConstantFP: {
1200 // Spill FP immediates to the constant pool if the target cannot directly
1201 // codegen them. Targets often have some immediate values that can be
1202 // efficiently generated into an FP register without a load. We explicitly
1203 // leave these constants as ConstantFP nodes for the target to deal with.
1204 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node);
1206 switch (TLI.getOperationAction(ISD::ConstantFP, CFP->getValueType(0))) {
1207 default: assert(0 && "This action is not supported yet!");
1208 case TargetLowering::Legal:
1210 case TargetLowering::Custom:
1211 Tmp3 = TLI.LowerOperation(Result, DAG);
1217 case TargetLowering::Expand: {
1218 // Check to see if this FP immediate is already legal.
1219 bool isLegal = false;
1220 for (TargetLowering::legal_fpimm_iterator I = TLI.legal_fpimm_begin(),
1221 E = TLI.legal_fpimm_end(); I != E; ++I) {
1222 if (CFP->isExactlyValue(*I)) {
1227 // If this is a legal constant, turn it into a TargetConstantFP node.
1230 Result = ExpandConstantFP(CFP, true, DAG, TLI);
1235 case ISD::TokenFactor:
1236 if (Node->getNumOperands() == 2) {
1237 Tmp1 = LegalizeOp(Node->getOperand(0));
1238 Tmp2 = LegalizeOp(Node->getOperand(1));
1239 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1240 } else if (Node->getNumOperands() == 3) {
1241 Tmp1 = LegalizeOp(Node->getOperand(0));
1242 Tmp2 = LegalizeOp(Node->getOperand(1));
1243 Tmp3 = LegalizeOp(Node->getOperand(2));
1244 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1246 SmallVector<SDOperand, 8> Ops;
1247 // Legalize the operands.
1248 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
1249 Ops.push_back(LegalizeOp(Node->getOperand(i)));
1250 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1254 case ISD::FORMAL_ARGUMENTS:
1256 // The only option for this is to custom lower it.
1257 Tmp3 = TLI.LowerOperation(Result.getValue(0), DAG);
1258 assert(Tmp3.Val && "Target didn't custom lower this node!");
1260 // The number of incoming and outgoing values should match; unless the final
1261 // outgoing value is a flag.
1262 assert((Tmp3.Val->getNumValues() == Result.Val->getNumValues() ||
1263 (Tmp3.Val->getNumValues() == Result.Val->getNumValues() + 1 &&
1264 Tmp3.Val->getValueType(Tmp3.Val->getNumValues() - 1) ==
1266 "Lowering call/formal_arguments produced unexpected # results!");
1268 // Since CALL/FORMAL_ARGUMENTS nodes produce multiple values, make sure to
1269 // remember that we legalized all of them, so it doesn't get relegalized.
1270 for (unsigned i = 0, e = Tmp3.Val->getNumValues(); i != e; ++i) {
1271 if (Tmp3.Val->getValueType(i) == MVT::Flag)
1273 Tmp1 = LegalizeOp(Tmp3.getValue(i));
1276 AddLegalizedOperand(SDOperand(Node, i), Tmp1);
1279 case ISD::EXTRACT_SUBREG: {
1280 Tmp1 = LegalizeOp(Node->getOperand(0));
1281 ConstantSDNode *idx = dyn_cast<ConstantSDNode>(Node->getOperand(1));
1282 assert(idx && "Operand must be a constant");
1283 Tmp2 = DAG.getTargetConstant(idx->getValue(), idx->getValueType(0));
1284 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1287 case ISD::INSERT_SUBREG: {
1288 Tmp1 = LegalizeOp(Node->getOperand(0));
1289 Tmp2 = LegalizeOp(Node->getOperand(1));
1290 ConstantSDNode *idx = dyn_cast<ConstantSDNode>(Node->getOperand(2));
1291 assert(idx && "Operand must be a constant");
1292 Tmp3 = DAG.getTargetConstant(idx->getValue(), idx->getValueType(0));
1293 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1296 case ISD::BUILD_VECTOR:
1297 switch (TLI.getOperationAction(ISD::BUILD_VECTOR, Node->getValueType(0))) {
1298 default: assert(0 && "This action is not supported yet!");
1299 case TargetLowering::Custom:
1300 Tmp3 = TLI.LowerOperation(Result, DAG);
1306 case TargetLowering::Expand:
1307 Result = ExpandBUILD_VECTOR(Result.Val);
1311 case ISD::INSERT_VECTOR_ELT:
1312 Tmp1 = LegalizeOp(Node->getOperand(0)); // InVec
1313 Tmp3 = LegalizeOp(Node->getOperand(2)); // InEltNo
1315 // The type of the value to insert may not be legal, even though the vector
1316 // type is legal. Legalize/Promote accordingly. We do not handle Expand
1318 switch (getTypeAction(Node->getOperand(1).getValueType())) {
1319 default: assert(0 && "Cannot expand insert element operand");
1320 case Legal: Tmp2 = LegalizeOp(Node->getOperand(1)); break;
1321 case Promote: Tmp2 = PromoteOp(Node->getOperand(1)); break;
1323 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1325 switch (TLI.getOperationAction(ISD::INSERT_VECTOR_ELT,
1326 Node->getValueType(0))) {
1327 default: assert(0 && "This action is not supported yet!");
1328 case TargetLowering::Legal:
1330 case TargetLowering::Custom:
1331 Tmp4 = TLI.LowerOperation(Result, DAG);
1337 case TargetLowering::Expand: {
1338 // If the insert index is a constant, codegen this as a scalar_to_vector,
1339 // then a shuffle that inserts it into the right position in the vector.
1340 if (ConstantSDNode *InsertPos = dyn_cast<ConstantSDNode>(Tmp3)) {
1341 // SCALAR_TO_VECTOR requires that the type of the value being inserted
1342 // match the element type of the vector being created.
1343 if (Tmp2.getValueType() ==
1344 MVT::getVectorElementType(Op.getValueType())) {
1345 SDOperand ScVec = DAG.getNode(ISD::SCALAR_TO_VECTOR,
1346 Tmp1.getValueType(), Tmp2);
1348 unsigned NumElts = MVT::getVectorNumElements(Tmp1.getValueType());
1349 MVT::ValueType ShufMaskVT = MVT::getIntVectorWithNumElements(NumElts);
1350 MVT::ValueType ShufMaskEltVT = MVT::getVectorElementType(ShufMaskVT);
1352 // We generate a shuffle of InVec and ScVec, so the shuffle mask
1353 // should be 0,1,2,3,4,5... with the appropriate element replaced with
1354 // elt 0 of the RHS.
1355 SmallVector<SDOperand, 8> ShufOps;
1356 for (unsigned i = 0; i != NumElts; ++i) {
1357 if (i != InsertPos->getValue())
1358 ShufOps.push_back(DAG.getConstant(i, ShufMaskEltVT));
1360 ShufOps.push_back(DAG.getConstant(NumElts, ShufMaskEltVT));
1362 SDOperand ShufMask = DAG.getNode(ISD::BUILD_VECTOR, ShufMaskVT,
1363 &ShufOps[0], ShufOps.size());
1365 Result = DAG.getNode(ISD::VECTOR_SHUFFLE, Tmp1.getValueType(),
1366 Tmp1, ScVec, ShufMask);
1367 Result = LegalizeOp(Result);
1372 // If the target doesn't support this, we have to spill the input vector
1373 // to a temporary stack slot, update the element, then reload it. This is
1374 // badness. We could also load the value into a vector register (either
1375 // with a "move to register" or "extload into register" instruction, then
1376 // permute it into place, if the idx is a constant and if the idx is
1377 // supported by the target.
1378 MVT::ValueType VT = Tmp1.getValueType();
1379 MVT::ValueType EltVT = MVT::getVectorElementType(VT);
1380 MVT::ValueType IdxVT = Tmp3.getValueType();
1381 MVT::ValueType PtrVT = TLI.getPointerTy();
1382 SDOperand StackPtr = DAG.CreateStackTemporary(VT);
1384 FrameIndexSDNode *StackPtrFI = cast<FrameIndexSDNode>(StackPtr.Val);
1385 int SPFI = StackPtrFI->getIndex();
1387 // Store the vector.
1388 SDOperand Ch = DAG.getStore(DAG.getEntryNode(), Tmp1, StackPtr,
1389 PseudoSourceValue::getFixedStack(),
1392 // Truncate or zero extend offset to target pointer type.
1393 unsigned CastOpc = (IdxVT > PtrVT) ? ISD::TRUNCATE : ISD::ZERO_EXTEND;
1394 Tmp3 = DAG.getNode(CastOpc, PtrVT, Tmp3);
1395 // Add the offset to the index.
1396 unsigned EltSize = MVT::getSizeInBits(EltVT)/8;
1397 Tmp3 = DAG.getNode(ISD::MUL, IdxVT, Tmp3,DAG.getConstant(EltSize, IdxVT));
1398 SDOperand StackPtr2 = DAG.getNode(ISD::ADD, IdxVT, Tmp3, StackPtr);
1399 // Store the scalar value.
1400 Ch = DAG.getTruncStore(Ch, Tmp2, StackPtr2,
1401 PseudoSourceValue::getFixedStack(), SPFI, EltVT);
1402 // Load the updated vector.
1403 Result = DAG.getLoad(VT, Ch, StackPtr,
1404 PseudoSourceValue::getFixedStack(), SPFI);
1409 case ISD::SCALAR_TO_VECTOR:
1410 if (!TLI.isTypeLegal(Node->getOperand(0).getValueType())) {
1411 Result = LegalizeOp(ExpandSCALAR_TO_VECTOR(Node));
1415 Tmp1 = LegalizeOp(Node->getOperand(0)); // InVal
1416 Result = DAG.UpdateNodeOperands(Result, Tmp1);
1417 switch (TLI.getOperationAction(ISD::SCALAR_TO_VECTOR,
1418 Node->getValueType(0))) {
1419 default: assert(0 && "This action is not supported yet!");
1420 case TargetLowering::Legal:
1422 case TargetLowering::Custom:
1423 Tmp3 = TLI.LowerOperation(Result, DAG);
1429 case TargetLowering::Expand:
1430 Result = LegalizeOp(ExpandSCALAR_TO_VECTOR(Node));
1434 case ISD::VECTOR_SHUFFLE:
1435 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the input vectors,
1436 Tmp2 = LegalizeOp(Node->getOperand(1)); // but not the shuffle mask.
1437 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
1439 // Allow targets to custom lower the SHUFFLEs they support.
1440 switch (TLI.getOperationAction(ISD::VECTOR_SHUFFLE,Result.getValueType())) {
1441 default: assert(0 && "Unknown operation action!");
1442 case TargetLowering::Legal:
1443 assert(isShuffleLegal(Result.getValueType(), Node->getOperand(2)) &&
1444 "vector shuffle should not be created if not legal!");
1446 case TargetLowering::Custom:
1447 Tmp3 = TLI.LowerOperation(Result, DAG);
1453 case TargetLowering::Expand: {
1454 MVT::ValueType VT = Node->getValueType(0);
1455 MVT::ValueType EltVT = MVT::getVectorElementType(VT);
1456 MVT::ValueType PtrVT = TLI.getPointerTy();
1457 SDOperand Mask = Node->getOperand(2);
1458 unsigned NumElems = Mask.getNumOperands();
1459 SmallVector<SDOperand,8> Ops;
1460 for (unsigned i = 0; i != NumElems; ++i) {
1461 SDOperand Arg = Mask.getOperand(i);
1462 if (Arg.getOpcode() == ISD::UNDEF) {
1463 Ops.push_back(DAG.getNode(ISD::UNDEF, EltVT));
1465 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
1466 unsigned Idx = cast<ConstantSDNode>(Arg)->getValue();
1468 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, Tmp1,
1469 DAG.getConstant(Idx, PtrVT)));
1471 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, Tmp2,
1472 DAG.getConstant(Idx - NumElems, PtrVT)));
1475 Result = DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size());
1478 case TargetLowering::Promote: {
1479 // Change base type to a different vector type.
1480 MVT::ValueType OVT = Node->getValueType(0);
1481 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
1483 // Cast the two input vectors.
1484 Tmp1 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp1);
1485 Tmp2 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp2);
1487 // Convert the shuffle mask to the right # elements.
1488 Tmp3 = SDOperand(isShuffleLegal(OVT, Node->getOperand(2)), 0);
1489 assert(Tmp3.Val && "Shuffle not legal?");
1490 Result = DAG.getNode(ISD::VECTOR_SHUFFLE, NVT, Tmp1, Tmp2, Tmp3);
1491 Result = DAG.getNode(ISD::BIT_CONVERT, OVT, Result);
1497 case ISD::EXTRACT_VECTOR_ELT:
1498 Tmp1 = Node->getOperand(0);
1499 Tmp2 = LegalizeOp(Node->getOperand(1));
1500 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1501 Result = ExpandEXTRACT_VECTOR_ELT(Result);
1504 case ISD::EXTRACT_SUBVECTOR:
1505 Tmp1 = Node->getOperand(0);
1506 Tmp2 = LegalizeOp(Node->getOperand(1));
1507 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1508 Result = ExpandEXTRACT_SUBVECTOR(Result);
1511 case ISD::CALLSEQ_START: {
1512 SDNode *CallEnd = FindCallEndFromCallStart(Node);
1514 // Recursively Legalize all of the inputs of the call end that do not lead
1515 // to this call start. This ensures that any libcalls that need be inserted
1516 // are inserted *before* the CALLSEQ_START.
1517 {SmallPtrSet<SDNode*, 32> NodesLeadingTo;
1518 for (unsigned i = 0, e = CallEnd->getNumOperands(); i != e; ++i)
1519 LegalizeAllNodesNotLeadingTo(CallEnd->getOperand(i).Val, Node,
1523 // Now that we legalized all of the inputs (which may have inserted
1524 // libcalls) create the new CALLSEQ_START node.
1525 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1527 // Merge in the last call, to ensure that this call start after the last
1529 if (LastCALLSEQ_END.getOpcode() != ISD::EntryToken) {
1530 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1531 Tmp1 = LegalizeOp(Tmp1);
1534 // Do not try to legalize the target-specific arguments (#1+).
1535 if (Tmp1 != Node->getOperand(0)) {
1536 SmallVector<SDOperand, 8> Ops(Node->op_begin(), Node->op_end());
1538 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1541 // Remember that the CALLSEQ_START is legalized.
1542 AddLegalizedOperand(Op.getValue(0), Result);
1543 if (Node->getNumValues() == 2) // If this has a flag result, remember it.
1544 AddLegalizedOperand(Op.getValue(1), Result.getValue(1));
1546 // Now that the callseq_start and all of the non-call nodes above this call
1547 // sequence have been legalized, legalize the call itself. During this
1548 // process, no libcalls can/will be inserted, guaranteeing that no calls
1550 assert(!IsLegalizingCall && "Inconsistent sequentialization of calls!");
1551 SDOperand InCallSEQ = LastCALLSEQ_END;
1552 // Note that we are selecting this call!
1553 LastCALLSEQ_END = SDOperand(CallEnd, 0);
1554 IsLegalizingCall = true;
1556 // Legalize the call, starting from the CALLSEQ_END.
1557 LegalizeOp(LastCALLSEQ_END);
1558 assert(!IsLegalizingCall && "CALLSEQ_END should have cleared this!");
1561 case ISD::CALLSEQ_END:
1562 // If the CALLSEQ_START node hasn't been legalized first, legalize it. This
1563 // will cause this node to be legalized as well as handling libcalls right.
1564 if (LastCALLSEQ_END.Val != Node) {
1565 LegalizeOp(SDOperand(FindCallStartFromCallEnd(Node), 0));
1566 DenseMap<SDOperand, SDOperand>::iterator I = LegalizedNodes.find(Op);
1567 assert(I != LegalizedNodes.end() &&
1568 "Legalizing the call start should have legalized this node!");
1572 // Otherwise, the call start has been legalized and everything is going
1573 // according to plan. Just legalize ourselves normally here.
1574 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1575 // Do not try to legalize the target-specific arguments (#1+), except for
1576 // an optional flag input.
1577 if (Node->getOperand(Node->getNumOperands()-1).getValueType() != MVT::Flag){
1578 if (Tmp1 != Node->getOperand(0)) {
1579 SmallVector<SDOperand, 8> Ops(Node->op_begin(), Node->op_end());
1581 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1584 Tmp2 = LegalizeOp(Node->getOperand(Node->getNumOperands()-1));
1585 if (Tmp1 != Node->getOperand(0) ||
1586 Tmp2 != Node->getOperand(Node->getNumOperands()-1)) {
1587 SmallVector<SDOperand, 8> Ops(Node->op_begin(), Node->op_end());
1590 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1593 assert(IsLegalizingCall && "Call sequence imbalance between start/end?");
1594 // This finishes up call legalization.
1595 IsLegalizingCall = false;
1597 // If the CALLSEQ_END node has a flag, remember that we legalized it.
1598 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
1599 if (Node->getNumValues() == 2)
1600 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
1601 return Result.getValue(Op.ResNo);
1602 case ISD::DYNAMIC_STACKALLOC: {
1603 MVT::ValueType VT = Node->getValueType(0);
1604 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1605 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the size.
1606 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the alignment.
1607 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1609 Tmp1 = Result.getValue(0);
1610 Tmp2 = Result.getValue(1);
1611 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
1612 default: assert(0 && "This action is not supported yet!");
1613 case TargetLowering::Expand: {
1614 unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore();
1615 assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and"
1616 " not tell us which reg is the stack pointer!");
1617 SDOperand Chain = Tmp1.getOperand(0);
1619 // Chain the dynamic stack allocation so that it doesn't modify the stack
1620 // pointer when other instructions are using the stack.
1621 Chain = DAG.getCALLSEQ_START(Chain,
1622 DAG.getConstant(0, TLI.getPointerTy()));
1624 SDOperand Size = Tmp2.getOperand(1);
1625 SDOperand SP = DAG.getCopyFromReg(Chain, SPReg, VT);
1626 Chain = SP.getValue(1);
1627 unsigned Align = cast<ConstantSDNode>(Tmp3)->getValue();
1628 unsigned StackAlign =
1629 TLI.getTargetMachine().getFrameInfo()->getStackAlignment();
1630 if (Align > StackAlign)
1631 SP = DAG.getNode(ISD::AND, VT, SP,
1632 DAG.getConstant(-(uint64_t)Align, VT));
1633 Tmp1 = DAG.getNode(ISD::SUB, VT, SP, Size); // Value
1634 Chain = DAG.getCopyToReg(Chain, SPReg, Tmp1); // Output chain
1637 DAG.getCALLSEQ_END(Chain,
1638 DAG.getConstant(0, TLI.getPointerTy()),
1639 DAG.getConstant(0, TLI.getPointerTy()),
1642 Tmp1 = LegalizeOp(Tmp1);
1643 Tmp2 = LegalizeOp(Tmp2);
1646 case TargetLowering::Custom:
1647 Tmp3 = TLI.LowerOperation(Tmp1, DAG);
1649 Tmp1 = LegalizeOp(Tmp3);
1650 Tmp2 = LegalizeOp(Tmp3.getValue(1));
1653 case TargetLowering::Legal:
1656 // Since this op produce two values, make sure to remember that we
1657 // legalized both of them.
1658 AddLegalizedOperand(SDOperand(Node, 0), Tmp1);
1659 AddLegalizedOperand(SDOperand(Node, 1), Tmp2);
1660 return Op.ResNo ? Tmp2 : Tmp1;
1662 case ISD::INLINEASM: {
1663 SmallVector<SDOperand, 8> Ops(Node->op_begin(), Node->op_end());
1664 bool Changed = false;
1665 // Legalize all of the operands of the inline asm, in case they are nodes
1666 // that need to be expanded or something. Note we skip the asm string and
1667 // all of the TargetConstant flags.
1668 SDOperand Op = LegalizeOp(Ops[0]);
1669 Changed = Op != Ops[0];
1672 bool HasInFlag = Ops.back().getValueType() == MVT::Flag;
1673 for (unsigned i = 2, e = Ops.size()-HasInFlag; i < e; ) {
1674 unsigned NumVals = cast<ConstantSDNode>(Ops[i])->getValue() >> 3;
1675 for (++i; NumVals; ++i, --NumVals) {
1676 SDOperand Op = LegalizeOp(Ops[i]);
1685 Op = LegalizeOp(Ops.back());
1686 Changed |= Op != Ops.back();
1691 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1693 // INLINE asm returns a chain and flag, make sure to add both to the map.
1694 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
1695 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
1696 return Result.getValue(Op.ResNo);
1699 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1700 // Ensure that libcalls are emitted before a branch.
1701 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1702 Tmp1 = LegalizeOp(Tmp1);
1703 LastCALLSEQ_END = DAG.getEntryNode();
1705 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
1708 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1709 // Ensure that libcalls are emitted before a branch.
1710 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1711 Tmp1 = LegalizeOp(Tmp1);
1712 LastCALLSEQ_END = DAG.getEntryNode();
1714 switch (getTypeAction(Node->getOperand(1).getValueType())) {
1715 default: assert(0 && "Indirect target must be legal type (pointer)!");
1717 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the condition.
1720 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1723 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1724 // Ensure that libcalls are emitted before a branch.
1725 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1726 Tmp1 = LegalizeOp(Tmp1);
1727 LastCALLSEQ_END = DAG.getEntryNode();
1729 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the jumptable node.
1730 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
1732 switch (TLI.getOperationAction(ISD::BR_JT, MVT::Other)) {
1733 default: assert(0 && "This action is not supported yet!");
1734 case TargetLowering::Legal: break;
1735 case TargetLowering::Custom:
1736 Tmp1 = TLI.LowerOperation(Result, DAG);
1737 if (Tmp1.Val) Result = Tmp1;
1739 case TargetLowering::Expand: {
1740 SDOperand Chain = Result.getOperand(0);
1741 SDOperand Table = Result.getOperand(1);
1742 SDOperand Index = Result.getOperand(2);
1744 MVT::ValueType PTy = TLI.getPointerTy();
1745 MachineFunction &MF = DAG.getMachineFunction();
1746 unsigned EntrySize = MF.getJumpTableInfo()->getEntrySize();
1747 Index= DAG.getNode(ISD::MUL, PTy, Index, DAG.getConstant(EntrySize, PTy));
1748 SDOperand Addr = DAG.getNode(ISD::ADD, PTy, Index, Table);
1751 switch (EntrySize) {
1752 default: assert(0 && "Size of jump table not supported yet."); break;
1753 case 4: LD = DAG.getLoad(MVT::i32, Chain, Addr,
1754 PseudoSourceValue::getJumpTable(), 0); break;
1755 case 8: LD = DAG.getLoad(MVT::i64, Chain, Addr,
1756 PseudoSourceValue::getJumpTable(), 0); break;
1760 if (TLI.getTargetMachine().getRelocationModel() == Reloc::PIC_) {
1761 // For PIC, the sequence is:
1762 // BRIND(load(Jumptable + index) + RelocBase)
1763 // RelocBase can be JumpTable, GOT or some sort of global base.
1764 if (PTy != MVT::i32)
1765 Addr = DAG.getNode(ISD::SIGN_EXTEND, PTy, Addr);
1766 Addr = DAG.getNode(ISD::ADD, PTy, Addr,
1767 TLI.getPICJumpTableRelocBase(Table, DAG));
1769 Result = DAG.getNode(ISD::BRIND, MVT::Other, LD.getValue(1), Addr);
1774 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1775 // Ensure that libcalls are emitted before a return.
1776 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1777 Tmp1 = LegalizeOp(Tmp1);
1778 LastCALLSEQ_END = DAG.getEntryNode();
1780 switch (getTypeAction(Node->getOperand(1).getValueType())) {
1781 case Expand: assert(0 && "It's impossible to expand bools");
1783 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the condition.
1786 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the condition.
1788 // The top bits of the promoted condition are not necessarily zero, ensure
1789 // that the value is properly zero extended.
1790 unsigned BitWidth = Tmp2.getValueSizeInBits();
1791 if (!DAG.MaskedValueIsZero(Tmp2,
1792 APInt::getHighBitsSet(BitWidth, BitWidth-1)))
1793 Tmp2 = DAG.getZeroExtendInReg(Tmp2, MVT::i1);
1798 // Basic block destination (Op#2) is always legal.
1799 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
1801 switch (TLI.getOperationAction(ISD::BRCOND, MVT::Other)) {
1802 default: assert(0 && "This action is not supported yet!");
1803 case TargetLowering::Legal: break;
1804 case TargetLowering::Custom:
1805 Tmp1 = TLI.LowerOperation(Result, DAG);
1806 if (Tmp1.Val) Result = Tmp1;
1808 case TargetLowering::Expand:
1809 // Expand brcond's setcc into its constituent parts and create a BR_CC
1811 if (Tmp2.getOpcode() == ISD::SETCC) {
1812 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1, Tmp2.getOperand(2),
1813 Tmp2.getOperand(0), Tmp2.getOperand(1),
1814 Node->getOperand(2));
1816 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1,
1817 DAG.getCondCode(ISD::SETNE), Tmp2,
1818 DAG.getConstant(0, Tmp2.getValueType()),
1819 Node->getOperand(2));
1825 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1826 // Ensure that libcalls are emitted before a branch.
1827 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1828 Tmp1 = LegalizeOp(Tmp1);
1829 Tmp2 = Node->getOperand(2); // LHS
1830 Tmp3 = Node->getOperand(3); // RHS
1831 Tmp4 = Node->getOperand(1); // CC
1833 LegalizeSetCCOperands(Tmp2, Tmp3, Tmp4);
1834 LastCALLSEQ_END = DAG.getEntryNode();
1836 // If we didn't get both a LHS and RHS back from LegalizeSetCCOperands,
1837 // the LHS is a legal SETCC itself. In this case, we need to compare
1838 // the result against zero to select between true and false values.
1839 if (Tmp3.Val == 0) {
1840 Tmp3 = DAG.getConstant(0, Tmp2.getValueType());
1841 Tmp4 = DAG.getCondCode(ISD::SETNE);
1844 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp4, Tmp2, Tmp3,
1845 Node->getOperand(4));
1847 switch (TLI.getOperationAction(ISD::BR_CC, Tmp3.getValueType())) {
1848 default: assert(0 && "Unexpected action for BR_CC!");
1849 case TargetLowering::Legal: break;
1850 case TargetLowering::Custom:
1851 Tmp4 = TLI.LowerOperation(Result, DAG);
1852 if (Tmp4.Val) Result = Tmp4;
1857 LoadSDNode *LD = cast<LoadSDNode>(Node);
1858 Tmp1 = LegalizeOp(LD->getChain()); // Legalize the chain.
1859 Tmp2 = LegalizeOp(LD->getBasePtr()); // Legalize the base pointer.
1861 ISD::LoadExtType ExtType = LD->getExtensionType();
1862 if (ExtType == ISD::NON_EXTLOAD) {
1863 MVT::ValueType VT = Node->getValueType(0);
1864 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, LD->getOffset());
1865 Tmp3 = Result.getValue(0);
1866 Tmp4 = Result.getValue(1);
1868 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
1869 default: assert(0 && "This action is not supported yet!");
1870 case TargetLowering::Legal:
1871 // If this is an unaligned load and the target doesn't support it,
1873 if (!TLI.allowsUnalignedMemoryAccesses()) {
1874 unsigned ABIAlignment = TLI.getTargetData()->
1875 getABITypeAlignment(MVT::getTypeForValueType(LD->getMemoryVT()));
1876 if (LD->getAlignment() < ABIAlignment){
1877 Result = ExpandUnalignedLoad(cast<LoadSDNode>(Result.Val), DAG,
1879 Tmp3 = Result.getOperand(0);
1880 Tmp4 = Result.getOperand(1);
1881 Tmp3 = LegalizeOp(Tmp3);
1882 Tmp4 = LegalizeOp(Tmp4);
1886 case TargetLowering::Custom:
1887 Tmp1 = TLI.LowerOperation(Tmp3, DAG);
1889 Tmp3 = LegalizeOp(Tmp1);
1890 Tmp4 = LegalizeOp(Tmp1.getValue(1));
1893 case TargetLowering::Promote: {
1894 // Only promote a load of vector type to another.
1895 assert(MVT::isVector(VT) && "Cannot promote this load!");
1896 // Change base type to a different vector type.
1897 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), VT);
1899 Tmp1 = DAG.getLoad(NVT, Tmp1, Tmp2, LD->getSrcValue(),
1900 LD->getSrcValueOffset(),
1901 LD->isVolatile(), LD->getAlignment());
1902 Tmp3 = LegalizeOp(DAG.getNode(ISD::BIT_CONVERT, VT, Tmp1));
1903 Tmp4 = LegalizeOp(Tmp1.getValue(1));
1907 // Since loads produce two values, make sure to remember that we
1908 // legalized both of them.
1909 AddLegalizedOperand(SDOperand(Node, 0), Tmp3);
1910 AddLegalizedOperand(SDOperand(Node, 1), Tmp4);
1911 return Op.ResNo ? Tmp4 : Tmp3;
1913 MVT::ValueType SrcVT = LD->getMemoryVT();
1914 unsigned SrcWidth = MVT::getSizeInBits(SrcVT);
1915 int SVOffset = LD->getSrcValueOffset();
1916 unsigned Alignment = LD->getAlignment();
1917 bool isVolatile = LD->isVolatile();
1919 if (SrcWidth != MVT::getStoreSizeInBits(SrcVT) &&
1920 // Some targets pretend to have an i1 loading operation, and actually
1921 // load an i8. This trick is correct for ZEXTLOAD because the top 7
1922 // bits are guaranteed to be zero; it helps the optimizers understand
1923 // that these bits are zero. It is also useful for EXTLOAD, since it
1924 // tells the optimizers that those bits are undefined. It would be
1925 // nice to have an effective generic way of getting these benefits...
1926 // Until such a way is found, don't insist on promoting i1 here.
1927 (SrcVT != MVT::i1 ||
1928 TLI.getLoadXAction(ExtType, MVT::i1) == TargetLowering::Promote)) {
1929 // Promote to a byte-sized load if not loading an integral number of
1930 // bytes. For example, promote EXTLOAD:i20 -> EXTLOAD:i24.
1931 unsigned NewWidth = MVT::getStoreSizeInBits(SrcVT);
1932 MVT::ValueType NVT = MVT::getIntegerType(NewWidth);
1935 // The extra bits are guaranteed to be zero, since we stored them that
1936 // way. A zext load from NVT thus automatically gives zext from SrcVT.
1938 ISD::LoadExtType NewExtType =
1939 ExtType == ISD::ZEXTLOAD ? ISD::ZEXTLOAD : ISD::EXTLOAD;
1941 Result = DAG.getExtLoad(NewExtType, Node->getValueType(0),
1942 Tmp1, Tmp2, LD->getSrcValue(), SVOffset,
1943 NVT, isVolatile, Alignment);
1945 Ch = Result.getValue(1); // The chain.
1947 if (ExtType == ISD::SEXTLOAD)
1948 // Having the top bits zero doesn't help when sign extending.
1949 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(),
1950 Result, DAG.getValueType(SrcVT));
1951 else if (ExtType == ISD::ZEXTLOAD || NVT == Result.getValueType())
1952 // All the top bits are guaranteed to be zero - inform the optimizers.
1953 Result = DAG.getNode(ISD::AssertZext, Result.getValueType(), Result,
1954 DAG.getValueType(SrcVT));
1956 Tmp1 = LegalizeOp(Result);
1957 Tmp2 = LegalizeOp(Ch);
1958 } else if (SrcWidth & (SrcWidth - 1)) {
1959 // If not loading a power-of-2 number of bits, expand as two loads.
1960 assert(MVT::isExtendedVT(SrcVT) && !MVT::isVector(SrcVT) &&
1961 "Unsupported extload!");
1962 unsigned RoundWidth = 1 << Log2_32(SrcWidth);
1963 assert(RoundWidth < SrcWidth);
1964 unsigned ExtraWidth = SrcWidth - RoundWidth;
1965 assert(ExtraWidth < RoundWidth);
1966 assert(!(RoundWidth % 8) && !(ExtraWidth % 8) &&
1967 "Load size not an integral number of bytes!");
1968 MVT::ValueType RoundVT = MVT::getIntegerType(RoundWidth);
1969 MVT::ValueType ExtraVT = MVT::getIntegerType(ExtraWidth);
1970 SDOperand Lo, Hi, Ch;
1971 unsigned IncrementSize;
1973 if (TLI.isLittleEndian()) {
1974 // EXTLOAD:i24 -> ZEXTLOAD:i16 | (shl EXTLOAD@+2:i8, 16)
1975 // Load the bottom RoundWidth bits.
1976 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, Node->getValueType(0), Tmp1, Tmp2,
1977 LD->getSrcValue(), SVOffset, RoundVT, isVolatile,
1980 // Load the remaining ExtraWidth bits.
1981 IncrementSize = RoundWidth / 8;
1982 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2,
1983 DAG.getIntPtrConstant(IncrementSize));
1984 Hi = DAG.getExtLoad(ExtType, Node->getValueType(0), Tmp1, Tmp2,
1985 LD->getSrcValue(), SVOffset + IncrementSize,
1986 ExtraVT, isVolatile,
1987 MinAlign(Alignment, IncrementSize));
1989 // Build a factor node to remember that this load is independent of the
1991 Ch = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
1994 // Move the top bits to the right place.
1995 Hi = DAG.getNode(ISD::SHL, Hi.getValueType(), Hi,
1996 DAG.getConstant(RoundWidth, TLI.getShiftAmountTy()));
1998 // Join the hi and lo parts.
1999 Result = DAG.getNode(ISD::OR, Node->getValueType(0), Lo, Hi);
2001 // Big endian - avoid unaligned loads.
2002 // EXTLOAD:i24 -> (shl EXTLOAD:i16, 8) | ZEXTLOAD@+2:i8
2003 // Load the top RoundWidth bits.
2004 Hi = DAG.getExtLoad(ExtType, Node->getValueType(0), Tmp1, Tmp2,
2005 LD->getSrcValue(), SVOffset, RoundVT, isVolatile,
2008 // Load the remaining ExtraWidth bits.
2009 IncrementSize = RoundWidth / 8;
2010 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2,
2011 DAG.getIntPtrConstant(IncrementSize));
2012 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, Node->getValueType(0), Tmp1, Tmp2,
2013 LD->getSrcValue(), SVOffset + IncrementSize,
2014 ExtraVT, isVolatile,
2015 MinAlign(Alignment, IncrementSize));
2017 // Build a factor node to remember that this load is independent of the
2019 Ch = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
2022 // Move the top bits to the right place.
2023 Hi = DAG.getNode(ISD::SHL, Hi.getValueType(), Hi,
2024 DAG.getConstant(ExtraWidth, TLI.getShiftAmountTy()));
2026 // Join the hi and lo parts.
2027 Result = DAG.getNode(ISD::OR, Node->getValueType(0), Lo, Hi);
2030 Tmp1 = LegalizeOp(Result);
2031 Tmp2 = LegalizeOp(Ch);
2033 switch (TLI.getLoadXAction(ExtType, SrcVT)) {
2034 default: assert(0 && "This action is not supported yet!");
2035 case TargetLowering::Custom:
2038 case TargetLowering::Legal:
2039 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, LD->getOffset());
2040 Tmp1 = Result.getValue(0);
2041 Tmp2 = Result.getValue(1);
2044 Tmp3 = TLI.LowerOperation(Result, DAG);
2046 Tmp1 = LegalizeOp(Tmp3);
2047 Tmp2 = LegalizeOp(Tmp3.getValue(1));
2050 // If this is an unaligned load and the target doesn't support it,
2052 if (!TLI.allowsUnalignedMemoryAccesses()) {
2053 unsigned ABIAlignment = TLI.getTargetData()->
2054 getABITypeAlignment(MVT::getTypeForValueType(LD->getMemoryVT()));
2055 if (LD->getAlignment() < ABIAlignment){
2056 Result = ExpandUnalignedLoad(cast<LoadSDNode>(Result.Val), DAG,
2058 Tmp1 = Result.getOperand(0);
2059 Tmp2 = Result.getOperand(1);
2060 Tmp1 = LegalizeOp(Tmp1);
2061 Tmp2 = LegalizeOp(Tmp2);
2066 case TargetLowering::Expand:
2067 // f64 = EXTLOAD f32 should expand to LOAD, FP_EXTEND
2068 if (SrcVT == MVT::f32 && Node->getValueType(0) == MVT::f64) {
2069 SDOperand Load = DAG.getLoad(SrcVT, Tmp1, Tmp2, LD->getSrcValue(),
2070 LD->getSrcValueOffset(),
2071 LD->isVolatile(), LD->getAlignment());
2072 Result = DAG.getNode(ISD::FP_EXTEND, Node->getValueType(0), Load);
2073 Tmp1 = LegalizeOp(Result); // Relegalize new nodes.
2074 Tmp2 = LegalizeOp(Load.getValue(1));
2077 assert(ExtType != ISD::EXTLOAD &&"EXTLOAD should always be supported!");
2078 // Turn the unsupported load into an EXTLOAD followed by an explicit
2079 // zero/sign extend inreg.
2080 Result = DAG.getExtLoad(ISD::EXTLOAD, Node->getValueType(0),
2081 Tmp1, Tmp2, LD->getSrcValue(),
2082 LD->getSrcValueOffset(), SrcVT,
2083 LD->isVolatile(), LD->getAlignment());
2085 if (ExtType == ISD::SEXTLOAD)
2086 ValRes = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(),
2087 Result, DAG.getValueType(SrcVT));
2089 ValRes = DAG.getZeroExtendInReg(Result, SrcVT);
2090 Tmp1 = LegalizeOp(ValRes); // Relegalize new nodes.
2091 Tmp2 = LegalizeOp(Result.getValue(1)); // Relegalize new nodes.
2096 // Since loads produce two values, make sure to remember that we legalized
2098 AddLegalizedOperand(SDOperand(Node, 0), Tmp1);
2099 AddLegalizedOperand(SDOperand(Node, 1), Tmp2);
2100 return Op.ResNo ? Tmp2 : Tmp1;
2103 case ISD::EXTRACT_ELEMENT: {
2104 MVT::ValueType OpTy = Node->getOperand(0).getValueType();
2105 switch (getTypeAction(OpTy)) {
2106 default: assert(0 && "EXTRACT_ELEMENT action for type unimplemented!");
2108 if (cast<ConstantSDNode>(Node->getOperand(1))->getValue()) {
2110 Result = DAG.getNode(ISD::SRL, OpTy, Node->getOperand(0),
2111 DAG.getConstant(MVT::getSizeInBits(OpTy)/2,
2112 TLI.getShiftAmountTy()));
2113 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), Result);
2116 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0),
2117 Node->getOperand(0));
2121 // Get both the low and high parts.
2122 ExpandOp(Node->getOperand(0), Tmp1, Tmp2);
2123 if (cast<ConstantSDNode>(Node->getOperand(1))->getValue())
2124 Result = Tmp2; // 1 -> Hi
2126 Result = Tmp1; // 0 -> Lo
2132 case ISD::CopyToReg:
2133 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2135 assert(isTypeLegal(Node->getOperand(2).getValueType()) &&
2136 "Register type must be legal!");
2137 // Legalize the incoming value (must be a legal type).
2138 Tmp2 = LegalizeOp(Node->getOperand(2));
2139 if (Node->getNumValues() == 1) {
2140 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1), Tmp2);
2142 assert(Node->getNumValues() == 2 && "Unknown CopyToReg");
2143 if (Node->getNumOperands() == 4) {
2144 Tmp3 = LegalizeOp(Node->getOperand(3));
2145 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1), Tmp2,
2148 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1),Tmp2);
2151 // Since this produces two values, make sure to remember that we legalized
2153 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
2154 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
2160 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2162 // Ensure that libcalls are emitted before a return.
2163 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
2164 Tmp1 = LegalizeOp(Tmp1);
2165 LastCALLSEQ_END = DAG.getEntryNode();
2167 switch (Node->getNumOperands()) {
2169 Tmp2 = Node->getOperand(1);
2170 Tmp3 = Node->getOperand(2); // Signness
2171 switch (getTypeAction(Tmp2.getValueType())) {
2173 Result = DAG.UpdateNodeOperands(Result, Tmp1, LegalizeOp(Tmp2), Tmp3);
2176 if (!MVT::isVector(Tmp2.getValueType())) {
2178 ExpandOp(Tmp2, Lo, Hi);
2180 // Big endian systems want the hi reg first.
2181 if (TLI.isBigEndian())
2185 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Tmp3, Hi,Tmp3);
2187 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Tmp3);
2188 Result = LegalizeOp(Result);
2190 SDNode *InVal = Tmp2.Val;
2191 int InIx = Tmp2.ResNo;
2192 unsigned NumElems = MVT::getVectorNumElements(InVal->getValueType(InIx));
2193 MVT::ValueType EVT = MVT::getVectorElementType(InVal->getValueType(InIx));
2195 // Figure out if there is a simple type corresponding to this Vector
2196 // type. If so, convert to the vector type.
2197 MVT::ValueType TVT = MVT::getVectorType(EVT, NumElems);
2198 if (TLI.isTypeLegal(TVT)) {
2199 // Turn this into a return of the vector type.
2200 Tmp2 = LegalizeOp(Tmp2);
2201 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2202 } else if (NumElems == 1) {
2203 // Turn this into a return of the scalar type.
2204 Tmp2 = ScalarizeVectorOp(Tmp2);
2205 Tmp2 = LegalizeOp(Tmp2);
2206 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2208 // FIXME: Returns of gcc generic vectors smaller than a legal type
2209 // should be returned in integer registers!
2211 // The scalarized value type may not be legal, e.g. it might require
2212 // promotion or expansion. Relegalize the return.
2213 Result = LegalizeOp(Result);
2215 // FIXME: Returns of gcc generic vectors larger than a legal vector
2216 // type should be returned by reference!
2218 SplitVectorOp(Tmp2, Lo, Hi);
2219 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Tmp3, Hi,Tmp3);
2220 Result = LegalizeOp(Result);
2225 Tmp2 = PromoteOp(Node->getOperand(1));
2226 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2227 Result = LegalizeOp(Result);
2232 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2234 default: { // ret <values>
2235 SmallVector<SDOperand, 8> NewValues;
2236 NewValues.push_back(Tmp1);
2237 for (unsigned i = 1, e = Node->getNumOperands(); i < e; i += 2)
2238 switch (getTypeAction(Node->getOperand(i).getValueType())) {
2240 NewValues.push_back(LegalizeOp(Node->getOperand(i)));
2241 NewValues.push_back(Node->getOperand(i+1));
2245 assert(!MVT::isExtendedVT(Node->getOperand(i).getValueType()) &&
2246 "FIXME: TODO: implement returning non-legal vector types!");
2247 ExpandOp(Node->getOperand(i), Lo, Hi);
2248 NewValues.push_back(Lo);
2249 NewValues.push_back(Node->getOperand(i+1));
2251 NewValues.push_back(Hi);
2252 NewValues.push_back(Node->getOperand(i+1));
2257 assert(0 && "Can't promote multiple return value yet!");
2260 if (NewValues.size() == Node->getNumOperands())
2261 Result = DAG.UpdateNodeOperands(Result, &NewValues[0],NewValues.size());
2263 Result = DAG.getNode(ISD::RET, MVT::Other,
2264 &NewValues[0], NewValues.size());
2269 if (Result.getOpcode() == ISD::RET) {
2270 switch (TLI.getOperationAction(Result.getOpcode(), MVT::Other)) {
2271 default: assert(0 && "This action is not supported yet!");
2272 case TargetLowering::Legal: break;
2273 case TargetLowering::Custom:
2274 Tmp1 = TLI.LowerOperation(Result, DAG);
2275 if (Tmp1.Val) Result = Tmp1;
2281 StoreSDNode *ST = cast<StoreSDNode>(Node);
2282 Tmp1 = LegalizeOp(ST->getChain()); // Legalize the chain.
2283 Tmp2 = LegalizeOp(ST->getBasePtr()); // Legalize the pointer.
2284 int SVOffset = ST->getSrcValueOffset();
2285 unsigned Alignment = ST->getAlignment();
2286 bool isVolatile = ST->isVolatile();
2288 if (!ST->isTruncatingStore()) {
2289 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr'
2290 // FIXME: We shouldn't do this for TargetConstantFP's.
2291 // FIXME: move this to the DAG Combiner! Note that we can't regress due
2292 // to phase ordering between legalized code and the dag combiner. This
2293 // probably means that we need to integrate dag combiner and legalizer
2295 // We generally can't do this one for long doubles.
2296 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(ST->getValue())) {
2297 if (CFP->getValueType(0) == MVT::f32 &&
2298 getTypeAction(MVT::i32) == Legal) {
2299 Tmp3 = DAG.getConstant((uint32_t)CFP->getValueAPF().
2300 convertToAPInt().getZExtValue(),
2302 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2303 SVOffset, isVolatile, Alignment);
2305 } else if (CFP->getValueType(0) == MVT::f64) {
2306 // If this target supports 64-bit registers, do a single 64-bit store.
2307 if (getTypeAction(MVT::i64) == Legal) {
2308 Tmp3 = DAG.getConstant(CFP->getValueAPF().convertToAPInt().
2309 getZExtValue(), MVT::i64);
2310 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2311 SVOffset, isVolatile, Alignment);
2313 } else if (getTypeAction(MVT::i32) == Legal) {
2314 // Otherwise, if the target supports 32-bit registers, use 2 32-bit
2315 // stores. If the target supports neither 32- nor 64-bits, this
2316 // xform is certainly not worth it.
2317 uint64_t IntVal =CFP->getValueAPF().convertToAPInt().getZExtValue();
2318 SDOperand Lo = DAG.getConstant(uint32_t(IntVal), MVT::i32);
2319 SDOperand Hi = DAG.getConstant(uint32_t(IntVal >>32), MVT::i32);
2320 if (TLI.isBigEndian()) std::swap(Lo, Hi);
2322 Lo = DAG.getStore(Tmp1, Lo, Tmp2, ST->getSrcValue(),
2323 SVOffset, isVolatile, Alignment);
2324 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2,
2325 DAG.getIntPtrConstant(4));
2326 Hi = DAG.getStore(Tmp1, Hi, Tmp2, ST->getSrcValue(), SVOffset+4,
2327 isVolatile, MinAlign(Alignment, 4U));
2329 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi);
2335 switch (getTypeAction(ST->getMemoryVT())) {
2337 Tmp3 = LegalizeOp(ST->getValue());
2338 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2,
2341 MVT::ValueType VT = Tmp3.getValueType();
2342 switch (TLI.getOperationAction(ISD::STORE, VT)) {
2343 default: assert(0 && "This action is not supported yet!");
2344 case TargetLowering::Legal:
2345 // If this is an unaligned store and the target doesn't support it,
2347 if (!TLI.allowsUnalignedMemoryAccesses()) {
2348 unsigned ABIAlignment = TLI.getTargetData()->
2349 getABITypeAlignment(MVT::getTypeForValueType(ST->getMemoryVT()));
2350 if (ST->getAlignment() < ABIAlignment)
2351 Result = ExpandUnalignedStore(cast<StoreSDNode>(Result.Val), DAG,
2355 case TargetLowering::Custom:
2356 Tmp1 = TLI.LowerOperation(Result, DAG);
2357 if (Tmp1.Val) Result = Tmp1;
2359 case TargetLowering::Promote:
2360 assert(MVT::isVector(VT) && "Unknown legal promote case!");
2361 Tmp3 = DAG.getNode(ISD::BIT_CONVERT,
2362 TLI.getTypeToPromoteTo(ISD::STORE, VT), Tmp3);
2363 Result = DAG.getStore(Tmp1, Tmp3, Tmp2,
2364 ST->getSrcValue(), SVOffset, isVolatile,
2371 // Truncate the value and store the result.
2372 Tmp3 = PromoteOp(ST->getValue());
2373 Result = DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2374 SVOffset, ST->getMemoryVT(),
2375 isVolatile, Alignment);
2379 unsigned IncrementSize = 0;
2382 // If this is a vector type, then we have to calculate the increment as
2383 // the product of the element size in bytes, and the number of elements
2384 // in the high half of the vector.
2385 if (MVT::isVector(ST->getValue().getValueType())) {
2386 SDNode *InVal = ST->getValue().Val;
2387 int InIx = ST->getValue().ResNo;
2388 MVT::ValueType InVT = InVal->getValueType(InIx);
2389 unsigned NumElems = MVT::getVectorNumElements(InVT);
2390 MVT::ValueType EVT = MVT::getVectorElementType(InVT);
2392 // Figure out if there is a simple type corresponding to this Vector
2393 // type. If so, convert to the vector type.
2394 MVT::ValueType TVT = MVT::getVectorType(EVT, NumElems);
2395 if (TLI.isTypeLegal(TVT)) {
2396 // Turn this into a normal store of the vector type.
2397 Tmp3 = LegalizeOp(ST->getValue());
2398 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2399 SVOffset, isVolatile, Alignment);
2400 Result = LegalizeOp(Result);
2402 } else if (NumElems == 1) {
2403 // Turn this into a normal store of the scalar type.
2404 Tmp3 = ScalarizeVectorOp(ST->getValue());
2405 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2406 SVOffset, isVolatile, Alignment);
2407 // The scalarized value type may not be legal, e.g. it might require
2408 // promotion or expansion. Relegalize the scalar store.
2409 Result = LegalizeOp(Result);
2412 SplitVectorOp(ST->getValue(), Lo, Hi);
2413 IncrementSize = MVT::getVectorNumElements(Lo.Val->getValueType(0)) *
2414 MVT::getSizeInBits(EVT)/8;
2417 ExpandOp(ST->getValue(), Lo, Hi);
2418 IncrementSize = Hi.Val ? MVT::getSizeInBits(Hi.getValueType())/8 : 0;
2420 if (TLI.isBigEndian())
2424 Lo = DAG.getStore(Tmp1, Lo, Tmp2, ST->getSrcValue(),
2425 SVOffset, isVolatile, Alignment);
2427 if (Hi.Val == NULL) {
2428 // Must be int <-> float one-to-one expansion.
2433 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2,
2434 DAG.getIntPtrConstant(IncrementSize));
2435 assert(isTypeLegal(Tmp2.getValueType()) &&
2436 "Pointers must be legal!");
2437 SVOffset += IncrementSize;
2438 Alignment = MinAlign(Alignment, IncrementSize);
2439 Hi = DAG.getStore(Tmp1, Hi, Tmp2, ST->getSrcValue(),
2440 SVOffset, isVolatile, Alignment);
2441 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi);
2445 switch (getTypeAction(ST->getValue().getValueType())) {
2447 Tmp3 = LegalizeOp(ST->getValue());
2450 // We can promote the value, the truncstore will still take care of it.
2451 Tmp3 = PromoteOp(ST->getValue());
2454 // Just store the low part. This may become a non-trunc store, so make
2455 // sure to use getTruncStore, not UpdateNodeOperands below.
2456 ExpandOp(ST->getValue(), Tmp3, Tmp4);
2457 return DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2458 SVOffset, MVT::i8, isVolatile, Alignment);
2461 MVT::ValueType StVT = ST->getMemoryVT();
2462 unsigned StWidth = MVT::getSizeInBits(StVT);
2464 if (StWidth != MVT::getStoreSizeInBits(StVT)) {
2465 // Promote to a byte-sized store with upper bits zero if not
2466 // storing an integral number of bytes. For example, promote
2467 // TRUNCSTORE:i1 X -> TRUNCSTORE:i8 (and X, 1)
2468 MVT::ValueType NVT = MVT::getIntegerType(MVT::getStoreSizeInBits(StVT));
2469 Tmp3 = DAG.getZeroExtendInReg(Tmp3, StVT);
2470 Result = DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2471 SVOffset, NVT, isVolatile, Alignment);
2472 } else if (StWidth & (StWidth - 1)) {
2473 // If not storing a power-of-2 number of bits, expand as two stores.
2474 assert(MVT::isExtendedVT(StVT) && !MVT::isVector(StVT) &&
2475 "Unsupported truncstore!");
2476 unsigned RoundWidth = 1 << Log2_32(StWidth);
2477 assert(RoundWidth < StWidth);
2478 unsigned ExtraWidth = StWidth - RoundWidth;
2479 assert(ExtraWidth < RoundWidth);
2480 assert(!(RoundWidth % 8) && !(ExtraWidth % 8) &&
2481 "Store size not an integral number of bytes!");
2482 MVT::ValueType RoundVT = MVT::getIntegerType(RoundWidth);
2483 MVT::ValueType ExtraVT = MVT::getIntegerType(ExtraWidth);
2485 unsigned IncrementSize;
2487 if (TLI.isLittleEndian()) {
2488 // TRUNCSTORE:i24 X -> TRUNCSTORE:i16 X, TRUNCSTORE@+2:i8 (srl X, 16)
2489 // Store the bottom RoundWidth bits.
2490 Lo = DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2492 isVolatile, Alignment);
2494 // Store the remaining ExtraWidth bits.
2495 IncrementSize = RoundWidth / 8;
2496 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2,
2497 DAG.getIntPtrConstant(IncrementSize));
2498 Hi = DAG.getNode(ISD::SRL, Tmp3.getValueType(), Tmp3,
2499 DAG.getConstant(RoundWidth, TLI.getShiftAmountTy()));
2500 Hi = DAG.getTruncStore(Tmp1, Hi, Tmp2, ST->getSrcValue(),
2501 SVOffset + IncrementSize, ExtraVT, isVolatile,
2502 MinAlign(Alignment, IncrementSize));
2504 // Big endian - avoid unaligned stores.
2505 // TRUNCSTORE:i24 X -> TRUNCSTORE:i16 (srl X, 8), TRUNCSTORE@+2:i8 X
2506 // Store the top RoundWidth bits.
2507 Hi = DAG.getNode(ISD::SRL, Tmp3.getValueType(), Tmp3,
2508 DAG.getConstant(ExtraWidth, TLI.getShiftAmountTy()));
2509 Hi = DAG.getTruncStore(Tmp1, Hi, Tmp2, ST->getSrcValue(), SVOffset,
2510 RoundVT, isVolatile, Alignment);
2512 // Store the remaining ExtraWidth bits.
2513 IncrementSize = RoundWidth / 8;
2514 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2,
2515 DAG.getIntPtrConstant(IncrementSize));
2516 Lo = DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2517 SVOffset + IncrementSize, ExtraVT, isVolatile,
2518 MinAlign(Alignment, IncrementSize));
2521 // The order of the stores doesn't matter.
2522 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi);
2524 if (Tmp1 != ST->getChain() || Tmp3 != ST->getValue() ||
2525 Tmp2 != ST->getBasePtr())
2526 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2,
2529 switch (TLI.getTruncStoreAction(ST->getValue().getValueType(), StVT)) {
2530 default: assert(0 && "This action is not supported yet!");
2531 case TargetLowering::Legal:
2532 // If this is an unaligned store and the target doesn't support it,
2534 if (!TLI.allowsUnalignedMemoryAccesses()) {
2535 unsigned ABIAlignment = TLI.getTargetData()->
2536 getABITypeAlignment(MVT::getTypeForValueType(ST->getMemoryVT()));
2537 if (ST->getAlignment() < ABIAlignment)
2538 Result = ExpandUnalignedStore(cast<StoreSDNode>(Result.Val), DAG,
2542 case TargetLowering::Custom:
2543 Result = TLI.LowerOperation(Result, DAG);
2546 // TRUNCSTORE:i16 i32 -> STORE i16
2547 assert(isTypeLegal(StVT) && "Do not know how to expand this store!");
2548 Tmp3 = DAG.getNode(ISD::TRUNCATE, StVT, Tmp3);
2549 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(), SVOffset,
2550 isVolatile, Alignment);
2558 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2559 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
2561 case ISD::STACKSAVE:
2562 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2563 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2564 Tmp1 = Result.getValue(0);
2565 Tmp2 = Result.getValue(1);
2567 switch (TLI.getOperationAction(ISD::STACKSAVE, MVT::Other)) {
2568 default: assert(0 && "This action is not supported yet!");
2569 case TargetLowering::Legal: break;
2570 case TargetLowering::Custom:
2571 Tmp3 = TLI.LowerOperation(Result, DAG);
2573 Tmp1 = LegalizeOp(Tmp3);
2574 Tmp2 = LegalizeOp(Tmp3.getValue(1));
2577 case TargetLowering::Expand:
2578 // Expand to CopyFromReg if the target set
2579 // StackPointerRegisterToSaveRestore.
2580 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) {
2581 Tmp1 = DAG.getCopyFromReg(Result.getOperand(0), SP,
2582 Node->getValueType(0));
2583 Tmp2 = Tmp1.getValue(1);
2585 Tmp1 = DAG.getNode(ISD::UNDEF, Node->getValueType(0));
2586 Tmp2 = Node->getOperand(0);
2591 // Since stacksave produce two values, make sure to remember that we
2592 // legalized both of them.
2593 AddLegalizedOperand(SDOperand(Node, 0), Tmp1);
2594 AddLegalizedOperand(SDOperand(Node, 1), Tmp2);
2595 return Op.ResNo ? Tmp2 : Tmp1;
2597 case ISD::STACKRESTORE:
2598 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2599 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
2600 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
2602 switch (TLI.getOperationAction(ISD::STACKRESTORE, MVT::Other)) {
2603 default: assert(0 && "This action is not supported yet!");
2604 case TargetLowering::Legal: break;
2605 case TargetLowering::Custom:
2606 Tmp1 = TLI.LowerOperation(Result, DAG);
2607 if (Tmp1.Val) Result = Tmp1;
2609 case TargetLowering::Expand:
2610 // Expand to CopyToReg if the target set
2611 // StackPointerRegisterToSaveRestore.
2612 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) {
2613 Result = DAG.getCopyToReg(Tmp1, SP, Tmp2);
2621 case ISD::READCYCLECOUNTER:
2622 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain
2623 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2624 switch (TLI.getOperationAction(ISD::READCYCLECOUNTER,
2625 Node->getValueType(0))) {
2626 default: assert(0 && "This action is not supported yet!");
2627 case TargetLowering::Legal:
2628 Tmp1 = Result.getValue(0);
2629 Tmp2 = Result.getValue(1);
2631 case TargetLowering::Custom:
2632 Result = TLI.LowerOperation(Result, DAG);
2633 Tmp1 = LegalizeOp(Result.getValue(0));
2634 Tmp2 = LegalizeOp(Result.getValue(1));
2638 // Since rdcc produce two values, make sure to remember that we legalized
2640 AddLegalizedOperand(SDOperand(Node, 0), Tmp1);
2641 AddLegalizedOperand(SDOperand(Node, 1), Tmp2);
2645 switch (getTypeAction(Node->getOperand(0).getValueType())) {
2646 case Expand: assert(0 && "It's impossible to expand bools");
2648 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the condition.
2651 Tmp1 = PromoteOp(Node->getOperand(0)); // Promote the condition.
2652 // Make sure the condition is either zero or one.
2653 unsigned BitWidth = Tmp1.getValueSizeInBits();
2654 if (!DAG.MaskedValueIsZero(Tmp1,
2655 APInt::getHighBitsSet(BitWidth, BitWidth-1)))
2656 Tmp1 = DAG.getZeroExtendInReg(Tmp1, MVT::i1);
2660 Tmp2 = LegalizeOp(Node->getOperand(1)); // TrueVal
2661 Tmp3 = LegalizeOp(Node->getOperand(2)); // FalseVal
2663 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2665 switch (TLI.getOperationAction(ISD::SELECT, Tmp2.getValueType())) {
2666 default: assert(0 && "This action is not supported yet!");
2667 case TargetLowering::Legal: break;
2668 case TargetLowering::Custom: {
2669 Tmp1 = TLI.LowerOperation(Result, DAG);
2670 if (Tmp1.Val) Result = Tmp1;
2673 case TargetLowering::Expand:
2674 if (Tmp1.getOpcode() == ISD::SETCC) {
2675 Result = DAG.getSelectCC(Tmp1.getOperand(0), Tmp1.getOperand(1),
2677 cast<CondCodeSDNode>(Tmp1.getOperand(2))->get());
2679 Result = DAG.getSelectCC(Tmp1,
2680 DAG.getConstant(0, Tmp1.getValueType()),
2681 Tmp2, Tmp3, ISD::SETNE);
2684 case TargetLowering::Promote: {
2685 MVT::ValueType NVT =
2686 TLI.getTypeToPromoteTo(ISD::SELECT, Tmp2.getValueType());
2687 unsigned ExtOp, TruncOp;
2688 if (MVT::isVector(Tmp2.getValueType())) {
2689 ExtOp = ISD::BIT_CONVERT;
2690 TruncOp = ISD::BIT_CONVERT;
2691 } else if (MVT::isInteger(Tmp2.getValueType())) {
2692 ExtOp = ISD::ANY_EXTEND;
2693 TruncOp = ISD::TRUNCATE;
2695 ExtOp = ISD::FP_EXTEND;
2696 TruncOp = ISD::FP_ROUND;
2698 // Promote each of the values to the new type.
2699 Tmp2 = DAG.getNode(ExtOp, NVT, Tmp2);
2700 Tmp3 = DAG.getNode(ExtOp, NVT, Tmp3);
2701 // Perform the larger operation, then round down.
2702 Result = DAG.getNode(ISD::SELECT, NVT, Tmp1, Tmp2,Tmp3);
2703 if (TruncOp != ISD::FP_ROUND)
2704 Result = DAG.getNode(TruncOp, Node->getValueType(0), Result);
2706 Result = DAG.getNode(TruncOp, Node->getValueType(0), Result,
2707 DAG.getIntPtrConstant(0));
2712 case ISD::SELECT_CC: {
2713 Tmp1 = Node->getOperand(0); // LHS
2714 Tmp2 = Node->getOperand(1); // RHS
2715 Tmp3 = LegalizeOp(Node->getOperand(2)); // True
2716 Tmp4 = LegalizeOp(Node->getOperand(3)); // False
2717 SDOperand CC = Node->getOperand(4);
2719 LegalizeSetCCOperands(Tmp1, Tmp2, CC);
2721 // If we didn't get both a LHS and RHS back from LegalizeSetCCOperands,
2722 // the LHS is a legal SETCC itself. In this case, we need to compare
2723 // the result against zero to select between true and false values.
2724 if (Tmp2.Val == 0) {
2725 Tmp2 = DAG.getConstant(0, Tmp1.getValueType());
2726 CC = DAG.getCondCode(ISD::SETNE);
2728 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4, CC);
2730 // Everything is legal, see if we should expand this op or something.
2731 switch (TLI.getOperationAction(ISD::SELECT_CC, Tmp3.getValueType())) {
2732 default: assert(0 && "This action is not supported yet!");
2733 case TargetLowering::Legal: break;
2734 case TargetLowering::Custom:
2735 Tmp1 = TLI.LowerOperation(Result, DAG);
2736 if (Tmp1.Val) Result = Tmp1;
2742 Tmp1 = Node->getOperand(0);
2743 Tmp2 = Node->getOperand(1);
2744 Tmp3 = Node->getOperand(2);
2745 LegalizeSetCCOperands(Tmp1, Tmp2, Tmp3);
2747 // If we had to Expand the SetCC operands into a SELECT node, then it may
2748 // not always be possible to return a true LHS & RHS. In this case, just
2749 // return the value we legalized, returned in the LHS
2750 if (Tmp2.Val == 0) {
2755 switch (TLI.getOperationAction(ISD::SETCC, Tmp1.getValueType())) {
2756 default: assert(0 && "Cannot handle this action for SETCC yet!");
2757 case TargetLowering::Custom:
2760 case TargetLowering::Legal:
2761 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2763 Tmp4 = TLI.LowerOperation(Result, DAG);
2764 if (Tmp4.Val) Result = Tmp4;
2767 case TargetLowering::Promote: {
2768 // First step, figure out the appropriate operation to use.
2769 // Allow SETCC to not be supported for all legal data types
2770 // Mostly this targets FP
2771 MVT::ValueType NewInTy = Node->getOperand(0).getValueType();
2772 MVT::ValueType OldVT = NewInTy; OldVT = OldVT;
2774 // Scan for the appropriate larger type to use.
2776 NewInTy = (MVT::ValueType)(NewInTy+1);
2778 assert(MVT::isInteger(NewInTy) == MVT::isInteger(OldVT) &&
2779 "Fell off of the edge of the integer world");
2780 assert(MVT::isFloatingPoint(NewInTy) == MVT::isFloatingPoint(OldVT) &&
2781 "Fell off of the edge of the floating point world");
2783 // If the target supports SETCC of this type, use it.
2784 if (TLI.isOperationLegal(ISD::SETCC, NewInTy))
2787 if (MVT::isInteger(NewInTy))
2788 assert(0 && "Cannot promote Legal Integer SETCC yet");
2790 Tmp1 = DAG.getNode(ISD::FP_EXTEND, NewInTy, Tmp1);
2791 Tmp2 = DAG.getNode(ISD::FP_EXTEND, NewInTy, Tmp2);
2793 Tmp1 = LegalizeOp(Tmp1);
2794 Tmp2 = LegalizeOp(Tmp2);
2795 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2796 Result = LegalizeOp(Result);
2799 case TargetLowering::Expand:
2800 // Expand a setcc node into a select_cc of the same condition, lhs, and
2801 // rhs that selects between const 1 (true) and const 0 (false).
2802 MVT::ValueType VT = Node->getValueType(0);
2803 Result = DAG.getNode(ISD::SELECT_CC, VT, Tmp1, Tmp2,
2804 DAG.getConstant(1, VT), DAG.getConstant(0, VT),
2811 case ISD::MEMMOVE: {
2812 Tmp1 = LegalizeOp(Node->getOperand(0)); // Chain
2813 Tmp2 = LegalizeOp(Node->getOperand(1)); // Pointer
2815 if (Node->getOpcode() == ISD::MEMSET) { // memset = ubyte
2816 switch (getTypeAction(Node->getOperand(2).getValueType())) {
2817 case Expand: assert(0 && "Cannot expand a byte!");
2819 Tmp3 = LegalizeOp(Node->getOperand(2));
2822 Tmp3 = PromoteOp(Node->getOperand(2));
2826 Tmp3 = LegalizeOp(Node->getOperand(2)); // memcpy/move = pointer,
2830 switch (getTypeAction(Node->getOperand(3).getValueType())) {
2832 // Length is too big, just take the lo-part of the length.
2834 ExpandOp(Node->getOperand(3), Tmp4, HiPart);
2838 Tmp4 = LegalizeOp(Node->getOperand(3));
2841 Tmp4 = PromoteOp(Node->getOperand(3));
2846 switch (getTypeAction(Node->getOperand(4).getValueType())) { // uint
2847 case Expand: assert(0 && "Cannot expand this yet!");
2849 Tmp5 = LegalizeOp(Node->getOperand(4));
2852 Tmp5 = PromoteOp(Node->getOperand(4));
2857 switch (getTypeAction(Node->getOperand(5).getValueType())) { // bool
2858 case Expand: assert(0 && "Cannot expand this yet!");
2860 Tmp6 = LegalizeOp(Node->getOperand(5));
2863 Tmp6 = PromoteOp(Node->getOperand(5));
2867 switch (TLI.getOperationAction(Node->getOpcode(), MVT::Other)) {
2868 default: assert(0 && "This action not implemented for this operation!");
2869 case TargetLowering::Custom:
2872 case TargetLowering::Legal: {
2873 SDOperand Ops[] = { Tmp1, Tmp2, Tmp3, Tmp4, Tmp5, Tmp6 };
2874 Result = DAG.UpdateNodeOperands(Result, Ops, 6);
2876 Tmp1 = TLI.LowerOperation(Result, DAG);
2877 if (Tmp1.Val) Result = Tmp1;
2881 case TargetLowering::Expand: {
2882 // Otherwise, the target does not support this operation. Lower the
2883 // operation to an explicit libcall as appropriate.
2884 MVT::ValueType IntPtr = TLI.getPointerTy();
2885 const Type *IntPtrTy = TLI.getTargetData()->getIntPtrType();
2886 TargetLowering::ArgListTy Args;
2887 TargetLowering::ArgListEntry Entry;
2889 const char *FnName = 0;
2890 if (Node->getOpcode() == ISD::MEMSET) {
2891 Entry.Node = Tmp2; Entry.Ty = IntPtrTy;
2892 Args.push_back(Entry);
2893 // Extend the (previously legalized) ubyte argument to be an int value
2895 if (Tmp3.getValueType() > MVT::i32)
2896 Tmp3 = DAG.getNode(ISD::TRUNCATE, MVT::i32, Tmp3);
2898 Tmp3 = DAG.getNode(ISD::ZERO_EXTEND, MVT::i32, Tmp3);
2899 Entry.Node = Tmp3; Entry.Ty = Type::Int32Ty; Entry.isSExt = true;
2900 Args.push_back(Entry);
2901 Entry.Node = Tmp4; Entry.Ty = IntPtrTy; Entry.isSExt = false;
2902 Args.push_back(Entry);
2905 } else if (Node->getOpcode() == ISD::MEMCPY ||
2906 Node->getOpcode() == ISD::MEMMOVE) {
2907 Entry.Ty = IntPtrTy;
2908 Entry.Node = Tmp2; Args.push_back(Entry);
2909 Entry.Node = Tmp3; Args.push_back(Entry);
2910 Entry.Node = Tmp4; Args.push_back(Entry);
2911 FnName = Node->getOpcode() == ISD::MEMMOVE ? "memmove" : "memcpy";
2913 assert(0 && "Unknown op!");
2916 std::pair<SDOperand,SDOperand> CallResult =
2917 TLI.LowerCallTo(Tmp1, Type::VoidTy,
2918 false, false, false, CallingConv::C, false,
2919 DAG.getExternalSymbol(FnName, IntPtr), Args, DAG);
2920 Result = CallResult.second;
2927 case ISD::SHL_PARTS:
2928 case ISD::SRA_PARTS:
2929 case ISD::SRL_PARTS: {
2930 SmallVector<SDOperand, 8> Ops;
2931 bool Changed = false;
2932 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
2933 Ops.push_back(LegalizeOp(Node->getOperand(i)));
2934 Changed |= Ops.back() != Node->getOperand(i);
2937 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
2939 switch (TLI.getOperationAction(Node->getOpcode(),
2940 Node->getValueType(0))) {
2941 default: assert(0 && "This action is not supported yet!");
2942 case TargetLowering::Legal: break;
2943 case TargetLowering::Custom:
2944 Tmp1 = TLI.LowerOperation(Result, DAG);
2946 SDOperand Tmp2, RetVal(0, 0);
2947 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) {
2948 Tmp2 = LegalizeOp(Tmp1.getValue(i));
2949 AddLegalizedOperand(SDOperand(Node, i), Tmp2);
2953 assert(RetVal.Val && "Illegal result number");
2959 // Since these produce multiple values, make sure to remember that we
2960 // legalized all of them.
2961 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
2962 AddLegalizedOperand(SDOperand(Node, i), Result.getValue(i));
2963 return Result.getValue(Op.ResNo);
2985 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
2986 switch (getTypeAction(Node->getOperand(1).getValueType())) {
2987 case Expand: assert(0 && "Not possible");
2989 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the RHS.
2992 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the RHS.
2996 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
2998 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
2999 default: assert(0 && "BinOp legalize operation not supported");
3000 case TargetLowering::Legal: break;
3001 case TargetLowering::Custom:
3002 Tmp1 = TLI.LowerOperation(Result, DAG);
3003 if (Tmp1.Val) Result = Tmp1;
3005 case TargetLowering::Expand: {
3006 MVT::ValueType VT = Op.getValueType();
3008 // See if multiply or divide can be lowered using two-result operations.
3009 SDVTList VTs = DAG.getVTList(VT, VT);
3010 if (Node->getOpcode() == ISD::MUL) {
3011 // We just need the low half of the multiply; try both the signed
3012 // and unsigned forms. If the target supports both SMUL_LOHI and
3013 // UMUL_LOHI, form a preference by checking which forms of plain
3014 // MULH it supports.
3015 bool HasSMUL_LOHI = TLI.isOperationLegal(ISD::SMUL_LOHI, VT);
3016 bool HasUMUL_LOHI = TLI.isOperationLegal(ISD::UMUL_LOHI, VT);
3017 bool HasMULHS = TLI.isOperationLegal(ISD::MULHS, VT);
3018 bool HasMULHU = TLI.isOperationLegal(ISD::MULHU, VT);
3019 unsigned OpToUse = 0;
3020 if (HasSMUL_LOHI && !HasMULHS) {
3021 OpToUse = ISD::SMUL_LOHI;
3022 } else if (HasUMUL_LOHI && !HasMULHU) {
3023 OpToUse = ISD::UMUL_LOHI;
3024 } else if (HasSMUL_LOHI) {
3025 OpToUse = ISD::SMUL_LOHI;
3026 } else if (HasUMUL_LOHI) {
3027 OpToUse = ISD::UMUL_LOHI;
3030 Result = SDOperand(DAG.getNode(OpToUse, VTs, Tmp1, Tmp2).Val, 0);
3034 if (Node->getOpcode() == ISD::MULHS &&
3035 TLI.isOperationLegal(ISD::SMUL_LOHI, VT)) {
3036 Result = SDOperand(DAG.getNode(ISD::SMUL_LOHI, VTs, Tmp1, Tmp2).Val, 1);
3039 if (Node->getOpcode() == ISD::MULHU &&
3040 TLI.isOperationLegal(ISD::UMUL_LOHI, VT)) {
3041 Result = SDOperand(DAG.getNode(ISD::UMUL_LOHI, VTs, Tmp1, Tmp2).Val, 1);
3044 if (Node->getOpcode() == ISD::SDIV &&
3045 TLI.isOperationLegal(ISD::SDIVREM, VT)) {
3046 Result = SDOperand(DAG.getNode(ISD::SDIVREM, VTs, Tmp1, Tmp2).Val, 0);
3049 if (Node->getOpcode() == ISD::UDIV &&
3050 TLI.isOperationLegal(ISD::UDIVREM, VT)) {
3051 Result = SDOperand(DAG.getNode(ISD::UDIVREM, VTs, Tmp1, Tmp2).Val, 0);
3055 // Check to see if we have a libcall for this operator.
3056 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
3057 bool isSigned = false;
3058 switch (Node->getOpcode()) {
3061 if (VT == MVT::i32) {
3062 LC = Node->getOpcode() == ISD::UDIV
3063 ? RTLIB::UDIV_I32 : RTLIB::SDIV_I32;
3064 isSigned = Node->getOpcode() == ISD::SDIV;
3068 LC = GetFPLibCall(VT, RTLIB::POW_F32, RTLIB::POW_F64, RTLIB::POW_F80,
3069 RTLIB::POW_PPCF128);
3073 if (LC != RTLIB::UNKNOWN_LIBCALL) {
3075 Result = ExpandLibCall(TLI.getLibcallName(LC), Node, isSigned, Dummy);
3079 assert(MVT::isVector(Node->getValueType(0)) &&
3080 "Cannot expand this binary operator!");
3081 // Expand the operation into a bunch of nasty scalar code.
3082 Result = LegalizeOp(UnrollVectorOp(Op));
3085 case TargetLowering::Promote: {
3086 switch (Node->getOpcode()) {
3087 default: assert(0 && "Do not know how to promote this BinOp!");
3091 MVT::ValueType OVT = Node->getValueType(0);
3092 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
3093 assert(MVT::isVector(OVT) && "Cannot promote this BinOp!");
3094 // Bit convert each of the values to the new type.
3095 Tmp1 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp1);
3096 Tmp2 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp2);
3097 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
3098 // Bit convert the result back the original type.
3099 Result = DAG.getNode(ISD::BIT_CONVERT, OVT, Result);
3107 case ISD::SMUL_LOHI:
3108 case ISD::UMUL_LOHI:
3111 // These nodes will only be produced by target-specific lowering, so
3112 // they shouldn't be here if they aren't legal.
3113 assert(TLI.isOperationLegal(Node->getOpcode(), Node->getValueType(0)) &&
3114 "This must be legal!");
3116 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
3117 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS
3118 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
3121 case ISD::FCOPYSIGN: // FCOPYSIGN does not require LHS/RHS to match type!
3122 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
3123 switch (getTypeAction(Node->getOperand(1).getValueType())) {
3124 case Expand: assert(0 && "Not possible");
3126 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the RHS.
3129 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the RHS.
3133 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
3135 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3136 default: assert(0 && "Operation not supported");
3137 case TargetLowering::Custom:
3138 Tmp1 = TLI.LowerOperation(Result, DAG);
3139 if (Tmp1.Val) Result = Tmp1;
3141 case TargetLowering::Legal: break;
3142 case TargetLowering::Expand: {
3143 // If this target supports fabs/fneg natively and select is cheap,
3144 // do this efficiently.
3145 if (!TLI.isSelectExpensive() &&
3146 TLI.getOperationAction(ISD::FABS, Tmp1.getValueType()) ==
3147 TargetLowering::Legal &&
3148 TLI.getOperationAction(ISD::FNEG, Tmp1.getValueType()) ==
3149 TargetLowering::Legal) {
3150 // Get the sign bit of the RHS.
3151 MVT::ValueType IVT =
3152 Tmp2.getValueType() == MVT::f32 ? MVT::i32 : MVT::i64;
3153 SDOperand SignBit = DAG.getNode(ISD::BIT_CONVERT, IVT, Tmp2);
3154 SignBit = DAG.getSetCC(TLI.getSetCCResultTy(),
3155 SignBit, DAG.getConstant(0, IVT), ISD::SETLT);
3156 // Get the absolute value of the result.
3157 SDOperand AbsVal = DAG.getNode(ISD::FABS, Tmp1.getValueType(), Tmp1);
3158 // Select between the nabs and abs value based on the sign bit of
3160 Result = DAG.getNode(ISD::SELECT, AbsVal.getValueType(), SignBit,
3161 DAG.getNode(ISD::FNEG, AbsVal.getValueType(),
3164 Result = LegalizeOp(Result);
3168 // Otherwise, do bitwise ops!
3169 MVT::ValueType NVT =
3170 Node->getValueType(0) == MVT::f32 ? MVT::i32 : MVT::i64;
3171 Result = ExpandFCOPYSIGNToBitwiseOps(Node, NVT, DAG, TLI);
3172 Result = DAG.getNode(ISD::BIT_CONVERT, Node->getValueType(0), Result);
3173 Result = LegalizeOp(Result);
3181 Tmp1 = LegalizeOp(Node->getOperand(0));
3182 Tmp2 = LegalizeOp(Node->getOperand(1));
3183 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
3184 // Since this produces two values, make sure to remember that we legalized
3186 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
3187 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
3192 Tmp1 = LegalizeOp(Node->getOperand(0));
3193 Tmp2 = LegalizeOp(Node->getOperand(1));
3194 Tmp3 = LegalizeOp(Node->getOperand(2));
3195 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
3196 // Since this produces two values, make sure to remember that we legalized
3198 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
3199 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
3202 case ISD::BUILD_PAIR: {
3203 MVT::ValueType PairTy = Node->getValueType(0);
3204 // TODO: handle the case where the Lo and Hi operands are not of legal type
3205 Tmp1 = LegalizeOp(Node->getOperand(0)); // Lo
3206 Tmp2 = LegalizeOp(Node->getOperand(1)); // Hi
3207 switch (TLI.getOperationAction(ISD::BUILD_PAIR, PairTy)) {
3208 case TargetLowering::Promote:
3209 case TargetLowering::Custom:
3210 assert(0 && "Cannot promote/custom this yet!");
3211 case TargetLowering::Legal:
3212 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1))
3213 Result = DAG.getNode(ISD::BUILD_PAIR, PairTy, Tmp1, Tmp2);
3215 case TargetLowering::Expand:
3216 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, PairTy, Tmp1);
3217 Tmp2 = DAG.getNode(ISD::ANY_EXTEND, PairTy, Tmp2);
3218 Tmp2 = DAG.getNode(ISD::SHL, PairTy, Tmp2,
3219 DAG.getConstant(MVT::getSizeInBits(PairTy)/2,
3220 TLI.getShiftAmountTy()));
3221 Result = DAG.getNode(ISD::OR, PairTy, Tmp1, Tmp2);
3230 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
3231 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS
3233 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3234 case TargetLowering::Promote: assert(0 && "Cannot promote this yet!");
3235 case TargetLowering::Custom:
3238 case TargetLowering::Legal:
3239 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
3241 Tmp1 = TLI.LowerOperation(Result, DAG);
3242 if (Tmp1.Val) Result = Tmp1;
3245 case TargetLowering::Expand: {
3246 unsigned DivOpc= (Node->getOpcode() == ISD::UREM) ? ISD::UDIV : ISD::SDIV;
3247 bool isSigned = DivOpc == ISD::SDIV;
3248 MVT::ValueType VT = Node->getValueType(0);
3250 // See if remainder can be lowered using two-result operations.
3251 SDVTList VTs = DAG.getVTList(VT, VT);
3252 if (Node->getOpcode() == ISD::SREM &&
3253 TLI.isOperationLegal(ISD::SDIVREM, VT)) {
3254 Result = SDOperand(DAG.getNode(ISD::SDIVREM, VTs, Tmp1, Tmp2).Val, 1);
3257 if (Node->getOpcode() == ISD::UREM &&
3258 TLI.isOperationLegal(ISD::UDIVREM, VT)) {
3259 Result = SDOperand(DAG.getNode(ISD::UDIVREM, VTs, Tmp1, Tmp2).Val, 1);
3263 if (MVT::isInteger(VT)) {
3264 if (TLI.getOperationAction(DivOpc, VT) ==
3265 TargetLowering::Legal) {
3267 Result = DAG.getNode(DivOpc, VT, Tmp1, Tmp2);
3268 Result = DAG.getNode(ISD::MUL, VT, Result, Tmp2);
3269 Result = DAG.getNode(ISD::SUB, VT, Tmp1, Result);
3270 } else if (MVT::isVector(VT)) {
3271 Result = LegalizeOp(UnrollVectorOp(Op));
3273 assert(VT == MVT::i32 &&
3274 "Cannot expand this binary operator!");
3275 RTLIB::Libcall LC = Node->getOpcode() == ISD::UREM
3276 ? RTLIB::UREM_I32 : RTLIB::SREM_I32;
3278 Result = ExpandLibCall(TLI.getLibcallName(LC), Node, isSigned, Dummy);
3281 assert(MVT::isFloatingPoint(VT) &&
3282 "remainder op must have integer or floating-point type");
3283 if (MVT::isVector(VT)) {
3284 Result = LegalizeOp(UnrollVectorOp(Op));
3286 // Floating point mod -> fmod libcall.
3287 RTLIB::Libcall LC = GetFPLibCall(VT, RTLIB::REM_F32, RTLIB::REM_F64,
3288 RTLIB::REM_F80, RTLIB::REM_PPCF128);
3290 Result = ExpandLibCall(TLI.getLibcallName(LC), Node,
3291 false/*sign irrelevant*/, Dummy);
3299 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
3300 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
3302 MVT::ValueType VT = Node->getValueType(0);
3303 switch (TLI.getOperationAction(Node->getOpcode(), MVT::Other)) {
3304 default: assert(0 && "This action is not supported yet!");
3305 case TargetLowering::Custom:
3308 case TargetLowering::Legal:
3309 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
3310 Result = Result.getValue(0);
3311 Tmp1 = Result.getValue(1);
3314 Tmp2 = TLI.LowerOperation(Result, DAG);
3316 Result = LegalizeOp(Tmp2);
3317 Tmp1 = LegalizeOp(Tmp2.getValue(1));
3321 case TargetLowering::Expand: {
3322 const Value *V = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
3323 SDOperand VAList = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp2, V, 0);
3324 // Increment the pointer, VAList, to the next vaarg
3325 Tmp3 = DAG.getNode(ISD::ADD, TLI.getPointerTy(), VAList,
3326 DAG.getConstant(MVT::getSizeInBits(VT)/8,
3327 TLI.getPointerTy()));
3328 // Store the incremented VAList to the legalized pointer
3329 Tmp3 = DAG.getStore(VAList.getValue(1), Tmp3, Tmp2, V, 0);
3330 // Load the actual argument out of the pointer VAList
3331 Result = DAG.getLoad(VT, Tmp3, VAList, NULL, 0);
3332 Tmp1 = LegalizeOp(Result.getValue(1));
3333 Result = LegalizeOp(Result);
3337 // Since VAARG produces two values, make sure to remember that we
3338 // legalized both of them.
3339 AddLegalizedOperand(SDOperand(Node, 0), Result);
3340 AddLegalizedOperand(SDOperand(Node, 1), Tmp1);
3341 return Op.ResNo ? Tmp1 : Result;
3345 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
3346 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the dest pointer.
3347 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the source pointer.
3349 switch (TLI.getOperationAction(ISD::VACOPY, MVT::Other)) {
3350 default: assert(0 && "This action is not supported yet!");
3351 case TargetLowering::Custom:
3354 case TargetLowering::Legal:
3355 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3,
3356 Node->getOperand(3), Node->getOperand(4));
3358 Tmp1 = TLI.LowerOperation(Result, DAG);
3359 if (Tmp1.Val) Result = Tmp1;
3362 case TargetLowering::Expand:
3363 // This defaults to loading a pointer from the input and storing it to the
3364 // output, returning the chain.
3365 const Value *VD = cast<SrcValueSDNode>(Node->getOperand(3))->getValue();
3366 const Value *VS = cast<SrcValueSDNode>(Node->getOperand(4))->getValue();
3367 Tmp4 = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp3, VD, 0);
3368 Result = DAG.getStore(Tmp4.getValue(1), Tmp4, Tmp2, VS, 0);
3374 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
3375 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
3377 switch (TLI.getOperationAction(ISD::VAEND, MVT::Other)) {
3378 default: assert(0 && "This action is not supported yet!");
3379 case TargetLowering::Custom:
3382 case TargetLowering::Legal:
3383 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
3385 Tmp1 = TLI.LowerOperation(Tmp1, DAG);
3386 if (Tmp1.Val) Result = Tmp1;
3389 case TargetLowering::Expand:
3390 Result = Tmp1; // Default to a no-op, return the chain
3396 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
3397 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
3399 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
3401 switch (TLI.getOperationAction(ISD::VASTART, MVT::Other)) {
3402 default: assert(0 && "This action is not supported yet!");
3403 case TargetLowering::Legal: break;
3404 case TargetLowering::Custom:
3405 Tmp1 = TLI.LowerOperation(Result, DAG);
3406 if (Tmp1.Val) Result = Tmp1;
3413 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
3414 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS
3415 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
3416 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3418 assert(0 && "ROTL/ROTR legalize operation not supported");
3420 case TargetLowering::Legal:
3422 case TargetLowering::Custom:
3423 Tmp1 = TLI.LowerOperation(Result, DAG);
3424 if (Tmp1.Val) Result = Tmp1;
3426 case TargetLowering::Promote:
3427 assert(0 && "Do not know how to promote ROTL/ROTR");
3429 case TargetLowering::Expand:
3430 assert(0 && "Do not know how to expand ROTL/ROTR");
3436 Tmp1 = LegalizeOp(Node->getOperand(0)); // Op
3437 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3438 case TargetLowering::Custom:
3439 assert(0 && "Cannot custom legalize this yet!");
3440 case TargetLowering::Legal:
3441 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3443 case TargetLowering::Promote: {
3444 MVT::ValueType OVT = Tmp1.getValueType();
3445 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
3446 unsigned DiffBits = MVT::getSizeInBits(NVT) - MVT::getSizeInBits(OVT);
3448 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1);
3449 Tmp1 = DAG.getNode(ISD::BSWAP, NVT, Tmp1);
3450 Result = DAG.getNode(ISD::SRL, NVT, Tmp1,
3451 DAG.getConstant(DiffBits, TLI.getShiftAmountTy()));
3454 case TargetLowering::Expand:
3455 Result = ExpandBSWAP(Tmp1);
3463 Tmp1 = LegalizeOp(Node->getOperand(0)); // Op
3464 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3465 case TargetLowering::Custom:
3466 case TargetLowering::Legal:
3467 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3468 if (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0)) ==
3469 TargetLowering::Custom) {
3470 Tmp1 = TLI.LowerOperation(Result, DAG);
3476 case TargetLowering::Promote: {
3477 MVT::ValueType OVT = Tmp1.getValueType();
3478 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
3480 // Zero extend the argument.
3481 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1);
3482 // Perform the larger operation, then subtract if needed.
3483 Tmp1 = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1);
3484 switch (Node->getOpcode()) {
3489 //if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT)
3490 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), Tmp1,
3491 DAG.getConstant(MVT::getSizeInBits(NVT), NVT),
3493 Result = DAG.getNode(ISD::SELECT, NVT, Tmp2,
3494 DAG.getConstant(MVT::getSizeInBits(OVT),NVT), Tmp1);
3497 // Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT))
3498 Result = DAG.getNode(ISD::SUB, NVT, Tmp1,
3499 DAG.getConstant(MVT::getSizeInBits(NVT) -
3500 MVT::getSizeInBits(OVT), NVT));
3505 case TargetLowering::Expand:
3506 Result = ExpandBitCount(Node->getOpcode(), Tmp1);
3517 Tmp1 = LegalizeOp(Node->getOperand(0));
3518 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3519 case TargetLowering::Promote:
3520 case TargetLowering::Custom:
3523 case TargetLowering::Legal:
3524 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3526 Tmp1 = TLI.LowerOperation(Result, DAG);
3527 if (Tmp1.Val) Result = Tmp1;
3530 case TargetLowering::Expand:
3531 switch (Node->getOpcode()) {
3532 default: assert(0 && "Unreachable!");
3534 // Expand Y = FNEG(X) -> Y = SUB -0.0, X
3535 Tmp2 = DAG.getConstantFP(-0.0, Node->getValueType(0));
3536 Result = DAG.getNode(ISD::FSUB, Node->getValueType(0), Tmp2, Tmp1);
3539 // Expand Y = FABS(X) -> Y = (X >u 0.0) ? X : fneg(X).
3540 MVT::ValueType VT = Node->getValueType(0);
3541 Tmp2 = DAG.getConstantFP(0.0, VT);
3542 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), Tmp1, Tmp2, ISD::SETUGT);
3543 Tmp3 = DAG.getNode(ISD::FNEG, VT, Tmp1);
3544 Result = DAG.getNode(ISD::SELECT, VT, Tmp2, Tmp1, Tmp3);
3550 MVT::ValueType VT = Node->getValueType(0);
3552 // Expand unsupported unary vector operators by unrolling them.
3553 if (MVT::isVector(VT)) {
3554 Result = LegalizeOp(UnrollVectorOp(Op));
3558 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
3559 switch(Node->getOpcode()) {
3561 LC = GetFPLibCall(VT, RTLIB::SQRT_F32, RTLIB::SQRT_F64,
3562 RTLIB::SQRT_F80, RTLIB::SQRT_PPCF128);
3565 LC = GetFPLibCall(VT, RTLIB::SIN_F32, RTLIB::SIN_F64,
3566 RTLIB::SIN_F80, RTLIB::SIN_PPCF128);
3569 LC = GetFPLibCall(VT, RTLIB::COS_F32, RTLIB::COS_F64,
3570 RTLIB::COS_F80, RTLIB::COS_PPCF128);
3572 default: assert(0 && "Unreachable!");
3575 Result = ExpandLibCall(TLI.getLibcallName(LC), Node,
3576 false/*sign irrelevant*/, Dummy);
3584 MVT::ValueType VT = Node->getValueType(0);
3586 // Expand unsupported unary vector operators by unrolling them.
3587 if (MVT::isVector(VT)) {
3588 Result = LegalizeOp(UnrollVectorOp(Op));
3592 // We always lower FPOWI into a libcall. No target support for it yet.
3593 RTLIB::Libcall LC = GetFPLibCall(VT, RTLIB::POWI_F32, RTLIB::POWI_F64,
3594 RTLIB::POWI_F80, RTLIB::POWI_PPCF128);
3596 Result = ExpandLibCall(TLI.getLibcallName(LC), Node,
3597 false/*sign irrelevant*/, Dummy);
3600 case ISD::BIT_CONVERT:
3601 if (!isTypeLegal(Node->getOperand(0).getValueType())) {
3602 Result = EmitStackConvert(Node->getOperand(0), Node->getValueType(0),
3603 Node->getValueType(0));
3604 } else if (MVT::isVector(Op.getOperand(0).getValueType())) {
3605 // The input has to be a vector type, we have to either scalarize it, pack
3606 // it, or convert it based on whether the input vector type is legal.
3607 SDNode *InVal = Node->getOperand(0).Val;
3608 int InIx = Node->getOperand(0).ResNo;
3609 unsigned NumElems = MVT::getVectorNumElements(InVal->getValueType(InIx));
3610 MVT::ValueType EVT = MVT::getVectorElementType(InVal->getValueType(InIx));
3612 // Figure out if there is a simple type corresponding to this Vector
3613 // type. If so, convert to the vector type.
3614 MVT::ValueType TVT = MVT::getVectorType(EVT, NumElems);
3615 if (TLI.isTypeLegal(TVT)) {
3616 // Turn this into a bit convert of the vector input.
3617 Result = DAG.getNode(ISD::BIT_CONVERT, Node->getValueType(0),
3618 LegalizeOp(Node->getOperand(0)));
3620 } else if (NumElems == 1) {
3621 // Turn this into a bit convert of the scalar input.
3622 Result = DAG.getNode(ISD::BIT_CONVERT, Node->getValueType(0),
3623 ScalarizeVectorOp(Node->getOperand(0)));
3626 // FIXME: UNIMP! Store then reload
3627 assert(0 && "Cast from unsupported vector type not implemented yet!");
3630 switch (TLI.getOperationAction(ISD::BIT_CONVERT,
3631 Node->getOperand(0).getValueType())) {
3632 default: assert(0 && "Unknown operation action!");
3633 case TargetLowering::Expand:
3634 Result = EmitStackConvert(Node->getOperand(0), Node->getValueType(0),
3635 Node->getValueType(0));
3637 case TargetLowering::Legal:
3638 Tmp1 = LegalizeOp(Node->getOperand(0));
3639 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3645 // Conversion operators. The source and destination have different types.
3646 case ISD::SINT_TO_FP:
3647 case ISD::UINT_TO_FP: {
3648 bool isSigned = Node->getOpcode() == ISD::SINT_TO_FP;
3649 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3651 switch (TLI.getOperationAction(Node->getOpcode(),
3652 Node->getOperand(0).getValueType())) {
3653 default: assert(0 && "Unknown operation action!");
3654 case TargetLowering::Custom:
3657 case TargetLowering::Legal:
3658 Tmp1 = LegalizeOp(Node->getOperand(0));
3659 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3661 Tmp1 = TLI.LowerOperation(Result, DAG);
3662 if (Tmp1.Val) Result = Tmp1;
3665 case TargetLowering::Expand:
3666 Result = ExpandLegalINT_TO_FP(isSigned,
3667 LegalizeOp(Node->getOperand(0)),
3668 Node->getValueType(0));
3670 case TargetLowering::Promote:
3671 Result = PromoteLegalINT_TO_FP(LegalizeOp(Node->getOperand(0)),
3672 Node->getValueType(0),
3678 Result = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP,
3679 Node->getValueType(0), Node->getOperand(0));
3682 Tmp1 = PromoteOp(Node->getOperand(0));
3684 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, Tmp1.getValueType(),
3685 Tmp1, DAG.getValueType(Node->getOperand(0).getValueType()));
3687 Tmp1 = DAG.getZeroExtendInReg(Tmp1,
3688 Node->getOperand(0).getValueType());
3690 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3691 Result = LegalizeOp(Result); // The 'op' is not necessarily legal!
3697 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3699 Tmp1 = LegalizeOp(Node->getOperand(0));
3700 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3703 ExpandOp(Node->getOperand(0), Tmp1, Tmp2);
3705 // Since the result is legal, we should just be able to truncate the low
3706 // part of the source.
3707 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), Tmp1);
3710 Result = PromoteOp(Node->getOperand(0));
3711 Result = DAG.getNode(ISD::TRUNCATE, Op.getValueType(), Result);
3716 case ISD::FP_TO_SINT:
3717 case ISD::FP_TO_UINT:
3718 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3720 Tmp1 = LegalizeOp(Node->getOperand(0));
3722 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))){
3723 default: assert(0 && "Unknown operation action!");
3724 case TargetLowering::Custom:
3727 case TargetLowering::Legal:
3728 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3730 Tmp1 = TLI.LowerOperation(Result, DAG);
3731 if (Tmp1.Val) Result = Tmp1;
3734 case TargetLowering::Promote:
3735 Result = PromoteLegalFP_TO_INT(Tmp1, Node->getValueType(0),
3736 Node->getOpcode() == ISD::FP_TO_SINT);
3738 case TargetLowering::Expand:
3739 if (Node->getOpcode() == ISD::FP_TO_UINT) {
3740 SDOperand True, False;
3741 MVT::ValueType VT = Node->getOperand(0).getValueType();
3742 MVT::ValueType NVT = Node->getValueType(0);
3743 unsigned ShiftAmt = MVT::getSizeInBits(NVT)-1;
3744 const uint64_t zero[] = {0, 0};
3745 APFloat apf = APFloat(APInt(MVT::getSizeInBits(VT), 2, zero));
3746 uint64_t x = 1ULL << ShiftAmt;
3747 (void)apf.convertFromZeroExtendedInteger
3748 (&x, MVT::getSizeInBits(NVT), false, APFloat::rmNearestTiesToEven);
3749 Tmp2 = DAG.getConstantFP(apf, VT);
3750 Tmp3 = DAG.getSetCC(TLI.getSetCCResultTy(),
3751 Node->getOperand(0), Tmp2, ISD::SETLT);
3752 True = DAG.getNode(ISD::FP_TO_SINT, NVT, Node->getOperand(0));
3753 False = DAG.getNode(ISD::FP_TO_SINT, NVT,
3754 DAG.getNode(ISD::FSUB, VT, Node->getOperand(0),
3756 False = DAG.getNode(ISD::XOR, NVT, False,
3757 DAG.getConstant(1ULL << ShiftAmt, NVT));
3758 Result = DAG.getNode(ISD::SELECT, NVT, Tmp3, True, False);
3761 assert(0 && "Do not know how to expand FP_TO_SINT yet!");
3767 MVT::ValueType VT = Op.getValueType();
3768 MVT::ValueType OVT = Node->getOperand(0).getValueType();
3769 // Convert ppcf128 to i32
3770 if (OVT == MVT::ppcf128 && VT == MVT::i32) {
3771 if (Node->getOpcode() == ISD::FP_TO_SINT) {
3772 Result = DAG.getNode(ISD::FP_ROUND_INREG, MVT::ppcf128,
3773 Node->getOperand(0), DAG.getValueType(MVT::f64));
3774 Result = DAG.getNode(ISD::FP_ROUND, MVT::f64, Result,
3775 DAG.getIntPtrConstant(1));
3776 Result = DAG.getNode(ISD::FP_TO_SINT, VT, Result);
3778 const uint64_t TwoE31[] = {0x41e0000000000000LL, 0};
3779 APFloat apf = APFloat(APInt(128, 2, TwoE31));
3780 Tmp2 = DAG.getConstantFP(apf, OVT);
3781 // X>=2^31 ? (int)(X-2^31)+0x80000000 : (int)X
3782 // FIXME: generated code sucks.
3783 Result = DAG.getNode(ISD::SELECT_CC, VT, Node->getOperand(0), Tmp2,
3784 DAG.getNode(ISD::ADD, MVT::i32,
3785 DAG.getNode(ISD::FP_TO_SINT, VT,
3786 DAG.getNode(ISD::FSUB, OVT,
3787 Node->getOperand(0), Tmp2)),
3788 DAG.getConstant(0x80000000, MVT::i32)),
3789 DAG.getNode(ISD::FP_TO_SINT, VT,
3790 Node->getOperand(0)),
3791 DAG.getCondCode(ISD::SETGE));
3795 // Convert f32 / f64 to i32 / i64.
3796 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
3797 switch (Node->getOpcode()) {
3798 case ISD::FP_TO_SINT: {
3799 if (OVT == MVT::f32)
3800 LC = (VT == MVT::i32)
3801 ? RTLIB::FPTOSINT_F32_I32 : RTLIB::FPTOSINT_F32_I64;
3802 else if (OVT == MVT::f64)
3803 LC = (VT == MVT::i32)
3804 ? RTLIB::FPTOSINT_F64_I32 : RTLIB::FPTOSINT_F64_I64;
3805 else if (OVT == MVT::f80) {
3806 assert(VT == MVT::i64);
3807 LC = RTLIB::FPTOSINT_F80_I64;
3809 else if (OVT == MVT::ppcf128) {
3810 assert(VT == MVT::i64);
3811 LC = RTLIB::FPTOSINT_PPCF128_I64;
3815 case ISD::FP_TO_UINT: {
3816 if (OVT == MVT::f32)
3817 LC = (VT == MVT::i32)
3818 ? RTLIB::FPTOUINT_F32_I32 : RTLIB::FPTOSINT_F32_I64;
3819 else if (OVT == MVT::f64)
3820 LC = (VT == MVT::i32)
3821 ? RTLIB::FPTOUINT_F64_I32 : RTLIB::FPTOSINT_F64_I64;
3822 else if (OVT == MVT::f80) {
3823 LC = (VT == MVT::i32)
3824 ? RTLIB::FPTOUINT_F80_I32 : RTLIB::FPTOUINT_F80_I64;
3826 else if (OVT == MVT::ppcf128) {
3827 assert(VT == MVT::i64);
3828 LC = RTLIB::FPTOUINT_PPCF128_I64;
3832 default: assert(0 && "Unreachable!");
3835 Result = ExpandLibCall(TLI.getLibcallName(LC), Node,
3836 false/*sign irrelevant*/, Dummy);
3840 Tmp1 = PromoteOp(Node->getOperand(0));
3841 Result = DAG.UpdateNodeOperands(Result, LegalizeOp(Tmp1));
3842 Result = LegalizeOp(Result);
3847 case ISD::FP_EXTEND: {
3848 MVT::ValueType DstVT = Op.getValueType();
3849 MVT::ValueType SrcVT = Op.getOperand(0).getValueType();
3850 if (TLI.getConvertAction(SrcVT, DstVT) == TargetLowering::Expand) {
3851 // The only other way we can lower this is to turn it into a STORE,
3852 // LOAD pair, targetting a temporary location (a stack slot).
3853 Result = EmitStackConvert(Node->getOperand(0), SrcVT, DstVT);
3856 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3857 case Expand: assert(0 && "Shouldn't need to expand other operators here!");
3859 Tmp1 = LegalizeOp(Node->getOperand(0));
3860 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3863 Tmp1 = PromoteOp(Node->getOperand(0));
3864 Result = DAG.getNode(ISD::FP_EXTEND, Op.getValueType(), Tmp1);
3869 case ISD::FP_ROUND: {
3870 MVT::ValueType DstVT = Op.getValueType();
3871 MVT::ValueType SrcVT = Op.getOperand(0).getValueType();
3872 if (TLI.getConvertAction(SrcVT, DstVT) == TargetLowering::Expand) {
3873 if (SrcVT == MVT::ppcf128) {
3875 ExpandOp(Node->getOperand(0), Lo, Result);
3876 // Round it the rest of the way (e.g. to f32) if needed.
3877 if (DstVT!=MVT::f64)
3878 Result = DAG.getNode(ISD::FP_ROUND, DstVT, Result, Op.getOperand(1));
3881 // The only other way we can lower this is to turn it into a STORE,
3882 // LOAD pair, targetting a temporary location (a stack slot).
3883 Result = EmitStackConvert(Node->getOperand(0), DstVT, DstVT);
3886 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3887 case Expand: assert(0 && "Shouldn't need to expand other operators here!");
3889 Tmp1 = LegalizeOp(Node->getOperand(0));
3890 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
3893 Tmp1 = PromoteOp(Node->getOperand(0));
3894 Result = DAG.getNode(ISD::FP_ROUND, Op.getValueType(), Tmp1,
3895 Node->getOperand(1));
3900 case ISD::ANY_EXTEND:
3901 case ISD::ZERO_EXTEND:
3902 case ISD::SIGN_EXTEND:
3903 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3904 case Expand: assert(0 && "Shouldn't need to expand other operators here!");
3906 Tmp1 = LegalizeOp(Node->getOperand(0));
3907 if (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0)) ==
3908 TargetLowering::Custom) {
3909 Tmp2 = TLI.LowerOperation(Result, DAG);
3914 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3917 switch (Node->getOpcode()) {
3918 case ISD::ANY_EXTEND:
3919 Tmp1 = PromoteOp(Node->getOperand(0));
3920 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Tmp1);
3922 case ISD::ZERO_EXTEND:
3923 Result = PromoteOp(Node->getOperand(0));
3924 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Result);
3925 Result = DAG.getZeroExtendInReg(Result,
3926 Node->getOperand(0).getValueType());
3928 case ISD::SIGN_EXTEND:
3929 Result = PromoteOp(Node->getOperand(0));
3930 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Result);
3931 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(),
3933 DAG.getValueType(Node->getOperand(0).getValueType()));
3938 case ISD::FP_ROUND_INREG:
3939 case ISD::SIGN_EXTEND_INREG: {
3940 Tmp1 = LegalizeOp(Node->getOperand(0));
3941 MVT::ValueType ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT();
3943 // If this operation is not supported, convert it to a shl/shr or load/store
3945 switch (TLI.getOperationAction(Node->getOpcode(), ExtraVT)) {
3946 default: assert(0 && "This action not supported for this op yet!");
3947 case TargetLowering::Legal:
3948 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
3950 case TargetLowering::Expand:
3951 // If this is an integer extend and shifts are supported, do that.
3952 if (Node->getOpcode() == ISD::SIGN_EXTEND_INREG) {
3953 // NOTE: we could fall back on load/store here too for targets without
3954 // SAR. However, it is doubtful that any exist.
3955 unsigned BitsDiff = MVT::getSizeInBits(Node->getValueType(0)) -
3956 MVT::getSizeInBits(ExtraVT);
3957 SDOperand ShiftCst = DAG.getConstant(BitsDiff, TLI.getShiftAmountTy());
3958 Result = DAG.getNode(ISD::SHL, Node->getValueType(0),
3959 Node->getOperand(0), ShiftCst);
3960 Result = DAG.getNode(ISD::SRA, Node->getValueType(0),
3962 } else if (Node->getOpcode() == ISD::FP_ROUND_INREG) {
3963 // The only way we can lower this is to turn it into a TRUNCSTORE,
3964 // EXTLOAD pair, targetting a temporary location (a stack slot).
3966 // NOTE: there is a choice here between constantly creating new stack
3967 // slots and always reusing the same one. We currently always create
3968 // new ones, as reuse may inhibit scheduling.
3969 Result = EmitStackConvert(Node->getOperand(0), ExtraVT,
3970 Node->getValueType(0));
3972 assert(0 && "Unknown op");
3978 case ISD::TRAMPOLINE: {
3980 for (unsigned i = 0; i != 6; ++i)
3981 Ops[i] = LegalizeOp(Node->getOperand(i));
3982 Result = DAG.UpdateNodeOperands(Result, Ops, 6);
3983 // The only option for this node is to custom lower it.
3984 Result = TLI.LowerOperation(Result, DAG);
3985 assert(Result.Val && "Should always custom lower!");
3987 // Since trampoline produces two values, make sure to remember that we
3988 // legalized both of them.
3989 Tmp1 = LegalizeOp(Result.getValue(1));
3990 Result = LegalizeOp(Result);
3991 AddLegalizedOperand(SDOperand(Node, 0), Result);
3992 AddLegalizedOperand(SDOperand(Node, 1), Tmp1);
3993 return Op.ResNo ? Tmp1 : Result;
3995 case ISD::FLT_ROUNDS_: {
3996 MVT::ValueType VT = Node->getValueType(0);
3997 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
3998 default: assert(0 && "This action not supported for this op yet!");
3999 case TargetLowering::Custom:
4000 Result = TLI.LowerOperation(Op, DAG);
4001 if (Result.Val) break;
4003 case TargetLowering::Legal:
4004 // If this operation is not supported, lower it to constant 1
4005 Result = DAG.getConstant(1, VT);
4010 MVT::ValueType VT = Node->getValueType(0);
4011 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
4012 default: assert(0 && "This action not supported for this op yet!");
4013 case TargetLowering::Legal:
4014 Tmp1 = LegalizeOp(Node->getOperand(0));
4015 Result = DAG.UpdateNodeOperands(Result, Tmp1);
4017 case TargetLowering::Custom:
4018 Result = TLI.LowerOperation(Op, DAG);
4019 if (Result.Val) break;
4021 case TargetLowering::Expand:
4022 // If this operation is not supported, lower it to 'abort()' call
4023 Tmp1 = LegalizeOp(Node->getOperand(0));
4024 TargetLowering::ArgListTy Args;
4025 std::pair<SDOperand,SDOperand> CallResult =
4026 TLI.LowerCallTo(Tmp1, Type::VoidTy,
4027 false, false, false, CallingConv::C, false,
4028 DAG.getExternalSymbol("abort", TLI.getPointerTy()),
4030 Result = CallResult.second;
4037 assert(Result.getValueType() == Op.getValueType() &&
4038 "Bad legalization!");
4040 // Make sure that the generated code is itself legal.
4042 Result = LegalizeOp(Result);
4044 // Note that LegalizeOp may be reentered even from single-use nodes, which
4045 // means that we always must cache transformed nodes.
4046 AddLegalizedOperand(Op, Result);
4050 /// PromoteOp - Given an operation that produces a value in an invalid type,
4051 /// promote it to compute the value into a larger type. The produced value will
4052 /// have the correct bits for the low portion of the register, but no guarantee
4053 /// is made about the top bits: it may be zero, sign-extended, or garbage.
4054 SDOperand SelectionDAGLegalize::PromoteOp(SDOperand Op) {
4055 MVT::ValueType VT = Op.getValueType();
4056 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT);
4057 assert(getTypeAction(VT) == Promote &&
4058 "Caller should expand or legalize operands that are not promotable!");
4059 assert(NVT > VT && MVT::isInteger(NVT) == MVT::isInteger(VT) &&
4060 "Cannot promote to smaller type!");
4062 SDOperand Tmp1, Tmp2, Tmp3;
4064 SDNode *Node = Op.Val;
4066 DenseMap<SDOperand, SDOperand>::iterator I = PromotedNodes.find(Op);
4067 if (I != PromotedNodes.end()) return I->second;
4069 switch (Node->getOpcode()) {
4070 case ISD::CopyFromReg:
4071 assert(0 && "CopyFromReg must be legal!");
4074 cerr << "NODE: "; Node->dump(&DAG); cerr << "\n";
4076 assert(0 && "Do not know how to promote this operator!");
4079 Result = DAG.getNode(ISD::UNDEF, NVT);
4083 Result = DAG.getNode(ISD::SIGN_EXTEND, NVT, Op);
4085 Result = DAG.getNode(ISD::ZERO_EXTEND, NVT, Op);
4086 assert(isa<ConstantSDNode>(Result) && "Didn't constant fold zext?");
4088 case ISD::ConstantFP:
4089 Result = DAG.getNode(ISD::FP_EXTEND, NVT, Op);
4090 assert(isa<ConstantFPSDNode>(Result) && "Didn't constant fold fp_extend?");
4094 assert(isTypeLegal(TLI.getSetCCResultTy()) && "SetCC type is not legal??");
4095 Result = DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(),Node->getOperand(0),
4096 Node->getOperand(1), Node->getOperand(2));
4100 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4102 Result = LegalizeOp(Node->getOperand(0));
4103 assert(Result.getValueType() >= NVT &&
4104 "This truncation doesn't make sense!");
4105 if (Result.getValueType() > NVT) // Truncate to NVT instead of VT
4106 Result = DAG.getNode(ISD::TRUNCATE, NVT, Result);
4109 // The truncation is not required, because we don't guarantee anything
4110 // about high bits anyway.
4111 Result = PromoteOp(Node->getOperand(0));
4114 ExpandOp(Node->getOperand(0), Tmp1, Tmp2);
4115 // Truncate the low part of the expanded value to the result type
4116 Result = DAG.getNode(ISD::TRUNCATE, NVT, Tmp1);
4119 case ISD::SIGN_EXTEND:
4120 case ISD::ZERO_EXTEND:
4121 case ISD::ANY_EXTEND:
4122 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4123 case Expand: assert(0 && "BUG: Smaller reg should have been promoted!");
4125 // Input is legal? Just do extend all the way to the larger type.
4126 Result = DAG.getNode(Node->getOpcode(), NVT, Node->getOperand(0));
4129 // Promote the reg if it's smaller.
4130 Result = PromoteOp(Node->getOperand(0));
4131 // The high bits are not guaranteed to be anything. Insert an extend.
4132 if (Node->getOpcode() == ISD::SIGN_EXTEND)
4133 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Result,
4134 DAG.getValueType(Node->getOperand(0).getValueType()));
4135 else if (Node->getOpcode() == ISD::ZERO_EXTEND)
4136 Result = DAG.getZeroExtendInReg(Result,
4137 Node->getOperand(0).getValueType());
4141 case ISD::BIT_CONVERT:
4142 Result = EmitStackConvert(Node->getOperand(0), Node->getValueType(0),
4143 Node->getValueType(0));
4144 Result = PromoteOp(Result);
4147 case ISD::FP_EXTEND:
4148 assert(0 && "Case not implemented. Dynamically dead with 2 FP types!");
4150 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4151 case Expand: assert(0 && "BUG: Cannot expand FP regs!");
4152 case Promote: assert(0 && "Unreachable with 2 FP types!");
4154 if (Node->getConstantOperandVal(1) == 0) {
4155 // Input is legal? Do an FP_ROUND_INREG.
4156 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Node->getOperand(0),
4157 DAG.getValueType(VT));
4159 // Just remove the truncate, it isn't affecting the value.
4160 Result = DAG.getNode(ISD::FP_ROUND, NVT, Node->getOperand(0),
4161 Node->getOperand(1));
4166 case ISD::SINT_TO_FP:
4167 case ISD::UINT_TO_FP:
4168 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4170 // No extra round required here.
4171 Result = DAG.getNode(Node->getOpcode(), NVT, Node->getOperand(0));
4175 Result = PromoteOp(Node->getOperand(0));
4176 if (Node->getOpcode() == ISD::SINT_TO_FP)
4177 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(),
4179 DAG.getValueType(Node->getOperand(0).getValueType()));
4181 Result = DAG.getZeroExtendInReg(Result,
4182 Node->getOperand(0).getValueType());
4183 // No extra round required here.
4184 Result = DAG.getNode(Node->getOpcode(), NVT, Result);
4187 Result = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP, NVT,
4188 Node->getOperand(0));
4189 // Round if we cannot tolerate excess precision.
4190 if (NoExcessFPPrecision)
4191 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
4192 DAG.getValueType(VT));
4197 case ISD::SIGN_EXTEND_INREG:
4198 Result = PromoteOp(Node->getOperand(0));
4199 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Result,
4200 Node->getOperand(1));
4202 case ISD::FP_TO_SINT:
4203 case ISD::FP_TO_UINT:
4204 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4207 Tmp1 = Node->getOperand(0);
4210 // The input result is prerounded, so we don't have to do anything
4212 Tmp1 = PromoteOp(Node->getOperand(0));
4215 // If we're promoting a UINT to a larger size, check to see if the new node
4216 // will be legal. If it isn't, check to see if FP_TO_SINT is legal, since
4217 // we can use that instead. This allows us to generate better code for
4218 // FP_TO_UINT for small destination sizes on targets where FP_TO_UINT is not
4219 // legal, such as PowerPC.
4220 if (Node->getOpcode() == ISD::FP_TO_UINT &&
4221 !TLI.isOperationLegal(ISD::FP_TO_UINT, NVT) &&
4222 (TLI.isOperationLegal(ISD::FP_TO_SINT, NVT) ||
4223 TLI.getOperationAction(ISD::FP_TO_SINT, NVT)==TargetLowering::Custom)){
4224 Result = DAG.getNode(ISD::FP_TO_SINT, NVT, Tmp1);
4226 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
4232 Tmp1 = PromoteOp(Node->getOperand(0));
4233 assert(Tmp1.getValueType() == NVT);
4234 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
4235 // NOTE: we do not have to do any extra rounding here for
4236 // NoExcessFPPrecision, because we know the input will have the appropriate
4237 // precision, and these operations don't modify precision at all.
4243 Tmp1 = PromoteOp(Node->getOperand(0));
4244 assert(Tmp1.getValueType() == NVT);
4245 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
4246 if (NoExcessFPPrecision)
4247 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
4248 DAG.getValueType(VT));
4252 // Promote f32 powi to f64 powi. Note that this could insert a libcall
4253 // directly as well, which may be better.
4254 Tmp1 = PromoteOp(Node->getOperand(0));
4255 assert(Tmp1.getValueType() == NVT);
4256 Result = DAG.getNode(ISD::FPOWI, NVT, Tmp1, Node->getOperand(1));
4257 if (NoExcessFPPrecision)
4258 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
4259 DAG.getValueType(VT));
4263 case ISD::ATOMIC_LCS: {
4264 Tmp2 = PromoteOp(Node->getOperand(2));
4265 Tmp3 = PromoteOp(Node->getOperand(3));
4266 Result = DAG.getAtomic(Node->getOpcode(), Node->getOperand(0),
4267 Node->getOperand(1), Tmp2, Tmp3,
4268 cast<AtomicSDNode>(Node)->getVT());
4269 // Remember that we legalized the chain.
4270 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
4273 case ISD::ATOMIC_LAS:
4274 case ISD::ATOMIC_SWAP: {
4275 Tmp2 = PromoteOp(Node->getOperand(2));
4276 Result = DAG.getAtomic(Node->getOpcode(), Node->getOperand(0),
4277 Node->getOperand(1), Tmp2,
4278 cast<AtomicSDNode>(Node)->getVT());
4279 // Remember that we legalized the chain.
4280 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
4290 // The input may have strange things in the top bits of the registers, but
4291 // these operations don't care. They may have weird bits going out, but
4292 // that too is okay if they are integer operations.
4293 Tmp1 = PromoteOp(Node->getOperand(0));
4294 Tmp2 = PromoteOp(Node->getOperand(1));
4295 assert(Tmp1.getValueType() == NVT && Tmp2.getValueType() == NVT);
4296 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
4301 Tmp1 = PromoteOp(Node->getOperand(0));
4302 Tmp2 = PromoteOp(Node->getOperand(1));
4303 assert(Tmp1.getValueType() == NVT && Tmp2.getValueType() == NVT);
4304 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
4306 // Floating point operations will give excess precision that we may not be
4307 // able to tolerate. If we DO allow excess precision, just leave it,
4308 // otherwise excise it.
4309 // FIXME: Why would we need to round FP ops more than integer ones?
4310 // Is Round(Add(Add(A,B),C)) != Round(Add(Round(Add(A,B)), C))
4311 if (NoExcessFPPrecision)
4312 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
4313 DAG.getValueType(VT));
4318 // These operators require that their input be sign extended.
4319 Tmp1 = PromoteOp(Node->getOperand(0));
4320 Tmp2 = PromoteOp(Node->getOperand(1));
4321 if (MVT::isInteger(NVT)) {
4322 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1,
4323 DAG.getValueType(VT));
4324 Tmp2 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp2,
4325 DAG.getValueType(VT));
4327 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
4329 // Perform FP_ROUND: this is probably overly pessimistic.
4330 if (MVT::isFloatingPoint(NVT) && NoExcessFPPrecision)
4331 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
4332 DAG.getValueType(VT));
4336 case ISD::FCOPYSIGN:
4337 // These operators require that their input be fp extended.
4338 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4339 case Expand: assert(0 && "not implemented");
4340 case Legal: Tmp1 = LegalizeOp(Node->getOperand(0)); break;
4341 case Promote: Tmp1 = PromoteOp(Node->getOperand(0)); break;
4343 switch (getTypeAction(Node->getOperand(1).getValueType())) {
4344 case Expand: assert(0 && "not implemented");
4345 case Legal: Tmp2 = LegalizeOp(Node->getOperand(1)); break;
4346 case Promote: Tmp2 = PromoteOp(Node->getOperand(1)); break;
4348 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
4350 // Perform FP_ROUND: this is probably overly pessimistic.
4351 if (NoExcessFPPrecision && Node->getOpcode() != ISD::FCOPYSIGN)
4352 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
4353 DAG.getValueType(VT));
4358 // These operators require that their input be zero extended.
4359 Tmp1 = PromoteOp(Node->getOperand(0));
4360 Tmp2 = PromoteOp(Node->getOperand(1));
4361 assert(MVT::isInteger(NVT) && "Operators don't apply to FP!");
4362 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT);
4363 Tmp2 = DAG.getZeroExtendInReg(Tmp2, VT);
4364 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
4368 Tmp1 = PromoteOp(Node->getOperand(0));
4369 Result = DAG.getNode(ISD::SHL, NVT, Tmp1, Node->getOperand(1));
4372 // The input value must be properly sign extended.
4373 Tmp1 = PromoteOp(Node->getOperand(0));
4374 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1,
4375 DAG.getValueType(VT));
4376 Result = DAG.getNode(ISD::SRA, NVT, Tmp1, Node->getOperand(1));
4379 // The input value must be properly zero extended.
4380 Tmp1 = PromoteOp(Node->getOperand(0));
4381 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT);
4382 Result = DAG.getNode(ISD::SRL, NVT, Tmp1, Node->getOperand(1));
4386 Tmp1 = Node->getOperand(0); // Get the chain.
4387 Tmp2 = Node->getOperand(1); // Get the pointer.
4388 if (TLI.getOperationAction(ISD::VAARG, VT) == TargetLowering::Custom) {
4389 Tmp3 = DAG.getVAArg(VT, Tmp1, Tmp2, Node->getOperand(2));
4390 Result = TLI.CustomPromoteOperation(Tmp3, DAG);
4392 const Value *V = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
4393 SDOperand VAList = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp2, V, 0);
4394 // Increment the pointer, VAList, to the next vaarg
4395 Tmp3 = DAG.getNode(ISD::ADD, TLI.getPointerTy(), VAList,
4396 DAG.getConstant(MVT::getSizeInBits(VT)/8,
4397 TLI.getPointerTy()));
4398 // Store the incremented VAList to the legalized pointer
4399 Tmp3 = DAG.getStore(VAList.getValue(1), Tmp3, Tmp2, V, 0);
4400 // Load the actual argument out of the pointer VAList
4401 Result = DAG.getExtLoad(ISD::EXTLOAD, NVT, Tmp3, VAList, NULL, 0, VT);
4403 // Remember that we legalized the chain.
4404 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
4408 LoadSDNode *LD = cast<LoadSDNode>(Node);
4409 ISD::LoadExtType ExtType = ISD::isNON_EXTLoad(Node)
4410 ? ISD::EXTLOAD : LD->getExtensionType();
4411 Result = DAG.getExtLoad(ExtType, NVT,
4412 LD->getChain(), LD->getBasePtr(),
4413 LD->getSrcValue(), LD->getSrcValueOffset(),
4416 LD->getAlignment());
4417 // Remember that we legalized the chain.
4418 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
4422 Tmp2 = PromoteOp(Node->getOperand(1)); // Legalize the op0
4423 Tmp3 = PromoteOp(Node->getOperand(2)); // Legalize the op1
4424 Result = DAG.getNode(ISD::SELECT, NVT, Node->getOperand(0), Tmp2, Tmp3);
4426 case ISD::SELECT_CC:
4427 Tmp2 = PromoteOp(Node->getOperand(2)); // True
4428 Tmp3 = PromoteOp(Node->getOperand(3)); // False
4429 Result = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0),
4430 Node->getOperand(1), Tmp2, Tmp3, Node->getOperand(4));
4433 Tmp1 = Node->getOperand(0);
4434 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1);
4435 Tmp1 = DAG.getNode(ISD::BSWAP, NVT, Tmp1);
4436 Result = DAG.getNode(ISD::SRL, NVT, Tmp1,
4437 DAG.getConstant(MVT::getSizeInBits(NVT) -
4438 MVT::getSizeInBits(VT),
4439 TLI.getShiftAmountTy()));
4444 // Zero extend the argument
4445 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Node->getOperand(0));
4446 // Perform the larger operation, then subtract if needed.
4447 Tmp1 = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
4448 switch(Node->getOpcode()) {
4453 // if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT)
4454 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), Tmp1,
4455 DAG.getConstant(MVT::getSizeInBits(NVT), NVT),
4457 Result = DAG.getNode(ISD::SELECT, NVT, Tmp2,
4458 DAG.getConstant(MVT::getSizeInBits(VT), NVT), Tmp1);
4461 //Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT))
4462 Result = DAG.getNode(ISD::SUB, NVT, Tmp1,
4463 DAG.getConstant(MVT::getSizeInBits(NVT) -
4464 MVT::getSizeInBits(VT), NVT));
4468 case ISD::EXTRACT_SUBVECTOR:
4469 Result = PromoteOp(ExpandEXTRACT_SUBVECTOR(Op));
4471 case ISD::EXTRACT_VECTOR_ELT:
4472 Result = PromoteOp(ExpandEXTRACT_VECTOR_ELT(Op));
4476 assert(Result.Val && "Didn't set a result!");
4478 // Make sure the result is itself legal.
4479 Result = LegalizeOp(Result);
4481 // Remember that we promoted this!
4482 AddPromotedOperand(Op, Result);
4486 /// ExpandEXTRACT_VECTOR_ELT - Expand an EXTRACT_VECTOR_ELT operation into
4487 /// a legal EXTRACT_VECTOR_ELT operation, scalar code, or memory traffic,
4488 /// based on the vector type. The return type of this matches the element type
4489 /// of the vector, which may not be legal for the target.
4490 SDOperand SelectionDAGLegalize::ExpandEXTRACT_VECTOR_ELT(SDOperand Op) {
4491 // We know that operand #0 is the Vec vector. If the index is a constant
4492 // or if the invec is a supported hardware type, we can use it. Otherwise,
4493 // lower to a store then an indexed load.
4494 SDOperand Vec = Op.getOperand(0);
4495 SDOperand Idx = Op.getOperand(1);
4497 MVT::ValueType TVT = Vec.getValueType();
4498 unsigned NumElems = MVT::getVectorNumElements(TVT);
4500 switch (TLI.getOperationAction(ISD::EXTRACT_VECTOR_ELT, TVT)) {
4501 default: assert(0 && "This action is not supported yet!");
4502 case TargetLowering::Custom: {
4503 Vec = LegalizeOp(Vec);
4504 Op = DAG.UpdateNodeOperands(Op, Vec, Idx);
4505 SDOperand Tmp3 = TLI.LowerOperation(Op, DAG);
4510 case TargetLowering::Legal:
4511 if (isTypeLegal(TVT)) {
4512 Vec = LegalizeOp(Vec);
4513 Op = DAG.UpdateNodeOperands(Op, Vec, Idx);
4517 case TargetLowering::Expand:
4521 if (NumElems == 1) {
4522 // This must be an access of the only element. Return it.
4523 Op = ScalarizeVectorOp(Vec);
4524 } else if (!TLI.isTypeLegal(TVT) && isa<ConstantSDNode>(Idx)) {
4525 unsigned NumLoElts = 1 << Log2_32(NumElems-1);
4526 ConstantSDNode *CIdx = cast<ConstantSDNode>(Idx);
4528 SplitVectorOp(Vec, Lo, Hi);
4529 if (CIdx->getValue() < NumLoElts) {
4533 Idx = DAG.getConstant(CIdx->getValue() - NumLoElts,
4534 Idx.getValueType());
4537 // It's now an extract from the appropriate high or low part. Recurse.
4538 Op = DAG.UpdateNodeOperands(Op, Vec, Idx);
4539 Op = ExpandEXTRACT_VECTOR_ELT(Op);
4541 // Store the value to a temporary stack slot, then LOAD the scalar
4542 // element back out.
4543 SDOperand StackPtr = DAG.CreateStackTemporary(Vec.getValueType());
4544 SDOperand Ch = DAG.getStore(DAG.getEntryNode(), Vec, StackPtr, NULL, 0);
4546 // Add the offset to the index.
4547 unsigned EltSize = MVT::getSizeInBits(Op.getValueType())/8;
4548 Idx = DAG.getNode(ISD::MUL, Idx.getValueType(), Idx,
4549 DAG.getConstant(EltSize, Idx.getValueType()));
4551 if (MVT::getSizeInBits(Idx.getValueType()) >
4552 MVT::getSizeInBits(TLI.getPointerTy()))
4553 Idx = DAG.getNode(ISD::TRUNCATE, TLI.getPointerTy(), Idx);
4555 Idx = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(), Idx);
4557 StackPtr = DAG.getNode(ISD::ADD, Idx.getValueType(), Idx, StackPtr);
4559 Op = DAG.getLoad(Op.getValueType(), Ch, StackPtr, NULL, 0);
4564 /// ExpandEXTRACT_SUBVECTOR - Expand a EXTRACT_SUBVECTOR operation. For now
4565 /// we assume the operation can be split if it is not already legal.
4566 SDOperand SelectionDAGLegalize::ExpandEXTRACT_SUBVECTOR(SDOperand Op) {
4567 // We know that operand #0 is the Vec vector. For now we assume the index
4568 // is a constant and that the extracted result is a supported hardware type.
4569 SDOperand Vec = Op.getOperand(0);
4570 SDOperand Idx = LegalizeOp(Op.getOperand(1));
4572 unsigned NumElems = MVT::getVectorNumElements(Vec.getValueType());
4574 if (NumElems == MVT::getVectorNumElements(Op.getValueType())) {
4575 // This must be an access of the desired vector length. Return it.
4579 ConstantSDNode *CIdx = cast<ConstantSDNode>(Idx);
4581 SplitVectorOp(Vec, Lo, Hi);
4582 if (CIdx->getValue() < NumElems/2) {
4586 Idx = DAG.getConstant(CIdx->getValue() - NumElems/2, Idx.getValueType());
4589 // It's now an extract from the appropriate high or low part. Recurse.
4590 Op = DAG.UpdateNodeOperands(Op, Vec, Idx);
4591 return ExpandEXTRACT_SUBVECTOR(Op);
4594 /// LegalizeSetCCOperands - Attempts to create a legal LHS and RHS for a SETCC
4595 /// with condition CC on the current target. This usually involves legalizing
4596 /// or promoting the arguments. In the case where LHS and RHS must be expanded,
4597 /// there may be no choice but to create a new SetCC node to represent the
4598 /// legalized value of setcc lhs, rhs. In this case, the value is returned in
4599 /// LHS, and the SDOperand returned in RHS has a nil SDNode value.
4600 void SelectionDAGLegalize::LegalizeSetCCOperands(SDOperand &LHS,
4603 SDOperand Tmp1, Tmp2, Tmp3, Result;
4605 switch (getTypeAction(LHS.getValueType())) {
4607 Tmp1 = LegalizeOp(LHS); // LHS
4608 Tmp2 = LegalizeOp(RHS); // RHS
4611 Tmp1 = PromoteOp(LHS); // LHS
4612 Tmp2 = PromoteOp(RHS); // RHS
4614 // If this is an FP compare, the operands have already been extended.
4615 if (MVT::isInteger(LHS.getValueType())) {
4616 MVT::ValueType VT = LHS.getValueType();
4617 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT);
4619 // Otherwise, we have to insert explicit sign or zero extends. Note
4620 // that we could insert sign extends for ALL conditions, but zero extend
4621 // is cheaper on many machines (an AND instead of two shifts), so prefer
4623 switch (cast<CondCodeSDNode>(CC)->get()) {
4624 default: assert(0 && "Unknown integer comparison!");
4631 // ALL of these operations will work if we either sign or zero extend
4632 // the operands (including the unsigned comparisons!). Zero extend is
4633 // usually a simpler/cheaper operation, so prefer it.
4634 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT);
4635 Tmp2 = DAG.getZeroExtendInReg(Tmp2, VT);
4641 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1,
4642 DAG.getValueType(VT));
4643 Tmp2 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp2,
4644 DAG.getValueType(VT));
4650 MVT::ValueType VT = LHS.getValueType();
4651 if (VT == MVT::f32 || VT == MVT::f64) {
4652 // Expand into one or more soft-fp libcall(s).
4653 RTLIB::Libcall LC1, LC2 = RTLIB::UNKNOWN_LIBCALL;
4654 switch (cast<CondCodeSDNode>(CC)->get()) {
4657 LC1 = (VT == MVT::f32) ? RTLIB::OEQ_F32 : RTLIB::OEQ_F64;
4661 LC1 = (VT == MVT::f32) ? RTLIB::UNE_F32 : RTLIB::UNE_F64;
4665 LC1 = (VT == MVT::f32) ? RTLIB::OGE_F32 : RTLIB::OGE_F64;
4669 LC1 = (VT == MVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64;
4673 LC1 = (VT == MVT::f32) ? RTLIB::OLE_F32 : RTLIB::OLE_F64;
4677 LC1 = (VT == MVT::f32) ? RTLIB::OGT_F32 : RTLIB::OGT_F64;
4680 LC1 = (VT == MVT::f32) ? RTLIB::UO_F32 : RTLIB::UO_F64;
4683 LC1 = (VT == MVT::f32) ? RTLIB::O_F32 : RTLIB::O_F64;
4686 LC1 = (VT == MVT::f32) ? RTLIB::UO_F32 : RTLIB::UO_F64;
4687 switch (cast<CondCodeSDNode>(CC)->get()) {
4689 // SETONE = SETOLT | SETOGT
4690 LC1 = (VT == MVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64;
4693 LC2 = (VT == MVT::f32) ? RTLIB::OGT_F32 : RTLIB::OGT_F64;
4696 LC2 = (VT == MVT::f32) ? RTLIB::OGE_F32 : RTLIB::OGE_F64;
4699 LC2 = (VT == MVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64;
4702 LC2 = (VT == MVT::f32) ? RTLIB::OLE_F32 : RTLIB::OLE_F64;
4705 LC2 = (VT == MVT::f32) ? RTLIB::OEQ_F32 : RTLIB::OEQ_F64;
4707 default: assert(0 && "Unsupported FP setcc!");
4712 Tmp1 = ExpandLibCall(TLI.getLibcallName(LC1),
4713 DAG.getNode(ISD::MERGE_VALUES, VT, LHS, RHS).Val,
4714 false /*sign irrelevant*/, Dummy);
4715 Tmp2 = DAG.getConstant(0, MVT::i32);
4716 CC = DAG.getCondCode(TLI.getCmpLibcallCC(LC1));
4717 if (LC2 != RTLIB::UNKNOWN_LIBCALL) {
4718 Tmp1 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(), Tmp1, Tmp2, CC);
4719 LHS = ExpandLibCall(TLI.getLibcallName(LC2),
4720 DAG.getNode(ISD::MERGE_VALUES, VT, LHS, RHS).Val,
4721 false /*sign irrelevant*/, Dummy);
4722 Tmp2 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(), LHS, Tmp2,
4723 DAG.getCondCode(TLI.getCmpLibcallCC(LC2)));
4724 Tmp1 = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp2);
4732 SDOperand LHSLo, LHSHi, RHSLo, RHSHi;
4733 ExpandOp(LHS, LHSLo, LHSHi);
4734 ExpandOp(RHS, RHSLo, RHSHi);
4735 ISD::CondCode CCCode = cast<CondCodeSDNode>(CC)->get();
4737 if (VT==MVT::ppcf128) {
4738 // FIXME: This generated code sucks. We want to generate
4739 // FCMP crN, hi1, hi2
4741 // FCMP crN, lo1, lo2
4742 // The following can be improved, but not that much.
4743 Tmp1 = DAG.getSetCC(TLI.getSetCCResultTy(), LHSHi, RHSHi, ISD::SETEQ);
4744 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), LHSLo, RHSLo, CCCode);
4745 Tmp3 = DAG.getNode(ISD::AND, Tmp1.getValueType(), Tmp1, Tmp2);
4746 Tmp1 = DAG.getSetCC(TLI.getSetCCResultTy(), LHSHi, RHSHi, ISD::SETNE);
4747 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), LHSHi, RHSHi, CCCode);
4748 Tmp1 = DAG.getNode(ISD::AND, Tmp1.getValueType(), Tmp1, Tmp2);
4749 Tmp1 = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp3);
4758 if (ConstantSDNode *RHSCST = dyn_cast<ConstantSDNode>(RHSLo))
4759 if (RHSCST->isAllOnesValue()) {
4760 // Comparison to -1.
4761 Tmp1 = DAG.getNode(ISD::AND, LHSLo.getValueType(), LHSLo, LHSHi);
4766 Tmp1 = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSLo, RHSLo);
4767 Tmp2 = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSHi, RHSHi);
4768 Tmp1 = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp2);
4769 Tmp2 = DAG.getConstant(0, Tmp1.getValueType());
4772 // If this is a comparison of the sign bit, just look at the top part.
4774 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(RHS))
4775 if ((cast<CondCodeSDNode>(CC)->get() == ISD::SETLT &&
4776 CST->getValue() == 0) || // X < 0
4777 (cast<CondCodeSDNode>(CC)->get() == ISD::SETGT &&
4778 CST->isAllOnesValue())) { // X > -1
4784 // FIXME: This generated code sucks.
4785 ISD::CondCode LowCC;
4787 default: assert(0 && "Unknown integer setcc!");
4789 case ISD::SETULT: LowCC = ISD::SETULT; break;
4791 case ISD::SETUGT: LowCC = ISD::SETUGT; break;
4793 case ISD::SETULE: LowCC = ISD::SETULE; break;
4795 case ISD::SETUGE: LowCC = ISD::SETUGE; break;
4798 // Tmp1 = lo(op1) < lo(op2) // Always unsigned comparison
4799 // Tmp2 = hi(op1) < hi(op2) // Signedness depends on operands
4800 // dest = hi(op1) == hi(op2) ? Tmp1 : Tmp2;
4802 // NOTE: on targets without efficient SELECT of bools, we can always use
4803 // this identity: (B1 ? B2 : B3) --> (B1 & B2)|(!B1&B3)
4804 TargetLowering::DAGCombinerInfo DagCombineInfo(DAG, false, true, NULL);
4805 Tmp1 = TLI.SimplifySetCC(TLI.getSetCCResultTy(), LHSLo, RHSLo, LowCC,
4806 false, DagCombineInfo);
4808 Tmp1 = DAG.getSetCC(TLI.getSetCCResultTy(), LHSLo, RHSLo, LowCC);
4809 Tmp2 = TLI.SimplifySetCC(TLI.getSetCCResultTy(), LHSHi, RHSHi,
4810 CCCode, false, DagCombineInfo);
4812 Tmp2 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(), LHSHi, RHSHi,CC);
4814 ConstantSDNode *Tmp1C = dyn_cast<ConstantSDNode>(Tmp1.Val);
4815 ConstantSDNode *Tmp2C = dyn_cast<ConstantSDNode>(Tmp2.Val);
4816 if ((Tmp1C && Tmp1C->getValue() == 0) ||
4817 (Tmp2C && Tmp2C->getValue() == 0 &&
4818 (CCCode == ISD::SETLE || CCCode == ISD::SETGE ||
4819 CCCode == ISD::SETUGE || CCCode == ISD::SETULE)) ||
4820 (Tmp2C && Tmp2C->getValue() == 1 &&
4821 (CCCode == ISD::SETLT || CCCode == ISD::SETGT ||
4822 CCCode == ISD::SETUGT || CCCode == ISD::SETULT))) {
4823 // low part is known false, returns high part.
4824 // For LE / GE, if high part is known false, ignore the low part.
4825 // For LT / GT, if high part is known true, ignore the low part.
4829 Result = TLI.SimplifySetCC(TLI.getSetCCResultTy(), LHSHi, RHSHi,
4830 ISD::SETEQ, false, DagCombineInfo);
4832 Result=DAG.getSetCC(TLI.getSetCCResultTy(), LHSHi, RHSHi, ISD::SETEQ);
4833 Result = LegalizeOp(DAG.getNode(ISD::SELECT, Tmp1.getValueType(),
4834 Result, Tmp1, Tmp2));
4845 /// EmitStackConvert - Emit a store/load combination to the stack. This stores
4846 /// SrcOp to a stack slot of type SlotVT, truncating it if needed. It then does
4847 /// a load from the stack slot to DestVT, extending it if needed.
4848 /// The resultant code need not be legal.
4849 SDOperand SelectionDAGLegalize::EmitStackConvert(SDOperand SrcOp,
4850 MVT::ValueType SlotVT,
4851 MVT::ValueType DestVT) {
4852 // Create the stack frame object.
4853 SDOperand FIPtr = DAG.CreateStackTemporary(SlotVT);
4855 FrameIndexSDNode *StackPtrFI = cast<FrameIndexSDNode>(FIPtr);
4856 int SPFI = StackPtrFI->getIndex();
4858 unsigned SrcSize = MVT::getSizeInBits(SrcOp.getValueType());
4859 unsigned SlotSize = MVT::getSizeInBits(SlotVT);
4860 unsigned DestSize = MVT::getSizeInBits(DestVT);
4862 // Emit a store to the stack slot. Use a truncstore if the input value is
4863 // later than DestVT.
4865 if (SrcSize > SlotSize)
4866 Store = DAG.getTruncStore(DAG.getEntryNode(), SrcOp, FIPtr,
4867 PseudoSourceValue::getFixedStack(),
4870 assert(SrcSize == SlotSize && "Invalid store");
4871 Store = DAG.getStore(DAG.getEntryNode(), SrcOp, FIPtr,
4872 PseudoSourceValue::getFixedStack(),
4876 // Result is a load from the stack slot.
4877 if (SlotSize == DestSize)
4878 return DAG.getLoad(DestVT, Store, FIPtr, NULL, 0);
4880 assert(SlotSize < DestSize && "Unknown extension!");
4881 return DAG.getExtLoad(ISD::EXTLOAD, DestVT, Store, FIPtr, NULL, 0, SlotVT);
4884 SDOperand SelectionDAGLegalize::ExpandSCALAR_TO_VECTOR(SDNode *Node) {
4885 // Create a vector sized/aligned stack slot, store the value to element #0,
4886 // then load the whole vector back out.
4887 SDOperand StackPtr = DAG.CreateStackTemporary(Node->getValueType(0));
4889 FrameIndexSDNode *StackPtrFI = cast<FrameIndexSDNode>(StackPtr);
4890 int SPFI = StackPtrFI->getIndex();
4892 SDOperand Ch = DAG.getStore(DAG.getEntryNode(), Node->getOperand(0), StackPtr,
4893 PseudoSourceValue::getFixedStack(), SPFI);
4894 return DAG.getLoad(Node->getValueType(0), Ch, StackPtr,
4895 PseudoSourceValue::getFixedStack(), SPFI);
4899 /// ExpandBUILD_VECTOR - Expand a BUILD_VECTOR node on targets that don't
4900 /// support the operation, but do support the resultant vector type.
4901 SDOperand SelectionDAGLegalize::ExpandBUILD_VECTOR(SDNode *Node) {
4903 // If the only non-undef value is the low element, turn this into a
4904 // SCALAR_TO_VECTOR node. If this is { X, X, X, X }, determine X.
4905 unsigned NumElems = Node->getNumOperands();
4906 bool isOnlyLowElement = true;
4907 SDOperand SplatValue = Node->getOperand(0);
4908 std::map<SDOperand, std::vector<unsigned> > Values;
4909 Values[SplatValue].push_back(0);
4910 bool isConstant = true;
4911 if (!isa<ConstantFPSDNode>(SplatValue) && !isa<ConstantSDNode>(SplatValue) &&
4912 SplatValue.getOpcode() != ISD::UNDEF)
4915 for (unsigned i = 1; i < NumElems; ++i) {
4916 SDOperand V = Node->getOperand(i);
4917 Values[V].push_back(i);
4918 if (V.getOpcode() != ISD::UNDEF)
4919 isOnlyLowElement = false;
4920 if (SplatValue != V)
4921 SplatValue = SDOperand(0,0);
4923 // If this isn't a constant element or an undef, we can't use a constant
4925 if (!isa<ConstantFPSDNode>(V) && !isa<ConstantSDNode>(V) &&
4926 V.getOpcode() != ISD::UNDEF)
4930 if (isOnlyLowElement) {
4931 // If the low element is an undef too, then this whole things is an undef.
4932 if (Node->getOperand(0).getOpcode() == ISD::UNDEF)
4933 return DAG.getNode(ISD::UNDEF, Node->getValueType(0));
4934 // Otherwise, turn this into a scalar_to_vector node.
4935 return DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0),
4936 Node->getOperand(0));
4939 // If all elements are constants, create a load from the constant pool.
4941 MVT::ValueType VT = Node->getValueType(0);
4943 MVT::getTypeForValueType(Node->getOperand(0).getValueType());
4944 std::vector<Constant*> CV;
4945 for (unsigned i = 0, e = NumElems; i != e; ++i) {
4946 if (ConstantFPSDNode *V =
4947 dyn_cast<ConstantFPSDNode>(Node->getOperand(i))) {
4948 CV.push_back(ConstantFP::get(OpNTy, V->getValueAPF()));
4949 } else if (ConstantSDNode *V =
4950 dyn_cast<ConstantSDNode>(Node->getOperand(i))) {
4951 CV.push_back(ConstantInt::get(OpNTy, V->getValue()));
4953 assert(Node->getOperand(i).getOpcode() == ISD::UNDEF);
4954 CV.push_back(UndefValue::get(OpNTy));
4957 Constant *CP = ConstantVector::get(CV);
4958 SDOperand CPIdx = DAG.getConstantPool(CP, TLI.getPointerTy());
4959 return DAG.getLoad(VT, DAG.getEntryNode(), CPIdx,
4960 PseudoSourceValue::getConstantPool(), 0);
4963 if (SplatValue.Val) { // Splat of one value?
4964 // Build the shuffle constant vector: <0, 0, 0, 0>
4965 MVT::ValueType MaskVT =
4966 MVT::getIntVectorWithNumElements(NumElems);
4967 SDOperand Zero = DAG.getConstant(0, MVT::getVectorElementType(MaskVT));
4968 std::vector<SDOperand> ZeroVec(NumElems, Zero);
4969 SDOperand SplatMask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
4970 &ZeroVec[0], ZeroVec.size());
4972 // If the target supports VECTOR_SHUFFLE and this shuffle mask, use it.
4973 if (isShuffleLegal(Node->getValueType(0), SplatMask)) {
4974 // Get the splatted value into the low element of a vector register.
4975 SDOperand LowValVec =
4976 DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0), SplatValue);
4978 // Return shuffle(LowValVec, undef, <0,0,0,0>)
4979 return DAG.getNode(ISD::VECTOR_SHUFFLE, Node->getValueType(0), LowValVec,
4980 DAG.getNode(ISD::UNDEF, Node->getValueType(0)),
4985 // If there are only two unique elements, we may be able to turn this into a
4987 if (Values.size() == 2) {
4988 // Build the shuffle constant vector: e.g. <0, 4, 0, 4>
4989 MVT::ValueType MaskVT =
4990 MVT::getIntVectorWithNumElements(NumElems);
4991 std::vector<SDOperand> MaskVec(NumElems);
4993 for (std::map<SDOperand,std::vector<unsigned> >::iterator I=Values.begin(),
4994 E = Values.end(); I != E; ++I) {
4995 for (std::vector<unsigned>::iterator II = I->second.begin(),
4996 EE = I->second.end(); II != EE; ++II)
4997 MaskVec[*II] = DAG.getConstant(i, MVT::getVectorElementType(MaskVT));
5000 SDOperand ShuffleMask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
5001 &MaskVec[0], MaskVec.size());
5003 // If the target supports VECTOR_SHUFFLE and this shuffle mask, use it.
5004 if (TLI.isOperationLegal(ISD::SCALAR_TO_VECTOR, Node->getValueType(0)) &&
5005 isShuffleLegal(Node->getValueType(0), ShuffleMask)) {
5006 SmallVector<SDOperand, 8> Ops;
5007 for(std::map<SDOperand,std::vector<unsigned> >::iterator I=Values.begin(),
5008 E = Values.end(); I != E; ++I) {
5009 SDOperand Op = DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0),
5013 Ops.push_back(ShuffleMask);
5015 // Return shuffle(LoValVec, HiValVec, <0,1,0,1>)
5016 return DAG.getNode(ISD::VECTOR_SHUFFLE, Node->getValueType(0),
5017 &Ops[0], Ops.size());
5021 // Otherwise, we can't handle this case efficiently. Allocate a sufficiently
5022 // aligned object on the stack, store each element into it, then load
5023 // the result as a vector.
5024 MVT::ValueType VT = Node->getValueType(0);
5025 // Create the stack frame object.
5026 SDOperand FIPtr = DAG.CreateStackTemporary(VT);
5028 // Emit a store of each element to the stack slot.
5029 SmallVector<SDOperand, 8> Stores;
5030 unsigned TypeByteSize =
5031 MVT::getSizeInBits(Node->getOperand(0).getValueType())/8;
5032 // Store (in the right endianness) the elements to memory.
5033 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
5034 // Ignore undef elements.
5035 if (Node->getOperand(i).getOpcode() == ISD::UNDEF) continue;
5037 unsigned Offset = TypeByteSize*i;
5039 SDOperand Idx = DAG.getConstant(Offset, FIPtr.getValueType());
5040 Idx = DAG.getNode(ISD::ADD, FIPtr.getValueType(), FIPtr, Idx);
5042 Stores.push_back(DAG.getStore(DAG.getEntryNode(), Node->getOperand(i), Idx,
5046 SDOperand StoreChain;
5047 if (!Stores.empty()) // Not all undef elements?
5048 StoreChain = DAG.getNode(ISD::TokenFactor, MVT::Other,
5049 &Stores[0], Stores.size());
5051 StoreChain = DAG.getEntryNode();
5053 // Result is a load from the stack slot.
5054 return DAG.getLoad(VT, StoreChain, FIPtr, NULL, 0);
5057 void SelectionDAGLegalize::ExpandShiftParts(unsigned NodeOp,
5058 SDOperand Op, SDOperand Amt,
5059 SDOperand &Lo, SDOperand &Hi) {
5060 // Expand the subcomponents.
5061 SDOperand LHSL, LHSH;
5062 ExpandOp(Op, LHSL, LHSH);
5064 SDOperand Ops[] = { LHSL, LHSH, Amt };
5065 MVT::ValueType VT = LHSL.getValueType();
5066 Lo = DAG.getNode(NodeOp, DAG.getNodeValueTypes(VT, VT), 2, Ops, 3);
5067 Hi = Lo.getValue(1);
5071 /// ExpandShift - Try to find a clever way to expand this shift operation out to
5072 /// smaller elements. If we can't find a way that is more efficient than a
5073 /// libcall on this target, return false. Otherwise, return true with the
5074 /// low-parts expanded into Lo and Hi.
5075 bool SelectionDAGLegalize::ExpandShift(unsigned Opc, SDOperand Op,SDOperand Amt,
5076 SDOperand &Lo, SDOperand &Hi) {
5077 assert((Opc == ISD::SHL || Opc == ISD::SRA || Opc == ISD::SRL) &&
5078 "This is not a shift!");
5080 MVT::ValueType NVT = TLI.getTypeToTransformTo(Op.getValueType());
5081 SDOperand ShAmt = LegalizeOp(Amt);
5082 MVT::ValueType ShTy = ShAmt.getValueType();
5083 unsigned ShBits = MVT::getSizeInBits(ShTy);
5084 unsigned VTBits = MVT::getSizeInBits(Op.getValueType());
5085 unsigned NVTBits = MVT::getSizeInBits(NVT);
5087 // Handle the case when Amt is an immediate.
5088 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Amt.Val)) {
5089 unsigned Cst = CN->getValue();
5090 // Expand the incoming operand to be shifted, so that we have its parts
5092 ExpandOp(Op, InL, InH);
5096 Lo = DAG.getConstant(0, NVT);
5097 Hi = DAG.getConstant(0, NVT);
5098 } else if (Cst > NVTBits) {
5099 Lo = DAG.getConstant(0, NVT);
5100 Hi = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Cst-NVTBits,ShTy));
5101 } else if (Cst == NVTBits) {
5102 Lo = DAG.getConstant(0, NVT);
5105 Lo = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Cst, ShTy));
5106 Hi = DAG.getNode(ISD::OR, NVT,
5107 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(Cst, ShTy)),
5108 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(NVTBits-Cst, ShTy)));
5113 Lo = DAG.getConstant(0, NVT);
5114 Hi = DAG.getConstant(0, NVT);
5115 } else if (Cst > NVTBits) {
5116 Lo = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Cst-NVTBits,ShTy));
5117 Hi = DAG.getConstant(0, NVT);
5118 } else if (Cst == NVTBits) {
5120 Hi = DAG.getConstant(0, NVT);
5122 Lo = DAG.getNode(ISD::OR, NVT,
5123 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(Cst, ShTy)),
5124 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(NVTBits-Cst, ShTy)));
5125 Hi = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Cst, ShTy));
5130 Hi = Lo = DAG.getNode(ISD::SRA, NVT, InH,
5131 DAG.getConstant(NVTBits-1, ShTy));
5132 } else if (Cst > NVTBits) {
5133 Lo = DAG.getNode(ISD::SRA, NVT, InH,
5134 DAG.getConstant(Cst-NVTBits, ShTy));
5135 Hi = DAG.getNode(ISD::SRA, NVT, InH,
5136 DAG.getConstant(NVTBits-1, ShTy));
5137 } else if (Cst == NVTBits) {
5139 Hi = DAG.getNode(ISD::SRA, NVT, InH,
5140 DAG.getConstant(NVTBits-1, ShTy));
5142 Lo = DAG.getNode(ISD::OR, NVT,
5143 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(Cst, ShTy)),
5144 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(NVTBits-Cst, ShTy)));
5145 Hi = DAG.getNode(ISD::SRA, NVT, InH, DAG.getConstant(Cst, ShTy));
5151 // Okay, the shift amount isn't constant. However, if we can tell that it is
5152 // >= 32 or < 32, we can still simplify it, without knowing the actual value.
5153 APInt Mask = APInt::getHighBitsSet(ShBits, ShBits - Log2_32(NVTBits));
5154 APInt KnownZero, KnownOne;
5155 DAG.ComputeMaskedBits(Amt, Mask, KnownZero, KnownOne);
5157 // If we know that if any of the high bits of the shift amount are one, then
5158 // we can do this as a couple of simple shifts.
5159 if (KnownOne.intersects(Mask)) {
5160 // Mask out the high bit, which we know is set.
5161 Amt = DAG.getNode(ISD::AND, Amt.getValueType(), Amt,
5162 DAG.getConstant(~Mask, Amt.getValueType()));
5164 // Expand the incoming operand to be shifted, so that we have its parts
5166 ExpandOp(Op, InL, InH);
5169 Lo = DAG.getConstant(0, NVT); // Low part is zero.
5170 Hi = DAG.getNode(ISD::SHL, NVT, InL, Amt); // High part from Lo part.
5173 Hi = DAG.getConstant(0, NVT); // Hi part is zero.
5174 Lo = DAG.getNode(ISD::SRL, NVT, InH, Amt); // Lo part from Hi part.
5177 Hi = DAG.getNode(ISD::SRA, NVT, InH, // Sign extend high part.
5178 DAG.getConstant(NVTBits-1, Amt.getValueType()));
5179 Lo = DAG.getNode(ISD::SRA, NVT, InH, Amt); // Lo part from Hi part.
5184 // If we know that the high bits of the shift amount are all zero, then we can
5185 // do this as a couple of simple shifts.
5186 if ((KnownZero & Mask) == Mask) {
5188 SDOperand Amt2 = DAG.getNode(ISD::SUB, Amt.getValueType(),
5189 DAG.getConstant(NVTBits, Amt.getValueType()),
5192 // Expand the incoming operand to be shifted, so that we have its parts
5194 ExpandOp(Op, InL, InH);
5197 Lo = DAG.getNode(ISD::SHL, NVT, InL, Amt);
5198 Hi = DAG.getNode(ISD::OR, NVT,
5199 DAG.getNode(ISD::SHL, NVT, InH, Amt),
5200 DAG.getNode(ISD::SRL, NVT, InL, Amt2));
5203 Hi = DAG.getNode(ISD::SRL, NVT, InH, Amt);
5204 Lo = DAG.getNode(ISD::OR, NVT,
5205 DAG.getNode(ISD::SRL, NVT, InL, Amt),
5206 DAG.getNode(ISD::SHL, NVT, InH, Amt2));
5209 Hi = DAG.getNode(ISD::SRA, NVT, InH, Amt);
5210 Lo = DAG.getNode(ISD::OR, NVT,
5211 DAG.getNode(ISD::SRL, NVT, InL, Amt),
5212 DAG.getNode(ISD::SHL, NVT, InH, Amt2));
5221 // ExpandLibCall - Expand a node into a call to a libcall. If the result value
5222 // does not fit into a register, return the lo part and set the hi part to the
5223 // by-reg argument. If it does fit into a single register, return the result
5224 // and leave the Hi part unset.
5225 SDOperand SelectionDAGLegalize::ExpandLibCall(const char *Name, SDNode *Node,
5226 bool isSigned, SDOperand &Hi) {
5227 assert(!IsLegalizingCall && "Cannot overlap legalization of calls!");
5228 // The input chain to this libcall is the entry node of the function.
5229 // Legalizing the call will automatically add the previous call to the
5231 SDOperand InChain = DAG.getEntryNode();
5233 TargetLowering::ArgListTy Args;
5234 TargetLowering::ArgListEntry Entry;
5235 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
5236 MVT::ValueType ArgVT = Node->getOperand(i).getValueType();
5237 const Type *ArgTy = MVT::getTypeForValueType(ArgVT);
5238 Entry.Node = Node->getOperand(i); Entry.Ty = ArgTy;
5239 Entry.isSExt = isSigned;
5240 Entry.isZExt = !isSigned;
5241 Args.push_back(Entry);
5243 SDOperand Callee = DAG.getExternalSymbol(Name, TLI.getPointerTy());
5245 // Splice the libcall in wherever FindInputOutputChains tells us to.
5246 const Type *RetTy = MVT::getTypeForValueType(Node->getValueType(0));
5247 std::pair<SDOperand,SDOperand> CallInfo =
5248 TLI.LowerCallTo(InChain, RetTy, isSigned, !isSigned, false, CallingConv::C,
5249 false, Callee, Args, DAG);
5251 // Legalize the call sequence, starting with the chain. This will advance
5252 // the LastCALLSEQ_END to the legalized version of the CALLSEQ_END node that
5253 // was added by LowerCallTo (guaranteeing proper serialization of calls).
5254 LegalizeOp(CallInfo.second);
5256 switch (getTypeAction(CallInfo.first.getValueType())) {
5257 default: assert(0 && "Unknown thing");
5259 Result = CallInfo.first;
5262 ExpandOp(CallInfo.first, Result, Hi);
5269 /// ExpandIntToFP - Expand a [US]INT_TO_FP operation.
5271 SDOperand SelectionDAGLegalize::
5272 ExpandIntToFP(bool isSigned, MVT::ValueType DestTy, SDOperand Source) {
5273 assert(getTypeAction(Source.getValueType()) == Expand &&
5274 "This is not an expansion!");
5275 assert(Source.getValueType() == MVT::i64 && "Only handle expand from i64!");
5278 assert(Source.getValueType() == MVT::i64 &&
5279 "This only works for 64-bit -> FP");
5280 // The 64-bit value loaded will be incorrectly if the 'sign bit' of the
5281 // incoming integer is set. To handle this, we dynamically test to see if
5282 // it is set, and, if so, add a fudge factor.
5284 ExpandOp(Source, Lo, Hi);
5286 // If this is unsigned, and not supported, first perform the conversion to
5287 // signed, then adjust the result if the sign bit is set.
5288 SDOperand SignedConv = ExpandIntToFP(true, DestTy,
5289 DAG.getNode(ISD::BUILD_PAIR, Source.getValueType(), Lo, Hi));
5291 SDOperand SignSet = DAG.getSetCC(TLI.getSetCCResultTy(), Hi,
5292 DAG.getConstant(0, Hi.getValueType()),
5294 SDOperand Zero = DAG.getIntPtrConstant(0), Four = DAG.getIntPtrConstant(4);
5295 SDOperand CstOffset = DAG.getNode(ISD::SELECT, Zero.getValueType(),
5296 SignSet, Four, Zero);
5297 uint64_t FF = 0x5f800000ULL;
5298 if (TLI.isLittleEndian()) FF <<= 32;
5299 static Constant *FudgeFactor = ConstantInt::get(Type::Int64Ty, FF);
5301 SDOperand CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy());
5302 CPIdx = DAG.getNode(ISD::ADD, TLI.getPointerTy(), CPIdx, CstOffset);
5303 SDOperand FudgeInReg;
5304 if (DestTy == MVT::f32)
5305 FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx,
5306 PseudoSourceValue::getConstantPool(), 0);
5307 else if (MVT::getSizeInBits(DestTy) > MVT::getSizeInBits(MVT::f32))
5308 // FIXME: Avoid the extend by construction the right constantpool?
5309 FudgeInReg = DAG.getExtLoad(ISD::EXTLOAD, DestTy, DAG.getEntryNode(),
5311 PseudoSourceValue::getConstantPool(), 0,
5314 assert(0 && "Unexpected conversion");
5316 MVT::ValueType SCVT = SignedConv.getValueType();
5317 if (SCVT != DestTy) {
5318 // Destination type needs to be expanded as well. The FADD now we are
5319 // constructing will be expanded into a libcall.
5320 if (MVT::getSizeInBits(SCVT) != MVT::getSizeInBits(DestTy)) {
5321 assert(SCVT == MVT::i32 && DestTy == MVT::f64);
5322 SignedConv = DAG.getNode(ISD::BUILD_PAIR, MVT::i64,
5323 SignedConv, SignedConv.getValue(1));
5325 SignedConv = DAG.getNode(ISD::BIT_CONVERT, DestTy, SignedConv);
5327 return DAG.getNode(ISD::FADD, DestTy, SignedConv, FudgeInReg);
5330 // Check to see if the target has a custom way to lower this. If so, use it.
5331 switch (TLI.getOperationAction(ISD::SINT_TO_FP, Source.getValueType())) {
5332 default: assert(0 && "This action not implemented for this operation!");
5333 case TargetLowering::Legal:
5334 case TargetLowering::Expand:
5335 break; // This case is handled below.
5336 case TargetLowering::Custom: {
5337 SDOperand NV = TLI.LowerOperation(DAG.getNode(ISD::SINT_TO_FP, DestTy,
5340 return LegalizeOp(NV);
5341 break; // The target decided this was legal after all
5345 // Expand the source, then glue it back together for the call. We must expand
5346 // the source in case it is shared (this pass of legalize must traverse it).
5347 SDOperand SrcLo, SrcHi;
5348 ExpandOp(Source, SrcLo, SrcHi);
5349 Source = DAG.getNode(ISD::BUILD_PAIR, Source.getValueType(), SrcLo, SrcHi);
5352 if (DestTy == MVT::f32)
5353 LC = RTLIB::SINTTOFP_I64_F32;
5355 assert(DestTy == MVT::f64 && "Unknown fp value type!");
5356 LC = RTLIB::SINTTOFP_I64_F64;
5359 assert(TLI.getLibcallName(LC) && "Don't know how to expand this SINT_TO_FP!");
5360 Source = DAG.getNode(ISD::SINT_TO_FP, DestTy, Source);
5361 SDOperand UnusedHiPart;
5362 return ExpandLibCall(TLI.getLibcallName(LC), Source.Val, isSigned,
5366 /// ExpandLegalINT_TO_FP - This function is responsible for legalizing a
5367 /// INT_TO_FP operation of the specified operand when the target requests that
5368 /// we expand it. At this point, we know that the result and operand types are
5369 /// legal for the target.
5370 SDOperand SelectionDAGLegalize::ExpandLegalINT_TO_FP(bool isSigned,
5372 MVT::ValueType DestVT) {
5373 if (Op0.getValueType() == MVT::i32) {
5374 // simple 32-bit [signed|unsigned] integer to float/double expansion
5376 // Get the stack frame index of a 8 byte buffer.
5377 SDOperand StackSlot = DAG.CreateStackTemporary(MVT::f64);
5379 // word offset constant for Hi/Lo address computation
5380 SDOperand WordOff = DAG.getConstant(sizeof(int), TLI.getPointerTy());
5381 // set up Hi and Lo (into buffer) address based on endian
5382 SDOperand Hi = StackSlot;
5383 SDOperand Lo = DAG.getNode(ISD::ADD, TLI.getPointerTy(), StackSlot,WordOff);
5384 if (TLI.isLittleEndian())
5387 // if signed map to unsigned space
5388 SDOperand Op0Mapped;
5390 // constant used to invert sign bit (signed to unsigned mapping)
5391 SDOperand SignBit = DAG.getConstant(0x80000000u, MVT::i32);
5392 Op0Mapped = DAG.getNode(ISD::XOR, MVT::i32, Op0, SignBit);
5396 // store the lo of the constructed double - based on integer input
5397 SDOperand Store1 = DAG.getStore(DAG.getEntryNode(),
5398 Op0Mapped, Lo, NULL, 0);
5399 // initial hi portion of constructed double
5400 SDOperand InitialHi = DAG.getConstant(0x43300000u, MVT::i32);
5401 // store the hi of the constructed double - biased exponent
5402 SDOperand Store2=DAG.getStore(Store1, InitialHi, Hi, NULL, 0);
5403 // load the constructed double
5404 SDOperand Load = DAG.getLoad(MVT::f64, Store2, StackSlot, NULL, 0);
5405 // FP constant to bias correct the final result
5406 SDOperand Bias = DAG.getConstantFP(isSigned ?
5407 BitsToDouble(0x4330000080000000ULL)
5408 : BitsToDouble(0x4330000000000000ULL),
5410 // subtract the bias
5411 SDOperand Sub = DAG.getNode(ISD::FSUB, MVT::f64, Load, Bias);
5414 // handle final rounding
5415 if (DestVT == MVT::f64) {
5418 } else if (MVT::getSizeInBits(DestVT) < MVT::getSizeInBits(MVT::f64)) {
5419 Result = DAG.getNode(ISD::FP_ROUND, DestVT, Sub,
5420 DAG.getIntPtrConstant(0));
5421 } else if (MVT::getSizeInBits(DestVT) > MVT::getSizeInBits(MVT::f64)) {
5422 Result = DAG.getNode(ISD::FP_EXTEND, DestVT, Sub);
5426 assert(!isSigned && "Legalize cannot Expand SINT_TO_FP for i64 yet");
5427 SDOperand Tmp1 = DAG.getNode(ISD::SINT_TO_FP, DestVT, Op0);
5429 SDOperand SignSet = DAG.getSetCC(TLI.getSetCCResultTy(), Op0,
5430 DAG.getConstant(0, Op0.getValueType()),
5432 SDOperand Zero = DAG.getIntPtrConstant(0), Four = DAG.getIntPtrConstant(4);
5433 SDOperand CstOffset = DAG.getNode(ISD::SELECT, Zero.getValueType(),
5434 SignSet, Four, Zero);
5436 // If the sign bit of the integer is set, the large number will be treated
5437 // as a negative number. To counteract this, the dynamic code adds an
5438 // offset depending on the data type.
5440 switch (Op0.getValueType()) {
5441 default: assert(0 && "Unsupported integer type!");
5442 case MVT::i8 : FF = 0x43800000ULL; break; // 2^8 (as a float)
5443 case MVT::i16: FF = 0x47800000ULL; break; // 2^16 (as a float)
5444 case MVT::i32: FF = 0x4F800000ULL; break; // 2^32 (as a float)
5445 case MVT::i64: FF = 0x5F800000ULL; break; // 2^64 (as a float)
5447 if (TLI.isLittleEndian()) FF <<= 32;
5448 static Constant *FudgeFactor = ConstantInt::get(Type::Int64Ty, FF);
5450 SDOperand CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy());
5451 CPIdx = DAG.getNode(ISD::ADD, TLI.getPointerTy(), CPIdx, CstOffset);
5452 SDOperand FudgeInReg;
5453 if (DestVT == MVT::f32)
5454 FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx,
5455 PseudoSourceValue::getConstantPool(), 0);
5458 LegalizeOp(DAG.getExtLoad(ISD::EXTLOAD, DestVT,
5459 DAG.getEntryNode(), CPIdx,
5460 PseudoSourceValue::getConstantPool(), 0,
5464 return DAG.getNode(ISD::FADD, DestVT, Tmp1, FudgeInReg);
5467 /// PromoteLegalINT_TO_FP - This function is responsible for legalizing a
5468 /// *INT_TO_FP operation of the specified operand when the target requests that
5469 /// we promote it. At this point, we know that the result and operand types are
5470 /// legal for the target, and that there is a legal UINT_TO_FP or SINT_TO_FP
5471 /// operation that takes a larger input.
5472 SDOperand SelectionDAGLegalize::PromoteLegalINT_TO_FP(SDOperand LegalOp,
5473 MVT::ValueType DestVT,
5475 // First step, figure out the appropriate *INT_TO_FP operation to use.
5476 MVT::ValueType NewInTy = LegalOp.getValueType();
5478 unsigned OpToUse = 0;
5480 // Scan for the appropriate larger type to use.
5482 NewInTy = (MVT::ValueType)(NewInTy+1);
5483 assert(MVT::isInteger(NewInTy) && "Ran out of possibilities!");
5485 // If the target supports SINT_TO_FP of this type, use it.
5486 switch (TLI.getOperationAction(ISD::SINT_TO_FP, NewInTy)) {
5488 case TargetLowering::Legal:
5489 if (!TLI.isTypeLegal(NewInTy))
5490 break; // Can't use this datatype.
5492 case TargetLowering::Custom:
5493 OpToUse = ISD::SINT_TO_FP;
5497 if (isSigned) continue;
5499 // If the target supports UINT_TO_FP of this type, use it.
5500 switch (TLI.getOperationAction(ISD::UINT_TO_FP, NewInTy)) {
5502 case TargetLowering::Legal:
5503 if (!TLI.isTypeLegal(NewInTy))
5504 break; // Can't use this datatype.
5506 case TargetLowering::Custom:
5507 OpToUse = ISD::UINT_TO_FP;
5512 // Otherwise, try a larger type.
5515 // Okay, we found the operation and type to use. Zero extend our input to the
5516 // desired type then run the operation on it.
5517 return DAG.getNode(OpToUse, DestVT,
5518 DAG.getNode(isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND,
5522 /// PromoteLegalFP_TO_INT - This function is responsible for legalizing a
5523 /// FP_TO_*INT operation of the specified operand when the target requests that
5524 /// we promote it. At this point, we know that the result and operand types are
5525 /// legal for the target, and that there is a legal FP_TO_UINT or FP_TO_SINT
5526 /// operation that returns a larger result.
5527 SDOperand SelectionDAGLegalize::PromoteLegalFP_TO_INT(SDOperand LegalOp,
5528 MVT::ValueType DestVT,
5530 // First step, figure out the appropriate FP_TO*INT operation to use.
5531 MVT::ValueType NewOutTy = DestVT;
5533 unsigned OpToUse = 0;
5535 // Scan for the appropriate larger type to use.
5537 NewOutTy = (MVT::ValueType)(NewOutTy+1);
5538 assert(MVT::isInteger(NewOutTy) && "Ran out of possibilities!");
5540 // If the target supports FP_TO_SINT returning this type, use it.
5541 switch (TLI.getOperationAction(ISD::FP_TO_SINT, NewOutTy)) {
5543 case TargetLowering::Legal:
5544 if (!TLI.isTypeLegal(NewOutTy))
5545 break; // Can't use this datatype.
5547 case TargetLowering::Custom:
5548 OpToUse = ISD::FP_TO_SINT;
5553 // If the target supports FP_TO_UINT of this type, use it.
5554 switch (TLI.getOperationAction(ISD::FP_TO_UINT, NewOutTy)) {
5556 case TargetLowering::Legal:
5557 if (!TLI.isTypeLegal(NewOutTy))
5558 break; // Can't use this datatype.
5560 case TargetLowering::Custom:
5561 OpToUse = ISD::FP_TO_UINT;
5566 // Otherwise, try a larger type.
5570 // Okay, we found the operation and type to use.
5571 SDOperand Operation = DAG.getNode(OpToUse, NewOutTy, LegalOp);
5573 // If the operation produces an invalid type, it must be custom lowered. Use
5574 // the target lowering hooks to expand it. Just keep the low part of the
5575 // expanded operation, we know that we're truncating anyway.
5576 if (getTypeAction(NewOutTy) == Expand) {
5577 Operation = SDOperand(TLI.ExpandOperationResult(Operation.Val, DAG), 0);
5578 assert(Operation.Val && "Didn't return anything");
5581 // Truncate the result of the extended FP_TO_*INT operation to the desired
5583 return DAG.getNode(ISD::TRUNCATE, DestVT, Operation);
5586 /// ExpandBSWAP - Open code the operations for BSWAP of the specified operation.
5588 SDOperand SelectionDAGLegalize::ExpandBSWAP(SDOperand Op) {
5589 MVT::ValueType VT = Op.getValueType();
5590 MVT::ValueType SHVT = TLI.getShiftAmountTy();
5591 SDOperand Tmp1, Tmp2, Tmp3, Tmp4, Tmp5, Tmp6, Tmp7, Tmp8;
5593 default: assert(0 && "Unhandled Expand type in BSWAP!"); abort();
5595 Tmp2 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT));
5596 Tmp1 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(8, SHVT));
5597 return DAG.getNode(ISD::OR, VT, Tmp1, Tmp2);
5599 Tmp4 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(24, SHVT));
5600 Tmp3 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT));
5601 Tmp2 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(8, SHVT));
5602 Tmp1 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(24, SHVT));
5603 Tmp3 = DAG.getNode(ISD::AND, VT, Tmp3, DAG.getConstant(0xFF0000, VT));
5604 Tmp2 = DAG.getNode(ISD::AND, VT, Tmp2, DAG.getConstant(0xFF00, VT));
5605 Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp3);
5606 Tmp2 = DAG.getNode(ISD::OR, VT, Tmp2, Tmp1);
5607 return DAG.getNode(ISD::OR, VT, Tmp4, Tmp2);
5609 Tmp8 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(56, SHVT));
5610 Tmp7 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(40, SHVT));
5611 Tmp6 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(24, SHVT));
5612 Tmp5 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT));
5613 Tmp4 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(8, SHVT));
5614 Tmp3 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(24, SHVT));
5615 Tmp2 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(40, SHVT));
5616 Tmp1 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(56, SHVT));
5617 Tmp7 = DAG.getNode(ISD::AND, VT, Tmp7, DAG.getConstant(255ULL<<48, VT));
5618 Tmp6 = DAG.getNode(ISD::AND, VT, Tmp6, DAG.getConstant(255ULL<<40, VT));
5619 Tmp5 = DAG.getNode(ISD::AND, VT, Tmp5, DAG.getConstant(255ULL<<32, VT));
5620 Tmp4 = DAG.getNode(ISD::AND, VT, Tmp4, DAG.getConstant(255ULL<<24, VT));
5621 Tmp3 = DAG.getNode(ISD::AND, VT, Tmp3, DAG.getConstant(255ULL<<16, VT));
5622 Tmp2 = DAG.getNode(ISD::AND, VT, Tmp2, DAG.getConstant(255ULL<<8 , VT));
5623 Tmp8 = DAG.getNode(ISD::OR, VT, Tmp8, Tmp7);
5624 Tmp6 = DAG.getNode(ISD::OR, VT, Tmp6, Tmp5);
5625 Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp3);
5626 Tmp2 = DAG.getNode(ISD::OR, VT, Tmp2, Tmp1);
5627 Tmp8 = DAG.getNode(ISD::OR, VT, Tmp8, Tmp6);
5628 Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp2);
5629 return DAG.getNode(ISD::OR, VT, Tmp8, Tmp4);
5633 /// ExpandBitCount - Expand the specified bitcount instruction into operations.
5635 SDOperand SelectionDAGLegalize::ExpandBitCount(unsigned Opc, SDOperand Op) {
5637 default: assert(0 && "Cannot expand this yet!");
5639 static const uint64_t mask[6] = {
5640 0x5555555555555555ULL, 0x3333333333333333ULL,
5641 0x0F0F0F0F0F0F0F0FULL, 0x00FF00FF00FF00FFULL,
5642 0x0000FFFF0000FFFFULL, 0x00000000FFFFFFFFULL
5644 MVT::ValueType VT = Op.getValueType();
5645 MVT::ValueType ShVT = TLI.getShiftAmountTy();
5646 unsigned len = MVT::getSizeInBits(VT);
5647 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) {
5648 //x = (x & mask[i][len/8]) + (x >> (1 << i) & mask[i][len/8])
5649 SDOperand Tmp2 = DAG.getConstant(mask[i], VT);
5650 SDOperand Tmp3 = DAG.getConstant(1ULL << i, ShVT);
5651 Op = DAG.getNode(ISD::ADD, VT, DAG.getNode(ISD::AND, VT, Op, Tmp2),
5652 DAG.getNode(ISD::AND, VT,
5653 DAG.getNode(ISD::SRL, VT, Op, Tmp3),Tmp2));
5658 // for now, we do this:
5659 // x = x | (x >> 1);
5660 // x = x | (x >> 2);
5662 // x = x | (x >>16);
5663 // x = x | (x >>32); // for 64-bit input
5664 // return popcount(~x);
5666 // but see also: http://www.hackersdelight.org/HDcode/nlz.cc
5667 MVT::ValueType VT = Op.getValueType();
5668 MVT::ValueType ShVT = TLI.getShiftAmountTy();
5669 unsigned len = MVT::getSizeInBits(VT);
5670 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) {
5671 SDOperand Tmp3 = DAG.getConstant(1ULL << i, ShVT);
5672 Op = DAG.getNode(ISD::OR, VT, Op, DAG.getNode(ISD::SRL, VT, Op, Tmp3));
5674 Op = DAG.getNode(ISD::XOR, VT, Op, DAG.getConstant(~0ULL, VT));
5675 return DAG.getNode(ISD::CTPOP, VT, Op);
5678 // for now, we use: { return popcount(~x & (x - 1)); }
5679 // unless the target has ctlz but not ctpop, in which case we use:
5680 // { return 32 - nlz(~x & (x-1)); }
5681 // see also http://www.hackersdelight.org/HDcode/ntz.cc
5682 MVT::ValueType VT = Op.getValueType();
5683 SDOperand Tmp2 = DAG.getConstant(~0ULL, VT);
5684 SDOperand Tmp3 = DAG.getNode(ISD::AND, VT,
5685 DAG.getNode(ISD::XOR, VT, Op, Tmp2),
5686 DAG.getNode(ISD::SUB, VT, Op, DAG.getConstant(1, VT)));
5687 // If ISD::CTLZ is legal and CTPOP isn't, then do that instead.
5688 if (!TLI.isOperationLegal(ISD::CTPOP, VT) &&
5689 TLI.isOperationLegal(ISD::CTLZ, VT))
5690 return DAG.getNode(ISD::SUB, VT,
5691 DAG.getConstant(MVT::getSizeInBits(VT), VT),
5692 DAG.getNode(ISD::CTLZ, VT, Tmp3));
5693 return DAG.getNode(ISD::CTPOP, VT, Tmp3);
5698 /// ExpandOp - Expand the specified SDOperand into its two component pieces
5699 /// Lo&Hi. Note that the Op MUST be an expanded type. As a result of this, the
5700 /// LegalizeNodes map is filled in for any results that are not expanded, the
5701 /// ExpandedNodes map is filled in for any results that are expanded, and the
5702 /// Lo/Hi values are returned.
5703 void SelectionDAGLegalize::ExpandOp(SDOperand Op, SDOperand &Lo, SDOperand &Hi){
5704 MVT::ValueType VT = Op.getValueType();
5705 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT);
5706 SDNode *Node = Op.Val;
5707 assert(getTypeAction(VT) == Expand && "Not an expanded type!");
5708 assert(((MVT::isInteger(NVT) && NVT < VT) || MVT::isFloatingPoint(VT) ||
5709 MVT::isVector(VT)) &&
5710 "Cannot expand to FP value or to larger int value!");
5712 // See if we already expanded it.
5713 DenseMap<SDOperand, std::pair<SDOperand, SDOperand> >::iterator I
5714 = ExpandedNodes.find(Op);
5715 if (I != ExpandedNodes.end()) {
5716 Lo = I->second.first;
5717 Hi = I->second.second;
5721 switch (Node->getOpcode()) {
5722 case ISD::CopyFromReg:
5723 assert(0 && "CopyFromReg must be legal!");
5724 case ISD::FP_ROUND_INREG:
5725 if (VT == MVT::ppcf128 &&
5726 TLI.getOperationAction(ISD::FP_ROUND_INREG, VT) ==
5727 TargetLowering::Custom) {
5728 SDOperand SrcLo, SrcHi, Src;
5729 ExpandOp(Op.getOperand(0), SrcLo, SrcHi);
5730 Src = DAG.getNode(ISD::BUILD_PAIR, VT, SrcLo, SrcHi);
5731 SDOperand Result = TLI.LowerOperation(
5732 DAG.getNode(ISD::FP_ROUND_INREG, VT, Src, Op.getOperand(1)), DAG);
5733 assert(Result.Val->getOpcode() == ISD::BUILD_PAIR);
5734 Lo = Result.Val->getOperand(0);
5735 Hi = Result.Val->getOperand(1);
5741 cerr << "NODE: "; Node->dump(&DAG); cerr << "\n";
5743 assert(0 && "Do not know how to expand this operator!");
5745 case ISD::EXTRACT_ELEMENT:
5746 ExpandOp(Node->getOperand(0), Lo, Hi);
5747 if (cast<ConstantSDNode>(Node->getOperand(1))->getValue())
5748 return ExpandOp(Hi, Lo, Hi);
5749 return ExpandOp(Lo, Lo, Hi);
5750 case ISD::EXTRACT_VECTOR_ELT:
5751 assert(VT==MVT::i64 && "Do not know how to expand this operator!");
5752 // ExpandEXTRACT_VECTOR_ELT tolerates invalid result types.
5753 Lo = ExpandEXTRACT_VECTOR_ELT(Op);
5754 return ExpandOp(Lo, Lo, Hi);
5756 NVT = TLI.getTypeToExpandTo(VT);
5757 Lo = DAG.getNode(ISD::UNDEF, NVT);
5758 Hi = DAG.getNode(ISD::UNDEF, NVT);
5760 case ISD::Constant: {
5761 uint64_t Cst = cast<ConstantSDNode>(Node)->getValue();
5762 Lo = DAG.getConstant(Cst, NVT);
5763 Hi = DAG.getConstant(Cst >> MVT::getSizeInBits(NVT), NVT);
5766 case ISD::ConstantFP: {
5767 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node);
5768 if (CFP->getValueType(0) == MVT::ppcf128) {
5769 APInt api = CFP->getValueAPF().convertToAPInt();
5770 Lo = DAG.getConstantFP(APFloat(APInt(64, 1, &api.getRawData()[1])),
5772 Hi = DAG.getConstantFP(APFloat(APInt(64, 1, &api.getRawData()[0])),
5776 Lo = ExpandConstantFP(CFP, false, DAG, TLI);
5777 if (getTypeAction(Lo.getValueType()) == Expand)
5778 ExpandOp(Lo, Lo, Hi);
5781 case ISD::BUILD_PAIR:
5782 // Return the operands.
5783 Lo = Node->getOperand(0);
5784 Hi = Node->getOperand(1);
5787 case ISD::MERGE_VALUES:
5788 if (Node->getNumValues() == 1) {
5789 ExpandOp(Op.getOperand(0), Lo, Hi);
5792 // FIXME: For now only expand i64,chain = MERGE_VALUES (x, y)
5793 assert(Op.ResNo == 0 && Node->getNumValues() == 2 &&
5794 Op.getValue(1).getValueType() == MVT::Other &&
5795 "unhandled MERGE_VALUES");
5796 ExpandOp(Op.getOperand(0), Lo, Hi);
5797 // Remember that we legalized the chain.
5798 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Op.getOperand(1)));
5801 case ISD::SIGN_EXTEND_INREG:
5802 ExpandOp(Node->getOperand(0), Lo, Hi);
5803 // sext_inreg the low part if needed.
5804 Lo = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Lo, Node->getOperand(1));
5806 // The high part gets the sign extension from the lo-part. This handles
5807 // things like sextinreg V:i64 from i8.
5808 Hi = DAG.getNode(ISD::SRA, NVT, Lo,
5809 DAG.getConstant(MVT::getSizeInBits(NVT)-1,
5810 TLI.getShiftAmountTy()));
5814 ExpandOp(Node->getOperand(0), Lo, Hi);
5815 SDOperand TempLo = DAG.getNode(ISD::BSWAP, NVT, Hi);
5816 Hi = DAG.getNode(ISD::BSWAP, NVT, Lo);
5822 ExpandOp(Node->getOperand(0), Lo, Hi);
5823 Lo = DAG.getNode(ISD::ADD, NVT, // ctpop(HL) -> ctpop(H)+ctpop(L)
5824 DAG.getNode(ISD::CTPOP, NVT, Lo),
5825 DAG.getNode(ISD::CTPOP, NVT, Hi));
5826 Hi = DAG.getConstant(0, NVT);
5830 // ctlz (HL) -> ctlz(H) != 32 ? ctlz(H) : (ctlz(L)+32)
5831 ExpandOp(Node->getOperand(0), Lo, Hi);
5832 SDOperand BitsC = DAG.getConstant(MVT::getSizeInBits(NVT), NVT);
5833 SDOperand HLZ = DAG.getNode(ISD::CTLZ, NVT, Hi);
5834 SDOperand TopNotZero = DAG.getSetCC(TLI.getSetCCResultTy(), HLZ, BitsC,
5836 SDOperand LowPart = DAG.getNode(ISD::CTLZ, NVT, Lo);
5837 LowPart = DAG.getNode(ISD::ADD, NVT, LowPart, BitsC);
5839 Lo = DAG.getNode(ISD::SELECT, NVT, TopNotZero, HLZ, LowPart);
5840 Hi = DAG.getConstant(0, NVT);
5845 // cttz (HL) -> cttz(L) != 32 ? cttz(L) : (cttz(H)+32)
5846 ExpandOp(Node->getOperand(0), Lo, Hi);
5847 SDOperand BitsC = DAG.getConstant(MVT::getSizeInBits(NVT), NVT);
5848 SDOperand LTZ = DAG.getNode(ISD::CTTZ, NVT, Lo);
5849 SDOperand BotNotZero = DAG.getSetCC(TLI.getSetCCResultTy(), LTZ, BitsC,
5851 SDOperand HiPart = DAG.getNode(ISD::CTTZ, NVT, Hi);
5852 HiPart = DAG.getNode(ISD::ADD, NVT, HiPart, BitsC);
5854 Lo = DAG.getNode(ISD::SELECT, NVT, BotNotZero, LTZ, HiPart);
5855 Hi = DAG.getConstant(0, NVT);
5860 SDOperand Ch = Node->getOperand(0); // Legalize the chain.
5861 SDOperand Ptr = Node->getOperand(1); // Legalize the pointer.
5862 Lo = DAG.getVAArg(NVT, Ch, Ptr, Node->getOperand(2));
5863 Hi = DAG.getVAArg(NVT, Lo.getValue(1), Ptr, Node->getOperand(2));
5865 // Remember that we legalized the chain.
5866 Hi = LegalizeOp(Hi);
5867 AddLegalizedOperand(Op.getValue(1), Hi.getValue(1));
5868 if (TLI.isBigEndian())
5874 LoadSDNode *LD = cast<LoadSDNode>(Node);
5875 SDOperand Ch = LD->getChain(); // Legalize the chain.
5876 SDOperand Ptr = LD->getBasePtr(); // Legalize the pointer.
5877 ISD::LoadExtType ExtType = LD->getExtensionType();
5878 int SVOffset = LD->getSrcValueOffset();
5879 unsigned Alignment = LD->getAlignment();
5880 bool isVolatile = LD->isVolatile();
5882 if (ExtType == ISD::NON_EXTLOAD) {
5883 Lo = DAG.getLoad(NVT, Ch, Ptr, LD->getSrcValue(), SVOffset,
5884 isVolatile, Alignment);
5885 if (VT == MVT::f32 || VT == MVT::f64) {
5886 // f32->i32 or f64->i64 one to one expansion.
5887 // Remember that we legalized the chain.
5888 AddLegalizedOperand(SDOperand(Node, 1), LegalizeOp(Lo.getValue(1)));
5889 // Recursively expand the new load.
5890 if (getTypeAction(NVT) == Expand)
5891 ExpandOp(Lo, Lo, Hi);
5895 // Increment the pointer to the other half.
5896 unsigned IncrementSize = MVT::getSizeInBits(Lo.getValueType())/8;
5897 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
5898 DAG.getIntPtrConstant(IncrementSize));
5899 SVOffset += IncrementSize;
5900 Alignment = MinAlign(Alignment, IncrementSize);
5901 Hi = DAG.getLoad(NVT, Ch, Ptr, LD->getSrcValue(), SVOffset,
5902 isVolatile, Alignment);
5904 // Build a factor node to remember that this load is independent of the
5906 SDOperand TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
5909 // Remember that we legalized the chain.
5910 AddLegalizedOperand(Op.getValue(1), LegalizeOp(TF));
5911 if (TLI.isBigEndian())
5914 MVT::ValueType EVT = LD->getMemoryVT();
5916 if ((VT == MVT::f64 && EVT == MVT::f32) ||
5917 (VT == MVT::ppcf128 && (EVT==MVT::f64 || EVT==MVT::f32))) {
5918 // f64 = EXTLOAD f32 should expand to LOAD, FP_EXTEND
5919 SDOperand Load = DAG.getLoad(EVT, Ch, Ptr, LD->getSrcValue(),
5920 SVOffset, isVolatile, Alignment);
5921 // Remember that we legalized the chain.
5922 AddLegalizedOperand(SDOperand(Node, 1), LegalizeOp(Load.getValue(1)));
5923 ExpandOp(DAG.getNode(ISD::FP_EXTEND, VT, Load), Lo, Hi);
5928 Lo = DAG.getLoad(NVT, Ch, Ptr, LD->getSrcValue(),
5929 SVOffset, isVolatile, Alignment);
5931 Lo = DAG.getExtLoad(ExtType, NVT, Ch, Ptr, LD->getSrcValue(),
5932 SVOffset, EVT, isVolatile,
5935 // Remember that we legalized the chain.
5936 AddLegalizedOperand(SDOperand(Node, 1), LegalizeOp(Lo.getValue(1)));
5938 if (ExtType == ISD::SEXTLOAD) {
5939 // The high part is obtained by SRA'ing all but one of the bits of the
5941 unsigned LoSize = MVT::getSizeInBits(Lo.getValueType());
5942 Hi = DAG.getNode(ISD::SRA, NVT, Lo,
5943 DAG.getConstant(LoSize-1, TLI.getShiftAmountTy()));
5944 } else if (ExtType == ISD::ZEXTLOAD) {
5945 // The high part is just a zero.
5946 Hi = DAG.getConstant(0, NVT);
5947 } else /* if (ExtType == ISD::EXTLOAD) */ {
5948 // The high part is undefined.
5949 Hi = DAG.getNode(ISD::UNDEF, NVT);
5956 case ISD::XOR: { // Simple logical operators -> two trivial pieces.
5957 SDOperand LL, LH, RL, RH;
5958 ExpandOp(Node->getOperand(0), LL, LH);
5959 ExpandOp(Node->getOperand(1), RL, RH);
5960 Lo = DAG.getNode(Node->getOpcode(), NVT, LL, RL);
5961 Hi = DAG.getNode(Node->getOpcode(), NVT, LH, RH);
5965 SDOperand LL, LH, RL, RH;
5966 ExpandOp(Node->getOperand(1), LL, LH);
5967 ExpandOp(Node->getOperand(2), RL, RH);
5968 if (getTypeAction(NVT) == Expand)
5969 NVT = TLI.getTypeToExpandTo(NVT);
5970 Lo = DAG.getNode(ISD::SELECT, NVT, Node->getOperand(0), LL, RL);
5972 Hi = DAG.getNode(ISD::SELECT, NVT, Node->getOperand(0), LH, RH);
5975 case ISD::SELECT_CC: {
5976 SDOperand TL, TH, FL, FH;
5977 ExpandOp(Node->getOperand(2), TL, TH);
5978 ExpandOp(Node->getOperand(3), FL, FH);
5979 if (getTypeAction(NVT) == Expand)
5980 NVT = TLI.getTypeToExpandTo(NVT);
5981 Lo = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0),
5982 Node->getOperand(1), TL, FL, Node->getOperand(4));
5984 Hi = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0),
5985 Node->getOperand(1), TH, FH, Node->getOperand(4));
5988 case ISD::ANY_EXTEND:
5989 // The low part is any extension of the input (which degenerates to a copy).
5990 Lo = DAG.getNode(ISD::ANY_EXTEND, NVT, Node->getOperand(0));
5991 // The high part is undefined.
5992 Hi = DAG.getNode(ISD::UNDEF, NVT);
5994 case ISD::SIGN_EXTEND: {
5995 // The low part is just a sign extension of the input (which degenerates to
5997 Lo = DAG.getNode(ISD::SIGN_EXTEND, NVT, Node->getOperand(0));
5999 // The high part is obtained by SRA'ing all but one of the bits of the lo
6001 unsigned LoSize = MVT::getSizeInBits(Lo.getValueType());
6002 Hi = DAG.getNode(ISD::SRA, NVT, Lo,
6003 DAG.getConstant(LoSize-1, TLI.getShiftAmountTy()));
6006 case ISD::ZERO_EXTEND:
6007 // The low part is just a zero extension of the input (which degenerates to
6009 Lo = DAG.getNode(ISD::ZERO_EXTEND, NVT, Node->getOperand(0));
6011 // The high part is just a zero.
6012 Hi = DAG.getConstant(0, NVT);
6015 case ISD::TRUNCATE: {
6016 // The input value must be larger than this value. Expand *it*.
6018 ExpandOp(Node->getOperand(0), NewLo, Hi);
6020 // The low part is now either the right size, or it is closer. If not the
6021 // right size, make an illegal truncate so we recursively expand it.
6022 if (NewLo.getValueType() != Node->getValueType(0))
6023 NewLo = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), NewLo);
6024 ExpandOp(NewLo, Lo, Hi);
6028 case ISD::BIT_CONVERT: {
6030 if (TLI.getOperationAction(ISD::BIT_CONVERT, VT) == TargetLowering::Custom){
6031 // If the target wants to, allow it to lower this itself.
6032 switch (getTypeAction(Node->getOperand(0).getValueType())) {
6033 case Expand: assert(0 && "cannot expand FP!");
6034 case Legal: Tmp = LegalizeOp(Node->getOperand(0)); break;
6035 case Promote: Tmp = PromoteOp (Node->getOperand(0)); break;
6037 Tmp = TLI.LowerOperation(DAG.getNode(ISD::BIT_CONVERT, VT, Tmp), DAG);
6040 // f32 / f64 must be expanded to i32 / i64.
6041 if (VT == MVT::f32 || VT == MVT::f64) {
6042 Lo = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0));
6043 if (getTypeAction(NVT) == Expand)
6044 ExpandOp(Lo, Lo, Hi);
6048 // If source operand will be expanded to the same type as VT, i.e.
6049 // i64 <- f64, i32 <- f32, expand the source operand instead.
6050 MVT::ValueType VT0 = Node->getOperand(0).getValueType();
6051 if (getTypeAction(VT0) == Expand && TLI.getTypeToTransformTo(VT0) == VT) {
6052 ExpandOp(Node->getOperand(0), Lo, Hi);
6056 // Turn this into a load/store pair by default.
6058 Tmp = EmitStackConvert(Node->getOperand(0), VT, VT);
6060 ExpandOp(Tmp, Lo, Hi);
6064 case ISD::READCYCLECOUNTER: {
6065 assert(TLI.getOperationAction(ISD::READCYCLECOUNTER, VT) ==
6066 TargetLowering::Custom &&
6067 "Must custom expand ReadCycleCounter");
6068 SDOperand Tmp = TLI.LowerOperation(Op, DAG);
6069 assert(Tmp.Val && "Node must be custom expanded!");
6070 ExpandOp(Tmp.getValue(0), Lo, Hi);
6071 AddLegalizedOperand(SDOperand(Node, 1), // Remember we legalized the chain.
6072 LegalizeOp(Tmp.getValue(1)));
6076 // These operators cannot be expanded directly, emit them as calls to
6077 // library functions.
6078 case ISD::FP_TO_SINT: {
6079 if (TLI.getOperationAction(ISD::FP_TO_SINT, VT) == TargetLowering::Custom) {
6081 switch (getTypeAction(Node->getOperand(0).getValueType())) {
6082 case Expand: assert(0 && "cannot expand FP!");
6083 case Legal: Op = LegalizeOp(Node->getOperand(0)); break;
6084 case Promote: Op = PromoteOp (Node->getOperand(0)); break;
6087 Op = TLI.LowerOperation(DAG.getNode(ISD::FP_TO_SINT, VT, Op), DAG);
6089 // Now that the custom expander is done, expand the result, which is still
6092 ExpandOp(Op, Lo, Hi);
6097 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
6098 if (Node->getOperand(0).getValueType() == MVT::f32)
6099 LC = RTLIB::FPTOSINT_F32_I64;
6100 else if (Node->getOperand(0).getValueType() == MVT::f64)
6101 LC = RTLIB::FPTOSINT_F64_I64;
6102 else if (Node->getOperand(0).getValueType() == MVT::f80)
6103 LC = RTLIB::FPTOSINT_F80_I64;
6104 else if (Node->getOperand(0).getValueType() == MVT::ppcf128)
6105 LC = RTLIB::FPTOSINT_PPCF128_I64;
6106 Lo = ExpandLibCall(TLI.getLibcallName(LC), Node,
6107 false/*sign irrelevant*/, Hi);
6111 case ISD::FP_TO_UINT: {
6112 if (TLI.getOperationAction(ISD::FP_TO_UINT, VT) == TargetLowering::Custom) {
6114 switch (getTypeAction(Node->getOperand(0).getValueType())) {
6115 case Expand: assert(0 && "cannot expand FP!");
6116 case Legal: Op = LegalizeOp(Node->getOperand(0)); break;
6117 case Promote: Op = PromoteOp (Node->getOperand(0)); break;
6120 Op = TLI.LowerOperation(DAG.getNode(ISD::FP_TO_UINT, VT, Op), DAG);
6122 // Now that the custom expander is done, expand the result.
6124 ExpandOp(Op, Lo, Hi);
6129 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
6130 if (Node->getOperand(0).getValueType() == MVT::f32)
6131 LC = RTLIB::FPTOUINT_F32_I64;
6132 else if (Node->getOperand(0).getValueType() == MVT::f64)
6133 LC = RTLIB::FPTOUINT_F64_I64;
6134 else if (Node->getOperand(0).getValueType() == MVT::f80)
6135 LC = RTLIB::FPTOUINT_F80_I64;
6136 else if (Node->getOperand(0).getValueType() == MVT::ppcf128)
6137 LC = RTLIB::FPTOUINT_PPCF128_I64;
6138 Lo = ExpandLibCall(TLI.getLibcallName(LC), Node,
6139 false/*sign irrelevant*/, Hi);
6144 // If the target wants custom lowering, do so.
6145 SDOperand ShiftAmt = LegalizeOp(Node->getOperand(1));
6146 if (TLI.getOperationAction(ISD::SHL, VT) == TargetLowering::Custom) {
6147 SDOperand Op = DAG.getNode(ISD::SHL, VT, Node->getOperand(0), ShiftAmt);
6148 Op = TLI.LowerOperation(Op, DAG);
6150 // Now that the custom expander is done, expand the result, which is
6152 ExpandOp(Op, Lo, Hi);
6157 // If ADDC/ADDE are supported and if the shift amount is a constant 1, emit
6158 // this X << 1 as X+X.
6159 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(ShiftAmt)) {
6160 if (ShAmt->getValue() == 1 && TLI.isOperationLegal(ISD::ADDC, NVT) &&
6161 TLI.isOperationLegal(ISD::ADDE, NVT)) {
6162 SDOperand LoOps[2], HiOps[3];
6163 ExpandOp(Node->getOperand(0), LoOps[0], HiOps[0]);
6164 SDVTList VTList = DAG.getVTList(LoOps[0].getValueType(), MVT::Flag);
6165 LoOps[1] = LoOps[0];
6166 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2);
6168 HiOps[1] = HiOps[0];
6169 HiOps[2] = Lo.getValue(1);
6170 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3);
6175 // If we can emit an efficient shift operation, do so now.
6176 if (ExpandShift(ISD::SHL, Node->getOperand(0), ShiftAmt, Lo, Hi))
6179 // If this target supports SHL_PARTS, use it.
6180 TargetLowering::LegalizeAction Action =
6181 TLI.getOperationAction(ISD::SHL_PARTS, NVT);
6182 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) ||
6183 Action == TargetLowering::Custom) {
6184 ExpandShiftParts(ISD::SHL_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi);
6188 // Otherwise, emit a libcall.
6189 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::SHL_I64), Node,
6190 false/*left shift=unsigned*/, Hi);
6195 // If the target wants custom lowering, do so.
6196 SDOperand ShiftAmt = LegalizeOp(Node->getOperand(1));
6197 if (TLI.getOperationAction(ISD::SRA, VT) == TargetLowering::Custom) {
6198 SDOperand Op = DAG.getNode(ISD::SRA, VT, Node->getOperand(0), ShiftAmt);
6199 Op = TLI.LowerOperation(Op, DAG);
6201 // Now that the custom expander is done, expand the result, which is
6203 ExpandOp(Op, Lo, Hi);
6208 // If we can emit an efficient shift operation, do so now.
6209 if (ExpandShift(ISD::SRA, Node->getOperand(0), ShiftAmt, Lo, Hi))
6212 // If this target supports SRA_PARTS, use it.
6213 TargetLowering::LegalizeAction Action =
6214 TLI.getOperationAction(ISD::SRA_PARTS, NVT);
6215 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) ||
6216 Action == TargetLowering::Custom) {
6217 ExpandShiftParts(ISD::SRA_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi);
6221 // Otherwise, emit a libcall.
6222 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::SRA_I64), Node,
6223 true/*ashr is signed*/, Hi);
6228 // If the target wants custom lowering, do so.
6229 SDOperand ShiftAmt = LegalizeOp(Node->getOperand(1));
6230 if (TLI.getOperationAction(ISD::SRL, VT) == TargetLowering::Custom) {
6231 SDOperand Op = DAG.getNode(ISD::SRL, VT, Node->getOperand(0), ShiftAmt);
6232 Op = TLI.LowerOperation(Op, DAG);
6234 // Now that the custom expander is done, expand the result, which is
6236 ExpandOp(Op, Lo, Hi);
6241 // If we can emit an efficient shift operation, do so now.
6242 if (ExpandShift(ISD::SRL, Node->getOperand(0), ShiftAmt, Lo, Hi))
6245 // If this target supports SRL_PARTS, use it.
6246 TargetLowering::LegalizeAction Action =
6247 TLI.getOperationAction(ISD::SRL_PARTS, NVT);
6248 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) ||
6249 Action == TargetLowering::Custom) {
6250 ExpandShiftParts(ISD::SRL_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi);
6254 // Otherwise, emit a libcall.
6255 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::SRL_I64), Node,
6256 false/*lshr is unsigned*/, Hi);
6262 // If the target wants to custom expand this, let them.
6263 if (TLI.getOperationAction(Node->getOpcode(), VT) ==
6264 TargetLowering::Custom) {
6265 Op = TLI.LowerOperation(Op, DAG);
6267 ExpandOp(Op, Lo, Hi);
6272 // Expand the subcomponents.
6273 SDOperand LHSL, LHSH, RHSL, RHSH;
6274 ExpandOp(Node->getOperand(0), LHSL, LHSH);
6275 ExpandOp(Node->getOperand(1), RHSL, RHSH);
6276 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag);
6277 SDOperand LoOps[2], HiOps[3];
6282 if (Node->getOpcode() == ISD::ADD) {
6283 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2);
6284 HiOps[2] = Lo.getValue(1);
6285 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3);
6287 Lo = DAG.getNode(ISD::SUBC, VTList, LoOps, 2);
6288 HiOps[2] = Lo.getValue(1);
6289 Hi = DAG.getNode(ISD::SUBE, VTList, HiOps, 3);
6296 // Expand the subcomponents.
6297 SDOperand LHSL, LHSH, RHSL, RHSH;
6298 ExpandOp(Node->getOperand(0), LHSL, LHSH);
6299 ExpandOp(Node->getOperand(1), RHSL, RHSH);
6300 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag);
6301 SDOperand LoOps[2] = { LHSL, RHSL };
6302 SDOperand HiOps[3] = { LHSH, RHSH };
6304 if (Node->getOpcode() == ISD::ADDC) {
6305 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2);
6306 HiOps[2] = Lo.getValue(1);
6307 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3);
6309 Lo = DAG.getNode(ISD::SUBC, VTList, LoOps, 2);
6310 HiOps[2] = Lo.getValue(1);
6311 Hi = DAG.getNode(ISD::SUBE, VTList, HiOps, 3);
6313 // Remember that we legalized the flag.
6314 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Hi.getValue(1)));
6319 // Expand the subcomponents.
6320 SDOperand LHSL, LHSH, RHSL, RHSH;
6321 ExpandOp(Node->getOperand(0), LHSL, LHSH);
6322 ExpandOp(Node->getOperand(1), RHSL, RHSH);
6323 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag);
6324 SDOperand LoOps[3] = { LHSL, RHSL, Node->getOperand(2) };
6325 SDOperand HiOps[3] = { LHSH, RHSH };
6327 Lo = DAG.getNode(Node->getOpcode(), VTList, LoOps, 3);
6328 HiOps[2] = Lo.getValue(1);
6329 Hi = DAG.getNode(Node->getOpcode(), VTList, HiOps, 3);
6331 // Remember that we legalized the flag.
6332 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Hi.getValue(1)));
6336 // If the target wants to custom expand this, let them.
6337 if (TLI.getOperationAction(ISD::MUL, VT) == TargetLowering::Custom) {
6338 SDOperand New = TLI.LowerOperation(Op, DAG);
6340 ExpandOp(New, Lo, Hi);
6345 bool HasMULHS = TLI.isOperationLegal(ISD::MULHS, NVT);
6346 bool HasMULHU = TLI.isOperationLegal(ISD::MULHU, NVT);
6347 bool HasSMUL_LOHI = TLI.isOperationLegal(ISD::SMUL_LOHI, NVT);
6348 bool HasUMUL_LOHI = TLI.isOperationLegal(ISD::UMUL_LOHI, NVT);
6349 if (HasMULHU || HasMULHS || HasUMUL_LOHI || HasSMUL_LOHI) {
6350 SDOperand LL, LH, RL, RH;
6351 ExpandOp(Node->getOperand(0), LL, LH);
6352 ExpandOp(Node->getOperand(1), RL, RH);
6353 unsigned OuterBitSize = Op.getValueSizeInBits();
6354 unsigned InnerBitSize = RH.getValueSizeInBits();
6355 unsigned LHSSB = DAG.ComputeNumSignBits(Op.getOperand(0));
6356 unsigned RHSSB = DAG.ComputeNumSignBits(Op.getOperand(1));
6357 if (DAG.MaskedValueIsZero(Op.getOperand(0),
6358 APInt::getHighBitsSet(OuterBitSize, LHSSB)) &&
6359 DAG.MaskedValueIsZero(Op.getOperand(1),
6360 APInt::getHighBitsSet(OuterBitSize, RHSSB))) {
6361 // The inputs are both zero-extended.
6363 // We can emit a umul_lohi.
6364 Lo = DAG.getNode(ISD::UMUL_LOHI, DAG.getVTList(NVT, NVT), LL, RL);
6365 Hi = SDOperand(Lo.Val, 1);
6369 // We can emit a mulhu+mul.
6370 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL);
6371 Hi = DAG.getNode(ISD::MULHU, NVT, LL, RL);
6375 if (LHSSB > InnerBitSize && RHSSB > InnerBitSize) {
6376 // The input values are both sign-extended.
6378 // We can emit a smul_lohi.
6379 Lo = DAG.getNode(ISD::SMUL_LOHI, DAG.getVTList(NVT, NVT), LL, RL);
6380 Hi = SDOperand(Lo.Val, 1);
6384 // We can emit a mulhs+mul.
6385 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL);
6386 Hi = DAG.getNode(ISD::MULHS, NVT, LL, RL);
6391 // Lo,Hi = umul LHS, RHS.
6392 SDOperand UMulLOHI = DAG.getNode(ISD::UMUL_LOHI,
6393 DAG.getVTList(NVT, NVT), LL, RL);
6395 Hi = UMulLOHI.getValue(1);
6396 RH = DAG.getNode(ISD::MUL, NVT, LL, RH);
6397 LH = DAG.getNode(ISD::MUL, NVT, LH, RL);
6398 Hi = DAG.getNode(ISD::ADD, NVT, Hi, RH);
6399 Hi = DAG.getNode(ISD::ADD, NVT, Hi, LH);
6403 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL);
6404 Hi = DAG.getNode(ISD::MULHU, NVT, LL, RL);
6405 RH = DAG.getNode(ISD::MUL, NVT, LL, RH);
6406 LH = DAG.getNode(ISD::MUL, NVT, LH, RL);
6407 Hi = DAG.getNode(ISD::ADD, NVT, Hi, RH);
6408 Hi = DAG.getNode(ISD::ADD, NVT, Hi, LH);
6413 // If nothing else, we can make a libcall.
6414 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::MUL_I64), Node,
6415 false/*sign irrelevant*/, Hi);
6419 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::SDIV_I64), Node, true, Hi);
6422 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::UDIV_I64), Node, true, Hi);
6425 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::SREM_I64), Node, true, Hi);
6428 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::UREM_I64), Node, true, Hi);
6432 Lo = ExpandLibCall(TLI.getLibcallName(GetFPLibCall(VT, RTLIB::ADD_F32,
6435 RTLIB::ADD_PPCF128)),
6439 Lo = ExpandLibCall(TLI.getLibcallName(GetFPLibCall(VT, RTLIB::SUB_F32,
6442 RTLIB::SUB_PPCF128)),
6446 Lo = ExpandLibCall(TLI.getLibcallName(GetFPLibCall(VT, RTLIB::MUL_F32,
6449 RTLIB::MUL_PPCF128)),
6453 Lo = ExpandLibCall(TLI.getLibcallName(GetFPLibCall(VT, RTLIB::DIV_F32,
6456 RTLIB::DIV_PPCF128)),
6459 case ISD::FP_EXTEND:
6460 if (VT == MVT::ppcf128) {
6461 assert(Node->getOperand(0).getValueType()==MVT::f32 ||
6462 Node->getOperand(0).getValueType()==MVT::f64);
6463 const uint64_t zero = 0;
6464 if (Node->getOperand(0).getValueType()==MVT::f32)
6465 Hi = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Node->getOperand(0));
6467 Hi = Node->getOperand(0);
6468 Lo = DAG.getConstantFP(APFloat(APInt(64, 1, &zero)), MVT::f64);
6471 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::FPEXT_F32_F64), Node, true,Hi);
6474 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::FPROUND_F64_F32),Node,true,Hi);
6477 Lo = ExpandLibCall(TLI.getLibcallName(GetFPLibCall(VT, RTLIB::POWI_F32,
6480 RTLIB::POWI_PPCF128)),
6486 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
6487 switch(Node->getOpcode()) {
6489 LC = GetFPLibCall(VT, RTLIB::SQRT_F32, RTLIB::SQRT_F64,
6490 RTLIB::SQRT_F80, RTLIB::SQRT_PPCF128);
6493 LC = GetFPLibCall(VT, RTLIB::SIN_F32, RTLIB::SIN_F64,
6494 RTLIB::SIN_F80, RTLIB::SIN_PPCF128);
6497 LC = GetFPLibCall(VT, RTLIB::COS_F32, RTLIB::COS_F64,
6498 RTLIB::COS_F80, RTLIB::COS_PPCF128);
6500 default: assert(0 && "Unreachable!");
6502 Lo = ExpandLibCall(TLI.getLibcallName(LC), Node, false, Hi);
6506 if (VT == MVT::ppcf128) {
6508 ExpandOp(Node->getOperand(0), Lo, Tmp);
6509 Hi = DAG.getNode(ISD::FABS, NVT, Tmp);
6510 // lo = hi==fabs(hi) ? lo : -lo;
6511 Lo = DAG.getNode(ISD::SELECT_CC, NVT, Hi, Tmp,
6512 Lo, DAG.getNode(ISD::FNEG, NVT, Lo),
6513 DAG.getCondCode(ISD::SETEQ));
6516 SDOperand Mask = (VT == MVT::f64)
6517 ? DAG.getConstantFP(BitsToDouble(~(1ULL << 63)), VT)
6518 : DAG.getConstantFP(BitsToFloat(~(1U << 31)), VT);
6519 Mask = DAG.getNode(ISD::BIT_CONVERT, NVT, Mask);
6520 Lo = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0));
6521 Lo = DAG.getNode(ISD::AND, NVT, Lo, Mask);
6522 if (getTypeAction(NVT) == Expand)
6523 ExpandOp(Lo, Lo, Hi);
6527 if (VT == MVT::ppcf128) {
6528 ExpandOp(Node->getOperand(0), Lo, Hi);
6529 Lo = DAG.getNode(ISD::FNEG, MVT::f64, Lo);
6530 Hi = DAG.getNode(ISD::FNEG, MVT::f64, Hi);
6533 SDOperand Mask = (VT == MVT::f64)
6534 ? DAG.getConstantFP(BitsToDouble(1ULL << 63), VT)
6535 : DAG.getConstantFP(BitsToFloat(1U << 31), VT);
6536 Mask = DAG.getNode(ISD::BIT_CONVERT, NVT, Mask);
6537 Lo = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0));
6538 Lo = DAG.getNode(ISD::XOR, NVT, Lo, Mask);
6539 if (getTypeAction(NVT) == Expand)
6540 ExpandOp(Lo, Lo, Hi);
6543 case ISD::FCOPYSIGN: {
6544 Lo = ExpandFCOPYSIGNToBitwiseOps(Node, NVT, DAG, TLI);
6545 if (getTypeAction(NVT) == Expand)
6546 ExpandOp(Lo, Lo, Hi);
6549 case ISD::SINT_TO_FP:
6550 case ISD::UINT_TO_FP: {
6551 bool isSigned = Node->getOpcode() == ISD::SINT_TO_FP;
6552 MVT::ValueType SrcVT = Node->getOperand(0).getValueType();
6553 if (VT == MVT::ppcf128 && SrcVT != MVT::i64) {
6554 static const uint64_t zero = 0;
6556 Hi = LegalizeOp(DAG.getNode(ISD::SINT_TO_FP, MVT::f64,
6557 Node->getOperand(0)));
6558 Lo = DAG.getConstantFP(APFloat(APInt(64, 1, &zero)), MVT::f64);
6560 static const uint64_t TwoE32[] = { 0x41f0000000000000LL, 0 };
6561 Hi = LegalizeOp(DAG.getNode(ISD::SINT_TO_FP, MVT::f64,
6562 Node->getOperand(0)));
6563 Lo = DAG.getConstantFP(APFloat(APInt(64, 1, &zero)), MVT::f64);
6564 Hi = DAG.getNode(ISD::BUILD_PAIR, VT, Lo, Hi);
6565 // X>=0 ? {(f64)x, 0} : {(f64)x, 0} + 2^32
6566 ExpandOp(DAG.getNode(ISD::SELECT_CC, MVT::ppcf128, Node->getOperand(0),
6567 DAG.getConstant(0, MVT::i32),
6568 DAG.getNode(ISD::FADD, MVT::ppcf128, Hi,
6570 APFloat(APInt(128, 2, TwoE32)),
6573 DAG.getCondCode(ISD::SETLT)),
6578 if (VT == MVT::ppcf128 && SrcVT == MVT::i64 && !isSigned) {
6579 // si64->ppcf128 done by libcall, below
6580 static const uint64_t TwoE64[] = { 0x43f0000000000000LL, 0 };
6581 ExpandOp(DAG.getNode(ISD::SINT_TO_FP, MVT::ppcf128, Node->getOperand(0)),
6583 Hi = DAG.getNode(ISD::BUILD_PAIR, VT, Lo, Hi);
6584 // x>=0 ? (ppcf128)(i64)x : (ppcf128)(i64)x + 2^64
6585 ExpandOp(DAG.getNode(ISD::SELECT_CC, MVT::ppcf128, Node->getOperand(0),
6586 DAG.getConstant(0, MVT::i64),
6587 DAG.getNode(ISD::FADD, MVT::ppcf128, Hi,
6589 APFloat(APInt(128, 2, TwoE64)),
6592 DAG.getCondCode(ISD::SETLT)),
6596 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
6597 if (Node->getOperand(0).getValueType() == MVT::i64) {
6599 LC = isSigned ? RTLIB::SINTTOFP_I64_F32 : RTLIB::UINTTOFP_I64_F32;
6600 else if (VT == MVT::f64)
6601 LC = isSigned ? RTLIB::SINTTOFP_I64_F64 : RTLIB::UINTTOFP_I64_F64;
6602 else if (VT == MVT::f80) {
6604 LC = RTLIB::SINTTOFP_I64_F80;
6606 else if (VT == MVT::ppcf128) {
6608 LC = RTLIB::SINTTOFP_I64_PPCF128;
6612 LC = isSigned ? RTLIB::SINTTOFP_I32_F32 : RTLIB::UINTTOFP_I32_F32;
6614 LC = isSigned ? RTLIB::SINTTOFP_I32_F64 : RTLIB::UINTTOFP_I32_F64;
6617 // Promote the operand if needed.
6618 if (getTypeAction(SrcVT) == Promote) {
6619 SDOperand Tmp = PromoteOp(Node->getOperand(0));
6621 ? DAG.getNode(ISD::SIGN_EXTEND_INREG, Tmp.getValueType(), Tmp,
6622 DAG.getValueType(SrcVT))
6623 : DAG.getZeroExtendInReg(Tmp, SrcVT);
6624 Node = DAG.UpdateNodeOperands(Op, Tmp).Val;
6627 const char *LibCall = TLI.getLibcallName(LC);
6629 Lo = ExpandLibCall(TLI.getLibcallName(LC), Node, isSigned, Hi);
6631 Lo = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP, VT,
6632 Node->getOperand(0));
6633 if (getTypeAction(Lo.getValueType()) == Expand)
6634 ExpandOp(Lo, Lo, Hi);
6640 // Make sure the resultant values have been legalized themselves, unless this
6641 // is a type that requires multi-step expansion.
6642 if (getTypeAction(NVT) != Expand && NVT != MVT::isVoid) {
6643 Lo = LegalizeOp(Lo);
6645 // Don't legalize the high part if it is expanded to a single node.
6646 Hi = LegalizeOp(Hi);
6649 // Remember in a map if the values will be reused later.
6650 bool isNew = ExpandedNodes.insert(std::make_pair(Op, std::make_pair(Lo, Hi)));
6651 assert(isNew && "Value already expanded?!?");
6654 /// SplitVectorOp - Given an operand of vector type, break it down into
6655 /// two smaller values, still of vector type.
6656 void SelectionDAGLegalize::SplitVectorOp(SDOperand Op, SDOperand &Lo,
6658 assert(MVT::isVector(Op.getValueType()) && "Cannot split non-vector type!");
6659 SDNode *Node = Op.Val;
6660 unsigned NumElements = MVT::getVectorNumElements(Op.getValueType());
6661 assert(NumElements > 1 && "Cannot split a single element vector!");
6663 MVT::ValueType NewEltVT = MVT::getVectorElementType(Op.getValueType());
6665 unsigned NewNumElts_Lo = 1 << Log2_32(NumElements-1);
6666 unsigned NewNumElts_Hi = NumElements - NewNumElts_Lo;
6668 MVT::ValueType NewVT_Lo = MVT::getVectorType(NewEltVT, NewNumElts_Lo);
6669 MVT::ValueType NewVT_Hi = MVT::getVectorType(NewEltVT, NewNumElts_Hi);
6671 // See if we already split it.
6672 std::map<SDOperand, std::pair<SDOperand, SDOperand> >::iterator I
6673 = SplitNodes.find(Op);
6674 if (I != SplitNodes.end()) {
6675 Lo = I->second.first;
6676 Hi = I->second.second;
6680 switch (Node->getOpcode()) {
6685 assert(0 && "Unhandled operation in SplitVectorOp!");
6687 Lo = DAG.getNode(ISD::UNDEF, NewVT_Lo);
6688 Hi = DAG.getNode(ISD::UNDEF, NewVT_Hi);
6690 case ISD::BUILD_PAIR:
6691 Lo = Node->getOperand(0);
6692 Hi = Node->getOperand(1);
6694 case ISD::INSERT_VECTOR_ELT: {
6695 SplitVectorOp(Node->getOperand(0), Lo, Hi);
6696 unsigned Index = cast<ConstantSDNode>(Node->getOperand(2))->getValue();
6697 SDOperand ScalarOp = Node->getOperand(1);
6698 if (Index < NewNumElts_Lo)
6699 Lo = DAG.getNode(ISD::INSERT_VECTOR_ELT, NewVT_Lo, Lo, ScalarOp,
6700 DAG.getConstant(Index, TLI.getPointerTy()));
6702 Hi = DAG.getNode(ISD::INSERT_VECTOR_ELT, NewVT_Hi, Hi, ScalarOp,
6703 DAG.getConstant(Index - NewNumElts_Lo,
6704 TLI.getPointerTy()));
6707 case ISD::VECTOR_SHUFFLE: {
6708 // Build the low part.
6709 SDOperand Mask = Node->getOperand(2);
6710 SmallVector<SDOperand, 8> Ops;
6711 MVT::ValueType PtrVT = TLI.getPointerTy();
6713 // Insert all of the elements from the input that are needed. We use
6714 // buildvector of extractelement here because the input vectors will have
6715 // to be legalized, so this makes the code simpler.
6716 for (unsigned i = 0; i != NewNumElts_Lo; ++i) {
6717 unsigned Idx = cast<ConstantSDNode>(Mask.getOperand(i))->getValue();
6718 SDOperand InVec = Node->getOperand(0);
6719 if (Idx >= NumElements) {
6720 InVec = Node->getOperand(1);
6723 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, NewEltVT, InVec,
6724 DAG.getConstant(Idx, PtrVT)));
6726 Lo = DAG.getNode(ISD::BUILD_VECTOR, NewVT_Lo, &Ops[0], Ops.size());
6729 for (unsigned i = NewNumElts_Lo; i != NumElements; ++i) {
6730 unsigned Idx = cast<ConstantSDNode>(Mask.getOperand(i))->getValue();
6731 SDOperand InVec = Node->getOperand(0);
6732 if (Idx >= NumElements) {
6733 InVec = Node->getOperand(1);
6736 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, NewEltVT, InVec,
6737 DAG.getConstant(Idx, PtrVT)));
6739 Hi = DAG.getNode(ISD::BUILD_VECTOR, NewVT_Lo, &Ops[0], Ops.size());
6742 case ISD::BUILD_VECTOR: {
6743 SmallVector<SDOperand, 8> LoOps(Node->op_begin(),
6744 Node->op_begin()+NewNumElts_Lo);
6745 Lo = DAG.getNode(ISD::BUILD_VECTOR, NewVT_Lo, &LoOps[0], LoOps.size());
6747 SmallVector<SDOperand, 8> HiOps(Node->op_begin()+NewNumElts_Lo,
6749 Hi = DAG.getNode(ISD::BUILD_VECTOR, NewVT_Hi, &HiOps[0], HiOps.size());
6752 case ISD::CONCAT_VECTORS: {
6753 // FIXME: Handle non-power-of-two vectors?
6754 unsigned NewNumSubvectors = Node->getNumOperands() / 2;
6755 if (NewNumSubvectors == 1) {
6756 Lo = Node->getOperand(0);
6757 Hi = Node->getOperand(1);
6759 SmallVector<SDOperand, 8> LoOps(Node->op_begin(),
6760 Node->op_begin()+NewNumSubvectors);
6761 Lo = DAG.getNode(ISD::CONCAT_VECTORS, NewVT_Lo, &LoOps[0], LoOps.size());
6763 SmallVector<SDOperand, 8> HiOps(Node->op_begin()+NewNumSubvectors,
6765 Hi = DAG.getNode(ISD::CONCAT_VECTORS, NewVT_Hi, &HiOps[0], HiOps.size());
6770 SDOperand Cond = Node->getOperand(0);
6772 SDOperand LL, LH, RL, RH;
6773 SplitVectorOp(Node->getOperand(1), LL, LH);
6774 SplitVectorOp(Node->getOperand(2), RL, RH);
6776 if (MVT::isVector(Cond.getValueType())) {
6777 // Handle a vector merge.
6779 SplitVectorOp(Cond, CL, CH);
6780 Lo = DAG.getNode(Node->getOpcode(), NewVT_Lo, CL, LL, RL);
6781 Hi = DAG.getNode(Node->getOpcode(), NewVT_Hi, CH, LH, RH);
6783 // Handle a simple select with vector operands.
6784 Lo = DAG.getNode(Node->getOpcode(), NewVT_Lo, Cond, LL, RL);
6785 Hi = DAG.getNode(Node->getOpcode(), NewVT_Hi, Cond, LH, RH);
6805 SDOperand LL, LH, RL, RH;
6806 SplitVectorOp(Node->getOperand(0), LL, LH);
6807 SplitVectorOp(Node->getOperand(1), RL, RH);
6809 Lo = DAG.getNode(Node->getOpcode(), NewVT_Lo, LL, RL);
6810 Hi = DAG.getNode(Node->getOpcode(), NewVT_Hi, LH, RH);
6815 SplitVectorOp(Node->getOperand(0), L, H);
6817 Lo = DAG.getNode(Node->getOpcode(), NewVT_Lo, L, Node->getOperand(1));
6818 Hi = DAG.getNode(Node->getOpcode(), NewVT_Hi, H, Node->getOperand(1));
6829 case ISD::FP_TO_SINT:
6830 case ISD::FP_TO_UINT:
6831 case ISD::SINT_TO_FP:
6832 case ISD::UINT_TO_FP: {
6834 SplitVectorOp(Node->getOperand(0), L, H);
6836 Lo = DAG.getNode(Node->getOpcode(), NewVT_Lo, L);
6837 Hi = DAG.getNode(Node->getOpcode(), NewVT_Hi, H);
6841 LoadSDNode *LD = cast<LoadSDNode>(Node);
6842 SDOperand Ch = LD->getChain();
6843 SDOperand Ptr = LD->getBasePtr();
6844 const Value *SV = LD->getSrcValue();
6845 int SVOffset = LD->getSrcValueOffset();
6846 unsigned Alignment = LD->getAlignment();
6847 bool isVolatile = LD->isVolatile();
6849 Lo = DAG.getLoad(NewVT_Lo, Ch, Ptr, SV, SVOffset, isVolatile, Alignment);
6850 unsigned IncrementSize = NewNumElts_Lo * MVT::getSizeInBits(NewEltVT)/8;
6851 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
6852 DAG.getIntPtrConstant(IncrementSize));
6853 SVOffset += IncrementSize;
6854 Alignment = MinAlign(Alignment, IncrementSize);
6855 Hi = DAG.getLoad(NewVT_Hi, Ch, Ptr, SV, SVOffset, isVolatile, Alignment);
6857 // Build a factor node to remember that this load is independent of the
6859 SDOperand TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
6862 // Remember that we legalized the chain.
6863 AddLegalizedOperand(Op.getValue(1), LegalizeOp(TF));
6866 case ISD::BIT_CONVERT: {
6867 // We know the result is a vector. The input may be either a vector or a
6869 SDOperand InOp = Node->getOperand(0);
6870 if (!MVT::isVector(InOp.getValueType()) ||
6871 MVT::getVectorNumElements(InOp.getValueType()) == 1) {
6872 // The input is a scalar or single-element vector.
6873 // Lower to a store/load so that it can be split.
6874 // FIXME: this could be improved probably.
6875 SDOperand Ptr = DAG.CreateStackTemporary(InOp.getValueType());
6876 FrameIndexSDNode *FI = cast<FrameIndexSDNode>(Ptr.Val);
6878 SDOperand St = DAG.getStore(DAG.getEntryNode(),
6880 PseudoSourceValue::getFixedStack(),
6882 InOp = DAG.getLoad(Op.getValueType(), St, Ptr,
6883 PseudoSourceValue::getFixedStack(),
6886 // Split the vector and convert each of the pieces now.
6887 SplitVectorOp(InOp, Lo, Hi);
6888 Lo = DAG.getNode(ISD::BIT_CONVERT, NewVT_Lo, Lo);
6889 Hi = DAG.getNode(ISD::BIT_CONVERT, NewVT_Hi, Hi);
6894 // Remember in a map if the values will be reused later.
6896 SplitNodes.insert(std::make_pair(Op, std::make_pair(Lo, Hi))).second;
6897 assert(isNew && "Value already split?!?");
6901 /// ScalarizeVectorOp - Given an operand of single-element vector type
6902 /// (e.g. v1f32), convert it into the equivalent operation that returns a
6903 /// scalar (e.g. f32) value.
6904 SDOperand SelectionDAGLegalize::ScalarizeVectorOp(SDOperand Op) {
6905 assert(MVT::isVector(Op.getValueType()) &&
6906 "Bad ScalarizeVectorOp invocation!");
6907 SDNode *Node = Op.Val;
6908 MVT::ValueType NewVT = MVT::getVectorElementType(Op.getValueType());
6909 assert(MVT::getVectorNumElements(Op.getValueType()) == 1);
6911 // See if we already scalarized it.
6912 std::map<SDOperand, SDOperand>::iterator I = ScalarizedNodes.find(Op);
6913 if (I != ScalarizedNodes.end()) return I->second;
6916 switch (Node->getOpcode()) {
6919 Node->dump(&DAG); cerr << "\n";
6921 assert(0 && "Unknown vector operation in ScalarizeVectorOp!");
6938 Result = DAG.getNode(Node->getOpcode(),
6940 ScalarizeVectorOp(Node->getOperand(0)),
6941 ScalarizeVectorOp(Node->getOperand(1)));
6948 Result = DAG.getNode(Node->getOpcode(),
6950 ScalarizeVectorOp(Node->getOperand(0)));
6953 Result = DAG.getNode(Node->getOpcode(),
6955 ScalarizeVectorOp(Node->getOperand(0)),
6956 Node->getOperand(1));
6959 LoadSDNode *LD = cast<LoadSDNode>(Node);
6960 SDOperand Ch = LegalizeOp(LD->getChain()); // Legalize the chain.
6961 SDOperand Ptr = LegalizeOp(LD->getBasePtr()); // Legalize the pointer.
6963 const Value *SV = LD->getSrcValue();
6964 int SVOffset = LD->getSrcValueOffset();
6965 Result = DAG.getLoad(NewVT, Ch, Ptr, SV, SVOffset,
6966 LD->isVolatile(), LD->getAlignment());
6968 // Remember that we legalized the chain.
6969 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
6972 case ISD::BUILD_VECTOR:
6973 Result = Node->getOperand(0);
6975 case ISD::INSERT_VECTOR_ELT:
6976 // Returning the inserted scalar element.
6977 Result = Node->getOperand(1);
6979 case ISD::CONCAT_VECTORS:
6980 assert(Node->getOperand(0).getValueType() == NewVT &&
6981 "Concat of non-legal vectors not yet supported!");
6982 Result = Node->getOperand(0);
6984 case ISD::VECTOR_SHUFFLE: {
6985 // Figure out if the scalar is the LHS or RHS and return it.
6986 SDOperand EltNum = Node->getOperand(2).getOperand(0);
6987 if (cast<ConstantSDNode>(EltNum)->getValue())
6988 Result = ScalarizeVectorOp(Node->getOperand(1));
6990 Result = ScalarizeVectorOp(Node->getOperand(0));
6993 case ISD::EXTRACT_SUBVECTOR:
6994 Result = Node->getOperand(0);
6995 assert(Result.getValueType() == NewVT);
6997 case ISD::BIT_CONVERT:
6998 Result = DAG.getNode(ISD::BIT_CONVERT, NewVT, Op.getOperand(0));
7001 Result = DAG.getNode(ISD::SELECT, NewVT, Op.getOperand(0),
7002 ScalarizeVectorOp(Op.getOperand(1)),
7003 ScalarizeVectorOp(Op.getOperand(2)));
7007 if (TLI.isTypeLegal(NewVT))
7008 Result = LegalizeOp(Result);
7009 bool isNew = ScalarizedNodes.insert(std::make_pair(Op, Result)).second;
7010 assert(isNew && "Value already scalarized?");
7015 // SelectionDAG::Legalize - This is the entry point for the file.
7017 void SelectionDAG::Legalize() {
7018 if (ViewLegalizeDAGs) viewGraph();
7020 /// run - This is the main entry point to this class.
7022 SelectionDAGLegalize(*this).LegalizeDAG();