1 //===-- LegalizeDAG.cpp - Implement SelectionDAG::Legalize ----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the SelectionDAG::Legalize method.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/Analysis/DebugInfo.h"
15 #include "llvm/CodeGen/Analysis.h"
16 #include "llvm/CodeGen/MachineFunction.h"
17 #include "llvm/CodeGen/MachineFrameInfo.h"
18 #include "llvm/CodeGen/MachineJumpTableInfo.h"
19 #include "llvm/CodeGen/MachineModuleInfo.h"
20 #include "llvm/CodeGen/PseudoSourceValue.h"
21 #include "llvm/CodeGen/SelectionDAG.h"
22 #include "llvm/Target/TargetFrameLowering.h"
23 #include "llvm/Target/TargetLowering.h"
24 #include "llvm/Target/TargetData.h"
25 #include "llvm/Target/TargetMachine.h"
26 #include "llvm/Target/TargetOptions.h"
27 #include "llvm/CallingConv.h"
28 #include "llvm/Constants.h"
29 #include "llvm/DerivedTypes.h"
30 #include "llvm/Function.h"
31 #include "llvm/GlobalVariable.h"
32 #include "llvm/LLVMContext.h"
33 #include "llvm/Support/CommandLine.h"
34 #include "llvm/Support/Debug.h"
35 #include "llvm/Support/ErrorHandling.h"
36 #include "llvm/Support/MathExtras.h"
37 #include "llvm/Support/raw_ostream.h"
38 #include "llvm/ADT/DenseMap.h"
39 #include "llvm/ADT/SmallVector.h"
40 #include "llvm/ADT/SmallPtrSet.h"
43 //===----------------------------------------------------------------------===//
44 /// SelectionDAGLegalize - This takes an arbitrary SelectionDAG as input and
45 /// hacks on it until the target machine can handle it. This involves
46 /// eliminating value sizes the machine cannot handle (promoting small sizes to
47 /// large sizes or splitting up large values into small values) as well as
48 /// eliminating operations the machine cannot handle.
50 /// This code also does a small amount of optimization and recognition of idioms
51 /// as part of its processing. For example, if a target does not support a
52 /// 'setcc' instruction efficiently, but does support 'brcc' instruction, this
53 /// will attempt merge setcc and brc instructions into brcc's.
56 class SelectionDAGLegalize {
57 const TargetMachine &TM;
58 const TargetLowering &TLI;
60 CodeGenOpt::Level OptLevel;
62 // Libcall insertion helpers.
64 /// LastCALLSEQ - This keeps track of the CALLSEQ_END node that has been
65 /// legalized. We use this to ensure that calls are properly serialized
66 /// against each other, including inserted libcalls.
67 SmallVector<SDValue, 8> LastCALLSEQ;
70 Legal, // The target natively supports this operation.
71 Promote, // This operation should be executed in a larger type.
72 Expand // Try to expand this to other ops, otherwise use a libcall.
75 /// ValueTypeActions - This is a bitvector that contains two bits for each
76 /// value type, where the two bits correspond to the LegalizeAction enum.
77 /// This can be queried with "getTypeAction(VT)".
78 TargetLowering::ValueTypeActionImpl ValueTypeActions;
80 /// LegalizedNodes - For nodes that are of legal width, and that have more
81 /// than one use, this map indicates what regularized operand to use. This
82 /// allows us to avoid legalizing the same thing more than once.
83 DenseMap<SDValue, SDValue> LegalizedNodes;
85 void AddLegalizedOperand(SDValue From, SDValue To) {
86 LegalizedNodes.insert(std::make_pair(From, To));
87 // If someone requests legalization of the new node, return itself.
89 LegalizedNodes.insert(std::make_pair(To, To));
91 // Transfer SDDbgValues.
92 DAG.TransferDbgValues(From, To);
96 SelectionDAGLegalize(SelectionDAG &DAG, CodeGenOpt::Level ol);
98 /// getTypeAction - Return how we should legalize values of this type, either
99 /// it is already legal or we need to expand it into multiple registers of
100 /// smaller integer type, or we need to promote it to a larger type.
101 LegalizeAction getTypeAction(EVT VT) const {
102 return (LegalizeAction)ValueTypeActions.getTypeAction(VT);
105 /// isTypeLegal - Return true if this type is legal on this target.
107 bool isTypeLegal(EVT VT) const {
108 return getTypeAction(VT) == Legal;
114 /// LegalizeOp - We know that the specified value has a legal type.
115 /// Recursively ensure that the operands have legal types, then return the
117 SDValue LegalizeOp(SDValue O);
119 SDValue OptimizeFloatStore(StoreSDNode *ST);
121 /// PerformInsertVectorEltInMemory - Some target cannot handle a variable
122 /// insertion index for the INSERT_VECTOR_ELT instruction. In this case, it
123 /// is necessary to spill the vector being inserted into to memory, perform
124 /// the insert there, and then read the result back.
125 SDValue PerformInsertVectorEltInMemory(SDValue Vec, SDValue Val,
126 SDValue Idx, DebugLoc dl);
127 SDValue ExpandINSERT_VECTOR_ELT(SDValue Vec, SDValue Val,
128 SDValue Idx, DebugLoc dl);
130 /// ShuffleWithNarrowerEltType - Return a vector shuffle operation which
131 /// performs the same shuffe in terms of order or result bytes, but on a type
132 /// whose vector element type is narrower than the original shuffle type.
133 /// e.g. <v4i32> <0, 1, 0, 1> -> v8i16 <0, 1, 2, 3, 0, 1, 2, 3>
134 SDValue ShuffleWithNarrowerEltType(EVT NVT, EVT VT, DebugLoc dl,
135 SDValue N1, SDValue N2,
136 SmallVectorImpl<int> &Mask) const;
138 bool LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest,
139 SmallPtrSet<SDNode*, 32> &NodesLeadingTo);
141 void LegalizeSetCCCondCode(EVT VT, SDValue &LHS, SDValue &RHS, SDValue &CC,
144 SDValue ExpandLibCall(RTLIB::Libcall LC, SDNode *Node, bool isSigned);
145 SDValue ExpandLibCall(RTLIB::Libcall LC, EVT RetVT, const SDValue *Ops,
146 unsigned NumOps, bool isSigned, DebugLoc dl);
148 std::pair<SDValue, SDValue> ExpandChainLibCall(RTLIB::Libcall LC,
149 SDNode *Node, bool isSigned);
150 SDValue ExpandFPLibCall(SDNode *Node, RTLIB::Libcall Call_F32,
151 RTLIB::Libcall Call_F64, RTLIB::Libcall Call_F80,
152 RTLIB::Libcall Call_PPCF128);
153 SDValue ExpandIntLibCall(SDNode *Node, bool isSigned,
154 RTLIB::Libcall Call_I8,
155 RTLIB::Libcall Call_I16,
156 RTLIB::Libcall Call_I32,
157 RTLIB::Libcall Call_I64,
158 RTLIB::Libcall Call_I128);
159 void ExpandDivRemLibCall(SDNode *Node, SmallVectorImpl<SDValue> &Results);
161 SDValue EmitStackConvert(SDValue SrcOp, EVT SlotVT, EVT DestVT, DebugLoc dl);
162 SDValue ExpandBUILD_VECTOR(SDNode *Node);
163 SDValue ExpandSCALAR_TO_VECTOR(SDNode *Node);
164 void ExpandDYNAMIC_STACKALLOC(SDNode *Node,
165 SmallVectorImpl<SDValue> &Results);
166 SDValue ExpandFCOPYSIGN(SDNode *Node);
167 SDValue ExpandLegalINT_TO_FP(bool isSigned, SDValue LegalOp, EVT DestVT,
169 SDValue PromoteLegalINT_TO_FP(SDValue LegalOp, EVT DestVT, bool isSigned,
171 SDValue PromoteLegalFP_TO_INT(SDValue LegalOp, EVT DestVT, bool isSigned,
174 SDValue ExpandBSWAP(SDValue Op, DebugLoc dl);
175 SDValue ExpandBitCount(unsigned Opc, SDValue Op, DebugLoc dl);
177 SDValue ExpandExtractFromVectorThroughStack(SDValue Op);
178 SDValue ExpandInsertToVectorThroughStack(SDValue Op);
179 SDValue ExpandVectorBuildThroughStack(SDNode* Node);
181 std::pair<SDValue, SDValue> ExpandAtomic(SDNode *Node);
183 void ExpandNode(SDNode *Node, SmallVectorImpl<SDValue> &Results);
184 void PromoteNode(SDNode *Node, SmallVectorImpl<SDValue> &Results);
186 SDValue getLastCALLSEQ() { return LastCALLSEQ.back(); }
187 void setLastCALLSEQ(const SDValue s) { LastCALLSEQ.back() = s; }
188 void pushLastCALLSEQ(SDValue s) {
189 LastCALLSEQ.push_back(s);
191 void popLastCALLSEQ() {
192 LastCALLSEQ.pop_back();
197 /// ShuffleWithNarrowerEltType - Return a vector shuffle operation which
198 /// performs the same shuffe in terms of order or result bytes, but on a type
199 /// whose vector element type is narrower than the original shuffle type.
200 /// e.g. <v4i32> <0, 1, 0, 1> -> v8i16 <0, 1, 2, 3, 0, 1, 2, 3>
202 SelectionDAGLegalize::ShuffleWithNarrowerEltType(EVT NVT, EVT VT, DebugLoc dl,
203 SDValue N1, SDValue N2,
204 SmallVectorImpl<int> &Mask) const {
205 unsigned NumMaskElts = VT.getVectorNumElements();
206 unsigned NumDestElts = NVT.getVectorNumElements();
207 unsigned NumEltsGrowth = NumDestElts / NumMaskElts;
209 assert(NumEltsGrowth && "Cannot promote to vector type with fewer elts!");
211 if (NumEltsGrowth == 1)
212 return DAG.getVectorShuffle(NVT, dl, N1, N2, &Mask[0]);
214 SmallVector<int, 8> NewMask;
215 for (unsigned i = 0; i != NumMaskElts; ++i) {
217 for (unsigned j = 0; j != NumEltsGrowth; ++j) {
219 NewMask.push_back(-1);
221 NewMask.push_back(Idx * NumEltsGrowth + j);
224 assert(NewMask.size() == NumDestElts && "Non-integer NumEltsGrowth?");
225 assert(TLI.isShuffleMaskLegal(NewMask, NVT) && "Shuffle not legal?");
226 return DAG.getVectorShuffle(NVT, dl, N1, N2, &NewMask[0]);
229 SelectionDAGLegalize::SelectionDAGLegalize(SelectionDAG &dag,
230 CodeGenOpt::Level ol)
231 : TM(dag.getTarget()), TLI(dag.getTargetLoweringInfo()),
232 DAG(dag), OptLevel(ol),
233 ValueTypeActions(TLI.getValueTypeActions()) {
234 assert(MVT::LAST_VALUETYPE <= MVT::MAX_ALLOWED_VALUETYPE &&
235 "Too many value types for ValueTypeActions to hold!");
238 void SelectionDAGLegalize::LegalizeDAG() {
239 pushLastCALLSEQ(DAG.getEntryNode());
241 // The legalize process is inherently a bottom-up recursive process (users
242 // legalize their uses before themselves). Given infinite stack space, we
243 // could just start legalizing on the root and traverse the whole graph. In
244 // practice however, this causes us to run out of stack space on large basic
245 // blocks. To avoid this problem, compute an ordering of the nodes where each
246 // node is only legalized after all of its operands are legalized.
247 DAG.AssignTopologicalOrder();
248 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(),
249 E = prior(DAG.allnodes_end()); I != llvm::next(E); ++I)
250 LegalizeOp(SDValue(I, 0));
252 // Finally, it's possible the root changed. Get the new root.
253 SDValue OldRoot = DAG.getRoot();
254 assert(LegalizedNodes.count(OldRoot) && "Root didn't get legalized?");
255 DAG.setRoot(LegalizedNodes[OldRoot]);
257 LegalizedNodes.clear();
259 // Remove dead nodes now.
260 DAG.RemoveDeadNodes();
264 /// FindCallEndFromCallStart - Given a chained node that is part of a call
265 /// sequence, find the CALLSEQ_END node that terminates the call sequence.
266 static SDNode *FindCallEndFromCallStart(SDNode *Node, int depth = 0) {
267 int next_depth = depth;
268 if (Node->getOpcode() == ISD::CALLSEQ_START)
269 next_depth = depth + 1;
270 if (Node->getOpcode() == ISD::CALLSEQ_END) {
271 assert(depth > 0 && "negative depth!");
275 next_depth = depth - 1;
277 if (Node->use_empty())
278 return 0; // No CallSeqEnd
280 // The chain is usually at the end.
281 SDValue TheChain(Node, Node->getNumValues()-1);
282 if (TheChain.getValueType() != MVT::Other) {
283 // Sometimes it's at the beginning.
284 TheChain = SDValue(Node, 0);
285 if (TheChain.getValueType() != MVT::Other) {
286 // Otherwise, hunt for it.
287 for (unsigned i = 1, e = Node->getNumValues(); i != e; ++i)
288 if (Node->getValueType(i) == MVT::Other) {
289 TheChain = SDValue(Node, i);
293 // Otherwise, we walked into a node without a chain.
294 if (TheChain.getValueType() != MVT::Other)
299 for (SDNode::use_iterator UI = Node->use_begin(),
300 E = Node->use_end(); UI != E; ++UI) {
302 // Make sure to only follow users of our token chain.
304 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i)
305 if (User->getOperand(i) == TheChain)
306 if (SDNode *Result = FindCallEndFromCallStart(User, next_depth))
312 /// FindCallStartFromCallEnd - Given a chained node that is part of a call
313 /// sequence, find the CALLSEQ_START node that initiates the call sequence.
314 static SDNode *FindCallStartFromCallEnd(SDNode *Node) {
316 assert(Node && "Didn't find callseq_start for a call??");
317 while (Node->getOpcode() != ISD::CALLSEQ_START || nested) {
318 Node = Node->getOperand(0).getNode();
319 assert(Node->getOperand(0).getValueType() == MVT::Other &&
320 "Node doesn't have a token chain argument!");
321 switch (Node->getOpcode()) {
324 case ISD::CALLSEQ_START:
327 Node = Node->getOperand(0).getNode();
330 case ISD::CALLSEQ_END:
335 return (Node->getOpcode() == ISD::CALLSEQ_START) ? Node : 0;
338 /// LegalizeAllNodesNotLeadingTo - Recursively walk the uses of N, looking to
339 /// see if any uses can reach Dest. If no dest operands can get to dest,
340 /// legalize them, legalize ourself, and return false, otherwise, return true.
342 /// Keep track of the nodes we fine that actually do lead to Dest in
343 /// NodesLeadingTo. This avoids retraversing them exponential number of times.
345 bool SelectionDAGLegalize::LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest,
346 SmallPtrSet<SDNode*, 32> &NodesLeadingTo) {
347 if (N == Dest) return true; // N certainly leads to Dest :)
349 // If we've already processed this node and it does lead to Dest, there is no
350 // need to reprocess it.
351 if (NodesLeadingTo.count(N)) return true;
353 // If the first result of this node has been already legalized, then it cannot
355 if (LegalizedNodes.count(SDValue(N, 0))) return false;
357 // Okay, this node has not already been legalized. Check and legalize all
358 // operands. If none lead to Dest, then we can legalize this node.
359 bool OperandsLeadToDest = false;
360 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
361 OperandsLeadToDest |= // If an operand leads to Dest, so do we.
362 LegalizeAllNodesNotLeadingTo(N->getOperand(i).getNode(), Dest,
365 if (OperandsLeadToDest) {
366 NodesLeadingTo.insert(N);
370 // Okay, this node looks safe, legalize it and return false.
371 LegalizeOp(SDValue(N, 0));
375 /// ExpandConstantFP - Expands the ConstantFP node to an integer constant or
376 /// a load from the constant pool.
377 static SDValue ExpandConstantFP(ConstantFPSDNode *CFP, bool UseCP,
378 SelectionDAG &DAG, const TargetLowering &TLI) {
380 DebugLoc dl = CFP->getDebugLoc();
382 // If a FP immediate is precise when represented as a float and if the
383 // target can do an extending load from float to double, we put it into
384 // the constant pool as a float, even if it's is statically typed as a
385 // double. This shrinks FP constants and canonicalizes them for targets where
386 // an FP extending load is the same cost as a normal load (such as on the x87
387 // fp stack or PPC FP unit).
388 EVT VT = CFP->getValueType(0);
389 ConstantFP *LLVMC = const_cast<ConstantFP*>(CFP->getConstantFPValue());
391 assert((VT == MVT::f64 || VT == MVT::f32) && "Invalid type expansion");
392 return DAG.getConstant(LLVMC->getValueAPF().bitcastToAPInt(),
393 (VT == MVT::f64) ? MVT::i64 : MVT::i32);
398 while (SVT != MVT::f32) {
399 SVT = (MVT::SimpleValueType)(SVT.getSimpleVT().SimpleTy - 1);
400 if (ConstantFPSDNode::isValueValidForType(SVT, CFP->getValueAPF()) &&
401 // Only do this if the target has a native EXTLOAD instruction from
403 TLI.isLoadExtLegal(ISD::EXTLOAD, SVT) &&
404 TLI.ShouldShrinkFPConstant(OrigVT)) {
405 const Type *SType = SVT.getTypeForEVT(*DAG.getContext());
406 LLVMC = cast<ConstantFP>(ConstantExpr::getFPTrunc(LLVMC, SType));
412 SDValue CPIdx = DAG.getConstantPool(LLVMC, TLI.getPointerTy());
413 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
415 return DAG.getExtLoad(ISD::EXTLOAD, dl, OrigVT,
417 CPIdx, MachinePointerInfo::getConstantPool(),
418 VT, false, false, Alignment);
419 return DAG.getLoad(OrigVT, dl, DAG.getEntryNode(), CPIdx,
420 MachinePointerInfo::getConstantPool(), false, false,
424 /// ExpandUnalignedStore - Expands an unaligned store to 2 half-size stores.
426 SDValue ExpandUnalignedStore(StoreSDNode *ST, SelectionDAG &DAG,
427 const TargetLowering &TLI) {
428 SDValue Chain = ST->getChain();
429 SDValue Ptr = ST->getBasePtr();
430 SDValue Val = ST->getValue();
431 EVT VT = Val.getValueType();
432 int Alignment = ST->getAlignment();
433 DebugLoc dl = ST->getDebugLoc();
434 if (ST->getMemoryVT().isFloatingPoint() ||
435 ST->getMemoryVT().isVector()) {
436 EVT intVT = EVT::getIntegerVT(*DAG.getContext(), VT.getSizeInBits());
437 if (TLI.isTypeLegal(intVT)) {
438 // Expand to a bitconvert of the value to the integer type of the
439 // same size, then a (misaligned) int store.
440 // FIXME: Does not handle truncating floating point stores!
441 SDValue Result = DAG.getNode(ISD::BITCAST, dl, intVT, Val);
442 return DAG.getStore(Chain, dl, Result, Ptr, ST->getPointerInfo(),
443 ST->isVolatile(), ST->isNonTemporal(), Alignment);
445 // Do a (aligned) store to a stack slot, then copy from the stack slot
446 // to the final destination using (unaligned) integer loads and stores.
447 EVT StoredVT = ST->getMemoryVT();
449 TLI.getRegisterType(*DAG.getContext(),
450 EVT::getIntegerVT(*DAG.getContext(),
451 StoredVT.getSizeInBits()));
452 unsigned StoredBytes = StoredVT.getSizeInBits() / 8;
453 unsigned RegBytes = RegVT.getSizeInBits() / 8;
454 unsigned NumRegs = (StoredBytes + RegBytes - 1) / RegBytes;
456 // Make sure the stack slot is also aligned for the register type.
457 SDValue StackPtr = DAG.CreateStackTemporary(StoredVT, RegVT);
459 // Perform the original store, only redirected to the stack slot.
460 SDValue Store = DAG.getTruncStore(Chain, dl,
461 Val, StackPtr, MachinePointerInfo(),
462 StoredVT, false, false, 0);
463 SDValue Increment = DAG.getConstant(RegBytes, TLI.getPointerTy());
464 SmallVector<SDValue, 8> Stores;
467 // Do all but one copies using the full register width.
468 for (unsigned i = 1; i < NumRegs; i++) {
469 // Load one integer register's worth from the stack slot.
470 SDValue Load = DAG.getLoad(RegVT, dl, Store, StackPtr,
471 MachinePointerInfo(),
473 // Store it to the final location. Remember the store.
474 Stores.push_back(DAG.getStore(Load.getValue(1), dl, Load, Ptr,
475 ST->getPointerInfo().getWithOffset(Offset),
476 ST->isVolatile(), ST->isNonTemporal(),
477 MinAlign(ST->getAlignment(), Offset)));
478 // Increment the pointers.
480 StackPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr,
482 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
485 // The last store may be partial. Do a truncating store. On big-endian
486 // machines this requires an extending load from the stack slot to ensure
487 // that the bits are in the right place.
488 EVT MemVT = EVT::getIntegerVT(*DAG.getContext(),
489 8 * (StoredBytes - Offset));
491 // Load from the stack slot.
492 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, RegVT, Store, StackPtr,
493 MachinePointerInfo(),
494 MemVT, false, false, 0);
496 Stores.push_back(DAG.getTruncStore(Load.getValue(1), dl, Load, Ptr,
498 .getWithOffset(Offset),
499 MemVT, ST->isVolatile(),
501 MinAlign(ST->getAlignment(), Offset)));
502 // The order of the stores doesn't matter - say it with a TokenFactor.
503 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Stores[0],
507 assert(ST->getMemoryVT().isInteger() &&
508 !ST->getMemoryVT().isVector() &&
509 "Unaligned store of unknown type.");
510 // Get the half-size VT
511 EVT NewStoredVT = ST->getMemoryVT().getHalfSizedIntegerVT(*DAG.getContext());
512 int NumBits = NewStoredVT.getSizeInBits();
513 int IncrementSize = NumBits / 8;
515 // Divide the stored value in two parts.
516 SDValue ShiftAmount = DAG.getConstant(NumBits,
517 TLI.getShiftAmountTy(Val.getValueType()));
519 SDValue Hi = DAG.getNode(ISD::SRL, dl, VT, Val, ShiftAmount);
521 // Store the two parts
522 SDValue Store1, Store2;
523 Store1 = DAG.getTruncStore(Chain, dl, TLI.isLittleEndian()?Lo:Hi, Ptr,
524 ST->getPointerInfo(), NewStoredVT,
525 ST->isVolatile(), ST->isNonTemporal(), Alignment);
526 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
527 DAG.getConstant(IncrementSize, TLI.getPointerTy()));
528 Alignment = MinAlign(Alignment, IncrementSize);
529 Store2 = DAG.getTruncStore(Chain, dl, TLI.isLittleEndian()?Hi:Lo, Ptr,
530 ST->getPointerInfo().getWithOffset(IncrementSize),
531 NewStoredVT, ST->isVolatile(), ST->isNonTemporal(),
534 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Store1, Store2);
537 /// ExpandUnalignedLoad - Expands an unaligned load to 2 half-size loads.
539 SDValue ExpandUnalignedLoad(LoadSDNode *LD, SelectionDAG &DAG,
540 const TargetLowering &TLI) {
541 SDValue Chain = LD->getChain();
542 SDValue Ptr = LD->getBasePtr();
543 EVT VT = LD->getValueType(0);
544 EVT LoadedVT = LD->getMemoryVT();
545 DebugLoc dl = LD->getDebugLoc();
546 if (VT.isFloatingPoint() || VT.isVector()) {
547 EVT intVT = EVT::getIntegerVT(*DAG.getContext(), LoadedVT.getSizeInBits());
548 if (TLI.isTypeLegal(intVT)) {
549 // Expand to a (misaligned) integer load of the same size,
550 // then bitconvert to floating point or vector.
551 SDValue newLoad = DAG.getLoad(intVT, dl, Chain, Ptr, LD->getPointerInfo(),
553 LD->isNonTemporal(), LD->getAlignment());
554 SDValue Result = DAG.getNode(ISD::BITCAST, dl, LoadedVT, newLoad);
555 if (VT.isFloatingPoint() && LoadedVT != VT)
556 Result = DAG.getNode(ISD::FP_EXTEND, dl, VT, Result);
558 SDValue Ops[] = { Result, Chain };
559 return DAG.getMergeValues(Ops, 2, dl);
562 // Copy the value to a (aligned) stack slot using (unaligned) integer
563 // loads and stores, then do a (aligned) load from the stack slot.
564 EVT RegVT = TLI.getRegisterType(*DAG.getContext(), intVT);
565 unsigned LoadedBytes = LoadedVT.getSizeInBits() / 8;
566 unsigned RegBytes = RegVT.getSizeInBits() / 8;
567 unsigned NumRegs = (LoadedBytes + RegBytes - 1) / RegBytes;
569 // Make sure the stack slot is also aligned for the register type.
570 SDValue StackBase = DAG.CreateStackTemporary(LoadedVT, RegVT);
572 SDValue Increment = DAG.getConstant(RegBytes, TLI.getPointerTy());
573 SmallVector<SDValue, 8> Stores;
574 SDValue StackPtr = StackBase;
577 // Do all but one copies using the full register width.
578 for (unsigned i = 1; i < NumRegs; i++) {
579 // Load one integer register's worth from the original location.
580 SDValue Load = DAG.getLoad(RegVT, dl, Chain, Ptr,
581 LD->getPointerInfo().getWithOffset(Offset),
582 LD->isVolatile(), LD->isNonTemporal(),
583 MinAlign(LD->getAlignment(), Offset));
584 // Follow the load with a store to the stack slot. Remember the store.
585 Stores.push_back(DAG.getStore(Load.getValue(1), dl, Load, StackPtr,
586 MachinePointerInfo(), false, false, 0));
587 // Increment the pointers.
589 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
590 StackPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr,
594 // The last copy may be partial. Do an extending load.
595 EVT MemVT = EVT::getIntegerVT(*DAG.getContext(),
596 8 * (LoadedBytes - Offset));
597 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, RegVT, Chain, Ptr,
598 LD->getPointerInfo().getWithOffset(Offset),
599 MemVT, LD->isVolatile(),
601 MinAlign(LD->getAlignment(), Offset));
602 // Follow the load with a store to the stack slot. Remember the store.
603 // On big-endian machines this requires a truncating store to ensure
604 // that the bits end up in the right place.
605 Stores.push_back(DAG.getTruncStore(Load.getValue(1), dl, Load, StackPtr,
606 MachinePointerInfo(), MemVT,
609 // The order of the stores doesn't matter - say it with a TokenFactor.
610 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Stores[0],
613 // Finally, perform the original load only redirected to the stack slot.
614 Load = DAG.getExtLoad(LD->getExtensionType(), dl, VT, TF, StackBase,
615 MachinePointerInfo(), LoadedVT, false, false, 0);
617 // Callers expect a MERGE_VALUES node.
618 SDValue Ops[] = { Load, TF };
619 return DAG.getMergeValues(Ops, 2, dl);
621 assert(LoadedVT.isInteger() && !LoadedVT.isVector() &&
622 "Unaligned load of unsupported type.");
624 // Compute the new VT that is half the size of the old one. This is an
626 unsigned NumBits = LoadedVT.getSizeInBits();
628 NewLoadedVT = EVT::getIntegerVT(*DAG.getContext(), NumBits/2);
631 unsigned Alignment = LD->getAlignment();
632 unsigned IncrementSize = NumBits / 8;
633 ISD::LoadExtType HiExtType = LD->getExtensionType();
635 // If the original load is NON_EXTLOAD, the hi part load must be ZEXTLOAD.
636 if (HiExtType == ISD::NON_EXTLOAD)
637 HiExtType = ISD::ZEXTLOAD;
639 // Load the value in two parts
641 if (TLI.isLittleEndian()) {
642 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, VT, Chain, Ptr, LD->getPointerInfo(),
643 NewLoadedVT, LD->isVolatile(),
644 LD->isNonTemporal(), Alignment);
645 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
646 DAG.getConstant(IncrementSize, TLI.getPointerTy()));
647 Hi = DAG.getExtLoad(HiExtType, dl, VT, Chain, Ptr,
648 LD->getPointerInfo().getWithOffset(IncrementSize),
649 NewLoadedVT, LD->isVolatile(),
650 LD->isNonTemporal(), MinAlign(Alignment,IncrementSize));
652 Hi = DAG.getExtLoad(HiExtType, dl, VT, Chain, Ptr, LD->getPointerInfo(),
653 NewLoadedVT, LD->isVolatile(),
654 LD->isNonTemporal(), Alignment);
655 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
656 DAG.getConstant(IncrementSize, TLI.getPointerTy()));
657 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, VT, Chain, Ptr,
658 LD->getPointerInfo().getWithOffset(IncrementSize),
659 NewLoadedVT, LD->isVolatile(),
660 LD->isNonTemporal(), MinAlign(Alignment,IncrementSize));
663 // aggregate the two parts
664 SDValue ShiftAmount = DAG.getConstant(NumBits,
665 TLI.getShiftAmountTy(Hi.getValueType()));
666 SDValue Result = DAG.getNode(ISD::SHL, dl, VT, Hi, ShiftAmount);
667 Result = DAG.getNode(ISD::OR, dl, VT, Result, Lo);
669 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
672 SDValue Ops[] = { Result, TF };
673 return DAG.getMergeValues(Ops, 2, dl);
676 /// PerformInsertVectorEltInMemory - Some target cannot handle a variable
677 /// insertion index for the INSERT_VECTOR_ELT instruction. In this case, it
678 /// is necessary to spill the vector being inserted into to memory, perform
679 /// the insert there, and then read the result back.
680 SDValue SelectionDAGLegalize::
681 PerformInsertVectorEltInMemory(SDValue Vec, SDValue Val, SDValue Idx,
687 // If the target doesn't support this, we have to spill the input vector
688 // to a temporary stack slot, update the element, then reload it. This is
689 // badness. We could also load the value into a vector register (either
690 // with a "move to register" or "extload into register" instruction, then
691 // permute it into place, if the idx is a constant and if the idx is
692 // supported by the target.
693 EVT VT = Tmp1.getValueType();
694 EVT EltVT = VT.getVectorElementType();
695 EVT IdxVT = Tmp3.getValueType();
696 EVT PtrVT = TLI.getPointerTy();
697 SDValue StackPtr = DAG.CreateStackTemporary(VT);
699 int SPFI = cast<FrameIndexSDNode>(StackPtr.getNode())->getIndex();
702 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, Tmp1, StackPtr,
703 MachinePointerInfo::getFixedStack(SPFI),
706 // Truncate or zero extend offset to target pointer type.
707 unsigned CastOpc = IdxVT.bitsGT(PtrVT) ? ISD::TRUNCATE : ISD::ZERO_EXTEND;
708 Tmp3 = DAG.getNode(CastOpc, dl, PtrVT, Tmp3);
709 // Add the offset to the index.
710 unsigned EltSize = EltVT.getSizeInBits()/8;
711 Tmp3 = DAG.getNode(ISD::MUL, dl, IdxVT, Tmp3,DAG.getConstant(EltSize, IdxVT));
712 SDValue StackPtr2 = DAG.getNode(ISD::ADD, dl, IdxVT, Tmp3, StackPtr);
713 // Store the scalar value.
714 Ch = DAG.getTruncStore(Ch, dl, Tmp2, StackPtr2, MachinePointerInfo(), EltVT,
716 // Load the updated vector.
717 return DAG.getLoad(VT, dl, Ch, StackPtr,
718 MachinePointerInfo::getFixedStack(SPFI), false, false, 0);
722 SDValue SelectionDAGLegalize::
723 ExpandINSERT_VECTOR_ELT(SDValue Vec, SDValue Val, SDValue Idx, DebugLoc dl) {
724 if (ConstantSDNode *InsertPos = dyn_cast<ConstantSDNode>(Idx)) {
725 // SCALAR_TO_VECTOR requires that the type of the value being inserted
726 // match the element type of the vector being created, except for
727 // integers in which case the inserted value can be over width.
728 EVT EltVT = Vec.getValueType().getVectorElementType();
729 if (Val.getValueType() == EltVT ||
730 (EltVT.isInteger() && Val.getValueType().bitsGE(EltVT))) {
731 SDValue ScVec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
732 Vec.getValueType(), Val);
734 unsigned NumElts = Vec.getValueType().getVectorNumElements();
735 // We generate a shuffle of InVec and ScVec, so the shuffle mask
736 // should be 0,1,2,3,4,5... with the appropriate element replaced with
738 SmallVector<int, 8> ShufOps;
739 for (unsigned i = 0; i != NumElts; ++i)
740 ShufOps.push_back(i != InsertPos->getZExtValue() ? i : NumElts);
742 return DAG.getVectorShuffle(Vec.getValueType(), dl, Vec, ScVec,
746 return PerformInsertVectorEltInMemory(Vec, Val, Idx, dl);
749 SDValue SelectionDAGLegalize::OptimizeFloatStore(StoreSDNode* ST) {
750 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr'
751 // FIXME: We shouldn't do this for TargetConstantFP's.
752 // FIXME: move this to the DAG Combiner! Note that we can't regress due
753 // to phase ordering between legalized code and the dag combiner. This
754 // probably means that we need to integrate dag combiner and legalizer
756 // We generally can't do this one for long doubles.
757 SDValue Tmp1 = ST->getChain();
758 SDValue Tmp2 = ST->getBasePtr();
760 unsigned Alignment = ST->getAlignment();
761 bool isVolatile = ST->isVolatile();
762 bool isNonTemporal = ST->isNonTemporal();
763 DebugLoc dl = ST->getDebugLoc();
764 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(ST->getValue())) {
765 if (CFP->getValueType(0) == MVT::f32 &&
766 getTypeAction(MVT::i32) == Legal) {
767 Tmp3 = DAG.getConstant(CFP->getValueAPF().
768 bitcastToAPInt().zextOrTrunc(32),
770 return DAG.getStore(Tmp1, dl, Tmp3, Tmp2, ST->getPointerInfo(),
771 isVolatile, isNonTemporal, Alignment);
774 if (CFP->getValueType(0) == MVT::f64) {
775 // If this target supports 64-bit registers, do a single 64-bit store.
776 if (getTypeAction(MVT::i64) == Legal) {
777 Tmp3 = DAG.getConstant(CFP->getValueAPF().bitcastToAPInt().
778 zextOrTrunc(64), MVT::i64);
779 return DAG.getStore(Tmp1, dl, Tmp3, Tmp2, ST->getPointerInfo(),
780 isVolatile, isNonTemporal, Alignment);
783 if (getTypeAction(MVT::i32) == Legal && !ST->isVolatile()) {
784 // Otherwise, if the target supports 32-bit registers, use 2 32-bit
785 // stores. If the target supports neither 32- nor 64-bits, this
786 // xform is certainly not worth it.
787 const APInt &IntVal =CFP->getValueAPF().bitcastToAPInt();
788 SDValue Lo = DAG.getConstant(IntVal.trunc(32), MVT::i32);
789 SDValue Hi = DAG.getConstant(IntVal.lshr(32).trunc(32), MVT::i32);
790 if (TLI.isBigEndian()) std::swap(Lo, Hi);
792 Lo = DAG.getStore(Tmp1, dl, Lo, Tmp2, ST->getPointerInfo(), isVolatile,
793 isNonTemporal, Alignment);
794 Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2,
795 DAG.getIntPtrConstant(4));
796 Hi = DAG.getStore(Tmp1, dl, Hi, Tmp2,
797 ST->getPointerInfo().getWithOffset(4),
798 isVolatile, isNonTemporal, MinAlign(Alignment, 4U));
800 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi);
804 return SDValue(0, 0);
807 /// LegalizeOp - We know that the specified value has a legal type, and
808 /// that its operands are legal. Now ensure that the operation itself
809 /// is legal, recursively ensuring that the operands' operations remain
811 SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
812 if (Op.getOpcode() == ISD::TargetConstant) // Allow illegal target nodes.
815 SDNode *Node = Op.getNode();
816 DebugLoc dl = Node->getDebugLoc();
818 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
819 assert(getTypeAction(Node->getValueType(i)) == Legal &&
820 "Unexpected illegal type!");
822 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
823 assert((isTypeLegal(Node->getOperand(i).getValueType()) ||
824 Node->getOperand(i).getOpcode() == ISD::TargetConstant) &&
825 "Unexpected illegal type!");
827 // Note that LegalizeOp may be reentered even from single-use nodes, which
828 // means that we always must cache transformed nodes.
829 DenseMap<SDValue, SDValue>::iterator I = LegalizedNodes.find(Op);
830 if (I != LegalizedNodes.end()) return I->second;
832 SDValue Tmp1, Tmp2, Tmp3, Tmp4;
834 bool isCustom = false;
836 // Figure out the correct action; the way to query this varies by opcode
837 TargetLowering::LegalizeAction Action = TargetLowering::Legal;
838 bool SimpleFinishLegalizing = true;
839 switch (Node->getOpcode()) {
840 case ISD::INTRINSIC_W_CHAIN:
841 case ISD::INTRINSIC_WO_CHAIN:
842 case ISD::INTRINSIC_VOID:
845 Action = TLI.getOperationAction(Node->getOpcode(), MVT::Other);
847 case ISD::SINT_TO_FP:
848 case ISD::UINT_TO_FP:
849 case ISD::EXTRACT_VECTOR_ELT:
850 Action = TLI.getOperationAction(Node->getOpcode(),
851 Node->getOperand(0).getValueType());
853 case ISD::FP_ROUND_INREG:
854 case ISD::SIGN_EXTEND_INREG: {
855 EVT InnerType = cast<VTSDNode>(Node->getOperand(1))->getVT();
856 Action = TLI.getOperationAction(Node->getOpcode(), InnerType);
862 unsigned CCOperand = Node->getOpcode() == ISD::SELECT_CC ? 4 :
863 Node->getOpcode() == ISD::SETCC ? 2 : 1;
864 unsigned CompareOperand = Node->getOpcode() == ISD::BR_CC ? 2 : 0;
865 EVT OpVT = Node->getOperand(CompareOperand).getValueType();
866 ISD::CondCode CCCode =
867 cast<CondCodeSDNode>(Node->getOperand(CCOperand))->get();
868 Action = TLI.getCondCodeAction(CCCode, OpVT);
869 if (Action == TargetLowering::Legal) {
870 if (Node->getOpcode() == ISD::SELECT_CC)
871 Action = TLI.getOperationAction(Node->getOpcode(),
872 Node->getValueType(0));
874 Action = TLI.getOperationAction(Node->getOpcode(), OpVT);
880 // FIXME: Model these properly. LOAD and STORE are complicated, and
881 // STORE expects the unlegalized operand in some cases.
882 SimpleFinishLegalizing = false;
884 case ISD::CALLSEQ_START:
885 case ISD::CALLSEQ_END:
886 // FIXME: This shouldn't be necessary. These nodes have special properties
887 // dealing with the recursive nature of legalization. Removing this
888 // special case should be done as part of making LegalizeDAG non-recursive.
889 SimpleFinishLegalizing = false;
891 case ISD::EXTRACT_ELEMENT:
892 case ISD::FLT_ROUNDS_:
900 case ISD::MERGE_VALUES:
902 case ISD::FRAME_TO_ARGS_OFFSET:
903 case ISD::EH_SJLJ_SETJMP:
904 case ISD::EH_SJLJ_LONGJMP:
905 case ISD::EH_SJLJ_DISPATCHSETUP:
906 // These operations lie about being legal: when they claim to be legal,
907 // they should actually be expanded.
908 Action = TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0));
909 if (Action == TargetLowering::Legal)
910 Action = TargetLowering::Expand;
912 case ISD::TRAMPOLINE:
914 case ISD::RETURNADDR:
915 // These operations lie about being legal: when they claim to be legal,
916 // they should actually be custom-lowered.
917 Action = TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0));
918 if (Action == TargetLowering::Legal)
919 Action = TargetLowering::Custom;
921 case ISD::BUILD_VECTOR:
922 // A weird case: legalization for BUILD_VECTOR never legalizes the
924 // FIXME: This really sucks... changing it isn't semantically incorrect,
925 // but it massively pessimizes the code for floating-point BUILD_VECTORs
926 // because ConstantFP operands get legalized into constant pool loads
927 // before the BUILD_VECTOR code can see them. It doesn't usually bite,
928 // though, because BUILD_VECTORS usually get lowered into other nodes
929 // which get legalized properly.
930 SimpleFinishLegalizing = false;
933 if (Node->getOpcode() >= ISD::BUILTIN_OP_END) {
934 Action = TargetLowering::Legal;
936 Action = TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0));
941 if (SimpleFinishLegalizing) {
942 SmallVector<SDValue, 8> Ops, ResultVals;
943 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
944 Ops.push_back(LegalizeOp(Node->getOperand(i)));
945 switch (Node->getOpcode()) {
952 assert(LastCALLSEQ.size() == 1 && "branch inside CALLSEQ_BEGIN/END?");
953 // Branches tweak the chain to include LastCALLSEQ
954 Ops[0] = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Ops[0],
956 Ops[0] = LegalizeOp(Ops[0]);
957 setLastCALLSEQ(DAG.getEntryNode());
964 // Legalizing shifts/rotates requires adjusting the shift amount
965 // to the appropriate width.
966 if (!Ops[1].getValueType().isVector())
967 Ops[1] = LegalizeOp(DAG.getShiftAmountOperand(Ops[0].getValueType(),
973 // Legalizing shifts/rotates requires adjusting the shift amount
974 // to the appropriate width.
975 if (!Ops[2].getValueType().isVector())
976 Ops[2] = LegalizeOp(DAG.getShiftAmountOperand(Ops[0].getValueType(),
981 Result = SDValue(DAG.UpdateNodeOperands(Result.getNode(), Ops.data(),
984 case TargetLowering::Legal:
985 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
986 ResultVals.push_back(Result.getValue(i));
988 case TargetLowering::Custom:
989 // FIXME: The handling for custom lowering with multiple results is
991 Tmp1 = TLI.LowerOperation(Result, DAG);
992 if (Tmp1.getNode()) {
993 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) {
995 ResultVals.push_back(Tmp1);
997 ResultVals.push_back(Tmp1.getValue(i));
1003 case TargetLowering::Expand:
1004 ExpandNode(Result.getNode(), ResultVals);
1006 case TargetLowering::Promote:
1007 PromoteNode(Result.getNode(), ResultVals);
1010 if (!ResultVals.empty()) {
1011 for (unsigned i = 0, e = ResultVals.size(); i != e; ++i) {
1012 if (ResultVals[i] != SDValue(Node, i))
1013 ResultVals[i] = LegalizeOp(ResultVals[i]);
1014 AddLegalizedOperand(SDValue(Node, i), ResultVals[i]);
1016 return ResultVals[Op.getResNo()];
1020 switch (Node->getOpcode()) {
1027 assert(0 && "Do not know how to legalize this operator!");
1029 case ISD::BUILD_VECTOR:
1030 switch (TLI.getOperationAction(ISD::BUILD_VECTOR, Node->getValueType(0))) {
1031 default: assert(0 && "This action is not supported yet!");
1032 case TargetLowering::Custom:
1033 Tmp3 = TLI.LowerOperation(Result, DAG);
1034 if (Tmp3.getNode()) {
1039 case TargetLowering::Expand:
1040 Result = ExpandBUILD_VECTOR(Result.getNode());
1044 case ISD::CALLSEQ_START: {
1045 SDNode *CallEnd = FindCallEndFromCallStart(Node);
1046 assert(CallEnd && "didn't find CALLSEQ_END!");
1048 // Recursively Legalize all of the inputs of the call end that do not lead
1049 // to this call start. This ensures that any libcalls that need be inserted
1050 // are inserted *before* the CALLSEQ_START.
1051 {SmallPtrSet<SDNode*, 32> NodesLeadingTo;
1052 for (unsigned i = 0, e = CallEnd->getNumOperands(); i != e; ++i)
1053 LegalizeAllNodesNotLeadingTo(CallEnd->getOperand(i).getNode(), Node,
1057 // Now that we have legalized all of the inputs (which may have inserted
1058 // libcalls), create the new CALLSEQ_START node.
1059 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1061 // Merge in the last call to ensure that this call starts after the last
1063 if (getLastCALLSEQ().getOpcode() != ISD::EntryToken) {
1064 Tmp1 = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
1065 Tmp1, getLastCALLSEQ());
1066 Tmp1 = LegalizeOp(Tmp1);
1069 // Do not try to legalize the target-specific arguments (#1+).
1070 if (Tmp1 != Node->getOperand(0)) {
1071 SmallVector<SDValue, 8> Ops(Node->op_begin(), Node->op_end());
1073 Result = SDValue(DAG.UpdateNodeOperands(Result.getNode(), &Ops[0],
1074 Ops.size()), Result.getResNo());
1077 // Remember that the CALLSEQ_START is legalized.
1078 AddLegalizedOperand(Op.getValue(0), Result);
1079 if (Node->getNumValues() == 2) // If this has a flag result, remember it.
1080 AddLegalizedOperand(Op.getValue(1), Result.getValue(1));
1082 // Now that the callseq_start and all of the non-call nodes above this call
1083 // sequence have been legalized, legalize the call itself. During this
1084 // process, no libcalls can/will be inserted, guaranteeing that no calls
1086 // Note that we are selecting this call!
1087 setLastCALLSEQ(SDValue(CallEnd, 0));
1089 // Legalize the call, starting from the CALLSEQ_END.
1090 LegalizeOp(getLastCALLSEQ());
1093 case ISD::CALLSEQ_END:
1095 SDNode *myCALLSEQ_BEGIN = FindCallStartFromCallEnd(Node);
1097 // If the CALLSEQ_START node hasn't been legalized first, legalize it.
1098 // This will cause this node to be legalized as well as handling libcalls
1100 if (getLastCALLSEQ().getNode() != Node) {
1101 LegalizeOp(SDValue(myCALLSEQ_BEGIN, 0));
1102 DenseMap<SDValue, SDValue>::iterator I = LegalizedNodes.find(Op);
1103 assert(I != LegalizedNodes.end() &&
1104 "Legalizing the call start should have legalized this node!");
1108 pushLastCALLSEQ(SDValue(myCALLSEQ_BEGIN, 0));
1111 // Otherwise, the call start has been legalized and everything is going
1112 // according to plan. Just legalize ourselves normally here.
1113 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1114 // Do not try to legalize the target-specific arguments (#1+), except for
1115 // an optional flag input.
1116 if (Node->getOperand(Node->getNumOperands()-1).getValueType() != MVT::Glue){
1117 if (Tmp1 != Node->getOperand(0)) {
1118 SmallVector<SDValue, 8> Ops(Node->op_begin(), Node->op_end());
1120 Result = SDValue(DAG.UpdateNodeOperands(Result.getNode(),
1121 &Ops[0], Ops.size()),
1125 Tmp2 = LegalizeOp(Node->getOperand(Node->getNumOperands()-1));
1126 if (Tmp1 != Node->getOperand(0) ||
1127 Tmp2 != Node->getOperand(Node->getNumOperands()-1)) {
1128 SmallVector<SDValue, 8> Ops(Node->op_begin(), Node->op_end());
1131 Result = SDValue(DAG.UpdateNodeOperands(Result.getNode(),
1132 &Ops[0], Ops.size()),
1136 // This finishes up call legalization.
1139 // If the CALLSEQ_END node has a flag, remember that we legalized it.
1140 AddLegalizedOperand(SDValue(Node, 0), Result.getValue(0));
1141 if (Node->getNumValues() == 2)
1142 AddLegalizedOperand(SDValue(Node, 1), Result.getValue(1));
1143 return Result.getValue(Op.getResNo());
1145 LoadSDNode *LD = cast<LoadSDNode>(Node);
1146 Tmp1 = LegalizeOp(LD->getChain()); // Legalize the chain.
1147 Tmp2 = LegalizeOp(LD->getBasePtr()); // Legalize the base pointer.
1149 ISD::LoadExtType ExtType = LD->getExtensionType();
1150 if (ExtType == ISD::NON_EXTLOAD) {
1151 EVT VT = Node->getValueType(0);
1152 Result = SDValue(DAG.UpdateNodeOperands(Result.getNode(),
1153 Tmp1, Tmp2, LD->getOffset()),
1155 Tmp3 = Result.getValue(0);
1156 Tmp4 = Result.getValue(1);
1158 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
1159 default: assert(0 && "This action is not supported yet!");
1160 case TargetLowering::Legal:
1161 // If this is an unaligned load and the target doesn't support it,
1163 if (!TLI.allowsUnalignedMemoryAccesses(LD->getMemoryVT())) {
1164 const Type *Ty = LD->getMemoryVT().getTypeForEVT(*DAG.getContext());
1165 unsigned ABIAlignment = TLI.getTargetData()->getABITypeAlignment(Ty);
1166 if (LD->getAlignment() < ABIAlignment){
1167 Result = ExpandUnalignedLoad(cast<LoadSDNode>(Result.getNode()),
1169 Tmp3 = Result.getOperand(0);
1170 Tmp4 = Result.getOperand(1);
1171 Tmp3 = LegalizeOp(Tmp3);
1172 Tmp4 = LegalizeOp(Tmp4);
1176 case TargetLowering::Custom:
1177 Tmp1 = TLI.LowerOperation(Tmp3, DAG);
1178 if (Tmp1.getNode()) {
1179 Tmp3 = LegalizeOp(Tmp1);
1180 Tmp4 = LegalizeOp(Tmp1.getValue(1));
1183 case TargetLowering::Promote: {
1184 // Only promote a load of vector type to another.
1185 assert(VT.isVector() && "Cannot promote this load!");
1186 // Change base type to a different vector type.
1187 EVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), VT);
1189 Tmp1 = DAG.getLoad(NVT, dl, Tmp1, Tmp2, LD->getPointerInfo(),
1190 LD->isVolatile(), LD->isNonTemporal(),
1191 LD->getAlignment());
1192 Tmp3 = LegalizeOp(DAG.getNode(ISD::BITCAST, dl, VT, Tmp1));
1193 Tmp4 = LegalizeOp(Tmp1.getValue(1));
1197 // Since loads produce two values, make sure to remember that we
1198 // legalized both of them.
1199 AddLegalizedOperand(SDValue(Node, 0), Tmp3);
1200 AddLegalizedOperand(SDValue(Node, 1), Tmp4);
1201 return Op.getResNo() ? Tmp4 : Tmp3;
1204 EVT SrcVT = LD->getMemoryVT();
1205 unsigned SrcWidth = SrcVT.getSizeInBits();
1206 unsigned Alignment = LD->getAlignment();
1207 bool isVolatile = LD->isVolatile();
1208 bool isNonTemporal = LD->isNonTemporal();
1210 if (SrcWidth != SrcVT.getStoreSizeInBits() &&
1211 // Some targets pretend to have an i1 loading operation, and actually
1212 // load an i8. This trick is correct for ZEXTLOAD because the top 7
1213 // bits are guaranteed to be zero; it helps the optimizers understand
1214 // that these bits are zero. It is also useful for EXTLOAD, since it
1215 // tells the optimizers that those bits are undefined. It would be
1216 // nice to have an effective generic way of getting these benefits...
1217 // Until such a way is found, don't insist on promoting i1 here.
1218 (SrcVT != MVT::i1 ||
1219 TLI.getLoadExtAction(ExtType, MVT::i1) == TargetLowering::Promote)) {
1220 // Promote to a byte-sized load if not loading an integral number of
1221 // bytes. For example, promote EXTLOAD:i20 -> EXTLOAD:i24.
1222 unsigned NewWidth = SrcVT.getStoreSizeInBits();
1223 EVT NVT = EVT::getIntegerVT(*DAG.getContext(), NewWidth);
1226 // The extra bits are guaranteed to be zero, since we stored them that
1227 // way. A zext load from NVT thus automatically gives zext from SrcVT.
1229 ISD::LoadExtType NewExtType =
1230 ExtType == ISD::ZEXTLOAD ? ISD::ZEXTLOAD : ISD::EXTLOAD;
1232 Result = DAG.getExtLoad(NewExtType, dl, Node->getValueType(0),
1233 Tmp1, Tmp2, LD->getPointerInfo(),
1234 NVT, isVolatile, isNonTemporal, Alignment);
1236 Ch = Result.getValue(1); // The chain.
1238 if (ExtType == ISD::SEXTLOAD)
1239 // Having the top bits zero doesn't help when sign extending.
1240 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl,
1241 Result.getValueType(),
1242 Result, DAG.getValueType(SrcVT));
1243 else if (ExtType == ISD::ZEXTLOAD || NVT == Result.getValueType())
1244 // All the top bits are guaranteed to be zero - inform the optimizers.
1245 Result = DAG.getNode(ISD::AssertZext, dl,
1246 Result.getValueType(), Result,
1247 DAG.getValueType(SrcVT));
1249 Tmp1 = LegalizeOp(Result);
1250 Tmp2 = LegalizeOp(Ch);
1251 } else if (SrcWidth & (SrcWidth - 1)) {
1252 // If not loading a power-of-2 number of bits, expand as two loads.
1253 assert(!SrcVT.isVector() && "Unsupported extload!");
1254 unsigned RoundWidth = 1 << Log2_32(SrcWidth);
1255 assert(RoundWidth < SrcWidth);
1256 unsigned ExtraWidth = SrcWidth - RoundWidth;
1257 assert(ExtraWidth < RoundWidth);
1258 assert(!(RoundWidth % 8) && !(ExtraWidth % 8) &&
1259 "Load size not an integral number of bytes!");
1260 EVT RoundVT = EVT::getIntegerVT(*DAG.getContext(), RoundWidth);
1261 EVT ExtraVT = EVT::getIntegerVT(*DAG.getContext(), ExtraWidth);
1263 unsigned IncrementSize;
1265 if (TLI.isLittleEndian()) {
1266 // EXTLOAD:i24 -> ZEXTLOAD:i16 | (shl EXTLOAD@+2:i8, 16)
1267 // Load the bottom RoundWidth bits.
1268 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, Node->getValueType(0),
1270 LD->getPointerInfo(), RoundVT, isVolatile,
1271 isNonTemporal, Alignment);
1273 // Load the remaining ExtraWidth bits.
1274 IncrementSize = RoundWidth / 8;
1275 Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2,
1276 DAG.getIntPtrConstant(IncrementSize));
1277 Hi = DAG.getExtLoad(ExtType, dl, Node->getValueType(0), Tmp1, Tmp2,
1278 LD->getPointerInfo().getWithOffset(IncrementSize),
1279 ExtraVT, isVolatile, isNonTemporal,
1280 MinAlign(Alignment, IncrementSize));
1282 // Build a factor node to remember that this load is independent of
1284 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
1287 // Move the top bits to the right place.
1288 Hi = DAG.getNode(ISD::SHL, dl, Hi.getValueType(), Hi,
1289 DAG.getConstant(RoundWidth,
1290 TLI.getShiftAmountTy(Hi.getValueType())));
1292 // Join the hi and lo parts.
1293 Result = DAG.getNode(ISD::OR, dl, Node->getValueType(0), Lo, Hi);
1295 // Big endian - avoid unaligned loads.
1296 // EXTLOAD:i24 -> (shl EXTLOAD:i16, 8) | ZEXTLOAD@+2:i8
1297 // Load the top RoundWidth bits.
1298 Hi = DAG.getExtLoad(ExtType, dl, Node->getValueType(0), Tmp1, Tmp2,
1299 LD->getPointerInfo(), RoundVT, isVolatile,
1300 isNonTemporal, Alignment);
1302 // Load the remaining ExtraWidth bits.
1303 IncrementSize = RoundWidth / 8;
1304 Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2,
1305 DAG.getIntPtrConstant(IncrementSize));
1306 Lo = DAG.getExtLoad(ISD::ZEXTLOAD,
1307 dl, Node->getValueType(0), Tmp1, Tmp2,
1308 LD->getPointerInfo().getWithOffset(IncrementSize),
1309 ExtraVT, isVolatile, isNonTemporal,
1310 MinAlign(Alignment, IncrementSize));
1312 // Build a factor node to remember that this load is independent of
1314 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
1317 // Move the top bits to the right place.
1318 Hi = DAG.getNode(ISD::SHL, dl, Hi.getValueType(), Hi,
1319 DAG.getConstant(ExtraWidth,
1320 TLI.getShiftAmountTy(Hi.getValueType())));
1322 // Join the hi and lo parts.
1323 Result = DAG.getNode(ISD::OR, dl, Node->getValueType(0), Lo, Hi);
1326 Tmp1 = LegalizeOp(Result);
1327 Tmp2 = LegalizeOp(Ch);
1329 switch (TLI.getLoadExtAction(ExtType, SrcVT)) {
1330 default: assert(0 && "This action is not supported yet!");
1331 case TargetLowering::Custom:
1334 case TargetLowering::Legal:
1335 Result = SDValue(DAG.UpdateNodeOperands(Result.getNode(),
1336 Tmp1, Tmp2, LD->getOffset()),
1338 Tmp1 = Result.getValue(0);
1339 Tmp2 = Result.getValue(1);
1342 Tmp3 = TLI.LowerOperation(Result, DAG);
1343 if (Tmp3.getNode()) {
1344 Tmp1 = LegalizeOp(Tmp3);
1345 Tmp2 = LegalizeOp(Tmp3.getValue(1));
1348 // If this is an unaligned load and the target doesn't support it,
1350 if (!TLI.allowsUnalignedMemoryAccesses(LD->getMemoryVT())) {
1352 LD->getMemoryVT().getTypeForEVT(*DAG.getContext());
1353 unsigned ABIAlignment =
1354 TLI.getTargetData()->getABITypeAlignment(Ty);
1355 if (LD->getAlignment() < ABIAlignment){
1356 Result = ExpandUnalignedLoad(cast<LoadSDNode>(Result.getNode()),
1358 Tmp1 = Result.getOperand(0);
1359 Tmp2 = Result.getOperand(1);
1360 Tmp1 = LegalizeOp(Tmp1);
1361 Tmp2 = LegalizeOp(Tmp2);
1366 case TargetLowering::Expand:
1367 if (!TLI.isLoadExtLegal(ISD::EXTLOAD, SrcVT) && isTypeLegal(SrcVT)) {
1368 SDValue Load = DAG.getLoad(SrcVT, dl, Tmp1, Tmp2,
1369 LD->getPointerInfo(),
1370 LD->isVolatile(), LD->isNonTemporal(),
1371 LD->getAlignment());
1375 ExtendOp = (SrcVT.isFloatingPoint() ?
1376 ISD::FP_EXTEND : ISD::ANY_EXTEND);
1378 case ISD::SEXTLOAD: ExtendOp = ISD::SIGN_EXTEND; break;
1379 case ISD::ZEXTLOAD: ExtendOp = ISD::ZERO_EXTEND; break;
1380 default: llvm_unreachable("Unexpected extend load type!");
1382 Result = DAG.getNode(ExtendOp, dl, Node->getValueType(0), Load);
1383 Tmp1 = LegalizeOp(Result); // Relegalize new nodes.
1384 Tmp2 = LegalizeOp(Load.getValue(1));
1387 // FIXME: This does not work for vectors on most targets. Sign- and
1388 // zero-extend operations are currently folded into extending loads,
1389 // whether they are legal or not, and then we end up here without any
1390 // support for legalizing them.
1391 assert(ExtType != ISD::EXTLOAD &&
1392 "EXTLOAD should always be supported!");
1393 // Turn the unsupported load into an EXTLOAD followed by an explicit
1394 // zero/sign extend inreg.
1395 Result = DAG.getExtLoad(ISD::EXTLOAD, dl, Node->getValueType(0),
1396 Tmp1, Tmp2, LD->getPointerInfo(), SrcVT,
1397 LD->isVolatile(), LD->isNonTemporal(),
1398 LD->getAlignment());
1400 if (ExtType == ISD::SEXTLOAD)
1401 ValRes = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl,
1402 Result.getValueType(),
1403 Result, DAG.getValueType(SrcVT));
1405 ValRes = DAG.getZeroExtendInReg(Result, dl, SrcVT.getScalarType());
1406 Tmp1 = LegalizeOp(ValRes); // Relegalize new nodes.
1407 Tmp2 = LegalizeOp(Result.getValue(1)); // Relegalize new nodes.
1412 // Since loads produce two values, make sure to remember that we legalized
1414 AddLegalizedOperand(SDValue(Node, 0), Tmp1);
1415 AddLegalizedOperand(SDValue(Node, 1), Tmp2);
1416 return Op.getResNo() ? Tmp2 : Tmp1;
1419 StoreSDNode *ST = cast<StoreSDNode>(Node);
1420 Tmp1 = LegalizeOp(ST->getChain()); // Legalize the chain.
1421 Tmp2 = LegalizeOp(ST->getBasePtr()); // Legalize the pointer.
1422 unsigned Alignment = ST->getAlignment();
1423 bool isVolatile = ST->isVolatile();
1424 bool isNonTemporal = ST->isNonTemporal();
1426 if (!ST->isTruncatingStore()) {
1427 if (SDNode *OptStore = OptimizeFloatStore(ST).getNode()) {
1428 Result = SDValue(OptStore, 0);
1433 Tmp3 = LegalizeOp(ST->getValue());
1434 Result = SDValue(DAG.UpdateNodeOperands(Result.getNode(),
1439 EVT VT = Tmp3.getValueType();
1440 switch (TLI.getOperationAction(ISD::STORE, VT)) {
1441 default: assert(0 && "This action is not supported yet!");
1442 case TargetLowering::Legal:
1443 // If this is an unaligned store and the target doesn't support it,
1445 if (!TLI.allowsUnalignedMemoryAccesses(ST->getMemoryVT())) {
1446 const Type *Ty = ST->getMemoryVT().getTypeForEVT(*DAG.getContext());
1447 unsigned ABIAlignment= TLI.getTargetData()->getABITypeAlignment(Ty);
1448 if (ST->getAlignment() < ABIAlignment)
1449 Result = ExpandUnalignedStore(cast<StoreSDNode>(Result.getNode()),
1453 case TargetLowering::Custom:
1454 Tmp1 = TLI.LowerOperation(Result, DAG);
1455 if (Tmp1.getNode()) Result = Tmp1;
1457 case TargetLowering::Promote:
1458 assert(VT.isVector() && "Unknown legal promote case!");
1459 Tmp3 = DAG.getNode(ISD::BITCAST, dl,
1460 TLI.getTypeToPromoteTo(ISD::STORE, VT), Tmp3);
1461 Result = DAG.getStore(Tmp1, dl, Tmp3, Tmp2,
1462 ST->getPointerInfo(), isVolatile,
1463 isNonTemporal, Alignment);
1469 Tmp3 = LegalizeOp(ST->getValue());
1471 EVT StVT = ST->getMemoryVT();
1472 unsigned StWidth = StVT.getSizeInBits();
1474 if (StWidth != StVT.getStoreSizeInBits()) {
1475 // Promote to a byte-sized store with upper bits zero if not
1476 // storing an integral number of bytes. For example, promote
1477 // TRUNCSTORE:i1 X -> TRUNCSTORE:i8 (and X, 1)
1478 EVT NVT = EVT::getIntegerVT(*DAG.getContext(),
1479 StVT.getStoreSizeInBits());
1480 Tmp3 = DAG.getZeroExtendInReg(Tmp3, dl, StVT);
1481 Result = DAG.getTruncStore(Tmp1, dl, Tmp3, Tmp2, ST->getPointerInfo(),
1482 NVT, isVolatile, isNonTemporal, Alignment);
1483 } else if (StWidth & (StWidth - 1)) {
1484 // If not storing a power-of-2 number of bits, expand as two stores.
1485 assert(!StVT.isVector() && "Unsupported truncstore!");
1486 unsigned RoundWidth = 1 << Log2_32(StWidth);
1487 assert(RoundWidth < StWidth);
1488 unsigned ExtraWidth = StWidth - RoundWidth;
1489 assert(ExtraWidth < RoundWidth);
1490 assert(!(RoundWidth % 8) && !(ExtraWidth % 8) &&
1491 "Store size not an integral number of bytes!");
1492 EVT RoundVT = EVT::getIntegerVT(*DAG.getContext(), RoundWidth);
1493 EVT ExtraVT = EVT::getIntegerVT(*DAG.getContext(), ExtraWidth);
1495 unsigned IncrementSize;
1497 if (TLI.isLittleEndian()) {
1498 // TRUNCSTORE:i24 X -> TRUNCSTORE:i16 X, TRUNCSTORE@+2:i8 (srl X, 16)
1499 // Store the bottom RoundWidth bits.
1500 Lo = DAG.getTruncStore(Tmp1, dl, Tmp3, Tmp2, ST->getPointerInfo(),
1502 isVolatile, isNonTemporal, Alignment);
1504 // Store the remaining ExtraWidth bits.
1505 IncrementSize = RoundWidth / 8;
1506 Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2,
1507 DAG.getIntPtrConstant(IncrementSize));
1508 Hi = DAG.getNode(ISD::SRL, dl, Tmp3.getValueType(), Tmp3,
1509 DAG.getConstant(RoundWidth,
1510 TLI.getShiftAmountTy(Tmp3.getValueType())));
1511 Hi = DAG.getTruncStore(Tmp1, dl, Hi, Tmp2,
1512 ST->getPointerInfo().getWithOffset(IncrementSize),
1513 ExtraVT, isVolatile, isNonTemporal,
1514 MinAlign(Alignment, IncrementSize));
1516 // Big endian - avoid unaligned stores.
1517 // TRUNCSTORE:i24 X -> TRUNCSTORE:i16 (srl X, 8), TRUNCSTORE@+2:i8 X
1518 // Store the top RoundWidth bits.
1519 Hi = DAG.getNode(ISD::SRL, dl, Tmp3.getValueType(), Tmp3,
1520 DAG.getConstant(ExtraWidth,
1521 TLI.getShiftAmountTy(Tmp3.getValueType())));
1522 Hi = DAG.getTruncStore(Tmp1, dl, Hi, Tmp2, ST->getPointerInfo(),
1523 RoundVT, isVolatile, isNonTemporal, Alignment);
1525 // Store the remaining ExtraWidth bits.
1526 IncrementSize = RoundWidth / 8;
1527 Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2,
1528 DAG.getIntPtrConstant(IncrementSize));
1529 Lo = DAG.getTruncStore(Tmp1, dl, Tmp3, Tmp2,
1530 ST->getPointerInfo().getWithOffset(IncrementSize),
1531 ExtraVT, isVolatile, isNonTemporal,
1532 MinAlign(Alignment, IncrementSize));
1535 // The order of the stores doesn't matter.
1536 Result = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi);
1538 if (Tmp1 != ST->getChain() || Tmp3 != ST->getValue() ||
1539 Tmp2 != ST->getBasePtr())
1540 Result = SDValue(DAG.UpdateNodeOperands(Result.getNode(),
1545 switch (TLI.getTruncStoreAction(ST->getValue().getValueType(), StVT)) {
1546 default: assert(0 && "This action is not supported yet!");
1547 case TargetLowering::Legal:
1548 // If this is an unaligned store and the target doesn't support it,
1550 if (!TLI.allowsUnalignedMemoryAccesses(ST->getMemoryVT())) {
1551 const Type *Ty = ST->getMemoryVT().getTypeForEVT(*DAG.getContext());
1552 unsigned ABIAlignment= TLI.getTargetData()->getABITypeAlignment(Ty);
1553 if (ST->getAlignment() < ABIAlignment)
1554 Result = ExpandUnalignedStore(cast<StoreSDNode>(Result.getNode()),
1558 case TargetLowering::Custom:
1559 Result = TLI.LowerOperation(Result, DAG);
1562 // TRUNCSTORE:i16 i32 -> STORE i16
1563 assert(isTypeLegal(StVT) && "Do not know how to expand this store!");
1564 Tmp3 = DAG.getNode(ISD::TRUNCATE, dl, StVT, Tmp3);
1565 Result = DAG.getStore(Tmp1, dl, Tmp3, Tmp2, ST->getPointerInfo(),
1566 isVolatile, isNonTemporal, Alignment);
1574 assert(Result.getValueType() == Op.getValueType() &&
1575 "Bad legalization!");
1577 // Make sure that the generated code is itself legal.
1579 Result = LegalizeOp(Result);
1581 // Note that LegalizeOp may be reentered even from single-use nodes, which
1582 // means that we always must cache transformed nodes.
1583 AddLegalizedOperand(Op, Result);
1587 SDValue SelectionDAGLegalize::ExpandExtractFromVectorThroughStack(SDValue Op) {
1588 SDValue Vec = Op.getOperand(0);
1589 SDValue Idx = Op.getOperand(1);
1590 DebugLoc dl = Op.getDebugLoc();
1591 // Store the value to a temporary stack slot, then LOAD the returned part.
1592 SDValue StackPtr = DAG.CreateStackTemporary(Vec.getValueType());
1593 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, Vec, StackPtr,
1594 MachinePointerInfo(), false, false, 0);
1596 // Add the offset to the index.
1598 Vec.getValueType().getVectorElementType().getSizeInBits()/8;
1599 Idx = DAG.getNode(ISD::MUL, dl, Idx.getValueType(), Idx,
1600 DAG.getConstant(EltSize, Idx.getValueType()));
1602 if (Idx.getValueType().bitsGT(TLI.getPointerTy()))
1603 Idx = DAG.getNode(ISD::TRUNCATE, dl, TLI.getPointerTy(), Idx);
1605 Idx = DAG.getNode(ISD::ZERO_EXTEND, dl, TLI.getPointerTy(), Idx);
1607 StackPtr = DAG.getNode(ISD::ADD, dl, Idx.getValueType(), Idx, StackPtr);
1609 if (Op.getValueType().isVector())
1610 return DAG.getLoad(Op.getValueType(), dl, Ch, StackPtr,MachinePointerInfo(),
1612 return DAG.getExtLoad(ISD::EXTLOAD, dl, Op.getValueType(), Ch, StackPtr,
1613 MachinePointerInfo(),
1614 Vec.getValueType().getVectorElementType(),
1618 SDValue SelectionDAGLegalize::ExpandInsertToVectorThroughStack(SDValue Op) {
1619 assert(Op.getValueType().isVector() && "Non-vector insert subvector!");
1621 SDValue Vec = Op.getOperand(0);
1622 SDValue Part = Op.getOperand(1);
1623 SDValue Idx = Op.getOperand(2);
1624 DebugLoc dl = Op.getDebugLoc();
1626 // Store the value to a temporary stack slot, then LOAD the returned part.
1628 SDValue StackPtr = DAG.CreateStackTemporary(Vec.getValueType());
1629 int FI = cast<FrameIndexSDNode>(StackPtr.getNode())->getIndex();
1630 MachinePointerInfo PtrInfo = MachinePointerInfo::getFixedStack(FI);
1632 // First store the whole vector.
1633 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, Vec, StackPtr, PtrInfo,
1636 // Then store the inserted part.
1638 // Add the offset to the index.
1640 Vec.getValueType().getVectorElementType().getSizeInBits()/8;
1642 Idx = DAG.getNode(ISD::MUL, dl, Idx.getValueType(), Idx,
1643 DAG.getConstant(EltSize, Idx.getValueType()));
1645 if (Idx.getValueType().bitsGT(TLI.getPointerTy()))
1646 Idx = DAG.getNode(ISD::TRUNCATE, dl, TLI.getPointerTy(), Idx);
1648 Idx = DAG.getNode(ISD::ZERO_EXTEND, dl, TLI.getPointerTy(), Idx);
1650 SDValue SubStackPtr = DAG.getNode(ISD::ADD, dl, Idx.getValueType(), Idx,
1653 // Store the subvector.
1654 Ch = DAG.getStore(DAG.getEntryNode(), dl, Part, SubStackPtr,
1655 MachinePointerInfo(), false, false, 0);
1657 // Finally, load the updated vector.
1658 return DAG.getLoad(Op.getValueType(), dl, Ch, StackPtr, PtrInfo,
1662 SDValue SelectionDAGLegalize::ExpandVectorBuildThroughStack(SDNode* Node) {
1663 // We can't handle this case efficiently. Allocate a sufficiently
1664 // aligned object on the stack, store each element into it, then load
1665 // the result as a vector.
1666 // Create the stack frame object.
1667 EVT VT = Node->getValueType(0);
1668 EVT EltVT = VT.getVectorElementType();
1669 DebugLoc dl = Node->getDebugLoc();
1670 SDValue FIPtr = DAG.CreateStackTemporary(VT);
1671 int FI = cast<FrameIndexSDNode>(FIPtr.getNode())->getIndex();
1672 MachinePointerInfo PtrInfo = MachinePointerInfo::getFixedStack(FI);
1674 // Emit a store of each element to the stack slot.
1675 SmallVector<SDValue, 8> Stores;
1676 unsigned TypeByteSize = EltVT.getSizeInBits() / 8;
1677 // Store (in the right endianness) the elements to memory.
1678 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
1679 // Ignore undef elements.
1680 if (Node->getOperand(i).getOpcode() == ISD::UNDEF) continue;
1682 unsigned Offset = TypeByteSize*i;
1684 SDValue Idx = DAG.getConstant(Offset, FIPtr.getValueType());
1685 Idx = DAG.getNode(ISD::ADD, dl, FIPtr.getValueType(), FIPtr, Idx);
1687 // If the destination vector element type is narrower than the source
1688 // element type, only store the bits necessary.
1689 if (EltVT.bitsLT(Node->getOperand(i).getValueType().getScalarType())) {
1690 Stores.push_back(DAG.getTruncStore(DAG.getEntryNode(), dl,
1691 Node->getOperand(i), Idx,
1692 PtrInfo.getWithOffset(Offset),
1693 EltVT, false, false, 0));
1695 Stores.push_back(DAG.getStore(DAG.getEntryNode(), dl,
1696 Node->getOperand(i), Idx,
1697 PtrInfo.getWithOffset(Offset),
1702 if (!Stores.empty()) // Not all undef elements?
1703 StoreChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
1704 &Stores[0], Stores.size());
1706 StoreChain = DAG.getEntryNode();
1708 // Result is a load from the stack slot.
1709 return DAG.getLoad(VT, dl, StoreChain, FIPtr, PtrInfo, false, false, 0);
1712 SDValue SelectionDAGLegalize::ExpandFCOPYSIGN(SDNode* Node) {
1713 DebugLoc dl = Node->getDebugLoc();
1714 SDValue Tmp1 = Node->getOperand(0);
1715 SDValue Tmp2 = Node->getOperand(1);
1717 // Get the sign bit of the RHS. First obtain a value that has the same
1718 // sign as the sign bit, i.e. negative if and only if the sign bit is 1.
1720 EVT FloatVT = Tmp2.getValueType();
1721 EVT IVT = EVT::getIntegerVT(*DAG.getContext(), FloatVT.getSizeInBits());
1722 if (isTypeLegal(IVT)) {
1723 // Convert to an integer with the same sign bit.
1724 SignBit = DAG.getNode(ISD::BITCAST, dl, IVT, Tmp2);
1726 // Store the float to memory, then load the sign part out as an integer.
1727 MVT LoadTy = TLI.getPointerTy();
1728 // First create a temporary that is aligned for both the load and store.
1729 SDValue StackPtr = DAG.CreateStackTemporary(FloatVT, LoadTy);
1730 // Then store the float to it.
1732 DAG.getStore(DAG.getEntryNode(), dl, Tmp2, StackPtr, MachinePointerInfo(),
1734 if (TLI.isBigEndian()) {
1735 assert(FloatVT.isByteSized() && "Unsupported floating point type!");
1736 // Load out a legal integer with the same sign bit as the float.
1737 SignBit = DAG.getLoad(LoadTy, dl, Ch, StackPtr, MachinePointerInfo(),
1739 } else { // Little endian
1740 SDValue LoadPtr = StackPtr;
1741 // The float may be wider than the integer we are going to load. Advance
1742 // the pointer so that the loaded integer will contain the sign bit.
1743 unsigned Strides = (FloatVT.getSizeInBits()-1)/LoadTy.getSizeInBits();
1744 unsigned ByteOffset = (Strides * LoadTy.getSizeInBits()) / 8;
1745 LoadPtr = DAG.getNode(ISD::ADD, dl, LoadPtr.getValueType(),
1746 LoadPtr, DAG.getIntPtrConstant(ByteOffset));
1747 // Load a legal integer containing the sign bit.
1748 SignBit = DAG.getLoad(LoadTy, dl, Ch, LoadPtr, MachinePointerInfo(),
1750 // Move the sign bit to the top bit of the loaded integer.
1751 unsigned BitShift = LoadTy.getSizeInBits() -
1752 (FloatVT.getSizeInBits() - 8 * ByteOffset);
1753 assert(BitShift < LoadTy.getSizeInBits() && "Pointer advanced wrong?");
1755 SignBit = DAG.getNode(ISD::SHL, dl, LoadTy, SignBit,
1756 DAG.getConstant(BitShift,
1757 TLI.getShiftAmountTy(SignBit.getValueType())));
1760 // Now get the sign bit proper, by seeing whether the value is negative.
1761 SignBit = DAG.getSetCC(dl, TLI.getSetCCResultType(SignBit.getValueType()),
1762 SignBit, DAG.getConstant(0, SignBit.getValueType()),
1764 // Get the absolute value of the result.
1765 SDValue AbsVal = DAG.getNode(ISD::FABS, dl, Tmp1.getValueType(), Tmp1);
1766 // Select between the nabs and abs value based on the sign bit of
1768 return DAG.getNode(ISD::SELECT, dl, AbsVal.getValueType(), SignBit,
1769 DAG.getNode(ISD::FNEG, dl, AbsVal.getValueType(), AbsVal),
1773 void SelectionDAGLegalize::ExpandDYNAMIC_STACKALLOC(SDNode* Node,
1774 SmallVectorImpl<SDValue> &Results) {
1775 unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore();
1776 assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and"
1777 " not tell us which reg is the stack pointer!");
1778 DebugLoc dl = Node->getDebugLoc();
1779 EVT VT = Node->getValueType(0);
1780 SDValue Tmp1 = SDValue(Node, 0);
1781 SDValue Tmp2 = SDValue(Node, 1);
1782 SDValue Tmp3 = Node->getOperand(2);
1783 SDValue Chain = Tmp1.getOperand(0);
1785 // Chain the dynamic stack allocation so that it doesn't modify the stack
1786 // pointer when other instructions are using the stack.
1787 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(0, true));
1789 SDValue Size = Tmp2.getOperand(1);
1790 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, VT);
1791 Chain = SP.getValue(1);
1792 unsigned Align = cast<ConstantSDNode>(Tmp3)->getZExtValue();
1793 unsigned StackAlign = TM.getFrameLowering()->getStackAlignment();
1794 if (Align > StackAlign)
1795 SP = DAG.getNode(ISD::AND, dl, VT, SP,
1796 DAG.getConstant(-(uint64_t)Align, VT));
1797 Tmp1 = DAG.getNode(ISD::SUB, dl, VT, SP, Size); // Value
1798 Chain = DAG.getCopyToReg(Chain, dl, SPReg, Tmp1); // Output chain
1800 Tmp2 = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(0, true),
1801 DAG.getIntPtrConstant(0, true), SDValue());
1803 Results.push_back(Tmp1);
1804 Results.push_back(Tmp2);
1807 /// LegalizeSetCCCondCode - Legalize a SETCC with given LHS and RHS and
1808 /// condition code CC on the current target. This routine expands SETCC with
1809 /// illegal condition code into AND / OR of multiple SETCC values.
1810 void SelectionDAGLegalize::LegalizeSetCCCondCode(EVT VT,
1811 SDValue &LHS, SDValue &RHS,
1814 EVT OpVT = LHS.getValueType();
1815 ISD::CondCode CCCode = cast<CondCodeSDNode>(CC)->get();
1816 switch (TLI.getCondCodeAction(CCCode, OpVT)) {
1817 default: assert(0 && "Unknown condition code action!");
1818 case TargetLowering::Legal:
1821 case TargetLowering::Expand: {
1822 ISD::CondCode CC1 = ISD::SETCC_INVALID, CC2 = ISD::SETCC_INVALID;
1825 default: assert(0 && "Don't know how to expand this condition!");
1826 case ISD::SETOEQ: CC1 = ISD::SETEQ; CC2 = ISD::SETO; Opc = ISD::AND; break;
1827 case ISD::SETOGT: CC1 = ISD::SETGT; CC2 = ISD::SETO; Opc = ISD::AND; break;
1828 case ISD::SETOGE: CC1 = ISD::SETGE; CC2 = ISD::SETO; Opc = ISD::AND; break;
1829 case ISD::SETOLT: CC1 = ISD::SETLT; CC2 = ISD::SETO; Opc = ISD::AND; break;
1830 case ISD::SETOLE: CC1 = ISD::SETLE; CC2 = ISD::SETO; Opc = ISD::AND; break;
1831 case ISD::SETONE: CC1 = ISD::SETNE; CC2 = ISD::SETO; Opc = ISD::AND; break;
1832 case ISD::SETUEQ: CC1 = ISD::SETEQ; CC2 = ISD::SETUO; Opc = ISD::OR; break;
1833 case ISD::SETUGT: CC1 = ISD::SETGT; CC2 = ISD::SETUO; Opc = ISD::OR; break;
1834 case ISD::SETUGE: CC1 = ISD::SETGE; CC2 = ISD::SETUO; Opc = ISD::OR; break;
1835 case ISD::SETULT: CC1 = ISD::SETLT; CC2 = ISD::SETUO; Opc = ISD::OR; break;
1836 case ISD::SETULE: CC1 = ISD::SETLE; CC2 = ISD::SETUO; Opc = ISD::OR; break;
1837 case ISD::SETUNE: CC1 = ISD::SETNE; CC2 = ISD::SETUO; Opc = ISD::OR; break;
1838 // FIXME: Implement more expansions.
1841 SDValue SetCC1 = DAG.getSetCC(dl, VT, LHS, RHS, CC1);
1842 SDValue SetCC2 = DAG.getSetCC(dl, VT, LHS, RHS, CC2);
1843 LHS = DAG.getNode(Opc, dl, VT, SetCC1, SetCC2);
1851 /// EmitStackConvert - Emit a store/load combination to the stack. This stores
1852 /// SrcOp to a stack slot of type SlotVT, truncating it if needed. It then does
1853 /// a load from the stack slot to DestVT, extending it if needed.
1854 /// The resultant code need not be legal.
1855 SDValue SelectionDAGLegalize::EmitStackConvert(SDValue SrcOp,
1859 // Create the stack frame object.
1861 TLI.getTargetData()->getPrefTypeAlignment(SrcOp.getValueType().
1862 getTypeForEVT(*DAG.getContext()));
1863 SDValue FIPtr = DAG.CreateStackTemporary(SlotVT, SrcAlign);
1865 FrameIndexSDNode *StackPtrFI = cast<FrameIndexSDNode>(FIPtr);
1866 int SPFI = StackPtrFI->getIndex();
1867 MachinePointerInfo PtrInfo = MachinePointerInfo::getFixedStack(SPFI);
1869 unsigned SrcSize = SrcOp.getValueType().getSizeInBits();
1870 unsigned SlotSize = SlotVT.getSizeInBits();
1871 unsigned DestSize = DestVT.getSizeInBits();
1872 const Type *DestType = DestVT.getTypeForEVT(*DAG.getContext());
1873 unsigned DestAlign = TLI.getTargetData()->getPrefTypeAlignment(DestType);
1875 // Emit a store to the stack slot. Use a truncstore if the input value is
1876 // later than DestVT.
1879 if (SrcSize > SlotSize)
1880 Store = DAG.getTruncStore(DAG.getEntryNode(), dl, SrcOp, FIPtr,
1881 PtrInfo, SlotVT, false, false, SrcAlign);
1883 assert(SrcSize == SlotSize && "Invalid store");
1884 Store = DAG.getStore(DAG.getEntryNode(), dl, SrcOp, FIPtr,
1885 PtrInfo, false, false, SrcAlign);
1888 // Result is a load from the stack slot.
1889 if (SlotSize == DestSize)
1890 return DAG.getLoad(DestVT, dl, Store, FIPtr, PtrInfo,
1891 false, false, DestAlign);
1893 assert(SlotSize < DestSize && "Unknown extension!");
1894 return DAG.getExtLoad(ISD::EXTLOAD, dl, DestVT, Store, FIPtr,
1895 PtrInfo, SlotVT, false, false, DestAlign);
1898 SDValue SelectionDAGLegalize::ExpandSCALAR_TO_VECTOR(SDNode *Node) {
1899 DebugLoc dl = Node->getDebugLoc();
1900 // Create a vector sized/aligned stack slot, store the value to element #0,
1901 // then load the whole vector back out.
1902 SDValue StackPtr = DAG.CreateStackTemporary(Node->getValueType(0));
1904 FrameIndexSDNode *StackPtrFI = cast<FrameIndexSDNode>(StackPtr);
1905 int SPFI = StackPtrFI->getIndex();
1907 SDValue Ch = DAG.getTruncStore(DAG.getEntryNode(), dl, Node->getOperand(0),
1909 MachinePointerInfo::getFixedStack(SPFI),
1910 Node->getValueType(0).getVectorElementType(),
1912 return DAG.getLoad(Node->getValueType(0), dl, Ch, StackPtr,
1913 MachinePointerInfo::getFixedStack(SPFI),
1918 /// ExpandBUILD_VECTOR - Expand a BUILD_VECTOR node on targets that don't
1919 /// support the operation, but do support the resultant vector type.
1920 SDValue SelectionDAGLegalize::ExpandBUILD_VECTOR(SDNode *Node) {
1921 unsigned NumElems = Node->getNumOperands();
1922 SDValue Value1, Value2;
1923 DebugLoc dl = Node->getDebugLoc();
1924 EVT VT = Node->getValueType(0);
1925 EVT OpVT = Node->getOperand(0).getValueType();
1926 EVT EltVT = VT.getVectorElementType();
1928 // If the only non-undef value is the low element, turn this into a
1929 // SCALAR_TO_VECTOR node. If this is { X, X, X, X }, determine X.
1930 bool isOnlyLowElement = true;
1931 bool MoreThanTwoValues = false;
1932 bool isConstant = true;
1933 for (unsigned i = 0; i < NumElems; ++i) {
1934 SDValue V = Node->getOperand(i);
1935 if (V.getOpcode() == ISD::UNDEF)
1938 isOnlyLowElement = false;
1939 if (!isa<ConstantFPSDNode>(V) && !isa<ConstantSDNode>(V))
1942 if (!Value1.getNode()) {
1944 } else if (!Value2.getNode()) {
1947 } else if (V != Value1 && V != Value2) {
1948 MoreThanTwoValues = true;
1952 if (!Value1.getNode())
1953 return DAG.getUNDEF(VT);
1955 if (isOnlyLowElement)
1956 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Node->getOperand(0));
1958 // If all elements are constants, create a load from the constant pool.
1960 std::vector<Constant*> CV;
1961 for (unsigned i = 0, e = NumElems; i != e; ++i) {
1962 if (ConstantFPSDNode *V =
1963 dyn_cast<ConstantFPSDNode>(Node->getOperand(i))) {
1964 CV.push_back(const_cast<ConstantFP *>(V->getConstantFPValue()));
1965 } else if (ConstantSDNode *V =
1966 dyn_cast<ConstantSDNode>(Node->getOperand(i))) {
1968 CV.push_back(const_cast<ConstantInt *>(V->getConstantIntValue()));
1970 // If OpVT and EltVT don't match, EltVT is not legal and the
1971 // element values have been promoted/truncated earlier. Undo this;
1972 // we don't want a v16i8 to become a v16i32 for example.
1973 const ConstantInt *CI = V->getConstantIntValue();
1974 CV.push_back(ConstantInt::get(EltVT.getTypeForEVT(*DAG.getContext()),
1975 CI->getZExtValue()));
1978 assert(Node->getOperand(i).getOpcode() == ISD::UNDEF);
1979 const Type *OpNTy = EltVT.getTypeForEVT(*DAG.getContext());
1980 CV.push_back(UndefValue::get(OpNTy));
1983 Constant *CP = ConstantVector::get(CV);
1984 SDValue CPIdx = DAG.getConstantPool(CP, TLI.getPointerTy());
1985 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
1986 return DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
1987 MachinePointerInfo::getConstantPool(),
1988 false, false, Alignment);
1991 if (!MoreThanTwoValues) {
1992 SmallVector<int, 8> ShuffleVec(NumElems, -1);
1993 for (unsigned i = 0; i < NumElems; ++i) {
1994 SDValue V = Node->getOperand(i);
1995 if (V.getOpcode() == ISD::UNDEF)
1997 ShuffleVec[i] = V == Value1 ? 0 : NumElems;
1999 if (TLI.isShuffleMaskLegal(ShuffleVec, Node->getValueType(0))) {
2000 // Get the splatted value into the low element of a vector register.
2001 SDValue Vec1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Value1);
2003 if (Value2.getNode())
2004 Vec2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Value2);
2006 Vec2 = DAG.getUNDEF(VT);
2008 // Return shuffle(LowValVec, undef, <0,0,0,0>)
2009 return DAG.getVectorShuffle(VT, dl, Vec1, Vec2, ShuffleVec.data());
2013 // Otherwise, we can't handle this case efficiently.
2014 return ExpandVectorBuildThroughStack(Node);
2017 // ExpandLibCall - Expand a node into a call to a libcall. If the result value
2018 // does not fit into a register, return the lo part and set the hi part to the
2019 // by-reg argument. If it does fit into a single register, return the result
2020 // and leave the Hi part unset.
2021 SDValue SelectionDAGLegalize::ExpandLibCall(RTLIB::Libcall LC, SDNode *Node,
2023 // The input chain to this libcall is the entry node of the function.
2024 // Legalizing the call will automatically add the previous call to the
2026 SDValue InChain = DAG.getEntryNode();
2028 TargetLowering::ArgListTy Args;
2029 TargetLowering::ArgListEntry Entry;
2030 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
2031 EVT ArgVT = Node->getOperand(i).getValueType();
2032 const Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
2033 Entry.Node = Node->getOperand(i); Entry.Ty = ArgTy;
2034 Entry.isSExt = isSigned;
2035 Entry.isZExt = !isSigned;
2036 Args.push_back(Entry);
2038 SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC),
2039 TLI.getPointerTy());
2041 // Splice the libcall in wherever FindInputOutputChains tells us to.
2042 const Type *RetTy = Node->getValueType(0).getTypeForEVT(*DAG.getContext());
2044 // isTailCall may be true since the callee does not reference caller stack
2045 // frame. Check if it's in the right position.
2046 bool isTailCall = isInTailCallPosition(DAG, Node, TLI);
2047 std::pair<SDValue, SDValue> CallInfo =
2048 TLI.LowerCallTo(InChain, RetTy, isSigned, !isSigned, false, false,
2049 0, TLI.getLibcallCallingConv(LC), isTailCall,
2050 /*isReturnValueUsed=*/true,
2051 Callee, Args, DAG, Node->getDebugLoc());
2053 if (!CallInfo.second.getNode())
2054 // It's a tailcall, return the chain (which is the DAG root).
2055 return DAG.getRoot();
2057 // Legalize the call sequence, starting with the chain. This will advance
2058 // the LastCALLSEQ to the legalized version of the CALLSEQ_END node that
2059 // was added by LowerCallTo (guaranteeing proper serialization of calls).
2060 LegalizeOp(CallInfo.second);
2061 return CallInfo.first;
2064 /// ExpandLibCall - Generate a libcall taking the given operands as arguments
2065 /// and returning a result of type RetVT.
2066 SDValue SelectionDAGLegalize::ExpandLibCall(RTLIB::Libcall LC, EVT RetVT,
2067 const SDValue *Ops, unsigned NumOps,
2068 bool isSigned, DebugLoc dl) {
2069 TargetLowering::ArgListTy Args;
2070 Args.reserve(NumOps);
2072 TargetLowering::ArgListEntry Entry;
2073 for (unsigned i = 0; i != NumOps; ++i) {
2074 Entry.Node = Ops[i];
2075 Entry.Ty = Entry.Node.getValueType().getTypeForEVT(*DAG.getContext());
2076 Entry.isSExt = isSigned;
2077 Entry.isZExt = !isSigned;
2078 Args.push_back(Entry);
2080 SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC),
2081 TLI.getPointerTy());
2083 const Type *RetTy = RetVT.getTypeForEVT(*DAG.getContext());
2084 std::pair<SDValue,SDValue> CallInfo =
2085 TLI.LowerCallTo(DAG.getEntryNode(), RetTy, isSigned, !isSigned, false,
2086 false, 0, TLI.getLibcallCallingConv(LC), false,
2087 /*isReturnValueUsed=*/true,
2088 Callee, Args, DAG, dl);
2090 // Legalize the call sequence, starting with the chain. This will advance
2091 // the LastCALLSEQ_END to the legalized version of the CALLSEQ_END node that
2092 // was added by LowerCallTo (guaranteeing proper serialization of calls).
2093 LegalizeOp(CallInfo.second);
2095 return CallInfo.first;
2098 // ExpandChainLibCall - Expand a node into a call to a libcall. Similar to
2099 // ExpandLibCall except that the first operand is the in-chain.
2100 std::pair<SDValue, SDValue>
2101 SelectionDAGLegalize::ExpandChainLibCall(RTLIB::Libcall LC,
2104 SDValue InChain = Node->getOperand(0);
2106 TargetLowering::ArgListTy Args;
2107 TargetLowering::ArgListEntry Entry;
2108 for (unsigned i = 1, e = Node->getNumOperands(); i != e; ++i) {
2109 EVT ArgVT = Node->getOperand(i).getValueType();
2110 const Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
2111 Entry.Node = Node->getOperand(i);
2113 Entry.isSExt = isSigned;
2114 Entry.isZExt = !isSigned;
2115 Args.push_back(Entry);
2117 SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC),
2118 TLI.getPointerTy());
2120 // Splice the libcall in wherever FindInputOutputChains tells us to.
2121 const Type *RetTy = Node->getValueType(0).getTypeForEVT(*DAG.getContext());
2122 std::pair<SDValue, SDValue> CallInfo =
2123 TLI.LowerCallTo(InChain, RetTy, isSigned, !isSigned, false, false,
2124 0, TLI.getLibcallCallingConv(LC), /*isTailCall=*/false,
2125 /*isReturnValueUsed=*/true,
2126 Callee, Args, DAG, Node->getDebugLoc());
2128 // Legalize the call sequence, starting with the chain. This will advance
2129 // the LastCALLSEQ to the legalized version of the CALLSEQ_END node that
2130 // was added by LowerCallTo (guaranteeing proper serialization of calls).
2131 LegalizeOp(CallInfo.second);
2135 SDValue SelectionDAGLegalize::ExpandFPLibCall(SDNode* Node,
2136 RTLIB::Libcall Call_F32,
2137 RTLIB::Libcall Call_F64,
2138 RTLIB::Libcall Call_F80,
2139 RTLIB::Libcall Call_PPCF128) {
2141 switch (Node->getValueType(0).getSimpleVT().SimpleTy) {
2142 default: assert(0 && "Unexpected request for libcall!");
2143 case MVT::f32: LC = Call_F32; break;
2144 case MVT::f64: LC = Call_F64; break;
2145 case MVT::f80: LC = Call_F80; break;
2146 case MVT::ppcf128: LC = Call_PPCF128; break;
2148 return ExpandLibCall(LC, Node, false);
2151 SDValue SelectionDAGLegalize::ExpandIntLibCall(SDNode* Node, bool isSigned,
2152 RTLIB::Libcall Call_I8,
2153 RTLIB::Libcall Call_I16,
2154 RTLIB::Libcall Call_I32,
2155 RTLIB::Libcall Call_I64,
2156 RTLIB::Libcall Call_I128) {
2158 switch (Node->getValueType(0).getSimpleVT().SimpleTy) {
2159 default: assert(0 && "Unexpected request for libcall!");
2160 case MVT::i8: LC = Call_I8; break;
2161 case MVT::i16: LC = Call_I16; break;
2162 case MVT::i32: LC = Call_I32; break;
2163 case MVT::i64: LC = Call_I64; break;
2164 case MVT::i128: LC = Call_I128; break;
2166 return ExpandLibCall(LC, Node, isSigned);
2169 /// isDivRemLibcallAvailable - Return true if divmod libcall is available.
2170 static bool isDivRemLibcallAvailable(SDNode *Node, bool isSigned,
2171 const TargetLowering &TLI) {
2173 switch (Node->getValueType(0).getSimpleVT().SimpleTy) {
2174 default: assert(0 && "Unexpected request for libcall!");
2175 case MVT::i8: LC= isSigned ? RTLIB::SDIVREM_I8 : RTLIB::UDIVREM_I8; break;
2176 case MVT::i16: LC= isSigned ? RTLIB::SDIVREM_I16 : RTLIB::UDIVREM_I16; break;
2177 case MVT::i32: LC= isSigned ? RTLIB::SDIVREM_I32 : RTLIB::UDIVREM_I32; break;
2178 case MVT::i64: LC= isSigned ? RTLIB::SDIVREM_I64 : RTLIB::UDIVREM_I64; break;
2179 case MVT::i128: LC= isSigned ? RTLIB::SDIVREM_I128:RTLIB::UDIVREM_I128; break;
2182 return TLI.getLibcallName(LC) != 0;
2185 /// UseDivRem - Only issue divrem libcall if both quotient and remainder are
2187 static bool UseDivRem(SDNode *Node, bool isSigned, bool isDIV) {
2188 unsigned OtherOpcode = 0;
2190 OtherOpcode = isDIV ? ISD::SREM : ISD::SDIV;
2192 OtherOpcode = isDIV ? ISD::UREM : ISD::UDIV;
2194 SDValue Op0 = Node->getOperand(0);
2195 SDValue Op1 = Node->getOperand(1);
2196 for (SDNode::use_iterator UI = Op0.getNode()->use_begin(),
2197 UE = Op0.getNode()->use_end(); UI != UE; ++UI) {
2201 if (User->getOpcode() == OtherOpcode &&
2202 User->getOperand(0) == Op0 &&
2203 User->getOperand(1) == Op1)
2209 /// ExpandDivRemLibCall - Issue libcalls to __{u}divmod to compute div / rem
2212 SelectionDAGLegalize::ExpandDivRemLibCall(SDNode *Node,
2213 SmallVectorImpl<SDValue> &Results) {
2214 unsigned Opcode = Node->getOpcode();
2215 bool isSigned = Opcode == ISD::SDIVREM;
2218 switch (Node->getValueType(0).getSimpleVT().SimpleTy) {
2219 default: assert(0 && "Unexpected request for libcall!");
2220 case MVT::i8: LC= isSigned ? RTLIB::SDIVREM_I8 : RTLIB::UDIVREM_I8; break;
2221 case MVT::i16: LC= isSigned ? RTLIB::SDIVREM_I16 : RTLIB::UDIVREM_I16; break;
2222 case MVT::i32: LC= isSigned ? RTLIB::SDIVREM_I32 : RTLIB::UDIVREM_I32; break;
2223 case MVT::i64: LC= isSigned ? RTLIB::SDIVREM_I64 : RTLIB::UDIVREM_I64; break;
2224 case MVT::i128: LC= isSigned ? RTLIB::SDIVREM_I128:RTLIB::UDIVREM_I128; break;
2227 // The input chain to this libcall is the entry node of the function.
2228 // Legalizing the call will automatically add the previous call to the
2230 SDValue InChain = DAG.getEntryNode();
2232 EVT RetVT = Node->getValueType(0);
2233 const Type *RetTy = RetVT.getTypeForEVT(*DAG.getContext());
2235 TargetLowering::ArgListTy Args;
2236 TargetLowering::ArgListEntry Entry;
2237 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
2238 EVT ArgVT = Node->getOperand(i).getValueType();
2239 const Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
2240 Entry.Node = Node->getOperand(i); Entry.Ty = ArgTy;
2241 Entry.isSExt = isSigned;
2242 Entry.isZExt = !isSigned;
2243 Args.push_back(Entry);
2246 // Also pass the return address of the remainder.
2247 SDValue FIPtr = DAG.CreateStackTemporary(RetVT);
2249 Entry.Ty = RetTy->getPointerTo();
2250 Entry.isSExt = isSigned;
2251 Entry.isZExt = !isSigned;
2252 Args.push_back(Entry);
2254 SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC),
2255 TLI.getPointerTy());
2257 // Splice the libcall in wherever FindInputOutputChains tells us to.
2258 DebugLoc dl = Node->getDebugLoc();
2259 std::pair<SDValue, SDValue> CallInfo =
2260 TLI.LowerCallTo(InChain, RetTy, isSigned, !isSigned, false, false,
2261 0, TLI.getLibcallCallingConv(LC), /*isTailCall=*/false,
2262 /*isReturnValueUsed=*/true, Callee, Args, DAG, dl);
2264 // Legalize the call sequence, starting with the chain. This will advance
2265 // the LastCALLSEQ to the legalized version of the CALLSEQ_END node that
2266 // was added by LowerCallTo (guaranteeing proper serialization of calls).
2267 LegalizeOp(CallInfo.second);
2269 // Remainder is loaded back from the stack frame.
2270 SDValue Rem = DAG.getLoad(RetVT, dl, getLastCALLSEQ(), FIPtr,
2271 MachinePointerInfo(), false, false, 0);
2272 Results.push_back(CallInfo.first);
2273 Results.push_back(Rem);
2276 /// ExpandLegalINT_TO_FP - This function is responsible for legalizing a
2277 /// INT_TO_FP operation of the specified operand when the target requests that
2278 /// we expand it. At this point, we know that the result and operand types are
2279 /// legal for the target.
2280 SDValue SelectionDAGLegalize::ExpandLegalINT_TO_FP(bool isSigned,
2284 if (Op0.getValueType() == MVT::i32) {
2285 // simple 32-bit [signed|unsigned] integer to float/double expansion
2287 // Get the stack frame index of a 8 byte buffer.
2288 SDValue StackSlot = DAG.CreateStackTemporary(MVT::f64);
2290 // word offset constant for Hi/Lo address computation
2291 SDValue WordOff = DAG.getConstant(sizeof(int), TLI.getPointerTy());
2292 // set up Hi and Lo (into buffer) address based on endian
2293 SDValue Hi = StackSlot;
2294 SDValue Lo = DAG.getNode(ISD::ADD, dl,
2295 TLI.getPointerTy(), StackSlot, WordOff);
2296 if (TLI.isLittleEndian())
2299 // if signed map to unsigned space
2302 // constant used to invert sign bit (signed to unsigned mapping)
2303 SDValue SignBit = DAG.getConstant(0x80000000u, MVT::i32);
2304 Op0Mapped = DAG.getNode(ISD::XOR, dl, MVT::i32, Op0, SignBit);
2308 // store the lo of the constructed double - based on integer input
2309 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl,
2310 Op0Mapped, Lo, MachinePointerInfo(),
2312 // initial hi portion of constructed double
2313 SDValue InitialHi = DAG.getConstant(0x43300000u, MVT::i32);
2314 // store the hi of the constructed double - biased exponent
2315 SDValue Store2 = DAG.getStore(Store1, dl, InitialHi, Hi,
2316 MachinePointerInfo(),
2318 // load the constructed double
2319 SDValue Load = DAG.getLoad(MVT::f64, dl, Store2, StackSlot,
2320 MachinePointerInfo(), false, false, 0);
2321 // FP constant to bias correct the final result
2322 SDValue Bias = DAG.getConstantFP(isSigned ?
2323 BitsToDouble(0x4330000080000000ULL) :
2324 BitsToDouble(0x4330000000000000ULL),
2326 // subtract the bias
2327 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Load, Bias);
2330 // handle final rounding
2331 if (DestVT == MVT::f64) {
2334 } else if (DestVT.bitsLT(MVT::f64)) {
2335 Result = DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub,
2336 DAG.getIntPtrConstant(0));
2337 } else if (DestVT.bitsGT(MVT::f64)) {
2338 Result = DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub);
2342 assert(!isSigned && "Legalize cannot Expand SINT_TO_FP for i64 yet");
2343 // Code below here assumes !isSigned without checking again.
2345 // Implementation of unsigned i64 to f64 following the algorithm in
2346 // __floatundidf in compiler_rt. This implementation has the advantage
2347 // of performing rounding correctly, both in the default rounding mode
2348 // and in all alternate rounding modes.
2349 // TODO: Generalize this for use with other types.
2350 if (Op0.getValueType() == MVT::i64 && DestVT == MVT::f64) {
2352 DAG.getConstant(UINT64_C(0x4330000000000000), MVT::i64);
2353 SDValue TwoP84PlusTwoP52 =
2354 DAG.getConstantFP(BitsToDouble(UINT64_C(0x4530000000100000)), MVT::f64);
2356 DAG.getConstant(UINT64_C(0x4530000000000000), MVT::i64);
2358 SDValue Lo = DAG.getZeroExtendInReg(Op0, dl, MVT::i32);
2359 SDValue Hi = DAG.getNode(ISD::SRL, dl, MVT::i64, Op0,
2360 DAG.getConstant(32, MVT::i64));
2361 SDValue LoOr = DAG.getNode(ISD::OR, dl, MVT::i64, Lo, TwoP52);
2362 SDValue HiOr = DAG.getNode(ISD::OR, dl, MVT::i64, Hi, TwoP84);
2363 SDValue LoFlt = DAG.getNode(ISD::BITCAST, dl, MVT::f64, LoOr);
2364 SDValue HiFlt = DAG.getNode(ISD::BITCAST, dl, MVT::f64, HiOr);
2365 SDValue HiSub = DAG.getNode(ISD::FSUB, dl, MVT::f64, HiFlt,
2367 return DAG.getNode(ISD::FADD, dl, MVT::f64, LoFlt, HiSub);
2370 // Implementation of unsigned i64 to f32.
2371 // TODO: Generalize this for use with other types.
2372 if (Op0.getValueType() == MVT::i64 && DestVT == MVT::f32) {
2373 // For unsigned conversions, convert them to signed conversions using the
2374 // algorithm from the x86_64 __floatundidf in compiler_rt.
2376 SDValue Fast = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, Op0);
2378 SDValue ShiftConst =
2379 DAG.getConstant(1, TLI.getShiftAmountTy(Op0.getValueType()));
2380 SDValue Shr = DAG.getNode(ISD::SRL, dl, MVT::i64, Op0, ShiftConst);
2381 SDValue AndConst = DAG.getConstant(1, MVT::i64);
2382 SDValue And = DAG.getNode(ISD::AND, dl, MVT::i64, Op0, AndConst);
2383 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::i64, And, Shr);
2385 SDValue SignCvt = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, Or);
2386 SDValue Slow = DAG.getNode(ISD::FADD, dl, MVT::f32, SignCvt, SignCvt);
2388 // TODO: This really should be implemented using a branch rather than a
2389 // select. We happen to get lucky and machinesink does the right
2390 // thing most of the time. This would be a good candidate for a
2391 //pseudo-op, or, even better, for whole-function isel.
2392 SDValue SignBitTest = DAG.getSetCC(dl, TLI.getSetCCResultType(MVT::i64),
2393 Op0, DAG.getConstant(0, MVT::i64), ISD::SETLT);
2394 return DAG.getNode(ISD::SELECT, dl, MVT::f32, SignBitTest, Slow, Fast);
2397 // Otherwise, implement the fully general conversion.
2399 SDValue And = DAG.getNode(ISD::AND, dl, MVT::i64, Op0,
2400 DAG.getConstant(UINT64_C(0xfffffffffffff800), MVT::i64));
2401 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::i64, And,
2402 DAG.getConstant(UINT64_C(0x800), MVT::i64));
2403 SDValue And2 = DAG.getNode(ISD::AND, dl, MVT::i64, Op0,
2404 DAG.getConstant(UINT64_C(0x7ff), MVT::i64));
2405 SDValue Ne = DAG.getSetCC(dl, TLI.getSetCCResultType(MVT::i64),
2406 And2, DAG.getConstant(UINT64_C(0), MVT::i64), ISD::SETNE);
2407 SDValue Sel = DAG.getNode(ISD::SELECT, dl, MVT::i64, Ne, Or, Op0);
2408 SDValue Ge = DAG.getSetCC(dl, TLI.getSetCCResultType(MVT::i64),
2409 Op0, DAG.getConstant(UINT64_C(0x0020000000000000), MVT::i64),
2411 SDValue Sel2 = DAG.getNode(ISD::SELECT, dl, MVT::i64, Ge, Sel, Op0);
2412 EVT SHVT = TLI.getShiftAmountTy(Sel2.getValueType());
2414 SDValue Sh = DAG.getNode(ISD::SRL, dl, MVT::i64, Sel2,
2415 DAG.getConstant(32, SHVT));
2416 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Sh);
2417 SDValue Fcvt = DAG.getNode(ISD::UINT_TO_FP, dl, MVT::f64, Trunc);
2419 DAG.getConstantFP(BitsToDouble(UINT64_C(0x41f0000000000000)), MVT::f64);
2420 SDValue Fmul = DAG.getNode(ISD::FMUL, dl, MVT::f64, TwoP32, Fcvt);
2421 SDValue Lo = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Sel2);
2422 SDValue Fcvt2 = DAG.getNode(ISD::UINT_TO_FP, dl, MVT::f64, Lo);
2423 SDValue Fadd = DAG.getNode(ISD::FADD, dl, MVT::f64, Fmul, Fcvt2);
2424 return DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, Fadd,
2425 DAG.getIntPtrConstant(0));
2428 SDValue Tmp1 = DAG.getNode(ISD::SINT_TO_FP, dl, DestVT, Op0);
2430 SDValue SignSet = DAG.getSetCC(dl, TLI.getSetCCResultType(Op0.getValueType()),
2431 Op0, DAG.getConstant(0, Op0.getValueType()),
2433 SDValue Zero = DAG.getIntPtrConstant(0), Four = DAG.getIntPtrConstant(4);
2434 SDValue CstOffset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(),
2435 SignSet, Four, Zero);
2437 // If the sign bit of the integer is set, the large number will be treated
2438 // as a negative number. To counteract this, the dynamic code adds an
2439 // offset depending on the data type.
2441 switch (Op0.getValueType().getSimpleVT().SimpleTy) {
2442 default: assert(0 && "Unsupported integer type!");
2443 case MVT::i8 : FF = 0x43800000ULL; break; // 2^8 (as a float)
2444 case MVT::i16: FF = 0x47800000ULL; break; // 2^16 (as a float)
2445 case MVT::i32: FF = 0x4F800000ULL; break; // 2^32 (as a float)
2446 case MVT::i64: FF = 0x5F800000ULL; break; // 2^64 (as a float)
2448 if (TLI.isLittleEndian()) FF <<= 32;
2449 Constant *FudgeFactor = ConstantInt::get(
2450 Type::getInt64Ty(*DAG.getContext()), FF);
2452 SDValue CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy());
2453 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
2454 CPIdx = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(), CPIdx, CstOffset);
2455 Alignment = std::min(Alignment, 4u);
2457 if (DestVT == MVT::f32)
2458 FudgeInReg = DAG.getLoad(MVT::f32, dl, DAG.getEntryNode(), CPIdx,
2459 MachinePointerInfo::getConstantPool(),
2460 false, false, Alignment);
2463 LegalizeOp(DAG.getExtLoad(ISD::EXTLOAD, dl, DestVT,
2464 DAG.getEntryNode(), CPIdx,
2465 MachinePointerInfo::getConstantPool(),
2466 MVT::f32, false, false, Alignment));
2469 return DAG.getNode(ISD::FADD, dl, DestVT, Tmp1, FudgeInReg);
2472 /// PromoteLegalINT_TO_FP - This function is responsible for legalizing a
2473 /// *INT_TO_FP operation of the specified operand when the target requests that
2474 /// we promote it. At this point, we know that the result and operand types are
2475 /// legal for the target, and that there is a legal UINT_TO_FP or SINT_TO_FP
2476 /// operation that takes a larger input.
2477 SDValue SelectionDAGLegalize::PromoteLegalINT_TO_FP(SDValue LegalOp,
2481 // First step, figure out the appropriate *INT_TO_FP operation to use.
2482 EVT NewInTy = LegalOp.getValueType();
2484 unsigned OpToUse = 0;
2486 // Scan for the appropriate larger type to use.
2488 NewInTy = (MVT::SimpleValueType)(NewInTy.getSimpleVT().SimpleTy+1);
2489 assert(NewInTy.isInteger() && "Ran out of possibilities!");
2491 // If the target supports SINT_TO_FP of this type, use it.
2492 if (TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, NewInTy)) {
2493 OpToUse = ISD::SINT_TO_FP;
2496 if (isSigned) continue;
2498 // If the target supports UINT_TO_FP of this type, use it.
2499 if (TLI.isOperationLegalOrCustom(ISD::UINT_TO_FP, NewInTy)) {
2500 OpToUse = ISD::UINT_TO_FP;
2504 // Otherwise, try a larger type.
2507 // Okay, we found the operation and type to use. Zero extend our input to the
2508 // desired type then run the operation on it.
2509 return DAG.getNode(OpToUse, dl, DestVT,
2510 DAG.getNode(isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND,
2511 dl, NewInTy, LegalOp));
2514 /// PromoteLegalFP_TO_INT - This function is responsible for legalizing a
2515 /// FP_TO_*INT operation of the specified operand when the target requests that
2516 /// we promote it. At this point, we know that the result and operand types are
2517 /// legal for the target, and that there is a legal FP_TO_UINT or FP_TO_SINT
2518 /// operation that returns a larger result.
2519 SDValue SelectionDAGLegalize::PromoteLegalFP_TO_INT(SDValue LegalOp,
2523 // First step, figure out the appropriate FP_TO*INT operation to use.
2524 EVT NewOutTy = DestVT;
2526 unsigned OpToUse = 0;
2528 // Scan for the appropriate larger type to use.
2530 NewOutTy = (MVT::SimpleValueType)(NewOutTy.getSimpleVT().SimpleTy+1);
2531 assert(NewOutTy.isInteger() && "Ran out of possibilities!");
2533 if (TLI.isOperationLegalOrCustom(ISD::FP_TO_SINT, NewOutTy)) {
2534 OpToUse = ISD::FP_TO_SINT;
2538 if (TLI.isOperationLegalOrCustom(ISD::FP_TO_UINT, NewOutTy)) {
2539 OpToUse = ISD::FP_TO_UINT;
2543 // Otherwise, try a larger type.
2547 // Okay, we found the operation and type to use.
2548 SDValue Operation = DAG.getNode(OpToUse, dl, NewOutTy, LegalOp);
2550 // Truncate the result of the extended FP_TO_*INT operation to the desired
2552 return DAG.getNode(ISD::TRUNCATE, dl, DestVT, Operation);
2555 /// ExpandBSWAP - Open code the operations for BSWAP of the specified operation.
2557 SDValue SelectionDAGLegalize::ExpandBSWAP(SDValue Op, DebugLoc dl) {
2558 EVT VT = Op.getValueType();
2559 EVT SHVT = TLI.getShiftAmountTy(VT);
2560 SDValue Tmp1, Tmp2, Tmp3, Tmp4, Tmp5, Tmp6, Tmp7, Tmp8;
2561 switch (VT.getSimpleVT().SimpleTy) {
2562 default: assert(0 && "Unhandled Expand type in BSWAP!");
2564 Tmp2 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, SHVT));
2565 Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, SHVT));
2566 return DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);
2568 Tmp4 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(24, SHVT));
2569 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, SHVT));
2570 Tmp2 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, SHVT));
2571 Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(24, SHVT));
2572 Tmp3 = DAG.getNode(ISD::AND, dl, VT, Tmp3, DAG.getConstant(0xFF0000, VT));
2573 Tmp2 = DAG.getNode(ISD::AND, dl, VT, Tmp2, DAG.getConstant(0xFF00, VT));
2574 Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp3);
2575 Tmp2 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp1);
2576 return DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp2);
2578 Tmp8 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(56, SHVT));
2579 Tmp7 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(40, SHVT));
2580 Tmp6 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(24, SHVT));
2581 Tmp5 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, SHVT));
2582 Tmp4 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, SHVT));
2583 Tmp3 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(24, SHVT));
2584 Tmp2 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(40, SHVT));
2585 Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(56, SHVT));
2586 Tmp7 = DAG.getNode(ISD::AND, dl, VT, Tmp7, DAG.getConstant(255ULL<<48, VT));
2587 Tmp6 = DAG.getNode(ISD::AND, dl, VT, Tmp6, DAG.getConstant(255ULL<<40, VT));
2588 Tmp5 = DAG.getNode(ISD::AND, dl, VT, Tmp5, DAG.getConstant(255ULL<<32, VT));
2589 Tmp4 = DAG.getNode(ISD::AND, dl, VT, Tmp4, DAG.getConstant(255ULL<<24, VT));
2590 Tmp3 = DAG.getNode(ISD::AND, dl, VT, Tmp3, DAG.getConstant(255ULL<<16, VT));
2591 Tmp2 = DAG.getNode(ISD::AND, dl, VT, Tmp2, DAG.getConstant(255ULL<<8 , VT));
2592 Tmp8 = DAG.getNode(ISD::OR, dl, VT, Tmp8, Tmp7);
2593 Tmp6 = DAG.getNode(ISD::OR, dl, VT, Tmp6, Tmp5);
2594 Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp3);
2595 Tmp2 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp1);
2596 Tmp8 = DAG.getNode(ISD::OR, dl, VT, Tmp8, Tmp6);
2597 Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp2);
2598 return DAG.getNode(ISD::OR, dl, VT, Tmp8, Tmp4);
2602 /// SplatByte - Distribute ByteVal over NumBits bits.
2603 // FIXME: Move this helper to a common place.
2604 static APInt SplatByte(unsigned NumBits, uint8_t ByteVal) {
2605 APInt Val = APInt(NumBits, ByteVal);
2607 for (unsigned i = NumBits; i > 8; i >>= 1) {
2608 Val = (Val << Shift) | Val;
2614 /// ExpandBitCount - Expand the specified bitcount instruction into operations.
2616 SDValue SelectionDAGLegalize::ExpandBitCount(unsigned Opc, SDValue Op,
2619 default: assert(0 && "Cannot expand this yet!");
2621 EVT VT = Op.getValueType();
2622 EVT ShVT = TLI.getShiftAmountTy(VT);
2623 unsigned Len = VT.getSizeInBits();
2625 assert(VT.isInteger() && Len <= 128 && Len % 8 == 0 &&
2626 "CTPOP not implemented for this type.");
2628 // This is the "best" algorithm from
2629 // http://graphics.stanford.edu/~seander/bithacks.html#CountBitsSetParallel
2631 SDValue Mask55 = DAG.getConstant(SplatByte(Len, 0x55), VT);
2632 SDValue Mask33 = DAG.getConstant(SplatByte(Len, 0x33), VT);
2633 SDValue Mask0F = DAG.getConstant(SplatByte(Len, 0x0F), VT);
2634 SDValue Mask01 = DAG.getConstant(SplatByte(Len, 0x01), VT);
2636 // v = v - ((v >> 1) & 0x55555555...)
2637 Op = DAG.getNode(ISD::SUB, dl, VT, Op,
2638 DAG.getNode(ISD::AND, dl, VT,
2639 DAG.getNode(ISD::SRL, dl, VT, Op,
2640 DAG.getConstant(1, ShVT)),
2642 // v = (v & 0x33333333...) + ((v >> 2) & 0x33333333...)
2643 Op = DAG.getNode(ISD::ADD, dl, VT,
2644 DAG.getNode(ISD::AND, dl, VT, Op, Mask33),
2645 DAG.getNode(ISD::AND, dl, VT,
2646 DAG.getNode(ISD::SRL, dl, VT, Op,
2647 DAG.getConstant(2, ShVT)),
2649 // v = (v + (v >> 4)) & 0x0F0F0F0F...
2650 Op = DAG.getNode(ISD::AND, dl, VT,
2651 DAG.getNode(ISD::ADD, dl, VT, Op,
2652 DAG.getNode(ISD::SRL, dl, VT, Op,
2653 DAG.getConstant(4, ShVT))),
2655 // v = (v * 0x01010101...) >> (Len - 8)
2656 Op = DAG.getNode(ISD::SRL, dl, VT,
2657 DAG.getNode(ISD::MUL, dl, VT, Op, Mask01),
2658 DAG.getConstant(Len - 8, ShVT));
2663 // for now, we do this:
2664 // x = x | (x >> 1);
2665 // x = x | (x >> 2);
2667 // x = x | (x >>16);
2668 // x = x | (x >>32); // for 64-bit input
2669 // return popcount(~x);
2671 // but see also: http://www.hackersdelight.org/HDcode/nlz.cc
2672 EVT VT = Op.getValueType();
2673 EVT ShVT = TLI.getShiftAmountTy(VT);
2674 unsigned len = VT.getSizeInBits();
2675 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) {
2676 SDValue Tmp3 = DAG.getConstant(1ULL << i, ShVT);
2677 Op = DAG.getNode(ISD::OR, dl, VT, Op,
2678 DAG.getNode(ISD::SRL, dl, VT, Op, Tmp3));
2680 Op = DAG.getNOT(dl, Op, VT);
2681 return DAG.getNode(ISD::CTPOP, dl, VT, Op);
2684 // for now, we use: { return popcount(~x & (x - 1)); }
2685 // unless the target has ctlz but not ctpop, in which case we use:
2686 // { return 32 - nlz(~x & (x-1)); }
2687 // see also http://www.hackersdelight.org/HDcode/ntz.cc
2688 EVT VT = Op.getValueType();
2689 SDValue Tmp3 = DAG.getNode(ISD::AND, dl, VT,
2690 DAG.getNOT(dl, Op, VT),
2691 DAG.getNode(ISD::SUB, dl, VT, Op,
2692 DAG.getConstant(1, VT)));
2693 // If ISD::CTLZ is legal and CTPOP isn't, then do that instead.
2694 if (!TLI.isOperationLegalOrCustom(ISD::CTPOP, VT) &&
2695 TLI.isOperationLegalOrCustom(ISD::CTLZ, VT))
2696 return DAG.getNode(ISD::SUB, dl, VT,
2697 DAG.getConstant(VT.getSizeInBits(), VT),
2698 DAG.getNode(ISD::CTLZ, dl, VT, Tmp3));
2699 return DAG.getNode(ISD::CTPOP, dl, VT, Tmp3);
2704 std::pair <SDValue, SDValue> SelectionDAGLegalize::ExpandAtomic(SDNode *Node) {
2705 unsigned Opc = Node->getOpcode();
2706 MVT VT = cast<AtomicSDNode>(Node)->getMemoryVT().getSimpleVT();
2711 llvm_unreachable("Unhandled atomic intrinsic Expand!");
2713 case ISD::ATOMIC_SWAP:
2714 switch (VT.SimpleTy) {
2715 default: llvm_unreachable("Unexpected value type for atomic!");
2716 case MVT::i8: LC = RTLIB::SYNC_LOCK_TEST_AND_SET_1; break;
2717 case MVT::i16: LC = RTLIB::SYNC_LOCK_TEST_AND_SET_2; break;
2718 case MVT::i32: LC = RTLIB::SYNC_LOCK_TEST_AND_SET_4; break;
2719 case MVT::i64: LC = RTLIB::SYNC_LOCK_TEST_AND_SET_8; break;
2722 case ISD::ATOMIC_CMP_SWAP:
2723 switch (VT.SimpleTy) {
2724 default: llvm_unreachable("Unexpected value type for atomic!");
2725 case MVT::i8: LC = RTLIB::SYNC_VAL_COMPARE_AND_SWAP_1; break;
2726 case MVT::i16: LC = RTLIB::SYNC_VAL_COMPARE_AND_SWAP_2; break;
2727 case MVT::i32: LC = RTLIB::SYNC_VAL_COMPARE_AND_SWAP_4; break;
2728 case MVT::i64: LC = RTLIB::SYNC_VAL_COMPARE_AND_SWAP_8; break;
2731 case ISD::ATOMIC_LOAD_ADD:
2732 switch (VT.SimpleTy) {
2733 default: llvm_unreachable("Unexpected value type for atomic!");
2734 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_ADD_1; break;
2735 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_ADD_2; break;
2736 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_ADD_4; break;
2737 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_ADD_8; break;
2740 case ISD::ATOMIC_LOAD_SUB:
2741 switch (VT.SimpleTy) {
2742 default: llvm_unreachable("Unexpected value type for atomic!");
2743 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_SUB_1; break;
2744 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_SUB_2; break;
2745 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_SUB_4; break;
2746 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_SUB_8; break;
2749 case ISD::ATOMIC_LOAD_AND:
2750 switch (VT.SimpleTy) {
2751 default: llvm_unreachable("Unexpected value type for atomic!");
2752 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_AND_1; break;
2753 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_AND_2; break;
2754 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_AND_4; break;
2755 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_AND_8; break;
2758 case ISD::ATOMIC_LOAD_OR:
2759 switch (VT.SimpleTy) {
2760 default: llvm_unreachable("Unexpected value type for atomic!");
2761 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_OR_1; break;
2762 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_OR_2; break;
2763 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_OR_4; break;
2764 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_OR_8; break;
2767 case ISD::ATOMIC_LOAD_XOR:
2768 switch (VT.SimpleTy) {
2769 default: llvm_unreachable("Unexpected value type for atomic!");
2770 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_XOR_1; break;
2771 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_XOR_2; break;
2772 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_XOR_4; break;
2773 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_XOR_8; break;
2776 case ISD::ATOMIC_LOAD_NAND:
2777 switch (VT.SimpleTy) {
2778 default: llvm_unreachable("Unexpected value type for atomic!");
2779 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_NAND_1; break;
2780 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_NAND_2; break;
2781 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_NAND_4; break;
2782 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_NAND_8; break;
2787 return ExpandChainLibCall(LC, Node, false);
2790 void SelectionDAGLegalize::ExpandNode(SDNode *Node,
2791 SmallVectorImpl<SDValue> &Results) {
2792 DebugLoc dl = Node->getDebugLoc();
2793 SDValue Tmp1, Tmp2, Tmp3, Tmp4;
2794 switch (Node->getOpcode()) {
2798 Tmp1 = ExpandBitCount(Node->getOpcode(), Node->getOperand(0), dl);
2799 Results.push_back(Tmp1);
2802 Results.push_back(ExpandBSWAP(Node->getOperand(0), dl));
2804 case ISD::FRAMEADDR:
2805 case ISD::RETURNADDR:
2806 case ISD::FRAME_TO_ARGS_OFFSET:
2807 Results.push_back(DAG.getConstant(0, Node->getValueType(0)));
2809 case ISD::FLT_ROUNDS_:
2810 Results.push_back(DAG.getConstant(1, Node->getValueType(0)));
2812 case ISD::EH_RETURN:
2816 case ISD::EH_SJLJ_LONGJMP:
2817 case ISD::EH_SJLJ_DISPATCHSETUP:
2818 // If the target didn't expand these, there's nothing to do, so just
2819 // preserve the chain and be done.
2820 Results.push_back(Node->getOperand(0));
2822 case ISD::EH_SJLJ_SETJMP:
2823 // If the target didn't expand this, just return 'zero' and preserve the
2825 Results.push_back(DAG.getConstant(0, MVT::i32));
2826 Results.push_back(Node->getOperand(0));
2828 case ISD::MEMBARRIER: {
2829 // If the target didn't lower this, lower it to '__sync_synchronize()' call
2830 TargetLowering::ArgListTy Args;
2831 std::pair<SDValue, SDValue> CallResult =
2832 TLI.LowerCallTo(Node->getOperand(0), Type::getVoidTy(*DAG.getContext()),
2833 false, false, false, false, 0, CallingConv::C,
2834 /*isTailCall=*/false,
2835 /*isReturnValueUsed=*/true,
2836 DAG.getExternalSymbol("__sync_synchronize",
2837 TLI.getPointerTy()),
2839 Results.push_back(CallResult.second);
2842 // By default, atomic intrinsics are marked Legal and lowered. Targets
2843 // which don't support them directly, however, may want libcalls, in which
2844 // case they mark them Expand, and we get here.
2845 case ISD::ATOMIC_SWAP:
2846 case ISD::ATOMIC_LOAD_ADD:
2847 case ISD::ATOMIC_LOAD_SUB:
2848 case ISD::ATOMIC_LOAD_AND:
2849 case ISD::ATOMIC_LOAD_OR:
2850 case ISD::ATOMIC_LOAD_XOR:
2851 case ISD::ATOMIC_LOAD_NAND:
2852 case ISD::ATOMIC_LOAD_MIN:
2853 case ISD::ATOMIC_LOAD_MAX:
2854 case ISD::ATOMIC_LOAD_UMIN:
2855 case ISD::ATOMIC_LOAD_UMAX:
2856 case ISD::ATOMIC_CMP_SWAP: {
2857 std::pair<SDValue, SDValue> Tmp = ExpandAtomic(Node);
2858 Results.push_back(Tmp.first);
2859 Results.push_back(Tmp.second);
2862 case ISD::DYNAMIC_STACKALLOC:
2863 ExpandDYNAMIC_STACKALLOC(Node, Results);
2865 case ISD::MERGE_VALUES:
2866 for (unsigned i = 0; i < Node->getNumValues(); i++)
2867 Results.push_back(Node->getOperand(i));
2870 EVT VT = Node->getValueType(0);
2872 Results.push_back(DAG.getConstant(0, VT));
2874 assert(VT.isFloatingPoint() && "Unknown value type!");
2875 Results.push_back(DAG.getConstantFP(0, VT));
2880 // If this operation is not supported, lower it to 'abort()' call
2881 TargetLowering::ArgListTy Args;
2882 std::pair<SDValue, SDValue> CallResult =
2883 TLI.LowerCallTo(Node->getOperand(0), Type::getVoidTy(*DAG.getContext()),
2884 false, false, false, false, 0, CallingConv::C,
2885 /*isTailCall=*/false,
2886 /*isReturnValueUsed=*/true,
2887 DAG.getExternalSymbol("abort", TLI.getPointerTy()),
2889 Results.push_back(CallResult.second);
2894 Tmp1 = EmitStackConvert(Node->getOperand(0), Node->getValueType(0),
2895 Node->getValueType(0), dl);
2896 Results.push_back(Tmp1);
2898 case ISD::FP_EXTEND:
2899 Tmp1 = EmitStackConvert(Node->getOperand(0),
2900 Node->getOperand(0).getValueType(),
2901 Node->getValueType(0), dl);
2902 Results.push_back(Tmp1);
2904 case ISD::SIGN_EXTEND_INREG: {
2905 // NOTE: we could fall back on load/store here too for targets without
2906 // SAR. However, it is doubtful that any exist.
2907 EVT ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT();
2908 EVT VT = Node->getValueType(0);
2909 EVT ShiftAmountTy = TLI.getShiftAmountTy(VT);
2912 unsigned BitsDiff = VT.getScalarType().getSizeInBits() -
2913 ExtraVT.getScalarType().getSizeInBits();
2914 SDValue ShiftCst = DAG.getConstant(BitsDiff, ShiftAmountTy);
2915 Tmp1 = DAG.getNode(ISD::SHL, dl, Node->getValueType(0),
2916 Node->getOperand(0), ShiftCst);
2917 Tmp1 = DAG.getNode(ISD::SRA, dl, Node->getValueType(0), Tmp1, ShiftCst);
2918 Results.push_back(Tmp1);
2921 case ISD::FP_ROUND_INREG: {
2922 // The only way we can lower this is to turn it into a TRUNCSTORE,
2923 // EXTLOAD pair, targeting a temporary location (a stack slot).
2925 // NOTE: there is a choice here between constantly creating new stack
2926 // slots and always reusing the same one. We currently always create
2927 // new ones, as reuse may inhibit scheduling.
2928 EVT ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT();
2929 Tmp1 = EmitStackConvert(Node->getOperand(0), ExtraVT,
2930 Node->getValueType(0), dl);
2931 Results.push_back(Tmp1);
2934 case ISD::SINT_TO_FP:
2935 case ISD::UINT_TO_FP:
2936 Tmp1 = ExpandLegalINT_TO_FP(Node->getOpcode() == ISD::SINT_TO_FP,
2937 Node->getOperand(0), Node->getValueType(0), dl);
2938 Results.push_back(Tmp1);
2940 case ISD::FP_TO_UINT: {
2941 SDValue True, False;
2942 EVT VT = Node->getOperand(0).getValueType();
2943 EVT NVT = Node->getValueType(0);
2944 APFloat apf(APInt::getNullValue(VT.getSizeInBits()));
2945 APInt x = APInt::getSignBit(NVT.getSizeInBits());
2946 (void)apf.convertFromAPInt(x, false, APFloat::rmNearestTiesToEven);
2947 Tmp1 = DAG.getConstantFP(apf, VT);
2948 Tmp2 = DAG.getSetCC(dl, TLI.getSetCCResultType(VT),
2949 Node->getOperand(0),
2951 True = DAG.getNode(ISD::FP_TO_SINT, dl, NVT, Node->getOperand(0));
2952 False = DAG.getNode(ISD::FP_TO_SINT, dl, NVT,
2953 DAG.getNode(ISD::FSUB, dl, VT,
2954 Node->getOperand(0), Tmp1));
2955 False = DAG.getNode(ISD::XOR, dl, NVT, False,
2956 DAG.getConstant(x, NVT));
2957 Tmp1 = DAG.getNode(ISD::SELECT, dl, NVT, Tmp2, True, False);
2958 Results.push_back(Tmp1);
2962 const Value *V = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
2963 EVT VT = Node->getValueType(0);
2964 Tmp1 = Node->getOperand(0);
2965 Tmp2 = Node->getOperand(1);
2966 unsigned Align = Node->getConstantOperandVal(3);
2968 SDValue VAListLoad = DAG.getLoad(TLI.getPointerTy(), dl, Tmp1, Tmp2,
2969 MachinePointerInfo(V), false, false, 0);
2970 SDValue VAList = VAListLoad;
2972 if (Align > TLI.getMinStackArgumentAlignment()) {
2973 assert(((Align & (Align-1)) == 0) && "Expected Align to be a power of 2");
2975 VAList = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(), VAList,
2976 DAG.getConstant(Align - 1,
2977 TLI.getPointerTy()));
2979 VAList = DAG.getNode(ISD::AND, dl, TLI.getPointerTy(), VAList,
2980 DAG.getConstant(-(int64_t)Align,
2981 TLI.getPointerTy()));
2984 // Increment the pointer, VAList, to the next vaarg
2985 Tmp3 = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(), VAList,
2986 DAG.getConstant(TLI.getTargetData()->
2987 getTypeAllocSize(VT.getTypeForEVT(*DAG.getContext())),
2988 TLI.getPointerTy()));
2989 // Store the incremented VAList to the legalized pointer
2990 Tmp3 = DAG.getStore(VAListLoad.getValue(1), dl, Tmp3, Tmp2,
2991 MachinePointerInfo(V), false, false, 0);
2992 // Load the actual argument out of the pointer VAList
2993 Results.push_back(DAG.getLoad(VT, dl, Tmp3, VAList, MachinePointerInfo(),
2995 Results.push_back(Results[0].getValue(1));
2999 // This defaults to loading a pointer from the input and storing it to the
3000 // output, returning the chain.
3001 const Value *VD = cast<SrcValueSDNode>(Node->getOperand(3))->getValue();
3002 const Value *VS = cast<SrcValueSDNode>(Node->getOperand(4))->getValue();
3003 Tmp1 = DAG.getLoad(TLI.getPointerTy(), dl, Node->getOperand(0),
3004 Node->getOperand(2), MachinePointerInfo(VS),
3006 Tmp1 = DAG.getStore(Tmp1.getValue(1), dl, Tmp1, Node->getOperand(1),
3007 MachinePointerInfo(VD), false, false, 0);
3008 Results.push_back(Tmp1);
3011 case ISD::EXTRACT_VECTOR_ELT:
3012 if (Node->getOperand(0).getValueType().getVectorNumElements() == 1)
3013 // This must be an access of the only element. Return it.
3014 Tmp1 = DAG.getNode(ISD::BITCAST, dl, Node->getValueType(0),
3015 Node->getOperand(0));
3017 Tmp1 = ExpandExtractFromVectorThroughStack(SDValue(Node, 0));
3018 Results.push_back(Tmp1);
3020 case ISD::EXTRACT_SUBVECTOR:
3021 Results.push_back(ExpandExtractFromVectorThroughStack(SDValue(Node, 0)));
3023 case ISD::INSERT_SUBVECTOR:
3024 Results.push_back(ExpandInsertToVectorThroughStack(SDValue(Node, 0)));
3026 case ISD::CONCAT_VECTORS: {
3027 Results.push_back(ExpandVectorBuildThroughStack(Node));
3030 case ISD::SCALAR_TO_VECTOR:
3031 Results.push_back(ExpandSCALAR_TO_VECTOR(Node));
3033 case ISD::INSERT_VECTOR_ELT:
3034 Results.push_back(ExpandINSERT_VECTOR_ELT(Node->getOperand(0),
3035 Node->getOperand(1),
3036 Node->getOperand(2), dl));
3038 case ISD::VECTOR_SHUFFLE: {
3039 SmallVector<int, 8> Mask;
3040 cast<ShuffleVectorSDNode>(Node)->getMask(Mask);
3042 EVT VT = Node->getValueType(0);
3043 EVT EltVT = VT.getVectorElementType();
3044 if (getTypeAction(EltVT) == Promote)
3045 EltVT = TLI.getTypeToTransformTo(*DAG.getContext(), EltVT);
3046 unsigned NumElems = VT.getVectorNumElements();
3047 SmallVector<SDValue, 8> Ops;
3048 for (unsigned i = 0; i != NumElems; ++i) {
3050 Ops.push_back(DAG.getUNDEF(EltVT));
3053 unsigned Idx = Mask[i];
3055 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT,
3056 Node->getOperand(0),
3057 DAG.getIntPtrConstant(Idx)));
3059 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT,
3060 Node->getOperand(1),
3061 DAG.getIntPtrConstant(Idx - NumElems)));
3063 Tmp1 = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &Ops[0], Ops.size());
3064 Results.push_back(Tmp1);
3067 case ISD::EXTRACT_ELEMENT: {
3068 EVT OpTy = Node->getOperand(0).getValueType();
3069 if (cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue()) {
3071 Tmp1 = DAG.getNode(ISD::SRL, dl, OpTy, Node->getOperand(0),
3072 DAG.getConstant(OpTy.getSizeInBits()/2,
3073 TLI.getShiftAmountTy(Node->getOperand(0).getValueType())));
3074 Tmp1 = DAG.getNode(ISD::TRUNCATE, dl, Node->getValueType(0), Tmp1);
3077 Tmp1 = DAG.getNode(ISD::TRUNCATE, dl, Node->getValueType(0),
3078 Node->getOperand(0));
3080 Results.push_back(Tmp1);
3083 case ISD::STACKSAVE:
3084 // Expand to CopyFromReg if the target set
3085 // StackPointerRegisterToSaveRestore.
3086 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) {
3087 Results.push_back(DAG.getCopyFromReg(Node->getOperand(0), dl, SP,
3088 Node->getValueType(0)));
3089 Results.push_back(Results[0].getValue(1));
3091 Results.push_back(DAG.getUNDEF(Node->getValueType(0)));
3092 Results.push_back(Node->getOperand(0));
3095 case ISD::STACKRESTORE:
3096 // Expand to CopyToReg if the target set
3097 // StackPointerRegisterToSaveRestore.
3098 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) {
3099 Results.push_back(DAG.getCopyToReg(Node->getOperand(0), dl, SP,
3100 Node->getOperand(1)));
3102 Results.push_back(Node->getOperand(0));
3105 case ISD::FCOPYSIGN:
3106 Results.push_back(ExpandFCOPYSIGN(Node));
3109 // Expand Y = FNEG(X) -> Y = SUB -0.0, X
3110 Tmp1 = DAG.getConstantFP(-0.0, Node->getValueType(0));
3111 Tmp1 = DAG.getNode(ISD::FSUB, dl, Node->getValueType(0), Tmp1,
3112 Node->getOperand(0));
3113 Results.push_back(Tmp1);
3116 // Expand Y = FABS(X) -> Y = (X >u 0.0) ? X : fneg(X).
3117 EVT VT = Node->getValueType(0);
3118 Tmp1 = Node->getOperand(0);
3119 Tmp2 = DAG.getConstantFP(0.0, VT);
3120 Tmp2 = DAG.getSetCC(dl, TLI.getSetCCResultType(Tmp1.getValueType()),
3121 Tmp1, Tmp2, ISD::SETUGT);
3122 Tmp3 = DAG.getNode(ISD::FNEG, dl, VT, Tmp1);
3123 Tmp1 = DAG.getNode(ISD::SELECT, dl, VT, Tmp2, Tmp1, Tmp3);
3124 Results.push_back(Tmp1);
3128 Results.push_back(ExpandFPLibCall(Node, RTLIB::SQRT_F32, RTLIB::SQRT_F64,
3129 RTLIB::SQRT_F80, RTLIB::SQRT_PPCF128));
3132 Results.push_back(ExpandFPLibCall(Node, RTLIB::SIN_F32, RTLIB::SIN_F64,
3133 RTLIB::SIN_F80, RTLIB::SIN_PPCF128));
3136 Results.push_back(ExpandFPLibCall(Node, RTLIB::COS_F32, RTLIB::COS_F64,
3137 RTLIB::COS_F80, RTLIB::COS_PPCF128));
3140 Results.push_back(ExpandFPLibCall(Node, RTLIB::LOG_F32, RTLIB::LOG_F64,
3141 RTLIB::LOG_F80, RTLIB::LOG_PPCF128));
3144 Results.push_back(ExpandFPLibCall(Node, RTLIB::LOG2_F32, RTLIB::LOG2_F64,
3145 RTLIB::LOG2_F80, RTLIB::LOG2_PPCF128));
3148 Results.push_back(ExpandFPLibCall(Node, RTLIB::LOG10_F32, RTLIB::LOG10_F64,
3149 RTLIB::LOG10_F80, RTLIB::LOG10_PPCF128));
3152 Results.push_back(ExpandFPLibCall(Node, RTLIB::EXP_F32, RTLIB::EXP_F64,
3153 RTLIB::EXP_F80, RTLIB::EXP_PPCF128));
3156 Results.push_back(ExpandFPLibCall(Node, RTLIB::EXP2_F32, RTLIB::EXP2_F64,
3157 RTLIB::EXP2_F80, RTLIB::EXP2_PPCF128));
3160 Results.push_back(ExpandFPLibCall(Node, RTLIB::TRUNC_F32, RTLIB::TRUNC_F64,
3161 RTLIB::TRUNC_F80, RTLIB::TRUNC_PPCF128));
3164 Results.push_back(ExpandFPLibCall(Node, RTLIB::FLOOR_F32, RTLIB::FLOOR_F64,
3165 RTLIB::FLOOR_F80, RTLIB::FLOOR_PPCF128));
3168 Results.push_back(ExpandFPLibCall(Node, RTLIB::CEIL_F32, RTLIB::CEIL_F64,
3169 RTLIB::CEIL_F80, RTLIB::CEIL_PPCF128));
3172 Results.push_back(ExpandFPLibCall(Node, RTLIB::RINT_F32, RTLIB::RINT_F64,
3173 RTLIB::RINT_F80, RTLIB::RINT_PPCF128));
3175 case ISD::FNEARBYINT:
3176 Results.push_back(ExpandFPLibCall(Node, RTLIB::NEARBYINT_F32,
3177 RTLIB::NEARBYINT_F64,
3178 RTLIB::NEARBYINT_F80,
3179 RTLIB::NEARBYINT_PPCF128));
3182 Results.push_back(ExpandFPLibCall(Node, RTLIB::POWI_F32, RTLIB::POWI_F64,
3183 RTLIB::POWI_F80, RTLIB::POWI_PPCF128));
3186 Results.push_back(ExpandFPLibCall(Node, RTLIB::POW_F32, RTLIB::POW_F64,
3187 RTLIB::POW_F80, RTLIB::POW_PPCF128));
3190 Results.push_back(ExpandFPLibCall(Node, RTLIB::DIV_F32, RTLIB::DIV_F64,
3191 RTLIB::DIV_F80, RTLIB::DIV_PPCF128));
3194 Results.push_back(ExpandFPLibCall(Node, RTLIB::REM_F32, RTLIB::REM_F64,
3195 RTLIB::REM_F80, RTLIB::REM_PPCF128));
3197 case ISD::FP16_TO_FP32:
3198 Results.push_back(ExpandLibCall(RTLIB::FPEXT_F16_F32, Node, false));
3200 case ISD::FP32_TO_FP16:
3201 Results.push_back(ExpandLibCall(RTLIB::FPROUND_F32_F16, Node, false));
3203 case ISD::ConstantFP: {
3204 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node);
3205 // Check to see if this FP immediate is already legal.
3206 // If this is a legal constant, turn it into a TargetConstantFP node.
3207 if (TLI.isFPImmLegal(CFP->getValueAPF(), Node->getValueType(0)))
3208 Results.push_back(SDValue(Node, 0));
3210 Results.push_back(ExpandConstantFP(CFP, true, DAG, TLI));
3213 case ISD::EHSELECTION: {
3214 unsigned Reg = TLI.getExceptionSelectorRegister();
3215 assert(Reg && "Can't expand to unknown register!");
3216 Results.push_back(DAG.getCopyFromReg(Node->getOperand(1), dl, Reg,
3217 Node->getValueType(0)));
3218 Results.push_back(Results[0].getValue(1));
3221 case ISD::EXCEPTIONADDR: {
3222 unsigned Reg = TLI.getExceptionAddressRegister();
3223 assert(Reg && "Can't expand to unknown register!");
3224 Results.push_back(DAG.getCopyFromReg(Node->getOperand(0), dl, Reg,
3225 Node->getValueType(0)));
3226 Results.push_back(Results[0].getValue(1));
3230 EVT VT = Node->getValueType(0);
3231 assert(TLI.isOperationLegalOrCustom(ISD::ADD, VT) &&
3232 TLI.isOperationLegalOrCustom(ISD::XOR, VT) &&
3233 "Don't know how to expand this subtraction!");
3234 Tmp1 = DAG.getNode(ISD::XOR, dl, VT, Node->getOperand(1),
3235 DAG.getConstant(APInt::getAllOnesValue(VT.getSizeInBits()), VT));
3236 Tmp1 = DAG.getNode(ISD::ADD, dl, VT, Tmp2, DAG.getConstant(1, VT));
3237 Results.push_back(DAG.getNode(ISD::ADD, dl, VT, Node->getOperand(0), Tmp1));
3242 EVT VT = Node->getValueType(0);
3243 SDVTList VTs = DAG.getVTList(VT, VT);
3244 bool isSigned = Node->getOpcode() == ISD::SREM;
3245 unsigned DivOpc = isSigned ? ISD::SDIV : ISD::UDIV;
3246 unsigned DivRemOpc = isSigned ? ISD::SDIVREM : ISD::UDIVREM;
3247 Tmp2 = Node->getOperand(0);
3248 Tmp3 = Node->getOperand(1);
3249 if (TLI.isOperationLegalOrCustom(DivRemOpc, VT) ||
3250 (isDivRemLibcallAvailable(Node, isSigned, TLI) &&
3251 UseDivRem(Node, isSigned, false))) {
3252 Tmp1 = DAG.getNode(DivRemOpc, dl, VTs, Tmp2, Tmp3).getValue(1);
3253 } else if (TLI.isOperationLegalOrCustom(DivOpc, VT)) {
3255 Tmp1 = DAG.getNode(DivOpc, dl, VT, Tmp2, Tmp3);
3256 Tmp1 = DAG.getNode(ISD::MUL, dl, VT, Tmp1, Tmp3);
3257 Tmp1 = DAG.getNode(ISD::SUB, dl, VT, Tmp2, Tmp1);
3258 } else if (isSigned)
3259 Tmp1 = ExpandIntLibCall(Node, true,
3261 RTLIB::SREM_I16, RTLIB::SREM_I32,
3262 RTLIB::SREM_I64, RTLIB::SREM_I128);
3264 Tmp1 = ExpandIntLibCall(Node, false,
3266 RTLIB::UREM_I16, RTLIB::UREM_I32,
3267 RTLIB::UREM_I64, RTLIB::UREM_I128);
3268 Results.push_back(Tmp1);
3273 bool isSigned = Node->getOpcode() == ISD::SDIV;
3274 unsigned DivRemOpc = isSigned ? ISD::SDIVREM : ISD::UDIVREM;
3275 EVT VT = Node->getValueType(0);
3276 SDVTList VTs = DAG.getVTList(VT, VT);
3277 if (TLI.isOperationLegalOrCustom(DivRemOpc, VT) ||
3278 (isDivRemLibcallAvailable(Node, isSigned, TLI) &&
3279 UseDivRem(Node, isSigned, true)))
3280 Tmp1 = DAG.getNode(DivRemOpc, dl, VTs, Node->getOperand(0),
3281 Node->getOperand(1));
3283 Tmp1 = ExpandIntLibCall(Node, true,
3285 RTLIB::SDIV_I16, RTLIB::SDIV_I32,
3286 RTLIB::SDIV_I64, RTLIB::SDIV_I128);
3288 Tmp1 = ExpandIntLibCall(Node, false,
3290 RTLIB::UDIV_I16, RTLIB::UDIV_I32,
3291 RTLIB::UDIV_I64, RTLIB::UDIV_I128);
3292 Results.push_back(Tmp1);
3297 unsigned ExpandOpcode = Node->getOpcode() == ISD::MULHU ? ISD::UMUL_LOHI :
3299 EVT VT = Node->getValueType(0);
3300 SDVTList VTs = DAG.getVTList(VT, VT);
3301 assert(TLI.isOperationLegalOrCustom(ExpandOpcode, VT) &&
3302 "If this wasn't legal, it shouldn't have been created!");
3303 Tmp1 = DAG.getNode(ExpandOpcode, dl, VTs, Node->getOperand(0),
3304 Node->getOperand(1));
3305 Results.push_back(Tmp1.getValue(1));
3310 // Expand into divrem libcall
3311 ExpandDivRemLibCall(Node, Results);
3314 EVT VT = Node->getValueType(0);
3315 SDVTList VTs = DAG.getVTList(VT, VT);
3316 // See if multiply or divide can be lowered using two-result operations.
3317 // We just need the low half of the multiply; try both the signed
3318 // and unsigned forms. If the target supports both SMUL_LOHI and
3319 // UMUL_LOHI, form a preference by checking which forms of plain
3320 // MULH it supports.
3321 bool HasSMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::SMUL_LOHI, VT);
3322 bool HasUMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::UMUL_LOHI, VT);
3323 bool HasMULHS = TLI.isOperationLegalOrCustom(ISD::MULHS, VT);
3324 bool HasMULHU = TLI.isOperationLegalOrCustom(ISD::MULHU, VT);
3325 unsigned OpToUse = 0;
3326 if (HasSMUL_LOHI && !HasMULHS) {
3327 OpToUse = ISD::SMUL_LOHI;
3328 } else if (HasUMUL_LOHI && !HasMULHU) {
3329 OpToUse = ISD::UMUL_LOHI;
3330 } else if (HasSMUL_LOHI) {
3331 OpToUse = ISD::SMUL_LOHI;
3332 } else if (HasUMUL_LOHI) {
3333 OpToUse = ISD::UMUL_LOHI;
3336 Results.push_back(DAG.getNode(OpToUse, dl, VTs, Node->getOperand(0),
3337 Node->getOperand(1)));
3340 Tmp1 = ExpandIntLibCall(Node, false,
3342 RTLIB::MUL_I16, RTLIB::MUL_I32,
3343 RTLIB::MUL_I64, RTLIB::MUL_I128);
3344 Results.push_back(Tmp1);
3349 SDValue LHS = Node->getOperand(0);
3350 SDValue RHS = Node->getOperand(1);
3351 SDValue Sum = DAG.getNode(Node->getOpcode() == ISD::SADDO ?
3352 ISD::ADD : ISD::SUB, dl, LHS.getValueType(),
3354 Results.push_back(Sum);
3355 EVT OType = Node->getValueType(1);
3357 SDValue Zero = DAG.getConstant(0, LHS.getValueType());
3359 // LHSSign -> LHS >= 0
3360 // RHSSign -> RHS >= 0
3361 // SumSign -> Sum >= 0
3364 // Overflow -> (LHSSign == RHSSign) && (LHSSign != SumSign)
3366 // Overflow -> (LHSSign != RHSSign) && (LHSSign != SumSign)
3368 SDValue LHSSign = DAG.getSetCC(dl, OType, LHS, Zero, ISD::SETGE);
3369 SDValue RHSSign = DAG.getSetCC(dl, OType, RHS, Zero, ISD::SETGE);
3370 SDValue SignsMatch = DAG.getSetCC(dl, OType, LHSSign, RHSSign,
3371 Node->getOpcode() == ISD::SADDO ?
3372 ISD::SETEQ : ISD::SETNE);
3374 SDValue SumSign = DAG.getSetCC(dl, OType, Sum, Zero, ISD::SETGE);
3375 SDValue SumSignNE = DAG.getSetCC(dl, OType, LHSSign, SumSign, ISD::SETNE);
3377 SDValue Cmp = DAG.getNode(ISD::AND, dl, OType, SignsMatch, SumSignNE);
3378 Results.push_back(Cmp);
3383 SDValue LHS = Node->getOperand(0);
3384 SDValue RHS = Node->getOperand(1);
3385 SDValue Sum = DAG.getNode(Node->getOpcode() == ISD::UADDO ?
3386 ISD::ADD : ISD::SUB, dl, LHS.getValueType(),
3388 Results.push_back(Sum);
3389 Results.push_back(DAG.getSetCC(dl, Node->getValueType(1), Sum, LHS,
3390 Node->getOpcode () == ISD::UADDO ?
3391 ISD::SETULT : ISD::SETUGT));
3396 EVT VT = Node->getValueType(0);
3397 EVT WideVT = EVT::getIntegerVT(*DAG.getContext(), VT.getSizeInBits() * 2);
3398 SDValue LHS = Node->getOperand(0);
3399 SDValue RHS = Node->getOperand(1);
3402 static const unsigned Ops[2][3] =
3403 { { ISD::MULHU, ISD::UMUL_LOHI, ISD::ZERO_EXTEND },
3404 { ISD::MULHS, ISD::SMUL_LOHI, ISD::SIGN_EXTEND }};
3405 bool isSigned = Node->getOpcode() == ISD::SMULO;
3406 if (TLI.isOperationLegalOrCustom(Ops[isSigned][0], VT)) {
3407 BottomHalf = DAG.getNode(ISD::MUL, dl, VT, LHS, RHS);
3408 TopHalf = DAG.getNode(Ops[isSigned][0], dl, VT, LHS, RHS);
3409 } else if (TLI.isOperationLegalOrCustom(Ops[isSigned][1], VT)) {
3410 BottomHalf = DAG.getNode(Ops[isSigned][1], dl, DAG.getVTList(VT, VT), LHS,
3412 TopHalf = BottomHalf.getValue(1);
3413 } else if (TLI.isTypeLegal(EVT::getIntegerVT(*DAG.getContext(),
3414 VT.getSizeInBits() * 2))) {
3415 LHS = DAG.getNode(Ops[isSigned][2], dl, WideVT, LHS);
3416 RHS = DAG.getNode(Ops[isSigned][2], dl, WideVT, RHS);
3417 Tmp1 = DAG.getNode(ISD::MUL, dl, WideVT, LHS, RHS);
3418 BottomHalf = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VT, Tmp1,
3419 DAG.getIntPtrConstant(0));
3420 TopHalf = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VT, Tmp1,
3421 DAG.getIntPtrConstant(1));
3423 // We can fall back to a libcall with an illegal type for the MUL if we
3424 // have a libcall big enough.
3425 // Also, we can fall back to a division in some cases, but that's a big
3426 // performance hit in the general case.
3427 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
3428 if (WideVT == MVT::i16)
3429 LC = RTLIB::MUL_I16;
3430 else if (WideVT == MVT::i32)
3431 LC = RTLIB::MUL_I32;
3432 else if (WideVT == MVT::i64)
3433 LC = RTLIB::MUL_I64;
3434 else if (WideVT == MVT::i128)
3435 LC = RTLIB::MUL_I128;
3436 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Cannot expand this operation!");
3438 // The high part is obtained by SRA'ing all but one of the bits of low
3440 unsigned LoSize = VT.getSizeInBits();
3441 SDValue HiLHS = DAG.getNode(ISD::SRA, dl, VT, RHS,
3442 DAG.getConstant(LoSize-1, TLI.getPointerTy()));
3443 SDValue HiRHS = DAG.getNode(ISD::SRA, dl, VT, LHS,
3444 DAG.getConstant(LoSize-1, TLI.getPointerTy()));
3446 // Here we're passing the 2 arguments explicitly as 4 arguments that are
3447 // pre-lowered to the correct types. This all depends upon WideVT not
3448 // being a legal type for the architecture and thus has to be split to
3450 SDValue Args[] = { LHS, HiLHS, RHS, HiRHS };
3451 SDValue Ret = ExpandLibCall(LC, WideVT, Args, 4, isSigned, dl);
3452 BottomHalf = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VT, Ret,
3453 DAG.getIntPtrConstant(0));
3454 TopHalf = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VT, Ret,
3455 DAG.getIntPtrConstant(1));
3459 Tmp1 = DAG.getConstant(VT.getSizeInBits() - 1,
3460 TLI.getShiftAmountTy(BottomHalf.getValueType()));
3461 Tmp1 = DAG.getNode(ISD::SRA, dl, VT, BottomHalf, Tmp1);
3462 TopHalf = DAG.getSetCC(dl, TLI.getSetCCResultType(VT), TopHalf, Tmp1,
3465 TopHalf = DAG.getSetCC(dl, TLI.getSetCCResultType(VT), TopHalf,
3466 DAG.getConstant(0, VT), ISD::SETNE);
3468 Results.push_back(BottomHalf);
3469 Results.push_back(TopHalf);
3472 case ISD::BUILD_PAIR: {
3473 EVT PairTy = Node->getValueType(0);
3474 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, PairTy, Node->getOperand(0));
3475 Tmp2 = DAG.getNode(ISD::ANY_EXTEND, dl, PairTy, Node->getOperand(1));
3476 Tmp2 = DAG.getNode(ISD::SHL, dl, PairTy, Tmp2,
3477 DAG.getConstant(PairTy.getSizeInBits()/2,
3478 TLI.getShiftAmountTy(PairTy)));
3479 Results.push_back(DAG.getNode(ISD::OR, dl, PairTy, Tmp1, Tmp2));
3483 Tmp1 = Node->getOperand(0);
3484 Tmp2 = Node->getOperand(1);
3485 Tmp3 = Node->getOperand(2);
3486 if (Tmp1.getOpcode() == ISD::SETCC) {
3487 Tmp1 = DAG.getSelectCC(dl, Tmp1.getOperand(0), Tmp1.getOperand(1),
3489 cast<CondCodeSDNode>(Tmp1.getOperand(2))->get());
3491 Tmp1 = DAG.getSelectCC(dl, Tmp1,
3492 DAG.getConstant(0, Tmp1.getValueType()),
3493 Tmp2, Tmp3, ISD::SETNE);
3495 Results.push_back(Tmp1);
3498 SDValue Chain = Node->getOperand(0);
3499 SDValue Table = Node->getOperand(1);
3500 SDValue Index = Node->getOperand(2);
3502 EVT PTy = TLI.getPointerTy();
3504 const TargetData &TD = *TLI.getTargetData();
3505 unsigned EntrySize =
3506 DAG.getMachineFunction().getJumpTableInfo()->getEntrySize(TD);
3508 Index = DAG.getNode(ISD::MUL, dl, PTy,
3509 Index, DAG.getConstant(EntrySize, PTy));
3510 SDValue Addr = DAG.getNode(ISD::ADD, dl, PTy, Index, Table);
3512 EVT MemVT = EVT::getIntegerVT(*DAG.getContext(), EntrySize * 8);
3513 SDValue LD = DAG.getExtLoad(ISD::SEXTLOAD, dl, PTy, Chain, Addr,
3514 MachinePointerInfo::getJumpTable(), MemVT,
3517 if (TM.getRelocationModel() == Reloc::PIC_) {
3518 // For PIC, the sequence is:
3519 // BRIND(load(Jumptable + index) + RelocBase)
3520 // RelocBase can be JumpTable, GOT or some sort of global base.
3521 Addr = DAG.getNode(ISD::ADD, dl, PTy, Addr,
3522 TLI.getPICJumpTableRelocBase(Table, DAG));
3524 Tmp1 = DAG.getNode(ISD::BRIND, dl, MVT::Other, LD.getValue(1), Addr);
3525 Results.push_back(Tmp1);
3529 // Expand brcond's setcc into its constituent parts and create a BR_CC
3531 Tmp1 = Node->getOperand(0);
3532 Tmp2 = Node->getOperand(1);
3533 if (Tmp2.getOpcode() == ISD::SETCC) {
3534 Tmp1 = DAG.getNode(ISD::BR_CC, dl, MVT::Other,
3535 Tmp1, Tmp2.getOperand(2),
3536 Tmp2.getOperand(0), Tmp2.getOperand(1),
3537 Node->getOperand(2));
3539 // We test only the i1 bit. Skip the AND if UNDEF.
3540 Tmp3 = (Tmp2.getOpcode() == ISD::UNDEF) ? Tmp2 :
3541 DAG.getNode(ISD::AND, dl, Tmp2.getValueType(), Tmp2,
3542 DAG.getConstant(1, Tmp2.getValueType()));
3543 Tmp1 = DAG.getNode(ISD::BR_CC, dl, MVT::Other, Tmp1,
3544 DAG.getCondCode(ISD::SETNE), Tmp3,
3545 DAG.getConstant(0, Tmp3.getValueType()),
3546 Node->getOperand(2));
3548 Results.push_back(Tmp1);
3551 Tmp1 = Node->getOperand(0);
3552 Tmp2 = Node->getOperand(1);
3553 Tmp3 = Node->getOperand(2);
3554 LegalizeSetCCCondCode(Node->getValueType(0), Tmp1, Tmp2, Tmp3, dl);
3556 // If we expanded the SETCC into an AND/OR, return the new node
3557 if (Tmp2.getNode() == 0) {
3558 Results.push_back(Tmp1);
3562 // Otherwise, SETCC for the given comparison type must be completely
3563 // illegal; expand it into a SELECT_CC.
3564 EVT VT = Node->getValueType(0);
3565 Tmp1 = DAG.getNode(ISD::SELECT_CC, dl, VT, Tmp1, Tmp2,
3566 DAG.getConstant(1, VT), DAG.getConstant(0, VT), Tmp3);
3567 Results.push_back(Tmp1);
3570 case ISD::SELECT_CC: {
3571 Tmp1 = Node->getOperand(0); // LHS
3572 Tmp2 = Node->getOperand(1); // RHS
3573 Tmp3 = Node->getOperand(2); // True
3574 Tmp4 = Node->getOperand(3); // False
3575 SDValue CC = Node->getOperand(4);
3577 LegalizeSetCCCondCode(TLI.getSetCCResultType(Tmp1.getValueType()),
3578 Tmp1, Tmp2, CC, dl);
3580 assert(!Tmp2.getNode() && "Can't legalize SELECT_CC with legal condition!");
3581 Tmp2 = DAG.getConstant(0, Tmp1.getValueType());
3582 CC = DAG.getCondCode(ISD::SETNE);
3583 Tmp1 = DAG.getNode(ISD::SELECT_CC, dl, Node->getValueType(0), Tmp1, Tmp2,
3585 Results.push_back(Tmp1);
3589 Tmp1 = Node->getOperand(0); // Chain
3590 Tmp2 = Node->getOperand(2); // LHS
3591 Tmp3 = Node->getOperand(3); // RHS
3592 Tmp4 = Node->getOperand(1); // CC
3594 LegalizeSetCCCondCode(TLI.getSetCCResultType(Tmp2.getValueType()),
3595 Tmp2, Tmp3, Tmp4, dl);
3596 assert(LastCALLSEQ.size() == 1 && "branch inside CALLSEQ_BEGIN/END?");
3597 setLastCALLSEQ(DAG.getEntryNode());
3599 assert(!Tmp3.getNode() && "Can't legalize BR_CC with legal condition!");
3600 Tmp3 = DAG.getConstant(0, Tmp2.getValueType());
3601 Tmp4 = DAG.getCondCode(ISD::SETNE);
3602 Tmp1 = DAG.getNode(ISD::BR_CC, dl, Node->getValueType(0), Tmp1, Tmp4, Tmp2,
3603 Tmp3, Node->getOperand(4));
3604 Results.push_back(Tmp1);
3607 case ISD::GLOBAL_OFFSET_TABLE:
3608 case ISD::GlobalAddress:
3609 case ISD::GlobalTLSAddress:
3610 case ISD::ExternalSymbol:
3611 case ISD::ConstantPool:
3612 case ISD::JumpTable:
3613 case ISD::INTRINSIC_W_CHAIN:
3614 case ISD::INTRINSIC_WO_CHAIN:
3615 case ISD::INTRINSIC_VOID:
3616 // FIXME: Custom lowering for these operations shouldn't return null!
3617 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
3618 Results.push_back(SDValue(Node, i));
3622 void SelectionDAGLegalize::PromoteNode(SDNode *Node,
3623 SmallVectorImpl<SDValue> &Results) {
3624 EVT OVT = Node->getValueType(0);
3625 if (Node->getOpcode() == ISD::UINT_TO_FP ||
3626 Node->getOpcode() == ISD::SINT_TO_FP ||
3627 Node->getOpcode() == ISD::SETCC) {
3628 OVT = Node->getOperand(0).getValueType();
3630 EVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
3631 DebugLoc dl = Node->getDebugLoc();
3632 SDValue Tmp1, Tmp2, Tmp3;
3633 switch (Node->getOpcode()) {
3637 // Zero extend the argument.
3638 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Node->getOperand(0));
3639 // Perform the larger operation.
3640 Tmp1 = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1);
3641 if (Node->getOpcode() == ISD::CTTZ) {
3642 //if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT)
3643 Tmp2 = DAG.getSetCC(dl, TLI.getSetCCResultType(NVT),
3644 Tmp1, DAG.getConstant(NVT.getSizeInBits(), NVT),
3646 Tmp1 = DAG.getNode(ISD::SELECT, dl, NVT, Tmp2,
3647 DAG.getConstant(OVT.getSizeInBits(), NVT), Tmp1);
3648 } else if (Node->getOpcode() == ISD::CTLZ) {
3649 // Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT))
3650 Tmp1 = DAG.getNode(ISD::SUB, dl, NVT, Tmp1,
3651 DAG.getConstant(NVT.getSizeInBits() -
3652 OVT.getSizeInBits(), NVT));
3654 Results.push_back(DAG.getNode(ISD::TRUNCATE, dl, OVT, Tmp1));
3657 unsigned DiffBits = NVT.getSizeInBits() - OVT.getSizeInBits();
3658 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Node->getOperand(0));
3659 Tmp1 = DAG.getNode(ISD::BSWAP, dl, NVT, Tmp1);
3660 Tmp1 = DAG.getNode(ISD::SRL, dl, NVT, Tmp1,
3661 DAG.getConstant(DiffBits, TLI.getShiftAmountTy(NVT)));
3662 Results.push_back(Tmp1);
3665 case ISD::FP_TO_UINT:
3666 case ISD::FP_TO_SINT:
3667 Tmp1 = PromoteLegalFP_TO_INT(Node->getOperand(0), Node->getValueType(0),
3668 Node->getOpcode() == ISD::FP_TO_SINT, dl);
3669 Results.push_back(Tmp1);
3671 case ISD::UINT_TO_FP:
3672 case ISD::SINT_TO_FP:
3673 Tmp1 = PromoteLegalINT_TO_FP(Node->getOperand(0), Node->getValueType(0),
3674 Node->getOpcode() == ISD::SINT_TO_FP, dl);
3675 Results.push_back(Tmp1);
3680 unsigned ExtOp, TruncOp;
3681 if (OVT.isVector()) {
3682 ExtOp = ISD::BITCAST;
3683 TruncOp = ISD::BITCAST;
3685 assert(OVT.isInteger() && "Cannot promote logic operation");
3686 ExtOp = ISD::ANY_EXTEND;
3687 TruncOp = ISD::TRUNCATE;
3689 // Promote each of the values to the new type.
3690 Tmp1 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(0));
3691 Tmp2 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(1));
3692 // Perform the larger operation, then convert back
3693 Tmp1 = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1, Tmp2);
3694 Results.push_back(DAG.getNode(TruncOp, dl, OVT, Tmp1));
3698 unsigned ExtOp, TruncOp;
3699 if (Node->getValueType(0).isVector()) {
3700 ExtOp = ISD::BITCAST;
3701 TruncOp = ISD::BITCAST;
3702 } else if (Node->getValueType(0).isInteger()) {
3703 ExtOp = ISD::ANY_EXTEND;
3704 TruncOp = ISD::TRUNCATE;
3706 ExtOp = ISD::FP_EXTEND;
3707 TruncOp = ISD::FP_ROUND;
3709 Tmp1 = Node->getOperand(0);
3710 // Promote each of the values to the new type.
3711 Tmp2 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(1));
3712 Tmp3 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(2));
3713 // Perform the larger operation, then round down.
3714 Tmp1 = DAG.getNode(ISD::SELECT, dl, NVT, Tmp1, Tmp2, Tmp3);
3715 if (TruncOp != ISD::FP_ROUND)
3716 Tmp1 = DAG.getNode(TruncOp, dl, Node->getValueType(0), Tmp1);
3718 Tmp1 = DAG.getNode(TruncOp, dl, Node->getValueType(0), Tmp1,
3719 DAG.getIntPtrConstant(0));
3720 Results.push_back(Tmp1);
3723 case ISD::VECTOR_SHUFFLE: {
3724 SmallVector<int, 8> Mask;
3725 cast<ShuffleVectorSDNode>(Node)->getMask(Mask);
3727 // Cast the two input vectors.
3728 Tmp1 = DAG.getNode(ISD::BITCAST, dl, NVT, Node->getOperand(0));
3729 Tmp2 = DAG.getNode(ISD::BITCAST, dl, NVT, Node->getOperand(1));
3731 // Convert the shuffle mask to the right # elements.
3732 Tmp1 = ShuffleWithNarrowerEltType(NVT, OVT, dl, Tmp1, Tmp2, Mask);
3733 Tmp1 = DAG.getNode(ISD::BITCAST, dl, OVT, Tmp1);
3734 Results.push_back(Tmp1);
3738 unsigned ExtOp = ISD::FP_EXTEND;
3739 if (NVT.isInteger()) {
3740 ISD::CondCode CCCode =
3741 cast<CondCodeSDNode>(Node->getOperand(2))->get();
3742 ExtOp = isSignedIntSetCC(CCCode) ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
3744 Tmp1 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(0));
3745 Tmp2 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(1));
3746 Results.push_back(DAG.getNode(ISD::SETCC, dl, Node->getValueType(0),
3747 Tmp1, Tmp2, Node->getOperand(2)));
3753 // SelectionDAG::Legalize - This is the entry point for the file.
3755 void SelectionDAG::Legalize(CodeGenOpt::Level OptLevel) {
3756 /// run - This is the main entry point to this class.
3758 SelectionDAGLegalize(*this, OptLevel).LegalizeDAG();