1 //===-- LegalizeDAG.cpp - Implement SelectionDAG::Legalize ----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the SelectionDAG::Legalize method.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/Analysis/DebugInfo.h"
15 #include "llvm/CodeGen/Analysis.h"
16 #include "llvm/CodeGen/MachineFunction.h"
17 #include "llvm/CodeGen/MachineJumpTableInfo.h"
18 #include "llvm/CodeGen/SelectionDAG.h"
19 #include "llvm/Target/TargetFrameLowering.h"
20 #include "llvm/Target/TargetLowering.h"
21 #include "llvm/Target/TargetData.h"
22 #include "llvm/Target/TargetMachine.h"
23 #include "llvm/CallingConv.h"
24 #include "llvm/Constants.h"
25 #include "llvm/DerivedTypes.h"
26 #include "llvm/LLVMContext.h"
27 #include "llvm/Support/Debug.h"
28 #include "llvm/Support/ErrorHandling.h"
29 #include "llvm/Support/MathExtras.h"
30 #include "llvm/Support/raw_ostream.h"
31 #include "llvm/ADT/DenseMap.h"
32 #include "llvm/ADT/SmallVector.h"
33 #include "llvm/ADT/SmallPtrSet.h"
36 //===----------------------------------------------------------------------===//
37 /// SelectionDAGLegalize - This takes an arbitrary SelectionDAG as input and
38 /// hacks on it until the target machine can handle it. This involves
39 /// eliminating value sizes the machine cannot handle (promoting small sizes to
40 /// large sizes or splitting up large values into small values) as well as
41 /// eliminating operations the machine cannot handle.
43 /// This code also does a small amount of optimization and recognition of idioms
44 /// as part of its processing. For example, if a target does not support a
45 /// 'setcc' instruction efficiently, but does support 'brcc' instruction, this
46 /// will attempt merge setcc and brc instructions into brcc's.
49 class SelectionDAGLegalize {
50 const TargetMachine &TM;
51 const TargetLowering &TLI;
54 // Libcall insertion helpers.
56 /// LastCALLSEQ - This keeps track of the CALLSEQ_END node that has been
57 /// legalized. We use this to ensure that calls are properly serialized
58 /// against each other, including inserted libcalls.
59 SmallVector<SDValue, 8> LastCALLSEQ;
62 Legal, // The target natively supports this operation.
63 Promote, // This operation should be executed in a larger type.
64 Expand // Try to expand this to other ops, otherwise use a libcall.
67 /// LegalizedNodes - For nodes that are of legal width, and that have more
68 /// than one use, this map indicates what regularized operand to use. This
69 /// allows us to avoid legalizing the same thing more than once.
70 DenseMap<SDValue, SDValue> LegalizedNodes;
72 void AddLegalizedOperand(SDValue From, SDValue To) {
73 LegalizedNodes.insert(std::make_pair(From, To));
74 // If someone requests legalization of the new node, return itself.
76 LegalizedNodes.insert(std::make_pair(To, To));
78 // Transfer SDDbgValues.
79 DAG.TransferDbgValues(From, To);
83 explicit SelectionDAGLegalize(SelectionDAG &DAG);
88 /// LegalizeOp - Return a legal replacement for the given operation, with
89 /// all legal operands.
90 SDValue LegalizeOp(SDValue O);
92 SDValue OptimizeFloatStore(StoreSDNode *ST);
94 /// PerformInsertVectorEltInMemory - Some target cannot handle a variable
95 /// insertion index for the INSERT_VECTOR_ELT instruction. In this case, it
96 /// is necessary to spill the vector being inserted into to memory, perform
97 /// the insert there, and then read the result back.
98 SDValue PerformInsertVectorEltInMemory(SDValue Vec, SDValue Val,
99 SDValue Idx, DebugLoc dl);
100 SDValue ExpandINSERT_VECTOR_ELT(SDValue Vec, SDValue Val,
101 SDValue Idx, DebugLoc dl);
103 /// ShuffleWithNarrowerEltType - Return a vector shuffle operation which
104 /// performs the same shuffe in terms of order or result bytes, but on a type
105 /// whose vector element type is narrower than the original shuffle type.
106 /// e.g. <v4i32> <0, 1, 0, 1> -> v8i16 <0, 1, 2, 3, 0, 1, 2, 3>
107 SDValue ShuffleWithNarrowerEltType(EVT NVT, EVT VT, DebugLoc dl,
108 SDValue N1, SDValue N2,
109 SmallVectorImpl<int> &Mask) const;
111 bool LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest,
112 SmallPtrSet<SDNode*, 32> &NodesLeadingTo);
114 void LegalizeSetCCCondCode(EVT VT, SDValue &LHS, SDValue &RHS, SDValue &CC,
117 SDValue ExpandLibCall(RTLIB::Libcall LC, SDNode *Node, bool isSigned);
118 SDValue ExpandLibCall(RTLIB::Libcall LC, EVT RetVT, const SDValue *Ops,
119 unsigned NumOps, bool isSigned, DebugLoc dl);
121 std::pair<SDValue, SDValue> ExpandChainLibCall(RTLIB::Libcall LC,
122 SDNode *Node, bool isSigned);
123 SDValue ExpandFPLibCall(SDNode *Node, RTLIB::Libcall Call_F32,
124 RTLIB::Libcall Call_F64, RTLIB::Libcall Call_F80,
125 RTLIB::Libcall Call_PPCF128);
126 SDValue ExpandIntLibCall(SDNode *Node, bool isSigned,
127 RTLIB::Libcall Call_I8,
128 RTLIB::Libcall Call_I16,
129 RTLIB::Libcall Call_I32,
130 RTLIB::Libcall Call_I64,
131 RTLIB::Libcall Call_I128);
132 void ExpandDivRemLibCall(SDNode *Node, SmallVectorImpl<SDValue> &Results);
134 SDValue EmitStackConvert(SDValue SrcOp, EVT SlotVT, EVT DestVT, DebugLoc dl);
135 SDValue ExpandBUILD_VECTOR(SDNode *Node);
136 SDValue ExpandSCALAR_TO_VECTOR(SDNode *Node);
137 void ExpandDYNAMIC_STACKALLOC(SDNode *Node,
138 SmallVectorImpl<SDValue> &Results);
139 SDValue ExpandFCOPYSIGN(SDNode *Node);
140 SDValue ExpandLegalINT_TO_FP(bool isSigned, SDValue LegalOp, EVT DestVT,
142 SDValue PromoteLegalINT_TO_FP(SDValue LegalOp, EVT DestVT, bool isSigned,
144 SDValue PromoteLegalFP_TO_INT(SDValue LegalOp, EVT DestVT, bool isSigned,
147 SDValue ExpandBSWAP(SDValue Op, DebugLoc dl);
148 SDValue ExpandBitCount(unsigned Opc, SDValue Op, DebugLoc dl);
150 SDValue ExpandExtractFromVectorThroughStack(SDValue Op);
151 SDValue ExpandInsertToVectorThroughStack(SDValue Op);
152 SDValue ExpandVectorBuildThroughStack(SDNode* Node);
154 std::pair<SDValue, SDValue> ExpandAtomic(SDNode *Node);
156 void ExpandNode(SDNode *Node, SmallVectorImpl<SDValue> &Results);
157 void PromoteNode(SDNode *Node, SmallVectorImpl<SDValue> &Results);
159 SDValue getLastCALLSEQ() { return LastCALLSEQ.back(); }
160 void setLastCALLSEQ(const SDValue s) { LastCALLSEQ.back() = s; }
161 void pushLastCALLSEQ(SDValue s) {
162 LastCALLSEQ.push_back(s);
164 void popLastCALLSEQ() {
165 LastCALLSEQ.pop_back();
170 /// ShuffleWithNarrowerEltType - Return a vector shuffle operation which
171 /// performs the same shuffe in terms of order or result bytes, but on a type
172 /// whose vector element type is narrower than the original shuffle type.
173 /// e.g. <v4i32> <0, 1, 0, 1> -> v8i16 <0, 1, 2, 3, 0, 1, 2, 3>
175 SelectionDAGLegalize::ShuffleWithNarrowerEltType(EVT NVT, EVT VT, DebugLoc dl,
176 SDValue N1, SDValue N2,
177 SmallVectorImpl<int> &Mask) const {
178 unsigned NumMaskElts = VT.getVectorNumElements();
179 unsigned NumDestElts = NVT.getVectorNumElements();
180 unsigned NumEltsGrowth = NumDestElts / NumMaskElts;
182 assert(NumEltsGrowth && "Cannot promote to vector type with fewer elts!");
184 if (NumEltsGrowth == 1)
185 return DAG.getVectorShuffle(NVT, dl, N1, N2, &Mask[0]);
187 SmallVector<int, 8> NewMask;
188 for (unsigned i = 0; i != NumMaskElts; ++i) {
190 for (unsigned j = 0; j != NumEltsGrowth; ++j) {
192 NewMask.push_back(-1);
194 NewMask.push_back(Idx * NumEltsGrowth + j);
197 assert(NewMask.size() == NumDestElts && "Non-integer NumEltsGrowth?");
198 assert(TLI.isShuffleMaskLegal(NewMask, NVT) && "Shuffle not legal?");
199 return DAG.getVectorShuffle(NVT, dl, N1, N2, &NewMask[0]);
202 SelectionDAGLegalize::SelectionDAGLegalize(SelectionDAG &dag)
203 : TM(dag.getTarget()), TLI(dag.getTargetLoweringInfo()),
207 void SelectionDAGLegalize::LegalizeDAG() {
208 pushLastCALLSEQ(DAG.getEntryNode());
210 // The legalize process is inherently a bottom-up recursive process (users
211 // legalize their uses before themselves). Given infinite stack space, we
212 // could just start legalizing on the root and traverse the whole graph. In
213 // practice however, this causes us to run out of stack space on large basic
214 // blocks. To avoid this problem, compute an ordering of the nodes where each
215 // node is only legalized after all of its operands are legalized.
216 DAG.AssignTopologicalOrder();
217 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(),
218 E = prior(DAG.allnodes_end()); I != llvm::next(E); ++I)
219 LegalizeOp(SDValue(I, 0));
221 // Finally, it's possible the root changed. Get the new root.
222 SDValue OldRoot = DAG.getRoot();
223 assert(LegalizedNodes.count(OldRoot) && "Root didn't get legalized?");
224 DAG.setRoot(LegalizedNodes[OldRoot]);
226 LegalizedNodes.clear();
228 // Remove dead nodes now.
229 DAG.RemoveDeadNodes();
233 /// FindCallEndFromCallStart - Given a chained node that is part of a call
234 /// sequence, find the CALLSEQ_END node that terminates the call sequence.
235 static SDNode *FindCallEndFromCallStart(SDNode *Node, int depth = 0) {
236 int next_depth = depth;
237 if (Node->getOpcode() == ISD::CALLSEQ_START)
238 next_depth = depth + 1;
239 if (Node->getOpcode() == ISD::CALLSEQ_END) {
240 assert(depth > 0 && "negative depth!");
244 next_depth = depth - 1;
246 if (Node->use_empty())
247 return 0; // No CallSeqEnd
249 // The chain is usually at the end.
250 SDValue TheChain(Node, Node->getNumValues()-1);
251 if (TheChain.getValueType() != MVT::Other) {
252 // Sometimes it's at the beginning.
253 TheChain = SDValue(Node, 0);
254 if (TheChain.getValueType() != MVT::Other) {
255 // Otherwise, hunt for it.
256 for (unsigned i = 1, e = Node->getNumValues(); i != e; ++i)
257 if (Node->getValueType(i) == MVT::Other) {
258 TheChain = SDValue(Node, i);
262 // Otherwise, we walked into a node without a chain.
263 if (TheChain.getValueType() != MVT::Other)
268 for (SDNode::use_iterator UI = Node->use_begin(),
269 E = Node->use_end(); UI != E; ++UI) {
271 // Make sure to only follow users of our token chain.
273 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i)
274 if (User->getOperand(i) == TheChain)
275 if (SDNode *Result = FindCallEndFromCallStart(User, next_depth))
281 /// FindCallStartFromCallEnd - Given a chained node that is part of a call
282 /// sequence, find the CALLSEQ_START node that initiates the call sequence.
283 static SDNode *FindCallStartFromCallEnd(SDNode *Node) {
285 assert(Node && "Didn't find callseq_start for a call??");
286 while (Node->getOpcode() != ISD::CALLSEQ_START || nested) {
287 Node = Node->getOperand(0).getNode();
288 assert(Node->getOperand(0).getValueType() == MVT::Other &&
289 "Node doesn't have a token chain argument!");
290 switch (Node->getOpcode()) {
293 case ISD::CALLSEQ_START:
296 Node = Node->getOperand(0).getNode();
299 case ISD::CALLSEQ_END:
304 return (Node->getOpcode() == ISD::CALLSEQ_START) ? Node : 0;
307 /// LegalizeAllNodesNotLeadingTo - Recursively walk the uses of N, looking to
308 /// see if any uses can reach Dest. If no dest operands can get to dest,
309 /// legalize them, legalize ourself, and return false, otherwise, return true.
311 /// Keep track of the nodes we fine that actually do lead to Dest in
312 /// NodesLeadingTo. This avoids retraversing them exponential number of times.
314 bool SelectionDAGLegalize::LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest,
315 SmallPtrSet<SDNode*, 32> &NodesLeadingTo) {
316 if (N == Dest) return true; // N certainly leads to Dest :)
318 // If we've already processed this node and it does lead to Dest, there is no
319 // need to reprocess it.
320 if (NodesLeadingTo.count(N)) return true;
322 // If the first result of this node has been already legalized, then it cannot
324 if (LegalizedNodes.count(SDValue(N, 0))) return false;
326 // Okay, this node has not already been legalized. Check and legalize all
327 // operands. If none lead to Dest, then we can legalize this node.
328 bool OperandsLeadToDest = false;
329 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
330 OperandsLeadToDest |= // If an operand leads to Dest, so do we.
331 LegalizeAllNodesNotLeadingTo(N->getOperand(i).getNode(), Dest,
334 if (OperandsLeadToDest) {
335 NodesLeadingTo.insert(N);
339 // Okay, this node looks safe, legalize it and return false.
340 LegalizeOp(SDValue(N, 0));
344 /// ExpandConstantFP - Expands the ConstantFP node to an integer constant or
345 /// a load from the constant pool.
346 static SDValue ExpandConstantFP(ConstantFPSDNode *CFP, bool UseCP,
347 SelectionDAG &DAG, const TargetLowering &TLI) {
349 DebugLoc dl = CFP->getDebugLoc();
351 // If a FP immediate is precise when represented as a float and if the
352 // target can do an extending load from float to double, we put it into
353 // the constant pool as a float, even if it's is statically typed as a
354 // double. This shrinks FP constants and canonicalizes them for targets where
355 // an FP extending load is the same cost as a normal load (such as on the x87
356 // fp stack or PPC FP unit).
357 EVT VT = CFP->getValueType(0);
358 ConstantFP *LLVMC = const_cast<ConstantFP*>(CFP->getConstantFPValue());
360 assert((VT == MVT::f64 || VT == MVT::f32) && "Invalid type expansion");
361 return DAG.getConstant(LLVMC->getValueAPF().bitcastToAPInt(),
362 (VT == MVT::f64) ? MVT::i64 : MVT::i32);
367 while (SVT != MVT::f32) {
368 SVT = (MVT::SimpleValueType)(SVT.getSimpleVT().SimpleTy - 1);
369 if (ConstantFPSDNode::isValueValidForType(SVT, CFP->getValueAPF()) &&
370 // Only do this if the target has a native EXTLOAD instruction from
372 TLI.isLoadExtLegal(ISD::EXTLOAD, SVT) &&
373 TLI.ShouldShrinkFPConstant(OrigVT)) {
374 const Type *SType = SVT.getTypeForEVT(*DAG.getContext());
375 LLVMC = cast<ConstantFP>(ConstantExpr::getFPTrunc(LLVMC, SType));
381 SDValue CPIdx = DAG.getConstantPool(LLVMC, TLI.getPointerTy());
382 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
384 return DAG.getExtLoad(ISD::EXTLOAD, dl, OrigVT,
386 CPIdx, MachinePointerInfo::getConstantPool(),
387 VT, false, false, Alignment);
388 return DAG.getLoad(OrigVT, dl, DAG.getEntryNode(), CPIdx,
389 MachinePointerInfo::getConstantPool(), false, false,
393 /// ExpandUnalignedStore - Expands an unaligned store to 2 half-size stores.
395 SDValue ExpandUnalignedStore(StoreSDNode *ST, SelectionDAG &DAG,
396 const TargetLowering &TLI) {
397 SDValue Chain = ST->getChain();
398 SDValue Ptr = ST->getBasePtr();
399 SDValue Val = ST->getValue();
400 EVT VT = Val.getValueType();
401 int Alignment = ST->getAlignment();
402 DebugLoc dl = ST->getDebugLoc();
403 if (ST->getMemoryVT().isFloatingPoint() ||
404 ST->getMemoryVT().isVector()) {
405 EVT intVT = EVT::getIntegerVT(*DAG.getContext(), VT.getSizeInBits());
406 if (TLI.isTypeLegal(intVT)) {
407 // Expand to a bitconvert of the value to the integer type of the
408 // same size, then a (misaligned) int store.
409 // FIXME: Does not handle truncating floating point stores!
410 SDValue Result = DAG.getNode(ISD::BITCAST, dl, intVT, Val);
411 return DAG.getStore(Chain, dl, Result, Ptr, ST->getPointerInfo(),
412 ST->isVolatile(), ST->isNonTemporal(), Alignment);
414 // Do a (aligned) store to a stack slot, then copy from the stack slot
415 // to the final destination using (unaligned) integer loads and stores.
416 EVT StoredVT = ST->getMemoryVT();
418 TLI.getRegisterType(*DAG.getContext(),
419 EVT::getIntegerVT(*DAG.getContext(),
420 StoredVT.getSizeInBits()));
421 unsigned StoredBytes = StoredVT.getSizeInBits() / 8;
422 unsigned RegBytes = RegVT.getSizeInBits() / 8;
423 unsigned NumRegs = (StoredBytes + RegBytes - 1) / RegBytes;
425 // Make sure the stack slot is also aligned for the register type.
426 SDValue StackPtr = DAG.CreateStackTemporary(StoredVT, RegVT);
428 // Perform the original store, only redirected to the stack slot.
429 SDValue Store = DAG.getTruncStore(Chain, dl,
430 Val, StackPtr, MachinePointerInfo(),
431 StoredVT, false, false, 0);
432 SDValue Increment = DAG.getConstant(RegBytes, TLI.getPointerTy());
433 SmallVector<SDValue, 8> Stores;
436 // Do all but one copies using the full register width.
437 for (unsigned i = 1; i < NumRegs; i++) {
438 // Load one integer register's worth from the stack slot.
439 SDValue Load = DAG.getLoad(RegVT, dl, Store, StackPtr,
440 MachinePointerInfo(),
442 // Store it to the final location. Remember the store.
443 Stores.push_back(DAG.getStore(Load.getValue(1), dl, Load, Ptr,
444 ST->getPointerInfo().getWithOffset(Offset),
445 ST->isVolatile(), ST->isNonTemporal(),
446 MinAlign(ST->getAlignment(), Offset)));
447 // Increment the pointers.
449 StackPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr,
451 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
454 // The last store may be partial. Do a truncating store. On big-endian
455 // machines this requires an extending load from the stack slot to ensure
456 // that the bits are in the right place.
457 EVT MemVT = EVT::getIntegerVT(*DAG.getContext(),
458 8 * (StoredBytes - Offset));
460 // Load from the stack slot.
461 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, RegVT, Store, StackPtr,
462 MachinePointerInfo(),
463 MemVT, false, false, 0);
465 Stores.push_back(DAG.getTruncStore(Load.getValue(1), dl, Load, Ptr,
467 .getWithOffset(Offset),
468 MemVT, ST->isVolatile(),
470 MinAlign(ST->getAlignment(), Offset)));
471 // The order of the stores doesn't matter - say it with a TokenFactor.
472 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Stores[0],
475 assert(ST->getMemoryVT().isInteger() &&
476 !ST->getMemoryVT().isVector() &&
477 "Unaligned store of unknown type.");
478 // Get the half-size VT
479 EVT NewStoredVT = ST->getMemoryVT().getHalfSizedIntegerVT(*DAG.getContext());
480 int NumBits = NewStoredVT.getSizeInBits();
481 int IncrementSize = NumBits / 8;
483 // Divide the stored value in two parts.
484 SDValue ShiftAmount = DAG.getConstant(NumBits,
485 TLI.getShiftAmountTy(Val.getValueType()));
487 SDValue Hi = DAG.getNode(ISD::SRL, dl, VT, Val, ShiftAmount);
489 // Store the two parts
490 SDValue Store1, Store2;
491 Store1 = DAG.getTruncStore(Chain, dl, TLI.isLittleEndian()?Lo:Hi, Ptr,
492 ST->getPointerInfo(), NewStoredVT,
493 ST->isVolatile(), ST->isNonTemporal(), Alignment);
494 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
495 DAG.getConstant(IncrementSize, TLI.getPointerTy()));
496 Alignment = MinAlign(Alignment, IncrementSize);
497 Store2 = DAG.getTruncStore(Chain, dl, TLI.isLittleEndian()?Hi:Lo, Ptr,
498 ST->getPointerInfo().getWithOffset(IncrementSize),
499 NewStoredVT, ST->isVolatile(), ST->isNonTemporal(),
502 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Store1, Store2);
505 /// ExpandUnalignedLoad - Expands an unaligned load to 2 half-size loads.
507 SDValue ExpandUnalignedLoad(LoadSDNode *LD, SelectionDAG &DAG,
508 const TargetLowering &TLI) {
509 SDValue Chain = LD->getChain();
510 SDValue Ptr = LD->getBasePtr();
511 EVT VT = LD->getValueType(0);
512 EVT LoadedVT = LD->getMemoryVT();
513 DebugLoc dl = LD->getDebugLoc();
514 if (VT.isFloatingPoint() || VT.isVector()) {
515 EVT intVT = EVT::getIntegerVT(*DAG.getContext(), LoadedVT.getSizeInBits());
516 if (TLI.isTypeLegal(intVT)) {
517 // Expand to a (misaligned) integer load of the same size,
518 // then bitconvert to floating point or vector.
519 SDValue newLoad = DAG.getLoad(intVT, dl, Chain, Ptr, LD->getPointerInfo(),
521 LD->isNonTemporal(), LD->getAlignment());
522 SDValue Result = DAG.getNode(ISD::BITCAST, dl, LoadedVT, newLoad);
523 if (VT.isFloatingPoint() && LoadedVT != VT)
524 Result = DAG.getNode(ISD::FP_EXTEND, dl, VT, Result);
526 SDValue Ops[] = { Result, Chain };
527 return DAG.getMergeValues(Ops, 2, dl);
530 // Copy the value to a (aligned) stack slot using (unaligned) integer
531 // loads and stores, then do a (aligned) load from the stack slot.
532 EVT RegVT = TLI.getRegisterType(*DAG.getContext(), intVT);
533 unsigned LoadedBytes = LoadedVT.getSizeInBits() / 8;
534 unsigned RegBytes = RegVT.getSizeInBits() / 8;
535 unsigned NumRegs = (LoadedBytes + RegBytes - 1) / RegBytes;
537 // Make sure the stack slot is also aligned for the register type.
538 SDValue StackBase = DAG.CreateStackTemporary(LoadedVT, RegVT);
540 SDValue Increment = DAG.getConstant(RegBytes, TLI.getPointerTy());
541 SmallVector<SDValue, 8> Stores;
542 SDValue StackPtr = StackBase;
545 // Do all but one copies using the full register width.
546 for (unsigned i = 1; i < NumRegs; i++) {
547 // Load one integer register's worth from the original location.
548 SDValue Load = DAG.getLoad(RegVT, dl, Chain, Ptr,
549 LD->getPointerInfo().getWithOffset(Offset),
550 LD->isVolatile(), LD->isNonTemporal(),
551 MinAlign(LD->getAlignment(), Offset));
552 // Follow the load with a store to the stack slot. Remember the store.
553 Stores.push_back(DAG.getStore(Load.getValue(1), dl, Load, StackPtr,
554 MachinePointerInfo(), false, false, 0));
555 // Increment the pointers.
557 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
558 StackPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr,
562 // The last copy may be partial. Do an extending load.
563 EVT MemVT = EVT::getIntegerVT(*DAG.getContext(),
564 8 * (LoadedBytes - Offset));
565 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, RegVT, Chain, Ptr,
566 LD->getPointerInfo().getWithOffset(Offset),
567 MemVT, LD->isVolatile(),
569 MinAlign(LD->getAlignment(), Offset));
570 // Follow the load with a store to the stack slot. Remember the store.
571 // On big-endian machines this requires a truncating store to ensure
572 // that the bits end up in the right place.
573 Stores.push_back(DAG.getTruncStore(Load.getValue(1), dl, Load, StackPtr,
574 MachinePointerInfo(), MemVT,
577 // The order of the stores doesn't matter - say it with a TokenFactor.
578 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Stores[0],
581 // Finally, perform the original load only redirected to the stack slot.
582 Load = DAG.getExtLoad(LD->getExtensionType(), dl, VT, TF, StackBase,
583 MachinePointerInfo(), LoadedVT, false, false, 0);
585 // Callers expect a MERGE_VALUES node.
586 SDValue Ops[] = { Load, TF };
587 return DAG.getMergeValues(Ops, 2, dl);
589 assert(LoadedVT.isInteger() && !LoadedVT.isVector() &&
590 "Unaligned load of unsupported type.");
592 // Compute the new VT that is half the size of the old one. This is an
594 unsigned NumBits = LoadedVT.getSizeInBits();
596 NewLoadedVT = EVT::getIntegerVT(*DAG.getContext(), NumBits/2);
599 unsigned Alignment = LD->getAlignment();
600 unsigned IncrementSize = NumBits / 8;
601 ISD::LoadExtType HiExtType = LD->getExtensionType();
603 // If the original load is NON_EXTLOAD, the hi part load must be ZEXTLOAD.
604 if (HiExtType == ISD::NON_EXTLOAD)
605 HiExtType = ISD::ZEXTLOAD;
607 // Load the value in two parts
609 if (TLI.isLittleEndian()) {
610 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, VT, Chain, Ptr, LD->getPointerInfo(),
611 NewLoadedVT, LD->isVolatile(),
612 LD->isNonTemporal(), Alignment);
613 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
614 DAG.getConstant(IncrementSize, TLI.getPointerTy()));
615 Hi = DAG.getExtLoad(HiExtType, dl, VT, Chain, Ptr,
616 LD->getPointerInfo().getWithOffset(IncrementSize),
617 NewLoadedVT, LD->isVolatile(),
618 LD->isNonTemporal(), MinAlign(Alignment,IncrementSize));
620 Hi = DAG.getExtLoad(HiExtType, dl, VT, Chain, Ptr, LD->getPointerInfo(),
621 NewLoadedVT, LD->isVolatile(),
622 LD->isNonTemporal(), Alignment);
623 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
624 DAG.getConstant(IncrementSize, TLI.getPointerTy()));
625 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, VT, Chain, Ptr,
626 LD->getPointerInfo().getWithOffset(IncrementSize),
627 NewLoadedVT, LD->isVolatile(),
628 LD->isNonTemporal(), MinAlign(Alignment,IncrementSize));
631 // aggregate the two parts
632 SDValue ShiftAmount = DAG.getConstant(NumBits,
633 TLI.getShiftAmountTy(Hi.getValueType()));
634 SDValue Result = DAG.getNode(ISD::SHL, dl, VT, Hi, ShiftAmount);
635 Result = DAG.getNode(ISD::OR, dl, VT, Result, Lo);
637 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
640 SDValue Ops[] = { Result, TF };
641 return DAG.getMergeValues(Ops, 2, dl);
644 /// PerformInsertVectorEltInMemory - Some target cannot handle a variable
645 /// insertion index for the INSERT_VECTOR_ELT instruction. In this case, it
646 /// is necessary to spill the vector being inserted into to memory, perform
647 /// the insert there, and then read the result back.
648 SDValue SelectionDAGLegalize::
649 PerformInsertVectorEltInMemory(SDValue Vec, SDValue Val, SDValue Idx,
655 // If the target doesn't support this, we have to spill the input vector
656 // to a temporary stack slot, update the element, then reload it. This is
657 // badness. We could also load the value into a vector register (either
658 // with a "move to register" or "extload into register" instruction, then
659 // permute it into place, if the idx is a constant and if the idx is
660 // supported by the target.
661 EVT VT = Tmp1.getValueType();
662 EVT EltVT = VT.getVectorElementType();
663 EVT IdxVT = Tmp3.getValueType();
664 EVT PtrVT = TLI.getPointerTy();
665 SDValue StackPtr = DAG.CreateStackTemporary(VT);
667 int SPFI = cast<FrameIndexSDNode>(StackPtr.getNode())->getIndex();
670 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, Tmp1, StackPtr,
671 MachinePointerInfo::getFixedStack(SPFI),
674 // Truncate or zero extend offset to target pointer type.
675 unsigned CastOpc = IdxVT.bitsGT(PtrVT) ? ISD::TRUNCATE : ISD::ZERO_EXTEND;
676 Tmp3 = DAG.getNode(CastOpc, dl, PtrVT, Tmp3);
677 // Add the offset to the index.
678 unsigned EltSize = EltVT.getSizeInBits()/8;
679 Tmp3 = DAG.getNode(ISD::MUL, dl, IdxVT, Tmp3,DAG.getConstant(EltSize, IdxVT));
680 SDValue StackPtr2 = DAG.getNode(ISD::ADD, dl, IdxVT, Tmp3, StackPtr);
681 // Store the scalar value.
682 Ch = DAG.getTruncStore(Ch, dl, Tmp2, StackPtr2, MachinePointerInfo(), EltVT,
684 // Load the updated vector.
685 return DAG.getLoad(VT, dl, Ch, StackPtr,
686 MachinePointerInfo::getFixedStack(SPFI), false, false, 0);
690 SDValue SelectionDAGLegalize::
691 ExpandINSERT_VECTOR_ELT(SDValue Vec, SDValue Val, SDValue Idx, DebugLoc dl) {
692 if (ConstantSDNode *InsertPos = dyn_cast<ConstantSDNode>(Idx)) {
693 // SCALAR_TO_VECTOR requires that the type of the value being inserted
694 // match the element type of the vector being created, except for
695 // integers in which case the inserted value can be over width.
696 EVT EltVT = Vec.getValueType().getVectorElementType();
697 if (Val.getValueType() == EltVT ||
698 (EltVT.isInteger() && Val.getValueType().bitsGE(EltVT))) {
699 SDValue ScVec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
700 Vec.getValueType(), Val);
702 unsigned NumElts = Vec.getValueType().getVectorNumElements();
703 // We generate a shuffle of InVec and ScVec, so the shuffle mask
704 // should be 0,1,2,3,4,5... with the appropriate element replaced with
706 SmallVector<int, 8> ShufOps;
707 for (unsigned i = 0; i != NumElts; ++i)
708 ShufOps.push_back(i != InsertPos->getZExtValue() ? i : NumElts);
710 return DAG.getVectorShuffle(Vec.getValueType(), dl, Vec, ScVec,
714 return PerformInsertVectorEltInMemory(Vec, Val, Idx, dl);
717 SDValue SelectionDAGLegalize::OptimizeFloatStore(StoreSDNode* ST) {
718 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr'
719 // FIXME: We shouldn't do this for TargetConstantFP's.
720 // FIXME: move this to the DAG Combiner! Note that we can't regress due
721 // to phase ordering between legalized code and the dag combiner. This
722 // probably means that we need to integrate dag combiner and legalizer
724 // We generally can't do this one for long doubles.
725 SDValue Tmp1 = ST->getChain();
726 SDValue Tmp2 = ST->getBasePtr();
728 unsigned Alignment = ST->getAlignment();
729 bool isVolatile = ST->isVolatile();
730 bool isNonTemporal = ST->isNonTemporal();
731 DebugLoc dl = ST->getDebugLoc();
732 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(ST->getValue())) {
733 if (CFP->getValueType(0) == MVT::f32 &&
734 TLI.isTypeLegal(MVT::i32)) {
735 Tmp3 = DAG.getConstant(CFP->getValueAPF().
736 bitcastToAPInt().zextOrTrunc(32),
738 return DAG.getStore(Tmp1, dl, Tmp3, Tmp2, ST->getPointerInfo(),
739 isVolatile, isNonTemporal, Alignment);
742 if (CFP->getValueType(0) == MVT::f64) {
743 // If this target supports 64-bit registers, do a single 64-bit store.
744 if (TLI.isTypeLegal(MVT::i64)) {
745 Tmp3 = DAG.getConstant(CFP->getValueAPF().bitcastToAPInt().
746 zextOrTrunc(64), MVT::i64);
747 return DAG.getStore(Tmp1, dl, Tmp3, Tmp2, ST->getPointerInfo(),
748 isVolatile, isNonTemporal, Alignment);
751 if (TLI.isTypeLegal(MVT::i32) && !ST->isVolatile()) {
752 // Otherwise, if the target supports 32-bit registers, use 2 32-bit
753 // stores. If the target supports neither 32- nor 64-bits, this
754 // xform is certainly not worth it.
755 const APInt &IntVal =CFP->getValueAPF().bitcastToAPInt();
756 SDValue Lo = DAG.getConstant(IntVal.trunc(32), MVT::i32);
757 SDValue Hi = DAG.getConstant(IntVal.lshr(32).trunc(32), MVT::i32);
758 if (TLI.isBigEndian()) std::swap(Lo, Hi);
760 Lo = DAG.getStore(Tmp1, dl, Lo, Tmp2, ST->getPointerInfo(), isVolatile,
761 isNonTemporal, Alignment);
762 Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2,
763 DAG.getIntPtrConstant(4));
764 Hi = DAG.getStore(Tmp1, dl, Hi, Tmp2,
765 ST->getPointerInfo().getWithOffset(4),
766 isVolatile, isNonTemporal, MinAlign(Alignment, 4U));
768 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi);
772 return SDValue(0, 0);
775 /// LegalizeOp - Return a legal replacement for the given operation, with
776 /// all legal operands.
777 SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
778 if (Op.getOpcode() == ISD::TargetConstant) // Allow illegal target nodes.
781 SDNode *Node = Op.getNode();
782 DebugLoc dl = Node->getDebugLoc();
784 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
785 assert(TLI.getTypeAction(*DAG.getContext(), Node->getValueType(i)) ==
786 TargetLowering::TypeLegal &&
787 "Unexpected illegal type!");
789 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
790 assert((TLI.getTypeAction(*DAG.getContext(),
791 Node->getOperand(i).getValueType()) ==
792 TargetLowering::TypeLegal ||
793 Node->getOperand(i).getOpcode() == ISD::TargetConstant) &&
794 "Unexpected illegal type!");
796 // Note that LegalizeOp may be reentered even from single-use nodes, which
797 // means that we always must cache transformed nodes.
798 DenseMap<SDValue, SDValue>::iterator I = LegalizedNodes.find(Op);
799 if (I != LegalizedNodes.end()) return I->second;
801 SDValue Tmp1, Tmp2, Tmp3, Tmp4;
803 bool isCustom = false;
805 // Figure out the correct action; the way to query this varies by opcode
806 TargetLowering::LegalizeAction Action = TargetLowering::Legal;
807 bool SimpleFinishLegalizing = true;
808 switch (Node->getOpcode()) {
809 case ISD::INTRINSIC_W_CHAIN:
810 case ISD::INTRINSIC_WO_CHAIN:
811 case ISD::INTRINSIC_VOID:
814 Action = TLI.getOperationAction(Node->getOpcode(), MVT::Other);
816 case ISD::SINT_TO_FP:
817 case ISD::UINT_TO_FP:
818 case ISD::EXTRACT_VECTOR_ELT:
819 Action = TLI.getOperationAction(Node->getOpcode(),
820 Node->getOperand(0).getValueType());
822 case ISD::FP_ROUND_INREG:
823 case ISD::SIGN_EXTEND_INREG: {
824 EVT InnerType = cast<VTSDNode>(Node->getOperand(1))->getVT();
825 Action = TLI.getOperationAction(Node->getOpcode(), InnerType);
831 unsigned CCOperand = Node->getOpcode() == ISD::SELECT_CC ? 4 :
832 Node->getOpcode() == ISD::SETCC ? 2 : 1;
833 unsigned CompareOperand = Node->getOpcode() == ISD::BR_CC ? 2 : 0;
834 EVT OpVT = Node->getOperand(CompareOperand).getValueType();
835 ISD::CondCode CCCode =
836 cast<CondCodeSDNode>(Node->getOperand(CCOperand))->get();
837 Action = TLI.getCondCodeAction(CCCode, OpVT);
838 if (Action == TargetLowering::Legal) {
839 if (Node->getOpcode() == ISD::SELECT_CC)
840 Action = TLI.getOperationAction(Node->getOpcode(),
841 Node->getValueType(0));
843 Action = TLI.getOperationAction(Node->getOpcode(), OpVT);
849 // FIXME: Model these properly. LOAD and STORE are complicated, and
850 // STORE expects the unlegalized operand in some cases.
851 SimpleFinishLegalizing = false;
853 case ISD::CALLSEQ_START:
854 case ISD::CALLSEQ_END:
855 // FIXME: This shouldn't be necessary. These nodes have special properties
856 // dealing with the recursive nature of legalization. Removing this
857 // special case should be done as part of making LegalizeDAG non-recursive.
858 SimpleFinishLegalizing = false;
860 case ISD::EXTRACT_ELEMENT:
861 case ISD::FLT_ROUNDS_:
869 case ISD::MERGE_VALUES:
871 case ISD::FRAME_TO_ARGS_OFFSET:
872 case ISD::EH_SJLJ_SETJMP:
873 case ISD::EH_SJLJ_LONGJMP:
874 case ISD::EH_SJLJ_DISPATCHSETUP:
875 // These operations lie about being legal: when they claim to be legal,
876 // they should actually be expanded.
877 Action = TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0));
878 if (Action == TargetLowering::Legal)
879 Action = TargetLowering::Expand;
881 case ISD::TRAMPOLINE:
883 case ISD::RETURNADDR:
884 // These operations lie about being legal: when they claim to be legal,
885 // they should actually be custom-lowered.
886 Action = TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0));
887 if (Action == TargetLowering::Legal)
888 Action = TargetLowering::Custom;
890 case ISD::BUILD_VECTOR:
891 // A weird case: legalization for BUILD_VECTOR never legalizes the
893 // FIXME: This really sucks... changing it isn't semantically incorrect,
894 // but it massively pessimizes the code for floating-point BUILD_VECTORs
895 // because ConstantFP operands get legalized into constant pool loads
896 // before the BUILD_VECTOR code can see them. It doesn't usually bite,
897 // though, because BUILD_VECTORS usually get lowered into other nodes
898 // which get legalized properly.
899 SimpleFinishLegalizing = false;
902 if (Node->getOpcode() >= ISD::BUILTIN_OP_END) {
903 Action = TargetLowering::Legal;
905 Action = TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0));
910 if (SimpleFinishLegalizing) {
911 SmallVector<SDValue, 8> Ops, ResultVals;
912 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
913 Ops.push_back(LegalizeOp(Node->getOperand(i)));
914 switch (Node->getOpcode()) {
921 assert(LastCALLSEQ.size() == 1 && "branch inside CALLSEQ_BEGIN/END?");
922 // Branches tweak the chain to include LastCALLSEQ
923 Ops[0] = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Ops[0],
925 Ops[0] = LegalizeOp(Ops[0]);
926 setLastCALLSEQ(DAG.getEntryNode());
933 // Legalizing shifts/rotates requires adjusting the shift amount
934 // to the appropriate width.
935 if (!Ops[1].getValueType().isVector())
936 Ops[1] = LegalizeOp(DAG.getShiftAmountOperand(Ops[0].getValueType(),
942 // Legalizing shifts/rotates requires adjusting the shift amount
943 // to the appropriate width.
944 if (!Ops[2].getValueType().isVector())
945 Ops[2] = LegalizeOp(DAG.getShiftAmountOperand(Ops[0].getValueType(),
950 Result = SDValue(DAG.UpdateNodeOperands(Result.getNode(), Ops.data(),
953 case TargetLowering::Legal:
954 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
955 ResultVals.push_back(Result.getValue(i));
957 case TargetLowering::Custom:
958 // FIXME: The handling for custom lowering with multiple results is
960 Tmp1 = TLI.LowerOperation(Result, DAG);
961 if (Tmp1.getNode()) {
962 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) {
964 ResultVals.push_back(Tmp1);
966 ResultVals.push_back(Tmp1.getValue(i));
972 case TargetLowering::Expand:
973 ExpandNode(Result.getNode(), ResultVals);
975 case TargetLowering::Promote:
976 PromoteNode(Result.getNode(), ResultVals);
979 if (!ResultVals.empty()) {
980 for (unsigned i = 0, e = ResultVals.size(); i != e; ++i) {
981 if (ResultVals[i] != SDValue(Node, i))
982 ResultVals[i] = LegalizeOp(ResultVals[i]);
983 AddLegalizedOperand(SDValue(Node, i), ResultVals[i]);
985 return ResultVals[Op.getResNo()];
989 switch (Node->getOpcode()) {
996 assert(0 && "Do not know how to legalize this operator!");
998 case ISD::BUILD_VECTOR:
999 switch (TLI.getOperationAction(ISD::BUILD_VECTOR, Node->getValueType(0))) {
1000 default: assert(0 && "This action is not supported yet!");
1001 case TargetLowering::Custom:
1002 Tmp3 = TLI.LowerOperation(Result, DAG);
1003 if (Tmp3.getNode()) {
1008 case TargetLowering::Expand:
1009 Result = ExpandBUILD_VECTOR(Result.getNode());
1013 case ISD::CALLSEQ_START: {
1014 SDNode *CallEnd = FindCallEndFromCallStart(Node);
1015 assert(CallEnd && "didn't find CALLSEQ_END!");
1017 // Recursively Legalize all of the inputs of the call end that do not lead
1018 // to this call start. This ensures that any libcalls that need be inserted
1019 // are inserted *before* the CALLSEQ_START.
1020 {SmallPtrSet<SDNode*, 32> NodesLeadingTo;
1021 for (unsigned i = 0, e = CallEnd->getNumOperands(); i != e; ++i)
1022 LegalizeAllNodesNotLeadingTo(CallEnd->getOperand(i).getNode(), Node,
1026 // Now that we have legalized all of the inputs (which may have inserted
1027 // libcalls), create the new CALLSEQ_START node.
1028 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1030 // Merge in the last call to ensure that this call starts after the last
1032 if (getLastCALLSEQ().getOpcode() != ISD::EntryToken) {
1033 Tmp1 = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
1034 Tmp1, getLastCALLSEQ());
1035 Tmp1 = LegalizeOp(Tmp1);
1038 // Do not try to legalize the target-specific arguments (#1+).
1039 if (Tmp1 != Node->getOperand(0)) {
1040 SmallVector<SDValue, 8> Ops(Node->op_begin(), Node->op_end());
1042 Result = SDValue(DAG.UpdateNodeOperands(Result.getNode(), &Ops[0],
1043 Ops.size()), Result.getResNo());
1046 // Remember that the CALLSEQ_START is legalized.
1047 AddLegalizedOperand(Op.getValue(0), Result);
1048 if (Node->getNumValues() == 2) // If this has a flag result, remember it.
1049 AddLegalizedOperand(Op.getValue(1), Result.getValue(1));
1051 // Now that the callseq_start and all of the non-call nodes above this call
1052 // sequence have been legalized, legalize the call itself. During this
1053 // process, no libcalls can/will be inserted, guaranteeing that no calls
1055 // Note that we are selecting this call!
1056 setLastCALLSEQ(SDValue(CallEnd, 0));
1058 // Legalize the call, starting from the CALLSEQ_END.
1059 LegalizeOp(getLastCALLSEQ());
1062 case ISD::CALLSEQ_END:
1064 SDNode *myCALLSEQ_BEGIN = FindCallStartFromCallEnd(Node);
1066 // If the CALLSEQ_START node hasn't been legalized first, legalize it.
1067 // This will cause this node to be legalized as well as handling libcalls
1069 if (getLastCALLSEQ().getNode() != Node) {
1070 LegalizeOp(SDValue(myCALLSEQ_BEGIN, 0));
1071 DenseMap<SDValue, SDValue>::iterator I = LegalizedNodes.find(Op);
1072 assert(I != LegalizedNodes.end() &&
1073 "Legalizing the call start should have legalized this node!");
1077 pushLastCALLSEQ(SDValue(myCALLSEQ_BEGIN, 0));
1080 // Otherwise, the call start has been legalized and everything is going
1081 // according to plan. Just legalize ourselves normally here.
1082 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1083 // Do not try to legalize the target-specific arguments (#1+), except for
1084 // an optional flag input.
1085 if (Node->getOperand(Node->getNumOperands()-1).getValueType() != MVT::Glue){
1086 if (Tmp1 != Node->getOperand(0)) {
1087 SmallVector<SDValue, 8> Ops(Node->op_begin(), Node->op_end());
1089 Result = SDValue(DAG.UpdateNodeOperands(Result.getNode(),
1090 &Ops[0], Ops.size()),
1094 Tmp2 = LegalizeOp(Node->getOperand(Node->getNumOperands()-1));
1095 if (Tmp1 != Node->getOperand(0) ||
1096 Tmp2 != Node->getOperand(Node->getNumOperands()-1)) {
1097 SmallVector<SDValue, 8> Ops(Node->op_begin(), Node->op_end());
1100 Result = SDValue(DAG.UpdateNodeOperands(Result.getNode(),
1101 &Ops[0], Ops.size()),
1105 // This finishes up call legalization.
1108 // If the CALLSEQ_END node has a flag, remember that we legalized it.
1109 AddLegalizedOperand(SDValue(Node, 0), Result.getValue(0));
1110 if (Node->getNumValues() == 2)
1111 AddLegalizedOperand(SDValue(Node, 1), Result.getValue(1));
1112 return Result.getValue(Op.getResNo());
1114 LoadSDNode *LD = cast<LoadSDNode>(Node);
1115 Tmp1 = LegalizeOp(LD->getChain()); // Legalize the chain.
1116 Tmp2 = LegalizeOp(LD->getBasePtr()); // Legalize the base pointer.
1118 ISD::LoadExtType ExtType = LD->getExtensionType();
1119 if (ExtType == ISD::NON_EXTLOAD) {
1120 EVT VT = Node->getValueType(0);
1121 Result = SDValue(DAG.UpdateNodeOperands(Result.getNode(),
1122 Tmp1, Tmp2, LD->getOffset()),
1124 Tmp3 = Result.getValue(0);
1125 Tmp4 = Result.getValue(1);
1127 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
1128 default: assert(0 && "This action is not supported yet!");
1129 case TargetLowering::Legal:
1130 // If this is an unaligned load and the target doesn't support it,
1132 if (!TLI.allowsUnalignedMemoryAccesses(LD->getMemoryVT())) {
1133 const Type *Ty = LD->getMemoryVT().getTypeForEVT(*DAG.getContext());
1134 unsigned ABIAlignment = TLI.getTargetData()->getABITypeAlignment(Ty);
1135 if (LD->getAlignment() < ABIAlignment){
1136 Result = ExpandUnalignedLoad(cast<LoadSDNode>(Result.getNode()),
1138 Tmp3 = Result.getOperand(0);
1139 Tmp4 = Result.getOperand(1);
1140 Tmp3 = LegalizeOp(Tmp3);
1141 Tmp4 = LegalizeOp(Tmp4);
1145 case TargetLowering::Custom:
1146 Tmp1 = TLI.LowerOperation(Tmp3, DAG);
1147 if (Tmp1.getNode()) {
1148 Tmp3 = LegalizeOp(Tmp1);
1149 Tmp4 = LegalizeOp(Tmp1.getValue(1));
1152 case TargetLowering::Promote: {
1153 // Only promote a load of vector type to another.
1154 assert(VT.isVector() && "Cannot promote this load!");
1155 // Change base type to a different vector type.
1156 EVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), VT);
1158 Tmp1 = DAG.getLoad(NVT, dl, Tmp1, Tmp2, LD->getPointerInfo(),
1159 LD->isVolatile(), LD->isNonTemporal(),
1160 LD->getAlignment());
1161 Tmp3 = LegalizeOp(DAG.getNode(ISD::BITCAST, dl, VT, Tmp1));
1162 Tmp4 = LegalizeOp(Tmp1.getValue(1));
1166 // Since loads produce two values, make sure to remember that we
1167 // legalized both of them.
1168 AddLegalizedOperand(SDValue(Node, 0), Tmp3);
1169 AddLegalizedOperand(SDValue(Node, 1), Tmp4);
1170 return Op.getResNo() ? Tmp4 : Tmp3;
1173 EVT SrcVT = LD->getMemoryVT();
1174 unsigned SrcWidth = SrcVT.getSizeInBits();
1175 unsigned Alignment = LD->getAlignment();
1176 bool isVolatile = LD->isVolatile();
1177 bool isNonTemporal = LD->isNonTemporal();
1179 if (SrcWidth != SrcVT.getStoreSizeInBits() &&
1180 // Some targets pretend to have an i1 loading operation, and actually
1181 // load an i8. This trick is correct for ZEXTLOAD because the top 7
1182 // bits are guaranteed to be zero; it helps the optimizers understand
1183 // that these bits are zero. It is also useful for EXTLOAD, since it
1184 // tells the optimizers that those bits are undefined. It would be
1185 // nice to have an effective generic way of getting these benefits...
1186 // Until such a way is found, don't insist on promoting i1 here.
1187 (SrcVT != MVT::i1 ||
1188 TLI.getLoadExtAction(ExtType, MVT::i1) == TargetLowering::Promote)) {
1189 // Promote to a byte-sized load if not loading an integral number of
1190 // bytes. For example, promote EXTLOAD:i20 -> EXTLOAD:i24.
1191 unsigned NewWidth = SrcVT.getStoreSizeInBits();
1192 EVT NVT = EVT::getIntegerVT(*DAG.getContext(), NewWidth);
1195 // The extra bits are guaranteed to be zero, since we stored them that
1196 // way. A zext load from NVT thus automatically gives zext from SrcVT.
1198 ISD::LoadExtType NewExtType =
1199 ExtType == ISD::ZEXTLOAD ? ISD::ZEXTLOAD : ISD::EXTLOAD;
1201 Result = DAG.getExtLoad(NewExtType, dl, Node->getValueType(0),
1202 Tmp1, Tmp2, LD->getPointerInfo(),
1203 NVT, isVolatile, isNonTemporal, Alignment);
1205 Ch = Result.getValue(1); // The chain.
1207 if (ExtType == ISD::SEXTLOAD)
1208 // Having the top bits zero doesn't help when sign extending.
1209 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl,
1210 Result.getValueType(),
1211 Result, DAG.getValueType(SrcVT));
1212 else if (ExtType == ISD::ZEXTLOAD || NVT == Result.getValueType())
1213 // All the top bits are guaranteed to be zero - inform the optimizers.
1214 Result = DAG.getNode(ISD::AssertZext, dl,
1215 Result.getValueType(), Result,
1216 DAG.getValueType(SrcVT));
1218 Tmp1 = LegalizeOp(Result);
1219 Tmp2 = LegalizeOp(Ch);
1220 } else if (SrcWidth & (SrcWidth - 1)) {
1221 // If not loading a power-of-2 number of bits, expand as two loads.
1222 assert(!SrcVT.isVector() && "Unsupported extload!");
1223 unsigned RoundWidth = 1 << Log2_32(SrcWidth);
1224 assert(RoundWidth < SrcWidth);
1225 unsigned ExtraWidth = SrcWidth - RoundWidth;
1226 assert(ExtraWidth < RoundWidth);
1227 assert(!(RoundWidth % 8) && !(ExtraWidth % 8) &&
1228 "Load size not an integral number of bytes!");
1229 EVT RoundVT = EVT::getIntegerVT(*DAG.getContext(), RoundWidth);
1230 EVT ExtraVT = EVT::getIntegerVT(*DAG.getContext(), ExtraWidth);
1232 unsigned IncrementSize;
1234 if (TLI.isLittleEndian()) {
1235 // EXTLOAD:i24 -> ZEXTLOAD:i16 | (shl EXTLOAD@+2:i8, 16)
1236 // Load the bottom RoundWidth bits.
1237 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, Node->getValueType(0),
1239 LD->getPointerInfo(), RoundVT, isVolatile,
1240 isNonTemporal, Alignment);
1242 // Load the remaining ExtraWidth bits.
1243 IncrementSize = RoundWidth / 8;
1244 Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2,
1245 DAG.getIntPtrConstant(IncrementSize));
1246 Hi = DAG.getExtLoad(ExtType, dl, Node->getValueType(0), Tmp1, Tmp2,
1247 LD->getPointerInfo().getWithOffset(IncrementSize),
1248 ExtraVT, isVolatile, isNonTemporal,
1249 MinAlign(Alignment, IncrementSize));
1251 // Build a factor node to remember that this load is independent of
1253 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
1256 // Move the top bits to the right place.
1257 Hi = DAG.getNode(ISD::SHL, dl, Hi.getValueType(), Hi,
1258 DAG.getConstant(RoundWidth,
1259 TLI.getShiftAmountTy(Hi.getValueType())));
1261 // Join the hi and lo parts.
1262 Result = DAG.getNode(ISD::OR, dl, Node->getValueType(0), Lo, Hi);
1264 // Big endian - avoid unaligned loads.
1265 // EXTLOAD:i24 -> (shl EXTLOAD:i16, 8) | ZEXTLOAD@+2:i8
1266 // Load the top RoundWidth bits.
1267 Hi = DAG.getExtLoad(ExtType, dl, Node->getValueType(0), Tmp1, Tmp2,
1268 LD->getPointerInfo(), RoundVT, isVolatile,
1269 isNonTemporal, Alignment);
1271 // Load the remaining ExtraWidth bits.
1272 IncrementSize = RoundWidth / 8;
1273 Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2,
1274 DAG.getIntPtrConstant(IncrementSize));
1275 Lo = DAG.getExtLoad(ISD::ZEXTLOAD,
1276 dl, Node->getValueType(0), Tmp1, Tmp2,
1277 LD->getPointerInfo().getWithOffset(IncrementSize),
1278 ExtraVT, isVolatile, isNonTemporal,
1279 MinAlign(Alignment, IncrementSize));
1281 // Build a factor node to remember that this load is independent of
1283 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
1286 // Move the top bits to the right place.
1287 Hi = DAG.getNode(ISD::SHL, dl, Hi.getValueType(), Hi,
1288 DAG.getConstant(ExtraWidth,
1289 TLI.getShiftAmountTy(Hi.getValueType())));
1291 // Join the hi and lo parts.
1292 Result = DAG.getNode(ISD::OR, dl, Node->getValueType(0), Lo, Hi);
1295 Tmp1 = LegalizeOp(Result);
1296 Tmp2 = LegalizeOp(Ch);
1298 switch (TLI.getLoadExtAction(ExtType, SrcVT)) {
1299 default: assert(0 && "This action is not supported yet!");
1300 case TargetLowering::Custom:
1303 case TargetLowering::Legal:
1304 Result = SDValue(DAG.UpdateNodeOperands(Result.getNode(),
1305 Tmp1, Tmp2, LD->getOffset()),
1307 Tmp1 = Result.getValue(0);
1308 Tmp2 = Result.getValue(1);
1311 Tmp3 = TLI.LowerOperation(Result, DAG);
1312 if (Tmp3.getNode()) {
1313 Tmp1 = LegalizeOp(Tmp3);
1314 Tmp2 = LegalizeOp(Tmp3.getValue(1));
1317 // If this is an unaligned load and the target doesn't support it,
1319 if (!TLI.allowsUnalignedMemoryAccesses(LD->getMemoryVT())) {
1321 LD->getMemoryVT().getTypeForEVT(*DAG.getContext());
1322 unsigned ABIAlignment =
1323 TLI.getTargetData()->getABITypeAlignment(Ty);
1324 if (LD->getAlignment() < ABIAlignment){
1325 Result = ExpandUnalignedLoad(cast<LoadSDNode>(Result.getNode()),
1327 Tmp1 = Result.getOperand(0);
1328 Tmp2 = Result.getOperand(1);
1329 Tmp1 = LegalizeOp(Tmp1);
1330 Tmp2 = LegalizeOp(Tmp2);
1335 case TargetLowering::Expand:
1336 if (!TLI.isLoadExtLegal(ISD::EXTLOAD, SrcVT) && TLI.isTypeLegal(SrcVT)) {
1337 SDValue Load = DAG.getLoad(SrcVT, dl, Tmp1, Tmp2,
1338 LD->getPointerInfo(),
1339 LD->isVolatile(), LD->isNonTemporal(),
1340 LD->getAlignment());
1344 ExtendOp = (SrcVT.isFloatingPoint() ?
1345 ISD::FP_EXTEND : ISD::ANY_EXTEND);
1347 case ISD::SEXTLOAD: ExtendOp = ISD::SIGN_EXTEND; break;
1348 case ISD::ZEXTLOAD: ExtendOp = ISD::ZERO_EXTEND; break;
1349 default: llvm_unreachable("Unexpected extend load type!");
1351 Result = DAG.getNode(ExtendOp, dl, Node->getValueType(0), Load);
1352 Tmp1 = LegalizeOp(Result); // Relegalize new nodes.
1353 Tmp2 = LegalizeOp(Load.getValue(1));
1357 // If this is a promoted vector load, and the vector element types are
1358 // legal, then scalarize it.
1359 if (ExtType == ISD::EXTLOAD && SrcVT.isVector() &&
1360 TLI.isTypeLegal(Node->getValueType(0).getScalarType())) {
1361 SmallVector<SDValue, 8> LoadVals;
1362 SmallVector<SDValue, 8> LoadChains;
1363 unsigned NumElem = SrcVT.getVectorNumElements();
1364 unsigned Stride = SrcVT.getScalarType().getSizeInBits()/8;
1366 for (unsigned Idx=0; Idx<NumElem; Idx++) {
1367 Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2,
1368 DAG.getIntPtrConstant(Stride));
1369 SDValue ScalarLoad = DAG.getExtLoad(ISD::EXTLOAD, dl,
1370 Node->getValueType(0).getScalarType(),
1371 Tmp1, Tmp2, LD->getPointerInfo().getWithOffset(Idx * Stride),
1372 SrcVT.getScalarType(),
1373 LD->isVolatile(), LD->isNonTemporal(),
1374 LD->getAlignment());
1376 LoadVals.push_back(ScalarLoad.getValue(0));
1377 LoadChains.push_back(ScalarLoad.getValue(1));
1379 Result = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
1380 &LoadChains[0], LoadChains.size());
1381 SDValue ValRes = DAG.getNode(ISD::BUILD_VECTOR, dl,
1382 Node->getValueType(0), &LoadVals[0], LoadVals.size());
1384 Tmp1 = LegalizeOp(ValRes); // Relegalize new nodes.
1385 Tmp2 = LegalizeOp(Result.getValue(0)); // Relegalize new nodes.
1389 // If this is a promoted vector load, and the vector element types are
1390 // illegal, create the promoted vector from bitcasted segments.
1391 if (ExtType == ISD::EXTLOAD && SrcVT.isVector()) {
1392 EVT MemElemTy = Node->getValueType(0).getScalarType();
1393 EVT SrcSclrTy = SrcVT.getScalarType();
1394 unsigned SizeRatio =
1395 (MemElemTy.getSizeInBits() / SrcSclrTy.getSizeInBits());
1397 SmallVector<SDValue, 8> LoadVals;
1398 SmallVector<SDValue, 8> LoadChains;
1399 unsigned NumElem = SrcVT.getVectorNumElements();
1400 unsigned Stride = SrcVT.getScalarType().getSizeInBits()/8;
1402 for (unsigned Idx=0; Idx<NumElem; Idx++) {
1403 Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2,
1404 DAG.getIntPtrConstant(Stride));
1405 SDValue ScalarLoad = DAG.getExtLoad(ISD::EXTLOAD, dl,
1406 SrcVT.getScalarType(),
1407 Tmp1, Tmp2, LD->getPointerInfo().getWithOffset(Idx * Stride),
1408 SrcVT.getScalarType(),
1409 LD->isVolatile(), LD->isNonTemporal(),
1410 LD->getAlignment());
1411 if (TLI.isBigEndian()) {
1412 // MSB (which is garbage, comes first)
1413 LoadVals.push_back(ScalarLoad.getValue(0));
1414 for (unsigned i = 0; i<SizeRatio-1; ++i)
1415 LoadVals.push_back(DAG.getUNDEF(SrcVT.getScalarType()));
1417 // LSB (which is data, comes first)
1418 for (unsigned i = 0; i<SizeRatio-1; ++i)
1419 LoadVals.push_back(DAG.getUNDEF(SrcVT.getScalarType()));
1420 LoadVals.push_back(ScalarLoad.getValue(0));
1422 LoadChains.push_back(ScalarLoad.getValue(1));
1425 Result = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
1426 &LoadChains[0], LoadChains.size());
1427 EVT TempWideVector = EVT::getVectorVT(*DAG.getContext(),
1428 SrcVT.getScalarType(), NumElem*SizeRatio);
1429 SDValue ValRes = DAG.getNode(ISD::BUILD_VECTOR, dl,
1430 TempWideVector, &LoadVals[0], LoadVals.size());
1432 // Cast to the correct type
1433 ValRes = DAG.getNode(ISD::BITCAST, dl, Node->getValueType(0), ValRes);
1435 Tmp1 = LegalizeOp(ValRes); // Relegalize new nodes.
1436 Tmp2 = LegalizeOp(Result.getValue(0)); // Relegalize new nodes.
1441 // FIXME: This does not work for vectors on most targets. Sign- and
1442 // zero-extend operations are currently folded into extending loads,
1443 // whether they are legal or not, and then we end up here without any
1444 // support for legalizing them.
1445 assert(ExtType != ISD::EXTLOAD &&
1446 "EXTLOAD should always be supported!");
1447 // Turn the unsupported load into an EXTLOAD followed by an explicit
1448 // zero/sign extend inreg.
1449 Result = DAG.getExtLoad(ISD::EXTLOAD, dl, Node->getValueType(0),
1450 Tmp1, Tmp2, LD->getPointerInfo(), SrcVT,
1451 LD->isVolatile(), LD->isNonTemporal(),
1452 LD->getAlignment());
1454 if (ExtType == ISD::SEXTLOAD)
1455 ValRes = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl,
1456 Result.getValueType(),
1457 Result, DAG.getValueType(SrcVT));
1459 ValRes = DAG.getZeroExtendInReg(Result, dl, SrcVT.getScalarType());
1460 Tmp1 = LegalizeOp(ValRes); // Relegalize new nodes.
1461 Tmp2 = LegalizeOp(Result.getValue(1)); // Relegalize new nodes.
1466 // Since loads produce two values, make sure to remember that we legalized
1468 AddLegalizedOperand(SDValue(Node, 0), Tmp1);
1469 AddLegalizedOperand(SDValue(Node, 1), Tmp2);
1470 return Op.getResNo() ? Tmp2 : Tmp1;
1473 StoreSDNode *ST = cast<StoreSDNode>(Node);
1474 Tmp1 = LegalizeOp(ST->getChain()); // Legalize the chain.
1475 Tmp2 = LegalizeOp(ST->getBasePtr()); // Legalize the pointer.
1476 unsigned Alignment = ST->getAlignment();
1477 bool isVolatile = ST->isVolatile();
1478 bool isNonTemporal = ST->isNonTemporal();
1480 if (!ST->isTruncatingStore()) {
1481 if (SDNode *OptStore = OptimizeFloatStore(ST).getNode()) {
1482 Result = SDValue(OptStore, 0);
1487 Tmp3 = LegalizeOp(ST->getValue());
1488 Result = SDValue(DAG.UpdateNodeOperands(Result.getNode(),
1493 EVT VT = Tmp3.getValueType();
1494 switch (TLI.getOperationAction(ISD::STORE, VT)) {
1495 default: assert(0 && "This action is not supported yet!");
1496 case TargetLowering::Legal:
1497 // If this is an unaligned store and the target doesn't support it,
1499 if (!TLI.allowsUnalignedMemoryAccesses(ST->getMemoryVT())) {
1500 const Type *Ty = ST->getMemoryVT().getTypeForEVT(*DAG.getContext());
1501 unsigned ABIAlignment= TLI.getTargetData()->getABITypeAlignment(Ty);
1502 if (ST->getAlignment() < ABIAlignment)
1503 Result = ExpandUnalignedStore(cast<StoreSDNode>(Result.getNode()),
1507 case TargetLowering::Custom:
1508 Tmp1 = TLI.LowerOperation(Result, DAG);
1509 if (Tmp1.getNode()) Result = Tmp1;
1511 case TargetLowering::Promote:
1512 assert(VT.isVector() && "Unknown legal promote case!");
1513 Tmp3 = DAG.getNode(ISD::BITCAST, dl,
1514 TLI.getTypeToPromoteTo(ISD::STORE, VT), Tmp3);
1515 Result = DAG.getStore(Tmp1, dl, Tmp3, Tmp2,
1516 ST->getPointerInfo(), isVolatile,
1517 isNonTemporal, Alignment);
1523 Tmp3 = LegalizeOp(ST->getValue());
1525 EVT StVT = ST->getMemoryVT();
1526 unsigned StWidth = StVT.getSizeInBits();
1528 if (StWidth != StVT.getStoreSizeInBits()) {
1529 // Promote to a byte-sized store with upper bits zero if not
1530 // storing an integral number of bytes. For example, promote
1531 // TRUNCSTORE:i1 X -> TRUNCSTORE:i8 (and X, 1)
1532 EVT NVT = EVT::getIntegerVT(*DAG.getContext(),
1533 StVT.getStoreSizeInBits());
1534 Tmp3 = DAG.getZeroExtendInReg(Tmp3, dl, StVT);
1535 Result = DAG.getTruncStore(Tmp1, dl, Tmp3, Tmp2, ST->getPointerInfo(),
1536 NVT, isVolatile, isNonTemporal, Alignment);
1537 } else if (StWidth & (StWidth - 1)) {
1538 // If not storing a power-of-2 number of bits, expand as two stores.
1539 assert(!StVT.isVector() && "Unsupported truncstore!");
1540 unsigned RoundWidth = 1 << Log2_32(StWidth);
1541 assert(RoundWidth < StWidth);
1542 unsigned ExtraWidth = StWidth - RoundWidth;
1543 assert(ExtraWidth < RoundWidth);
1544 assert(!(RoundWidth % 8) && !(ExtraWidth % 8) &&
1545 "Store size not an integral number of bytes!");
1546 EVT RoundVT = EVT::getIntegerVT(*DAG.getContext(), RoundWidth);
1547 EVT ExtraVT = EVT::getIntegerVT(*DAG.getContext(), ExtraWidth);
1549 unsigned IncrementSize;
1551 if (TLI.isLittleEndian()) {
1552 // TRUNCSTORE:i24 X -> TRUNCSTORE:i16 X, TRUNCSTORE@+2:i8 (srl X, 16)
1553 // Store the bottom RoundWidth bits.
1554 Lo = DAG.getTruncStore(Tmp1, dl, Tmp3, Tmp2, ST->getPointerInfo(),
1556 isVolatile, isNonTemporal, Alignment);
1558 // Store the remaining ExtraWidth bits.
1559 IncrementSize = RoundWidth / 8;
1560 Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2,
1561 DAG.getIntPtrConstant(IncrementSize));
1562 Hi = DAG.getNode(ISD::SRL, dl, Tmp3.getValueType(), Tmp3,
1563 DAG.getConstant(RoundWidth,
1564 TLI.getShiftAmountTy(Tmp3.getValueType())));
1565 Hi = DAG.getTruncStore(Tmp1, dl, Hi, Tmp2,
1566 ST->getPointerInfo().getWithOffset(IncrementSize),
1567 ExtraVT, isVolatile, isNonTemporal,
1568 MinAlign(Alignment, IncrementSize));
1570 // Big endian - avoid unaligned stores.
1571 // TRUNCSTORE:i24 X -> TRUNCSTORE:i16 (srl X, 8), TRUNCSTORE@+2:i8 X
1572 // Store the top RoundWidth bits.
1573 Hi = DAG.getNode(ISD::SRL, dl, Tmp3.getValueType(), Tmp3,
1574 DAG.getConstant(ExtraWidth,
1575 TLI.getShiftAmountTy(Tmp3.getValueType())));
1576 Hi = DAG.getTruncStore(Tmp1, dl, Hi, Tmp2, ST->getPointerInfo(),
1577 RoundVT, isVolatile, isNonTemporal, Alignment);
1579 // Store the remaining ExtraWidth bits.
1580 IncrementSize = RoundWidth / 8;
1581 Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2,
1582 DAG.getIntPtrConstant(IncrementSize));
1583 Lo = DAG.getTruncStore(Tmp1, dl, Tmp3, Tmp2,
1584 ST->getPointerInfo().getWithOffset(IncrementSize),
1585 ExtraVT, isVolatile, isNonTemporal,
1586 MinAlign(Alignment, IncrementSize));
1589 // The order of the stores doesn't matter.
1590 Result = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi);
1592 if (Tmp1 != ST->getChain() || Tmp3 != ST->getValue() ||
1593 Tmp2 != ST->getBasePtr())
1594 Result = SDValue(DAG.UpdateNodeOperands(Result.getNode(),
1599 switch (TLI.getTruncStoreAction(ST->getValue().getValueType(), StVT)) {
1600 default: assert(0 && "This action is not supported yet!");
1601 case TargetLowering::Legal:
1602 // If this is an unaligned store and the target doesn't support it,
1604 if (!TLI.allowsUnalignedMemoryAccesses(ST->getMemoryVT())) {
1605 const Type *Ty = ST->getMemoryVT().getTypeForEVT(*DAG.getContext());
1606 unsigned ABIAlignment= TLI.getTargetData()->getABITypeAlignment(Ty);
1607 if (ST->getAlignment() < ABIAlignment)
1608 Result = ExpandUnalignedStore(cast<StoreSDNode>(Result.getNode()),
1612 case TargetLowering::Custom:
1613 Result = TLI.LowerOperation(Result, DAG);
1617 EVT WideScalarVT = Tmp3.getValueType().getScalarType();
1618 EVT NarrowScalarVT = StVT.getScalarType();
1620 // The Store type is illegal, must scalarize the vector store.
1621 SmallVector<SDValue, 8> Stores;
1622 bool ScalarLegal = TLI.isTypeLegal(WideScalarVT);
1623 if (!TLI.isTypeLegal(StVT) && StVT.isVector() && ScalarLegal) {
1624 unsigned NumElem = StVT.getVectorNumElements();
1626 unsigned ScalarSize = StVT.getScalarType().getSizeInBits();
1627 // Round odd types to the next pow of two.
1628 if (!isPowerOf2_32(ScalarSize))
1629 ScalarSize = NextPowerOf2(ScalarSize);
1630 // Types smaller than 8 bits are promoted to 8 bits.
1631 ScalarSize = std::max<unsigned>(ScalarSize, 8);
1633 unsigned Stride = ScalarSize/8;
1634 assert(isPowerOf2_32(Stride) && "Stride must be a power of two");
1636 for (unsigned Idx=0; Idx<NumElem; Idx++) {
1637 SDValue Ex = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
1638 WideScalarVT, Tmp3, DAG.getIntPtrConstant(Idx));
1641 EVT NVT = EVT::getIntegerVT(*DAG.getContext(), ScalarSize);
1643 Ex = DAG.getNode(ISD::TRUNCATE, dl, NVT, Ex);
1644 Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2,
1645 DAG.getIntPtrConstant(Stride));
1646 SDValue Store = DAG.getStore(Tmp1, dl, Ex, Tmp2,
1647 ST->getPointerInfo().getWithOffset(Idx*Stride),
1648 isVolatile, isNonTemporal, Alignment);
1649 Stores.push_back(Store);
1651 Result = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
1652 &Stores[0], Stores.size());
1656 // The Store type is illegal, must scalarize the vector store.
1657 // However, the scalar type is illegal. Must bitcast the result
1658 // and store it in smaller parts.
1659 if (!TLI.isTypeLegal(StVT) && StVT.isVector()) {
1660 unsigned WideNumElem = StVT.getVectorNumElements();
1661 unsigned Stride = NarrowScalarVT.getSizeInBits()/8;
1663 unsigned SizeRatio =
1664 (WideScalarVT.getSizeInBits() / NarrowScalarVT.getSizeInBits());
1666 EVT CastValueVT = EVT::getVectorVT(*DAG.getContext(), NarrowScalarVT,
1667 SizeRatio*WideNumElem);
1669 // Cast the wide elem vector to wider vec with smaller elem type.
1670 // Example <2 x i64> -> <4 x i32>
1671 Tmp3 = DAG.getNode(ISD::BITCAST, dl, CastValueVT, Tmp3);
1673 for (unsigned Idx=0; Idx<WideNumElem*SizeRatio; Idx++) {
1675 SDValue Ex = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
1676 NarrowScalarVT, Tmp3, DAG.getIntPtrConstant(Idx));
1678 Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2,
1679 DAG.getIntPtrConstant(Stride));
1681 // Store if, this element is:
1682 // - First element on big endian, or
1683 // - Last element on little endian
1684 if (( TLI.isBigEndian() && (Idx%SizeRatio == 0)) ||
1685 ((!TLI.isBigEndian() && (Idx%SizeRatio == SizeRatio-1)))) {
1686 SDValue Store = DAG.getStore(Tmp1, dl, Ex, Tmp2,
1687 ST->getPointerInfo().getWithOffset(Idx*Stride),
1688 isVolatile, isNonTemporal, Alignment);
1689 Stores.push_back(Store);
1692 Result = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
1693 &Stores[0], Stores.size());
1698 // TRUNCSTORE:i16 i32 -> STORE i16
1699 assert(TLI.isTypeLegal(StVT) && "Do not know how to expand this store!");
1700 Tmp3 = DAG.getNode(ISD::TRUNCATE, dl, StVT, Tmp3);
1701 Result = DAG.getStore(Tmp1, dl, Tmp3, Tmp2, ST->getPointerInfo(),
1702 isVolatile, isNonTemporal, Alignment);
1710 assert(Result.getValueType() == Op.getValueType() &&
1711 "Bad legalization!");
1713 // Make sure that the generated code is itself legal.
1715 Result = LegalizeOp(Result);
1717 // Note that LegalizeOp may be reentered even from single-use nodes, which
1718 // means that we always must cache transformed nodes.
1719 AddLegalizedOperand(Op, Result);
1723 SDValue SelectionDAGLegalize::ExpandExtractFromVectorThroughStack(SDValue Op) {
1724 SDValue Vec = Op.getOperand(0);
1725 SDValue Idx = Op.getOperand(1);
1726 DebugLoc dl = Op.getDebugLoc();
1727 // Store the value to a temporary stack slot, then LOAD the returned part.
1728 SDValue StackPtr = DAG.CreateStackTemporary(Vec.getValueType());
1729 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, Vec, StackPtr,
1730 MachinePointerInfo(), false, false, 0);
1732 // Add the offset to the index.
1734 Vec.getValueType().getVectorElementType().getSizeInBits()/8;
1735 Idx = DAG.getNode(ISD::MUL, dl, Idx.getValueType(), Idx,
1736 DAG.getConstant(EltSize, Idx.getValueType()));
1738 if (Idx.getValueType().bitsGT(TLI.getPointerTy()))
1739 Idx = DAG.getNode(ISD::TRUNCATE, dl, TLI.getPointerTy(), Idx);
1741 Idx = DAG.getNode(ISD::ZERO_EXTEND, dl, TLI.getPointerTy(), Idx);
1743 StackPtr = DAG.getNode(ISD::ADD, dl, Idx.getValueType(), Idx, StackPtr);
1745 if (Op.getValueType().isVector())
1746 return DAG.getLoad(Op.getValueType(), dl, Ch, StackPtr,MachinePointerInfo(),
1748 return DAG.getExtLoad(ISD::EXTLOAD, dl, Op.getValueType(), Ch, StackPtr,
1749 MachinePointerInfo(),
1750 Vec.getValueType().getVectorElementType(),
1754 SDValue SelectionDAGLegalize::ExpandInsertToVectorThroughStack(SDValue Op) {
1755 assert(Op.getValueType().isVector() && "Non-vector insert subvector!");
1757 SDValue Vec = Op.getOperand(0);
1758 SDValue Part = Op.getOperand(1);
1759 SDValue Idx = Op.getOperand(2);
1760 DebugLoc dl = Op.getDebugLoc();
1762 // Store the value to a temporary stack slot, then LOAD the returned part.
1764 SDValue StackPtr = DAG.CreateStackTemporary(Vec.getValueType());
1765 int FI = cast<FrameIndexSDNode>(StackPtr.getNode())->getIndex();
1766 MachinePointerInfo PtrInfo = MachinePointerInfo::getFixedStack(FI);
1768 // First store the whole vector.
1769 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, Vec, StackPtr, PtrInfo,
1772 // Then store the inserted part.
1774 // Add the offset to the index.
1776 Vec.getValueType().getVectorElementType().getSizeInBits()/8;
1778 Idx = DAG.getNode(ISD::MUL, dl, Idx.getValueType(), Idx,
1779 DAG.getConstant(EltSize, Idx.getValueType()));
1781 if (Idx.getValueType().bitsGT(TLI.getPointerTy()))
1782 Idx = DAG.getNode(ISD::TRUNCATE, dl, TLI.getPointerTy(), Idx);
1784 Idx = DAG.getNode(ISD::ZERO_EXTEND, dl, TLI.getPointerTy(), Idx);
1786 SDValue SubStackPtr = DAG.getNode(ISD::ADD, dl, Idx.getValueType(), Idx,
1789 // Store the subvector.
1790 Ch = DAG.getStore(DAG.getEntryNode(), dl, Part, SubStackPtr,
1791 MachinePointerInfo(), false, false, 0);
1793 // Finally, load the updated vector.
1794 return DAG.getLoad(Op.getValueType(), dl, Ch, StackPtr, PtrInfo,
1798 SDValue SelectionDAGLegalize::ExpandVectorBuildThroughStack(SDNode* Node) {
1799 // We can't handle this case efficiently. Allocate a sufficiently
1800 // aligned object on the stack, store each element into it, then load
1801 // the result as a vector.
1802 // Create the stack frame object.
1803 EVT VT = Node->getValueType(0);
1804 EVT EltVT = VT.getVectorElementType();
1805 DebugLoc dl = Node->getDebugLoc();
1806 SDValue FIPtr = DAG.CreateStackTemporary(VT);
1807 int FI = cast<FrameIndexSDNode>(FIPtr.getNode())->getIndex();
1808 MachinePointerInfo PtrInfo = MachinePointerInfo::getFixedStack(FI);
1810 // Emit a store of each element to the stack slot.
1811 SmallVector<SDValue, 8> Stores;
1812 unsigned TypeByteSize = EltVT.getSizeInBits() / 8;
1813 // Store (in the right endianness) the elements to memory.
1814 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
1815 // Ignore undef elements.
1816 if (Node->getOperand(i).getOpcode() == ISD::UNDEF) continue;
1818 unsigned Offset = TypeByteSize*i;
1820 SDValue Idx = DAG.getConstant(Offset, FIPtr.getValueType());
1821 Idx = DAG.getNode(ISD::ADD, dl, FIPtr.getValueType(), FIPtr, Idx);
1823 // If the destination vector element type is narrower than the source
1824 // element type, only store the bits necessary.
1825 if (EltVT.bitsLT(Node->getOperand(i).getValueType().getScalarType())) {
1826 Stores.push_back(DAG.getTruncStore(DAG.getEntryNode(), dl,
1827 Node->getOperand(i), Idx,
1828 PtrInfo.getWithOffset(Offset),
1829 EltVT, false, false, 0));
1831 Stores.push_back(DAG.getStore(DAG.getEntryNode(), dl,
1832 Node->getOperand(i), Idx,
1833 PtrInfo.getWithOffset(Offset),
1838 if (!Stores.empty()) // Not all undef elements?
1839 StoreChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
1840 &Stores[0], Stores.size());
1842 StoreChain = DAG.getEntryNode();
1844 // Result is a load from the stack slot.
1845 return DAG.getLoad(VT, dl, StoreChain, FIPtr, PtrInfo, false, false, 0);
1848 SDValue SelectionDAGLegalize::ExpandFCOPYSIGN(SDNode* Node) {
1849 DebugLoc dl = Node->getDebugLoc();
1850 SDValue Tmp1 = Node->getOperand(0);
1851 SDValue Tmp2 = Node->getOperand(1);
1853 // Get the sign bit of the RHS. First obtain a value that has the same
1854 // sign as the sign bit, i.e. negative if and only if the sign bit is 1.
1856 EVT FloatVT = Tmp2.getValueType();
1857 EVT IVT = EVT::getIntegerVT(*DAG.getContext(), FloatVT.getSizeInBits());
1858 if (TLI.isTypeLegal(IVT)) {
1859 // Convert to an integer with the same sign bit.
1860 SignBit = DAG.getNode(ISD::BITCAST, dl, IVT, Tmp2);
1862 // Store the float to memory, then load the sign part out as an integer.
1863 MVT LoadTy = TLI.getPointerTy();
1864 // First create a temporary that is aligned for both the load and store.
1865 SDValue StackPtr = DAG.CreateStackTemporary(FloatVT, LoadTy);
1866 // Then store the float to it.
1868 DAG.getStore(DAG.getEntryNode(), dl, Tmp2, StackPtr, MachinePointerInfo(),
1870 if (TLI.isBigEndian()) {
1871 assert(FloatVT.isByteSized() && "Unsupported floating point type!");
1872 // Load out a legal integer with the same sign bit as the float.
1873 SignBit = DAG.getLoad(LoadTy, dl, Ch, StackPtr, MachinePointerInfo(),
1875 } else { // Little endian
1876 SDValue LoadPtr = StackPtr;
1877 // The float may be wider than the integer we are going to load. Advance
1878 // the pointer so that the loaded integer will contain the sign bit.
1879 unsigned Strides = (FloatVT.getSizeInBits()-1)/LoadTy.getSizeInBits();
1880 unsigned ByteOffset = (Strides * LoadTy.getSizeInBits()) / 8;
1881 LoadPtr = DAG.getNode(ISD::ADD, dl, LoadPtr.getValueType(),
1882 LoadPtr, DAG.getIntPtrConstant(ByteOffset));
1883 // Load a legal integer containing the sign bit.
1884 SignBit = DAG.getLoad(LoadTy, dl, Ch, LoadPtr, MachinePointerInfo(),
1886 // Move the sign bit to the top bit of the loaded integer.
1887 unsigned BitShift = LoadTy.getSizeInBits() -
1888 (FloatVT.getSizeInBits() - 8 * ByteOffset);
1889 assert(BitShift < LoadTy.getSizeInBits() && "Pointer advanced wrong?");
1891 SignBit = DAG.getNode(ISD::SHL, dl, LoadTy, SignBit,
1892 DAG.getConstant(BitShift,
1893 TLI.getShiftAmountTy(SignBit.getValueType())));
1896 // Now get the sign bit proper, by seeing whether the value is negative.
1897 SignBit = DAG.getSetCC(dl, TLI.getSetCCResultType(SignBit.getValueType()),
1898 SignBit, DAG.getConstant(0, SignBit.getValueType()),
1900 // Get the absolute value of the result.
1901 SDValue AbsVal = DAG.getNode(ISD::FABS, dl, Tmp1.getValueType(), Tmp1);
1902 // Select between the nabs and abs value based on the sign bit of
1904 return DAG.getNode(ISD::SELECT, dl, AbsVal.getValueType(), SignBit,
1905 DAG.getNode(ISD::FNEG, dl, AbsVal.getValueType(), AbsVal),
1909 void SelectionDAGLegalize::ExpandDYNAMIC_STACKALLOC(SDNode* Node,
1910 SmallVectorImpl<SDValue> &Results) {
1911 unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore();
1912 assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and"
1913 " not tell us which reg is the stack pointer!");
1914 DebugLoc dl = Node->getDebugLoc();
1915 EVT VT = Node->getValueType(0);
1916 SDValue Tmp1 = SDValue(Node, 0);
1917 SDValue Tmp2 = SDValue(Node, 1);
1918 SDValue Tmp3 = Node->getOperand(2);
1919 SDValue Chain = Tmp1.getOperand(0);
1921 // Chain the dynamic stack allocation so that it doesn't modify the stack
1922 // pointer when other instructions are using the stack.
1923 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(0, true));
1925 SDValue Size = Tmp2.getOperand(1);
1926 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, VT);
1927 Chain = SP.getValue(1);
1928 unsigned Align = cast<ConstantSDNode>(Tmp3)->getZExtValue();
1929 unsigned StackAlign = TM.getFrameLowering()->getStackAlignment();
1930 if (Align > StackAlign)
1931 SP = DAG.getNode(ISD::AND, dl, VT, SP,
1932 DAG.getConstant(-(uint64_t)Align, VT));
1933 Tmp1 = DAG.getNode(ISD::SUB, dl, VT, SP, Size); // Value
1934 Chain = DAG.getCopyToReg(Chain, dl, SPReg, Tmp1); // Output chain
1936 Tmp2 = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(0, true),
1937 DAG.getIntPtrConstant(0, true), SDValue());
1939 Results.push_back(Tmp1);
1940 Results.push_back(Tmp2);
1943 /// LegalizeSetCCCondCode - Legalize a SETCC with given LHS and RHS and
1944 /// condition code CC on the current target. This routine expands SETCC with
1945 /// illegal condition code into AND / OR of multiple SETCC values.
1946 void SelectionDAGLegalize::LegalizeSetCCCondCode(EVT VT,
1947 SDValue &LHS, SDValue &RHS,
1950 EVT OpVT = LHS.getValueType();
1951 ISD::CondCode CCCode = cast<CondCodeSDNode>(CC)->get();
1952 switch (TLI.getCondCodeAction(CCCode, OpVT)) {
1953 default: assert(0 && "Unknown condition code action!");
1954 case TargetLowering::Legal:
1957 case TargetLowering::Expand: {
1958 ISD::CondCode CC1 = ISD::SETCC_INVALID, CC2 = ISD::SETCC_INVALID;
1961 default: assert(0 && "Don't know how to expand this condition!");
1962 case ISD::SETOEQ: CC1 = ISD::SETEQ; CC2 = ISD::SETO; Opc = ISD::AND; break;
1963 case ISD::SETOGT: CC1 = ISD::SETGT; CC2 = ISD::SETO; Opc = ISD::AND; break;
1964 case ISD::SETOGE: CC1 = ISD::SETGE; CC2 = ISD::SETO; Opc = ISD::AND; break;
1965 case ISD::SETOLT: CC1 = ISD::SETLT; CC2 = ISD::SETO; Opc = ISD::AND; break;
1966 case ISD::SETOLE: CC1 = ISD::SETLE; CC2 = ISD::SETO; Opc = ISD::AND; break;
1967 case ISD::SETONE: CC1 = ISD::SETNE; CC2 = ISD::SETO; Opc = ISD::AND; break;
1968 case ISD::SETUEQ: CC1 = ISD::SETEQ; CC2 = ISD::SETUO; Opc = ISD::OR; break;
1969 case ISD::SETUGT: CC1 = ISD::SETGT; CC2 = ISD::SETUO; Opc = ISD::OR; break;
1970 case ISD::SETUGE: CC1 = ISD::SETGE; CC2 = ISD::SETUO; Opc = ISD::OR; break;
1971 case ISD::SETULT: CC1 = ISD::SETLT; CC2 = ISD::SETUO; Opc = ISD::OR; break;
1972 case ISD::SETULE: CC1 = ISD::SETLE; CC2 = ISD::SETUO; Opc = ISD::OR; break;
1973 case ISD::SETUNE: CC1 = ISD::SETNE; CC2 = ISD::SETUO; Opc = ISD::OR; break;
1974 // FIXME: Implement more expansions.
1977 SDValue SetCC1 = DAG.getSetCC(dl, VT, LHS, RHS, CC1);
1978 SDValue SetCC2 = DAG.getSetCC(dl, VT, LHS, RHS, CC2);
1979 LHS = DAG.getNode(Opc, dl, VT, SetCC1, SetCC2);
1987 /// EmitStackConvert - Emit a store/load combination to the stack. This stores
1988 /// SrcOp to a stack slot of type SlotVT, truncating it if needed. It then does
1989 /// a load from the stack slot to DestVT, extending it if needed.
1990 /// The resultant code need not be legal.
1991 SDValue SelectionDAGLegalize::EmitStackConvert(SDValue SrcOp,
1995 // Create the stack frame object.
1997 TLI.getTargetData()->getPrefTypeAlignment(SrcOp.getValueType().
1998 getTypeForEVT(*DAG.getContext()));
1999 SDValue FIPtr = DAG.CreateStackTemporary(SlotVT, SrcAlign);
2001 FrameIndexSDNode *StackPtrFI = cast<FrameIndexSDNode>(FIPtr);
2002 int SPFI = StackPtrFI->getIndex();
2003 MachinePointerInfo PtrInfo = MachinePointerInfo::getFixedStack(SPFI);
2005 unsigned SrcSize = SrcOp.getValueType().getSizeInBits();
2006 unsigned SlotSize = SlotVT.getSizeInBits();
2007 unsigned DestSize = DestVT.getSizeInBits();
2008 const Type *DestType = DestVT.getTypeForEVT(*DAG.getContext());
2009 unsigned DestAlign = TLI.getTargetData()->getPrefTypeAlignment(DestType);
2011 // Emit a store to the stack slot. Use a truncstore if the input value is
2012 // later than DestVT.
2015 if (SrcSize > SlotSize)
2016 Store = DAG.getTruncStore(DAG.getEntryNode(), dl, SrcOp, FIPtr,
2017 PtrInfo, SlotVT, false, false, SrcAlign);
2019 assert(SrcSize == SlotSize && "Invalid store");
2020 Store = DAG.getStore(DAG.getEntryNode(), dl, SrcOp, FIPtr,
2021 PtrInfo, false, false, SrcAlign);
2024 // Result is a load from the stack slot.
2025 if (SlotSize == DestSize)
2026 return DAG.getLoad(DestVT, dl, Store, FIPtr, PtrInfo,
2027 false, false, DestAlign);
2029 assert(SlotSize < DestSize && "Unknown extension!");
2030 return DAG.getExtLoad(ISD::EXTLOAD, dl, DestVT, Store, FIPtr,
2031 PtrInfo, SlotVT, false, false, DestAlign);
2034 SDValue SelectionDAGLegalize::ExpandSCALAR_TO_VECTOR(SDNode *Node) {
2035 DebugLoc dl = Node->getDebugLoc();
2036 // Create a vector sized/aligned stack slot, store the value to element #0,
2037 // then load the whole vector back out.
2038 SDValue StackPtr = DAG.CreateStackTemporary(Node->getValueType(0));
2040 FrameIndexSDNode *StackPtrFI = cast<FrameIndexSDNode>(StackPtr);
2041 int SPFI = StackPtrFI->getIndex();
2043 SDValue Ch = DAG.getTruncStore(DAG.getEntryNode(), dl, Node->getOperand(0),
2045 MachinePointerInfo::getFixedStack(SPFI),
2046 Node->getValueType(0).getVectorElementType(),
2048 return DAG.getLoad(Node->getValueType(0), dl, Ch, StackPtr,
2049 MachinePointerInfo::getFixedStack(SPFI),
2054 /// ExpandBUILD_VECTOR - Expand a BUILD_VECTOR node on targets that don't
2055 /// support the operation, but do support the resultant vector type.
2056 SDValue SelectionDAGLegalize::ExpandBUILD_VECTOR(SDNode *Node) {
2057 unsigned NumElems = Node->getNumOperands();
2058 SDValue Value1, Value2;
2059 DebugLoc dl = Node->getDebugLoc();
2060 EVT VT = Node->getValueType(0);
2061 EVT OpVT = Node->getOperand(0).getValueType();
2062 EVT EltVT = VT.getVectorElementType();
2064 // If the only non-undef value is the low element, turn this into a
2065 // SCALAR_TO_VECTOR node. If this is { X, X, X, X }, determine X.
2066 bool isOnlyLowElement = true;
2067 bool MoreThanTwoValues = false;
2068 bool isConstant = true;
2069 for (unsigned i = 0; i < NumElems; ++i) {
2070 SDValue V = Node->getOperand(i);
2071 if (V.getOpcode() == ISD::UNDEF)
2074 isOnlyLowElement = false;
2075 if (!isa<ConstantFPSDNode>(V) && !isa<ConstantSDNode>(V))
2078 if (!Value1.getNode()) {
2080 } else if (!Value2.getNode()) {
2083 } else if (V != Value1 && V != Value2) {
2084 MoreThanTwoValues = true;
2088 if (!Value1.getNode())
2089 return DAG.getUNDEF(VT);
2091 if (isOnlyLowElement)
2092 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Node->getOperand(0));
2094 // If all elements are constants, create a load from the constant pool.
2096 std::vector<Constant*> CV;
2097 for (unsigned i = 0, e = NumElems; i != e; ++i) {
2098 if (ConstantFPSDNode *V =
2099 dyn_cast<ConstantFPSDNode>(Node->getOperand(i))) {
2100 CV.push_back(const_cast<ConstantFP *>(V->getConstantFPValue()));
2101 } else if (ConstantSDNode *V =
2102 dyn_cast<ConstantSDNode>(Node->getOperand(i))) {
2104 CV.push_back(const_cast<ConstantInt *>(V->getConstantIntValue()));
2106 // If OpVT and EltVT don't match, EltVT is not legal and the
2107 // element values have been promoted/truncated earlier. Undo this;
2108 // we don't want a v16i8 to become a v16i32 for example.
2109 const ConstantInt *CI = V->getConstantIntValue();
2110 CV.push_back(ConstantInt::get(EltVT.getTypeForEVT(*DAG.getContext()),
2111 CI->getZExtValue()));
2114 assert(Node->getOperand(i).getOpcode() == ISD::UNDEF);
2115 const Type *OpNTy = EltVT.getTypeForEVT(*DAG.getContext());
2116 CV.push_back(UndefValue::get(OpNTy));
2119 Constant *CP = ConstantVector::get(CV);
2120 SDValue CPIdx = DAG.getConstantPool(CP, TLI.getPointerTy());
2121 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
2122 return DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
2123 MachinePointerInfo::getConstantPool(),
2124 false, false, Alignment);
2127 if (!MoreThanTwoValues) {
2128 SmallVector<int, 8> ShuffleVec(NumElems, -1);
2129 for (unsigned i = 0; i < NumElems; ++i) {
2130 SDValue V = Node->getOperand(i);
2131 if (V.getOpcode() == ISD::UNDEF)
2133 ShuffleVec[i] = V == Value1 ? 0 : NumElems;
2135 if (TLI.isShuffleMaskLegal(ShuffleVec, Node->getValueType(0))) {
2136 // Get the splatted value into the low element of a vector register.
2137 SDValue Vec1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Value1);
2139 if (Value2.getNode())
2140 Vec2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Value2);
2142 Vec2 = DAG.getUNDEF(VT);
2144 // Return shuffle(LowValVec, undef, <0,0,0,0>)
2145 return DAG.getVectorShuffle(VT, dl, Vec1, Vec2, ShuffleVec.data());
2149 // Otherwise, we can't handle this case efficiently.
2150 return ExpandVectorBuildThroughStack(Node);
2153 // ExpandLibCall - Expand a node into a call to a libcall. If the result value
2154 // does not fit into a register, return the lo part and set the hi part to the
2155 // by-reg argument. If it does fit into a single register, return the result
2156 // and leave the Hi part unset.
2157 SDValue SelectionDAGLegalize::ExpandLibCall(RTLIB::Libcall LC, SDNode *Node,
2159 // The input chain to this libcall is the entry node of the function.
2160 // Legalizing the call will automatically add the previous call to the
2162 SDValue InChain = DAG.getEntryNode();
2164 TargetLowering::ArgListTy Args;
2165 TargetLowering::ArgListEntry Entry;
2166 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
2167 EVT ArgVT = Node->getOperand(i).getValueType();
2168 const Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
2169 Entry.Node = Node->getOperand(i); Entry.Ty = ArgTy;
2170 Entry.isSExt = isSigned;
2171 Entry.isZExt = !isSigned;
2172 Args.push_back(Entry);
2174 SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC),
2175 TLI.getPointerTy());
2177 // Splice the libcall in wherever FindInputOutputChains tells us to.
2178 const Type *RetTy = Node->getValueType(0).getTypeForEVT(*DAG.getContext());
2180 // isTailCall may be true since the callee does not reference caller stack
2181 // frame. Check if it's in the right position.
2182 bool isTailCall = isInTailCallPosition(DAG, Node, TLI);
2183 std::pair<SDValue, SDValue> CallInfo =
2184 TLI.LowerCallTo(InChain, RetTy, isSigned, !isSigned, false, false,
2185 0, TLI.getLibcallCallingConv(LC), isTailCall,
2186 /*isReturnValueUsed=*/true,
2187 Callee, Args, DAG, Node->getDebugLoc());
2189 if (!CallInfo.second.getNode())
2190 // It's a tailcall, return the chain (which is the DAG root).
2191 return DAG.getRoot();
2193 // Legalize the call sequence, starting with the chain. This will advance
2194 // the LastCALLSEQ to the legalized version of the CALLSEQ_END node that
2195 // was added by LowerCallTo (guaranteeing proper serialization of calls).
2196 LegalizeOp(CallInfo.second);
2197 return CallInfo.first;
2200 /// ExpandLibCall - Generate a libcall taking the given operands as arguments
2201 /// and returning a result of type RetVT.
2202 SDValue SelectionDAGLegalize::ExpandLibCall(RTLIB::Libcall LC, EVT RetVT,
2203 const SDValue *Ops, unsigned NumOps,
2204 bool isSigned, DebugLoc dl) {
2205 TargetLowering::ArgListTy Args;
2206 Args.reserve(NumOps);
2208 TargetLowering::ArgListEntry Entry;
2209 for (unsigned i = 0; i != NumOps; ++i) {
2210 Entry.Node = Ops[i];
2211 Entry.Ty = Entry.Node.getValueType().getTypeForEVT(*DAG.getContext());
2212 Entry.isSExt = isSigned;
2213 Entry.isZExt = !isSigned;
2214 Args.push_back(Entry);
2216 SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC),
2217 TLI.getPointerTy());
2219 const Type *RetTy = RetVT.getTypeForEVT(*DAG.getContext());
2220 std::pair<SDValue,SDValue> CallInfo =
2221 TLI.LowerCallTo(DAG.getEntryNode(), RetTy, isSigned, !isSigned, false,
2222 false, 0, TLI.getLibcallCallingConv(LC), false,
2223 /*isReturnValueUsed=*/true,
2224 Callee, Args, DAG, dl);
2226 // Legalize the call sequence, starting with the chain. This will advance
2227 // the LastCALLSEQ_END to the legalized version of the CALLSEQ_END node that
2228 // was added by LowerCallTo (guaranteeing proper serialization of calls).
2229 LegalizeOp(CallInfo.second);
2231 return CallInfo.first;
2234 // ExpandChainLibCall - Expand a node into a call to a libcall. Similar to
2235 // ExpandLibCall except that the first operand is the in-chain.
2236 std::pair<SDValue, SDValue>
2237 SelectionDAGLegalize::ExpandChainLibCall(RTLIB::Libcall LC,
2240 SDValue InChain = Node->getOperand(0);
2242 TargetLowering::ArgListTy Args;
2243 TargetLowering::ArgListEntry Entry;
2244 for (unsigned i = 1, e = Node->getNumOperands(); i != e; ++i) {
2245 EVT ArgVT = Node->getOperand(i).getValueType();
2246 const Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
2247 Entry.Node = Node->getOperand(i);
2249 Entry.isSExt = isSigned;
2250 Entry.isZExt = !isSigned;
2251 Args.push_back(Entry);
2253 SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC),
2254 TLI.getPointerTy());
2256 // Splice the libcall in wherever FindInputOutputChains tells us to.
2257 const Type *RetTy = Node->getValueType(0).getTypeForEVT(*DAG.getContext());
2258 std::pair<SDValue, SDValue> CallInfo =
2259 TLI.LowerCallTo(InChain, RetTy, isSigned, !isSigned, false, false,
2260 0, TLI.getLibcallCallingConv(LC), /*isTailCall=*/false,
2261 /*isReturnValueUsed=*/true,
2262 Callee, Args, DAG, Node->getDebugLoc());
2264 // Legalize the call sequence, starting with the chain. This will advance
2265 // the LastCALLSEQ to the legalized version of the CALLSEQ_END node that
2266 // was added by LowerCallTo (guaranteeing proper serialization of calls).
2267 LegalizeOp(CallInfo.second);
2271 SDValue SelectionDAGLegalize::ExpandFPLibCall(SDNode* Node,
2272 RTLIB::Libcall Call_F32,
2273 RTLIB::Libcall Call_F64,
2274 RTLIB::Libcall Call_F80,
2275 RTLIB::Libcall Call_PPCF128) {
2277 switch (Node->getValueType(0).getSimpleVT().SimpleTy) {
2278 default: assert(0 && "Unexpected request for libcall!");
2279 case MVT::f32: LC = Call_F32; break;
2280 case MVT::f64: LC = Call_F64; break;
2281 case MVT::f80: LC = Call_F80; break;
2282 case MVT::ppcf128: LC = Call_PPCF128; break;
2284 return ExpandLibCall(LC, Node, false);
2287 SDValue SelectionDAGLegalize::ExpandIntLibCall(SDNode* Node, bool isSigned,
2288 RTLIB::Libcall Call_I8,
2289 RTLIB::Libcall Call_I16,
2290 RTLIB::Libcall Call_I32,
2291 RTLIB::Libcall Call_I64,
2292 RTLIB::Libcall Call_I128) {
2294 switch (Node->getValueType(0).getSimpleVT().SimpleTy) {
2295 default: assert(0 && "Unexpected request for libcall!");
2296 case MVT::i8: LC = Call_I8; break;
2297 case MVT::i16: LC = Call_I16; break;
2298 case MVT::i32: LC = Call_I32; break;
2299 case MVT::i64: LC = Call_I64; break;
2300 case MVT::i128: LC = Call_I128; break;
2302 return ExpandLibCall(LC, Node, isSigned);
2305 /// isDivRemLibcallAvailable - Return true if divmod libcall is available.
2306 static bool isDivRemLibcallAvailable(SDNode *Node, bool isSigned,
2307 const TargetLowering &TLI) {
2309 switch (Node->getValueType(0).getSimpleVT().SimpleTy) {
2310 default: assert(0 && "Unexpected request for libcall!");
2311 case MVT::i8: LC= isSigned ? RTLIB::SDIVREM_I8 : RTLIB::UDIVREM_I8; break;
2312 case MVT::i16: LC= isSigned ? RTLIB::SDIVREM_I16 : RTLIB::UDIVREM_I16; break;
2313 case MVT::i32: LC= isSigned ? RTLIB::SDIVREM_I32 : RTLIB::UDIVREM_I32; break;
2314 case MVT::i64: LC= isSigned ? RTLIB::SDIVREM_I64 : RTLIB::UDIVREM_I64; break;
2315 case MVT::i128: LC= isSigned ? RTLIB::SDIVREM_I128:RTLIB::UDIVREM_I128; break;
2318 return TLI.getLibcallName(LC) != 0;
2321 /// UseDivRem - Only issue divrem libcall if both quotient and remainder are
2323 static bool UseDivRem(SDNode *Node, bool isSigned, bool isDIV) {
2324 unsigned OtherOpcode = 0;
2326 OtherOpcode = isDIV ? ISD::SREM : ISD::SDIV;
2328 OtherOpcode = isDIV ? ISD::UREM : ISD::UDIV;
2330 SDValue Op0 = Node->getOperand(0);
2331 SDValue Op1 = Node->getOperand(1);
2332 for (SDNode::use_iterator UI = Op0.getNode()->use_begin(),
2333 UE = Op0.getNode()->use_end(); UI != UE; ++UI) {
2337 if (User->getOpcode() == OtherOpcode &&
2338 User->getOperand(0) == Op0 &&
2339 User->getOperand(1) == Op1)
2345 /// ExpandDivRemLibCall - Issue libcalls to __{u}divmod to compute div / rem
2348 SelectionDAGLegalize::ExpandDivRemLibCall(SDNode *Node,
2349 SmallVectorImpl<SDValue> &Results) {
2350 unsigned Opcode = Node->getOpcode();
2351 bool isSigned = Opcode == ISD::SDIVREM;
2354 switch (Node->getValueType(0).getSimpleVT().SimpleTy) {
2355 default: assert(0 && "Unexpected request for libcall!");
2356 case MVT::i8: LC= isSigned ? RTLIB::SDIVREM_I8 : RTLIB::UDIVREM_I8; break;
2357 case MVT::i16: LC= isSigned ? RTLIB::SDIVREM_I16 : RTLIB::UDIVREM_I16; break;
2358 case MVT::i32: LC= isSigned ? RTLIB::SDIVREM_I32 : RTLIB::UDIVREM_I32; break;
2359 case MVT::i64: LC= isSigned ? RTLIB::SDIVREM_I64 : RTLIB::UDIVREM_I64; break;
2360 case MVT::i128: LC= isSigned ? RTLIB::SDIVREM_I128:RTLIB::UDIVREM_I128; break;
2363 // The input chain to this libcall is the entry node of the function.
2364 // Legalizing the call will automatically add the previous call to the
2366 SDValue InChain = DAG.getEntryNode();
2368 EVT RetVT = Node->getValueType(0);
2369 const Type *RetTy = RetVT.getTypeForEVT(*DAG.getContext());
2371 TargetLowering::ArgListTy Args;
2372 TargetLowering::ArgListEntry Entry;
2373 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
2374 EVT ArgVT = Node->getOperand(i).getValueType();
2375 const Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
2376 Entry.Node = Node->getOperand(i); Entry.Ty = ArgTy;
2377 Entry.isSExt = isSigned;
2378 Entry.isZExt = !isSigned;
2379 Args.push_back(Entry);
2382 // Also pass the return address of the remainder.
2383 SDValue FIPtr = DAG.CreateStackTemporary(RetVT);
2385 Entry.Ty = RetTy->getPointerTo();
2386 Entry.isSExt = isSigned;
2387 Entry.isZExt = !isSigned;
2388 Args.push_back(Entry);
2390 SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC),
2391 TLI.getPointerTy());
2393 // Splice the libcall in wherever FindInputOutputChains tells us to.
2394 DebugLoc dl = Node->getDebugLoc();
2395 std::pair<SDValue, SDValue> CallInfo =
2396 TLI.LowerCallTo(InChain, RetTy, isSigned, !isSigned, false, false,
2397 0, TLI.getLibcallCallingConv(LC), /*isTailCall=*/false,
2398 /*isReturnValueUsed=*/true, Callee, Args, DAG, dl);
2400 // Legalize the call sequence, starting with the chain. This will advance
2401 // the LastCALLSEQ to the legalized version of the CALLSEQ_END node that
2402 // was added by LowerCallTo (guaranteeing proper serialization of calls).
2403 LegalizeOp(CallInfo.second);
2405 // Remainder is loaded back from the stack frame.
2406 SDValue Rem = DAG.getLoad(RetVT, dl, getLastCALLSEQ(), FIPtr,
2407 MachinePointerInfo(), false, false, 0);
2408 Results.push_back(CallInfo.first);
2409 Results.push_back(Rem);
2412 /// ExpandLegalINT_TO_FP - This function is responsible for legalizing a
2413 /// INT_TO_FP operation of the specified operand when the target requests that
2414 /// we expand it. At this point, we know that the result and operand types are
2415 /// legal for the target.
2416 SDValue SelectionDAGLegalize::ExpandLegalINT_TO_FP(bool isSigned,
2420 if (Op0.getValueType() == MVT::i32) {
2421 // simple 32-bit [signed|unsigned] integer to float/double expansion
2423 // Get the stack frame index of a 8 byte buffer.
2424 SDValue StackSlot = DAG.CreateStackTemporary(MVT::f64);
2426 // word offset constant for Hi/Lo address computation
2427 SDValue WordOff = DAG.getConstant(sizeof(int), TLI.getPointerTy());
2428 // set up Hi and Lo (into buffer) address based on endian
2429 SDValue Hi = StackSlot;
2430 SDValue Lo = DAG.getNode(ISD::ADD, dl,
2431 TLI.getPointerTy(), StackSlot, WordOff);
2432 if (TLI.isLittleEndian())
2435 // if signed map to unsigned space
2438 // constant used to invert sign bit (signed to unsigned mapping)
2439 SDValue SignBit = DAG.getConstant(0x80000000u, MVT::i32);
2440 Op0Mapped = DAG.getNode(ISD::XOR, dl, MVT::i32, Op0, SignBit);
2444 // store the lo of the constructed double - based on integer input
2445 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl,
2446 Op0Mapped, Lo, MachinePointerInfo(),
2448 // initial hi portion of constructed double
2449 SDValue InitialHi = DAG.getConstant(0x43300000u, MVT::i32);
2450 // store the hi of the constructed double - biased exponent
2451 SDValue Store2 = DAG.getStore(Store1, dl, InitialHi, Hi,
2452 MachinePointerInfo(),
2454 // load the constructed double
2455 SDValue Load = DAG.getLoad(MVT::f64, dl, Store2, StackSlot,
2456 MachinePointerInfo(), false, false, 0);
2457 // FP constant to bias correct the final result
2458 SDValue Bias = DAG.getConstantFP(isSigned ?
2459 BitsToDouble(0x4330000080000000ULL) :
2460 BitsToDouble(0x4330000000000000ULL),
2462 // subtract the bias
2463 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Load, Bias);
2466 // handle final rounding
2467 if (DestVT == MVT::f64) {
2470 } else if (DestVT.bitsLT(MVT::f64)) {
2471 Result = DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub,
2472 DAG.getIntPtrConstant(0));
2473 } else if (DestVT.bitsGT(MVT::f64)) {
2474 Result = DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub);
2478 assert(!isSigned && "Legalize cannot Expand SINT_TO_FP for i64 yet");
2479 // Code below here assumes !isSigned without checking again.
2481 // Implementation of unsigned i64 to f64 following the algorithm in
2482 // __floatundidf in compiler_rt. This implementation has the advantage
2483 // of performing rounding correctly, both in the default rounding mode
2484 // and in all alternate rounding modes.
2485 // TODO: Generalize this for use with other types.
2486 if (Op0.getValueType() == MVT::i64 && DestVT == MVT::f64) {
2488 DAG.getConstant(UINT64_C(0x4330000000000000), MVT::i64);
2489 SDValue TwoP84PlusTwoP52 =
2490 DAG.getConstantFP(BitsToDouble(UINT64_C(0x4530000000100000)), MVT::f64);
2492 DAG.getConstant(UINT64_C(0x4530000000000000), MVT::i64);
2494 SDValue Lo = DAG.getZeroExtendInReg(Op0, dl, MVT::i32);
2495 SDValue Hi = DAG.getNode(ISD::SRL, dl, MVT::i64, Op0,
2496 DAG.getConstant(32, MVT::i64));
2497 SDValue LoOr = DAG.getNode(ISD::OR, dl, MVT::i64, Lo, TwoP52);
2498 SDValue HiOr = DAG.getNode(ISD::OR, dl, MVT::i64, Hi, TwoP84);
2499 SDValue LoFlt = DAG.getNode(ISD::BITCAST, dl, MVT::f64, LoOr);
2500 SDValue HiFlt = DAG.getNode(ISD::BITCAST, dl, MVT::f64, HiOr);
2501 SDValue HiSub = DAG.getNode(ISD::FSUB, dl, MVT::f64, HiFlt,
2503 return DAG.getNode(ISD::FADD, dl, MVT::f64, LoFlt, HiSub);
2506 // Implementation of unsigned i64 to f32.
2507 // TODO: Generalize this for use with other types.
2508 if (Op0.getValueType() == MVT::i64 && DestVT == MVT::f32) {
2509 // For unsigned conversions, convert them to signed conversions using the
2510 // algorithm from the x86_64 __floatundidf in compiler_rt.
2512 SDValue Fast = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, Op0);
2514 SDValue ShiftConst =
2515 DAG.getConstant(1, TLI.getShiftAmountTy(Op0.getValueType()));
2516 SDValue Shr = DAG.getNode(ISD::SRL, dl, MVT::i64, Op0, ShiftConst);
2517 SDValue AndConst = DAG.getConstant(1, MVT::i64);
2518 SDValue And = DAG.getNode(ISD::AND, dl, MVT::i64, Op0, AndConst);
2519 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::i64, And, Shr);
2521 SDValue SignCvt = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, Or);
2522 SDValue Slow = DAG.getNode(ISD::FADD, dl, MVT::f32, SignCvt, SignCvt);
2524 // TODO: This really should be implemented using a branch rather than a
2525 // select. We happen to get lucky and machinesink does the right
2526 // thing most of the time. This would be a good candidate for a
2527 //pseudo-op, or, even better, for whole-function isel.
2528 SDValue SignBitTest = DAG.getSetCC(dl, TLI.getSetCCResultType(MVT::i64),
2529 Op0, DAG.getConstant(0, MVT::i64), ISD::SETLT);
2530 return DAG.getNode(ISD::SELECT, dl, MVT::f32, SignBitTest, Slow, Fast);
2533 // Otherwise, implement the fully general conversion.
2535 SDValue And = DAG.getNode(ISD::AND, dl, MVT::i64, Op0,
2536 DAG.getConstant(UINT64_C(0xfffffffffffff800), MVT::i64));
2537 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::i64, And,
2538 DAG.getConstant(UINT64_C(0x800), MVT::i64));
2539 SDValue And2 = DAG.getNode(ISD::AND, dl, MVT::i64, Op0,
2540 DAG.getConstant(UINT64_C(0x7ff), MVT::i64));
2541 SDValue Ne = DAG.getSetCC(dl, TLI.getSetCCResultType(MVT::i64),
2542 And2, DAG.getConstant(UINT64_C(0), MVT::i64), ISD::SETNE);
2543 SDValue Sel = DAG.getNode(ISD::SELECT, dl, MVT::i64, Ne, Or, Op0);
2544 SDValue Ge = DAG.getSetCC(dl, TLI.getSetCCResultType(MVT::i64),
2545 Op0, DAG.getConstant(UINT64_C(0x0020000000000000), MVT::i64),
2547 SDValue Sel2 = DAG.getNode(ISD::SELECT, dl, MVT::i64, Ge, Sel, Op0);
2548 EVT SHVT = TLI.getShiftAmountTy(Sel2.getValueType());
2550 SDValue Sh = DAG.getNode(ISD::SRL, dl, MVT::i64, Sel2,
2551 DAG.getConstant(32, SHVT));
2552 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Sh);
2553 SDValue Fcvt = DAG.getNode(ISD::UINT_TO_FP, dl, MVT::f64, Trunc);
2555 DAG.getConstantFP(BitsToDouble(UINT64_C(0x41f0000000000000)), MVT::f64);
2556 SDValue Fmul = DAG.getNode(ISD::FMUL, dl, MVT::f64, TwoP32, Fcvt);
2557 SDValue Lo = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Sel2);
2558 SDValue Fcvt2 = DAG.getNode(ISD::UINT_TO_FP, dl, MVT::f64, Lo);
2559 SDValue Fadd = DAG.getNode(ISD::FADD, dl, MVT::f64, Fmul, Fcvt2);
2560 return DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, Fadd,
2561 DAG.getIntPtrConstant(0));
2564 SDValue Tmp1 = DAG.getNode(ISD::SINT_TO_FP, dl, DestVT, Op0);
2566 SDValue SignSet = DAG.getSetCC(dl, TLI.getSetCCResultType(Op0.getValueType()),
2567 Op0, DAG.getConstant(0, Op0.getValueType()),
2569 SDValue Zero = DAG.getIntPtrConstant(0), Four = DAG.getIntPtrConstant(4);
2570 SDValue CstOffset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(),
2571 SignSet, Four, Zero);
2573 // If the sign bit of the integer is set, the large number will be treated
2574 // as a negative number. To counteract this, the dynamic code adds an
2575 // offset depending on the data type.
2577 switch (Op0.getValueType().getSimpleVT().SimpleTy) {
2578 default: assert(0 && "Unsupported integer type!");
2579 case MVT::i8 : FF = 0x43800000ULL; break; // 2^8 (as a float)
2580 case MVT::i16: FF = 0x47800000ULL; break; // 2^16 (as a float)
2581 case MVT::i32: FF = 0x4F800000ULL; break; // 2^32 (as a float)
2582 case MVT::i64: FF = 0x5F800000ULL; break; // 2^64 (as a float)
2584 if (TLI.isLittleEndian()) FF <<= 32;
2585 Constant *FudgeFactor = ConstantInt::get(
2586 Type::getInt64Ty(*DAG.getContext()), FF);
2588 SDValue CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy());
2589 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
2590 CPIdx = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(), CPIdx, CstOffset);
2591 Alignment = std::min(Alignment, 4u);
2593 if (DestVT == MVT::f32)
2594 FudgeInReg = DAG.getLoad(MVT::f32, dl, DAG.getEntryNode(), CPIdx,
2595 MachinePointerInfo::getConstantPool(),
2596 false, false, Alignment);
2599 LegalizeOp(DAG.getExtLoad(ISD::EXTLOAD, dl, DestVT,
2600 DAG.getEntryNode(), CPIdx,
2601 MachinePointerInfo::getConstantPool(),
2602 MVT::f32, false, false, Alignment));
2605 return DAG.getNode(ISD::FADD, dl, DestVT, Tmp1, FudgeInReg);
2608 /// PromoteLegalINT_TO_FP - This function is responsible for legalizing a
2609 /// *INT_TO_FP operation of the specified operand when the target requests that
2610 /// we promote it. At this point, we know that the result and operand types are
2611 /// legal for the target, and that there is a legal UINT_TO_FP or SINT_TO_FP
2612 /// operation that takes a larger input.
2613 SDValue SelectionDAGLegalize::PromoteLegalINT_TO_FP(SDValue LegalOp,
2617 // First step, figure out the appropriate *INT_TO_FP operation to use.
2618 EVT NewInTy = LegalOp.getValueType();
2620 unsigned OpToUse = 0;
2622 // Scan for the appropriate larger type to use.
2624 NewInTy = (MVT::SimpleValueType)(NewInTy.getSimpleVT().SimpleTy+1);
2625 assert(NewInTy.isInteger() && "Ran out of possibilities!");
2627 // If the target supports SINT_TO_FP of this type, use it.
2628 if (TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, NewInTy)) {
2629 OpToUse = ISD::SINT_TO_FP;
2632 if (isSigned) continue;
2634 // If the target supports UINT_TO_FP of this type, use it.
2635 if (TLI.isOperationLegalOrCustom(ISD::UINT_TO_FP, NewInTy)) {
2636 OpToUse = ISD::UINT_TO_FP;
2640 // Otherwise, try a larger type.
2643 // Okay, we found the operation and type to use. Zero extend our input to the
2644 // desired type then run the operation on it.
2645 return DAG.getNode(OpToUse, dl, DestVT,
2646 DAG.getNode(isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND,
2647 dl, NewInTy, LegalOp));
2650 /// PromoteLegalFP_TO_INT - This function is responsible for legalizing a
2651 /// FP_TO_*INT operation of the specified operand when the target requests that
2652 /// we promote it. At this point, we know that the result and operand types are
2653 /// legal for the target, and that there is a legal FP_TO_UINT or FP_TO_SINT
2654 /// operation that returns a larger result.
2655 SDValue SelectionDAGLegalize::PromoteLegalFP_TO_INT(SDValue LegalOp,
2659 // First step, figure out the appropriate FP_TO*INT operation to use.
2660 EVT NewOutTy = DestVT;
2662 unsigned OpToUse = 0;
2664 // Scan for the appropriate larger type to use.
2666 NewOutTy = (MVT::SimpleValueType)(NewOutTy.getSimpleVT().SimpleTy+1);
2667 assert(NewOutTy.isInteger() && "Ran out of possibilities!");
2669 if (TLI.isOperationLegalOrCustom(ISD::FP_TO_SINT, NewOutTy)) {
2670 OpToUse = ISD::FP_TO_SINT;
2674 if (TLI.isOperationLegalOrCustom(ISD::FP_TO_UINT, NewOutTy)) {
2675 OpToUse = ISD::FP_TO_UINT;
2679 // Otherwise, try a larger type.
2683 // Okay, we found the operation and type to use.
2684 SDValue Operation = DAG.getNode(OpToUse, dl, NewOutTy, LegalOp);
2686 // Truncate the result of the extended FP_TO_*INT operation to the desired
2688 return DAG.getNode(ISD::TRUNCATE, dl, DestVT, Operation);
2691 /// ExpandBSWAP - Open code the operations for BSWAP of the specified operation.
2693 SDValue SelectionDAGLegalize::ExpandBSWAP(SDValue Op, DebugLoc dl) {
2694 EVT VT = Op.getValueType();
2695 EVT SHVT = TLI.getShiftAmountTy(VT);
2696 SDValue Tmp1, Tmp2, Tmp3, Tmp4, Tmp5, Tmp6, Tmp7, Tmp8;
2697 switch (VT.getSimpleVT().SimpleTy) {
2698 default: assert(0 && "Unhandled Expand type in BSWAP!");
2700 Tmp2 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, SHVT));
2701 Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, SHVT));
2702 return DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);
2704 Tmp4 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(24, SHVT));
2705 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, SHVT));
2706 Tmp2 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, SHVT));
2707 Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(24, SHVT));
2708 Tmp3 = DAG.getNode(ISD::AND, dl, VT, Tmp3, DAG.getConstant(0xFF0000, VT));
2709 Tmp2 = DAG.getNode(ISD::AND, dl, VT, Tmp2, DAG.getConstant(0xFF00, VT));
2710 Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp3);
2711 Tmp2 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp1);
2712 return DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp2);
2714 Tmp8 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(56, SHVT));
2715 Tmp7 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(40, SHVT));
2716 Tmp6 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(24, SHVT));
2717 Tmp5 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, SHVT));
2718 Tmp4 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, SHVT));
2719 Tmp3 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(24, SHVT));
2720 Tmp2 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(40, SHVT));
2721 Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(56, SHVT));
2722 Tmp7 = DAG.getNode(ISD::AND, dl, VT, Tmp7, DAG.getConstant(255ULL<<48, VT));
2723 Tmp6 = DAG.getNode(ISD::AND, dl, VT, Tmp6, DAG.getConstant(255ULL<<40, VT));
2724 Tmp5 = DAG.getNode(ISD::AND, dl, VT, Tmp5, DAG.getConstant(255ULL<<32, VT));
2725 Tmp4 = DAG.getNode(ISD::AND, dl, VT, Tmp4, DAG.getConstant(255ULL<<24, VT));
2726 Tmp3 = DAG.getNode(ISD::AND, dl, VT, Tmp3, DAG.getConstant(255ULL<<16, VT));
2727 Tmp2 = DAG.getNode(ISD::AND, dl, VT, Tmp2, DAG.getConstant(255ULL<<8 , VT));
2728 Tmp8 = DAG.getNode(ISD::OR, dl, VT, Tmp8, Tmp7);
2729 Tmp6 = DAG.getNode(ISD::OR, dl, VT, Tmp6, Tmp5);
2730 Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp3);
2731 Tmp2 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp1);
2732 Tmp8 = DAG.getNode(ISD::OR, dl, VT, Tmp8, Tmp6);
2733 Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp2);
2734 return DAG.getNode(ISD::OR, dl, VT, Tmp8, Tmp4);
2738 /// SplatByte - Distribute ByteVal over NumBits bits.
2739 // FIXME: Move this helper to a common place.
2740 static APInt SplatByte(unsigned NumBits, uint8_t ByteVal) {
2741 APInt Val = APInt(NumBits, ByteVal);
2743 for (unsigned i = NumBits; i > 8; i >>= 1) {
2744 Val = (Val << Shift) | Val;
2750 /// ExpandBitCount - Expand the specified bitcount instruction into operations.
2752 SDValue SelectionDAGLegalize::ExpandBitCount(unsigned Opc, SDValue Op,
2755 default: assert(0 && "Cannot expand this yet!");
2757 EVT VT = Op.getValueType();
2758 EVT ShVT = TLI.getShiftAmountTy(VT);
2759 unsigned Len = VT.getSizeInBits();
2761 assert(VT.isInteger() && Len <= 128 && Len % 8 == 0 &&
2762 "CTPOP not implemented for this type.");
2764 // This is the "best" algorithm from
2765 // http://graphics.stanford.edu/~seander/bithacks.html#CountBitsSetParallel
2767 SDValue Mask55 = DAG.getConstant(SplatByte(Len, 0x55), VT);
2768 SDValue Mask33 = DAG.getConstant(SplatByte(Len, 0x33), VT);
2769 SDValue Mask0F = DAG.getConstant(SplatByte(Len, 0x0F), VT);
2770 SDValue Mask01 = DAG.getConstant(SplatByte(Len, 0x01), VT);
2772 // v = v - ((v >> 1) & 0x55555555...)
2773 Op = DAG.getNode(ISD::SUB, dl, VT, Op,
2774 DAG.getNode(ISD::AND, dl, VT,
2775 DAG.getNode(ISD::SRL, dl, VT, Op,
2776 DAG.getConstant(1, ShVT)),
2778 // v = (v & 0x33333333...) + ((v >> 2) & 0x33333333...)
2779 Op = DAG.getNode(ISD::ADD, dl, VT,
2780 DAG.getNode(ISD::AND, dl, VT, Op, Mask33),
2781 DAG.getNode(ISD::AND, dl, VT,
2782 DAG.getNode(ISD::SRL, dl, VT, Op,
2783 DAG.getConstant(2, ShVT)),
2785 // v = (v + (v >> 4)) & 0x0F0F0F0F...
2786 Op = DAG.getNode(ISD::AND, dl, VT,
2787 DAG.getNode(ISD::ADD, dl, VT, Op,
2788 DAG.getNode(ISD::SRL, dl, VT, Op,
2789 DAG.getConstant(4, ShVT))),
2791 // v = (v * 0x01010101...) >> (Len - 8)
2792 Op = DAG.getNode(ISD::SRL, dl, VT,
2793 DAG.getNode(ISD::MUL, dl, VT, Op, Mask01),
2794 DAG.getConstant(Len - 8, ShVT));
2799 // for now, we do this:
2800 // x = x | (x >> 1);
2801 // x = x | (x >> 2);
2803 // x = x | (x >>16);
2804 // x = x | (x >>32); // for 64-bit input
2805 // return popcount(~x);
2807 // but see also: http://www.hackersdelight.org/HDcode/nlz.cc
2808 EVT VT = Op.getValueType();
2809 EVT ShVT = TLI.getShiftAmountTy(VT);
2810 unsigned len = VT.getSizeInBits();
2811 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) {
2812 SDValue Tmp3 = DAG.getConstant(1ULL << i, ShVT);
2813 Op = DAG.getNode(ISD::OR, dl, VT, Op,
2814 DAG.getNode(ISD::SRL, dl, VT, Op, Tmp3));
2816 Op = DAG.getNOT(dl, Op, VT);
2817 return DAG.getNode(ISD::CTPOP, dl, VT, Op);
2820 // for now, we use: { return popcount(~x & (x - 1)); }
2821 // unless the target has ctlz but not ctpop, in which case we use:
2822 // { return 32 - nlz(~x & (x-1)); }
2823 // see also http://www.hackersdelight.org/HDcode/ntz.cc
2824 EVT VT = Op.getValueType();
2825 SDValue Tmp3 = DAG.getNode(ISD::AND, dl, VT,
2826 DAG.getNOT(dl, Op, VT),
2827 DAG.getNode(ISD::SUB, dl, VT, Op,
2828 DAG.getConstant(1, VT)));
2829 // If ISD::CTLZ is legal and CTPOP isn't, then do that instead.
2830 if (!TLI.isOperationLegalOrCustom(ISD::CTPOP, VT) &&
2831 TLI.isOperationLegalOrCustom(ISD::CTLZ, VT))
2832 return DAG.getNode(ISD::SUB, dl, VT,
2833 DAG.getConstant(VT.getSizeInBits(), VT),
2834 DAG.getNode(ISD::CTLZ, dl, VT, Tmp3));
2835 return DAG.getNode(ISD::CTPOP, dl, VT, Tmp3);
2840 std::pair <SDValue, SDValue> SelectionDAGLegalize::ExpandAtomic(SDNode *Node) {
2841 unsigned Opc = Node->getOpcode();
2842 MVT VT = cast<AtomicSDNode>(Node)->getMemoryVT().getSimpleVT();
2847 llvm_unreachable("Unhandled atomic intrinsic Expand!");
2849 case ISD::ATOMIC_SWAP:
2850 switch (VT.SimpleTy) {
2851 default: llvm_unreachable("Unexpected value type for atomic!");
2852 case MVT::i8: LC = RTLIB::SYNC_LOCK_TEST_AND_SET_1; break;
2853 case MVT::i16: LC = RTLIB::SYNC_LOCK_TEST_AND_SET_2; break;
2854 case MVT::i32: LC = RTLIB::SYNC_LOCK_TEST_AND_SET_4; break;
2855 case MVT::i64: LC = RTLIB::SYNC_LOCK_TEST_AND_SET_8; break;
2858 case ISD::ATOMIC_CMP_SWAP:
2859 switch (VT.SimpleTy) {
2860 default: llvm_unreachable("Unexpected value type for atomic!");
2861 case MVT::i8: LC = RTLIB::SYNC_VAL_COMPARE_AND_SWAP_1; break;
2862 case MVT::i16: LC = RTLIB::SYNC_VAL_COMPARE_AND_SWAP_2; break;
2863 case MVT::i32: LC = RTLIB::SYNC_VAL_COMPARE_AND_SWAP_4; break;
2864 case MVT::i64: LC = RTLIB::SYNC_VAL_COMPARE_AND_SWAP_8; break;
2867 case ISD::ATOMIC_LOAD_ADD:
2868 switch (VT.SimpleTy) {
2869 default: llvm_unreachable("Unexpected value type for atomic!");
2870 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_ADD_1; break;
2871 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_ADD_2; break;
2872 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_ADD_4; break;
2873 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_ADD_8; break;
2876 case ISD::ATOMIC_LOAD_SUB:
2877 switch (VT.SimpleTy) {
2878 default: llvm_unreachable("Unexpected value type for atomic!");
2879 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_SUB_1; break;
2880 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_SUB_2; break;
2881 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_SUB_4; break;
2882 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_SUB_8; break;
2885 case ISD::ATOMIC_LOAD_AND:
2886 switch (VT.SimpleTy) {
2887 default: llvm_unreachable("Unexpected value type for atomic!");
2888 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_AND_1; break;
2889 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_AND_2; break;
2890 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_AND_4; break;
2891 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_AND_8; break;
2894 case ISD::ATOMIC_LOAD_OR:
2895 switch (VT.SimpleTy) {
2896 default: llvm_unreachable("Unexpected value type for atomic!");
2897 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_OR_1; break;
2898 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_OR_2; break;
2899 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_OR_4; break;
2900 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_OR_8; break;
2903 case ISD::ATOMIC_LOAD_XOR:
2904 switch (VT.SimpleTy) {
2905 default: llvm_unreachable("Unexpected value type for atomic!");
2906 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_XOR_1; break;
2907 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_XOR_2; break;
2908 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_XOR_4; break;
2909 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_XOR_8; break;
2912 case ISD::ATOMIC_LOAD_NAND:
2913 switch (VT.SimpleTy) {
2914 default: llvm_unreachable("Unexpected value type for atomic!");
2915 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_NAND_1; break;
2916 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_NAND_2; break;
2917 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_NAND_4; break;
2918 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_NAND_8; break;
2923 return ExpandChainLibCall(LC, Node, false);
2926 void SelectionDAGLegalize::ExpandNode(SDNode *Node,
2927 SmallVectorImpl<SDValue> &Results) {
2928 DebugLoc dl = Node->getDebugLoc();
2929 SDValue Tmp1, Tmp2, Tmp3, Tmp4;
2930 switch (Node->getOpcode()) {
2934 Tmp1 = ExpandBitCount(Node->getOpcode(), Node->getOperand(0), dl);
2935 Results.push_back(Tmp1);
2938 Results.push_back(ExpandBSWAP(Node->getOperand(0), dl));
2940 case ISD::FRAMEADDR:
2941 case ISD::RETURNADDR:
2942 case ISD::FRAME_TO_ARGS_OFFSET:
2943 Results.push_back(DAG.getConstant(0, Node->getValueType(0)));
2945 case ISD::FLT_ROUNDS_:
2946 Results.push_back(DAG.getConstant(1, Node->getValueType(0)));
2948 case ISD::EH_RETURN:
2952 case ISD::EH_SJLJ_LONGJMP:
2953 case ISD::EH_SJLJ_DISPATCHSETUP:
2954 // If the target didn't expand these, there's nothing to do, so just
2955 // preserve the chain and be done.
2956 Results.push_back(Node->getOperand(0));
2958 case ISD::EH_SJLJ_SETJMP:
2959 // If the target didn't expand this, just return 'zero' and preserve the
2961 Results.push_back(DAG.getConstant(0, MVT::i32));
2962 Results.push_back(Node->getOperand(0));
2964 case ISD::MEMBARRIER: {
2965 // If the target didn't lower this, lower it to '__sync_synchronize()' call
2966 TargetLowering::ArgListTy Args;
2967 std::pair<SDValue, SDValue> CallResult =
2968 TLI.LowerCallTo(Node->getOperand(0), Type::getVoidTy(*DAG.getContext()),
2969 false, false, false, false, 0, CallingConv::C,
2970 /*isTailCall=*/false,
2971 /*isReturnValueUsed=*/true,
2972 DAG.getExternalSymbol("__sync_synchronize",
2973 TLI.getPointerTy()),
2975 Results.push_back(CallResult.second);
2978 // By default, atomic intrinsics are marked Legal and lowered. Targets
2979 // which don't support them directly, however, may want libcalls, in which
2980 // case they mark them Expand, and we get here.
2981 case ISD::ATOMIC_SWAP:
2982 case ISD::ATOMIC_LOAD_ADD:
2983 case ISD::ATOMIC_LOAD_SUB:
2984 case ISD::ATOMIC_LOAD_AND:
2985 case ISD::ATOMIC_LOAD_OR:
2986 case ISD::ATOMIC_LOAD_XOR:
2987 case ISD::ATOMIC_LOAD_NAND:
2988 case ISD::ATOMIC_LOAD_MIN:
2989 case ISD::ATOMIC_LOAD_MAX:
2990 case ISD::ATOMIC_LOAD_UMIN:
2991 case ISD::ATOMIC_LOAD_UMAX:
2992 case ISD::ATOMIC_CMP_SWAP: {
2993 std::pair<SDValue, SDValue> Tmp = ExpandAtomic(Node);
2994 Results.push_back(Tmp.first);
2995 Results.push_back(Tmp.second);
2998 case ISD::DYNAMIC_STACKALLOC:
2999 ExpandDYNAMIC_STACKALLOC(Node, Results);
3001 case ISD::MERGE_VALUES:
3002 for (unsigned i = 0; i < Node->getNumValues(); i++)
3003 Results.push_back(Node->getOperand(i));
3006 EVT VT = Node->getValueType(0);
3008 Results.push_back(DAG.getConstant(0, VT));
3010 assert(VT.isFloatingPoint() && "Unknown value type!");
3011 Results.push_back(DAG.getConstantFP(0, VT));
3016 // If this operation is not supported, lower it to 'abort()' call
3017 TargetLowering::ArgListTy Args;
3018 std::pair<SDValue, SDValue> CallResult =
3019 TLI.LowerCallTo(Node->getOperand(0), Type::getVoidTy(*DAG.getContext()),
3020 false, false, false, false, 0, CallingConv::C,
3021 /*isTailCall=*/false,
3022 /*isReturnValueUsed=*/true,
3023 DAG.getExternalSymbol("abort", TLI.getPointerTy()),
3025 Results.push_back(CallResult.second);
3030 Tmp1 = EmitStackConvert(Node->getOperand(0), Node->getValueType(0),
3031 Node->getValueType(0), dl);
3032 Results.push_back(Tmp1);
3034 case ISD::FP_EXTEND:
3035 Tmp1 = EmitStackConvert(Node->getOperand(0),
3036 Node->getOperand(0).getValueType(),
3037 Node->getValueType(0), dl);
3038 Results.push_back(Tmp1);
3040 case ISD::SIGN_EXTEND_INREG: {
3041 // NOTE: we could fall back on load/store here too for targets without
3042 // SAR. However, it is doubtful that any exist.
3043 EVT ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT();
3044 EVT VT = Node->getValueType(0);
3045 EVT ShiftAmountTy = TLI.getShiftAmountTy(VT);
3048 unsigned BitsDiff = VT.getScalarType().getSizeInBits() -
3049 ExtraVT.getScalarType().getSizeInBits();
3050 SDValue ShiftCst = DAG.getConstant(BitsDiff, ShiftAmountTy);
3051 Tmp1 = DAG.getNode(ISD::SHL, dl, Node->getValueType(0),
3052 Node->getOperand(0), ShiftCst);
3053 Tmp1 = DAG.getNode(ISD::SRA, dl, Node->getValueType(0), Tmp1, ShiftCst);
3054 Results.push_back(Tmp1);
3057 case ISD::FP_ROUND_INREG: {
3058 // The only way we can lower this is to turn it into a TRUNCSTORE,
3059 // EXTLOAD pair, targeting a temporary location (a stack slot).
3061 // NOTE: there is a choice here between constantly creating new stack
3062 // slots and always reusing the same one. We currently always create
3063 // new ones, as reuse may inhibit scheduling.
3064 EVT ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT();
3065 Tmp1 = EmitStackConvert(Node->getOperand(0), ExtraVT,
3066 Node->getValueType(0), dl);
3067 Results.push_back(Tmp1);
3070 case ISD::SINT_TO_FP:
3071 case ISD::UINT_TO_FP:
3072 Tmp1 = ExpandLegalINT_TO_FP(Node->getOpcode() == ISD::SINT_TO_FP,
3073 Node->getOperand(0), Node->getValueType(0), dl);
3074 Results.push_back(Tmp1);
3076 case ISD::FP_TO_UINT: {
3077 SDValue True, False;
3078 EVT VT = Node->getOperand(0).getValueType();
3079 EVT NVT = Node->getValueType(0);
3080 APFloat apf(APInt::getNullValue(VT.getSizeInBits()));
3081 APInt x = APInt::getSignBit(NVT.getSizeInBits());
3082 (void)apf.convertFromAPInt(x, false, APFloat::rmNearestTiesToEven);
3083 Tmp1 = DAG.getConstantFP(apf, VT);
3084 Tmp2 = DAG.getSetCC(dl, TLI.getSetCCResultType(VT),
3085 Node->getOperand(0),
3087 True = DAG.getNode(ISD::FP_TO_SINT, dl, NVT, Node->getOperand(0));
3088 False = DAG.getNode(ISD::FP_TO_SINT, dl, NVT,
3089 DAG.getNode(ISD::FSUB, dl, VT,
3090 Node->getOperand(0), Tmp1));
3091 False = DAG.getNode(ISD::XOR, dl, NVT, False,
3092 DAG.getConstant(x, NVT));
3093 Tmp1 = DAG.getNode(ISD::SELECT, dl, NVT, Tmp2, True, False);
3094 Results.push_back(Tmp1);
3098 const Value *V = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
3099 EVT VT = Node->getValueType(0);
3100 Tmp1 = Node->getOperand(0);
3101 Tmp2 = Node->getOperand(1);
3102 unsigned Align = Node->getConstantOperandVal(3);
3104 SDValue VAListLoad = DAG.getLoad(TLI.getPointerTy(), dl, Tmp1, Tmp2,
3105 MachinePointerInfo(V), false, false, 0);
3106 SDValue VAList = VAListLoad;
3108 if (Align > TLI.getMinStackArgumentAlignment()) {
3109 assert(((Align & (Align-1)) == 0) && "Expected Align to be a power of 2");
3111 VAList = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(), VAList,
3112 DAG.getConstant(Align - 1,
3113 TLI.getPointerTy()));
3115 VAList = DAG.getNode(ISD::AND, dl, TLI.getPointerTy(), VAList,
3116 DAG.getConstant(-(int64_t)Align,
3117 TLI.getPointerTy()));
3120 // Increment the pointer, VAList, to the next vaarg
3121 Tmp3 = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(), VAList,
3122 DAG.getConstant(TLI.getTargetData()->
3123 getTypeAllocSize(VT.getTypeForEVT(*DAG.getContext())),
3124 TLI.getPointerTy()));
3125 // Store the incremented VAList to the legalized pointer
3126 Tmp3 = DAG.getStore(VAListLoad.getValue(1), dl, Tmp3, Tmp2,
3127 MachinePointerInfo(V), false, false, 0);
3128 // Load the actual argument out of the pointer VAList
3129 Results.push_back(DAG.getLoad(VT, dl, Tmp3, VAList, MachinePointerInfo(),
3131 Results.push_back(Results[0].getValue(1));
3135 // This defaults to loading a pointer from the input and storing it to the
3136 // output, returning the chain.
3137 const Value *VD = cast<SrcValueSDNode>(Node->getOperand(3))->getValue();
3138 const Value *VS = cast<SrcValueSDNode>(Node->getOperand(4))->getValue();
3139 Tmp1 = DAG.getLoad(TLI.getPointerTy(), dl, Node->getOperand(0),
3140 Node->getOperand(2), MachinePointerInfo(VS),
3142 Tmp1 = DAG.getStore(Tmp1.getValue(1), dl, Tmp1, Node->getOperand(1),
3143 MachinePointerInfo(VD), false, false, 0);
3144 Results.push_back(Tmp1);
3147 case ISD::EXTRACT_VECTOR_ELT:
3148 if (Node->getOperand(0).getValueType().getVectorNumElements() == 1)
3149 // This must be an access of the only element. Return it.
3150 Tmp1 = DAG.getNode(ISD::BITCAST, dl, Node->getValueType(0),
3151 Node->getOperand(0));
3153 Tmp1 = ExpandExtractFromVectorThroughStack(SDValue(Node, 0));
3154 Results.push_back(Tmp1);
3156 case ISD::EXTRACT_SUBVECTOR:
3157 Results.push_back(ExpandExtractFromVectorThroughStack(SDValue(Node, 0)));
3159 case ISD::INSERT_SUBVECTOR:
3160 Results.push_back(ExpandInsertToVectorThroughStack(SDValue(Node, 0)));
3162 case ISD::CONCAT_VECTORS: {
3163 Results.push_back(ExpandVectorBuildThroughStack(Node));
3166 case ISD::SCALAR_TO_VECTOR:
3167 Results.push_back(ExpandSCALAR_TO_VECTOR(Node));
3169 case ISD::INSERT_VECTOR_ELT:
3170 Results.push_back(ExpandINSERT_VECTOR_ELT(Node->getOperand(0),
3171 Node->getOperand(1),
3172 Node->getOperand(2), dl));
3174 case ISD::VECTOR_SHUFFLE: {
3175 SmallVector<int, 8> Mask;
3176 cast<ShuffleVectorSDNode>(Node)->getMask(Mask);
3178 EVT VT = Node->getValueType(0);
3179 EVT EltVT = VT.getVectorElementType();
3180 if (!TLI.isTypeLegal(EltVT))
3181 EltVT = TLI.getTypeToTransformTo(*DAG.getContext(), EltVT);
3182 unsigned NumElems = VT.getVectorNumElements();
3183 SmallVector<SDValue, 8> Ops;
3184 for (unsigned i = 0; i != NumElems; ++i) {
3186 Ops.push_back(DAG.getUNDEF(EltVT));
3189 unsigned Idx = Mask[i];
3191 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT,
3192 Node->getOperand(0),
3193 DAG.getIntPtrConstant(Idx)));
3195 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT,
3196 Node->getOperand(1),
3197 DAG.getIntPtrConstant(Idx - NumElems)));
3199 Tmp1 = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &Ops[0], Ops.size());
3200 Results.push_back(Tmp1);
3203 case ISD::EXTRACT_ELEMENT: {
3204 EVT OpTy = Node->getOperand(0).getValueType();
3205 if (cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue()) {
3207 Tmp1 = DAG.getNode(ISD::SRL, dl, OpTy, Node->getOperand(0),
3208 DAG.getConstant(OpTy.getSizeInBits()/2,
3209 TLI.getShiftAmountTy(Node->getOperand(0).getValueType())));
3210 Tmp1 = DAG.getNode(ISD::TRUNCATE, dl, Node->getValueType(0), Tmp1);
3213 Tmp1 = DAG.getNode(ISD::TRUNCATE, dl, Node->getValueType(0),
3214 Node->getOperand(0));
3216 Results.push_back(Tmp1);
3219 case ISD::STACKSAVE:
3220 // Expand to CopyFromReg if the target set
3221 // StackPointerRegisterToSaveRestore.
3222 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) {
3223 Results.push_back(DAG.getCopyFromReg(Node->getOperand(0), dl, SP,
3224 Node->getValueType(0)));
3225 Results.push_back(Results[0].getValue(1));
3227 Results.push_back(DAG.getUNDEF(Node->getValueType(0)));
3228 Results.push_back(Node->getOperand(0));
3231 case ISD::STACKRESTORE:
3232 // Expand to CopyToReg if the target set
3233 // StackPointerRegisterToSaveRestore.
3234 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) {
3235 Results.push_back(DAG.getCopyToReg(Node->getOperand(0), dl, SP,
3236 Node->getOperand(1)));
3238 Results.push_back(Node->getOperand(0));
3241 case ISD::FCOPYSIGN:
3242 Results.push_back(ExpandFCOPYSIGN(Node));
3245 // Expand Y = FNEG(X) -> Y = SUB -0.0, X
3246 Tmp1 = DAG.getConstantFP(-0.0, Node->getValueType(0));
3247 Tmp1 = DAG.getNode(ISD::FSUB, dl, Node->getValueType(0), Tmp1,
3248 Node->getOperand(0));
3249 Results.push_back(Tmp1);
3252 // Expand Y = FABS(X) -> Y = (X >u 0.0) ? X : fneg(X).
3253 EVT VT = Node->getValueType(0);
3254 Tmp1 = Node->getOperand(0);
3255 Tmp2 = DAG.getConstantFP(0.0, VT);
3256 Tmp2 = DAG.getSetCC(dl, TLI.getSetCCResultType(Tmp1.getValueType()),
3257 Tmp1, Tmp2, ISD::SETUGT);
3258 Tmp3 = DAG.getNode(ISD::FNEG, dl, VT, Tmp1);
3259 Tmp1 = DAG.getNode(ISD::SELECT, dl, VT, Tmp2, Tmp1, Tmp3);
3260 Results.push_back(Tmp1);
3264 Results.push_back(ExpandFPLibCall(Node, RTLIB::SQRT_F32, RTLIB::SQRT_F64,
3265 RTLIB::SQRT_F80, RTLIB::SQRT_PPCF128));
3268 Results.push_back(ExpandFPLibCall(Node, RTLIB::SIN_F32, RTLIB::SIN_F64,
3269 RTLIB::SIN_F80, RTLIB::SIN_PPCF128));
3272 Results.push_back(ExpandFPLibCall(Node, RTLIB::COS_F32, RTLIB::COS_F64,
3273 RTLIB::COS_F80, RTLIB::COS_PPCF128));
3276 Results.push_back(ExpandFPLibCall(Node, RTLIB::LOG_F32, RTLIB::LOG_F64,
3277 RTLIB::LOG_F80, RTLIB::LOG_PPCF128));
3280 Results.push_back(ExpandFPLibCall(Node, RTLIB::LOG2_F32, RTLIB::LOG2_F64,
3281 RTLIB::LOG2_F80, RTLIB::LOG2_PPCF128));
3284 Results.push_back(ExpandFPLibCall(Node, RTLIB::LOG10_F32, RTLIB::LOG10_F64,
3285 RTLIB::LOG10_F80, RTLIB::LOG10_PPCF128));
3288 Results.push_back(ExpandFPLibCall(Node, RTLIB::EXP_F32, RTLIB::EXP_F64,
3289 RTLIB::EXP_F80, RTLIB::EXP_PPCF128));
3292 Results.push_back(ExpandFPLibCall(Node, RTLIB::EXP2_F32, RTLIB::EXP2_F64,
3293 RTLIB::EXP2_F80, RTLIB::EXP2_PPCF128));
3296 Results.push_back(ExpandFPLibCall(Node, RTLIB::TRUNC_F32, RTLIB::TRUNC_F64,
3297 RTLIB::TRUNC_F80, RTLIB::TRUNC_PPCF128));
3300 Results.push_back(ExpandFPLibCall(Node, RTLIB::FLOOR_F32, RTLIB::FLOOR_F64,
3301 RTLIB::FLOOR_F80, RTLIB::FLOOR_PPCF128));
3304 Results.push_back(ExpandFPLibCall(Node, RTLIB::CEIL_F32, RTLIB::CEIL_F64,
3305 RTLIB::CEIL_F80, RTLIB::CEIL_PPCF128));
3308 Results.push_back(ExpandFPLibCall(Node, RTLIB::RINT_F32, RTLIB::RINT_F64,
3309 RTLIB::RINT_F80, RTLIB::RINT_PPCF128));
3311 case ISD::FNEARBYINT:
3312 Results.push_back(ExpandFPLibCall(Node, RTLIB::NEARBYINT_F32,
3313 RTLIB::NEARBYINT_F64,
3314 RTLIB::NEARBYINT_F80,
3315 RTLIB::NEARBYINT_PPCF128));
3318 Results.push_back(ExpandFPLibCall(Node, RTLIB::POWI_F32, RTLIB::POWI_F64,
3319 RTLIB::POWI_F80, RTLIB::POWI_PPCF128));
3322 Results.push_back(ExpandFPLibCall(Node, RTLIB::POW_F32, RTLIB::POW_F64,
3323 RTLIB::POW_F80, RTLIB::POW_PPCF128));
3326 Results.push_back(ExpandFPLibCall(Node, RTLIB::DIV_F32, RTLIB::DIV_F64,
3327 RTLIB::DIV_F80, RTLIB::DIV_PPCF128));
3330 Results.push_back(ExpandFPLibCall(Node, RTLIB::REM_F32, RTLIB::REM_F64,
3331 RTLIB::REM_F80, RTLIB::REM_PPCF128));
3334 Results.push_back(ExpandFPLibCall(Node, RTLIB::FMA_F32, RTLIB::FMA_F64,
3335 RTLIB::FMA_F80, RTLIB::FMA_PPCF128));
3337 case ISD::FP16_TO_FP32:
3338 Results.push_back(ExpandLibCall(RTLIB::FPEXT_F16_F32, Node, false));
3340 case ISD::FP32_TO_FP16:
3341 Results.push_back(ExpandLibCall(RTLIB::FPROUND_F32_F16, Node, false));
3343 case ISD::ConstantFP: {
3344 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node);
3345 // Check to see if this FP immediate is already legal.
3346 // If this is a legal constant, turn it into a TargetConstantFP node.
3347 if (TLI.isFPImmLegal(CFP->getValueAPF(), Node->getValueType(0)))
3348 Results.push_back(SDValue(Node, 0));
3350 Results.push_back(ExpandConstantFP(CFP, true, DAG, TLI));
3353 case ISD::EHSELECTION: {
3354 unsigned Reg = TLI.getExceptionSelectorRegister();
3355 assert(Reg && "Can't expand to unknown register!");
3356 Results.push_back(DAG.getCopyFromReg(Node->getOperand(1), dl, Reg,
3357 Node->getValueType(0)));
3358 Results.push_back(Results[0].getValue(1));
3361 case ISD::EXCEPTIONADDR: {
3362 unsigned Reg = TLI.getExceptionAddressRegister();
3363 assert(Reg && "Can't expand to unknown register!");
3364 Results.push_back(DAG.getCopyFromReg(Node->getOperand(0), dl, Reg,
3365 Node->getValueType(0)));
3366 Results.push_back(Results[0].getValue(1));
3370 EVT VT = Node->getValueType(0);
3371 assert(TLI.isOperationLegalOrCustom(ISD::ADD, VT) &&
3372 TLI.isOperationLegalOrCustom(ISD::XOR, VT) &&
3373 "Don't know how to expand this subtraction!");
3374 Tmp1 = DAG.getNode(ISD::XOR, dl, VT, Node->getOperand(1),
3375 DAG.getConstant(APInt::getAllOnesValue(VT.getSizeInBits()), VT));
3376 Tmp1 = DAG.getNode(ISD::ADD, dl, VT, Tmp2, DAG.getConstant(1, VT));
3377 Results.push_back(DAG.getNode(ISD::ADD, dl, VT, Node->getOperand(0), Tmp1));
3382 EVT VT = Node->getValueType(0);
3383 SDVTList VTs = DAG.getVTList(VT, VT);
3384 bool isSigned = Node->getOpcode() == ISD::SREM;
3385 unsigned DivOpc = isSigned ? ISD::SDIV : ISD::UDIV;
3386 unsigned DivRemOpc = isSigned ? ISD::SDIVREM : ISD::UDIVREM;
3387 Tmp2 = Node->getOperand(0);
3388 Tmp3 = Node->getOperand(1);
3389 if (TLI.isOperationLegalOrCustom(DivRemOpc, VT) ||
3390 (isDivRemLibcallAvailable(Node, isSigned, TLI) &&
3391 UseDivRem(Node, isSigned, false))) {
3392 Tmp1 = DAG.getNode(DivRemOpc, dl, VTs, Tmp2, Tmp3).getValue(1);
3393 } else if (TLI.isOperationLegalOrCustom(DivOpc, VT)) {
3395 Tmp1 = DAG.getNode(DivOpc, dl, VT, Tmp2, Tmp3);
3396 Tmp1 = DAG.getNode(ISD::MUL, dl, VT, Tmp1, Tmp3);
3397 Tmp1 = DAG.getNode(ISD::SUB, dl, VT, Tmp2, Tmp1);
3398 } else if (isSigned)
3399 Tmp1 = ExpandIntLibCall(Node, true,
3401 RTLIB::SREM_I16, RTLIB::SREM_I32,
3402 RTLIB::SREM_I64, RTLIB::SREM_I128);
3404 Tmp1 = ExpandIntLibCall(Node, false,
3406 RTLIB::UREM_I16, RTLIB::UREM_I32,
3407 RTLIB::UREM_I64, RTLIB::UREM_I128);
3408 Results.push_back(Tmp1);
3413 bool isSigned = Node->getOpcode() == ISD::SDIV;
3414 unsigned DivRemOpc = isSigned ? ISD::SDIVREM : ISD::UDIVREM;
3415 EVT VT = Node->getValueType(0);
3416 SDVTList VTs = DAG.getVTList(VT, VT);
3417 if (TLI.isOperationLegalOrCustom(DivRemOpc, VT) ||
3418 (isDivRemLibcallAvailable(Node, isSigned, TLI) &&
3419 UseDivRem(Node, isSigned, true)))
3420 Tmp1 = DAG.getNode(DivRemOpc, dl, VTs, Node->getOperand(0),
3421 Node->getOperand(1));
3423 Tmp1 = ExpandIntLibCall(Node, true,
3425 RTLIB::SDIV_I16, RTLIB::SDIV_I32,
3426 RTLIB::SDIV_I64, RTLIB::SDIV_I128);
3428 Tmp1 = ExpandIntLibCall(Node, false,
3430 RTLIB::UDIV_I16, RTLIB::UDIV_I32,
3431 RTLIB::UDIV_I64, RTLIB::UDIV_I128);
3432 Results.push_back(Tmp1);
3437 unsigned ExpandOpcode = Node->getOpcode() == ISD::MULHU ? ISD::UMUL_LOHI :
3439 EVT VT = Node->getValueType(0);
3440 SDVTList VTs = DAG.getVTList(VT, VT);
3441 assert(TLI.isOperationLegalOrCustom(ExpandOpcode, VT) &&
3442 "If this wasn't legal, it shouldn't have been created!");
3443 Tmp1 = DAG.getNode(ExpandOpcode, dl, VTs, Node->getOperand(0),
3444 Node->getOperand(1));
3445 Results.push_back(Tmp1.getValue(1));
3450 // Expand into divrem libcall
3451 ExpandDivRemLibCall(Node, Results);
3454 EVT VT = Node->getValueType(0);
3455 SDVTList VTs = DAG.getVTList(VT, VT);
3456 // See if multiply or divide can be lowered using two-result operations.
3457 // We just need the low half of the multiply; try both the signed
3458 // and unsigned forms. If the target supports both SMUL_LOHI and
3459 // UMUL_LOHI, form a preference by checking which forms of plain
3460 // MULH it supports.
3461 bool HasSMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::SMUL_LOHI, VT);
3462 bool HasUMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::UMUL_LOHI, VT);
3463 bool HasMULHS = TLI.isOperationLegalOrCustom(ISD::MULHS, VT);
3464 bool HasMULHU = TLI.isOperationLegalOrCustom(ISD::MULHU, VT);
3465 unsigned OpToUse = 0;
3466 if (HasSMUL_LOHI && !HasMULHS) {
3467 OpToUse = ISD::SMUL_LOHI;
3468 } else if (HasUMUL_LOHI && !HasMULHU) {
3469 OpToUse = ISD::UMUL_LOHI;
3470 } else if (HasSMUL_LOHI) {
3471 OpToUse = ISD::SMUL_LOHI;
3472 } else if (HasUMUL_LOHI) {
3473 OpToUse = ISD::UMUL_LOHI;
3476 Results.push_back(DAG.getNode(OpToUse, dl, VTs, Node->getOperand(0),
3477 Node->getOperand(1)));
3480 Tmp1 = ExpandIntLibCall(Node, false,
3482 RTLIB::MUL_I16, RTLIB::MUL_I32,
3483 RTLIB::MUL_I64, RTLIB::MUL_I128);
3484 Results.push_back(Tmp1);
3489 SDValue LHS = Node->getOperand(0);
3490 SDValue RHS = Node->getOperand(1);
3491 SDValue Sum = DAG.getNode(Node->getOpcode() == ISD::SADDO ?
3492 ISD::ADD : ISD::SUB, dl, LHS.getValueType(),
3494 Results.push_back(Sum);
3495 EVT OType = Node->getValueType(1);
3497 SDValue Zero = DAG.getConstant(0, LHS.getValueType());
3499 // LHSSign -> LHS >= 0
3500 // RHSSign -> RHS >= 0
3501 // SumSign -> Sum >= 0
3504 // Overflow -> (LHSSign == RHSSign) && (LHSSign != SumSign)
3506 // Overflow -> (LHSSign != RHSSign) && (LHSSign != SumSign)
3508 SDValue LHSSign = DAG.getSetCC(dl, OType, LHS, Zero, ISD::SETGE);
3509 SDValue RHSSign = DAG.getSetCC(dl, OType, RHS, Zero, ISD::SETGE);
3510 SDValue SignsMatch = DAG.getSetCC(dl, OType, LHSSign, RHSSign,
3511 Node->getOpcode() == ISD::SADDO ?
3512 ISD::SETEQ : ISD::SETNE);
3514 SDValue SumSign = DAG.getSetCC(dl, OType, Sum, Zero, ISD::SETGE);
3515 SDValue SumSignNE = DAG.getSetCC(dl, OType, LHSSign, SumSign, ISD::SETNE);
3517 SDValue Cmp = DAG.getNode(ISD::AND, dl, OType, SignsMatch, SumSignNE);
3518 Results.push_back(Cmp);
3523 SDValue LHS = Node->getOperand(0);
3524 SDValue RHS = Node->getOperand(1);
3525 SDValue Sum = DAG.getNode(Node->getOpcode() == ISD::UADDO ?
3526 ISD::ADD : ISD::SUB, dl, LHS.getValueType(),
3528 Results.push_back(Sum);
3529 Results.push_back(DAG.getSetCC(dl, Node->getValueType(1), Sum, LHS,
3530 Node->getOpcode () == ISD::UADDO ?
3531 ISD::SETULT : ISD::SETUGT));
3536 EVT VT = Node->getValueType(0);
3537 EVT WideVT = EVT::getIntegerVT(*DAG.getContext(), VT.getSizeInBits() * 2);
3538 SDValue LHS = Node->getOperand(0);
3539 SDValue RHS = Node->getOperand(1);
3542 static const unsigned Ops[2][3] =
3543 { { ISD::MULHU, ISD::UMUL_LOHI, ISD::ZERO_EXTEND },
3544 { ISD::MULHS, ISD::SMUL_LOHI, ISD::SIGN_EXTEND }};
3545 bool isSigned = Node->getOpcode() == ISD::SMULO;
3546 if (TLI.isOperationLegalOrCustom(Ops[isSigned][0], VT)) {
3547 BottomHalf = DAG.getNode(ISD::MUL, dl, VT, LHS, RHS);
3548 TopHalf = DAG.getNode(Ops[isSigned][0], dl, VT, LHS, RHS);
3549 } else if (TLI.isOperationLegalOrCustom(Ops[isSigned][1], VT)) {
3550 BottomHalf = DAG.getNode(Ops[isSigned][1], dl, DAG.getVTList(VT, VT), LHS,
3552 TopHalf = BottomHalf.getValue(1);
3553 } else if (TLI.isTypeLegal(EVT::getIntegerVT(*DAG.getContext(),
3554 VT.getSizeInBits() * 2))) {
3555 LHS = DAG.getNode(Ops[isSigned][2], dl, WideVT, LHS);
3556 RHS = DAG.getNode(Ops[isSigned][2], dl, WideVT, RHS);
3557 Tmp1 = DAG.getNode(ISD::MUL, dl, WideVT, LHS, RHS);
3558 BottomHalf = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VT, Tmp1,
3559 DAG.getIntPtrConstant(0));
3560 TopHalf = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VT, Tmp1,
3561 DAG.getIntPtrConstant(1));
3563 // We can fall back to a libcall with an illegal type for the MUL if we
3564 // have a libcall big enough.
3565 // Also, we can fall back to a division in some cases, but that's a big
3566 // performance hit in the general case.
3567 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
3568 if (WideVT == MVT::i16)
3569 LC = RTLIB::MUL_I16;
3570 else if (WideVT == MVT::i32)
3571 LC = RTLIB::MUL_I32;
3572 else if (WideVT == MVT::i64)
3573 LC = RTLIB::MUL_I64;
3574 else if (WideVT == MVT::i128)
3575 LC = RTLIB::MUL_I128;
3576 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Cannot expand this operation!");
3578 // The high part is obtained by SRA'ing all but one of the bits of low
3580 unsigned LoSize = VT.getSizeInBits();
3581 SDValue HiLHS = DAG.getNode(ISD::SRA, dl, VT, RHS,
3582 DAG.getConstant(LoSize-1, TLI.getPointerTy()));
3583 SDValue HiRHS = DAG.getNode(ISD::SRA, dl, VT, LHS,
3584 DAG.getConstant(LoSize-1, TLI.getPointerTy()));
3586 // Here we're passing the 2 arguments explicitly as 4 arguments that are
3587 // pre-lowered to the correct types. This all depends upon WideVT not
3588 // being a legal type for the architecture and thus has to be split to
3590 SDValue Args[] = { LHS, HiLHS, RHS, HiRHS };
3591 SDValue Ret = ExpandLibCall(LC, WideVT, Args, 4, isSigned, dl);
3592 BottomHalf = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VT, Ret,
3593 DAG.getIntPtrConstant(0));
3594 TopHalf = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VT, Ret,
3595 DAG.getIntPtrConstant(1));
3599 Tmp1 = DAG.getConstant(VT.getSizeInBits() - 1,
3600 TLI.getShiftAmountTy(BottomHalf.getValueType()));
3601 Tmp1 = DAG.getNode(ISD::SRA, dl, VT, BottomHalf, Tmp1);
3602 TopHalf = DAG.getSetCC(dl, TLI.getSetCCResultType(VT), TopHalf, Tmp1,
3605 TopHalf = DAG.getSetCC(dl, TLI.getSetCCResultType(VT), TopHalf,
3606 DAG.getConstant(0, VT), ISD::SETNE);
3608 Results.push_back(BottomHalf);
3609 Results.push_back(TopHalf);
3612 case ISD::BUILD_PAIR: {
3613 EVT PairTy = Node->getValueType(0);
3614 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, PairTy, Node->getOperand(0));
3615 Tmp2 = DAG.getNode(ISD::ANY_EXTEND, dl, PairTy, Node->getOperand(1));
3616 Tmp2 = DAG.getNode(ISD::SHL, dl, PairTy, Tmp2,
3617 DAG.getConstant(PairTy.getSizeInBits()/2,
3618 TLI.getShiftAmountTy(PairTy)));
3619 Results.push_back(DAG.getNode(ISD::OR, dl, PairTy, Tmp1, Tmp2));
3623 Tmp1 = Node->getOperand(0);
3624 Tmp2 = Node->getOperand(1);
3625 Tmp3 = Node->getOperand(2);
3626 if (Tmp1.getOpcode() == ISD::SETCC) {
3627 Tmp1 = DAG.getSelectCC(dl, Tmp1.getOperand(0), Tmp1.getOperand(1),
3629 cast<CondCodeSDNode>(Tmp1.getOperand(2))->get());
3631 Tmp1 = DAG.getSelectCC(dl, Tmp1,
3632 DAG.getConstant(0, Tmp1.getValueType()),
3633 Tmp2, Tmp3, ISD::SETNE);
3635 Results.push_back(Tmp1);
3638 SDValue Chain = Node->getOperand(0);
3639 SDValue Table = Node->getOperand(1);
3640 SDValue Index = Node->getOperand(2);
3642 EVT PTy = TLI.getPointerTy();
3644 const TargetData &TD = *TLI.getTargetData();
3645 unsigned EntrySize =
3646 DAG.getMachineFunction().getJumpTableInfo()->getEntrySize(TD);
3648 Index = DAG.getNode(ISD::MUL, dl, PTy,
3649 Index, DAG.getConstant(EntrySize, PTy));
3650 SDValue Addr = DAG.getNode(ISD::ADD, dl, PTy, Index, Table);
3652 EVT MemVT = EVT::getIntegerVT(*DAG.getContext(), EntrySize * 8);
3653 SDValue LD = DAG.getExtLoad(ISD::SEXTLOAD, dl, PTy, Chain, Addr,
3654 MachinePointerInfo::getJumpTable(), MemVT,
3657 if (TM.getRelocationModel() == Reloc::PIC_) {
3658 // For PIC, the sequence is:
3659 // BRIND(load(Jumptable + index) + RelocBase)
3660 // RelocBase can be JumpTable, GOT or some sort of global base.
3661 Addr = DAG.getNode(ISD::ADD, dl, PTy, Addr,
3662 TLI.getPICJumpTableRelocBase(Table, DAG));
3664 Tmp1 = DAG.getNode(ISD::BRIND, dl, MVT::Other, LD.getValue(1), Addr);
3665 Results.push_back(Tmp1);
3669 // Expand brcond's setcc into its constituent parts and create a BR_CC
3671 Tmp1 = Node->getOperand(0);
3672 Tmp2 = Node->getOperand(1);
3673 if (Tmp2.getOpcode() == ISD::SETCC) {
3674 Tmp1 = DAG.getNode(ISD::BR_CC, dl, MVT::Other,
3675 Tmp1, Tmp2.getOperand(2),
3676 Tmp2.getOperand(0), Tmp2.getOperand(1),
3677 Node->getOperand(2));
3679 // We test only the i1 bit. Skip the AND if UNDEF.
3680 Tmp3 = (Tmp2.getOpcode() == ISD::UNDEF) ? Tmp2 :
3681 DAG.getNode(ISD::AND, dl, Tmp2.getValueType(), Tmp2,
3682 DAG.getConstant(1, Tmp2.getValueType()));
3683 Tmp1 = DAG.getNode(ISD::BR_CC, dl, MVT::Other, Tmp1,
3684 DAG.getCondCode(ISD::SETNE), Tmp3,
3685 DAG.getConstant(0, Tmp3.getValueType()),
3686 Node->getOperand(2));
3688 Results.push_back(Tmp1);
3691 Tmp1 = Node->getOperand(0);
3692 Tmp2 = Node->getOperand(1);
3693 Tmp3 = Node->getOperand(2);
3694 LegalizeSetCCCondCode(Node->getValueType(0), Tmp1, Tmp2, Tmp3, dl);
3696 // If we expanded the SETCC into an AND/OR, return the new node
3697 if (Tmp2.getNode() == 0) {
3698 Results.push_back(Tmp1);
3702 // Otherwise, SETCC for the given comparison type must be completely
3703 // illegal; expand it into a SELECT_CC.
3704 EVT VT = Node->getValueType(0);
3705 Tmp1 = DAG.getNode(ISD::SELECT_CC, dl, VT, Tmp1, Tmp2,
3706 DAG.getConstant(1, VT), DAG.getConstant(0, VT), Tmp3);
3707 Results.push_back(Tmp1);
3710 case ISD::SELECT_CC: {
3711 Tmp1 = Node->getOperand(0); // LHS
3712 Tmp2 = Node->getOperand(1); // RHS
3713 Tmp3 = Node->getOperand(2); // True
3714 Tmp4 = Node->getOperand(3); // False
3715 SDValue CC = Node->getOperand(4);
3717 LegalizeSetCCCondCode(TLI.getSetCCResultType(Tmp1.getValueType()),
3718 Tmp1, Tmp2, CC, dl);
3720 assert(!Tmp2.getNode() && "Can't legalize SELECT_CC with legal condition!");
3721 Tmp2 = DAG.getConstant(0, Tmp1.getValueType());
3722 CC = DAG.getCondCode(ISD::SETNE);
3723 Tmp1 = DAG.getNode(ISD::SELECT_CC, dl, Node->getValueType(0), Tmp1, Tmp2,
3725 Results.push_back(Tmp1);
3729 Tmp1 = Node->getOperand(0); // Chain
3730 Tmp2 = Node->getOperand(2); // LHS
3731 Tmp3 = Node->getOperand(3); // RHS
3732 Tmp4 = Node->getOperand(1); // CC
3734 LegalizeSetCCCondCode(TLI.getSetCCResultType(Tmp2.getValueType()),
3735 Tmp2, Tmp3, Tmp4, dl);
3736 assert(LastCALLSEQ.size() == 1 && "branch inside CALLSEQ_BEGIN/END?");
3737 setLastCALLSEQ(DAG.getEntryNode());
3739 assert(!Tmp3.getNode() && "Can't legalize BR_CC with legal condition!");
3740 Tmp3 = DAG.getConstant(0, Tmp2.getValueType());
3741 Tmp4 = DAG.getCondCode(ISD::SETNE);
3742 Tmp1 = DAG.getNode(ISD::BR_CC, dl, Node->getValueType(0), Tmp1, Tmp4, Tmp2,
3743 Tmp3, Node->getOperand(4));
3744 Results.push_back(Tmp1);
3747 case ISD::GLOBAL_OFFSET_TABLE:
3748 case ISD::GlobalAddress:
3749 case ISD::GlobalTLSAddress:
3750 case ISD::ExternalSymbol:
3751 case ISD::ConstantPool:
3752 case ISD::JumpTable:
3753 case ISD::INTRINSIC_W_CHAIN:
3754 case ISD::INTRINSIC_WO_CHAIN:
3755 case ISD::INTRINSIC_VOID:
3756 // FIXME: Custom lowering for these operations shouldn't return null!
3757 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
3758 Results.push_back(SDValue(Node, i));
3762 void SelectionDAGLegalize::PromoteNode(SDNode *Node,
3763 SmallVectorImpl<SDValue> &Results) {
3764 EVT OVT = Node->getValueType(0);
3765 if (Node->getOpcode() == ISD::UINT_TO_FP ||
3766 Node->getOpcode() == ISD::SINT_TO_FP ||
3767 Node->getOpcode() == ISD::SETCC) {
3768 OVT = Node->getOperand(0).getValueType();
3770 EVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
3771 DebugLoc dl = Node->getDebugLoc();
3772 SDValue Tmp1, Tmp2, Tmp3;
3773 switch (Node->getOpcode()) {
3777 // Zero extend the argument.
3778 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Node->getOperand(0));
3779 // Perform the larger operation.
3780 Tmp1 = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1);
3781 if (Node->getOpcode() == ISD::CTTZ) {
3782 //if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT)
3783 Tmp2 = DAG.getSetCC(dl, TLI.getSetCCResultType(NVT),
3784 Tmp1, DAG.getConstant(NVT.getSizeInBits(), NVT),
3786 Tmp1 = DAG.getNode(ISD::SELECT, dl, NVT, Tmp2,
3787 DAG.getConstant(OVT.getSizeInBits(), NVT), Tmp1);
3788 } else if (Node->getOpcode() == ISD::CTLZ) {
3789 // Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT))
3790 Tmp1 = DAG.getNode(ISD::SUB, dl, NVT, Tmp1,
3791 DAG.getConstant(NVT.getSizeInBits() -
3792 OVT.getSizeInBits(), NVT));
3794 Results.push_back(DAG.getNode(ISD::TRUNCATE, dl, OVT, Tmp1));
3797 unsigned DiffBits = NVT.getSizeInBits() - OVT.getSizeInBits();
3798 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Node->getOperand(0));
3799 Tmp1 = DAG.getNode(ISD::BSWAP, dl, NVT, Tmp1);
3800 Tmp1 = DAG.getNode(ISD::SRL, dl, NVT, Tmp1,
3801 DAG.getConstant(DiffBits, TLI.getShiftAmountTy(NVT)));
3802 Results.push_back(Tmp1);
3805 case ISD::FP_TO_UINT:
3806 case ISD::FP_TO_SINT:
3807 Tmp1 = PromoteLegalFP_TO_INT(Node->getOperand(0), Node->getValueType(0),
3808 Node->getOpcode() == ISD::FP_TO_SINT, dl);
3809 Results.push_back(Tmp1);
3811 case ISD::UINT_TO_FP:
3812 case ISD::SINT_TO_FP:
3813 Tmp1 = PromoteLegalINT_TO_FP(Node->getOperand(0), Node->getValueType(0),
3814 Node->getOpcode() == ISD::SINT_TO_FP, dl);
3815 Results.push_back(Tmp1);
3820 unsigned ExtOp, TruncOp;
3821 if (OVT.isVector()) {
3822 ExtOp = ISD::BITCAST;
3823 TruncOp = ISD::BITCAST;
3825 assert(OVT.isInteger() && "Cannot promote logic operation");
3826 ExtOp = ISD::ANY_EXTEND;
3827 TruncOp = ISD::TRUNCATE;
3829 // Promote each of the values to the new type.
3830 Tmp1 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(0));
3831 Tmp2 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(1));
3832 // Perform the larger operation, then convert back
3833 Tmp1 = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1, Tmp2);
3834 Results.push_back(DAG.getNode(TruncOp, dl, OVT, Tmp1));
3838 unsigned ExtOp, TruncOp;
3839 if (Node->getValueType(0).isVector()) {
3840 ExtOp = ISD::BITCAST;
3841 TruncOp = ISD::BITCAST;
3842 } else if (Node->getValueType(0).isInteger()) {
3843 ExtOp = ISD::ANY_EXTEND;
3844 TruncOp = ISD::TRUNCATE;
3846 ExtOp = ISD::FP_EXTEND;
3847 TruncOp = ISD::FP_ROUND;
3849 Tmp1 = Node->getOperand(0);
3850 // Promote each of the values to the new type.
3851 Tmp2 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(1));
3852 Tmp3 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(2));
3853 // Perform the larger operation, then round down.
3854 Tmp1 = DAG.getNode(ISD::SELECT, dl, NVT, Tmp1, Tmp2, Tmp3);
3855 if (TruncOp != ISD::FP_ROUND)
3856 Tmp1 = DAG.getNode(TruncOp, dl, Node->getValueType(0), Tmp1);
3858 Tmp1 = DAG.getNode(TruncOp, dl, Node->getValueType(0), Tmp1,
3859 DAG.getIntPtrConstant(0));
3860 Results.push_back(Tmp1);
3863 case ISD::VECTOR_SHUFFLE: {
3864 SmallVector<int, 8> Mask;
3865 cast<ShuffleVectorSDNode>(Node)->getMask(Mask);
3867 // Cast the two input vectors.
3868 Tmp1 = DAG.getNode(ISD::BITCAST, dl, NVT, Node->getOperand(0));
3869 Tmp2 = DAG.getNode(ISD::BITCAST, dl, NVT, Node->getOperand(1));
3871 // Convert the shuffle mask to the right # elements.
3872 Tmp1 = ShuffleWithNarrowerEltType(NVT, OVT, dl, Tmp1, Tmp2, Mask);
3873 Tmp1 = DAG.getNode(ISD::BITCAST, dl, OVT, Tmp1);
3874 Results.push_back(Tmp1);
3878 unsigned ExtOp = ISD::FP_EXTEND;
3879 if (NVT.isInteger()) {
3880 ISD::CondCode CCCode =
3881 cast<CondCodeSDNode>(Node->getOperand(2))->get();
3882 ExtOp = isSignedIntSetCC(CCCode) ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
3884 Tmp1 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(0));
3885 Tmp2 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(1));
3886 Results.push_back(DAG.getNode(ISD::SETCC, dl, Node->getValueType(0),
3887 Tmp1, Tmp2, Node->getOperand(2)));
3893 // SelectionDAG::Legalize - This is the entry point for the file.
3895 void SelectionDAG::Legalize() {
3896 /// run - This is the main entry point to this class.
3898 SelectionDAGLegalize(*this).LegalizeDAG();