1 //===-- LegalizeDAG.cpp - Implement SelectionDAG::Legalize ----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the SelectionDAG::Legalize method.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/CodeGen/SelectionDAG.h"
15 #include "llvm/CodeGen/MachineFunction.h"
16 #include "llvm/CodeGen/MachineFrameInfo.h"
17 #include "llvm/CodeGen/MachineJumpTableInfo.h"
18 #include "llvm/CodeGen/MachineModuleInfo.h"
19 #include "llvm/CodeGen/PseudoSourceValue.h"
20 #include "llvm/Target/TargetFrameInfo.h"
21 #include "llvm/Target/TargetLowering.h"
22 #include "llvm/Target/TargetData.h"
23 #include "llvm/Target/TargetMachine.h"
24 #include "llvm/Target/TargetOptions.h"
25 #include "llvm/Target/TargetSubtarget.h"
26 #include "llvm/CallingConv.h"
27 #include "llvm/Constants.h"
28 #include "llvm/DerivedTypes.h"
29 #include "llvm/Support/CommandLine.h"
30 #include "llvm/Support/Compiler.h"
31 #include "llvm/Support/MathExtras.h"
32 #include "llvm/ADT/DenseMap.h"
33 #include "llvm/ADT/SmallVector.h"
34 #include "llvm/ADT/SmallPtrSet.h"
40 ViewLegalizeDAGs("view-legalize-dags", cl::Hidden,
41 cl::desc("Pop up a window to show dags before legalize"));
43 static const bool ViewLegalizeDAGs = 0;
46 //===----------------------------------------------------------------------===//
47 /// SelectionDAGLegalize - This takes an arbitrary SelectionDAG as input and
48 /// hacks on it until the target machine can handle it. This involves
49 /// eliminating value sizes the machine cannot handle (promoting small sizes to
50 /// large sizes or splitting up large values into small values) as well as
51 /// eliminating operations the machine cannot handle.
53 /// This code also does a small amount of optimization and recognition of idioms
54 /// as part of its processing. For example, if a target does not support a
55 /// 'setcc' instruction efficiently, but does support 'brcc' instruction, this
56 /// will attempt merge setcc and brc instructions into brcc's.
59 class VISIBILITY_HIDDEN SelectionDAGLegalize {
63 // Libcall insertion helpers.
65 /// LastCALLSEQ_END - This keeps track of the CALLSEQ_END node that has been
66 /// legalized. We use this to ensure that calls are properly serialized
67 /// against each other, including inserted libcalls.
68 SDOperand LastCALLSEQ_END;
70 /// IsLegalizingCall - This member is used *only* for purposes of providing
71 /// helpful assertions that a libcall isn't created while another call is
72 /// being legalized (which could lead to non-serialized call sequences).
73 bool IsLegalizingCall;
76 Legal, // The target natively supports this operation.
77 Promote, // This operation should be executed in a larger type.
78 Expand // Try to expand this to other ops, otherwise use a libcall.
81 /// ValueTypeActions - This is a bitvector that contains two bits for each
82 /// value type, where the two bits correspond to the LegalizeAction enum.
83 /// This can be queried with "getTypeAction(VT)".
84 TargetLowering::ValueTypeActionImpl ValueTypeActions;
86 /// LegalizedNodes - For nodes that are of legal width, and that have more
87 /// than one use, this map indicates what regularized operand to use. This
88 /// allows us to avoid legalizing the same thing more than once.
89 DenseMap<SDOperand, SDOperand> LegalizedNodes;
91 /// PromotedNodes - For nodes that are below legal width, and that have more
92 /// than one use, this map indicates what promoted value to use. This allows
93 /// us to avoid promoting the same thing more than once.
94 DenseMap<SDOperand, SDOperand> PromotedNodes;
96 /// ExpandedNodes - For nodes that need to be expanded this map indicates
97 /// which which operands are the expanded version of the input. This allows
98 /// us to avoid expanding the same node more than once.
99 DenseMap<SDOperand, std::pair<SDOperand, SDOperand> > ExpandedNodes;
101 /// SplitNodes - For vector nodes that need to be split, this map indicates
102 /// which which operands are the split version of the input. This allows us
103 /// to avoid splitting the same node more than once.
104 std::map<SDOperand, std::pair<SDOperand, SDOperand> > SplitNodes;
106 /// ScalarizedNodes - For nodes that need to be converted from vector types to
107 /// scalar types, this contains the mapping of ones we have already
108 /// processed to the result.
109 std::map<SDOperand, SDOperand> ScalarizedNodes;
111 void AddLegalizedOperand(SDOperand From, SDOperand To) {
112 LegalizedNodes.insert(std::make_pair(From, To));
113 // If someone requests legalization of the new node, return itself.
115 LegalizedNodes.insert(std::make_pair(To, To));
117 void AddPromotedOperand(SDOperand From, SDOperand To) {
118 bool isNew = PromotedNodes.insert(std::make_pair(From, To)).second;
119 assert(isNew && "Got into the map somehow?");
120 // If someone requests legalization of the new node, return itself.
121 LegalizedNodes.insert(std::make_pair(To, To));
125 explicit SelectionDAGLegalize(SelectionDAG &DAG);
127 /// getTypeAction - Return how we should legalize values of this type, either
128 /// it is already legal or we need to expand it into multiple registers of
129 /// smaller integer type, or we need to promote it to a larger type.
130 LegalizeAction getTypeAction(MVT VT) const {
131 return (LegalizeAction)ValueTypeActions.getTypeAction(VT);
134 /// isTypeLegal - Return true if this type is legal on this target.
136 bool isTypeLegal(MVT VT) const {
137 return getTypeAction(VT) == Legal;
143 /// HandleOp - Legalize, Promote, or Expand the specified operand as
144 /// appropriate for its type.
145 void HandleOp(SDOperand Op);
147 /// LegalizeOp - We know that the specified value has a legal type.
148 /// Recursively ensure that the operands have legal types, then return the
150 SDOperand LegalizeOp(SDOperand O);
152 /// UnrollVectorOp - We know that the given vector has a legal type, however
153 /// the operation it performs is not legal and is an operation that we have
154 /// no way of lowering. "Unroll" the vector, splitting out the scalars and
155 /// operating on each element individually.
156 SDOperand UnrollVectorOp(SDOperand O);
158 /// PerformInsertVectorEltInMemory - Some target cannot handle a variable
159 /// insertion index for the INSERT_VECTOR_ELT instruction. In this case, it
160 /// is necessary to spill the vector being inserted into to memory, perform
161 /// the insert there, and then read the result back.
162 SDOperand PerformInsertVectorEltInMemory(SDOperand Vec, SDOperand Val,
165 /// PromoteOp - Given an operation that produces a value in an invalid type,
166 /// promote it to compute the value into a larger type. The produced value
167 /// will have the correct bits for the low portion of the register, but no
168 /// guarantee is made about the top bits: it may be zero, sign-extended, or
170 SDOperand PromoteOp(SDOperand O);
172 /// ExpandOp - Expand the specified SDOperand into its two component pieces
173 /// Lo&Hi. Note that the Op MUST be an expanded type. As a result of this,
174 /// the LegalizeNodes map is filled in for any results that are not expanded,
175 /// the ExpandedNodes map is filled in for any results that are expanded, and
176 /// the Lo/Hi values are returned. This applies to integer types and Vector
178 void ExpandOp(SDOperand O, SDOperand &Lo, SDOperand &Hi);
180 /// SplitVectorOp - Given an operand of vector type, break it down into
181 /// two smaller values.
182 void SplitVectorOp(SDOperand O, SDOperand &Lo, SDOperand &Hi);
184 /// ScalarizeVectorOp - Given an operand of single-element vector type
185 /// (e.g. v1f32), convert it into the equivalent operation that returns a
186 /// scalar (e.g. f32) value.
187 SDOperand ScalarizeVectorOp(SDOperand O);
189 /// isShuffleLegal - Return true if a vector shuffle is legal with the
190 /// specified mask and type. Targets can specify exactly which masks they
191 /// support and the code generator is tasked with not creating illegal masks.
193 /// Note that this will also return true for shuffles that are promoted to a
196 /// If this is a legal shuffle, this method returns the (possibly promoted)
197 /// build_vector Mask. If it's not a legal shuffle, it returns null.
198 SDNode *isShuffleLegal(MVT VT, SDOperand Mask) const;
200 bool LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest,
201 SmallPtrSet<SDNode*, 32> &NodesLeadingTo);
203 void LegalizeSetCCOperands(SDOperand &LHS, SDOperand &RHS, SDOperand &CC);
205 SDOperand ExpandLibCall(RTLIB::Libcall LC, SDNode *Node, bool isSigned,
207 SDOperand ExpandIntToFP(bool isSigned, MVT DestTy, SDOperand Source);
209 SDOperand EmitStackConvert(SDOperand SrcOp, MVT SlotVT, MVT DestVT);
210 SDOperand ExpandBUILD_VECTOR(SDNode *Node);
211 SDOperand ExpandSCALAR_TO_VECTOR(SDNode *Node);
212 SDOperand ExpandLegalINT_TO_FP(bool isSigned, SDOperand LegalOp, MVT DestVT);
213 SDOperand PromoteLegalINT_TO_FP(SDOperand LegalOp, MVT DestVT, bool isSigned);
214 SDOperand PromoteLegalFP_TO_INT(SDOperand LegalOp, MVT DestVT, bool isSigned);
216 SDOperand ExpandBSWAP(SDOperand Op);
217 SDOperand ExpandBitCount(unsigned Opc, SDOperand Op);
218 bool ExpandShift(unsigned Opc, SDOperand Op, SDOperand Amt,
219 SDOperand &Lo, SDOperand &Hi);
220 void ExpandShiftParts(unsigned NodeOp, SDOperand Op, SDOperand Amt,
221 SDOperand &Lo, SDOperand &Hi);
223 SDOperand ExpandEXTRACT_SUBVECTOR(SDOperand Op);
224 SDOperand ExpandEXTRACT_VECTOR_ELT(SDOperand Op);
228 /// isVectorShuffleLegal - Return true if a vector shuffle is legal with the
229 /// specified mask and type. Targets can specify exactly which masks they
230 /// support and the code generator is tasked with not creating illegal masks.
232 /// Note that this will also return true for shuffles that are promoted to a
234 SDNode *SelectionDAGLegalize::isShuffleLegal(MVT VT, SDOperand Mask) const {
235 switch (TLI.getOperationAction(ISD::VECTOR_SHUFFLE, VT)) {
237 case TargetLowering::Legal:
238 case TargetLowering::Custom:
240 case TargetLowering::Promote: {
241 // If this is promoted to a different type, convert the shuffle mask and
242 // ask if it is legal in the promoted type!
243 MVT NVT = TLI.getTypeToPromoteTo(ISD::VECTOR_SHUFFLE, VT);
245 // If we changed # elements, change the shuffle mask.
246 unsigned NumEltsGrowth =
247 NVT.getVectorNumElements() / VT.getVectorNumElements();
248 assert(NumEltsGrowth && "Cannot promote to vector type with fewer elts!");
249 if (NumEltsGrowth > 1) {
250 // Renumber the elements.
251 SmallVector<SDOperand, 8> Ops;
252 for (unsigned i = 0, e = Mask.getNumOperands(); i != e; ++i) {
253 SDOperand InOp = Mask.getOperand(i);
254 for (unsigned j = 0; j != NumEltsGrowth; ++j) {
255 if (InOp.getOpcode() == ISD::UNDEF)
256 Ops.push_back(DAG.getNode(ISD::UNDEF, MVT::i32));
258 unsigned InEltNo = cast<ConstantSDNode>(InOp)->getValue();
259 Ops.push_back(DAG.getConstant(InEltNo*NumEltsGrowth+j, MVT::i32));
263 Mask = DAG.getNode(ISD::BUILD_VECTOR, NVT, &Ops[0], Ops.size());
269 return TLI.isShuffleMaskLegal(Mask, VT) ? Mask.Val : 0;
272 SelectionDAGLegalize::SelectionDAGLegalize(SelectionDAG &dag)
273 : TLI(dag.getTargetLoweringInfo()), DAG(dag),
274 ValueTypeActions(TLI.getValueTypeActions()) {
275 assert(MVT::LAST_VALUETYPE <= 32 &&
276 "Too many value types for ValueTypeActions to hold!");
279 /// ComputeTopDownOrdering - Compute a top-down ordering of the dag, where Order
280 /// contains all of a nodes operands before it contains the node.
281 static void ComputeTopDownOrdering(SelectionDAG &DAG,
282 SmallVector<SDNode*, 64> &Order) {
284 DenseMap<SDNode*, unsigned> Visited;
285 std::vector<SDNode*> Worklist;
286 Worklist.reserve(128);
288 // Compute ordering from all of the leaves in the graphs, those (like the
289 // entry node) that have no operands.
290 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(),
291 E = DAG.allnodes_end(); I != E; ++I) {
292 if (I->getNumOperands() == 0) {
294 Worklist.push_back(I);
298 while (!Worklist.empty()) {
299 SDNode *N = Worklist.back();
302 if (++Visited[N] != N->getNumOperands())
303 continue; // Haven't visited all operands yet
307 // Now that we have N in, add anything that uses it if all of their operands
309 for (SDNode::use_iterator UI = N->use_begin(), E = N->use_end();
311 Worklist.push_back(UI->getUser());
314 assert(Order.size() == Visited.size() &&
315 Order.size() == DAG.allnodes_size() &&
316 "Error: DAG is cyclic!");
320 void SelectionDAGLegalize::LegalizeDAG() {
321 LastCALLSEQ_END = DAG.getEntryNode();
322 IsLegalizingCall = false;
324 // The legalize process is inherently a bottom-up recursive process (users
325 // legalize their uses before themselves). Given infinite stack space, we
326 // could just start legalizing on the root and traverse the whole graph. In
327 // practice however, this causes us to run out of stack space on large basic
328 // blocks. To avoid this problem, compute an ordering of the nodes where each
329 // node is only legalized after all of its operands are legalized.
330 SmallVector<SDNode*, 64> Order;
331 ComputeTopDownOrdering(DAG, Order);
333 for (unsigned i = 0, e = Order.size(); i != e; ++i)
334 HandleOp(SDOperand(Order[i], 0));
336 // Finally, it's possible the root changed. Get the new root.
337 SDOperand OldRoot = DAG.getRoot();
338 assert(LegalizedNodes.count(OldRoot) && "Root didn't get legalized?");
339 DAG.setRoot(LegalizedNodes[OldRoot]);
341 ExpandedNodes.clear();
342 LegalizedNodes.clear();
343 PromotedNodes.clear();
345 ScalarizedNodes.clear();
347 // Remove dead nodes now.
348 DAG.RemoveDeadNodes();
352 /// FindCallEndFromCallStart - Given a chained node that is part of a call
353 /// sequence, find the CALLSEQ_END node that terminates the call sequence.
354 static SDNode *FindCallEndFromCallStart(SDNode *Node) {
355 if (Node->getOpcode() == ISD::CALLSEQ_END)
357 if (Node->use_empty())
358 return 0; // No CallSeqEnd
360 // The chain is usually at the end.
361 SDOperand TheChain(Node, Node->getNumValues()-1);
362 if (TheChain.getValueType() != MVT::Other) {
363 // Sometimes it's at the beginning.
364 TheChain = SDOperand(Node, 0);
365 if (TheChain.getValueType() != MVT::Other) {
366 // Otherwise, hunt for it.
367 for (unsigned i = 1, e = Node->getNumValues(); i != e; ++i)
368 if (Node->getValueType(i) == MVT::Other) {
369 TheChain = SDOperand(Node, i);
373 // Otherwise, we walked into a node without a chain.
374 if (TheChain.getValueType() != MVT::Other)
379 for (SDNode::use_iterator UI = Node->use_begin(),
380 E = Node->use_end(); UI != E; ++UI) {
382 // Make sure to only follow users of our token chain.
383 SDNode *User = UI->getUser();
384 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i)
385 if (User->getOperand(i) == TheChain)
386 if (SDNode *Result = FindCallEndFromCallStart(User))
392 /// FindCallStartFromCallEnd - Given a chained node that is part of a call
393 /// sequence, find the CALLSEQ_START node that initiates the call sequence.
394 static SDNode *FindCallStartFromCallEnd(SDNode *Node) {
395 assert(Node && "Didn't find callseq_start for a call??");
396 if (Node->getOpcode() == ISD::CALLSEQ_START) return Node;
398 assert(Node->getOperand(0).getValueType() == MVT::Other &&
399 "Node doesn't have a token chain argument!");
400 return FindCallStartFromCallEnd(Node->getOperand(0).Val);
403 /// LegalizeAllNodesNotLeadingTo - Recursively walk the uses of N, looking to
404 /// see if any uses can reach Dest. If no dest operands can get to dest,
405 /// legalize them, legalize ourself, and return false, otherwise, return true.
407 /// Keep track of the nodes we fine that actually do lead to Dest in
408 /// NodesLeadingTo. This avoids retraversing them exponential number of times.
410 bool SelectionDAGLegalize::LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest,
411 SmallPtrSet<SDNode*, 32> &NodesLeadingTo) {
412 if (N == Dest) return true; // N certainly leads to Dest :)
414 // If we've already processed this node and it does lead to Dest, there is no
415 // need to reprocess it.
416 if (NodesLeadingTo.count(N)) return true;
418 // If the first result of this node has been already legalized, then it cannot
420 switch (getTypeAction(N->getValueType(0))) {
422 if (LegalizedNodes.count(SDOperand(N, 0))) return false;
425 if (PromotedNodes.count(SDOperand(N, 0))) return false;
428 if (ExpandedNodes.count(SDOperand(N, 0))) return false;
432 // Okay, this node has not already been legalized. Check and legalize all
433 // operands. If none lead to Dest, then we can legalize this node.
434 bool OperandsLeadToDest = false;
435 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
436 OperandsLeadToDest |= // If an operand leads to Dest, so do we.
437 LegalizeAllNodesNotLeadingTo(N->getOperand(i).Val, Dest, NodesLeadingTo);
439 if (OperandsLeadToDest) {
440 NodesLeadingTo.insert(N);
444 // Okay, this node looks safe, legalize it and return false.
445 HandleOp(SDOperand(N, 0));
449 /// HandleOp - Legalize, Promote, or Expand the specified operand as
450 /// appropriate for its type.
451 void SelectionDAGLegalize::HandleOp(SDOperand Op) {
452 MVT VT = Op.getValueType();
453 switch (getTypeAction(VT)) {
454 default: assert(0 && "Bad type action!");
455 case Legal: (void)LegalizeOp(Op); break;
456 case Promote: (void)PromoteOp(Op); break;
458 if (!VT.isVector()) {
459 // If this is an illegal scalar, expand it into its two component
462 if (Op.getOpcode() == ISD::TargetConstant)
463 break; // Allow illegal target nodes.
465 } else if (VT.getVectorNumElements() == 1) {
466 // If this is an illegal single element vector, convert it to a
468 (void)ScalarizeVectorOp(Op);
470 // Otherwise, this is an illegal multiple element vector.
471 // Split it in half and legalize both parts.
473 SplitVectorOp(Op, X, Y);
479 /// ExpandConstantFP - Expands the ConstantFP node to an integer constant or
480 /// a load from the constant pool.
481 static SDOperand ExpandConstantFP(ConstantFPSDNode *CFP, bool UseCP,
482 SelectionDAG &DAG, TargetLowering &TLI) {
485 // If a FP immediate is precise when represented as a float and if the
486 // target can do an extending load from float to double, we put it into
487 // the constant pool as a float, even if it's is statically typed as a
488 // double. This shrinks FP constants and canonicalizes them for targets where
489 // an FP extending load is the same cost as a normal load (such as on the x87
490 // fp stack or PPC FP unit).
491 MVT VT = CFP->getValueType(0);
492 ConstantFP *LLVMC = ConstantFP::get(CFP->getValueAPF());
494 if (VT!=MVT::f64 && VT!=MVT::f32)
495 assert(0 && "Invalid type expansion");
496 return DAG.getConstant(LLVMC->getValueAPF().convertToAPInt(),
497 (VT == MVT::f64) ? MVT::i64 : MVT::i32);
502 while (SVT != MVT::f32) {
503 SVT = (MVT::SimpleValueType)(SVT.getSimpleVT() - 1);
504 if (CFP->isValueValidForType(SVT, CFP->getValueAPF()) &&
505 // Only do this if the target has a native EXTLOAD instruction from
507 TLI.isLoadXLegal(ISD::EXTLOAD, SVT) &&
508 TLI.ShouldShrinkFPConstant(OrigVT)) {
509 const Type *SType = SVT.getTypeForMVT();
510 LLVMC = cast<ConstantFP>(ConstantExpr::getFPTrunc(LLVMC, SType));
516 SDOperand CPIdx = DAG.getConstantPool(LLVMC, TLI.getPointerTy());
518 return DAG.getExtLoad(ISD::EXTLOAD, OrigVT, DAG.getEntryNode(),
519 CPIdx, PseudoSourceValue::getConstantPool(),
521 return DAG.getLoad(OrigVT, DAG.getEntryNode(), CPIdx,
522 PseudoSourceValue::getConstantPool(), 0);
526 /// ExpandFCOPYSIGNToBitwiseOps - Expands fcopysign to a series of bitwise
529 SDOperand ExpandFCOPYSIGNToBitwiseOps(SDNode *Node, MVT NVT,
530 SelectionDAG &DAG, TargetLowering &TLI) {
531 MVT VT = Node->getValueType(0);
532 MVT SrcVT = Node->getOperand(1).getValueType();
533 assert((SrcVT == MVT::f32 || SrcVT == MVT::f64) &&
534 "fcopysign expansion only supported for f32 and f64");
535 MVT SrcNVT = (SrcVT == MVT::f64) ? MVT::i64 : MVT::i32;
537 // First get the sign bit of second operand.
538 SDOperand Mask1 = (SrcVT == MVT::f64)
539 ? DAG.getConstantFP(BitsToDouble(1ULL << 63), SrcVT)
540 : DAG.getConstantFP(BitsToFloat(1U << 31), SrcVT);
541 Mask1 = DAG.getNode(ISD::BIT_CONVERT, SrcNVT, Mask1);
542 SDOperand SignBit= DAG.getNode(ISD::BIT_CONVERT, SrcNVT, Node->getOperand(1));
543 SignBit = DAG.getNode(ISD::AND, SrcNVT, SignBit, Mask1);
544 // Shift right or sign-extend it if the two operands have different types.
545 int SizeDiff = SrcNVT.getSizeInBits() - NVT.getSizeInBits();
547 SignBit = DAG.getNode(ISD::SRL, SrcNVT, SignBit,
548 DAG.getConstant(SizeDiff, TLI.getShiftAmountTy()));
549 SignBit = DAG.getNode(ISD::TRUNCATE, NVT, SignBit);
550 } else if (SizeDiff < 0) {
551 SignBit = DAG.getNode(ISD::ZERO_EXTEND, NVT, SignBit);
552 SignBit = DAG.getNode(ISD::SHL, NVT, SignBit,
553 DAG.getConstant(-SizeDiff, TLI.getShiftAmountTy()));
556 // Clear the sign bit of first operand.
557 SDOperand Mask2 = (VT == MVT::f64)
558 ? DAG.getConstantFP(BitsToDouble(~(1ULL << 63)), VT)
559 : DAG.getConstantFP(BitsToFloat(~(1U << 31)), VT);
560 Mask2 = DAG.getNode(ISD::BIT_CONVERT, NVT, Mask2);
561 SDOperand Result = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0));
562 Result = DAG.getNode(ISD::AND, NVT, Result, Mask2);
564 // Or the value with the sign bit.
565 Result = DAG.getNode(ISD::OR, NVT, Result, SignBit);
569 /// ExpandUnalignedStore - Expands an unaligned store to 2 half-size stores.
571 SDOperand ExpandUnalignedStore(StoreSDNode *ST, SelectionDAG &DAG,
572 TargetLowering &TLI) {
573 SDOperand Chain = ST->getChain();
574 SDOperand Ptr = ST->getBasePtr();
575 SDOperand Val = ST->getValue();
576 MVT VT = Val.getValueType();
577 int Alignment = ST->getAlignment();
578 int SVOffset = ST->getSrcValueOffset();
579 if (ST->getMemoryVT().isFloatingPoint() ||
580 ST->getMemoryVT().isVector()) {
581 // Expand to a bitconvert of the value to the integer type of the
582 // same size, then a (misaligned) int store.
584 if (VT.is128BitVector() || VT == MVT::ppcf128 || VT == MVT::f128)
586 else if (VT.is64BitVector() || VT==MVT::f64)
588 else if (VT==MVT::f32)
591 assert(0 && "Unaligned store of unsupported type");
593 SDOperand Result = DAG.getNode(ISD::BIT_CONVERT, intVT, Val);
594 return DAG.getStore(Chain, Result, Ptr, ST->getSrcValue(),
595 SVOffset, ST->isVolatile(), Alignment);
597 assert(ST->getMemoryVT().isInteger() &&
598 !ST->getMemoryVT().isVector() &&
599 "Unaligned store of unknown type.");
600 // Get the half-size VT
602 (MVT::SimpleValueType)(ST->getMemoryVT().getSimpleVT() - 1);
603 int NumBits = NewStoredVT.getSizeInBits();
604 int IncrementSize = NumBits / 8;
606 // Divide the stored value in two parts.
607 SDOperand ShiftAmount = DAG.getConstant(NumBits, TLI.getShiftAmountTy());
609 SDOperand Hi = DAG.getNode(ISD::SRL, VT, Val, ShiftAmount);
611 // Store the two parts
612 SDOperand Store1, Store2;
613 Store1 = DAG.getTruncStore(Chain, TLI.isLittleEndian()?Lo:Hi, Ptr,
614 ST->getSrcValue(), SVOffset, NewStoredVT,
615 ST->isVolatile(), Alignment);
616 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
617 DAG.getConstant(IncrementSize, TLI.getPointerTy()));
618 Alignment = MinAlign(Alignment, IncrementSize);
619 Store2 = DAG.getTruncStore(Chain, TLI.isLittleEndian()?Hi:Lo, Ptr,
620 ST->getSrcValue(), SVOffset + IncrementSize,
621 NewStoredVT, ST->isVolatile(), Alignment);
623 return DAG.getNode(ISD::TokenFactor, MVT::Other, Store1, Store2);
626 /// ExpandUnalignedLoad - Expands an unaligned load to 2 half-size loads.
628 SDOperand ExpandUnalignedLoad(LoadSDNode *LD, SelectionDAG &DAG,
629 TargetLowering &TLI) {
630 int SVOffset = LD->getSrcValueOffset();
631 SDOperand Chain = LD->getChain();
632 SDOperand Ptr = LD->getBasePtr();
633 MVT VT = LD->getValueType(0);
634 MVT LoadedVT = LD->getMemoryVT();
635 if (VT.isFloatingPoint() || VT.isVector()) {
636 // Expand to a (misaligned) integer load of the same size,
637 // then bitconvert to floating point or vector.
639 if (LoadedVT.is128BitVector() ||
640 LoadedVT == MVT::ppcf128 || LoadedVT == MVT::f128)
642 else if (LoadedVT.is64BitVector() || LoadedVT == MVT::f64)
644 else if (LoadedVT == MVT::f32)
647 assert(0 && "Unaligned load of unsupported type");
649 SDOperand newLoad = DAG.getLoad(intVT, Chain, Ptr, LD->getSrcValue(),
650 SVOffset, LD->isVolatile(),
652 SDOperand Result = DAG.getNode(ISD::BIT_CONVERT, LoadedVT, newLoad);
653 if (VT.isFloatingPoint() && LoadedVT != VT)
654 Result = DAG.getNode(ISD::FP_EXTEND, VT, Result);
656 SDOperand Ops[] = { Result, Chain };
657 return DAG.getMergeValues(Ops, 2);
659 assert(LoadedVT.isInteger() && !LoadedVT.isVector() &&
660 "Unaligned load of unsupported type.");
662 // Compute the new VT that is half the size of the old one. This is an
664 unsigned NumBits = LoadedVT.getSizeInBits();
666 NewLoadedVT = MVT::getIntegerVT(NumBits/2);
669 unsigned Alignment = LD->getAlignment();
670 unsigned IncrementSize = NumBits / 8;
671 ISD::LoadExtType HiExtType = LD->getExtensionType();
673 // If the original load is NON_EXTLOAD, the hi part load must be ZEXTLOAD.
674 if (HiExtType == ISD::NON_EXTLOAD)
675 HiExtType = ISD::ZEXTLOAD;
677 // Load the value in two parts
679 if (TLI.isLittleEndian()) {
680 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, VT, Chain, Ptr, LD->getSrcValue(),
681 SVOffset, NewLoadedVT, LD->isVolatile(), Alignment);
682 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
683 DAG.getConstant(IncrementSize, TLI.getPointerTy()));
684 Hi = DAG.getExtLoad(HiExtType, VT, Chain, Ptr, LD->getSrcValue(),
685 SVOffset + IncrementSize, NewLoadedVT, LD->isVolatile(),
686 MinAlign(Alignment, IncrementSize));
688 Hi = DAG.getExtLoad(HiExtType, VT, Chain, Ptr, LD->getSrcValue(), SVOffset,
689 NewLoadedVT,LD->isVolatile(), Alignment);
690 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
691 DAG.getConstant(IncrementSize, TLI.getPointerTy()));
692 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, VT, Chain, Ptr, LD->getSrcValue(),
693 SVOffset + IncrementSize, NewLoadedVT, LD->isVolatile(),
694 MinAlign(Alignment, IncrementSize));
697 // aggregate the two parts
698 SDOperand ShiftAmount = DAG.getConstant(NumBits, TLI.getShiftAmountTy());
699 SDOperand Result = DAG.getNode(ISD::SHL, VT, Hi, ShiftAmount);
700 Result = DAG.getNode(ISD::OR, VT, Result, Lo);
702 SDOperand TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
705 SDOperand Ops[] = { Result, TF };
706 return DAG.getMergeValues(Ops, 2);
709 /// UnrollVectorOp - We know that the given vector has a legal type, however
710 /// the operation it performs is not legal and is an operation that we have
711 /// no way of lowering. "Unroll" the vector, splitting out the scalars and
712 /// operating on each element individually.
713 SDOperand SelectionDAGLegalize::UnrollVectorOp(SDOperand Op) {
714 MVT VT = Op.getValueType();
715 assert(isTypeLegal(VT) &&
716 "Caller should expand or promote operands that are not legal!");
717 assert(Op.Val->getNumValues() == 1 &&
718 "Can't unroll a vector with multiple results!");
719 unsigned NE = VT.getVectorNumElements();
720 MVT EltVT = VT.getVectorElementType();
722 SmallVector<SDOperand, 8> Scalars;
723 SmallVector<SDOperand, 4> Operands(Op.getNumOperands());
724 for (unsigned i = 0; i != NE; ++i) {
725 for (unsigned j = 0; j != Op.getNumOperands(); ++j) {
726 SDOperand Operand = Op.getOperand(j);
727 MVT OperandVT = Operand.getValueType();
728 if (OperandVT.isVector()) {
729 // A vector operand; extract a single element.
730 MVT OperandEltVT = OperandVT.getVectorElementType();
731 Operands[j] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT,
734 DAG.getConstant(i, MVT::i32));
736 // A scalar operand; just use it as is.
737 Operands[j] = Operand;
740 Scalars.push_back(DAG.getNode(Op.getOpcode(), EltVT,
741 &Operands[0], Operands.size()));
744 return DAG.getNode(ISD::BUILD_VECTOR, VT, &Scalars[0], Scalars.size());
747 /// GetFPLibCall - Return the right libcall for the given floating point type.
748 static RTLIB::Libcall GetFPLibCall(MVT VT,
749 RTLIB::Libcall Call_F32,
750 RTLIB::Libcall Call_F64,
751 RTLIB::Libcall Call_F80,
752 RTLIB::Libcall Call_PPCF128) {
754 VT == MVT::f32 ? Call_F32 :
755 VT == MVT::f64 ? Call_F64 :
756 VT == MVT::f80 ? Call_F80 :
757 VT == MVT::ppcf128 ? Call_PPCF128 :
758 RTLIB::UNKNOWN_LIBCALL;
761 /// PerformInsertVectorEltInMemory - Some target cannot handle a variable
762 /// insertion index for the INSERT_VECTOR_ELT instruction. In this case, it
763 /// is necessary to spill the vector being inserted into to memory, perform
764 /// the insert there, and then read the result back.
765 SDOperand SelectionDAGLegalize::
766 PerformInsertVectorEltInMemory(SDOperand Vec, SDOperand Val, SDOperand Idx) {
767 SDOperand Tmp1 = Vec;
768 SDOperand Tmp2 = Val;
769 SDOperand Tmp3 = Idx;
771 // If the target doesn't support this, we have to spill the input vector
772 // to a temporary stack slot, update the element, then reload it. This is
773 // badness. We could also load the value into a vector register (either
774 // with a "move to register" or "extload into register" instruction, then
775 // permute it into place, if the idx is a constant and if the idx is
776 // supported by the target.
777 MVT VT = Tmp1.getValueType();
778 MVT EltVT = VT.getVectorElementType();
779 MVT IdxVT = Tmp3.getValueType();
780 MVT PtrVT = TLI.getPointerTy();
781 SDOperand StackPtr = DAG.CreateStackTemporary(VT);
783 int SPFI = cast<FrameIndexSDNode>(StackPtr.Val)->getIndex();
786 SDOperand Ch = DAG.getStore(DAG.getEntryNode(), Tmp1, StackPtr,
787 PseudoSourceValue::getFixedStack(SPFI), 0);
789 // Truncate or zero extend offset to target pointer type.
790 unsigned CastOpc = IdxVT.bitsGT(PtrVT) ? ISD::TRUNCATE : ISD::ZERO_EXTEND;
791 Tmp3 = DAG.getNode(CastOpc, PtrVT, Tmp3);
792 // Add the offset to the index.
793 unsigned EltSize = EltVT.getSizeInBits()/8;
794 Tmp3 = DAG.getNode(ISD::MUL, IdxVT, Tmp3,DAG.getConstant(EltSize, IdxVT));
795 SDOperand StackPtr2 = DAG.getNode(ISD::ADD, IdxVT, Tmp3, StackPtr);
796 // Store the scalar value.
797 Ch = DAG.getTruncStore(Ch, Tmp2, StackPtr2,
798 PseudoSourceValue::getFixedStack(SPFI), 0, EltVT);
799 // Load the updated vector.
800 return DAG.getLoad(VT, Ch, StackPtr,
801 PseudoSourceValue::getFixedStack(SPFI), 0);
804 /// LegalizeOp - We know that the specified value has a legal type, and
805 /// that its operands are legal. Now ensure that the operation itself
806 /// is legal, recursively ensuring that the operands' operations remain
808 SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
809 if (Op.getOpcode() == ISD::TargetConstant) // Allow illegal target nodes.
812 assert(isTypeLegal(Op.getValueType()) &&
813 "Caller should expand or promote operands that are not legal!");
814 SDNode *Node = Op.Val;
816 // If this operation defines any values that cannot be represented in a
817 // register on this target, make sure to expand or promote them.
818 if (Node->getNumValues() > 1) {
819 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
820 if (getTypeAction(Node->getValueType(i)) != Legal) {
821 HandleOp(Op.getValue(i));
822 assert(LegalizedNodes.count(Op) &&
823 "Handling didn't add legal operands!");
824 return LegalizedNodes[Op];
828 // Note that LegalizeOp may be reentered even from single-use nodes, which
829 // means that we always must cache transformed nodes.
830 DenseMap<SDOperand, SDOperand>::iterator I = LegalizedNodes.find(Op);
831 if (I != LegalizedNodes.end()) return I->second;
833 SDOperand Tmp1, Tmp2, Tmp3, Tmp4;
834 SDOperand Result = Op;
835 bool isCustom = false;
837 switch (Node->getOpcode()) {
838 case ISD::FrameIndex:
839 case ISD::EntryToken:
841 case ISD::BasicBlock:
842 case ISD::TargetFrameIndex:
843 case ISD::TargetJumpTable:
844 case ISD::TargetConstant:
845 case ISD::TargetConstantFP:
846 case ISD::TargetConstantPool:
847 case ISD::TargetGlobalAddress:
848 case ISD::TargetGlobalTLSAddress:
849 case ISD::TargetExternalSymbol:
852 case ISD::MEMOPERAND:
855 // Primitives must all be legal.
856 assert(TLI.isOperationLegal(Node->getOpcode(), Node->getValueType(0)) &&
857 "This must be legal!");
860 if (Node->getOpcode() >= ISD::BUILTIN_OP_END) {
861 // If this is a target node, legalize it by legalizing the operands then
862 // passing it through.
863 SmallVector<SDOperand, 8> Ops;
864 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
865 Ops.push_back(LegalizeOp(Node->getOperand(i)));
867 Result = DAG.UpdateNodeOperands(Result.getValue(0), &Ops[0], Ops.size());
869 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
870 AddLegalizedOperand(Op.getValue(i), Result.getValue(i));
871 return Result.getValue(Op.ResNo);
873 // Otherwise this is an unhandled builtin node. splat.
875 cerr << "NODE: "; Node->dump(&DAG); cerr << "\n";
877 assert(0 && "Do not know how to legalize this operator!");
879 case ISD::GLOBAL_OFFSET_TABLE:
880 case ISD::GlobalAddress:
881 case ISD::GlobalTLSAddress:
882 case ISD::ExternalSymbol:
883 case ISD::ConstantPool:
884 case ISD::JumpTable: // Nothing to do.
885 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
886 default: assert(0 && "This action is not supported yet!");
887 case TargetLowering::Custom:
888 Tmp1 = TLI.LowerOperation(Op, DAG);
889 if (Tmp1.Val) Result = Tmp1;
890 // FALLTHROUGH if the target doesn't want to lower this op after all.
891 case TargetLowering::Legal:
896 case ISD::RETURNADDR:
897 // The only option for these nodes is to custom lower them. If the target
898 // does not custom lower them, then return zero.
899 Tmp1 = TLI.LowerOperation(Op, DAG);
903 Result = DAG.getConstant(0, TLI.getPointerTy());
905 case ISD::FRAME_TO_ARGS_OFFSET: {
906 MVT VT = Node->getValueType(0);
907 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
908 default: assert(0 && "This action is not supported yet!");
909 case TargetLowering::Custom:
910 Result = TLI.LowerOperation(Op, DAG);
911 if (Result.Val) break;
913 case TargetLowering::Legal:
914 Result = DAG.getConstant(0, VT);
919 case ISD::EXCEPTIONADDR: {
920 Tmp1 = LegalizeOp(Node->getOperand(0));
921 MVT VT = Node->getValueType(0);
922 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
923 default: assert(0 && "This action is not supported yet!");
924 case TargetLowering::Expand: {
925 unsigned Reg = TLI.getExceptionAddressRegister();
926 Result = DAG.getCopyFromReg(Tmp1, Reg, VT);
929 case TargetLowering::Custom:
930 Result = TLI.LowerOperation(Op, DAG);
931 if (Result.Val) break;
933 case TargetLowering::Legal: {
934 SDOperand Ops[] = { DAG.getConstant(0, VT), Tmp1 };
935 Result = DAG.getMergeValues(Ops, 2);
940 if (Result.Val->getNumValues() == 1) break;
942 assert(Result.Val->getNumValues() == 2 &&
943 "Cannot return more than two values!");
945 // Since we produced two values, make sure to remember that we
946 // legalized both of them.
947 Tmp1 = LegalizeOp(Result);
948 Tmp2 = LegalizeOp(Result.getValue(1));
949 AddLegalizedOperand(Op.getValue(0), Tmp1);
950 AddLegalizedOperand(Op.getValue(1), Tmp2);
951 return Op.ResNo ? Tmp2 : Tmp1;
952 case ISD::EHSELECTION: {
953 Tmp1 = LegalizeOp(Node->getOperand(0));
954 Tmp2 = LegalizeOp(Node->getOperand(1));
955 MVT VT = Node->getValueType(0);
956 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
957 default: assert(0 && "This action is not supported yet!");
958 case TargetLowering::Expand: {
959 unsigned Reg = TLI.getExceptionSelectorRegister();
960 Result = DAG.getCopyFromReg(Tmp2, Reg, VT);
963 case TargetLowering::Custom:
964 Result = TLI.LowerOperation(Op, DAG);
965 if (Result.Val) break;
967 case TargetLowering::Legal: {
968 SDOperand Ops[] = { DAG.getConstant(0, VT), Tmp2 };
969 Result = DAG.getMergeValues(Ops, 2);
974 if (Result.Val->getNumValues() == 1) break;
976 assert(Result.Val->getNumValues() == 2 &&
977 "Cannot return more than two values!");
979 // Since we produced two values, make sure to remember that we
980 // legalized both of them.
981 Tmp1 = LegalizeOp(Result);
982 Tmp2 = LegalizeOp(Result.getValue(1));
983 AddLegalizedOperand(Op.getValue(0), Tmp1);
984 AddLegalizedOperand(Op.getValue(1), Tmp2);
985 return Op.ResNo ? Tmp2 : Tmp1;
986 case ISD::EH_RETURN: {
987 MVT VT = Node->getValueType(0);
988 // The only "good" option for this node is to custom lower it.
989 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
990 default: assert(0 && "This action is not supported at all!");
991 case TargetLowering::Custom:
992 Result = TLI.LowerOperation(Op, DAG);
993 if (Result.Val) break;
995 case TargetLowering::Legal:
996 // Target does not know, how to lower this, lower to noop
997 Result = LegalizeOp(Node->getOperand(0));
1002 case ISD::AssertSext:
1003 case ISD::AssertZext:
1004 Tmp1 = LegalizeOp(Node->getOperand(0));
1005 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
1007 case ISD::MERGE_VALUES:
1008 // Legalize eliminates MERGE_VALUES nodes.
1009 Result = Node->getOperand(Op.ResNo);
1011 case ISD::CopyFromReg:
1012 Tmp1 = LegalizeOp(Node->getOperand(0));
1013 Result = Op.getValue(0);
1014 if (Node->getNumValues() == 2) {
1015 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
1017 assert(Node->getNumValues() == 3 && "Invalid copyfromreg!");
1018 if (Node->getNumOperands() == 3) {
1019 Tmp2 = LegalizeOp(Node->getOperand(2));
1020 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1),Tmp2);
1022 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
1024 AddLegalizedOperand(Op.getValue(2), Result.getValue(2));
1026 // Since CopyFromReg produces two values, make sure to remember that we
1027 // legalized both of them.
1028 AddLegalizedOperand(Op.getValue(0), Result);
1029 AddLegalizedOperand(Op.getValue(1), Result.getValue(1));
1030 return Result.getValue(Op.ResNo);
1032 MVT VT = Op.getValueType();
1033 switch (TLI.getOperationAction(ISD::UNDEF, VT)) {
1034 default: assert(0 && "This action is not supported yet!");
1035 case TargetLowering::Expand:
1037 Result = DAG.getConstant(0, VT);
1038 else if (VT.isFloatingPoint())
1039 Result = DAG.getConstantFP(APFloat(APInt(VT.getSizeInBits(), 0)),
1042 assert(0 && "Unknown value type!");
1044 case TargetLowering::Legal:
1050 case ISD::INTRINSIC_W_CHAIN:
1051 case ISD::INTRINSIC_WO_CHAIN:
1052 case ISD::INTRINSIC_VOID: {
1053 SmallVector<SDOperand, 8> Ops;
1054 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
1055 Ops.push_back(LegalizeOp(Node->getOperand(i)));
1056 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1058 // Allow the target to custom lower its intrinsics if it wants to.
1059 if (TLI.getOperationAction(Node->getOpcode(), MVT::Other) ==
1060 TargetLowering::Custom) {
1061 Tmp3 = TLI.LowerOperation(Result, DAG);
1062 if (Tmp3.Val) Result = Tmp3;
1065 if (Result.Val->getNumValues() == 1) break;
1067 // Must have return value and chain result.
1068 assert(Result.Val->getNumValues() == 2 &&
1069 "Cannot return more than two values!");
1071 // Since loads produce two values, make sure to remember that we
1072 // legalized both of them.
1073 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
1074 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
1075 return Result.getValue(Op.ResNo);
1078 case ISD::DBG_STOPPOINT:
1079 assert(Node->getNumOperands() == 1 && "Invalid DBG_STOPPOINT node!");
1080 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the input chain.
1082 switch (TLI.getOperationAction(ISD::DBG_STOPPOINT, MVT::Other)) {
1083 case TargetLowering::Promote:
1084 default: assert(0 && "This action is not supported yet!");
1085 case TargetLowering::Expand: {
1086 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
1087 bool useDEBUG_LOC = TLI.isOperationLegal(ISD::DEBUG_LOC, MVT::Other);
1088 bool useLABEL = TLI.isOperationLegal(ISD::DBG_LABEL, MVT::Other);
1090 const DbgStopPointSDNode *DSP = cast<DbgStopPointSDNode>(Node);
1091 if (MMI && (useDEBUG_LOC || useLABEL)) {
1092 const CompileUnitDesc *CompileUnit = DSP->getCompileUnit();
1093 unsigned SrcFile = MMI->RecordSource(CompileUnit);
1095 unsigned Line = DSP->getLine();
1096 unsigned Col = DSP->getColumn();
1099 SDOperand Ops[] = { Tmp1, DAG.getConstant(Line, MVT::i32),
1100 DAG.getConstant(Col, MVT::i32),
1101 DAG.getConstant(SrcFile, MVT::i32) };
1102 Result = DAG.getNode(ISD::DEBUG_LOC, MVT::Other, Ops, 4);
1104 unsigned ID = MMI->RecordSourceLine(Line, Col, SrcFile);
1105 Result = DAG.getLabel(ISD::DBG_LABEL, Tmp1, ID);
1108 Result = Tmp1; // chain
1112 case TargetLowering::Legal: {
1113 LegalizeAction Action = getTypeAction(Node->getOperand(1).getValueType());
1114 if (Action == Legal && Tmp1 == Node->getOperand(0))
1117 SmallVector<SDOperand, 8> Ops;
1118 Ops.push_back(Tmp1);
1119 if (Action == Legal) {
1120 Ops.push_back(Node->getOperand(1)); // line # must be legal.
1121 Ops.push_back(Node->getOperand(2)); // col # must be legal.
1123 // Otherwise promote them.
1124 Ops.push_back(PromoteOp(Node->getOperand(1)));
1125 Ops.push_back(PromoteOp(Node->getOperand(2)));
1127 Ops.push_back(Node->getOperand(3)); // filename must be legal.
1128 Ops.push_back(Node->getOperand(4)); // working dir # must be legal.
1129 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1136 assert(Node->getNumOperands() == 3 && "Invalid DECLARE node!");
1137 switch (TLI.getOperationAction(ISD::DECLARE, MVT::Other)) {
1138 default: assert(0 && "This action is not supported yet!");
1139 case TargetLowering::Legal:
1140 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1141 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the address.
1142 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the variable.
1143 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1145 case TargetLowering::Expand:
1146 Result = LegalizeOp(Node->getOperand(0));
1151 case ISD::DEBUG_LOC:
1152 assert(Node->getNumOperands() == 4 && "Invalid DEBUG_LOC node!");
1153 switch (TLI.getOperationAction(ISD::DEBUG_LOC, MVT::Other)) {
1154 default: assert(0 && "This action is not supported yet!");
1155 case TargetLowering::Legal: {
1156 LegalizeAction Action = getTypeAction(Node->getOperand(1).getValueType());
1157 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1158 if (Action == Legal && Tmp1 == Node->getOperand(0))
1160 if (Action == Legal) {
1161 Tmp2 = Node->getOperand(1);
1162 Tmp3 = Node->getOperand(2);
1163 Tmp4 = Node->getOperand(3);
1165 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the line #.
1166 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the col #.
1167 Tmp4 = LegalizeOp(Node->getOperand(3)); // Legalize the source file id.
1169 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4);
1175 case ISD::DBG_LABEL:
1177 assert(Node->getNumOperands() == 1 && "Invalid LABEL node!");
1178 switch (TLI.getOperationAction(Node->getOpcode(), MVT::Other)) {
1179 default: assert(0 && "This action is not supported yet!");
1180 case TargetLowering::Legal:
1181 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1182 Result = DAG.UpdateNodeOperands(Result, Tmp1);
1184 case TargetLowering::Expand:
1185 Result = LegalizeOp(Node->getOperand(0));
1191 assert(Node->getNumOperands() == 4 && "Invalid Prefetch node!");
1192 switch (TLI.getOperationAction(ISD::PREFETCH, MVT::Other)) {
1193 default: assert(0 && "This action is not supported yet!");
1194 case TargetLowering::Legal:
1195 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1196 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the address.
1197 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the rw specifier.
1198 Tmp4 = LegalizeOp(Node->getOperand(3)); // Legalize locality specifier.
1199 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4);
1201 case TargetLowering::Expand:
1203 Result = LegalizeOp(Node->getOperand(0));
1208 case ISD::MEMBARRIER: {
1209 assert(Node->getNumOperands() == 6 && "Invalid MemBarrier node!");
1210 switch (TLI.getOperationAction(ISD::MEMBARRIER, MVT::Other)) {
1211 default: assert(0 && "This action is not supported yet!");
1212 case TargetLowering::Legal: {
1214 Ops[0] = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1215 for (int x = 1; x < 6; ++x) {
1216 Ops[x] = Node->getOperand(x);
1217 if (!isTypeLegal(Ops[x].getValueType()))
1218 Ops[x] = PromoteOp(Ops[x]);
1220 Result = DAG.UpdateNodeOperands(Result, &Ops[0], 6);
1223 case TargetLowering::Expand:
1224 //There is no libgcc call for this op
1225 Result = Node->getOperand(0); // Noop
1231 case ISD::ATOMIC_CMP_SWAP: {
1232 unsigned int num_operands = 4;
1233 assert(Node->getNumOperands() == num_operands && "Invalid Atomic node!");
1235 for (unsigned int x = 0; x < num_operands; ++x)
1236 Ops[x] = LegalizeOp(Node->getOperand(x));
1237 Result = DAG.UpdateNodeOperands(Result, &Ops[0], num_operands);
1239 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
1240 default: assert(0 && "This action is not supported yet!");
1241 case TargetLowering::Custom:
1242 Result = TLI.LowerOperation(Result, DAG);
1244 case TargetLowering::Legal:
1247 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
1248 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
1249 return Result.getValue(Op.ResNo);
1251 case ISD::ATOMIC_LOAD_ADD:
1252 case ISD::ATOMIC_LOAD_SUB:
1253 case ISD::ATOMIC_LOAD_AND:
1254 case ISD::ATOMIC_LOAD_OR:
1255 case ISD::ATOMIC_LOAD_XOR:
1256 case ISD::ATOMIC_LOAD_NAND:
1257 case ISD::ATOMIC_LOAD_MIN:
1258 case ISD::ATOMIC_LOAD_MAX:
1259 case ISD::ATOMIC_LOAD_UMIN:
1260 case ISD::ATOMIC_LOAD_UMAX:
1261 case ISD::ATOMIC_SWAP: {
1262 unsigned int num_operands = 3;
1263 assert(Node->getNumOperands() == num_operands && "Invalid Atomic node!");
1265 for (unsigned int x = 0; x < num_operands; ++x)
1266 Ops[x] = LegalizeOp(Node->getOperand(x));
1267 Result = DAG.UpdateNodeOperands(Result, &Ops[0], num_operands);
1269 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
1270 default: assert(0 && "This action is not supported yet!");
1271 case TargetLowering::Custom:
1272 Result = TLI.LowerOperation(Result, DAG);
1274 case TargetLowering::Expand:
1275 Result = SDOperand(TLI.ReplaceNodeResults(Op.Val, DAG),0);
1277 case TargetLowering::Legal:
1280 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
1281 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
1282 return Result.getValue(Op.ResNo);
1284 case ISD::Constant: {
1285 ConstantSDNode *CN = cast<ConstantSDNode>(Node);
1287 TLI.getOperationAction(ISD::Constant, CN->getValueType(0));
1289 // We know we don't need to expand constants here, constants only have one
1290 // value and we check that it is fine above.
1292 if (opAction == TargetLowering::Custom) {
1293 Tmp1 = TLI.LowerOperation(Result, DAG);
1299 case ISD::ConstantFP: {
1300 // Spill FP immediates to the constant pool if the target cannot directly
1301 // codegen them. Targets often have some immediate values that can be
1302 // efficiently generated into an FP register without a load. We explicitly
1303 // leave these constants as ConstantFP nodes for the target to deal with.
1304 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node);
1306 switch (TLI.getOperationAction(ISD::ConstantFP, CFP->getValueType(0))) {
1307 default: assert(0 && "This action is not supported yet!");
1308 case TargetLowering::Legal:
1310 case TargetLowering::Custom:
1311 Tmp3 = TLI.LowerOperation(Result, DAG);
1317 case TargetLowering::Expand: {
1318 // Check to see if this FP immediate is already legal.
1319 bool isLegal = false;
1320 for (TargetLowering::legal_fpimm_iterator I = TLI.legal_fpimm_begin(),
1321 E = TLI.legal_fpimm_end(); I != E; ++I) {
1322 if (CFP->isExactlyValue(*I)) {
1327 // If this is a legal constant, turn it into a TargetConstantFP node.
1330 Result = ExpandConstantFP(CFP, true, DAG, TLI);
1335 case ISD::TokenFactor:
1336 if (Node->getNumOperands() == 2) {
1337 Tmp1 = LegalizeOp(Node->getOperand(0));
1338 Tmp2 = LegalizeOp(Node->getOperand(1));
1339 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1340 } else if (Node->getNumOperands() == 3) {
1341 Tmp1 = LegalizeOp(Node->getOperand(0));
1342 Tmp2 = LegalizeOp(Node->getOperand(1));
1343 Tmp3 = LegalizeOp(Node->getOperand(2));
1344 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1346 SmallVector<SDOperand, 8> Ops;
1347 // Legalize the operands.
1348 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
1349 Ops.push_back(LegalizeOp(Node->getOperand(i)));
1350 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1354 case ISD::FORMAL_ARGUMENTS:
1356 // The only option for this is to custom lower it.
1357 Tmp3 = TLI.LowerOperation(Result.getValue(0), DAG);
1358 assert(Tmp3.Val && "Target didn't custom lower this node!");
1359 // A call within a calling sequence must be legalized to something
1360 // other than the normal CALLSEQ_END. Violating this gets Legalize
1361 // into an infinite loop.
1362 assert ((!IsLegalizingCall ||
1363 Node->getOpcode() != ISD::CALL ||
1364 Tmp3.Val->getOpcode() != ISD::CALLSEQ_END) &&
1365 "Nested CALLSEQ_START..CALLSEQ_END not supported.");
1367 // The number of incoming and outgoing values should match; unless the final
1368 // outgoing value is a flag.
1369 assert((Tmp3.Val->getNumValues() == Result.Val->getNumValues() ||
1370 (Tmp3.Val->getNumValues() == Result.Val->getNumValues() + 1 &&
1371 Tmp3.Val->getValueType(Tmp3.Val->getNumValues() - 1) ==
1373 "Lowering call/formal_arguments produced unexpected # results!");
1375 // Since CALL/FORMAL_ARGUMENTS nodes produce multiple values, make sure to
1376 // remember that we legalized all of them, so it doesn't get relegalized.
1377 for (unsigned i = 0, e = Tmp3.Val->getNumValues(); i != e; ++i) {
1378 if (Tmp3.Val->getValueType(i) == MVT::Flag)
1380 Tmp1 = LegalizeOp(Tmp3.getValue(i));
1383 AddLegalizedOperand(SDOperand(Node, i), Tmp1);
1386 case ISD::EXTRACT_SUBREG: {
1387 Tmp1 = LegalizeOp(Node->getOperand(0));
1388 ConstantSDNode *idx = dyn_cast<ConstantSDNode>(Node->getOperand(1));
1389 assert(idx && "Operand must be a constant");
1390 Tmp2 = DAG.getTargetConstant(idx->getValue(), idx->getValueType(0));
1391 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1394 case ISD::INSERT_SUBREG: {
1395 Tmp1 = LegalizeOp(Node->getOperand(0));
1396 Tmp2 = LegalizeOp(Node->getOperand(1));
1397 ConstantSDNode *idx = dyn_cast<ConstantSDNode>(Node->getOperand(2));
1398 assert(idx && "Operand must be a constant");
1399 Tmp3 = DAG.getTargetConstant(idx->getValue(), idx->getValueType(0));
1400 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1403 case ISD::BUILD_VECTOR:
1404 switch (TLI.getOperationAction(ISD::BUILD_VECTOR, Node->getValueType(0))) {
1405 default: assert(0 && "This action is not supported yet!");
1406 case TargetLowering::Custom:
1407 Tmp3 = TLI.LowerOperation(Result, DAG);
1413 case TargetLowering::Expand:
1414 Result = ExpandBUILD_VECTOR(Result.Val);
1418 case ISD::INSERT_VECTOR_ELT:
1419 Tmp1 = LegalizeOp(Node->getOperand(0)); // InVec
1420 Tmp3 = LegalizeOp(Node->getOperand(2)); // InEltNo
1422 // The type of the value to insert may not be legal, even though the vector
1423 // type is legal. Legalize/Promote accordingly. We do not handle Expand
1425 switch (getTypeAction(Node->getOperand(1).getValueType())) {
1426 default: assert(0 && "Cannot expand insert element operand");
1427 case Legal: Tmp2 = LegalizeOp(Node->getOperand(1)); break;
1428 case Promote: Tmp2 = PromoteOp(Node->getOperand(1)); break;
1430 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1432 switch (TLI.getOperationAction(ISD::INSERT_VECTOR_ELT,
1433 Node->getValueType(0))) {
1434 default: assert(0 && "This action is not supported yet!");
1435 case TargetLowering::Legal:
1437 case TargetLowering::Custom:
1438 Tmp4 = TLI.LowerOperation(Result, DAG);
1444 case TargetLowering::Expand: {
1445 // If the insert index is a constant, codegen this as a scalar_to_vector,
1446 // then a shuffle that inserts it into the right position in the vector.
1447 if (ConstantSDNode *InsertPos = dyn_cast<ConstantSDNode>(Tmp3)) {
1448 // SCALAR_TO_VECTOR requires that the type of the value being inserted
1449 // match the element type of the vector being created.
1450 if (Tmp2.getValueType() ==
1451 Op.getValueType().getVectorElementType()) {
1452 SDOperand ScVec = DAG.getNode(ISD::SCALAR_TO_VECTOR,
1453 Tmp1.getValueType(), Tmp2);
1455 unsigned NumElts = Tmp1.getValueType().getVectorNumElements();
1457 MVT::getIntVectorWithNumElements(NumElts);
1458 MVT ShufMaskEltVT = ShufMaskVT.getVectorElementType();
1460 // We generate a shuffle of InVec and ScVec, so the shuffle mask
1461 // should be 0,1,2,3,4,5... with the appropriate element replaced with
1462 // elt 0 of the RHS.
1463 SmallVector<SDOperand, 8> ShufOps;
1464 for (unsigned i = 0; i != NumElts; ++i) {
1465 if (i != InsertPos->getValue())
1466 ShufOps.push_back(DAG.getConstant(i, ShufMaskEltVT));
1468 ShufOps.push_back(DAG.getConstant(NumElts, ShufMaskEltVT));
1470 SDOperand ShufMask = DAG.getNode(ISD::BUILD_VECTOR, ShufMaskVT,
1471 &ShufOps[0], ShufOps.size());
1473 Result = DAG.getNode(ISD::VECTOR_SHUFFLE, Tmp1.getValueType(),
1474 Tmp1, ScVec, ShufMask);
1475 Result = LegalizeOp(Result);
1479 Result = PerformInsertVectorEltInMemory(Tmp1, Tmp2, Tmp3);
1484 case ISD::SCALAR_TO_VECTOR:
1485 if (!TLI.isTypeLegal(Node->getOperand(0).getValueType())) {
1486 Result = LegalizeOp(ExpandSCALAR_TO_VECTOR(Node));
1490 Tmp1 = LegalizeOp(Node->getOperand(0)); // InVal
1491 Result = DAG.UpdateNodeOperands(Result, Tmp1);
1492 switch (TLI.getOperationAction(ISD::SCALAR_TO_VECTOR,
1493 Node->getValueType(0))) {
1494 default: assert(0 && "This action is not supported yet!");
1495 case TargetLowering::Legal:
1497 case TargetLowering::Custom:
1498 Tmp3 = TLI.LowerOperation(Result, DAG);
1504 case TargetLowering::Expand:
1505 Result = LegalizeOp(ExpandSCALAR_TO_VECTOR(Node));
1509 case ISD::VECTOR_SHUFFLE:
1510 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the input vectors,
1511 Tmp2 = LegalizeOp(Node->getOperand(1)); // but not the shuffle mask.
1512 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
1514 // Allow targets to custom lower the SHUFFLEs they support.
1515 switch (TLI.getOperationAction(ISD::VECTOR_SHUFFLE,Result.getValueType())) {
1516 default: assert(0 && "Unknown operation action!");
1517 case TargetLowering::Legal:
1518 assert(isShuffleLegal(Result.getValueType(), Node->getOperand(2)) &&
1519 "vector shuffle should not be created if not legal!");
1521 case TargetLowering::Custom:
1522 Tmp3 = TLI.LowerOperation(Result, DAG);
1528 case TargetLowering::Expand: {
1529 MVT VT = Node->getValueType(0);
1530 MVT EltVT = VT.getVectorElementType();
1531 MVT PtrVT = TLI.getPointerTy();
1532 SDOperand Mask = Node->getOperand(2);
1533 unsigned NumElems = Mask.getNumOperands();
1534 SmallVector<SDOperand,8> Ops;
1535 for (unsigned i = 0; i != NumElems; ++i) {
1536 SDOperand Arg = Mask.getOperand(i);
1537 if (Arg.getOpcode() == ISD::UNDEF) {
1538 Ops.push_back(DAG.getNode(ISD::UNDEF, EltVT));
1540 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
1541 unsigned Idx = cast<ConstantSDNode>(Arg)->getValue();
1543 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, Tmp1,
1544 DAG.getConstant(Idx, PtrVT)));
1546 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, Tmp2,
1547 DAG.getConstant(Idx - NumElems, PtrVT)));
1550 Result = DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size());
1553 case TargetLowering::Promote: {
1554 // Change base type to a different vector type.
1555 MVT OVT = Node->getValueType(0);
1556 MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
1558 // Cast the two input vectors.
1559 Tmp1 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp1);
1560 Tmp2 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp2);
1562 // Convert the shuffle mask to the right # elements.
1563 Tmp3 = SDOperand(isShuffleLegal(OVT, Node->getOperand(2)), 0);
1564 assert(Tmp3.Val && "Shuffle not legal?");
1565 Result = DAG.getNode(ISD::VECTOR_SHUFFLE, NVT, Tmp1, Tmp2, Tmp3);
1566 Result = DAG.getNode(ISD::BIT_CONVERT, OVT, Result);
1572 case ISD::EXTRACT_VECTOR_ELT:
1573 Tmp1 = Node->getOperand(0);
1574 Tmp2 = LegalizeOp(Node->getOperand(1));
1575 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1576 Result = ExpandEXTRACT_VECTOR_ELT(Result);
1579 case ISD::EXTRACT_SUBVECTOR:
1580 Tmp1 = Node->getOperand(0);
1581 Tmp2 = LegalizeOp(Node->getOperand(1));
1582 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1583 Result = ExpandEXTRACT_SUBVECTOR(Result);
1586 case ISD::CALLSEQ_START: {
1587 SDNode *CallEnd = FindCallEndFromCallStart(Node);
1589 // Recursively Legalize all of the inputs of the call end that do not lead
1590 // to this call start. This ensures that any libcalls that need be inserted
1591 // are inserted *before* the CALLSEQ_START.
1592 {SmallPtrSet<SDNode*, 32> NodesLeadingTo;
1593 for (unsigned i = 0, e = CallEnd->getNumOperands(); i != e; ++i)
1594 LegalizeAllNodesNotLeadingTo(CallEnd->getOperand(i).Val, Node,
1598 // Now that we legalized all of the inputs (which may have inserted
1599 // libcalls) create the new CALLSEQ_START node.
1600 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1602 // Merge in the last call, to ensure that this call start after the last
1604 if (LastCALLSEQ_END.getOpcode() != ISD::EntryToken) {
1605 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1606 Tmp1 = LegalizeOp(Tmp1);
1609 // Do not try to legalize the target-specific arguments (#1+).
1610 if (Tmp1 != Node->getOperand(0)) {
1611 SmallVector<SDOperand, 8> Ops(Node->op_begin(), Node->op_end());
1613 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1616 // Remember that the CALLSEQ_START is legalized.
1617 AddLegalizedOperand(Op.getValue(0), Result);
1618 if (Node->getNumValues() == 2) // If this has a flag result, remember it.
1619 AddLegalizedOperand(Op.getValue(1), Result.getValue(1));
1621 // Now that the callseq_start and all of the non-call nodes above this call
1622 // sequence have been legalized, legalize the call itself. During this
1623 // process, no libcalls can/will be inserted, guaranteeing that no calls
1625 assert(!IsLegalizingCall && "Inconsistent sequentialization of calls!");
1626 // Note that we are selecting this call!
1627 LastCALLSEQ_END = SDOperand(CallEnd, 0);
1628 IsLegalizingCall = true;
1630 // Legalize the call, starting from the CALLSEQ_END.
1631 LegalizeOp(LastCALLSEQ_END);
1632 assert(!IsLegalizingCall && "CALLSEQ_END should have cleared this!");
1635 case ISD::CALLSEQ_END:
1636 // If the CALLSEQ_START node hasn't been legalized first, legalize it. This
1637 // will cause this node to be legalized as well as handling libcalls right.
1638 if (LastCALLSEQ_END.Val != Node) {
1639 LegalizeOp(SDOperand(FindCallStartFromCallEnd(Node), 0));
1640 DenseMap<SDOperand, SDOperand>::iterator I = LegalizedNodes.find(Op);
1641 assert(I != LegalizedNodes.end() &&
1642 "Legalizing the call start should have legalized this node!");
1646 // Otherwise, the call start has been legalized and everything is going
1647 // according to plan. Just legalize ourselves normally here.
1648 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1649 // Do not try to legalize the target-specific arguments (#1+), except for
1650 // an optional flag input.
1651 if (Node->getOperand(Node->getNumOperands()-1).getValueType() != MVT::Flag){
1652 if (Tmp1 != Node->getOperand(0)) {
1653 SmallVector<SDOperand, 8> Ops(Node->op_begin(), Node->op_end());
1655 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1658 Tmp2 = LegalizeOp(Node->getOperand(Node->getNumOperands()-1));
1659 if (Tmp1 != Node->getOperand(0) ||
1660 Tmp2 != Node->getOperand(Node->getNumOperands()-1)) {
1661 SmallVector<SDOperand, 8> Ops(Node->op_begin(), Node->op_end());
1664 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1667 assert(IsLegalizingCall && "Call sequence imbalance between start/end?");
1668 // This finishes up call legalization.
1669 IsLegalizingCall = false;
1671 // If the CALLSEQ_END node has a flag, remember that we legalized it.
1672 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
1673 if (Node->getNumValues() == 2)
1674 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
1675 return Result.getValue(Op.ResNo);
1676 case ISD::DYNAMIC_STACKALLOC: {
1677 MVT VT = Node->getValueType(0);
1678 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1679 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the size.
1680 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the alignment.
1681 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1683 Tmp1 = Result.getValue(0);
1684 Tmp2 = Result.getValue(1);
1685 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
1686 default: assert(0 && "This action is not supported yet!");
1687 case TargetLowering::Expand: {
1688 unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore();
1689 assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and"
1690 " not tell us which reg is the stack pointer!");
1691 SDOperand Chain = Tmp1.getOperand(0);
1693 // Chain the dynamic stack allocation so that it doesn't modify the stack
1694 // pointer when other instructions are using the stack.
1695 Chain = DAG.getCALLSEQ_START(Chain,
1696 DAG.getConstant(0, TLI.getPointerTy()));
1698 SDOperand Size = Tmp2.getOperand(1);
1699 SDOperand SP = DAG.getCopyFromReg(Chain, SPReg, VT);
1700 Chain = SP.getValue(1);
1701 unsigned Align = cast<ConstantSDNode>(Tmp3)->getValue();
1702 unsigned StackAlign =
1703 TLI.getTargetMachine().getFrameInfo()->getStackAlignment();
1704 if (Align > StackAlign)
1705 SP = DAG.getNode(ISD::AND, VT, SP,
1706 DAG.getConstant(-(uint64_t)Align, VT));
1707 Tmp1 = DAG.getNode(ISD::SUB, VT, SP, Size); // Value
1708 Chain = DAG.getCopyToReg(Chain, SPReg, Tmp1); // Output chain
1711 DAG.getCALLSEQ_END(Chain,
1712 DAG.getConstant(0, TLI.getPointerTy()),
1713 DAG.getConstant(0, TLI.getPointerTy()),
1716 Tmp1 = LegalizeOp(Tmp1);
1717 Tmp2 = LegalizeOp(Tmp2);
1720 case TargetLowering::Custom:
1721 Tmp3 = TLI.LowerOperation(Tmp1, DAG);
1723 Tmp1 = LegalizeOp(Tmp3);
1724 Tmp2 = LegalizeOp(Tmp3.getValue(1));
1727 case TargetLowering::Legal:
1730 // Since this op produce two values, make sure to remember that we
1731 // legalized both of them.
1732 AddLegalizedOperand(SDOperand(Node, 0), Tmp1);
1733 AddLegalizedOperand(SDOperand(Node, 1), Tmp2);
1734 return Op.ResNo ? Tmp2 : Tmp1;
1736 case ISD::INLINEASM: {
1737 SmallVector<SDOperand, 8> Ops(Node->op_begin(), Node->op_end());
1738 bool Changed = false;
1739 // Legalize all of the operands of the inline asm, in case they are nodes
1740 // that need to be expanded or something. Note we skip the asm string and
1741 // all of the TargetConstant flags.
1742 SDOperand Op = LegalizeOp(Ops[0]);
1743 Changed = Op != Ops[0];
1746 bool HasInFlag = Ops.back().getValueType() == MVT::Flag;
1747 for (unsigned i = 2, e = Ops.size()-HasInFlag; i < e; ) {
1748 unsigned NumVals = cast<ConstantSDNode>(Ops[i])->getValue() >> 3;
1749 for (++i; NumVals; ++i, --NumVals) {
1750 SDOperand Op = LegalizeOp(Ops[i]);
1759 Op = LegalizeOp(Ops.back());
1760 Changed |= Op != Ops.back();
1765 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1767 // INLINE asm returns a chain and flag, make sure to add both to the map.
1768 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
1769 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
1770 return Result.getValue(Op.ResNo);
1773 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1774 // Ensure that libcalls are emitted before a branch.
1775 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1776 Tmp1 = LegalizeOp(Tmp1);
1777 LastCALLSEQ_END = DAG.getEntryNode();
1779 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
1782 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1783 // Ensure that libcalls are emitted before a branch.
1784 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1785 Tmp1 = LegalizeOp(Tmp1);
1786 LastCALLSEQ_END = DAG.getEntryNode();
1788 switch (getTypeAction(Node->getOperand(1).getValueType())) {
1789 default: assert(0 && "Indirect target must be legal type (pointer)!");
1791 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the condition.
1794 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1797 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1798 // Ensure that libcalls are emitted before a branch.
1799 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1800 Tmp1 = LegalizeOp(Tmp1);
1801 LastCALLSEQ_END = DAG.getEntryNode();
1803 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the jumptable node.
1804 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
1806 switch (TLI.getOperationAction(ISD::BR_JT, MVT::Other)) {
1807 default: assert(0 && "This action is not supported yet!");
1808 case TargetLowering::Legal: break;
1809 case TargetLowering::Custom:
1810 Tmp1 = TLI.LowerOperation(Result, DAG);
1811 if (Tmp1.Val) Result = Tmp1;
1813 case TargetLowering::Expand: {
1814 SDOperand Chain = Result.getOperand(0);
1815 SDOperand Table = Result.getOperand(1);
1816 SDOperand Index = Result.getOperand(2);
1818 MVT PTy = TLI.getPointerTy();
1819 MachineFunction &MF = DAG.getMachineFunction();
1820 unsigned EntrySize = MF.getJumpTableInfo()->getEntrySize();
1821 Index= DAG.getNode(ISD::MUL, PTy, Index, DAG.getConstant(EntrySize, PTy));
1822 SDOperand Addr = DAG.getNode(ISD::ADD, PTy, Index, Table);
1825 switch (EntrySize) {
1826 default: assert(0 && "Size of jump table not supported yet."); break;
1827 case 4: LD = DAG.getLoad(MVT::i32, Chain, Addr,
1828 PseudoSourceValue::getJumpTable(), 0); break;
1829 case 8: LD = DAG.getLoad(MVT::i64, Chain, Addr,
1830 PseudoSourceValue::getJumpTable(), 0); break;
1834 if (TLI.getTargetMachine().getRelocationModel() == Reloc::PIC_) {
1835 // For PIC, the sequence is:
1836 // BRIND(load(Jumptable + index) + RelocBase)
1837 // RelocBase can be JumpTable, GOT or some sort of global base.
1838 if (PTy != MVT::i32)
1839 Addr = DAG.getNode(ISD::SIGN_EXTEND, PTy, Addr);
1840 Addr = DAG.getNode(ISD::ADD, PTy, Addr,
1841 TLI.getPICJumpTableRelocBase(Table, DAG));
1843 Result = DAG.getNode(ISD::BRIND, MVT::Other, LD.getValue(1), Addr);
1848 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1849 // Ensure that libcalls are emitted before a return.
1850 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1851 Tmp1 = LegalizeOp(Tmp1);
1852 LastCALLSEQ_END = DAG.getEntryNode();
1854 switch (getTypeAction(Node->getOperand(1).getValueType())) {
1855 case Expand: assert(0 && "It's impossible to expand bools");
1857 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the condition.
1860 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the condition.
1862 // The top bits of the promoted condition are not necessarily zero, ensure
1863 // that the value is properly zero extended.
1864 unsigned BitWidth = Tmp2.getValueSizeInBits();
1865 if (!DAG.MaskedValueIsZero(Tmp2,
1866 APInt::getHighBitsSet(BitWidth, BitWidth-1)))
1867 Tmp2 = DAG.getZeroExtendInReg(Tmp2, MVT::i1);
1872 // Basic block destination (Op#2) is always legal.
1873 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
1875 switch (TLI.getOperationAction(ISD::BRCOND, MVT::Other)) {
1876 default: assert(0 && "This action is not supported yet!");
1877 case TargetLowering::Legal: break;
1878 case TargetLowering::Custom:
1879 Tmp1 = TLI.LowerOperation(Result, DAG);
1880 if (Tmp1.Val) Result = Tmp1;
1882 case TargetLowering::Expand:
1883 // Expand brcond's setcc into its constituent parts and create a BR_CC
1885 if (Tmp2.getOpcode() == ISD::SETCC) {
1886 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1, Tmp2.getOperand(2),
1887 Tmp2.getOperand(0), Tmp2.getOperand(1),
1888 Node->getOperand(2));
1890 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1,
1891 DAG.getCondCode(ISD::SETNE), Tmp2,
1892 DAG.getConstant(0, Tmp2.getValueType()),
1893 Node->getOperand(2));
1899 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1900 // Ensure that libcalls are emitted before a branch.
1901 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1902 Tmp1 = LegalizeOp(Tmp1);
1903 Tmp2 = Node->getOperand(2); // LHS
1904 Tmp3 = Node->getOperand(3); // RHS
1905 Tmp4 = Node->getOperand(1); // CC
1907 LegalizeSetCCOperands(Tmp2, Tmp3, Tmp4);
1908 LastCALLSEQ_END = DAG.getEntryNode();
1910 // If we didn't get both a LHS and RHS back from LegalizeSetCCOperands,
1911 // the LHS is a legal SETCC itself. In this case, we need to compare
1912 // the result against zero to select between true and false values.
1913 if (Tmp3.Val == 0) {
1914 Tmp3 = DAG.getConstant(0, Tmp2.getValueType());
1915 Tmp4 = DAG.getCondCode(ISD::SETNE);
1918 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp4, Tmp2, Tmp3,
1919 Node->getOperand(4));
1921 switch (TLI.getOperationAction(ISD::BR_CC, Tmp3.getValueType())) {
1922 default: assert(0 && "Unexpected action for BR_CC!");
1923 case TargetLowering::Legal: break;
1924 case TargetLowering::Custom:
1925 Tmp4 = TLI.LowerOperation(Result, DAG);
1926 if (Tmp4.Val) Result = Tmp4;
1931 LoadSDNode *LD = cast<LoadSDNode>(Node);
1932 Tmp1 = LegalizeOp(LD->getChain()); // Legalize the chain.
1933 Tmp2 = LegalizeOp(LD->getBasePtr()); // Legalize the base pointer.
1935 ISD::LoadExtType ExtType = LD->getExtensionType();
1936 if (ExtType == ISD::NON_EXTLOAD) {
1937 MVT VT = Node->getValueType(0);
1938 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, LD->getOffset());
1939 Tmp3 = Result.getValue(0);
1940 Tmp4 = Result.getValue(1);
1942 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
1943 default: assert(0 && "This action is not supported yet!");
1944 case TargetLowering::Legal:
1945 // If this is an unaligned load and the target doesn't support it,
1947 if (!TLI.allowsUnalignedMemoryAccesses()) {
1948 unsigned ABIAlignment = TLI.getTargetData()->
1949 getABITypeAlignment(LD->getMemoryVT().getTypeForMVT());
1950 if (LD->getAlignment() < ABIAlignment){
1951 Result = ExpandUnalignedLoad(cast<LoadSDNode>(Result.Val), DAG,
1953 Tmp3 = Result.getOperand(0);
1954 Tmp4 = Result.getOperand(1);
1955 Tmp3 = LegalizeOp(Tmp3);
1956 Tmp4 = LegalizeOp(Tmp4);
1960 case TargetLowering::Custom:
1961 Tmp1 = TLI.LowerOperation(Tmp3, DAG);
1963 Tmp3 = LegalizeOp(Tmp1);
1964 Tmp4 = LegalizeOp(Tmp1.getValue(1));
1967 case TargetLowering::Promote: {
1968 // Only promote a load of vector type to another.
1969 assert(VT.isVector() && "Cannot promote this load!");
1970 // Change base type to a different vector type.
1971 MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), VT);
1973 Tmp1 = DAG.getLoad(NVT, Tmp1, Tmp2, LD->getSrcValue(),
1974 LD->getSrcValueOffset(),
1975 LD->isVolatile(), LD->getAlignment());
1976 Tmp3 = LegalizeOp(DAG.getNode(ISD::BIT_CONVERT, VT, Tmp1));
1977 Tmp4 = LegalizeOp(Tmp1.getValue(1));
1981 // Since loads produce two values, make sure to remember that we
1982 // legalized both of them.
1983 AddLegalizedOperand(SDOperand(Node, 0), Tmp3);
1984 AddLegalizedOperand(SDOperand(Node, 1), Tmp4);
1985 return Op.ResNo ? Tmp4 : Tmp3;
1987 MVT SrcVT = LD->getMemoryVT();
1988 unsigned SrcWidth = SrcVT.getSizeInBits();
1989 int SVOffset = LD->getSrcValueOffset();
1990 unsigned Alignment = LD->getAlignment();
1991 bool isVolatile = LD->isVolatile();
1993 if (SrcWidth != SrcVT.getStoreSizeInBits() &&
1994 // Some targets pretend to have an i1 loading operation, and actually
1995 // load an i8. This trick is correct for ZEXTLOAD because the top 7
1996 // bits are guaranteed to be zero; it helps the optimizers understand
1997 // that these bits are zero. It is also useful for EXTLOAD, since it
1998 // tells the optimizers that those bits are undefined. It would be
1999 // nice to have an effective generic way of getting these benefits...
2000 // Until such a way is found, don't insist on promoting i1 here.
2001 (SrcVT != MVT::i1 ||
2002 TLI.getLoadXAction(ExtType, MVT::i1) == TargetLowering::Promote)) {
2003 // Promote to a byte-sized load if not loading an integral number of
2004 // bytes. For example, promote EXTLOAD:i20 -> EXTLOAD:i24.
2005 unsigned NewWidth = SrcVT.getStoreSizeInBits();
2006 MVT NVT = MVT::getIntegerVT(NewWidth);
2009 // The extra bits are guaranteed to be zero, since we stored them that
2010 // way. A zext load from NVT thus automatically gives zext from SrcVT.
2012 ISD::LoadExtType NewExtType =
2013 ExtType == ISD::ZEXTLOAD ? ISD::ZEXTLOAD : ISD::EXTLOAD;
2015 Result = DAG.getExtLoad(NewExtType, Node->getValueType(0),
2016 Tmp1, Tmp2, LD->getSrcValue(), SVOffset,
2017 NVT, isVolatile, Alignment);
2019 Ch = Result.getValue(1); // The chain.
2021 if (ExtType == ISD::SEXTLOAD)
2022 // Having the top bits zero doesn't help when sign extending.
2023 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(),
2024 Result, DAG.getValueType(SrcVT));
2025 else if (ExtType == ISD::ZEXTLOAD || NVT == Result.getValueType())
2026 // All the top bits are guaranteed to be zero - inform the optimizers.
2027 Result = DAG.getNode(ISD::AssertZext, Result.getValueType(), Result,
2028 DAG.getValueType(SrcVT));
2030 Tmp1 = LegalizeOp(Result);
2031 Tmp2 = LegalizeOp(Ch);
2032 } else if (SrcWidth & (SrcWidth - 1)) {
2033 // If not loading a power-of-2 number of bits, expand as two loads.
2034 assert(SrcVT.isExtended() && !SrcVT.isVector() &&
2035 "Unsupported extload!");
2036 unsigned RoundWidth = 1 << Log2_32(SrcWidth);
2037 assert(RoundWidth < SrcWidth);
2038 unsigned ExtraWidth = SrcWidth - RoundWidth;
2039 assert(ExtraWidth < RoundWidth);
2040 assert(!(RoundWidth % 8) && !(ExtraWidth % 8) &&
2041 "Load size not an integral number of bytes!");
2042 MVT RoundVT = MVT::getIntegerVT(RoundWidth);
2043 MVT ExtraVT = MVT::getIntegerVT(ExtraWidth);
2044 SDOperand Lo, Hi, Ch;
2045 unsigned IncrementSize;
2047 if (TLI.isLittleEndian()) {
2048 // EXTLOAD:i24 -> ZEXTLOAD:i16 | (shl EXTLOAD@+2:i8, 16)
2049 // Load the bottom RoundWidth bits.
2050 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, Node->getValueType(0), Tmp1, Tmp2,
2051 LD->getSrcValue(), SVOffset, RoundVT, isVolatile,
2054 // Load the remaining ExtraWidth bits.
2055 IncrementSize = RoundWidth / 8;
2056 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2,
2057 DAG.getIntPtrConstant(IncrementSize));
2058 Hi = DAG.getExtLoad(ExtType, Node->getValueType(0), Tmp1, Tmp2,
2059 LD->getSrcValue(), SVOffset + IncrementSize,
2060 ExtraVT, isVolatile,
2061 MinAlign(Alignment, IncrementSize));
2063 // Build a factor node to remember that this load is independent of the
2065 Ch = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
2068 // Move the top bits to the right place.
2069 Hi = DAG.getNode(ISD::SHL, Hi.getValueType(), Hi,
2070 DAG.getConstant(RoundWidth, TLI.getShiftAmountTy()));
2072 // Join the hi and lo parts.
2073 Result = DAG.getNode(ISD::OR, Node->getValueType(0), Lo, Hi);
2075 // Big endian - avoid unaligned loads.
2076 // EXTLOAD:i24 -> (shl EXTLOAD:i16, 8) | ZEXTLOAD@+2:i8
2077 // Load the top RoundWidth bits.
2078 Hi = DAG.getExtLoad(ExtType, Node->getValueType(0), Tmp1, Tmp2,
2079 LD->getSrcValue(), SVOffset, RoundVT, isVolatile,
2082 // Load the remaining ExtraWidth bits.
2083 IncrementSize = RoundWidth / 8;
2084 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2,
2085 DAG.getIntPtrConstant(IncrementSize));
2086 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, Node->getValueType(0), Tmp1, Tmp2,
2087 LD->getSrcValue(), SVOffset + IncrementSize,
2088 ExtraVT, isVolatile,
2089 MinAlign(Alignment, IncrementSize));
2091 // Build a factor node to remember that this load is independent of the
2093 Ch = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
2096 // Move the top bits to the right place.
2097 Hi = DAG.getNode(ISD::SHL, Hi.getValueType(), Hi,
2098 DAG.getConstant(ExtraWidth, TLI.getShiftAmountTy()));
2100 // Join the hi and lo parts.
2101 Result = DAG.getNode(ISD::OR, Node->getValueType(0), Lo, Hi);
2104 Tmp1 = LegalizeOp(Result);
2105 Tmp2 = LegalizeOp(Ch);
2107 switch (TLI.getLoadXAction(ExtType, SrcVT)) {
2108 default: assert(0 && "This action is not supported yet!");
2109 case TargetLowering::Custom:
2112 case TargetLowering::Legal:
2113 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, LD->getOffset());
2114 Tmp1 = Result.getValue(0);
2115 Tmp2 = Result.getValue(1);
2118 Tmp3 = TLI.LowerOperation(Result, DAG);
2120 Tmp1 = LegalizeOp(Tmp3);
2121 Tmp2 = LegalizeOp(Tmp3.getValue(1));
2124 // If this is an unaligned load and the target doesn't support it,
2126 if (!TLI.allowsUnalignedMemoryAccesses()) {
2127 unsigned ABIAlignment = TLI.getTargetData()->
2128 getABITypeAlignment(LD->getMemoryVT().getTypeForMVT());
2129 if (LD->getAlignment() < ABIAlignment){
2130 Result = ExpandUnalignedLoad(cast<LoadSDNode>(Result.Val), DAG,
2132 Tmp1 = Result.getOperand(0);
2133 Tmp2 = Result.getOperand(1);
2134 Tmp1 = LegalizeOp(Tmp1);
2135 Tmp2 = LegalizeOp(Tmp2);
2140 case TargetLowering::Expand:
2141 // f64 = EXTLOAD f32 should expand to LOAD, FP_EXTEND
2142 if (SrcVT == MVT::f32 && Node->getValueType(0) == MVT::f64) {
2143 SDOperand Load = DAG.getLoad(SrcVT, Tmp1, Tmp2, LD->getSrcValue(),
2144 LD->getSrcValueOffset(),
2145 LD->isVolatile(), LD->getAlignment());
2146 Result = DAG.getNode(ISD::FP_EXTEND, Node->getValueType(0), Load);
2147 Tmp1 = LegalizeOp(Result); // Relegalize new nodes.
2148 Tmp2 = LegalizeOp(Load.getValue(1));
2151 assert(ExtType != ISD::EXTLOAD &&"EXTLOAD should always be supported!");
2152 // Turn the unsupported load into an EXTLOAD followed by an explicit
2153 // zero/sign extend inreg.
2154 Result = DAG.getExtLoad(ISD::EXTLOAD, Node->getValueType(0),
2155 Tmp1, Tmp2, LD->getSrcValue(),
2156 LD->getSrcValueOffset(), SrcVT,
2157 LD->isVolatile(), LD->getAlignment());
2159 if (ExtType == ISD::SEXTLOAD)
2160 ValRes = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(),
2161 Result, DAG.getValueType(SrcVT));
2163 ValRes = DAG.getZeroExtendInReg(Result, SrcVT);
2164 Tmp1 = LegalizeOp(ValRes); // Relegalize new nodes.
2165 Tmp2 = LegalizeOp(Result.getValue(1)); // Relegalize new nodes.
2170 // Since loads produce two values, make sure to remember that we legalized
2172 AddLegalizedOperand(SDOperand(Node, 0), Tmp1);
2173 AddLegalizedOperand(SDOperand(Node, 1), Tmp2);
2174 return Op.ResNo ? Tmp2 : Tmp1;
2177 case ISD::EXTRACT_ELEMENT: {
2178 MVT OpTy = Node->getOperand(0).getValueType();
2179 switch (getTypeAction(OpTy)) {
2180 default: assert(0 && "EXTRACT_ELEMENT action for type unimplemented!");
2182 if (cast<ConstantSDNode>(Node->getOperand(1))->getValue()) {
2184 Result = DAG.getNode(ISD::SRL, OpTy, Node->getOperand(0),
2185 DAG.getConstant(OpTy.getSizeInBits()/2,
2186 TLI.getShiftAmountTy()));
2187 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), Result);
2190 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0),
2191 Node->getOperand(0));
2195 // Get both the low and high parts.
2196 ExpandOp(Node->getOperand(0), Tmp1, Tmp2);
2197 if (cast<ConstantSDNode>(Node->getOperand(1))->getValue())
2198 Result = Tmp2; // 1 -> Hi
2200 Result = Tmp1; // 0 -> Lo
2206 case ISD::CopyToReg:
2207 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2209 assert(isTypeLegal(Node->getOperand(2).getValueType()) &&
2210 "Register type must be legal!");
2211 // Legalize the incoming value (must be a legal type).
2212 Tmp2 = LegalizeOp(Node->getOperand(2));
2213 if (Node->getNumValues() == 1) {
2214 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1), Tmp2);
2216 assert(Node->getNumValues() == 2 && "Unknown CopyToReg");
2217 if (Node->getNumOperands() == 4) {
2218 Tmp3 = LegalizeOp(Node->getOperand(3));
2219 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1), Tmp2,
2222 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1),Tmp2);
2225 // Since this produces two values, make sure to remember that we legalized
2227 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
2228 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
2234 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2236 // Ensure that libcalls are emitted before a return.
2237 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
2238 Tmp1 = LegalizeOp(Tmp1);
2239 LastCALLSEQ_END = DAG.getEntryNode();
2241 switch (Node->getNumOperands()) {
2243 Tmp2 = Node->getOperand(1);
2244 Tmp3 = Node->getOperand(2); // Signness
2245 switch (getTypeAction(Tmp2.getValueType())) {
2247 Result = DAG.UpdateNodeOperands(Result, Tmp1, LegalizeOp(Tmp2), Tmp3);
2250 if (!Tmp2.getValueType().isVector()) {
2252 ExpandOp(Tmp2, Lo, Hi);
2254 // Big endian systems want the hi reg first.
2255 if (TLI.isBigEndian())
2259 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Tmp3, Hi,Tmp3);
2261 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Tmp3);
2262 Result = LegalizeOp(Result);
2264 SDNode *InVal = Tmp2.Val;
2265 int InIx = Tmp2.ResNo;
2266 unsigned NumElems = InVal->getValueType(InIx).getVectorNumElements();
2267 MVT EVT = InVal->getValueType(InIx).getVectorElementType();
2269 // Figure out if there is a simple type corresponding to this Vector
2270 // type. If so, convert to the vector type.
2271 MVT TVT = MVT::getVectorVT(EVT, NumElems);
2272 if (TLI.isTypeLegal(TVT)) {
2273 // Turn this into a return of the vector type.
2274 Tmp2 = LegalizeOp(Tmp2);
2275 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2276 } else if (NumElems == 1) {
2277 // Turn this into a return of the scalar type.
2278 Tmp2 = ScalarizeVectorOp(Tmp2);
2279 Tmp2 = LegalizeOp(Tmp2);
2280 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2282 // FIXME: Returns of gcc generic vectors smaller than a legal type
2283 // should be returned in integer registers!
2285 // The scalarized value type may not be legal, e.g. it might require
2286 // promotion or expansion. Relegalize the return.
2287 Result = LegalizeOp(Result);
2289 // FIXME: Returns of gcc generic vectors larger than a legal vector
2290 // type should be returned by reference!
2292 SplitVectorOp(Tmp2, Lo, Hi);
2293 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Tmp3, Hi,Tmp3);
2294 Result = LegalizeOp(Result);
2299 Tmp2 = PromoteOp(Node->getOperand(1));
2300 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2301 Result = LegalizeOp(Result);
2306 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2308 default: { // ret <values>
2309 SmallVector<SDOperand, 8> NewValues;
2310 NewValues.push_back(Tmp1);
2311 for (unsigned i = 1, e = Node->getNumOperands(); i < e; i += 2)
2312 switch (getTypeAction(Node->getOperand(i).getValueType())) {
2314 NewValues.push_back(LegalizeOp(Node->getOperand(i)));
2315 NewValues.push_back(Node->getOperand(i+1));
2319 assert(!Node->getOperand(i).getValueType().isExtended() &&
2320 "FIXME: TODO: implement returning non-legal vector types!");
2321 ExpandOp(Node->getOperand(i), Lo, Hi);
2322 NewValues.push_back(Lo);
2323 NewValues.push_back(Node->getOperand(i+1));
2325 NewValues.push_back(Hi);
2326 NewValues.push_back(Node->getOperand(i+1));
2331 assert(0 && "Can't promote multiple return value yet!");
2334 if (NewValues.size() == Node->getNumOperands())
2335 Result = DAG.UpdateNodeOperands(Result, &NewValues[0],NewValues.size());
2337 Result = DAG.getNode(ISD::RET, MVT::Other,
2338 &NewValues[0], NewValues.size());
2343 if (Result.getOpcode() == ISD::RET) {
2344 switch (TLI.getOperationAction(Result.getOpcode(), MVT::Other)) {
2345 default: assert(0 && "This action is not supported yet!");
2346 case TargetLowering::Legal: break;
2347 case TargetLowering::Custom:
2348 Tmp1 = TLI.LowerOperation(Result, DAG);
2349 if (Tmp1.Val) Result = Tmp1;
2355 StoreSDNode *ST = cast<StoreSDNode>(Node);
2356 Tmp1 = LegalizeOp(ST->getChain()); // Legalize the chain.
2357 Tmp2 = LegalizeOp(ST->getBasePtr()); // Legalize the pointer.
2358 int SVOffset = ST->getSrcValueOffset();
2359 unsigned Alignment = ST->getAlignment();
2360 bool isVolatile = ST->isVolatile();
2362 if (!ST->isTruncatingStore()) {
2363 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr'
2364 // FIXME: We shouldn't do this for TargetConstantFP's.
2365 // FIXME: move this to the DAG Combiner! Note that we can't regress due
2366 // to phase ordering between legalized code and the dag combiner. This
2367 // probably means that we need to integrate dag combiner and legalizer
2369 // We generally can't do this one for long doubles.
2370 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(ST->getValue())) {
2371 if (CFP->getValueType(0) == MVT::f32 &&
2372 getTypeAction(MVT::i32) == Legal) {
2373 Tmp3 = DAG.getConstant(CFP->getValueAPF().
2374 convertToAPInt().zextOrTrunc(32),
2376 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2377 SVOffset, isVolatile, Alignment);
2379 } else if (CFP->getValueType(0) == MVT::f64) {
2380 // If this target supports 64-bit registers, do a single 64-bit store.
2381 if (getTypeAction(MVT::i64) == Legal) {
2382 Tmp3 = DAG.getConstant(CFP->getValueAPF().convertToAPInt().
2383 zextOrTrunc(64), MVT::i64);
2384 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2385 SVOffset, isVolatile, Alignment);
2387 } else if (getTypeAction(MVT::i32) == Legal && !ST->isVolatile()) {
2388 // Otherwise, if the target supports 32-bit registers, use 2 32-bit
2389 // stores. If the target supports neither 32- nor 64-bits, this
2390 // xform is certainly not worth it.
2391 const APInt &IntVal =CFP->getValueAPF().convertToAPInt();
2392 SDOperand Lo = DAG.getConstant(APInt(IntVal).trunc(32), MVT::i32);
2393 SDOperand Hi = DAG.getConstant(IntVal.lshr(32).trunc(32), MVT::i32);
2394 if (TLI.isBigEndian()) std::swap(Lo, Hi);
2396 Lo = DAG.getStore(Tmp1, Lo, Tmp2, ST->getSrcValue(),
2397 SVOffset, isVolatile, Alignment);
2398 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2,
2399 DAG.getIntPtrConstant(4));
2400 Hi = DAG.getStore(Tmp1, Hi, Tmp2, ST->getSrcValue(), SVOffset+4,
2401 isVolatile, MinAlign(Alignment, 4U));
2403 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi);
2409 switch (getTypeAction(ST->getMemoryVT())) {
2411 Tmp3 = LegalizeOp(ST->getValue());
2412 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2,
2415 MVT VT = Tmp3.getValueType();
2416 switch (TLI.getOperationAction(ISD::STORE, VT)) {
2417 default: assert(0 && "This action is not supported yet!");
2418 case TargetLowering::Legal:
2419 // If this is an unaligned store and the target doesn't support it,
2421 if (!TLI.allowsUnalignedMemoryAccesses()) {
2422 unsigned ABIAlignment = TLI.getTargetData()->
2423 getABITypeAlignment(ST->getMemoryVT().getTypeForMVT());
2424 if (ST->getAlignment() < ABIAlignment)
2425 Result = ExpandUnalignedStore(cast<StoreSDNode>(Result.Val), DAG,
2429 case TargetLowering::Custom:
2430 Tmp1 = TLI.LowerOperation(Result, DAG);
2431 if (Tmp1.Val) Result = Tmp1;
2433 case TargetLowering::Promote:
2434 assert(VT.isVector() && "Unknown legal promote case!");
2435 Tmp3 = DAG.getNode(ISD::BIT_CONVERT,
2436 TLI.getTypeToPromoteTo(ISD::STORE, VT), Tmp3);
2437 Result = DAG.getStore(Tmp1, Tmp3, Tmp2,
2438 ST->getSrcValue(), SVOffset, isVolatile,
2445 // Truncate the value and store the result.
2446 Tmp3 = PromoteOp(ST->getValue());
2447 Result = DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2448 SVOffset, ST->getMemoryVT(),
2449 isVolatile, Alignment);
2453 unsigned IncrementSize = 0;
2456 // If this is a vector type, then we have to calculate the increment as
2457 // the product of the element size in bytes, and the number of elements
2458 // in the high half of the vector.
2459 if (ST->getValue().getValueType().isVector()) {
2460 SDNode *InVal = ST->getValue().Val;
2461 int InIx = ST->getValue().ResNo;
2462 MVT InVT = InVal->getValueType(InIx);
2463 unsigned NumElems = InVT.getVectorNumElements();
2464 MVT EVT = InVT.getVectorElementType();
2466 // Figure out if there is a simple type corresponding to this Vector
2467 // type. If so, convert to the vector type.
2468 MVT TVT = MVT::getVectorVT(EVT, NumElems);
2469 if (TLI.isTypeLegal(TVT)) {
2470 // Turn this into a normal store of the vector type.
2471 Tmp3 = LegalizeOp(ST->getValue());
2472 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2473 SVOffset, isVolatile, Alignment);
2474 Result = LegalizeOp(Result);
2476 } else if (NumElems == 1) {
2477 // Turn this into a normal store of the scalar type.
2478 Tmp3 = ScalarizeVectorOp(ST->getValue());
2479 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2480 SVOffset, isVolatile, Alignment);
2481 // The scalarized value type may not be legal, e.g. it might require
2482 // promotion or expansion. Relegalize the scalar store.
2483 Result = LegalizeOp(Result);
2486 SplitVectorOp(ST->getValue(), Lo, Hi);
2487 IncrementSize = Lo.Val->getValueType(0).getVectorNumElements() *
2488 EVT.getSizeInBits()/8;
2491 ExpandOp(ST->getValue(), Lo, Hi);
2492 IncrementSize = Hi.Val ? Hi.getValueType().getSizeInBits()/8 : 0;
2494 if (TLI.isBigEndian())
2498 Lo = DAG.getStore(Tmp1, Lo, Tmp2, ST->getSrcValue(),
2499 SVOffset, isVolatile, Alignment);
2501 if (Hi.Val == NULL) {
2502 // Must be int <-> float one-to-one expansion.
2507 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2,
2508 DAG.getIntPtrConstant(IncrementSize));
2509 assert(isTypeLegal(Tmp2.getValueType()) &&
2510 "Pointers must be legal!");
2511 SVOffset += IncrementSize;
2512 Alignment = MinAlign(Alignment, IncrementSize);
2513 Hi = DAG.getStore(Tmp1, Hi, Tmp2, ST->getSrcValue(),
2514 SVOffset, isVolatile, Alignment);
2515 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi);
2519 switch (getTypeAction(ST->getValue().getValueType())) {
2521 Tmp3 = LegalizeOp(ST->getValue());
2524 // We can promote the value, the truncstore will still take care of it.
2525 Tmp3 = PromoteOp(ST->getValue());
2528 // Just store the low part. This may become a non-trunc store, so make
2529 // sure to use getTruncStore, not UpdateNodeOperands below.
2530 ExpandOp(ST->getValue(), Tmp3, Tmp4);
2531 return DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2532 SVOffset, MVT::i8, isVolatile, Alignment);
2535 MVT StVT = ST->getMemoryVT();
2536 unsigned StWidth = StVT.getSizeInBits();
2538 if (StWidth != StVT.getStoreSizeInBits()) {
2539 // Promote to a byte-sized store with upper bits zero if not
2540 // storing an integral number of bytes. For example, promote
2541 // TRUNCSTORE:i1 X -> TRUNCSTORE:i8 (and X, 1)
2542 MVT NVT = MVT::getIntegerVT(StVT.getStoreSizeInBits());
2543 Tmp3 = DAG.getZeroExtendInReg(Tmp3, StVT);
2544 Result = DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2545 SVOffset, NVT, isVolatile, Alignment);
2546 } else if (StWidth & (StWidth - 1)) {
2547 // If not storing a power-of-2 number of bits, expand as two stores.
2548 assert(StVT.isExtended() && !StVT.isVector() &&
2549 "Unsupported truncstore!");
2550 unsigned RoundWidth = 1 << Log2_32(StWidth);
2551 assert(RoundWidth < StWidth);
2552 unsigned ExtraWidth = StWidth - RoundWidth;
2553 assert(ExtraWidth < RoundWidth);
2554 assert(!(RoundWidth % 8) && !(ExtraWidth % 8) &&
2555 "Store size not an integral number of bytes!");
2556 MVT RoundVT = MVT::getIntegerVT(RoundWidth);
2557 MVT ExtraVT = MVT::getIntegerVT(ExtraWidth);
2559 unsigned IncrementSize;
2561 if (TLI.isLittleEndian()) {
2562 // TRUNCSTORE:i24 X -> TRUNCSTORE:i16 X, TRUNCSTORE@+2:i8 (srl X, 16)
2563 // Store the bottom RoundWidth bits.
2564 Lo = DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2566 isVolatile, Alignment);
2568 // Store the remaining ExtraWidth bits.
2569 IncrementSize = RoundWidth / 8;
2570 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2,
2571 DAG.getIntPtrConstant(IncrementSize));
2572 Hi = DAG.getNode(ISD::SRL, Tmp3.getValueType(), Tmp3,
2573 DAG.getConstant(RoundWidth, TLI.getShiftAmountTy()));
2574 Hi = DAG.getTruncStore(Tmp1, Hi, Tmp2, ST->getSrcValue(),
2575 SVOffset + IncrementSize, ExtraVT, isVolatile,
2576 MinAlign(Alignment, IncrementSize));
2578 // Big endian - avoid unaligned stores.
2579 // TRUNCSTORE:i24 X -> TRUNCSTORE:i16 (srl X, 8), TRUNCSTORE@+2:i8 X
2580 // Store the top RoundWidth bits.
2581 Hi = DAG.getNode(ISD::SRL, Tmp3.getValueType(), Tmp3,
2582 DAG.getConstant(ExtraWidth, TLI.getShiftAmountTy()));
2583 Hi = DAG.getTruncStore(Tmp1, Hi, Tmp2, ST->getSrcValue(), SVOffset,
2584 RoundVT, isVolatile, Alignment);
2586 // Store the remaining ExtraWidth bits.
2587 IncrementSize = RoundWidth / 8;
2588 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2,
2589 DAG.getIntPtrConstant(IncrementSize));
2590 Lo = DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2591 SVOffset + IncrementSize, ExtraVT, isVolatile,
2592 MinAlign(Alignment, IncrementSize));
2595 // The order of the stores doesn't matter.
2596 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi);
2598 if (Tmp1 != ST->getChain() || Tmp3 != ST->getValue() ||
2599 Tmp2 != ST->getBasePtr())
2600 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2,
2603 switch (TLI.getTruncStoreAction(ST->getValue().getValueType(), StVT)) {
2604 default: assert(0 && "This action is not supported yet!");
2605 case TargetLowering::Legal:
2606 // If this is an unaligned store and the target doesn't support it,
2608 if (!TLI.allowsUnalignedMemoryAccesses()) {
2609 unsigned ABIAlignment = TLI.getTargetData()->
2610 getABITypeAlignment(ST->getMemoryVT().getTypeForMVT());
2611 if (ST->getAlignment() < ABIAlignment)
2612 Result = ExpandUnalignedStore(cast<StoreSDNode>(Result.Val), DAG,
2616 case TargetLowering::Custom:
2617 Result = TLI.LowerOperation(Result, DAG);
2620 // TRUNCSTORE:i16 i32 -> STORE i16
2621 assert(isTypeLegal(StVT) && "Do not know how to expand this store!");
2622 Tmp3 = DAG.getNode(ISD::TRUNCATE, StVT, Tmp3);
2623 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(), SVOffset,
2624 isVolatile, Alignment);
2632 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2633 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
2635 case ISD::STACKSAVE:
2636 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2637 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2638 Tmp1 = Result.getValue(0);
2639 Tmp2 = Result.getValue(1);
2641 switch (TLI.getOperationAction(ISD::STACKSAVE, MVT::Other)) {
2642 default: assert(0 && "This action is not supported yet!");
2643 case TargetLowering::Legal: break;
2644 case TargetLowering::Custom:
2645 Tmp3 = TLI.LowerOperation(Result, DAG);
2647 Tmp1 = LegalizeOp(Tmp3);
2648 Tmp2 = LegalizeOp(Tmp3.getValue(1));
2651 case TargetLowering::Expand:
2652 // Expand to CopyFromReg if the target set
2653 // StackPointerRegisterToSaveRestore.
2654 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) {
2655 Tmp1 = DAG.getCopyFromReg(Result.getOperand(0), SP,
2656 Node->getValueType(0));
2657 Tmp2 = Tmp1.getValue(1);
2659 Tmp1 = DAG.getNode(ISD::UNDEF, Node->getValueType(0));
2660 Tmp2 = Node->getOperand(0);
2665 // Since stacksave produce two values, make sure to remember that we
2666 // legalized both of them.
2667 AddLegalizedOperand(SDOperand(Node, 0), Tmp1);
2668 AddLegalizedOperand(SDOperand(Node, 1), Tmp2);
2669 return Op.ResNo ? Tmp2 : Tmp1;
2671 case ISD::STACKRESTORE:
2672 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2673 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
2674 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
2676 switch (TLI.getOperationAction(ISD::STACKRESTORE, MVT::Other)) {
2677 default: assert(0 && "This action is not supported yet!");
2678 case TargetLowering::Legal: break;
2679 case TargetLowering::Custom:
2680 Tmp1 = TLI.LowerOperation(Result, DAG);
2681 if (Tmp1.Val) Result = Tmp1;
2683 case TargetLowering::Expand:
2684 // Expand to CopyToReg if the target set
2685 // StackPointerRegisterToSaveRestore.
2686 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) {
2687 Result = DAG.getCopyToReg(Tmp1, SP, Tmp2);
2695 case ISD::READCYCLECOUNTER:
2696 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain
2697 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2698 switch (TLI.getOperationAction(ISD::READCYCLECOUNTER,
2699 Node->getValueType(0))) {
2700 default: assert(0 && "This action is not supported yet!");
2701 case TargetLowering::Legal:
2702 Tmp1 = Result.getValue(0);
2703 Tmp2 = Result.getValue(1);
2705 case TargetLowering::Custom:
2706 Result = TLI.LowerOperation(Result, DAG);
2707 Tmp1 = LegalizeOp(Result.getValue(0));
2708 Tmp2 = LegalizeOp(Result.getValue(1));
2712 // Since rdcc produce two values, make sure to remember that we legalized
2714 AddLegalizedOperand(SDOperand(Node, 0), Tmp1);
2715 AddLegalizedOperand(SDOperand(Node, 1), Tmp2);
2719 switch (getTypeAction(Node->getOperand(0).getValueType())) {
2720 case Expand: assert(0 && "It's impossible to expand bools");
2722 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the condition.
2725 Tmp1 = PromoteOp(Node->getOperand(0)); // Promote the condition.
2726 // Make sure the condition is either zero or one.
2727 unsigned BitWidth = Tmp1.getValueSizeInBits();
2728 if (!DAG.MaskedValueIsZero(Tmp1,
2729 APInt::getHighBitsSet(BitWidth, BitWidth-1)))
2730 Tmp1 = DAG.getZeroExtendInReg(Tmp1, MVT::i1);
2734 Tmp2 = LegalizeOp(Node->getOperand(1)); // TrueVal
2735 Tmp3 = LegalizeOp(Node->getOperand(2)); // FalseVal
2737 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2739 switch (TLI.getOperationAction(ISD::SELECT, Tmp2.getValueType())) {
2740 default: assert(0 && "This action is not supported yet!");
2741 case TargetLowering::Legal: break;
2742 case TargetLowering::Custom: {
2743 Tmp1 = TLI.LowerOperation(Result, DAG);
2744 if (Tmp1.Val) Result = Tmp1;
2747 case TargetLowering::Expand:
2748 if (Tmp1.getOpcode() == ISD::SETCC) {
2749 Result = DAG.getSelectCC(Tmp1.getOperand(0), Tmp1.getOperand(1),
2751 cast<CondCodeSDNode>(Tmp1.getOperand(2))->get());
2753 Result = DAG.getSelectCC(Tmp1,
2754 DAG.getConstant(0, Tmp1.getValueType()),
2755 Tmp2, Tmp3, ISD::SETNE);
2758 case TargetLowering::Promote: {
2760 TLI.getTypeToPromoteTo(ISD::SELECT, Tmp2.getValueType());
2761 unsigned ExtOp, TruncOp;
2762 if (Tmp2.getValueType().isVector()) {
2763 ExtOp = ISD::BIT_CONVERT;
2764 TruncOp = ISD::BIT_CONVERT;
2765 } else if (Tmp2.getValueType().isInteger()) {
2766 ExtOp = ISD::ANY_EXTEND;
2767 TruncOp = ISD::TRUNCATE;
2769 ExtOp = ISD::FP_EXTEND;
2770 TruncOp = ISD::FP_ROUND;
2772 // Promote each of the values to the new type.
2773 Tmp2 = DAG.getNode(ExtOp, NVT, Tmp2);
2774 Tmp3 = DAG.getNode(ExtOp, NVT, Tmp3);
2775 // Perform the larger operation, then round down.
2776 Result = DAG.getNode(ISD::SELECT, NVT, Tmp1, Tmp2,Tmp3);
2777 if (TruncOp != ISD::FP_ROUND)
2778 Result = DAG.getNode(TruncOp, Node->getValueType(0), Result);
2780 Result = DAG.getNode(TruncOp, Node->getValueType(0), Result,
2781 DAG.getIntPtrConstant(0));
2786 case ISD::SELECT_CC: {
2787 Tmp1 = Node->getOperand(0); // LHS
2788 Tmp2 = Node->getOperand(1); // RHS
2789 Tmp3 = LegalizeOp(Node->getOperand(2)); // True
2790 Tmp4 = LegalizeOp(Node->getOperand(3)); // False
2791 SDOperand CC = Node->getOperand(4);
2793 LegalizeSetCCOperands(Tmp1, Tmp2, CC);
2795 // If we didn't get both a LHS and RHS back from LegalizeSetCCOperands,
2796 // the LHS is a legal SETCC itself. In this case, we need to compare
2797 // the result against zero to select between true and false values.
2798 if (Tmp2.Val == 0) {
2799 Tmp2 = DAG.getConstant(0, Tmp1.getValueType());
2800 CC = DAG.getCondCode(ISD::SETNE);
2802 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4, CC);
2804 // Everything is legal, see if we should expand this op or something.
2805 switch (TLI.getOperationAction(ISD::SELECT_CC, Tmp3.getValueType())) {
2806 default: assert(0 && "This action is not supported yet!");
2807 case TargetLowering::Legal: break;
2808 case TargetLowering::Custom:
2809 Tmp1 = TLI.LowerOperation(Result, DAG);
2810 if (Tmp1.Val) Result = Tmp1;
2816 Tmp1 = Node->getOperand(0);
2817 Tmp2 = Node->getOperand(1);
2818 Tmp3 = Node->getOperand(2);
2819 LegalizeSetCCOperands(Tmp1, Tmp2, Tmp3);
2821 // If we had to Expand the SetCC operands into a SELECT node, then it may
2822 // not always be possible to return a true LHS & RHS. In this case, just
2823 // return the value we legalized, returned in the LHS
2824 if (Tmp2.Val == 0) {
2829 switch (TLI.getOperationAction(ISD::SETCC, Tmp1.getValueType())) {
2830 default: assert(0 && "Cannot handle this action for SETCC yet!");
2831 case TargetLowering::Custom:
2834 case TargetLowering::Legal:
2835 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2837 Tmp4 = TLI.LowerOperation(Result, DAG);
2838 if (Tmp4.Val) Result = Tmp4;
2841 case TargetLowering::Promote: {
2842 // First step, figure out the appropriate operation to use.
2843 // Allow SETCC to not be supported for all legal data types
2844 // Mostly this targets FP
2845 MVT NewInTy = Node->getOperand(0).getValueType();
2846 MVT OldVT = NewInTy; OldVT = OldVT;
2848 // Scan for the appropriate larger type to use.
2850 NewInTy = (MVT::SimpleValueType)(NewInTy.getSimpleVT()+1);
2852 assert(NewInTy.isInteger() == OldVT.isInteger() &&
2853 "Fell off of the edge of the integer world");
2854 assert(NewInTy.isFloatingPoint() == OldVT.isFloatingPoint() &&
2855 "Fell off of the edge of the floating point world");
2857 // If the target supports SETCC of this type, use it.
2858 if (TLI.isOperationLegal(ISD::SETCC, NewInTy))
2861 if (NewInTy.isInteger())
2862 assert(0 && "Cannot promote Legal Integer SETCC yet");
2864 Tmp1 = DAG.getNode(ISD::FP_EXTEND, NewInTy, Tmp1);
2865 Tmp2 = DAG.getNode(ISD::FP_EXTEND, NewInTy, Tmp2);
2867 Tmp1 = LegalizeOp(Tmp1);
2868 Tmp2 = LegalizeOp(Tmp2);
2869 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2870 Result = LegalizeOp(Result);
2873 case TargetLowering::Expand:
2874 // Expand a setcc node into a select_cc of the same condition, lhs, and
2875 // rhs that selects between const 1 (true) and const 0 (false).
2876 MVT VT = Node->getValueType(0);
2877 Result = DAG.getNode(ISD::SELECT_CC, VT, Tmp1, Tmp2,
2878 DAG.getConstant(1, VT), DAG.getConstant(0, VT),
2884 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
2885 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS
2886 SDOperand CC = Node->getOperand(2);
2888 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, CC);
2890 // Everything is legal, see if we should expand this op or something.
2891 switch (TLI.getOperationAction(ISD::VSETCC, Tmp1.getValueType())) {
2892 default: assert(0 && "This action is not supported yet!");
2893 case TargetLowering::Legal: break;
2894 case TargetLowering::Custom:
2895 Tmp1 = TLI.LowerOperation(Result, DAG);
2896 if (Tmp1.Val) Result = Tmp1;
2902 case ISD::SHL_PARTS:
2903 case ISD::SRA_PARTS:
2904 case ISD::SRL_PARTS: {
2905 SmallVector<SDOperand, 8> Ops;
2906 bool Changed = false;
2907 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
2908 Ops.push_back(LegalizeOp(Node->getOperand(i)));
2909 Changed |= Ops.back() != Node->getOperand(i);
2912 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
2914 switch (TLI.getOperationAction(Node->getOpcode(),
2915 Node->getValueType(0))) {
2916 default: assert(0 && "This action is not supported yet!");
2917 case TargetLowering::Legal: break;
2918 case TargetLowering::Custom:
2919 Tmp1 = TLI.LowerOperation(Result, DAG);
2921 SDOperand Tmp2, RetVal(0, 0);
2922 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) {
2923 Tmp2 = LegalizeOp(Tmp1.getValue(i));
2924 AddLegalizedOperand(SDOperand(Node, i), Tmp2);
2928 assert(RetVal.Val && "Illegal result number");
2934 // Since these produce multiple values, make sure to remember that we
2935 // legalized all of them.
2936 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
2937 AddLegalizedOperand(SDOperand(Node, i), Result.getValue(i));
2938 return Result.getValue(Op.ResNo);
2960 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
2961 switch (getTypeAction(Node->getOperand(1).getValueType())) {
2962 case Expand: assert(0 && "Not possible");
2964 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the RHS.
2967 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the RHS.
2971 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
2973 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
2974 default: assert(0 && "BinOp legalize operation not supported");
2975 case TargetLowering::Legal: break;
2976 case TargetLowering::Custom:
2977 Tmp1 = TLI.LowerOperation(Result, DAG);
2978 if (Tmp1.Val) Result = Tmp1;
2980 case TargetLowering::Expand: {
2981 MVT VT = Op.getValueType();
2983 // See if multiply or divide can be lowered using two-result operations.
2984 SDVTList VTs = DAG.getVTList(VT, VT);
2985 if (Node->getOpcode() == ISD::MUL) {
2986 // We just need the low half of the multiply; try both the signed
2987 // and unsigned forms. If the target supports both SMUL_LOHI and
2988 // UMUL_LOHI, form a preference by checking which forms of plain
2989 // MULH it supports.
2990 bool HasSMUL_LOHI = TLI.isOperationLegal(ISD::SMUL_LOHI, VT);
2991 bool HasUMUL_LOHI = TLI.isOperationLegal(ISD::UMUL_LOHI, VT);
2992 bool HasMULHS = TLI.isOperationLegal(ISD::MULHS, VT);
2993 bool HasMULHU = TLI.isOperationLegal(ISD::MULHU, VT);
2994 unsigned OpToUse = 0;
2995 if (HasSMUL_LOHI && !HasMULHS) {
2996 OpToUse = ISD::SMUL_LOHI;
2997 } else if (HasUMUL_LOHI && !HasMULHU) {
2998 OpToUse = ISD::UMUL_LOHI;
2999 } else if (HasSMUL_LOHI) {
3000 OpToUse = ISD::SMUL_LOHI;
3001 } else if (HasUMUL_LOHI) {
3002 OpToUse = ISD::UMUL_LOHI;
3005 Result = SDOperand(DAG.getNode(OpToUse, VTs, Tmp1, Tmp2).Val, 0);
3009 if (Node->getOpcode() == ISD::MULHS &&
3010 TLI.isOperationLegal(ISD::SMUL_LOHI, VT)) {
3011 Result = SDOperand(DAG.getNode(ISD::SMUL_LOHI, VTs, Tmp1, Tmp2).Val, 1);
3014 if (Node->getOpcode() == ISD::MULHU &&
3015 TLI.isOperationLegal(ISD::UMUL_LOHI, VT)) {
3016 Result = SDOperand(DAG.getNode(ISD::UMUL_LOHI, VTs, Tmp1, Tmp2).Val, 1);
3019 if (Node->getOpcode() == ISD::SDIV &&
3020 TLI.isOperationLegal(ISD::SDIVREM, VT)) {
3021 Result = SDOperand(DAG.getNode(ISD::SDIVREM, VTs, Tmp1, Tmp2).Val, 0);
3024 if (Node->getOpcode() == ISD::UDIV &&
3025 TLI.isOperationLegal(ISD::UDIVREM, VT)) {
3026 Result = SDOperand(DAG.getNode(ISD::UDIVREM, VTs, Tmp1, Tmp2).Val, 0);
3030 // Check to see if we have a libcall for this operator.
3031 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
3032 bool isSigned = false;
3033 switch (Node->getOpcode()) {
3036 if (VT == MVT::i32) {
3037 LC = Node->getOpcode() == ISD::UDIV
3038 ? RTLIB::UDIV_I32 : RTLIB::SDIV_I32;
3039 isSigned = Node->getOpcode() == ISD::SDIV;
3043 LC = GetFPLibCall(VT, RTLIB::POW_F32, RTLIB::POW_F64, RTLIB::POW_F80,
3044 RTLIB::POW_PPCF128);
3048 if (LC != RTLIB::UNKNOWN_LIBCALL) {
3050 Result = ExpandLibCall(LC, Node, isSigned, Dummy);
3054 assert(Node->getValueType(0).isVector() &&
3055 "Cannot expand this binary operator!");
3056 // Expand the operation into a bunch of nasty scalar code.
3057 Result = LegalizeOp(UnrollVectorOp(Op));
3060 case TargetLowering::Promote: {
3061 switch (Node->getOpcode()) {
3062 default: assert(0 && "Do not know how to promote this BinOp!");
3066 MVT OVT = Node->getValueType(0);
3067 MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
3068 assert(OVT.isVector() && "Cannot promote this BinOp!");
3069 // Bit convert each of the values to the new type.
3070 Tmp1 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp1);
3071 Tmp2 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp2);
3072 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
3073 // Bit convert the result back the original type.
3074 Result = DAG.getNode(ISD::BIT_CONVERT, OVT, Result);
3082 case ISD::SMUL_LOHI:
3083 case ISD::UMUL_LOHI:
3086 // These nodes will only be produced by target-specific lowering, so
3087 // they shouldn't be here if they aren't legal.
3088 assert(TLI.isOperationLegal(Node->getOpcode(), Node->getValueType(0)) &&
3089 "This must be legal!");
3091 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
3092 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS
3093 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
3096 case ISD::FCOPYSIGN: // FCOPYSIGN does not require LHS/RHS to match type!
3097 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
3098 switch (getTypeAction(Node->getOperand(1).getValueType())) {
3099 case Expand: assert(0 && "Not possible");
3101 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the RHS.
3104 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the RHS.
3108 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
3110 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3111 default: assert(0 && "Operation not supported");
3112 case TargetLowering::Custom:
3113 Tmp1 = TLI.LowerOperation(Result, DAG);
3114 if (Tmp1.Val) Result = Tmp1;
3116 case TargetLowering::Legal: break;
3117 case TargetLowering::Expand: {
3118 // If this target supports fabs/fneg natively and select is cheap,
3119 // do this efficiently.
3120 if (!TLI.isSelectExpensive() &&
3121 TLI.getOperationAction(ISD::FABS, Tmp1.getValueType()) ==
3122 TargetLowering::Legal &&
3123 TLI.getOperationAction(ISD::FNEG, Tmp1.getValueType()) ==
3124 TargetLowering::Legal) {
3125 // Get the sign bit of the RHS.
3127 Tmp2.getValueType() == MVT::f32 ? MVT::i32 : MVT::i64;
3128 SDOperand SignBit = DAG.getNode(ISD::BIT_CONVERT, IVT, Tmp2);
3129 SignBit = DAG.getSetCC(TLI.getSetCCResultType(SignBit),
3130 SignBit, DAG.getConstant(0, IVT), ISD::SETLT);
3131 // Get the absolute value of the result.
3132 SDOperand AbsVal = DAG.getNode(ISD::FABS, Tmp1.getValueType(), Tmp1);
3133 // Select between the nabs and abs value based on the sign bit of
3135 Result = DAG.getNode(ISD::SELECT, AbsVal.getValueType(), SignBit,
3136 DAG.getNode(ISD::FNEG, AbsVal.getValueType(),
3139 Result = LegalizeOp(Result);
3143 // Otherwise, do bitwise ops!
3145 Node->getValueType(0) == MVT::f32 ? MVT::i32 : MVT::i64;
3146 Result = ExpandFCOPYSIGNToBitwiseOps(Node, NVT, DAG, TLI);
3147 Result = DAG.getNode(ISD::BIT_CONVERT, Node->getValueType(0), Result);
3148 Result = LegalizeOp(Result);
3156 Tmp1 = LegalizeOp(Node->getOperand(0));
3157 Tmp2 = LegalizeOp(Node->getOperand(1));
3158 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
3159 // Since this produces two values, make sure to remember that we legalized
3161 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
3162 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
3167 Tmp1 = LegalizeOp(Node->getOperand(0));
3168 Tmp2 = LegalizeOp(Node->getOperand(1));
3169 Tmp3 = LegalizeOp(Node->getOperand(2));
3170 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
3171 // Since this produces two values, make sure to remember that we legalized
3173 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
3174 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
3177 case ISD::BUILD_PAIR: {
3178 MVT PairTy = Node->getValueType(0);
3179 // TODO: handle the case where the Lo and Hi operands are not of legal type
3180 Tmp1 = LegalizeOp(Node->getOperand(0)); // Lo
3181 Tmp2 = LegalizeOp(Node->getOperand(1)); // Hi
3182 switch (TLI.getOperationAction(ISD::BUILD_PAIR, PairTy)) {
3183 case TargetLowering::Promote:
3184 case TargetLowering::Custom:
3185 assert(0 && "Cannot promote/custom this yet!");
3186 case TargetLowering::Legal:
3187 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1))
3188 Result = DAG.getNode(ISD::BUILD_PAIR, PairTy, Tmp1, Tmp2);
3190 case TargetLowering::Expand:
3191 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, PairTy, Tmp1);
3192 Tmp2 = DAG.getNode(ISD::ANY_EXTEND, PairTy, Tmp2);
3193 Tmp2 = DAG.getNode(ISD::SHL, PairTy, Tmp2,
3194 DAG.getConstant(PairTy.getSizeInBits()/2,
3195 TLI.getShiftAmountTy()));
3196 Result = DAG.getNode(ISD::OR, PairTy, Tmp1, Tmp2);
3205 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
3206 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS
3208 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3209 case TargetLowering::Promote: assert(0 && "Cannot promote this yet!");
3210 case TargetLowering::Custom:
3213 case TargetLowering::Legal:
3214 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
3216 Tmp1 = TLI.LowerOperation(Result, DAG);
3217 if (Tmp1.Val) Result = Tmp1;
3220 case TargetLowering::Expand: {
3221 unsigned DivOpc= (Node->getOpcode() == ISD::UREM) ? ISD::UDIV : ISD::SDIV;
3222 bool isSigned = DivOpc == ISD::SDIV;
3223 MVT VT = Node->getValueType(0);
3225 // See if remainder can be lowered using two-result operations.
3226 SDVTList VTs = DAG.getVTList(VT, VT);
3227 if (Node->getOpcode() == ISD::SREM &&
3228 TLI.isOperationLegal(ISD::SDIVREM, VT)) {
3229 Result = SDOperand(DAG.getNode(ISD::SDIVREM, VTs, Tmp1, Tmp2).Val, 1);
3232 if (Node->getOpcode() == ISD::UREM &&
3233 TLI.isOperationLegal(ISD::UDIVREM, VT)) {
3234 Result = SDOperand(DAG.getNode(ISD::UDIVREM, VTs, Tmp1, Tmp2).Val, 1);
3238 if (VT.isInteger()) {
3239 if (TLI.getOperationAction(DivOpc, VT) ==
3240 TargetLowering::Legal) {
3242 Result = DAG.getNode(DivOpc, VT, Tmp1, Tmp2);
3243 Result = DAG.getNode(ISD::MUL, VT, Result, Tmp2);
3244 Result = DAG.getNode(ISD::SUB, VT, Tmp1, Result);
3245 } else if (VT.isVector()) {
3246 Result = LegalizeOp(UnrollVectorOp(Op));
3248 assert(VT == MVT::i32 &&
3249 "Cannot expand this binary operator!");
3250 RTLIB::Libcall LC = Node->getOpcode() == ISD::UREM
3251 ? RTLIB::UREM_I32 : RTLIB::SREM_I32;
3253 Result = ExpandLibCall(LC, Node, isSigned, Dummy);
3256 assert(VT.isFloatingPoint() &&
3257 "remainder op must have integer or floating-point type");
3258 if (VT.isVector()) {
3259 Result = LegalizeOp(UnrollVectorOp(Op));
3261 // Floating point mod -> fmod libcall.
3262 RTLIB::Libcall LC = GetFPLibCall(VT, RTLIB::REM_F32, RTLIB::REM_F64,
3263 RTLIB::REM_F80, RTLIB::REM_PPCF128);
3265 Result = ExpandLibCall(LC, Node, false/*sign irrelevant*/, Dummy);
3273 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
3274 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
3276 MVT VT = Node->getValueType(0);
3277 switch (TLI.getOperationAction(Node->getOpcode(), MVT::Other)) {
3278 default: assert(0 && "This action is not supported yet!");
3279 case TargetLowering::Custom:
3282 case TargetLowering::Legal:
3283 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
3284 Result = Result.getValue(0);
3285 Tmp1 = Result.getValue(1);
3288 Tmp2 = TLI.LowerOperation(Result, DAG);
3290 Result = LegalizeOp(Tmp2);
3291 Tmp1 = LegalizeOp(Tmp2.getValue(1));
3295 case TargetLowering::Expand: {
3296 const Value *V = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
3297 SDOperand VAList = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp2, V, 0);
3298 // Increment the pointer, VAList, to the next vaarg
3299 Tmp3 = DAG.getNode(ISD::ADD, TLI.getPointerTy(), VAList,
3300 DAG.getConstant(VT.getSizeInBits()/8,
3301 TLI.getPointerTy()));
3302 // Store the incremented VAList to the legalized pointer
3303 Tmp3 = DAG.getStore(VAList.getValue(1), Tmp3, Tmp2, V, 0);
3304 // Load the actual argument out of the pointer VAList
3305 Result = DAG.getLoad(VT, Tmp3, VAList, NULL, 0);
3306 Tmp1 = LegalizeOp(Result.getValue(1));
3307 Result = LegalizeOp(Result);
3311 // Since VAARG produces two values, make sure to remember that we
3312 // legalized both of them.
3313 AddLegalizedOperand(SDOperand(Node, 0), Result);
3314 AddLegalizedOperand(SDOperand(Node, 1), Tmp1);
3315 return Op.ResNo ? Tmp1 : Result;
3319 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
3320 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the dest pointer.
3321 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the source pointer.
3323 switch (TLI.getOperationAction(ISD::VACOPY, MVT::Other)) {
3324 default: assert(0 && "This action is not supported yet!");
3325 case TargetLowering::Custom:
3328 case TargetLowering::Legal:
3329 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3,
3330 Node->getOperand(3), Node->getOperand(4));
3332 Tmp1 = TLI.LowerOperation(Result, DAG);
3333 if (Tmp1.Val) Result = Tmp1;
3336 case TargetLowering::Expand:
3337 // This defaults to loading a pointer from the input and storing it to the
3338 // output, returning the chain.
3339 const Value *VD = cast<SrcValueSDNode>(Node->getOperand(3))->getValue();
3340 const Value *VS = cast<SrcValueSDNode>(Node->getOperand(4))->getValue();
3341 Tmp4 = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp3, VS, 0);
3342 Result = DAG.getStore(Tmp4.getValue(1), Tmp4, Tmp2, VD, 0);
3348 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
3349 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
3351 switch (TLI.getOperationAction(ISD::VAEND, MVT::Other)) {
3352 default: assert(0 && "This action is not supported yet!");
3353 case TargetLowering::Custom:
3356 case TargetLowering::Legal:
3357 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
3359 Tmp1 = TLI.LowerOperation(Tmp1, DAG);
3360 if (Tmp1.Val) Result = Tmp1;
3363 case TargetLowering::Expand:
3364 Result = Tmp1; // Default to a no-op, return the chain
3370 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
3371 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
3373 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
3375 switch (TLI.getOperationAction(ISD::VASTART, MVT::Other)) {
3376 default: assert(0 && "This action is not supported yet!");
3377 case TargetLowering::Legal: break;
3378 case TargetLowering::Custom:
3379 Tmp1 = TLI.LowerOperation(Result, DAG);
3380 if (Tmp1.Val) Result = Tmp1;
3387 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
3388 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS
3389 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
3390 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3392 assert(0 && "ROTL/ROTR legalize operation not supported");
3394 case TargetLowering::Legal:
3396 case TargetLowering::Custom:
3397 Tmp1 = TLI.LowerOperation(Result, DAG);
3398 if (Tmp1.Val) Result = Tmp1;
3400 case TargetLowering::Promote:
3401 assert(0 && "Do not know how to promote ROTL/ROTR");
3403 case TargetLowering::Expand:
3404 assert(0 && "Do not know how to expand ROTL/ROTR");
3410 Tmp1 = LegalizeOp(Node->getOperand(0)); // Op
3411 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3412 case TargetLowering::Custom:
3413 assert(0 && "Cannot custom legalize this yet!");
3414 case TargetLowering::Legal:
3415 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3417 case TargetLowering::Promote: {
3418 MVT OVT = Tmp1.getValueType();
3419 MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
3420 unsigned DiffBits = NVT.getSizeInBits() - OVT.getSizeInBits();
3422 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1);
3423 Tmp1 = DAG.getNode(ISD::BSWAP, NVT, Tmp1);
3424 Result = DAG.getNode(ISD::SRL, NVT, Tmp1,
3425 DAG.getConstant(DiffBits, TLI.getShiftAmountTy()));
3428 case TargetLowering::Expand:
3429 Result = ExpandBSWAP(Tmp1);
3437 Tmp1 = LegalizeOp(Node->getOperand(0)); // Op
3438 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3439 case TargetLowering::Custom:
3440 case TargetLowering::Legal:
3441 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3442 if (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0)) ==
3443 TargetLowering::Custom) {
3444 Tmp1 = TLI.LowerOperation(Result, DAG);
3450 case TargetLowering::Promote: {
3451 MVT OVT = Tmp1.getValueType();
3452 MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
3454 // Zero extend the argument.
3455 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1);
3456 // Perform the larger operation, then subtract if needed.
3457 Tmp1 = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1);
3458 switch (Node->getOpcode()) {
3463 //if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT)
3464 Tmp2 = DAG.getSetCC(TLI.getSetCCResultType(Tmp1), Tmp1,
3465 DAG.getConstant(NVT.getSizeInBits(), NVT),
3467 Result = DAG.getNode(ISD::SELECT, NVT, Tmp2,
3468 DAG.getConstant(OVT.getSizeInBits(), NVT), Tmp1);
3471 // Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT))
3472 Result = DAG.getNode(ISD::SUB, NVT, Tmp1,
3473 DAG.getConstant(NVT.getSizeInBits() -
3474 OVT.getSizeInBits(), NVT));
3479 case TargetLowering::Expand:
3480 Result = ExpandBitCount(Node->getOpcode(), Tmp1);
3491 Tmp1 = LegalizeOp(Node->getOperand(0));
3492 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3493 case TargetLowering::Promote:
3494 case TargetLowering::Custom:
3497 case TargetLowering::Legal:
3498 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3500 Tmp1 = TLI.LowerOperation(Result, DAG);
3501 if (Tmp1.Val) Result = Tmp1;
3504 case TargetLowering::Expand:
3505 switch (Node->getOpcode()) {
3506 default: assert(0 && "Unreachable!");
3508 // Expand Y = FNEG(X) -> Y = SUB -0.0, X
3509 Tmp2 = DAG.getConstantFP(-0.0, Node->getValueType(0));
3510 Result = DAG.getNode(ISD::FSUB, Node->getValueType(0), Tmp2, Tmp1);
3513 // Expand Y = FABS(X) -> Y = (X >u 0.0) ? X : fneg(X).
3514 MVT VT = Node->getValueType(0);
3515 Tmp2 = DAG.getConstantFP(0.0, VT);
3516 Tmp2 = DAG.getSetCC(TLI.getSetCCResultType(Tmp1), Tmp1, Tmp2,
3518 Tmp3 = DAG.getNode(ISD::FNEG, VT, Tmp1);
3519 Result = DAG.getNode(ISD::SELECT, VT, Tmp2, Tmp1, Tmp3);
3525 MVT VT = Node->getValueType(0);
3527 // Expand unsupported unary vector operators by unrolling them.
3528 if (VT.isVector()) {
3529 Result = LegalizeOp(UnrollVectorOp(Op));
3533 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
3534 switch(Node->getOpcode()) {
3536 LC = GetFPLibCall(VT, RTLIB::SQRT_F32, RTLIB::SQRT_F64,
3537 RTLIB::SQRT_F80, RTLIB::SQRT_PPCF128);
3540 LC = GetFPLibCall(VT, RTLIB::SIN_F32, RTLIB::SIN_F64,
3541 RTLIB::SIN_F80, RTLIB::SIN_PPCF128);
3544 LC = GetFPLibCall(VT, RTLIB::COS_F32, RTLIB::COS_F64,
3545 RTLIB::COS_F80, RTLIB::COS_PPCF128);
3547 default: assert(0 && "Unreachable!");
3550 Result = ExpandLibCall(LC, Node, false/*sign irrelevant*/, Dummy);
3558 MVT VT = Node->getValueType(0);
3560 // Expand unsupported unary vector operators by unrolling them.
3561 if (VT.isVector()) {
3562 Result = LegalizeOp(UnrollVectorOp(Op));
3566 // We always lower FPOWI into a libcall. No target support for it yet.
3567 RTLIB::Libcall LC = GetFPLibCall(VT, RTLIB::POWI_F32, RTLIB::POWI_F64,
3568 RTLIB::POWI_F80, RTLIB::POWI_PPCF128);
3570 Result = ExpandLibCall(LC, Node, false/*sign irrelevant*/, Dummy);
3573 case ISD::BIT_CONVERT:
3574 if (!isTypeLegal(Node->getOperand(0).getValueType())) {
3575 Result = EmitStackConvert(Node->getOperand(0), Node->getValueType(0),
3576 Node->getValueType(0));
3577 } else if (Op.getOperand(0).getValueType().isVector()) {
3578 // The input has to be a vector type, we have to either scalarize it, pack
3579 // it, or convert it based on whether the input vector type is legal.
3580 SDNode *InVal = Node->getOperand(0).Val;
3581 int InIx = Node->getOperand(0).ResNo;
3582 unsigned NumElems = InVal->getValueType(InIx).getVectorNumElements();
3583 MVT EVT = InVal->getValueType(InIx).getVectorElementType();
3585 // Figure out if there is a simple type corresponding to this Vector
3586 // type. If so, convert to the vector type.
3587 MVT TVT = MVT::getVectorVT(EVT, NumElems);
3588 if (TLI.isTypeLegal(TVT)) {
3589 // Turn this into a bit convert of the vector input.
3590 Result = DAG.getNode(ISD::BIT_CONVERT, Node->getValueType(0),
3591 LegalizeOp(Node->getOperand(0)));
3593 } else if (NumElems == 1) {
3594 // Turn this into a bit convert of the scalar input.
3595 Result = DAG.getNode(ISD::BIT_CONVERT, Node->getValueType(0),
3596 ScalarizeVectorOp(Node->getOperand(0)));
3599 // FIXME: UNIMP! Store then reload
3600 assert(0 && "Cast from unsupported vector type not implemented yet!");
3603 switch (TLI.getOperationAction(ISD::BIT_CONVERT,
3604 Node->getOperand(0).getValueType())) {
3605 default: assert(0 && "Unknown operation action!");
3606 case TargetLowering::Expand:
3607 Result = EmitStackConvert(Node->getOperand(0), Node->getValueType(0),
3608 Node->getValueType(0));
3610 case TargetLowering::Legal:
3611 Tmp1 = LegalizeOp(Node->getOperand(0));
3612 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3618 // Conversion operators. The source and destination have different types.
3619 case ISD::SINT_TO_FP:
3620 case ISD::UINT_TO_FP: {
3621 bool isSigned = Node->getOpcode() == ISD::SINT_TO_FP;
3622 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3624 switch (TLI.getOperationAction(Node->getOpcode(),
3625 Node->getOperand(0).getValueType())) {
3626 default: assert(0 && "Unknown operation action!");
3627 case TargetLowering::Custom:
3630 case TargetLowering::Legal:
3631 Tmp1 = LegalizeOp(Node->getOperand(0));
3632 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3634 Tmp1 = TLI.LowerOperation(Result, DAG);
3635 if (Tmp1.Val) Result = Tmp1;
3638 case TargetLowering::Expand:
3639 Result = ExpandLegalINT_TO_FP(isSigned,
3640 LegalizeOp(Node->getOperand(0)),
3641 Node->getValueType(0));
3643 case TargetLowering::Promote:
3644 Result = PromoteLegalINT_TO_FP(LegalizeOp(Node->getOperand(0)),
3645 Node->getValueType(0),
3651 Result = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP,
3652 Node->getValueType(0), Node->getOperand(0));
3655 Tmp1 = PromoteOp(Node->getOperand(0));
3657 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, Tmp1.getValueType(),
3658 Tmp1, DAG.getValueType(Node->getOperand(0).getValueType()));
3660 Tmp1 = DAG.getZeroExtendInReg(Tmp1,
3661 Node->getOperand(0).getValueType());
3663 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3664 Result = LegalizeOp(Result); // The 'op' is not necessarily legal!
3670 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3672 Tmp1 = LegalizeOp(Node->getOperand(0));
3673 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3676 ExpandOp(Node->getOperand(0), Tmp1, Tmp2);
3678 // Since the result is legal, we should just be able to truncate the low
3679 // part of the source.
3680 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), Tmp1);
3683 Result = PromoteOp(Node->getOperand(0));
3684 Result = DAG.getNode(ISD::TRUNCATE, Op.getValueType(), Result);
3689 case ISD::FP_TO_SINT:
3690 case ISD::FP_TO_UINT:
3691 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3693 Tmp1 = LegalizeOp(Node->getOperand(0));
3695 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))){
3696 default: assert(0 && "Unknown operation action!");
3697 case TargetLowering::Custom:
3700 case TargetLowering::Legal:
3701 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3703 Tmp1 = TLI.LowerOperation(Result, DAG);
3704 if (Tmp1.Val) Result = Tmp1;
3707 case TargetLowering::Promote:
3708 Result = PromoteLegalFP_TO_INT(Tmp1, Node->getValueType(0),
3709 Node->getOpcode() == ISD::FP_TO_SINT);
3711 case TargetLowering::Expand:
3712 if (Node->getOpcode() == ISD::FP_TO_UINT) {
3713 SDOperand True, False;
3714 MVT VT = Node->getOperand(0).getValueType();
3715 MVT NVT = Node->getValueType(0);
3716 const uint64_t zero[] = {0, 0};
3717 APFloat apf = APFloat(APInt(VT.getSizeInBits(), 2, zero));
3718 APInt x = APInt::getSignBit(NVT.getSizeInBits());
3719 (void)apf.convertFromAPInt(x, false, APFloat::rmNearestTiesToEven);
3720 Tmp2 = DAG.getConstantFP(apf, VT);
3721 Tmp3 = DAG.getSetCC(TLI.getSetCCResultType(Node->getOperand(0)),
3722 Node->getOperand(0), Tmp2, ISD::SETLT);
3723 True = DAG.getNode(ISD::FP_TO_SINT, NVT, Node->getOperand(0));
3724 False = DAG.getNode(ISD::FP_TO_SINT, NVT,
3725 DAG.getNode(ISD::FSUB, VT, Node->getOperand(0),
3727 False = DAG.getNode(ISD::XOR, NVT, False,
3728 DAG.getConstant(x, NVT));
3729 Result = DAG.getNode(ISD::SELECT, NVT, Tmp3, True, False);
3732 assert(0 && "Do not know how to expand FP_TO_SINT yet!");
3738 MVT VT = Op.getValueType();
3739 MVT OVT = Node->getOperand(0).getValueType();
3740 // Convert ppcf128 to i32
3741 if (OVT == MVT::ppcf128 && VT == MVT::i32) {
3742 if (Node->getOpcode() == ISD::FP_TO_SINT) {
3743 Result = DAG.getNode(ISD::FP_ROUND_INREG, MVT::ppcf128,
3744 Node->getOperand(0), DAG.getValueType(MVT::f64));
3745 Result = DAG.getNode(ISD::FP_ROUND, MVT::f64, Result,
3746 DAG.getIntPtrConstant(1));
3747 Result = DAG.getNode(ISD::FP_TO_SINT, VT, Result);
3749 const uint64_t TwoE31[] = {0x41e0000000000000LL, 0};
3750 APFloat apf = APFloat(APInt(128, 2, TwoE31));
3751 Tmp2 = DAG.getConstantFP(apf, OVT);
3752 // X>=2^31 ? (int)(X-2^31)+0x80000000 : (int)X
3753 // FIXME: generated code sucks.
3754 Result = DAG.getNode(ISD::SELECT_CC, VT, Node->getOperand(0), Tmp2,
3755 DAG.getNode(ISD::ADD, MVT::i32,
3756 DAG.getNode(ISD::FP_TO_SINT, VT,
3757 DAG.getNode(ISD::FSUB, OVT,
3758 Node->getOperand(0), Tmp2)),
3759 DAG.getConstant(0x80000000, MVT::i32)),
3760 DAG.getNode(ISD::FP_TO_SINT, VT,
3761 Node->getOperand(0)),
3762 DAG.getCondCode(ISD::SETGE));
3766 // Convert f32 / f64 to i32 / i64 / i128.
3767 RTLIB::Libcall LC = (Node->getOpcode() == ISD::FP_TO_SINT) ?
3768 RTLIB::getFPTOSINT(OVT, VT) : RTLIB::getFPTOUINT(OVT, VT);
3769 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpectd fp-to-int conversion!");
3771 Result = ExpandLibCall(LC, Node, false/*sign irrelevant*/, Dummy);
3775 Tmp1 = PromoteOp(Node->getOperand(0));
3776 Result = DAG.UpdateNodeOperands(Result, LegalizeOp(Tmp1));
3777 Result = LegalizeOp(Result);
3782 case ISD::FP_EXTEND: {
3783 MVT DstVT = Op.getValueType();
3784 MVT SrcVT = Op.getOperand(0).getValueType();
3785 if (TLI.getConvertAction(SrcVT, DstVT) == TargetLowering::Expand) {
3786 // The only other way we can lower this is to turn it into a STORE,
3787 // LOAD pair, targetting a temporary location (a stack slot).
3788 Result = EmitStackConvert(Node->getOperand(0), SrcVT, DstVT);
3791 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3792 case Expand: assert(0 && "Shouldn't need to expand other operators here!");
3794 Tmp1 = LegalizeOp(Node->getOperand(0));
3795 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3798 Tmp1 = PromoteOp(Node->getOperand(0));
3799 Result = DAG.getNode(ISD::FP_EXTEND, Op.getValueType(), Tmp1);
3804 case ISD::FP_ROUND: {
3805 MVT DstVT = Op.getValueType();
3806 MVT SrcVT = Op.getOperand(0).getValueType();
3807 if (TLI.getConvertAction(SrcVT, DstVT) == TargetLowering::Expand) {
3808 if (SrcVT == MVT::ppcf128) {
3810 ExpandOp(Node->getOperand(0), Lo, Result);
3811 // Round it the rest of the way (e.g. to f32) if needed.
3812 if (DstVT!=MVT::f64)
3813 Result = DAG.getNode(ISD::FP_ROUND, DstVT, Result, Op.getOperand(1));
3816 // The only other way we can lower this is to turn it into a STORE,
3817 // LOAD pair, targetting a temporary location (a stack slot).
3818 Result = EmitStackConvert(Node->getOperand(0), DstVT, DstVT);
3821 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3822 case Expand: assert(0 && "Shouldn't need to expand other operators here!");
3824 Tmp1 = LegalizeOp(Node->getOperand(0));
3825 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
3828 Tmp1 = PromoteOp(Node->getOperand(0));
3829 Result = DAG.getNode(ISD::FP_ROUND, Op.getValueType(), Tmp1,
3830 Node->getOperand(1));
3835 case ISD::ANY_EXTEND:
3836 case ISD::ZERO_EXTEND:
3837 case ISD::SIGN_EXTEND:
3838 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3839 case Expand: assert(0 && "Shouldn't need to expand other operators here!");
3841 Tmp1 = LegalizeOp(Node->getOperand(0));
3842 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3843 if (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0)) ==
3844 TargetLowering::Custom) {
3845 Tmp1 = TLI.LowerOperation(Result, DAG);
3846 if (Tmp1.Val) Result = Tmp1;
3850 switch (Node->getOpcode()) {
3851 case ISD::ANY_EXTEND:
3852 Tmp1 = PromoteOp(Node->getOperand(0));
3853 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Tmp1);
3855 case ISD::ZERO_EXTEND:
3856 Result = PromoteOp(Node->getOperand(0));
3857 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Result);
3858 Result = DAG.getZeroExtendInReg(Result,
3859 Node->getOperand(0).getValueType());
3861 case ISD::SIGN_EXTEND:
3862 Result = PromoteOp(Node->getOperand(0));
3863 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Result);
3864 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(),
3866 DAG.getValueType(Node->getOperand(0).getValueType()));
3871 case ISD::FP_ROUND_INREG:
3872 case ISD::SIGN_EXTEND_INREG: {
3873 Tmp1 = LegalizeOp(Node->getOperand(0));
3874 MVT ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT();
3876 // If this operation is not supported, convert it to a shl/shr or load/store
3878 switch (TLI.getOperationAction(Node->getOpcode(), ExtraVT)) {
3879 default: assert(0 && "This action not supported for this op yet!");
3880 case TargetLowering::Legal:
3881 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
3883 case TargetLowering::Expand:
3884 // If this is an integer extend and shifts are supported, do that.
3885 if (Node->getOpcode() == ISD::SIGN_EXTEND_INREG) {
3886 // NOTE: we could fall back on load/store here too for targets without
3887 // SAR. However, it is doubtful that any exist.
3888 unsigned BitsDiff = Node->getValueType(0).getSizeInBits() -
3889 ExtraVT.getSizeInBits();
3890 SDOperand ShiftCst = DAG.getConstant(BitsDiff, TLI.getShiftAmountTy());
3891 Result = DAG.getNode(ISD::SHL, Node->getValueType(0),
3892 Node->getOperand(0), ShiftCst);
3893 Result = DAG.getNode(ISD::SRA, Node->getValueType(0),
3895 } else if (Node->getOpcode() == ISD::FP_ROUND_INREG) {
3896 // The only way we can lower this is to turn it into a TRUNCSTORE,
3897 // EXTLOAD pair, targetting a temporary location (a stack slot).
3899 // NOTE: there is a choice here between constantly creating new stack
3900 // slots and always reusing the same one. We currently always create
3901 // new ones, as reuse may inhibit scheduling.
3902 Result = EmitStackConvert(Node->getOperand(0), ExtraVT,
3903 Node->getValueType(0));
3905 assert(0 && "Unknown op");
3911 case ISD::TRAMPOLINE: {
3913 for (unsigned i = 0; i != 6; ++i)
3914 Ops[i] = LegalizeOp(Node->getOperand(i));
3915 Result = DAG.UpdateNodeOperands(Result, Ops, 6);
3916 // The only option for this node is to custom lower it.
3917 Result = TLI.LowerOperation(Result, DAG);
3918 assert(Result.Val && "Should always custom lower!");
3920 // Since trampoline produces two values, make sure to remember that we
3921 // legalized both of them.
3922 Tmp1 = LegalizeOp(Result.getValue(1));
3923 Result = LegalizeOp(Result);
3924 AddLegalizedOperand(SDOperand(Node, 0), Result);
3925 AddLegalizedOperand(SDOperand(Node, 1), Tmp1);
3926 return Op.ResNo ? Tmp1 : Result;
3928 case ISD::FLT_ROUNDS_: {
3929 MVT VT = Node->getValueType(0);
3930 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
3931 default: assert(0 && "This action not supported for this op yet!");
3932 case TargetLowering::Custom:
3933 Result = TLI.LowerOperation(Op, DAG);
3934 if (Result.Val) break;
3936 case TargetLowering::Legal:
3937 // If this operation is not supported, lower it to constant 1
3938 Result = DAG.getConstant(1, VT);
3944 MVT VT = Node->getValueType(0);
3945 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
3946 default: assert(0 && "This action not supported for this op yet!");
3947 case TargetLowering::Legal:
3948 Tmp1 = LegalizeOp(Node->getOperand(0));
3949 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3951 case TargetLowering::Custom:
3952 Result = TLI.LowerOperation(Op, DAG);
3953 if (Result.Val) break;
3955 case TargetLowering::Expand:
3956 // If this operation is not supported, lower it to 'abort()' call
3957 Tmp1 = LegalizeOp(Node->getOperand(0));
3958 TargetLowering::ArgListTy Args;
3959 std::pair<SDOperand,SDOperand> CallResult =
3960 TLI.LowerCallTo(Tmp1, Type::VoidTy,
3961 false, false, false, CallingConv::C, false,
3962 DAG.getExternalSymbol("abort", TLI.getPointerTy()),
3964 Result = CallResult.second;
3971 assert(Result.getValueType() == Op.getValueType() &&
3972 "Bad legalization!");
3974 // Make sure that the generated code is itself legal.
3976 Result = LegalizeOp(Result);
3978 // Note that LegalizeOp may be reentered even from single-use nodes, which
3979 // means that we always must cache transformed nodes.
3980 AddLegalizedOperand(Op, Result);
3984 /// PromoteOp - Given an operation that produces a value in an invalid type,
3985 /// promote it to compute the value into a larger type. The produced value will
3986 /// have the correct bits for the low portion of the register, but no guarantee
3987 /// is made about the top bits: it may be zero, sign-extended, or garbage.
3988 SDOperand SelectionDAGLegalize::PromoteOp(SDOperand Op) {
3989 MVT VT = Op.getValueType();
3990 MVT NVT = TLI.getTypeToTransformTo(VT);
3991 assert(getTypeAction(VT) == Promote &&
3992 "Caller should expand or legalize operands that are not promotable!");
3993 assert(NVT.bitsGT(VT) && NVT.isInteger() == VT.isInteger() &&
3994 "Cannot promote to smaller type!");
3996 SDOperand Tmp1, Tmp2, Tmp3;
3998 SDNode *Node = Op.Val;
4000 DenseMap<SDOperand, SDOperand>::iterator I = PromotedNodes.find(Op);
4001 if (I != PromotedNodes.end()) return I->second;
4003 switch (Node->getOpcode()) {
4004 case ISD::CopyFromReg:
4005 assert(0 && "CopyFromReg must be legal!");
4008 cerr << "NODE: "; Node->dump(&DAG); cerr << "\n";
4010 assert(0 && "Do not know how to promote this operator!");
4013 Result = DAG.getNode(ISD::UNDEF, NVT);
4017 Result = DAG.getNode(ISD::SIGN_EXTEND, NVT, Op);
4019 Result = DAG.getNode(ISD::ZERO_EXTEND, NVT, Op);
4020 assert(isa<ConstantSDNode>(Result) && "Didn't constant fold zext?");
4022 case ISD::ConstantFP:
4023 Result = DAG.getNode(ISD::FP_EXTEND, NVT, Op);
4024 assert(isa<ConstantFPSDNode>(Result) && "Didn't constant fold fp_extend?");
4028 assert(isTypeLegal(TLI.getSetCCResultType(Node->getOperand(0)))
4029 && "SetCC type is not legal??");
4030 Result = DAG.getNode(ISD::SETCC,
4031 TLI.getSetCCResultType(Node->getOperand(0)),
4032 Node->getOperand(0), Node->getOperand(1),
4033 Node->getOperand(2));
4037 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4039 Result = LegalizeOp(Node->getOperand(0));
4040 assert(Result.getValueType().bitsGE(NVT) &&
4041 "This truncation doesn't make sense!");
4042 if (Result.getValueType().bitsGT(NVT)) // Truncate to NVT instead of VT
4043 Result = DAG.getNode(ISD::TRUNCATE, NVT, Result);
4046 // The truncation is not required, because we don't guarantee anything
4047 // about high bits anyway.
4048 Result = PromoteOp(Node->getOperand(0));
4051 ExpandOp(Node->getOperand(0), Tmp1, Tmp2);
4052 // Truncate the low part of the expanded value to the result type
4053 Result = DAG.getNode(ISD::TRUNCATE, NVT, Tmp1);
4056 case ISD::SIGN_EXTEND:
4057 case ISD::ZERO_EXTEND:
4058 case ISD::ANY_EXTEND:
4059 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4060 case Expand: assert(0 && "BUG: Smaller reg should have been promoted!");
4062 // Input is legal? Just do extend all the way to the larger type.
4063 Result = DAG.getNode(Node->getOpcode(), NVT, Node->getOperand(0));
4066 // Promote the reg if it's smaller.
4067 Result = PromoteOp(Node->getOperand(0));
4068 // The high bits are not guaranteed to be anything. Insert an extend.
4069 if (Node->getOpcode() == ISD::SIGN_EXTEND)
4070 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Result,
4071 DAG.getValueType(Node->getOperand(0).getValueType()));
4072 else if (Node->getOpcode() == ISD::ZERO_EXTEND)
4073 Result = DAG.getZeroExtendInReg(Result,
4074 Node->getOperand(0).getValueType());
4078 case ISD::BIT_CONVERT:
4079 Result = EmitStackConvert(Node->getOperand(0), Node->getValueType(0),
4080 Node->getValueType(0));
4081 Result = PromoteOp(Result);
4084 case ISD::FP_EXTEND:
4085 assert(0 && "Case not implemented. Dynamically dead with 2 FP types!");
4087 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4088 case Expand: assert(0 && "BUG: Cannot expand FP regs!");
4089 case Promote: assert(0 && "Unreachable with 2 FP types!");
4091 if (Node->getConstantOperandVal(1) == 0) {
4092 // Input is legal? Do an FP_ROUND_INREG.
4093 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Node->getOperand(0),
4094 DAG.getValueType(VT));
4096 // Just remove the truncate, it isn't affecting the value.
4097 Result = DAG.getNode(ISD::FP_ROUND, NVT, Node->getOperand(0),
4098 Node->getOperand(1));
4103 case ISD::SINT_TO_FP:
4104 case ISD::UINT_TO_FP:
4105 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4107 // No extra round required here.
4108 Result = DAG.getNode(Node->getOpcode(), NVT, Node->getOperand(0));
4112 Result = PromoteOp(Node->getOperand(0));
4113 if (Node->getOpcode() == ISD::SINT_TO_FP)
4114 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(),
4116 DAG.getValueType(Node->getOperand(0).getValueType()));
4118 Result = DAG.getZeroExtendInReg(Result,
4119 Node->getOperand(0).getValueType());
4120 // No extra round required here.
4121 Result = DAG.getNode(Node->getOpcode(), NVT, Result);
4124 Result = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP, NVT,
4125 Node->getOperand(0));
4126 // Round if we cannot tolerate excess precision.
4127 if (NoExcessFPPrecision)
4128 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
4129 DAG.getValueType(VT));
4134 case ISD::SIGN_EXTEND_INREG:
4135 Result = PromoteOp(Node->getOperand(0));
4136 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Result,
4137 Node->getOperand(1));
4139 case ISD::FP_TO_SINT:
4140 case ISD::FP_TO_UINT:
4141 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4144 Tmp1 = Node->getOperand(0);
4147 // The input result is prerounded, so we don't have to do anything
4149 Tmp1 = PromoteOp(Node->getOperand(0));
4152 // If we're promoting a UINT to a larger size, check to see if the new node
4153 // will be legal. If it isn't, check to see if FP_TO_SINT is legal, since
4154 // we can use that instead. This allows us to generate better code for
4155 // FP_TO_UINT for small destination sizes on targets where FP_TO_UINT is not
4156 // legal, such as PowerPC.
4157 if (Node->getOpcode() == ISD::FP_TO_UINT &&
4158 !TLI.isOperationLegal(ISD::FP_TO_UINT, NVT) &&
4159 (TLI.isOperationLegal(ISD::FP_TO_SINT, NVT) ||
4160 TLI.getOperationAction(ISD::FP_TO_SINT, NVT)==TargetLowering::Custom)){
4161 Result = DAG.getNode(ISD::FP_TO_SINT, NVT, Tmp1);
4163 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
4169 Tmp1 = PromoteOp(Node->getOperand(0));
4170 assert(Tmp1.getValueType() == NVT);
4171 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
4172 // NOTE: we do not have to do any extra rounding here for
4173 // NoExcessFPPrecision, because we know the input will have the appropriate
4174 // precision, and these operations don't modify precision at all.
4180 Tmp1 = PromoteOp(Node->getOperand(0));
4181 assert(Tmp1.getValueType() == NVT);
4182 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
4183 if (NoExcessFPPrecision)
4184 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
4185 DAG.getValueType(VT));
4189 // Promote f32 powi to f64 powi. Note that this could insert a libcall
4190 // directly as well, which may be better.
4191 Tmp1 = PromoteOp(Node->getOperand(0));
4192 assert(Tmp1.getValueType() == NVT);
4193 Result = DAG.getNode(ISD::FPOWI, NVT, Tmp1, Node->getOperand(1));
4194 if (NoExcessFPPrecision)
4195 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
4196 DAG.getValueType(VT));
4200 case ISD::ATOMIC_CMP_SWAP: {
4201 AtomicSDNode* AtomNode = cast<AtomicSDNode>(Node);
4202 Tmp2 = PromoteOp(Node->getOperand(2));
4203 Tmp3 = PromoteOp(Node->getOperand(3));
4204 Result = DAG.getAtomic(Node->getOpcode(), AtomNode->getChain(),
4205 AtomNode->getBasePtr(), Tmp2, Tmp3,
4206 AtomNode->getSrcValue(),
4207 AtomNode->getAlignment());
4208 // Remember that we legalized the chain.
4209 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
4212 case ISD::ATOMIC_LOAD_ADD:
4213 case ISD::ATOMIC_LOAD_SUB:
4214 case ISD::ATOMIC_LOAD_AND:
4215 case ISD::ATOMIC_LOAD_OR:
4216 case ISD::ATOMIC_LOAD_XOR:
4217 case ISD::ATOMIC_LOAD_NAND:
4218 case ISD::ATOMIC_LOAD_MIN:
4219 case ISD::ATOMIC_LOAD_MAX:
4220 case ISD::ATOMIC_LOAD_UMIN:
4221 case ISD::ATOMIC_LOAD_UMAX:
4222 case ISD::ATOMIC_SWAP: {
4223 AtomicSDNode* AtomNode = cast<AtomicSDNode>(Node);
4224 Tmp2 = PromoteOp(Node->getOperand(2));
4225 Result = DAG.getAtomic(Node->getOpcode(), AtomNode->getChain(),
4226 AtomNode->getBasePtr(), Tmp2,
4227 AtomNode->getSrcValue(),
4228 AtomNode->getAlignment());
4229 // Remember that we legalized the chain.
4230 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
4240 // The input may have strange things in the top bits of the registers, but
4241 // these operations don't care. They may have weird bits going out, but
4242 // that too is okay if they are integer operations.
4243 Tmp1 = PromoteOp(Node->getOperand(0));
4244 Tmp2 = PromoteOp(Node->getOperand(1));
4245 assert(Tmp1.getValueType() == NVT && Tmp2.getValueType() == NVT);
4246 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
4251 Tmp1 = PromoteOp(Node->getOperand(0));
4252 Tmp2 = PromoteOp(Node->getOperand(1));
4253 assert(Tmp1.getValueType() == NVT && Tmp2.getValueType() == NVT);
4254 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
4256 // Floating point operations will give excess precision that we may not be
4257 // able to tolerate. If we DO allow excess precision, just leave it,
4258 // otherwise excise it.
4259 // FIXME: Why would we need to round FP ops more than integer ones?
4260 // Is Round(Add(Add(A,B),C)) != Round(Add(Round(Add(A,B)), C))
4261 if (NoExcessFPPrecision)
4262 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
4263 DAG.getValueType(VT));
4268 // These operators require that their input be sign extended.
4269 Tmp1 = PromoteOp(Node->getOperand(0));
4270 Tmp2 = PromoteOp(Node->getOperand(1));
4271 if (NVT.isInteger()) {
4272 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1,
4273 DAG.getValueType(VT));
4274 Tmp2 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp2,
4275 DAG.getValueType(VT));
4277 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
4279 // Perform FP_ROUND: this is probably overly pessimistic.
4280 if (NVT.isFloatingPoint() && NoExcessFPPrecision)
4281 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
4282 DAG.getValueType(VT));
4286 case ISD::FCOPYSIGN:
4287 // These operators require that their input be fp extended.
4288 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4289 case Expand: assert(0 && "not implemented");
4290 case Legal: Tmp1 = LegalizeOp(Node->getOperand(0)); break;
4291 case Promote: Tmp1 = PromoteOp(Node->getOperand(0)); break;
4293 switch (getTypeAction(Node->getOperand(1).getValueType())) {
4294 case Expand: assert(0 && "not implemented");
4295 case Legal: Tmp2 = LegalizeOp(Node->getOperand(1)); break;
4296 case Promote: Tmp2 = PromoteOp(Node->getOperand(1)); break;
4298 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
4300 // Perform FP_ROUND: this is probably overly pessimistic.
4301 if (NoExcessFPPrecision && Node->getOpcode() != ISD::FCOPYSIGN)
4302 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
4303 DAG.getValueType(VT));
4308 // These operators require that their input be zero extended.
4309 Tmp1 = PromoteOp(Node->getOperand(0));
4310 Tmp2 = PromoteOp(Node->getOperand(1));
4311 assert(NVT.isInteger() && "Operators don't apply to FP!");
4312 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT);
4313 Tmp2 = DAG.getZeroExtendInReg(Tmp2, VT);
4314 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
4318 Tmp1 = PromoteOp(Node->getOperand(0));
4319 Result = DAG.getNode(ISD::SHL, NVT, Tmp1, Node->getOperand(1));
4322 // The input value must be properly sign extended.
4323 Tmp1 = PromoteOp(Node->getOperand(0));
4324 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1,
4325 DAG.getValueType(VT));
4326 Result = DAG.getNode(ISD::SRA, NVT, Tmp1, Node->getOperand(1));
4329 // The input value must be properly zero extended.
4330 Tmp1 = PromoteOp(Node->getOperand(0));
4331 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT);
4332 Result = DAG.getNode(ISD::SRL, NVT, Tmp1, Node->getOperand(1));
4336 Tmp1 = Node->getOperand(0); // Get the chain.
4337 Tmp2 = Node->getOperand(1); // Get the pointer.
4338 if (TLI.getOperationAction(ISD::VAARG, VT) == TargetLowering::Custom) {
4339 Tmp3 = DAG.getVAArg(VT, Tmp1, Tmp2, Node->getOperand(2));
4340 Result = TLI.LowerOperation(Tmp3, DAG);
4342 const Value *V = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
4343 SDOperand VAList = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp2, V, 0);
4344 // Increment the pointer, VAList, to the next vaarg
4345 Tmp3 = DAG.getNode(ISD::ADD, TLI.getPointerTy(), VAList,
4346 DAG.getConstant(VT.getSizeInBits()/8,
4347 TLI.getPointerTy()));
4348 // Store the incremented VAList to the legalized pointer
4349 Tmp3 = DAG.getStore(VAList.getValue(1), Tmp3, Tmp2, V, 0);
4350 // Load the actual argument out of the pointer VAList
4351 Result = DAG.getExtLoad(ISD::EXTLOAD, NVT, Tmp3, VAList, NULL, 0, VT);
4353 // Remember that we legalized the chain.
4354 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
4358 LoadSDNode *LD = cast<LoadSDNode>(Node);
4359 ISD::LoadExtType ExtType = ISD::isNON_EXTLoad(Node)
4360 ? ISD::EXTLOAD : LD->getExtensionType();
4361 Result = DAG.getExtLoad(ExtType, NVT,
4362 LD->getChain(), LD->getBasePtr(),
4363 LD->getSrcValue(), LD->getSrcValueOffset(),
4366 LD->getAlignment());
4367 // Remember that we legalized the chain.
4368 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
4372 Tmp2 = PromoteOp(Node->getOperand(1)); // Legalize the op0
4373 Tmp3 = PromoteOp(Node->getOperand(2)); // Legalize the op1
4375 MVT VT2 = Tmp2.getValueType();
4376 assert(VT2 == Tmp3.getValueType()
4377 && "PromoteOp SELECT: Operands 2 and 3 ValueTypes don't match");
4378 // Ensure that the resulting node is at least the same size as the operands'
4379 // value types, because we cannot assume that TLI.getSetCCValueType() is
4381 Result = DAG.getNode(ISD::SELECT, VT2, Node->getOperand(0), Tmp2, Tmp3);
4384 case ISD::SELECT_CC:
4385 Tmp2 = PromoteOp(Node->getOperand(2)); // True
4386 Tmp3 = PromoteOp(Node->getOperand(3)); // False
4387 Result = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0),
4388 Node->getOperand(1), Tmp2, Tmp3, Node->getOperand(4));
4391 Tmp1 = Node->getOperand(0);
4392 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1);
4393 Tmp1 = DAG.getNode(ISD::BSWAP, NVT, Tmp1);
4394 Result = DAG.getNode(ISD::SRL, NVT, Tmp1,
4395 DAG.getConstant(NVT.getSizeInBits() -
4397 TLI.getShiftAmountTy()));
4402 // Zero extend the argument
4403 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Node->getOperand(0));
4404 // Perform the larger operation, then subtract if needed.
4405 Tmp1 = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
4406 switch(Node->getOpcode()) {
4411 // if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT)
4412 Tmp2 = DAG.getSetCC(TLI.getSetCCResultType(Tmp1), Tmp1,
4413 DAG.getConstant(NVT.getSizeInBits(), NVT),
4415 Result = DAG.getNode(ISD::SELECT, NVT, Tmp2,
4416 DAG.getConstant(VT.getSizeInBits(), NVT), Tmp1);
4419 //Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT))
4420 Result = DAG.getNode(ISD::SUB, NVT, Tmp1,
4421 DAG.getConstant(NVT.getSizeInBits() -
4422 VT.getSizeInBits(), NVT));
4426 case ISD::EXTRACT_SUBVECTOR:
4427 Result = PromoteOp(ExpandEXTRACT_SUBVECTOR(Op));
4429 case ISD::EXTRACT_VECTOR_ELT:
4430 Result = PromoteOp(ExpandEXTRACT_VECTOR_ELT(Op));
4434 assert(Result.Val && "Didn't set a result!");
4436 // Make sure the result is itself legal.
4437 Result = LegalizeOp(Result);
4439 // Remember that we promoted this!
4440 AddPromotedOperand(Op, Result);
4444 /// ExpandEXTRACT_VECTOR_ELT - Expand an EXTRACT_VECTOR_ELT operation into
4445 /// a legal EXTRACT_VECTOR_ELT operation, scalar code, or memory traffic,
4446 /// based on the vector type. The return type of this matches the element type
4447 /// of the vector, which may not be legal for the target.
4448 SDOperand SelectionDAGLegalize::ExpandEXTRACT_VECTOR_ELT(SDOperand Op) {
4449 // We know that operand #0 is the Vec vector. If the index is a constant
4450 // or if the invec is a supported hardware type, we can use it. Otherwise,
4451 // lower to a store then an indexed load.
4452 SDOperand Vec = Op.getOperand(0);
4453 SDOperand Idx = Op.getOperand(1);
4455 MVT TVT = Vec.getValueType();
4456 unsigned NumElems = TVT.getVectorNumElements();
4458 switch (TLI.getOperationAction(ISD::EXTRACT_VECTOR_ELT, TVT)) {
4459 default: assert(0 && "This action is not supported yet!");
4460 case TargetLowering::Custom: {
4461 Vec = LegalizeOp(Vec);
4462 Op = DAG.UpdateNodeOperands(Op, Vec, Idx);
4463 SDOperand Tmp3 = TLI.LowerOperation(Op, DAG);
4468 case TargetLowering::Legal:
4469 if (isTypeLegal(TVT)) {
4470 Vec = LegalizeOp(Vec);
4471 Op = DAG.UpdateNodeOperands(Op, Vec, Idx);
4475 case TargetLowering::Expand:
4479 if (NumElems == 1) {
4480 // This must be an access of the only element. Return it.
4481 Op = ScalarizeVectorOp(Vec);
4482 } else if (!TLI.isTypeLegal(TVT) && isa<ConstantSDNode>(Idx)) {
4483 unsigned NumLoElts = 1 << Log2_32(NumElems-1);
4484 ConstantSDNode *CIdx = cast<ConstantSDNode>(Idx);
4486 SplitVectorOp(Vec, Lo, Hi);
4487 if (CIdx->getValue() < NumLoElts) {
4491 Idx = DAG.getConstant(CIdx->getValue() - NumLoElts,
4492 Idx.getValueType());
4495 // It's now an extract from the appropriate high or low part. Recurse.
4496 Op = DAG.UpdateNodeOperands(Op, Vec, Idx);
4497 Op = ExpandEXTRACT_VECTOR_ELT(Op);
4499 // Store the value to a temporary stack slot, then LOAD the scalar
4500 // element back out.
4501 SDOperand StackPtr = DAG.CreateStackTemporary(Vec.getValueType());
4502 SDOperand Ch = DAG.getStore(DAG.getEntryNode(), Vec, StackPtr, NULL, 0);
4504 // Add the offset to the index.
4505 unsigned EltSize = Op.getValueType().getSizeInBits()/8;
4506 Idx = DAG.getNode(ISD::MUL, Idx.getValueType(), Idx,
4507 DAG.getConstant(EltSize, Idx.getValueType()));
4509 if (Idx.getValueType().bitsGT(TLI.getPointerTy()))
4510 Idx = DAG.getNode(ISD::TRUNCATE, TLI.getPointerTy(), Idx);
4512 Idx = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(), Idx);
4514 StackPtr = DAG.getNode(ISD::ADD, Idx.getValueType(), Idx, StackPtr);
4516 Op = DAG.getLoad(Op.getValueType(), Ch, StackPtr, NULL, 0);
4521 /// ExpandEXTRACT_SUBVECTOR - Expand a EXTRACT_SUBVECTOR operation. For now
4522 /// we assume the operation can be split if it is not already legal.
4523 SDOperand SelectionDAGLegalize::ExpandEXTRACT_SUBVECTOR(SDOperand Op) {
4524 // We know that operand #0 is the Vec vector. For now we assume the index
4525 // is a constant and that the extracted result is a supported hardware type.
4526 SDOperand Vec = Op.getOperand(0);
4527 SDOperand Idx = LegalizeOp(Op.getOperand(1));
4529 unsigned NumElems = Vec.getValueType().getVectorNumElements();
4531 if (NumElems == Op.getValueType().getVectorNumElements()) {
4532 // This must be an access of the desired vector length. Return it.
4536 ConstantSDNode *CIdx = cast<ConstantSDNode>(Idx);
4538 SplitVectorOp(Vec, Lo, Hi);
4539 if (CIdx->getValue() < NumElems/2) {
4543 Idx = DAG.getConstant(CIdx->getValue() - NumElems/2, Idx.getValueType());
4546 // It's now an extract from the appropriate high or low part. Recurse.
4547 Op = DAG.UpdateNodeOperands(Op, Vec, Idx);
4548 return ExpandEXTRACT_SUBVECTOR(Op);
4551 /// LegalizeSetCCOperands - Attempts to create a legal LHS and RHS for a SETCC
4552 /// with condition CC on the current target. This usually involves legalizing
4553 /// or promoting the arguments. In the case where LHS and RHS must be expanded,
4554 /// there may be no choice but to create a new SetCC node to represent the
4555 /// legalized value of setcc lhs, rhs. In this case, the value is returned in
4556 /// LHS, and the SDOperand returned in RHS has a nil SDNode value.
4557 void SelectionDAGLegalize::LegalizeSetCCOperands(SDOperand &LHS,
4560 SDOperand Tmp1, Tmp2, Tmp3, Result;
4562 switch (getTypeAction(LHS.getValueType())) {
4564 Tmp1 = LegalizeOp(LHS); // LHS
4565 Tmp2 = LegalizeOp(RHS); // RHS
4568 Tmp1 = PromoteOp(LHS); // LHS
4569 Tmp2 = PromoteOp(RHS); // RHS
4571 // If this is an FP compare, the operands have already been extended.
4572 if (LHS.getValueType().isInteger()) {
4573 MVT VT = LHS.getValueType();
4574 MVT NVT = TLI.getTypeToTransformTo(VT);
4576 // Otherwise, we have to insert explicit sign or zero extends. Note
4577 // that we could insert sign extends for ALL conditions, but zero extend
4578 // is cheaper on many machines (an AND instead of two shifts), so prefer
4580 switch (cast<CondCodeSDNode>(CC)->get()) {
4581 default: assert(0 && "Unknown integer comparison!");
4588 // ALL of these operations will work if we either sign or zero extend
4589 // the operands (including the unsigned comparisons!). Zero extend is
4590 // usually a simpler/cheaper operation, so prefer it.
4591 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT);
4592 Tmp2 = DAG.getZeroExtendInReg(Tmp2, VT);
4598 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1,
4599 DAG.getValueType(VT));
4600 Tmp2 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp2,
4601 DAG.getValueType(VT));
4607 MVT VT = LHS.getValueType();
4608 if (VT == MVT::f32 || VT == MVT::f64) {
4609 // Expand into one or more soft-fp libcall(s).
4610 RTLIB::Libcall LC1 = RTLIB::UNKNOWN_LIBCALL, LC2 = RTLIB::UNKNOWN_LIBCALL;
4611 switch (cast<CondCodeSDNode>(CC)->get()) {
4614 LC1 = (VT == MVT::f32) ? RTLIB::OEQ_F32 : RTLIB::OEQ_F64;
4618 LC1 = (VT == MVT::f32) ? RTLIB::UNE_F32 : RTLIB::UNE_F64;
4622 LC1 = (VT == MVT::f32) ? RTLIB::OGE_F32 : RTLIB::OGE_F64;
4626 LC1 = (VT == MVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64;
4630 LC1 = (VT == MVT::f32) ? RTLIB::OLE_F32 : RTLIB::OLE_F64;
4634 LC1 = (VT == MVT::f32) ? RTLIB::OGT_F32 : RTLIB::OGT_F64;
4637 LC1 = (VT == MVT::f32) ? RTLIB::UO_F32 : RTLIB::UO_F64;
4640 LC1 = (VT == MVT::f32) ? RTLIB::O_F32 : RTLIB::O_F64;
4643 LC1 = (VT == MVT::f32) ? RTLIB::UO_F32 : RTLIB::UO_F64;
4644 switch (cast<CondCodeSDNode>(CC)->get()) {
4646 // SETONE = SETOLT | SETOGT
4647 LC1 = (VT == MVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64;
4650 LC2 = (VT == MVT::f32) ? RTLIB::OGT_F32 : RTLIB::OGT_F64;
4653 LC2 = (VT == MVT::f32) ? RTLIB::OGE_F32 : RTLIB::OGE_F64;
4656 LC2 = (VT == MVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64;
4659 LC2 = (VT == MVT::f32) ? RTLIB::OLE_F32 : RTLIB::OLE_F64;
4662 LC2 = (VT == MVT::f32) ? RTLIB::OEQ_F32 : RTLIB::OEQ_F64;
4664 default: assert(0 && "Unsupported FP setcc!");
4669 SDOperand Ops[2] = { LHS, RHS };
4670 Tmp1 = ExpandLibCall(LC1, DAG.getMergeValues(Ops, 2).Val,
4671 false /*sign irrelevant*/, Dummy);
4672 Tmp2 = DAG.getConstant(0, MVT::i32);
4673 CC = DAG.getCondCode(TLI.getCmpLibcallCC(LC1));
4674 if (LC2 != RTLIB::UNKNOWN_LIBCALL) {
4675 Tmp1 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultType(Tmp1), Tmp1, Tmp2,
4677 LHS = ExpandLibCall(LC2, DAG.getMergeValues(Ops, 2).Val,
4678 false /*sign irrelevant*/, Dummy);
4679 Tmp2 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultType(LHS), LHS, Tmp2,
4680 DAG.getCondCode(TLI.getCmpLibcallCC(LC2)));
4681 Tmp1 = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp2);
4684 LHS = LegalizeOp(Tmp1);
4689 SDOperand LHSLo, LHSHi, RHSLo, RHSHi;
4690 ExpandOp(LHS, LHSLo, LHSHi);
4691 ExpandOp(RHS, RHSLo, RHSHi);
4692 ISD::CondCode CCCode = cast<CondCodeSDNode>(CC)->get();
4694 if (VT==MVT::ppcf128) {
4695 // FIXME: This generated code sucks. We want to generate
4696 // FCMP crN, hi1, hi2
4698 // FCMP crN, lo1, lo2
4699 // The following can be improved, but not that much.
4700 Tmp1 = DAG.getSetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi, ISD::SETEQ);
4701 Tmp2 = DAG.getSetCC(TLI.getSetCCResultType(LHSLo), LHSLo, RHSLo, CCCode);
4702 Tmp3 = DAG.getNode(ISD::AND, Tmp1.getValueType(), Tmp1, Tmp2);
4703 Tmp1 = DAG.getSetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi, ISD::SETNE);
4704 Tmp2 = DAG.getSetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi, CCCode);
4705 Tmp1 = DAG.getNode(ISD::AND, Tmp1.getValueType(), Tmp1, Tmp2);
4706 Tmp1 = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp3);
4715 if (ConstantSDNode *RHSCST = dyn_cast<ConstantSDNode>(RHSLo))
4716 if (RHSCST->isAllOnesValue()) {
4717 // Comparison to -1.
4718 Tmp1 = DAG.getNode(ISD::AND, LHSLo.getValueType(), LHSLo, LHSHi);
4723 Tmp1 = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSLo, RHSLo);
4724 Tmp2 = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSHi, RHSHi);
4725 Tmp1 = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp2);
4726 Tmp2 = DAG.getConstant(0, Tmp1.getValueType());
4729 // If this is a comparison of the sign bit, just look at the top part.
4731 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(RHS))
4732 if ((cast<CondCodeSDNode>(CC)->get() == ISD::SETLT &&
4733 CST->isNullValue()) || // X < 0
4734 (cast<CondCodeSDNode>(CC)->get() == ISD::SETGT &&
4735 CST->isAllOnesValue())) { // X > -1
4741 // FIXME: This generated code sucks.
4742 ISD::CondCode LowCC;
4744 default: assert(0 && "Unknown integer setcc!");
4746 case ISD::SETULT: LowCC = ISD::SETULT; break;
4748 case ISD::SETUGT: LowCC = ISD::SETUGT; break;
4750 case ISD::SETULE: LowCC = ISD::SETULE; break;
4752 case ISD::SETUGE: LowCC = ISD::SETUGE; break;
4755 // Tmp1 = lo(op1) < lo(op2) // Always unsigned comparison
4756 // Tmp2 = hi(op1) < hi(op2) // Signedness depends on operands
4757 // dest = hi(op1) == hi(op2) ? Tmp1 : Tmp2;
4759 // NOTE: on targets without efficient SELECT of bools, we can always use
4760 // this identity: (B1 ? B2 : B3) --> (B1 & B2)|(!B1&B3)
4761 TargetLowering::DAGCombinerInfo DagCombineInfo(DAG, false, true, NULL);
4762 Tmp1 = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSLo), LHSLo, RHSLo,
4763 LowCC, false, DagCombineInfo);
4765 Tmp1 = DAG.getSetCC(TLI.getSetCCResultType(LHSLo), LHSLo, RHSLo, LowCC);
4766 Tmp2 = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi,
4767 CCCode, false, DagCombineInfo);
4769 Tmp2 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultType(LHSHi), LHSHi,
4772 ConstantSDNode *Tmp1C = dyn_cast<ConstantSDNode>(Tmp1.Val);
4773 ConstantSDNode *Tmp2C = dyn_cast<ConstantSDNode>(Tmp2.Val);
4774 if ((Tmp1C && Tmp1C->isNullValue()) ||
4775 (Tmp2C && Tmp2C->isNullValue() &&
4776 (CCCode == ISD::SETLE || CCCode == ISD::SETGE ||
4777 CCCode == ISD::SETUGE || CCCode == ISD::SETULE)) ||
4778 (Tmp2C && Tmp2C->getAPIntValue() == 1 &&
4779 (CCCode == ISD::SETLT || CCCode == ISD::SETGT ||
4780 CCCode == ISD::SETUGT || CCCode == ISD::SETULT))) {
4781 // low part is known false, returns high part.
4782 // For LE / GE, if high part is known false, ignore the low part.
4783 // For LT / GT, if high part is known true, ignore the low part.
4787 Result = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi,
4788 ISD::SETEQ, false, DagCombineInfo);
4790 Result=DAG.getSetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi,
4792 Result = LegalizeOp(DAG.getNode(ISD::SELECT, Tmp1.getValueType(),
4793 Result, Tmp1, Tmp2));
4804 /// EmitStackConvert - Emit a store/load combination to the stack. This stores
4805 /// SrcOp to a stack slot of type SlotVT, truncating it if needed. It then does
4806 /// a load from the stack slot to DestVT, extending it if needed.
4807 /// The resultant code need not be legal.
4808 SDOperand SelectionDAGLegalize::EmitStackConvert(SDOperand SrcOp,
4811 // Create the stack frame object.
4812 unsigned SrcAlign = TLI.getTargetData()->getPrefTypeAlignment(
4813 SrcOp.getValueType().getTypeForMVT());
4814 SDOperand FIPtr = DAG.CreateStackTemporary(SlotVT, SrcAlign);
4816 FrameIndexSDNode *StackPtrFI = cast<FrameIndexSDNode>(FIPtr);
4817 int SPFI = StackPtrFI->getIndex();
4819 unsigned SrcSize = SrcOp.getValueType().getSizeInBits();
4820 unsigned SlotSize = SlotVT.getSizeInBits();
4821 unsigned DestSize = DestVT.getSizeInBits();
4822 unsigned DestAlign = TLI.getTargetData()->getPrefTypeAlignment(
4823 DestVT.getTypeForMVT());
4825 // Emit a store to the stack slot. Use a truncstore if the input value is
4826 // later than DestVT.
4829 if (SrcSize > SlotSize)
4830 Store = DAG.getTruncStore(DAG.getEntryNode(), SrcOp, FIPtr,
4831 PseudoSourceValue::getFixedStack(SPFI), 0,
4832 SlotVT, false, SrcAlign);
4834 assert(SrcSize == SlotSize && "Invalid store");
4835 Store = DAG.getStore(DAG.getEntryNode(), SrcOp, FIPtr,
4836 PseudoSourceValue::getFixedStack(SPFI), 0,
4840 // Result is a load from the stack slot.
4841 if (SlotSize == DestSize)
4842 return DAG.getLoad(DestVT, Store, FIPtr, NULL, 0, false, DestAlign);
4844 assert(SlotSize < DestSize && "Unknown extension!");
4845 return DAG.getExtLoad(ISD::EXTLOAD, DestVT, Store, FIPtr, NULL, 0, SlotVT,
4849 SDOperand SelectionDAGLegalize::ExpandSCALAR_TO_VECTOR(SDNode *Node) {
4850 // Create a vector sized/aligned stack slot, store the value to element #0,
4851 // then load the whole vector back out.
4852 SDOperand StackPtr = DAG.CreateStackTemporary(Node->getValueType(0));
4854 FrameIndexSDNode *StackPtrFI = cast<FrameIndexSDNode>(StackPtr);
4855 int SPFI = StackPtrFI->getIndex();
4857 SDOperand Ch = DAG.getStore(DAG.getEntryNode(), Node->getOperand(0), StackPtr,
4858 PseudoSourceValue::getFixedStack(SPFI), 0);
4859 return DAG.getLoad(Node->getValueType(0), Ch, StackPtr,
4860 PseudoSourceValue::getFixedStack(SPFI), 0);
4864 /// ExpandBUILD_VECTOR - Expand a BUILD_VECTOR node on targets that don't
4865 /// support the operation, but do support the resultant vector type.
4866 SDOperand SelectionDAGLegalize::ExpandBUILD_VECTOR(SDNode *Node) {
4868 // If the only non-undef value is the low element, turn this into a
4869 // SCALAR_TO_VECTOR node. If this is { X, X, X, X }, determine X.
4870 unsigned NumElems = Node->getNumOperands();
4871 bool isOnlyLowElement = true;
4872 SDOperand SplatValue = Node->getOperand(0);
4874 // FIXME: it would be far nicer to change this into map<SDOperand,uint64_t>
4875 // and use a bitmask instead of a list of elements.
4876 std::map<SDOperand, std::vector<unsigned> > Values;
4877 Values[SplatValue].push_back(0);
4878 bool isConstant = true;
4879 if (!isa<ConstantFPSDNode>(SplatValue) && !isa<ConstantSDNode>(SplatValue) &&
4880 SplatValue.getOpcode() != ISD::UNDEF)
4883 for (unsigned i = 1; i < NumElems; ++i) {
4884 SDOperand V = Node->getOperand(i);
4885 Values[V].push_back(i);
4886 if (V.getOpcode() != ISD::UNDEF)
4887 isOnlyLowElement = false;
4888 if (SplatValue != V)
4889 SplatValue = SDOperand(0,0);
4891 // If this isn't a constant element or an undef, we can't use a constant
4893 if (!isa<ConstantFPSDNode>(V) && !isa<ConstantSDNode>(V) &&
4894 V.getOpcode() != ISD::UNDEF)
4898 if (isOnlyLowElement) {
4899 // If the low element is an undef too, then this whole things is an undef.
4900 if (Node->getOperand(0).getOpcode() == ISD::UNDEF)
4901 return DAG.getNode(ISD::UNDEF, Node->getValueType(0));
4902 // Otherwise, turn this into a scalar_to_vector node.
4903 return DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0),
4904 Node->getOperand(0));
4907 // If all elements are constants, create a load from the constant pool.
4909 MVT VT = Node->getValueType(0);
4910 std::vector<Constant*> CV;
4911 for (unsigned i = 0, e = NumElems; i != e; ++i) {
4912 if (ConstantFPSDNode *V =
4913 dyn_cast<ConstantFPSDNode>(Node->getOperand(i))) {
4914 CV.push_back(ConstantFP::get(V->getValueAPF()));
4915 } else if (ConstantSDNode *V =
4916 dyn_cast<ConstantSDNode>(Node->getOperand(i))) {
4917 CV.push_back(ConstantInt::get(V->getAPIntValue()));
4919 assert(Node->getOperand(i).getOpcode() == ISD::UNDEF);
4921 Node->getOperand(0).getValueType().getTypeForMVT();
4922 CV.push_back(UndefValue::get(OpNTy));
4925 Constant *CP = ConstantVector::get(CV);
4926 SDOperand CPIdx = DAG.getConstantPool(CP, TLI.getPointerTy());
4927 return DAG.getLoad(VT, DAG.getEntryNode(), CPIdx,
4928 PseudoSourceValue::getConstantPool(), 0);
4931 if (SplatValue.Val) { // Splat of one value?
4932 // Build the shuffle constant vector: <0, 0, 0, 0>
4933 MVT MaskVT = MVT::getIntVectorWithNumElements(NumElems);
4934 SDOperand Zero = DAG.getConstant(0, MaskVT.getVectorElementType());
4935 std::vector<SDOperand> ZeroVec(NumElems, Zero);
4936 SDOperand SplatMask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
4937 &ZeroVec[0], ZeroVec.size());
4939 // If the target supports VECTOR_SHUFFLE and this shuffle mask, use it.
4940 if (isShuffleLegal(Node->getValueType(0), SplatMask)) {
4941 // Get the splatted value into the low element of a vector register.
4942 SDOperand LowValVec =
4943 DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0), SplatValue);
4945 // Return shuffle(LowValVec, undef, <0,0,0,0>)
4946 return DAG.getNode(ISD::VECTOR_SHUFFLE, Node->getValueType(0), LowValVec,
4947 DAG.getNode(ISD::UNDEF, Node->getValueType(0)),
4952 // If there are only two unique elements, we may be able to turn this into a
4954 if (Values.size() == 2) {
4955 // Get the two values in deterministic order.
4956 SDOperand Val1 = Node->getOperand(1);
4958 std::map<SDOperand, std::vector<unsigned> >::iterator MI = Values.begin();
4959 if (MI->first != Val1)
4962 Val2 = (++MI)->first;
4964 // If Val1 is an undef, make sure end ends up as Val2, to ensure that our
4965 // vector shuffle has the undef vector on the RHS.
4966 if (Val1.getOpcode() == ISD::UNDEF)
4967 std::swap(Val1, Val2);
4969 // Build the shuffle constant vector: e.g. <0, 4, 0, 4>
4970 MVT MaskVT = MVT::getIntVectorWithNumElements(NumElems);
4971 MVT MaskEltVT = MaskVT.getVectorElementType();
4972 std::vector<SDOperand> MaskVec(NumElems);
4974 // Set elements of the shuffle mask for Val1.
4975 std::vector<unsigned> &Val1Elts = Values[Val1];
4976 for (unsigned i = 0, e = Val1Elts.size(); i != e; ++i)
4977 MaskVec[Val1Elts[i]] = DAG.getConstant(0, MaskEltVT);
4979 // Set elements of the shuffle mask for Val2.
4980 std::vector<unsigned> &Val2Elts = Values[Val2];
4981 for (unsigned i = 0, e = Val2Elts.size(); i != e; ++i)
4982 if (Val2.getOpcode() != ISD::UNDEF)
4983 MaskVec[Val2Elts[i]] = DAG.getConstant(NumElems, MaskEltVT);
4985 MaskVec[Val2Elts[i]] = DAG.getNode(ISD::UNDEF, MaskEltVT);
4987 SDOperand ShuffleMask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
4988 &MaskVec[0], MaskVec.size());
4990 // If the target supports SCALAR_TO_VECTOR and this shuffle mask, use it.
4991 if (TLI.isOperationLegal(ISD::SCALAR_TO_VECTOR, Node->getValueType(0)) &&
4992 isShuffleLegal(Node->getValueType(0), ShuffleMask)) {
4993 Val1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0), Val1);
4994 Val2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0), Val2);
4995 SDOperand Ops[] = { Val1, Val2, ShuffleMask };
4997 // Return shuffle(LoValVec, HiValVec, <0,1,0,1>)
4998 return DAG.getNode(ISD::VECTOR_SHUFFLE, Node->getValueType(0), Ops, 3);
5002 // Otherwise, we can't handle this case efficiently. Allocate a sufficiently
5003 // aligned object on the stack, store each element into it, then load
5004 // the result as a vector.
5005 MVT VT = Node->getValueType(0);
5006 // Create the stack frame object.
5007 SDOperand FIPtr = DAG.CreateStackTemporary(VT);
5009 // Emit a store of each element to the stack slot.
5010 SmallVector<SDOperand, 8> Stores;
5011 unsigned TypeByteSize = Node->getOperand(0).getValueType().getSizeInBits()/8;
5012 // Store (in the right endianness) the elements to memory.
5013 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
5014 // Ignore undef elements.
5015 if (Node->getOperand(i).getOpcode() == ISD::UNDEF) continue;
5017 unsigned Offset = TypeByteSize*i;
5019 SDOperand Idx = DAG.getConstant(Offset, FIPtr.getValueType());
5020 Idx = DAG.getNode(ISD::ADD, FIPtr.getValueType(), FIPtr, Idx);
5022 Stores.push_back(DAG.getStore(DAG.getEntryNode(), Node->getOperand(i), Idx,
5026 SDOperand StoreChain;
5027 if (!Stores.empty()) // Not all undef elements?
5028 StoreChain = DAG.getNode(ISD::TokenFactor, MVT::Other,
5029 &Stores[0], Stores.size());
5031 StoreChain = DAG.getEntryNode();
5033 // Result is a load from the stack slot.
5034 return DAG.getLoad(VT, StoreChain, FIPtr, NULL, 0);
5037 void SelectionDAGLegalize::ExpandShiftParts(unsigned NodeOp,
5038 SDOperand Op, SDOperand Amt,
5039 SDOperand &Lo, SDOperand &Hi) {
5040 // Expand the subcomponents.
5041 SDOperand LHSL, LHSH;
5042 ExpandOp(Op, LHSL, LHSH);
5044 SDOperand Ops[] = { LHSL, LHSH, Amt };
5045 MVT VT = LHSL.getValueType();
5046 Lo = DAG.getNode(NodeOp, DAG.getNodeValueTypes(VT, VT), 2, Ops, 3);
5047 Hi = Lo.getValue(1);
5051 /// ExpandShift - Try to find a clever way to expand this shift operation out to
5052 /// smaller elements. If we can't find a way that is more efficient than a
5053 /// libcall on this target, return false. Otherwise, return true with the
5054 /// low-parts expanded into Lo and Hi.
5055 bool SelectionDAGLegalize::ExpandShift(unsigned Opc, SDOperand Op,SDOperand Amt,
5056 SDOperand &Lo, SDOperand &Hi) {
5057 assert((Opc == ISD::SHL || Opc == ISD::SRA || Opc == ISD::SRL) &&
5058 "This is not a shift!");
5060 MVT NVT = TLI.getTypeToTransformTo(Op.getValueType());
5061 SDOperand ShAmt = LegalizeOp(Amt);
5062 MVT ShTy = ShAmt.getValueType();
5063 unsigned ShBits = ShTy.getSizeInBits();
5064 unsigned VTBits = Op.getValueType().getSizeInBits();
5065 unsigned NVTBits = NVT.getSizeInBits();
5067 // Handle the case when Amt is an immediate.
5068 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Amt.Val)) {
5069 unsigned Cst = CN->getValue();
5070 // Expand the incoming operand to be shifted, so that we have its parts
5072 ExpandOp(Op, InL, InH);
5076 Lo = DAG.getConstant(0, NVT);
5077 Hi = DAG.getConstant(0, NVT);
5078 } else if (Cst > NVTBits) {
5079 Lo = DAG.getConstant(0, NVT);
5080 Hi = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Cst-NVTBits,ShTy));
5081 } else if (Cst == NVTBits) {
5082 Lo = DAG.getConstant(0, NVT);
5085 Lo = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Cst, ShTy));
5086 Hi = DAG.getNode(ISD::OR, NVT,
5087 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(Cst, ShTy)),
5088 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(NVTBits-Cst, ShTy)));
5093 Lo = DAG.getConstant(0, NVT);
5094 Hi = DAG.getConstant(0, NVT);
5095 } else if (Cst > NVTBits) {
5096 Lo = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Cst-NVTBits,ShTy));
5097 Hi = DAG.getConstant(0, NVT);
5098 } else if (Cst == NVTBits) {
5100 Hi = DAG.getConstant(0, NVT);
5102 Lo = DAG.getNode(ISD::OR, NVT,
5103 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(Cst, ShTy)),
5104 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(NVTBits-Cst, ShTy)));
5105 Hi = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Cst, ShTy));
5110 Hi = Lo = DAG.getNode(ISD::SRA, NVT, InH,
5111 DAG.getConstant(NVTBits-1, ShTy));
5112 } else if (Cst > NVTBits) {
5113 Lo = DAG.getNode(ISD::SRA, NVT, InH,
5114 DAG.getConstant(Cst-NVTBits, ShTy));
5115 Hi = DAG.getNode(ISD::SRA, NVT, InH,
5116 DAG.getConstant(NVTBits-1, ShTy));
5117 } else if (Cst == NVTBits) {
5119 Hi = DAG.getNode(ISD::SRA, NVT, InH,
5120 DAG.getConstant(NVTBits-1, ShTy));
5122 Lo = DAG.getNode(ISD::OR, NVT,
5123 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(Cst, ShTy)),
5124 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(NVTBits-Cst, ShTy)));
5125 Hi = DAG.getNode(ISD::SRA, NVT, InH, DAG.getConstant(Cst, ShTy));
5131 // Okay, the shift amount isn't constant. However, if we can tell that it is
5132 // >= 32 or < 32, we can still simplify it, without knowing the actual value.
5133 APInt Mask = APInt::getHighBitsSet(ShBits, ShBits - Log2_32(NVTBits));
5134 APInt KnownZero, KnownOne;
5135 DAG.ComputeMaskedBits(Amt, Mask, KnownZero, KnownOne);
5137 // If we know that if any of the high bits of the shift amount are one, then
5138 // we can do this as a couple of simple shifts.
5139 if (KnownOne.intersects(Mask)) {
5140 // Mask out the high bit, which we know is set.
5141 Amt = DAG.getNode(ISD::AND, Amt.getValueType(), Amt,
5142 DAG.getConstant(~Mask, Amt.getValueType()));
5144 // Expand the incoming operand to be shifted, so that we have its parts
5146 ExpandOp(Op, InL, InH);
5149 Lo = DAG.getConstant(0, NVT); // Low part is zero.
5150 Hi = DAG.getNode(ISD::SHL, NVT, InL, Amt); // High part from Lo part.
5153 Hi = DAG.getConstant(0, NVT); // Hi part is zero.
5154 Lo = DAG.getNode(ISD::SRL, NVT, InH, Amt); // Lo part from Hi part.
5157 Hi = DAG.getNode(ISD::SRA, NVT, InH, // Sign extend high part.
5158 DAG.getConstant(NVTBits-1, Amt.getValueType()));
5159 Lo = DAG.getNode(ISD::SRA, NVT, InH, Amt); // Lo part from Hi part.
5164 // If we know that the high bits of the shift amount are all zero, then we can
5165 // do this as a couple of simple shifts.
5166 if ((KnownZero & Mask) == Mask) {
5168 SDOperand Amt2 = DAG.getNode(ISD::SUB, Amt.getValueType(),
5169 DAG.getConstant(NVTBits, Amt.getValueType()),
5172 // Expand the incoming operand to be shifted, so that we have its parts
5174 ExpandOp(Op, InL, InH);
5177 Lo = DAG.getNode(ISD::SHL, NVT, InL, Amt);
5178 Hi = DAG.getNode(ISD::OR, NVT,
5179 DAG.getNode(ISD::SHL, NVT, InH, Amt),
5180 DAG.getNode(ISD::SRL, NVT, InL, Amt2));
5183 Hi = DAG.getNode(ISD::SRL, NVT, InH, Amt);
5184 Lo = DAG.getNode(ISD::OR, NVT,
5185 DAG.getNode(ISD::SRL, NVT, InL, Amt),
5186 DAG.getNode(ISD::SHL, NVT, InH, Amt2));
5189 Hi = DAG.getNode(ISD::SRA, NVT, InH, Amt);
5190 Lo = DAG.getNode(ISD::OR, NVT,
5191 DAG.getNode(ISD::SRL, NVT, InL, Amt),
5192 DAG.getNode(ISD::SHL, NVT, InH, Amt2));
5201 // ExpandLibCall - Expand a node into a call to a libcall. If the result value
5202 // does not fit into a register, return the lo part and set the hi part to the
5203 // by-reg argument. If it does fit into a single register, return the result
5204 // and leave the Hi part unset.
5205 SDOperand SelectionDAGLegalize::ExpandLibCall(RTLIB::Libcall LC, SDNode *Node,
5206 bool isSigned, SDOperand &Hi) {
5207 assert(!IsLegalizingCall && "Cannot overlap legalization of calls!");
5208 // The input chain to this libcall is the entry node of the function.
5209 // Legalizing the call will automatically add the previous call to the
5211 SDOperand InChain = DAG.getEntryNode();
5213 TargetLowering::ArgListTy Args;
5214 TargetLowering::ArgListEntry Entry;
5215 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
5216 MVT ArgVT = Node->getOperand(i).getValueType();
5217 const Type *ArgTy = ArgVT.getTypeForMVT();
5218 Entry.Node = Node->getOperand(i); Entry.Ty = ArgTy;
5219 Entry.isSExt = isSigned;
5220 Entry.isZExt = !isSigned;
5221 Args.push_back(Entry);
5223 SDOperand Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC),
5224 TLI.getPointerTy());
5226 // Splice the libcall in wherever FindInputOutputChains tells us to.
5227 const Type *RetTy = Node->getValueType(0).getTypeForMVT();
5228 std::pair<SDOperand,SDOperand> CallInfo =
5229 TLI.LowerCallTo(InChain, RetTy, isSigned, !isSigned, false, CallingConv::C,
5230 false, Callee, Args, DAG);
5232 // Legalize the call sequence, starting with the chain. This will advance
5233 // the LastCALLSEQ_END to the legalized version of the CALLSEQ_END node that
5234 // was added by LowerCallTo (guaranteeing proper serialization of calls).
5235 LegalizeOp(CallInfo.second);
5237 switch (getTypeAction(CallInfo.first.getValueType())) {
5238 default: assert(0 && "Unknown thing");
5240 Result = CallInfo.first;
5243 ExpandOp(CallInfo.first, Result, Hi);
5250 /// ExpandIntToFP - Expand a [US]INT_TO_FP operation.
5252 SDOperand SelectionDAGLegalize::
5253 ExpandIntToFP(bool isSigned, MVT DestTy, SDOperand Source) {
5254 MVT SourceVT = Source.getValueType();
5255 bool ExpandSource = getTypeAction(SourceVT) == Expand;
5257 // Special case for i32 source to take advantage of UINTTOFP_I32_F32, etc.
5258 if (!isSigned && SourceVT != MVT::i32) {
5259 // The integer value loaded will be incorrectly if the 'sign bit' of the
5260 // incoming integer is set. To handle this, we dynamically test to see if
5261 // it is set, and, if so, add a fudge factor.
5265 ExpandOp(Source, Lo, Hi);
5266 Source = DAG.getNode(ISD::BUILD_PAIR, SourceVT, Lo, Hi);
5268 // The comparison for the sign bit will use the entire operand.
5272 // If this is unsigned, and not supported, first perform the conversion to
5273 // signed, then adjust the result if the sign bit is set.
5274 SDOperand SignedConv = ExpandIntToFP(true, DestTy, Source);
5276 SDOperand SignSet = DAG.getSetCC(TLI.getSetCCResultType(Hi), Hi,
5277 DAG.getConstant(0, Hi.getValueType()),
5279 SDOperand Zero = DAG.getIntPtrConstant(0), Four = DAG.getIntPtrConstant(4);
5280 SDOperand CstOffset = DAG.getNode(ISD::SELECT, Zero.getValueType(),
5281 SignSet, Four, Zero);
5282 uint64_t FF = 0x5f800000ULL;
5283 if (TLI.isLittleEndian()) FF <<= 32;
5284 static Constant *FudgeFactor = ConstantInt::get(Type::Int64Ty, FF);
5286 SDOperand CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy());
5287 CPIdx = DAG.getNode(ISD::ADD, TLI.getPointerTy(), CPIdx, CstOffset);
5288 SDOperand FudgeInReg;
5289 if (DestTy == MVT::f32)
5290 FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx,
5291 PseudoSourceValue::getConstantPool(), 0);
5292 else if (DestTy.bitsGT(MVT::f32))
5293 // FIXME: Avoid the extend by construction the right constantpool?
5294 FudgeInReg = DAG.getExtLoad(ISD::EXTLOAD, DestTy, DAG.getEntryNode(),
5296 PseudoSourceValue::getConstantPool(), 0,
5299 assert(0 && "Unexpected conversion");
5301 MVT SCVT = SignedConv.getValueType();
5302 if (SCVT != DestTy) {
5303 // Destination type needs to be expanded as well. The FADD now we are
5304 // constructing will be expanded into a libcall.
5305 if (SCVT.getSizeInBits() != DestTy.getSizeInBits()) {
5306 assert(SCVT.getSizeInBits() * 2 == DestTy.getSizeInBits());
5307 SignedConv = DAG.getNode(ISD::BUILD_PAIR, DestTy,
5308 SignedConv, SignedConv.getValue(1));
5310 SignedConv = DAG.getNode(ISD::BIT_CONVERT, DestTy, SignedConv);
5312 return DAG.getNode(ISD::FADD, DestTy, SignedConv, FudgeInReg);
5315 // Check to see if the target has a custom way to lower this. If so, use it.
5316 switch (TLI.getOperationAction(ISD::SINT_TO_FP, SourceVT)) {
5317 default: assert(0 && "This action not implemented for this operation!");
5318 case TargetLowering::Legal:
5319 case TargetLowering::Expand:
5320 break; // This case is handled below.
5321 case TargetLowering::Custom: {
5322 SDOperand NV = TLI.LowerOperation(DAG.getNode(ISD::SINT_TO_FP, DestTy,
5325 return LegalizeOp(NV);
5326 break; // The target decided this was legal after all
5330 // Expand the source, then glue it back together for the call. We must expand
5331 // the source in case it is shared (this pass of legalize must traverse it).
5333 SDOperand SrcLo, SrcHi;
5334 ExpandOp(Source, SrcLo, SrcHi);
5335 Source = DAG.getNode(ISD::BUILD_PAIR, SourceVT, SrcLo, SrcHi);
5338 RTLIB::Libcall LC = isSigned ?
5339 RTLIB::getSINTTOFP(SourceVT, DestTy) :
5340 RTLIB::getUINTTOFP(SourceVT, DestTy);
5341 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unknown int value type");
5343 Source = DAG.getNode(ISD::SINT_TO_FP, DestTy, Source);
5345 SDOperand Result = ExpandLibCall(LC, Source.Val, isSigned, HiPart);
5346 if (Result.getValueType() != DestTy && HiPart.Val)
5347 Result = DAG.getNode(ISD::BUILD_PAIR, DestTy, Result, HiPart);
5351 /// ExpandLegalINT_TO_FP - This function is responsible for legalizing a
5352 /// INT_TO_FP operation of the specified operand when the target requests that
5353 /// we expand it. At this point, we know that the result and operand types are
5354 /// legal for the target.
5355 SDOperand SelectionDAGLegalize::ExpandLegalINT_TO_FP(bool isSigned,
5358 if (Op0.getValueType() == MVT::i32) {
5359 // simple 32-bit [signed|unsigned] integer to float/double expansion
5361 // Get the stack frame index of a 8 byte buffer.
5362 SDOperand StackSlot = DAG.CreateStackTemporary(MVT::f64);
5364 // word offset constant for Hi/Lo address computation
5365 SDOperand WordOff = DAG.getConstant(sizeof(int), TLI.getPointerTy());
5366 // set up Hi and Lo (into buffer) address based on endian
5367 SDOperand Hi = StackSlot;
5368 SDOperand Lo = DAG.getNode(ISD::ADD, TLI.getPointerTy(), StackSlot,WordOff);
5369 if (TLI.isLittleEndian())
5372 // if signed map to unsigned space
5373 SDOperand Op0Mapped;
5375 // constant used to invert sign bit (signed to unsigned mapping)
5376 SDOperand SignBit = DAG.getConstant(0x80000000u, MVT::i32);
5377 Op0Mapped = DAG.getNode(ISD::XOR, MVT::i32, Op0, SignBit);
5381 // store the lo of the constructed double - based on integer input
5382 SDOperand Store1 = DAG.getStore(DAG.getEntryNode(),
5383 Op0Mapped, Lo, NULL, 0);
5384 // initial hi portion of constructed double
5385 SDOperand InitialHi = DAG.getConstant(0x43300000u, MVT::i32);
5386 // store the hi of the constructed double - biased exponent
5387 SDOperand Store2=DAG.getStore(Store1, InitialHi, Hi, NULL, 0);
5388 // load the constructed double
5389 SDOperand Load = DAG.getLoad(MVT::f64, Store2, StackSlot, NULL, 0);
5390 // FP constant to bias correct the final result
5391 SDOperand Bias = DAG.getConstantFP(isSigned ?
5392 BitsToDouble(0x4330000080000000ULL)
5393 : BitsToDouble(0x4330000000000000ULL),
5395 // subtract the bias
5396 SDOperand Sub = DAG.getNode(ISD::FSUB, MVT::f64, Load, Bias);
5399 // handle final rounding
5400 if (DestVT == MVT::f64) {
5403 } else if (DestVT.bitsLT(MVT::f64)) {
5404 Result = DAG.getNode(ISD::FP_ROUND, DestVT, Sub,
5405 DAG.getIntPtrConstant(0));
5406 } else if (DestVT.bitsGT(MVT::f64)) {
5407 Result = DAG.getNode(ISD::FP_EXTEND, DestVT, Sub);
5411 assert(!isSigned && "Legalize cannot Expand SINT_TO_FP for i64 yet");
5412 SDOperand Tmp1 = DAG.getNode(ISD::SINT_TO_FP, DestVT, Op0);
5414 SDOperand SignSet = DAG.getSetCC(TLI.getSetCCResultType(Op0), Op0,
5415 DAG.getConstant(0, Op0.getValueType()),
5417 SDOperand Zero = DAG.getIntPtrConstant(0), Four = DAG.getIntPtrConstant(4);
5418 SDOperand CstOffset = DAG.getNode(ISD::SELECT, Zero.getValueType(),
5419 SignSet, Four, Zero);
5421 // If the sign bit of the integer is set, the large number will be treated
5422 // as a negative number. To counteract this, the dynamic code adds an
5423 // offset depending on the data type.
5425 switch (Op0.getValueType().getSimpleVT()) {
5426 default: assert(0 && "Unsupported integer type!");
5427 case MVT::i8 : FF = 0x43800000ULL; break; // 2^8 (as a float)
5428 case MVT::i16: FF = 0x47800000ULL; break; // 2^16 (as a float)
5429 case MVT::i32: FF = 0x4F800000ULL; break; // 2^32 (as a float)
5430 case MVT::i64: FF = 0x5F800000ULL; break; // 2^64 (as a float)
5432 if (TLI.isLittleEndian()) FF <<= 32;
5433 static Constant *FudgeFactor = ConstantInt::get(Type::Int64Ty, FF);
5435 SDOperand CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy());
5436 CPIdx = DAG.getNode(ISD::ADD, TLI.getPointerTy(), CPIdx, CstOffset);
5437 SDOperand FudgeInReg;
5438 if (DestVT == MVT::f32)
5439 FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx,
5440 PseudoSourceValue::getConstantPool(), 0);
5443 LegalizeOp(DAG.getExtLoad(ISD::EXTLOAD, DestVT,
5444 DAG.getEntryNode(), CPIdx,
5445 PseudoSourceValue::getConstantPool(), 0,
5449 return DAG.getNode(ISD::FADD, DestVT, Tmp1, FudgeInReg);
5452 /// PromoteLegalINT_TO_FP - This function is responsible for legalizing a
5453 /// *INT_TO_FP operation of the specified operand when the target requests that
5454 /// we promote it. At this point, we know that the result and operand types are
5455 /// legal for the target, and that there is a legal UINT_TO_FP or SINT_TO_FP
5456 /// operation that takes a larger input.
5457 SDOperand SelectionDAGLegalize::PromoteLegalINT_TO_FP(SDOperand LegalOp,
5460 // First step, figure out the appropriate *INT_TO_FP operation to use.
5461 MVT NewInTy = LegalOp.getValueType();
5463 unsigned OpToUse = 0;
5465 // Scan for the appropriate larger type to use.
5467 NewInTy = (MVT::SimpleValueType)(NewInTy.getSimpleVT()+1);
5468 assert(NewInTy.isInteger() && "Ran out of possibilities!");
5470 // If the target supports SINT_TO_FP of this type, use it.
5471 switch (TLI.getOperationAction(ISD::SINT_TO_FP, NewInTy)) {
5473 case TargetLowering::Legal:
5474 if (!TLI.isTypeLegal(NewInTy))
5475 break; // Can't use this datatype.
5477 case TargetLowering::Custom:
5478 OpToUse = ISD::SINT_TO_FP;
5482 if (isSigned) continue;
5484 // If the target supports UINT_TO_FP of this type, use it.
5485 switch (TLI.getOperationAction(ISD::UINT_TO_FP, NewInTy)) {
5487 case TargetLowering::Legal:
5488 if (!TLI.isTypeLegal(NewInTy))
5489 break; // Can't use this datatype.
5491 case TargetLowering::Custom:
5492 OpToUse = ISD::UINT_TO_FP;
5497 // Otherwise, try a larger type.
5500 // Okay, we found the operation and type to use. Zero extend our input to the
5501 // desired type then run the operation on it.
5502 return DAG.getNode(OpToUse, DestVT,
5503 DAG.getNode(isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND,
5507 /// PromoteLegalFP_TO_INT - This function is responsible for legalizing a
5508 /// FP_TO_*INT operation of the specified operand when the target requests that
5509 /// we promote it. At this point, we know that the result and operand types are
5510 /// legal for the target, and that there is a legal FP_TO_UINT or FP_TO_SINT
5511 /// operation that returns a larger result.
5512 SDOperand SelectionDAGLegalize::PromoteLegalFP_TO_INT(SDOperand LegalOp,
5515 // First step, figure out the appropriate FP_TO*INT operation to use.
5516 MVT NewOutTy = DestVT;
5518 unsigned OpToUse = 0;
5520 // Scan for the appropriate larger type to use.
5522 NewOutTy = (MVT::SimpleValueType)(NewOutTy.getSimpleVT()+1);
5523 assert(NewOutTy.isInteger() && "Ran out of possibilities!");
5525 // If the target supports FP_TO_SINT returning this type, use it.
5526 switch (TLI.getOperationAction(ISD::FP_TO_SINT, NewOutTy)) {
5528 case TargetLowering::Legal:
5529 if (!TLI.isTypeLegal(NewOutTy))
5530 break; // Can't use this datatype.
5532 case TargetLowering::Custom:
5533 OpToUse = ISD::FP_TO_SINT;
5538 // If the target supports FP_TO_UINT of this type, use it.
5539 switch (TLI.getOperationAction(ISD::FP_TO_UINT, NewOutTy)) {
5541 case TargetLowering::Legal:
5542 if (!TLI.isTypeLegal(NewOutTy))
5543 break; // Can't use this datatype.
5545 case TargetLowering::Custom:
5546 OpToUse = ISD::FP_TO_UINT;
5551 // Otherwise, try a larger type.
5555 // Okay, we found the operation and type to use.
5556 SDOperand Operation = DAG.getNode(OpToUse, NewOutTy, LegalOp);
5558 // If the operation produces an invalid type, it must be custom lowered. Use
5559 // the target lowering hooks to expand it. Just keep the low part of the
5560 // expanded operation, we know that we're truncating anyway.
5561 if (getTypeAction(NewOutTy) == Expand) {
5562 Operation = SDOperand(TLI.ReplaceNodeResults(Operation.Val, DAG), 0);
5563 assert(Operation.Val && "Didn't return anything");
5566 // Truncate the result of the extended FP_TO_*INT operation to the desired
5568 return DAG.getNode(ISD::TRUNCATE, DestVT, Operation);
5571 /// ExpandBSWAP - Open code the operations for BSWAP of the specified operation.
5573 SDOperand SelectionDAGLegalize::ExpandBSWAP(SDOperand Op) {
5574 MVT VT = Op.getValueType();
5575 MVT SHVT = TLI.getShiftAmountTy();
5576 SDOperand Tmp1, Tmp2, Tmp3, Tmp4, Tmp5, Tmp6, Tmp7, Tmp8;
5577 switch (VT.getSimpleVT()) {
5578 default: assert(0 && "Unhandled Expand type in BSWAP!"); abort();
5580 Tmp2 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT));
5581 Tmp1 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(8, SHVT));
5582 return DAG.getNode(ISD::OR, VT, Tmp1, Tmp2);
5584 Tmp4 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(24, SHVT));
5585 Tmp3 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT));
5586 Tmp2 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(8, SHVT));
5587 Tmp1 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(24, SHVT));
5588 Tmp3 = DAG.getNode(ISD::AND, VT, Tmp3, DAG.getConstant(0xFF0000, VT));
5589 Tmp2 = DAG.getNode(ISD::AND, VT, Tmp2, DAG.getConstant(0xFF00, VT));
5590 Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp3);
5591 Tmp2 = DAG.getNode(ISD::OR, VT, Tmp2, Tmp1);
5592 return DAG.getNode(ISD::OR, VT, Tmp4, Tmp2);
5594 Tmp8 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(56, SHVT));
5595 Tmp7 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(40, SHVT));
5596 Tmp6 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(24, SHVT));
5597 Tmp5 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT));
5598 Tmp4 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(8, SHVT));
5599 Tmp3 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(24, SHVT));
5600 Tmp2 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(40, SHVT));
5601 Tmp1 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(56, SHVT));
5602 Tmp7 = DAG.getNode(ISD::AND, VT, Tmp7, DAG.getConstant(255ULL<<48, VT));
5603 Tmp6 = DAG.getNode(ISD::AND, VT, Tmp6, DAG.getConstant(255ULL<<40, VT));
5604 Tmp5 = DAG.getNode(ISD::AND, VT, Tmp5, DAG.getConstant(255ULL<<32, VT));
5605 Tmp4 = DAG.getNode(ISD::AND, VT, Tmp4, DAG.getConstant(255ULL<<24, VT));
5606 Tmp3 = DAG.getNode(ISD::AND, VT, Tmp3, DAG.getConstant(255ULL<<16, VT));
5607 Tmp2 = DAG.getNode(ISD::AND, VT, Tmp2, DAG.getConstant(255ULL<<8 , VT));
5608 Tmp8 = DAG.getNode(ISD::OR, VT, Tmp8, Tmp7);
5609 Tmp6 = DAG.getNode(ISD::OR, VT, Tmp6, Tmp5);
5610 Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp3);
5611 Tmp2 = DAG.getNode(ISD::OR, VT, Tmp2, Tmp1);
5612 Tmp8 = DAG.getNode(ISD::OR, VT, Tmp8, Tmp6);
5613 Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp2);
5614 return DAG.getNode(ISD::OR, VT, Tmp8, Tmp4);
5618 /// ExpandBitCount - Expand the specified bitcount instruction into operations.
5620 SDOperand SelectionDAGLegalize::ExpandBitCount(unsigned Opc, SDOperand Op) {
5622 default: assert(0 && "Cannot expand this yet!");
5624 static const uint64_t mask[6] = {
5625 0x5555555555555555ULL, 0x3333333333333333ULL,
5626 0x0F0F0F0F0F0F0F0FULL, 0x00FF00FF00FF00FFULL,
5627 0x0000FFFF0000FFFFULL, 0x00000000FFFFFFFFULL
5629 MVT VT = Op.getValueType();
5630 MVT ShVT = TLI.getShiftAmountTy();
5631 unsigned len = VT.getSizeInBits();
5632 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) {
5633 //x = (x & mask[i][len/8]) + (x >> (1 << i) & mask[i][len/8])
5634 SDOperand Tmp2 = DAG.getConstant(mask[i], VT);
5635 SDOperand Tmp3 = DAG.getConstant(1ULL << i, ShVT);
5636 Op = DAG.getNode(ISD::ADD, VT, DAG.getNode(ISD::AND, VT, Op, Tmp2),
5637 DAG.getNode(ISD::AND, VT,
5638 DAG.getNode(ISD::SRL, VT, Op, Tmp3),Tmp2));
5643 // for now, we do this:
5644 // x = x | (x >> 1);
5645 // x = x | (x >> 2);
5647 // x = x | (x >>16);
5648 // x = x | (x >>32); // for 64-bit input
5649 // return popcount(~x);
5651 // but see also: http://www.hackersdelight.org/HDcode/nlz.cc
5652 MVT VT = Op.getValueType();
5653 MVT ShVT = TLI.getShiftAmountTy();
5654 unsigned len = VT.getSizeInBits();
5655 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) {
5656 SDOperand Tmp3 = DAG.getConstant(1ULL << i, ShVT);
5657 Op = DAG.getNode(ISD::OR, VT, Op, DAG.getNode(ISD::SRL, VT, Op, Tmp3));
5659 Op = DAG.getNode(ISD::XOR, VT, Op, DAG.getConstant(~0ULL, VT));
5660 return DAG.getNode(ISD::CTPOP, VT, Op);
5663 // for now, we use: { return popcount(~x & (x - 1)); }
5664 // unless the target has ctlz but not ctpop, in which case we use:
5665 // { return 32 - nlz(~x & (x-1)); }
5666 // see also http://www.hackersdelight.org/HDcode/ntz.cc
5667 MVT VT = Op.getValueType();
5668 SDOperand Tmp2 = DAG.getConstant(~0ULL, VT);
5669 SDOperand Tmp3 = DAG.getNode(ISD::AND, VT,
5670 DAG.getNode(ISD::XOR, VT, Op, Tmp2),
5671 DAG.getNode(ISD::SUB, VT, Op, DAG.getConstant(1, VT)));
5672 // If ISD::CTLZ is legal and CTPOP isn't, then do that instead.
5673 if (!TLI.isOperationLegal(ISD::CTPOP, VT) &&
5674 TLI.isOperationLegal(ISD::CTLZ, VT))
5675 return DAG.getNode(ISD::SUB, VT,
5676 DAG.getConstant(VT.getSizeInBits(), VT),
5677 DAG.getNode(ISD::CTLZ, VT, Tmp3));
5678 return DAG.getNode(ISD::CTPOP, VT, Tmp3);
5683 /// ExpandOp - Expand the specified SDOperand into its two component pieces
5684 /// Lo&Hi. Note that the Op MUST be an expanded type. As a result of this, the
5685 /// LegalizeNodes map is filled in for any results that are not expanded, the
5686 /// ExpandedNodes map is filled in for any results that are expanded, and the
5687 /// Lo/Hi values are returned.
5688 void SelectionDAGLegalize::ExpandOp(SDOperand Op, SDOperand &Lo, SDOperand &Hi){
5689 MVT VT = Op.getValueType();
5690 MVT NVT = TLI.getTypeToTransformTo(VT);
5691 SDNode *Node = Op.Val;
5692 assert(getTypeAction(VT) == Expand && "Not an expanded type!");
5693 assert(((NVT.isInteger() && NVT.bitsLT(VT)) || VT.isFloatingPoint() ||
5694 VT.isVector()) && "Cannot expand to FP value or to larger int value!");
5696 // See if we already expanded it.
5697 DenseMap<SDOperand, std::pair<SDOperand, SDOperand> >::iterator I
5698 = ExpandedNodes.find(Op);
5699 if (I != ExpandedNodes.end()) {
5700 Lo = I->second.first;
5701 Hi = I->second.second;
5705 switch (Node->getOpcode()) {
5706 case ISD::CopyFromReg:
5707 assert(0 && "CopyFromReg must be legal!");
5708 case ISD::FP_ROUND_INREG:
5709 if (VT == MVT::ppcf128 &&
5710 TLI.getOperationAction(ISD::FP_ROUND_INREG, VT) ==
5711 TargetLowering::Custom) {
5712 SDOperand SrcLo, SrcHi, Src;
5713 ExpandOp(Op.getOperand(0), SrcLo, SrcHi);
5714 Src = DAG.getNode(ISD::BUILD_PAIR, VT, SrcLo, SrcHi);
5715 SDOperand Result = TLI.LowerOperation(
5716 DAG.getNode(ISD::FP_ROUND_INREG, VT, Src, Op.getOperand(1)), DAG);
5717 assert(Result.Val->getOpcode() == ISD::BUILD_PAIR);
5718 Lo = Result.Val->getOperand(0);
5719 Hi = Result.Val->getOperand(1);
5725 cerr << "NODE: "; Node->dump(&DAG); cerr << "\n";
5727 assert(0 && "Do not know how to expand this operator!");
5729 case ISD::EXTRACT_ELEMENT:
5730 ExpandOp(Node->getOperand(0), Lo, Hi);
5731 if (cast<ConstantSDNode>(Node->getOperand(1))->getValue())
5732 return ExpandOp(Hi, Lo, Hi);
5733 return ExpandOp(Lo, Lo, Hi);
5734 case ISD::EXTRACT_VECTOR_ELT:
5735 assert(VT==MVT::i64 && "Do not know how to expand this operator!");
5736 // ExpandEXTRACT_VECTOR_ELT tolerates invalid result types.
5737 Lo = ExpandEXTRACT_VECTOR_ELT(Op);
5738 return ExpandOp(Lo, Lo, Hi);
5740 Lo = DAG.getNode(ISD::UNDEF, NVT);
5741 Hi = DAG.getNode(ISD::UNDEF, NVT);
5743 case ISD::Constant: {
5744 unsigned NVTBits = NVT.getSizeInBits();
5745 const APInt &Cst = cast<ConstantSDNode>(Node)->getAPIntValue();
5746 Lo = DAG.getConstant(APInt(Cst).trunc(NVTBits), NVT);
5747 Hi = DAG.getConstant(Cst.lshr(NVTBits).trunc(NVTBits), NVT);
5750 case ISD::ConstantFP: {
5751 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node);
5752 if (CFP->getValueType(0) == MVT::ppcf128) {
5753 APInt api = CFP->getValueAPF().convertToAPInt();
5754 Lo = DAG.getConstantFP(APFloat(APInt(64, 1, &api.getRawData()[1])),
5756 Hi = DAG.getConstantFP(APFloat(APInt(64, 1, &api.getRawData()[0])),
5760 Lo = ExpandConstantFP(CFP, false, DAG, TLI);
5761 if (getTypeAction(Lo.getValueType()) == Expand)
5762 ExpandOp(Lo, Lo, Hi);
5765 case ISD::BUILD_PAIR:
5766 // Return the operands.
5767 Lo = Node->getOperand(0);
5768 Hi = Node->getOperand(1);
5771 case ISD::MERGE_VALUES:
5772 if (Node->getNumValues() == 1) {
5773 ExpandOp(Op.getOperand(0), Lo, Hi);
5776 // FIXME: For now only expand i64,chain = MERGE_VALUES (x, y)
5777 assert(Op.ResNo == 0 && Node->getNumValues() == 2 &&
5778 Op.getValue(1).getValueType() == MVT::Other &&
5779 "unhandled MERGE_VALUES");
5780 ExpandOp(Op.getOperand(0), Lo, Hi);
5781 // Remember that we legalized the chain.
5782 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Op.getOperand(1)));
5785 case ISD::SIGN_EXTEND_INREG:
5786 ExpandOp(Node->getOperand(0), Lo, Hi);
5787 // sext_inreg the low part if needed.
5788 Lo = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Lo, Node->getOperand(1));
5790 // The high part gets the sign extension from the lo-part. This handles
5791 // things like sextinreg V:i64 from i8.
5792 Hi = DAG.getNode(ISD::SRA, NVT, Lo,
5793 DAG.getConstant(NVT.getSizeInBits()-1,
5794 TLI.getShiftAmountTy()));
5798 ExpandOp(Node->getOperand(0), Lo, Hi);
5799 SDOperand TempLo = DAG.getNode(ISD::BSWAP, NVT, Hi);
5800 Hi = DAG.getNode(ISD::BSWAP, NVT, Lo);
5806 ExpandOp(Node->getOperand(0), Lo, Hi);
5807 Lo = DAG.getNode(ISD::ADD, NVT, // ctpop(HL) -> ctpop(H)+ctpop(L)
5808 DAG.getNode(ISD::CTPOP, NVT, Lo),
5809 DAG.getNode(ISD::CTPOP, NVT, Hi));
5810 Hi = DAG.getConstant(0, NVT);
5814 // ctlz (HL) -> ctlz(H) != 32 ? ctlz(H) : (ctlz(L)+32)
5815 ExpandOp(Node->getOperand(0), Lo, Hi);
5816 SDOperand BitsC = DAG.getConstant(NVT.getSizeInBits(), NVT);
5817 SDOperand HLZ = DAG.getNode(ISD::CTLZ, NVT, Hi);
5818 SDOperand TopNotZero = DAG.getSetCC(TLI.getSetCCResultType(HLZ), HLZ, BitsC,
5820 SDOperand LowPart = DAG.getNode(ISD::CTLZ, NVT, Lo);
5821 LowPart = DAG.getNode(ISD::ADD, NVT, LowPart, BitsC);
5823 Lo = DAG.getNode(ISD::SELECT, NVT, TopNotZero, HLZ, LowPart);
5824 Hi = DAG.getConstant(0, NVT);
5829 // cttz (HL) -> cttz(L) != 32 ? cttz(L) : (cttz(H)+32)
5830 ExpandOp(Node->getOperand(0), Lo, Hi);
5831 SDOperand BitsC = DAG.getConstant(NVT.getSizeInBits(), NVT);
5832 SDOperand LTZ = DAG.getNode(ISD::CTTZ, NVT, Lo);
5833 SDOperand BotNotZero = DAG.getSetCC(TLI.getSetCCResultType(LTZ), LTZ, BitsC,
5835 SDOperand HiPart = DAG.getNode(ISD::CTTZ, NVT, Hi);
5836 HiPart = DAG.getNode(ISD::ADD, NVT, HiPart, BitsC);
5838 Lo = DAG.getNode(ISD::SELECT, NVT, BotNotZero, LTZ, HiPart);
5839 Hi = DAG.getConstant(0, NVT);
5844 SDOperand Ch = Node->getOperand(0); // Legalize the chain.
5845 SDOperand Ptr = Node->getOperand(1); // Legalize the pointer.
5846 Lo = DAG.getVAArg(NVT, Ch, Ptr, Node->getOperand(2));
5847 Hi = DAG.getVAArg(NVT, Lo.getValue(1), Ptr, Node->getOperand(2));
5849 // Remember that we legalized the chain.
5850 Hi = LegalizeOp(Hi);
5851 AddLegalizedOperand(Op.getValue(1), Hi.getValue(1));
5852 if (TLI.isBigEndian())
5858 LoadSDNode *LD = cast<LoadSDNode>(Node);
5859 SDOperand Ch = LD->getChain(); // Legalize the chain.
5860 SDOperand Ptr = LD->getBasePtr(); // Legalize the pointer.
5861 ISD::LoadExtType ExtType = LD->getExtensionType();
5862 int SVOffset = LD->getSrcValueOffset();
5863 unsigned Alignment = LD->getAlignment();
5864 bool isVolatile = LD->isVolatile();
5866 if (ExtType == ISD::NON_EXTLOAD) {
5867 Lo = DAG.getLoad(NVT, Ch, Ptr, LD->getSrcValue(), SVOffset,
5868 isVolatile, Alignment);
5869 if (VT == MVT::f32 || VT == MVT::f64) {
5870 // f32->i32 or f64->i64 one to one expansion.
5871 // Remember that we legalized the chain.
5872 AddLegalizedOperand(SDOperand(Node, 1), LegalizeOp(Lo.getValue(1)));
5873 // Recursively expand the new load.
5874 if (getTypeAction(NVT) == Expand)
5875 ExpandOp(Lo, Lo, Hi);
5879 // Increment the pointer to the other half.
5880 unsigned IncrementSize = Lo.getValueType().getSizeInBits()/8;
5881 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
5882 DAG.getIntPtrConstant(IncrementSize));
5883 SVOffset += IncrementSize;
5884 Alignment = MinAlign(Alignment, IncrementSize);
5885 Hi = DAG.getLoad(NVT, Ch, Ptr, LD->getSrcValue(), SVOffset,
5886 isVolatile, Alignment);
5888 // Build a factor node to remember that this load is independent of the
5890 SDOperand TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
5893 // Remember that we legalized the chain.
5894 AddLegalizedOperand(Op.getValue(1), LegalizeOp(TF));
5895 if (TLI.isBigEndian())
5898 MVT EVT = LD->getMemoryVT();
5900 if ((VT == MVT::f64 && EVT == MVT::f32) ||
5901 (VT == MVT::ppcf128 && (EVT==MVT::f64 || EVT==MVT::f32))) {
5902 // f64 = EXTLOAD f32 should expand to LOAD, FP_EXTEND
5903 SDOperand Load = DAG.getLoad(EVT, Ch, Ptr, LD->getSrcValue(),
5904 SVOffset, isVolatile, Alignment);
5905 // Remember that we legalized the chain.
5906 AddLegalizedOperand(SDOperand(Node, 1), LegalizeOp(Load.getValue(1)));
5907 ExpandOp(DAG.getNode(ISD::FP_EXTEND, VT, Load), Lo, Hi);
5912 Lo = DAG.getLoad(NVT, Ch, Ptr, LD->getSrcValue(),
5913 SVOffset, isVolatile, Alignment);
5915 Lo = DAG.getExtLoad(ExtType, NVT, Ch, Ptr, LD->getSrcValue(),
5916 SVOffset, EVT, isVolatile,
5919 // Remember that we legalized the chain.
5920 AddLegalizedOperand(SDOperand(Node, 1), LegalizeOp(Lo.getValue(1)));
5922 if (ExtType == ISD::SEXTLOAD) {
5923 // The high part is obtained by SRA'ing all but one of the bits of the
5925 unsigned LoSize = Lo.getValueType().getSizeInBits();
5926 Hi = DAG.getNode(ISD::SRA, NVT, Lo,
5927 DAG.getConstant(LoSize-1, TLI.getShiftAmountTy()));
5928 } else if (ExtType == ISD::ZEXTLOAD) {
5929 // The high part is just a zero.
5930 Hi = DAG.getConstant(0, NVT);
5931 } else /* if (ExtType == ISD::EXTLOAD) */ {
5932 // The high part is undefined.
5933 Hi = DAG.getNode(ISD::UNDEF, NVT);
5940 case ISD::XOR: { // Simple logical operators -> two trivial pieces.
5941 SDOperand LL, LH, RL, RH;
5942 ExpandOp(Node->getOperand(0), LL, LH);
5943 ExpandOp(Node->getOperand(1), RL, RH);
5944 Lo = DAG.getNode(Node->getOpcode(), NVT, LL, RL);
5945 Hi = DAG.getNode(Node->getOpcode(), NVT, LH, RH);
5949 SDOperand LL, LH, RL, RH;
5950 ExpandOp(Node->getOperand(1), LL, LH);
5951 ExpandOp(Node->getOperand(2), RL, RH);
5952 if (getTypeAction(NVT) == Expand)
5953 NVT = TLI.getTypeToExpandTo(NVT);
5954 Lo = DAG.getNode(ISD::SELECT, NVT, Node->getOperand(0), LL, RL);
5956 Hi = DAG.getNode(ISD::SELECT, NVT, Node->getOperand(0), LH, RH);
5959 case ISD::SELECT_CC: {
5960 SDOperand TL, TH, FL, FH;
5961 ExpandOp(Node->getOperand(2), TL, TH);
5962 ExpandOp(Node->getOperand(3), FL, FH);
5963 if (getTypeAction(NVT) == Expand)
5964 NVT = TLI.getTypeToExpandTo(NVT);
5965 Lo = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0),
5966 Node->getOperand(1), TL, FL, Node->getOperand(4));
5968 Hi = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0),
5969 Node->getOperand(1), TH, FH, Node->getOperand(4));
5972 case ISD::ANY_EXTEND:
5973 // The low part is any extension of the input (which degenerates to a copy).
5974 Lo = DAG.getNode(ISD::ANY_EXTEND, NVT, Node->getOperand(0));
5975 // The high part is undefined.
5976 Hi = DAG.getNode(ISD::UNDEF, NVT);
5978 case ISD::SIGN_EXTEND: {
5979 // The low part is just a sign extension of the input (which degenerates to
5981 Lo = DAG.getNode(ISD::SIGN_EXTEND, NVT, Node->getOperand(0));
5983 // The high part is obtained by SRA'ing all but one of the bits of the lo
5985 unsigned LoSize = Lo.getValueType().getSizeInBits();
5986 Hi = DAG.getNode(ISD::SRA, NVT, Lo,
5987 DAG.getConstant(LoSize-1, TLI.getShiftAmountTy()));
5990 case ISD::ZERO_EXTEND:
5991 // The low part is just a zero extension of the input (which degenerates to
5993 Lo = DAG.getNode(ISD::ZERO_EXTEND, NVT, Node->getOperand(0));
5995 // The high part is just a zero.
5996 Hi = DAG.getConstant(0, NVT);
5999 case ISD::TRUNCATE: {
6000 // The input value must be larger than this value. Expand *it*.
6002 ExpandOp(Node->getOperand(0), NewLo, Hi);
6004 // The low part is now either the right size, or it is closer. If not the
6005 // right size, make an illegal truncate so we recursively expand it.
6006 if (NewLo.getValueType() != Node->getValueType(0))
6007 NewLo = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), NewLo);
6008 ExpandOp(NewLo, Lo, Hi);
6012 case ISD::BIT_CONVERT: {
6014 if (TLI.getOperationAction(ISD::BIT_CONVERT, VT) == TargetLowering::Custom){
6015 // If the target wants to, allow it to lower this itself.
6016 switch (getTypeAction(Node->getOperand(0).getValueType())) {
6017 case Expand: assert(0 && "cannot expand FP!");
6018 case Legal: Tmp = LegalizeOp(Node->getOperand(0)); break;
6019 case Promote: Tmp = PromoteOp (Node->getOperand(0)); break;
6021 Tmp = TLI.LowerOperation(DAG.getNode(ISD::BIT_CONVERT, VT, Tmp), DAG);
6024 // f32 / f64 must be expanded to i32 / i64.
6025 if (VT == MVT::f32 || VT == MVT::f64) {
6026 Lo = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0));
6027 if (getTypeAction(NVT) == Expand)
6028 ExpandOp(Lo, Lo, Hi);
6032 // If source operand will be expanded to the same type as VT, i.e.
6033 // i64 <- f64, i32 <- f32, expand the source operand instead.
6034 MVT VT0 = Node->getOperand(0).getValueType();
6035 if (getTypeAction(VT0) == Expand && TLI.getTypeToTransformTo(VT0) == VT) {
6036 ExpandOp(Node->getOperand(0), Lo, Hi);
6040 // Turn this into a load/store pair by default.
6042 Tmp = EmitStackConvert(Node->getOperand(0), VT, VT);
6044 ExpandOp(Tmp, Lo, Hi);
6048 case ISD::READCYCLECOUNTER: {
6049 assert(TLI.getOperationAction(ISD::READCYCLECOUNTER, VT) ==
6050 TargetLowering::Custom &&
6051 "Must custom expand ReadCycleCounter");
6052 SDOperand Tmp = TLI.LowerOperation(Op, DAG);
6053 assert(Tmp.Val && "Node must be custom expanded!");
6054 ExpandOp(Tmp.getValue(0), Lo, Hi);
6055 AddLegalizedOperand(SDOperand(Node, 1), // Remember we legalized the chain.
6056 LegalizeOp(Tmp.getValue(1)));
6060 case ISD::ATOMIC_CMP_SWAP: {
6061 SDOperand Tmp = TLI.LowerOperation(Op, DAG);
6062 assert(Tmp.Val && "Node must be custom expanded!");
6063 ExpandOp(Tmp.getValue(0), Lo, Hi);
6064 AddLegalizedOperand(SDOperand(Node, 1), // Remember we legalized the chain.
6065 LegalizeOp(Tmp.getValue(1)));
6071 // These operators cannot be expanded directly, emit them as calls to
6072 // library functions.
6073 case ISD::FP_TO_SINT: {
6074 if (TLI.getOperationAction(ISD::FP_TO_SINT, VT) == TargetLowering::Custom) {
6076 switch (getTypeAction(Node->getOperand(0).getValueType())) {
6077 case Expand: assert(0 && "cannot expand FP!");
6078 case Legal: Op = LegalizeOp(Node->getOperand(0)); break;
6079 case Promote: Op = PromoteOp (Node->getOperand(0)); break;
6082 Op = TLI.LowerOperation(DAG.getNode(ISD::FP_TO_SINT, VT, Op), DAG);
6084 // Now that the custom expander is done, expand the result, which is still
6087 ExpandOp(Op, Lo, Hi);
6092 RTLIB::Libcall LC = RTLIB::getFPTOSINT(Node->getOperand(0).getValueType(),
6094 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected uint-to-fp conversion!");
6095 Lo = ExpandLibCall(LC, Node, false/*sign irrelevant*/, Hi);
6099 case ISD::FP_TO_UINT: {
6100 if (TLI.getOperationAction(ISD::FP_TO_UINT, VT) == TargetLowering::Custom) {
6102 switch (getTypeAction(Node->getOperand(0).getValueType())) {
6103 case Expand: assert(0 && "cannot expand FP!");
6104 case Legal: Op = LegalizeOp(Node->getOperand(0)); break;
6105 case Promote: Op = PromoteOp (Node->getOperand(0)); break;
6108 Op = TLI.LowerOperation(DAG.getNode(ISD::FP_TO_UINT, VT, Op), DAG);
6110 // Now that the custom expander is done, expand the result.
6112 ExpandOp(Op, Lo, Hi);
6117 RTLIB::Libcall LC = RTLIB::getFPTOUINT(Node->getOperand(0).getValueType(),
6119 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected fp-to-uint conversion!");
6120 Lo = ExpandLibCall(LC, Node, false/*sign irrelevant*/, Hi);
6125 // If the target wants custom lowering, do so.
6126 SDOperand ShiftAmt = LegalizeOp(Node->getOperand(1));
6127 if (TLI.getOperationAction(ISD::SHL, VT) == TargetLowering::Custom) {
6128 SDOperand Op = DAG.getNode(ISD::SHL, VT, Node->getOperand(0), ShiftAmt);
6129 Op = TLI.LowerOperation(Op, DAG);
6131 // Now that the custom expander is done, expand the result, which is
6133 ExpandOp(Op, Lo, Hi);
6138 // If ADDC/ADDE are supported and if the shift amount is a constant 1, emit
6139 // this X << 1 as X+X.
6140 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(ShiftAmt)) {
6141 if (ShAmt->getAPIntValue() == 1 && TLI.isOperationLegal(ISD::ADDC, NVT) &&
6142 TLI.isOperationLegal(ISD::ADDE, NVT)) {
6143 SDOperand LoOps[2], HiOps[3];
6144 ExpandOp(Node->getOperand(0), LoOps[0], HiOps[0]);
6145 SDVTList VTList = DAG.getVTList(LoOps[0].getValueType(), MVT::Flag);
6146 LoOps[1] = LoOps[0];
6147 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2);
6149 HiOps[1] = HiOps[0];
6150 HiOps[2] = Lo.getValue(1);
6151 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3);
6156 // If we can emit an efficient shift operation, do so now.
6157 if (ExpandShift(ISD::SHL, Node->getOperand(0), ShiftAmt, Lo, Hi))
6160 // If this target supports SHL_PARTS, use it.
6161 TargetLowering::LegalizeAction Action =
6162 TLI.getOperationAction(ISD::SHL_PARTS, NVT);
6163 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) ||
6164 Action == TargetLowering::Custom) {
6165 ExpandShiftParts(ISD::SHL_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi);
6169 // Otherwise, emit a libcall.
6170 Lo = ExpandLibCall(RTLIB::SHL_I64, Node, false/*left shift=unsigned*/, Hi);
6175 // If the target wants custom lowering, do so.
6176 SDOperand ShiftAmt = LegalizeOp(Node->getOperand(1));
6177 if (TLI.getOperationAction(ISD::SRA, VT) == TargetLowering::Custom) {
6178 SDOperand Op = DAG.getNode(ISD::SRA, VT, Node->getOperand(0), ShiftAmt);
6179 Op = TLI.LowerOperation(Op, DAG);
6181 // Now that the custom expander is done, expand the result, which is
6183 ExpandOp(Op, Lo, Hi);
6188 // If we can emit an efficient shift operation, do so now.
6189 if (ExpandShift(ISD::SRA, Node->getOperand(0), ShiftAmt, Lo, Hi))
6192 // If this target supports SRA_PARTS, use it.
6193 TargetLowering::LegalizeAction Action =
6194 TLI.getOperationAction(ISD::SRA_PARTS, NVT);
6195 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) ||
6196 Action == TargetLowering::Custom) {
6197 ExpandShiftParts(ISD::SRA_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi);
6201 // Otherwise, emit a libcall.
6202 Lo = ExpandLibCall(RTLIB::SRA_I64, Node, true/*ashr is signed*/, Hi);
6207 // If the target wants custom lowering, do so.
6208 SDOperand ShiftAmt = LegalizeOp(Node->getOperand(1));
6209 if (TLI.getOperationAction(ISD::SRL, VT) == TargetLowering::Custom) {
6210 SDOperand Op = DAG.getNode(ISD::SRL, VT, Node->getOperand(0), ShiftAmt);
6211 Op = TLI.LowerOperation(Op, DAG);
6213 // Now that the custom expander is done, expand the result, which is
6215 ExpandOp(Op, Lo, Hi);
6220 // If we can emit an efficient shift operation, do so now.
6221 if (ExpandShift(ISD::SRL, Node->getOperand(0), ShiftAmt, Lo, Hi))
6224 // If this target supports SRL_PARTS, use it.
6225 TargetLowering::LegalizeAction Action =
6226 TLI.getOperationAction(ISD::SRL_PARTS, NVT);
6227 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) ||
6228 Action == TargetLowering::Custom) {
6229 ExpandShiftParts(ISD::SRL_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi);
6233 // Otherwise, emit a libcall.
6234 Lo = ExpandLibCall(RTLIB::SRL_I64, Node, false/*lshr is unsigned*/, Hi);
6240 // If the target wants to custom expand this, let them.
6241 if (TLI.getOperationAction(Node->getOpcode(), VT) ==
6242 TargetLowering::Custom) {
6243 SDOperand Result = TLI.LowerOperation(Op, DAG);
6245 ExpandOp(Result, Lo, Hi);
6250 // Expand the subcomponents.
6251 SDOperand LHSL, LHSH, RHSL, RHSH;
6252 ExpandOp(Node->getOperand(0), LHSL, LHSH);
6253 ExpandOp(Node->getOperand(1), RHSL, RHSH);
6254 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag);
6255 SDOperand LoOps[2], HiOps[3];
6260 if (Node->getOpcode() == ISD::ADD) {
6261 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2);
6262 HiOps[2] = Lo.getValue(1);
6263 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3);
6265 Lo = DAG.getNode(ISD::SUBC, VTList, LoOps, 2);
6266 HiOps[2] = Lo.getValue(1);
6267 Hi = DAG.getNode(ISD::SUBE, VTList, HiOps, 3);
6274 // Expand the subcomponents.
6275 SDOperand LHSL, LHSH, RHSL, RHSH;
6276 ExpandOp(Node->getOperand(0), LHSL, LHSH);
6277 ExpandOp(Node->getOperand(1), RHSL, RHSH);
6278 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag);
6279 SDOperand LoOps[2] = { LHSL, RHSL };
6280 SDOperand HiOps[3] = { LHSH, RHSH };
6282 if (Node->getOpcode() == ISD::ADDC) {
6283 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2);
6284 HiOps[2] = Lo.getValue(1);
6285 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3);
6287 Lo = DAG.getNode(ISD::SUBC, VTList, LoOps, 2);
6288 HiOps[2] = Lo.getValue(1);
6289 Hi = DAG.getNode(ISD::SUBE, VTList, HiOps, 3);
6291 // Remember that we legalized the flag.
6292 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Hi.getValue(1)));
6297 // Expand the subcomponents.
6298 SDOperand LHSL, LHSH, RHSL, RHSH;
6299 ExpandOp(Node->getOperand(0), LHSL, LHSH);
6300 ExpandOp(Node->getOperand(1), RHSL, RHSH);
6301 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag);
6302 SDOperand LoOps[3] = { LHSL, RHSL, Node->getOperand(2) };
6303 SDOperand HiOps[3] = { LHSH, RHSH };
6305 Lo = DAG.getNode(Node->getOpcode(), VTList, LoOps, 3);
6306 HiOps[2] = Lo.getValue(1);
6307 Hi = DAG.getNode(Node->getOpcode(), VTList, HiOps, 3);
6309 // Remember that we legalized the flag.
6310 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Hi.getValue(1)));
6314 // If the target wants to custom expand this, let them.
6315 if (TLI.getOperationAction(ISD::MUL, VT) == TargetLowering::Custom) {
6316 SDOperand New = TLI.LowerOperation(Op, DAG);
6318 ExpandOp(New, Lo, Hi);
6323 bool HasMULHS = TLI.isOperationLegal(ISD::MULHS, NVT);
6324 bool HasMULHU = TLI.isOperationLegal(ISD::MULHU, NVT);
6325 bool HasSMUL_LOHI = TLI.isOperationLegal(ISD::SMUL_LOHI, NVT);
6326 bool HasUMUL_LOHI = TLI.isOperationLegal(ISD::UMUL_LOHI, NVT);
6327 if (HasMULHU || HasMULHS || HasUMUL_LOHI || HasSMUL_LOHI) {
6328 SDOperand LL, LH, RL, RH;
6329 ExpandOp(Node->getOperand(0), LL, LH);
6330 ExpandOp(Node->getOperand(1), RL, RH);
6331 unsigned OuterBitSize = Op.getValueSizeInBits();
6332 unsigned InnerBitSize = RH.getValueSizeInBits();
6333 unsigned LHSSB = DAG.ComputeNumSignBits(Op.getOperand(0));
6334 unsigned RHSSB = DAG.ComputeNumSignBits(Op.getOperand(1));
6335 APInt HighMask = APInt::getHighBitsSet(OuterBitSize, InnerBitSize);
6336 if (DAG.MaskedValueIsZero(Node->getOperand(0), HighMask) &&
6337 DAG.MaskedValueIsZero(Node->getOperand(1), HighMask)) {
6338 // The inputs are both zero-extended.
6340 // We can emit a umul_lohi.
6341 Lo = DAG.getNode(ISD::UMUL_LOHI, DAG.getVTList(NVT, NVT), LL, RL);
6342 Hi = SDOperand(Lo.Val, 1);
6346 // We can emit a mulhu+mul.
6347 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL);
6348 Hi = DAG.getNode(ISD::MULHU, NVT, LL, RL);
6352 if (LHSSB > InnerBitSize && RHSSB > InnerBitSize) {
6353 // The input values are both sign-extended.
6355 // We can emit a smul_lohi.
6356 Lo = DAG.getNode(ISD::SMUL_LOHI, DAG.getVTList(NVT, NVT), LL, RL);
6357 Hi = SDOperand(Lo.Val, 1);
6361 // We can emit a mulhs+mul.
6362 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL);
6363 Hi = DAG.getNode(ISD::MULHS, NVT, LL, RL);
6368 // Lo,Hi = umul LHS, RHS.
6369 SDOperand UMulLOHI = DAG.getNode(ISD::UMUL_LOHI,
6370 DAG.getVTList(NVT, NVT), LL, RL);
6372 Hi = UMulLOHI.getValue(1);
6373 RH = DAG.getNode(ISD::MUL, NVT, LL, RH);
6374 LH = DAG.getNode(ISD::MUL, NVT, LH, RL);
6375 Hi = DAG.getNode(ISD::ADD, NVT, Hi, RH);
6376 Hi = DAG.getNode(ISD::ADD, NVT, Hi, LH);
6380 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL);
6381 Hi = DAG.getNode(ISD::MULHU, NVT, LL, RL);
6382 RH = DAG.getNode(ISD::MUL, NVT, LL, RH);
6383 LH = DAG.getNode(ISD::MUL, NVT, LH, RL);
6384 Hi = DAG.getNode(ISD::ADD, NVT, Hi, RH);
6385 Hi = DAG.getNode(ISD::ADD, NVT, Hi, LH);
6390 // If nothing else, we can make a libcall.
6391 Lo = ExpandLibCall(RTLIB::MUL_I64, Node, false/*sign irrelevant*/, Hi);
6395 Lo = ExpandLibCall(RTLIB::SDIV_I64, Node, true, Hi);
6398 Lo = ExpandLibCall(RTLIB::UDIV_I64, Node, true, Hi);
6401 Lo = ExpandLibCall(RTLIB::SREM_I64, Node, true, Hi);
6404 Lo = ExpandLibCall(RTLIB::UREM_I64, Node, true, Hi);
6408 Lo = ExpandLibCall(GetFPLibCall(VT, RTLIB::ADD_F32,
6411 RTLIB::ADD_PPCF128),
6415 Lo = ExpandLibCall(GetFPLibCall(VT, RTLIB::SUB_F32,
6418 RTLIB::SUB_PPCF128),
6422 Lo = ExpandLibCall(GetFPLibCall(VT, RTLIB::MUL_F32,
6425 RTLIB::MUL_PPCF128),
6429 Lo = ExpandLibCall(GetFPLibCall(VT, RTLIB::DIV_F32,
6432 RTLIB::DIV_PPCF128),
6435 case ISD::FP_EXTEND: {
6436 if (VT == MVT::ppcf128) {
6437 assert(Node->getOperand(0).getValueType()==MVT::f32 ||
6438 Node->getOperand(0).getValueType()==MVT::f64);
6439 const uint64_t zero = 0;
6440 if (Node->getOperand(0).getValueType()==MVT::f32)
6441 Hi = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Node->getOperand(0));
6443 Hi = Node->getOperand(0);
6444 Lo = DAG.getConstantFP(APFloat(APInt(64, 1, &zero)), MVT::f64);
6447 RTLIB::Libcall LC = RTLIB::getFPEXT(Node->getOperand(0).getValueType(), VT);
6448 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported FP_EXTEND!");
6449 Lo = ExpandLibCall(LC, Node, true, Hi);
6452 case ISD::FP_ROUND: {
6453 RTLIB::Libcall LC = RTLIB::getFPROUND(Node->getOperand(0).getValueType(),
6455 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported FP_ROUND!");
6456 Lo = ExpandLibCall(LC, Node, true, Hi);
6460 Lo = ExpandLibCall(GetFPLibCall(VT, RTLIB::POWI_F32,
6463 RTLIB::POWI_PPCF128),
6469 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
6470 switch(Node->getOpcode()) {
6472 LC = GetFPLibCall(VT, RTLIB::SQRT_F32, RTLIB::SQRT_F64,
6473 RTLIB::SQRT_F80, RTLIB::SQRT_PPCF128);
6476 LC = GetFPLibCall(VT, RTLIB::SIN_F32, RTLIB::SIN_F64,
6477 RTLIB::SIN_F80, RTLIB::SIN_PPCF128);
6480 LC = GetFPLibCall(VT, RTLIB::COS_F32, RTLIB::COS_F64,
6481 RTLIB::COS_F80, RTLIB::COS_PPCF128);
6483 default: assert(0 && "Unreachable!");
6485 Lo = ExpandLibCall(LC, Node, false, Hi);
6489 if (VT == MVT::ppcf128) {
6491 ExpandOp(Node->getOperand(0), Lo, Tmp);
6492 Hi = DAG.getNode(ISD::FABS, NVT, Tmp);
6493 // lo = hi==fabs(hi) ? lo : -lo;
6494 Lo = DAG.getNode(ISD::SELECT_CC, NVT, Hi, Tmp,
6495 Lo, DAG.getNode(ISD::FNEG, NVT, Lo),
6496 DAG.getCondCode(ISD::SETEQ));
6499 SDOperand Mask = (VT == MVT::f64)
6500 ? DAG.getConstantFP(BitsToDouble(~(1ULL << 63)), VT)
6501 : DAG.getConstantFP(BitsToFloat(~(1U << 31)), VT);
6502 Mask = DAG.getNode(ISD::BIT_CONVERT, NVT, Mask);
6503 Lo = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0));
6504 Lo = DAG.getNode(ISD::AND, NVT, Lo, Mask);
6505 if (getTypeAction(NVT) == Expand)
6506 ExpandOp(Lo, Lo, Hi);
6510 if (VT == MVT::ppcf128) {
6511 ExpandOp(Node->getOperand(0), Lo, Hi);
6512 Lo = DAG.getNode(ISD::FNEG, MVT::f64, Lo);
6513 Hi = DAG.getNode(ISD::FNEG, MVT::f64, Hi);
6516 SDOperand Mask = (VT == MVT::f64)
6517 ? DAG.getConstantFP(BitsToDouble(1ULL << 63), VT)
6518 : DAG.getConstantFP(BitsToFloat(1U << 31), VT);
6519 Mask = DAG.getNode(ISD::BIT_CONVERT, NVT, Mask);
6520 Lo = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0));
6521 Lo = DAG.getNode(ISD::XOR, NVT, Lo, Mask);
6522 if (getTypeAction(NVT) == Expand)
6523 ExpandOp(Lo, Lo, Hi);
6526 case ISD::FCOPYSIGN: {
6527 Lo = ExpandFCOPYSIGNToBitwiseOps(Node, NVT, DAG, TLI);
6528 if (getTypeAction(NVT) == Expand)
6529 ExpandOp(Lo, Lo, Hi);
6532 case ISD::SINT_TO_FP:
6533 case ISD::UINT_TO_FP: {
6534 bool isSigned = Node->getOpcode() == ISD::SINT_TO_FP;
6535 MVT SrcVT = Node->getOperand(0).getValueType();
6537 // Promote the operand if needed. Do this before checking for
6538 // ppcf128 so conversions of i16 and i8 work.
6539 if (getTypeAction(SrcVT) == Promote) {
6540 SDOperand Tmp = PromoteOp(Node->getOperand(0));
6542 ? DAG.getNode(ISD::SIGN_EXTEND_INREG, Tmp.getValueType(), Tmp,
6543 DAG.getValueType(SrcVT))
6544 : DAG.getZeroExtendInReg(Tmp, SrcVT);
6545 Node = DAG.UpdateNodeOperands(Op, Tmp).Val;
6546 SrcVT = Node->getOperand(0).getValueType();
6549 if (VT == MVT::ppcf128 && SrcVT == MVT::i32) {
6550 static const uint64_t zero = 0;
6552 Hi = LegalizeOp(DAG.getNode(ISD::SINT_TO_FP, MVT::f64,
6553 Node->getOperand(0)));
6554 Lo = DAG.getConstantFP(APFloat(APInt(64, 1, &zero)), MVT::f64);
6556 static const uint64_t TwoE32[] = { 0x41f0000000000000LL, 0 };
6557 Hi = LegalizeOp(DAG.getNode(ISD::SINT_TO_FP, MVT::f64,
6558 Node->getOperand(0)));
6559 Lo = DAG.getConstantFP(APFloat(APInt(64, 1, &zero)), MVT::f64);
6560 Hi = DAG.getNode(ISD::BUILD_PAIR, VT, Lo, Hi);
6561 // X>=0 ? {(f64)x, 0} : {(f64)x, 0} + 2^32
6562 ExpandOp(DAG.getNode(ISD::SELECT_CC, MVT::ppcf128, Node->getOperand(0),
6563 DAG.getConstant(0, MVT::i32),
6564 DAG.getNode(ISD::FADD, MVT::ppcf128, Hi,
6566 APFloat(APInt(128, 2, TwoE32)),
6569 DAG.getCondCode(ISD::SETLT)),
6574 if (VT == MVT::ppcf128 && SrcVT == MVT::i64 && !isSigned) {
6575 // si64->ppcf128 done by libcall, below
6576 static const uint64_t TwoE64[] = { 0x43f0000000000000LL, 0 };
6577 ExpandOp(DAG.getNode(ISD::SINT_TO_FP, MVT::ppcf128, Node->getOperand(0)),
6579 Hi = DAG.getNode(ISD::BUILD_PAIR, VT, Lo, Hi);
6580 // x>=0 ? (ppcf128)(i64)x : (ppcf128)(i64)x + 2^64
6581 ExpandOp(DAG.getNode(ISD::SELECT_CC, MVT::ppcf128, Node->getOperand(0),
6582 DAG.getConstant(0, MVT::i64),
6583 DAG.getNode(ISD::FADD, MVT::ppcf128, Hi,
6585 APFloat(APInt(128, 2, TwoE64)),
6588 DAG.getCondCode(ISD::SETLT)),
6593 Lo = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP, VT,
6594 Node->getOperand(0));
6595 if (getTypeAction(Lo.getValueType()) == Expand)
6596 // float to i32 etc. can be 'expanded' to a single node.
6597 ExpandOp(Lo, Lo, Hi);
6602 // Make sure the resultant values have been legalized themselves, unless this
6603 // is a type that requires multi-step expansion.
6604 if (getTypeAction(NVT) != Expand && NVT != MVT::isVoid) {
6605 Lo = LegalizeOp(Lo);
6607 // Don't legalize the high part if it is expanded to a single node.
6608 Hi = LegalizeOp(Hi);
6611 // Remember in a map if the values will be reused later.
6613 ExpandedNodes.insert(std::make_pair(Op, std::make_pair(Lo, Hi))).second;
6614 assert(isNew && "Value already expanded?!?");
6617 /// SplitVectorOp - Given an operand of vector type, break it down into
6618 /// two smaller values, still of vector type.
6619 void SelectionDAGLegalize::SplitVectorOp(SDOperand Op, SDOperand &Lo,
6621 assert(Op.getValueType().isVector() && "Cannot split non-vector type!");
6622 SDNode *Node = Op.Val;
6623 unsigned NumElements = Op.getValueType().getVectorNumElements();
6624 assert(NumElements > 1 && "Cannot split a single element vector!");
6626 MVT NewEltVT = Op.getValueType().getVectorElementType();
6628 unsigned NewNumElts_Lo = 1 << Log2_32(NumElements-1);
6629 unsigned NewNumElts_Hi = NumElements - NewNumElts_Lo;
6631 MVT NewVT_Lo = MVT::getVectorVT(NewEltVT, NewNumElts_Lo);
6632 MVT NewVT_Hi = MVT::getVectorVT(NewEltVT, NewNumElts_Hi);
6634 // See if we already split it.
6635 std::map<SDOperand, std::pair<SDOperand, SDOperand> >::iterator I
6636 = SplitNodes.find(Op);
6637 if (I != SplitNodes.end()) {
6638 Lo = I->second.first;
6639 Hi = I->second.second;
6643 switch (Node->getOpcode()) {
6648 assert(0 && "Unhandled operation in SplitVectorOp!");
6650 Lo = DAG.getNode(ISD::UNDEF, NewVT_Lo);
6651 Hi = DAG.getNode(ISD::UNDEF, NewVT_Hi);
6653 case ISD::BUILD_PAIR:
6654 Lo = Node->getOperand(0);
6655 Hi = Node->getOperand(1);
6657 case ISD::INSERT_VECTOR_ELT: {
6658 if (ConstantSDNode *Idx = dyn_cast<ConstantSDNode>(Node->getOperand(2))) {
6659 SplitVectorOp(Node->getOperand(0), Lo, Hi);
6660 unsigned Index = Idx->getValue();
6661 SDOperand ScalarOp = Node->getOperand(1);
6662 if (Index < NewNumElts_Lo)
6663 Lo = DAG.getNode(ISD::INSERT_VECTOR_ELT, NewVT_Lo, Lo, ScalarOp,
6664 DAG.getIntPtrConstant(Index));
6666 Hi = DAG.getNode(ISD::INSERT_VECTOR_ELT, NewVT_Hi, Hi, ScalarOp,
6667 DAG.getIntPtrConstant(Index - NewNumElts_Lo));
6670 SDOperand Tmp = PerformInsertVectorEltInMemory(Node->getOperand(0),
6671 Node->getOperand(1),
6672 Node->getOperand(2));
6673 SplitVectorOp(Tmp, Lo, Hi);
6676 case ISD::VECTOR_SHUFFLE: {
6677 // Build the low part.
6678 SDOperand Mask = Node->getOperand(2);
6679 SmallVector<SDOperand, 8> Ops;
6680 MVT PtrVT = TLI.getPointerTy();
6682 // Insert all of the elements from the input that are needed. We use
6683 // buildvector of extractelement here because the input vectors will have
6684 // to be legalized, so this makes the code simpler.
6685 for (unsigned i = 0; i != NewNumElts_Lo; ++i) {
6686 SDOperand IdxNode = Mask.getOperand(i);
6687 if (IdxNode.getOpcode() == ISD::UNDEF) {
6688 Ops.push_back(DAG.getNode(ISD::UNDEF, NewEltVT));
6691 unsigned Idx = cast<ConstantSDNode>(IdxNode)->getValue();
6692 SDOperand InVec = Node->getOperand(0);
6693 if (Idx >= NumElements) {
6694 InVec = Node->getOperand(1);
6697 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, NewEltVT, InVec,
6698 DAG.getConstant(Idx, PtrVT)));
6700 Lo = DAG.getNode(ISD::BUILD_VECTOR, NewVT_Lo, &Ops[0], Ops.size());
6703 for (unsigned i = NewNumElts_Lo; i != NumElements; ++i) {
6704 SDOperand IdxNode = Mask.getOperand(i);
6705 if (IdxNode.getOpcode() == ISD::UNDEF) {
6706 Ops.push_back(DAG.getNode(ISD::UNDEF, NewEltVT));
6709 unsigned Idx = cast<ConstantSDNode>(IdxNode)->getValue();
6710 SDOperand InVec = Node->getOperand(0);
6711 if (Idx >= NumElements) {
6712 InVec = Node->getOperand(1);
6715 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, NewEltVT, InVec,
6716 DAG.getConstant(Idx, PtrVT)));
6718 Hi = DAG.getNode(ISD::BUILD_VECTOR, NewVT_Lo, &Ops[0], Ops.size());
6721 case ISD::BUILD_VECTOR: {
6722 SmallVector<SDOperand, 8> LoOps(Node->op_begin(),
6723 Node->op_begin()+NewNumElts_Lo);
6724 Lo = DAG.getNode(ISD::BUILD_VECTOR, NewVT_Lo, &LoOps[0], LoOps.size());
6726 SmallVector<SDOperand, 8> HiOps(Node->op_begin()+NewNumElts_Lo,
6728 Hi = DAG.getNode(ISD::BUILD_VECTOR, NewVT_Hi, &HiOps[0], HiOps.size());
6731 case ISD::CONCAT_VECTORS: {
6732 // FIXME: Handle non-power-of-two vectors?
6733 unsigned NewNumSubvectors = Node->getNumOperands() / 2;
6734 if (NewNumSubvectors == 1) {
6735 Lo = Node->getOperand(0);
6736 Hi = Node->getOperand(1);
6738 SmallVector<SDOperand, 8> LoOps(Node->op_begin(),
6739 Node->op_begin()+NewNumSubvectors);
6740 Lo = DAG.getNode(ISD::CONCAT_VECTORS, NewVT_Lo, &LoOps[0], LoOps.size());
6742 SmallVector<SDOperand, 8> HiOps(Node->op_begin()+NewNumSubvectors,
6744 Hi = DAG.getNode(ISD::CONCAT_VECTORS, NewVT_Hi, &HiOps[0], HiOps.size());
6749 SDOperand Cond = Node->getOperand(0);
6751 SDOperand LL, LH, RL, RH;
6752 SplitVectorOp(Node->getOperand(1), LL, LH);
6753 SplitVectorOp(Node->getOperand(2), RL, RH);
6755 if (Cond.getValueType().isVector()) {
6756 // Handle a vector merge.
6758 SplitVectorOp(Cond, CL, CH);
6759 Lo = DAG.getNode(Node->getOpcode(), NewVT_Lo, CL, LL, RL);
6760 Hi = DAG.getNode(Node->getOpcode(), NewVT_Hi, CH, LH, RH);
6762 // Handle a simple select with vector operands.
6763 Lo = DAG.getNode(Node->getOpcode(), NewVT_Lo, Cond, LL, RL);
6764 Hi = DAG.getNode(Node->getOpcode(), NewVT_Hi, Cond, LH, RH);
6768 case ISD::SELECT_CC: {
6769 SDOperand CondLHS = Node->getOperand(0);
6770 SDOperand CondRHS = Node->getOperand(1);
6771 SDOperand CondCode = Node->getOperand(4);
6773 SDOperand LL, LH, RL, RH;
6774 SplitVectorOp(Node->getOperand(2), LL, LH);
6775 SplitVectorOp(Node->getOperand(3), RL, RH);
6777 // Handle a simple select with vector operands.
6778 Lo = DAG.getNode(ISD::SELECT_CC, NewVT_Lo, CondLHS, CondRHS,
6780 Hi = DAG.getNode(ISD::SELECT_CC, NewVT_Hi, CondLHS, CondRHS,
6785 SDOperand LL, LH, RL, RH;
6786 SplitVectorOp(Node->getOperand(0), LL, LH);
6787 SplitVectorOp(Node->getOperand(1), RL, RH);
6788 Lo = DAG.getNode(ISD::VSETCC, NewVT_Lo, LL, RL, Node->getOperand(2));
6789 Hi = DAG.getNode(ISD::VSETCC, NewVT_Hi, LH, RH, Node->getOperand(2));
6808 SDOperand LL, LH, RL, RH;
6809 SplitVectorOp(Node->getOperand(0), LL, LH);
6810 SplitVectorOp(Node->getOperand(1), RL, RH);
6812 Lo = DAG.getNode(Node->getOpcode(), NewVT_Lo, LL, RL);
6813 Hi = DAG.getNode(Node->getOpcode(), NewVT_Hi, LH, RH);
6818 SplitVectorOp(Node->getOperand(0), L, H);
6820 Lo = DAG.getNode(Node->getOpcode(), NewVT_Lo, L, Node->getOperand(1));
6821 Hi = DAG.getNode(Node->getOpcode(), NewVT_Hi, H, Node->getOperand(1));
6832 case ISD::FP_TO_SINT:
6833 case ISD::FP_TO_UINT:
6834 case ISD::SINT_TO_FP:
6835 case ISD::UINT_TO_FP: {
6837 SplitVectorOp(Node->getOperand(0), L, H);
6839 Lo = DAG.getNode(Node->getOpcode(), NewVT_Lo, L);
6840 Hi = DAG.getNode(Node->getOpcode(), NewVT_Hi, H);
6844 LoadSDNode *LD = cast<LoadSDNode>(Node);
6845 SDOperand Ch = LD->getChain();
6846 SDOperand Ptr = LD->getBasePtr();
6847 const Value *SV = LD->getSrcValue();
6848 int SVOffset = LD->getSrcValueOffset();
6849 unsigned Alignment = LD->getAlignment();
6850 bool isVolatile = LD->isVolatile();
6852 Lo = DAG.getLoad(NewVT_Lo, Ch, Ptr, SV, SVOffset, isVolatile, Alignment);
6853 unsigned IncrementSize = NewNumElts_Lo * NewEltVT.getSizeInBits()/8;
6854 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
6855 DAG.getIntPtrConstant(IncrementSize));
6856 SVOffset += IncrementSize;
6857 Alignment = MinAlign(Alignment, IncrementSize);
6858 Hi = DAG.getLoad(NewVT_Hi, Ch, Ptr, SV, SVOffset, isVolatile, Alignment);
6860 // Build a factor node to remember that this load is independent of the
6862 SDOperand TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
6865 // Remember that we legalized the chain.
6866 AddLegalizedOperand(Op.getValue(1), LegalizeOp(TF));
6869 case ISD::BIT_CONVERT: {
6870 // We know the result is a vector. The input may be either a vector or a
6872 SDOperand InOp = Node->getOperand(0);
6873 if (!InOp.getValueType().isVector() ||
6874 InOp.getValueType().getVectorNumElements() == 1) {
6875 // The input is a scalar or single-element vector.
6876 // Lower to a store/load so that it can be split.
6877 // FIXME: this could be improved probably.
6878 unsigned LdAlign = TLI.getTargetData()->getPrefTypeAlignment(
6879 Op.getValueType().getTypeForMVT());
6880 SDOperand Ptr = DAG.CreateStackTemporary(InOp.getValueType(), LdAlign);
6881 int FI = cast<FrameIndexSDNode>(Ptr.Val)->getIndex();
6883 SDOperand St = DAG.getStore(DAG.getEntryNode(),
6885 PseudoSourceValue::getFixedStack(FI), 0);
6886 InOp = DAG.getLoad(Op.getValueType(), St, Ptr,
6887 PseudoSourceValue::getFixedStack(FI), 0);
6889 // Split the vector and convert each of the pieces now.
6890 SplitVectorOp(InOp, Lo, Hi);
6891 Lo = DAG.getNode(ISD::BIT_CONVERT, NewVT_Lo, Lo);
6892 Hi = DAG.getNode(ISD::BIT_CONVERT, NewVT_Hi, Hi);
6897 // Remember in a map if the values will be reused later.
6899 SplitNodes.insert(std::make_pair(Op, std::make_pair(Lo, Hi))).second;
6900 assert(isNew && "Value already split?!?");
6904 /// ScalarizeVectorOp - Given an operand of single-element vector type
6905 /// (e.g. v1f32), convert it into the equivalent operation that returns a
6906 /// scalar (e.g. f32) value.
6907 SDOperand SelectionDAGLegalize::ScalarizeVectorOp(SDOperand Op) {
6908 assert(Op.getValueType().isVector() && "Bad ScalarizeVectorOp invocation!");
6909 SDNode *Node = Op.Val;
6910 MVT NewVT = Op.getValueType().getVectorElementType();
6911 assert(Op.getValueType().getVectorNumElements() == 1);
6913 // See if we already scalarized it.
6914 std::map<SDOperand, SDOperand>::iterator I = ScalarizedNodes.find(Op);
6915 if (I != ScalarizedNodes.end()) return I->second;
6918 switch (Node->getOpcode()) {
6921 Node->dump(&DAG); cerr << "\n";
6923 assert(0 && "Unknown vector operation in ScalarizeVectorOp!");
6940 Result = DAG.getNode(Node->getOpcode(),
6942 ScalarizeVectorOp(Node->getOperand(0)),
6943 ScalarizeVectorOp(Node->getOperand(1)));
6950 Result = DAG.getNode(Node->getOpcode(),
6952 ScalarizeVectorOp(Node->getOperand(0)));
6955 Result = DAG.getNode(Node->getOpcode(),
6957 ScalarizeVectorOp(Node->getOperand(0)),
6958 Node->getOperand(1));
6961 LoadSDNode *LD = cast<LoadSDNode>(Node);
6962 SDOperand Ch = LegalizeOp(LD->getChain()); // Legalize the chain.
6963 SDOperand Ptr = LegalizeOp(LD->getBasePtr()); // Legalize the pointer.
6965 const Value *SV = LD->getSrcValue();
6966 int SVOffset = LD->getSrcValueOffset();
6967 Result = DAG.getLoad(NewVT, Ch, Ptr, SV, SVOffset,
6968 LD->isVolatile(), LD->getAlignment());
6970 // Remember that we legalized the chain.
6971 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
6974 case ISD::BUILD_VECTOR:
6975 Result = Node->getOperand(0);
6977 case ISD::INSERT_VECTOR_ELT:
6978 // Returning the inserted scalar element.
6979 Result = Node->getOperand(1);
6981 case ISD::CONCAT_VECTORS:
6982 assert(Node->getOperand(0).getValueType() == NewVT &&
6983 "Concat of non-legal vectors not yet supported!");
6984 Result = Node->getOperand(0);
6986 case ISD::VECTOR_SHUFFLE: {
6987 // Figure out if the scalar is the LHS or RHS and return it.
6988 SDOperand EltNum = Node->getOperand(2).getOperand(0);
6989 if (cast<ConstantSDNode>(EltNum)->getValue())
6990 Result = ScalarizeVectorOp(Node->getOperand(1));
6992 Result = ScalarizeVectorOp(Node->getOperand(0));
6995 case ISD::EXTRACT_SUBVECTOR:
6996 Result = Node->getOperand(0);
6997 assert(Result.getValueType() == NewVT);
6999 case ISD::BIT_CONVERT: {
7000 SDOperand Op0 = Op.getOperand(0);
7001 if (Op0.getValueType().getVectorNumElements() == 1)
7002 Op0 = ScalarizeVectorOp(Op0);
7003 Result = DAG.getNode(ISD::BIT_CONVERT, NewVT, Op0);
7007 Result = DAG.getNode(ISD::SELECT, NewVT, Op.getOperand(0),
7008 ScalarizeVectorOp(Op.getOperand(1)),
7009 ScalarizeVectorOp(Op.getOperand(2)));
7011 case ISD::SELECT_CC:
7012 Result = DAG.getNode(ISD::SELECT_CC, NewVT, Node->getOperand(0),
7013 Node->getOperand(1),
7014 ScalarizeVectorOp(Op.getOperand(2)),
7015 ScalarizeVectorOp(Op.getOperand(3)),
7016 Node->getOperand(4));
7019 SDOperand Op0 = ScalarizeVectorOp(Op.getOperand(0));
7020 SDOperand Op1 = ScalarizeVectorOp(Op.getOperand(1));
7021 Result = DAG.getNode(ISD::SETCC, TLI.getSetCCResultType(Op0), Op0, Op1,
7023 Result = DAG.getNode(ISD::SELECT, NewVT, Result,
7024 DAG.getConstant(-1ULL, NewVT),
7025 DAG.getConstant(0ULL, NewVT));
7030 if (TLI.isTypeLegal(NewVT))
7031 Result = LegalizeOp(Result);
7032 bool isNew = ScalarizedNodes.insert(std::make_pair(Op, Result)).second;
7033 assert(isNew && "Value already scalarized?");
7038 // SelectionDAG::Legalize - This is the entry point for the file.
7040 void SelectionDAG::Legalize() {
7041 if (ViewLegalizeDAGs) viewGraph();
7043 /// run - This is the main entry point to this class.
7045 SelectionDAGLegalize(*this).LegalizeDAG();