1 //===-- LegalizeDAG.cpp - Implement SelectionDAG::Legalize ----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the SelectionDAG::Legalize method.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/CodeGen/SelectionDAG.h"
15 #include "llvm/CodeGen/MachineFunction.h"
16 #include "llvm/CodeGen/MachineFrameInfo.h"
17 #include "llvm/CodeGen/MachineJumpTableInfo.h"
18 #include "llvm/CodeGen/MachineModuleInfo.h"
19 #include "llvm/Target/TargetFrameInfo.h"
20 #include "llvm/Target/TargetLowering.h"
21 #include "llvm/Target/TargetData.h"
22 #include "llvm/Target/TargetMachine.h"
23 #include "llvm/Target/TargetOptions.h"
24 #include "llvm/CallingConv.h"
25 #include "llvm/Constants.h"
26 #include "llvm/DerivedTypes.h"
27 #include "llvm/Support/CommandLine.h"
28 #include "llvm/Support/Compiler.h"
29 #include "llvm/Support/MathExtras.h"
30 #include "llvm/ADT/DenseMap.h"
31 #include "llvm/ADT/SmallVector.h"
32 #include "llvm/ADT/SmallPtrSet.h"
38 ViewLegalizeDAGs("view-legalize-dags", cl::Hidden,
39 cl::desc("Pop up a window to show dags before legalize"));
41 static const bool ViewLegalizeDAGs = 0;
44 //===----------------------------------------------------------------------===//
45 /// SelectionDAGLegalize - This takes an arbitrary SelectionDAG as input and
46 /// hacks on it until the target machine can handle it. This involves
47 /// eliminating value sizes the machine cannot handle (promoting small sizes to
48 /// large sizes or splitting up large values into small values) as well as
49 /// eliminating operations the machine cannot handle.
51 /// This code also does a small amount of optimization and recognition of idioms
52 /// as part of its processing. For example, if a target does not support a
53 /// 'setcc' instruction efficiently, but does support 'brcc' instruction, this
54 /// will attempt merge setcc and brc instructions into brcc's.
57 class VISIBILITY_HIDDEN SelectionDAGLegalize {
61 // Libcall insertion helpers.
63 /// LastCALLSEQ_END - This keeps track of the CALLSEQ_END node that has been
64 /// legalized. We use this to ensure that calls are properly serialized
65 /// against each other, including inserted libcalls.
66 SDOperand LastCALLSEQ_END;
68 /// IsLegalizingCall - This member is used *only* for purposes of providing
69 /// helpful assertions that a libcall isn't created while another call is
70 /// being legalized (which could lead to non-serialized call sequences).
71 bool IsLegalizingCall;
74 Legal, // The target natively supports this operation.
75 Promote, // This operation should be executed in a larger type.
76 Expand // Try to expand this to other ops, otherwise use a libcall.
79 /// ValueTypeActions - This is a bitvector that contains two bits for each
80 /// value type, where the two bits correspond to the LegalizeAction enum.
81 /// This can be queried with "getTypeAction(VT)".
82 TargetLowering::ValueTypeActionImpl ValueTypeActions;
84 /// LegalizedNodes - For nodes that are of legal width, and that have more
85 /// than one use, this map indicates what regularized operand to use. This
86 /// allows us to avoid legalizing the same thing more than once.
87 DenseMap<SDOperand, SDOperand> LegalizedNodes;
89 /// PromotedNodes - For nodes that are below legal width, and that have more
90 /// than one use, this map indicates what promoted value to use. This allows
91 /// us to avoid promoting the same thing more than once.
92 DenseMap<SDOperand, SDOperand> PromotedNodes;
94 /// ExpandedNodes - For nodes that need to be expanded this map indicates
95 /// which which operands are the expanded version of the input. This allows
96 /// us to avoid expanding the same node more than once.
97 DenseMap<SDOperand, std::pair<SDOperand, SDOperand> > ExpandedNodes;
99 /// SplitNodes - For vector nodes that need to be split, this map indicates
100 /// which which operands are the split version of the input. This allows us
101 /// to avoid splitting the same node more than once.
102 std::map<SDOperand, std::pair<SDOperand, SDOperand> > SplitNodes;
104 /// ScalarizedNodes - For nodes that need to be converted from vector types to
105 /// scalar types, this contains the mapping of ones we have already
106 /// processed to the result.
107 std::map<SDOperand, SDOperand> ScalarizedNodes;
109 void AddLegalizedOperand(SDOperand From, SDOperand To) {
110 LegalizedNodes.insert(std::make_pair(From, To));
111 // If someone requests legalization of the new node, return itself.
113 LegalizedNodes.insert(std::make_pair(To, To));
115 void AddPromotedOperand(SDOperand From, SDOperand To) {
116 bool isNew = PromotedNodes.insert(std::make_pair(From, To));
117 assert(isNew && "Got into the map somehow?");
118 // If someone requests legalization of the new node, return itself.
119 LegalizedNodes.insert(std::make_pair(To, To));
124 SelectionDAGLegalize(SelectionDAG &DAG);
126 /// getTypeAction - Return how we should legalize values of this type, either
127 /// it is already legal or we need to expand it into multiple registers of
128 /// smaller integer type, or we need to promote it to a larger type.
129 LegalizeAction getTypeAction(MVT::ValueType VT) const {
130 return (LegalizeAction)ValueTypeActions.getTypeAction(VT);
133 /// isTypeLegal - Return true if this type is legal on this target.
135 bool isTypeLegal(MVT::ValueType VT) const {
136 return getTypeAction(VT) == Legal;
142 /// HandleOp - Legalize, Promote, or Expand the specified operand as
143 /// appropriate for its type.
144 void HandleOp(SDOperand Op);
146 /// LegalizeOp - We know that the specified value has a legal type.
147 /// Recursively ensure that the operands have legal types, then return the
149 SDOperand LegalizeOp(SDOperand O);
151 /// UnrollVectorOp - We know that the given vector has a legal type, however
152 /// the operation it performs is not legal and is an operation that we have
153 /// no way of lowering. "Unroll" the vector, splitting out the scalars and
154 /// operating on each element individually.
155 SDOperand UnrollVectorOp(SDOperand O);
157 /// PromoteOp - Given an operation that produces a value in an invalid type,
158 /// promote it to compute the value into a larger type. The produced value
159 /// will have the correct bits for the low portion of the register, but no
160 /// guarantee is made about the top bits: it may be zero, sign-extended, or
162 SDOperand PromoteOp(SDOperand O);
164 /// ExpandOp - Expand the specified SDOperand into its two component pieces
165 /// Lo&Hi. Note that the Op MUST be an expanded type. As a result of this,
166 /// the LegalizeNodes map is filled in for any results that are not expanded,
167 /// the ExpandedNodes map is filled in for any results that are expanded, and
168 /// the Lo/Hi values are returned. This applies to integer types and Vector
170 void ExpandOp(SDOperand O, SDOperand &Lo, SDOperand &Hi);
172 /// SplitVectorOp - Given an operand of vector type, break it down into
173 /// two smaller values.
174 void SplitVectorOp(SDOperand O, SDOperand &Lo, SDOperand &Hi);
176 /// ScalarizeVectorOp - Given an operand of single-element vector type
177 /// (e.g. v1f32), convert it into the equivalent operation that returns a
178 /// scalar (e.g. f32) value.
179 SDOperand ScalarizeVectorOp(SDOperand O);
181 /// isShuffleLegal - Return true if a vector shuffle is legal with the
182 /// specified mask and type. Targets can specify exactly which masks they
183 /// support and the code generator is tasked with not creating illegal masks.
185 /// Note that this will also return true for shuffles that are promoted to a
188 /// If this is a legal shuffle, this method returns the (possibly promoted)
189 /// build_vector Mask. If it's not a legal shuffle, it returns null.
190 SDNode *isShuffleLegal(MVT::ValueType VT, SDOperand Mask) const;
192 bool LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest,
193 SmallPtrSet<SDNode*, 32> &NodesLeadingTo);
195 void LegalizeSetCCOperands(SDOperand &LHS, SDOperand &RHS, SDOperand &CC);
197 SDOperand ExpandLibCall(const char *Name, SDNode *Node, bool isSigned,
199 SDOperand ExpandIntToFP(bool isSigned, MVT::ValueType DestTy,
202 SDOperand EmitStackConvert(SDOperand SrcOp, MVT::ValueType SlotVT,
203 MVT::ValueType DestVT);
204 SDOperand ExpandBUILD_VECTOR(SDNode *Node);
205 SDOperand ExpandSCALAR_TO_VECTOR(SDNode *Node);
206 SDOperand ExpandLegalINT_TO_FP(bool isSigned,
208 MVT::ValueType DestVT);
209 SDOperand PromoteLegalINT_TO_FP(SDOperand LegalOp, MVT::ValueType DestVT,
211 SDOperand PromoteLegalFP_TO_INT(SDOperand LegalOp, MVT::ValueType DestVT,
214 SDOperand ExpandBSWAP(SDOperand Op);
215 SDOperand ExpandBitCount(unsigned Opc, SDOperand Op);
216 bool ExpandShift(unsigned Opc, SDOperand Op, SDOperand Amt,
217 SDOperand &Lo, SDOperand &Hi);
218 void ExpandShiftParts(unsigned NodeOp, SDOperand Op, SDOperand Amt,
219 SDOperand &Lo, SDOperand &Hi);
221 SDOperand ExpandEXTRACT_SUBVECTOR(SDOperand Op);
222 SDOperand ExpandEXTRACT_VECTOR_ELT(SDOperand Op);
226 /// isVectorShuffleLegal - Return true if a vector shuffle is legal with the
227 /// specified mask and type. Targets can specify exactly which masks they
228 /// support and the code generator is tasked with not creating illegal masks.
230 /// Note that this will also return true for shuffles that are promoted to a
232 SDNode *SelectionDAGLegalize::isShuffleLegal(MVT::ValueType VT,
233 SDOperand Mask) const {
234 switch (TLI.getOperationAction(ISD::VECTOR_SHUFFLE, VT)) {
236 case TargetLowering::Legal:
237 case TargetLowering::Custom:
239 case TargetLowering::Promote: {
240 // If this is promoted to a different type, convert the shuffle mask and
241 // ask if it is legal in the promoted type!
242 MVT::ValueType NVT = TLI.getTypeToPromoteTo(ISD::VECTOR_SHUFFLE, VT);
244 // If we changed # elements, change the shuffle mask.
245 unsigned NumEltsGrowth =
246 MVT::getVectorNumElements(NVT) / MVT::getVectorNumElements(VT);
247 assert(NumEltsGrowth && "Cannot promote to vector type with fewer elts!");
248 if (NumEltsGrowth > 1) {
249 // Renumber the elements.
250 SmallVector<SDOperand, 8> Ops;
251 for (unsigned i = 0, e = Mask.getNumOperands(); i != e; ++i) {
252 SDOperand InOp = Mask.getOperand(i);
253 for (unsigned j = 0; j != NumEltsGrowth; ++j) {
254 if (InOp.getOpcode() == ISD::UNDEF)
255 Ops.push_back(DAG.getNode(ISD::UNDEF, MVT::i32));
257 unsigned InEltNo = cast<ConstantSDNode>(InOp)->getValue();
258 Ops.push_back(DAG.getConstant(InEltNo*NumEltsGrowth+j, MVT::i32));
262 Mask = DAG.getNode(ISD::BUILD_VECTOR, NVT, &Ops[0], Ops.size());
268 return TLI.isShuffleMaskLegal(Mask, VT) ? Mask.Val : 0;
271 SelectionDAGLegalize::SelectionDAGLegalize(SelectionDAG &dag)
272 : TLI(dag.getTargetLoweringInfo()), DAG(dag),
273 ValueTypeActions(TLI.getValueTypeActions()) {
274 assert(MVT::LAST_VALUETYPE <= 32 &&
275 "Too many value types for ValueTypeActions to hold!");
278 /// ComputeTopDownOrdering - Compute a top-down ordering of the dag, where Order
279 /// contains all of a nodes operands before it contains the node.
280 static void ComputeTopDownOrdering(SelectionDAG &DAG,
281 SmallVector<SDNode*, 64> &Order) {
283 DenseMap<SDNode*, unsigned> Visited;
284 std::vector<SDNode*> Worklist;
285 Worklist.reserve(128);
287 // Compute ordering from all of the leaves in the graphs, those (like the
288 // entry node) that have no operands.
289 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(),
290 E = DAG.allnodes_end(); I != E; ++I) {
291 if (I->getNumOperands() == 0) {
293 Worklist.push_back(I);
297 while (!Worklist.empty()) {
298 SDNode *N = Worklist.back();
301 if (++Visited[N] != N->getNumOperands())
302 continue; // Haven't visited all operands yet
306 // Now that we have N in, add anything that uses it if all of their operands
308 for (SDNode::use_iterator UI = N->use_begin(), E = N->use_end();
310 Worklist.push_back(*UI);
313 assert(Order.size() == Visited.size() &&
315 (unsigned)std::distance(DAG.allnodes_begin(), DAG.allnodes_end()) &&
316 "Error: DAG is cyclic!");
320 void SelectionDAGLegalize::LegalizeDAG() {
321 LastCALLSEQ_END = DAG.getEntryNode();
322 IsLegalizingCall = false;
324 // The legalize process is inherently a bottom-up recursive process (users
325 // legalize their uses before themselves). Given infinite stack space, we
326 // could just start legalizing on the root and traverse the whole graph. In
327 // practice however, this causes us to run out of stack space on large basic
328 // blocks. To avoid this problem, compute an ordering of the nodes where each
329 // node is only legalized after all of its operands are legalized.
330 SmallVector<SDNode*, 64> Order;
331 ComputeTopDownOrdering(DAG, Order);
333 for (unsigned i = 0, e = Order.size(); i != e; ++i)
334 HandleOp(SDOperand(Order[i], 0));
336 // Finally, it's possible the root changed. Get the new root.
337 SDOperand OldRoot = DAG.getRoot();
338 assert(LegalizedNodes.count(OldRoot) && "Root didn't get legalized?");
339 DAG.setRoot(LegalizedNodes[OldRoot]);
341 ExpandedNodes.clear();
342 LegalizedNodes.clear();
343 PromotedNodes.clear();
345 ScalarizedNodes.clear();
347 // Remove dead nodes now.
348 DAG.RemoveDeadNodes();
352 /// FindCallEndFromCallStart - Given a chained node that is part of a call
353 /// sequence, find the CALLSEQ_END node that terminates the call sequence.
354 static SDNode *FindCallEndFromCallStart(SDNode *Node) {
355 if (Node->getOpcode() == ISD::CALLSEQ_END)
357 if (Node->use_empty())
358 return 0; // No CallSeqEnd
360 // The chain is usually at the end.
361 SDOperand TheChain(Node, Node->getNumValues()-1);
362 if (TheChain.getValueType() != MVT::Other) {
363 // Sometimes it's at the beginning.
364 TheChain = SDOperand(Node, 0);
365 if (TheChain.getValueType() != MVT::Other) {
366 // Otherwise, hunt for it.
367 for (unsigned i = 1, e = Node->getNumValues(); i != e; ++i)
368 if (Node->getValueType(i) == MVT::Other) {
369 TheChain = SDOperand(Node, i);
373 // Otherwise, we walked into a node without a chain.
374 if (TheChain.getValueType() != MVT::Other)
379 for (SDNode::use_iterator UI = Node->use_begin(),
380 E = Node->use_end(); UI != E; ++UI) {
382 // Make sure to only follow users of our token chain.
384 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i)
385 if (User->getOperand(i) == TheChain)
386 if (SDNode *Result = FindCallEndFromCallStart(User))
392 /// FindCallStartFromCallEnd - Given a chained node that is part of a call
393 /// sequence, find the CALLSEQ_START node that initiates the call sequence.
394 static SDNode *FindCallStartFromCallEnd(SDNode *Node) {
395 assert(Node && "Didn't find callseq_start for a call??");
396 if (Node->getOpcode() == ISD::CALLSEQ_START) return Node;
398 assert(Node->getOperand(0).getValueType() == MVT::Other &&
399 "Node doesn't have a token chain argument!");
400 return FindCallStartFromCallEnd(Node->getOperand(0).Val);
403 /// LegalizeAllNodesNotLeadingTo - Recursively walk the uses of N, looking to
404 /// see if any uses can reach Dest. If no dest operands can get to dest,
405 /// legalize them, legalize ourself, and return false, otherwise, return true.
407 /// Keep track of the nodes we fine that actually do lead to Dest in
408 /// NodesLeadingTo. This avoids retraversing them exponential number of times.
410 bool SelectionDAGLegalize::LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest,
411 SmallPtrSet<SDNode*, 32> &NodesLeadingTo) {
412 if (N == Dest) return true; // N certainly leads to Dest :)
414 // If we've already processed this node and it does lead to Dest, there is no
415 // need to reprocess it.
416 if (NodesLeadingTo.count(N)) return true;
418 // If the first result of this node has been already legalized, then it cannot
420 switch (getTypeAction(N->getValueType(0))) {
422 if (LegalizedNodes.count(SDOperand(N, 0))) return false;
425 if (PromotedNodes.count(SDOperand(N, 0))) return false;
428 if (ExpandedNodes.count(SDOperand(N, 0))) return false;
432 // Okay, this node has not already been legalized. Check and legalize all
433 // operands. If none lead to Dest, then we can legalize this node.
434 bool OperandsLeadToDest = false;
435 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
436 OperandsLeadToDest |= // If an operand leads to Dest, so do we.
437 LegalizeAllNodesNotLeadingTo(N->getOperand(i).Val, Dest, NodesLeadingTo);
439 if (OperandsLeadToDest) {
440 NodesLeadingTo.insert(N);
444 // Okay, this node looks safe, legalize it and return false.
445 HandleOp(SDOperand(N, 0));
449 /// HandleOp - Legalize, Promote, or Expand the specified operand as
450 /// appropriate for its type.
451 void SelectionDAGLegalize::HandleOp(SDOperand Op) {
452 MVT::ValueType VT = Op.getValueType();
453 switch (getTypeAction(VT)) {
454 default: assert(0 && "Bad type action!");
455 case Legal: (void)LegalizeOp(Op); break;
456 case Promote: (void)PromoteOp(Op); break;
458 if (!MVT::isVector(VT)) {
459 // If this is an illegal scalar, expand it into its two component
462 if (Op.getOpcode() == ISD::TargetConstant)
463 break; // Allow illegal target nodes.
465 } else if (MVT::getVectorNumElements(VT) == 1) {
466 // If this is an illegal single element vector, convert it to a
468 (void)ScalarizeVectorOp(Op);
470 // Otherwise, this is an illegal multiple element vector.
471 // Split it in half and legalize both parts.
473 SplitVectorOp(Op, X, Y);
479 /// ExpandConstantFP - Expands the ConstantFP node to an integer constant or
480 /// a load from the constant pool.
481 static SDOperand ExpandConstantFP(ConstantFPSDNode *CFP, bool UseCP,
482 SelectionDAG &DAG, TargetLowering &TLI) {
485 // If a FP immediate is precise when represented as a float and if the
486 // target can do an extending load from float to double, we put it into
487 // the constant pool as a float, even if it's is statically typed as a
489 MVT::ValueType VT = CFP->getValueType(0);
490 bool isDouble = VT == MVT::f64;
491 ConstantFP *LLVMC = ConstantFP::get(MVT::getTypeForValueType(VT),
494 if (VT!=MVT::f64 && VT!=MVT::f32)
495 assert(0 && "Invalid type expansion");
496 return DAG.getConstant(LLVMC->getValueAPF().convertToAPInt().getZExtValue(),
497 isDouble ? MVT::i64 : MVT::i32);
500 if (isDouble && CFP->isValueValidForType(MVT::f32, CFP->getValueAPF()) &&
501 // Only do this if the target has a native EXTLOAD instruction from f32.
502 // Do not try to be clever about long doubles (so far)
503 TLI.isLoadXLegal(ISD::EXTLOAD, MVT::f32)) {
504 LLVMC = cast<ConstantFP>(ConstantExpr::getFPTrunc(LLVMC,Type::FloatTy));
509 SDOperand CPIdx = DAG.getConstantPool(LLVMC, TLI.getPointerTy());
511 return DAG.getExtLoad(ISD::EXTLOAD, MVT::f64, DAG.getEntryNode(),
512 CPIdx, NULL, 0, MVT::f32);
514 return DAG.getLoad(VT, DAG.getEntryNode(), CPIdx, NULL, 0);
519 /// ExpandFCOPYSIGNToBitwiseOps - Expands fcopysign to a series of bitwise
522 SDOperand ExpandFCOPYSIGNToBitwiseOps(SDNode *Node, MVT::ValueType NVT,
523 SelectionDAG &DAG, TargetLowering &TLI) {
524 MVT::ValueType VT = Node->getValueType(0);
525 MVT::ValueType SrcVT = Node->getOperand(1).getValueType();
526 assert((SrcVT == MVT::f32 || SrcVT == MVT::f64) &&
527 "fcopysign expansion only supported for f32 and f64");
528 MVT::ValueType SrcNVT = (SrcVT == MVT::f64) ? MVT::i64 : MVT::i32;
530 // First get the sign bit of second operand.
531 SDOperand Mask1 = (SrcVT == MVT::f64)
532 ? DAG.getConstantFP(BitsToDouble(1ULL << 63), SrcVT)
533 : DAG.getConstantFP(BitsToFloat(1U << 31), SrcVT);
534 Mask1 = DAG.getNode(ISD::BIT_CONVERT, SrcNVT, Mask1);
535 SDOperand SignBit= DAG.getNode(ISD::BIT_CONVERT, SrcNVT, Node->getOperand(1));
536 SignBit = DAG.getNode(ISD::AND, SrcNVT, SignBit, Mask1);
537 // Shift right or sign-extend it if the two operands have different types.
538 int SizeDiff = MVT::getSizeInBits(SrcNVT) - MVT::getSizeInBits(NVT);
540 SignBit = DAG.getNode(ISD::SRL, SrcNVT, SignBit,
541 DAG.getConstant(SizeDiff, TLI.getShiftAmountTy()));
542 SignBit = DAG.getNode(ISD::TRUNCATE, NVT, SignBit);
543 } else if (SizeDiff < 0)
544 SignBit = DAG.getNode(ISD::SIGN_EXTEND, NVT, SignBit);
546 // Clear the sign bit of first operand.
547 SDOperand Mask2 = (VT == MVT::f64)
548 ? DAG.getConstantFP(BitsToDouble(~(1ULL << 63)), VT)
549 : DAG.getConstantFP(BitsToFloat(~(1U << 31)), VT);
550 Mask2 = DAG.getNode(ISD::BIT_CONVERT, NVT, Mask2);
551 SDOperand Result = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0));
552 Result = DAG.getNode(ISD::AND, NVT, Result, Mask2);
554 // Or the value with the sign bit.
555 Result = DAG.getNode(ISD::OR, NVT, Result, SignBit);
559 /// ExpandUnalignedStore - Expands an unaligned store to 2 half-size stores.
561 SDOperand ExpandUnalignedStore(StoreSDNode *ST, SelectionDAG &DAG,
562 TargetLowering &TLI) {
563 SDOperand Chain = ST->getChain();
564 SDOperand Ptr = ST->getBasePtr();
565 SDOperand Val = ST->getValue();
566 MVT::ValueType VT = Val.getValueType();
567 int Alignment = ST->getAlignment();
568 int SVOffset = ST->getSrcValueOffset();
569 if (MVT::isFloatingPoint(ST->getMemoryVT())) {
570 // Expand to a bitconvert of the value to the integer type of the
571 // same size, then a (misaligned) int store.
572 MVT::ValueType intVT;
575 else if (VT==MVT::f32)
578 assert(0 && "Unaligned load of unsupported floating point type");
580 SDOperand Result = DAG.getNode(ISD::BIT_CONVERT, intVT, Val);
581 return DAG.getStore(Chain, Result, Ptr, ST->getSrcValue(),
582 SVOffset, ST->isVolatile(), Alignment);
584 assert(MVT::isInteger(ST->getMemoryVT()) &&
585 "Unaligned store of unknown type.");
586 // Get the half-size VT
587 MVT::ValueType NewStoredVT = ST->getMemoryVT() - 1;
588 int NumBits = MVT::getSizeInBits(NewStoredVT);
589 int IncrementSize = NumBits / 8;
591 // Divide the stored value in two parts.
592 SDOperand ShiftAmount = DAG.getConstant(NumBits, TLI.getShiftAmountTy());
594 SDOperand Hi = DAG.getNode(ISD::SRL, VT, Val, ShiftAmount);
596 // Store the two parts
597 SDOperand Store1, Store2;
598 Store1 = DAG.getTruncStore(Chain, TLI.isLittleEndian()?Lo:Hi, Ptr,
599 ST->getSrcValue(), SVOffset, NewStoredVT,
600 ST->isVolatile(), Alignment);
601 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
602 DAG.getConstant(IncrementSize, TLI.getPointerTy()));
603 Alignment = MinAlign(Alignment, IncrementSize);
604 Store2 = DAG.getTruncStore(Chain, TLI.isLittleEndian()?Hi:Lo, Ptr,
605 ST->getSrcValue(), SVOffset + IncrementSize,
606 NewStoredVT, ST->isVolatile(), Alignment);
608 return DAG.getNode(ISD::TokenFactor, MVT::Other, Store1, Store2);
611 /// ExpandUnalignedLoad - Expands an unaligned load to 2 half-size loads.
613 SDOperand ExpandUnalignedLoad(LoadSDNode *LD, SelectionDAG &DAG,
614 TargetLowering &TLI) {
615 int SVOffset = LD->getSrcValueOffset();
616 SDOperand Chain = LD->getChain();
617 SDOperand Ptr = LD->getBasePtr();
618 MVT::ValueType VT = LD->getValueType(0);
619 MVT::ValueType LoadedVT = LD->getMemoryVT();
620 if (MVT::isFloatingPoint(VT) && !MVT::isVector(VT)) {
621 // Expand to a (misaligned) integer load of the same size,
622 // then bitconvert to floating point.
623 MVT::ValueType intVT;
624 if (LoadedVT == MVT::f64)
626 else if (LoadedVT == MVT::f32)
629 assert(0 && "Unaligned load of unsupported floating point type");
631 SDOperand newLoad = DAG.getLoad(intVT, Chain, Ptr, LD->getSrcValue(),
632 SVOffset, LD->isVolatile(),
634 SDOperand Result = DAG.getNode(ISD::BIT_CONVERT, LoadedVT, newLoad);
636 Result = DAG.getNode(ISD::FP_EXTEND, VT, Result);
638 SDOperand Ops[] = { Result, Chain };
639 return DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(VT, MVT::Other),
642 assert((MVT::isInteger(LoadedVT) || MVT::isVector(LoadedVT)) &&
643 "Unaligned load of unsupported type.");
645 // Compute the new VT that is half the size of the old one. We either have an
646 // integer MVT or we have a vector MVT.
647 unsigned NumBits = MVT::getSizeInBits(LoadedVT);
648 MVT::ValueType NewLoadedVT;
649 if (!MVT::isVector(LoadedVT)) {
650 NewLoadedVT = MVT::getIntegerType(NumBits/2);
652 // FIXME: This is not right for <1 x anything> it is also not right for
653 // non-power-of-two vectors.
654 NewLoadedVT = MVT::getVectorType(MVT::getVectorElementType(LoadedVT),
655 MVT::getVectorNumElements(LoadedVT)/2);
659 unsigned Alignment = LD->getAlignment();
660 unsigned IncrementSize = NumBits / 8;
661 ISD::LoadExtType HiExtType = LD->getExtensionType();
663 // If the original load is NON_EXTLOAD, the hi part load must be ZEXTLOAD.
664 if (HiExtType == ISD::NON_EXTLOAD)
665 HiExtType = ISD::ZEXTLOAD;
667 // Load the value in two parts
669 if (TLI.isLittleEndian()) {
670 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, VT, Chain, Ptr, LD->getSrcValue(),
671 SVOffset, NewLoadedVT, LD->isVolatile(), Alignment);
672 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
673 DAG.getConstant(IncrementSize, TLI.getPointerTy()));
674 Hi = DAG.getExtLoad(HiExtType, VT, Chain, Ptr, LD->getSrcValue(),
675 SVOffset + IncrementSize, NewLoadedVT, LD->isVolatile(),
676 MinAlign(Alignment, IncrementSize));
678 Hi = DAG.getExtLoad(HiExtType, VT, Chain, Ptr, LD->getSrcValue(), SVOffset,
679 NewLoadedVT,LD->isVolatile(), Alignment);
680 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
681 DAG.getConstant(IncrementSize, TLI.getPointerTy()));
682 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, VT, Chain, Ptr, LD->getSrcValue(),
683 SVOffset + IncrementSize, NewLoadedVT, LD->isVolatile(),
684 MinAlign(Alignment, IncrementSize));
687 // aggregate the two parts
688 SDOperand ShiftAmount = DAG.getConstant(NumBits, TLI.getShiftAmountTy());
689 SDOperand Result = DAG.getNode(ISD::SHL, VT, Hi, ShiftAmount);
690 Result = DAG.getNode(ISD::OR, VT, Result, Lo);
692 SDOperand TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
695 SDOperand Ops[] = { Result, TF };
696 return DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(VT, MVT::Other), Ops, 2);
699 /// UnrollVectorOp - We know that the given vector has a legal type, however
700 /// the operation it performs is not legal and is an operation that we have
701 /// no way of lowering. "Unroll" the vector, splitting out the scalars and
702 /// operating on each element individually.
703 SDOperand SelectionDAGLegalize::UnrollVectorOp(SDOperand Op) {
704 MVT::ValueType VT = Op.getValueType();
705 assert(isTypeLegal(VT) &&
706 "Caller should expand or promote operands that are not legal!");
707 assert(Op.Val->getNumValues() == 1 &&
708 "Can't unroll a vector with multiple results!");
709 unsigned NE = MVT::getVectorNumElements(VT);
710 MVT::ValueType EltVT = MVT::getVectorElementType(VT);
712 SmallVector<SDOperand, 8> Scalars;
713 SmallVector<SDOperand, 4> Operands(Op.getNumOperands());
714 for (unsigned i = 0; i != NE; ++i) {
715 for (unsigned j = 0; j != Op.getNumOperands(); ++j) {
716 SDOperand Operand = Op.getOperand(j);
717 MVT::ValueType OperandVT = Operand.getValueType();
718 if (MVT::isVector(OperandVT)) {
719 // A vector operand; extract a single element.
720 MVT::ValueType OperandEltVT = MVT::getVectorElementType(OperandVT);
721 Operands[j] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT,
724 DAG.getConstant(i, MVT::i32));
726 // A scalar operand; just use it as is.
727 Operands[j] = Operand;
730 Scalars.push_back(DAG.getNode(Op.getOpcode(), EltVT,
731 &Operands[0], Operands.size()));
734 return DAG.getNode(ISD::BUILD_VECTOR, VT, &Scalars[0], Scalars.size());
737 /// GetFPLibCall - Return the right libcall for the given floating point type.
738 static RTLIB::Libcall GetFPLibCall(MVT::ValueType VT,
739 RTLIB::Libcall Call_F32,
740 RTLIB::Libcall Call_F64,
741 RTLIB::Libcall Call_F80,
742 RTLIB::Libcall Call_PPCF128) {
744 VT == MVT::f32 ? Call_F32 :
745 VT == MVT::f64 ? Call_F64 :
746 VT == MVT::f80 ? Call_F80 :
747 VT == MVT::ppcf128 ? Call_PPCF128 :
748 RTLIB::UNKNOWN_LIBCALL;
751 /// LegalizeOp - We know that the specified value has a legal type, and
752 /// that its operands are legal. Now ensure that the operation itself
753 /// is legal, recursively ensuring that the operands' operations remain
755 SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
756 if (Op.getOpcode() == ISD::TargetConstant) // Allow illegal target nodes.
759 assert(isTypeLegal(Op.getValueType()) &&
760 "Caller should expand or promote operands that are not legal!");
761 SDNode *Node = Op.Val;
763 // If this operation defines any values that cannot be represented in a
764 // register on this target, make sure to expand or promote them.
765 if (Node->getNumValues() > 1) {
766 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
767 if (getTypeAction(Node->getValueType(i)) != Legal) {
768 HandleOp(Op.getValue(i));
769 assert(LegalizedNodes.count(Op) &&
770 "Handling didn't add legal operands!");
771 return LegalizedNodes[Op];
775 // Note that LegalizeOp may be reentered even from single-use nodes, which
776 // means that we always must cache transformed nodes.
777 DenseMap<SDOperand, SDOperand>::iterator I = LegalizedNodes.find(Op);
778 if (I != LegalizedNodes.end()) return I->second;
780 SDOperand Tmp1, Tmp2, Tmp3, Tmp4;
781 SDOperand Result = Op;
782 bool isCustom = false;
784 switch (Node->getOpcode()) {
785 case ISD::FrameIndex:
786 case ISD::EntryToken:
788 case ISD::BasicBlock:
789 case ISD::TargetFrameIndex:
790 case ISD::TargetJumpTable:
791 case ISD::TargetConstant:
792 case ISD::TargetConstantFP:
793 case ISD::TargetConstantPool:
794 case ISD::TargetGlobalAddress:
795 case ISD::TargetGlobalTLSAddress:
796 case ISD::TargetExternalSymbol:
801 // Primitives must all be legal.
802 assert(TLI.isOperationLegal(Node->getOpcode(), Node->getValueType(0)) &&
803 "This must be legal!");
806 if (Node->getOpcode() >= ISD::BUILTIN_OP_END) {
807 // If this is a target node, legalize it by legalizing the operands then
808 // passing it through.
809 SmallVector<SDOperand, 8> Ops;
810 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
811 Ops.push_back(LegalizeOp(Node->getOperand(i)));
813 Result = DAG.UpdateNodeOperands(Result.getValue(0), &Ops[0], Ops.size());
815 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
816 AddLegalizedOperand(Op.getValue(i), Result.getValue(i));
817 return Result.getValue(Op.ResNo);
819 // Otherwise this is an unhandled builtin node. splat.
821 cerr << "NODE: "; Node->dump(&DAG); cerr << "\n";
823 assert(0 && "Do not know how to legalize this operator!");
825 case ISD::GLOBAL_OFFSET_TABLE:
826 case ISD::GlobalAddress:
827 case ISD::GlobalTLSAddress:
828 case ISD::ExternalSymbol:
829 case ISD::ConstantPool:
830 case ISD::JumpTable: // Nothing to do.
831 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
832 default: assert(0 && "This action is not supported yet!");
833 case TargetLowering::Custom:
834 Tmp1 = TLI.LowerOperation(Op, DAG);
835 if (Tmp1.Val) Result = Tmp1;
836 // FALLTHROUGH if the target doesn't want to lower this op after all.
837 case TargetLowering::Legal:
842 case ISD::RETURNADDR:
843 // The only option for these nodes is to custom lower them. If the target
844 // does not custom lower them, then return zero.
845 Tmp1 = TLI.LowerOperation(Op, DAG);
849 Result = DAG.getConstant(0, TLI.getPointerTy());
851 case ISD::FRAME_TO_ARGS_OFFSET: {
852 MVT::ValueType VT = Node->getValueType(0);
853 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
854 default: assert(0 && "This action is not supported yet!");
855 case TargetLowering::Custom:
856 Result = TLI.LowerOperation(Op, DAG);
857 if (Result.Val) break;
859 case TargetLowering::Legal:
860 Result = DAG.getConstant(0, VT);
865 case ISD::EXCEPTIONADDR: {
866 Tmp1 = LegalizeOp(Node->getOperand(0));
867 MVT::ValueType VT = Node->getValueType(0);
868 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
869 default: assert(0 && "This action is not supported yet!");
870 case TargetLowering::Expand: {
871 unsigned Reg = TLI.getExceptionAddressRegister();
872 Result = DAG.getCopyFromReg(Tmp1, Reg, VT);
875 case TargetLowering::Custom:
876 Result = TLI.LowerOperation(Op, DAG);
877 if (Result.Val) break;
879 case TargetLowering::Legal: {
880 SDOperand Ops[] = { DAG.getConstant(0, VT), Tmp1 };
881 Result = DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(VT, MVT::Other),
887 if (Result.Val->getNumValues() == 1) break;
889 assert(Result.Val->getNumValues() == 2 &&
890 "Cannot return more than two values!");
892 // Since we produced two values, make sure to remember that we
893 // legalized both of them.
894 Tmp1 = LegalizeOp(Result);
895 Tmp2 = LegalizeOp(Result.getValue(1));
896 AddLegalizedOperand(Op.getValue(0), Tmp1);
897 AddLegalizedOperand(Op.getValue(1), Tmp2);
898 return Op.ResNo ? Tmp2 : Tmp1;
899 case ISD::EHSELECTION: {
900 Tmp1 = LegalizeOp(Node->getOperand(0));
901 Tmp2 = LegalizeOp(Node->getOperand(1));
902 MVT::ValueType VT = Node->getValueType(0);
903 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
904 default: assert(0 && "This action is not supported yet!");
905 case TargetLowering::Expand: {
906 unsigned Reg = TLI.getExceptionSelectorRegister();
907 Result = DAG.getCopyFromReg(Tmp2, Reg, VT);
910 case TargetLowering::Custom:
911 Result = TLI.LowerOperation(Op, DAG);
912 if (Result.Val) break;
914 case TargetLowering::Legal: {
915 SDOperand Ops[] = { DAG.getConstant(0, VT), Tmp2 };
916 Result = DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(VT, MVT::Other),
922 if (Result.Val->getNumValues() == 1) break;
924 assert(Result.Val->getNumValues() == 2 &&
925 "Cannot return more than two values!");
927 // Since we produced two values, make sure to remember that we
928 // legalized both of them.
929 Tmp1 = LegalizeOp(Result);
930 Tmp2 = LegalizeOp(Result.getValue(1));
931 AddLegalizedOperand(Op.getValue(0), Tmp1);
932 AddLegalizedOperand(Op.getValue(1), Tmp2);
933 return Op.ResNo ? Tmp2 : Tmp1;
934 case ISD::EH_RETURN: {
935 MVT::ValueType VT = Node->getValueType(0);
936 // The only "good" option for this node is to custom lower it.
937 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
938 default: assert(0 && "This action is not supported at all!");
939 case TargetLowering::Custom:
940 Result = TLI.LowerOperation(Op, DAG);
941 if (Result.Val) break;
943 case TargetLowering::Legal:
944 // Target does not know, how to lower this, lower to noop
945 Result = LegalizeOp(Node->getOperand(0));
950 case ISD::AssertSext:
951 case ISD::AssertZext:
952 Tmp1 = LegalizeOp(Node->getOperand(0));
953 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
955 case ISD::MERGE_VALUES:
956 // Legalize eliminates MERGE_VALUES nodes.
957 Result = Node->getOperand(Op.ResNo);
959 case ISD::CopyFromReg:
960 Tmp1 = LegalizeOp(Node->getOperand(0));
961 Result = Op.getValue(0);
962 if (Node->getNumValues() == 2) {
963 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
965 assert(Node->getNumValues() == 3 && "Invalid copyfromreg!");
966 if (Node->getNumOperands() == 3) {
967 Tmp2 = LegalizeOp(Node->getOperand(2));
968 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1),Tmp2);
970 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
972 AddLegalizedOperand(Op.getValue(2), Result.getValue(2));
974 // Since CopyFromReg produces two values, make sure to remember that we
975 // legalized both of them.
976 AddLegalizedOperand(Op.getValue(0), Result);
977 AddLegalizedOperand(Op.getValue(1), Result.getValue(1));
978 return Result.getValue(Op.ResNo);
980 MVT::ValueType VT = Op.getValueType();
981 switch (TLI.getOperationAction(ISD::UNDEF, VT)) {
982 default: assert(0 && "This action is not supported yet!");
983 case TargetLowering::Expand:
984 if (MVT::isInteger(VT))
985 Result = DAG.getConstant(0, VT);
986 else if (MVT::isFloatingPoint(VT))
987 Result = DAG.getConstantFP(APFloat(APInt(MVT::getSizeInBits(VT), 0)),
990 assert(0 && "Unknown value type!");
992 case TargetLowering::Legal:
998 case ISD::INTRINSIC_W_CHAIN:
999 case ISD::INTRINSIC_WO_CHAIN:
1000 case ISD::INTRINSIC_VOID: {
1001 SmallVector<SDOperand, 8> Ops;
1002 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
1003 Ops.push_back(LegalizeOp(Node->getOperand(i)));
1004 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1006 // Allow the target to custom lower its intrinsics if it wants to.
1007 if (TLI.getOperationAction(Node->getOpcode(), MVT::Other) ==
1008 TargetLowering::Custom) {
1009 Tmp3 = TLI.LowerOperation(Result, DAG);
1010 if (Tmp3.Val) Result = Tmp3;
1013 if (Result.Val->getNumValues() == 1) break;
1015 // Must have return value and chain result.
1016 assert(Result.Val->getNumValues() == 2 &&
1017 "Cannot return more than two values!");
1019 // Since loads produce two values, make sure to remember that we
1020 // legalized both of them.
1021 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
1022 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
1023 return Result.getValue(Op.ResNo);
1027 assert(Node->getNumOperands() == 5 && "Invalid LOCATION node!");
1028 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the input chain.
1030 switch (TLI.getOperationAction(ISD::LOCATION, MVT::Other)) {
1031 case TargetLowering::Promote:
1032 default: assert(0 && "This action is not supported yet!");
1033 case TargetLowering::Expand: {
1034 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
1035 bool useDEBUG_LOC = TLI.isOperationLegal(ISD::DEBUG_LOC, MVT::Other);
1036 bool useLABEL = TLI.isOperationLegal(ISD::LABEL, MVT::Other);
1038 if (MMI && (useDEBUG_LOC || useLABEL)) {
1039 const std::string &FName =
1040 cast<StringSDNode>(Node->getOperand(3))->getValue();
1041 const std::string &DirName =
1042 cast<StringSDNode>(Node->getOperand(4))->getValue();
1043 unsigned SrcFile = MMI->RecordSource(DirName, FName);
1045 SmallVector<SDOperand, 8> Ops;
1046 Ops.push_back(Tmp1); // chain
1047 SDOperand LineOp = Node->getOperand(1);
1048 SDOperand ColOp = Node->getOperand(2);
1051 Ops.push_back(LineOp); // line #
1052 Ops.push_back(ColOp); // col #
1053 Ops.push_back(DAG.getConstant(SrcFile, MVT::i32)); // source file id
1054 Result = DAG.getNode(ISD::DEBUG_LOC, MVT::Other, &Ops[0], Ops.size());
1056 unsigned Line = cast<ConstantSDNode>(LineOp)->getValue();
1057 unsigned Col = cast<ConstantSDNode>(ColOp)->getValue();
1058 unsigned ID = MMI->RecordSourceLine(Line, Col, SrcFile);
1059 Ops.push_back(DAG.getConstant(ID, MVT::i32));
1060 Ops.push_back(DAG.getConstant(0, MVT::i32)); // a debug label
1061 Result = DAG.getNode(ISD::LABEL, MVT::Other, &Ops[0], Ops.size());
1064 Result = Tmp1; // chain
1068 case TargetLowering::Legal:
1069 if (Tmp1 != Node->getOperand(0) ||
1070 getTypeAction(Node->getOperand(1).getValueType()) == Promote) {
1071 SmallVector<SDOperand, 8> Ops;
1072 Ops.push_back(Tmp1);
1073 if (getTypeAction(Node->getOperand(1).getValueType()) == Legal) {
1074 Ops.push_back(Node->getOperand(1)); // line # must be legal.
1075 Ops.push_back(Node->getOperand(2)); // col # must be legal.
1077 // Otherwise promote them.
1078 Ops.push_back(PromoteOp(Node->getOperand(1)));
1079 Ops.push_back(PromoteOp(Node->getOperand(2)));
1081 Ops.push_back(Node->getOperand(3)); // filename must be legal.
1082 Ops.push_back(Node->getOperand(4)); // working dir # must be legal.
1083 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1090 assert(Node->getNumOperands() == 3 && "Invalid DECLARE node!");
1091 switch (TLI.getOperationAction(ISD::DECLARE, MVT::Other)) {
1092 default: assert(0 && "This action is not supported yet!");
1093 case TargetLowering::Legal:
1094 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1095 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the address.
1096 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the variable.
1097 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1102 case ISD::DEBUG_LOC:
1103 assert(Node->getNumOperands() == 4 && "Invalid DEBUG_LOC node!");
1104 switch (TLI.getOperationAction(ISD::DEBUG_LOC, MVT::Other)) {
1105 default: assert(0 && "This action is not supported yet!");
1106 case TargetLowering::Legal:
1107 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1108 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the line #.
1109 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the col #.
1110 Tmp4 = LegalizeOp(Node->getOperand(3)); // Legalize the source file id.
1111 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4);
1117 assert(Node->getNumOperands() == 3 && "Invalid LABEL node!");
1118 switch (TLI.getOperationAction(ISD::LABEL, MVT::Other)) {
1119 default: assert(0 && "This action is not supported yet!");
1120 case TargetLowering::Legal:
1121 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1122 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the label id.
1123 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the "flavor" operand.
1124 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1126 case TargetLowering::Expand:
1127 Result = LegalizeOp(Node->getOperand(0));
1132 case ISD::Constant: {
1133 ConstantSDNode *CN = cast<ConstantSDNode>(Node);
1135 TLI.getOperationAction(ISD::Constant, CN->getValueType(0));
1137 // We know we don't need to expand constants here, constants only have one
1138 // value and we check that it is fine above.
1140 if (opAction == TargetLowering::Custom) {
1141 Tmp1 = TLI.LowerOperation(Result, DAG);
1147 case ISD::ConstantFP: {
1148 // Spill FP immediates to the constant pool if the target cannot directly
1149 // codegen them. Targets often have some immediate values that can be
1150 // efficiently generated into an FP register without a load. We explicitly
1151 // leave these constants as ConstantFP nodes for the target to deal with.
1152 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node);
1154 // Check to see if this FP immediate is already legal.
1155 bool isLegal = false;
1156 for (TargetLowering::legal_fpimm_iterator I = TLI.legal_fpimm_begin(),
1157 E = TLI.legal_fpimm_end(); I != E; ++I)
1158 if (CFP->isExactlyValue(*I)) {
1163 // If this is a legal constant, turn it into a TargetConstantFP node.
1165 Result = DAG.getTargetConstantFP(CFP->getValueAPF(),
1166 CFP->getValueType(0));
1170 switch (TLI.getOperationAction(ISD::ConstantFP, CFP->getValueType(0))) {
1171 default: assert(0 && "This action is not supported yet!");
1172 case TargetLowering::Custom:
1173 Tmp3 = TLI.LowerOperation(Result, DAG);
1179 case TargetLowering::Expand:
1180 Result = ExpandConstantFP(CFP, true, DAG, TLI);
1184 case ISD::TokenFactor:
1185 if (Node->getNumOperands() == 2) {
1186 Tmp1 = LegalizeOp(Node->getOperand(0));
1187 Tmp2 = LegalizeOp(Node->getOperand(1));
1188 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1189 } else if (Node->getNumOperands() == 3) {
1190 Tmp1 = LegalizeOp(Node->getOperand(0));
1191 Tmp2 = LegalizeOp(Node->getOperand(1));
1192 Tmp3 = LegalizeOp(Node->getOperand(2));
1193 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1195 SmallVector<SDOperand, 8> Ops;
1196 // Legalize the operands.
1197 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
1198 Ops.push_back(LegalizeOp(Node->getOperand(i)));
1199 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1203 case ISD::FORMAL_ARGUMENTS:
1205 // The only option for this is to custom lower it.
1206 Tmp3 = TLI.LowerOperation(Result.getValue(0), DAG);
1207 assert(Tmp3.Val && "Target didn't custom lower this node!");
1209 // The number of incoming and outgoing values should match; unless the final
1210 // outgoing value is a flag.
1211 assert((Tmp3.Val->getNumValues() == Result.Val->getNumValues() ||
1212 (Tmp3.Val->getNumValues() == Result.Val->getNumValues() + 1 &&
1213 Tmp3.Val->getValueType(Tmp3.Val->getNumValues() - 1) ==
1215 "Lowering call/formal_arguments produced unexpected # results!");
1217 // Since CALL/FORMAL_ARGUMENTS nodes produce multiple values, make sure to
1218 // remember that we legalized all of them, so it doesn't get relegalized.
1219 for (unsigned i = 0, e = Tmp3.Val->getNumValues(); i != e; ++i) {
1220 if (Tmp3.Val->getValueType(i) == MVT::Flag)
1222 Tmp1 = LegalizeOp(Tmp3.getValue(i));
1225 AddLegalizedOperand(SDOperand(Node, i), Tmp1);
1228 case ISD::EXTRACT_SUBREG: {
1229 Tmp1 = LegalizeOp(Node->getOperand(0));
1230 ConstantSDNode *idx = dyn_cast<ConstantSDNode>(Node->getOperand(1));
1231 assert(idx && "Operand must be a constant");
1232 Tmp2 = DAG.getTargetConstant(idx->getValue(), idx->getValueType(0));
1233 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1236 case ISD::INSERT_SUBREG: {
1237 Tmp1 = LegalizeOp(Node->getOperand(0));
1238 Tmp2 = LegalizeOp(Node->getOperand(1));
1239 ConstantSDNode *idx = dyn_cast<ConstantSDNode>(Node->getOperand(2));
1240 assert(idx && "Operand must be a constant");
1241 Tmp3 = DAG.getTargetConstant(idx->getValue(), idx->getValueType(0));
1242 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1245 case ISD::BUILD_VECTOR:
1246 switch (TLI.getOperationAction(ISD::BUILD_VECTOR, Node->getValueType(0))) {
1247 default: assert(0 && "This action is not supported yet!");
1248 case TargetLowering::Custom:
1249 Tmp3 = TLI.LowerOperation(Result, DAG);
1255 case TargetLowering::Expand:
1256 Result = ExpandBUILD_VECTOR(Result.Val);
1260 case ISD::INSERT_VECTOR_ELT:
1261 Tmp1 = LegalizeOp(Node->getOperand(0)); // InVec
1262 Tmp2 = LegalizeOp(Node->getOperand(1)); // InVal
1263 Tmp3 = LegalizeOp(Node->getOperand(2)); // InEltNo
1264 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1266 switch (TLI.getOperationAction(ISD::INSERT_VECTOR_ELT,
1267 Node->getValueType(0))) {
1268 default: assert(0 && "This action is not supported yet!");
1269 case TargetLowering::Legal:
1271 case TargetLowering::Custom:
1272 Tmp4 = TLI.LowerOperation(Result, DAG);
1278 case TargetLowering::Expand: {
1279 // If the insert index is a constant, codegen this as a scalar_to_vector,
1280 // then a shuffle that inserts it into the right position in the vector.
1281 if (ConstantSDNode *InsertPos = dyn_cast<ConstantSDNode>(Tmp3)) {
1282 SDOperand ScVec = DAG.getNode(ISD::SCALAR_TO_VECTOR,
1283 Tmp1.getValueType(), Tmp2);
1285 unsigned NumElts = MVT::getVectorNumElements(Tmp1.getValueType());
1286 MVT::ValueType ShufMaskVT = MVT::getIntVectorWithNumElements(NumElts);
1287 MVT::ValueType ShufMaskEltVT = MVT::getVectorElementType(ShufMaskVT);
1289 // We generate a shuffle of InVec and ScVec, so the shuffle mask should
1290 // be 0,1,2,3,4,5... with the appropriate element replaced with elt 0 of
1292 SmallVector<SDOperand, 8> ShufOps;
1293 for (unsigned i = 0; i != NumElts; ++i) {
1294 if (i != InsertPos->getValue())
1295 ShufOps.push_back(DAG.getConstant(i, ShufMaskEltVT));
1297 ShufOps.push_back(DAG.getConstant(NumElts, ShufMaskEltVT));
1299 SDOperand ShufMask = DAG.getNode(ISD::BUILD_VECTOR, ShufMaskVT,
1300 &ShufOps[0], ShufOps.size());
1302 Result = DAG.getNode(ISD::VECTOR_SHUFFLE, Tmp1.getValueType(),
1303 Tmp1, ScVec, ShufMask);
1304 Result = LegalizeOp(Result);
1308 // If the target doesn't support this, we have to spill the input vector
1309 // to a temporary stack slot, update the element, then reload it. This is
1310 // badness. We could also load the value into a vector register (either
1311 // with a "move to register" or "extload into register" instruction, then
1312 // permute it into place, if the idx is a constant and if the idx is
1313 // supported by the target.
1314 MVT::ValueType VT = Tmp1.getValueType();
1315 MVT::ValueType EltVT = Tmp2.getValueType();
1316 MVT::ValueType IdxVT = Tmp3.getValueType();
1317 MVT::ValueType PtrVT = TLI.getPointerTy();
1318 SDOperand StackPtr = DAG.CreateStackTemporary(VT);
1319 // Store the vector.
1320 SDOperand Ch = DAG.getStore(DAG.getEntryNode(), Tmp1, StackPtr, NULL, 0);
1322 // Truncate or zero extend offset to target pointer type.
1323 unsigned CastOpc = (IdxVT > PtrVT) ? ISD::TRUNCATE : ISD::ZERO_EXTEND;
1324 Tmp3 = DAG.getNode(CastOpc, PtrVT, Tmp3);
1325 // Add the offset to the index.
1326 unsigned EltSize = MVT::getSizeInBits(EltVT)/8;
1327 Tmp3 = DAG.getNode(ISD::MUL, IdxVT, Tmp3,DAG.getConstant(EltSize, IdxVT));
1328 SDOperand StackPtr2 = DAG.getNode(ISD::ADD, IdxVT, Tmp3, StackPtr);
1329 // Store the scalar value.
1330 Ch = DAG.getStore(Ch, Tmp2, StackPtr2, NULL, 0);
1331 // Load the updated vector.
1332 Result = DAG.getLoad(VT, Ch, StackPtr, NULL, 0);
1337 case ISD::SCALAR_TO_VECTOR:
1338 if (!TLI.isTypeLegal(Node->getOperand(0).getValueType())) {
1339 Result = LegalizeOp(ExpandSCALAR_TO_VECTOR(Node));
1343 Tmp1 = LegalizeOp(Node->getOperand(0)); // InVal
1344 Result = DAG.UpdateNodeOperands(Result, Tmp1);
1345 switch (TLI.getOperationAction(ISD::SCALAR_TO_VECTOR,
1346 Node->getValueType(0))) {
1347 default: assert(0 && "This action is not supported yet!");
1348 case TargetLowering::Legal:
1350 case TargetLowering::Custom:
1351 Tmp3 = TLI.LowerOperation(Result, DAG);
1357 case TargetLowering::Expand:
1358 Result = LegalizeOp(ExpandSCALAR_TO_VECTOR(Node));
1362 case ISD::VECTOR_SHUFFLE:
1363 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the input vectors,
1364 Tmp2 = LegalizeOp(Node->getOperand(1)); // but not the shuffle mask.
1365 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
1367 // Allow targets to custom lower the SHUFFLEs they support.
1368 switch (TLI.getOperationAction(ISD::VECTOR_SHUFFLE,Result.getValueType())) {
1369 default: assert(0 && "Unknown operation action!");
1370 case TargetLowering::Legal:
1371 assert(isShuffleLegal(Result.getValueType(), Node->getOperand(2)) &&
1372 "vector shuffle should not be created if not legal!");
1374 case TargetLowering::Custom:
1375 Tmp3 = TLI.LowerOperation(Result, DAG);
1381 case TargetLowering::Expand: {
1382 MVT::ValueType VT = Node->getValueType(0);
1383 MVT::ValueType EltVT = MVT::getVectorElementType(VT);
1384 MVT::ValueType PtrVT = TLI.getPointerTy();
1385 SDOperand Mask = Node->getOperand(2);
1386 unsigned NumElems = Mask.getNumOperands();
1387 SmallVector<SDOperand,8> Ops;
1388 for (unsigned i = 0; i != NumElems; ++i) {
1389 SDOperand Arg = Mask.getOperand(i);
1390 if (Arg.getOpcode() == ISD::UNDEF) {
1391 Ops.push_back(DAG.getNode(ISD::UNDEF, EltVT));
1393 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
1394 unsigned Idx = cast<ConstantSDNode>(Arg)->getValue();
1396 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, Tmp1,
1397 DAG.getConstant(Idx, PtrVT)));
1399 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, Tmp2,
1400 DAG.getConstant(Idx - NumElems, PtrVT)));
1403 Result = DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size());
1406 case TargetLowering::Promote: {
1407 // Change base type to a different vector type.
1408 MVT::ValueType OVT = Node->getValueType(0);
1409 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
1411 // Cast the two input vectors.
1412 Tmp1 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp1);
1413 Tmp2 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp2);
1415 // Convert the shuffle mask to the right # elements.
1416 Tmp3 = SDOperand(isShuffleLegal(OVT, Node->getOperand(2)), 0);
1417 assert(Tmp3.Val && "Shuffle not legal?");
1418 Result = DAG.getNode(ISD::VECTOR_SHUFFLE, NVT, Tmp1, Tmp2, Tmp3);
1419 Result = DAG.getNode(ISD::BIT_CONVERT, OVT, Result);
1425 case ISD::EXTRACT_VECTOR_ELT:
1426 Tmp1 = Node->getOperand(0);
1427 Tmp2 = LegalizeOp(Node->getOperand(1));
1428 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1429 Result = ExpandEXTRACT_VECTOR_ELT(Result);
1432 case ISD::EXTRACT_SUBVECTOR:
1433 Tmp1 = Node->getOperand(0);
1434 Tmp2 = LegalizeOp(Node->getOperand(1));
1435 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1436 Result = ExpandEXTRACT_SUBVECTOR(Result);
1439 case ISD::CALLSEQ_START: {
1440 SDNode *CallEnd = FindCallEndFromCallStart(Node);
1442 // Recursively Legalize all of the inputs of the call end that do not lead
1443 // to this call start. This ensures that any libcalls that need be inserted
1444 // are inserted *before* the CALLSEQ_START.
1445 {SmallPtrSet<SDNode*, 32> NodesLeadingTo;
1446 for (unsigned i = 0, e = CallEnd->getNumOperands(); i != e; ++i)
1447 LegalizeAllNodesNotLeadingTo(CallEnd->getOperand(i).Val, Node,
1451 // Now that we legalized all of the inputs (which may have inserted
1452 // libcalls) create the new CALLSEQ_START node.
1453 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1455 // Merge in the last call, to ensure that this call start after the last
1457 if (LastCALLSEQ_END.getOpcode() != ISD::EntryToken) {
1458 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1459 Tmp1 = LegalizeOp(Tmp1);
1462 // Do not try to legalize the target-specific arguments (#1+).
1463 if (Tmp1 != Node->getOperand(0)) {
1464 SmallVector<SDOperand, 8> Ops(Node->op_begin(), Node->op_end());
1466 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1469 // Remember that the CALLSEQ_START is legalized.
1470 AddLegalizedOperand(Op.getValue(0), Result);
1471 if (Node->getNumValues() == 2) // If this has a flag result, remember it.
1472 AddLegalizedOperand(Op.getValue(1), Result.getValue(1));
1474 // Now that the callseq_start and all of the non-call nodes above this call
1475 // sequence have been legalized, legalize the call itself. During this
1476 // process, no libcalls can/will be inserted, guaranteeing that no calls
1478 assert(!IsLegalizingCall && "Inconsistent sequentialization of calls!");
1479 SDOperand InCallSEQ = LastCALLSEQ_END;
1480 // Note that we are selecting this call!
1481 LastCALLSEQ_END = SDOperand(CallEnd, 0);
1482 IsLegalizingCall = true;
1484 // Legalize the call, starting from the CALLSEQ_END.
1485 LegalizeOp(LastCALLSEQ_END);
1486 assert(!IsLegalizingCall && "CALLSEQ_END should have cleared this!");
1489 case ISD::CALLSEQ_END:
1490 // If the CALLSEQ_START node hasn't been legalized first, legalize it. This
1491 // will cause this node to be legalized as well as handling libcalls right.
1492 if (LastCALLSEQ_END.Val != Node) {
1493 LegalizeOp(SDOperand(FindCallStartFromCallEnd(Node), 0));
1494 DenseMap<SDOperand, SDOperand>::iterator I = LegalizedNodes.find(Op);
1495 assert(I != LegalizedNodes.end() &&
1496 "Legalizing the call start should have legalized this node!");
1500 // Otherwise, the call start has been legalized and everything is going
1501 // according to plan. Just legalize ourselves normally here.
1502 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1503 // Do not try to legalize the target-specific arguments (#1+), except for
1504 // an optional flag input.
1505 if (Node->getOperand(Node->getNumOperands()-1).getValueType() != MVT::Flag){
1506 if (Tmp1 != Node->getOperand(0)) {
1507 SmallVector<SDOperand, 8> Ops(Node->op_begin(), Node->op_end());
1509 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1512 Tmp2 = LegalizeOp(Node->getOperand(Node->getNumOperands()-1));
1513 if (Tmp1 != Node->getOperand(0) ||
1514 Tmp2 != Node->getOperand(Node->getNumOperands()-1)) {
1515 SmallVector<SDOperand, 8> Ops(Node->op_begin(), Node->op_end());
1518 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1521 assert(IsLegalizingCall && "Call sequence imbalance between start/end?");
1522 // This finishes up call legalization.
1523 IsLegalizingCall = false;
1525 // If the CALLSEQ_END node has a flag, remember that we legalized it.
1526 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
1527 if (Node->getNumValues() == 2)
1528 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
1529 return Result.getValue(Op.ResNo);
1530 case ISD::DYNAMIC_STACKALLOC: {
1531 MVT::ValueType VT = Node->getValueType(0);
1532 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1533 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the size.
1534 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the alignment.
1535 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1537 Tmp1 = Result.getValue(0);
1538 Tmp2 = Result.getValue(1);
1539 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
1540 default: assert(0 && "This action is not supported yet!");
1541 case TargetLowering::Expand: {
1542 unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore();
1543 assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and"
1544 " not tell us which reg is the stack pointer!");
1545 SDOperand Chain = Tmp1.getOperand(0);
1547 // Chain the dynamic stack allocation so that it doesn't modify the stack
1548 // pointer when other instructions are using the stack.
1549 Chain = DAG.getCALLSEQ_START(Chain,
1550 DAG.getConstant(0, TLI.getPointerTy()));
1552 SDOperand Size = Tmp2.getOperand(1);
1553 SDOperand SP = DAG.getCopyFromReg(Chain, SPReg, VT);
1554 Chain = SP.getValue(1);
1555 unsigned Align = cast<ConstantSDNode>(Tmp3)->getValue();
1556 unsigned StackAlign =
1557 TLI.getTargetMachine().getFrameInfo()->getStackAlignment();
1558 if (Align > StackAlign)
1559 SP = DAG.getNode(ISD::AND, VT, SP,
1560 DAG.getConstant(-(uint64_t)Align, VT));
1561 Tmp1 = DAG.getNode(ISD::SUB, VT, SP, Size); // Value
1562 Chain = DAG.getCopyToReg(Chain, SPReg, Tmp1); // Output chain
1565 DAG.getCALLSEQ_END(Chain,
1566 DAG.getConstant(0, TLI.getPointerTy()),
1567 DAG.getConstant(0, TLI.getPointerTy()),
1570 Tmp1 = LegalizeOp(Tmp1);
1571 Tmp2 = LegalizeOp(Tmp2);
1574 case TargetLowering::Custom:
1575 Tmp3 = TLI.LowerOperation(Tmp1, DAG);
1577 Tmp1 = LegalizeOp(Tmp3);
1578 Tmp2 = LegalizeOp(Tmp3.getValue(1));
1581 case TargetLowering::Legal:
1584 // Since this op produce two values, make sure to remember that we
1585 // legalized both of them.
1586 AddLegalizedOperand(SDOperand(Node, 0), Tmp1);
1587 AddLegalizedOperand(SDOperand(Node, 1), Tmp2);
1588 return Op.ResNo ? Tmp2 : Tmp1;
1590 case ISD::INLINEASM: {
1591 SmallVector<SDOperand, 8> Ops(Node->op_begin(), Node->op_end());
1592 bool Changed = false;
1593 // Legalize all of the operands of the inline asm, in case they are nodes
1594 // that need to be expanded or something. Note we skip the asm string and
1595 // all of the TargetConstant flags.
1596 SDOperand Op = LegalizeOp(Ops[0]);
1597 Changed = Op != Ops[0];
1600 bool HasInFlag = Ops.back().getValueType() == MVT::Flag;
1601 for (unsigned i = 2, e = Ops.size()-HasInFlag; i < e; ) {
1602 unsigned NumVals = cast<ConstantSDNode>(Ops[i])->getValue() >> 3;
1603 for (++i; NumVals; ++i, --NumVals) {
1604 SDOperand Op = LegalizeOp(Ops[i]);
1613 Op = LegalizeOp(Ops.back());
1614 Changed |= Op != Ops.back();
1619 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1621 // INLINE asm returns a chain and flag, make sure to add both to the map.
1622 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
1623 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
1624 return Result.getValue(Op.ResNo);
1627 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1628 // Ensure that libcalls are emitted before a branch.
1629 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1630 Tmp1 = LegalizeOp(Tmp1);
1631 LastCALLSEQ_END = DAG.getEntryNode();
1633 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
1636 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1637 // Ensure that libcalls are emitted before a branch.
1638 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1639 Tmp1 = LegalizeOp(Tmp1);
1640 LastCALLSEQ_END = DAG.getEntryNode();
1642 switch (getTypeAction(Node->getOperand(1).getValueType())) {
1643 default: assert(0 && "Indirect target must be legal type (pointer)!");
1645 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the condition.
1648 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1651 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1652 // Ensure that libcalls are emitted before a branch.
1653 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1654 Tmp1 = LegalizeOp(Tmp1);
1655 LastCALLSEQ_END = DAG.getEntryNode();
1657 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the jumptable node.
1658 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
1660 switch (TLI.getOperationAction(ISD::BR_JT, MVT::Other)) {
1661 default: assert(0 && "This action is not supported yet!");
1662 case TargetLowering::Legal: break;
1663 case TargetLowering::Custom:
1664 Tmp1 = TLI.LowerOperation(Result, DAG);
1665 if (Tmp1.Val) Result = Tmp1;
1667 case TargetLowering::Expand: {
1668 SDOperand Chain = Result.getOperand(0);
1669 SDOperand Table = Result.getOperand(1);
1670 SDOperand Index = Result.getOperand(2);
1672 MVT::ValueType PTy = TLI.getPointerTy();
1673 MachineFunction &MF = DAG.getMachineFunction();
1674 unsigned EntrySize = MF.getJumpTableInfo()->getEntrySize();
1675 Index= DAG.getNode(ISD::MUL, PTy, Index, DAG.getConstant(EntrySize, PTy));
1676 SDOperand Addr = DAG.getNode(ISD::ADD, PTy, Index, Table);
1679 switch (EntrySize) {
1680 default: assert(0 && "Size of jump table not supported yet."); break;
1681 case 4: LD = DAG.getLoad(MVT::i32, Chain, Addr, NULL, 0); break;
1682 case 8: LD = DAG.getLoad(MVT::i64, Chain, Addr, NULL, 0); break;
1686 if (TLI.getTargetMachine().getRelocationModel() == Reloc::PIC_) {
1687 // For PIC, the sequence is:
1688 // BRIND(load(Jumptable + index) + RelocBase)
1689 // RelocBase can be JumpTable, GOT or some sort of global base.
1690 if (PTy != MVT::i32)
1691 Addr = DAG.getNode(ISD::SIGN_EXTEND, PTy, Addr);
1692 Addr = DAG.getNode(ISD::ADD, PTy, Addr,
1693 TLI.getPICJumpTableRelocBase(Table, DAG));
1695 Result = DAG.getNode(ISD::BRIND, MVT::Other, LD.getValue(1), Addr);
1700 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1701 // Ensure that libcalls are emitted before a return.
1702 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1703 Tmp1 = LegalizeOp(Tmp1);
1704 LastCALLSEQ_END = DAG.getEntryNode();
1706 switch (getTypeAction(Node->getOperand(1).getValueType())) {
1707 case Expand: assert(0 && "It's impossible to expand bools");
1709 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the condition.
1712 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the condition.
1714 // The top bits of the promoted condition are not necessarily zero, ensure
1715 // that the value is properly zero extended.
1716 if (!DAG.MaskedValueIsZero(Tmp2,
1717 MVT::getIntVTBitMask(Tmp2.getValueType())^1))
1718 Tmp2 = DAG.getZeroExtendInReg(Tmp2, MVT::i1);
1722 // Basic block destination (Op#2) is always legal.
1723 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
1725 switch (TLI.getOperationAction(ISD::BRCOND, MVT::Other)) {
1726 default: assert(0 && "This action is not supported yet!");
1727 case TargetLowering::Legal: break;
1728 case TargetLowering::Custom:
1729 Tmp1 = TLI.LowerOperation(Result, DAG);
1730 if (Tmp1.Val) Result = Tmp1;
1732 case TargetLowering::Expand:
1733 // Expand brcond's setcc into its constituent parts and create a BR_CC
1735 if (Tmp2.getOpcode() == ISD::SETCC) {
1736 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1, Tmp2.getOperand(2),
1737 Tmp2.getOperand(0), Tmp2.getOperand(1),
1738 Node->getOperand(2));
1740 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1,
1741 DAG.getCondCode(ISD::SETNE), Tmp2,
1742 DAG.getConstant(0, Tmp2.getValueType()),
1743 Node->getOperand(2));
1749 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1750 // Ensure that libcalls are emitted before a branch.
1751 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1752 Tmp1 = LegalizeOp(Tmp1);
1753 Tmp2 = Node->getOperand(2); // LHS
1754 Tmp3 = Node->getOperand(3); // RHS
1755 Tmp4 = Node->getOperand(1); // CC
1757 LegalizeSetCCOperands(Tmp2, Tmp3, Tmp4);
1758 LastCALLSEQ_END = DAG.getEntryNode();
1760 // If we didn't get both a LHS and RHS back from LegalizeSetCCOperands,
1761 // the LHS is a legal SETCC itself. In this case, we need to compare
1762 // the result against zero to select between true and false values.
1763 if (Tmp3.Val == 0) {
1764 Tmp3 = DAG.getConstant(0, Tmp2.getValueType());
1765 Tmp4 = DAG.getCondCode(ISD::SETNE);
1768 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp4, Tmp2, Tmp3,
1769 Node->getOperand(4));
1771 switch (TLI.getOperationAction(ISD::BR_CC, Tmp3.getValueType())) {
1772 default: assert(0 && "Unexpected action for BR_CC!");
1773 case TargetLowering::Legal: break;
1774 case TargetLowering::Custom:
1775 Tmp4 = TLI.LowerOperation(Result, DAG);
1776 if (Tmp4.Val) Result = Tmp4;
1781 LoadSDNode *LD = cast<LoadSDNode>(Node);
1782 Tmp1 = LegalizeOp(LD->getChain()); // Legalize the chain.
1783 Tmp2 = LegalizeOp(LD->getBasePtr()); // Legalize the base pointer.
1785 ISD::LoadExtType ExtType = LD->getExtensionType();
1786 if (ExtType == ISD::NON_EXTLOAD) {
1787 MVT::ValueType VT = Node->getValueType(0);
1788 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, LD->getOffset());
1789 Tmp3 = Result.getValue(0);
1790 Tmp4 = Result.getValue(1);
1792 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
1793 default: assert(0 && "This action is not supported yet!");
1794 case TargetLowering::Legal:
1795 // If this is an unaligned load and the target doesn't support it,
1797 if (!TLI.allowsUnalignedMemoryAccesses()) {
1798 unsigned ABIAlignment = TLI.getTargetData()->
1799 getABITypeAlignment(MVT::getTypeForValueType(LD->getMemoryVT()));
1800 if (LD->getAlignment() < ABIAlignment){
1801 Result = ExpandUnalignedLoad(cast<LoadSDNode>(Result.Val), DAG,
1803 Tmp3 = Result.getOperand(0);
1804 Tmp4 = Result.getOperand(1);
1805 Tmp3 = LegalizeOp(Tmp3);
1806 Tmp4 = LegalizeOp(Tmp4);
1810 case TargetLowering::Custom:
1811 Tmp1 = TLI.LowerOperation(Tmp3, DAG);
1813 Tmp3 = LegalizeOp(Tmp1);
1814 Tmp4 = LegalizeOp(Tmp1.getValue(1));
1817 case TargetLowering::Promote: {
1818 // Only promote a load of vector type to another.
1819 assert(MVT::isVector(VT) && "Cannot promote this load!");
1820 // Change base type to a different vector type.
1821 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), VT);
1823 Tmp1 = DAG.getLoad(NVT, Tmp1, Tmp2, LD->getSrcValue(),
1824 LD->getSrcValueOffset(),
1825 LD->isVolatile(), LD->getAlignment());
1826 Tmp3 = LegalizeOp(DAG.getNode(ISD::BIT_CONVERT, VT, Tmp1));
1827 Tmp4 = LegalizeOp(Tmp1.getValue(1));
1831 // Since loads produce two values, make sure to remember that we
1832 // legalized both of them.
1833 AddLegalizedOperand(SDOperand(Node, 0), Tmp3);
1834 AddLegalizedOperand(SDOperand(Node, 1), Tmp4);
1835 return Op.ResNo ? Tmp4 : Tmp3;
1837 MVT::ValueType SrcVT = LD->getMemoryVT();
1838 unsigned SrcWidth = MVT::getSizeInBits(SrcVT);
1839 int SVOffset = LD->getSrcValueOffset();
1840 unsigned Alignment = LD->getAlignment();
1841 bool isVolatile = LD->isVolatile();
1843 if (SrcWidth != MVT::getStoreSizeInBits(SrcVT) &&
1844 // Some targets pretend to have an i1 loading operation, and actually
1845 // load an i8. This trick is correct for ZEXTLOAD because the top 7
1846 // bits are guaranteed to be zero; it helps the optimizers understand
1847 // that these bits are zero. It is also useful for EXTLOAD, since it
1848 // tells the optimizers that those bits are undefined. It would be
1849 // nice to have an effective generic way of getting these benefits...
1850 // Until such a way is found, don't insist on promoting i1 here.
1851 (SrcVT != MVT::i1 ||
1852 TLI.getLoadXAction(ExtType, MVT::i1) == TargetLowering::Promote)) {
1853 // Promote to a byte-sized load if not loading an integral number of
1854 // bytes. For example, promote EXTLOAD:i20 -> EXTLOAD:i24.
1855 unsigned NewWidth = MVT::getStoreSizeInBits(SrcVT);
1856 MVT::ValueType NVT = MVT::getIntegerType(NewWidth);
1859 // The extra bits are guaranteed to be zero, since we stored them that
1860 // way. A zext load from NVT thus automatically gives zext from SrcVT.
1862 ISD::LoadExtType NewExtType =
1863 ExtType == ISD::ZEXTLOAD ? ISD::ZEXTLOAD : ISD::EXTLOAD;
1865 Result = DAG.getExtLoad(NewExtType, Node->getValueType(0),
1866 Tmp1, Tmp2, LD->getSrcValue(), SVOffset,
1867 NVT, isVolatile, Alignment);
1869 Ch = Result.getValue(1); // The chain.
1871 if (ExtType == ISD::SEXTLOAD)
1872 // Having the top bits zero doesn't help when sign extending.
1873 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(),
1874 Result, DAG.getValueType(SrcVT));
1875 else if (ExtType == ISD::ZEXTLOAD || NVT == Result.getValueType())
1876 // All the top bits are guaranteed to be zero - inform the optimizers.
1877 Result = DAG.getNode(ISD::AssertZext, Result.getValueType(), Result,
1878 DAG.getValueType(SrcVT));
1880 Tmp1 = LegalizeOp(Result);
1881 Tmp2 = LegalizeOp(Ch);
1882 } else if (SrcWidth & (SrcWidth - 1)) {
1883 // If not loading a power-of-2 number of bits, expand as two loads.
1884 assert(MVT::isExtendedVT(SrcVT) && !MVT::isVector(SrcVT) &&
1885 "Unsupported extload!");
1886 unsigned RoundWidth = 1 << Log2_32(SrcWidth);
1887 assert(RoundWidth < SrcWidth);
1888 unsigned ExtraWidth = SrcWidth - RoundWidth;
1889 assert(ExtraWidth < RoundWidth);
1890 assert(!(RoundWidth % 8) && !(ExtraWidth % 8) &&
1891 "Load size not an integral number of bytes!");
1892 MVT::ValueType RoundVT = MVT::getIntegerType(RoundWidth);
1893 MVT::ValueType ExtraVT = MVT::getIntegerType(ExtraWidth);
1894 SDOperand Lo, Hi, Ch;
1895 unsigned IncrementSize;
1897 if (TLI.isLittleEndian()) {
1898 // EXTLOAD:i24 -> ZEXTLOAD:i16 | (shl EXTLOAD@+2:i8, 16)
1899 // Load the bottom RoundWidth bits.
1900 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, Node->getValueType(0), Tmp1, Tmp2,
1901 LD->getSrcValue(), SVOffset, RoundVT, isVolatile,
1904 // Load the remaining ExtraWidth bits.
1905 IncrementSize = RoundWidth / 8;
1906 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2,
1907 DAG.getIntPtrConstant(IncrementSize));
1908 Hi = DAG.getExtLoad(ExtType, Node->getValueType(0), Tmp1, Tmp2,
1909 LD->getSrcValue(), SVOffset + IncrementSize,
1910 ExtraVT, isVolatile,
1911 MinAlign(Alignment, IncrementSize));
1913 // Build a factor node to remember that this load is independent of the
1915 Ch = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
1918 // Move the top bits to the right place.
1919 Hi = DAG.getNode(ISD::SHL, Hi.getValueType(), Hi,
1920 DAG.getConstant(RoundWidth, TLI.getShiftAmountTy()));
1922 // Join the hi and lo parts.
1923 Result = DAG.getNode(ISD::OR, Node->getValueType(0), Lo, Hi);
1925 // Big endian - avoid unaligned loads.
1926 // EXTLOAD:i24 -> (shl EXTLOAD:i16, 8) | ZEXTLOAD@+2:i8
1927 // Load the top RoundWidth bits.
1928 Hi = DAG.getExtLoad(ExtType, Node->getValueType(0), Tmp1, Tmp2,
1929 LD->getSrcValue(), SVOffset, RoundVT, isVolatile,
1932 // Load the remaining ExtraWidth bits.
1933 IncrementSize = RoundWidth / 8;
1934 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2,
1935 DAG.getIntPtrConstant(IncrementSize));
1936 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, Node->getValueType(0), Tmp1, Tmp2,
1937 LD->getSrcValue(), SVOffset + IncrementSize,
1938 ExtraVT, isVolatile,
1939 MinAlign(Alignment, IncrementSize));
1941 // Build a factor node to remember that this load is independent of the
1943 Ch = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
1946 // Move the top bits to the right place.
1947 Hi = DAG.getNode(ISD::SHL, Hi.getValueType(), Hi,
1948 DAG.getConstant(ExtraWidth, TLI.getShiftAmountTy()));
1950 // Join the hi and lo parts.
1951 Result = DAG.getNode(ISD::OR, Node->getValueType(0), Lo, Hi);
1954 Tmp1 = LegalizeOp(Result);
1955 Tmp2 = LegalizeOp(Ch);
1957 switch (TLI.getLoadXAction(ExtType, SrcVT)) {
1958 default: assert(0 && "This action is not supported yet!");
1959 case TargetLowering::Custom:
1962 case TargetLowering::Legal:
1963 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, LD->getOffset());
1964 Tmp1 = Result.getValue(0);
1965 Tmp2 = Result.getValue(1);
1968 Tmp3 = TLI.LowerOperation(Result, DAG);
1970 Tmp1 = LegalizeOp(Tmp3);
1971 Tmp2 = LegalizeOp(Tmp3.getValue(1));
1974 // If this is an unaligned load and the target doesn't support it,
1976 if (!TLI.allowsUnalignedMemoryAccesses()) {
1977 unsigned ABIAlignment = TLI.getTargetData()->
1978 getABITypeAlignment(MVT::getTypeForValueType(LD->getMemoryVT()));
1979 if (LD->getAlignment() < ABIAlignment){
1980 Result = ExpandUnalignedLoad(cast<LoadSDNode>(Result.Val), DAG,
1982 Tmp1 = Result.getOperand(0);
1983 Tmp2 = Result.getOperand(1);
1984 Tmp1 = LegalizeOp(Tmp1);
1985 Tmp2 = LegalizeOp(Tmp2);
1990 case TargetLowering::Expand:
1991 // f64 = EXTLOAD f32 should expand to LOAD, FP_EXTEND
1992 if (SrcVT == MVT::f32 && Node->getValueType(0) == MVT::f64) {
1993 SDOperand Load = DAG.getLoad(SrcVT, Tmp1, Tmp2, LD->getSrcValue(),
1994 LD->getSrcValueOffset(),
1995 LD->isVolatile(), LD->getAlignment());
1996 Result = DAG.getNode(ISD::FP_EXTEND, Node->getValueType(0), Load);
1997 Tmp1 = LegalizeOp(Result); // Relegalize new nodes.
1998 Tmp2 = LegalizeOp(Load.getValue(1));
2001 assert(ExtType != ISD::EXTLOAD &&"EXTLOAD should always be supported!");
2002 // Turn the unsupported load into an EXTLOAD followed by an explicit
2003 // zero/sign extend inreg.
2004 Result = DAG.getExtLoad(ISD::EXTLOAD, Node->getValueType(0),
2005 Tmp1, Tmp2, LD->getSrcValue(),
2006 LD->getSrcValueOffset(), SrcVT,
2007 LD->isVolatile(), LD->getAlignment());
2009 if (ExtType == ISD::SEXTLOAD)
2010 ValRes = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(),
2011 Result, DAG.getValueType(SrcVT));
2013 ValRes = DAG.getZeroExtendInReg(Result, SrcVT);
2014 Tmp1 = LegalizeOp(ValRes); // Relegalize new nodes.
2015 Tmp2 = LegalizeOp(Result.getValue(1)); // Relegalize new nodes.
2020 // Since loads produce two values, make sure to remember that we legalized
2022 AddLegalizedOperand(SDOperand(Node, 0), Tmp1);
2023 AddLegalizedOperand(SDOperand(Node, 1), Tmp2);
2024 return Op.ResNo ? Tmp2 : Tmp1;
2027 case ISD::EXTRACT_ELEMENT: {
2028 MVT::ValueType OpTy = Node->getOperand(0).getValueType();
2029 switch (getTypeAction(OpTy)) {
2030 default: assert(0 && "EXTRACT_ELEMENT action for type unimplemented!");
2032 if (cast<ConstantSDNode>(Node->getOperand(1))->getValue()) {
2034 Result = DAG.getNode(ISD::SRL, OpTy, Node->getOperand(0),
2035 DAG.getConstant(MVT::getSizeInBits(OpTy)/2,
2036 TLI.getShiftAmountTy()));
2037 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), Result);
2040 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0),
2041 Node->getOperand(0));
2045 // Get both the low and high parts.
2046 ExpandOp(Node->getOperand(0), Tmp1, Tmp2);
2047 if (cast<ConstantSDNode>(Node->getOperand(1))->getValue())
2048 Result = Tmp2; // 1 -> Hi
2050 Result = Tmp1; // 0 -> Lo
2056 case ISD::CopyToReg:
2057 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2059 assert(isTypeLegal(Node->getOperand(2).getValueType()) &&
2060 "Register type must be legal!");
2061 // Legalize the incoming value (must be a legal type).
2062 Tmp2 = LegalizeOp(Node->getOperand(2));
2063 if (Node->getNumValues() == 1) {
2064 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1), Tmp2);
2066 assert(Node->getNumValues() == 2 && "Unknown CopyToReg");
2067 if (Node->getNumOperands() == 4) {
2068 Tmp3 = LegalizeOp(Node->getOperand(3));
2069 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1), Tmp2,
2072 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1),Tmp2);
2075 // Since this produces two values, make sure to remember that we legalized
2077 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
2078 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
2084 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2086 // Ensure that libcalls are emitted before a return.
2087 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
2088 Tmp1 = LegalizeOp(Tmp1);
2089 LastCALLSEQ_END = DAG.getEntryNode();
2091 switch (Node->getNumOperands()) {
2093 Tmp2 = Node->getOperand(1);
2094 Tmp3 = Node->getOperand(2); // Signness
2095 switch (getTypeAction(Tmp2.getValueType())) {
2097 Result = DAG.UpdateNodeOperands(Result, Tmp1, LegalizeOp(Tmp2), Tmp3);
2100 if (!MVT::isVector(Tmp2.getValueType())) {
2102 ExpandOp(Tmp2, Lo, Hi);
2104 // Big endian systems want the hi reg first.
2105 if (!TLI.isLittleEndian())
2109 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Tmp3, Hi,Tmp3);
2111 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Tmp3);
2112 Result = LegalizeOp(Result);
2114 SDNode *InVal = Tmp2.Val;
2115 int InIx = Tmp2.ResNo;
2116 unsigned NumElems = MVT::getVectorNumElements(InVal->getValueType(InIx));
2117 MVT::ValueType EVT = MVT::getVectorElementType(InVal->getValueType(InIx));
2119 // Figure out if there is a simple type corresponding to this Vector
2120 // type. If so, convert to the vector type.
2121 MVT::ValueType TVT = MVT::getVectorType(EVT, NumElems);
2122 if (TLI.isTypeLegal(TVT)) {
2123 // Turn this into a return of the vector type.
2124 Tmp2 = LegalizeOp(Tmp2);
2125 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2126 } else if (NumElems == 1) {
2127 // Turn this into a return of the scalar type.
2128 Tmp2 = ScalarizeVectorOp(Tmp2);
2129 Tmp2 = LegalizeOp(Tmp2);
2130 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2132 // FIXME: Returns of gcc generic vectors smaller than a legal type
2133 // should be returned in integer registers!
2135 // The scalarized value type may not be legal, e.g. it might require
2136 // promotion or expansion. Relegalize the return.
2137 Result = LegalizeOp(Result);
2139 // FIXME: Returns of gcc generic vectors larger than a legal vector
2140 // type should be returned by reference!
2142 SplitVectorOp(Tmp2, Lo, Hi);
2143 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Tmp3, Hi,Tmp3);
2144 Result = LegalizeOp(Result);
2149 Tmp2 = PromoteOp(Node->getOperand(1));
2150 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2151 Result = LegalizeOp(Result);
2156 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2158 default: { // ret <values>
2159 SmallVector<SDOperand, 8> NewValues;
2160 NewValues.push_back(Tmp1);
2161 for (unsigned i = 1, e = Node->getNumOperands(); i < e; i += 2)
2162 switch (getTypeAction(Node->getOperand(i).getValueType())) {
2164 NewValues.push_back(LegalizeOp(Node->getOperand(i)));
2165 NewValues.push_back(Node->getOperand(i+1));
2169 assert(!MVT::isExtendedVT(Node->getOperand(i).getValueType()) &&
2170 "FIXME: TODO: implement returning non-legal vector types!");
2171 ExpandOp(Node->getOperand(i), Lo, Hi);
2172 NewValues.push_back(Lo);
2173 NewValues.push_back(Node->getOperand(i+1));
2175 NewValues.push_back(Hi);
2176 NewValues.push_back(Node->getOperand(i+1));
2181 assert(0 && "Can't promote multiple return value yet!");
2184 if (NewValues.size() == Node->getNumOperands())
2185 Result = DAG.UpdateNodeOperands(Result, &NewValues[0],NewValues.size());
2187 Result = DAG.getNode(ISD::RET, MVT::Other,
2188 &NewValues[0], NewValues.size());
2193 if (Result.getOpcode() == ISD::RET) {
2194 switch (TLI.getOperationAction(Result.getOpcode(), MVT::Other)) {
2195 default: assert(0 && "This action is not supported yet!");
2196 case TargetLowering::Legal: break;
2197 case TargetLowering::Custom:
2198 Tmp1 = TLI.LowerOperation(Result, DAG);
2199 if (Tmp1.Val) Result = Tmp1;
2205 StoreSDNode *ST = cast<StoreSDNode>(Node);
2206 Tmp1 = LegalizeOp(ST->getChain()); // Legalize the chain.
2207 Tmp2 = LegalizeOp(ST->getBasePtr()); // Legalize the pointer.
2208 int SVOffset = ST->getSrcValueOffset();
2209 unsigned Alignment = ST->getAlignment();
2210 bool isVolatile = ST->isVolatile();
2212 if (!ST->isTruncatingStore()) {
2213 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr'
2214 // FIXME: We shouldn't do this for TargetConstantFP's.
2215 // FIXME: move this to the DAG Combiner! Note that we can't regress due
2216 // to phase ordering between legalized code and the dag combiner. This
2217 // probably means that we need to integrate dag combiner and legalizer
2219 // We generally can't do this one for long doubles.
2220 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(ST->getValue())) {
2221 if (CFP->getValueType(0) == MVT::f32 &&
2222 getTypeAction(MVT::i32) == Legal) {
2223 Tmp3 = DAG.getConstant((uint32_t)CFP->getValueAPF().
2224 convertToAPInt().getZExtValue(),
2226 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2227 SVOffset, isVolatile, Alignment);
2229 } else if (CFP->getValueType(0) == MVT::f64) {
2230 // If this target supports 64-bit registers, do a single 64-bit store.
2231 if (getTypeAction(MVT::i64) == Legal) {
2232 Tmp3 = DAG.getConstant(CFP->getValueAPF().convertToAPInt().
2233 getZExtValue(), MVT::i64);
2234 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2235 SVOffset, isVolatile, Alignment);
2237 } else if (getTypeAction(MVT::i32) == Legal) {
2238 // Otherwise, if the target supports 32-bit registers, use 2 32-bit
2239 // stores. If the target supports neither 32- nor 64-bits, this
2240 // xform is certainly not worth it.
2241 uint64_t IntVal =CFP->getValueAPF().convertToAPInt().getZExtValue();
2242 SDOperand Lo = DAG.getConstant(uint32_t(IntVal), MVT::i32);
2243 SDOperand Hi = DAG.getConstant(uint32_t(IntVal >>32), MVT::i32);
2244 if (!TLI.isLittleEndian()) std::swap(Lo, Hi);
2246 Lo = DAG.getStore(Tmp1, Lo, Tmp2, ST->getSrcValue(),
2247 SVOffset, isVolatile, Alignment);
2248 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2,
2249 DAG.getIntPtrConstant(4));
2250 Hi = DAG.getStore(Tmp1, Hi, Tmp2, ST->getSrcValue(), SVOffset+4,
2251 isVolatile, MinAlign(Alignment, 4U));
2253 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi);
2259 switch (getTypeAction(ST->getMemoryVT())) {
2261 Tmp3 = LegalizeOp(ST->getValue());
2262 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2,
2265 MVT::ValueType VT = Tmp3.getValueType();
2266 switch (TLI.getOperationAction(ISD::STORE, VT)) {
2267 default: assert(0 && "This action is not supported yet!");
2268 case TargetLowering::Legal:
2269 // If this is an unaligned store and the target doesn't support it,
2271 if (!TLI.allowsUnalignedMemoryAccesses()) {
2272 unsigned ABIAlignment = TLI.getTargetData()->
2273 getABITypeAlignment(MVT::getTypeForValueType(ST->getMemoryVT()));
2274 if (ST->getAlignment() < ABIAlignment)
2275 Result = ExpandUnalignedStore(cast<StoreSDNode>(Result.Val), DAG,
2279 case TargetLowering::Custom:
2280 Tmp1 = TLI.LowerOperation(Result, DAG);
2281 if (Tmp1.Val) Result = Tmp1;
2283 case TargetLowering::Promote:
2284 assert(MVT::isVector(VT) && "Unknown legal promote case!");
2285 Tmp3 = DAG.getNode(ISD::BIT_CONVERT,
2286 TLI.getTypeToPromoteTo(ISD::STORE, VT), Tmp3);
2287 Result = DAG.getStore(Tmp1, Tmp3, Tmp2,
2288 ST->getSrcValue(), SVOffset, isVolatile,
2295 // Truncate the value and store the result.
2296 Tmp3 = PromoteOp(ST->getValue());
2297 Result = DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2298 SVOffset, ST->getMemoryVT(),
2299 isVolatile, Alignment);
2303 unsigned IncrementSize = 0;
2306 // If this is a vector type, then we have to calculate the increment as
2307 // the product of the element size in bytes, and the number of elements
2308 // in the high half of the vector.
2309 if (MVT::isVector(ST->getValue().getValueType())) {
2310 SDNode *InVal = ST->getValue().Val;
2311 int InIx = ST->getValue().ResNo;
2312 MVT::ValueType InVT = InVal->getValueType(InIx);
2313 unsigned NumElems = MVT::getVectorNumElements(InVT);
2314 MVT::ValueType EVT = MVT::getVectorElementType(InVT);
2316 // Figure out if there is a simple type corresponding to this Vector
2317 // type. If so, convert to the vector type.
2318 MVT::ValueType TVT = MVT::getVectorType(EVT, NumElems);
2319 if (TLI.isTypeLegal(TVT)) {
2320 // Turn this into a normal store of the vector type.
2321 Tmp3 = LegalizeOp(Node->getOperand(1));
2322 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2323 SVOffset, isVolatile, Alignment);
2324 Result = LegalizeOp(Result);
2326 } else if (NumElems == 1) {
2327 // Turn this into a normal store of the scalar type.
2328 Tmp3 = ScalarizeVectorOp(Node->getOperand(1));
2329 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2330 SVOffset, isVolatile, Alignment);
2331 // The scalarized value type may not be legal, e.g. it might require
2332 // promotion or expansion. Relegalize the scalar store.
2333 Result = LegalizeOp(Result);
2336 SplitVectorOp(Node->getOperand(1), Lo, Hi);
2337 IncrementSize = MVT::getVectorNumElements(Lo.Val->getValueType(0)) *
2338 MVT::getSizeInBits(EVT)/8;
2341 ExpandOp(Node->getOperand(1), Lo, Hi);
2342 IncrementSize = Hi.Val ? MVT::getSizeInBits(Hi.getValueType())/8 : 0;
2344 if (!TLI.isLittleEndian())
2348 Lo = DAG.getStore(Tmp1, Lo, Tmp2, ST->getSrcValue(),
2349 SVOffset, isVolatile, Alignment);
2351 if (Hi.Val == NULL) {
2352 // Must be int <-> float one-to-one expansion.
2357 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2,
2358 DAG.getIntPtrConstant(IncrementSize));
2359 assert(isTypeLegal(Tmp2.getValueType()) &&
2360 "Pointers must be legal!");
2361 SVOffset += IncrementSize;
2362 Alignment = MinAlign(Alignment, IncrementSize);
2363 Hi = DAG.getStore(Tmp1, Hi, Tmp2, ST->getSrcValue(),
2364 SVOffset, isVolatile, Alignment);
2365 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi);
2369 switch (getTypeAction(ST->getValue().getValueType())) {
2371 Tmp3 = LegalizeOp(ST->getValue());
2374 // We can promote the value, the truncstore will still take care of it.
2375 Tmp3 = PromoteOp(ST->getValue());
2378 // Just store the low part. This may become a non-trunc store, so make
2379 // sure to use getTruncStore, not UpdateNodeOperands below.
2380 ExpandOp(ST->getValue(), Tmp3, Tmp4);
2381 return DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2382 SVOffset, MVT::i8, isVolatile, Alignment);
2385 MVT::ValueType StVT = ST->getMemoryVT();
2386 unsigned StWidth = MVT::getSizeInBits(StVT);
2388 if (StWidth != MVT::getStoreSizeInBits(StVT)) {
2389 // Promote to a byte-sized store with upper bits zero if not
2390 // storing an integral number of bytes. For example, promote
2391 // TRUNCSTORE:i1 X -> TRUNCSTORE:i8 (and X, 1)
2392 MVT::ValueType NVT = MVT::getIntegerType(MVT::getStoreSizeInBits(StVT));
2393 Tmp3 = DAG.getZeroExtendInReg(Tmp3, StVT);
2394 Result = DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2395 SVOffset, NVT, isVolatile, Alignment);
2396 } else if (StWidth & (StWidth - 1)) {
2397 // If not storing a power-of-2 number of bits, expand as two stores.
2398 assert(MVT::isExtendedVT(StVT) && !MVT::isVector(StVT) &&
2399 "Unsupported truncstore!");
2400 unsigned RoundWidth = 1 << Log2_32(StWidth);
2401 assert(RoundWidth < StWidth);
2402 unsigned ExtraWidth = StWidth - RoundWidth;
2403 assert(ExtraWidth < RoundWidth);
2404 assert(!(RoundWidth % 8) && !(ExtraWidth % 8) &&
2405 "Store size not an integral number of bytes!");
2406 MVT::ValueType RoundVT = MVT::getIntegerType(RoundWidth);
2407 MVT::ValueType ExtraVT = MVT::getIntegerType(ExtraWidth);
2409 unsigned IncrementSize;
2411 if (TLI.isLittleEndian()) {
2412 // TRUNCSTORE:i24 X -> TRUNCSTORE:i16 X, TRUNCSTORE@+2:i8 (srl X, 16)
2413 // Store the bottom RoundWidth bits.
2414 Lo = DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2416 isVolatile, Alignment);
2418 // Store the remaining ExtraWidth bits.
2419 IncrementSize = RoundWidth / 8;
2420 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2,
2421 DAG.getIntPtrConstant(IncrementSize));
2422 Hi = DAG.getNode(ISD::SRL, Tmp3.getValueType(), Tmp3,
2423 DAG.getConstant(RoundWidth, TLI.getShiftAmountTy()));
2424 Hi = DAG.getTruncStore(Tmp1, Hi, Tmp2, ST->getSrcValue(),
2425 SVOffset + IncrementSize, ExtraVT, isVolatile,
2426 MinAlign(Alignment, IncrementSize));
2428 // Big endian - avoid unaligned stores.
2429 // TRUNCSTORE:i24 X -> TRUNCSTORE:i16 (srl X, 8), TRUNCSTORE@+2:i8 X
2430 // Store the top RoundWidth bits.
2431 Hi = DAG.getNode(ISD::SRL, Tmp3.getValueType(), Tmp3,
2432 DAG.getConstant(ExtraWidth, TLI.getShiftAmountTy()));
2433 Hi = DAG.getTruncStore(Tmp1, Hi, Tmp2, ST->getSrcValue(), SVOffset,
2434 RoundVT, isVolatile, Alignment);
2436 // Store the remaining ExtraWidth bits.
2437 IncrementSize = RoundWidth / 8;
2438 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2,
2439 DAG.getIntPtrConstant(IncrementSize));
2440 Lo = DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2441 SVOffset + IncrementSize, ExtraVT, isVolatile,
2442 MinAlign(Alignment, IncrementSize));
2445 // The order of the stores doesn't matter.
2446 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi);
2448 if (Tmp1 != ST->getChain() || Tmp3 != ST->getValue() ||
2449 Tmp2 != ST->getBasePtr())
2450 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2,
2453 switch (TLI.getTruncStoreAction(ST->getValue().getValueType(), StVT)) {
2454 default: assert(0 && "This action is not supported yet!");
2455 case TargetLowering::Legal:
2456 // If this is an unaligned store and the target doesn't support it,
2458 if (!TLI.allowsUnalignedMemoryAccesses()) {
2459 unsigned ABIAlignment = TLI.getTargetData()->
2460 getABITypeAlignment(MVT::getTypeForValueType(ST->getMemoryVT()));
2461 if (ST->getAlignment() < ABIAlignment)
2462 Result = ExpandUnalignedStore(cast<StoreSDNode>(Result.Val), DAG,
2466 case TargetLowering::Custom:
2467 Result = TLI.LowerOperation(Result, DAG);
2470 // TRUNCSTORE:i16 i32 -> STORE i16
2471 assert(isTypeLegal(StVT) && "Do not know how to expand this store!");
2472 Tmp3 = DAG.getNode(ISD::TRUNCATE, StVT, Tmp3);
2473 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(), SVOffset,
2474 isVolatile, Alignment);
2482 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2483 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
2485 case ISD::STACKSAVE:
2486 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2487 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2488 Tmp1 = Result.getValue(0);
2489 Tmp2 = Result.getValue(1);
2491 switch (TLI.getOperationAction(ISD::STACKSAVE, MVT::Other)) {
2492 default: assert(0 && "This action is not supported yet!");
2493 case TargetLowering::Legal: break;
2494 case TargetLowering::Custom:
2495 Tmp3 = TLI.LowerOperation(Result, DAG);
2497 Tmp1 = LegalizeOp(Tmp3);
2498 Tmp2 = LegalizeOp(Tmp3.getValue(1));
2501 case TargetLowering::Expand:
2502 // Expand to CopyFromReg if the target set
2503 // StackPointerRegisterToSaveRestore.
2504 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) {
2505 Tmp1 = DAG.getCopyFromReg(Result.getOperand(0), SP,
2506 Node->getValueType(0));
2507 Tmp2 = Tmp1.getValue(1);
2509 Tmp1 = DAG.getNode(ISD::UNDEF, Node->getValueType(0));
2510 Tmp2 = Node->getOperand(0);
2515 // Since stacksave produce two values, make sure to remember that we
2516 // legalized both of them.
2517 AddLegalizedOperand(SDOperand(Node, 0), Tmp1);
2518 AddLegalizedOperand(SDOperand(Node, 1), Tmp2);
2519 return Op.ResNo ? Tmp2 : Tmp1;
2521 case ISD::STACKRESTORE:
2522 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2523 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
2524 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
2526 switch (TLI.getOperationAction(ISD::STACKRESTORE, MVT::Other)) {
2527 default: assert(0 && "This action is not supported yet!");
2528 case TargetLowering::Legal: break;
2529 case TargetLowering::Custom:
2530 Tmp1 = TLI.LowerOperation(Result, DAG);
2531 if (Tmp1.Val) Result = Tmp1;
2533 case TargetLowering::Expand:
2534 // Expand to CopyToReg if the target set
2535 // StackPointerRegisterToSaveRestore.
2536 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) {
2537 Result = DAG.getCopyToReg(Tmp1, SP, Tmp2);
2545 case ISD::READCYCLECOUNTER:
2546 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain
2547 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2548 switch (TLI.getOperationAction(ISD::READCYCLECOUNTER,
2549 Node->getValueType(0))) {
2550 default: assert(0 && "This action is not supported yet!");
2551 case TargetLowering::Legal:
2552 Tmp1 = Result.getValue(0);
2553 Tmp2 = Result.getValue(1);
2555 case TargetLowering::Custom:
2556 Result = TLI.LowerOperation(Result, DAG);
2557 Tmp1 = LegalizeOp(Result.getValue(0));
2558 Tmp2 = LegalizeOp(Result.getValue(1));
2562 // Since rdcc produce two values, make sure to remember that we legalized
2564 AddLegalizedOperand(SDOperand(Node, 0), Tmp1);
2565 AddLegalizedOperand(SDOperand(Node, 1), Tmp2);
2569 switch (getTypeAction(Node->getOperand(0).getValueType())) {
2570 case Expand: assert(0 && "It's impossible to expand bools");
2572 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the condition.
2575 Tmp1 = PromoteOp(Node->getOperand(0)); // Promote the condition.
2576 // Make sure the condition is either zero or one.
2577 if (!DAG.MaskedValueIsZero(Tmp1,
2578 MVT::getIntVTBitMask(Tmp1.getValueType())^1))
2579 Tmp1 = DAG.getZeroExtendInReg(Tmp1, MVT::i1);
2582 Tmp2 = LegalizeOp(Node->getOperand(1)); // TrueVal
2583 Tmp3 = LegalizeOp(Node->getOperand(2)); // FalseVal
2585 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2587 switch (TLI.getOperationAction(ISD::SELECT, Tmp2.getValueType())) {
2588 default: assert(0 && "This action is not supported yet!");
2589 case TargetLowering::Legal: break;
2590 case TargetLowering::Custom: {
2591 Tmp1 = TLI.LowerOperation(Result, DAG);
2592 if (Tmp1.Val) Result = Tmp1;
2595 case TargetLowering::Expand:
2596 if (Tmp1.getOpcode() == ISD::SETCC) {
2597 Result = DAG.getSelectCC(Tmp1.getOperand(0), Tmp1.getOperand(1),
2599 cast<CondCodeSDNode>(Tmp1.getOperand(2))->get());
2601 Result = DAG.getSelectCC(Tmp1,
2602 DAG.getConstant(0, Tmp1.getValueType()),
2603 Tmp2, Tmp3, ISD::SETNE);
2606 case TargetLowering::Promote: {
2607 MVT::ValueType NVT =
2608 TLI.getTypeToPromoteTo(ISD::SELECT, Tmp2.getValueType());
2609 unsigned ExtOp, TruncOp;
2610 if (MVT::isVector(Tmp2.getValueType())) {
2611 ExtOp = ISD::BIT_CONVERT;
2612 TruncOp = ISD::BIT_CONVERT;
2613 } else if (MVT::isInteger(Tmp2.getValueType())) {
2614 ExtOp = ISD::ANY_EXTEND;
2615 TruncOp = ISD::TRUNCATE;
2617 ExtOp = ISD::FP_EXTEND;
2618 TruncOp = ISD::FP_ROUND;
2620 // Promote each of the values to the new type.
2621 Tmp2 = DAG.getNode(ExtOp, NVT, Tmp2);
2622 Tmp3 = DAG.getNode(ExtOp, NVT, Tmp3);
2623 // Perform the larger operation, then round down.
2624 Result = DAG.getNode(ISD::SELECT, NVT, Tmp1, Tmp2,Tmp3);
2625 if (TruncOp != ISD::FP_ROUND)
2626 Result = DAG.getNode(TruncOp, Node->getValueType(0), Result);
2628 Result = DAG.getNode(TruncOp, Node->getValueType(0), Result,
2629 DAG.getIntPtrConstant(0));
2634 case ISD::SELECT_CC: {
2635 Tmp1 = Node->getOperand(0); // LHS
2636 Tmp2 = Node->getOperand(1); // RHS
2637 Tmp3 = LegalizeOp(Node->getOperand(2)); // True
2638 Tmp4 = LegalizeOp(Node->getOperand(3)); // False
2639 SDOperand CC = Node->getOperand(4);
2641 LegalizeSetCCOperands(Tmp1, Tmp2, CC);
2643 // If we didn't get both a LHS and RHS back from LegalizeSetCCOperands,
2644 // the LHS is a legal SETCC itself. In this case, we need to compare
2645 // the result against zero to select between true and false values.
2646 if (Tmp2.Val == 0) {
2647 Tmp2 = DAG.getConstant(0, Tmp1.getValueType());
2648 CC = DAG.getCondCode(ISD::SETNE);
2650 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4, CC);
2652 // Everything is legal, see if we should expand this op or something.
2653 switch (TLI.getOperationAction(ISD::SELECT_CC, Tmp3.getValueType())) {
2654 default: assert(0 && "This action is not supported yet!");
2655 case TargetLowering::Legal: break;
2656 case TargetLowering::Custom:
2657 Tmp1 = TLI.LowerOperation(Result, DAG);
2658 if (Tmp1.Val) Result = Tmp1;
2664 Tmp1 = Node->getOperand(0);
2665 Tmp2 = Node->getOperand(1);
2666 Tmp3 = Node->getOperand(2);
2667 LegalizeSetCCOperands(Tmp1, Tmp2, Tmp3);
2669 // If we had to Expand the SetCC operands into a SELECT node, then it may
2670 // not always be possible to return a true LHS & RHS. In this case, just
2671 // return the value we legalized, returned in the LHS
2672 if (Tmp2.Val == 0) {
2677 switch (TLI.getOperationAction(ISD::SETCC, Tmp1.getValueType())) {
2678 default: assert(0 && "Cannot handle this action for SETCC yet!");
2679 case TargetLowering::Custom:
2682 case TargetLowering::Legal:
2683 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2685 Tmp4 = TLI.LowerOperation(Result, DAG);
2686 if (Tmp4.Val) Result = Tmp4;
2689 case TargetLowering::Promote: {
2690 // First step, figure out the appropriate operation to use.
2691 // Allow SETCC to not be supported for all legal data types
2692 // Mostly this targets FP
2693 MVT::ValueType NewInTy = Node->getOperand(0).getValueType();
2694 MVT::ValueType OldVT = NewInTy; OldVT = OldVT;
2696 // Scan for the appropriate larger type to use.
2698 NewInTy = (MVT::ValueType)(NewInTy+1);
2700 assert(MVT::isInteger(NewInTy) == MVT::isInteger(OldVT) &&
2701 "Fell off of the edge of the integer world");
2702 assert(MVT::isFloatingPoint(NewInTy) == MVT::isFloatingPoint(OldVT) &&
2703 "Fell off of the edge of the floating point world");
2705 // If the target supports SETCC of this type, use it.
2706 if (TLI.isOperationLegal(ISD::SETCC, NewInTy))
2709 if (MVT::isInteger(NewInTy))
2710 assert(0 && "Cannot promote Legal Integer SETCC yet");
2712 Tmp1 = DAG.getNode(ISD::FP_EXTEND, NewInTy, Tmp1);
2713 Tmp2 = DAG.getNode(ISD::FP_EXTEND, NewInTy, Tmp2);
2715 Tmp1 = LegalizeOp(Tmp1);
2716 Tmp2 = LegalizeOp(Tmp2);
2717 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2718 Result = LegalizeOp(Result);
2721 case TargetLowering::Expand:
2722 // Expand a setcc node into a select_cc of the same condition, lhs, and
2723 // rhs that selects between const 1 (true) and const 0 (false).
2724 MVT::ValueType VT = Node->getValueType(0);
2725 Result = DAG.getNode(ISD::SELECT_CC, VT, Tmp1, Tmp2,
2726 DAG.getConstant(1, VT), DAG.getConstant(0, VT),
2733 case ISD::MEMMOVE: {
2734 Tmp1 = LegalizeOp(Node->getOperand(0)); // Chain
2735 Tmp2 = LegalizeOp(Node->getOperand(1)); // Pointer
2737 if (Node->getOpcode() == ISD::MEMSET) { // memset = ubyte
2738 switch (getTypeAction(Node->getOperand(2).getValueType())) {
2739 case Expand: assert(0 && "Cannot expand a byte!");
2741 Tmp3 = LegalizeOp(Node->getOperand(2));
2744 Tmp3 = PromoteOp(Node->getOperand(2));
2748 Tmp3 = LegalizeOp(Node->getOperand(2)); // memcpy/move = pointer,
2752 switch (getTypeAction(Node->getOperand(3).getValueType())) {
2754 // Length is too big, just take the lo-part of the length.
2756 ExpandOp(Node->getOperand(3), Tmp4, HiPart);
2760 Tmp4 = LegalizeOp(Node->getOperand(3));
2763 Tmp4 = PromoteOp(Node->getOperand(3));
2768 switch (getTypeAction(Node->getOperand(4).getValueType())) { // uint
2769 case Expand: assert(0 && "Cannot expand this yet!");
2771 Tmp5 = LegalizeOp(Node->getOperand(4));
2774 Tmp5 = PromoteOp(Node->getOperand(4));
2779 switch (getTypeAction(Node->getOperand(5).getValueType())) { // bool
2780 case Expand: assert(0 && "Cannot expand this yet!");
2782 Tmp6 = LegalizeOp(Node->getOperand(5));
2785 Tmp6 = PromoteOp(Node->getOperand(5));
2789 switch (TLI.getOperationAction(Node->getOpcode(), MVT::Other)) {
2790 default: assert(0 && "This action not implemented for this operation!");
2791 case TargetLowering::Custom:
2794 case TargetLowering::Legal: {
2795 SDOperand Ops[] = { Tmp1, Tmp2, Tmp3, Tmp4, Tmp5, Tmp6 };
2796 Result = DAG.UpdateNodeOperands(Result, Ops, 6);
2798 Tmp1 = TLI.LowerOperation(Result, DAG);
2799 if (Tmp1.Val) Result = Tmp1;
2803 case TargetLowering::Expand: {
2804 // Otherwise, the target does not support this operation. Lower the
2805 // operation to an explicit libcall as appropriate.
2806 MVT::ValueType IntPtr = TLI.getPointerTy();
2807 const Type *IntPtrTy = TLI.getTargetData()->getIntPtrType();
2808 TargetLowering::ArgListTy Args;
2809 TargetLowering::ArgListEntry Entry;
2811 const char *FnName = 0;
2812 if (Node->getOpcode() == ISD::MEMSET) {
2813 Entry.Node = Tmp2; Entry.Ty = IntPtrTy;
2814 Args.push_back(Entry);
2815 // Extend the (previously legalized) ubyte argument to be an int value
2817 if (Tmp3.getValueType() > MVT::i32)
2818 Tmp3 = DAG.getNode(ISD::TRUNCATE, MVT::i32, Tmp3);
2820 Tmp3 = DAG.getNode(ISD::ZERO_EXTEND, MVT::i32, Tmp3);
2821 Entry.Node = Tmp3; Entry.Ty = Type::Int32Ty; Entry.isSExt = true;
2822 Args.push_back(Entry);
2823 Entry.Node = Tmp4; Entry.Ty = IntPtrTy; Entry.isSExt = false;
2824 Args.push_back(Entry);
2827 } else if (Node->getOpcode() == ISD::MEMCPY ||
2828 Node->getOpcode() == ISD::MEMMOVE) {
2829 Entry.Ty = IntPtrTy;
2830 Entry.Node = Tmp2; Args.push_back(Entry);
2831 Entry.Node = Tmp3; Args.push_back(Entry);
2832 Entry.Node = Tmp4; Args.push_back(Entry);
2833 FnName = Node->getOpcode() == ISD::MEMMOVE ? "memmove" : "memcpy";
2835 assert(0 && "Unknown op!");
2838 std::pair<SDOperand,SDOperand> CallResult =
2839 TLI.LowerCallTo(Tmp1, Type::VoidTy, false, false, CallingConv::C, false,
2840 DAG.getExternalSymbol(FnName, IntPtr), Args, DAG);
2841 Result = CallResult.second;
2848 case ISD::SHL_PARTS:
2849 case ISD::SRA_PARTS:
2850 case ISD::SRL_PARTS: {
2851 SmallVector<SDOperand, 8> Ops;
2852 bool Changed = false;
2853 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
2854 Ops.push_back(LegalizeOp(Node->getOperand(i)));
2855 Changed |= Ops.back() != Node->getOperand(i);
2858 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
2860 switch (TLI.getOperationAction(Node->getOpcode(),
2861 Node->getValueType(0))) {
2862 default: assert(0 && "This action is not supported yet!");
2863 case TargetLowering::Legal: break;
2864 case TargetLowering::Custom:
2865 Tmp1 = TLI.LowerOperation(Result, DAG);
2867 SDOperand Tmp2, RetVal(0, 0);
2868 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) {
2869 Tmp2 = LegalizeOp(Tmp1.getValue(i));
2870 AddLegalizedOperand(SDOperand(Node, i), Tmp2);
2874 assert(RetVal.Val && "Illegal result number");
2880 // Since these produce multiple values, make sure to remember that we
2881 // legalized all of them.
2882 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
2883 AddLegalizedOperand(SDOperand(Node, i), Result.getValue(i));
2884 return Result.getValue(Op.ResNo);
2906 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
2907 switch (getTypeAction(Node->getOperand(1).getValueType())) {
2908 case Expand: assert(0 && "Not possible");
2910 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the RHS.
2913 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the RHS.
2917 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
2919 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
2920 default: assert(0 && "BinOp legalize operation not supported");
2921 case TargetLowering::Legal: break;
2922 case TargetLowering::Custom:
2923 Tmp1 = TLI.LowerOperation(Result, DAG);
2924 if (Tmp1.Val) Result = Tmp1;
2926 case TargetLowering::Expand: {
2927 MVT::ValueType VT = Op.getValueType();
2929 // See if multiply or divide can be lowered using two-result operations.
2930 SDVTList VTs = DAG.getVTList(VT, VT);
2931 if (Node->getOpcode() == ISD::MUL) {
2932 // We just need the low half of the multiply; try both the signed
2933 // and unsigned forms. If the target supports both SMUL_LOHI and
2934 // UMUL_LOHI, form a preference by checking which forms of plain
2935 // MULH it supports.
2936 bool HasSMUL_LOHI = TLI.isOperationLegal(ISD::SMUL_LOHI, VT);
2937 bool HasUMUL_LOHI = TLI.isOperationLegal(ISD::UMUL_LOHI, VT);
2938 bool HasMULHS = TLI.isOperationLegal(ISD::MULHS, VT);
2939 bool HasMULHU = TLI.isOperationLegal(ISD::MULHU, VT);
2940 unsigned OpToUse = 0;
2941 if (HasSMUL_LOHI && !HasMULHS) {
2942 OpToUse = ISD::SMUL_LOHI;
2943 } else if (HasUMUL_LOHI && !HasMULHU) {
2944 OpToUse = ISD::UMUL_LOHI;
2945 } else if (HasSMUL_LOHI) {
2946 OpToUse = ISD::SMUL_LOHI;
2947 } else if (HasUMUL_LOHI) {
2948 OpToUse = ISD::UMUL_LOHI;
2951 Result = SDOperand(DAG.getNode(OpToUse, VTs, Tmp1, Tmp2).Val, 0);
2955 if (Node->getOpcode() == ISD::MULHS &&
2956 TLI.isOperationLegal(ISD::SMUL_LOHI, VT)) {
2957 Result = SDOperand(DAG.getNode(ISD::SMUL_LOHI, VTs, Tmp1, Tmp2).Val, 1);
2960 if (Node->getOpcode() == ISD::MULHU &&
2961 TLI.isOperationLegal(ISD::UMUL_LOHI, VT)) {
2962 Result = SDOperand(DAG.getNode(ISD::UMUL_LOHI, VTs, Tmp1, Tmp2).Val, 1);
2965 if (Node->getOpcode() == ISD::SDIV &&
2966 TLI.isOperationLegal(ISD::SDIVREM, VT)) {
2967 Result = SDOperand(DAG.getNode(ISD::SDIVREM, VTs, Tmp1, Tmp2).Val, 0);
2970 if (Node->getOpcode() == ISD::UDIV &&
2971 TLI.isOperationLegal(ISD::UDIVREM, VT)) {
2972 Result = SDOperand(DAG.getNode(ISD::UDIVREM, VTs, Tmp1, Tmp2).Val, 0);
2976 // Check to see if we have a libcall for this operator.
2977 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
2978 bool isSigned = false;
2979 switch (Node->getOpcode()) {
2982 if (VT == MVT::i32) {
2983 LC = Node->getOpcode() == ISD::UDIV
2984 ? RTLIB::UDIV_I32 : RTLIB::SDIV_I32;
2985 isSigned = Node->getOpcode() == ISD::SDIV;
2989 LC = GetFPLibCall(VT, RTLIB::POW_F32, RTLIB::POW_F64, RTLIB::POW_F80,
2990 RTLIB::POW_PPCF128);
2994 if (LC != RTLIB::UNKNOWN_LIBCALL) {
2996 Result = ExpandLibCall(TLI.getLibcallName(LC), Node, isSigned, Dummy);
3000 assert(MVT::isVector(Node->getValueType(0)) &&
3001 "Cannot expand this binary operator!");
3002 // Expand the operation into a bunch of nasty scalar code.
3003 Result = LegalizeOp(UnrollVectorOp(Op));
3006 case TargetLowering::Promote: {
3007 switch (Node->getOpcode()) {
3008 default: assert(0 && "Do not know how to promote this BinOp!");
3012 MVT::ValueType OVT = Node->getValueType(0);
3013 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
3014 assert(MVT::isVector(OVT) && "Cannot promote this BinOp!");
3015 // Bit convert each of the values to the new type.
3016 Tmp1 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp1);
3017 Tmp2 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp2);
3018 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
3019 // Bit convert the result back the original type.
3020 Result = DAG.getNode(ISD::BIT_CONVERT, OVT, Result);
3028 case ISD::SMUL_LOHI:
3029 case ISD::UMUL_LOHI:
3032 // These nodes will only be produced by target-specific lowering, so
3033 // they shouldn't be here if they aren't legal.
3034 assert(TLI.isOperationLegal(Node->getOpcode(), Node->getValueType(0)) &&
3035 "This must be legal!");
3037 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
3038 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS
3039 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
3042 case ISD::FCOPYSIGN: // FCOPYSIGN does not require LHS/RHS to match type!
3043 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
3044 switch (getTypeAction(Node->getOperand(1).getValueType())) {
3045 case Expand: assert(0 && "Not possible");
3047 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the RHS.
3050 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the RHS.
3054 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
3056 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3057 default: assert(0 && "Operation not supported");
3058 case TargetLowering::Custom:
3059 Tmp1 = TLI.LowerOperation(Result, DAG);
3060 if (Tmp1.Val) Result = Tmp1;
3062 case TargetLowering::Legal: break;
3063 case TargetLowering::Expand: {
3064 // If this target supports fabs/fneg natively and select is cheap,
3065 // do this efficiently.
3066 if (!TLI.isSelectExpensive() &&
3067 TLI.getOperationAction(ISD::FABS, Tmp1.getValueType()) ==
3068 TargetLowering::Legal &&
3069 TLI.getOperationAction(ISD::FNEG, Tmp1.getValueType()) ==
3070 TargetLowering::Legal) {
3071 // Get the sign bit of the RHS.
3072 MVT::ValueType IVT =
3073 Tmp2.getValueType() == MVT::f32 ? MVT::i32 : MVT::i64;
3074 SDOperand SignBit = DAG.getNode(ISD::BIT_CONVERT, IVT, Tmp2);
3075 SignBit = DAG.getSetCC(TLI.getSetCCResultTy(),
3076 SignBit, DAG.getConstant(0, IVT), ISD::SETLT);
3077 // Get the absolute value of the result.
3078 SDOperand AbsVal = DAG.getNode(ISD::FABS, Tmp1.getValueType(), Tmp1);
3079 // Select between the nabs and abs value based on the sign bit of
3081 Result = DAG.getNode(ISD::SELECT, AbsVal.getValueType(), SignBit,
3082 DAG.getNode(ISD::FNEG, AbsVal.getValueType(),
3085 Result = LegalizeOp(Result);
3089 // Otherwise, do bitwise ops!
3090 MVT::ValueType NVT =
3091 Node->getValueType(0) == MVT::f32 ? MVT::i32 : MVT::i64;
3092 Result = ExpandFCOPYSIGNToBitwiseOps(Node, NVT, DAG, TLI);
3093 Result = DAG.getNode(ISD::BIT_CONVERT, Node->getValueType(0), Result);
3094 Result = LegalizeOp(Result);
3102 Tmp1 = LegalizeOp(Node->getOperand(0));
3103 Tmp2 = LegalizeOp(Node->getOperand(1));
3104 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
3105 // Since this produces two values, make sure to remember that we legalized
3107 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
3108 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
3113 Tmp1 = LegalizeOp(Node->getOperand(0));
3114 Tmp2 = LegalizeOp(Node->getOperand(1));
3115 Tmp3 = LegalizeOp(Node->getOperand(2));
3116 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
3117 // Since this produces two values, make sure to remember that we legalized
3119 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
3120 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
3123 case ISD::BUILD_PAIR: {
3124 MVT::ValueType PairTy = Node->getValueType(0);
3125 // TODO: handle the case where the Lo and Hi operands are not of legal type
3126 Tmp1 = LegalizeOp(Node->getOperand(0)); // Lo
3127 Tmp2 = LegalizeOp(Node->getOperand(1)); // Hi
3128 switch (TLI.getOperationAction(ISD::BUILD_PAIR, PairTy)) {
3129 case TargetLowering::Promote:
3130 case TargetLowering::Custom:
3131 assert(0 && "Cannot promote/custom this yet!");
3132 case TargetLowering::Legal:
3133 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1))
3134 Result = DAG.getNode(ISD::BUILD_PAIR, PairTy, Tmp1, Tmp2);
3136 case TargetLowering::Expand:
3137 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, PairTy, Tmp1);
3138 Tmp2 = DAG.getNode(ISD::ANY_EXTEND, PairTy, Tmp2);
3139 Tmp2 = DAG.getNode(ISD::SHL, PairTy, Tmp2,
3140 DAG.getConstant(MVT::getSizeInBits(PairTy)/2,
3141 TLI.getShiftAmountTy()));
3142 Result = DAG.getNode(ISD::OR, PairTy, Tmp1, Tmp2);
3151 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
3152 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS
3154 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3155 case TargetLowering::Promote: assert(0 && "Cannot promote this yet!");
3156 case TargetLowering::Custom:
3159 case TargetLowering::Legal:
3160 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
3162 Tmp1 = TLI.LowerOperation(Result, DAG);
3163 if (Tmp1.Val) Result = Tmp1;
3166 case TargetLowering::Expand: {
3167 unsigned DivOpc= (Node->getOpcode() == ISD::UREM) ? ISD::UDIV : ISD::SDIV;
3168 bool isSigned = DivOpc == ISD::SDIV;
3169 MVT::ValueType VT = Node->getValueType(0);
3171 // See if remainder can be lowered using two-result operations.
3172 SDVTList VTs = DAG.getVTList(VT, VT);
3173 if (Node->getOpcode() == ISD::SREM &&
3174 TLI.isOperationLegal(ISD::SDIVREM, VT)) {
3175 Result = SDOperand(DAG.getNode(ISD::SDIVREM, VTs, Tmp1, Tmp2).Val, 1);
3178 if (Node->getOpcode() == ISD::UREM &&
3179 TLI.isOperationLegal(ISD::UDIVREM, VT)) {
3180 Result = SDOperand(DAG.getNode(ISD::UDIVREM, VTs, Tmp1, Tmp2).Val, 1);
3184 if (MVT::isInteger(VT)) {
3185 if (TLI.getOperationAction(DivOpc, VT) ==
3186 TargetLowering::Legal) {
3188 Result = DAG.getNode(DivOpc, VT, Tmp1, Tmp2);
3189 Result = DAG.getNode(ISD::MUL, VT, Result, Tmp2);
3190 Result = DAG.getNode(ISD::SUB, VT, Tmp1, Result);
3191 } else if (MVT::isVector(VT)) {
3192 Result = LegalizeOp(UnrollVectorOp(Op));
3194 assert(VT == MVT::i32 &&
3195 "Cannot expand this binary operator!");
3196 RTLIB::Libcall LC = Node->getOpcode() == ISD::UREM
3197 ? RTLIB::UREM_I32 : RTLIB::SREM_I32;
3199 Result = ExpandLibCall(TLI.getLibcallName(LC), Node, isSigned, Dummy);
3202 assert(MVT::isFloatingPoint(VT) &&
3203 "remainder op must have integer or floating-point type");
3204 if (MVT::isVector(VT)) {
3205 Result = LegalizeOp(UnrollVectorOp(Op));
3207 // Floating point mod -> fmod libcall.
3208 RTLIB::Libcall LC = GetFPLibCall(VT, RTLIB::REM_F32, RTLIB::REM_F64,
3209 RTLIB::REM_F80, RTLIB::REM_PPCF128);
3211 Result = ExpandLibCall(TLI.getLibcallName(LC), Node,
3212 false/*sign irrelevant*/, Dummy);
3220 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
3221 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
3223 MVT::ValueType VT = Node->getValueType(0);
3224 switch (TLI.getOperationAction(Node->getOpcode(), MVT::Other)) {
3225 default: assert(0 && "This action is not supported yet!");
3226 case TargetLowering::Custom:
3229 case TargetLowering::Legal:
3230 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
3231 Result = Result.getValue(0);
3232 Tmp1 = Result.getValue(1);
3235 Tmp2 = TLI.LowerOperation(Result, DAG);
3237 Result = LegalizeOp(Tmp2);
3238 Tmp1 = LegalizeOp(Tmp2.getValue(1));
3242 case TargetLowering::Expand: {
3243 SrcValueSDNode *SV = cast<SrcValueSDNode>(Node->getOperand(2));
3244 SDOperand VAList = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp2,
3245 SV->getValue(), SV->getOffset());
3246 // Increment the pointer, VAList, to the next vaarg
3247 Tmp3 = DAG.getNode(ISD::ADD, TLI.getPointerTy(), VAList,
3248 DAG.getConstant(MVT::getSizeInBits(VT)/8,
3249 TLI.getPointerTy()));
3250 // Store the incremented VAList to the legalized pointer
3251 Tmp3 = DAG.getStore(VAList.getValue(1), Tmp3, Tmp2, SV->getValue(),
3253 // Load the actual argument out of the pointer VAList
3254 Result = DAG.getLoad(VT, Tmp3, VAList, NULL, 0);
3255 Tmp1 = LegalizeOp(Result.getValue(1));
3256 Result = LegalizeOp(Result);
3260 // Since VAARG produces two values, make sure to remember that we
3261 // legalized both of them.
3262 AddLegalizedOperand(SDOperand(Node, 0), Result);
3263 AddLegalizedOperand(SDOperand(Node, 1), Tmp1);
3264 return Op.ResNo ? Tmp1 : Result;
3268 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
3269 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the dest pointer.
3270 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the source pointer.
3272 switch (TLI.getOperationAction(ISD::VACOPY, MVT::Other)) {
3273 default: assert(0 && "This action is not supported yet!");
3274 case TargetLowering::Custom:
3277 case TargetLowering::Legal:
3278 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3,
3279 Node->getOperand(3), Node->getOperand(4));
3281 Tmp1 = TLI.LowerOperation(Result, DAG);
3282 if (Tmp1.Val) Result = Tmp1;
3285 case TargetLowering::Expand:
3286 // This defaults to loading a pointer from the input and storing it to the
3287 // output, returning the chain.
3288 SrcValueSDNode *SVD = cast<SrcValueSDNode>(Node->getOperand(3));
3289 SrcValueSDNode *SVS = cast<SrcValueSDNode>(Node->getOperand(4));
3290 Tmp4 = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp3, SVD->getValue(),
3292 Result = DAG.getStore(Tmp4.getValue(1), Tmp4, Tmp2, SVS->getValue(),
3299 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
3300 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
3302 switch (TLI.getOperationAction(ISD::VAEND, MVT::Other)) {
3303 default: assert(0 && "This action is not supported yet!");
3304 case TargetLowering::Custom:
3307 case TargetLowering::Legal:
3308 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
3310 Tmp1 = TLI.LowerOperation(Tmp1, DAG);
3311 if (Tmp1.Val) Result = Tmp1;
3314 case TargetLowering::Expand:
3315 Result = Tmp1; // Default to a no-op, return the chain
3321 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
3322 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
3324 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
3326 switch (TLI.getOperationAction(ISD::VASTART, MVT::Other)) {
3327 default: assert(0 && "This action is not supported yet!");
3328 case TargetLowering::Legal: break;
3329 case TargetLowering::Custom:
3330 Tmp1 = TLI.LowerOperation(Result, DAG);
3331 if (Tmp1.Val) Result = Tmp1;
3338 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
3339 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS
3340 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
3341 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3343 assert(0 && "ROTL/ROTR legalize operation not supported");
3345 case TargetLowering::Legal:
3347 case TargetLowering::Custom:
3348 Tmp1 = TLI.LowerOperation(Result, DAG);
3349 if (Tmp1.Val) Result = Tmp1;
3351 case TargetLowering::Promote:
3352 assert(0 && "Do not know how to promote ROTL/ROTR");
3354 case TargetLowering::Expand:
3355 assert(0 && "Do not know how to expand ROTL/ROTR");
3361 Tmp1 = LegalizeOp(Node->getOperand(0)); // Op
3362 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3363 case TargetLowering::Custom:
3364 assert(0 && "Cannot custom legalize this yet!");
3365 case TargetLowering::Legal:
3366 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3368 case TargetLowering::Promote: {
3369 MVT::ValueType OVT = Tmp1.getValueType();
3370 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
3371 unsigned DiffBits = MVT::getSizeInBits(NVT) - MVT::getSizeInBits(OVT);
3373 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1);
3374 Tmp1 = DAG.getNode(ISD::BSWAP, NVT, Tmp1);
3375 Result = DAG.getNode(ISD::SRL, NVT, Tmp1,
3376 DAG.getConstant(DiffBits, TLI.getShiftAmountTy()));
3379 case TargetLowering::Expand:
3380 Result = ExpandBSWAP(Tmp1);
3388 Tmp1 = LegalizeOp(Node->getOperand(0)); // Op
3389 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3390 case TargetLowering::Custom:
3391 case TargetLowering::Legal:
3392 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3393 if (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0)) ==
3394 TargetLowering::Custom) {
3395 Tmp1 = TLI.LowerOperation(Result, DAG);
3401 case TargetLowering::Promote: {
3402 MVT::ValueType OVT = Tmp1.getValueType();
3403 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
3405 // Zero extend the argument.
3406 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1);
3407 // Perform the larger operation, then subtract if needed.
3408 Tmp1 = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1);
3409 switch (Node->getOpcode()) {
3414 //if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT)
3415 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), Tmp1,
3416 DAG.getConstant(MVT::getSizeInBits(NVT), NVT),
3418 Result = DAG.getNode(ISD::SELECT, NVT, Tmp2,
3419 DAG.getConstant(MVT::getSizeInBits(OVT),NVT), Tmp1);
3422 // Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT))
3423 Result = DAG.getNode(ISD::SUB, NVT, Tmp1,
3424 DAG.getConstant(MVT::getSizeInBits(NVT) -
3425 MVT::getSizeInBits(OVT), NVT));
3430 case TargetLowering::Expand:
3431 Result = ExpandBitCount(Node->getOpcode(), Tmp1);
3442 Tmp1 = LegalizeOp(Node->getOperand(0));
3443 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3444 case TargetLowering::Promote:
3445 case TargetLowering::Custom:
3448 case TargetLowering::Legal:
3449 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3451 Tmp1 = TLI.LowerOperation(Result, DAG);
3452 if (Tmp1.Val) Result = Tmp1;
3455 case TargetLowering::Expand:
3456 switch (Node->getOpcode()) {
3457 default: assert(0 && "Unreachable!");
3459 // Expand Y = FNEG(X) -> Y = SUB -0.0, X
3460 Tmp2 = DAG.getConstantFP(-0.0, Node->getValueType(0));
3461 Result = DAG.getNode(ISD::FSUB, Node->getValueType(0), Tmp2, Tmp1);
3464 // Expand Y = FABS(X) -> Y = (X >u 0.0) ? X : fneg(X).
3465 MVT::ValueType VT = Node->getValueType(0);
3466 Tmp2 = DAG.getConstantFP(0.0, VT);
3467 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), Tmp1, Tmp2, ISD::SETUGT);
3468 Tmp3 = DAG.getNode(ISD::FNEG, VT, Tmp1);
3469 Result = DAG.getNode(ISD::SELECT, VT, Tmp2, Tmp1, Tmp3);
3475 MVT::ValueType VT = Node->getValueType(0);
3477 // Expand unsupported unary vector operators by unrolling them.
3478 if (MVT::isVector(VT)) {
3479 Result = LegalizeOp(UnrollVectorOp(Op));
3483 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
3484 switch(Node->getOpcode()) {
3486 LC = GetFPLibCall(VT, RTLIB::SQRT_F32, RTLIB::SQRT_F64,
3487 RTLIB::SQRT_F80, RTLIB::SQRT_PPCF128);
3490 LC = GetFPLibCall(VT, RTLIB::SIN_F32, RTLIB::SIN_F64,
3491 RTLIB::SIN_F80, RTLIB::SIN_PPCF128);
3494 LC = GetFPLibCall(VT, RTLIB::COS_F32, RTLIB::COS_F64,
3495 RTLIB::COS_F80, RTLIB::COS_PPCF128);
3497 default: assert(0 && "Unreachable!");
3500 Result = ExpandLibCall(TLI.getLibcallName(LC), Node,
3501 false/*sign irrelevant*/, Dummy);
3509 MVT::ValueType VT = Node->getValueType(0);
3511 // Expand unsupported unary vector operators by unrolling them.
3512 if (MVT::isVector(VT)) {
3513 Result = LegalizeOp(UnrollVectorOp(Op));
3517 // We always lower FPOWI into a libcall. No target support for it yet.
3518 RTLIB::Libcall LC = GetFPLibCall(VT, RTLIB::POWI_F32, RTLIB::POWI_F64,
3519 RTLIB::POWI_F80, RTLIB::POWI_PPCF128);
3521 Result = ExpandLibCall(TLI.getLibcallName(LC), Node,
3522 false/*sign irrelevant*/, Dummy);
3525 case ISD::BIT_CONVERT:
3526 if (!isTypeLegal(Node->getOperand(0).getValueType())) {
3527 Result = EmitStackConvert(Node->getOperand(0), Node->getValueType(0),
3528 Node->getValueType(0));
3529 } else if (MVT::isVector(Op.getOperand(0).getValueType())) {
3530 // The input has to be a vector type, we have to either scalarize it, pack
3531 // it, or convert it based on whether the input vector type is legal.
3532 SDNode *InVal = Node->getOperand(0).Val;
3533 int InIx = Node->getOperand(0).ResNo;
3534 unsigned NumElems = MVT::getVectorNumElements(InVal->getValueType(InIx));
3535 MVT::ValueType EVT = MVT::getVectorElementType(InVal->getValueType(InIx));
3537 // Figure out if there is a simple type corresponding to this Vector
3538 // type. If so, convert to the vector type.
3539 MVT::ValueType TVT = MVT::getVectorType(EVT, NumElems);
3540 if (TLI.isTypeLegal(TVT)) {
3541 // Turn this into a bit convert of the vector input.
3542 Result = DAG.getNode(ISD::BIT_CONVERT, Node->getValueType(0),
3543 LegalizeOp(Node->getOperand(0)));
3545 } else if (NumElems == 1) {
3546 // Turn this into a bit convert of the scalar input.
3547 Result = DAG.getNode(ISD::BIT_CONVERT, Node->getValueType(0),
3548 ScalarizeVectorOp(Node->getOperand(0)));
3551 // FIXME: UNIMP! Store then reload
3552 assert(0 && "Cast from unsupported vector type not implemented yet!");
3555 switch (TLI.getOperationAction(ISD::BIT_CONVERT,
3556 Node->getOperand(0).getValueType())) {
3557 default: assert(0 && "Unknown operation action!");
3558 case TargetLowering::Expand:
3559 Result = EmitStackConvert(Node->getOperand(0), Node->getValueType(0),
3560 Node->getValueType(0));
3562 case TargetLowering::Legal:
3563 Tmp1 = LegalizeOp(Node->getOperand(0));
3564 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3570 // Conversion operators. The source and destination have different types.
3571 case ISD::SINT_TO_FP:
3572 case ISD::UINT_TO_FP: {
3573 bool isSigned = Node->getOpcode() == ISD::SINT_TO_FP;
3574 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3576 switch (TLI.getOperationAction(Node->getOpcode(),
3577 Node->getOperand(0).getValueType())) {
3578 default: assert(0 && "Unknown operation action!");
3579 case TargetLowering::Custom:
3582 case TargetLowering::Legal:
3583 Tmp1 = LegalizeOp(Node->getOperand(0));
3584 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3586 Tmp1 = TLI.LowerOperation(Result, DAG);
3587 if (Tmp1.Val) Result = Tmp1;
3590 case TargetLowering::Expand:
3591 Result = ExpandLegalINT_TO_FP(isSigned,
3592 LegalizeOp(Node->getOperand(0)),
3593 Node->getValueType(0));
3595 case TargetLowering::Promote:
3596 Result = PromoteLegalINT_TO_FP(LegalizeOp(Node->getOperand(0)),
3597 Node->getValueType(0),
3603 Result = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP,
3604 Node->getValueType(0), Node->getOperand(0));
3607 Tmp1 = PromoteOp(Node->getOperand(0));
3609 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, Tmp1.getValueType(),
3610 Tmp1, DAG.getValueType(Node->getOperand(0).getValueType()));
3612 Tmp1 = DAG.getZeroExtendInReg(Tmp1,
3613 Node->getOperand(0).getValueType());
3615 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3616 Result = LegalizeOp(Result); // The 'op' is not necessarily legal!
3622 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3624 Tmp1 = LegalizeOp(Node->getOperand(0));
3625 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3628 ExpandOp(Node->getOperand(0), Tmp1, Tmp2);
3630 // Since the result is legal, we should just be able to truncate the low
3631 // part of the source.
3632 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), Tmp1);
3635 Result = PromoteOp(Node->getOperand(0));
3636 Result = DAG.getNode(ISD::TRUNCATE, Op.getValueType(), Result);
3641 case ISD::FP_TO_SINT:
3642 case ISD::FP_TO_UINT:
3643 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3645 Tmp1 = LegalizeOp(Node->getOperand(0));
3647 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))){
3648 default: assert(0 && "Unknown operation action!");
3649 case TargetLowering::Custom:
3652 case TargetLowering::Legal:
3653 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3655 Tmp1 = TLI.LowerOperation(Result, DAG);
3656 if (Tmp1.Val) Result = Tmp1;
3659 case TargetLowering::Promote:
3660 Result = PromoteLegalFP_TO_INT(Tmp1, Node->getValueType(0),
3661 Node->getOpcode() == ISD::FP_TO_SINT);
3663 case TargetLowering::Expand:
3664 if (Node->getOpcode() == ISD::FP_TO_UINT) {
3665 SDOperand True, False;
3666 MVT::ValueType VT = Node->getOperand(0).getValueType();
3667 MVT::ValueType NVT = Node->getValueType(0);
3668 unsigned ShiftAmt = MVT::getSizeInBits(NVT)-1;
3669 const uint64_t zero[] = {0, 0};
3670 APFloat apf = APFloat(APInt(MVT::getSizeInBits(VT), 2, zero));
3671 uint64_t x = 1ULL << ShiftAmt;
3672 (void)apf.convertFromZeroExtendedInteger
3673 (&x, MVT::getSizeInBits(NVT), false, APFloat::rmNearestTiesToEven);
3674 Tmp2 = DAG.getConstantFP(apf, VT);
3675 Tmp3 = DAG.getSetCC(TLI.getSetCCResultTy(),
3676 Node->getOperand(0), Tmp2, ISD::SETLT);
3677 True = DAG.getNode(ISD::FP_TO_SINT, NVT, Node->getOperand(0));
3678 False = DAG.getNode(ISD::FP_TO_SINT, NVT,
3679 DAG.getNode(ISD::FSUB, VT, Node->getOperand(0),
3681 False = DAG.getNode(ISD::XOR, NVT, False,
3682 DAG.getConstant(1ULL << ShiftAmt, NVT));
3683 Result = DAG.getNode(ISD::SELECT, NVT, Tmp3, True, False);
3686 assert(0 && "Do not know how to expand FP_TO_SINT yet!");
3692 MVT::ValueType VT = Op.getValueType();
3693 MVT::ValueType OVT = Node->getOperand(0).getValueType();
3694 // Convert ppcf128 to i32
3695 if (OVT == MVT::ppcf128 && VT == MVT::i32) {
3696 if (Node->getOpcode() == ISD::FP_TO_SINT) {
3697 Result = DAG.getNode(ISD::FP_ROUND_INREG, MVT::ppcf128,
3698 Node->getOperand(0), DAG.getValueType(MVT::f64));
3699 Result = DAG.getNode(ISD::FP_ROUND, MVT::f64, Result,
3700 DAG.getIntPtrConstant(1));
3701 Result = DAG.getNode(ISD::FP_TO_SINT, VT, Result);
3703 const uint64_t TwoE31[] = {0x41e0000000000000LL, 0};
3704 APFloat apf = APFloat(APInt(128, 2, TwoE31));
3705 Tmp2 = DAG.getConstantFP(apf, OVT);
3706 // X>=2^31 ? (int)(X-2^31)+0x80000000 : (int)X
3707 // FIXME: generated code sucks.
3708 Result = DAG.getNode(ISD::SELECT_CC, VT, Node->getOperand(0), Tmp2,
3709 DAG.getNode(ISD::ADD, MVT::i32,
3710 DAG.getNode(ISD::FP_TO_SINT, VT,
3711 DAG.getNode(ISD::FSUB, OVT,
3712 Node->getOperand(0), Tmp2)),
3713 DAG.getConstant(0x80000000, MVT::i32)),
3714 DAG.getNode(ISD::FP_TO_SINT, VT,
3715 Node->getOperand(0)),
3716 DAG.getCondCode(ISD::SETGE));
3720 // Convert f32 / f64 to i32 / i64.
3721 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
3722 switch (Node->getOpcode()) {
3723 case ISD::FP_TO_SINT: {
3724 if (OVT == MVT::f32)
3725 LC = (VT == MVT::i32)
3726 ? RTLIB::FPTOSINT_F32_I32 : RTLIB::FPTOSINT_F32_I64;
3727 else if (OVT == MVT::f64)
3728 LC = (VT == MVT::i32)
3729 ? RTLIB::FPTOSINT_F64_I32 : RTLIB::FPTOSINT_F64_I64;
3730 else if (OVT == MVT::f80) {
3731 assert(VT == MVT::i64);
3732 LC = RTLIB::FPTOSINT_F80_I64;
3734 else if (OVT == MVT::ppcf128) {
3735 assert(VT == MVT::i64);
3736 LC = RTLIB::FPTOSINT_PPCF128_I64;
3740 case ISD::FP_TO_UINT: {
3741 if (OVT == MVT::f32)
3742 LC = (VT == MVT::i32)
3743 ? RTLIB::FPTOUINT_F32_I32 : RTLIB::FPTOSINT_F32_I64;
3744 else if (OVT == MVT::f64)
3745 LC = (VT == MVT::i32)
3746 ? RTLIB::FPTOUINT_F64_I32 : RTLIB::FPTOSINT_F64_I64;
3747 else if (OVT == MVT::f80) {
3748 LC = (VT == MVT::i32)
3749 ? RTLIB::FPTOUINT_F80_I32 : RTLIB::FPTOUINT_F80_I64;
3751 else if (OVT == MVT::ppcf128) {
3752 assert(VT == MVT::i64);
3753 LC = RTLIB::FPTOUINT_PPCF128_I64;
3757 default: assert(0 && "Unreachable!");
3760 Result = ExpandLibCall(TLI.getLibcallName(LC), Node,
3761 false/*sign irrelevant*/, Dummy);
3765 Tmp1 = PromoteOp(Node->getOperand(0));
3766 Result = DAG.UpdateNodeOperands(Result, LegalizeOp(Tmp1));
3767 Result = LegalizeOp(Result);
3772 case ISD::FP_EXTEND: {
3773 MVT::ValueType DstVT = Op.getValueType();
3774 MVT::ValueType SrcVT = Op.getOperand(0).getValueType();
3775 if (TLI.getConvertAction(SrcVT, DstVT) == TargetLowering::Expand) {
3776 // The only other way we can lower this is to turn it into a STORE,
3777 // LOAD pair, targetting a temporary location (a stack slot).
3778 Result = EmitStackConvert(Node->getOperand(0), SrcVT, DstVT);
3781 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3782 case Expand: assert(0 && "Shouldn't need to expand other operators here!");
3784 Tmp1 = LegalizeOp(Node->getOperand(0));
3785 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3788 Tmp1 = PromoteOp(Node->getOperand(0));
3789 Result = DAG.getNode(ISD::FP_EXTEND, Op.getValueType(), Tmp1);
3794 case ISD::FP_ROUND: {
3795 MVT::ValueType DstVT = Op.getValueType();
3796 MVT::ValueType SrcVT = Op.getOperand(0).getValueType();
3797 if (TLI.getConvertAction(SrcVT, DstVT) == TargetLowering::Expand) {
3798 if (SrcVT == MVT::ppcf128) {
3800 ExpandOp(Node->getOperand(0), Lo, Result);
3801 // Round it the rest of the way (e.g. to f32) if needed.
3802 if (DstVT!=MVT::f64)
3803 Result = DAG.getNode(ISD::FP_ROUND, DstVT, Result, Op.getOperand(1));
3806 // The only other way we can lower this is to turn it into a STORE,
3807 // LOAD pair, targetting a temporary location (a stack slot).
3808 Result = EmitStackConvert(Node->getOperand(0), DstVT, DstVT);
3811 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3812 case Expand: assert(0 && "Shouldn't need to expand other operators here!");
3814 Tmp1 = LegalizeOp(Node->getOperand(0));
3815 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
3818 Tmp1 = PromoteOp(Node->getOperand(0));
3819 Result = DAG.getNode(ISD::FP_ROUND, Op.getValueType(), Tmp1,
3820 Node->getOperand(1));
3825 case ISD::ANY_EXTEND:
3826 case ISD::ZERO_EXTEND:
3827 case ISD::SIGN_EXTEND:
3828 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3829 case Expand: assert(0 && "Shouldn't need to expand other operators here!");
3831 Tmp1 = LegalizeOp(Node->getOperand(0));
3832 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3835 switch (Node->getOpcode()) {
3836 case ISD::ANY_EXTEND:
3837 Tmp1 = PromoteOp(Node->getOperand(0));
3838 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Tmp1);
3840 case ISD::ZERO_EXTEND:
3841 Result = PromoteOp(Node->getOperand(0));
3842 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Result);
3843 Result = DAG.getZeroExtendInReg(Result,
3844 Node->getOperand(0).getValueType());
3846 case ISD::SIGN_EXTEND:
3847 Result = PromoteOp(Node->getOperand(0));
3848 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Result);
3849 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(),
3851 DAG.getValueType(Node->getOperand(0).getValueType()));
3856 case ISD::FP_ROUND_INREG:
3857 case ISD::SIGN_EXTEND_INREG: {
3858 Tmp1 = LegalizeOp(Node->getOperand(0));
3859 MVT::ValueType ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT();
3861 // If this operation is not supported, convert it to a shl/shr or load/store
3863 switch (TLI.getOperationAction(Node->getOpcode(), ExtraVT)) {
3864 default: assert(0 && "This action not supported for this op yet!");
3865 case TargetLowering::Legal:
3866 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
3868 case TargetLowering::Expand:
3869 // If this is an integer extend and shifts are supported, do that.
3870 if (Node->getOpcode() == ISD::SIGN_EXTEND_INREG) {
3871 // NOTE: we could fall back on load/store here too for targets without
3872 // SAR. However, it is doubtful that any exist.
3873 unsigned BitsDiff = MVT::getSizeInBits(Node->getValueType(0)) -
3874 MVT::getSizeInBits(ExtraVT);
3875 SDOperand ShiftCst = DAG.getConstant(BitsDiff, TLI.getShiftAmountTy());
3876 Result = DAG.getNode(ISD::SHL, Node->getValueType(0),
3877 Node->getOperand(0), ShiftCst);
3878 Result = DAG.getNode(ISD::SRA, Node->getValueType(0),
3880 } else if (Node->getOpcode() == ISD::FP_ROUND_INREG) {
3881 // The only way we can lower this is to turn it into a TRUNCSTORE,
3882 // EXTLOAD pair, targetting a temporary location (a stack slot).
3884 // NOTE: there is a choice here between constantly creating new stack
3885 // slots and always reusing the same one. We currently always create
3886 // new ones, as reuse may inhibit scheduling.
3887 Result = EmitStackConvert(Node->getOperand(0), ExtraVT,
3888 Node->getValueType(0));
3890 assert(0 && "Unknown op");
3896 case ISD::TRAMPOLINE: {
3898 for (unsigned i = 0; i != 6; ++i)
3899 Ops[i] = LegalizeOp(Node->getOperand(i));
3900 Result = DAG.UpdateNodeOperands(Result, Ops, 6);
3901 // The only option for this node is to custom lower it.
3902 Result = TLI.LowerOperation(Result, DAG);
3903 assert(Result.Val && "Should always custom lower!");
3905 // Since trampoline produces two values, make sure to remember that we
3906 // legalized both of them.
3907 Tmp1 = LegalizeOp(Result.getValue(1));
3908 Result = LegalizeOp(Result);
3909 AddLegalizedOperand(SDOperand(Node, 0), Result);
3910 AddLegalizedOperand(SDOperand(Node, 1), Tmp1);
3911 return Op.ResNo ? Tmp1 : Result;
3913 case ISD::FLT_ROUNDS_: {
3914 MVT::ValueType VT = Node->getValueType(0);
3915 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
3916 default: assert(0 && "This action not supported for this op yet!");
3917 case TargetLowering::Custom:
3918 Result = TLI.LowerOperation(Op, DAG);
3919 if (Result.Val) break;
3921 case TargetLowering::Legal:
3922 // If this operation is not supported, lower it to constant 1
3923 Result = DAG.getConstant(1, VT);
3928 MVT::ValueType VT = Node->getValueType(0);
3929 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
3930 default: assert(0 && "This action not supported for this op yet!");
3931 case TargetLowering::Legal:
3932 Tmp1 = LegalizeOp(Node->getOperand(0));
3933 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3935 case TargetLowering::Custom:
3936 Result = TLI.LowerOperation(Op, DAG);
3937 if (Result.Val) break;
3939 case TargetLowering::Expand:
3940 // If this operation is not supported, lower it to 'abort()' call
3941 Tmp1 = LegalizeOp(Node->getOperand(0));
3942 TargetLowering::ArgListTy Args;
3943 std::pair<SDOperand,SDOperand> CallResult =
3944 TLI.LowerCallTo(Tmp1, Type::VoidTy, false, false, CallingConv::C, false,
3945 DAG.getExternalSymbol("abort", TLI.getPointerTy()),
3947 Result = CallResult.second;
3954 assert(Result.getValueType() == Op.getValueType() &&
3955 "Bad legalization!");
3957 // Make sure that the generated code is itself legal.
3959 Result = LegalizeOp(Result);
3961 // Note that LegalizeOp may be reentered even from single-use nodes, which
3962 // means that we always must cache transformed nodes.
3963 AddLegalizedOperand(Op, Result);
3967 /// PromoteOp - Given an operation that produces a value in an invalid type,
3968 /// promote it to compute the value into a larger type. The produced value will
3969 /// have the correct bits for the low portion of the register, but no guarantee
3970 /// is made about the top bits: it may be zero, sign-extended, or garbage.
3971 SDOperand SelectionDAGLegalize::PromoteOp(SDOperand Op) {
3972 MVT::ValueType VT = Op.getValueType();
3973 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT);
3974 assert(getTypeAction(VT) == Promote &&
3975 "Caller should expand or legalize operands that are not promotable!");
3976 assert(NVT > VT && MVT::isInteger(NVT) == MVT::isInteger(VT) &&
3977 "Cannot promote to smaller type!");
3979 SDOperand Tmp1, Tmp2, Tmp3;
3981 SDNode *Node = Op.Val;
3983 DenseMap<SDOperand, SDOperand>::iterator I = PromotedNodes.find(Op);
3984 if (I != PromotedNodes.end()) return I->second;
3986 switch (Node->getOpcode()) {
3987 case ISD::CopyFromReg:
3988 assert(0 && "CopyFromReg must be legal!");
3991 cerr << "NODE: "; Node->dump(&DAG); cerr << "\n";
3993 assert(0 && "Do not know how to promote this operator!");
3996 Result = DAG.getNode(ISD::UNDEF, NVT);
4000 Result = DAG.getNode(ISD::SIGN_EXTEND, NVT, Op);
4002 Result = DAG.getNode(ISD::ZERO_EXTEND, NVT, Op);
4003 assert(isa<ConstantSDNode>(Result) && "Didn't constant fold zext?");
4005 case ISD::ConstantFP:
4006 Result = DAG.getNode(ISD::FP_EXTEND, NVT, Op);
4007 assert(isa<ConstantFPSDNode>(Result) && "Didn't constant fold fp_extend?");
4011 assert(isTypeLegal(TLI.getSetCCResultTy()) && "SetCC type is not legal??");
4012 Result = DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(),Node->getOperand(0),
4013 Node->getOperand(1), Node->getOperand(2));
4017 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4019 Result = LegalizeOp(Node->getOperand(0));
4020 assert(Result.getValueType() >= NVT &&
4021 "This truncation doesn't make sense!");
4022 if (Result.getValueType() > NVT) // Truncate to NVT instead of VT
4023 Result = DAG.getNode(ISD::TRUNCATE, NVT, Result);
4026 // The truncation is not required, because we don't guarantee anything
4027 // about high bits anyway.
4028 Result = PromoteOp(Node->getOperand(0));
4031 ExpandOp(Node->getOperand(0), Tmp1, Tmp2);
4032 // Truncate the low part of the expanded value to the result type
4033 Result = DAG.getNode(ISD::TRUNCATE, NVT, Tmp1);
4036 case ISD::SIGN_EXTEND:
4037 case ISD::ZERO_EXTEND:
4038 case ISD::ANY_EXTEND:
4039 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4040 case Expand: assert(0 && "BUG: Smaller reg should have been promoted!");
4042 // Input is legal? Just do extend all the way to the larger type.
4043 Result = DAG.getNode(Node->getOpcode(), NVT, Node->getOperand(0));
4046 // Promote the reg if it's smaller.
4047 Result = PromoteOp(Node->getOperand(0));
4048 // The high bits are not guaranteed to be anything. Insert an extend.
4049 if (Node->getOpcode() == ISD::SIGN_EXTEND)
4050 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Result,
4051 DAG.getValueType(Node->getOperand(0).getValueType()));
4052 else if (Node->getOpcode() == ISD::ZERO_EXTEND)
4053 Result = DAG.getZeroExtendInReg(Result,
4054 Node->getOperand(0).getValueType());
4058 case ISD::BIT_CONVERT:
4059 Result = EmitStackConvert(Node->getOperand(0), Node->getValueType(0),
4060 Node->getValueType(0));
4061 Result = PromoteOp(Result);
4064 case ISD::FP_EXTEND:
4065 assert(0 && "Case not implemented. Dynamically dead with 2 FP types!");
4067 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4068 case Expand: assert(0 && "BUG: Cannot expand FP regs!");
4069 case Promote: assert(0 && "Unreachable with 2 FP types!");
4071 if (Node->getConstantOperandVal(1) == 0) {
4072 // Input is legal? Do an FP_ROUND_INREG.
4073 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Node->getOperand(0),
4074 DAG.getValueType(VT));
4076 // Just remove the truncate, it isn't affecting the value.
4077 Result = DAG.getNode(ISD::FP_ROUND, NVT, Node->getOperand(0),
4078 Node->getOperand(1));
4083 case ISD::SINT_TO_FP:
4084 case ISD::UINT_TO_FP:
4085 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4087 // No extra round required here.
4088 Result = DAG.getNode(Node->getOpcode(), NVT, Node->getOperand(0));
4092 Result = PromoteOp(Node->getOperand(0));
4093 if (Node->getOpcode() == ISD::SINT_TO_FP)
4094 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(),
4096 DAG.getValueType(Node->getOperand(0).getValueType()));
4098 Result = DAG.getZeroExtendInReg(Result,
4099 Node->getOperand(0).getValueType());
4100 // No extra round required here.
4101 Result = DAG.getNode(Node->getOpcode(), NVT, Result);
4104 Result = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP, NVT,
4105 Node->getOperand(0));
4106 // Round if we cannot tolerate excess precision.
4107 if (NoExcessFPPrecision)
4108 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
4109 DAG.getValueType(VT));
4114 case ISD::SIGN_EXTEND_INREG:
4115 Result = PromoteOp(Node->getOperand(0));
4116 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Result,
4117 Node->getOperand(1));
4119 case ISD::FP_TO_SINT:
4120 case ISD::FP_TO_UINT:
4121 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4124 Tmp1 = Node->getOperand(0);
4127 // The input result is prerounded, so we don't have to do anything
4129 Tmp1 = PromoteOp(Node->getOperand(0));
4132 // If we're promoting a UINT to a larger size, check to see if the new node
4133 // will be legal. If it isn't, check to see if FP_TO_SINT is legal, since
4134 // we can use that instead. This allows us to generate better code for
4135 // FP_TO_UINT for small destination sizes on targets where FP_TO_UINT is not
4136 // legal, such as PowerPC.
4137 if (Node->getOpcode() == ISD::FP_TO_UINT &&
4138 !TLI.isOperationLegal(ISD::FP_TO_UINT, NVT) &&
4139 (TLI.isOperationLegal(ISD::FP_TO_SINT, NVT) ||
4140 TLI.getOperationAction(ISD::FP_TO_SINT, NVT)==TargetLowering::Custom)){
4141 Result = DAG.getNode(ISD::FP_TO_SINT, NVT, Tmp1);
4143 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
4149 Tmp1 = PromoteOp(Node->getOperand(0));
4150 assert(Tmp1.getValueType() == NVT);
4151 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
4152 // NOTE: we do not have to do any extra rounding here for
4153 // NoExcessFPPrecision, because we know the input will have the appropriate
4154 // precision, and these operations don't modify precision at all.
4160 Tmp1 = PromoteOp(Node->getOperand(0));
4161 assert(Tmp1.getValueType() == NVT);
4162 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
4163 if (NoExcessFPPrecision)
4164 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
4165 DAG.getValueType(VT));
4169 // Promote f32 powi to f64 powi. Note that this could insert a libcall
4170 // directly as well, which may be better.
4171 Tmp1 = PromoteOp(Node->getOperand(0));
4172 assert(Tmp1.getValueType() == NVT);
4173 Result = DAG.getNode(ISD::FPOWI, NVT, Tmp1, Node->getOperand(1));
4174 if (NoExcessFPPrecision)
4175 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
4176 DAG.getValueType(VT));
4186 // The input may have strange things in the top bits of the registers, but
4187 // these operations don't care. They may have weird bits going out, but
4188 // that too is okay if they are integer operations.
4189 Tmp1 = PromoteOp(Node->getOperand(0));
4190 Tmp2 = PromoteOp(Node->getOperand(1));
4191 assert(Tmp1.getValueType() == NVT && Tmp2.getValueType() == NVT);
4192 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
4197 Tmp1 = PromoteOp(Node->getOperand(0));
4198 Tmp2 = PromoteOp(Node->getOperand(1));
4199 assert(Tmp1.getValueType() == NVT && Tmp2.getValueType() == NVT);
4200 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
4202 // Floating point operations will give excess precision that we may not be
4203 // able to tolerate. If we DO allow excess precision, just leave it,
4204 // otherwise excise it.
4205 // FIXME: Why would we need to round FP ops more than integer ones?
4206 // Is Round(Add(Add(A,B),C)) != Round(Add(Round(Add(A,B)), C))
4207 if (NoExcessFPPrecision)
4208 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
4209 DAG.getValueType(VT));
4214 // These operators require that their input be sign extended.
4215 Tmp1 = PromoteOp(Node->getOperand(0));
4216 Tmp2 = PromoteOp(Node->getOperand(1));
4217 if (MVT::isInteger(NVT)) {
4218 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1,
4219 DAG.getValueType(VT));
4220 Tmp2 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp2,
4221 DAG.getValueType(VT));
4223 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
4225 // Perform FP_ROUND: this is probably overly pessimistic.
4226 if (MVT::isFloatingPoint(NVT) && NoExcessFPPrecision)
4227 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
4228 DAG.getValueType(VT));
4232 case ISD::FCOPYSIGN:
4233 // These operators require that their input be fp extended.
4234 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4235 case Expand: assert(0 && "not implemented");
4236 case Legal: Tmp1 = LegalizeOp(Node->getOperand(0)); break;
4237 case Promote: Tmp1 = PromoteOp(Node->getOperand(0)); break;
4239 switch (getTypeAction(Node->getOperand(1).getValueType())) {
4240 case Expand: assert(0 && "not implemented");
4241 case Legal: Tmp2 = LegalizeOp(Node->getOperand(1)); break;
4242 case Promote: Tmp2 = PromoteOp(Node->getOperand(1)); break;
4244 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
4246 // Perform FP_ROUND: this is probably overly pessimistic.
4247 if (NoExcessFPPrecision && Node->getOpcode() != ISD::FCOPYSIGN)
4248 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
4249 DAG.getValueType(VT));
4254 // These operators require that their input be zero extended.
4255 Tmp1 = PromoteOp(Node->getOperand(0));
4256 Tmp2 = PromoteOp(Node->getOperand(1));
4257 assert(MVT::isInteger(NVT) && "Operators don't apply to FP!");
4258 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT);
4259 Tmp2 = DAG.getZeroExtendInReg(Tmp2, VT);
4260 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
4264 Tmp1 = PromoteOp(Node->getOperand(0));
4265 Result = DAG.getNode(ISD::SHL, NVT, Tmp1, Node->getOperand(1));
4268 // The input value must be properly sign extended.
4269 Tmp1 = PromoteOp(Node->getOperand(0));
4270 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1,
4271 DAG.getValueType(VT));
4272 Result = DAG.getNode(ISD::SRA, NVT, Tmp1, Node->getOperand(1));
4275 // The input value must be properly zero extended.
4276 Tmp1 = PromoteOp(Node->getOperand(0));
4277 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT);
4278 Result = DAG.getNode(ISD::SRL, NVT, Tmp1, Node->getOperand(1));
4282 Tmp1 = Node->getOperand(0); // Get the chain.
4283 Tmp2 = Node->getOperand(1); // Get the pointer.
4284 if (TLI.getOperationAction(ISD::VAARG, VT) == TargetLowering::Custom) {
4285 Tmp3 = DAG.getVAArg(VT, Tmp1, Tmp2, Node->getOperand(2));
4286 Result = TLI.CustomPromoteOperation(Tmp3, DAG);
4288 SrcValueSDNode *SV = cast<SrcValueSDNode>(Node->getOperand(2));
4289 SDOperand VAList = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp2,
4290 SV->getValue(), SV->getOffset());
4291 // Increment the pointer, VAList, to the next vaarg
4292 Tmp3 = DAG.getNode(ISD::ADD, TLI.getPointerTy(), VAList,
4293 DAG.getConstant(MVT::getSizeInBits(VT)/8,
4294 TLI.getPointerTy()));
4295 // Store the incremented VAList to the legalized pointer
4296 Tmp3 = DAG.getStore(VAList.getValue(1), Tmp3, Tmp2, SV->getValue(),
4298 // Load the actual argument out of the pointer VAList
4299 Result = DAG.getExtLoad(ISD::EXTLOAD, NVT, Tmp3, VAList, NULL, 0, VT);
4301 // Remember that we legalized the chain.
4302 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
4306 LoadSDNode *LD = cast<LoadSDNode>(Node);
4307 ISD::LoadExtType ExtType = ISD::isNON_EXTLoad(Node)
4308 ? ISD::EXTLOAD : LD->getExtensionType();
4309 Result = DAG.getExtLoad(ExtType, NVT,
4310 LD->getChain(), LD->getBasePtr(),
4311 LD->getSrcValue(), LD->getSrcValueOffset(),
4314 LD->getAlignment());
4315 // Remember that we legalized the chain.
4316 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
4320 Tmp2 = PromoteOp(Node->getOperand(1)); // Legalize the op0
4321 Tmp3 = PromoteOp(Node->getOperand(2)); // Legalize the op1
4322 Result = DAG.getNode(ISD::SELECT, NVT, Node->getOperand(0), Tmp2, Tmp3);
4324 case ISD::SELECT_CC:
4325 Tmp2 = PromoteOp(Node->getOperand(2)); // True
4326 Tmp3 = PromoteOp(Node->getOperand(3)); // False
4327 Result = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0),
4328 Node->getOperand(1), Tmp2, Tmp3, Node->getOperand(4));
4331 Tmp1 = Node->getOperand(0);
4332 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1);
4333 Tmp1 = DAG.getNode(ISD::BSWAP, NVT, Tmp1);
4334 Result = DAG.getNode(ISD::SRL, NVT, Tmp1,
4335 DAG.getConstant(MVT::getSizeInBits(NVT) -
4336 MVT::getSizeInBits(VT),
4337 TLI.getShiftAmountTy()));
4342 // Zero extend the argument
4343 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Node->getOperand(0));
4344 // Perform the larger operation, then subtract if needed.
4345 Tmp1 = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
4346 switch(Node->getOpcode()) {
4351 // if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT)
4352 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), Tmp1,
4353 DAG.getConstant(MVT::getSizeInBits(NVT), NVT),
4355 Result = DAG.getNode(ISD::SELECT, NVT, Tmp2,
4356 DAG.getConstant(MVT::getSizeInBits(VT), NVT), Tmp1);
4359 //Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT))
4360 Result = DAG.getNode(ISD::SUB, NVT, Tmp1,
4361 DAG.getConstant(MVT::getSizeInBits(NVT) -
4362 MVT::getSizeInBits(VT), NVT));
4366 case ISD::EXTRACT_SUBVECTOR:
4367 Result = PromoteOp(ExpandEXTRACT_SUBVECTOR(Op));
4369 case ISD::EXTRACT_VECTOR_ELT:
4370 Result = PromoteOp(ExpandEXTRACT_VECTOR_ELT(Op));
4374 assert(Result.Val && "Didn't set a result!");
4376 // Make sure the result is itself legal.
4377 Result = LegalizeOp(Result);
4379 // Remember that we promoted this!
4380 AddPromotedOperand(Op, Result);
4384 /// ExpandEXTRACT_VECTOR_ELT - Expand an EXTRACT_VECTOR_ELT operation into
4385 /// a legal EXTRACT_VECTOR_ELT operation, scalar code, or memory traffic,
4386 /// based on the vector type. The return type of this matches the element type
4387 /// of the vector, which may not be legal for the target.
4388 SDOperand SelectionDAGLegalize::ExpandEXTRACT_VECTOR_ELT(SDOperand Op) {
4389 // We know that operand #0 is the Vec vector. If the index is a constant
4390 // or if the invec is a supported hardware type, we can use it. Otherwise,
4391 // lower to a store then an indexed load.
4392 SDOperand Vec = Op.getOperand(0);
4393 SDOperand Idx = Op.getOperand(1);
4395 MVT::ValueType TVT = Vec.getValueType();
4396 unsigned NumElems = MVT::getVectorNumElements(TVT);
4398 switch (TLI.getOperationAction(ISD::EXTRACT_VECTOR_ELT, TVT)) {
4399 default: assert(0 && "This action is not supported yet!");
4400 case TargetLowering::Custom: {
4401 Vec = LegalizeOp(Vec);
4402 Op = DAG.UpdateNodeOperands(Op, Vec, Idx);
4403 SDOperand Tmp3 = TLI.LowerOperation(Op, DAG);
4408 case TargetLowering::Legal:
4409 if (isTypeLegal(TVT)) {
4410 Vec = LegalizeOp(Vec);
4411 Op = DAG.UpdateNodeOperands(Op, Vec, Idx);
4415 case TargetLowering::Expand:
4419 if (NumElems == 1) {
4420 // This must be an access of the only element. Return it.
4421 Op = ScalarizeVectorOp(Vec);
4422 } else if (!TLI.isTypeLegal(TVT) && isa<ConstantSDNode>(Idx)) {
4423 unsigned NumLoElts = 1 << Log2_32(NumElems-1);
4424 ConstantSDNode *CIdx = cast<ConstantSDNode>(Idx);
4426 SplitVectorOp(Vec, Lo, Hi);
4427 if (CIdx->getValue() < NumLoElts) {
4431 Idx = DAG.getConstant(CIdx->getValue() - NumLoElts,
4432 Idx.getValueType());
4435 // It's now an extract from the appropriate high or low part. Recurse.
4436 Op = DAG.UpdateNodeOperands(Op, Vec, Idx);
4437 Op = ExpandEXTRACT_VECTOR_ELT(Op);
4439 // Store the value to a temporary stack slot, then LOAD the scalar
4440 // element back out.
4441 SDOperand StackPtr = DAG.CreateStackTemporary(Vec.getValueType());
4442 SDOperand Ch = DAG.getStore(DAG.getEntryNode(), Vec, StackPtr, NULL, 0);
4444 // Add the offset to the index.
4445 unsigned EltSize = MVT::getSizeInBits(Op.getValueType())/8;
4446 Idx = DAG.getNode(ISD::MUL, Idx.getValueType(), Idx,
4447 DAG.getConstant(EltSize, Idx.getValueType()));
4449 if (MVT::getSizeInBits(Idx.getValueType()) >
4450 MVT::getSizeInBits(TLI.getPointerTy()))
4451 Idx = DAG.getNode(ISD::TRUNCATE, TLI.getPointerTy(), Idx);
4453 Idx = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(), Idx);
4455 StackPtr = DAG.getNode(ISD::ADD, Idx.getValueType(), Idx, StackPtr);
4457 Op = DAG.getLoad(Op.getValueType(), Ch, StackPtr, NULL, 0);
4462 /// ExpandEXTRACT_SUBVECTOR - Expand a EXTRACT_SUBVECTOR operation. For now
4463 /// we assume the operation can be split if it is not already legal.
4464 SDOperand SelectionDAGLegalize::ExpandEXTRACT_SUBVECTOR(SDOperand Op) {
4465 // We know that operand #0 is the Vec vector. For now we assume the index
4466 // is a constant and that the extracted result is a supported hardware type.
4467 SDOperand Vec = Op.getOperand(0);
4468 SDOperand Idx = LegalizeOp(Op.getOperand(1));
4470 unsigned NumElems = MVT::getVectorNumElements(Vec.getValueType());
4472 if (NumElems == MVT::getVectorNumElements(Op.getValueType())) {
4473 // This must be an access of the desired vector length. Return it.
4477 ConstantSDNode *CIdx = cast<ConstantSDNode>(Idx);
4479 SplitVectorOp(Vec, Lo, Hi);
4480 if (CIdx->getValue() < NumElems/2) {
4484 Idx = DAG.getConstant(CIdx->getValue() - NumElems/2, Idx.getValueType());
4487 // It's now an extract from the appropriate high or low part. Recurse.
4488 Op = DAG.UpdateNodeOperands(Op, Vec, Idx);
4489 return ExpandEXTRACT_SUBVECTOR(Op);
4492 /// LegalizeSetCCOperands - Attempts to create a legal LHS and RHS for a SETCC
4493 /// with condition CC on the current target. This usually involves legalizing
4494 /// or promoting the arguments. In the case where LHS and RHS must be expanded,
4495 /// there may be no choice but to create a new SetCC node to represent the
4496 /// legalized value of setcc lhs, rhs. In this case, the value is returned in
4497 /// LHS, and the SDOperand returned in RHS has a nil SDNode value.
4498 void SelectionDAGLegalize::LegalizeSetCCOperands(SDOperand &LHS,
4501 SDOperand Tmp1, Tmp2, Tmp3, Result;
4503 switch (getTypeAction(LHS.getValueType())) {
4505 Tmp1 = LegalizeOp(LHS); // LHS
4506 Tmp2 = LegalizeOp(RHS); // RHS
4509 Tmp1 = PromoteOp(LHS); // LHS
4510 Tmp2 = PromoteOp(RHS); // RHS
4512 // If this is an FP compare, the operands have already been extended.
4513 if (MVT::isInteger(LHS.getValueType())) {
4514 MVT::ValueType VT = LHS.getValueType();
4515 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT);
4517 // Otherwise, we have to insert explicit sign or zero extends. Note
4518 // that we could insert sign extends for ALL conditions, but zero extend
4519 // is cheaper on many machines (an AND instead of two shifts), so prefer
4521 switch (cast<CondCodeSDNode>(CC)->get()) {
4522 default: assert(0 && "Unknown integer comparison!");
4529 // ALL of these operations will work if we either sign or zero extend
4530 // the operands (including the unsigned comparisons!). Zero extend is
4531 // usually a simpler/cheaper operation, so prefer it.
4532 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT);
4533 Tmp2 = DAG.getZeroExtendInReg(Tmp2, VT);
4539 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1,
4540 DAG.getValueType(VT));
4541 Tmp2 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp2,
4542 DAG.getValueType(VT));
4548 MVT::ValueType VT = LHS.getValueType();
4549 if (VT == MVT::f32 || VT == MVT::f64) {
4550 // Expand into one or more soft-fp libcall(s).
4551 RTLIB::Libcall LC1, LC2 = RTLIB::UNKNOWN_LIBCALL;
4552 switch (cast<CondCodeSDNode>(CC)->get()) {
4555 LC1 = (VT == MVT::f32) ? RTLIB::OEQ_F32 : RTLIB::OEQ_F64;
4559 LC1 = (VT == MVT::f32) ? RTLIB::UNE_F32 : RTLIB::UNE_F64;
4563 LC1 = (VT == MVT::f32) ? RTLIB::OGE_F32 : RTLIB::OGE_F64;
4567 LC1 = (VT == MVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64;
4571 LC1 = (VT == MVT::f32) ? RTLIB::OLE_F32 : RTLIB::OLE_F64;
4575 LC1 = (VT == MVT::f32) ? RTLIB::OGT_F32 : RTLIB::OGT_F64;
4578 LC1 = (VT == MVT::f32) ? RTLIB::UO_F32 : RTLIB::UO_F64;
4581 LC1 = (VT == MVT::f32) ? RTLIB::O_F32 : RTLIB::O_F64;
4584 LC1 = (VT == MVT::f32) ? RTLIB::UO_F32 : RTLIB::UO_F64;
4585 switch (cast<CondCodeSDNode>(CC)->get()) {
4587 // SETONE = SETOLT | SETOGT
4588 LC1 = (VT == MVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64;
4591 LC2 = (VT == MVT::f32) ? RTLIB::OGT_F32 : RTLIB::OGT_F64;
4594 LC2 = (VT == MVT::f32) ? RTLIB::OGE_F32 : RTLIB::OGE_F64;
4597 LC2 = (VT == MVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64;
4600 LC2 = (VT == MVT::f32) ? RTLIB::OLE_F32 : RTLIB::OLE_F64;
4603 LC2 = (VT == MVT::f32) ? RTLIB::OEQ_F32 : RTLIB::OEQ_F64;
4605 default: assert(0 && "Unsupported FP setcc!");
4610 Tmp1 = ExpandLibCall(TLI.getLibcallName(LC1),
4611 DAG.getNode(ISD::MERGE_VALUES, VT, LHS, RHS).Val,
4612 false /*sign irrelevant*/, Dummy);
4613 Tmp2 = DAG.getConstant(0, MVT::i32);
4614 CC = DAG.getCondCode(TLI.getCmpLibcallCC(LC1));
4615 if (LC2 != RTLIB::UNKNOWN_LIBCALL) {
4616 Tmp1 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(), Tmp1, Tmp2, CC);
4617 LHS = ExpandLibCall(TLI.getLibcallName(LC2),
4618 DAG.getNode(ISD::MERGE_VALUES, VT, LHS, RHS).Val,
4619 false /*sign irrelevant*/, Dummy);
4620 Tmp2 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(), LHS, Tmp2,
4621 DAG.getCondCode(TLI.getCmpLibcallCC(LC2)));
4622 Tmp1 = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp2);
4630 SDOperand LHSLo, LHSHi, RHSLo, RHSHi;
4631 ExpandOp(LHS, LHSLo, LHSHi);
4632 ExpandOp(RHS, RHSLo, RHSHi);
4633 ISD::CondCode CCCode = cast<CondCodeSDNode>(CC)->get();
4635 if (VT==MVT::ppcf128) {
4636 // FIXME: This generated code sucks. We want to generate
4637 // FCMP crN, hi1, hi2
4639 // FCMP crN, lo1, lo2
4640 // The following can be improved, but not that much.
4641 Tmp1 = DAG.getSetCC(TLI.getSetCCResultTy(), LHSHi, RHSHi, ISD::SETEQ);
4642 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), LHSLo, RHSLo, CCCode);
4643 Tmp3 = DAG.getNode(ISD::AND, Tmp1.getValueType(), Tmp1, Tmp2);
4644 Tmp1 = DAG.getSetCC(TLI.getSetCCResultTy(), LHSHi, RHSHi, ISD::SETNE);
4645 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), LHSHi, RHSHi, CCCode);
4646 Tmp1 = DAG.getNode(ISD::AND, Tmp1.getValueType(), Tmp1, Tmp2);
4647 Tmp1 = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp3);
4656 if (ConstantSDNode *RHSCST = dyn_cast<ConstantSDNode>(RHSLo))
4657 if (RHSCST->isAllOnesValue()) {
4658 // Comparison to -1.
4659 Tmp1 = DAG.getNode(ISD::AND, LHSLo.getValueType(), LHSLo, LHSHi);
4664 Tmp1 = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSLo, RHSLo);
4665 Tmp2 = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSHi, RHSHi);
4666 Tmp1 = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp2);
4667 Tmp2 = DAG.getConstant(0, Tmp1.getValueType());
4670 // If this is a comparison of the sign bit, just look at the top part.
4672 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(RHS))
4673 if ((cast<CondCodeSDNode>(CC)->get() == ISD::SETLT &&
4674 CST->getValue() == 0) || // X < 0
4675 (cast<CondCodeSDNode>(CC)->get() == ISD::SETGT &&
4676 CST->isAllOnesValue())) { // X > -1
4682 // FIXME: This generated code sucks.
4683 ISD::CondCode LowCC;
4685 default: assert(0 && "Unknown integer setcc!");
4687 case ISD::SETULT: LowCC = ISD::SETULT; break;
4689 case ISD::SETUGT: LowCC = ISD::SETUGT; break;
4691 case ISD::SETULE: LowCC = ISD::SETULE; break;
4693 case ISD::SETUGE: LowCC = ISD::SETUGE; break;
4696 // Tmp1 = lo(op1) < lo(op2) // Always unsigned comparison
4697 // Tmp2 = hi(op1) < hi(op2) // Signedness depends on operands
4698 // dest = hi(op1) == hi(op2) ? Tmp1 : Tmp2;
4700 // NOTE: on targets without efficient SELECT of bools, we can always use
4701 // this identity: (B1 ? B2 : B3) --> (B1 & B2)|(!B1&B3)
4702 TargetLowering::DAGCombinerInfo DagCombineInfo(DAG, false, true, NULL);
4703 Tmp1 = TLI.SimplifySetCC(TLI.getSetCCResultTy(), LHSLo, RHSLo, LowCC,
4704 false, DagCombineInfo);
4706 Tmp1 = DAG.getSetCC(TLI.getSetCCResultTy(), LHSLo, RHSLo, LowCC);
4707 Tmp2 = TLI.SimplifySetCC(TLI.getSetCCResultTy(), LHSHi, RHSHi,
4708 CCCode, false, DagCombineInfo);
4710 Tmp2 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(), LHSHi, RHSHi,CC);
4712 ConstantSDNode *Tmp1C = dyn_cast<ConstantSDNode>(Tmp1.Val);
4713 ConstantSDNode *Tmp2C = dyn_cast<ConstantSDNode>(Tmp2.Val);
4714 if ((Tmp1C && Tmp1C->getValue() == 0) ||
4715 (Tmp2C && Tmp2C->getValue() == 0 &&
4716 (CCCode == ISD::SETLE || CCCode == ISD::SETGE ||
4717 CCCode == ISD::SETUGE || CCCode == ISD::SETULE)) ||
4718 (Tmp2C && Tmp2C->getValue() == 1 &&
4719 (CCCode == ISD::SETLT || CCCode == ISD::SETGT ||
4720 CCCode == ISD::SETUGT || CCCode == ISD::SETULT))) {
4721 // low part is known false, returns high part.
4722 // For LE / GE, if high part is known false, ignore the low part.
4723 // For LT / GT, if high part is known true, ignore the low part.
4727 Result = TLI.SimplifySetCC(TLI.getSetCCResultTy(), LHSHi, RHSHi,
4728 ISD::SETEQ, false, DagCombineInfo);
4730 Result=DAG.getSetCC(TLI.getSetCCResultTy(), LHSHi, RHSHi, ISD::SETEQ);
4731 Result = LegalizeOp(DAG.getNode(ISD::SELECT, Tmp1.getValueType(),
4732 Result, Tmp1, Tmp2));
4743 /// EmitStackConvert - Emit a store/load combination to the stack. This stores
4744 /// SrcOp to a stack slot of type SlotVT, truncating it if needed. It then does
4745 /// a load from the stack slot to DestVT, extending it if needed.
4746 /// The resultant code need not be legal.
4747 SDOperand SelectionDAGLegalize::EmitStackConvert(SDOperand SrcOp,
4748 MVT::ValueType SlotVT,
4749 MVT::ValueType DestVT) {
4750 // Create the stack frame object.
4751 SDOperand FIPtr = DAG.CreateStackTemporary(SlotVT);
4753 unsigned SrcSize = MVT::getSizeInBits(SrcOp.getValueType());
4754 unsigned SlotSize = MVT::getSizeInBits(SlotVT);
4755 unsigned DestSize = MVT::getSizeInBits(DestVT);
4757 // Emit a store to the stack slot. Use a truncstore if the input value is
4758 // later than DestVT.
4760 if (SrcSize > SlotSize)
4761 Store = DAG.getTruncStore(DAG.getEntryNode(), SrcOp, FIPtr, NULL, 0,SlotVT);
4763 assert(SrcSize == SlotSize && "Invalid store");
4764 Store = DAG.getStore(DAG.getEntryNode(), SrcOp, FIPtr, NULL, 0);
4767 // Result is a load from the stack slot.
4768 if (SlotSize == DestSize)
4769 return DAG.getLoad(DestVT, Store, FIPtr, NULL, 0);
4771 assert(SlotSize < DestSize && "Unknown extension!");
4772 return DAG.getExtLoad(ISD::EXTLOAD, DestVT, Store, FIPtr, NULL, 0, SlotVT);
4775 SDOperand SelectionDAGLegalize::ExpandSCALAR_TO_VECTOR(SDNode *Node) {
4776 // Create a vector sized/aligned stack slot, store the value to element #0,
4777 // then load the whole vector back out.
4778 SDOperand StackPtr = DAG.CreateStackTemporary(Node->getValueType(0));
4779 SDOperand Ch = DAG.getStore(DAG.getEntryNode(), Node->getOperand(0), StackPtr,
4781 return DAG.getLoad(Node->getValueType(0), Ch, StackPtr, NULL, 0);
4785 /// ExpandBUILD_VECTOR - Expand a BUILD_VECTOR node on targets that don't
4786 /// support the operation, but do support the resultant vector type.
4787 SDOperand SelectionDAGLegalize::ExpandBUILD_VECTOR(SDNode *Node) {
4789 // If the only non-undef value is the low element, turn this into a
4790 // SCALAR_TO_VECTOR node. If this is { X, X, X, X }, determine X.
4791 unsigned NumElems = Node->getNumOperands();
4792 bool isOnlyLowElement = true;
4793 SDOperand SplatValue = Node->getOperand(0);
4794 std::map<SDOperand, std::vector<unsigned> > Values;
4795 Values[SplatValue].push_back(0);
4796 bool isConstant = true;
4797 if (!isa<ConstantFPSDNode>(SplatValue) && !isa<ConstantSDNode>(SplatValue) &&
4798 SplatValue.getOpcode() != ISD::UNDEF)
4801 for (unsigned i = 1; i < NumElems; ++i) {
4802 SDOperand V = Node->getOperand(i);
4803 Values[V].push_back(i);
4804 if (V.getOpcode() != ISD::UNDEF)
4805 isOnlyLowElement = false;
4806 if (SplatValue != V)
4807 SplatValue = SDOperand(0,0);
4809 // If this isn't a constant element or an undef, we can't use a constant
4811 if (!isa<ConstantFPSDNode>(V) && !isa<ConstantSDNode>(V) &&
4812 V.getOpcode() != ISD::UNDEF)
4816 if (isOnlyLowElement) {
4817 // If the low element is an undef too, then this whole things is an undef.
4818 if (Node->getOperand(0).getOpcode() == ISD::UNDEF)
4819 return DAG.getNode(ISD::UNDEF, Node->getValueType(0));
4820 // Otherwise, turn this into a scalar_to_vector node.
4821 return DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0),
4822 Node->getOperand(0));
4825 // If all elements are constants, create a load from the constant pool.
4827 MVT::ValueType VT = Node->getValueType(0);
4829 MVT::getTypeForValueType(Node->getOperand(0).getValueType());
4830 std::vector<Constant*> CV;
4831 for (unsigned i = 0, e = NumElems; i != e; ++i) {
4832 if (ConstantFPSDNode *V =
4833 dyn_cast<ConstantFPSDNode>(Node->getOperand(i))) {
4834 CV.push_back(ConstantFP::get(OpNTy, V->getValueAPF()));
4835 } else if (ConstantSDNode *V =
4836 dyn_cast<ConstantSDNode>(Node->getOperand(i))) {
4837 CV.push_back(ConstantInt::get(OpNTy, V->getValue()));
4839 assert(Node->getOperand(i).getOpcode() == ISD::UNDEF);
4840 CV.push_back(UndefValue::get(OpNTy));
4843 Constant *CP = ConstantVector::get(CV);
4844 SDOperand CPIdx = DAG.getConstantPool(CP, TLI.getPointerTy());
4845 return DAG.getLoad(VT, DAG.getEntryNode(), CPIdx, NULL, 0);
4848 if (SplatValue.Val) { // Splat of one value?
4849 // Build the shuffle constant vector: <0, 0, 0, 0>
4850 MVT::ValueType MaskVT =
4851 MVT::getIntVectorWithNumElements(NumElems);
4852 SDOperand Zero = DAG.getConstant(0, MVT::getVectorElementType(MaskVT));
4853 std::vector<SDOperand> ZeroVec(NumElems, Zero);
4854 SDOperand SplatMask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
4855 &ZeroVec[0], ZeroVec.size());
4857 // If the target supports VECTOR_SHUFFLE and this shuffle mask, use it.
4858 if (isShuffleLegal(Node->getValueType(0), SplatMask)) {
4859 // Get the splatted value into the low element of a vector register.
4860 SDOperand LowValVec =
4861 DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0), SplatValue);
4863 // Return shuffle(LowValVec, undef, <0,0,0,0>)
4864 return DAG.getNode(ISD::VECTOR_SHUFFLE, Node->getValueType(0), LowValVec,
4865 DAG.getNode(ISD::UNDEF, Node->getValueType(0)),
4870 // If there are only two unique elements, we may be able to turn this into a
4872 if (Values.size() == 2) {
4873 // Build the shuffle constant vector: e.g. <0, 4, 0, 4>
4874 MVT::ValueType MaskVT =
4875 MVT::getIntVectorWithNumElements(NumElems);
4876 std::vector<SDOperand> MaskVec(NumElems);
4878 for (std::map<SDOperand,std::vector<unsigned> >::iterator I=Values.begin(),
4879 E = Values.end(); I != E; ++I) {
4880 for (std::vector<unsigned>::iterator II = I->second.begin(),
4881 EE = I->second.end(); II != EE; ++II)
4882 MaskVec[*II] = DAG.getConstant(i, MVT::getVectorElementType(MaskVT));
4885 SDOperand ShuffleMask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
4886 &MaskVec[0], MaskVec.size());
4888 // If the target supports VECTOR_SHUFFLE and this shuffle mask, use it.
4889 if (TLI.isOperationLegal(ISD::SCALAR_TO_VECTOR, Node->getValueType(0)) &&
4890 isShuffleLegal(Node->getValueType(0), ShuffleMask)) {
4891 SmallVector<SDOperand, 8> Ops;
4892 for(std::map<SDOperand,std::vector<unsigned> >::iterator I=Values.begin(),
4893 E = Values.end(); I != E; ++I) {
4894 SDOperand Op = DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0),
4898 Ops.push_back(ShuffleMask);
4900 // Return shuffle(LoValVec, HiValVec, <0,1,0,1>)
4901 return DAG.getNode(ISD::VECTOR_SHUFFLE, Node->getValueType(0),
4902 &Ops[0], Ops.size());
4906 // Otherwise, we can't handle this case efficiently. Allocate a sufficiently
4907 // aligned object on the stack, store each element into it, then load
4908 // the result as a vector.
4909 MVT::ValueType VT = Node->getValueType(0);
4910 // Create the stack frame object.
4911 SDOperand FIPtr = DAG.CreateStackTemporary(VT);
4913 // Emit a store of each element to the stack slot.
4914 SmallVector<SDOperand, 8> Stores;
4915 unsigned TypeByteSize =
4916 MVT::getSizeInBits(Node->getOperand(0).getValueType())/8;
4917 // Store (in the right endianness) the elements to memory.
4918 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
4919 // Ignore undef elements.
4920 if (Node->getOperand(i).getOpcode() == ISD::UNDEF) continue;
4922 unsigned Offset = TypeByteSize*i;
4924 SDOperand Idx = DAG.getConstant(Offset, FIPtr.getValueType());
4925 Idx = DAG.getNode(ISD::ADD, FIPtr.getValueType(), FIPtr, Idx);
4927 Stores.push_back(DAG.getStore(DAG.getEntryNode(), Node->getOperand(i), Idx,
4931 SDOperand StoreChain;
4932 if (!Stores.empty()) // Not all undef elements?
4933 StoreChain = DAG.getNode(ISD::TokenFactor, MVT::Other,
4934 &Stores[0], Stores.size());
4936 StoreChain = DAG.getEntryNode();
4938 // Result is a load from the stack slot.
4939 return DAG.getLoad(VT, StoreChain, FIPtr, NULL, 0);
4942 void SelectionDAGLegalize::ExpandShiftParts(unsigned NodeOp,
4943 SDOperand Op, SDOperand Amt,
4944 SDOperand &Lo, SDOperand &Hi) {
4945 // Expand the subcomponents.
4946 SDOperand LHSL, LHSH;
4947 ExpandOp(Op, LHSL, LHSH);
4949 SDOperand Ops[] = { LHSL, LHSH, Amt };
4950 MVT::ValueType VT = LHSL.getValueType();
4951 Lo = DAG.getNode(NodeOp, DAG.getNodeValueTypes(VT, VT), 2, Ops, 3);
4952 Hi = Lo.getValue(1);
4956 /// ExpandShift - Try to find a clever way to expand this shift operation out to
4957 /// smaller elements. If we can't find a way that is more efficient than a
4958 /// libcall on this target, return false. Otherwise, return true with the
4959 /// low-parts expanded into Lo and Hi.
4960 bool SelectionDAGLegalize::ExpandShift(unsigned Opc, SDOperand Op,SDOperand Amt,
4961 SDOperand &Lo, SDOperand &Hi) {
4962 assert((Opc == ISD::SHL || Opc == ISD::SRA || Opc == ISD::SRL) &&
4963 "This is not a shift!");
4965 MVT::ValueType NVT = TLI.getTypeToTransformTo(Op.getValueType());
4966 SDOperand ShAmt = LegalizeOp(Amt);
4967 MVT::ValueType ShTy = ShAmt.getValueType();
4968 unsigned VTBits = MVT::getSizeInBits(Op.getValueType());
4969 unsigned NVTBits = MVT::getSizeInBits(NVT);
4971 // Handle the case when Amt is an immediate.
4972 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Amt.Val)) {
4973 unsigned Cst = CN->getValue();
4974 // Expand the incoming operand to be shifted, so that we have its parts
4976 ExpandOp(Op, InL, InH);
4980 Lo = DAG.getConstant(0, NVT);
4981 Hi = DAG.getConstant(0, NVT);
4982 } else if (Cst > NVTBits) {
4983 Lo = DAG.getConstant(0, NVT);
4984 Hi = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Cst-NVTBits,ShTy));
4985 } else if (Cst == NVTBits) {
4986 Lo = DAG.getConstant(0, NVT);
4989 Lo = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Cst, ShTy));
4990 Hi = DAG.getNode(ISD::OR, NVT,
4991 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(Cst, ShTy)),
4992 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(NVTBits-Cst, ShTy)));
4997 Lo = DAG.getConstant(0, NVT);
4998 Hi = DAG.getConstant(0, NVT);
4999 } else if (Cst > NVTBits) {
5000 Lo = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Cst-NVTBits,ShTy));
5001 Hi = DAG.getConstant(0, NVT);
5002 } else if (Cst == NVTBits) {
5004 Hi = DAG.getConstant(0, NVT);
5006 Lo = DAG.getNode(ISD::OR, NVT,
5007 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(Cst, ShTy)),
5008 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(NVTBits-Cst, ShTy)));
5009 Hi = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Cst, ShTy));
5014 Hi = Lo = DAG.getNode(ISD::SRA, NVT, InH,
5015 DAG.getConstant(NVTBits-1, ShTy));
5016 } else if (Cst > NVTBits) {
5017 Lo = DAG.getNode(ISD::SRA, NVT, InH,
5018 DAG.getConstant(Cst-NVTBits, ShTy));
5019 Hi = DAG.getNode(ISD::SRA, NVT, InH,
5020 DAG.getConstant(NVTBits-1, ShTy));
5021 } else if (Cst == NVTBits) {
5023 Hi = DAG.getNode(ISD::SRA, NVT, InH,
5024 DAG.getConstant(NVTBits-1, ShTy));
5026 Lo = DAG.getNode(ISD::OR, NVT,
5027 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(Cst, ShTy)),
5028 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(NVTBits-Cst, ShTy)));
5029 Hi = DAG.getNode(ISD::SRA, NVT, InH, DAG.getConstant(Cst, ShTy));
5035 // Okay, the shift amount isn't constant. However, if we can tell that it is
5036 // >= 32 or < 32, we can still simplify it, without knowing the actual value.
5037 uint64_t Mask = NVTBits, KnownZero, KnownOne;
5038 DAG.ComputeMaskedBits(Amt, Mask, KnownZero, KnownOne);
5040 // If we know that the high bit of the shift amount is one, then we can do
5041 // this as a couple of simple shifts.
5042 if (KnownOne & Mask) {
5043 // Mask out the high bit, which we know is set.
5044 Amt = DAG.getNode(ISD::AND, Amt.getValueType(), Amt,
5045 DAG.getConstant(NVTBits-1, Amt.getValueType()));
5047 // Expand the incoming operand to be shifted, so that we have its parts
5049 ExpandOp(Op, InL, InH);
5052 Lo = DAG.getConstant(0, NVT); // Low part is zero.
5053 Hi = DAG.getNode(ISD::SHL, NVT, InL, Amt); // High part from Lo part.
5056 Hi = DAG.getConstant(0, NVT); // Hi part is zero.
5057 Lo = DAG.getNode(ISD::SRL, NVT, InH, Amt); // Lo part from Hi part.
5060 Hi = DAG.getNode(ISD::SRA, NVT, InH, // Sign extend high part.
5061 DAG.getConstant(NVTBits-1, Amt.getValueType()));
5062 Lo = DAG.getNode(ISD::SRA, NVT, InH, Amt); // Lo part from Hi part.
5067 // If we know that the high bit of the shift amount is zero, then we can do
5068 // this as a couple of simple shifts.
5069 if (KnownZero & Mask) {
5071 SDOperand Amt2 = DAG.getNode(ISD::SUB, Amt.getValueType(),
5072 DAG.getConstant(NVTBits, Amt.getValueType()),
5075 // Expand the incoming operand to be shifted, so that we have its parts
5077 ExpandOp(Op, InL, InH);
5080 Lo = DAG.getNode(ISD::SHL, NVT, InL, Amt);
5081 Hi = DAG.getNode(ISD::OR, NVT,
5082 DAG.getNode(ISD::SHL, NVT, InH, Amt),
5083 DAG.getNode(ISD::SRL, NVT, InL, Amt2));
5086 Hi = DAG.getNode(ISD::SRL, NVT, InH, Amt);
5087 Lo = DAG.getNode(ISD::OR, NVT,
5088 DAG.getNode(ISD::SRL, NVT, InL, Amt),
5089 DAG.getNode(ISD::SHL, NVT, InH, Amt2));
5092 Hi = DAG.getNode(ISD::SRA, NVT, InH, Amt);
5093 Lo = DAG.getNode(ISD::OR, NVT,
5094 DAG.getNode(ISD::SRL, NVT, InL, Amt),
5095 DAG.getNode(ISD::SHL, NVT, InH, Amt2));
5104 // ExpandLibCall - Expand a node into a call to a libcall. If the result value
5105 // does not fit into a register, return the lo part and set the hi part to the
5106 // by-reg argument. If it does fit into a single register, return the result
5107 // and leave the Hi part unset.
5108 SDOperand SelectionDAGLegalize::ExpandLibCall(const char *Name, SDNode *Node,
5109 bool isSigned, SDOperand &Hi) {
5110 assert(!IsLegalizingCall && "Cannot overlap legalization of calls!");
5111 // The input chain to this libcall is the entry node of the function.
5112 // Legalizing the call will automatically add the previous call to the
5114 SDOperand InChain = DAG.getEntryNode();
5116 TargetLowering::ArgListTy Args;
5117 TargetLowering::ArgListEntry Entry;
5118 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
5119 MVT::ValueType ArgVT = Node->getOperand(i).getValueType();
5120 const Type *ArgTy = MVT::getTypeForValueType(ArgVT);
5121 Entry.Node = Node->getOperand(i); Entry.Ty = ArgTy;
5122 Entry.isSExt = isSigned;
5123 Args.push_back(Entry);
5125 SDOperand Callee = DAG.getExternalSymbol(Name, TLI.getPointerTy());
5127 // Splice the libcall in wherever FindInputOutputChains tells us to.
5128 const Type *RetTy = MVT::getTypeForValueType(Node->getValueType(0));
5129 std::pair<SDOperand,SDOperand> CallInfo =
5130 TLI.LowerCallTo(InChain, RetTy, isSigned, false, CallingConv::C, false,
5133 // Legalize the call sequence, starting with the chain. This will advance
5134 // the LastCALLSEQ_END to the legalized version of the CALLSEQ_END node that
5135 // was added by LowerCallTo (guaranteeing proper serialization of calls).
5136 LegalizeOp(CallInfo.second);
5138 switch (getTypeAction(CallInfo.first.getValueType())) {
5139 default: assert(0 && "Unknown thing");
5141 Result = CallInfo.first;
5144 ExpandOp(CallInfo.first, Result, Hi);
5151 /// ExpandIntToFP - Expand a [US]INT_TO_FP operation.
5153 SDOperand SelectionDAGLegalize::
5154 ExpandIntToFP(bool isSigned, MVT::ValueType DestTy, SDOperand Source) {
5155 assert(getTypeAction(Source.getValueType()) == Expand &&
5156 "This is not an expansion!");
5157 assert(Source.getValueType() == MVT::i64 && "Only handle expand from i64!");
5160 assert(Source.getValueType() == MVT::i64 &&
5161 "This only works for 64-bit -> FP");
5162 // The 64-bit value loaded will be incorrectly if the 'sign bit' of the
5163 // incoming integer is set. To handle this, we dynamically test to see if
5164 // it is set, and, if so, add a fudge factor.
5166 ExpandOp(Source, Lo, Hi);
5168 // If this is unsigned, and not supported, first perform the conversion to
5169 // signed, then adjust the result if the sign bit is set.
5170 SDOperand SignedConv = ExpandIntToFP(true, DestTy,
5171 DAG.getNode(ISD::BUILD_PAIR, Source.getValueType(), Lo, Hi));
5173 SDOperand SignSet = DAG.getSetCC(TLI.getSetCCResultTy(), Hi,
5174 DAG.getConstant(0, Hi.getValueType()),
5176 SDOperand Zero = DAG.getIntPtrConstant(0), Four = DAG.getIntPtrConstant(4);
5177 SDOperand CstOffset = DAG.getNode(ISD::SELECT, Zero.getValueType(),
5178 SignSet, Four, Zero);
5179 uint64_t FF = 0x5f800000ULL;
5180 if (TLI.isLittleEndian()) FF <<= 32;
5181 static Constant *FudgeFactor = ConstantInt::get(Type::Int64Ty, FF);
5183 SDOperand CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy());
5184 CPIdx = DAG.getNode(ISD::ADD, TLI.getPointerTy(), CPIdx, CstOffset);
5185 SDOperand FudgeInReg;
5186 if (DestTy == MVT::f32)
5187 FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx, NULL, 0);
5188 else if (MVT::getSizeInBits(DestTy) > MVT::getSizeInBits(MVT::f32))
5189 // FIXME: Avoid the extend by construction the right constantpool?
5190 FudgeInReg = DAG.getExtLoad(ISD::EXTLOAD, DestTy, DAG.getEntryNode(),
5191 CPIdx, NULL, 0, MVT::f32);
5193 assert(0 && "Unexpected conversion");
5195 MVT::ValueType SCVT = SignedConv.getValueType();
5196 if (SCVT != DestTy) {
5197 // Destination type needs to be expanded as well. The FADD now we are
5198 // constructing will be expanded into a libcall.
5199 if (MVT::getSizeInBits(SCVT) != MVT::getSizeInBits(DestTy)) {
5200 assert(SCVT == MVT::i32 && DestTy == MVT::f64);
5201 SignedConv = DAG.getNode(ISD::BUILD_PAIR, MVT::i64,
5202 SignedConv, SignedConv.getValue(1));
5204 SignedConv = DAG.getNode(ISD::BIT_CONVERT, DestTy, SignedConv);
5206 return DAG.getNode(ISD::FADD, DestTy, SignedConv, FudgeInReg);
5209 // Check to see if the target has a custom way to lower this. If so, use it.
5210 switch (TLI.getOperationAction(ISD::SINT_TO_FP, Source.getValueType())) {
5211 default: assert(0 && "This action not implemented for this operation!");
5212 case TargetLowering::Legal:
5213 case TargetLowering::Expand:
5214 break; // This case is handled below.
5215 case TargetLowering::Custom: {
5216 SDOperand NV = TLI.LowerOperation(DAG.getNode(ISD::SINT_TO_FP, DestTy,
5219 return LegalizeOp(NV);
5220 break; // The target decided this was legal after all
5224 // Expand the source, then glue it back together for the call. We must expand
5225 // the source in case it is shared (this pass of legalize must traverse it).
5226 SDOperand SrcLo, SrcHi;
5227 ExpandOp(Source, SrcLo, SrcHi);
5228 Source = DAG.getNode(ISD::BUILD_PAIR, Source.getValueType(), SrcLo, SrcHi);
5231 if (DestTy == MVT::f32)
5232 LC = RTLIB::SINTTOFP_I64_F32;
5234 assert(DestTy == MVT::f64 && "Unknown fp value type!");
5235 LC = RTLIB::SINTTOFP_I64_F64;
5238 assert(TLI.getLibcallName(LC) && "Don't know how to expand this SINT_TO_FP!");
5239 Source = DAG.getNode(ISD::SINT_TO_FP, DestTy, Source);
5240 SDOperand UnusedHiPart;
5241 return ExpandLibCall(TLI.getLibcallName(LC), Source.Val, isSigned,
5245 /// ExpandLegalINT_TO_FP - This function is responsible for legalizing a
5246 /// INT_TO_FP operation of the specified operand when the target requests that
5247 /// we expand it. At this point, we know that the result and operand types are
5248 /// legal for the target.
5249 SDOperand SelectionDAGLegalize::ExpandLegalINT_TO_FP(bool isSigned,
5251 MVT::ValueType DestVT) {
5252 if (Op0.getValueType() == MVT::i32) {
5253 // simple 32-bit [signed|unsigned] integer to float/double expansion
5255 // Get the stack frame index of a 8 byte buffer.
5256 SDOperand StackSlot = DAG.CreateStackTemporary(MVT::f64);
5258 // word offset constant for Hi/Lo address computation
5259 SDOperand WordOff = DAG.getConstant(sizeof(int), TLI.getPointerTy());
5260 // set up Hi and Lo (into buffer) address based on endian
5261 SDOperand Hi = StackSlot;
5262 SDOperand Lo = DAG.getNode(ISD::ADD, TLI.getPointerTy(), StackSlot,WordOff);
5263 if (TLI.isLittleEndian())
5266 // if signed map to unsigned space
5267 SDOperand Op0Mapped;
5269 // constant used to invert sign bit (signed to unsigned mapping)
5270 SDOperand SignBit = DAG.getConstant(0x80000000u, MVT::i32);
5271 Op0Mapped = DAG.getNode(ISD::XOR, MVT::i32, Op0, SignBit);
5275 // store the lo of the constructed double - based on integer input
5276 SDOperand Store1 = DAG.getStore(DAG.getEntryNode(),
5277 Op0Mapped, Lo, NULL, 0);
5278 // initial hi portion of constructed double
5279 SDOperand InitialHi = DAG.getConstant(0x43300000u, MVT::i32);
5280 // store the hi of the constructed double - biased exponent
5281 SDOperand Store2=DAG.getStore(Store1, InitialHi, Hi, NULL, 0);
5282 // load the constructed double
5283 SDOperand Load = DAG.getLoad(MVT::f64, Store2, StackSlot, NULL, 0);
5284 // FP constant to bias correct the final result
5285 SDOperand Bias = DAG.getConstantFP(isSigned ?
5286 BitsToDouble(0x4330000080000000ULL)
5287 : BitsToDouble(0x4330000000000000ULL),
5289 // subtract the bias
5290 SDOperand Sub = DAG.getNode(ISD::FSUB, MVT::f64, Load, Bias);
5293 // handle final rounding
5294 if (DestVT == MVT::f64) {
5297 } else if (MVT::getSizeInBits(DestVT) < MVT::getSizeInBits(MVT::f64)) {
5298 Result = DAG.getNode(ISD::FP_ROUND, DestVT, Sub,
5299 DAG.getIntPtrConstant(0));
5300 } else if (MVT::getSizeInBits(DestVT) > MVT::getSizeInBits(MVT::f64)) {
5301 Result = DAG.getNode(ISD::FP_EXTEND, DestVT, Sub);
5305 assert(!isSigned && "Legalize cannot Expand SINT_TO_FP for i64 yet");
5306 SDOperand Tmp1 = DAG.getNode(ISD::SINT_TO_FP, DestVT, Op0);
5308 SDOperand SignSet = DAG.getSetCC(TLI.getSetCCResultTy(), Op0,
5309 DAG.getConstant(0, Op0.getValueType()),
5311 SDOperand Zero = DAG.getIntPtrConstant(0), Four = DAG.getIntPtrConstant(4);
5312 SDOperand CstOffset = DAG.getNode(ISD::SELECT, Zero.getValueType(),
5313 SignSet, Four, Zero);
5315 // If the sign bit of the integer is set, the large number will be treated
5316 // as a negative number. To counteract this, the dynamic code adds an
5317 // offset depending on the data type.
5319 switch (Op0.getValueType()) {
5320 default: assert(0 && "Unsupported integer type!");
5321 case MVT::i8 : FF = 0x43800000ULL; break; // 2^8 (as a float)
5322 case MVT::i16: FF = 0x47800000ULL; break; // 2^16 (as a float)
5323 case MVT::i32: FF = 0x4F800000ULL; break; // 2^32 (as a float)
5324 case MVT::i64: FF = 0x5F800000ULL; break; // 2^64 (as a float)
5326 if (TLI.isLittleEndian()) FF <<= 32;
5327 static Constant *FudgeFactor = ConstantInt::get(Type::Int64Ty, FF);
5329 SDOperand CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy());
5330 CPIdx = DAG.getNode(ISD::ADD, TLI.getPointerTy(), CPIdx, CstOffset);
5331 SDOperand FudgeInReg;
5332 if (DestVT == MVT::f32)
5333 FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx, NULL, 0);
5335 FudgeInReg = LegalizeOp(DAG.getExtLoad(ISD::EXTLOAD, DestVT,
5336 DAG.getEntryNode(), CPIdx,
5337 NULL, 0, MVT::f32));
5340 return DAG.getNode(ISD::FADD, DestVT, Tmp1, FudgeInReg);
5343 /// PromoteLegalINT_TO_FP - This function is responsible for legalizing a
5344 /// *INT_TO_FP operation of the specified operand when the target requests that
5345 /// we promote it. At this point, we know that the result and operand types are
5346 /// legal for the target, and that there is a legal UINT_TO_FP or SINT_TO_FP
5347 /// operation that takes a larger input.
5348 SDOperand SelectionDAGLegalize::PromoteLegalINT_TO_FP(SDOperand LegalOp,
5349 MVT::ValueType DestVT,
5351 // First step, figure out the appropriate *INT_TO_FP operation to use.
5352 MVT::ValueType NewInTy = LegalOp.getValueType();
5354 unsigned OpToUse = 0;
5356 // Scan for the appropriate larger type to use.
5358 NewInTy = (MVT::ValueType)(NewInTy+1);
5359 assert(MVT::isInteger(NewInTy) && "Ran out of possibilities!");
5361 // If the target supports SINT_TO_FP of this type, use it.
5362 switch (TLI.getOperationAction(ISD::SINT_TO_FP, NewInTy)) {
5364 case TargetLowering::Legal:
5365 if (!TLI.isTypeLegal(NewInTy))
5366 break; // Can't use this datatype.
5368 case TargetLowering::Custom:
5369 OpToUse = ISD::SINT_TO_FP;
5373 if (isSigned) continue;
5375 // If the target supports UINT_TO_FP of this type, use it.
5376 switch (TLI.getOperationAction(ISD::UINT_TO_FP, NewInTy)) {
5378 case TargetLowering::Legal:
5379 if (!TLI.isTypeLegal(NewInTy))
5380 break; // Can't use this datatype.
5382 case TargetLowering::Custom:
5383 OpToUse = ISD::UINT_TO_FP;
5388 // Otherwise, try a larger type.
5391 // Okay, we found the operation and type to use. Zero extend our input to the
5392 // desired type then run the operation on it.
5393 return DAG.getNode(OpToUse, DestVT,
5394 DAG.getNode(isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND,
5398 /// PromoteLegalFP_TO_INT - This function is responsible for legalizing a
5399 /// FP_TO_*INT operation of the specified operand when the target requests that
5400 /// we promote it. At this point, we know that the result and operand types are
5401 /// legal for the target, and that there is a legal FP_TO_UINT or FP_TO_SINT
5402 /// operation that returns a larger result.
5403 SDOperand SelectionDAGLegalize::PromoteLegalFP_TO_INT(SDOperand LegalOp,
5404 MVT::ValueType DestVT,
5406 // First step, figure out the appropriate FP_TO*INT operation to use.
5407 MVT::ValueType NewOutTy = DestVT;
5409 unsigned OpToUse = 0;
5411 // Scan for the appropriate larger type to use.
5413 NewOutTy = (MVT::ValueType)(NewOutTy+1);
5414 assert(MVT::isInteger(NewOutTy) && "Ran out of possibilities!");
5416 // If the target supports FP_TO_SINT returning this type, use it.
5417 switch (TLI.getOperationAction(ISD::FP_TO_SINT, NewOutTy)) {
5419 case TargetLowering::Legal:
5420 if (!TLI.isTypeLegal(NewOutTy))
5421 break; // Can't use this datatype.
5423 case TargetLowering::Custom:
5424 OpToUse = ISD::FP_TO_SINT;
5429 // If the target supports FP_TO_UINT of this type, use it.
5430 switch (TLI.getOperationAction(ISD::FP_TO_UINT, NewOutTy)) {
5432 case TargetLowering::Legal:
5433 if (!TLI.isTypeLegal(NewOutTy))
5434 break; // Can't use this datatype.
5436 case TargetLowering::Custom:
5437 OpToUse = ISD::FP_TO_UINT;
5442 // Otherwise, try a larger type.
5446 // Okay, we found the operation and type to use.
5447 SDOperand Operation = DAG.getNode(OpToUse, NewOutTy, LegalOp);
5449 // If the operation produces an invalid type, it must be custom lowered. Use
5450 // the target lowering hooks to expand it. Just keep the low part of the
5451 // expanded operation, we know that we're truncating anyway.
5452 if (getTypeAction(NewOutTy) == Expand) {
5453 Operation = SDOperand(TLI.ExpandOperationResult(Operation.Val, DAG), 0);
5454 assert(Operation.Val && "Didn't return anything");
5457 // Truncate the result of the extended FP_TO_*INT operation to the desired
5459 return DAG.getNode(ISD::TRUNCATE, DestVT, Operation);
5462 /// ExpandBSWAP - Open code the operations for BSWAP of the specified operation.
5464 SDOperand SelectionDAGLegalize::ExpandBSWAP(SDOperand Op) {
5465 MVT::ValueType VT = Op.getValueType();
5466 MVT::ValueType SHVT = TLI.getShiftAmountTy();
5467 SDOperand Tmp1, Tmp2, Tmp3, Tmp4, Tmp5, Tmp6, Tmp7, Tmp8;
5469 default: assert(0 && "Unhandled Expand type in BSWAP!"); abort();
5471 Tmp2 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT));
5472 Tmp1 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(8, SHVT));
5473 return DAG.getNode(ISD::OR, VT, Tmp1, Tmp2);
5475 Tmp4 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(24, SHVT));
5476 Tmp3 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT));
5477 Tmp2 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(8, SHVT));
5478 Tmp1 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(24, SHVT));
5479 Tmp3 = DAG.getNode(ISD::AND, VT, Tmp3, DAG.getConstant(0xFF0000, VT));
5480 Tmp2 = DAG.getNode(ISD::AND, VT, Tmp2, DAG.getConstant(0xFF00, VT));
5481 Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp3);
5482 Tmp2 = DAG.getNode(ISD::OR, VT, Tmp2, Tmp1);
5483 return DAG.getNode(ISD::OR, VT, Tmp4, Tmp2);
5485 Tmp8 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(56, SHVT));
5486 Tmp7 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(40, SHVT));
5487 Tmp6 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(24, SHVT));
5488 Tmp5 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT));
5489 Tmp4 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(8, SHVT));
5490 Tmp3 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(24, SHVT));
5491 Tmp2 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(40, SHVT));
5492 Tmp1 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(56, SHVT));
5493 Tmp7 = DAG.getNode(ISD::AND, VT, Tmp7, DAG.getConstant(255ULL<<48, VT));
5494 Tmp6 = DAG.getNode(ISD::AND, VT, Tmp6, DAG.getConstant(255ULL<<40, VT));
5495 Tmp5 = DAG.getNode(ISD::AND, VT, Tmp5, DAG.getConstant(255ULL<<32, VT));
5496 Tmp4 = DAG.getNode(ISD::AND, VT, Tmp4, DAG.getConstant(255ULL<<24, VT));
5497 Tmp3 = DAG.getNode(ISD::AND, VT, Tmp3, DAG.getConstant(255ULL<<16, VT));
5498 Tmp2 = DAG.getNode(ISD::AND, VT, Tmp2, DAG.getConstant(255ULL<<8 , VT));
5499 Tmp8 = DAG.getNode(ISD::OR, VT, Tmp8, Tmp7);
5500 Tmp6 = DAG.getNode(ISD::OR, VT, Tmp6, Tmp5);
5501 Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp3);
5502 Tmp2 = DAG.getNode(ISD::OR, VT, Tmp2, Tmp1);
5503 Tmp8 = DAG.getNode(ISD::OR, VT, Tmp8, Tmp6);
5504 Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp2);
5505 return DAG.getNode(ISD::OR, VT, Tmp8, Tmp4);
5509 /// ExpandBitCount - Expand the specified bitcount instruction into operations.
5511 SDOperand SelectionDAGLegalize::ExpandBitCount(unsigned Opc, SDOperand Op) {
5513 default: assert(0 && "Cannot expand this yet!");
5515 static const uint64_t mask[6] = {
5516 0x5555555555555555ULL, 0x3333333333333333ULL,
5517 0x0F0F0F0F0F0F0F0FULL, 0x00FF00FF00FF00FFULL,
5518 0x0000FFFF0000FFFFULL, 0x00000000FFFFFFFFULL
5520 MVT::ValueType VT = Op.getValueType();
5521 MVT::ValueType ShVT = TLI.getShiftAmountTy();
5522 unsigned len = MVT::getSizeInBits(VT);
5523 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) {
5524 //x = (x & mask[i][len/8]) + (x >> (1 << i) & mask[i][len/8])
5525 SDOperand Tmp2 = DAG.getConstant(mask[i], VT);
5526 SDOperand Tmp3 = DAG.getConstant(1ULL << i, ShVT);
5527 Op = DAG.getNode(ISD::ADD, VT, DAG.getNode(ISD::AND, VT, Op, Tmp2),
5528 DAG.getNode(ISD::AND, VT,
5529 DAG.getNode(ISD::SRL, VT, Op, Tmp3),Tmp2));
5534 // for now, we do this:
5535 // x = x | (x >> 1);
5536 // x = x | (x >> 2);
5538 // x = x | (x >>16);
5539 // x = x | (x >>32); // for 64-bit input
5540 // return popcount(~x);
5542 // but see also: http://www.hackersdelight.org/HDcode/nlz.cc
5543 MVT::ValueType VT = Op.getValueType();
5544 MVT::ValueType ShVT = TLI.getShiftAmountTy();
5545 unsigned len = MVT::getSizeInBits(VT);
5546 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) {
5547 SDOperand Tmp3 = DAG.getConstant(1ULL << i, ShVT);
5548 Op = DAG.getNode(ISD::OR, VT, Op, DAG.getNode(ISD::SRL, VT, Op, Tmp3));
5550 Op = DAG.getNode(ISD::XOR, VT, Op, DAG.getConstant(~0ULL, VT));
5551 return DAG.getNode(ISD::CTPOP, VT, Op);
5554 // for now, we use: { return popcount(~x & (x - 1)); }
5555 // unless the target has ctlz but not ctpop, in which case we use:
5556 // { return 32 - nlz(~x & (x-1)); }
5557 // see also http://www.hackersdelight.org/HDcode/ntz.cc
5558 MVT::ValueType VT = Op.getValueType();
5559 SDOperand Tmp2 = DAG.getConstant(~0ULL, VT);
5560 SDOperand Tmp3 = DAG.getNode(ISD::AND, VT,
5561 DAG.getNode(ISD::XOR, VT, Op, Tmp2),
5562 DAG.getNode(ISD::SUB, VT, Op, DAG.getConstant(1, VT)));
5563 // If ISD::CTLZ is legal and CTPOP isn't, then do that instead.
5564 if (!TLI.isOperationLegal(ISD::CTPOP, VT) &&
5565 TLI.isOperationLegal(ISD::CTLZ, VT))
5566 return DAG.getNode(ISD::SUB, VT,
5567 DAG.getConstant(MVT::getSizeInBits(VT), VT),
5568 DAG.getNode(ISD::CTLZ, VT, Tmp3));
5569 return DAG.getNode(ISD::CTPOP, VT, Tmp3);
5574 /// ExpandOp - Expand the specified SDOperand into its two component pieces
5575 /// Lo&Hi. Note that the Op MUST be an expanded type. As a result of this, the
5576 /// LegalizeNodes map is filled in for any results that are not expanded, the
5577 /// ExpandedNodes map is filled in for any results that are expanded, and the
5578 /// Lo/Hi values are returned.
5579 void SelectionDAGLegalize::ExpandOp(SDOperand Op, SDOperand &Lo, SDOperand &Hi){
5580 MVT::ValueType VT = Op.getValueType();
5581 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT);
5582 SDNode *Node = Op.Val;
5583 assert(getTypeAction(VT) == Expand && "Not an expanded type!");
5584 assert(((MVT::isInteger(NVT) && NVT < VT) || MVT::isFloatingPoint(VT) ||
5585 MVT::isVector(VT)) &&
5586 "Cannot expand to FP value or to larger int value!");
5588 // See if we already expanded it.
5589 DenseMap<SDOperand, std::pair<SDOperand, SDOperand> >::iterator I
5590 = ExpandedNodes.find(Op);
5591 if (I != ExpandedNodes.end()) {
5592 Lo = I->second.first;
5593 Hi = I->second.second;
5597 switch (Node->getOpcode()) {
5598 case ISD::CopyFromReg:
5599 assert(0 && "CopyFromReg must be legal!");
5600 case ISD::FP_ROUND_INREG:
5601 if (VT == MVT::ppcf128 &&
5602 TLI.getOperationAction(ISD::FP_ROUND_INREG, VT) ==
5603 TargetLowering::Custom) {
5604 SDOperand SrcLo, SrcHi, Src;
5605 ExpandOp(Op.getOperand(0), SrcLo, SrcHi);
5606 Src = DAG.getNode(ISD::BUILD_PAIR, VT, SrcLo, SrcHi);
5607 SDOperand Result = TLI.LowerOperation(
5608 DAG.getNode(ISD::FP_ROUND_INREG, VT, Src, Op.getOperand(1)), DAG);
5609 assert(Result.Val->getOpcode() == ISD::BUILD_PAIR);
5610 Lo = Result.Val->getOperand(0);
5611 Hi = Result.Val->getOperand(1);
5617 cerr << "NODE: "; Node->dump(&DAG); cerr << "\n";
5619 assert(0 && "Do not know how to expand this operator!");
5621 case ISD::EXTRACT_VECTOR_ELT:
5622 assert(VT==MVT::i64 && "Do not know how to expand this operator!");
5623 // ExpandEXTRACT_VECTOR_ELT tolerates invalid result types.
5624 Lo = ExpandEXTRACT_VECTOR_ELT(Op);
5625 return ExpandOp(Lo, Lo, Hi);
5627 NVT = TLI.getTypeToExpandTo(VT);
5628 Lo = DAG.getNode(ISD::UNDEF, NVT);
5629 Hi = DAG.getNode(ISD::UNDEF, NVT);
5631 case ISD::Constant: {
5632 uint64_t Cst = cast<ConstantSDNode>(Node)->getValue();
5633 Lo = DAG.getConstant(Cst, NVT);
5634 Hi = DAG.getConstant(Cst >> MVT::getSizeInBits(NVT), NVT);
5637 case ISD::ConstantFP: {
5638 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node);
5639 if (CFP->getValueType(0) == MVT::ppcf128) {
5640 APInt api = CFP->getValueAPF().convertToAPInt();
5641 Lo = DAG.getConstantFP(APFloat(APInt(64, 1, &api.getRawData()[1])),
5643 Hi = DAG.getConstantFP(APFloat(APInt(64, 1, &api.getRawData()[0])),
5647 Lo = ExpandConstantFP(CFP, false, DAG, TLI);
5648 if (getTypeAction(Lo.getValueType()) == Expand)
5649 ExpandOp(Lo, Lo, Hi);
5652 case ISD::BUILD_PAIR:
5653 // Return the operands.
5654 Lo = Node->getOperand(0);
5655 Hi = Node->getOperand(1);
5658 case ISD::MERGE_VALUES:
5659 if (Node->getNumValues() == 1) {
5660 ExpandOp(Op.getOperand(0), Lo, Hi);
5663 // FIXME: For now only expand i64,chain = MERGE_VALUES (x, y)
5664 assert(Op.ResNo == 0 && Node->getNumValues() == 2 &&
5665 Op.getValue(1).getValueType() == MVT::Other &&
5666 "unhandled MERGE_VALUES");
5667 ExpandOp(Op.getOperand(0), Lo, Hi);
5668 // Remember that we legalized the chain.
5669 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Op.getOperand(1)));
5672 case ISD::SIGN_EXTEND_INREG:
5673 ExpandOp(Node->getOperand(0), Lo, Hi);
5674 // sext_inreg the low part if needed.
5675 Lo = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Lo, Node->getOperand(1));
5677 // The high part gets the sign extension from the lo-part. This handles
5678 // things like sextinreg V:i64 from i8.
5679 Hi = DAG.getNode(ISD::SRA, NVT, Lo,
5680 DAG.getConstant(MVT::getSizeInBits(NVT)-1,
5681 TLI.getShiftAmountTy()));
5685 ExpandOp(Node->getOperand(0), Lo, Hi);
5686 SDOperand TempLo = DAG.getNode(ISD::BSWAP, NVT, Hi);
5687 Hi = DAG.getNode(ISD::BSWAP, NVT, Lo);
5693 ExpandOp(Node->getOperand(0), Lo, Hi);
5694 Lo = DAG.getNode(ISD::ADD, NVT, // ctpop(HL) -> ctpop(H)+ctpop(L)
5695 DAG.getNode(ISD::CTPOP, NVT, Lo),
5696 DAG.getNode(ISD::CTPOP, NVT, Hi));
5697 Hi = DAG.getConstant(0, NVT);
5701 // ctlz (HL) -> ctlz(H) != 32 ? ctlz(H) : (ctlz(L)+32)
5702 ExpandOp(Node->getOperand(0), Lo, Hi);
5703 SDOperand BitsC = DAG.getConstant(MVT::getSizeInBits(NVT), NVT);
5704 SDOperand HLZ = DAG.getNode(ISD::CTLZ, NVT, Hi);
5705 SDOperand TopNotZero = DAG.getSetCC(TLI.getSetCCResultTy(), HLZ, BitsC,
5707 SDOperand LowPart = DAG.getNode(ISD::CTLZ, NVT, Lo);
5708 LowPart = DAG.getNode(ISD::ADD, NVT, LowPart, BitsC);
5710 Lo = DAG.getNode(ISD::SELECT, NVT, TopNotZero, HLZ, LowPart);
5711 Hi = DAG.getConstant(0, NVT);
5716 // cttz (HL) -> cttz(L) != 32 ? cttz(L) : (cttz(H)+32)
5717 ExpandOp(Node->getOperand(0), Lo, Hi);
5718 SDOperand BitsC = DAG.getConstant(MVT::getSizeInBits(NVT), NVT);
5719 SDOperand LTZ = DAG.getNode(ISD::CTTZ, NVT, Lo);
5720 SDOperand BotNotZero = DAG.getSetCC(TLI.getSetCCResultTy(), LTZ, BitsC,
5722 SDOperand HiPart = DAG.getNode(ISD::CTTZ, NVT, Hi);
5723 HiPart = DAG.getNode(ISD::ADD, NVT, HiPart, BitsC);
5725 Lo = DAG.getNode(ISD::SELECT, NVT, BotNotZero, LTZ, HiPart);
5726 Hi = DAG.getConstant(0, NVT);
5731 SDOperand Ch = Node->getOperand(0); // Legalize the chain.
5732 SDOperand Ptr = Node->getOperand(1); // Legalize the pointer.
5733 Lo = DAG.getVAArg(NVT, Ch, Ptr, Node->getOperand(2));
5734 Hi = DAG.getVAArg(NVT, Lo.getValue(1), Ptr, Node->getOperand(2));
5736 // Remember that we legalized the chain.
5737 Hi = LegalizeOp(Hi);
5738 AddLegalizedOperand(Op.getValue(1), Hi.getValue(1));
5739 if (!TLI.isLittleEndian())
5745 LoadSDNode *LD = cast<LoadSDNode>(Node);
5746 SDOperand Ch = LD->getChain(); // Legalize the chain.
5747 SDOperand Ptr = LD->getBasePtr(); // Legalize the pointer.
5748 ISD::LoadExtType ExtType = LD->getExtensionType();
5749 int SVOffset = LD->getSrcValueOffset();
5750 unsigned Alignment = LD->getAlignment();
5751 bool isVolatile = LD->isVolatile();
5753 if (ExtType == ISD::NON_EXTLOAD) {
5754 Lo = DAG.getLoad(NVT, Ch, Ptr, LD->getSrcValue(), SVOffset,
5755 isVolatile, Alignment);
5756 if (VT == MVT::f32 || VT == MVT::f64) {
5757 // f32->i32 or f64->i64 one to one expansion.
5758 // Remember that we legalized the chain.
5759 AddLegalizedOperand(SDOperand(Node, 1), LegalizeOp(Lo.getValue(1)));
5760 // Recursively expand the new load.
5761 if (getTypeAction(NVT) == Expand)
5762 ExpandOp(Lo, Lo, Hi);
5766 // Increment the pointer to the other half.
5767 unsigned IncrementSize = MVT::getSizeInBits(Lo.getValueType())/8;
5768 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
5769 DAG.getIntPtrConstant(IncrementSize));
5770 SVOffset += IncrementSize;
5771 Alignment = MinAlign(Alignment, IncrementSize);
5772 Hi = DAG.getLoad(NVT, Ch, Ptr, LD->getSrcValue(), SVOffset,
5773 isVolatile, Alignment);
5775 // Build a factor node to remember that this load is independent of the
5777 SDOperand TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
5780 // Remember that we legalized the chain.
5781 AddLegalizedOperand(Op.getValue(1), LegalizeOp(TF));
5782 if (!TLI.isLittleEndian())
5785 MVT::ValueType EVT = LD->getMemoryVT();
5787 if ((VT == MVT::f64 && EVT == MVT::f32) ||
5788 (VT == MVT::ppcf128 && (EVT==MVT::f64 || EVT==MVT::f32))) {
5789 // f64 = EXTLOAD f32 should expand to LOAD, FP_EXTEND
5790 SDOperand Load = DAG.getLoad(EVT, Ch, Ptr, LD->getSrcValue(),
5791 SVOffset, isVolatile, Alignment);
5792 // Remember that we legalized the chain.
5793 AddLegalizedOperand(SDOperand(Node, 1), LegalizeOp(Load.getValue(1)));
5794 ExpandOp(DAG.getNode(ISD::FP_EXTEND, VT, Load), Lo, Hi);
5799 Lo = DAG.getLoad(NVT, Ch, Ptr, LD->getSrcValue(),
5800 SVOffset, isVolatile, Alignment);
5802 Lo = DAG.getExtLoad(ExtType, NVT, Ch, Ptr, LD->getSrcValue(),
5803 SVOffset, EVT, isVolatile,
5806 // Remember that we legalized the chain.
5807 AddLegalizedOperand(SDOperand(Node, 1), LegalizeOp(Lo.getValue(1)));
5809 if (ExtType == ISD::SEXTLOAD) {
5810 // The high part is obtained by SRA'ing all but one of the bits of the
5812 unsigned LoSize = MVT::getSizeInBits(Lo.getValueType());
5813 Hi = DAG.getNode(ISD::SRA, NVT, Lo,
5814 DAG.getConstant(LoSize-1, TLI.getShiftAmountTy()));
5815 } else if (ExtType == ISD::ZEXTLOAD) {
5816 // The high part is just a zero.
5817 Hi = DAG.getConstant(0, NVT);
5818 } else /* if (ExtType == ISD::EXTLOAD) */ {
5819 // The high part is undefined.
5820 Hi = DAG.getNode(ISD::UNDEF, NVT);
5827 case ISD::XOR: { // Simple logical operators -> two trivial pieces.
5828 SDOperand LL, LH, RL, RH;
5829 ExpandOp(Node->getOperand(0), LL, LH);
5830 ExpandOp(Node->getOperand(1), RL, RH);
5831 Lo = DAG.getNode(Node->getOpcode(), NVT, LL, RL);
5832 Hi = DAG.getNode(Node->getOpcode(), NVT, LH, RH);
5836 SDOperand LL, LH, RL, RH;
5837 ExpandOp(Node->getOperand(1), LL, LH);
5838 ExpandOp(Node->getOperand(2), RL, RH);
5839 if (getTypeAction(NVT) == Expand)
5840 NVT = TLI.getTypeToExpandTo(NVT);
5841 Lo = DAG.getNode(ISD::SELECT, NVT, Node->getOperand(0), LL, RL);
5843 Hi = DAG.getNode(ISD::SELECT, NVT, Node->getOperand(0), LH, RH);
5846 case ISD::SELECT_CC: {
5847 SDOperand TL, TH, FL, FH;
5848 ExpandOp(Node->getOperand(2), TL, TH);
5849 ExpandOp(Node->getOperand(3), FL, FH);
5850 if (getTypeAction(NVT) == Expand)
5851 NVT = TLI.getTypeToExpandTo(NVT);
5852 Lo = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0),
5853 Node->getOperand(1), TL, FL, Node->getOperand(4));
5855 Hi = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0),
5856 Node->getOperand(1), TH, FH, Node->getOperand(4));
5859 case ISD::ANY_EXTEND:
5860 // The low part is any extension of the input (which degenerates to a copy).
5861 Lo = DAG.getNode(ISD::ANY_EXTEND, NVT, Node->getOperand(0));
5862 // The high part is undefined.
5863 Hi = DAG.getNode(ISD::UNDEF, NVT);
5865 case ISD::SIGN_EXTEND: {
5866 // The low part is just a sign extension of the input (which degenerates to
5868 Lo = DAG.getNode(ISD::SIGN_EXTEND, NVT, Node->getOperand(0));
5870 // The high part is obtained by SRA'ing all but one of the bits of the lo
5872 unsigned LoSize = MVT::getSizeInBits(Lo.getValueType());
5873 Hi = DAG.getNode(ISD::SRA, NVT, Lo,
5874 DAG.getConstant(LoSize-1, TLI.getShiftAmountTy()));
5877 case ISD::ZERO_EXTEND:
5878 // The low part is just a zero extension of the input (which degenerates to
5880 Lo = DAG.getNode(ISD::ZERO_EXTEND, NVT, Node->getOperand(0));
5882 // The high part is just a zero.
5883 Hi = DAG.getConstant(0, NVT);
5886 case ISD::TRUNCATE: {
5887 // The input value must be larger than this value. Expand *it*.
5889 ExpandOp(Node->getOperand(0), NewLo, Hi);
5891 // The low part is now either the right size, or it is closer. If not the
5892 // right size, make an illegal truncate so we recursively expand it.
5893 if (NewLo.getValueType() != Node->getValueType(0))
5894 NewLo = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), NewLo);
5895 ExpandOp(NewLo, Lo, Hi);
5899 case ISD::BIT_CONVERT: {
5901 if (TLI.getOperationAction(ISD::BIT_CONVERT, VT) == TargetLowering::Custom){
5902 // If the target wants to, allow it to lower this itself.
5903 switch (getTypeAction(Node->getOperand(0).getValueType())) {
5904 case Expand: assert(0 && "cannot expand FP!");
5905 case Legal: Tmp = LegalizeOp(Node->getOperand(0)); break;
5906 case Promote: Tmp = PromoteOp (Node->getOperand(0)); break;
5908 Tmp = TLI.LowerOperation(DAG.getNode(ISD::BIT_CONVERT, VT, Tmp), DAG);
5911 // f32 / f64 must be expanded to i32 / i64.
5912 if (VT == MVT::f32 || VT == MVT::f64) {
5913 Lo = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0));
5914 if (getTypeAction(NVT) == Expand)
5915 ExpandOp(Lo, Lo, Hi);
5919 // If source operand will be expanded to the same type as VT, i.e.
5920 // i64 <- f64, i32 <- f32, expand the source operand instead.
5921 MVT::ValueType VT0 = Node->getOperand(0).getValueType();
5922 if (getTypeAction(VT0) == Expand && TLI.getTypeToTransformTo(VT0) == VT) {
5923 ExpandOp(Node->getOperand(0), Lo, Hi);
5927 // Turn this into a load/store pair by default.
5929 Tmp = EmitStackConvert(Node->getOperand(0), VT, VT);
5931 ExpandOp(Tmp, Lo, Hi);
5935 case ISD::READCYCLECOUNTER: {
5936 assert(TLI.getOperationAction(ISD::READCYCLECOUNTER, VT) ==
5937 TargetLowering::Custom &&
5938 "Must custom expand ReadCycleCounter");
5939 SDOperand Tmp = TLI.LowerOperation(Op, DAG);
5940 assert(Tmp.Val && "Node must be custom expanded!");
5941 ExpandOp(Tmp.getValue(0), Lo, Hi);
5942 AddLegalizedOperand(SDOperand(Node, 1), // Remember we legalized the chain.
5943 LegalizeOp(Tmp.getValue(1)));
5947 // These operators cannot be expanded directly, emit them as calls to
5948 // library functions.
5949 case ISD::FP_TO_SINT: {
5950 if (TLI.getOperationAction(ISD::FP_TO_SINT, VT) == TargetLowering::Custom) {
5952 switch (getTypeAction(Node->getOperand(0).getValueType())) {
5953 case Expand: assert(0 && "cannot expand FP!");
5954 case Legal: Op = LegalizeOp(Node->getOperand(0)); break;
5955 case Promote: Op = PromoteOp (Node->getOperand(0)); break;
5958 Op = TLI.LowerOperation(DAG.getNode(ISD::FP_TO_SINT, VT, Op), DAG);
5960 // Now that the custom expander is done, expand the result, which is still
5963 ExpandOp(Op, Lo, Hi);
5968 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
5969 if (Node->getOperand(0).getValueType() == MVT::f32)
5970 LC = RTLIB::FPTOSINT_F32_I64;
5971 else if (Node->getOperand(0).getValueType() == MVT::f64)
5972 LC = RTLIB::FPTOSINT_F64_I64;
5973 else if (Node->getOperand(0).getValueType() == MVT::f80)
5974 LC = RTLIB::FPTOSINT_F80_I64;
5975 else if (Node->getOperand(0).getValueType() == MVT::ppcf128)
5976 LC = RTLIB::FPTOSINT_PPCF128_I64;
5977 Lo = ExpandLibCall(TLI.getLibcallName(LC), Node,
5978 false/*sign irrelevant*/, Hi);
5982 case ISD::FP_TO_UINT: {
5983 if (TLI.getOperationAction(ISD::FP_TO_UINT, VT) == TargetLowering::Custom) {
5985 switch (getTypeAction(Node->getOperand(0).getValueType())) {
5986 case Expand: assert(0 && "cannot expand FP!");
5987 case Legal: Op = LegalizeOp(Node->getOperand(0)); break;
5988 case Promote: Op = PromoteOp (Node->getOperand(0)); break;
5991 Op = TLI.LowerOperation(DAG.getNode(ISD::FP_TO_UINT, VT, Op), DAG);
5993 // Now that the custom expander is done, expand the result.
5995 ExpandOp(Op, Lo, Hi);
6000 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
6001 if (Node->getOperand(0).getValueType() == MVT::f32)
6002 LC = RTLIB::FPTOUINT_F32_I64;
6003 else if (Node->getOperand(0).getValueType() == MVT::f64)
6004 LC = RTLIB::FPTOUINT_F64_I64;
6005 else if (Node->getOperand(0).getValueType() == MVT::f80)
6006 LC = RTLIB::FPTOUINT_F80_I64;
6007 else if (Node->getOperand(0).getValueType() == MVT::ppcf128)
6008 LC = RTLIB::FPTOUINT_PPCF128_I64;
6009 Lo = ExpandLibCall(TLI.getLibcallName(LC), Node,
6010 false/*sign irrelevant*/, Hi);
6015 // If the target wants custom lowering, do so.
6016 SDOperand ShiftAmt = LegalizeOp(Node->getOperand(1));
6017 if (TLI.getOperationAction(ISD::SHL, VT) == TargetLowering::Custom) {
6018 SDOperand Op = DAG.getNode(ISD::SHL, VT, Node->getOperand(0), ShiftAmt);
6019 Op = TLI.LowerOperation(Op, DAG);
6021 // Now that the custom expander is done, expand the result, which is
6023 ExpandOp(Op, Lo, Hi);
6028 // If ADDC/ADDE are supported and if the shift amount is a constant 1, emit
6029 // this X << 1 as X+X.
6030 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(ShiftAmt)) {
6031 if (ShAmt->getValue() == 1 && TLI.isOperationLegal(ISD::ADDC, NVT) &&
6032 TLI.isOperationLegal(ISD::ADDE, NVT)) {
6033 SDOperand LoOps[2], HiOps[3];
6034 ExpandOp(Node->getOperand(0), LoOps[0], HiOps[0]);
6035 SDVTList VTList = DAG.getVTList(LoOps[0].getValueType(), MVT::Flag);
6036 LoOps[1] = LoOps[0];
6037 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2);
6039 HiOps[1] = HiOps[0];
6040 HiOps[2] = Lo.getValue(1);
6041 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3);
6046 // If we can emit an efficient shift operation, do so now.
6047 if (ExpandShift(ISD::SHL, Node->getOperand(0), ShiftAmt, Lo, Hi))
6050 // If this target supports SHL_PARTS, use it.
6051 TargetLowering::LegalizeAction Action =
6052 TLI.getOperationAction(ISD::SHL_PARTS, NVT);
6053 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) ||
6054 Action == TargetLowering::Custom) {
6055 ExpandShiftParts(ISD::SHL_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi);
6059 // Otherwise, emit a libcall.
6060 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::SHL_I64), Node,
6061 false/*left shift=unsigned*/, Hi);
6066 // If the target wants custom lowering, do so.
6067 SDOperand ShiftAmt = LegalizeOp(Node->getOperand(1));
6068 if (TLI.getOperationAction(ISD::SRA, VT) == TargetLowering::Custom) {
6069 SDOperand Op = DAG.getNode(ISD::SRA, VT, Node->getOperand(0), ShiftAmt);
6070 Op = TLI.LowerOperation(Op, DAG);
6072 // Now that the custom expander is done, expand the result, which is
6074 ExpandOp(Op, Lo, Hi);
6079 // If we can emit an efficient shift operation, do so now.
6080 if (ExpandShift(ISD::SRA, Node->getOperand(0), ShiftAmt, Lo, Hi))
6083 // If this target supports SRA_PARTS, use it.
6084 TargetLowering::LegalizeAction Action =
6085 TLI.getOperationAction(ISD::SRA_PARTS, NVT);
6086 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) ||
6087 Action == TargetLowering::Custom) {
6088 ExpandShiftParts(ISD::SRA_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi);
6092 // Otherwise, emit a libcall.
6093 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::SRA_I64), Node,
6094 true/*ashr is signed*/, Hi);
6099 // If the target wants custom lowering, do so.
6100 SDOperand ShiftAmt = LegalizeOp(Node->getOperand(1));
6101 if (TLI.getOperationAction(ISD::SRL, VT) == TargetLowering::Custom) {
6102 SDOperand Op = DAG.getNode(ISD::SRL, VT, Node->getOperand(0), ShiftAmt);
6103 Op = TLI.LowerOperation(Op, DAG);
6105 // Now that the custom expander is done, expand the result, which is
6107 ExpandOp(Op, Lo, Hi);
6112 // If we can emit an efficient shift operation, do so now.
6113 if (ExpandShift(ISD::SRL, Node->getOperand(0), ShiftAmt, Lo, Hi))
6116 // If this target supports SRL_PARTS, use it.
6117 TargetLowering::LegalizeAction Action =
6118 TLI.getOperationAction(ISD::SRL_PARTS, NVT);
6119 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) ||
6120 Action == TargetLowering::Custom) {
6121 ExpandShiftParts(ISD::SRL_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi);
6125 // Otherwise, emit a libcall.
6126 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::SRL_I64), Node,
6127 false/*lshr is unsigned*/, Hi);
6133 // If the target wants to custom expand this, let them.
6134 if (TLI.getOperationAction(Node->getOpcode(), VT) ==
6135 TargetLowering::Custom) {
6136 Op = TLI.LowerOperation(Op, DAG);
6138 ExpandOp(Op, Lo, Hi);
6143 // Expand the subcomponents.
6144 SDOperand LHSL, LHSH, RHSL, RHSH;
6145 ExpandOp(Node->getOperand(0), LHSL, LHSH);
6146 ExpandOp(Node->getOperand(1), RHSL, RHSH);
6147 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag);
6148 SDOperand LoOps[2], HiOps[3];
6153 if (Node->getOpcode() == ISD::ADD) {
6154 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2);
6155 HiOps[2] = Lo.getValue(1);
6156 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3);
6158 Lo = DAG.getNode(ISD::SUBC, VTList, LoOps, 2);
6159 HiOps[2] = Lo.getValue(1);
6160 Hi = DAG.getNode(ISD::SUBE, VTList, HiOps, 3);
6167 // Expand the subcomponents.
6168 SDOperand LHSL, LHSH, RHSL, RHSH;
6169 ExpandOp(Node->getOperand(0), LHSL, LHSH);
6170 ExpandOp(Node->getOperand(1), RHSL, RHSH);
6171 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag);
6172 SDOperand LoOps[2] = { LHSL, RHSL };
6173 SDOperand HiOps[3] = { LHSH, RHSH };
6175 if (Node->getOpcode() == ISD::ADDC) {
6176 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2);
6177 HiOps[2] = Lo.getValue(1);
6178 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3);
6180 Lo = DAG.getNode(ISD::SUBC, VTList, LoOps, 2);
6181 HiOps[2] = Lo.getValue(1);
6182 Hi = DAG.getNode(ISD::SUBE, VTList, HiOps, 3);
6184 // Remember that we legalized the flag.
6185 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Hi.getValue(1)));
6190 // Expand the subcomponents.
6191 SDOperand LHSL, LHSH, RHSL, RHSH;
6192 ExpandOp(Node->getOperand(0), LHSL, LHSH);
6193 ExpandOp(Node->getOperand(1), RHSL, RHSH);
6194 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag);
6195 SDOperand LoOps[3] = { LHSL, RHSL, Node->getOperand(2) };
6196 SDOperand HiOps[3] = { LHSH, RHSH };
6198 Lo = DAG.getNode(Node->getOpcode(), VTList, LoOps, 3);
6199 HiOps[2] = Lo.getValue(1);
6200 Hi = DAG.getNode(Node->getOpcode(), VTList, HiOps, 3);
6202 // Remember that we legalized the flag.
6203 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Hi.getValue(1)));
6207 // If the target wants to custom expand this, let them.
6208 if (TLI.getOperationAction(ISD::MUL, VT) == TargetLowering::Custom) {
6209 SDOperand New = TLI.LowerOperation(Op, DAG);
6211 ExpandOp(New, Lo, Hi);
6216 bool HasMULHS = TLI.isOperationLegal(ISD::MULHS, NVT);
6217 bool HasMULHU = TLI.isOperationLegal(ISD::MULHU, NVT);
6218 bool HasSMUL_LOHI = TLI.isOperationLegal(ISD::SMUL_LOHI, NVT);
6219 bool HasUMUL_LOHI = TLI.isOperationLegal(ISD::UMUL_LOHI, NVT);
6220 if (HasMULHU || HasMULHS || HasUMUL_LOHI || HasSMUL_LOHI) {
6221 SDOperand LL, LH, RL, RH;
6222 ExpandOp(Node->getOperand(0), LL, LH);
6223 ExpandOp(Node->getOperand(1), RL, RH);
6224 unsigned BitSize = MVT::getSizeInBits(RH.getValueType());
6225 unsigned LHSSB = DAG.ComputeNumSignBits(Op.getOperand(0));
6226 unsigned RHSSB = DAG.ComputeNumSignBits(Op.getOperand(1));
6227 // FIXME: generalize this to handle other bit sizes
6228 if (LHSSB == 32 && RHSSB == 32 &&
6229 DAG.MaskedValueIsZero(Op.getOperand(0), 0xFFFFFFFF00000000ULL) &&
6230 DAG.MaskedValueIsZero(Op.getOperand(1), 0xFFFFFFFF00000000ULL)) {
6231 // The inputs are both zero-extended.
6233 // We can emit a umul_lohi.
6234 Lo = DAG.getNode(ISD::UMUL_LOHI, DAG.getVTList(NVT, NVT), LL, RL);
6235 Hi = SDOperand(Lo.Val, 1);
6239 // We can emit a mulhu+mul.
6240 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL);
6241 Hi = DAG.getNode(ISD::MULHU, NVT, LL, RL);
6245 if (LHSSB > BitSize && RHSSB > BitSize) {
6246 // The input values are both sign-extended.
6248 // We can emit a smul_lohi.
6249 Lo = DAG.getNode(ISD::SMUL_LOHI, DAG.getVTList(NVT, NVT), LL, RL);
6250 Hi = SDOperand(Lo.Val, 1);
6254 // We can emit a mulhs+mul.
6255 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL);
6256 Hi = DAG.getNode(ISD::MULHS, NVT, LL, RL);
6261 // Lo,Hi = umul LHS, RHS.
6262 SDOperand UMulLOHI = DAG.getNode(ISD::UMUL_LOHI,
6263 DAG.getVTList(NVT, NVT), LL, RL);
6265 Hi = UMulLOHI.getValue(1);
6266 RH = DAG.getNode(ISD::MUL, NVT, LL, RH);
6267 LH = DAG.getNode(ISD::MUL, NVT, LH, RL);
6268 Hi = DAG.getNode(ISD::ADD, NVT, Hi, RH);
6269 Hi = DAG.getNode(ISD::ADD, NVT, Hi, LH);
6273 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL);
6274 Hi = DAG.getNode(ISD::MULHU, NVT, LL, RL);
6275 RH = DAG.getNode(ISD::MUL, NVT, LL, RH);
6276 LH = DAG.getNode(ISD::MUL, NVT, LH, RL);
6277 Hi = DAG.getNode(ISD::ADD, NVT, Hi, RH);
6278 Hi = DAG.getNode(ISD::ADD, NVT, Hi, LH);
6283 // If nothing else, we can make a libcall.
6284 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::MUL_I64), Node,
6285 false/*sign irrelevant*/, Hi);
6289 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::SDIV_I64), Node, true, Hi);
6292 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::UDIV_I64), Node, true, Hi);
6295 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::SREM_I64), Node, true, Hi);
6298 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::UREM_I64), Node, true, Hi);
6302 Lo = ExpandLibCall(TLI.getLibcallName(GetFPLibCall(VT, RTLIB::ADD_F32,
6305 RTLIB::ADD_PPCF128)),
6309 Lo = ExpandLibCall(TLI.getLibcallName(GetFPLibCall(VT, RTLIB::SUB_F32,
6312 RTLIB::SUB_PPCF128)),
6316 Lo = ExpandLibCall(TLI.getLibcallName(GetFPLibCall(VT, RTLIB::MUL_F32,
6319 RTLIB::MUL_PPCF128)),
6323 Lo = ExpandLibCall(TLI.getLibcallName(GetFPLibCall(VT, RTLIB::DIV_F32,
6326 RTLIB::DIV_PPCF128)),
6329 case ISD::FP_EXTEND:
6330 if (VT == MVT::ppcf128) {
6331 assert(Node->getOperand(0).getValueType()==MVT::f32 ||
6332 Node->getOperand(0).getValueType()==MVT::f64);
6333 const uint64_t zero = 0;
6334 if (Node->getOperand(0).getValueType()==MVT::f32)
6335 Hi = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Node->getOperand(0));
6337 Hi = Node->getOperand(0);
6338 Lo = DAG.getConstantFP(APFloat(APInt(64, 1, &zero)), MVT::f64);
6341 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::FPEXT_F32_F64), Node, true,Hi);
6344 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::FPROUND_F64_F32),Node,true,Hi);
6347 Lo = ExpandLibCall(TLI.getLibcallName(GetFPLibCall(VT, RTLIB::POWI_F32,
6350 RTLIB::POWI_PPCF128)),
6356 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
6357 switch(Node->getOpcode()) {
6359 LC = GetFPLibCall(VT, RTLIB::SQRT_F32, RTLIB::SQRT_F64,
6360 RTLIB::SQRT_F80, RTLIB::SQRT_PPCF128);
6363 LC = GetFPLibCall(VT, RTLIB::SIN_F32, RTLIB::SIN_F64,
6364 RTLIB::SIN_F80, RTLIB::SIN_PPCF128);
6367 LC = GetFPLibCall(VT, RTLIB::COS_F32, RTLIB::COS_F64,
6368 RTLIB::COS_F80, RTLIB::COS_PPCF128);
6370 default: assert(0 && "Unreachable!");
6372 Lo = ExpandLibCall(TLI.getLibcallName(LC), Node, false, Hi);
6376 if (VT == MVT::ppcf128) {
6378 ExpandOp(Node->getOperand(0), Lo, Tmp);
6379 Hi = DAG.getNode(ISD::FABS, NVT, Tmp);
6380 // lo = hi==fabs(hi) ? lo : -lo;
6381 Lo = DAG.getNode(ISD::SELECT_CC, NVT, Hi, Tmp,
6382 Lo, DAG.getNode(ISD::FNEG, NVT, Lo),
6383 DAG.getCondCode(ISD::SETEQ));
6386 SDOperand Mask = (VT == MVT::f64)
6387 ? DAG.getConstantFP(BitsToDouble(~(1ULL << 63)), VT)
6388 : DAG.getConstantFP(BitsToFloat(~(1U << 31)), VT);
6389 Mask = DAG.getNode(ISD::BIT_CONVERT, NVT, Mask);
6390 Lo = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0));
6391 Lo = DAG.getNode(ISD::AND, NVT, Lo, Mask);
6392 if (getTypeAction(NVT) == Expand)
6393 ExpandOp(Lo, Lo, Hi);
6397 if (VT == MVT::ppcf128) {
6398 ExpandOp(Node->getOperand(0), Lo, Hi);
6399 Lo = DAG.getNode(ISD::FNEG, MVT::f64, Lo);
6400 Hi = DAG.getNode(ISD::FNEG, MVT::f64, Hi);
6403 SDOperand Mask = (VT == MVT::f64)
6404 ? DAG.getConstantFP(BitsToDouble(1ULL << 63), VT)
6405 : DAG.getConstantFP(BitsToFloat(1U << 31), VT);
6406 Mask = DAG.getNode(ISD::BIT_CONVERT, NVT, Mask);
6407 Lo = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0));
6408 Lo = DAG.getNode(ISD::XOR, NVT, Lo, Mask);
6409 if (getTypeAction(NVT) == Expand)
6410 ExpandOp(Lo, Lo, Hi);
6413 case ISD::FCOPYSIGN: {
6414 Lo = ExpandFCOPYSIGNToBitwiseOps(Node, NVT, DAG, TLI);
6415 if (getTypeAction(NVT) == Expand)
6416 ExpandOp(Lo, Lo, Hi);
6419 case ISD::SINT_TO_FP:
6420 case ISD::UINT_TO_FP: {
6421 bool isSigned = Node->getOpcode() == ISD::SINT_TO_FP;
6422 MVT::ValueType SrcVT = Node->getOperand(0).getValueType();
6423 if (VT == MVT::ppcf128 && SrcVT != MVT::i64) {
6424 static uint64_t zero = 0;
6426 Hi = LegalizeOp(DAG.getNode(ISD::SINT_TO_FP, MVT::f64,
6427 Node->getOperand(0)));
6428 Lo = DAG.getConstantFP(APFloat(APInt(64, 1, &zero)), MVT::f64);
6430 static uint64_t TwoE32[] = { 0x41f0000000000000LL, 0 };
6431 Hi = LegalizeOp(DAG.getNode(ISD::SINT_TO_FP, MVT::f64,
6432 Node->getOperand(0)));
6433 Lo = DAG.getConstantFP(APFloat(APInt(64, 1, &zero)), MVT::f64);
6434 Hi = DAG.getNode(ISD::BUILD_PAIR, VT, Lo, Hi);
6435 // X>=0 ? {(f64)x, 0} : {(f64)x, 0} + 2^32
6436 ExpandOp(DAG.getNode(ISD::SELECT_CC, MVT::ppcf128, Node->getOperand(0),
6437 DAG.getConstant(0, MVT::i32),
6438 DAG.getNode(ISD::FADD, MVT::ppcf128, Hi,
6440 APFloat(APInt(128, 2, TwoE32)),
6443 DAG.getCondCode(ISD::SETLT)),
6448 if (VT == MVT::ppcf128 && SrcVT == MVT::i64 && !isSigned) {
6449 // si64->ppcf128 done by libcall, below
6450 static uint64_t TwoE64[] = { 0x43f0000000000000LL, 0 };
6451 ExpandOp(DAG.getNode(ISD::SINT_TO_FP, MVT::ppcf128, Node->getOperand(0)),
6453 Hi = DAG.getNode(ISD::BUILD_PAIR, VT, Lo, Hi);
6454 // x>=0 ? (ppcf128)(i64)x : (ppcf128)(i64)x + 2^64
6455 ExpandOp(DAG.getNode(ISD::SELECT_CC, MVT::ppcf128, Node->getOperand(0),
6456 DAG.getConstant(0, MVT::i64),
6457 DAG.getNode(ISD::FADD, MVT::ppcf128, Hi,
6459 APFloat(APInt(128, 2, TwoE64)),
6462 DAG.getCondCode(ISD::SETLT)),
6466 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
6467 if (Node->getOperand(0).getValueType() == MVT::i64) {
6469 LC = isSigned ? RTLIB::SINTTOFP_I64_F32 : RTLIB::UINTTOFP_I64_F32;
6470 else if (VT == MVT::f64)
6471 LC = isSigned ? RTLIB::SINTTOFP_I64_F64 : RTLIB::UINTTOFP_I64_F64;
6472 else if (VT == MVT::f80) {
6474 LC = RTLIB::SINTTOFP_I64_F80;
6476 else if (VT == MVT::ppcf128) {
6478 LC = RTLIB::SINTTOFP_I64_PPCF128;
6482 LC = isSigned ? RTLIB::SINTTOFP_I32_F32 : RTLIB::UINTTOFP_I32_F32;
6484 LC = isSigned ? RTLIB::SINTTOFP_I32_F64 : RTLIB::UINTTOFP_I32_F64;
6487 // Promote the operand if needed.
6488 if (getTypeAction(SrcVT) == Promote) {
6489 SDOperand Tmp = PromoteOp(Node->getOperand(0));
6491 ? DAG.getNode(ISD::SIGN_EXTEND_INREG, Tmp.getValueType(), Tmp,
6492 DAG.getValueType(SrcVT))
6493 : DAG.getZeroExtendInReg(Tmp, SrcVT);
6494 Node = DAG.UpdateNodeOperands(Op, Tmp).Val;
6497 const char *LibCall = TLI.getLibcallName(LC);
6499 Lo = ExpandLibCall(TLI.getLibcallName(LC), Node, isSigned, Hi);
6501 Lo = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP, VT,
6502 Node->getOperand(0));
6503 if (getTypeAction(Lo.getValueType()) == Expand)
6504 ExpandOp(Lo, Lo, Hi);
6510 // Make sure the resultant values have been legalized themselves, unless this
6511 // is a type that requires multi-step expansion.
6512 if (getTypeAction(NVT) != Expand && NVT != MVT::isVoid) {
6513 Lo = LegalizeOp(Lo);
6515 // Don't legalize the high part if it is expanded to a single node.
6516 Hi = LegalizeOp(Hi);
6519 // Remember in a map if the values will be reused later.
6520 bool isNew = ExpandedNodes.insert(std::make_pair(Op, std::make_pair(Lo, Hi)));
6521 assert(isNew && "Value already expanded?!?");
6524 /// SplitVectorOp - Given an operand of vector type, break it down into
6525 /// two smaller values, still of vector type.
6526 void SelectionDAGLegalize::SplitVectorOp(SDOperand Op, SDOperand &Lo,
6528 assert(MVT::isVector(Op.getValueType()) && "Cannot split non-vector type!");
6529 SDNode *Node = Op.Val;
6530 unsigned NumElements = MVT::getVectorNumElements(Op.getValueType());
6531 assert(NumElements > 1 && "Cannot split a single element vector!");
6533 MVT::ValueType NewEltVT = MVT::getVectorElementType(Op.getValueType());
6535 unsigned NewNumElts_Lo = 1 << Log2_32(NumElements-1);
6536 unsigned NewNumElts_Hi = NumElements - NewNumElts_Lo;
6538 MVT::ValueType NewVT_Lo = MVT::getVectorType(NewEltVT, NewNumElts_Lo);
6539 MVT::ValueType NewVT_Hi = MVT::getVectorType(NewEltVT, NewNumElts_Hi);
6541 // See if we already split it.
6542 std::map<SDOperand, std::pair<SDOperand, SDOperand> >::iterator I
6543 = SplitNodes.find(Op);
6544 if (I != SplitNodes.end()) {
6545 Lo = I->second.first;
6546 Hi = I->second.second;
6550 switch (Node->getOpcode()) {
6555 assert(0 && "Unhandled operation in SplitVectorOp!");
6557 Lo = DAG.getNode(ISD::UNDEF, NewVT_Lo);
6558 Hi = DAG.getNode(ISD::UNDEF, NewVT_Hi);
6560 case ISD::BUILD_PAIR:
6561 Lo = Node->getOperand(0);
6562 Hi = Node->getOperand(1);
6564 case ISD::INSERT_VECTOR_ELT: {
6565 SplitVectorOp(Node->getOperand(0), Lo, Hi);
6566 unsigned Index = cast<ConstantSDNode>(Node->getOperand(2))->getValue();
6567 SDOperand ScalarOp = Node->getOperand(1);
6568 if (Index < NewNumElts_Lo)
6569 Lo = DAG.getNode(ISD::INSERT_VECTOR_ELT, NewVT_Lo, Lo, ScalarOp,
6570 DAG.getConstant(Index, TLI.getPointerTy()));
6572 Hi = DAG.getNode(ISD::INSERT_VECTOR_ELT, NewVT_Hi, Hi, ScalarOp,
6573 DAG.getConstant(Index - NewNumElts_Lo,
6574 TLI.getPointerTy()));
6577 case ISD::VECTOR_SHUFFLE: {
6578 // Build the low part.
6579 SDOperand Mask = Node->getOperand(2);
6580 SmallVector<SDOperand, 8> Ops;
6581 MVT::ValueType PtrVT = TLI.getPointerTy();
6583 // Insert all of the elements from the input that are needed. We use
6584 // buildvector of extractelement here because the input vectors will have
6585 // to be legalized, so this makes the code simpler.
6586 for (unsigned i = 0; i != NewNumElts_Lo; ++i) {
6587 unsigned Idx = cast<ConstantSDNode>(Mask.getOperand(i))->getValue();
6588 SDOperand InVec = Node->getOperand(0);
6589 if (Idx >= NumElements) {
6590 InVec = Node->getOperand(1);
6593 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, NewEltVT, InVec,
6594 DAG.getConstant(Idx, PtrVT)));
6596 Lo = DAG.getNode(ISD::BUILD_VECTOR, NewVT_Lo, &Ops[0], Ops.size());
6599 for (unsigned i = NewNumElts_Lo; i != NumElements; ++i) {
6600 unsigned Idx = cast<ConstantSDNode>(Mask.getOperand(i))->getValue();
6601 SDOperand InVec = Node->getOperand(0);
6602 if (Idx >= NumElements) {
6603 InVec = Node->getOperand(1);
6606 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, NewEltVT, InVec,
6607 DAG.getConstant(Idx, PtrVT)));
6609 Hi = DAG.getNode(ISD::BUILD_VECTOR, NewVT_Lo, &Ops[0], Ops.size());
6612 case ISD::BUILD_VECTOR: {
6613 SmallVector<SDOperand, 8> LoOps(Node->op_begin(),
6614 Node->op_begin()+NewNumElts_Lo);
6615 Lo = DAG.getNode(ISD::BUILD_VECTOR, NewVT_Lo, &LoOps[0], LoOps.size());
6617 SmallVector<SDOperand, 8> HiOps(Node->op_begin()+NewNumElts_Lo,
6619 Hi = DAG.getNode(ISD::BUILD_VECTOR, NewVT_Hi, &HiOps[0], HiOps.size());
6622 case ISD::CONCAT_VECTORS: {
6623 // FIXME: Handle non-power-of-two vectors?
6624 unsigned NewNumSubvectors = Node->getNumOperands() / 2;
6625 if (NewNumSubvectors == 1) {
6626 Lo = Node->getOperand(0);
6627 Hi = Node->getOperand(1);
6629 SmallVector<SDOperand, 8> LoOps(Node->op_begin(),
6630 Node->op_begin()+NewNumSubvectors);
6631 Lo = DAG.getNode(ISD::CONCAT_VECTORS, NewVT_Lo, &LoOps[0], LoOps.size());
6633 SmallVector<SDOperand, 8> HiOps(Node->op_begin()+NewNumSubvectors,
6635 Hi = DAG.getNode(ISD::CONCAT_VECTORS, NewVT_Hi, &HiOps[0], HiOps.size());
6640 SDOperand Cond = Node->getOperand(0);
6642 SDOperand LL, LH, RL, RH;
6643 SplitVectorOp(Node->getOperand(1), LL, LH);
6644 SplitVectorOp(Node->getOperand(2), RL, RH);
6646 if (MVT::isVector(Cond.getValueType())) {
6647 // Handle a vector merge.
6649 SplitVectorOp(Cond, CL, CH);
6650 Lo = DAG.getNode(Node->getOpcode(), NewVT_Lo, CL, LL, RL);
6651 Hi = DAG.getNode(Node->getOpcode(), NewVT_Hi, CH, LH, RH);
6653 // Handle a simple select with vector operands.
6654 Lo = DAG.getNode(Node->getOpcode(), NewVT_Lo, Cond, LL, RL);
6655 Hi = DAG.getNode(Node->getOpcode(), NewVT_Hi, Cond, LH, RH);
6675 SDOperand LL, LH, RL, RH;
6676 SplitVectorOp(Node->getOperand(0), LL, LH);
6677 SplitVectorOp(Node->getOperand(1), RL, RH);
6679 Lo = DAG.getNode(Node->getOpcode(), NewVT_Lo, LL, RL);
6680 Hi = DAG.getNode(Node->getOpcode(), NewVT_Hi, LH, RH);
6685 SplitVectorOp(Node->getOperand(0), L, H);
6687 Lo = DAG.getNode(Node->getOpcode(), NewVT_Lo, L, Node->getOperand(1));
6688 Hi = DAG.getNode(Node->getOpcode(), NewVT_Hi, H, Node->getOperand(1));
6699 case ISD::FP_TO_SINT:
6700 case ISD::FP_TO_UINT:
6701 case ISD::SINT_TO_FP:
6702 case ISD::UINT_TO_FP: {
6704 SplitVectorOp(Node->getOperand(0), L, H);
6706 Lo = DAG.getNode(Node->getOpcode(), NewVT_Lo, L);
6707 Hi = DAG.getNode(Node->getOpcode(), NewVT_Hi, H);
6711 LoadSDNode *LD = cast<LoadSDNode>(Node);
6712 SDOperand Ch = LD->getChain();
6713 SDOperand Ptr = LD->getBasePtr();
6714 const Value *SV = LD->getSrcValue();
6715 int SVOffset = LD->getSrcValueOffset();
6716 unsigned Alignment = LD->getAlignment();
6717 bool isVolatile = LD->isVolatile();
6719 Lo = DAG.getLoad(NewVT_Lo, Ch, Ptr, SV, SVOffset, isVolatile, Alignment);
6720 unsigned IncrementSize = NewNumElts_Lo * MVT::getSizeInBits(NewEltVT)/8;
6721 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
6722 DAG.getIntPtrConstant(IncrementSize));
6723 SVOffset += IncrementSize;
6724 Alignment = MinAlign(Alignment, IncrementSize);
6725 Hi = DAG.getLoad(NewVT_Hi, Ch, Ptr, SV, SVOffset, isVolatile, Alignment);
6727 // Build a factor node to remember that this load is independent of the
6729 SDOperand TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
6732 // Remember that we legalized the chain.
6733 AddLegalizedOperand(Op.getValue(1), LegalizeOp(TF));
6736 case ISD::BIT_CONVERT: {
6737 // We know the result is a vector. The input may be either a vector or a
6739 SDOperand InOp = Node->getOperand(0);
6740 if (!MVT::isVector(InOp.getValueType()) ||
6741 MVT::getVectorNumElements(InOp.getValueType()) == 1) {
6742 // The input is a scalar or single-element vector.
6743 // Lower to a store/load so that it can be split.
6744 // FIXME: this could be improved probably.
6745 SDOperand Ptr = DAG.CreateStackTemporary(InOp.getValueType());
6747 SDOperand St = DAG.getStore(DAG.getEntryNode(),
6748 InOp, Ptr, NULL, 0);
6749 InOp = DAG.getLoad(Op.getValueType(), St, Ptr, NULL, 0);
6751 // Split the vector and convert each of the pieces now.
6752 SplitVectorOp(InOp, Lo, Hi);
6753 Lo = DAG.getNode(ISD::BIT_CONVERT, NewVT_Lo, Lo);
6754 Hi = DAG.getNode(ISD::BIT_CONVERT, NewVT_Hi, Hi);
6759 // Remember in a map if the values will be reused later.
6761 SplitNodes.insert(std::make_pair(Op, std::make_pair(Lo, Hi))).second;
6762 assert(isNew && "Value already split?!?");
6766 /// ScalarizeVectorOp - Given an operand of single-element vector type
6767 /// (e.g. v1f32), convert it into the equivalent operation that returns a
6768 /// scalar (e.g. f32) value.
6769 SDOperand SelectionDAGLegalize::ScalarizeVectorOp(SDOperand Op) {
6770 assert(MVT::isVector(Op.getValueType()) &&
6771 "Bad ScalarizeVectorOp invocation!");
6772 SDNode *Node = Op.Val;
6773 MVT::ValueType NewVT = MVT::getVectorElementType(Op.getValueType());
6774 assert(MVT::getVectorNumElements(Op.getValueType()) == 1);
6776 // See if we already scalarized it.
6777 std::map<SDOperand, SDOperand>::iterator I = ScalarizedNodes.find(Op);
6778 if (I != ScalarizedNodes.end()) return I->second;
6781 switch (Node->getOpcode()) {
6784 Node->dump(&DAG); cerr << "\n";
6786 assert(0 && "Unknown vector operation in ScalarizeVectorOp!");
6803 Result = DAG.getNode(Node->getOpcode(),
6805 ScalarizeVectorOp(Node->getOperand(0)),
6806 ScalarizeVectorOp(Node->getOperand(1)));
6813 Result = DAG.getNode(Node->getOpcode(),
6815 ScalarizeVectorOp(Node->getOperand(0)));
6818 Result = DAG.getNode(Node->getOpcode(),
6820 ScalarizeVectorOp(Node->getOperand(0)),
6821 Node->getOperand(1));
6824 LoadSDNode *LD = cast<LoadSDNode>(Node);
6825 SDOperand Ch = LegalizeOp(LD->getChain()); // Legalize the chain.
6826 SDOperand Ptr = LegalizeOp(LD->getBasePtr()); // Legalize the pointer.
6828 const Value *SV = LD->getSrcValue();
6829 int SVOffset = LD->getSrcValueOffset();
6830 Result = DAG.getLoad(NewVT, Ch, Ptr, SV, SVOffset,
6831 LD->isVolatile(), LD->getAlignment());
6833 // Remember that we legalized the chain.
6834 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
6837 case ISD::BUILD_VECTOR:
6838 Result = Node->getOperand(0);
6840 case ISD::INSERT_VECTOR_ELT:
6841 // Returning the inserted scalar element.
6842 Result = Node->getOperand(1);
6844 case ISD::CONCAT_VECTORS:
6845 assert(Node->getOperand(0).getValueType() == NewVT &&
6846 "Concat of non-legal vectors not yet supported!");
6847 Result = Node->getOperand(0);
6849 case ISD::VECTOR_SHUFFLE: {
6850 // Figure out if the scalar is the LHS or RHS and return it.
6851 SDOperand EltNum = Node->getOperand(2).getOperand(0);
6852 if (cast<ConstantSDNode>(EltNum)->getValue())
6853 Result = ScalarizeVectorOp(Node->getOperand(1));
6855 Result = ScalarizeVectorOp(Node->getOperand(0));
6858 case ISD::EXTRACT_SUBVECTOR:
6859 Result = Node->getOperand(0);
6860 assert(Result.getValueType() == NewVT);
6862 case ISD::BIT_CONVERT:
6863 Result = DAG.getNode(ISD::BIT_CONVERT, NewVT, Op.getOperand(0));
6866 Result = DAG.getNode(ISD::SELECT, NewVT, Op.getOperand(0),
6867 ScalarizeVectorOp(Op.getOperand(1)),
6868 ScalarizeVectorOp(Op.getOperand(2)));
6872 if (TLI.isTypeLegal(NewVT))
6873 Result = LegalizeOp(Result);
6874 bool isNew = ScalarizedNodes.insert(std::make_pair(Op, Result)).second;
6875 assert(isNew && "Value already scalarized?");
6880 // SelectionDAG::Legalize - This is the entry point for the file.
6882 void SelectionDAG::Legalize() {
6883 if (ViewLegalizeDAGs) viewGraph();
6885 /// run - This is the main entry point to this class.
6887 SelectionDAGLegalize(*this).LegalizeDAG();