1 //===-- LegalizeDAG.cpp - Implement SelectionDAG::Legalize ----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the SelectionDAG::Legalize method.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/CodeGen/SelectionDAG.h"
15 #include "llvm/CodeGen/MachineFunction.h"
16 #include "llvm/CodeGen/MachineFrameInfo.h"
17 #include "llvm/Support/MathExtras.h"
18 #include "llvm/Target/TargetLowering.h"
19 #include "llvm/Target/TargetData.h"
20 #include "llvm/Target/TargetOptions.h"
21 #include "llvm/CallingConv.h"
22 #include "llvm/Constants.h"
27 //===----------------------------------------------------------------------===//
28 /// SelectionDAGLegalize - This takes an arbitrary SelectionDAG as input and
29 /// hacks on it until the target machine can handle it. This involves
30 /// eliminating value sizes the machine cannot handle (promoting small sizes to
31 /// large sizes or splitting up large values into small values) as well as
32 /// eliminating operations the machine cannot handle.
34 /// This code also does a small amount of optimization and recognition of idioms
35 /// as part of its processing. For example, if a target does not support a
36 /// 'setcc' instruction efficiently, but does support 'brcc' instruction, this
37 /// will attempt merge setcc and brc instructions into brcc's.
40 class SelectionDAGLegalize {
44 /// LegalizeAction - This enum indicates what action we should take for each
45 /// value type the can occur in the program.
47 Legal, // The target natively supports this value type.
48 Promote, // This should be promoted to the next larger type.
49 Expand, // This integer type should be broken into smaller pieces.
52 /// ValueTypeActions - This is a bitvector that contains two bits for each
53 /// value type, where the two bits correspond to the LegalizeAction enum.
54 /// This can be queried with "getTypeAction(VT)".
55 unsigned ValueTypeActions;
57 /// NeedsAnotherIteration - This is set when we expand a large integer
58 /// operation into smaller integer operations, but the smaller operations are
59 /// not set. This occurs only rarely in practice, for targets that don't have
60 /// 32-bit or larger integer registers.
61 bool NeedsAnotherIteration;
63 /// LegalizedNodes - For nodes that are of legal width, and that have more
64 /// than one use, this map indicates what regularized operand to use. This
65 /// allows us to avoid legalizing the same thing more than once.
66 std::map<SDOperand, SDOperand> LegalizedNodes;
68 /// PromotedNodes - For nodes that are below legal width, and that have more
69 /// than one use, this map indicates what promoted value to use. This allows
70 /// us to avoid promoting the same thing more than once.
71 std::map<SDOperand, SDOperand> PromotedNodes;
73 /// ExpandedNodes - For nodes that need to be expanded, and which have more
74 /// than one use, this map indicates which which operands are the expanded
75 /// version of the input. This allows us to avoid expanding the same node
77 std::map<SDOperand, std::pair<SDOperand, SDOperand> > ExpandedNodes;
79 void AddLegalizedOperand(SDOperand From, SDOperand To) {
80 bool isNew = LegalizedNodes.insert(std::make_pair(From, To)).second;
81 assert(isNew && "Got into the map somehow?");
83 void AddPromotedOperand(SDOperand From, SDOperand To) {
84 bool isNew = PromotedNodes.insert(std::make_pair(From, To)).second;
85 assert(isNew && "Got into the map somehow?");
90 SelectionDAGLegalize(SelectionDAG &DAG);
92 /// Run - While there is still lowering to do, perform a pass over the DAG.
93 /// Most regularization can be done in a single pass, but targets that require
94 /// large values to be split into registers multiple times (e.g. i64 -> 4x
95 /// i16) require iteration for these values (the first iteration will demote
96 /// to i32, the second will demote to i16).
99 NeedsAnotherIteration = false;
101 } while (NeedsAnotherIteration);
104 /// getTypeAction - Return how we should legalize values of this type, either
105 /// it is already legal or we need to expand it into multiple registers of
106 /// smaller integer type, or we need to promote it to a larger type.
107 LegalizeAction getTypeAction(MVT::ValueType VT) const {
108 return (LegalizeAction)((ValueTypeActions >> (2*VT)) & 3);
111 /// isTypeLegal - Return true if this type is legal on this target.
113 bool isTypeLegal(MVT::ValueType VT) const {
114 return getTypeAction(VT) == Legal;
120 SDOperand LegalizeOp(SDOperand O);
121 void ExpandOp(SDOperand O, SDOperand &Lo, SDOperand &Hi);
122 SDOperand PromoteOp(SDOperand O);
124 SDOperand ExpandLibCall(const char *Name, SDNode *Node,
126 SDOperand ExpandIntToFP(bool isSigned, MVT::ValueType DestTy,
129 SDOperand ExpandLegalINT_TO_FP(bool isSigned,
131 MVT::ValueType DestVT);
132 SDOperand PromoteLegalINT_TO_FP(SDOperand LegalOp, MVT::ValueType DestVT,
134 SDOperand PromoteLegalFP_TO_INT(SDOperand LegalOp, MVT::ValueType DestVT,
137 bool ExpandShift(unsigned Opc, SDOperand Op, SDOperand Amt,
138 SDOperand &Lo, SDOperand &Hi);
139 void ExpandShiftParts(unsigned NodeOp, SDOperand Op, SDOperand Amt,
140 SDOperand &Lo, SDOperand &Hi);
141 void ExpandByParts(unsigned NodeOp, SDOperand LHS, SDOperand RHS,
142 SDOperand &Lo, SDOperand &Hi);
144 void SpliceCallInto(const SDOperand &CallResult, SDNode *OutChain);
146 SDOperand getIntPtrConstant(uint64_t Val) {
147 return DAG.getConstant(Val, TLI.getPointerTy());
153 SelectionDAGLegalize::SelectionDAGLegalize(SelectionDAG &dag)
154 : TLI(dag.getTargetLoweringInfo()), DAG(dag),
155 ValueTypeActions(TLI.getValueTypeActions()) {
156 assert(MVT::LAST_VALUETYPE <= 16 &&
157 "Too many value types for ValueTypeActions to hold!");
160 /// ExpandLegalINT_TO_FP - This function is responsible for legalizing a
161 /// INT_TO_FP operation of the specified operand when the target requests that
162 /// we expand it. At this point, we know that the result and operand types are
163 /// legal for the target.
164 SDOperand SelectionDAGLegalize::ExpandLegalINT_TO_FP(bool isSigned,
166 MVT::ValueType DestVT) {
167 if (Op0.getValueType() == MVT::i32) {
168 // simple 32-bit [signed|unsigned] integer to float/double expansion
170 // get the stack frame index of a 8 byte buffer
171 MachineFunction &MF = DAG.getMachineFunction();
172 int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8);
173 // get address of 8 byte buffer
174 SDOperand StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy());
175 // word offset constant for Hi/Lo address computation
176 SDOperand WordOff = DAG.getConstant(sizeof(int), TLI.getPointerTy());
177 // set up Hi and Lo (into buffer) address based on endian
179 if (TLI.isLittleEndian()) {
180 Hi = DAG.getNode(ISD::ADD, TLI.getPointerTy(), StackSlot, WordOff);
184 Lo = DAG.getNode(ISD::ADD, TLI.getPointerTy(), StackSlot, WordOff);
186 // if signed map to unsigned space
189 // constant used to invert sign bit (signed to unsigned mapping)
190 SDOperand SignBit = DAG.getConstant(0x80000000u, MVT::i32);
191 Op0Mapped = DAG.getNode(ISD::XOR, MVT::i32, Op0, SignBit);
195 // store the lo of the constructed double - based on integer input
196 SDOperand Store1 = DAG.getNode(ISD::STORE, MVT::Other, DAG.getEntryNode(),
197 Op0Mapped, Lo, DAG.getSrcValue(NULL));
198 // initial hi portion of constructed double
199 SDOperand InitialHi = DAG.getConstant(0x43300000u, MVT::i32);
200 // store the hi of the constructed double - biased exponent
201 SDOperand Store2 = DAG.getNode(ISD::STORE, MVT::Other, Store1,
202 InitialHi, Hi, DAG.getSrcValue(NULL));
203 // load the constructed double
204 SDOperand Load = DAG.getLoad(MVT::f64, Store2, StackSlot,
205 DAG.getSrcValue(NULL));
206 // FP constant to bias correct the final result
207 SDOperand Bias = DAG.getConstantFP(isSigned ?
208 BitsToDouble(0x4330000080000000ULL)
209 : BitsToDouble(0x4330000000000000ULL),
212 SDOperand Sub = DAG.getNode(ISD::FSUB, MVT::f64, Load, Bias);
215 // handle final rounding
216 if (DestVT == MVT::f64) {
220 // if f32 then cast to f32
221 Result = DAG.getNode(ISD::FP_ROUND, MVT::f32, Sub);
223 NeedsAnotherIteration = true;
226 assert(!isSigned && "Legalize cannot Expand SINT_TO_FP for i64 yet");
227 SDOperand Tmp1 = DAG.getNode(ISD::SINT_TO_FP, DestVT, Op0);
229 SDOperand SignSet = DAG.getSetCC(TLI.getSetCCResultTy(), Op0,
230 DAG.getConstant(0, Op0.getValueType()),
232 SDOperand Zero = getIntPtrConstant(0), Four = getIntPtrConstant(4);
233 SDOperand CstOffset = DAG.getNode(ISD::SELECT, Zero.getValueType(),
234 SignSet, Four, Zero);
236 // If the sign bit of the integer is set, the large number will be treated
237 // as a negative number. To counteract this, the dynamic code adds an
238 // offset depending on the data type.
240 switch (Op0.getValueType()) {
241 default: assert(0 && "Unsupported integer type!");
242 case MVT::i8 : FF = 0x43800000ULL; break; // 2^8 (as a float)
243 case MVT::i16: FF = 0x47800000ULL; break; // 2^16 (as a float)
244 case MVT::i32: FF = 0x4F800000ULL; break; // 2^32 (as a float)
245 case MVT::i64: FF = 0x5F800000ULL; break; // 2^64 (as a float)
247 if (TLI.isLittleEndian()) FF <<= 32;
248 static Constant *FudgeFactor = ConstantUInt::get(Type::ULongTy, FF);
250 SDOperand CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy());
251 CPIdx = DAG.getNode(ISD::ADD, TLI.getPointerTy(), CPIdx, CstOffset);
252 SDOperand FudgeInReg;
253 if (DestVT == MVT::f32)
254 FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx,
255 DAG.getSrcValue(NULL));
257 assert(DestVT == MVT::f64 && "Unexpected conversion");
258 FudgeInReg = LegalizeOp(DAG.getExtLoad(ISD::EXTLOAD, MVT::f64,
259 DAG.getEntryNode(), CPIdx,
260 DAG.getSrcValue(NULL), MVT::f32));
263 NeedsAnotherIteration = true;
264 return DAG.getNode(ISD::FADD, DestVT, Tmp1, FudgeInReg);
267 /// PromoteLegalINT_TO_FP - This function is responsible for legalizing a
268 /// *INT_TO_FP operation of the specified operand when the target requests that
269 /// we promote it. At this point, we know that the result and operand types are
270 /// legal for the target, and that there is a legal UINT_TO_FP or SINT_TO_FP
271 /// operation that takes a larger input.
272 SDOperand SelectionDAGLegalize::PromoteLegalINT_TO_FP(SDOperand LegalOp,
273 MVT::ValueType DestVT,
275 // First step, figure out the appropriate *INT_TO_FP operation to use.
276 MVT::ValueType NewInTy = LegalOp.getValueType();
278 unsigned OpToUse = 0;
280 // Scan for the appropriate larger type to use.
282 NewInTy = (MVT::ValueType)(NewInTy+1);
283 assert(MVT::isInteger(NewInTy) && "Ran out of possibilities!");
285 // If the target supports SINT_TO_FP of this type, use it.
286 switch (TLI.getOperationAction(ISD::SINT_TO_FP, NewInTy)) {
288 case TargetLowering::Legal:
289 if (!TLI.isTypeLegal(NewInTy))
290 break; // Can't use this datatype.
292 case TargetLowering::Custom:
293 OpToUse = ISD::SINT_TO_FP;
297 if (isSigned) continue;
299 // If the target supports UINT_TO_FP of this type, use it.
300 switch (TLI.getOperationAction(ISD::UINT_TO_FP, NewInTy)) {
302 case TargetLowering::Legal:
303 if (!TLI.isTypeLegal(NewInTy))
304 break; // Can't use this datatype.
306 case TargetLowering::Custom:
307 OpToUse = ISD::UINT_TO_FP;
312 // Otherwise, try a larger type.
315 // Make sure to legalize any nodes we create here in the next pass.
316 NeedsAnotherIteration = true;
318 // Okay, we found the operation and type to use. Zero extend our input to the
319 // desired type then run the operation on it.
320 return DAG.getNode(OpToUse, DestVT,
321 DAG.getNode(isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND,
325 /// PromoteLegalFP_TO_INT - This function is responsible for legalizing a
326 /// FP_TO_*INT operation of the specified operand when the target requests that
327 /// we promote it. At this point, we know that the result and operand types are
328 /// legal for the target, and that there is a legal FP_TO_UINT or FP_TO_SINT
329 /// operation that returns a larger result.
330 SDOperand SelectionDAGLegalize::PromoteLegalFP_TO_INT(SDOperand LegalOp,
331 MVT::ValueType DestVT,
333 // First step, figure out the appropriate FP_TO*INT operation to use.
334 MVT::ValueType NewOutTy = DestVT;
336 unsigned OpToUse = 0;
338 // Scan for the appropriate larger type to use.
340 NewOutTy = (MVT::ValueType)(NewOutTy+1);
341 assert(MVT::isInteger(NewOutTy) && "Ran out of possibilities!");
343 // If the target supports FP_TO_SINT returning this type, use it.
344 switch (TLI.getOperationAction(ISD::FP_TO_SINT, NewOutTy)) {
346 case TargetLowering::Legal:
347 if (!TLI.isTypeLegal(NewOutTy))
348 break; // Can't use this datatype.
350 case TargetLowering::Custom:
351 OpToUse = ISD::FP_TO_SINT;
356 // If the target supports FP_TO_UINT of this type, use it.
357 switch (TLI.getOperationAction(ISD::FP_TO_UINT, NewOutTy)) {
359 case TargetLowering::Legal:
360 if (!TLI.isTypeLegal(NewOutTy))
361 break; // Can't use this datatype.
363 case TargetLowering::Custom:
364 OpToUse = ISD::FP_TO_UINT;
369 // Otherwise, try a larger type.
372 // Make sure to legalize any nodes we create here in the next pass.
373 NeedsAnotherIteration = true;
375 // Okay, we found the operation and type to use. Truncate the result of the
376 // extended FP_TO_*INT operation to the desired size.
377 return DAG.getNode(ISD::TRUNCATE, DestVT,
378 DAG.getNode(OpToUse, NewOutTy, LegalOp));
381 /// ComputeTopDownOrdering - Add the specified node to the Order list if it has
382 /// not been visited yet and if all of its operands have already been visited.
383 static void ComputeTopDownOrdering(SDNode *N, std::vector<SDNode*> &Order,
384 std::map<SDNode*, unsigned> &Visited) {
385 if (++Visited[N] != N->getNumOperands())
386 return; // Haven't visited all operands yet
390 if (N->hasOneUse()) { // Tail recurse in common case.
391 ComputeTopDownOrdering(*N->use_begin(), Order, Visited);
395 // Now that we have N in, add anything that uses it if all of their operands
398 for (SDNode::use_iterator UI = N->use_begin(), E = N->use_end(); UI != E;++UI)
399 ComputeTopDownOrdering(*UI, Order, Visited);
403 void SelectionDAGLegalize::LegalizeDAG() {
404 // The legalize process is inherently a bottom-up recursive process (users
405 // legalize their uses before themselves). Given infinite stack space, we
406 // could just start legalizing on the root and traverse the whole graph. In
407 // practice however, this causes us to run out of stack space on large basic
408 // blocks. To avoid this problem, compute an ordering of the nodes where each
409 // node is only legalized after all of its operands are legalized.
410 std::map<SDNode*, unsigned> Visited;
411 std::vector<SDNode*> Order;
413 // Compute ordering from all of the leaves in the graphs, those (like the
414 // entry node) that have no operands.
415 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(),
416 E = DAG.allnodes_end(); I != E; ++I) {
417 if ((*I)->getNumOperands() == 0) {
418 Visited[*I] = 0 - 1U;
419 ComputeTopDownOrdering(*I, Order, Visited);
423 assert(Order.size() == Visited.size() && Order.size() == DAG.allnodes_size()&&
424 "Error: DAG is cyclic!");
427 for (unsigned i = 0, e = Order.size(); i != e; ++i) {
428 SDNode *N = Order[i];
429 switch (getTypeAction(N->getValueType(0))) {
430 default: assert(0 && "Bad type action!");
432 LegalizeOp(SDOperand(N, 0));
435 PromoteOp(SDOperand(N, 0));
439 ExpandOp(SDOperand(N, 0), X, Y);
445 // Finally, it's possible the root changed. Get the new root.
446 SDOperand OldRoot = DAG.getRoot();
447 assert(LegalizedNodes.count(OldRoot) && "Root didn't get legalized?");
448 DAG.setRoot(LegalizedNodes[OldRoot]);
450 ExpandedNodes.clear();
451 LegalizedNodes.clear();
452 PromotedNodes.clear();
454 // Remove dead nodes now.
455 DAG.RemoveDeadNodes(OldRoot.Val);
458 SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
459 assert(isTypeLegal(Op.getValueType()) &&
460 "Caller should expand or promote operands that are not legal!");
461 SDNode *Node = Op.Val;
463 // If this operation defines any values that cannot be represented in a
464 // register on this target, make sure to expand or promote them.
465 if (Node->getNumValues() > 1) {
466 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
467 switch (getTypeAction(Node->getValueType(i))) {
468 case Legal: break; // Nothing to do.
471 ExpandOp(Op.getValue(i), T1, T2);
472 assert(LegalizedNodes.count(Op) &&
473 "Expansion didn't add legal operands!");
474 return LegalizedNodes[Op];
477 PromoteOp(Op.getValue(i));
478 assert(LegalizedNodes.count(Op) &&
479 "Expansion didn't add legal operands!");
480 return LegalizedNodes[Op];
484 // Note that LegalizeOp may be reentered even from single-use nodes, which
485 // means that we always must cache transformed nodes.
486 std::map<SDOperand, SDOperand>::iterator I = LegalizedNodes.find(Op);
487 if (I != LegalizedNodes.end()) return I->second;
489 SDOperand Tmp1, Tmp2, Tmp3, Tmp4;
491 SDOperand Result = Op;
493 switch (Node->getOpcode()) {
495 if (Node->getOpcode() >= ISD::BUILTIN_OP_END) {
496 // If this is a target node, legalize it by legalizing the operands then
497 // passing it through.
498 std::vector<SDOperand> Ops;
499 bool Changed = false;
500 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
501 Ops.push_back(LegalizeOp(Node->getOperand(i)));
502 Changed = Changed || Node->getOperand(i) != Ops.back();
505 if (Node->getNumValues() == 1)
506 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Ops);
508 std::vector<MVT::ValueType> VTs(Node->value_begin(),
510 Result = DAG.getNode(Node->getOpcode(), VTs, Ops);
513 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
514 AddLegalizedOperand(Op.getValue(i), Result.getValue(i));
515 return Result.getValue(Op.ResNo);
517 // Otherwise this is an unhandled builtin node. splat.
518 std::cerr << "NODE: "; Node->dump(); std::cerr << "\n";
519 assert(0 && "Do not know how to legalize this operator!");
521 case ISD::EntryToken:
522 case ISD::FrameIndex:
523 case ISD::TargetFrameIndex:
525 case ISD::TargetConstant:
526 case ISD::GlobalAddress:
527 case ISD::ExternalSymbol:
528 case ISD::ConstantPool: // Nothing to do.
529 case ISD::BasicBlock:
533 assert(isTypeLegal(Node->getValueType(0)) && "This must be legal!");
535 case ISD::AssertSext:
536 case ISD::AssertZext:
537 Tmp1 = LegalizeOp(Node->getOperand(0));
538 if (Tmp1 != Node->getOperand(0))
539 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1,
540 Node->getOperand(1));
542 case ISD::CopyFromReg:
543 Tmp1 = LegalizeOp(Node->getOperand(0));
544 if (Tmp1 != Node->getOperand(0))
545 Result = DAG.getCopyFromReg(Tmp1,
546 cast<RegisterSDNode>(Node->getOperand(1))->getReg(),
547 Node->getValueType(0));
549 Result = Op.getValue(0);
551 // Since CopyFromReg produces two values, make sure to remember that we
552 // legalized both of them.
553 AddLegalizedOperand(Op.getValue(0), Result);
554 AddLegalizedOperand(Op.getValue(1), Result.getValue(1));
555 return Result.getValue(Op.ResNo);
556 case ISD::ImplicitDef:
557 Tmp1 = LegalizeOp(Node->getOperand(0));
558 if (Tmp1 != Node->getOperand(0))
559 Result = DAG.getNode(ISD::ImplicitDef, MVT::Other,
560 Tmp1, Node->getOperand(1));
563 MVT::ValueType VT = Op.getValueType();
564 switch (TLI.getOperationAction(ISD::UNDEF, VT)) {
565 default: assert(0 && "This action is not supported yet!");
566 case TargetLowering::Expand:
567 case TargetLowering::Promote:
568 if (MVT::isInteger(VT))
569 Result = DAG.getConstant(0, VT);
570 else if (MVT::isFloatingPoint(VT))
571 Result = DAG.getConstantFP(0, VT);
573 assert(0 && "Unknown value type!");
575 case TargetLowering::Legal:
581 // We know we don't need to expand constants here, constants only have one
582 // value and we check that it is fine above.
584 // FIXME: Maybe we should handle things like targets that don't support full
585 // 32-bit immediates?
587 case ISD::ConstantFP: {
588 // Spill FP immediates to the constant pool if the target cannot directly
589 // codegen them. Targets often have some immediate values that can be
590 // efficiently generated into an FP register without a load. We explicitly
591 // leave these constants as ConstantFP nodes for the target to deal with.
593 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node);
595 // Check to see if this FP immediate is already legal.
596 bool isLegal = false;
597 for (TargetLowering::legal_fpimm_iterator I = TLI.legal_fpimm_begin(),
598 E = TLI.legal_fpimm_end(); I != E; ++I)
599 if (CFP->isExactlyValue(*I)) {
605 // Otherwise we need to spill the constant to memory.
608 // If a FP immediate is precise when represented as a float, we put it
609 // into the constant pool as a float, even if it's is statically typed
611 MVT::ValueType VT = CFP->getValueType(0);
612 bool isDouble = VT == MVT::f64;
613 ConstantFP *LLVMC = ConstantFP::get(isDouble ? Type::DoubleTy :
614 Type::FloatTy, CFP->getValue());
615 if (isDouble && CFP->isExactlyValue((float)CFP->getValue()) &&
616 // Only do this if the target has a native EXTLOAD instruction from
618 TLI.isOperationLegal(ISD::EXTLOAD, MVT::f32)) {
619 LLVMC = cast<ConstantFP>(ConstantExpr::getCast(LLVMC, Type::FloatTy));
624 SDOperand CPIdx = DAG.getConstantPool(LLVMC, TLI.getPointerTy());
626 Result = DAG.getExtLoad(ISD::EXTLOAD, MVT::f64, DAG.getEntryNode(),
627 CPIdx, DAG.getSrcValue(NULL), MVT::f32);
629 Result = DAG.getLoad(VT, DAG.getEntryNode(), CPIdx,
630 DAG.getSrcValue(NULL));
635 case ISD::TokenFactor: {
636 std::vector<SDOperand> Ops;
637 bool Changed = false;
638 // Legalize the operands
639 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
640 SDOperand Op = Node->getOperand(i);
641 Ops.push_back(LegalizeOp(Op));
642 Changed |= Ops[i] != Op;
645 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, Ops);
649 case ISD::CALLSEQ_START:
650 case ISD::CALLSEQ_END:
651 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
652 // Do not try to legalize the target-specific arguments (#1+)
653 Tmp2 = Node->getOperand(0);
655 Node->setAdjCallChain(Tmp1);
657 // Note that we do not create new CALLSEQ_DOWN/UP nodes here. These
658 // nodes are treated specially and are mutated in place. This makes the dag
659 // legalization process more efficient and also makes libcall insertion
662 case ISD::DYNAMIC_STACKALLOC:
663 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
664 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the size.
665 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the alignment.
666 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1) ||
667 Tmp3 != Node->getOperand(2)) {
668 std::vector<MVT::ValueType> VTs(Node->value_begin(), Node->value_end());
669 std::vector<SDOperand> Ops;
670 Ops.push_back(Tmp1); Ops.push_back(Tmp2); Ops.push_back(Tmp3);
671 Result = DAG.getNode(ISD::DYNAMIC_STACKALLOC, VTs, Ops);
673 Result = Op.getValue(0);
675 // Since this op produces two values, make sure to remember that we
676 // legalized both of them.
677 AddLegalizedOperand(SDOperand(Node, 0), Result);
678 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
679 return Result.getValue(Op.ResNo);
683 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
684 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the callee.
686 bool Changed = false;
687 std::vector<SDOperand> Ops;
688 for (unsigned i = 2, e = Node->getNumOperands(); i != e; ++i) {
689 Ops.push_back(LegalizeOp(Node->getOperand(i)));
690 Changed |= Ops.back() != Node->getOperand(i);
693 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1) || Changed) {
694 std::vector<MVT::ValueType> RetTyVTs;
695 RetTyVTs.reserve(Node->getNumValues());
696 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
697 RetTyVTs.push_back(Node->getValueType(i));
698 Result = SDOperand(DAG.getCall(RetTyVTs, Tmp1, Tmp2, Ops,
699 Node->getOpcode() == ISD::TAILCALL), 0);
701 Result = Result.getValue(0);
703 // Since calls produce multiple values, make sure to remember that we
704 // legalized all of them.
705 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
706 AddLegalizedOperand(SDOperand(Node, i), Result.getValue(i));
707 return Result.getValue(Op.ResNo);
710 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
711 if (Tmp1 != Node->getOperand(0))
712 Result = DAG.getNode(ISD::BR, MVT::Other, Tmp1, Node->getOperand(1));
716 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
718 switch (getTypeAction(Node->getOperand(1).getValueType())) {
719 case Expand: assert(0 && "It's impossible to expand bools");
721 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the condition.
724 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the condition.
728 switch (TLI.getOperationAction(ISD::BRCOND, MVT::Other)) {
729 default: assert(0 && "This action is not supported yet!");
730 case TargetLowering::Expand:
731 // Expand brcond's setcc into its constituent parts and create a BR_CC
733 if (Tmp2.getOpcode() == ISD::SETCC) {
734 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1, Tmp2.getOperand(2),
735 Tmp2.getOperand(0), Tmp2.getOperand(1),
736 Node->getOperand(2));
738 // Make sure the condition is either zero or one. It may have been
739 // promoted from something else.
740 Tmp2 = DAG.getZeroExtendInReg(Tmp2, MVT::i1);
742 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1,
743 DAG.getCondCode(ISD::SETNE), Tmp2,
744 DAG.getConstant(0, Tmp2.getValueType()),
745 Node->getOperand(2));
748 case TargetLowering::Legal:
749 // Basic block destination (Op#2) is always legal.
750 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1))
751 Result = DAG.getNode(ISD::BRCOND, MVT::Other, Tmp1, Tmp2,
752 Node->getOperand(2));
757 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
759 if (isTypeLegal(Node->getOperand(2).getValueType())) {
760 Tmp2 = LegalizeOp(Node->getOperand(2)); // LHS
761 Tmp3 = LegalizeOp(Node->getOperand(3)); // RHS
762 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(2) ||
763 Tmp3 != Node->getOperand(3)) {
764 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1, Node->getOperand(1),
765 Tmp2, Tmp3, Node->getOperand(4));
769 Tmp2 = LegalizeOp(DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(),
770 Node->getOperand(2), // LHS
771 Node->getOperand(3), // RHS
772 Node->getOperand(1)));
773 // If we get a SETCC back from legalizing the SETCC node we just
774 // created, then use its LHS, RHS, and CC directly in creating a new
775 // node. Otherwise, select between the true and false value based on
776 // comparing the result of the legalized with zero.
777 if (Tmp2.getOpcode() == ISD::SETCC) {
778 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1, Tmp2.getOperand(2),
779 Tmp2.getOperand(0), Tmp2.getOperand(1),
780 Node->getOperand(4));
782 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1,
783 DAG.getCondCode(ISD::SETNE),
784 Tmp2, DAG.getConstant(0, Tmp2.getValueType()),
785 Node->getOperand(4));
789 case ISD::BRCONDTWOWAY:
790 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
791 switch (getTypeAction(Node->getOperand(1).getValueType())) {
792 case Expand: assert(0 && "It's impossible to expand bools");
794 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the condition.
797 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the condition.
800 // If this target does not support BRCONDTWOWAY, lower it to a BRCOND/BR
802 switch (TLI.getOperationAction(ISD::BRCONDTWOWAY, MVT::Other)) {
803 case TargetLowering::Promote:
804 default: assert(0 && "This action is not supported yet!");
805 case TargetLowering::Legal:
806 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1)) {
807 std::vector<SDOperand> Ops;
810 Ops.push_back(Node->getOperand(2));
811 Ops.push_back(Node->getOperand(3));
812 Result = DAG.getNode(ISD::BRCONDTWOWAY, MVT::Other, Ops);
815 case TargetLowering::Expand:
816 // If BRTWOWAY_CC is legal for this target, then simply expand this node
817 // to that. Otherwise, skip BRTWOWAY_CC and expand directly to a
819 if (TLI.isOperationLegal(ISD::BRTWOWAY_CC, MVT::Other)) {
820 if (Tmp2.getOpcode() == ISD::SETCC) {
821 Result = DAG.getBR2Way_CC(Tmp1, Tmp2.getOperand(2),
822 Tmp2.getOperand(0), Tmp2.getOperand(1),
823 Node->getOperand(2), Node->getOperand(3));
825 Result = DAG.getBR2Way_CC(Tmp1, DAG.getCondCode(ISD::SETNE), Tmp2,
826 DAG.getConstant(0, Tmp2.getValueType()),
827 Node->getOperand(2), Node->getOperand(3));
830 Result = DAG.getNode(ISD::BRCOND, MVT::Other, Tmp1, Tmp2,
831 Node->getOperand(2));
832 Result = DAG.getNode(ISD::BR, MVT::Other, Result, Node->getOperand(3));
837 case ISD::BRTWOWAY_CC:
838 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
839 if (isTypeLegal(Node->getOperand(2).getValueType())) {
840 Tmp2 = LegalizeOp(Node->getOperand(2)); // LHS
841 Tmp3 = LegalizeOp(Node->getOperand(3)); // RHS
842 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(2) ||
843 Tmp3 != Node->getOperand(3)) {
844 Result = DAG.getBR2Way_CC(Tmp1, Node->getOperand(1), Tmp2, Tmp3,
845 Node->getOperand(4), Node->getOperand(5));
849 Tmp2 = LegalizeOp(DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(),
850 Node->getOperand(2), // LHS
851 Node->getOperand(3), // RHS
852 Node->getOperand(1)));
853 // If this target does not support BRTWOWAY_CC, lower it to a BRCOND/BR
855 switch (TLI.getOperationAction(ISD::BRTWOWAY_CC, MVT::Other)) {
856 default: assert(0 && "This action is not supported yet!");
857 case TargetLowering::Legal:
858 // If we get a SETCC back from legalizing the SETCC node we just
859 // created, then use its LHS, RHS, and CC directly in creating a new
860 // node. Otherwise, select between the true and false value based on
861 // comparing the result of the legalized with zero.
862 if (Tmp2.getOpcode() == ISD::SETCC) {
863 Result = DAG.getBR2Way_CC(Tmp1, Tmp2.getOperand(2),
864 Tmp2.getOperand(0), Tmp2.getOperand(1),
865 Node->getOperand(4), Node->getOperand(5));
867 Result = DAG.getBR2Way_CC(Tmp1, DAG.getCondCode(ISD::SETNE), Tmp2,
868 DAG.getConstant(0, Tmp2.getValueType()),
869 Node->getOperand(4), Node->getOperand(5));
872 case TargetLowering::Expand:
873 Result = DAG.getNode(ISD::BRCOND, MVT::Other, Tmp1, Tmp2,
874 Node->getOperand(4));
875 Result = DAG.getNode(ISD::BR, MVT::Other, Result, Node->getOperand(5));
881 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
882 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
884 if (Tmp1 != Node->getOperand(0) ||
885 Tmp2 != Node->getOperand(1))
886 Result = DAG.getLoad(Node->getValueType(0), Tmp1, Tmp2,
887 Node->getOperand(2));
889 Result = SDOperand(Node, 0);
891 // Since loads produce two values, make sure to remember that we legalized
893 AddLegalizedOperand(SDOperand(Node, 0), Result);
894 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
895 return Result.getValue(Op.ResNo);
899 case ISD::ZEXTLOAD: {
900 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
901 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
903 MVT::ValueType SrcVT = cast<VTSDNode>(Node->getOperand(3))->getVT();
904 switch (TLI.getOperationAction(Node->getOpcode(), SrcVT)) {
905 default: assert(0 && "This action is not supported yet!");
906 case TargetLowering::Promote:
907 assert(SrcVT == MVT::i1 && "Can only promote EXTLOAD from i1 -> i8!");
908 Result = DAG.getExtLoad(Node->getOpcode(), Node->getValueType(0),
909 Tmp1, Tmp2, Node->getOperand(2), MVT::i8);
910 // Since loads produce two values, make sure to remember that we legalized
912 AddLegalizedOperand(SDOperand(Node, 0), Result);
913 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
914 return Result.getValue(Op.ResNo);
916 case TargetLowering::Legal:
917 if (Tmp1 != Node->getOperand(0) ||
918 Tmp2 != Node->getOperand(1))
919 Result = DAG.getExtLoad(Node->getOpcode(), Node->getValueType(0),
920 Tmp1, Tmp2, Node->getOperand(2), SrcVT);
922 Result = SDOperand(Node, 0);
924 // Since loads produce two values, make sure to remember that we legalized
926 AddLegalizedOperand(SDOperand(Node, 0), Result);
927 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
928 return Result.getValue(Op.ResNo);
929 case TargetLowering::Expand:
930 //f64 = EXTLOAD f32 should expand to LOAD, FP_EXTEND
931 if (SrcVT == MVT::f32 && Node->getValueType(0) == MVT::f64) {
932 SDOperand Load = DAG.getLoad(SrcVT, Tmp1, Tmp2, Node->getOperand(2));
933 Result = DAG.getNode(ISD::FP_EXTEND, Node->getValueType(0), Load);
935 return Load.getValue(1);
938 assert(Node->getOpcode() != ISD::EXTLOAD &&
939 "EXTLOAD should always be supported!");
940 // Turn the unsupported load into an EXTLOAD followed by an explicit
941 // zero/sign extend inreg.
942 Result = DAG.getExtLoad(ISD::EXTLOAD, Node->getValueType(0),
943 Tmp1, Tmp2, Node->getOperand(2), SrcVT);
945 if (Node->getOpcode() == ISD::SEXTLOAD)
946 ValRes = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(),
947 Result, DAG.getValueType(SrcVT));
949 ValRes = DAG.getZeroExtendInReg(Result, SrcVT);
950 AddLegalizedOperand(SDOperand(Node, 0), ValRes);
951 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
953 return Result.getValue(1);
956 assert(0 && "Unreachable");
958 case ISD::EXTRACT_ELEMENT:
959 // Get both the low and high parts.
960 ExpandOp(Node->getOperand(0), Tmp1, Tmp2);
961 if (cast<ConstantSDNode>(Node->getOperand(1))->getValue())
962 Result = Tmp2; // 1 -> Hi
964 Result = Tmp1; // 0 -> Lo
968 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
970 assert(isTypeLegal(Node->getOperand(2).getValueType()) &&
971 "Register type must be legal!");
972 // Legalize the incoming value (must be legal).
973 Tmp2 = LegalizeOp(Node->getOperand(2));
974 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(2))
975 Result = DAG.getNode(ISD::CopyToReg, MVT::Other, Tmp1,
976 Node->getOperand(1), Tmp2);
980 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
981 switch (Node->getNumOperands()) {
983 switch (getTypeAction(Node->getOperand(1).getValueType())) {
985 Tmp2 = LegalizeOp(Node->getOperand(1));
986 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1))
987 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Tmp2);
991 ExpandOp(Node->getOperand(1), Lo, Hi);
992 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Hi);
996 Tmp2 = PromoteOp(Node->getOperand(1));
997 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Tmp2);
1002 if (Tmp1 != Node->getOperand(0))
1003 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1);
1005 default: { // ret <values>
1006 std::vector<SDOperand> NewValues;
1007 NewValues.push_back(Tmp1);
1008 for (unsigned i = 1, e = Node->getNumOperands(); i != e; ++i)
1009 switch (getTypeAction(Node->getOperand(i).getValueType())) {
1011 NewValues.push_back(LegalizeOp(Node->getOperand(i)));
1015 ExpandOp(Node->getOperand(i), Lo, Hi);
1016 NewValues.push_back(Lo);
1017 NewValues.push_back(Hi);
1021 assert(0 && "Can't promote multiple return value yet!");
1023 Result = DAG.getNode(ISD::RET, MVT::Other, NewValues);
1029 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1030 Tmp2 = LegalizeOp(Node->getOperand(2)); // Legalize the pointer.
1032 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr'
1033 if (ConstantFPSDNode *CFP =dyn_cast<ConstantFPSDNode>(Node->getOperand(1))){
1034 if (CFP->getValueType(0) == MVT::f32) {
1035 Result = DAG.getNode(ISD::STORE, MVT::Other, Tmp1,
1036 DAG.getConstant(FloatToBits(CFP->getValue()),
1039 Node->getOperand(3));
1041 assert(CFP->getValueType(0) == MVT::f64 && "Unknown FP type!");
1042 Result = DAG.getNode(ISD::STORE, MVT::Other, Tmp1,
1043 DAG.getConstant(DoubleToBits(CFP->getValue()),
1046 Node->getOperand(3));
1051 switch (getTypeAction(Node->getOperand(1).getValueType())) {
1053 SDOperand Val = LegalizeOp(Node->getOperand(1));
1054 if (Val != Node->getOperand(1) || Tmp1 != Node->getOperand(0) ||
1055 Tmp2 != Node->getOperand(2))
1056 Result = DAG.getNode(ISD::STORE, MVT::Other, Tmp1, Val, Tmp2,
1057 Node->getOperand(3));
1061 // Truncate the value and store the result.
1062 Tmp3 = PromoteOp(Node->getOperand(1));
1063 Result = DAG.getNode(ISD::TRUNCSTORE, MVT::Other, Tmp1, Tmp3, Tmp2,
1064 Node->getOperand(3),
1065 DAG.getValueType(Node->getOperand(1).getValueType()));
1070 ExpandOp(Node->getOperand(1), Lo, Hi);
1072 if (!TLI.isLittleEndian())
1075 Lo = DAG.getNode(ISD::STORE, MVT::Other, Tmp1, Lo, Tmp2,
1076 Node->getOperand(3));
1077 unsigned IncrementSize = MVT::getSizeInBits(Hi.getValueType())/8;
1078 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2,
1079 getIntPtrConstant(IncrementSize));
1080 assert(isTypeLegal(Tmp2.getValueType()) &&
1081 "Pointers must be legal!");
1082 //Again, claiming both parts of the store came form the same Instr
1083 Hi = DAG.getNode(ISD::STORE, MVT::Other, Tmp1, Hi, Tmp2,
1084 Node->getOperand(3));
1085 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi);
1090 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1091 if (Tmp1 != Node->getOperand(0))
1092 Result = DAG.getNode(ISD::PCMARKER, MVT::Other, Tmp1,Node->getOperand(1));
1094 case ISD::TRUNCSTORE:
1095 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1096 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the pointer.
1098 switch (getTypeAction(Node->getOperand(1).getValueType())) {
1100 Tmp2 = LegalizeOp(Node->getOperand(1));
1102 // The only promote case we handle is TRUNCSTORE:i1 X into
1103 // -> TRUNCSTORE:i8 (and X, 1)
1104 if (cast<VTSDNode>(Node->getOperand(4))->getVT() == MVT::i1 &&
1105 TLI.getOperationAction(ISD::TRUNCSTORE, MVT::i1) ==
1106 TargetLowering::Promote) {
1107 // Promote the bool to a mask then store.
1108 Tmp2 = DAG.getNode(ISD::AND, Tmp2.getValueType(), Tmp2,
1109 DAG.getConstant(1, Tmp2.getValueType()));
1110 Result = DAG.getNode(ISD::TRUNCSTORE, MVT::Other, Tmp1, Tmp2, Tmp3,
1111 Node->getOperand(3), DAG.getValueType(MVT::i8));
1113 } else if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1) ||
1114 Tmp3 != Node->getOperand(2)) {
1115 Result = DAG.getNode(ISD::TRUNCSTORE, MVT::Other, Tmp1, Tmp2, Tmp3,
1116 Node->getOperand(3), Node->getOperand(4));
1121 assert(0 && "Cannot handle illegal TRUNCSTORE yet!");
1125 switch (getTypeAction(Node->getOperand(0).getValueType())) {
1126 case Expand: assert(0 && "It's impossible to expand bools");
1128 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the condition.
1131 Tmp1 = PromoteOp(Node->getOperand(0)); // Promote the condition.
1134 Tmp2 = LegalizeOp(Node->getOperand(1)); // TrueVal
1135 Tmp3 = LegalizeOp(Node->getOperand(2)); // FalseVal
1137 switch (TLI.getOperationAction(ISD::SELECT, Tmp2.getValueType())) {
1138 default: assert(0 && "This action is not supported yet!");
1139 case TargetLowering::Expand:
1140 if (Tmp1.getOpcode() == ISD::SETCC) {
1141 Result = DAG.getSelectCC(Tmp1.getOperand(0), Tmp1.getOperand(1),
1143 cast<CondCodeSDNode>(Tmp1.getOperand(2))->get());
1145 // Make sure the condition is either zero or one. It may have been
1146 // promoted from something else.
1147 Tmp1 = DAG.getZeroExtendInReg(Tmp1, MVT::i1);
1148 Result = DAG.getSelectCC(Tmp1,
1149 DAG.getConstant(0, Tmp1.getValueType()),
1150 Tmp2, Tmp3, ISD::SETNE);
1153 case TargetLowering::Legal:
1154 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1) ||
1155 Tmp3 != Node->getOperand(2))
1156 Result = DAG.getNode(ISD::SELECT, Node->getValueType(0),
1159 case TargetLowering::Promote: {
1160 MVT::ValueType NVT =
1161 TLI.getTypeToPromoteTo(ISD::SELECT, Tmp2.getValueType());
1162 unsigned ExtOp, TruncOp;
1163 if (MVT::isInteger(Tmp2.getValueType())) {
1164 ExtOp = ISD::ANY_EXTEND;
1165 TruncOp = ISD::TRUNCATE;
1167 ExtOp = ISD::FP_EXTEND;
1168 TruncOp = ISD::FP_ROUND;
1170 // Promote each of the values to the new type.
1171 Tmp2 = DAG.getNode(ExtOp, NVT, Tmp2);
1172 Tmp3 = DAG.getNode(ExtOp, NVT, Tmp3);
1173 // Perform the larger operation, then round down.
1174 Result = DAG.getNode(ISD::SELECT, NVT, Tmp1, Tmp2,Tmp3);
1175 Result = DAG.getNode(TruncOp, Node->getValueType(0), Result);
1180 case ISD::SELECT_CC:
1181 Tmp3 = LegalizeOp(Node->getOperand(2)); // True
1182 Tmp4 = LegalizeOp(Node->getOperand(3)); // False
1184 if (isTypeLegal(Node->getOperand(0).getValueType())) {
1185 // Everything is legal, see if we should expand this op or something.
1186 switch (TLI.getOperationAction(ISD::SELECT_CC,
1187 Node->getOperand(0).getValueType())) {
1188 default: assert(0 && "This action is not supported yet!");
1189 case TargetLowering::Custom: {
1191 TLI.LowerOperation(DAG.getNode(ISD::SELECT_CC, Node->getValueType(0),
1192 Node->getOperand(0),
1193 Node->getOperand(1), Tmp3, Tmp4,
1194 Node->getOperand(4)), DAG);
1196 Result = LegalizeOp(Tmp);
1199 } // FALLTHROUGH if the target can't lower this operation after all.
1200 case TargetLowering::Legal:
1201 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
1202 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS
1203 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1) ||
1204 Tmp3 != Node->getOperand(2) || Tmp4 != Node->getOperand(3)) {
1205 Result = DAG.getNode(ISD::SELECT_CC, Node->getValueType(0), Tmp1, Tmp2,
1206 Tmp3, Tmp4, Node->getOperand(4));
1212 Tmp1 = LegalizeOp(DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(),
1213 Node->getOperand(0), // LHS
1214 Node->getOperand(1), // RHS
1215 Node->getOperand(4)));
1216 // If we get a SETCC back from legalizing the SETCC node we just
1217 // created, then use its LHS, RHS, and CC directly in creating a new
1218 // node. Otherwise, select between the true and false value based on
1219 // comparing the result of the legalized with zero.
1220 if (Tmp1.getOpcode() == ISD::SETCC) {
1221 Result = DAG.getNode(ISD::SELECT_CC, Tmp3.getValueType(),
1222 Tmp1.getOperand(0), Tmp1.getOperand(1),
1223 Tmp3, Tmp4, Tmp1.getOperand(2));
1225 Result = DAG.getSelectCC(Tmp1,
1226 DAG.getConstant(0, Tmp1.getValueType()),
1227 Tmp3, Tmp4, ISD::SETNE);
1232 switch (getTypeAction(Node->getOperand(0).getValueType())) {
1234 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
1235 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS
1238 Tmp1 = PromoteOp(Node->getOperand(0)); // LHS
1239 Tmp2 = PromoteOp(Node->getOperand(1)); // RHS
1241 // If this is an FP compare, the operands have already been extended.
1242 if (MVT::isInteger(Node->getOperand(0).getValueType())) {
1243 MVT::ValueType VT = Node->getOperand(0).getValueType();
1244 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT);
1246 // Otherwise, we have to insert explicit sign or zero extends. Note
1247 // that we could insert sign extends for ALL conditions, but zero extend
1248 // is cheaper on many machines (an AND instead of two shifts), so prefer
1250 switch (cast<CondCodeSDNode>(Node->getOperand(2))->get()) {
1251 default: assert(0 && "Unknown integer comparison!");
1258 // ALL of these operations will work if we either sign or zero extend
1259 // the operands (including the unsigned comparisons!). Zero extend is
1260 // usually a simpler/cheaper operation, so prefer it.
1261 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT);
1262 Tmp2 = DAG.getZeroExtendInReg(Tmp2, VT);
1268 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1,
1269 DAG.getValueType(VT));
1270 Tmp2 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp2,
1271 DAG.getValueType(VT));
1277 SDOperand LHSLo, LHSHi, RHSLo, RHSHi;
1278 ExpandOp(Node->getOperand(0), LHSLo, LHSHi);
1279 ExpandOp(Node->getOperand(1), RHSLo, RHSHi);
1280 switch (cast<CondCodeSDNode>(Node->getOperand(2))->get()) {
1284 if (ConstantSDNode *RHSCST = dyn_cast<ConstantSDNode>(RHSLo))
1285 if (RHSCST->isAllOnesValue()) {
1286 // Comparison to -1.
1287 Tmp1 = DAG.getNode(ISD::AND, LHSLo.getValueType(), LHSLo, LHSHi);
1292 Tmp1 = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSLo, RHSLo);
1293 Tmp2 = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSHi, RHSHi);
1294 Tmp1 = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp2);
1295 Tmp2 = DAG.getConstant(0, Tmp1.getValueType());
1298 // If this is a comparison of the sign bit, just look at the top part.
1300 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Node->getOperand(1)))
1301 if ((cast<CondCodeSDNode>(Node->getOperand(2))->get() == ISD::SETLT &&
1302 CST->getValue() == 0) || // X < 0
1303 (cast<CondCodeSDNode>(Node->getOperand(2))->get() == ISD::SETGT &&
1304 (CST->isAllOnesValue()))) { // X > -1
1310 // FIXME: This generated code sucks.
1311 ISD::CondCode LowCC;
1312 switch (cast<CondCodeSDNode>(Node->getOperand(2))->get()) {
1313 default: assert(0 && "Unknown integer setcc!");
1315 case ISD::SETULT: LowCC = ISD::SETULT; break;
1317 case ISD::SETUGT: LowCC = ISD::SETUGT; break;
1319 case ISD::SETULE: LowCC = ISD::SETULE; break;
1321 case ISD::SETUGE: LowCC = ISD::SETUGE; break;
1324 // Tmp1 = lo(op1) < lo(op2) // Always unsigned comparison
1325 // Tmp2 = hi(op1) < hi(op2) // Signedness depends on operands
1326 // dest = hi(op1) == hi(op2) ? Tmp1 : Tmp2;
1328 // NOTE: on targets without efficient SELECT of bools, we can always use
1329 // this identity: (B1 ? B2 : B3) --> (B1 & B2)|(!B1&B3)
1330 Tmp1 = DAG.getSetCC(Node->getValueType(0), LHSLo, RHSLo, LowCC);
1331 Tmp2 = DAG.getNode(ISD::SETCC, Node->getValueType(0), LHSHi, RHSHi,
1332 Node->getOperand(2));
1333 Result = DAG.getSetCC(Node->getValueType(0), LHSHi, RHSHi, ISD::SETEQ);
1334 Result = LegalizeOp(DAG.getNode(ISD::SELECT, Tmp1.getValueType(),
1335 Result, Tmp1, Tmp2));
1340 switch(TLI.getOperationAction(ISD::SETCC, Node->getOperand(0).getValueType())) {
1342 assert(0 && "Cannot handle this action for SETCC yet!");
1344 case TargetLowering::Promote:
1345 Result = DAG.getNode(ISD::SETCC, Node->getValueType(0), Tmp1, Tmp2,
1346 Node->getOperand(2));
1348 case TargetLowering::Legal:
1349 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1))
1350 Result = DAG.getNode(ISD::SETCC, Node->getValueType(0), Tmp1, Tmp2,
1351 Node->getOperand(2));
1353 case TargetLowering::Expand:
1354 // Expand a setcc node into a select_cc of the same condition, lhs, and
1355 // rhs that selects between const 1 (true) and const 0 (false).
1356 MVT::ValueType VT = Node->getValueType(0);
1357 Result = DAG.getNode(ISD::SELECT_CC, VT, Tmp1, Tmp2,
1358 DAG.getConstant(1, VT), DAG.getConstant(0, VT),
1359 Node->getOperand(2));
1360 Result = LegalizeOp(Result);
1367 case ISD::MEMMOVE: {
1368 Tmp1 = LegalizeOp(Node->getOperand(0)); // Chain
1369 Tmp2 = LegalizeOp(Node->getOperand(1)); // Pointer
1371 if (Node->getOpcode() == ISD::MEMSET) { // memset = ubyte
1372 switch (getTypeAction(Node->getOperand(2).getValueType())) {
1373 case Expand: assert(0 && "Cannot expand a byte!");
1375 Tmp3 = LegalizeOp(Node->getOperand(2));
1378 Tmp3 = PromoteOp(Node->getOperand(2));
1382 Tmp3 = LegalizeOp(Node->getOperand(2)); // memcpy/move = pointer,
1386 switch (getTypeAction(Node->getOperand(3).getValueType())) {
1388 // Length is too big, just take the lo-part of the length.
1390 ExpandOp(Node->getOperand(3), HiPart, Tmp4);
1394 Tmp4 = LegalizeOp(Node->getOperand(3));
1397 Tmp4 = PromoteOp(Node->getOperand(3));
1402 switch (getTypeAction(Node->getOperand(4).getValueType())) { // uint
1403 case Expand: assert(0 && "Cannot expand this yet!");
1405 Tmp5 = LegalizeOp(Node->getOperand(4));
1408 Tmp5 = PromoteOp(Node->getOperand(4));
1412 switch (TLI.getOperationAction(Node->getOpcode(), MVT::Other)) {
1413 default: assert(0 && "This action not implemented for this operation!");
1414 case TargetLowering::Custom: {
1416 TLI.LowerOperation(DAG.getNode(Node->getOpcode(), MVT::Other, Tmp1,
1417 Tmp2, Tmp3, Tmp4, Tmp5), DAG);
1419 Result = LegalizeOp(Tmp);
1422 // FALLTHROUGH if the target thinks it is legal.
1424 case TargetLowering::Legal:
1425 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1) ||
1426 Tmp3 != Node->getOperand(2) || Tmp4 != Node->getOperand(3) ||
1427 Tmp5 != Node->getOperand(4)) {
1428 std::vector<SDOperand> Ops;
1429 Ops.push_back(Tmp1); Ops.push_back(Tmp2); Ops.push_back(Tmp3);
1430 Ops.push_back(Tmp4); Ops.push_back(Tmp5);
1431 Result = DAG.getNode(Node->getOpcode(), MVT::Other, Ops);
1434 case TargetLowering::Expand: {
1435 // Otherwise, the target does not support this operation. Lower the
1436 // operation to an explicit libcall as appropriate.
1437 MVT::ValueType IntPtr = TLI.getPointerTy();
1438 const Type *IntPtrTy = TLI.getTargetData().getIntPtrType();
1439 std::vector<std::pair<SDOperand, const Type*> > Args;
1441 const char *FnName = 0;
1442 if (Node->getOpcode() == ISD::MEMSET) {
1443 Args.push_back(std::make_pair(Tmp2, IntPtrTy));
1444 // Extend the ubyte argument to be an int value for the call.
1445 Tmp3 = DAG.getNode(ISD::ZERO_EXTEND, MVT::i32, Tmp3);
1446 Args.push_back(std::make_pair(Tmp3, Type::IntTy));
1447 Args.push_back(std::make_pair(Tmp4, IntPtrTy));
1450 } else if (Node->getOpcode() == ISD::MEMCPY ||
1451 Node->getOpcode() == ISD::MEMMOVE) {
1452 Args.push_back(std::make_pair(Tmp2, IntPtrTy));
1453 Args.push_back(std::make_pair(Tmp3, IntPtrTy));
1454 Args.push_back(std::make_pair(Tmp4, IntPtrTy));
1455 FnName = Node->getOpcode() == ISD::MEMMOVE ? "memmove" : "memcpy";
1457 assert(0 && "Unknown op!");
1460 std::pair<SDOperand,SDOperand> CallResult =
1461 TLI.LowerCallTo(Tmp1, Type::VoidTy, false, CallingConv::C, false,
1462 DAG.getExternalSymbol(FnName, IntPtr), Args, DAG);
1463 Result = CallResult.second;
1464 NeedsAnotherIteration = true;
1472 Tmp1 = LegalizeOp(Node->getOperand(0));
1473 Tmp2 = LegalizeOp(Node->getOperand(1));
1475 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1)) {
1476 std::vector<MVT::ValueType> VTs(Node->value_begin(), Node->value_end());
1477 std::vector<SDOperand> Ops;
1478 Ops.push_back(Tmp1);
1479 Ops.push_back(Tmp2);
1480 Result = DAG.getNode(ISD::READPORT, VTs, Ops);
1482 Result = SDOperand(Node, 0);
1483 // Since these produce two values, make sure to remember that we legalized
1485 AddLegalizedOperand(SDOperand(Node, 0), Result);
1486 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
1487 return Result.getValue(Op.ResNo);
1488 case ISD::WRITEPORT:
1489 Tmp1 = LegalizeOp(Node->getOperand(0));
1490 Tmp2 = LegalizeOp(Node->getOperand(1));
1491 Tmp3 = LegalizeOp(Node->getOperand(2));
1492 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1) ||
1493 Tmp3 != Node->getOperand(2))
1494 Result = DAG.getNode(Node->getOpcode(), MVT::Other, Tmp1, Tmp2, Tmp3);
1498 Tmp1 = LegalizeOp(Node->getOperand(0));
1499 Tmp2 = LegalizeOp(Node->getOperand(1));
1501 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
1502 case TargetLowering::Custom:
1503 default: assert(0 && "This action not implemented for this operation!");
1504 case TargetLowering::Legal:
1505 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1)) {
1506 std::vector<MVT::ValueType> VTs(Node->value_begin(), Node->value_end());
1507 std::vector<SDOperand> Ops;
1508 Ops.push_back(Tmp1);
1509 Ops.push_back(Tmp2);
1510 Result = DAG.getNode(ISD::READPORT, VTs, Ops);
1512 Result = SDOperand(Node, 0);
1514 case TargetLowering::Expand:
1515 // Replace this with a load from memory.
1516 Result = DAG.getLoad(Node->getValueType(0), Node->getOperand(0),
1517 Node->getOperand(1), DAG.getSrcValue(NULL));
1518 Result = LegalizeOp(Result);
1522 // Since these produce two values, make sure to remember that we legalized
1524 AddLegalizedOperand(SDOperand(Node, 0), Result);
1525 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
1526 return Result.getValue(Op.ResNo);
1529 Tmp1 = LegalizeOp(Node->getOperand(0));
1530 Tmp2 = LegalizeOp(Node->getOperand(1));
1531 Tmp3 = LegalizeOp(Node->getOperand(2));
1533 switch (TLI.getOperationAction(Node->getOpcode(),
1534 Node->getOperand(1).getValueType())) {
1535 case TargetLowering::Custom:
1536 default: assert(0 && "This action not implemented for this operation!");
1537 case TargetLowering::Legal:
1538 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1) ||
1539 Tmp3 != Node->getOperand(2))
1540 Result = DAG.getNode(Node->getOpcode(), MVT::Other, Tmp1, Tmp2, Tmp3);
1542 case TargetLowering::Expand:
1543 // Replace this with a store to memory.
1544 Result = DAG.getNode(ISD::STORE, MVT::Other, Node->getOperand(0),
1545 Node->getOperand(1), Node->getOperand(2),
1546 DAG.getSrcValue(NULL));
1547 Result = LegalizeOp(Result);
1552 case ISD::ADD_PARTS:
1553 case ISD::SUB_PARTS:
1554 case ISD::SHL_PARTS:
1555 case ISD::SRA_PARTS:
1556 case ISD::SRL_PARTS: {
1557 std::vector<SDOperand> Ops;
1558 bool Changed = false;
1559 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
1560 Ops.push_back(LegalizeOp(Node->getOperand(i)));
1561 Changed |= Ops.back() != Node->getOperand(i);
1564 std::vector<MVT::ValueType> VTs(Node->value_begin(), Node->value_end());
1565 Result = DAG.getNode(Node->getOpcode(), VTs, Ops);
1568 // Since these produce multiple values, make sure to remember that we
1569 // legalized all of them.
1570 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
1571 AddLegalizedOperand(SDOperand(Node, i), Result.getValue(i));
1572 return Result.getValue(Op.ResNo);
1593 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
1594 switch (getTypeAction(Node->getOperand(1).getValueType())) {
1595 case Expand: assert(0 && "Not possible");
1597 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the RHS.
1600 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the RHS.
1603 if (Tmp1 != Node->getOperand(0) ||
1604 Tmp2 != Node->getOperand(1))
1605 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1,Tmp2);
1611 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
1612 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS
1613 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
1614 case TargetLowering::Legal:
1615 if (Tmp1 != Node->getOperand(0) ||
1616 Tmp2 != Node->getOperand(1))
1617 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1,
1620 case TargetLowering::Promote:
1621 case TargetLowering::Custom:
1622 assert(0 && "Cannot promote/custom handle this yet!");
1623 case TargetLowering::Expand:
1624 if (MVT::isInteger(Node->getValueType(0))) {
1625 MVT::ValueType VT = Node->getValueType(0);
1626 unsigned Opc = (Node->getOpcode() == ISD::UREM) ? ISD::UDIV : ISD::SDIV;
1627 Result = DAG.getNode(Opc, VT, Tmp1, Tmp2);
1628 Result = DAG.getNode(ISD::MUL, VT, Result, Tmp2);
1629 Result = DAG.getNode(ISD::SUB, VT, Tmp1, Result);
1631 // Floating point mod -> fmod libcall.
1632 const char *FnName = Node->getValueType(0) == MVT::f32 ? "fmodf":"fmod";
1634 Result = ExpandLibCall(FnName, Node, Dummy);
1643 Tmp1 = LegalizeOp(Node->getOperand(0)); // Op
1644 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
1645 case TargetLowering::Legal:
1646 if (Tmp1 != Node->getOperand(0))
1647 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1);
1649 case TargetLowering::Promote: {
1650 MVT::ValueType OVT = Tmp1.getValueType();
1651 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
1653 // Zero extend the argument.
1654 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1);
1655 // Perform the larger operation, then subtract if needed.
1656 Tmp1 = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1);
1657 switch(Node->getOpcode())
1663 //if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT)
1664 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), Tmp1,
1665 DAG.getConstant(getSizeInBits(NVT), NVT),
1667 Result = DAG.getNode(ISD::SELECT, NVT, Tmp2,
1668 DAG.getConstant(getSizeInBits(OVT),NVT), Tmp1);
1671 //Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT))
1672 Result = DAG.getNode(ISD::SUB, NVT, Tmp1,
1673 DAG.getConstant(getSizeInBits(NVT) -
1674 getSizeInBits(OVT), NVT));
1679 case TargetLowering::Custom:
1680 assert(0 && "Cannot custom handle this yet!");
1681 case TargetLowering::Expand:
1682 switch(Node->getOpcode())
1685 static const uint64_t mask[6] = {
1686 0x5555555555555555ULL, 0x3333333333333333ULL,
1687 0x0F0F0F0F0F0F0F0FULL, 0x00FF00FF00FF00FFULL,
1688 0x0000FFFF0000FFFFULL, 0x00000000FFFFFFFFULL
1690 MVT::ValueType VT = Tmp1.getValueType();
1691 MVT::ValueType ShVT = TLI.getShiftAmountTy();
1692 unsigned len = getSizeInBits(VT);
1693 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) {
1694 //x = (x & mask[i][len/8]) + (x >> (1 << i) & mask[i][len/8])
1695 Tmp2 = DAG.getConstant(mask[i], VT);
1696 Tmp3 = DAG.getConstant(1ULL << i, ShVT);
1697 Tmp1 = DAG.getNode(ISD::ADD, VT,
1698 DAG.getNode(ISD::AND, VT, Tmp1, Tmp2),
1699 DAG.getNode(ISD::AND, VT,
1700 DAG.getNode(ISD::SRL, VT, Tmp1, Tmp3),
1707 /* for now, we do this:
1712 x = x | (x >>32); // for 64-bit input
1713 return popcount(~x);
1715 but see also: http://www.hackersdelight.org/HDcode/nlz.cc */
1716 MVT::ValueType VT = Tmp1.getValueType();
1717 MVT::ValueType ShVT = TLI.getShiftAmountTy();
1718 unsigned len = getSizeInBits(VT);
1719 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) {
1720 Tmp3 = DAG.getConstant(1ULL << i, ShVT);
1721 Tmp1 = DAG.getNode(ISD::OR, VT, Tmp1,
1722 DAG.getNode(ISD::SRL, VT, Tmp1, Tmp3));
1724 Tmp3 = DAG.getNode(ISD::XOR, VT, Tmp1, DAG.getConstant(~0ULL, VT));
1725 Result = LegalizeOp(DAG.getNode(ISD::CTPOP, VT, Tmp3));
1729 // for now, we use: { return popcount(~x & (x - 1)); }
1730 // unless the target has ctlz but not ctpop, in which case we use:
1731 // { return 32 - nlz(~x & (x-1)); }
1732 // see also http://www.hackersdelight.org/HDcode/ntz.cc
1733 MVT::ValueType VT = Tmp1.getValueType();
1734 Tmp2 = DAG.getConstant(~0ULL, VT);
1735 Tmp3 = DAG.getNode(ISD::AND, VT,
1736 DAG.getNode(ISD::XOR, VT, Tmp1, Tmp2),
1737 DAG.getNode(ISD::SUB, VT, Tmp1,
1738 DAG.getConstant(1, VT)));
1739 // If ISD::CTLZ is legal and CTPOP isn't, then do that instead
1740 if (!TLI.isOperationLegal(ISD::CTPOP, VT) &&
1741 TLI.isOperationLegal(ISD::CTLZ, VT)) {
1742 Result = LegalizeOp(DAG.getNode(ISD::SUB, VT,
1743 DAG.getConstant(getSizeInBits(VT), VT),
1744 DAG.getNode(ISD::CTLZ, VT, Tmp3)));
1746 Result = LegalizeOp(DAG.getNode(ISD::CTPOP, VT, Tmp3));
1751 assert(0 && "Cannot expand this yet!");
1764 Tmp1 = LegalizeOp(Node->getOperand(0));
1765 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
1766 case TargetLowering::Legal:
1767 if (Tmp1 != Node->getOperand(0))
1768 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1);
1770 case TargetLowering::Promote:
1771 case TargetLowering::Custom:
1772 assert(0 && "Cannot promote/custom handle this yet!");
1773 case TargetLowering::Expand:
1774 switch(Node->getOpcode()) {
1776 // Expand Y = FNEG(X) -> Y = SUB -0.0, X
1777 Tmp2 = DAG.getConstantFP(-0.0, Node->getValueType(0));
1778 Result = LegalizeOp(DAG.getNode(ISD::FSUB, Node->getValueType(0),
1783 // Expand Y = FABS(X) -> Y = (X >u 0.0) ? X : fneg(X).
1784 MVT::ValueType VT = Node->getValueType(0);
1785 Tmp2 = DAG.getConstantFP(0.0, VT);
1786 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), Tmp1, Tmp2, ISD::SETUGT);
1787 Tmp3 = DAG.getNode(ISD::FNEG, VT, Tmp1);
1788 Result = DAG.getNode(ISD::SELECT, VT, Tmp2, Tmp1, Tmp3);
1789 Result = LegalizeOp(Result);
1795 MVT::ValueType VT = Node->getValueType(0);
1796 const char *FnName = 0;
1797 switch(Node->getOpcode()) {
1798 case ISD::FSQRT: FnName = VT == MVT::f32 ? "sqrtf" : "sqrt"; break;
1799 case ISD::FSIN: FnName = VT == MVT::f32 ? "sinf" : "sin"; break;
1800 case ISD::FCOS: FnName = VT == MVT::f32 ? "cosf" : "cos"; break;
1801 default: assert(0 && "Unreachable!");
1804 Result = ExpandLibCall(FnName, Node, Dummy);
1808 assert(0 && "Unreachable!");
1814 // Conversion operators. The source and destination have different types.
1815 case ISD::SINT_TO_FP:
1816 case ISD::UINT_TO_FP: {
1817 bool isSigned = Node->getOpcode() == ISD::SINT_TO_FP;
1818 switch (getTypeAction(Node->getOperand(0).getValueType())) {
1820 switch (TLI.getOperationAction(Node->getOpcode(),
1821 Node->getOperand(0).getValueType())) {
1822 default: assert(0 && "Unknown operation action!");
1823 case TargetLowering::Expand:
1824 Result = ExpandLegalINT_TO_FP(isSigned,
1825 LegalizeOp(Node->getOperand(0)),
1826 Node->getValueType(0));
1827 AddLegalizedOperand(Op, Result);
1829 case TargetLowering::Promote:
1830 Result = PromoteLegalINT_TO_FP(LegalizeOp(Node->getOperand(0)),
1831 Node->getValueType(0),
1833 AddLegalizedOperand(Op, Result);
1835 case TargetLowering::Legal:
1839 Tmp1 = LegalizeOp(Node->getOperand(0));
1840 if (Tmp1 != Node->getOperand(0))
1841 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1);
1844 Result = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP,
1845 Node->getValueType(0), Node->getOperand(0));
1849 Result = PromoteOp(Node->getOperand(0));
1850 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(),
1851 Result, DAG.getValueType(Node->getOperand(0).getValueType()));
1852 Result = DAG.getNode(ISD::SINT_TO_FP, Op.getValueType(), Result);
1854 Result = PromoteOp(Node->getOperand(0));
1855 Result = DAG.getZeroExtendInReg(Result,
1856 Node->getOperand(0).getValueType());
1857 Result = DAG.getNode(ISD::UINT_TO_FP, Op.getValueType(), Result);
1864 switch (getTypeAction(Node->getOperand(0).getValueType())) {
1866 Tmp1 = LegalizeOp(Node->getOperand(0));
1867 if (Tmp1 != Node->getOperand(0))
1868 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1);
1871 ExpandOp(Node->getOperand(0), Tmp1, Tmp2);
1873 // Since the result is legal, we should just be able to truncate the low
1874 // part of the source.
1875 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), Tmp1);
1878 Result = PromoteOp(Node->getOperand(0));
1879 Result = DAG.getNode(ISD::TRUNCATE, Op.getValueType(), Result);
1884 case ISD::FP_TO_SINT:
1885 case ISD::FP_TO_UINT:
1886 switch (getTypeAction(Node->getOperand(0).getValueType())) {
1888 Tmp1 = LegalizeOp(Node->getOperand(0));
1890 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))){
1891 default: assert(0 && "Unknown operation action!");
1892 case TargetLowering::Expand:
1893 if (Node->getOpcode() == ISD::FP_TO_UINT) {
1894 SDOperand True, False;
1895 MVT::ValueType VT = Node->getOperand(0).getValueType();
1896 MVT::ValueType NVT = Node->getValueType(0);
1897 unsigned ShiftAmt = MVT::getSizeInBits(Node->getValueType(0))-1;
1898 Tmp2 = DAG.getConstantFP((double)(1ULL << ShiftAmt), VT);
1899 Tmp3 = DAG.getSetCC(TLI.getSetCCResultTy(),
1900 Node->getOperand(0), Tmp2, ISD::SETLT);
1901 True = DAG.getNode(ISD::FP_TO_SINT, NVT, Node->getOperand(0));
1902 False = DAG.getNode(ISD::FP_TO_SINT, NVT,
1903 DAG.getNode(ISD::FSUB, VT, Node->getOperand(0),
1905 False = DAG.getNode(ISD::XOR, NVT, False,
1906 DAG.getConstant(1ULL << ShiftAmt, NVT));
1907 Result = LegalizeOp(DAG.getNode(ISD::SELECT, NVT, Tmp3, True, False));
1910 assert(0 && "Do not know how to expand FP_TO_SINT yet!");
1913 case TargetLowering::Promote:
1914 Result = PromoteLegalFP_TO_INT(Tmp1, Node->getValueType(0),
1915 Node->getOpcode() == ISD::FP_TO_SINT);
1916 AddLegalizedOperand(Op, Result);
1918 case TargetLowering::Custom: {
1920 DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1);
1921 Tmp = TLI.LowerOperation(Tmp, DAG);
1923 AddLegalizedOperand(Op, Tmp);
1924 NeedsAnotherIteration = true;
1927 // The target thinks this is legal afterall.
1931 case TargetLowering::Legal:
1935 if (Tmp1 != Node->getOperand(0))
1936 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1);
1939 assert(0 && "Shouldn't need to expand other operators here!");
1941 Result = PromoteOp(Node->getOperand(0));
1942 Result = DAG.getNode(Node->getOpcode(), Op.getValueType(), Result);
1947 case ISD::ANY_EXTEND:
1948 case ISD::ZERO_EXTEND:
1949 case ISD::SIGN_EXTEND:
1950 case ISD::FP_EXTEND:
1952 switch (getTypeAction(Node->getOperand(0).getValueType())) {
1954 Tmp1 = LegalizeOp(Node->getOperand(0));
1955 if (Tmp1 != Node->getOperand(0))
1956 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1);
1959 assert(0 && "Shouldn't need to expand other operators here!");
1962 switch (Node->getOpcode()) {
1963 case ISD::ANY_EXTEND:
1964 Result = PromoteOp(Node->getOperand(0));
1965 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Result);
1967 case ISD::ZERO_EXTEND:
1968 Result = PromoteOp(Node->getOperand(0));
1969 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Result);
1970 Result = DAG.getZeroExtendInReg(Result,
1971 Node->getOperand(0).getValueType());
1973 case ISD::SIGN_EXTEND:
1974 Result = PromoteOp(Node->getOperand(0));
1975 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Result);
1976 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(),
1978 DAG.getValueType(Node->getOperand(0).getValueType()));
1980 case ISD::FP_EXTEND:
1981 Result = PromoteOp(Node->getOperand(0));
1982 if (Result.getValueType() != Op.getValueType())
1983 // Dynamically dead while we have only 2 FP types.
1984 Result = DAG.getNode(ISD::FP_EXTEND, Op.getValueType(), Result);
1987 Result = PromoteOp(Node->getOperand(0));
1988 Result = DAG.getNode(Node->getOpcode(), Op.getValueType(), Result);
1993 case ISD::FP_ROUND_INREG:
1994 case ISD::SIGN_EXTEND_INREG: {
1995 Tmp1 = LegalizeOp(Node->getOperand(0));
1996 MVT::ValueType ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT();
1998 // If this operation is not supported, convert it to a shl/shr or load/store
2000 switch (TLI.getOperationAction(Node->getOpcode(), ExtraVT)) {
2001 default: assert(0 && "This action not supported for this op yet!");
2002 case TargetLowering::Legal:
2003 if (Tmp1 != Node->getOperand(0))
2004 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1,
2005 DAG.getValueType(ExtraVT));
2007 case TargetLowering::Expand:
2008 // If this is an integer extend and shifts are supported, do that.
2009 if (Node->getOpcode() == ISD::SIGN_EXTEND_INREG) {
2010 // NOTE: we could fall back on load/store here too for targets without
2011 // SAR. However, it is doubtful that any exist.
2012 unsigned BitsDiff = MVT::getSizeInBits(Node->getValueType(0)) -
2013 MVT::getSizeInBits(ExtraVT);
2014 SDOperand ShiftCst = DAG.getConstant(BitsDiff, TLI.getShiftAmountTy());
2015 Result = DAG.getNode(ISD::SHL, Node->getValueType(0),
2016 Node->getOperand(0), ShiftCst);
2017 Result = DAG.getNode(ISD::SRA, Node->getValueType(0),
2019 } else if (Node->getOpcode() == ISD::FP_ROUND_INREG) {
2020 // The only way we can lower this is to turn it into a STORETRUNC,
2021 // EXTLOAD pair, targetting a temporary location (a stack slot).
2023 // NOTE: there is a choice here between constantly creating new stack
2024 // slots and always reusing the same one. We currently always create
2025 // new ones, as reuse may inhibit scheduling.
2026 const Type *Ty = MVT::getTypeForValueType(ExtraVT);
2027 unsigned TySize = (unsigned)TLI.getTargetData().getTypeSize(Ty);
2028 unsigned Align = TLI.getTargetData().getTypeAlignment(Ty);
2029 MachineFunction &MF = DAG.getMachineFunction();
2031 MF.getFrameInfo()->CreateStackObject((unsigned)TySize, Align);
2032 SDOperand StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy());
2033 Result = DAG.getNode(ISD::TRUNCSTORE, MVT::Other, DAG.getEntryNode(),
2034 Node->getOperand(0), StackSlot,
2035 DAG.getSrcValue(NULL), DAG.getValueType(ExtraVT));
2036 Result = DAG.getExtLoad(ISD::EXTLOAD, Node->getValueType(0),
2037 Result, StackSlot, DAG.getSrcValue(NULL),
2040 assert(0 && "Unknown op");
2042 Result = LegalizeOp(Result);
2049 // Note that LegalizeOp may be reentered even from single-use nodes, which
2050 // means that we always must cache transformed nodes.
2051 AddLegalizedOperand(Op, Result);
2055 /// PromoteOp - Given an operation that produces a value in an invalid type,
2056 /// promote it to compute the value into a larger type. The produced value will
2057 /// have the correct bits for the low portion of the register, but no guarantee
2058 /// is made about the top bits: it may be zero, sign-extended, or garbage.
2059 SDOperand SelectionDAGLegalize::PromoteOp(SDOperand Op) {
2060 MVT::ValueType VT = Op.getValueType();
2061 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT);
2062 assert(getTypeAction(VT) == Promote &&
2063 "Caller should expand or legalize operands that are not promotable!");
2064 assert(NVT > VT && MVT::isInteger(NVT) == MVT::isInteger(VT) &&
2065 "Cannot promote to smaller type!");
2067 SDOperand Tmp1, Tmp2, Tmp3;
2070 SDNode *Node = Op.Val;
2072 std::map<SDOperand, SDOperand>::iterator I = PromotedNodes.find(Op);
2073 if (I != PromotedNodes.end()) return I->second;
2075 // Promotion needs an optimization step to clean up after it, and is not
2076 // careful to avoid operations the target does not support. Make sure that
2077 // all generated operations are legalized in the next iteration.
2078 NeedsAnotherIteration = true;
2080 switch (Node->getOpcode()) {
2081 case ISD::CopyFromReg:
2082 assert(0 && "CopyFromReg must be legal!");
2084 std::cerr << "NODE: "; Node->dump(); std::cerr << "\n";
2085 assert(0 && "Do not know how to promote this operator!");
2088 Result = DAG.getNode(ISD::UNDEF, NVT);
2092 Result = DAG.getNode(ISD::SIGN_EXTEND, NVT, Op);
2094 Result = DAG.getNode(ISD::ZERO_EXTEND, NVT, Op);
2095 assert(isa<ConstantSDNode>(Result) && "Didn't constant fold zext?");
2097 case ISD::ConstantFP:
2098 Result = DAG.getNode(ISD::FP_EXTEND, NVT, Op);
2099 assert(isa<ConstantFPSDNode>(Result) && "Didn't constant fold fp_extend?");
2103 assert(isTypeLegal(TLI.getSetCCResultTy()) && "SetCC type is not legal??");
2104 Result = DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(),Node->getOperand(0),
2105 Node->getOperand(1), Node->getOperand(2));
2106 Result = LegalizeOp(Result);
2110 switch (getTypeAction(Node->getOperand(0).getValueType())) {
2112 Result = LegalizeOp(Node->getOperand(0));
2113 assert(Result.getValueType() >= NVT &&
2114 "This truncation doesn't make sense!");
2115 if (Result.getValueType() > NVT) // Truncate to NVT instead of VT
2116 Result = DAG.getNode(ISD::TRUNCATE, NVT, Result);
2119 // The truncation is not required, because we don't guarantee anything
2120 // about high bits anyway.
2121 Result = PromoteOp(Node->getOperand(0));
2124 ExpandOp(Node->getOperand(0), Tmp1, Tmp2);
2125 // Truncate the low part of the expanded value to the result type
2126 Result = DAG.getNode(ISD::TRUNCATE, NVT, Tmp1);
2129 case ISD::SIGN_EXTEND:
2130 case ISD::ZERO_EXTEND:
2131 case ISD::ANY_EXTEND:
2132 switch (getTypeAction(Node->getOperand(0).getValueType())) {
2133 case Expand: assert(0 && "BUG: Smaller reg should have been promoted!");
2135 // Input is legal? Just do extend all the way to the larger type.
2136 Result = LegalizeOp(Node->getOperand(0));
2137 Result = DAG.getNode(Node->getOpcode(), NVT, Result);
2140 // Promote the reg if it's smaller.
2141 Result = PromoteOp(Node->getOperand(0));
2142 // The high bits are not guaranteed to be anything. Insert an extend.
2143 if (Node->getOpcode() == ISD::SIGN_EXTEND)
2144 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Result,
2145 DAG.getValueType(Node->getOperand(0).getValueType()));
2146 else if (Node->getOpcode() == ISD::ZERO_EXTEND)
2147 Result = DAG.getZeroExtendInReg(Result,
2148 Node->getOperand(0).getValueType());
2153 case ISD::FP_EXTEND:
2154 assert(0 && "Case not implemented. Dynamically dead with 2 FP types!");
2156 switch (getTypeAction(Node->getOperand(0).getValueType())) {
2157 case Expand: assert(0 && "BUG: Cannot expand FP regs!");
2158 case Promote: assert(0 && "Unreachable with 2 FP types!");
2160 // Input is legal? Do an FP_ROUND_INREG.
2161 Result = LegalizeOp(Node->getOperand(0));
2162 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
2163 DAG.getValueType(VT));
2168 case ISD::SINT_TO_FP:
2169 case ISD::UINT_TO_FP:
2170 switch (getTypeAction(Node->getOperand(0).getValueType())) {
2172 Result = LegalizeOp(Node->getOperand(0));
2173 // No extra round required here.
2174 Result = DAG.getNode(Node->getOpcode(), NVT, Result);
2178 Result = PromoteOp(Node->getOperand(0));
2179 if (Node->getOpcode() == ISD::SINT_TO_FP)
2180 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(),
2182 DAG.getValueType(Node->getOperand(0).getValueType()));
2184 Result = DAG.getZeroExtendInReg(Result,
2185 Node->getOperand(0).getValueType());
2186 // No extra round required here.
2187 Result = DAG.getNode(Node->getOpcode(), NVT, Result);
2190 Result = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP, NVT,
2191 Node->getOperand(0));
2192 // Round if we cannot tolerate excess precision.
2193 if (NoExcessFPPrecision)
2194 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
2195 DAG.getValueType(VT));
2200 case ISD::FP_TO_SINT:
2201 case ISD::FP_TO_UINT:
2202 switch (getTypeAction(Node->getOperand(0).getValueType())) {
2204 Tmp1 = LegalizeOp(Node->getOperand(0));
2207 // The input result is prerounded, so we don't have to do anything
2209 Tmp1 = PromoteOp(Node->getOperand(0));
2212 assert(0 && "not implemented");
2214 // If we're promoting a UINT to a larger size, check to see if the new node
2215 // will be legal. If it isn't, check to see if FP_TO_SINT is legal, since
2216 // we can use that instead. This allows us to generate better code for
2217 // FP_TO_UINT for small destination sizes on targets where FP_TO_UINT is not
2218 // legal, such as PowerPC.
2219 if (Node->getOpcode() == ISD::FP_TO_UINT &&
2220 !TLI.isOperationLegal(ISD::FP_TO_UINT, NVT) &&
2221 TLI.isOperationLegal(ISD::FP_TO_SINT, NVT)) {
2222 Result = DAG.getNode(ISD::FP_TO_SINT, NVT, Tmp1);
2224 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
2230 Tmp1 = PromoteOp(Node->getOperand(0));
2231 assert(Tmp1.getValueType() == NVT);
2232 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
2233 // NOTE: we do not have to do any extra rounding here for
2234 // NoExcessFPPrecision, because we know the input will have the appropriate
2235 // precision, and these operations don't modify precision at all.
2241 Tmp1 = PromoteOp(Node->getOperand(0));
2242 assert(Tmp1.getValueType() == NVT);
2243 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
2244 if(NoExcessFPPrecision)
2245 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
2246 DAG.getValueType(VT));
2255 // The input may have strange things in the top bits of the registers, but
2256 // these operations don't care. They may have weird bits going out, but
2257 // that too is okay if they are integer operations.
2258 Tmp1 = PromoteOp(Node->getOperand(0));
2259 Tmp2 = PromoteOp(Node->getOperand(1));
2260 assert(Tmp1.getValueType() == NVT && Tmp2.getValueType() == NVT);
2261 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
2266 // The input may have strange things in the top bits of the registers, but
2267 // these operations don't care.
2268 Tmp1 = PromoteOp(Node->getOperand(0));
2269 Tmp2 = PromoteOp(Node->getOperand(1));
2270 assert(Tmp1.getValueType() == NVT && Tmp2.getValueType() == NVT);
2271 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
2273 // Floating point operations will give excess precision that we may not be
2274 // able to tolerate. If we DO allow excess precision, just leave it,
2275 // otherwise excise it.
2276 // FIXME: Why would we need to round FP ops more than integer ones?
2277 // Is Round(Add(Add(A,B),C)) != Round(Add(Round(Add(A,B)), C))
2278 if (NoExcessFPPrecision)
2279 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
2280 DAG.getValueType(VT));
2285 // These operators require that their input be sign extended.
2286 Tmp1 = PromoteOp(Node->getOperand(0));
2287 Tmp2 = PromoteOp(Node->getOperand(1));
2288 if (MVT::isInteger(NVT)) {
2289 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1,
2290 DAG.getValueType(VT));
2291 Tmp2 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp2,
2292 DAG.getValueType(VT));
2294 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
2296 // Perform FP_ROUND: this is probably overly pessimistic.
2297 if (MVT::isFloatingPoint(NVT) && NoExcessFPPrecision)
2298 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
2299 DAG.getValueType(VT));
2303 // These operators require that their input be fp extended.
2304 Tmp1 = PromoteOp(Node->getOperand(0));
2305 Tmp2 = PromoteOp(Node->getOperand(1));
2306 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
2308 // Perform FP_ROUND: this is probably overly pessimistic.
2309 if (NoExcessFPPrecision)
2310 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
2311 DAG.getValueType(VT));
2316 // These operators require that their input be zero extended.
2317 Tmp1 = PromoteOp(Node->getOperand(0));
2318 Tmp2 = PromoteOp(Node->getOperand(1));
2319 assert(MVT::isInteger(NVT) && "Operators don't apply to FP!");
2320 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT);
2321 Tmp2 = DAG.getZeroExtendInReg(Tmp2, VT);
2322 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
2326 Tmp1 = PromoteOp(Node->getOperand(0));
2327 Tmp2 = LegalizeOp(Node->getOperand(1));
2328 Result = DAG.getNode(ISD::SHL, NVT, Tmp1, Tmp2);
2331 // The input value must be properly sign extended.
2332 Tmp1 = PromoteOp(Node->getOperand(0));
2333 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1,
2334 DAG.getValueType(VT));
2335 Tmp2 = LegalizeOp(Node->getOperand(1));
2336 Result = DAG.getNode(ISD::SRA, NVT, Tmp1, Tmp2);
2339 // The input value must be properly zero extended.
2340 Tmp1 = PromoteOp(Node->getOperand(0));
2341 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT);
2342 Tmp2 = LegalizeOp(Node->getOperand(1));
2343 Result = DAG.getNode(ISD::SRL, NVT, Tmp1, Tmp2);
2346 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2347 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
2348 Result = DAG.getExtLoad(ISD::EXTLOAD, NVT, Tmp1, Tmp2,
2349 Node->getOperand(2), VT);
2350 // Remember that we legalized the chain.
2351 AddLegalizedOperand(Op.getValue(1), Result.getValue(1));
2356 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2357 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
2358 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2,
2359 Node->getOperand(2), Node->getOperand(3));
2360 // Remember that we legalized the chain.
2361 AddLegalizedOperand(Op.getValue(1), Result.getValue(1));
2364 switch (getTypeAction(Node->getOperand(0).getValueType())) {
2365 case Expand: assert(0 && "It's impossible to expand bools");
2367 Tmp1 = LegalizeOp(Node->getOperand(0));// Legalize the condition.
2370 Tmp1 = PromoteOp(Node->getOperand(0)); // Promote the condition.
2373 Tmp2 = PromoteOp(Node->getOperand(1)); // Legalize the op0
2374 Tmp3 = PromoteOp(Node->getOperand(2)); // Legalize the op1
2375 Result = DAG.getNode(ISD::SELECT, NVT, Tmp1, Tmp2, Tmp3);
2377 case ISD::SELECT_CC:
2378 Tmp2 = PromoteOp(Node->getOperand(2)); // True
2379 Tmp3 = PromoteOp(Node->getOperand(3)); // False
2380 Result = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0),
2381 Node->getOperand(1), Tmp2, Tmp3,
2382 Node->getOperand(4));
2386 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2387 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the callee.
2389 std::vector<SDOperand> Ops;
2390 for (unsigned i = 2, e = Node->getNumOperands(); i != e; ++i)
2391 Ops.push_back(LegalizeOp(Node->getOperand(i)));
2393 assert(Node->getNumValues() == 2 && Op.ResNo == 0 &&
2394 "Can only promote single result calls");
2395 std::vector<MVT::ValueType> RetTyVTs;
2396 RetTyVTs.reserve(2);
2397 RetTyVTs.push_back(NVT);
2398 RetTyVTs.push_back(MVT::Other);
2399 SDNode *NC = DAG.getCall(RetTyVTs, Tmp1, Tmp2, Ops,
2400 Node->getOpcode() == ISD::TAILCALL);
2401 Result = SDOperand(NC, 0);
2403 // Insert the new chain mapping.
2404 AddLegalizedOperand(Op.getValue(1), Result.getValue(1));
2410 Tmp1 = Node->getOperand(0);
2411 //Zero extend the argument
2412 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1);
2413 // Perform the larger operation, then subtract if needed.
2414 Tmp1 = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
2415 switch(Node->getOpcode())
2421 //if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT)
2422 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), Tmp1,
2423 DAG.getConstant(getSizeInBits(NVT), NVT), ISD::SETEQ);
2424 Result = DAG.getNode(ISD::SELECT, NVT, Tmp2,
2425 DAG.getConstant(getSizeInBits(VT),NVT), Tmp1);
2428 //Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT))
2429 Result = DAG.getNode(ISD::SUB, NVT, Tmp1,
2430 DAG.getConstant(getSizeInBits(NVT) -
2431 getSizeInBits(VT), NVT));
2437 assert(Result.Val && "Didn't set a result!");
2438 AddPromotedOperand(Op, Result);
2442 /// ExpandAddSub - Find a clever way to expand this add operation into
2444 void SelectionDAGLegalize::
2445 ExpandByParts(unsigned NodeOp, SDOperand LHS, SDOperand RHS,
2446 SDOperand &Lo, SDOperand &Hi) {
2447 // Expand the subcomponents.
2448 SDOperand LHSL, LHSH, RHSL, RHSH;
2449 ExpandOp(LHS, LHSL, LHSH);
2450 ExpandOp(RHS, RHSL, RHSH);
2452 // FIXME: this should be moved to the dag combiner someday.
2453 assert(NodeOp == ISD::ADD_PARTS || NodeOp == ISD::SUB_PARTS);
2454 if (LHSL.getValueType() == MVT::i32) {
2455 SDOperand LowEl = SDOperand(0,0);
2456 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(LHSL))
2457 if (C->getValue() == 0)
2459 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHSL))
2460 if (C->getValue() == 0)
2463 // Turn this into an add/sub of the high part only.
2465 DAG.getNode(NodeOp == ISD::ADD_PARTS ? ISD::ADD : ISD::SUB,
2466 LowEl.getValueType(), LHSH, RHSH);
2473 std::vector<SDOperand> Ops;
2474 Ops.push_back(LHSL);
2475 Ops.push_back(LHSH);
2476 Ops.push_back(RHSL);
2477 Ops.push_back(RHSH);
2479 std::vector<MVT::ValueType> VTs(2, LHSL.getValueType());
2480 Lo = DAG.getNode(NodeOp, VTs, Ops);
2481 Hi = Lo.getValue(1);
2484 void SelectionDAGLegalize::ExpandShiftParts(unsigned NodeOp,
2485 SDOperand Op, SDOperand Amt,
2486 SDOperand &Lo, SDOperand &Hi) {
2487 // Expand the subcomponents.
2488 SDOperand LHSL, LHSH;
2489 ExpandOp(Op, LHSL, LHSH);
2491 std::vector<SDOperand> Ops;
2492 Ops.push_back(LHSL);
2493 Ops.push_back(LHSH);
2495 std::vector<MVT::ValueType> VTs(2, LHSL.getValueType());
2496 Lo = DAG.getNode(NodeOp, VTs, Ops);
2497 Hi = Lo.getValue(1);
2501 /// ExpandShift - Try to find a clever way to expand this shift operation out to
2502 /// smaller elements. If we can't find a way that is more efficient than a
2503 /// libcall on this target, return false. Otherwise, return true with the
2504 /// low-parts expanded into Lo and Hi.
2505 bool SelectionDAGLegalize::ExpandShift(unsigned Opc, SDOperand Op,SDOperand Amt,
2506 SDOperand &Lo, SDOperand &Hi) {
2507 assert((Opc == ISD::SHL || Opc == ISD::SRA || Opc == ISD::SRL) &&
2508 "This is not a shift!");
2510 MVT::ValueType NVT = TLI.getTypeToTransformTo(Op.getValueType());
2511 SDOperand ShAmt = LegalizeOp(Amt);
2512 MVT::ValueType ShTy = ShAmt.getValueType();
2513 unsigned VTBits = MVT::getSizeInBits(Op.getValueType());
2514 unsigned NVTBits = MVT::getSizeInBits(NVT);
2516 // Handle the case when Amt is an immediate. Other cases are currently broken
2517 // and are disabled.
2518 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Amt.Val)) {
2519 unsigned Cst = CN->getValue();
2520 // Expand the incoming operand to be shifted, so that we have its parts
2522 ExpandOp(Op, InL, InH);
2526 Lo = DAG.getConstant(0, NVT);
2527 Hi = DAG.getConstant(0, NVT);
2528 } else if (Cst > NVTBits) {
2529 Lo = DAG.getConstant(0, NVT);
2530 Hi = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Cst-NVTBits,ShTy));
2531 } else if (Cst == NVTBits) {
2532 Lo = DAG.getConstant(0, NVT);
2535 Lo = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Cst, ShTy));
2536 Hi = DAG.getNode(ISD::OR, NVT,
2537 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(Cst, ShTy)),
2538 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(NVTBits-Cst, ShTy)));
2543 Lo = DAG.getConstant(0, NVT);
2544 Hi = DAG.getConstant(0, NVT);
2545 } else if (Cst > NVTBits) {
2546 Lo = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Cst-NVTBits,ShTy));
2547 Hi = DAG.getConstant(0, NVT);
2548 } else if (Cst == NVTBits) {
2550 Hi = DAG.getConstant(0, NVT);
2552 Lo = DAG.getNode(ISD::OR, NVT,
2553 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(Cst, ShTy)),
2554 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(NVTBits-Cst, ShTy)));
2555 Hi = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Cst, ShTy));
2560 Hi = Lo = DAG.getNode(ISD::SRA, NVT, InH,
2561 DAG.getConstant(NVTBits-1, ShTy));
2562 } else if (Cst > NVTBits) {
2563 Lo = DAG.getNode(ISD::SRA, NVT, InH,
2564 DAG.getConstant(Cst-NVTBits, ShTy));
2565 Hi = DAG.getNode(ISD::SRA, NVT, InH,
2566 DAG.getConstant(NVTBits-1, ShTy));
2567 } else if (Cst == NVTBits) {
2569 Hi = DAG.getNode(ISD::SRA, NVT, InH,
2570 DAG.getConstant(NVTBits-1, ShTy));
2572 Lo = DAG.getNode(ISD::OR, NVT,
2573 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(Cst, ShTy)),
2574 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(NVTBits-Cst, ShTy)));
2575 Hi = DAG.getNode(ISD::SRA, NVT, InH, DAG.getConstant(Cst, ShTy));
2580 // FIXME: The following code for expanding shifts using ISD::SELECT is buggy,
2581 // so disable it for now. Currently targets are handling this via SHL_PARTS
2585 // If we have an efficient select operation (or if the selects will all fold
2586 // away), lower to some complex code, otherwise just emit the libcall.
2587 if (!TLI.isOperationLegal(ISD::SELECT, NVT) && !isa<ConstantSDNode>(Amt))
2591 ExpandOp(Op, InL, InH);
2592 SDOperand NAmt = DAG.getNode(ISD::SUB, ShTy, // NAmt = 32-ShAmt
2593 DAG.getConstant(NVTBits, ShTy), ShAmt);
2595 // Compare the unmasked shift amount against 32.
2596 SDOperand Cond = DAG.getSetCC(TLI.getSetCCResultTy(), ShAmt,
2597 DAG.getConstant(NVTBits, ShTy), ISD::SETGE);
2599 if (TLI.getShiftAmountFlavor() != TargetLowering::Mask) {
2600 ShAmt = DAG.getNode(ISD::AND, ShTy, ShAmt, // ShAmt &= 31
2601 DAG.getConstant(NVTBits-1, ShTy));
2602 NAmt = DAG.getNode(ISD::AND, ShTy, NAmt, // NAmt &= 31
2603 DAG.getConstant(NVTBits-1, ShTy));
2606 if (Opc == ISD::SHL) {
2607 SDOperand T1 = DAG.getNode(ISD::OR, NVT,// T1 = (Hi << Amt) | (Lo >> NAmt)
2608 DAG.getNode(ISD::SHL, NVT, InH, ShAmt),
2609 DAG.getNode(ISD::SRL, NVT, InL, NAmt));
2610 SDOperand T2 = DAG.getNode(ISD::SHL, NVT, InL, ShAmt); // T2 = Lo << Amt&31
2612 Hi = DAG.getNode(ISD::SELECT, NVT, Cond, T2, T1);
2613 Lo = DAG.getNode(ISD::SELECT, NVT, Cond, DAG.getConstant(0, NVT), T2);
2615 SDOperand HiLoPart = DAG.getNode(ISD::SELECT, NVT,
2616 DAG.getSetCC(TLI.getSetCCResultTy(), NAmt,
2617 DAG.getConstant(32, ShTy),
2619 DAG.getConstant(0, NVT),
2620 DAG.getNode(ISD::SHL, NVT, InH, NAmt));
2621 SDOperand T1 = DAG.getNode(ISD::OR, NVT,// T1 = (Hi << NAmt) | (Lo >> Amt)
2623 DAG.getNode(ISD::SRL, NVT, InL, ShAmt));
2624 SDOperand T2 = DAG.getNode(Opc, NVT, InH, ShAmt); // T2 = InH >> ShAmt&31
2627 if (Opc == ISD::SRA)
2628 HiPart = DAG.getNode(ISD::SRA, NVT, InH,
2629 DAG.getConstant(NVTBits-1, ShTy));
2631 HiPart = DAG.getConstant(0, NVT);
2632 Lo = DAG.getNode(ISD::SELECT, NVT, Cond, T2, T1);
2633 Hi = DAG.getNode(ISD::SELECT, NVT, Cond, HiPart, T2);
2638 /// FindLatestCallSeqStart - Scan up the dag to find the latest (highest
2639 /// NodeDepth) node that is an CallSeqStart operation and occurs later than
2641 static void FindLatestCallSeqStart(SDNode *Node, SDNode *&Found) {
2642 if (Node->getNodeDepth() <= Found->getNodeDepth()) return;
2644 // If we found an CALLSEQ_START, we already know this node occurs later
2645 // than the Found node. Just remember this node and return.
2646 if (Node->getOpcode() == ISD::CALLSEQ_START) {
2651 // Otherwise, scan the operands of Node to see if any of them is a call.
2652 assert(Node->getNumOperands() != 0 &&
2653 "All leaves should have depth equal to the entry node!");
2654 for (unsigned i = 0, e = Node->getNumOperands()-1; i != e; ++i)
2655 FindLatestCallSeqStart(Node->getOperand(i).Val, Found);
2657 // Tail recurse for the last iteration.
2658 FindLatestCallSeqStart(Node->getOperand(Node->getNumOperands()-1).Val,
2663 /// FindEarliestCallSeqEnd - Scan down the dag to find the earliest (lowest
2664 /// NodeDepth) node that is an CallSeqEnd operation and occurs more recent
2666 static void FindEarliestCallSeqEnd(SDNode *Node, SDNode *&Found,
2667 std::set<SDNode*> &Visited) {
2668 if ((Found && Node->getNodeDepth() >= Found->getNodeDepth()) ||
2669 !Visited.insert(Node).second) return;
2671 // If we found an CALLSEQ_END, we already know this node occurs earlier
2672 // than the Found node. Just remember this node and return.
2673 if (Node->getOpcode() == ISD::CALLSEQ_END) {
2678 // Otherwise, scan the operands of Node to see if any of them is a call.
2679 SDNode::use_iterator UI = Node->use_begin(), E = Node->use_end();
2680 if (UI == E) return;
2681 for (--E; UI != E; ++UI)
2682 FindEarliestCallSeqEnd(*UI, Found, Visited);
2684 // Tail recurse for the last iteration.
2685 FindEarliestCallSeqEnd(*UI, Found, Visited);
2688 /// FindCallSeqEnd - Given a chained node that is part of a call sequence,
2689 /// find the CALLSEQ_END node that terminates the call sequence.
2690 static SDNode *FindCallSeqEnd(SDNode *Node) {
2691 if (Node->getOpcode() == ISD::CALLSEQ_END)
2693 if (Node->use_empty())
2694 return 0; // No CallSeqEnd
2696 SDOperand TheChain(Node, Node->getNumValues()-1);
2697 if (TheChain.getValueType() != MVT::Other)
2698 TheChain = SDOperand(Node, 0);
2699 if (TheChain.getValueType() != MVT::Other)
2702 for (SDNode::use_iterator UI = Node->use_begin(),
2703 E = Node->use_end(); UI != E; ++UI) {
2705 // Make sure to only follow users of our token chain.
2707 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i)
2708 if (User->getOperand(i) == TheChain)
2709 if (SDNode *Result = FindCallSeqEnd(User))
2715 /// FindCallSeqStart - Given a chained node that is part of a call sequence,
2716 /// find the CALLSEQ_START node that initiates the call sequence.
2717 static SDNode *FindCallSeqStart(SDNode *Node) {
2718 assert(Node && "Didn't find callseq_start for a call??");
2719 if (Node->getOpcode() == ISD::CALLSEQ_START) return Node;
2721 assert(Node->getOperand(0).getValueType() == MVT::Other &&
2722 "Node doesn't have a token chain argument!");
2723 return FindCallSeqStart(Node->getOperand(0).Val);
2727 /// FindInputOutputChains - If we are replacing an operation with a call we need
2728 /// to find the call that occurs before and the call that occurs after it to
2729 /// properly serialize the calls in the block. The returned operand is the
2730 /// input chain value for the new call (e.g. the entry node or the previous
2731 /// call), and OutChain is set to be the chain node to update to point to the
2732 /// end of the call chain.
2733 static SDOperand FindInputOutputChains(SDNode *OpNode, SDNode *&OutChain,
2735 SDNode *LatestCallSeqStart = Entry.Val;
2736 SDNode *LatestCallSeqEnd = 0;
2737 FindLatestCallSeqStart(OpNode, LatestCallSeqStart);
2738 //std::cerr<<"Found node: "; LatestCallSeqStart->dump(); std::cerr <<"\n";
2740 // It is possible that no ISD::CALLSEQ_START was found because there is no
2741 // previous call in the function. LatestCallStackDown may in that case be
2742 // the entry node itself. Do not attempt to find a matching CALLSEQ_END
2743 // unless LatestCallStackDown is an CALLSEQ_START.
2744 if (LatestCallSeqStart->getOpcode() == ISD::CALLSEQ_START) {
2745 LatestCallSeqEnd = FindCallSeqEnd(LatestCallSeqStart);
2746 //std::cerr<<"Found end node: "; LatestCallSeqEnd->dump(); std::cerr <<"\n";
2748 LatestCallSeqEnd = Entry.Val;
2750 assert(LatestCallSeqEnd && "NULL return from FindCallSeqEnd");
2752 // Finally, find the first call that this must come before, first we find the
2753 // CallSeqEnd that ends the call.
2755 std::set<SDNode*> Visited;
2756 FindEarliestCallSeqEnd(OpNode, OutChain, Visited);
2758 // If we found one, translate from the adj up to the callseq_start.
2760 OutChain = FindCallSeqStart(OutChain);
2762 return SDOperand(LatestCallSeqEnd, 0);
2765 /// SpliceCallInto - Given the result chain of a libcall (CallResult), and a
2766 void SelectionDAGLegalize::SpliceCallInto(const SDOperand &CallResult,
2768 // Nothing to splice it into?
2769 if (OutChain == 0) return;
2771 assert(OutChain->getOperand(0).getValueType() == MVT::Other);
2774 // Form a token factor node merging the old inval and the new inval.
2775 SDOperand InToken = DAG.getNode(ISD::TokenFactor, MVT::Other, CallResult,
2776 OutChain->getOperand(0));
2777 // Change the node to refer to the new token.
2778 OutChain->setAdjCallChain(InToken);
2782 // ExpandLibCall - Expand a node into a call to a libcall. If the result value
2783 // does not fit into a register, return the lo part and set the hi part to the
2784 // by-reg argument. If it does fit into a single register, return the result
2785 // and leave the Hi part unset.
2786 SDOperand SelectionDAGLegalize::ExpandLibCall(const char *Name, SDNode *Node,
2789 SDOperand InChain = FindInputOutputChains(Node, OutChain,
2790 DAG.getEntryNode());
2791 if (InChain.Val == 0)
2792 InChain = DAG.getEntryNode();
2794 TargetLowering::ArgListTy Args;
2795 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
2796 MVT::ValueType ArgVT = Node->getOperand(i).getValueType();
2797 const Type *ArgTy = MVT::getTypeForValueType(ArgVT);
2798 Args.push_back(std::make_pair(Node->getOperand(i), ArgTy));
2800 SDOperand Callee = DAG.getExternalSymbol(Name, TLI.getPointerTy());
2802 // Splice the libcall in wherever FindInputOutputChains tells us to.
2803 const Type *RetTy = MVT::getTypeForValueType(Node->getValueType(0));
2804 std::pair<SDOperand,SDOperand> CallInfo =
2805 TLI.LowerCallTo(InChain, RetTy, false, CallingConv::C, false,
2809 switch (getTypeAction(CallInfo.first.getValueType())) {
2810 default: assert(0 && "Unknown thing");
2812 Result = CallInfo.first;
2815 assert(0 && "Cannot promote this yet!");
2817 ExpandOp(CallInfo.first, Result, Hi);
2818 CallInfo.second = LegalizeOp(CallInfo.second);
2822 SpliceCallInto(CallInfo.second, OutChain);
2823 NeedsAnotherIteration = true;
2828 /// ExpandIntToFP - Expand a [US]INT_TO_FP operation, assuming that the
2829 /// destination type is legal.
2830 SDOperand SelectionDAGLegalize::
2831 ExpandIntToFP(bool isSigned, MVT::ValueType DestTy, SDOperand Source) {
2832 assert(isTypeLegal(DestTy) && "Destination type is not legal!");
2833 assert(getTypeAction(Source.getValueType()) == Expand &&
2834 "This is not an expansion!");
2835 assert(Source.getValueType() == MVT::i64 && "Only handle expand from i64!");
2838 assert(Source.getValueType() == MVT::i64 &&
2839 "This only works for 64-bit -> FP");
2840 // The 64-bit value loaded will be incorrectly if the 'sign bit' of the
2841 // incoming integer is set. To handle this, we dynamically test to see if
2842 // it is set, and, if so, add a fudge factor.
2844 ExpandOp(Source, Lo, Hi);
2846 // If this is unsigned, and not supported, first perform the conversion to
2847 // signed, then adjust the result if the sign bit is set.
2848 SDOperand SignedConv = ExpandIntToFP(true, DestTy,
2849 DAG.getNode(ISD::BUILD_PAIR, Source.getValueType(), Lo, Hi));
2851 SDOperand SignSet = DAG.getSetCC(TLI.getSetCCResultTy(), Hi,
2852 DAG.getConstant(0, Hi.getValueType()),
2854 SDOperand Zero = getIntPtrConstant(0), Four = getIntPtrConstant(4);
2855 SDOperand CstOffset = DAG.getNode(ISD::SELECT, Zero.getValueType(),
2856 SignSet, Four, Zero);
2857 uint64_t FF = 0x5f800000ULL;
2858 if (TLI.isLittleEndian()) FF <<= 32;
2859 static Constant *FudgeFactor = ConstantUInt::get(Type::ULongTy, FF);
2861 SDOperand CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy());
2862 CPIdx = DAG.getNode(ISD::ADD, TLI.getPointerTy(), CPIdx, CstOffset);
2863 SDOperand FudgeInReg;
2864 if (DestTy == MVT::f32)
2865 FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx,
2866 DAG.getSrcValue(NULL));
2868 assert(DestTy == MVT::f64 && "Unexpected conversion");
2869 FudgeInReg = DAG.getExtLoad(ISD::EXTLOAD, MVT::f64, DAG.getEntryNode(),
2870 CPIdx, DAG.getSrcValue(NULL), MVT::f32);
2872 return DAG.getNode(ISD::FADD, DestTy, SignedConv, FudgeInReg);
2875 // Check to see if the target has a custom way to lower this. If so, use it.
2876 switch (TLI.getOperationAction(ISD::SINT_TO_FP, Source.getValueType())) {
2877 default: assert(0 && "This action not implemented for this operation!");
2878 case TargetLowering::Legal:
2879 case TargetLowering::Expand:
2880 break; // This case is handled below.
2881 case TargetLowering::Custom: {
2882 SDOperand NV = TLI.LowerOperation(DAG.getNode(ISD::SINT_TO_FP, DestTy,
2885 return LegalizeOp(NV);
2886 break; // The target decided this was legal after all
2890 // Expand the source, then glue it back together for the call. We must expand
2891 // the source in case it is shared (this pass of legalize must traverse it).
2892 SDOperand SrcLo, SrcHi;
2893 ExpandOp(Source, SrcLo, SrcHi);
2894 Source = DAG.getNode(ISD::BUILD_PAIR, Source.getValueType(), SrcLo, SrcHi);
2896 SDNode *OutChain = 0;
2897 SDOperand InChain = FindInputOutputChains(Source.Val, OutChain,
2898 DAG.getEntryNode());
2899 const char *FnName = 0;
2900 if (DestTy == MVT::f32)
2901 FnName = "__floatdisf";
2903 assert(DestTy == MVT::f64 && "Unknown fp value type!");
2904 FnName = "__floatdidf";
2907 SDOperand Callee = DAG.getExternalSymbol(FnName, TLI.getPointerTy());
2909 TargetLowering::ArgListTy Args;
2910 const Type *ArgTy = MVT::getTypeForValueType(Source.getValueType());
2912 Args.push_back(std::make_pair(Source, ArgTy));
2914 // We don't care about token chains for libcalls. We just use the entry
2915 // node as our input and ignore the output chain. This allows us to place
2916 // calls wherever we need them to satisfy data dependences.
2917 const Type *RetTy = MVT::getTypeForValueType(DestTy);
2919 std::pair<SDOperand,SDOperand> CallResult =
2920 TLI.LowerCallTo(InChain, RetTy, false, CallingConv::C, true,
2923 SpliceCallInto(CallResult.second, OutChain);
2924 return CallResult.first;
2929 /// ExpandOp - Expand the specified SDOperand into its two component pieces
2930 /// Lo&Hi. Note that the Op MUST be an expanded type. As a result of this, the
2931 /// LegalizeNodes map is filled in for any results that are not expanded, the
2932 /// ExpandedNodes map is filled in for any results that are expanded, and the
2933 /// Lo/Hi values are returned.
2934 void SelectionDAGLegalize::ExpandOp(SDOperand Op, SDOperand &Lo, SDOperand &Hi){
2935 MVT::ValueType VT = Op.getValueType();
2936 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT);
2937 SDNode *Node = Op.Val;
2938 assert(getTypeAction(VT) == Expand && "Not an expanded type!");
2939 assert(MVT::isInteger(VT) && "Cannot expand FP values!");
2940 assert(MVT::isInteger(NVT) && NVT < VT &&
2941 "Cannot expand to FP value or to larger int value!");
2943 // See if we already expanded it.
2944 std::map<SDOperand, std::pair<SDOperand, SDOperand> >::iterator I
2945 = ExpandedNodes.find(Op);
2946 if (I != ExpandedNodes.end()) {
2947 Lo = I->second.first;
2948 Hi = I->second.second;
2952 // Expanding to multiple registers needs to perform an optimization step, and
2953 // is not careful to avoid operations the target does not support. Make sure
2954 // that all generated operations are legalized in the next iteration.
2955 NeedsAnotherIteration = true;
2957 switch (Node->getOpcode()) {
2958 case ISD::CopyFromReg:
2959 assert(0 && "CopyFromReg must be legal!");
2961 std::cerr << "NODE: "; Node->dump(); std::cerr << "\n";
2962 assert(0 && "Do not know how to expand this operator!");
2965 Lo = DAG.getNode(ISD::UNDEF, NVT);
2966 Hi = DAG.getNode(ISD::UNDEF, NVT);
2968 case ISD::Constant: {
2969 uint64_t Cst = cast<ConstantSDNode>(Node)->getValue();
2970 Lo = DAG.getConstant(Cst, NVT);
2971 Hi = DAG.getConstant(Cst >> MVT::getSizeInBits(NVT), NVT);
2975 case ISD::BUILD_PAIR:
2976 // Legalize both operands. FIXME: in the future we should handle the case
2977 // where the two elements are not legal.
2978 assert(isTypeLegal(NVT) && "Cannot expand this multiple times yet!");
2979 Lo = LegalizeOp(Node->getOperand(0));
2980 Hi = LegalizeOp(Node->getOperand(1));
2984 ExpandOp(Node->getOperand(0), Lo, Hi);
2985 Lo = DAG.getNode(ISD::ADD, NVT, // ctpop(HL) -> ctpop(H)+ctpop(L)
2986 DAG.getNode(ISD::CTPOP, NVT, Lo),
2987 DAG.getNode(ISD::CTPOP, NVT, Hi));
2988 Hi = DAG.getConstant(0, NVT);
2992 // ctlz (HL) -> ctlz(H) != 32 ? ctlz(H) : (ctlz(L)+32)
2993 ExpandOp(Node->getOperand(0), Lo, Hi);
2994 SDOperand BitsC = DAG.getConstant(MVT::getSizeInBits(NVT), NVT);
2995 SDOperand HLZ = DAG.getNode(ISD::CTLZ, NVT, Hi);
2996 SDOperand TopNotZero = DAG.getSetCC(TLI.getSetCCResultTy(), HLZ, BitsC,
2998 SDOperand LowPart = DAG.getNode(ISD::CTLZ, NVT, Lo);
2999 LowPart = DAG.getNode(ISD::ADD, NVT, LowPart, BitsC);
3001 Lo = DAG.getNode(ISD::SELECT, NVT, TopNotZero, HLZ, LowPart);
3002 Hi = DAG.getConstant(0, NVT);
3007 // cttz (HL) -> cttz(L) != 32 ? cttz(L) : (cttz(H)+32)
3008 ExpandOp(Node->getOperand(0), Lo, Hi);
3009 SDOperand BitsC = DAG.getConstant(MVT::getSizeInBits(NVT), NVT);
3010 SDOperand LTZ = DAG.getNode(ISD::CTTZ, NVT, Lo);
3011 SDOperand BotNotZero = DAG.getSetCC(TLI.getSetCCResultTy(), LTZ, BitsC,
3013 SDOperand HiPart = DAG.getNode(ISD::CTTZ, NVT, Hi);
3014 HiPart = DAG.getNode(ISD::ADD, NVT, HiPart, BitsC);
3016 Lo = DAG.getNode(ISD::SELECT, NVT, BotNotZero, LTZ, HiPart);
3017 Hi = DAG.getConstant(0, NVT);
3022 SDOperand Ch = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
3023 SDOperand Ptr = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
3024 Lo = DAG.getLoad(NVT, Ch, Ptr, Node->getOperand(2));
3026 // Increment the pointer to the other half.
3027 unsigned IncrementSize = MVT::getSizeInBits(Lo.getValueType())/8;
3028 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
3029 getIntPtrConstant(IncrementSize));
3030 //Is this safe? declaring that the two parts of the split load
3031 //are from the same instruction?
3032 Hi = DAG.getLoad(NVT, Ch, Ptr, Node->getOperand(2));
3034 // Build a factor node to remember that this load is independent of the
3036 SDOperand TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
3039 // Remember that we legalized the chain.
3040 AddLegalizedOperand(Op.getValue(1), TF);
3041 if (!TLI.isLittleEndian())
3047 SDOperand Chain = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
3048 SDOperand Callee = LegalizeOp(Node->getOperand(1)); // Legalize the callee.
3050 bool Changed = false;
3051 std::vector<SDOperand> Ops;
3052 for (unsigned i = 2, e = Node->getNumOperands(); i != e; ++i) {
3053 Ops.push_back(LegalizeOp(Node->getOperand(i)));
3054 Changed |= Ops.back() != Node->getOperand(i);
3057 assert(Node->getNumValues() == 2 && Op.ResNo == 0 &&
3058 "Can only expand a call once so far, not i64 -> i16!");
3060 std::vector<MVT::ValueType> RetTyVTs;
3061 RetTyVTs.reserve(3);
3062 RetTyVTs.push_back(NVT);
3063 RetTyVTs.push_back(NVT);
3064 RetTyVTs.push_back(MVT::Other);
3065 SDNode *NC = DAG.getCall(RetTyVTs, Chain, Callee, Ops,
3066 Node->getOpcode() == ISD::TAILCALL);
3067 Lo = SDOperand(NC, 0);
3068 Hi = SDOperand(NC, 1);
3070 // Insert the new chain mapping.
3071 AddLegalizedOperand(Op.getValue(1), Hi.getValue(2));
3076 case ISD::XOR: { // Simple logical operators -> two trivial pieces.
3077 SDOperand LL, LH, RL, RH;
3078 ExpandOp(Node->getOperand(0), LL, LH);
3079 ExpandOp(Node->getOperand(1), RL, RH);
3080 Lo = DAG.getNode(Node->getOpcode(), NVT, LL, RL);
3081 Hi = DAG.getNode(Node->getOpcode(), NVT, LH, RH);
3085 SDOperand C, LL, LH, RL, RH;
3087 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3088 case Expand: assert(0 && "It's impossible to expand bools");
3090 C = LegalizeOp(Node->getOperand(0)); // Legalize the condition.
3093 C = PromoteOp(Node->getOperand(0)); // Promote the condition.
3096 ExpandOp(Node->getOperand(1), LL, LH);
3097 ExpandOp(Node->getOperand(2), RL, RH);
3098 Lo = DAG.getNode(ISD::SELECT, NVT, C, LL, RL);
3099 Hi = DAG.getNode(ISD::SELECT, NVT, C, LH, RH);
3102 case ISD::SELECT_CC: {
3103 SDOperand TL, TH, FL, FH;
3104 ExpandOp(Node->getOperand(2), TL, TH);
3105 ExpandOp(Node->getOperand(3), FL, FH);
3106 Lo = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0),
3107 Node->getOperand(1), TL, FL, Node->getOperand(4));
3108 Hi = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0),
3109 Node->getOperand(1), TH, FH, Node->getOperand(4));
3110 Lo = LegalizeOp(Lo);
3111 Hi = LegalizeOp(Hi);
3114 case ISD::SEXTLOAD: {
3115 SDOperand Chain = LegalizeOp(Node->getOperand(0));
3116 SDOperand Ptr = LegalizeOp(Node->getOperand(1));
3117 MVT::ValueType EVT = cast<VTSDNode>(Node->getOperand(3))->getVT();
3120 Lo = DAG.getLoad(NVT, Chain, Ptr, Node->getOperand(2));
3122 Lo = DAG.getExtLoad(ISD::SEXTLOAD, NVT, Chain, Ptr, Node->getOperand(2),
3124 // The high part is obtained by SRA'ing all but one of the bits of the lo
3126 unsigned LoSize = MVT::getSizeInBits(Lo.getValueType());
3127 Hi = DAG.getNode(ISD::SRA, NVT, Lo, DAG.getConstant(LoSize-1,
3128 TLI.getShiftAmountTy()));
3129 Lo = LegalizeOp(Lo);
3130 Hi = LegalizeOp(Hi);
3133 case ISD::ZEXTLOAD: {
3134 SDOperand Chain = LegalizeOp(Node->getOperand(0));
3135 SDOperand Ptr = LegalizeOp(Node->getOperand(1));
3136 MVT::ValueType EVT = cast<VTSDNode>(Node->getOperand(3))->getVT();
3139 Lo = DAG.getLoad(NVT, Chain, Ptr, Node->getOperand(2));
3141 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, NVT, Chain, Ptr, Node->getOperand(2),
3143 // The high part is just a zero.
3144 Hi = DAG.getConstant(0, NVT);
3145 Lo = LegalizeOp(Lo);
3146 Hi = LegalizeOp(Hi);
3149 case ISD::ANY_EXTEND: {
3151 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3152 case Expand: assert(0 && "expand-expand not implemented yet!");
3153 case Legal: In = LegalizeOp(Node->getOperand(0)); break;
3155 In = PromoteOp(Node->getOperand(0));
3159 // The low part is any extension of the input (which degenerates to a copy).
3160 Lo = DAG.getNode(ISD::ANY_EXTEND, NVT, In);
3161 // The high part is undefined.
3162 Hi = DAG.getNode(ISD::UNDEF, NVT);
3165 case ISD::SIGN_EXTEND: {
3167 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3168 case Expand: assert(0 && "expand-expand not implemented yet!");
3169 case Legal: In = LegalizeOp(Node->getOperand(0)); break;
3171 In = PromoteOp(Node->getOperand(0));
3172 // Emit the appropriate sign_extend_inreg to get the value we want.
3173 In = DAG.getNode(ISD::SIGN_EXTEND_INREG, In.getValueType(), In,
3174 DAG.getValueType(Node->getOperand(0).getValueType()));
3178 // The low part is just a sign extension of the input (which degenerates to
3180 Lo = DAG.getNode(ISD::SIGN_EXTEND, NVT, In);
3182 // The high part is obtained by SRA'ing all but one of the bits of the lo
3184 unsigned LoSize = MVT::getSizeInBits(Lo.getValueType());
3185 Hi = DAG.getNode(ISD::SRA, NVT, Lo, DAG.getConstant(LoSize-1,
3186 TLI.getShiftAmountTy()));
3189 case ISD::ZERO_EXTEND: {
3191 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3192 case Expand: assert(0 && "expand-expand not implemented yet!");
3193 case Legal: In = LegalizeOp(Node->getOperand(0)); break;
3195 In = PromoteOp(Node->getOperand(0));
3196 // Emit the appropriate zero_extend_inreg to get the value we want.
3197 In = DAG.getZeroExtendInReg(In, Node->getOperand(0).getValueType());
3201 // The low part is just a zero extension of the input (which degenerates to
3203 Lo = DAG.getNode(ISD::ZERO_EXTEND, NVT, In);
3205 // The high part is just a zero.
3206 Hi = DAG.getConstant(0, NVT);
3209 // These operators cannot be expanded directly, emit them as calls to
3210 // library functions.
3211 case ISD::FP_TO_SINT:
3212 if (TLI.getOperationAction(ISD::FP_TO_SINT, VT) == TargetLowering::Custom) {
3214 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3215 case Expand: assert(0 && "cannot expand FP!");
3216 case Legal: Op = LegalizeOp(Node->getOperand(0)); break;
3217 case Promote: Op = PromoteOp(Node->getOperand(0)); break;
3220 Op = TLI.LowerOperation(DAG.getNode(ISD::FP_TO_SINT, VT, Op), DAG);
3222 // Now that the custom expander is done, expand the result, which is still
3225 ExpandOp(Op, Lo, Hi);
3230 if (Node->getOperand(0).getValueType() == MVT::f32)
3231 Lo = ExpandLibCall("__fixsfdi", Node, Hi);
3233 Lo = ExpandLibCall("__fixdfdi", Node, Hi);
3236 case ISD::FP_TO_UINT:
3237 if (TLI.getOperationAction(ISD::FP_TO_UINT, VT) == TargetLowering::Custom) {
3238 SDOperand Op = DAG.getNode(ISD::FP_TO_UINT, VT,
3239 LegalizeOp(Node->getOperand(0)));
3240 // Now that the custom expander is done, expand the result, which is still
3242 Op = TLI.LowerOperation(Op, DAG);
3244 ExpandOp(Op, Lo, Hi);
3249 if (Node->getOperand(0).getValueType() == MVT::f32)
3250 Lo = ExpandLibCall("__fixunssfdi", Node, Hi);
3252 Lo = ExpandLibCall("__fixunsdfdi", Node, Hi);
3256 // If the target wants custom lowering, do so.
3257 if (TLI.getOperationAction(ISD::SHL, VT) == TargetLowering::Custom) {
3258 SDOperand Op = DAG.getNode(ISD::SHL, VT, Node->getOperand(0),
3259 LegalizeOp(Node->getOperand(1)));
3260 Op = TLI.LowerOperation(Op, DAG);
3262 // Now that the custom expander is done, expand the result, which is
3264 ExpandOp(Op, Lo, Hi);
3269 // If we can emit an efficient shift operation, do so now.
3270 if (ExpandShift(ISD::SHL, Node->getOperand(0), Node->getOperand(1), Lo, Hi))
3273 // If this target supports SHL_PARTS, use it.
3274 if (TLI.isOperationLegal(ISD::SHL_PARTS, NVT)) {
3275 ExpandShiftParts(ISD::SHL_PARTS, Node->getOperand(0), Node->getOperand(1),
3280 // Otherwise, emit a libcall.
3281 Lo = ExpandLibCall("__ashldi3", Node, Hi);
3285 // If the target wants custom lowering, do so.
3286 if (TLI.getOperationAction(ISD::SRA, VT) == TargetLowering::Custom) {
3287 SDOperand Op = DAG.getNode(ISD::SRA, VT, Node->getOperand(0),
3288 LegalizeOp(Node->getOperand(1)));
3289 Op = TLI.LowerOperation(Op, DAG);
3291 // Now that the custom expander is done, expand the result, which is
3293 ExpandOp(Op, Lo, Hi);
3298 // If we can emit an efficient shift operation, do so now.
3299 if (ExpandShift(ISD::SRA, Node->getOperand(0), Node->getOperand(1), Lo, Hi))
3302 // If this target supports SRA_PARTS, use it.
3303 if (TLI.isOperationLegal(ISD::SRA_PARTS, NVT)) {
3304 ExpandShiftParts(ISD::SRA_PARTS, Node->getOperand(0), Node->getOperand(1),
3309 // Otherwise, emit a libcall.
3310 Lo = ExpandLibCall("__ashrdi3", Node, Hi);
3313 // If the target wants custom lowering, do so.
3314 if (TLI.getOperationAction(ISD::SRL, VT) == TargetLowering::Custom) {
3315 SDOperand Op = DAG.getNode(ISD::SRL, VT, Node->getOperand(0),
3316 LegalizeOp(Node->getOperand(1)));
3317 Op = TLI.LowerOperation(Op, DAG);
3319 // Now that the custom expander is done, expand the result, which is
3321 ExpandOp(Op, Lo, Hi);
3326 // If we can emit an efficient shift operation, do so now.
3327 if (ExpandShift(ISD::SRL, Node->getOperand(0), Node->getOperand(1), Lo, Hi))
3330 // If this target supports SRL_PARTS, use it.
3331 if (TLI.isOperationLegal(ISD::SRL_PARTS, NVT)) {
3332 ExpandShiftParts(ISD::SRL_PARTS, Node->getOperand(0), Node->getOperand(1),
3337 // Otherwise, emit a libcall.
3338 Lo = ExpandLibCall("__lshrdi3", Node, Hi);
3342 ExpandByParts(ISD::ADD_PARTS, Node->getOperand(0), Node->getOperand(1),
3346 ExpandByParts(ISD::SUB_PARTS, Node->getOperand(0), Node->getOperand(1),
3350 if (TLI.isOperationLegal(ISD::MULHU, NVT)) {
3351 SDOperand LL, LH, RL, RH;
3352 ExpandOp(Node->getOperand(0), LL, LH);
3353 ExpandOp(Node->getOperand(1), RL, RH);
3354 unsigned SH = MVT::getSizeInBits(RH.getValueType())-1;
3355 // MULHS implicitly sign extends its inputs. Check to see if ExpandOp
3356 // extended the sign bit of the low half through the upper half, and if so
3357 // emit a MULHS instead of the alternate sequence that is valid for any
3358 // i64 x i64 multiply.
3359 if (TLI.isOperationLegal(ISD::MULHS, NVT) &&
3360 // is RH an extension of the sign bit of RL?
3361 RH.getOpcode() == ISD::SRA && RH.getOperand(0) == RL &&
3362 RH.getOperand(1).getOpcode() == ISD::Constant &&
3363 cast<ConstantSDNode>(RH.getOperand(1))->getValue() == SH &&
3364 // is LH an extension of the sign bit of LL?
3365 LH.getOpcode() == ISD::SRA && LH.getOperand(0) == LL &&
3366 LH.getOperand(1).getOpcode() == ISD::Constant &&
3367 cast<ConstantSDNode>(LH.getOperand(1))->getValue() == SH) {
3368 Hi = DAG.getNode(ISD::MULHS, NVT, LL, RL);
3370 Hi = DAG.getNode(ISD::MULHU, NVT, LL, RL);
3371 RH = DAG.getNode(ISD::MUL, NVT, LL, RH);
3372 LH = DAG.getNode(ISD::MUL, NVT, LH, RL);
3373 Hi = DAG.getNode(ISD::ADD, NVT, Hi, RH);
3374 Hi = DAG.getNode(ISD::ADD, NVT, Hi, LH);
3376 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL);
3378 Lo = ExpandLibCall("__muldi3" , Node, Hi); break;
3382 case ISD::SDIV: Lo = ExpandLibCall("__divdi3" , Node, Hi); break;
3383 case ISD::UDIV: Lo = ExpandLibCall("__udivdi3", Node, Hi); break;
3384 case ISD::SREM: Lo = ExpandLibCall("__moddi3" , Node, Hi); break;
3385 case ISD::UREM: Lo = ExpandLibCall("__umoddi3", Node, Hi); break;
3388 // Remember in a map if the values will be reused later.
3389 bool isNew = ExpandedNodes.insert(std::make_pair(Op,
3390 std::make_pair(Lo, Hi))).second;
3391 assert(isNew && "Value already expanded?!?");
3395 // SelectionDAG::Legalize - This is the entry point for the file.
3397 void SelectionDAG::Legalize() {
3398 /// run - This is the main entry point to this class.
3400 SelectionDAGLegalize(*this).Run();