1 //===-- LegalizeDAG.cpp - Implement SelectionDAG::Legalize ----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the SelectionDAG::Legalize method.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/CodeGen/SelectionDAG.h"
15 #include "llvm/CodeGen/MachineFunction.h"
16 #include "llvm/CodeGen/MachineFrameInfo.h"
17 #include "llvm/CodeGen/MachineJumpTableInfo.h"
18 #include "llvm/Target/TargetFrameInfo.h"
19 #include "llvm/Target/TargetLowering.h"
20 #include "llvm/Target/TargetData.h"
21 #include "llvm/Target/TargetMachine.h"
22 #include "llvm/Target/TargetOptions.h"
23 #include "llvm/CallingConv.h"
24 #include "llvm/Constants.h"
25 #include "llvm/DerivedTypes.h"
26 #include "llvm/Support/MathExtras.h"
27 #include "llvm/Support/CommandLine.h"
28 #include "llvm/Support/Compiler.h"
29 #include "llvm/ADT/DenseMap.h"
30 #include "llvm/ADT/SmallVector.h"
31 #include "llvm/ADT/SmallPtrSet.h"
37 ViewLegalizeDAGs("view-legalize-dags", cl::Hidden,
38 cl::desc("Pop up a window to show dags before legalize"));
40 static const bool ViewLegalizeDAGs = 0;
43 //===----------------------------------------------------------------------===//
44 /// SelectionDAGLegalize - This takes an arbitrary SelectionDAG as input and
45 /// hacks on it until the target machine can handle it. This involves
46 /// eliminating value sizes the machine cannot handle (promoting small sizes to
47 /// large sizes or splitting up large values into small values) as well as
48 /// eliminating operations the machine cannot handle.
50 /// This code also does a small amount of optimization and recognition of idioms
51 /// as part of its processing. For example, if a target does not support a
52 /// 'setcc' instruction efficiently, but does support 'brcc' instruction, this
53 /// will attempt merge setcc and brc instructions into brcc's.
56 class VISIBILITY_HIDDEN SelectionDAGLegalize {
60 // Libcall insertion helpers.
62 /// LastCALLSEQ_END - This keeps track of the CALLSEQ_END node that has been
63 /// legalized. We use this to ensure that calls are properly serialized
64 /// against each other, including inserted libcalls.
65 SDOperand LastCALLSEQ_END;
67 /// IsLegalizingCall - This member is used *only* for purposes of providing
68 /// helpful assertions that a libcall isn't created while another call is
69 /// being legalized (which could lead to non-serialized call sequences).
70 bool IsLegalizingCall;
73 Legal, // The target natively supports this operation.
74 Promote, // This operation should be executed in a larger type.
75 Expand // Try to expand this to other ops, otherwise use a libcall.
78 /// ValueTypeActions - This is a bitvector that contains two bits for each
79 /// value type, where the two bits correspond to the LegalizeAction enum.
80 /// This can be queried with "getTypeAction(VT)".
81 TargetLowering::ValueTypeActionImpl ValueTypeActions;
83 /// LegalizedNodes - For nodes that are of legal width, and that have more
84 /// than one use, this map indicates what regularized operand to use. This
85 /// allows us to avoid legalizing the same thing more than once.
86 DenseMap<SDOperand, SDOperand> LegalizedNodes;
88 /// PromotedNodes - For nodes that are below legal width, and that have more
89 /// than one use, this map indicates what promoted value to use. This allows
90 /// us to avoid promoting the same thing more than once.
91 DenseMap<SDOperand, SDOperand> PromotedNodes;
93 /// ExpandedNodes - For nodes that need to be expanded this map indicates
94 /// which which operands are the expanded version of the input. This allows
95 /// us to avoid expanding the same node more than once.
96 DenseMap<SDOperand, std::pair<SDOperand, SDOperand> > ExpandedNodes;
98 /// SplitNodes - For vector nodes that need to be split, this map indicates
99 /// which which operands are the split version of the input. This allows us
100 /// to avoid splitting the same node more than once.
101 std::map<SDOperand, std::pair<SDOperand, SDOperand> > SplitNodes;
103 /// ScalarizedNodes - For nodes that need to be converted from vector types to
104 /// scalar types, this contains the mapping of ones we have already
105 /// processed to the result.
106 std::map<SDOperand, SDOperand> ScalarizedNodes;
108 void AddLegalizedOperand(SDOperand From, SDOperand To) {
109 LegalizedNodes.insert(std::make_pair(From, To));
110 // If someone requests legalization of the new node, return itself.
112 LegalizedNodes.insert(std::make_pair(To, To));
114 void AddPromotedOperand(SDOperand From, SDOperand To) {
115 bool isNew = PromotedNodes.insert(std::make_pair(From, To));
116 assert(isNew && "Got into the map somehow?");
117 // If someone requests legalization of the new node, return itself.
118 LegalizedNodes.insert(std::make_pair(To, To));
123 SelectionDAGLegalize(SelectionDAG &DAG);
125 /// getTypeAction - Return how we should legalize values of this type, either
126 /// it is already legal or we need to expand it into multiple registers of
127 /// smaller integer type, or we need to promote it to a larger type.
128 LegalizeAction getTypeAction(MVT::ValueType VT) const {
129 return (LegalizeAction)ValueTypeActions.getTypeAction(VT);
132 /// isTypeLegal - Return true if this type is legal on this target.
134 bool isTypeLegal(MVT::ValueType VT) const {
135 return getTypeAction(VT) == Legal;
141 /// HandleOp - Legalize, Promote, or Expand the specified operand as
142 /// appropriate for its type.
143 void HandleOp(SDOperand Op);
145 /// LegalizeOp - We know that the specified value has a legal type.
146 /// Recursively ensure that the operands have legal types, then return the
148 SDOperand LegalizeOp(SDOperand O);
150 /// PromoteOp - Given an operation that produces a value in an invalid type,
151 /// promote it to compute the value into a larger type. The produced value
152 /// will have the correct bits for the low portion of the register, but no
153 /// guarantee is made about the top bits: it may be zero, sign-extended, or
155 SDOperand PromoteOp(SDOperand O);
157 /// ExpandOp - Expand the specified SDOperand into its two component pieces
158 /// Lo&Hi. Note that the Op MUST be an expanded type. As a result of this,
159 /// the LegalizeNodes map is filled in for any results that are not expanded,
160 /// the ExpandedNodes map is filled in for any results that are expanded, and
161 /// the Lo/Hi values are returned. This applies to integer types and Vector
163 void ExpandOp(SDOperand O, SDOperand &Lo, SDOperand &Hi);
165 /// SplitVectorOp - Given an operand of vector type, break it down into
166 /// two smaller values.
167 void SplitVectorOp(SDOperand O, SDOperand &Lo, SDOperand &Hi);
169 /// ScalarizeVectorOp - Given an operand of single-element vector type
170 /// (e.g. v1f32), convert it into the equivalent operation that returns a
171 /// scalar (e.g. f32) value.
172 SDOperand ScalarizeVectorOp(SDOperand O);
174 /// isShuffleLegal - Return true if a vector shuffle is legal with the
175 /// specified mask and type. Targets can specify exactly which masks they
176 /// support and the code generator is tasked with not creating illegal masks.
178 /// Note that this will also return true for shuffles that are promoted to a
181 /// If this is a legal shuffle, this method returns the (possibly promoted)
182 /// build_vector Mask. If it's not a legal shuffle, it returns null.
183 SDNode *isShuffleLegal(MVT::ValueType VT, SDOperand Mask) const;
185 bool LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest,
186 SmallPtrSet<SDNode*, 32> &NodesLeadingTo);
188 void LegalizeSetCCOperands(SDOperand &LHS, SDOperand &RHS, SDOperand &CC);
190 SDOperand CreateStackTemporary(MVT::ValueType VT);
192 SDOperand ExpandLibCall(const char *Name, SDNode *Node, bool isSigned,
194 SDOperand ExpandIntToFP(bool isSigned, MVT::ValueType DestTy,
197 SDOperand ExpandBIT_CONVERT(MVT::ValueType DestVT, SDOperand SrcOp);
198 SDOperand ExpandBUILD_VECTOR(SDNode *Node);
199 SDOperand ExpandSCALAR_TO_VECTOR(SDNode *Node);
200 SDOperand ExpandLegalINT_TO_FP(bool isSigned,
202 MVT::ValueType DestVT);
203 SDOperand PromoteLegalINT_TO_FP(SDOperand LegalOp, MVT::ValueType DestVT,
205 SDOperand PromoteLegalFP_TO_INT(SDOperand LegalOp, MVT::ValueType DestVT,
208 SDOperand ExpandBSWAP(SDOperand Op);
209 SDOperand ExpandBitCount(unsigned Opc, SDOperand Op);
210 bool ExpandShift(unsigned Opc, SDOperand Op, SDOperand Amt,
211 SDOperand &Lo, SDOperand &Hi);
212 void ExpandShiftParts(unsigned NodeOp, SDOperand Op, SDOperand Amt,
213 SDOperand &Lo, SDOperand &Hi);
215 SDOperand ExpandEXTRACT_SUBVECTOR(SDOperand Op);
216 SDOperand ExpandEXTRACT_VECTOR_ELT(SDOperand Op);
218 SDOperand getIntPtrConstant(uint64_t Val) {
219 return DAG.getConstant(Val, TLI.getPointerTy());
224 /// isVectorShuffleLegal - Return true if a vector shuffle is legal with the
225 /// specified mask and type. Targets can specify exactly which masks they
226 /// support and the code generator is tasked with not creating illegal masks.
228 /// Note that this will also return true for shuffles that are promoted to a
230 SDNode *SelectionDAGLegalize::isShuffleLegal(MVT::ValueType VT,
231 SDOperand Mask) const {
232 switch (TLI.getOperationAction(ISD::VECTOR_SHUFFLE, VT)) {
234 case TargetLowering::Legal:
235 case TargetLowering::Custom:
237 case TargetLowering::Promote: {
238 // If this is promoted to a different type, convert the shuffle mask and
239 // ask if it is legal in the promoted type!
240 MVT::ValueType NVT = TLI.getTypeToPromoteTo(ISD::VECTOR_SHUFFLE, VT);
242 // If we changed # elements, change the shuffle mask.
243 unsigned NumEltsGrowth =
244 MVT::getVectorNumElements(NVT) / MVT::getVectorNumElements(VT);
245 assert(NumEltsGrowth && "Cannot promote to vector type with fewer elts!");
246 if (NumEltsGrowth > 1) {
247 // Renumber the elements.
248 SmallVector<SDOperand, 8> Ops;
249 for (unsigned i = 0, e = Mask.getNumOperands(); i != e; ++i) {
250 SDOperand InOp = Mask.getOperand(i);
251 for (unsigned j = 0; j != NumEltsGrowth; ++j) {
252 if (InOp.getOpcode() == ISD::UNDEF)
253 Ops.push_back(DAG.getNode(ISD::UNDEF, MVT::i32));
255 unsigned InEltNo = cast<ConstantSDNode>(InOp)->getValue();
256 Ops.push_back(DAG.getConstant(InEltNo*NumEltsGrowth+j, MVT::i32));
260 Mask = DAG.getNode(ISD::BUILD_VECTOR, NVT, &Ops[0], Ops.size());
266 return TLI.isShuffleMaskLegal(Mask, VT) ? Mask.Val : 0;
269 SelectionDAGLegalize::SelectionDAGLegalize(SelectionDAG &dag)
270 : TLI(dag.getTargetLoweringInfo()), DAG(dag),
271 ValueTypeActions(TLI.getValueTypeActions()) {
272 assert(MVT::LAST_VALUETYPE <= 32 &&
273 "Too many value types for ValueTypeActions to hold!");
276 /// ComputeTopDownOrdering - Compute a top-down ordering of the dag, where Order
277 /// contains all of a nodes operands before it contains the node.
278 static void ComputeTopDownOrdering(SelectionDAG &DAG,
279 SmallVector<SDNode*, 64> &Order) {
281 DenseMap<SDNode*, unsigned> Visited;
282 std::vector<SDNode*> Worklist;
283 Worklist.reserve(128);
285 // Compute ordering from all of the leaves in the graphs, those (like the
286 // entry node) that have no operands.
287 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(),
288 E = DAG.allnodes_end(); I != E; ++I) {
289 if (I->getNumOperands() == 0) {
291 Worklist.push_back(I);
295 while (!Worklist.empty()) {
296 SDNode *N = Worklist.back();
299 if (++Visited[N] != N->getNumOperands())
300 continue; // Haven't visited all operands yet
304 // Now that we have N in, add anything that uses it if all of their operands
306 for (SDNode::use_iterator UI = N->use_begin(), E = N->use_end();
308 Worklist.push_back(*UI);
311 assert(Order.size() == Visited.size() &&
313 (unsigned)std::distance(DAG.allnodes_begin(), DAG.allnodes_end()) &&
314 "Error: DAG is cyclic!");
318 void SelectionDAGLegalize::LegalizeDAG() {
319 LastCALLSEQ_END = DAG.getEntryNode();
320 IsLegalizingCall = false;
322 // The legalize process is inherently a bottom-up recursive process (users
323 // legalize their uses before themselves). Given infinite stack space, we
324 // could just start legalizing on the root and traverse the whole graph. In
325 // practice however, this causes us to run out of stack space on large basic
326 // blocks. To avoid this problem, compute an ordering of the nodes where each
327 // node is only legalized after all of its operands are legalized.
328 SmallVector<SDNode*, 64> Order;
329 ComputeTopDownOrdering(DAG, Order);
331 for (unsigned i = 0, e = Order.size(); i != e; ++i)
332 HandleOp(SDOperand(Order[i], 0));
334 // Finally, it's possible the root changed. Get the new root.
335 SDOperand OldRoot = DAG.getRoot();
336 assert(LegalizedNodes.count(OldRoot) && "Root didn't get legalized?");
337 DAG.setRoot(LegalizedNodes[OldRoot]);
339 ExpandedNodes.clear();
340 LegalizedNodes.clear();
341 PromotedNodes.clear();
343 ScalarizedNodes.clear();
345 // Remove dead nodes now.
346 DAG.RemoveDeadNodes();
350 /// FindCallEndFromCallStart - Given a chained node that is part of a call
351 /// sequence, find the CALLSEQ_END node that terminates the call sequence.
352 static SDNode *FindCallEndFromCallStart(SDNode *Node) {
353 if (Node->getOpcode() == ISD::CALLSEQ_END)
355 if (Node->use_empty())
356 return 0; // No CallSeqEnd
358 // The chain is usually at the end.
359 SDOperand TheChain(Node, Node->getNumValues()-1);
360 if (TheChain.getValueType() != MVT::Other) {
361 // Sometimes it's at the beginning.
362 TheChain = SDOperand(Node, 0);
363 if (TheChain.getValueType() != MVT::Other) {
364 // Otherwise, hunt for it.
365 for (unsigned i = 1, e = Node->getNumValues(); i != e; ++i)
366 if (Node->getValueType(i) == MVT::Other) {
367 TheChain = SDOperand(Node, i);
371 // Otherwise, we walked into a node without a chain.
372 if (TheChain.getValueType() != MVT::Other)
377 for (SDNode::use_iterator UI = Node->use_begin(),
378 E = Node->use_end(); UI != E; ++UI) {
380 // Make sure to only follow users of our token chain.
382 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i)
383 if (User->getOperand(i) == TheChain)
384 if (SDNode *Result = FindCallEndFromCallStart(User))
390 /// FindCallStartFromCallEnd - Given a chained node that is part of a call
391 /// sequence, find the CALLSEQ_START node that initiates the call sequence.
392 static SDNode *FindCallStartFromCallEnd(SDNode *Node) {
393 assert(Node && "Didn't find callseq_start for a call??");
394 if (Node->getOpcode() == ISD::CALLSEQ_START) return Node;
396 assert(Node->getOperand(0).getValueType() == MVT::Other &&
397 "Node doesn't have a token chain argument!");
398 return FindCallStartFromCallEnd(Node->getOperand(0).Val);
401 /// LegalizeAllNodesNotLeadingTo - Recursively walk the uses of N, looking to
402 /// see if any uses can reach Dest. If no dest operands can get to dest,
403 /// legalize them, legalize ourself, and return false, otherwise, return true.
405 /// Keep track of the nodes we fine that actually do lead to Dest in
406 /// NodesLeadingTo. This avoids retraversing them exponential number of times.
408 bool SelectionDAGLegalize::LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest,
409 SmallPtrSet<SDNode*, 32> &NodesLeadingTo) {
410 if (N == Dest) return true; // N certainly leads to Dest :)
412 // If we've already processed this node and it does lead to Dest, there is no
413 // need to reprocess it.
414 if (NodesLeadingTo.count(N)) return true;
416 // If the first result of this node has been already legalized, then it cannot
418 switch (getTypeAction(N->getValueType(0))) {
420 if (LegalizedNodes.count(SDOperand(N, 0))) return false;
423 if (PromotedNodes.count(SDOperand(N, 0))) return false;
426 if (ExpandedNodes.count(SDOperand(N, 0))) return false;
430 // Okay, this node has not already been legalized. Check and legalize all
431 // operands. If none lead to Dest, then we can legalize this node.
432 bool OperandsLeadToDest = false;
433 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
434 OperandsLeadToDest |= // If an operand leads to Dest, so do we.
435 LegalizeAllNodesNotLeadingTo(N->getOperand(i).Val, Dest, NodesLeadingTo);
437 if (OperandsLeadToDest) {
438 NodesLeadingTo.insert(N);
442 // Okay, this node looks safe, legalize it and return false.
443 HandleOp(SDOperand(N, 0));
447 /// HandleOp - Legalize, Promote, or Expand the specified operand as
448 /// appropriate for its type.
449 void SelectionDAGLegalize::HandleOp(SDOperand Op) {
450 MVT::ValueType VT = Op.getValueType();
451 switch (getTypeAction(VT)) {
452 default: assert(0 && "Bad type action!");
453 case Legal: (void)LegalizeOp(Op); break;
454 case Promote: (void)PromoteOp(Op); break;
456 if (!MVT::isVector(VT)) {
457 // If this is an illegal scalar, expand it into its two component
460 if (Op.getOpcode() == ISD::TargetConstant)
461 break; // Allow illegal target nodes.
463 } else if (MVT::getVectorNumElements(VT) == 1) {
464 // If this is an illegal single element vector, convert it to a
466 (void)ScalarizeVectorOp(Op);
468 // Otherwise, this is an illegal multiple element vector.
469 // Split it in half and legalize both parts.
471 SplitVectorOp(Op, X, Y);
477 /// ExpandConstantFP - Expands the ConstantFP node to an integer constant or
478 /// a load from the constant pool.
479 static SDOperand ExpandConstantFP(ConstantFPSDNode *CFP, bool UseCP,
480 SelectionDAG &DAG, TargetLowering &TLI) {
483 // If a FP immediate is precise when represented as a float and if the
484 // target can do an extending load from float to double, we put it into
485 // the constant pool as a float, even if it's is statically typed as a
487 MVT::ValueType VT = CFP->getValueType(0);
488 bool isDouble = VT == MVT::f64;
489 ConstantFP *LLVMC = ConstantFP::get(MVT::getTypeForValueType(VT),
492 if (VT!=MVT::f64 && VT!=MVT::f32)
493 assert(0 && "Invalid type expansion");
494 return DAG.getConstant(LLVMC->getValueAPF().convertToAPInt().getZExtValue(),
495 isDouble ? MVT::i64 : MVT::i32);
498 if (isDouble && CFP->isValueValidForType(MVT::f32, CFP->getValueAPF()) &&
499 // Only do this if the target has a native EXTLOAD instruction from f32.
500 // Do not try to be clever about long doubles (so far)
501 TLI.isLoadXLegal(ISD::EXTLOAD, MVT::f32)) {
502 LLVMC = cast<ConstantFP>(ConstantExpr::getFPTrunc(LLVMC,Type::FloatTy));
507 SDOperand CPIdx = DAG.getConstantPool(LLVMC, TLI.getPointerTy());
509 return DAG.getExtLoad(ISD::EXTLOAD, MVT::f64, DAG.getEntryNode(),
510 CPIdx, NULL, 0, MVT::f32);
512 return DAG.getLoad(VT, DAG.getEntryNode(), CPIdx, NULL, 0);
517 /// ExpandFCOPYSIGNToBitwiseOps - Expands fcopysign to a series of bitwise
520 SDOperand ExpandFCOPYSIGNToBitwiseOps(SDNode *Node, MVT::ValueType NVT,
521 SelectionDAG &DAG, TargetLowering &TLI) {
522 MVT::ValueType VT = Node->getValueType(0);
523 MVT::ValueType SrcVT = Node->getOperand(1).getValueType();
524 assert((SrcVT == MVT::f32 || SrcVT == MVT::f64) &&
525 "fcopysign expansion only supported for f32 and f64");
526 MVT::ValueType SrcNVT = (SrcVT == MVT::f64) ? MVT::i64 : MVT::i32;
528 // First get the sign bit of second operand.
529 SDOperand Mask1 = (SrcVT == MVT::f64)
530 ? DAG.getConstantFP(BitsToDouble(1ULL << 63), SrcVT)
531 : DAG.getConstantFP(BitsToFloat(1U << 31), SrcVT);
532 Mask1 = DAG.getNode(ISD::BIT_CONVERT, SrcNVT, Mask1);
533 SDOperand SignBit= DAG.getNode(ISD::BIT_CONVERT, SrcNVT, Node->getOperand(1));
534 SignBit = DAG.getNode(ISD::AND, SrcNVT, SignBit, Mask1);
535 // Shift right or sign-extend it if the two operands have different types.
536 int SizeDiff = MVT::getSizeInBits(SrcNVT) - MVT::getSizeInBits(NVT);
538 SignBit = DAG.getNode(ISD::SRL, SrcNVT, SignBit,
539 DAG.getConstant(SizeDiff, TLI.getShiftAmountTy()));
540 SignBit = DAG.getNode(ISD::TRUNCATE, NVT, SignBit);
541 } else if (SizeDiff < 0)
542 SignBit = DAG.getNode(ISD::SIGN_EXTEND, NVT, SignBit);
544 // Clear the sign bit of first operand.
545 SDOperand Mask2 = (VT == MVT::f64)
546 ? DAG.getConstantFP(BitsToDouble(~(1ULL << 63)), VT)
547 : DAG.getConstantFP(BitsToFloat(~(1U << 31)), VT);
548 Mask2 = DAG.getNode(ISD::BIT_CONVERT, NVT, Mask2);
549 SDOperand Result = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0));
550 Result = DAG.getNode(ISD::AND, NVT, Result, Mask2);
552 // Or the value with the sign bit.
553 Result = DAG.getNode(ISD::OR, NVT, Result, SignBit);
557 /// ExpandUnalignedStore - Expands an unaligned store to 2 half-size stores.
559 SDOperand ExpandUnalignedStore(StoreSDNode *ST, SelectionDAG &DAG,
560 TargetLowering &TLI) {
561 SDOperand Chain = ST->getChain();
562 SDOperand Ptr = ST->getBasePtr();
563 SDOperand Val = ST->getValue();
564 MVT::ValueType VT = Val.getValueType();
565 int Alignment = ST->getAlignment();
566 int SVOffset = ST->getSrcValueOffset();
567 if (MVT::isFloatingPoint(ST->getStoredVT())) {
568 // Expand to a bitconvert of the value to the integer type of the
569 // same size, then a (misaligned) int store.
570 MVT::ValueType intVT;
573 else if (VT==MVT::f32)
576 assert(0 && "Unaligned load of unsupported floating point type");
578 SDOperand Result = DAG.getNode(ISD::BIT_CONVERT, intVT, Val);
579 return DAG.getStore(Chain, Result, Ptr, ST->getSrcValue(),
580 SVOffset, ST->isVolatile(), Alignment);
582 assert(MVT::isInteger(ST->getStoredVT()) &&
583 "Unaligned store of unknown type.");
584 // Get the half-size VT
585 MVT::ValueType NewStoredVT = ST->getStoredVT() - 1;
586 int NumBits = MVT::getSizeInBits(NewStoredVT);
587 int IncrementSize = NumBits / 8;
589 // Divide the stored value in two parts.
590 SDOperand ShiftAmount = DAG.getConstant(NumBits, TLI.getShiftAmountTy());
592 SDOperand Hi = DAG.getNode(ISD::SRL, VT, Val, ShiftAmount);
594 // Store the two parts
595 SDOperand Store1, Store2;
596 Store1 = DAG.getTruncStore(Chain, TLI.isLittleEndian()?Lo:Hi, Ptr,
597 ST->getSrcValue(), SVOffset, NewStoredVT,
598 ST->isVolatile(), Alignment);
599 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
600 DAG.getConstant(IncrementSize, TLI.getPointerTy()));
601 Store2 = DAG.getTruncStore(Chain, TLI.isLittleEndian()?Hi:Lo, Ptr,
602 ST->getSrcValue(), SVOffset + IncrementSize,
603 NewStoredVT, ST->isVolatile(), Alignment);
605 return DAG.getNode(ISD::TokenFactor, MVT::Other, Store1, Store2);
608 /// ExpandUnalignedLoad - Expands an unaligned load to 2 half-size loads.
610 SDOperand ExpandUnalignedLoad(LoadSDNode *LD, SelectionDAG &DAG,
611 TargetLowering &TLI) {
612 int SVOffset = LD->getSrcValueOffset();
613 SDOperand Chain = LD->getChain();
614 SDOperand Ptr = LD->getBasePtr();
615 MVT::ValueType VT = LD->getValueType(0);
616 MVT::ValueType LoadedVT = LD->getLoadedVT();
617 if (MVT::isFloatingPoint(VT)) {
618 // Expand to a (misaligned) integer load of the same size,
619 // then bitconvert to floating point.
620 MVT::ValueType intVT;
621 if (LoadedVT==MVT::f64)
623 else if (LoadedVT==MVT::f32)
626 assert(0 && "Unaligned load of unsupported floating point type");
628 SDOperand newLoad = DAG.getLoad(intVT, Chain, Ptr, LD->getSrcValue(),
629 SVOffset, LD->isVolatile(),
631 SDOperand Result = DAG.getNode(ISD::BIT_CONVERT, LoadedVT, newLoad);
633 Result = DAG.getNode(ISD::FP_EXTEND, VT, Result);
635 SDOperand Ops[] = { Result, Chain };
636 return DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(VT, MVT::Other),
639 assert(MVT::isInteger(LoadedVT) && "Unaligned load of unsupported type.");
640 MVT::ValueType NewLoadedVT = LoadedVT - 1;
641 int NumBits = MVT::getSizeInBits(NewLoadedVT);
642 int Alignment = LD->getAlignment();
643 int IncrementSize = NumBits / 8;
644 ISD::LoadExtType HiExtType = LD->getExtensionType();
646 // If the original load is NON_EXTLOAD, the hi part load must be ZEXTLOAD.
647 if (HiExtType == ISD::NON_EXTLOAD)
648 HiExtType = ISD::ZEXTLOAD;
650 // Load the value in two parts
652 if (TLI.isLittleEndian()) {
653 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, VT, Chain, Ptr, LD->getSrcValue(),
654 SVOffset, NewLoadedVT, LD->isVolatile(), Alignment);
655 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
656 DAG.getConstant(IncrementSize, TLI.getPointerTy()));
657 Hi = DAG.getExtLoad(HiExtType, VT, Chain, Ptr, LD->getSrcValue(),
658 SVOffset + IncrementSize, NewLoadedVT, LD->isVolatile(),
661 Hi = DAG.getExtLoad(HiExtType, VT, Chain, Ptr, LD->getSrcValue(), SVOffset,
662 NewLoadedVT,LD->isVolatile(), Alignment);
663 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
664 DAG.getConstant(IncrementSize, TLI.getPointerTy()));
665 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, VT, Chain, Ptr, LD->getSrcValue(),
666 SVOffset + IncrementSize, NewLoadedVT, LD->isVolatile(),
670 // aggregate the two parts
671 SDOperand ShiftAmount = DAG.getConstant(NumBits, TLI.getShiftAmountTy());
672 SDOperand Result = DAG.getNode(ISD::SHL, VT, Hi, ShiftAmount);
673 Result = DAG.getNode(ISD::OR, VT, Result, Lo);
675 SDOperand TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
678 SDOperand Ops[] = { Result, TF };
679 return DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(VT, MVT::Other), Ops, 2);
682 /// LegalizeOp - We know that the specified value has a legal type, and
683 /// that its operands are legal. Now ensure that the operation itself
684 /// is legal, recursively ensuring that the operands' operations remain
686 SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
687 if (Op.getOpcode() == ISD::TargetConstant) // Allow illegal target nodes.
690 assert(isTypeLegal(Op.getValueType()) &&
691 "Caller should expand or promote operands that are not legal!");
692 SDNode *Node = Op.Val;
694 // If this operation defines any values that cannot be represented in a
695 // register on this target, make sure to expand or promote them.
696 if (Node->getNumValues() > 1) {
697 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
698 if (getTypeAction(Node->getValueType(i)) != Legal) {
699 HandleOp(Op.getValue(i));
700 assert(LegalizedNodes.count(Op) &&
701 "Handling didn't add legal operands!");
702 return LegalizedNodes[Op];
706 // Note that LegalizeOp may be reentered even from single-use nodes, which
707 // means that we always must cache transformed nodes.
708 DenseMap<SDOperand, SDOperand>::iterator I = LegalizedNodes.find(Op);
709 if (I != LegalizedNodes.end()) return I->second;
711 SDOperand Tmp1, Tmp2, Tmp3, Tmp4;
712 SDOperand Result = Op;
713 bool isCustom = false;
715 switch (Node->getOpcode()) {
716 case ISD::FrameIndex:
717 case ISD::EntryToken:
719 case ISD::BasicBlock:
720 case ISD::TargetFrameIndex:
721 case ISD::TargetJumpTable:
722 case ISD::TargetConstant:
723 case ISD::TargetConstantFP:
724 case ISD::TargetConstantPool:
725 case ISD::TargetGlobalAddress:
726 case ISD::TargetGlobalTLSAddress:
727 case ISD::TargetExternalSymbol:
732 // Primitives must all be legal.
733 assert(TLI.isOperationLegal(Node->getValueType(0), Node->getValueType(0)) &&
734 "This must be legal!");
737 if (Node->getOpcode() >= ISD::BUILTIN_OP_END) {
738 // If this is a target node, legalize it by legalizing the operands then
739 // passing it through.
740 SmallVector<SDOperand, 8> Ops;
741 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
742 Ops.push_back(LegalizeOp(Node->getOperand(i)));
744 Result = DAG.UpdateNodeOperands(Result.getValue(0), &Ops[0], Ops.size());
746 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
747 AddLegalizedOperand(Op.getValue(i), Result.getValue(i));
748 return Result.getValue(Op.ResNo);
750 // Otherwise this is an unhandled builtin node. splat.
752 cerr << "NODE: "; Node->dump(&DAG); cerr << "\n";
754 assert(0 && "Do not know how to legalize this operator!");
756 case ISD::GLOBAL_OFFSET_TABLE:
757 case ISD::GlobalAddress:
758 case ISD::GlobalTLSAddress:
759 case ISD::ExternalSymbol:
760 case ISD::ConstantPool:
761 case ISD::JumpTable: // Nothing to do.
762 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
763 default: assert(0 && "This action is not supported yet!");
764 case TargetLowering::Custom:
765 Tmp1 = TLI.LowerOperation(Op, DAG);
766 if (Tmp1.Val) Result = Tmp1;
767 // FALLTHROUGH if the target doesn't want to lower this op after all.
768 case TargetLowering::Legal:
773 case ISD::RETURNADDR:
774 // The only option for these nodes is to custom lower them. If the target
775 // does not custom lower them, then return zero.
776 Tmp1 = TLI.LowerOperation(Op, DAG);
780 Result = DAG.getConstant(0, TLI.getPointerTy());
782 case ISD::FRAME_TO_ARGS_OFFSET: {
783 MVT::ValueType VT = Node->getValueType(0);
784 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
785 default: assert(0 && "This action is not supported yet!");
786 case TargetLowering::Custom:
787 Result = TLI.LowerOperation(Op, DAG);
788 if (Result.Val) break;
790 case TargetLowering::Legal:
791 Result = DAG.getConstant(0, VT);
796 case ISD::EXCEPTIONADDR: {
797 Tmp1 = LegalizeOp(Node->getOperand(0));
798 MVT::ValueType VT = Node->getValueType(0);
799 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
800 default: assert(0 && "This action is not supported yet!");
801 case TargetLowering::Expand: {
802 unsigned Reg = TLI.getExceptionAddressRegister();
803 Result = DAG.getCopyFromReg(Tmp1, Reg, VT).getValue(Op.ResNo);
806 case TargetLowering::Custom:
807 Result = TLI.LowerOperation(Op, DAG);
808 if (Result.Val) break;
810 case TargetLowering::Legal: {
811 SDOperand Ops[] = { DAG.getConstant(0, VT), Tmp1 };
812 Result = DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(VT, MVT::Other),
813 Ops, 2).getValue(Op.ResNo);
819 case ISD::EHSELECTION: {
820 Tmp1 = LegalizeOp(Node->getOperand(0));
821 Tmp2 = LegalizeOp(Node->getOperand(1));
822 MVT::ValueType VT = Node->getValueType(0);
823 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
824 default: assert(0 && "This action is not supported yet!");
825 case TargetLowering::Expand: {
826 unsigned Reg = TLI.getExceptionSelectorRegister();
827 Result = DAG.getCopyFromReg(Tmp2, Reg, VT).getValue(Op.ResNo);
830 case TargetLowering::Custom:
831 Result = TLI.LowerOperation(Op, DAG);
832 if (Result.Val) break;
834 case TargetLowering::Legal: {
835 SDOperand Ops[] = { DAG.getConstant(0, VT), Tmp2 };
836 Result = DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(VT, MVT::Other),
837 Ops, 2).getValue(Op.ResNo);
843 case ISD::EH_RETURN: {
844 MVT::ValueType VT = Node->getValueType(0);
845 // The only "good" option for this node is to custom lower it.
846 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
847 default: assert(0 && "This action is not supported at all!");
848 case TargetLowering::Custom:
849 Result = TLI.LowerOperation(Op, DAG);
850 if (Result.Val) break;
852 case TargetLowering::Legal:
853 // Target does not know, how to lower this, lower to noop
854 Result = LegalizeOp(Node->getOperand(0));
859 case ISD::AssertSext:
860 case ISD::AssertZext:
861 Tmp1 = LegalizeOp(Node->getOperand(0));
862 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
864 case ISD::MERGE_VALUES:
865 // Legalize eliminates MERGE_VALUES nodes.
866 Result = Node->getOperand(Op.ResNo);
868 case ISD::CopyFromReg:
869 Tmp1 = LegalizeOp(Node->getOperand(0));
870 Result = Op.getValue(0);
871 if (Node->getNumValues() == 2) {
872 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
874 assert(Node->getNumValues() == 3 && "Invalid copyfromreg!");
875 if (Node->getNumOperands() == 3) {
876 Tmp2 = LegalizeOp(Node->getOperand(2));
877 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1),Tmp2);
879 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
881 AddLegalizedOperand(Op.getValue(2), Result.getValue(2));
883 // Since CopyFromReg produces two values, make sure to remember that we
884 // legalized both of them.
885 AddLegalizedOperand(Op.getValue(0), Result);
886 AddLegalizedOperand(Op.getValue(1), Result.getValue(1));
887 return Result.getValue(Op.ResNo);
889 MVT::ValueType VT = Op.getValueType();
890 switch (TLI.getOperationAction(ISD::UNDEF, VT)) {
891 default: assert(0 && "This action is not supported yet!");
892 case TargetLowering::Expand:
893 if (MVT::isInteger(VT))
894 Result = DAG.getConstant(0, VT);
895 else if (MVT::isFloatingPoint(VT))
896 Result = DAG.getConstantFP(0, VT);
898 assert(0 && "Unknown value type!");
900 case TargetLowering::Legal:
906 case ISD::INTRINSIC_W_CHAIN:
907 case ISD::INTRINSIC_WO_CHAIN:
908 case ISD::INTRINSIC_VOID: {
909 SmallVector<SDOperand, 8> Ops;
910 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
911 Ops.push_back(LegalizeOp(Node->getOperand(i)));
912 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
914 // Allow the target to custom lower its intrinsics if it wants to.
915 if (TLI.getOperationAction(Node->getOpcode(), MVT::Other) ==
916 TargetLowering::Custom) {
917 Tmp3 = TLI.LowerOperation(Result, DAG);
918 if (Tmp3.Val) Result = Tmp3;
921 if (Result.Val->getNumValues() == 1) break;
923 // Must have return value and chain result.
924 assert(Result.Val->getNumValues() == 2 &&
925 "Cannot return more than two values!");
927 // Since loads produce two values, make sure to remember that we
928 // legalized both of them.
929 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
930 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
931 return Result.getValue(Op.ResNo);
935 assert(Node->getNumOperands() == 5 && "Invalid LOCATION node!");
936 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the input chain.
938 switch (TLI.getOperationAction(ISD::LOCATION, MVT::Other)) {
939 case TargetLowering::Promote:
940 default: assert(0 && "This action is not supported yet!");
941 case TargetLowering::Expand: {
942 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
943 bool useDEBUG_LOC = TLI.isOperationLegal(ISD::DEBUG_LOC, MVT::Other);
944 bool useLABEL = TLI.isOperationLegal(ISD::LABEL, MVT::Other);
946 if (MMI && (useDEBUG_LOC || useLABEL)) {
947 const std::string &FName =
948 cast<StringSDNode>(Node->getOperand(3))->getValue();
949 const std::string &DirName =
950 cast<StringSDNode>(Node->getOperand(4))->getValue();
951 unsigned SrcFile = MMI->RecordSource(DirName, FName);
953 SmallVector<SDOperand, 8> Ops;
954 Ops.push_back(Tmp1); // chain
955 SDOperand LineOp = Node->getOperand(1);
956 SDOperand ColOp = Node->getOperand(2);
959 Ops.push_back(LineOp); // line #
960 Ops.push_back(ColOp); // col #
961 Ops.push_back(DAG.getConstant(SrcFile, MVT::i32)); // source file id
962 Result = DAG.getNode(ISD::DEBUG_LOC, MVT::Other, &Ops[0], Ops.size());
964 unsigned Line = cast<ConstantSDNode>(LineOp)->getValue();
965 unsigned Col = cast<ConstantSDNode>(ColOp)->getValue();
966 unsigned ID = MMI->RecordLabel(Line, Col, SrcFile);
967 Ops.push_back(DAG.getConstant(ID, MVT::i32));
968 Result = DAG.getNode(ISD::LABEL, MVT::Other,&Ops[0],Ops.size());
971 Result = Tmp1; // chain
975 case TargetLowering::Legal:
976 if (Tmp1 != Node->getOperand(0) ||
977 getTypeAction(Node->getOperand(1).getValueType()) == Promote) {
978 SmallVector<SDOperand, 8> Ops;
980 if (getTypeAction(Node->getOperand(1).getValueType()) == Legal) {
981 Ops.push_back(Node->getOperand(1)); // line # must be legal.
982 Ops.push_back(Node->getOperand(2)); // col # must be legal.
984 // Otherwise promote them.
985 Ops.push_back(PromoteOp(Node->getOperand(1)));
986 Ops.push_back(PromoteOp(Node->getOperand(2)));
988 Ops.push_back(Node->getOperand(3)); // filename must be legal.
989 Ops.push_back(Node->getOperand(4)); // working dir # must be legal.
990 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
997 assert(Node->getNumOperands() == 4 && "Invalid DEBUG_LOC node!");
998 switch (TLI.getOperationAction(ISD::DEBUG_LOC, MVT::Other)) {
999 default: assert(0 && "This action is not supported yet!");
1000 case TargetLowering::Legal:
1001 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1002 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the line #.
1003 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the col #.
1004 Tmp4 = LegalizeOp(Node->getOperand(3)); // Legalize the source file id.
1005 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4);
1011 assert(Node->getNumOperands() == 2 && "Invalid LABEL node!");
1012 switch (TLI.getOperationAction(ISD::LABEL, MVT::Other)) {
1013 default: assert(0 && "This action is not supported yet!");
1014 case TargetLowering::Legal:
1015 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1016 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the label id.
1017 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1019 case TargetLowering::Expand:
1020 Result = LegalizeOp(Node->getOperand(0));
1025 case ISD::Constant: {
1026 ConstantSDNode *CN = cast<ConstantSDNode>(Node);
1028 TLI.getOperationAction(ISD::Constant, CN->getValueType(0));
1030 // We know we don't need to expand constants here, constants only have one
1031 // value and we check that it is fine above.
1033 if (opAction == TargetLowering::Custom) {
1034 Tmp1 = TLI.LowerOperation(Result, DAG);
1040 case ISD::ConstantFP: {
1041 // Spill FP immediates to the constant pool if the target cannot directly
1042 // codegen them. Targets often have some immediate values that can be
1043 // efficiently generated into an FP register without a load. We explicitly
1044 // leave these constants as ConstantFP nodes for the target to deal with.
1045 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node);
1047 // Check to see if this FP immediate is already legal.
1048 bool isLegal = false;
1049 for (TargetLowering::legal_fpimm_iterator I = TLI.legal_fpimm_begin(),
1050 E = TLI.legal_fpimm_end(); I != E; ++I)
1051 if (CFP->isExactlyValue(*I)) {
1056 // If this is a legal constant, turn it into a TargetConstantFP node.
1058 Result = DAG.getTargetConstantFP(CFP->getValueAPF(),
1059 CFP->getValueType(0));
1063 switch (TLI.getOperationAction(ISD::ConstantFP, CFP->getValueType(0))) {
1064 default: assert(0 && "This action is not supported yet!");
1065 case TargetLowering::Custom:
1066 Tmp3 = TLI.LowerOperation(Result, DAG);
1072 case TargetLowering::Expand:
1073 Result = ExpandConstantFP(CFP, true, DAG, TLI);
1077 case ISD::TokenFactor:
1078 if (Node->getNumOperands() == 2) {
1079 Tmp1 = LegalizeOp(Node->getOperand(0));
1080 Tmp2 = LegalizeOp(Node->getOperand(1));
1081 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1082 } else if (Node->getNumOperands() == 3) {
1083 Tmp1 = LegalizeOp(Node->getOperand(0));
1084 Tmp2 = LegalizeOp(Node->getOperand(1));
1085 Tmp3 = LegalizeOp(Node->getOperand(2));
1086 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1088 SmallVector<SDOperand, 8> Ops;
1089 // Legalize the operands.
1090 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
1091 Ops.push_back(LegalizeOp(Node->getOperand(i)));
1092 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1096 case ISD::FORMAL_ARGUMENTS:
1098 // The only option for this is to custom lower it.
1099 Tmp3 = TLI.LowerOperation(Result.getValue(0), DAG);
1100 assert(Tmp3.Val && "Target didn't custom lower this node!");
1101 assert(Tmp3.Val->getNumValues() == Result.Val->getNumValues() &&
1102 "Lowering call/formal_arguments produced unexpected # results!");
1104 // Since CALL/FORMAL_ARGUMENTS nodes produce multiple values, make sure to
1105 // remember that we legalized all of them, so it doesn't get relegalized.
1106 for (unsigned i = 0, e = Tmp3.Val->getNumValues(); i != e; ++i) {
1107 Tmp1 = LegalizeOp(Tmp3.getValue(i));
1110 AddLegalizedOperand(SDOperand(Node, i), Tmp1);
1113 case ISD::EXTRACT_SUBREG: {
1114 Tmp1 = LegalizeOp(Node->getOperand(0));
1115 ConstantSDNode *idx = dyn_cast<ConstantSDNode>(Node->getOperand(1));
1116 assert(idx && "Operand must be a constant");
1117 Tmp2 = DAG.getTargetConstant(idx->getValue(), idx->getValueType(0));
1118 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1121 case ISD::INSERT_SUBREG: {
1122 Tmp1 = LegalizeOp(Node->getOperand(0));
1123 Tmp2 = LegalizeOp(Node->getOperand(1));
1124 ConstantSDNode *idx = dyn_cast<ConstantSDNode>(Node->getOperand(2));
1125 assert(idx && "Operand must be a constant");
1126 Tmp3 = DAG.getTargetConstant(idx->getValue(), idx->getValueType(0));
1127 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1130 case ISD::BUILD_VECTOR:
1131 switch (TLI.getOperationAction(ISD::BUILD_VECTOR, Node->getValueType(0))) {
1132 default: assert(0 && "This action is not supported yet!");
1133 case TargetLowering::Custom:
1134 Tmp3 = TLI.LowerOperation(Result, DAG);
1140 case TargetLowering::Expand:
1141 Result = ExpandBUILD_VECTOR(Result.Val);
1145 case ISD::INSERT_VECTOR_ELT:
1146 Tmp1 = LegalizeOp(Node->getOperand(0)); // InVec
1147 Tmp2 = LegalizeOp(Node->getOperand(1)); // InVal
1148 Tmp3 = LegalizeOp(Node->getOperand(2)); // InEltNo
1149 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1151 switch (TLI.getOperationAction(ISD::INSERT_VECTOR_ELT,
1152 Node->getValueType(0))) {
1153 default: assert(0 && "This action is not supported yet!");
1154 case TargetLowering::Legal:
1156 case TargetLowering::Custom:
1157 Tmp3 = TLI.LowerOperation(Result, DAG);
1163 case TargetLowering::Expand: {
1164 // If the insert index is a constant, codegen this as a scalar_to_vector,
1165 // then a shuffle that inserts it into the right position in the vector.
1166 if (ConstantSDNode *InsertPos = dyn_cast<ConstantSDNode>(Tmp3)) {
1167 SDOperand ScVec = DAG.getNode(ISD::SCALAR_TO_VECTOR,
1168 Tmp1.getValueType(), Tmp2);
1170 unsigned NumElts = MVT::getVectorNumElements(Tmp1.getValueType());
1171 MVT::ValueType ShufMaskVT = MVT::getIntVectorWithNumElements(NumElts);
1172 MVT::ValueType ShufMaskEltVT = MVT::getVectorElementType(ShufMaskVT);
1174 // We generate a shuffle of InVec and ScVec, so the shuffle mask should
1175 // be 0,1,2,3,4,5... with the appropriate element replaced with elt 0 of
1177 SmallVector<SDOperand, 8> ShufOps;
1178 for (unsigned i = 0; i != NumElts; ++i) {
1179 if (i != InsertPos->getValue())
1180 ShufOps.push_back(DAG.getConstant(i, ShufMaskEltVT));
1182 ShufOps.push_back(DAG.getConstant(NumElts, ShufMaskEltVT));
1184 SDOperand ShufMask = DAG.getNode(ISD::BUILD_VECTOR, ShufMaskVT,
1185 &ShufOps[0], ShufOps.size());
1187 Result = DAG.getNode(ISD::VECTOR_SHUFFLE, Tmp1.getValueType(),
1188 Tmp1, ScVec, ShufMask);
1189 Result = LegalizeOp(Result);
1193 // If the target doesn't support this, we have to spill the input vector
1194 // to a temporary stack slot, update the element, then reload it. This is
1195 // badness. We could also load the value into a vector register (either
1196 // with a "move to register" or "extload into register" instruction, then
1197 // permute it into place, if the idx is a constant and if the idx is
1198 // supported by the target.
1199 MVT::ValueType VT = Tmp1.getValueType();
1200 MVT::ValueType EltVT = Tmp2.getValueType();
1201 MVT::ValueType IdxVT = Tmp3.getValueType();
1202 MVT::ValueType PtrVT = TLI.getPointerTy();
1203 SDOperand StackPtr = CreateStackTemporary(VT);
1204 // Store the vector.
1205 SDOperand Ch = DAG.getStore(DAG.getEntryNode(), Tmp1, StackPtr, NULL, 0);
1207 // Truncate or zero extend offset to target pointer type.
1208 unsigned CastOpc = (IdxVT > PtrVT) ? ISD::TRUNCATE : ISD::ZERO_EXTEND;
1209 Tmp3 = DAG.getNode(CastOpc, PtrVT, Tmp3);
1210 // Add the offset to the index.
1211 unsigned EltSize = MVT::getSizeInBits(EltVT)/8;
1212 Tmp3 = DAG.getNode(ISD::MUL, IdxVT, Tmp3,DAG.getConstant(EltSize, IdxVT));
1213 SDOperand StackPtr2 = DAG.getNode(ISD::ADD, IdxVT, Tmp3, StackPtr);
1214 // Store the scalar value.
1215 Ch = DAG.getStore(Ch, Tmp2, StackPtr2, NULL, 0);
1216 // Load the updated vector.
1217 Result = DAG.getLoad(VT, Ch, StackPtr, NULL, 0);
1222 case ISD::SCALAR_TO_VECTOR:
1223 if (!TLI.isTypeLegal(Node->getOperand(0).getValueType())) {
1224 Result = LegalizeOp(ExpandSCALAR_TO_VECTOR(Node));
1228 Tmp1 = LegalizeOp(Node->getOperand(0)); // InVal
1229 Result = DAG.UpdateNodeOperands(Result, Tmp1);
1230 switch (TLI.getOperationAction(ISD::SCALAR_TO_VECTOR,
1231 Node->getValueType(0))) {
1232 default: assert(0 && "This action is not supported yet!");
1233 case TargetLowering::Legal:
1235 case TargetLowering::Custom:
1236 Tmp3 = TLI.LowerOperation(Result, DAG);
1242 case TargetLowering::Expand:
1243 Result = LegalizeOp(ExpandSCALAR_TO_VECTOR(Node));
1247 case ISD::VECTOR_SHUFFLE:
1248 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the input vectors,
1249 Tmp2 = LegalizeOp(Node->getOperand(1)); // but not the shuffle mask.
1250 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
1252 // Allow targets to custom lower the SHUFFLEs they support.
1253 switch (TLI.getOperationAction(ISD::VECTOR_SHUFFLE,Result.getValueType())) {
1254 default: assert(0 && "Unknown operation action!");
1255 case TargetLowering::Legal:
1256 assert(isShuffleLegal(Result.getValueType(), Node->getOperand(2)) &&
1257 "vector shuffle should not be created if not legal!");
1259 case TargetLowering::Custom:
1260 Tmp3 = TLI.LowerOperation(Result, DAG);
1266 case TargetLowering::Expand: {
1267 MVT::ValueType VT = Node->getValueType(0);
1268 MVT::ValueType EltVT = MVT::getVectorElementType(VT);
1269 MVT::ValueType PtrVT = TLI.getPointerTy();
1270 SDOperand Mask = Node->getOperand(2);
1271 unsigned NumElems = Mask.getNumOperands();
1272 SmallVector<SDOperand,8> Ops;
1273 for (unsigned i = 0; i != NumElems; ++i) {
1274 SDOperand Arg = Mask.getOperand(i);
1275 if (Arg.getOpcode() == ISD::UNDEF) {
1276 Ops.push_back(DAG.getNode(ISD::UNDEF, EltVT));
1278 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
1279 unsigned Idx = cast<ConstantSDNode>(Arg)->getValue();
1281 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, Tmp1,
1282 DAG.getConstant(Idx, PtrVT)));
1284 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, Tmp2,
1285 DAG.getConstant(Idx - NumElems, PtrVT)));
1288 Result = DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size());
1291 case TargetLowering::Promote: {
1292 // Change base type to a different vector type.
1293 MVT::ValueType OVT = Node->getValueType(0);
1294 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
1296 // Cast the two input vectors.
1297 Tmp1 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp1);
1298 Tmp2 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp2);
1300 // Convert the shuffle mask to the right # elements.
1301 Tmp3 = SDOperand(isShuffleLegal(OVT, Node->getOperand(2)), 0);
1302 assert(Tmp3.Val && "Shuffle not legal?");
1303 Result = DAG.getNode(ISD::VECTOR_SHUFFLE, NVT, Tmp1, Tmp2, Tmp3);
1304 Result = DAG.getNode(ISD::BIT_CONVERT, OVT, Result);
1310 case ISD::EXTRACT_VECTOR_ELT:
1311 Tmp1 = Node->getOperand(0);
1312 Tmp2 = LegalizeOp(Node->getOperand(1));
1313 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1314 Result = ExpandEXTRACT_VECTOR_ELT(Result);
1317 case ISD::EXTRACT_SUBVECTOR:
1318 Tmp1 = Node->getOperand(0);
1319 Tmp2 = LegalizeOp(Node->getOperand(1));
1320 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1321 Result = ExpandEXTRACT_SUBVECTOR(Result);
1324 case ISD::CALLSEQ_START: {
1325 SDNode *CallEnd = FindCallEndFromCallStart(Node);
1327 // Recursively Legalize all of the inputs of the call end that do not lead
1328 // to this call start. This ensures that any libcalls that need be inserted
1329 // are inserted *before* the CALLSEQ_START.
1330 {SmallPtrSet<SDNode*, 32> NodesLeadingTo;
1331 for (unsigned i = 0, e = CallEnd->getNumOperands(); i != e; ++i)
1332 LegalizeAllNodesNotLeadingTo(CallEnd->getOperand(i).Val, Node,
1336 // Now that we legalized all of the inputs (which may have inserted
1337 // libcalls) create the new CALLSEQ_START node.
1338 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1340 // Merge in the last call, to ensure that this call start after the last
1342 if (LastCALLSEQ_END.getOpcode() != ISD::EntryToken) {
1343 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1344 Tmp1 = LegalizeOp(Tmp1);
1347 // Do not try to legalize the target-specific arguments (#1+).
1348 if (Tmp1 != Node->getOperand(0)) {
1349 SmallVector<SDOperand, 8> Ops(Node->op_begin(), Node->op_end());
1351 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1354 // Remember that the CALLSEQ_START is legalized.
1355 AddLegalizedOperand(Op.getValue(0), Result);
1356 if (Node->getNumValues() == 2) // If this has a flag result, remember it.
1357 AddLegalizedOperand(Op.getValue(1), Result.getValue(1));
1359 // Now that the callseq_start and all of the non-call nodes above this call
1360 // sequence have been legalized, legalize the call itself. During this
1361 // process, no libcalls can/will be inserted, guaranteeing that no calls
1363 assert(!IsLegalizingCall && "Inconsistent sequentialization of calls!");
1364 SDOperand InCallSEQ = LastCALLSEQ_END;
1365 // Note that we are selecting this call!
1366 LastCALLSEQ_END = SDOperand(CallEnd, 0);
1367 IsLegalizingCall = true;
1369 // Legalize the call, starting from the CALLSEQ_END.
1370 LegalizeOp(LastCALLSEQ_END);
1371 assert(!IsLegalizingCall && "CALLSEQ_END should have cleared this!");
1374 case ISD::CALLSEQ_END:
1375 // If the CALLSEQ_START node hasn't been legalized first, legalize it. This
1376 // will cause this node to be legalized as well as handling libcalls right.
1377 if (LastCALLSEQ_END.Val != Node) {
1378 LegalizeOp(SDOperand(FindCallStartFromCallEnd(Node), 0));
1379 DenseMap<SDOperand, SDOperand>::iterator I = LegalizedNodes.find(Op);
1380 assert(I != LegalizedNodes.end() &&
1381 "Legalizing the call start should have legalized this node!");
1385 // Otherwise, the call start has been legalized and everything is going
1386 // according to plan. Just legalize ourselves normally here.
1387 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1388 // Do not try to legalize the target-specific arguments (#1+), except for
1389 // an optional flag input.
1390 if (Node->getOperand(Node->getNumOperands()-1).getValueType() != MVT::Flag){
1391 if (Tmp1 != Node->getOperand(0)) {
1392 SmallVector<SDOperand, 8> Ops(Node->op_begin(), Node->op_end());
1394 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1397 Tmp2 = LegalizeOp(Node->getOperand(Node->getNumOperands()-1));
1398 if (Tmp1 != Node->getOperand(0) ||
1399 Tmp2 != Node->getOperand(Node->getNumOperands()-1)) {
1400 SmallVector<SDOperand, 8> Ops(Node->op_begin(), Node->op_end());
1403 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1406 assert(IsLegalizingCall && "Call sequence imbalance between start/end?");
1407 // This finishes up call legalization.
1408 IsLegalizingCall = false;
1410 // If the CALLSEQ_END node has a flag, remember that we legalized it.
1411 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
1412 if (Node->getNumValues() == 2)
1413 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
1414 return Result.getValue(Op.ResNo);
1415 case ISD::DYNAMIC_STACKALLOC: {
1416 MVT::ValueType VT = Node->getValueType(0);
1417 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1418 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the size.
1419 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the alignment.
1420 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1422 Tmp1 = Result.getValue(0);
1423 Tmp2 = Result.getValue(1);
1424 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
1425 default: assert(0 && "This action is not supported yet!");
1426 case TargetLowering::Expand: {
1427 unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore();
1428 assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and"
1429 " not tell us which reg is the stack pointer!");
1430 SDOperand Chain = Tmp1.getOperand(0);
1431 SDOperand Size = Tmp2.getOperand(1);
1432 SDOperand SP = DAG.getCopyFromReg(Chain, SPReg, VT);
1433 Chain = SP.getValue(1);
1434 unsigned Align = cast<ConstantSDNode>(Tmp3)->getValue();
1435 unsigned StackAlign =
1436 TLI.getTargetMachine().getFrameInfo()->getStackAlignment();
1437 if (Align > StackAlign)
1438 SP = DAG.getNode(ISD::AND, VT, SP,
1439 DAG.getConstant(-(uint64_t)Align, VT));
1440 Tmp1 = DAG.getNode(ISD::SUB, VT, SP, Size); // Value
1441 Tmp2 = DAG.getCopyToReg(Chain, SPReg, Tmp1); // Output chain
1442 Tmp1 = LegalizeOp(Tmp1);
1443 Tmp2 = LegalizeOp(Tmp2);
1446 case TargetLowering::Custom:
1447 Tmp3 = TLI.LowerOperation(Tmp1, DAG);
1449 Tmp1 = LegalizeOp(Tmp3);
1450 Tmp2 = LegalizeOp(Tmp3.getValue(1));
1453 case TargetLowering::Legal:
1456 // Since this op produce two values, make sure to remember that we
1457 // legalized both of them.
1458 AddLegalizedOperand(SDOperand(Node, 0), Tmp1);
1459 AddLegalizedOperand(SDOperand(Node, 1), Tmp2);
1460 return Op.ResNo ? Tmp2 : Tmp1;
1462 case ISD::INLINEASM: {
1463 SmallVector<SDOperand, 8> Ops(Node->op_begin(), Node->op_end());
1464 bool Changed = false;
1465 // Legalize all of the operands of the inline asm, in case they are nodes
1466 // that need to be expanded or something. Note we skip the asm string and
1467 // all of the TargetConstant flags.
1468 SDOperand Op = LegalizeOp(Ops[0]);
1469 Changed = Op != Ops[0];
1472 bool HasInFlag = Ops.back().getValueType() == MVT::Flag;
1473 for (unsigned i = 2, e = Ops.size()-HasInFlag; i < e; ) {
1474 unsigned NumVals = cast<ConstantSDNode>(Ops[i])->getValue() >> 3;
1475 for (++i; NumVals; ++i, --NumVals) {
1476 SDOperand Op = LegalizeOp(Ops[i]);
1485 Op = LegalizeOp(Ops.back());
1486 Changed |= Op != Ops.back();
1491 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1493 // INLINE asm returns a chain and flag, make sure to add both to the map.
1494 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
1495 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
1496 return Result.getValue(Op.ResNo);
1499 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1500 // Ensure that libcalls are emitted before a branch.
1501 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1502 Tmp1 = LegalizeOp(Tmp1);
1503 LastCALLSEQ_END = DAG.getEntryNode();
1505 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
1508 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1509 // Ensure that libcalls are emitted before a branch.
1510 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1511 Tmp1 = LegalizeOp(Tmp1);
1512 LastCALLSEQ_END = DAG.getEntryNode();
1514 switch (getTypeAction(Node->getOperand(1).getValueType())) {
1515 default: assert(0 && "Indirect target must be legal type (pointer)!");
1517 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the condition.
1520 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1523 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1524 // Ensure that libcalls are emitted before a branch.
1525 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1526 Tmp1 = LegalizeOp(Tmp1);
1527 LastCALLSEQ_END = DAG.getEntryNode();
1529 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the jumptable node.
1530 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
1532 switch (TLI.getOperationAction(ISD::BR_JT, MVT::Other)) {
1533 default: assert(0 && "This action is not supported yet!");
1534 case TargetLowering::Legal: break;
1535 case TargetLowering::Custom:
1536 Tmp1 = TLI.LowerOperation(Result, DAG);
1537 if (Tmp1.Val) Result = Tmp1;
1539 case TargetLowering::Expand: {
1540 SDOperand Chain = Result.getOperand(0);
1541 SDOperand Table = Result.getOperand(1);
1542 SDOperand Index = Result.getOperand(2);
1544 MVT::ValueType PTy = TLI.getPointerTy();
1545 MachineFunction &MF = DAG.getMachineFunction();
1546 unsigned EntrySize = MF.getJumpTableInfo()->getEntrySize();
1547 Index= DAG.getNode(ISD::MUL, PTy, Index, DAG.getConstant(EntrySize, PTy));
1548 SDOperand Addr = DAG.getNode(ISD::ADD, PTy, Index, Table);
1551 switch (EntrySize) {
1552 default: assert(0 && "Size of jump table not supported yet."); break;
1553 case 4: LD = DAG.getLoad(MVT::i32, Chain, Addr, NULL, 0); break;
1554 case 8: LD = DAG.getLoad(MVT::i64, Chain, Addr, NULL, 0); break;
1557 if (TLI.getTargetMachine().getRelocationModel() == Reloc::PIC_) {
1558 // For PIC, the sequence is:
1559 // BRIND(load(Jumptable + index) + RelocBase)
1560 // RelocBase is the JumpTable on PPC and X86, GOT on Alpha
1562 if (TLI.usesGlobalOffsetTable())
1563 Reloc = DAG.getNode(ISD::GLOBAL_OFFSET_TABLE, PTy);
1566 Addr = (PTy != MVT::i32) ? DAG.getNode(ISD::SIGN_EXTEND, PTy, LD) : LD;
1567 Addr = DAG.getNode(ISD::ADD, PTy, Addr, Reloc);
1568 Result = DAG.getNode(ISD::BRIND, MVT::Other, LD.getValue(1), Addr);
1570 Result = DAG.getNode(ISD::BRIND, MVT::Other, LD.getValue(1), LD);
1576 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1577 // Ensure that libcalls are emitted before a return.
1578 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1579 Tmp1 = LegalizeOp(Tmp1);
1580 LastCALLSEQ_END = DAG.getEntryNode();
1582 switch (getTypeAction(Node->getOperand(1).getValueType())) {
1583 case Expand: assert(0 && "It's impossible to expand bools");
1585 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the condition.
1588 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the condition.
1590 // The top bits of the promoted condition are not necessarily zero, ensure
1591 // that the value is properly zero extended.
1592 if (!DAG.MaskedValueIsZero(Tmp2,
1593 MVT::getIntVTBitMask(Tmp2.getValueType())^1))
1594 Tmp2 = DAG.getZeroExtendInReg(Tmp2, MVT::i1);
1598 // Basic block destination (Op#2) is always legal.
1599 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
1601 switch (TLI.getOperationAction(ISD::BRCOND, MVT::Other)) {
1602 default: assert(0 && "This action is not supported yet!");
1603 case TargetLowering::Legal: break;
1604 case TargetLowering::Custom:
1605 Tmp1 = TLI.LowerOperation(Result, DAG);
1606 if (Tmp1.Val) Result = Tmp1;
1608 case TargetLowering::Expand:
1609 // Expand brcond's setcc into its constituent parts and create a BR_CC
1611 if (Tmp2.getOpcode() == ISD::SETCC) {
1612 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1, Tmp2.getOperand(2),
1613 Tmp2.getOperand(0), Tmp2.getOperand(1),
1614 Node->getOperand(2));
1616 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1,
1617 DAG.getCondCode(ISD::SETNE), Tmp2,
1618 DAG.getConstant(0, Tmp2.getValueType()),
1619 Node->getOperand(2));
1625 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1626 // Ensure that libcalls are emitted before a branch.
1627 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1628 Tmp1 = LegalizeOp(Tmp1);
1629 Tmp2 = Node->getOperand(2); // LHS
1630 Tmp3 = Node->getOperand(3); // RHS
1631 Tmp4 = Node->getOperand(1); // CC
1633 LegalizeSetCCOperands(Tmp2, Tmp3, Tmp4);
1634 LastCALLSEQ_END = DAG.getEntryNode();
1636 // If we didn't get both a LHS and RHS back from LegalizeSetCCOperands,
1637 // the LHS is a legal SETCC itself. In this case, we need to compare
1638 // the result against zero to select between true and false values.
1639 if (Tmp3.Val == 0) {
1640 Tmp3 = DAG.getConstant(0, Tmp2.getValueType());
1641 Tmp4 = DAG.getCondCode(ISD::SETNE);
1644 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp4, Tmp2, Tmp3,
1645 Node->getOperand(4));
1647 switch (TLI.getOperationAction(ISD::BR_CC, Tmp3.getValueType())) {
1648 default: assert(0 && "Unexpected action for BR_CC!");
1649 case TargetLowering::Legal: break;
1650 case TargetLowering::Custom:
1651 Tmp4 = TLI.LowerOperation(Result, DAG);
1652 if (Tmp4.Val) Result = Tmp4;
1657 LoadSDNode *LD = cast<LoadSDNode>(Node);
1658 Tmp1 = LegalizeOp(LD->getChain()); // Legalize the chain.
1659 Tmp2 = LegalizeOp(LD->getBasePtr()); // Legalize the base pointer.
1661 ISD::LoadExtType ExtType = LD->getExtensionType();
1662 if (ExtType == ISD::NON_EXTLOAD) {
1663 MVT::ValueType VT = Node->getValueType(0);
1664 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, LD->getOffset());
1665 Tmp3 = Result.getValue(0);
1666 Tmp4 = Result.getValue(1);
1668 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
1669 default: assert(0 && "This action is not supported yet!");
1670 case TargetLowering::Legal:
1671 // If this is an unaligned load and the target doesn't support it,
1673 if (!TLI.allowsUnalignedMemoryAccesses()) {
1674 unsigned ABIAlignment = TLI.getTargetData()->
1675 getABITypeAlignment(MVT::getTypeForValueType(LD->getLoadedVT()));
1676 if (LD->getAlignment() < ABIAlignment){
1677 Result = ExpandUnalignedLoad(cast<LoadSDNode>(Result.Val), DAG,
1679 Tmp3 = Result.getOperand(0);
1680 Tmp4 = Result.getOperand(1);
1681 Tmp3 = LegalizeOp(Tmp3);
1682 Tmp4 = LegalizeOp(Tmp4);
1686 case TargetLowering::Custom:
1687 Tmp1 = TLI.LowerOperation(Tmp3, DAG);
1689 Tmp3 = LegalizeOp(Tmp1);
1690 Tmp4 = LegalizeOp(Tmp1.getValue(1));
1693 case TargetLowering::Promote: {
1694 // Only promote a load of vector type to another.
1695 assert(MVT::isVector(VT) && "Cannot promote this load!");
1696 // Change base type to a different vector type.
1697 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), VT);
1699 Tmp1 = DAG.getLoad(NVT, Tmp1, Tmp2, LD->getSrcValue(),
1700 LD->getSrcValueOffset(),
1701 LD->isVolatile(), LD->getAlignment());
1702 Tmp3 = LegalizeOp(DAG.getNode(ISD::BIT_CONVERT, VT, Tmp1));
1703 Tmp4 = LegalizeOp(Tmp1.getValue(1));
1707 // Since loads produce two values, make sure to remember that we
1708 // legalized both of them.
1709 AddLegalizedOperand(SDOperand(Node, 0), Tmp3);
1710 AddLegalizedOperand(SDOperand(Node, 1), Tmp4);
1711 return Op.ResNo ? Tmp4 : Tmp3;
1713 MVT::ValueType SrcVT = LD->getLoadedVT();
1714 switch (TLI.getLoadXAction(ExtType, SrcVT)) {
1715 default: assert(0 && "This action is not supported yet!");
1716 case TargetLowering::Promote:
1717 assert(SrcVT == MVT::i1 &&
1718 "Can only promote extending LOAD from i1 -> i8!");
1719 Result = DAG.getExtLoad(ExtType, Node->getValueType(0), Tmp1, Tmp2,
1720 LD->getSrcValue(), LD->getSrcValueOffset(),
1721 MVT::i8, LD->isVolatile(), LD->getAlignment());
1722 Tmp1 = Result.getValue(0);
1723 Tmp2 = Result.getValue(1);
1725 case TargetLowering::Custom:
1728 case TargetLowering::Legal:
1729 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, LD->getOffset());
1730 Tmp1 = Result.getValue(0);
1731 Tmp2 = Result.getValue(1);
1734 Tmp3 = TLI.LowerOperation(Result, DAG);
1736 Tmp1 = LegalizeOp(Tmp3);
1737 Tmp2 = LegalizeOp(Tmp3.getValue(1));
1740 // If this is an unaligned load and the target doesn't support it,
1742 if (!TLI.allowsUnalignedMemoryAccesses()) {
1743 unsigned ABIAlignment = TLI.getTargetData()->
1744 getABITypeAlignment(MVT::getTypeForValueType(LD->getLoadedVT()));
1745 if (LD->getAlignment() < ABIAlignment){
1746 Result = ExpandUnalignedLoad(cast<LoadSDNode>(Result.Val), DAG,
1748 Tmp1 = Result.getOperand(0);
1749 Tmp2 = Result.getOperand(1);
1750 Tmp1 = LegalizeOp(Tmp1);
1751 Tmp2 = LegalizeOp(Tmp2);
1756 case TargetLowering::Expand:
1757 // f64 = EXTLOAD f32 should expand to LOAD, FP_EXTEND
1758 if (SrcVT == MVT::f32 && Node->getValueType(0) == MVT::f64) {
1759 SDOperand Load = DAG.getLoad(SrcVT, Tmp1, Tmp2, LD->getSrcValue(),
1760 LD->getSrcValueOffset(),
1761 LD->isVolatile(), LD->getAlignment());
1762 Result = DAG.getNode(ISD::FP_EXTEND, Node->getValueType(0), Load);
1763 Tmp1 = LegalizeOp(Result); // Relegalize new nodes.
1764 Tmp2 = LegalizeOp(Load.getValue(1));
1767 assert(ExtType != ISD::EXTLOAD &&"EXTLOAD should always be supported!");
1768 // Turn the unsupported load into an EXTLOAD followed by an explicit
1769 // zero/sign extend inreg.
1770 Result = DAG.getExtLoad(ISD::EXTLOAD, Node->getValueType(0),
1771 Tmp1, Tmp2, LD->getSrcValue(),
1772 LD->getSrcValueOffset(), SrcVT,
1773 LD->isVolatile(), LD->getAlignment());
1775 if (ExtType == ISD::SEXTLOAD)
1776 ValRes = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(),
1777 Result, DAG.getValueType(SrcVT));
1779 ValRes = DAG.getZeroExtendInReg(Result, SrcVT);
1780 Tmp1 = LegalizeOp(ValRes); // Relegalize new nodes.
1781 Tmp2 = LegalizeOp(Result.getValue(1)); // Relegalize new nodes.
1784 // Since loads produce two values, make sure to remember that we legalized
1786 AddLegalizedOperand(SDOperand(Node, 0), Tmp1);
1787 AddLegalizedOperand(SDOperand(Node, 1), Tmp2);
1788 return Op.ResNo ? Tmp2 : Tmp1;
1791 case ISD::EXTRACT_ELEMENT: {
1792 MVT::ValueType OpTy = Node->getOperand(0).getValueType();
1793 switch (getTypeAction(OpTy)) {
1794 default: assert(0 && "EXTRACT_ELEMENT action for type unimplemented!");
1796 if (cast<ConstantSDNode>(Node->getOperand(1))->getValue()) {
1798 Result = DAG.getNode(ISD::SRL, OpTy, Node->getOperand(0),
1799 DAG.getConstant(MVT::getSizeInBits(OpTy)/2,
1800 TLI.getShiftAmountTy()));
1801 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), Result);
1804 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0),
1805 Node->getOperand(0));
1809 // Get both the low and high parts.
1810 ExpandOp(Node->getOperand(0), Tmp1, Tmp2);
1811 if (cast<ConstantSDNode>(Node->getOperand(1))->getValue())
1812 Result = Tmp2; // 1 -> Hi
1814 Result = Tmp1; // 0 -> Lo
1820 case ISD::CopyToReg:
1821 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1823 assert(isTypeLegal(Node->getOperand(2).getValueType()) &&
1824 "Register type must be legal!");
1825 // Legalize the incoming value (must be a legal type).
1826 Tmp2 = LegalizeOp(Node->getOperand(2));
1827 if (Node->getNumValues() == 1) {
1828 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1), Tmp2);
1830 assert(Node->getNumValues() == 2 && "Unknown CopyToReg");
1831 if (Node->getNumOperands() == 4) {
1832 Tmp3 = LegalizeOp(Node->getOperand(3));
1833 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1), Tmp2,
1836 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1),Tmp2);
1839 // Since this produces two values, make sure to remember that we legalized
1841 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
1842 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
1848 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1850 // Ensure that libcalls are emitted before a return.
1851 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1852 Tmp1 = LegalizeOp(Tmp1);
1853 LastCALLSEQ_END = DAG.getEntryNode();
1855 switch (Node->getNumOperands()) {
1857 Tmp2 = Node->getOperand(1);
1858 Tmp3 = Node->getOperand(2); // Signness
1859 switch (getTypeAction(Tmp2.getValueType())) {
1861 Result = DAG.UpdateNodeOperands(Result, Tmp1, LegalizeOp(Tmp2), Tmp3);
1864 if (!MVT::isVector(Tmp2.getValueType())) {
1866 ExpandOp(Tmp2, Lo, Hi);
1868 // Big endian systems want the hi reg first.
1869 if (!TLI.isLittleEndian())
1873 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Tmp3, Hi,Tmp3);
1875 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Tmp3);
1876 Result = LegalizeOp(Result);
1878 SDNode *InVal = Tmp2.Val;
1879 unsigned NumElems = MVT::getVectorNumElements(InVal->getValueType(0));
1880 MVT::ValueType EVT = MVT::getVectorElementType(InVal->getValueType(0));
1882 // Figure out if there is a simple type corresponding to this Vector
1883 // type. If so, convert to the vector type.
1884 MVT::ValueType TVT = MVT::getVectorType(EVT, NumElems);
1885 if (TLI.isTypeLegal(TVT)) {
1886 // Turn this into a return of the vector type.
1887 Tmp2 = LegalizeOp(Tmp2);
1888 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1889 } else if (NumElems == 1) {
1890 // Turn this into a return of the scalar type.
1891 Tmp2 = ScalarizeVectorOp(Tmp2);
1892 Tmp2 = LegalizeOp(Tmp2);
1893 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1895 // FIXME: Returns of gcc generic vectors smaller than a legal type
1896 // should be returned in integer registers!
1898 // The scalarized value type may not be legal, e.g. it might require
1899 // promotion or expansion. Relegalize the return.
1900 Result = LegalizeOp(Result);
1902 // FIXME: Returns of gcc generic vectors larger than a legal vector
1903 // type should be returned by reference!
1905 SplitVectorOp(Tmp2, Lo, Hi);
1906 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Tmp3, Hi,Tmp3);
1907 Result = LegalizeOp(Result);
1912 Tmp2 = PromoteOp(Node->getOperand(1));
1913 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1914 Result = LegalizeOp(Result);
1919 Result = DAG.UpdateNodeOperands(Result, Tmp1);
1921 default: { // ret <values>
1922 SmallVector<SDOperand, 8> NewValues;
1923 NewValues.push_back(Tmp1);
1924 for (unsigned i = 1, e = Node->getNumOperands(); i < e; i += 2)
1925 switch (getTypeAction(Node->getOperand(i).getValueType())) {
1927 NewValues.push_back(LegalizeOp(Node->getOperand(i)));
1928 NewValues.push_back(Node->getOperand(i+1));
1932 assert(!MVT::isExtendedVT(Node->getOperand(i).getValueType()) &&
1933 "FIXME: TODO: implement returning non-legal vector types!");
1934 ExpandOp(Node->getOperand(i), Lo, Hi);
1935 NewValues.push_back(Lo);
1936 NewValues.push_back(Node->getOperand(i+1));
1938 NewValues.push_back(Hi);
1939 NewValues.push_back(Node->getOperand(i+1));
1944 assert(0 && "Can't promote multiple return value yet!");
1947 if (NewValues.size() == Node->getNumOperands())
1948 Result = DAG.UpdateNodeOperands(Result, &NewValues[0],NewValues.size());
1950 Result = DAG.getNode(ISD::RET, MVT::Other,
1951 &NewValues[0], NewValues.size());
1956 if (Result.getOpcode() == ISD::RET) {
1957 switch (TLI.getOperationAction(Result.getOpcode(), MVT::Other)) {
1958 default: assert(0 && "This action is not supported yet!");
1959 case TargetLowering::Legal: break;
1960 case TargetLowering::Custom:
1961 Tmp1 = TLI.LowerOperation(Result, DAG);
1962 if (Tmp1.Val) Result = Tmp1;
1968 StoreSDNode *ST = cast<StoreSDNode>(Node);
1969 Tmp1 = LegalizeOp(ST->getChain()); // Legalize the chain.
1970 Tmp2 = LegalizeOp(ST->getBasePtr()); // Legalize the pointer.
1971 int SVOffset = ST->getSrcValueOffset();
1972 unsigned Alignment = ST->getAlignment();
1973 bool isVolatile = ST->isVolatile();
1975 if (!ST->isTruncatingStore()) {
1976 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr'
1977 // FIXME: We shouldn't do this for TargetConstantFP's.
1978 // FIXME: move this to the DAG Combiner! Note that we can't regress due
1979 // to phase ordering between legalized code and the dag combiner. This
1980 // probably means that we need to integrate dag combiner and legalizer
1982 // We generally can't do this one for long doubles.
1983 if (ConstantFPSDNode *CFP =dyn_cast<ConstantFPSDNode>(ST->getValue())) {
1984 if (CFP->getValueType(0) == MVT::f32) {
1985 Tmp3 = DAG.getConstant((uint32_t)CFP->getValueAPF().
1986 convertToAPInt().getZExtValue(),
1988 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
1989 SVOffset, isVolatile, Alignment);
1991 } else if (CFP->getValueType(0) == MVT::f64) {
1992 Tmp3 = DAG.getConstant(CFP->getValueAPF().convertToAPInt().
1993 getZExtValue(), MVT::i64);
1994 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
1995 SVOffset, isVolatile, Alignment);
2000 switch (getTypeAction(ST->getStoredVT())) {
2002 Tmp3 = LegalizeOp(ST->getValue());
2003 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2,
2006 MVT::ValueType VT = Tmp3.getValueType();
2007 switch (TLI.getOperationAction(ISD::STORE, VT)) {
2008 default: assert(0 && "This action is not supported yet!");
2009 case TargetLowering::Legal:
2010 // If this is an unaligned store and the target doesn't support it,
2012 if (!TLI.allowsUnalignedMemoryAccesses()) {
2013 unsigned ABIAlignment = TLI.getTargetData()->
2014 getABITypeAlignment(MVT::getTypeForValueType(ST->getStoredVT()));
2015 if (ST->getAlignment() < ABIAlignment)
2016 Result = ExpandUnalignedStore(cast<StoreSDNode>(Result.Val), DAG,
2020 case TargetLowering::Custom:
2021 Tmp1 = TLI.LowerOperation(Result, DAG);
2022 if (Tmp1.Val) Result = Tmp1;
2024 case TargetLowering::Promote:
2025 assert(MVT::isVector(VT) && "Unknown legal promote case!");
2026 Tmp3 = DAG.getNode(ISD::BIT_CONVERT,
2027 TLI.getTypeToPromoteTo(ISD::STORE, VT), Tmp3);
2028 Result = DAG.getStore(Tmp1, Tmp3, Tmp2,
2029 ST->getSrcValue(), SVOffset, isVolatile,
2036 // Truncate the value and store the result.
2037 Tmp3 = PromoteOp(ST->getValue());
2038 Result = DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2039 SVOffset, ST->getStoredVT(),
2040 isVolatile, Alignment);
2044 unsigned IncrementSize = 0;
2047 // If this is a vector type, then we have to calculate the increment as
2048 // the product of the element size in bytes, and the number of elements
2049 // in the high half of the vector.
2050 if (MVT::isVector(ST->getValue().getValueType())) {
2051 SDNode *InVal = ST->getValue().Val;
2052 unsigned NumElems = MVT::getVectorNumElements(InVal->getValueType(0));
2053 MVT::ValueType EVT = MVT::getVectorElementType(InVal->getValueType(0));
2055 // Figure out if there is a simple type corresponding to this Vector
2056 // type. If so, convert to the vector type.
2057 MVT::ValueType TVT = MVT::getVectorType(EVT, NumElems);
2058 if (TLI.isTypeLegal(TVT)) {
2059 // Turn this into a normal store of the vector type.
2060 Tmp3 = LegalizeOp(Node->getOperand(1));
2061 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2062 SVOffset, isVolatile, Alignment);
2063 Result = LegalizeOp(Result);
2065 } else if (NumElems == 1) {
2066 // Turn this into a normal store of the scalar type.
2067 Tmp3 = ScalarizeVectorOp(Node->getOperand(1));
2068 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2069 SVOffset, isVolatile, Alignment);
2070 // The scalarized value type may not be legal, e.g. it might require
2071 // promotion or expansion. Relegalize the scalar store.
2072 Result = LegalizeOp(Result);
2075 SplitVectorOp(Node->getOperand(1), Lo, Hi);
2076 IncrementSize = NumElems/2 * MVT::getSizeInBits(EVT)/8;
2079 ExpandOp(Node->getOperand(1), Lo, Hi);
2080 IncrementSize = Hi.Val ? MVT::getSizeInBits(Hi.getValueType())/8 : 0;
2082 if (!TLI.isLittleEndian())
2086 Lo = DAG.getStore(Tmp1, Lo, Tmp2, ST->getSrcValue(),
2087 SVOffset, isVolatile, Alignment);
2089 if (Hi.Val == NULL) {
2090 // Must be int <-> float one-to-one expansion.
2095 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2,
2096 getIntPtrConstant(IncrementSize));
2097 assert(isTypeLegal(Tmp2.getValueType()) &&
2098 "Pointers must be legal!");
2099 SVOffset += IncrementSize;
2100 if (Alignment > IncrementSize)
2101 Alignment = IncrementSize;
2102 Hi = DAG.getStore(Tmp1, Hi, Tmp2, ST->getSrcValue(),
2103 SVOffset, isVolatile, Alignment);
2104 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi);
2109 assert(isTypeLegal(ST->getValue().getValueType()) &&
2110 "Cannot handle illegal TRUNCSTORE yet!");
2111 Tmp3 = LegalizeOp(ST->getValue());
2113 // The only promote case we handle is TRUNCSTORE:i1 X into
2114 // -> TRUNCSTORE:i8 (and X, 1)
2115 if (ST->getStoredVT() == MVT::i1 &&
2116 TLI.getStoreXAction(MVT::i1) == TargetLowering::Promote) {
2117 // Promote the bool to a mask then store.
2118 Tmp3 = DAG.getNode(ISD::AND, Tmp3.getValueType(), Tmp3,
2119 DAG.getConstant(1, Tmp3.getValueType()));
2120 Result = DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2122 isVolatile, Alignment);
2123 } else if (Tmp1 != ST->getChain() || Tmp3 != ST->getValue() ||
2124 Tmp2 != ST->getBasePtr()) {
2125 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2,
2129 MVT::ValueType StVT = cast<StoreSDNode>(Result.Val)->getStoredVT();
2130 switch (TLI.getStoreXAction(StVT)) {
2131 default: assert(0 && "This action is not supported yet!");
2132 case TargetLowering::Legal:
2133 // If this is an unaligned store and the target doesn't support it,
2135 if (!TLI.allowsUnalignedMemoryAccesses()) {
2136 unsigned ABIAlignment = TLI.getTargetData()->
2137 getABITypeAlignment(MVT::getTypeForValueType(ST->getStoredVT()));
2138 if (ST->getAlignment() < ABIAlignment)
2139 Result = ExpandUnalignedStore(cast<StoreSDNode>(Result.Val), DAG,
2143 case TargetLowering::Custom:
2144 Tmp1 = TLI.LowerOperation(Result, DAG);
2145 if (Tmp1.Val) Result = Tmp1;
2152 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2153 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
2155 case ISD::STACKSAVE:
2156 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2157 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2158 Tmp1 = Result.getValue(0);
2159 Tmp2 = Result.getValue(1);
2161 switch (TLI.getOperationAction(ISD::STACKSAVE, MVT::Other)) {
2162 default: assert(0 && "This action is not supported yet!");
2163 case TargetLowering::Legal: break;
2164 case TargetLowering::Custom:
2165 Tmp3 = TLI.LowerOperation(Result, DAG);
2167 Tmp1 = LegalizeOp(Tmp3);
2168 Tmp2 = LegalizeOp(Tmp3.getValue(1));
2171 case TargetLowering::Expand:
2172 // Expand to CopyFromReg if the target set
2173 // StackPointerRegisterToSaveRestore.
2174 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) {
2175 Tmp1 = DAG.getCopyFromReg(Result.getOperand(0), SP,
2176 Node->getValueType(0));
2177 Tmp2 = Tmp1.getValue(1);
2179 Tmp1 = DAG.getNode(ISD::UNDEF, Node->getValueType(0));
2180 Tmp2 = Node->getOperand(0);
2185 // Since stacksave produce two values, make sure to remember that we
2186 // legalized both of them.
2187 AddLegalizedOperand(SDOperand(Node, 0), Tmp1);
2188 AddLegalizedOperand(SDOperand(Node, 1), Tmp2);
2189 return Op.ResNo ? Tmp2 : Tmp1;
2191 case ISD::STACKRESTORE:
2192 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2193 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
2194 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
2196 switch (TLI.getOperationAction(ISD::STACKRESTORE, MVT::Other)) {
2197 default: assert(0 && "This action is not supported yet!");
2198 case TargetLowering::Legal: break;
2199 case TargetLowering::Custom:
2200 Tmp1 = TLI.LowerOperation(Result, DAG);
2201 if (Tmp1.Val) Result = Tmp1;
2203 case TargetLowering::Expand:
2204 // Expand to CopyToReg if the target set
2205 // StackPointerRegisterToSaveRestore.
2206 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) {
2207 Result = DAG.getCopyToReg(Tmp1, SP, Tmp2);
2215 case ISD::READCYCLECOUNTER:
2216 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain
2217 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2218 switch (TLI.getOperationAction(ISD::READCYCLECOUNTER,
2219 Node->getValueType(0))) {
2220 default: assert(0 && "This action is not supported yet!");
2221 case TargetLowering::Legal:
2222 Tmp1 = Result.getValue(0);
2223 Tmp2 = Result.getValue(1);
2225 case TargetLowering::Custom:
2226 Result = TLI.LowerOperation(Result, DAG);
2227 Tmp1 = LegalizeOp(Result.getValue(0));
2228 Tmp2 = LegalizeOp(Result.getValue(1));
2232 // Since rdcc produce two values, make sure to remember that we legalized
2234 AddLegalizedOperand(SDOperand(Node, 0), Tmp1);
2235 AddLegalizedOperand(SDOperand(Node, 1), Tmp2);
2239 switch (getTypeAction(Node->getOperand(0).getValueType())) {
2240 case Expand: assert(0 && "It's impossible to expand bools");
2242 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the condition.
2245 Tmp1 = PromoteOp(Node->getOperand(0)); // Promote the condition.
2246 // Make sure the condition is either zero or one.
2247 if (!DAG.MaskedValueIsZero(Tmp1,
2248 MVT::getIntVTBitMask(Tmp1.getValueType())^1))
2249 Tmp1 = DAG.getZeroExtendInReg(Tmp1, MVT::i1);
2252 Tmp2 = LegalizeOp(Node->getOperand(1)); // TrueVal
2253 Tmp3 = LegalizeOp(Node->getOperand(2)); // FalseVal
2255 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2257 switch (TLI.getOperationAction(ISD::SELECT, Tmp2.getValueType())) {
2258 default: assert(0 && "This action is not supported yet!");
2259 case TargetLowering::Legal: break;
2260 case TargetLowering::Custom: {
2261 Tmp1 = TLI.LowerOperation(Result, DAG);
2262 if (Tmp1.Val) Result = Tmp1;
2265 case TargetLowering::Expand:
2266 if (Tmp1.getOpcode() == ISD::SETCC) {
2267 Result = DAG.getSelectCC(Tmp1.getOperand(0), Tmp1.getOperand(1),
2269 cast<CondCodeSDNode>(Tmp1.getOperand(2))->get());
2271 Result = DAG.getSelectCC(Tmp1,
2272 DAG.getConstant(0, Tmp1.getValueType()),
2273 Tmp2, Tmp3, ISD::SETNE);
2276 case TargetLowering::Promote: {
2277 MVT::ValueType NVT =
2278 TLI.getTypeToPromoteTo(ISD::SELECT, Tmp2.getValueType());
2279 unsigned ExtOp, TruncOp;
2280 if (MVT::isVector(Tmp2.getValueType())) {
2281 ExtOp = ISD::BIT_CONVERT;
2282 TruncOp = ISD::BIT_CONVERT;
2283 } else if (MVT::isInteger(Tmp2.getValueType())) {
2284 ExtOp = ISD::ANY_EXTEND;
2285 TruncOp = ISD::TRUNCATE;
2287 ExtOp = ISD::FP_EXTEND;
2288 TruncOp = ISD::FP_ROUND;
2290 // Promote each of the values to the new type.
2291 Tmp2 = DAG.getNode(ExtOp, NVT, Tmp2);
2292 Tmp3 = DAG.getNode(ExtOp, NVT, Tmp3);
2293 // Perform the larger operation, then round down.
2294 Result = DAG.getNode(ISD::SELECT, NVT, Tmp1, Tmp2,Tmp3);
2295 Result = DAG.getNode(TruncOp, Node->getValueType(0), Result);
2300 case ISD::SELECT_CC: {
2301 Tmp1 = Node->getOperand(0); // LHS
2302 Tmp2 = Node->getOperand(1); // RHS
2303 Tmp3 = LegalizeOp(Node->getOperand(2)); // True
2304 Tmp4 = LegalizeOp(Node->getOperand(3)); // False
2305 SDOperand CC = Node->getOperand(4);
2307 LegalizeSetCCOperands(Tmp1, Tmp2, CC);
2309 // If we didn't get both a LHS and RHS back from LegalizeSetCCOperands,
2310 // the LHS is a legal SETCC itself. In this case, we need to compare
2311 // the result against zero to select between true and false values.
2312 if (Tmp2.Val == 0) {
2313 Tmp2 = DAG.getConstant(0, Tmp1.getValueType());
2314 CC = DAG.getCondCode(ISD::SETNE);
2316 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4, CC);
2318 // Everything is legal, see if we should expand this op or something.
2319 switch (TLI.getOperationAction(ISD::SELECT_CC, Tmp3.getValueType())) {
2320 default: assert(0 && "This action is not supported yet!");
2321 case TargetLowering::Legal: break;
2322 case TargetLowering::Custom:
2323 Tmp1 = TLI.LowerOperation(Result, DAG);
2324 if (Tmp1.Val) Result = Tmp1;
2330 Tmp1 = Node->getOperand(0);
2331 Tmp2 = Node->getOperand(1);
2332 Tmp3 = Node->getOperand(2);
2333 LegalizeSetCCOperands(Tmp1, Tmp2, Tmp3);
2335 // If we had to Expand the SetCC operands into a SELECT node, then it may
2336 // not always be possible to return a true LHS & RHS. In this case, just
2337 // return the value we legalized, returned in the LHS
2338 if (Tmp2.Val == 0) {
2343 switch (TLI.getOperationAction(ISD::SETCC, Tmp1.getValueType())) {
2344 default: assert(0 && "Cannot handle this action for SETCC yet!");
2345 case TargetLowering::Custom:
2348 case TargetLowering::Legal:
2349 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2351 Tmp4 = TLI.LowerOperation(Result, DAG);
2352 if (Tmp4.Val) Result = Tmp4;
2355 case TargetLowering::Promote: {
2356 // First step, figure out the appropriate operation to use.
2357 // Allow SETCC to not be supported for all legal data types
2358 // Mostly this targets FP
2359 MVT::ValueType NewInTy = Node->getOperand(0).getValueType();
2360 MVT::ValueType OldVT = NewInTy; OldVT = OldVT;
2362 // Scan for the appropriate larger type to use.
2364 NewInTy = (MVT::ValueType)(NewInTy+1);
2366 assert(MVT::isInteger(NewInTy) == MVT::isInteger(OldVT) &&
2367 "Fell off of the edge of the integer world");
2368 assert(MVT::isFloatingPoint(NewInTy) == MVT::isFloatingPoint(OldVT) &&
2369 "Fell off of the edge of the floating point world");
2371 // If the target supports SETCC of this type, use it.
2372 if (TLI.isOperationLegal(ISD::SETCC, NewInTy))
2375 if (MVT::isInteger(NewInTy))
2376 assert(0 && "Cannot promote Legal Integer SETCC yet");
2378 Tmp1 = DAG.getNode(ISD::FP_EXTEND, NewInTy, Tmp1);
2379 Tmp2 = DAG.getNode(ISD::FP_EXTEND, NewInTy, Tmp2);
2381 Tmp1 = LegalizeOp(Tmp1);
2382 Tmp2 = LegalizeOp(Tmp2);
2383 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2384 Result = LegalizeOp(Result);
2387 case TargetLowering::Expand:
2388 // Expand a setcc node into a select_cc of the same condition, lhs, and
2389 // rhs that selects between const 1 (true) and const 0 (false).
2390 MVT::ValueType VT = Node->getValueType(0);
2391 Result = DAG.getNode(ISD::SELECT_CC, VT, Tmp1, Tmp2,
2392 DAG.getConstant(1, VT), DAG.getConstant(0, VT),
2399 case ISD::MEMMOVE: {
2400 Tmp1 = LegalizeOp(Node->getOperand(0)); // Chain
2401 Tmp2 = LegalizeOp(Node->getOperand(1)); // Pointer
2403 if (Node->getOpcode() == ISD::MEMSET) { // memset = ubyte
2404 switch (getTypeAction(Node->getOperand(2).getValueType())) {
2405 case Expand: assert(0 && "Cannot expand a byte!");
2407 Tmp3 = LegalizeOp(Node->getOperand(2));
2410 Tmp3 = PromoteOp(Node->getOperand(2));
2414 Tmp3 = LegalizeOp(Node->getOperand(2)); // memcpy/move = pointer,
2418 switch (getTypeAction(Node->getOperand(3).getValueType())) {
2420 // Length is too big, just take the lo-part of the length.
2422 ExpandOp(Node->getOperand(3), Tmp4, HiPart);
2426 Tmp4 = LegalizeOp(Node->getOperand(3));
2429 Tmp4 = PromoteOp(Node->getOperand(3));
2434 switch (getTypeAction(Node->getOperand(4).getValueType())) { // uint
2435 case Expand: assert(0 && "Cannot expand this yet!");
2437 Tmp5 = LegalizeOp(Node->getOperand(4));
2440 Tmp5 = PromoteOp(Node->getOperand(4));
2444 switch (TLI.getOperationAction(Node->getOpcode(), MVT::Other)) {
2445 default: assert(0 && "This action not implemented for this operation!");
2446 case TargetLowering::Custom:
2449 case TargetLowering::Legal:
2450 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4, Tmp5);
2452 Tmp1 = TLI.LowerOperation(Result, DAG);
2453 if (Tmp1.Val) Result = Tmp1;
2456 case TargetLowering::Expand: {
2457 // Otherwise, the target does not support this operation. Lower the
2458 // operation to an explicit libcall as appropriate.
2459 MVT::ValueType IntPtr = TLI.getPointerTy();
2460 const Type *IntPtrTy = TLI.getTargetData()->getIntPtrType();
2461 TargetLowering::ArgListTy Args;
2462 TargetLowering::ArgListEntry Entry;
2464 const char *FnName = 0;
2465 if (Node->getOpcode() == ISD::MEMSET) {
2466 Entry.Node = Tmp2; Entry.Ty = IntPtrTy;
2467 Args.push_back(Entry);
2468 // Extend the (previously legalized) ubyte argument to be an int value
2470 if (Tmp3.getValueType() > MVT::i32)
2471 Tmp3 = DAG.getNode(ISD::TRUNCATE, MVT::i32, Tmp3);
2473 Tmp3 = DAG.getNode(ISD::ZERO_EXTEND, MVT::i32, Tmp3);
2474 Entry.Node = Tmp3; Entry.Ty = Type::Int32Ty; Entry.isSExt = true;
2475 Args.push_back(Entry);
2476 Entry.Node = Tmp4; Entry.Ty = IntPtrTy; Entry.isSExt = false;
2477 Args.push_back(Entry);
2480 } else if (Node->getOpcode() == ISD::MEMCPY ||
2481 Node->getOpcode() == ISD::MEMMOVE) {
2482 Entry.Ty = IntPtrTy;
2483 Entry.Node = Tmp2; Args.push_back(Entry);
2484 Entry.Node = Tmp3; Args.push_back(Entry);
2485 Entry.Node = Tmp4; Args.push_back(Entry);
2486 FnName = Node->getOpcode() == ISD::MEMMOVE ? "memmove" : "memcpy";
2488 assert(0 && "Unknown op!");
2491 std::pair<SDOperand,SDOperand> CallResult =
2492 TLI.LowerCallTo(Tmp1, Type::VoidTy, false, false, CallingConv::C, false,
2493 DAG.getExternalSymbol(FnName, IntPtr), Args, DAG);
2494 Result = CallResult.second;
2501 case ISD::SHL_PARTS:
2502 case ISD::SRA_PARTS:
2503 case ISD::SRL_PARTS: {
2504 SmallVector<SDOperand, 8> Ops;
2505 bool Changed = false;
2506 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
2507 Ops.push_back(LegalizeOp(Node->getOperand(i)));
2508 Changed |= Ops.back() != Node->getOperand(i);
2511 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
2513 switch (TLI.getOperationAction(Node->getOpcode(),
2514 Node->getValueType(0))) {
2515 default: assert(0 && "This action is not supported yet!");
2516 case TargetLowering::Legal: break;
2517 case TargetLowering::Custom:
2518 Tmp1 = TLI.LowerOperation(Result, DAG);
2520 SDOperand Tmp2, RetVal(0, 0);
2521 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) {
2522 Tmp2 = LegalizeOp(Tmp1.getValue(i));
2523 AddLegalizedOperand(SDOperand(Node, i), Tmp2);
2527 assert(RetVal.Val && "Illegal result number");
2533 // Since these produce multiple values, make sure to remember that we
2534 // legalized all of them.
2535 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
2536 AddLegalizedOperand(SDOperand(Node, i), Result.getValue(i));
2537 return Result.getValue(Op.ResNo);
2558 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
2559 switch (getTypeAction(Node->getOperand(1).getValueType())) {
2560 case Expand: assert(0 && "Not possible");
2562 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the RHS.
2565 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the RHS.
2569 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
2571 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
2572 default: assert(0 && "BinOp legalize operation not supported");
2573 case TargetLowering::Legal: break;
2574 case TargetLowering::Custom:
2575 Tmp1 = TLI.LowerOperation(Result, DAG);
2576 if (Tmp1.Val) Result = Tmp1;
2578 case TargetLowering::Expand: {
2579 if (Node->getValueType(0) == MVT::i32) {
2580 switch (Node->getOpcode()) {
2581 default: assert(0 && "Do not know how to expand this integer BinOp!");
2584 RTLIB::Libcall LC = Node->getOpcode() == ISD::UDIV
2585 ? RTLIB::UDIV_I32 : RTLIB::SDIV_I32;
2587 bool isSigned = Node->getOpcode() == ISD::SDIV;
2588 Result = ExpandLibCall(TLI.getLibcallName(LC), Node, isSigned, Dummy);
2593 assert(MVT::isVector(Node->getValueType(0)) &&
2594 "Cannot expand this binary operator!");
2595 // Expand the operation into a bunch of nasty scalar code.
2596 SmallVector<SDOperand, 8> Ops;
2597 MVT::ValueType EltVT = MVT::getVectorElementType(Node->getValueType(0));
2598 MVT::ValueType PtrVT = TLI.getPointerTy();
2599 for (unsigned i = 0, e = MVT::getVectorNumElements(Node->getValueType(0));
2601 SDOperand Idx = DAG.getConstant(i, PtrVT);
2602 SDOperand LHS = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, Tmp1, Idx);
2603 SDOperand RHS = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, Tmp2, Idx);
2604 Ops.push_back(DAG.getNode(Node->getOpcode(), EltVT, LHS, RHS));
2606 Result = DAG.getNode(ISD::BUILD_VECTOR, Node->getValueType(0),
2607 &Ops[0], Ops.size());
2610 case TargetLowering::Promote: {
2611 switch (Node->getOpcode()) {
2612 default: assert(0 && "Do not know how to promote this BinOp!");
2616 MVT::ValueType OVT = Node->getValueType(0);
2617 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
2618 assert(MVT::isVector(OVT) && "Cannot promote this BinOp!");
2619 // Bit convert each of the values to the new type.
2620 Tmp1 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp1);
2621 Tmp2 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp2);
2622 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
2623 // Bit convert the result back the original type.
2624 Result = DAG.getNode(ISD::BIT_CONVERT, OVT, Result);
2632 case ISD::FCOPYSIGN: // FCOPYSIGN does not require LHS/RHS to match type!
2633 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
2634 switch (getTypeAction(Node->getOperand(1).getValueType())) {
2635 case Expand: assert(0 && "Not possible");
2637 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the RHS.
2640 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the RHS.
2644 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
2646 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
2647 default: assert(0 && "Operation not supported");
2648 case TargetLowering::Custom:
2649 Tmp1 = TLI.LowerOperation(Result, DAG);
2650 if (Tmp1.Val) Result = Tmp1;
2652 case TargetLowering::Legal: break;
2653 case TargetLowering::Expand: {
2654 // If this target supports fabs/fneg natively and select is cheap,
2655 // do this efficiently.
2656 if (!TLI.isSelectExpensive() &&
2657 TLI.getOperationAction(ISD::FABS, Tmp1.getValueType()) ==
2658 TargetLowering::Legal &&
2659 TLI.getOperationAction(ISD::FNEG, Tmp1.getValueType()) ==
2660 TargetLowering::Legal) {
2661 // Get the sign bit of the RHS.
2662 MVT::ValueType IVT =
2663 Tmp2.getValueType() == MVT::f32 ? MVT::i32 : MVT::i64;
2664 SDOperand SignBit = DAG.getNode(ISD::BIT_CONVERT, IVT, Tmp2);
2665 SignBit = DAG.getSetCC(TLI.getSetCCResultTy(),
2666 SignBit, DAG.getConstant(0, IVT), ISD::SETLT);
2667 // Get the absolute value of the result.
2668 SDOperand AbsVal = DAG.getNode(ISD::FABS, Tmp1.getValueType(), Tmp1);
2669 // Select between the nabs and abs value based on the sign bit of
2671 Result = DAG.getNode(ISD::SELECT, AbsVal.getValueType(), SignBit,
2672 DAG.getNode(ISD::FNEG, AbsVal.getValueType(),
2675 Result = LegalizeOp(Result);
2679 // Otherwise, do bitwise ops!
2680 MVT::ValueType NVT =
2681 Node->getValueType(0) == MVT::f32 ? MVT::i32 : MVT::i64;
2682 Result = ExpandFCOPYSIGNToBitwiseOps(Node, NVT, DAG, TLI);
2683 Result = DAG.getNode(ISD::BIT_CONVERT, Node->getValueType(0), Result);
2684 Result = LegalizeOp(Result);
2692 Tmp1 = LegalizeOp(Node->getOperand(0));
2693 Tmp2 = LegalizeOp(Node->getOperand(1));
2694 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
2695 // Since this produces two values, make sure to remember that we legalized
2697 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
2698 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
2703 Tmp1 = LegalizeOp(Node->getOperand(0));
2704 Tmp2 = LegalizeOp(Node->getOperand(1));
2705 Tmp3 = LegalizeOp(Node->getOperand(2));
2706 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2707 // Since this produces two values, make sure to remember that we legalized
2709 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
2710 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
2713 case ISD::BUILD_PAIR: {
2714 MVT::ValueType PairTy = Node->getValueType(0);
2715 // TODO: handle the case where the Lo and Hi operands are not of legal type
2716 Tmp1 = LegalizeOp(Node->getOperand(0)); // Lo
2717 Tmp2 = LegalizeOp(Node->getOperand(1)); // Hi
2718 switch (TLI.getOperationAction(ISD::BUILD_PAIR, PairTy)) {
2719 case TargetLowering::Promote:
2720 case TargetLowering::Custom:
2721 assert(0 && "Cannot promote/custom this yet!");
2722 case TargetLowering::Legal:
2723 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1))
2724 Result = DAG.getNode(ISD::BUILD_PAIR, PairTy, Tmp1, Tmp2);
2726 case TargetLowering::Expand:
2727 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, PairTy, Tmp1);
2728 Tmp2 = DAG.getNode(ISD::ANY_EXTEND, PairTy, Tmp2);
2729 Tmp2 = DAG.getNode(ISD::SHL, PairTy, Tmp2,
2730 DAG.getConstant(MVT::getSizeInBits(PairTy)/2,
2731 TLI.getShiftAmountTy()));
2732 Result = DAG.getNode(ISD::OR, PairTy, Tmp1, Tmp2);
2741 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
2742 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS
2744 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
2745 case TargetLowering::Promote: assert(0 && "Cannot promote this yet!");
2746 case TargetLowering::Custom:
2749 case TargetLowering::Legal:
2750 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
2752 Tmp1 = TLI.LowerOperation(Result, DAG);
2753 if (Tmp1.Val) Result = Tmp1;
2756 case TargetLowering::Expand:
2757 unsigned DivOpc= (Node->getOpcode() == ISD::UREM) ? ISD::UDIV : ISD::SDIV;
2758 bool isSigned = DivOpc == ISD::SDIV;
2759 if (MVT::isInteger(Node->getValueType(0))) {
2760 if (TLI.getOperationAction(DivOpc, Node->getValueType(0)) ==
2761 TargetLowering::Legal) {
2763 MVT::ValueType VT = Node->getValueType(0);
2764 Result = DAG.getNode(DivOpc, VT, Tmp1, Tmp2);
2765 Result = DAG.getNode(ISD::MUL, VT, Result, Tmp2);
2766 Result = DAG.getNode(ISD::SUB, VT, Tmp1, Result);
2768 assert(Node->getValueType(0) == MVT::i32 &&
2769 "Cannot expand this binary operator!");
2770 RTLIB::Libcall LC = Node->getOpcode() == ISD::UREM
2771 ? RTLIB::UREM_I32 : RTLIB::SREM_I32;
2773 Result = ExpandLibCall(TLI.getLibcallName(LC), Node, isSigned, Dummy);
2776 // Floating point mod -> fmod libcall.
2777 RTLIB::Libcall LC = Node->getValueType(0) == MVT::f32
2778 ? RTLIB::REM_F32 : RTLIB::REM_F64;
2780 Result = ExpandLibCall(TLI.getLibcallName(LC), Node,
2781 false/*sign irrelevant*/, Dummy);
2787 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2788 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
2790 MVT::ValueType VT = Node->getValueType(0);
2791 switch (TLI.getOperationAction(Node->getOpcode(), MVT::Other)) {
2792 default: assert(0 && "This action is not supported yet!");
2793 case TargetLowering::Custom:
2796 case TargetLowering::Legal:
2797 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
2798 Result = Result.getValue(0);
2799 Tmp1 = Result.getValue(1);
2802 Tmp2 = TLI.LowerOperation(Result, DAG);
2804 Result = LegalizeOp(Tmp2);
2805 Tmp1 = LegalizeOp(Tmp2.getValue(1));
2809 case TargetLowering::Expand: {
2810 SrcValueSDNode *SV = cast<SrcValueSDNode>(Node->getOperand(2));
2811 SDOperand VAList = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp2,
2812 SV->getValue(), SV->getOffset());
2813 // Increment the pointer, VAList, to the next vaarg
2814 Tmp3 = DAG.getNode(ISD::ADD, TLI.getPointerTy(), VAList,
2815 DAG.getConstant(MVT::getSizeInBits(VT)/8,
2816 TLI.getPointerTy()));
2817 // Store the incremented VAList to the legalized pointer
2818 Tmp3 = DAG.getStore(VAList.getValue(1), Tmp3, Tmp2, SV->getValue(),
2820 // Load the actual argument out of the pointer VAList
2821 Result = DAG.getLoad(VT, Tmp3, VAList, NULL, 0);
2822 Tmp1 = LegalizeOp(Result.getValue(1));
2823 Result = LegalizeOp(Result);
2827 // Since VAARG produces two values, make sure to remember that we
2828 // legalized both of them.
2829 AddLegalizedOperand(SDOperand(Node, 0), Result);
2830 AddLegalizedOperand(SDOperand(Node, 1), Tmp1);
2831 return Op.ResNo ? Tmp1 : Result;
2835 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2836 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the dest pointer.
2837 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the source pointer.
2839 switch (TLI.getOperationAction(ISD::VACOPY, MVT::Other)) {
2840 default: assert(0 && "This action is not supported yet!");
2841 case TargetLowering::Custom:
2844 case TargetLowering::Legal:
2845 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3,
2846 Node->getOperand(3), Node->getOperand(4));
2848 Tmp1 = TLI.LowerOperation(Result, DAG);
2849 if (Tmp1.Val) Result = Tmp1;
2852 case TargetLowering::Expand:
2853 // This defaults to loading a pointer from the input and storing it to the
2854 // output, returning the chain.
2855 SrcValueSDNode *SVD = cast<SrcValueSDNode>(Node->getOperand(3));
2856 SrcValueSDNode *SVS = cast<SrcValueSDNode>(Node->getOperand(4));
2857 Tmp4 = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp3, SVD->getValue(),
2859 Result = DAG.getStore(Tmp4.getValue(1), Tmp4, Tmp2, SVS->getValue(),
2866 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2867 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
2869 switch (TLI.getOperationAction(ISD::VAEND, MVT::Other)) {
2870 default: assert(0 && "This action is not supported yet!");
2871 case TargetLowering::Custom:
2874 case TargetLowering::Legal:
2875 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
2877 Tmp1 = TLI.LowerOperation(Tmp1, DAG);
2878 if (Tmp1.Val) Result = Tmp1;
2881 case TargetLowering::Expand:
2882 Result = Tmp1; // Default to a no-op, return the chain
2888 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2889 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
2891 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
2893 switch (TLI.getOperationAction(ISD::VASTART, MVT::Other)) {
2894 default: assert(0 && "This action is not supported yet!");
2895 case TargetLowering::Legal: break;
2896 case TargetLowering::Custom:
2897 Tmp1 = TLI.LowerOperation(Result, DAG);
2898 if (Tmp1.Val) Result = Tmp1;
2905 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
2906 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS
2907 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
2908 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
2910 assert(0 && "ROTL/ROTR legalize operation not supported");
2912 case TargetLowering::Legal:
2914 case TargetLowering::Custom:
2915 Tmp1 = TLI.LowerOperation(Result, DAG);
2916 if (Tmp1.Val) Result = Tmp1;
2918 case TargetLowering::Promote:
2919 assert(0 && "Do not know how to promote ROTL/ROTR");
2921 case TargetLowering::Expand:
2922 assert(0 && "Do not know how to expand ROTL/ROTR");
2928 Tmp1 = LegalizeOp(Node->getOperand(0)); // Op
2929 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
2930 case TargetLowering::Custom:
2931 assert(0 && "Cannot custom legalize this yet!");
2932 case TargetLowering::Legal:
2933 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2935 case TargetLowering::Promote: {
2936 MVT::ValueType OVT = Tmp1.getValueType();
2937 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
2938 unsigned DiffBits = MVT::getSizeInBits(NVT) - MVT::getSizeInBits(OVT);
2940 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1);
2941 Tmp1 = DAG.getNode(ISD::BSWAP, NVT, Tmp1);
2942 Result = DAG.getNode(ISD::SRL, NVT, Tmp1,
2943 DAG.getConstant(DiffBits, TLI.getShiftAmountTy()));
2946 case TargetLowering::Expand:
2947 Result = ExpandBSWAP(Tmp1);
2955 Tmp1 = LegalizeOp(Node->getOperand(0)); // Op
2956 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
2957 case TargetLowering::Custom:
2958 case TargetLowering::Legal:
2959 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2960 if (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0)) ==
2961 TargetLowering::Custom) {
2962 Tmp1 = TLI.LowerOperation(Result, DAG);
2968 case TargetLowering::Promote: {
2969 MVT::ValueType OVT = Tmp1.getValueType();
2970 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
2972 // Zero extend the argument.
2973 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1);
2974 // Perform the larger operation, then subtract if needed.
2975 Tmp1 = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1);
2976 switch (Node->getOpcode()) {
2981 //if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT)
2982 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), Tmp1,
2983 DAG.getConstant(MVT::getSizeInBits(NVT), NVT),
2985 Result = DAG.getNode(ISD::SELECT, NVT, Tmp2,
2986 DAG.getConstant(MVT::getSizeInBits(OVT),NVT), Tmp1);
2989 // Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT))
2990 Result = DAG.getNode(ISD::SUB, NVT, Tmp1,
2991 DAG.getConstant(MVT::getSizeInBits(NVT) -
2992 MVT::getSizeInBits(OVT), NVT));
2997 case TargetLowering::Expand:
2998 Result = ExpandBitCount(Node->getOpcode(), Tmp1);
3009 Tmp1 = LegalizeOp(Node->getOperand(0));
3010 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3011 case TargetLowering::Promote:
3012 case TargetLowering::Custom:
3015 case TargetLowering::Legal:
3016 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3018 Tmp1 = TLI.LowerOperation(Result, DAG);
3019 if (Tmp1.Val) Result = Tmp1;
3022 case TargetLowering::Expand:
3023 switch (Node->getOpcode()) {
3024 default: assert(0 && "Unreachable!");
3026 // Expand Y = FNEG(X) -> Y = SUB -0.0, X
3027 Tmp2 = DAG.getConstantFP(-0.0, Node->getValueType(0));
3028 Result = DAG.getNode(ISD::FSUB, Node->getValueType(0), Tmp2, Tmp1);
3031 // Expand Y = FABS(X) -> Y = (X >u 0.0) ? X : fneg(X).
3032 MVT::ValueType VT = Node->getValueType(0);
3033 Tmp2 = DAG.getConstantFP(0.0, VT);
3034 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), Tmp1, Tmp2, ISD::SETUGT);
3035 Tmp3 = DAG.getNode(ISD::FNEG, VT, Tmp1);
3036 Result = DAG.getNode(ISD::SELECT, VT, Tmp2, Tmp1, Tmp3);
3042 MVT::ValueType VT = Node->getValueType(0);
3043 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
3044 switch(Node->getOpcode()) {
3046 LC = VT == MVT::f32 ? RTLIB::SQRT_F32 : RTLIB::SQRT_F64;
3049 LC = VT == MVT::f32 ? RTLIB::SIN_F32 : RTLIB::SIN_F64;
3052 LC = VT == MVT::f32 ? RTLIB::COS_F32 : RTLIB::COS_F64;
3054 default: assert(0 && "Unreachable!");
3057 Result = ExpandLibCall(TLI.getLibcallName(LC), Node,
3058 false/*sign irrelevant*/, Dummy);
3066 // We always lower FPOWI into a libcall. No target support it yet.
3067 RTLIB::Libcall LC = Node->getValueType(0) == MVT::f32
3068 ? RTLIB::POWI_F32 : RTLIB::POWI_F64;
3070 Result = ExpandLibCall(TLI.getLibcallName(LC), Node,
3071 false/*sign irrelevant*/, Dummy);
3074 case ISD::BIT_CONVERT:
3075 if (!isTypeLegal(Node->getOperand(0).getValueType())) {
3076 Result = ExpandBIT_CONVERT(Node->getValueType(0), Node->getOperand(0));
3077 } else if (MVT::isVector(Op.getOperand(0).getValueType())) {
3078 // The input has to be a vector type, we have to either scalarize it, pack
3079 // it, or convert it based on whether the input vector type is legal.
3080 SDNode *InVal = Node->getOperand(0).Val;
3081 unsigned NumElems = MVT::getVectorNumElements(InVal->getValueType(0));
3082 MVT::ValueType EVT = MVT::getVectorElementType(InVal->getValueType(0));
3084 // Figure out if there is a simple type corresponding to this Vector
3085 // type. If so, convert to the vector type.
3086 MVT::ValueType TVT = MVT::getVectorType(EVT, NumElems);
3087 if (TLI.isTypeLegal(TVT)) {
3088 // Turn this into a bit convert of the vector input.
3089 Result = DAG.getNode(ISD::BIT_CONVERT, Node->getValueType(0),
3090 LegalizeOp(Node->getOperand(0)));
3092 } else if (NumElems == 1) {
3093 // Turn this into a bit convert of the scalar input.
3094 Result = DAG.getNode(ISD::BIT_CONVERT, Node->getValueType(0),
3095 ScalarizeVectorOp(Node->getOperand(0)));
3098 // FIXME: UNIMP! Store then reload
3099 assert(0 && "Cast from unsupported vector type not implemented yet!");
3102 switch (TLI.getOperationAction(ISD::BIT_CONVERT,
3103 Node->getOperand(0).getValueType())) {
3104 default: assert(0 && "Unknown operation action!");
3105 case TargetLowering::Expand:
3106 Result = ExpandBIT_CONVERT(Node->getValueType(0), Node->getOperand(0));
3108 case TargetLowering::Legal:
3109 Tmp1 = LegalizeOp(Node->getOperand(0));
3110 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3116 // Conversion operators. The source and destination have different types.
3117 case ISD::SINT_TO_FP:
3118 case ISD::UINT_TO_FP: {
3119 bool isSigned = Node->getOpcode() == ISD::SINT_TO_FP;
3120 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3122 switch (TLI.getOperationAction(Node->getOpcode(),
3123 Node->getOperand(0).getValueType())) {
3124 default: assert(0 && "Unknown operation action!");
3125 case TargetLowering::Custom:
3128 case TargetLowering::Legal:
3129 Tmp1 = LegalizeOp(Node->getOperand(0));
3130 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3132 Tmp1 = TLI.LowerOperation(Result, DAG);
3133 if (Tmp1.Val) Result = Tmp1;
3136 case TargetLowering::Expand:
3137 Result = ExpandLegalINT_TO_FP(isSigned,
3138 LegalizeOp(Node->getOperand(0)),
3139 Node->getValueType(0));
3141 case TargetLowering::Promote:
3142 Result = PromoteLegalINT_TO_FP(LegalizeOp(Node->getOperand(0)),
3143 Node->getValueType(0),
3149 Result = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP,
3150 Node->getValueType(0), Node->getOperand(0));
3153 Tmp1 = PromoteOp(Node->getOperand(0));
3155 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, Tmp1.getValueType(),
3156 Tmp1, DAG.getValueType(Node->getOperand(0).getValueType()));
3158 Tmp1 = DAG.getZeroExtendInReg(Tmp1,
3159 Node->getOperand(0).getValueType());
3161 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3162 Result = LegalizeOp(Result); // The 'op' is not necessarily legal!
3168 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3170 Tmp1 = LegalizeOp(Node->getOperand(0));
3171 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3174 ExpandOp(Node->getOperand(0), Tmp1, Tmp2);
3176 // Since the result is legal, we should just be able to truncate the low
3177 // part of the source.
3178 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), Tmp1);
3181 Result = PromoteOp(Node->getOperand(0));
3182 Result = DAG.getNode(ISD::TRUNCATE, Op.getValueType(), Result);
3187 case ISD::FP_TO_SINT:
3188 case ISD::FP_TO_UINT:
3189 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3191 Tmp1 = LegalizeOp(Node->getOperand(0));
3193 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))){
3194 default: assert(0 && "Unknown operation action!");
3195 case TargetLowering::Custom:
3198 case TargetLowering::Legal:
3199 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3201 Tmp1 = TLI.LowerOperation(Result, DAG);
3202 if (Tmp1.Val) Result = Tmp1;
3205 case TargetLowering::Promote:
3206 Result = PromoteLegalFP_TO_INT(Tmp1, Node->getValueType(0),
3207 Node->getOpcode() == ISD::FP_TO_SINT);
3209 case TargetLowering::Expand:
3210 if (Node->getOpcode() == ISD::FP_TO_UINT) {
3211 SDOperand True, False;
3212 MVT::ValueType VT = Node->getOperand(0).getValueType();
3213 MVT::ValueType NVT = Node->getValueType(0);
3214 unsigned ShiftAmt = MVT::getSizeInBits(NVT)-1;
3215 const uint64_t zero[] = {0, 0};
3216 APFloat apf = APFloat(APInt(MVT::getSizeInBits(VT), 2, zero));
3217 uint64_t x = 1ULL << ShiftAmt;
3218 (void)apf.convertFromInteger(&x, 1, false, APFloat::rmTowardZero);
3219 Tmp2 = DAG.getConstantFP(apf, VT);
3220 Tmp3 = DAG.getSetCC(TLI.getSetCCResultTy(),
3221 Node->getOperand(0), Tmp2, ISD::SETLT);
3222 True = DAG.getNode(ISD::FP_TO_SINT, NVT, Node->getOperand(0));
3223 False = DAG.getNode(ISD::FP_TO_SINT, NVT,
3224 DAG.getNode(ISD::FSUB, VT, Node->getOperand(0),
3226 False = DAG.getNode(ISD::XOR, NVT, False,
3227 DAG.getConstant(1ULL << ShiftAmt, NVT));
3228 Result = DAG.getNode(ISD::SELECT, NVT, Tmp3, True, False);
3231 assert(0 && "Do not know how to expand FP_TO_SINT yet!");
3237 // Convert f32 / f64 to i32 / i64.
3238 MVT::ValueType VT = Op.getValueType();
3239 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
3240 switch (Node->getOpcode()) {
3241 case ISD::FP_TO_SINT: {
3242 MVT::ValueType OVT = Node->getOperand(0).getValueType();
3243 if (OVT == MVT::f32)
3244 LC = (VT == MVT::i32)
3245 ? RTLIB::FPTOSINT_F32_I32 : RTLIB::FPTOSINT_F32_I64;
3246 else if (OVT == MVT::f64)
3247 LC = (VT == MVT::i32)
3248 ? RTLIB::FPTOSINT_F64_I32 : RTLIB::FPTOSINT_F64_I64;
3249 else if (OVT == MVT::f80 || OVT == MVT::f128 || OVT == MVT::ppcf128) {
3250 assert(VT == MVT::i64);
3251 LC = RTLIB::FPTOSINT_LD_I64;
3255 case ISD::FP_TO_UINT: {
3256 MVT::ValueType OVT = Node->getOperand(0).getValueType();
3257 if (OVT == MVT::f32)
3258 LC = (VT == MVT::i32)
3259 ? RTLIB::FPTOUINT_F32_I32 : RTLIB::FPTOSINT_F32_I64;
3260 else if (OVT == MVT::f64)
3261 LC = (VT == MVT::i32)
3262 ? RTLIB::FPTOUINT_F64_I32 : RTLIB::FPTOSINT_F64_I64;
3263 else if (OVT == MVT::f80 || OVT == MVT::f128 || OVT == MVT::ppcf128) {
3264 LC = (VT == MVT::i32)
3265 ? RTLIB::FPTOUINT_LD_I32 : RTLIB::FPTOUINT_LD_I64;
3269 default: assert(0 && "Unreachable!");
3272 Result = ExpandLibCall(TLI.getLibcallName(LC), Node,
3273 false/*sign irrelevant*/, Dummy);
3277 Tmp1 = PromoteOp(Node->getOperand(0));
3278 Result = DAG.UpdateNodeOperands(Result, LegalizeOp(Tmp1));
3279 Result = LegalizeOp(Result);
3284 case ISD::FP_EXTEND:
3285 case ISD::FP_ROUND: {
3286 MVT::ValueType newVT = Op.getValueType();
3287 MVT::ValueType oldVT = Op.getOperand(0).getValueType();
3288 if (TLI.getConvertAction(oldVT, newVT) == TargetLowering::Expand) {
3289 // The only way we can lower this is to turn it into a STORE,
3290 // LOAD pair, targetting a temporary location (a stack slot).
3292 // NOTE: there is a choice here between constantly creating new stack
3293 // slots and always reusing the same one. We currently always create
3294 // new ones, as reuse may inhibit scheduling.
3295 MVT::ValueType slotVT =
3296 (Node->getOpcode() == ISD::FP_EXTEND) ? oldVT : newVT;
3297 const Type *Ty = MVT::getTypeForValueType(slotVT);
3298 uint64_t TySize = TLI.getTargetData()->getTypeSize(Ty);
3299 unsigned Align = TLI.getTargetData()->getPrefTypeAlignment(Ty);
3300 MachineFunction &MF = DAG.getMachineFunction();
3302 MF.getFrameInfo()->CreateStackObject(TySize, Align);
3303 SDOperand StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy());
3304 if (Node->getOpcode() == ISD::FP_EXTEND) {
3305 Result = DAG.getStore(DAG.getEntryNode(), Node->getOperand(0),
3306 StackSlot, NULL, 0);
3307 Result = DAG.getExtLoad(ISD::EXTLOAD, newVT,
3308 Result, StackSlot, NULL, 0, oldVT);
3310 Result = DAG.getTruncStore(DAG.getEntryNode(), Node->getOperand(0),
3311 StackSlot, NULL, 0, newVT);
3312 Result = DAG.getLoad(newVT, Result, StackSlot, NULL, 0, newVT);
3318 case ISD::ANY_EXTEND:
3319 case ISD::ZERO_EXTEND:
3320 case ISD::SIGN_EXTEND:
3321 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3322 case Expand: assert(0 && "Shouldn't need to expand other operators here!");
3324 Tmp1 = LegalizeOp(Node->getOperand(0));
3325 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3328 switch (Node->getOpcode()) {
3329 case ISD::ANY_EXTEND:
3330 Tmp1 = PromoteOp(Node->getOperand(0));
3331 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Tmp1);
3333 case ISD::ZERO_EXTEND:
3334 Result = PromoteOp(Node->getOperand(0));
3335 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Result);
3336 Result = DAG.getZeroExtendInReg(Result,
3337 Node->getOperand(0).getValueType());
3339 case ISD::SIGN_EXTEND:
3340 Result = PromoteOp(Node->getOperand(0));
3341 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Result);
3342 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(),
3344 DAG.getValueType(Node->getOperand(0).getValueType()));
3346 case ISD::FP_EXTEND:
3347 Result = PromoteOp(Node->getOperand(0));
3348 if (Result.getValueType() != Op.getValueType())
3349 // Dynamically dead while we have only 2 FP types.
3350 Result = DAG.getNode(ISD::FP_EXTEND, Op.getValueType(), Result);
3353 Result = PromoteOp(Node->getOperand(0));
3354 Result = DAG.getNode(Node->getOpcode(), Op.getValueType(), Result);
3359 case ISD::FP_ROUND_INREG:
3360 case ISD::SIGN_EXTEND_INREG: {
3361 Tmp1 = LegalizeOp(Node->getOperand(0));
3362 MVT::ValueType ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT();
3364 // If this operation is not supported, convert it to a shl/shr or load/store
3366 switch (TLI.getOperationAction(Node->getOpcode(), ExtraVT)) {
3367 default: assert(0 && "This action not supported for this op yet!");
3368 case TargetLowering::Legal:
3369 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
3371 case TargetLowering::Expand:
3372 // If this is an integer extend and shifts are supported, do that.
3373 if (Node->getOpcode() == ISD::SIGN_EXTEND_INREG) {
3374 // NOTE: we could fall back on load/store here too for targets without
3375 // SAR. However, it is doubtful that any exist.
3376 unsigned BitsDiff = MVT::getSizeInBits(Node->getValueType(0)) -
3377 MVT::getSizeInBits(ExtraVT);
3378 SDOperand ShiftCst = DAG.getConstant(BitsDiff, TLI.getShiftAmountTy());
3379 Result = DAG.getNode(ISD::SHL, Node->getValueType(0),
3380 Node->getOperand(0), ShiftCst);
3381 Result = DAG.getNode(ISD::SRA, Node->getValueType(0),
3383 } else if (Node->getOpcode() == ISD::FP_ROUND_INREG) {
3384 // The only way we can lower this is to turn it into a TRUNCSTORE,
3385 // EXTLOAD pair, targetting a temporary location (a stack slot).
3387 // NOTE: there is a choice here between constantly creating new stack
3388 // slots and always reusing the same one. We currently always create
3389 // new ones, as reuse may inhibit scheduling.
3390 const Type *Ty = MVT::getTypeForValueType(ExtraVT);
3391 uint64_t TySize = TLI.getTargetData()->getTypeSize(Ty);
3392 unsigned Align = TLI.getTargetData()->getPrefTypeAlignment(Ty);
3393 MachineFunction &MF = DAG.getMachineFunction();
3395 MF.getFrameInfo()->CreateStackObject(TySize, Align);
3396 SDOperand StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy());
3397 Result = DAG.getTruncStore(DAG.getEntryNode(), Node->getOperand(0),
3398 StackSlot, NULL, 0, ExtraVT);
3399 Result = DAG.getExtLoad(ISD::EXTLOAD, Node->getValueType(0),
3400 Result, StackSlot, NULL, 0, ExtraVT);
3402 assert(0 && "Unknown op");
3408 case ISD::TRAMPOLINE: {
3410 for (unsigned i = 0; i != 6; ++i)
3411 Ops[i] = LegalizeOp(Node->getOperand(i));
3412 Result = DAG.UpdateNodeOperands(Result, Ops, 6);
3413 // The only option for this node is to custom lower it.
3414 Result = TLI.LowerOperation(Result, DAG);
3415 assert(Result.Val && "Should always custom lower!");
3417 // Since trampoline produces two values, make sure to remember that we
3418 // legalized both of them.
3419 Tmp1 = LegalizeOp(Result.getValue(1));
3420 Result = LegalizeOp(Result);
3421 AddLegalizedOperand(SDOperand(Node, 0), Result);
3422 AddLegalizedOperand(SDOperand(Node, 1), Tmp1);
3423 return Op.ResNo ? Tmp1 : Result;
3427 assert(Result.getValueType() == Op.getValueType() &&
3428 "Bad legalization!");
3430 // Make sure that the generated code is itself legal.
3432 Result = LegalizeOp(Result);
3434 // Note that LegalizeOp may be reentered even from single-use nodes, which
3435 // means that we always must cache transformed nodes.
3436 AddLegalizedOperand(Op, Result);
3440 /// PromoteOp - Given an operation that produces a value in an invalid type,
3441 /// promote it to compute the value into a larger type. The produced value will
3442 /// have the correct bits for the low portion of the register, but no guarantee
3443 /// is made about the top bits: it may be zero, sign-extended, or garbage.
3444 SDOperand SelectionDAGLegalize::PromoteOp(SDOperand Op) {
3445 MVT::ValueType VT = Op.getValueType();
3446 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT);
3447 assert(getTypeAction(VT) == Promote &&
3448 "Caller should expand or legalize operands that are not promotable!");
3449 assert(NVT > VT && MVT::isInteger(NVT) == MVT::isInteger(VT) &&
3450 "Cannot promote to smaller type!");
3452 SDOperand Tmp1, Tmp2, Tmp3;
3454 SDNode *Node = Op.Val;
3456 DenseMap<SDOperand, SDOperand>::iterator I = PromotedNodes.find(Op);
3457 if (I != PromotedNodes.end()) return I->second;
3459 switch (Node->getOpcode()) {
3460 case ISD::CopyFromReg:
3461 assert(0 && "CopyFromReg must be legal!");
3464 cerr << "NODE: "; Node->dump(&DAG); cerr << "\n";
3466 assert(0 && "Do not know how to promote this operator!");
3469 Result = DAG.getNode(ISD::UNDEF, NVT);
3473 Result = DAG.getNode(ISD::SIGN_EXTEND, NVT, Op);
3475 Result = DAG.getNode(ISD::ZERO_EXTEND, NVT, Op);
3476 assert(isa<ConstantSDNode>(Result) && "Didn't constant fold zext?");
3478 case ISD::ConstantFP:
3479 Result = DAG.getNode(ISD::FP_EXTEND, NVT, Op);
3480 assert(isa<ConstantFPSDNode>(Result) && "Didn't constant fold fp_extend?");
3484 assert(isTypeLegal(TLI.getSetCCResultTy()) && "SetCC type is not legal??");
3485 Result = DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(),Node->getOperand(0),
3486 Node->getOperand(1), Node->getOperand(2));
3490 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3492 Result = LegalizeOp(Node->getOperand(0));
3493 assert(Result.getValueType() >= NVT &&
3494 "This truncation doesn't make sense!");
3495 if (Result.getValueType() > NVT) // Truncate to NVT instead of VT
3496 Result = DAG.getNode(ISD::TRUNCATE, NVT, Result);
3499 // The truncation is not required, because we don't guarantee anything
3500 // about high bits anyway.
3501 Result = PromoteOp(Node->getOperand(0));
3504 ExpandOp(Node->getOperand(0), Tmp1, Tmp2);
3505 // Truncate the low part of the expanded value to the result type
3506 Result = DAG.getNode(ISD::TRUNCATE, NVT, Tmp1);
3509 case ISD::SIGN_EXTEND:
3510 case ISD::ZERO_EXTEND:
3511 case ISD::ANY_EXTEND:
3512 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3513 case Expand: assert(0 && "BUG: Smaller reg should have been promoted!");
3515 // Input is legal? Just do extend all the way to the larger type.
3516 Result = DAG.getNode(Node->getOpcode(), NVT, Node->getOperand(0));
3519 // Promote the reg if it's smaller.
3520 Result = PromoteOp(Node->getOperand(0));
3521 // The high bits are not guaranteed to be anything. Insert an extend.
3522 if (Node->getOpcode() == ISD::SIGN_EXTEND)
3523 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Result,
3524 DAG.getValueType(Node->getOperand(0).getValueType()));
3525 else if (Node->getOpcode() == ISD::ZERO_EXTEND)
3526 Result = DAG.getZeroExtendInReg(Result,
3527 Node->getOperand(0).getValueType());
3531 case ISD::BIT_CONVERT:
3532 Result = ExpandBIT_CONVERT(Node->getValueType(0), Node->getOperand(0));
3533 Result = PromoteOp(Result);
3536 case ISD::FP_EXTEND:
3537 assert(0 && "Case not implemented. Dynamically dead with 2 FP types!");
3539 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3540 case Expand: assert(0 && "BUG: Cannot expand FP regs!");
3541 case Promote: assert(0 && "Unreachable with 2 FP types!");
3543 // Input is legal? Do an FP_ROUND_INREG.
3544 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Node->getOperand(0),
3545 DAG.getValueType(VT));
3550 case ISD::SINT_TO_FP:
3551 case ISD::UINT_TO_FP:
3552 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3554 // No extra round required here.
3555 Result = DAG.getNode(Node->getOpcode(), NVT, Node->getOperand(0));
3559 Result = PromoteOp(Node->getOperand(0));
3560 if (Node->getOpcode() == ISD::SINT_TO_FP)
3561 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(),
3563 DAG.getValueType(Node->getOperand(0).getValueType()));
3565 Result = DAG.getZeroExtendInReg(Result,
3566 Node->getOperand(0).getValueType());
3567 // No extra round required here.
3568 Result = DAG.getNode(Node->getOpcode(), NVT, Result);
3571 Result = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP, NVT,
3572 Node->getOperand(0));
3573 // Round if we cannot tolerate excess precision.
3574 if (NoExcessFPPrecision)
3575 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
3576 DAG.getValueType(VT));
3581 case ISD::SIGN_EXTEND_INREG:
3582 Result = PromoteOp(Node->getOperand(0));
3583 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Result,
3584 Node->getOperand(1));
3586 case ISD::FP_TO_SINT:
3587 case ISD::FP_TO_UINT:
3588 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3591 Tmp1 = Node->getOperand(0);
3594 // The input result is prerounded, so we don't have to do anything
3596 Tmp1 = PromoteOp(Node->getOperand(0));
3599 // If we're promoting a UINT to a larger size, check to see if the new node
3600 // will be legal. If it isn't, check to see if FP_TO_SINT is legal, since
3601 // we can use that instead. This allows us to generate better code for
3602 // FP_TO_UINT for small destination sizes on targets where FP_TO_UINT is not
3603 // legal, such as PowerPC.
3604 if (Node->getOpcode() == ISD::FP_TO_UINT &&
3605 !TLI.isOperationLegal(ISD::FP_TO_UINT, NVT) &&
3606 (TLI.isOperationLegal(ISD::FP_TO_SINT, NVT) ||
3607 TLI.getOperationAction(ISD::FP_TO_SINT, NVT)==TargetLowering::Custom)){
3608 Result = DAG.getNode(ISD::FP_TO_SINT, NVT, Tmp1);
3610 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
3616 Tmp1 = PromoteOp(Node->getOperand(0));
3617 assert(Tmp1.getValueType() == NVT);
3618 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
3619 // NOTE: we do not have to do any extra rounding here for
3620 // NoExcessFPPrecision, because we know the input will have the appropriate
3621 // precision, and these operations don't modify precision at all.
3627 Tmp1 = PromoteOp(Node->getOperand(0));
3628 assert(Tmp1.getValueType() == NVT);
3629 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
3630 if (NoExcessFPPrecision)
3631 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
3632 DAG.getValueType(VT));
3636 // Promote f32 powi to f64 powi. Note that this could insert a libcall
3637 // directly as well, which may be better.
3638 Tmp1 = PromoteOp(Node->getOperand(0));
3639 assert(Tmp1.getValueType() == NVT);
3640 Result = DAG.getNode(ISD::FPOWI, NVT, Tmp1, Node->getOperand(1));
3641 if (NoExcessFPPrecision)
3642 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
3643 DAG.getValueType(VT));
3653 // The input may have strange things in the top bits of the registers, but
3654 // these operations don't care. They may have weird bits going out, but
3655 // that too is okay if they are integer operations.
3656 Tmp1 = PromoteOp(Node->getOperand(0));
3657 Tmp2 = PromoteOp(Node->getOperand(1));
3658 assert(Tmp1.getValueType() == NVT && Tmp2.getValueType() == NVT);
3659 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
3664 Tmp1 = PromoteOp(Node->getOperand(0));
3665 Tmp2 = PromoteOp(Node->getOperand(1));
3666 assert(Tmp1.getValueType() == NVT && Tmp2.getValueType() == NVT);
3667 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
3669 // Floating point operations will give excess precision that we may not be
3670 // able to tolerate. If we DO allow excess precision, just leave it,
3671 // otherwise excise it.
3672 // FIXME: Why would we need to round FP ops more than integer ones?
3673 // Is Round(Add(Add(A,B),C)) != Round(Add(Round(Add(A,B)), C))
3674 if (NoExcessFPPrecision)
3675 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
3676 DAG.getValueType(VT));
3681 // These operators require that their input be sign extended.
3682 Tmp1 = PromoteOp(Node->getOperand(0));
3683 Tmp2 = PromoteOp(Node->getOperand(1));
3684 if (MVT::isInteger(NVT)) {
3685 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1,
3686 DAG.getValueType(VT));
3687 Tmp2 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp2,
3688 DAG.getValueType(VT));
3690 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
3692 // Perform FP_ROUND: this is probably overly pessimistic.
3693 if (MVT::isFloatingPoint(NVT) && NoExcessFPPrecision)
3694 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
3695 DAG.getValueType(VT));
3699 case ISD::FCOPYSIGN:
3700 // These operators require that their input be fp extended.
3701 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3703 Tmp1 = LegalizeOp(Node->getOperand(0));
3706 Tmp1 = PromoteOp(Node->getOperand(0));
3709 assert(0 && "not implemented");
3711 switch (getTypeAction(Node->getOperand(1).getValueType())) {
3713 Tmp2 = LegalizeOp(Node->getOperand(1));
3716 Tmp2 = PromoteOp(Node->getOperand(1));
3719 assert(0 && "not implemented");
3721 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
3723 // Perform FP_ROUND: this is probably overly pessimistic.
3724 if (NoExcessFPPrecision && Node->getOpcode() != ISD::FCOPYSIGN)
3725 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
3726 DAG.getValueType(VT));
3731 // These operators require that their input be zero extended.
3732 Tmp1 = PromoteOp(Node->getOperand(0));
3733 Tmp2 = PromoteOp(Node->getOperand(1));
3734 assert(MVT::isInteger(NVT) && "Operators don't apply to FP!");
3735 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT);
3736 Tmp2 = DAG.getZeroExtendInReg(Tmp2, VT);
3737 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
3741 Tmp1 = PromoteOp(Node->getOperand(0));
3742 Result = DAG.getNode(ISD::SHL, NVT, Tmp1, Node->getOperand(1));
3745 // The input value must be properly sign extended.
3746 Tmp1 = PromoteOp(Node->getOperand(0));
3747 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1,
3748 DAG.getValueType(VT));
3749 Result = DAG.getNode(ISD::SRA, NVT, Tmp1, Node->getOperand(1));
3752 // The input value must be properly zero extended.
3753 Tmp1 = PromoteOp(Node->getOperand(0));
3754 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT);
3755 Result = DAG.getNode(ISD::SRL, NVT, Tmp1, Node->getOperand(1));
3759 Tmp1 = Node->getOperand(0); // Get the chain.
3760 Tmp2 = Node->getOperand(1); // Get the pointer.
3761 if (TLI.getOperationAction(ISD::VAARG, VT) == TargetLowering::Custom) {
3762 Tmp3 = DAG.getVAArg(VT, Tmp1, Tmp2, Node->getOperand(2));
3763 Result = TLI.CustomPromoteOperation(Tmp3, DAG);
3765 SrcValueSDNode *SV = cast<SrcValueSDNode>(Node->getOperand(2));
3766 SDOperand VAList = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp2,
3767 SV->getValue(), SV->getOffset());
3768 // Increment the pointer, VAList, to the next vaarg
3769 Tmp3 = DAG.getNode(ISD::ADD, TLI.getPointerTy(), VAList,
3770 DAG.getConstant(MVT::getSizeInBits(VT)/8,
3771 TLI.getPointerTy()));
3772 // Store the incremented VAList to the legalized pointer
3773 Tmp3 = DAG.getStore(VAList.getValue(1), Tmp3, Tmp2, SV->getValue(),
3775 // Load the actual argument out of the pointer VAList
3776 Result = DAG.getExtLoad(ISD::EXTLOAD, NVT, Tmp3, VAList, NULL, 0, VT);
3778 // Remember that we legalized the chain.
3779 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
3783 LoadSDNode *LD = cast<LoadSDNode>(Node);
3784 ISD::LoadExtType ExtType = ISD::isNON_EXTLoad(Node)
3785 ? ISD::EXTLOAD : LD->getExtensionType();
3786 Result = DAG.getExtLoad(ExtType, NVT,
3787 LD->getChain(), LD->getBasePtr(),
3788 LD->getSrcValue(), LD->getSrcValueOffset(),
3791 LD->getAlignment());
3792 // Remember that we legalized the chain.
3793 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
3797 Tmp2 = PromoteOp(Node->getOperand(1)); // Legalize the op0
3798 Tmp3 = PromoteOp(Node->getOperand(2)); // Legalize the op1
3799 Result = DAG.getNode(ISD::SELECT, NVT, Node->getOperand(0), Tmp2, Tmp3);
3801 case ISD::SELECT_CC:
3802 Tmp2 = PromoteOp(Node->getOperand(2)); // True
3803 Tmp3 = PromoteOp(Node->getOperand(3)); // False
3804 Result = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0),
3805 Node->getOperand(1), Tmp2, Tmp3, Node->getOperand(4));
3808 Tmp1 = Node->getOperand(0);
3809 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1);
3810 Tmp1 = DAG.getNode(ISD::BSWAP, NVT, Tmp1);
3811 Result = DAG.getNode(ISD::SRL, NVT, Tmp1,
3812 DAG.getConstant(MVT::getSizeInBits(NVT) -
3813 MVT::getSizeInBits(VT),
3814 TLI.getShiftAmountTy()));
3819 // Zero extend the argument
3820 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Node->getOperand(0));
3821 // Perform the larger operation, then subtract if needed.
3822 Tmp1 = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
3823 switch(Node->getOpcode()) {
3828 // if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT)
3829 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), Tmp1,
3830 DAG.getConstant(MVT::getSizeInBits(NVT), NVT),
3832 Result = DAG.getNode(ISD::SELECT, NVT, Tmp2,
3833 DAG.getConstant(MVT::getSizeInBits(VT), NVT), Tmp1);
3836 //Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT))
3837 Result = DAG.getNode(ISD::SUB, NVT, Tmp1,
3838 DAG.getConstant(MVT::getSizeInBits(NVT) -
3839 MVT::getSizeInBits(VT), NVT));
3843 case ISD::EXTRACT_SUBVECTOR:
3844 Result = PromoteOp(ExpandEXTRACT_SUBVECTOR(Op));
3846 case ISD::EXTRACT_VECTOR_ELT:
3847 Result = PromoteOp(ExpandEXTRACT_VECTOR_ELT(Op));
3851 assert(Result.Val && "Didn't set a result!");
3853 // Make sure the result is itself legal.
3854 Result = LegalizeOp(Result);
3856 // Remember that we promoted this!
3857 AddPromotedOperand(Op, Result);
3861 /// ExpandEXTRACT_VECTOR_ELT - Expand an EXTRACT_VECTOR_ELT operation into
3862 /// a legal EXTRACT_VECTOR_ELT operation, scalar code, or memory traffic,
3863 /// based on the vector type. The return type of this matches the element type
3864 /// of the vector, which may not be legal for the target.
3865 SDOperand SelectionDAGLegalize::ExpandEXTRACT_VECTOR_ELT(SDOperand Op) {
3866 // We know that operand #0 is the Vec vector. If the index is a constant
3867 // or if the invec is a supported hardware type, we can use it. Otherwise,
3868 // lower to a store then an indexed load.
3869 SDOperand Vec = Op.getOperand(0);
3870 SDOperand Idx = Op.getOperand(1);
3872 SDNode *InVal = Vec.Val;
3873 MVT::ValueType TVT = InVal->getValueType(0);
3874 unsigned NumElems = MVT::getVectorNumElements(TVT);
3876 switch (TLI.getOperationAction(ISD::EXTRACT_VECTOR_ELT, TVT)) {
3877 default: assert(0 && "This action is not supported yet!");
3878 case TargetLowering::Custom: {
3879 Vec = LegalizeOp(Vec);
3880 Op = DAG.UpdateNodeOperands(Op, Vec, Idx);
3881 SDOperand Tmp3 = TLI.LowerOperation(Op, DAG);
3886 case TargetLowering::Legal:
3887 if (isTypeLegal(TVT)) {
3888 Vec = LegalizeOp(Vec);
3889 Op = DAG.UpdateNodeOperands(Op, Vec, Idx);
3893 case TargetLowering::Expand:
3897 if (NumElems == 1) {
3898 // This must be an access of the only element. Return it.
3899 Op = ScalarizeVectorOp(Vec);
3900 } else if (!TLI.isTypeLegal(TVT) && isa<ConstantSDNode>(Idx)) {
3901 ConstantSDNode *CIdx = cast<ConstantSDNode>(Idx);
3903 SplitVectorOp(Vec, Lo, Hi);
3904 if (CIdx->getValue() < NumElems/2) {
3908 Idx = DAG.getConstant(CIdx->getValue() - NumElems/2,
3909 Idx.getValueType());
3912 // It's now an extract from the appropriate high or low part. Recurse.
3913 Op = DAG.UpdateNodeOperands(Op, Vec, Idx);
3914 Op = ExpandEXTRACT_VECTOR_ELT(Op);
3916 // Store the value to a temporary stack slot, then LOAD the scalar
3917 // element back out.
3918 SDOperand StackPtr = CreateStackTemporary(Vec.getValueType());
3919 SDOperand Ch = DAG.getStore(DAG.getEntryNode(), Vec, StackPtr, NULL, 0);
3921 // Add the offset to the index.
3922 unsigned EltSize = MVT::getSizeInBits(Op.getValueType())/8;
3923 Idx = DAG.getNode(ISD::MUL, Idx.getValueType(), Idx,
3924 DAG.getConstant(EltSize, Idx.getValueType()));
3925 StackPtr = DAG.getNode(ISD::ADD, Idx.getValueType(), Idx, StackPtr);
3927 Op = DAG.getLoad(Op.getValueType(), Ch, StackPtr, NULL, 0);
3932 /// ExpandEXTRACT_SUBVECTOR - Expand a EXTRACT_SUBVECTOR operation. For now
3933 /// we assume the operation can be split if it is not already legal.
3934 SDOperand SelectionDAGLegalize::ExpandEXTRACT_SUBVECTOR(SDOperand Op) {
3935 // We know that operand #0 is the Vec vector. For now we assume the index
3936 // is a constant and that the extracted result is a supported hardware type.
3937 SDOperand Vec = Op.getOperand(0);
3938 SDOperand Idx = LegalizeOp(Op.getOperand(1));
3940 unsigned NumElems = MVT::getVectorNumElements(Vec.getValueType());
3942 if (NumElems == MVT::getVectorNumElements(Op.getValueType())) {
3943 // This must be an access of the desired vector length. Return it.
3947 ConstantSDNode *CIdx = cast<ConstantSDNode>(Idx);
3949 SplitVectorOp(Vec, Lo, Hi);
3950 if (CIdx->getValue() < NumElems/2) {
3954 Idx = DAG.getConstant(CIdx->getValue() - NumElems/2, Idx.getValueType());
3957 // It's now an extract from the appropriate high or low part. Recurse.
3958 Op = DAG.UpdateNodeOperands(Op, Vec, Idx);
3959 return ExpandEXTRACT_SUBVECTOR(Op);
3962 /// LegalizeSetCCOperands - Attempts to create a legal LHS and RHS for a SETCC
3963 /// with condition CC on the current target. This usually involves legalizing
3964 /// or promoting the arguments. In the case where LHS and RHS must be expanded,
3965 /// there may be no choice but to create a new SetCC node to represent the
3966 /// legalized value of setcc lhs, rhs. In this case, the value is returned in
3967 /// LHS, and the SDOperand returned in RHS has a nil SDNode value.
3968 void SelectionDAGLegalize::LegalizeSetCCOperands(SDOperand &LHS,
3971 SDOperand Tmp1, Tmp2, Result;
3973 switch (getTypeAction(LHS.getValueType())) {
3975 Tmp1 = LegalizeOp(LHS); // LHS
3976 Tmp2 = LegalizeOp(RHS); // RHS
3979 Tmp1 = PromoteOp(LHS); // LHS
3980 Tmp2 = PromoteOp(RHS); // RHS
3982 // If this is an FP compare, the operands have already been extended.
3983 if (MVT::isInteger(LHS.getValueType())) {
3984 MVT::ValueType VT = LHS.getValueType();
3985 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT);
3987 // Otherwise, we have to insert explicit sign or zero extends. Note
3988 // that we could insert sign extends for ALL conditions, but zero extend
3989 // is cheaper on many machines (an AND instead of two shifts), so prefer
3991 switch (cast<CondCodeSDNode>(CC)->get()) {
3992 default: assert(0 && "Unknown integer comparison!");
3999 // ALL of these operations will work if we either sign or zero extend
4000 // the operands (including the unsigned comparisons!). Zero extend is
4001 // usually a simpler/cheaper operation, so prefer it.
4002 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT);
4003 Tmp2 = DAG.getZeroExtendInReg(Tmp2, VT);
4009 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1,
4010 DAG.getValueType(VT));
4011 Tmp2 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp2,
4012 DAG.getValueType(VT));
4018 MVT::ValueType VT = LHS.getValueType();
4019 if (VT == MVT::f32 || VT == MVT::f64) {
4020 // Expand into one or more soft-fp libcall(s).
4021 RTLIB::Libcall LC1, LC2 = RTLIB::UNKNOWN_LIBCALL;
4022 switch (cast<CondCodeSDNode>(CC)->get()) {
4025 LC1 = (VT == MVT::f32) ? RTLIB::OEQ_F32 : RTLIB::OEQ_F64;
4029 LC1 = (VT == MVT::f32) ? RTLIB::UNE_F32 : RTLIB::UNE_F64;
4033 LC1 = (VT == MVT::f32) ? RTLIB::OGE_F32 : RTLIB::OGE_F64;
4037 LC1 = (VT == MVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64;
4041 LC1 = (VT == MVT::f32) ? RTLIB::OLE_F32 : RTLIB::OLE_F64;
4045 LC1 = (VT == MVT::f32) ? RTLIB::OGT_F32 : RTLIB::OGT_F64;
4048 LC1 = (VT == MVT::f32) ? RTLIB::UO_F32 : RTLIB::UO_F64;
4051 LC1 = (VT == MVT::f32) ? RTLIB::O_F32 : RTLIB::O_F64;
4054 LC1 = (VT == MVT::f32) ? RTLIB::UO_F32 : RTLIB::UO_F64;
4055 switch (cast<CondCodeSDNode>(CC)->get()) {
4057 // SETONE = SETOLT | SETOGT
4058 LC1 = (VT == MVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64;
4061 LC2 = (VT == MVT::f32) ? RTLIB::OGT_F32 : RTLIB::OGT_F64;
4064 LC2 = (VT == MVT::f32) ? RTLIB::OGE_F32 : RTLIB::OGE_F64;
4067 LC2 = (VT == MVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64;
4070 LC2 = (VT == MVT::f32) ? RTLIB::OLE_F32 : RTLIB::OLE_F64;
4073 LC2 = (VT == MVT::f32) ? RTLIB::OEQ_F32 : RTLIB::OEQ_F64;
4075 default: assert(0 && "Unsupported FP setcc!");
4080 Tmp1 = ExpandLibCall(TLI.getLibcallName(LC1),
4081 DAG.getNode(ISD::MERGE_VALUES, VT, LHS, RHS).Val,
4082 false /*sign irrelevant*/, Dummy);
4083 Tmp2 = DAG.getConstant(0, MVT::i32);
4084 CC = DAG.getCondCode(TLI.getCmpLibcallCC(LC1));
4085 if (LC2 != RTLIB::UNKNOWN_LIBCALL) {
4086 Tmp1 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(), Tmp1, Tmp2, CC);
4087 LHS = ExpandLibCall(TLI.getLibcallName(LC2),
4088 DAG.getNode(ISD::MERGE_VALUES, VT, LHS, RHS).Val,
4089 false /*sign irrelevant*/, Dummy);
4090 Tmp2 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(), LHS, Tmp2,
4091 DAG.getCondCode(TLI.getCmpLibcallCC(LC2)));
4092 Tmp1 = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp2);
4100 SDOperand LHSLo, LHSHi, RHSLo, RHSHi;
4101 ExpandOp(LHS, LHSLo, LHSHi);
4102 ExpandOp(RHS, RHSLo, RHSHi);
4103 switch (cast<CondCodeSDNode>(CC)->get()) {
4107 if (ConstantSDNode *RHSCST = dyn_cast<ConstantSDNode>(RHSLo))
4108 if (RHSCST->isAllOnesValue()) {
4109 // Comparison to -1.
4110 Tmp1 = DAG.getNode(ISD::AND, LHSLo.getValueType(), LHSLo, LHSHi);
4115 Tmp1 = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSLo, RHSLo);
4116 Tmp2 = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSHi, RHSHi);
4117 Tmp1 = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp2);
4118 Tmp2 = DAG.getConstant(0, Tmp1.getValueType());
4121 // If this is a comparison of the sign bit, just look at the top part.
4123 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(RHS))
4124 if ((cast<CondCodeSDNode>(CC)->get() == ISD::SETLT &&
4125 CST->getValue() == 0) || // X < 0
4126 (cast<CondCodeSDNode>(CC)->get() == ISD::SETGT &&
4127 CST->isAllOnesValue())) { // X > -1
4133 // FIXME: This generated code sucks.
4134 ISD::CondCode LowCC;
4135 ISD::CondCode CCCode = cast<CondCodeSDNode>(CC)->get();
4137 default: assert(0 && "Unknown integer setcc!");
4139 case ISD::SETULT: LowCC = ISD::SETULT; break;
4141 case ISD::SETUGT: LowCC = ISD::SETUGT; break;
4143 case ISD::SETULE: LowCC = ISD::SETULE; break;
4145 case ISD::SETUGE: LowCC = ISD::SETUGE; break;
4148 // Tmp1 = lo(op1) < lo(op2) // Always unsigned comparison
4149 // Tmp2 = hi(op1) < hi(op2) // Signedness depends on operands
4150 // dest = hi(op1) == hi(op2) ? Tmp1 : Tmp2;
4152 // NOTE: on targets without efficient SELECT of bools, we can always use
4153 // this identity: (B1 ? B2 : B3) --> (B1 & B2)|(!B1&B3)
4154 TargetLowering::DAGCombinerInfo DagCombineInfo(DAG, false, true, NULL);
4155 Tmp1 = TLI.SimplifySetCC(TLI.getSetCCResultTy(), LHSLo, RHSLo, LowCC,
4156 false, DagCombineInfo);
4158 Tmp1 = DAG.getSetCC(TLI.getSetCCResultTy(), LHSLo, RHSLo, LowCC);
4159 Tmp2 = TLI.SimplifySetCC(TLI.getSetCCResultTy(), LHSHi, RHSHi,
4160 CCCode, false, DagCombineInfo);
4162 Tmp2 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(), LHSHi, RHSHi, CC);
4164 ConstantSDNode *Tmp1C = dyn_cast<ConstantSDNode>(Tmp1.Val);
4165 ConstantSDNode *Tmp2C = dyn_cast<ConstantSDNode>(Tmp2.Val);
4166 if ((Tmp1C && Tmp1C->getValue() == 0) ||
4167 (Tmp2C && Tmp2C->getValue() == 0 &&
4168 (CCCode == ISD::SETLE || CCCode == ISD::SETGE ||
4169 CCCode == ISD::SETUGE || CCCode == ISD::SETULE)) ||
4170 (Tmp2C && Tmp2C->getValue() == 1 &&
4171 (CCCode == ISD::SETLT || CCCode == ISD::SETGT ||
4172 CCCode == ISD::SETUGT || CCCode == ISD::SETULT))) {
4173 // low part is known false, returns high part.
4174 // For LE / GE, if high part is known false, ignore the low part.
4175 // For LT / GT, if high part is known true, ignore the low part.
4179 Result = TLI.SimplifySetCC(TLI.getSetCCResultTy(), LHSHi, RHSHi,
4180 ISD::SETEQ, false, DagCombineInfo);
4182 Result=DAG.getSetCC(TLI.getSetCCResultTy(), LHSHi, RHSHi, ISD::SETEQ);
4183 Result = LegalizeOp(DAG.getNode(ISD::SELECT, Tmp1.getValueType(),
4184 Result, Tmp1, Tmp2));
4195 /// ExpandBIT_CONVERT - Expand a BIT_CONVERT node into a store/load combination.
4196 /// The resultant code need not be legal. Note that SrcOp is the input operand
4197 /// to the BIT_CONVERT, not the BIT_CONVERT node itself.
4198 SDOperand SelectionDAGLegalize::ExpandBIT_CONVERT(MVT::ValueType DestVT,
4200 // Create the stack frame object.
4201 SDOperand FIPtr = CreateStackTemporary(DestVT);
4203 // Emit a store to the stack slot.
4204 SDOperand Store = DAG.getStore(DAG.getEntryNode(), SrcOp, FIPtr, NULL, 0);
4205 // Result is a load from the stack slot.
4206 return DAG.getLoad(DestVT, Store, FIPtr, NULL, 0);
4209 SDOperand SelectionDAGLegalize::ExpandSCALAR_TO_VECTOR(SDNode *Node) {
4210 // Create a vector sized/aligned stack slot, store the value to element #0,
4211 // then load the whole vector back out.
4212 SDOperand StackPtr = CreateStackTemporary(Node->getValueType(0));
4213 SDOperand Ch = DAG.getStore(DAG.getEntryNode(), Node->getOperand(0), StackPtr,
4215 return DAG.getLoad(Node->getValueType(0), Ch, StackPtr, NULL, 0);
4219 /// ExpandBUILD_VECTOR - Expand a BUILD_VECTOR node on targets that don't
4220 /// support the operation, but do support the resultant vector type.
4221 SDOperand SelectionDAGLegalize::ExpandBUILD_VECTOR(SDNode *Node) {
4223 // If the only non-undef value is the low element, turn this into a
4224 // SCALAR_TO_VECTOR node. If this is { X, X, X, X }, determine X.
4225 unsigned NumElems = Node->getNumOperands();
4226 bool isOnlyLowElement = true;
4227 SDOperand SplatValue = Node->getOperand(0);
4228 std::map<SDOperand, std::vector<unsigned> > Values;
4229 Values[SplatValue].push_back(0);
4230 bool isConstant = true;
4231 if (!isa<ConstantFPSDNode>(SplatValue) && !isa<ConstantSDNode>(SplatValue) &&
4232 SplatValue.getOpcode() != ISD::UNDEF)
4235 for (unsigned i = 1; i < NumElems; ++i) {
4236 SDOperand V = Node->getOperand(i);
4237 Values[V].push_back(i);
4238 if (V.getOpcode() != ISD::UNDEF)
4239 isOnlyLowElement = false;
4240 if (SplatValue != V)
4241 SplatValue = SDOperand(0,0);
4243 // If this isn't a constant element or an undef, we can't use a constant
4245 if (!isa<ConstantFPSDNode>(V) && !isa<ConstantSDNode>(V) &&
4246 V.getOpcode() != ISD::UNDEF)
4250 if (isOnlyLowElement) {
4251 // If the low element is an undef too, then this whole things is an undef.
4252 if (Node->getOperand(0).getOpcode() == ISD::UNDEF)
4253 return DAG.getNode(ISD::UNDEF, Node->getValueType(0));
4254 // Otherwise, turn this into a scalar_to_vector node.
4255 return DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0),
4256 Node->getOperand(0));
4259 // If all elements are constants, create a load from the constant pool.
4261 MVT::ValueType VT = Node->getValueType(0);
4263 MVT::getTypeForValueType(Node->getOperand(0).getValueType());
4264 std::vector<Constant*> CV;
4265 for (unsigned i = 0, e = NumElems; i != e; ++i) {
4266 if (ConstantFPSDNode *V =
4267 dyn_cast<ConstantFPSDNode>(Node->getOperand(i))) {
4268 CV.push_back(ConstantFP::get(OpNTy, V->getValueAPF()));
4269 } else if (ConstantSDNode *V =
4270 dyn_cast<ConstantSDNode>(Node->getOperand(i))) {
4271 CV.push_back(ConstantInt::get(OpNTy, V->getValue()));
4273 assert(Node->getOperand(i).getOpcode() == ISD::UNDEF);
4274 CV.push_back(UndefValue::get(OpNTy));
4277 Constant *CP = ConstantVector::get(CV);
4278 SDOperand CPIdx = DAG.getConstantPool(CP, TLI.getPointerTy());
4279 return DAG.getLoad(VT, DAG.getEntryNode(), CPIdx, NULL, 0);
4282 if (SplatValue.Val) { // Splat of one value?
4283 // Build the shuffle constant vector: <0, 0, 0, 0>
4284 MVT::ValueType MaskVT =
4285 MVT::getIntVectorWithNumElements(NumElems);
4286 SDOperand Zero = DAG.getConstant(0, MVT::getVectorElementType(MaskVT));
4287 std::vector<SDOperand> ZeroVec(NumElems, Zero);
4288 SDOperand SplatMask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
4289 &ZeroVec[0], ZeroVec.size());
4291 // If the target supports VECTOR_SHUFFLE and this shuffle mask, use it.
4292 if (isShuffleLegal(Node->getValueType(0), SplatMask)) {
4293 // Get the splatted value into the low element of a vector register.
4294 SDOperand LowValVec =
4295 DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0), SplatValue);
4297 // Return shuffle(LowValVec, undef, <0,0,0,0>)
4298 return DAG.getNode(ISD::VECTOR_SHUFFLE, Node->getValueType(0), LowValVec,
4299 DAG.getNode(ISD::UNDEF, Node->getValueType(0)),
4304 // If there are only two unique elements, we may be able to turn this into a
4306 if (Values.size() == 2) {
4307 // Build the shuffle constant vector: e.g. <0, 4, 0, 4>
4308 MVT::ValueType MaskVT =
4309 MVT::getIntVectorWithNumElements(NumElems);
4310 std::vector<SDOperand> MaskVec(NumElems);
4312 for (std::map<SDOperand,std::vector<unsigned> >::iterator I=Values.begin(),
4313 E = Values.end(); I != E; ++I) {
4314 for (std::vector<unsigned>::iterator II = I->second.begin(),
4315 EE = I->second.end(); II != EE; ++II)
4316 MaskVec[*II] = DAG.getConstant(i, MVT::getVectorElementType(MaskVT));
4319 SDOperand ShuffleMask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
4320 &MaskVec[0], MaskVec.size());
4322 // If the target supports VECTOR_SHUFFLE and this shuffle mask, use it.
4323 if (TLI.isOperationLegal(ISD::SCALAR_TO_VECTOR, Node->getValueType(0)) &&
4324 isShuffleLegal(Node->getValueType(0), ShuffleMask)) {
4325 SmallVector<SDOperand, 8> Ops;
4326 for(std::map<SDOperand,std::vector<unsigned> >::iterator I=Values.begin(),
4327 E = Values.end(); I != E; ++I) {
4328 SDOperand Op = DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0),
4332 Ops.push_back(ShuffleMask);
4334 // Return shuffle(LoValVec, HiValVec, <0,1,0,1>)
4335 return DAG.getNode(ISD::VECTOR_SHUFFLE, Node->getValueType(0),
4336 &Ops[0], Ops.size());
4340 // Otherwise, we can't handle this case efficiently. Allocate a sufficiently
4341 // aligned object on the stack, store each element into it, then load
4342 // the result as a vector.
4343 MVT::ValueType VT = Node->getValueType(0);
4344 // Create the stack frame object.
4345 SDOperand FIPtr = CreateStackTemporary(VT);
4347 // Emit a store of each element to the stack slot.
4348 SmallVector<SDOperand, 8> Stores;
4349 unsigned TypeByteSize =
4350 MVT::getSizeInBits(Node->getOperand(0).getValueType())/8;
4351 // Store (in the right endianness) the elements to memory.
4352 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
4353 // Ignore undef elements.
4354 if (Node->getOperand(i).getOpcode() == ISD::UNDEF) continue;
4356 unsigned Offset = TypeByteSize*i;
4358 SDOperand Idx = DAG.getConstant(Offset, FIPtr.getValueType());
4359 Idx = DAG.getNode(ISD::ADD, FIPtr.getValueType(), FIPtr, Idx);
4361 Stores.push_back(DAG.getStore(DAG.getEntryNode(), Node->getOperand(i), Idx,
4365 SDOperand StoreChain;
4366 if (!Stores.empty()) // Not all undef elements?
4367 StoreChain = DAG.getNode(ISD::TokenFactor, MVT::Other,
4368 &Stores[0], Stores.size());
4370 StoreChain = DAG.getEntryNode();
4372 // Result is a load from the stack slot.
4373 return DAG.getLoad(VT, StoreChain, FIPtr, NULL, 0);
4376 /// CreateStackTemporary - Create a stack temporary, suitable for holding the
4377 /// specified value type.
4378 SDOperand SelectionDAGLegalize::CreateStackTemporary(MVT::ValueType VT) {
4379 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo();
4380 unsigned ByteSize = MVT::getSizeInBits(VT)/8;
4381 const Type *Ty = MVT::getTypeForValueType(VT);
4382 unsigned StackAlign = (unsigned)TLI.getTargetData()->getPrefTypeAlignment(Ty);
4383 int FrameIdx = FrameInfo->CreateStackObject(ByteSize, StackAlign);
4384 return DAG.getFrameIndex(FrameIdx, TLI.getPointerTy());
4387 void SelectionDAGLegalize::ExpandShiftParts(unsigned NodeOp,
4388 SDOperand Op, SDOperand Amt,
4389 SDOperand &Lo, SDOperand &Hi) {
4390 // Expand the subcomponents.
4391 SDOperand LHSL, LHSH;
4392 ExpandOp(Op, LHSL, LHSH);
4394 SDOperand Ops[] = { LHSL, LHSH, Amt };
4395 MVT::ValueType VT = LHSL.getValueType();
4396 Lo = DAG.getNode(NodeOp, DAG.getNodeValueTypes(VT, VT), 2, Ops, 3);
4397 Hi = Lo.getValue(1);
4401 /// ExpandShift - Try to find a clever way to expand this shift operation out to
4402 /// smaller elements. If we can't find a way that is more efficient than a
4403 /// libcall on this target, return false. Otherwise, return true with the
4404 /// low-parts expanded into Lo and Hi.
4405 bool SelectionDAGLegalize::ExpandShift(unsigned Opc, SDOperand Op,SDOperand Amt,
4406 SDOperand &Lo, SDOperand &Hi) {
4407 assert((Opc == ISD::SHL || Opc == ISD::SRA || Opc == ISD::SRL) &&
4408 "This is not a shift!");
4410 MVT::ValueType NVT = TLI.getTypeToTransformTo(Op.getValueType());
4411 SDOperand ShAmt = LegalizeOp(Amt);
4412 MVT::ValueType ShTy = ShAmt.getValueType();
4413 unsigned VTBits = MVT::getSizeInBits(Op.getValueType());
4414 unsigned NVTBits = MVT::getSizeInBits(NVT);
4416 // Handle the case when Amt is an immediate. Other cases are currently broken
4417 // and are disabled.
4418 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Amt.Val)) {
4419 unsigned Cst = CN->getValue();
4420 // Expand the incoming operand to be shifted, so that we have its parts
4422 ExpandOp(Op, InL, InH);
4426 Lo = DAG.getConstant(0, NVT);
4427 Hi = DAG.getConstant(0, NVT);
4428 } else if (Cst > NVTBits) {
4429 Lo = DAG.getConstant(0, NVT);
4430 Hi = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Cst-NVTBits,ShTy));
4431 } else if (Cst == NVTBits) {
4432 Lo = DAG.getConstant(0, NVT);
4435 Lo = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Cst, ShTy));
4436 Hi = DAG.getNode(ISD::OR, NVT,
4437 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(Cst, ShTy)),
4438 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(NVTBits-Cst, ShTy)));
4443 Lo = DAG.getConstant(0, NVT);
4444 Hi = DAG.getConstant(0, NVT);
4445 } else if (Cst > NVTBits) {
4446 Lo = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Cst-NVTBits,ShTy));
4447 Hi = DAG.getConstant(0, NVT);
4448 } else if (Cst == NVTBits) {
4450 Hi = DAG.getConstant(0, NVT);
4452 Lo = DAG.getNode(ISD::OR, NVT,
4453 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(Cst, ShTy)),
4454 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(NVTBits-Cst, ShTy)));
4455 Hi = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Cst, ShTy));
4460 Hi = Lo = DAG.getNode(ISD::SRA, NVT, InH,
4461 DAG.getConstant(NVTBits-1, ShTy));
4462 } else if (Cst > NVTBits) {
4463 Lo = DAG.getNode(ISD::SRA, NVT, InH,
4464 DAG.getConstant(Cst-NVTBits, ShTy));
4465 Hi = DAG.getNode(ISD::SRA, NVT, InH,
4466 DAG.getConstant(NVTBits-1, ShTy));
4467 } else if (Cst == NVTBits) {
4469 Hi = DAG.getNode(ISD::SRA, NVT, InH,
4470 DAG.getConstant(NVTBits-1, ShTy));
4472 Lo = DAG.getNode(ISD::OR, NVT,
4473 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(Cst, ShTy)),
4474 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(NVTBits-Cst, ShTy)));
4475 Hi = DAG.getNode(ISD::SRA, NVT, InH, DAG.getConstant(Cst, ShTy));
4481 // Okay, the shift amount isn't constant. However, if we can tell that it is
4482 // >= 32 or < 32, we can still simplify it, without knowing the actual value.
4483 uint64_t Mask = NVTBits, KnownZero, KnownOne;
4484 DAG.ComputeMaskedBits(Amt, Mask, KnownZero, KnownOne);
4486 // If we know that the high bit of the shift amount is one, then we can do
4487 // this as a couple of simple shifts.
4488 if (KnownOne & Mask) {
4489 // Mask out the high bit, which we know is set.
4490 Amt = DAG.getNode(ISD::AND, Amt.getValueType(), Amt,
4491 DAG.getConstant(NVTBits-1, Amt.getValueType()));
4493 // Expand the incoming operand to be shifted, so that we have its parts
4495 ExpandOp(Op, InL, InH);
4498 Lo = DAG.getConstant(0, NVT); // Low part is zero.
4499 Hi = DAG.getNode(ISD::SHL, NVT, InL, Amt); // High part from Lo part.
4502 Hi = DAG.getConstant(0, NVT); // Hi part is zero.
4503 Lo = DAG.getNode(ISD::SRL, NVT, InH, Amt); // Lo part from Hi part.
4506 Hi = DAG.getNode(ISD::SRA, NVT, InH, // Sign extend high part.
4507 DAG.getConstant(NVTBits-1, Amt.getValueType()));
4508 Lo = DAG.getNode(ISD::SRA, NVT, InH, Amt); // Lo part from Hi part.
4513 // If we know that the high bit of the shift amount is zero, then we can do
4514 // this as a couple of simple shifts.
4515 if (KnownZero & Mask) {
4517 SDOperand Amt2 = DAG.getNode(ISD::SUB, Amt.getValueType(),
4518 DAG.getConstant(NVTBits, Amt.getValueType()),
4521 // Expand the incoming operand to be shifted, so that we have its parts
4523 ExpandOp(Op, InL, InH);
4526 Lo = DAG.getNode(ISD::SHL, NVT, InL, Amt);
4527 Hi = DAG.getNode(ISD::OR, NVT,
4528 DAG.getNode(ISD::SHL, NVT, InH, Amt),
4529 DAG.getNode(ISD::SRL, NVT, InL, Amt2));
4532 Hi = DAG.getNode(ISD::SRL, NVT, InH, Amt);
4533 Lo = DAG.getNode(ISD::OR, NVT,
4534 DAG.getNode(ISD::SRL, NVT, InL, Amt),
4535 DAG.getNode(ISD::SHL, NVT, InH, Amt2));
4538 Hi = DAG.getNode(ISD::SRA, NVT, InH, Amt);
4539 Lo = DAG.getNode(ISD::OR, NVT,
4540 DAG.getNode(ISD::SRL, NVT, InL, Amt),
4541 DAG.getNode(ISD::SHL, NVT, InH, Amt2));
4550 // ExpandLibCall - Expand a node into a call to a libcall. If the result value
4551 // does not fit into a register, return the lo part and set the hi part to the
4552 // by-reg argument. If it does fit into a single register, return the result
4553 // and leave the Hi part unset.
4554 SDOperand SelectionDAGLegalize::ExpandLibCall(const char *Name, SDNode *Node,
4555 bool isSigned, SDOperand &Hi) {
4556 assert(!IsLegalizingCall && "Cannot overlap legalization of calls!");
4557 // The input chain to this libcall is the entry node of the function.
4558 // Legalizing the call will automatically add the previous call to the
4560 SDOperand InChain = DAG.getEntryNode();
4562 TargetLowering::ArgListTy Args;
4563 TargetLowering::ArgListEntry Entry;
4564 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
4565 MVT::ValueType ArgVT = Node->getOperand(i).getValueType();
4566 const Type *ArgTy = MVT::getTypeForValueType(ArgVT);
4567 Entry.Node = Node->getOperand(i); Entry.Ty = ArgTy;
4568 Entry.isSExt = isSigned;
4569 Args.push_back(Entry);
4571 SDOperand Callee = DAG.getExternalSymbol(Name, TLI.getPointerTy());
4573 // Splice the libcall in wherever FindInputOutputChains tells us to.
4574 const Type *RetTy = MVT::getTypeForValueType(Node->getValueType(0));
4575 std::pair<SDOperand,SDOperand> CallInfo =
4576 TLI.LowerCallTo(InChain, RetTy, isSigned, false, CallingConv::C, false,
4579 // Legalize the call sequence, starting with the chain. This will advance
4580 // the LastCALLSEQ_END to the legalized version of the CALLSEQ_END node that
4581 // was added by LowerCallTo (guaranteeing proper serialization of calls).
4582 LegalizeOp(CallInfo.second);
4584 switch (getTypeAction(CallInfo.first.getValueType())) {
4585 default: assert(0 && "Unknown thing");
4587 Result = CallInfo.first;
4590 ExpandOp(CallInfo.first, Result, Hi);
4597 /// ExpandIntToFP - Expand a [US]INT_TO_FP operation.
4599 SDOperand SelectionDAGLegalize::
4600 ExpandIntToFP(bool isSigned, MVT::ValueType DestTy, SDOperand Source) {
4601 assert(getTypeAction(Source.getValueType()) == Expand &&
4602 "This is not an expansion!");
4603 assert(Source.getValueType() == MVT::i64 && "Only handle expand from i64!");
4606 assert(Source.getValueType() == MVT::i64 &&
4607 "This only works for 64-bit -> FP");
4608 // The 64-bit value loaded will be incorrectly if the 'sign bit' of the
4609 // incoming integer is set. To handle this, we dynamically test to see if
4610 // it is set, and, if so, add a fudge factor.
4612 ExpandOp(Source, Lo, Hi);
4614 // If this is unsigned, and not supported, first perform the conversion to
4615 // signed, then adjust the result if the sign bit is set.
4616 SDOperand SignedConv = ExpandIntToFP(true, DestTy,
4617 DAG.getNode(ISD::BUILD_PAIR, Source.getValueType(), Lo, Hi));
4619 SDOperand SignSet = DAG.getSetCC(TLI.getSetCCResultTy(), Hi,
4620 DAG.getConstant(0, Hi.getValueType()),
4622 SDOperand Zero = getIntPtrConstant(0), Four = getIntPtrConstant(4);
4623 SDOperand CstOffset = DAG.getNode(ISD::SELECT, Zero.getValueType(),
4624 SignSet, Four, Zero);
4625 uint64_t FF = 0x5f800000ULL;
4626 if (TLI.isLittleEndian()) FF <<= 32;
4627 static Constant *FudgeFactor = ConstantInt::get(Type::Int64Ty, FF);
4629 SDOperand CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy());
4630 CPIdx = DAG.getNode(ISD::ADD, TLI.getPointerTy(), CPIdx, CstOffset);
4631 SDOperand FudgeInReg;
4632 if (DestTy == MVT::f32)
4633 FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx, NULL, 0);
4634 else if (MVT::getSizeInBits(DestTy) > MVT::getSizeInBits(MVT::f32))
4635 // FIXME: Avoid the extend by construction the right constantpool?
4636 FudgeInReg = DAG.getExtLoad(ISD::EXTLOAD, DestTy, DAG.getEntryNode(),
4637 CPIdx, NULL, 0, MVT::f32);
4639 assert(0 && "Unexpected conversion");
4641 MVT::ValueType SCVT = SignedConv.getValueType();
4642 if (SCVT != DestTy) {
4643 // Destination type needs to be expanded as well. The FADD now we are
4644 // constructing will be expanded into a libcall.
4645 if (MVT::getSizeInBits(SCVT) != MVT::getSizeInBits(DestTy)) {
4646 assert(SCVT == MVT::i32 && DestTy == MVT::f64);
4647 SignedConv = DAG.getNode(ISD::BUILD_PAIR, MVT::i64,
4648 SignedConv, SignedConv.getValue(1));
4650 SignedConv = DAG.getNode(ISD::BIT_CONVERT, DestTy, SignedConv);
4652 return DAG.getNode(ISD::FADD, DestTy, SignedConv, FudgeInReg);
4655 // Check to see if the target has a custom way to lower this. If so, use it.
4656 switch (TLI.getOperationAction(ISD::SINT_TO_FP, Source.getValueType())) {
4657 default: assert(0 && "This action not implemented for this operation!");
4658 case TargetLowering::Legal:
4659 case TargetLowering::Expand:
4660 break; // This case is handled below.
4661 case TargetLowering::Custom: {
4662 SDOperand NV = TLI.LowerOperation(DAG.getNode(ISD::SINT_TO_FP, DestTy,
4665 return LegalizeOp(NV);
4666 break; // The target decided this was legal after all
4670 // Expand the source, then glue it back together for the call. We must expand
4671 // the source in case it is shared (this pass of legalize must traverse it).
4672 SDOperand SrcLo, SrcHi;
4673 ExpandOp(Source, SrcLo, SrcHi);
4674 Source = DAG.getNode(ISD::BUILD_PAIR, Source.getValueType(), SrcLo, SrcHi);
4677 if (DestTy == MVT::f32)
4678 LC = RTLIB::SINTTOFP_I64_F32;
4680 assert(DestTy == MVT::f64 && "Unknown fp value type!");
4681 LC = RTLIB::SINTTOFP_I64_F64;
4684 assert(TLI.getLibcallName(LC) && "Don't know how to expand this SINT_TO_FP!");
4685 Source = DAG.getNode(ISD::SINT_TO_FP, DestTy, Source);
4686 SDOperand UnusedHiPart;
4687 return ExpandLibCall(TLI.getLibcallName(LC), Source.Val, isSigned,
4691 /// ExpandLegalINT_TO_FP - This function is responsible for legalizing a
4692 /// INT_TO_FP operation of the specified operand when the target requests that
4693 /// we expand it. At this point, we know that the result and operand types are
4694 /// legal for the target.
4695 SDOperand SelectionDAGLegalize::ExpandLegalINT_TO_FP(bool isSigned,
4697 MVT::ValueType DestVT) {
4698 if (Op0.getValueType() == MVT::i32) {
4699 // simple 32-bit [signed|unsigned] integer to float/double expansion
4701 // get the stack frame index of a 8 byte buffer, pessimistically aligned
4702 MachineFunction &MF = DAG.getMachineFunction();
4703 const Type *F64Type = MVT::getTypeForValueType(MVT::f64);
4704 unsigned StackAlign =
4705 (unsigned)TLI.getTargetData()->getPrefTypeAlignment(F64Type);
4706 int SSFI = MF.getFrameInfo()->CreateStackObject(8, StackAlign);
4707 // get address of 8 byte buffer
4708 SDOperand StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy());
4709 // word offset constant for Hi/Lo address computation
4710 SDOperand WordOff = DAG.getConstant(sizeof(int), TLI.getPointerTy());
4711 // set up Hi and Lo (into buffer) address based on endian
4712 SDOperand Hi = StackSlot;
4713 SDOperand Lo = DAG.getNode(ISD::ADD, TLI.getPointerTy(), StackSlot,WordOff);
4714 if (TLI.isLittleEndian())
4717 // if signed map to unsigned space
4718 SDOperand Op0Mapped;
4720 // constant used to invert sign bit (signed to unsigned mapping)
4721 SDOperand SignBit = DAG.getConstant(0x80000000u, MVT::i32);
4722 Op0Mapped = DAG.getNode(ISD::XOR, MVT::i32, Op0, SignBit);
4726 // store the lo of the constructed double - based on integer input
4727 SDOperand Store1 = DAG.getStore(DAG.getEntryNode(),
4728 Op0Mapped, Lo, NULL, 0);
4729 // initial hi portion of constructed double
4730 SDOperand InitialHi = DAG.getConstant(0x43300000u, MVT::i32);
4731 // store the hi of the constructed double - biased exponent
4732 SDOperand Store2=DAG.getStore(Store1, InitialHi, Hi, NULL, 0);
4733 // load the constructed double
4734 SDOperand Load = DAG.getLoad(MVT::f64, Store2, StackSlot, NULL, 0);
4735 // FP constant to bias correct the final result
4736 SDOperand Bias = DAG.getConstantFP(isSigned ?
4737 BitsToDouble(0x4330000080000000ULL)
4738 : BitsToDouble(0x4330000000000000ULL),
4740 // subtract the bias
4741 SDOperand Sub = DAG.getNode(ISD::FSUB, MVT::f64, Load, Bias);
4744 // handle final rounding
4745 if (DestVT == MVT::f64) {
4748 } else if (MVT::getSizeInBits(DestVT) < MVT::getSizeInBits(MVT::f64)) {
4749 Result = DAG.getNode(ISD::FP_ROUND, DestVT, Sub);
4750 } else if (MVT::getSizeInBits(DestVT) > MVT::getSizeInBits(MVT::f64)) {
4751 Result = DAG.getNode(ISD::FP_EXTEND, DestVT, Sub);
4755 assert(!isSigned && "Legalize cannot Expand SINT_TO_FP for i64 yet");
4756 SDOperand Tmp1 = DAG.getNode(ISD::SINT_TO_FP, DestVT, Op0);
4758 SDOperand SignSet = DAG.getSetCC(TLI.getSetCCResultTy(), Op0,
4759 DAG.getConstant(0, Op0.getValueType()),
4761 SDOperand Zero = getIntPtrConstant(0), Four = getIntPtrConstant(4);
4762 SDOperand CstOffset = DAG.getNode(ISD::SELECT, Zero.getValueType(),
4763 SignSet, Four, Zero);
4765 // If the sign bit of the integer is set, the large number will be treated
4766 // as a negative number. To counteract this, the dynamic code adds an
4767 // offset depending on the data type.
4769 switch (Op0.getValueType()) {
4770 default: assert(0 && "Unsupported integer type!");
4771 case MVT::i8 : FF = 0x43800000ULL; break; // 2^8 (as a float)
4772 case MVT::i16: FF = 0x47800000ULL; break; // 2^16 (as a float)
4773 case MVT::i32: FF = 0x4F800000ULL; break; // 2^32 (as a float)
4774 case MVT::i64: FF = 0x5F800000ULL; break; // 2^64 (as a float)
4776 if (TLI.isLittleEndian()) FF <<= 32;
4777 static Constant *FudgeFactor = ConstantInt::get(Type::Int64Ty, FF);
4779 SDOperand CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy());
4780 CPIdx = DAG.getNode(ISD::ADD, TLI.getPointerTy(), CPIdx, CstOffset);
4781 SDOperand FudgeInReg;
4782 if (DestVT == MVT::f32)
4783 FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx, NULL, 0);
4785 FudgeInReg = LegalizeOp(DAG.getExtLoad(ISD::EXTLOAD, DestVT,
4786 DAG.getEntryNode(), CPIdx,
4787 NULL, 0, MVT::f32));
4790 return DAG.getNode(ISD::FADD, DestVT, Tmp1, FudgeInReg);
4793 /// PromoteLegalINT_TO_FP - This function is responsible for legalizing a
4794 /// *INT_TO_FP operation of the specified operand when the target requests that
4795 /// we promote it. At this point, we know that the result and operand types are
4796 /// legal for the target, and that there is a legal UINT_TO_FP or SINT_TO_FP
4797 /// operation that takes a larger input.
4798 SDOperand SelectionDAGLegalize::PromoteLegalINT_TO_FP(SDOperand LegalOp,
4799 MVT::ValueType DestVT,
4801 // First step, figure out the appropriate *INT_TO_FP operation to use.
4802 MVT::ValueType NewInTy = LegalOp.getValueType();
4804 unsigned OpToUse = 0;
4806 // Scan for the appropriate larger type to use.
4808 NewInTy = (MVT::ValueType)(NewInTy+1);
4809 assert(MVT::isInteger(NewInTy) && "Ran out of possibilities!");
4811 // If the target supports SINT_TO_FP of this type, use it.
4812 switch (TLI.getOperationAction(ISD::SINT_TO_FP, NewInTy)) {
4814 case TargetLowering::Legal:
4815 if (!TLI.isTypeLegal(NewInTy))
4816 break; // Can't use this datatype.
4818 case TargetLowering::Custom:
4819 OpToUse = ISD::SINT_TO_FP;
4823 if (isSigned) continue;
4825 // If the target supports UINT_TO_FP of this type, use it.
4826 switch (TLI.getOperationAction(ISD::UINT_TO_FP, NewInTy)) {
4828 case TargetLowering::Legal:
4829 if (!TLI.isTypeLegal(NewInTy))
4830 break; // Can't use this datatype.
4832 case TargetLowering::Custom:
4833 OpToUse = ISD::UINT_TO_FP;
4838 // Otherwise, try a larger type.
4841 // Okay, we found the operation and type to use. Zero extend our input to the
4842 // desired type then run the operation on it.
4843 return DAG.getNode(OpToUse, DestVT,
4844 DAG.getNode(isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND,
4848 /// PromoteLegalFP_TO_INT - This function is responsible for legalizing a
4849 /// FP_TO_*INT operation of the specified operand when the target requests that
4850 /// we promote it. At this point, we know that the result and operand types are
4851 /// legal for the target, and that there is a legal FP_TO_UINT or FP_TO_SINT
4852 /// operation that returns a larger result.
4853 SDOperand SelectionDAGLegalize::PromoteLegalFP_TO_INT(SDOperand LegalOp,
4854 MVT::ValueType DestVT,
4856 // First step, figure out the appropriate FP_TO*INT operation to use.
4857 MVT::ValueType NewOutTy = DestVT;
4859 unsigned OpToUse = 0;
4861 // Scan for the appropriate larger type to use.
4863 NewOutTy = (MVT::ValueType)(NewOutTy+1);
4864 assert(MVT::isInteger(NewOutTy) && "Ran out of possibilities!");
4866 // If the target supports FP_TO_SINT returning this type, use it.
4867 switch (TLI.getOperationAction(ISD::FP_TO_SINT, NewOutTy)) {
4869 case TargetLowering::Legal:
4870 if (!TLI.isTypeLegal(NewOutTy))
4871 break; // Can't use this datatype.
4873 case TargetLowering::Custom:
4874 OpToUse = ISD::FP_TO_SINT;
4879 // If the target supports FP_TO_UINT of this type, use it.
4880 switch (TLI.getOperationAction(ISD::FP_TO_UINT, NewOutTy)) {
4882 case TargetLowering::Legal:
4883 if (!TLI.isTypeLegal(NewOutTy))
4884 break; // Can't use this datatype.
4886 case TargetLowering::Custom:
4887 OpToUse = ISD::FP_TO_UINT;
4892 // Otherwise, try a larger type.
4895 // Okay, we found the operation and type to use. Truncate the result of the
4896 // extended FP_TO_*INT operation to the desired size.
4897 return DAG.getNode(ISD::TRUNCATE, DestVT,
4898 DAG.getNode(OpToUse, NewOutTy, LegalOp));
4901 /// ExpandBSWAP - Open code the operations for BSWAP of the specified operation.
4903 SDOperand SelectionDAGLegalize::ExpandBSWAP(SDOperand Op) {
4904 MVT::ValueType VT = Op.getValueType();
4905 MVT::ValueType SHVT = TLI.getShiftAmountTy();
4906 SDOperand Tmp1, Tmp2, Tmp3, Tmp4, Tmp5, Tmp6, Tmp7, Tmp8;
4908 default: assert(0 && "Unhandled Expand type in BSWAP!"); abort();
4910 Tmp2 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT));
4911 Tmp1 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(8, SHVT));
4912 return DAG.getNode(ISD::OR, VT, Tmp1, Tmp2);
4914 Tmp4 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(24, SHVT));
4915 Tmp3 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT));
4916 Tmp2 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(8, SHVT));
4917 Tmp1 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(24, SHVT));
4918 Tmp3 = DAG.getNode(ISD::AND, VT, Tmp3, DAG.getConstant(0xFF0000, VT));
4919 Tmp2 = DAG.getNode(ISD::AND, VT, Tmp2, DAG.getConstant(0xFF00, VT));
4920 Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp3);
4921 Tmp2 = DAG.getNode(ISD::OR, VT, Tmp2, Tmp1);
4922 return DAG.getNode(ISD::OR, VT, Tmp4, Tmp2);
4924 Tmp8 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(56, SHVT));
4925 Tmp7 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(40, SHVT));
4926 Tmp6 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(24, SHVT));
4927 Tmp5 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT));
4928 Tmp4 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(8, SHVT));
4929 Tmp3 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(24, SHVT));
4930 Tmp2 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(40, SHVT));
4931 Tmp1 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(56, SHVT));
4932 Tmp7 = DAG.getNode(ISD::AND, VT, Tmp7, DAG.getConstant(255ULL<<48, VT));
4933 Tmp6 = DAG.getNode(ISD::AND, VT, Tmp6, DAG.getConstant(255ULL<<40, VT));
4934 Tmp5 = DAG.getNode(ISD::AND, VT, Tmp5, DAG.getConstant(255ULL<<32, VT));
4935 Tmp4 = DAG.getNode(ISD::AND, VT, Tmp4, DAG.getConstant(255ULL<<24, VT));
4936 Tmp3 = DAG.getNode(ISD::AND, VT, Tmp3, DAG.getConstant(255ULL<<16, VT));
4937 Tmp2 = DAG.getNode(ISD::AND, VT, Tmp2, DAG.getConstant(255ULL<<8 , VT));
4938 Tmp8 = DAG.getNode(ISD::OR, VT, Tmp8, Tmp7);
4939 Tmp6 = DAG.getNode(ISD::OR, VT, Tmp6, Tmp5);
4940 Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp3);
4941 Tmp2 = DAG.getNode(ISD::OR, VT, Tmp2, Tmp1);
4942 Tmp8 = DAG.getNode(ISD::OR, VT, Tmp8, Tmp6);
4943 Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp2);
4944 return DAG.getNode(ISD::OR, VT, Tmp8, Tmp4);
4948 /// ExpandBitCount - Expand the specified bitcount instruction into operations.
4950 SDOperand SelectionDAGLegalize::ExpandBitCount(unsigned Opc, SDOperand Op) {
4952 default: assert(0 && "Cannot expand this yet!");
4954 static const uint64_t mask[6] = {
4955 0x5555555555555555ULL, 0x3333333333333333ULL,
4956 0x0F0F0F0F0F0F0F0FULL, 0x00FF00FF00FF00FFULL,
4957 0x0000FFFF0000FFFFULL, 0x00000000FFFFFFFFULL
4959 MVT::ValueType VT = Op.getValueType();
4960 MVT::ValueType ShVT = TLI.getShiftAmountTy();
4961 unsigned len = MVT::getSizeInBits(VT);
4962 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) {
4963 //x = (x & mask[i][len/8]) + (x >> (1 << i) & mask[i][len/8])
4964 SDOperand Tmp2 = DAG.getConstant(mask[i], VT);
4965 SDOperand Tmp3 = DAG.getConstant(1ULL << i, ShVT);
4966 Op = DAG.getNode(ISD::ADD, VT, DAG.getNode(ISD::AND, VT, Op, Tmp2),
4967 DAG.getNode(ISD::AND, VT,
4968 DAG.getNode(ISD::SRL, VT, Op, Tmp3),Tmp2));
4973 // for now, we do this:
4974 // x = x | (x >> 1);
4975 // x = x | (x >> 2);
4977 // x = x | (x >>16);
4978 // x = x | (x >>32); // for 64-bit input
4979 // return popcount(~x);
4981 // but see also: http://www.hackersdelight.org/HDcode/nlz.cc
4982 MVT::ValueType VT = Op.getValueType();
4983 MVT::ValueType ShVT = TLI.getShiftAmountTy();
4984 unsigned len = MVT::getSizeInBits(VT);
4985 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) {
4986 SDOperand Tmp3 = DAG.getConstant(1ULL << i, ShVT);
4987 Op = DAG.getNode(ISD::OR, VT, Op, DAG.getNode(ISD::SRL, VT, Op, Tmp3));
4989 Op = DAG.getNode(ISD::XOR, VT, Op, DAG.getConstant(~0ULL, VT));
4990 return DAG.getNode(ISD::CTPOP, VT, Op);
4993 // for now, we use: { return popcount(~x & (x - 1)); }
4994 // unless the target has ctlz but not ctpop, in which case we use:
4995 // { return 32 - nlz(~x & (x-1)); }
4996 // see also http://www.hackersdelight.org/HDcode/ntz.cc
4997 MVT::ValueType VT = Op.getValueType();
4998 SDOperand Tmp2 = DAG.getConstant(~0ULL, VT);
4999 SDOperand Tmp3 = DAG.getNode(ISD::AND, VT,
5000 DAG.getNode(ISD::XOR, VT, Op, Tmp2),
5001 DAG.getNode(ISD::SUB, VT, Op, DAG.getConstant(1, VT)));
5002 // If ISD::CTLZ is legal and CTPOP isn't, then do that instead.
5003 if (!TLI.isOperationLegal(ISD::CTPOP, VT) &&
5004 TLI.isOperationLegal(ISD::CTLZ, VT))
5005 return DAG.getNode(ISD::SUB, VT,
5006 DAG.getConstant(MVT::getSizeInBits(VT), VT),
5007 DAG.getNode(ISD::CTLZ, VT, Tmp3));
5008 return DAG.getNode(ISD::CTPOP, VT, Tmp3);
5013 /// ExpandOp - Expand the specified SDOperand into its two component pieces
5014 /// Lo&Hi. Note that the Op MUST be an expanded type. As a result of this, the
5015 /// LegalizeNodes map is filled in for any results that are not expanded, the
5016 /// ExpandedNodes map is filled in for any results that are expanded, and the
5017 /// Lo/Hi values are returned.
5018 void SelectionDAGLegalize::ExpandOp(SDOperand Op, SDOperand &Lo, SDOperand &Hi){
5019 MVT::ValueType VT = Op.getValueType();
5020 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT);
5021 SDNode *Node = Op.Val;
5022 assert(getTypeAction(VT) == Expand && "Not an expanded type!");
5023 assert(((MVT::isInteger(NVT) && NVT < VT) || MVT::isFloatingPoint(VT) ||
5024 MVT::isVector(VT)) &&
5025 "Cannot expand to FP value or to larger int value!");
5027 // See if we already expanded it.
5028 DenseMap<SDOperand, std::pair<SDOperand, SDOperand> >::iterator I
5029 = ExpandedNodes.find(Op);
5030 if (I != ExpandedNodes.end()) {
5031 Lo = I->second.first;
5032 Hi = I->second.second;
5036 switch (Node->getOpcode()) {
5037 case ISD::CopyFromReg:
5038 assert(0 && "CopyFromReg must be legal!");
5041 cerr << "NODE: "; Node->dump(&DAG); cerr << "\n";
5043 assert(0 && "Do not know how to expand this operator!");
5046 NVT = TLI.getTypeToExpandTo(VT);
5047 Lo = DAG.getNode(ISD::UNDEF, NVT);
5048 Hi = DAG.getNode(ISD::UNDEF, NVT);
5050 case ISD::Constant: {
5051 uint64_t Cst = cast<ConstantSDNode>(Node)->getValue();
5052 Lo = DAG.getConstant(Cst, NVT);
5053 Hi = DAG.getConstant(Cst >> MVT::getSizeInBits(NVT), NVT);
5056 case ISD::ConstantFP: {
5057 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node);
5058 Lo = ExpandConstantFP(CFP, false, DAG, TLI);
5059 if (getTypeAction(Lo.getValueType()) == Expand)
5060 ExpandOp(Lo, Lo, Hi);
5063 case ISD::BUILD_PAIR:
5064 // Return the operands.
5065 Lo = Node->getOperand(0);
5066 Hi = Node->getOperand(1);
5069 case ISD::SIGN_EXTEND_INREG:
5070 ExpandOp(Node->getOperand(0), Lo, Hi);
5071 // sext_inreg the low part if needed.
5072 Lo = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Lo, Node->getOperand(1));
5074 // The high part gets the sign extension from the lo-part. This handles
5075 // things like sextinreg V:i64 from i8.
5076 Hi = DAG.getNode(ISD::SRA, NVT, Lo,
5077 DAG.getConstant(MVT::getSizeInBits(NVT)-1,
5078 TLI.getShiftAmountTy()));
5082 ExpandOp(Node->getOperand(0), Lo, Hi);
5083 SDOperand TempLo = DAG.getNode(ISD::BSWAP, NVT, Hi);
5084 Hi = DAG.getNode(ISD::BSWAP, NVT, Lo);
5090 ExpandOp(Node->getOperand(0), Lo, Hi);
5091 Lo = DAG.getNode(ISD::ADD, NVT, // ctpop(HL) -> ctpop(H)+ctpop(L)
5092 DAG.getNode(ISD::CTPOP, NVT, Lo),
5093 DAG.getNode(ISD::CTPOP, NVT, Hi));
5094 Hi = DAG.getConstant(0, NVT);
5098 // ctlz (HL) -> ctlz(H) != 32 ? ctlz(H) : (ctlz(L)+32)
5099 ExpandOp(Node->getOperand(0), Lo, Hi);
5100 SDOperand BitsC = DAG.getConstant(MVT::getSizeInBits(NVT), NVT);
5101 SDOperand HLZ = DAG.getNode(ISD::CTLZ, NVT, Hi);
5102 SDOperand TopNotZero = DAG.getSetCC(TLI.getSetCCResultTy(), HLZ, BitsC,
5104 SDOperand LowPart = DAG.getNode(ISD::CTLZ, NVT, Lo);
5105 LowPart = DAG.getNode(ISD::ADD, NVT, LowPart, BitsC);
5107 Lo = DAG.getNode(ISD::SELECT, NVT, TopNotZero, HLZ, LowPart);
5108 Hi = DAG.getConstant(0, NVT);
5113 // cttz (HL) -> cttz(L) != 32 ? cttz(L) : (cttz(H)+32)
5114 ExpandOp(Node->getOperand(0), Lo, Hi);
5115 SDOperand BitsC = DAG.getConstant(MVT::getSizeInBits(NVT), NVT);
5116 SDOperand LTZ = DAG.getNode(ISD::CTTZ, NVT, Lo);
5117 SDOperand BotNotZero = DAG.getSetCC(TLI.getSetCCResultTy(), LTZ, BitsC,
5119 SDOperand HiPart = DAG.getNode(ISD::CTTZ, NVT, Hi);
5120 HiPart = DAG.getNode(ISD::ADD, NVT, HiPart, BitsC);
5122 Lo = DAG.getNode(ISD::SELECT, NVT, BotNotZero, LTZ, HiPart);
5123 Hi = DAG.getConstant(0, NVT);
5128 SDOperand Ch = Node->getOperand(0); // Legalize the chain.
5129 SDOperand Ptr = Node->getOperand(1); // Legalize the pointer.
5130 Lo = DAG.getVAArg(NVT, Ch, Ptr, Node->getOperand(2));
5131 Hi = DAG.getVAArg(NVT, Lo.getValue(1), Ptr, Node->getOperand(2));
5133 // Remember that we legalized the chain.
5134 Hi = LegalizeOp(Hi);
5135 AddLegalizedOperand(Op.getValue(1), Hi.getValue(1));
5136 if (!TLI.isLittleEndian())
5142 LoadSDNode *LD = cast<LoadSDNode>(Node);
5143 SDOperand Ch = LD->getChain(); // Legalize the chain.
5144 SDOperand Ptr = LD->getBasePtr(); // Legalize the pointer.
5145 ISD::LoadExtType ExtType = LD->getExtensionType();
5146 int SVOffset = LD->getSrcValueOffset();
5147 unsigned Alignment = LD->getAlignment();
5148 bool isVolatile = LD->isVolatile();
5150 if (ExtType == ISD::NON_EXTLOAD) {
5151 Lo = DAG.getLoad(NVT, Ch, Ptr, LD->getSrcValue(), SVOffset,
5152 isVolatile, Alignment);
5153 if (VT == MVT::f32 || VT == MVT::f64) {
5154 // f32->i32 or f64->i64 one to one expansion.
5155 // Remember that we legalized the chain.
5156 AddLegalizedOperand(SDOperand(Node, 1), LegalizeOp(Lo.getValue(1)));
5157 // Recursively expand the new load.
5158 if (getTypeAction(NVT) == Expand)
5159 ExpandOp(Lo, Lo, Hi);
5163 // Increment the pointer to the other half.
5164 unsigned IncrementSize = MVT::getSizeInBits(Lo.getValueType())/8;
5165 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
5166 getIntPtrConstant(IncrementSize));
5167 SVOffset += IncrementSize;
5168 if (Alignment > IncrementSize)
5169 Alignment = IncrementSize;
5170 Hi = DAG.getLoad(NVT, Ch, Ptr, LD->getSrcValue(), SVOffset,
5171 isVolatile, Alignment);
5173 // Build a factor node to remember that this load is independent of the
5175 SDOperand TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
5178 // Remember that we legalized the chain.
5179 AddLegalizedOperand(Op.getValue(1), LegalizeOp(TF));
5180 if (!TLI.isLittleEndian())
5183 MVT::ValueType EVT = LD->getLoadedVT();
5185 if (VT == MVT::f64 && EVT == MVT::f32) {
5186 // f64 = EXTLOAD f32 should expand to LOAD, FP_EXTEND
5187 SDOperand Load = DAG.getLoad(EVT, Ch, Ptr, LD->getSrcValue(),
5188 SVOffset, isVolatile, Alignment);
5189 // Remember that we legalized the chain.
5190 AddLegalizedOperand(SDOperand(Node, 1), LegalizeOp(Load.getValue(1)));
5191 ExpandOp(DAG.getNode(ISD::FP_EXTEND, VT, Load), Lo, Hi);
5196 Lo = DAG.getLoad(NVT, Ch, Ptr, LD->getSrcValue(),
5197 SVOffset, isVolatile, Alignment);
5199 Lo = DAG.getExtLoad(ExtType, NVT, Ch, Ptr, LD->getSrcValue(),
5200 SVOffset, EVT, isVolatile,
5203 // Remember that we legalized the chain.
5204 AddLegalizedOperand(SDOperand(Node, 1), LegalizeOp(Lo.getValue(1)));
5206 if (ExtType == ISD::SEXTLOAD) {
5207 // The high part is obtained by SRA'ing all but one of the bits of the
5209 unsigned LoSize = MVT::getSizeInBits(Lo.getValueType());
5210 Hi = DAG.getNode(ISD::SRA, NVT, Lo,
5211 DAG.getConstant(LoSize-1, TLI.getShiftAmountTy()));
5212 } else if (ExtType == ISD::ZEXTLOAD) {
5213 // The high part is just a zero.
5214 Hi = DAG.getConstant(0, NVT);
5215 } else /* if (ExtType == ISD::EXTLOAD) */ {
5216 // The high part is undefined.
5217 Hi = DAG.getNode(ISD::UNDEF, NVT);
5224 case ISD::XOR: { // Simple logical operators -> two trivial pieces.
5225 SDOperand LL, LH, RL, RH;
5226 ExpandOp(Node->getOperand(0), LL, LH);
5227 ExpandOp(Node->getOperand(1), RL, RH);
5228 Lo = DAG.getNode(Node->getOpcode(), NVT, LL, RL);
5229 Hi = DAG.getNode(Node->getOpcode(), NVT, LH, RH);
5233 SDOperand LL, LH, RL, RH;
5234 ExpandOp(Node->getOperand(1), LL, LH);
5235 ExpandOp(Node->getOperand(2), RL, RH);
5236 if (getTypeAction(NVT) == Expand)
5237 NVT = TLI.getTypeToExpandTo(NVT);
5238 Lo = DAG.getNode(ISD::SELECT, NVT, Node->getOperand(0), LL, RL);
5240 Hi = DAG.getNode(ISD::SELECT, NVT, Node->getOperand(0), LH, RH);
5243 case ISD::SELECT_CC: {
5244 SDOperand TL, TH, FL, FH;
5245 ExpandOp(Node->getOperand(2), TL, TH);
5246 ExpandOp(Node->getOperand(3), FL, FH);
5247 if (getTypeAction(NVT) == Expand)
5248 NVT = TLI.getTypeToExpandTo(NVT);
5249 Lo = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0),
5250 Node->getOperand(1), TL, FL, Node->getOperand(4));
5252 Hi = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0),
5253 Node->getOperand(1), TH, FH, Node->getOperand(4));
5256 case ISD::ANY_EXTEND:
5257 // The low part is any extension of the input (which degenerates to a copy).
5258 Lo = DAG.getNode(ISD::ANY_EXTEND, NVT, Node->getOperand(0));
5259 // The high part is undefined.
5260 Hi = DAG.getNode(ISD::UNDEF, NVT);
5262 case ISD::SIGN_EXTEND: {
5263 // The low part is just a sign extension of the input (which degenerates to
5265 Lo = DAG.getNode(ISD::SIGN_EXTEND, NVT, Node->getOperand(0));
5267 // The high part is obtained by SRA'ing all but one of the bits of the lo
5269 unsigned LoSize = MVT::getSizeInBits(Lo.getValueType());
5270 Hi = DAG.getNode(ISD::SRA, NVT, Lo,
5271 DAG.getConstant(LoSize-1, TLI.getShiftAmountTy()));
5274 case ISD::ZERO_EXTEND:
5275 // The low part is just a zero extension of the input (which degenerates to
5277 Lo = DAG.getNode(ISD::ZERO_EXTEND, NVT, Node->getOperand(0));
5279 // The high part is just a zero.
5280 Hi = DAG.getConstant(0, NVT);
5283 case ISD::TRUNCATE: {
5284 // The input value must be larger than this value. Expand *it*.
5286 ExpandOp(Node->getOperand(0), NewLo, Hi);
5288 // The low part is now either the right size, or it is closer. If not the
5289 // right size, make an illegal truncate so we recursively expand it.
5290 if (NewLo.getValueType() != Node->getValueType(0))
5291 NewLo = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), NewLo);
5292 ExpandOp(NewLo, Lo, Hi);
5296 case ISD::BIT_CONVERT: {
5298 if (TLI.getOperationAction(ISD::BIT_CONVERT, VT) == TargetLowering::Custom){
5299 // If the target wants to, allow it to lower this itself.
5300 switch (getTypeAction(Node->getOperand(0).getValueType())) {
5301 case Expand: assert(0 && "cannot expand FP!");
5302 case Legal: Tmp = LegalizeOp(Node->getOperand(0)); break;
5303 case Promote: Tmp = PromoteOp (Node->getOperand(0)); break;
5305 Tmp = TLI.LowerOperation(DAG.getNode(ISD::BIT_CONVERT, VT, Tmp), DAG);
5308 // f32 / f64 must be expanded to i32 / i64.
5309 if (VT == MVT::f32 || VT == MVT::f64) {
5310 Lo = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0));
5311 if (getTypeAction(NVT) == Expand)
5312 ExpandOp(Lo, Lo, Hi);
5316 // If source operand will be expanded to the same type as VT, i.e.
5317 // i64 <- f64, i32 <- f32, expand the source operand instead.
5318 MVT::ValueType VT0 = Node->getOperand(0).getValueType();
5319 if (getTypeAction(VT0) == Expand && TLI.getTypeToTransformTo(VT0) == VT) {
5320 ExpandOp(Node->getOperand(0), Lo, Hi);
5324 // Turn this into a load/store pair by default.
5326 Tmp = ExpandBIT_CONVERT(VT, Node->getOperand(0));
5328 ExpandOp(Tmp, Lo, Hi);
5332 case ISD::READCYCLECOUNTER:
5333 assert(TLI.getOperationAction(ISD::READCYCLECOUNTER, VT) ==
5334 TargetLowering::Custom &&
5335 "Must custom expand ReadCycleCounter");
5336 Lo = TLI.LowerOperation(Op, DAG);
5337 assert(Lo.Val && "Node must be custom expanded!");
5338 Hi = Lo.getValue(1);
5339 AddLegalizedOperand(SDOperand(Node, 1), // Remember we legalized the chain.
5340 LegalizeOp(Lo.getValue(2)));
5343 // These operators cannot be expanded directly, emit them as calls to
5344 // library functions.
5345 case ISD::FP_TO_SINT: {
5346 if (TLI.getOperationAction(ISD::FP_TO_SINT, VT) == TargetLowering::Custom) {
5348 switch (getTypeAction(Node->getOperand(0).getValueType())) {
5349 case Expand: assert(0 && "cannot expand FP!");
5350 case Legal: Op = LegalizeOp(Node->getOperand(0)); break;
5351 case Promote: Op = PromoteOp (Node->getOperand(0)); break;
5354 Op = TLI.LowerOperation(DAG.getNode(ISD::FP_TO_SINT, VT, Op), DAG);
5356 // Now that the custom expander is done, expand the result, which is still
5359 ExpandOp(Op, Lo, Hi);
5365 if (Node->getOperand(0).getValueType() == MVT::f32)
5366 LC = RTLIB::FPTOSINT_F32_I64;
5367 else if (Node->getOperand(0).getValueType() == MVT::f64)
5368 LC = RTLIB::FPTOSINT_F64_I64;
5370 LC = RTLIB::FPTOSINT_LD_I64;
5371 Lo = ExpandLibCall(TLI.getLibcallName(LC), Node,
5372 false/*sign irrelevant*/, Hi);
5376 case ISD::FP_TO_UINT: {
5377 if (TLI.getOperationAction(ISD::FP_TO_UINT, VT) == TargetLowering::Custom) {
5379 switch (getTypeAction(Node->getOperand(0).getValueType())) {
5380 case Expand: assert(0 && "cannot expand FP!");
5381 case Legal: Op = LegalizeOp(Node->getOperand(0)); break;
5382 case Promote: Op = PromoteOp (Node->getOperand(0)); break;
5385 Op = TLI.LowerOperation(DAG.getNode(ISD::FP_TO_UINT, VT, Op), DAG);
5387 // Now that the custom expander is done, expand the result.
5389 ExpandOp(Op, Lo, Hi);
5395 if (Node->getOperand(0).getValueType() == MVT::f32)
5396 LC = RTLIB::FPTOUINT_F32_I64;
5398 LC = RTLIB::FPTOUINT_F64_I64;
5399 Lo = ExpandLibCall(TLI.getLibcallName(LC), Node,
5400 false/*sign irrelevant*/, Hi);
5405 // If the target wants custom lowering, do so.
5406 SDOperand ShiftAmt = LegalizeOp(Node->getOperand(1));
5407 if (TLI.getOperationAction(ISD::SHL, VT) == TargetLowering::Custom) {
5408 SDOperand Op = DAG.getNode(ISD::SHL, VT, Node->getOperand(0), ShiftAmt);
5409 Op = TLI.LowerOperation(Op, DAG);
5411 // Now that the custom expander is done, expand the result, which is
5413 ExpandOp(Op, Lo, Hi);
5418 // If ADDC/ADDE are supported and if the shift amount is a constant 1, emit
5419 // this X << 1 as X+X.
5420 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(ShiftAmt)) {
5421 if (ShAmt->getValue() == 1 && TLI.isOperationLegal(ISD::ADDC, NVT) &&
5422 TLI.isOperationLegal(ISD::ADDE, NVT)) {
5423 SDOperand LoOps[2], HiOps[3];
5424 ExpandOp(Node->getOperand(0), LoOps[0], HiOps[0]);
5425 SDVTList VTList = DAG.getVTList(LoOps[0].getValueType(), MVT::Flag);
5426 LoOps[1] = LoOps[0];
5427 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2);
5429 HiOps[1] = HiOps[0];
5430 HiOps[2] = Lo.getValue(1);
5431 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3);
5436 // If we can emit an efficient shift operation, do so now.
5437 if (ExpandShift(ISD::SHL, Node->getOperand(0), ShiftAmt, Lo, Hi))
5440 // If this target supports SHL_PARTS, use it.
5441 TargetLowering::LegalizeAction Action =
5442 TLI.getOperationAction(ISD::SHL_PARTS, NVT);
5443 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) ||
5444 Action == TargetLowering::Custom) {
5445 ExpandShiftParts(ISD::SHL_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi);
5449 // Otherwise, emit a libcall.
5450 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::SHL_I64), Node,
5451 false/*left shift=unsigned*/, Hi);
5456 // If the target wants custom lowering, do so.
5457 SDOperand ShiftAmt = LegalizeOp(Node->getOperand(1));
5458 if (TLI.getOperationAction(ISD::SRA, VT) == TargetLowering::Custom) {
5459 SDOperand Op = DAG.getNode(ISD::SRA, VT, Node->getOperand(0), ShiftAmt);
5460 Op = TLI.LowerOperation(Op, DAG);
5462 // Now that the custom expander is done, expand the result, which is
5464 ExpandOp(Op, Lo, Hi);
5469 // If we can emit an efficient shift operation, do so now.
5470 if (ExpandShift(ISD::SRA, Node->getOperand(0), ShiftAmt, Lo, Hi))
5473 // If this target supports SRA_PARTS, use it.
5474 TargetLowering::LegalizeAction Action =
5475 TLI.getOperationAction(ISD::SRA_PARTS, NVT);
5476 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) ||
5477 Action == TargetLowering::Custom) {
5478 ExpandShiftParts(ISD::SRA_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi);
5482 // Otherwise, emit a libcall.
5483 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::SRA_I64), Node,
5484 true/*ashr is signed*/, Hi);
5489 // If the target wants custom lowering, do so.
5490 SDOperand ShiftAmt = LegalizeOp(Node->getOperand(1));
5491 if (TLI.getOperationAction(ISD::SRL, VT) == TargetLowering::Custom) {
5492 SDOperand Op = DAG.getNode(ISD::SRL, VT, Node->getOperand(0), ShiftAmt);
5493 Op = TLI.LowerOperation(Op, DAG);
5495 // Now that the custom expander is done, expand the result, which is
5497 ExpandOp(Op, Lo, Hi);
5502 // If we can emit an efficient shift operation, do so now.
5503 if (ExpandShift(ISD::SRL, Node->getOperand(0), ShiftAmt, Lo, Hi))
5506 // If this target supports SRL_PARTS, use it.
5507 TargetLowering::LegalizeAction Action =
5508 TLI.getOperationAction(ISD::SRL_PARTS, NVT);
5509 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) ||
5510 Action == TargetLowering::Custom) {
5511 ExpandShiftParts(ISD::SRL_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi);
5515 // Otherwise, emit a libcall.
5516 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::SRL_I64), Node,
5517 false/*lshr is unsigned*/, Hi);
5523 // If the target wants to custom expand this, let them.
5524 if (TLI.getOperationAction(Node->getOpcode(), VT) ==
5525 TargetLowering::Custom) {
5526 Op = TLI.LowerOperation(Op, DAG);
5528 ExpandOp(Op, Lo, Hi);
5533 // Expand the subcomponents.
5534 SDOperand LHSL, LHSH, RHSL, RHSH;
5535 ExpandOp(Node->getOperand(0), LHSL, LHSH);
5536 ExpandOp(Node->getOperand(1), RHSL, RHSH);
5537 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag);
5538 SDOperand LoOps[2], HiOps[3];
5543 if (Node->getOpcode() == ISD::ADD) {
5544 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2);
5545 HiOps[2] = Lo.getValue(1);
5546 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3);
5548 Lo = DAG.getNode(ISD::SUBC, VTList, LoOps, 2);
5549 HiOps[2] = Lo.getValue(1);
5550 Hi = DAG.getNode(ISD::SUBE, VTList, HiOps, 3);
5557 // Expand the subcomponents.
5558 SDOperand LHSL, LHSH, RHSL, RHSH;
5559 ExpandOp(Node->getOperand(0), LHSL, LHSH);
5560 ExpandOp(Node->getOperand(1), RHSL, RHSH);
5561 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag);
5562 SDOperand LoOps[2] = { LHSL, RHSL };
5563 SDOperand HiOps[3] = { LHSH, RHSH };
5565 if (Node->getOpcode() == ISD::ADDC) {
5566 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2);
5567 HiOps[2] = Lo.getValue(1);
5568 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3);
5570 Lo = DAG.getNode(ISD::SUBC, VTList, LoOps, 2);
5571 HiOps[2] = Lo.getValue(1);
5572 Hi = DAG.getNode(ISD::SUBE, VTList, HiOps, 3);
5574 // Remember that we legalized the flag.
5575 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Hi.getValue(1)));
5580 // Expand the subcomponents.
5581 SDOperand LHSL, LHSH, RHSL, RHSH;
5582 ExpandOp(Node->getOperand(0), LHSL, LHSH);
5583 ExpandOp(Node->getOperand(1), RHSL, RHSH);
5584 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag);
5585 SDOperand LoOps[3] = { LHSL, RHSL, Node->getOperand(2) };
5586 SDOperand HiOps[3] = { LHSH, RHSH };
5588 Lo = DAG.getNode(Node->getOpcode(), VTList, LoOps, 3);
5589 HiOps[2] = Lo.getValue(1);
5590 Hi = DAG.getNode(Node->getOpcode(), VTList, HiOps, 3);
5592 // Remember that we legalized the flag.
5593 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Hi.getValue(1)));
5597 // If the target wants to custom expand this, let them.
5598 if (TLI.getOperationAction(ISD::MUL, VT) == TargetLowering::Custom) {
5599 SDOperand New = TLI.LowerOperation(Op, DAG);
5601 ExpandOp(New, Lo, Hi);
5606 bool HasMULHS = TLI.isOperationLegal(ISD::MULHS, NVT);
5607 bool HasMULHU = TLI.isOperationLegal(ISD::MULHU, NVT);
5608 if (HasMULHS || HasMULHU) {
5609 SDOperand LL, LH, RL, RH;
5610 ExpandOp(Node->getOperand(0), LL, LH);
5611 ExpandOp(Node->getOperand(1), RL, RH);
5612 unsigned SH = MVT::getSizeInBits(RH.getValueType())-1;
5613 // FIXME: Move this to the dag combiner.
5614 // MULHS implicitly sign extends its inputs. Check to see if ExpandOp
5615 // extended the sign bit of the low half through the upper half, and if so
5616 // emit a MULHS instead of the alternate sequence that is valid for any
5617 // i64 x i64 multiply.
5619 // is RH an extension of the sign bit of RL?
5620 RH.getOpcode() == ISD::SRA && RH.getOperand(0) == RL &&
5621 RH.getOperand(1).getOpcode() == ISD::Constant &&
5622 cast<ConstantSDNode>(RH.getOperand(1))->getValue() == SH &&
5623 // is LH an extension of the sign bit of LL?
5624 LH.getOpcode() == ISD::SRA && LH.getOperand(0) == LL &&
5625 LH.getOperand(1).getOpcode() == ISD::Constant &&
5626 cast<ConstantSDNode>(LH.getOperand(1))->getValue() == SH) {
5628 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL);
5630 Hi = DAG.getNode(ISD::MULHS, NVT, LL, RL);
5632 } else if (HasMULHU) {
5634 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL);
5637 Hi = DAG.getNode(ISD::MULHU, NVT, LL, RL);
5638 RH = DAG.getNode(ISD::MUL, NVT, LL, RH);
5639 LH = DAG.getNode(ISD::MUL, NVT, LH, RL);
5640 Hi = DAG.getNode(ISD::ADD, NVT, Hi, RH);
5641 Hi = DAG.getNode(ISD::ADD, NVT, Hi, LH);
5646 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::MUL_I64), Node,
5647 false/*sign irrelevant*/, Hi);
5651 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::SDIV_I64), Node, true, Hi);
5654 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::UDIV_I64), Node, true, Hi);
5657 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::SREM_I64), Node, true, Hi);
5660 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::UREM_I64), Node, true, Hi);
5664 Lo = ExpandLibCall(TLI.getLibcallName((VT == MVT::f32)
5665 ? RTLIB::ADD_F32 : RTLIB::ADD_F64),
5669 Lo = ExpandLibCall(TLI.getLibcallName((VT == MVT::f32)
5670 ? RTLIB::SUB_F32 : RTLIB::SUB_F64),
5674 Lo = ExpandLibCall(TLI.getLibcallName((VT == MVT::f32)
5675 ? RTLIB::MUL_F32 : RTLIB::MUL_F64),
5679 Lo = ExpandLibCall(TLI.getLibcallName((VT == MVT::f32)
5680 ? RTLIB::DIV_F32 : RTLIB::DIV_F64),
5683 case ISD::FP_EXTEND:
5684 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::FPEXT_F32_F64), Node, true,Hi);
5687 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::FPROUND_F64_F32),Node,true,Hi);
5690 Lo = ExpandLibCall(TLI.getLibcallName((VT == MVT::f32)
5691 ? RTLIB::POWI_F32 : RTLIB::POWI_F64),
5697 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
5698 switch(Node->getOpcode()) {
5700 LC = (VT == MVT::f32) ? RTLIB::SQRT_F32 : RTLIB::SQRT_F64;
5703 LC = (VT == MVT::f32) ? RTLIB::SIN_F32 : RTLIB::SIN_F64;
5706 LC = (VT == MVT::f32) ? RTLIB::COS_F32 : RTLIB::COS_F64;
5708 default: assert(0 && "Unreachable!");
5710 Lo = ExpandLibCall(TLI.getLibcallName(LC), Node, false, Hi);
5714 SDOperand Mask = (VT == MVT::f64)
5715 ? DAG.getConstantFP(BitsToDouble(~(1ULL << 63)), VT)
5716 : DAG.getConstantFP(BitsToFloat(~(1U << 31)), VT);
5717 Mask = DAG.getNode(ISD::BIT_CONVERT, NVT, Mask);
5718 Lo = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0));
5719 Lo = DAG.getNode(ISD::AND, NVT, Lo, Mask);
5720 if (getTypeAction(NVT) == Expand)
5721 ExpandOp(Lo, Lo, Hi);
5725 SDOperand Mask = (VT == MVT::f64)
5726 ? DAG.getConstantFP(BitsToDouble(1ULL << 63), VT)
5727 : DAG.getConstantFP(BitsToFloat(1U << 31), VT);
5728 Mask = DAG.getNode(ISD::BIT_CONVERT, NVT, Mask);
5729 Lo = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0));
5730 Lo = DAG.getNode(ISD::XOR, NVT, Lo, Mask);
5731 if (getTypeAction(NVT) == Expand)
5732 ExpandOp(Lo, Lo, Hi);
5735 case ISD::FCOPYSIGN: {
5736 Lo = ExpandFCOPYSIGNToBitwiseOps(Node, NVT, DAG, TLI);
5737 if (getTypeAction(NVT) == Expand)
5738 ExpandOp(Lo, Lo, Hi);
5741 case ISD::SINT_TO_FP:
5742 case ISD::UINT_TO_FP: {
5743 bool isSigned = Node->getOpcode() == ISD::SINT_TO_FP;
5744 MVT::ValueType SrcVT = Node->getOperand(0).getValueType();
5746 if (Node->getOperand(0).getValueType() == MVT::i64) {
5748 LC = isSigned ? RTLIB::SINTTOFP_I64_F32 : RTLIB::UINTTOFP_I64_F32;
5749 else if (VT == MVT::f64)
5750 LC = isSigned ? RTLIB::SINTTOFP_I64_F64 : RTLIB::UINTTOFP_I64_F64;
5751 else if (VT == MVT::f80 || VT == MVT::f128 || VT == MVT::ppcf128) {
5753 LC = RTLIB::SINTTOFP_I64_LD;
5757 LC = isSigned ? RTLIB::SINTTOFP_I32_F32 : RTLIB::UINTTOFP_I32_F32;
5759 LC = isSigned ? RTLIB::SINTTOFP_I32_F64 : RTLIB::UINTTOFP_I32_F64;
5762 // Promote the operand if needed.
5763 if (getTypeAction(SrcVT) == Promote) {
5764 SDOperand Tmp = PromoteOp(Node->getOperand(0));
5766 ? DAG.getNode(ISD::SIGN_EXTEND_INREG, Tmp.getValueType(), Tmp,
5767 DAG.getValueType(SrcVT))
5768 : DAG.getZeroExtendInReg(Tmp, SrcVT);
5769 Node = DAG.UpdateNodeOperands(Op, Tmp).Val;
5772 const char *LibCall = TLI.getLibcallName(LC);
5774 Lo = ExpandLibCall(TLI.getLibcallName(LC), Node, isSigned, Hi);
5776 Lo = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP, VT,
5777 Node->getOperand(0));
5778 if (getTypeAction(Lo.getValueType()) == Expand)
5779 ExpandOp(Lo, Lo, Hi);
5785 // Make sure the resultant values have been legalized themselves, unless this
5786 // is a type that requires multi-step expansion.
5787 if (getTypeAction(NVT) != Expand && NVT != MVT::isVoid) {
5788 Lo = LegalizeOp(Lo);
5790 // Don't legalize the high part if it is expanded to a single node.
5791 Hi = LegalizeOp(Hi);
5794 // Remember in a map if the values will be reused later.
5795 bool isNew = ExpandedNodes.insert(std::make_pair(Op, std::make_pair(Lo, Hi)));
5796 assert(isNew && "Value already expanded?!?");
5799 /// SplitVectorOp - Given an operand of vector type, break it down into
5800 /// two smaller values, still of vector type.
5801 void SelectionDAGLegalize::SplitVectorOp(SDOperand Op, SDOperand &Lo,
5803 assert(MVT::isVector(Op.getValueType()) && "Cannot split non-vector type!");
5804 SDNode *Node = Op.Val;
5805 unsigned NumElements = MVT::getVectorNumElements(Node->getValueType(0));
5806 assert(NumElements > 1 && "Cannot split a single element vector!");
5807 unsigned NewNumElts = NumElements/2;
5808 MVT::ValueType NewEltVT = MVT::getVectorElementType(Node->getValueType(0));
5809 MVT::ValueType NewVT = MVT::getVectorType(NewEltVT, NewNumElts);
5811 // See if we already split it.
5812 std::map<SDOperand, std::pair<SDOperand, SDOperand> >::iterator I
5813 = SplitNodes.find(Op);
5814 if (I != SplitNodes.end()) {
5815 Lo = I->second.first;
5816 Hi = I->second.second;
5820 switch (Node->getOpcode()) {
5825 assert(0 && "Unhandled operation in SplitVectorOp!");
5826 case ISD::BUILD_PAIR:
5827 Lo = Node->getOperand(0);
5828 Hi = Node->getOperand(1);
5830 case ISD::BUILD_VECTOR: {
5831 SmallVector<SDOperand, 8> LoOps(Node->op_begin(),
5832 Node->op_begin()+NewNumElts);
5833 Lo = DAG.getNode(ISD::BUILD_VECTOR, NewVT, &LoOps[0], LoOps.size());
5835 SmallVector<SDOperand, 8> HiOps(Node->op_begin()+NewNumElts,
5837 Hi = DAG.getNode(ISD::BUILD_VECTOR, NewVT, &HiOps[0], HiOps.size());
5840 case ISD::CONCAT_VECTORS: {
5841 unsigned NewNumSubvectors = Node->getNumOperands() / 2;
5842 if (NewNumSubvectors == 1) {
5843 Lo = Node->getOperand(0);
5844 Hi = Node->getOperand(1);
5846 SmallVector<SDOperand, 8> LoOps(Node->op_begin(),
5847 Node->op_begin()+NewNumSubvectors);
5848 Lo = DAG.getNode(ISD::CONCAT_VECTORS, NewVT, &LoOps[0], LoOps.size());
5850 SmallVector<SDOperand, 8> HiOps(Node->op_begin()+NewNumSubvectors,
5852 Hi = DAG.getNode(ISD::CONCAT_VECTORS, NewVT, &HiOps[0], HiOps.size());
5868 SDOperand LL, LH, RL, RH;
5869 SplitVectorOp(Node->getOperand(0), LL, LH);
5870 SplitVectorOp(Node->getOperand(1), RL, RH);
5872 Lo = DAG.getNode(Node->getOpcode(), NewVT, LL, RL);
5873 Hi = DAG.getNode(Node->getOpcode(), NewVT, LH, RH);
5877 LoadSDNode *LD = cast<LoadSDNode>(Node);
5878 SDOperand Ch = LD->getChain();
5879 SDOperand Ptr = LD->getBasePtr();
5880 const Value *SV = LD->getSrcValue();
5881 int SVOffset = LD->getSrcValueOffset();
5882 unsigned Alignment = LD->getAlignment();
5883 bool isVolatile = LD->isVolatile();
5885 Lo = DAG.getLoad(NewVT, Ch, Ptr, SV, SVOffset, isVolatile, Alignment);
5886 unsigned IncrementSize = NewNumElts * MVT::getSizeInBits(NewEltVT)/8;
5887 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
5888 getIntPtrConstant(IncrementSize));
5889 SVOffset += IncrementSize;
5890 if (Alignment > IncrementSize)
5891 Alignment = IncrementSize;
5892 Hi = DAG.getLoad(NewVT, Ch, Ptr, SV, SVOffset, isVolatile, Alignment);
5894 // Build a factor node to remember that this load is independent of the
5896 SDOperand TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
5899 // Remember that we legalized the chain.
5900 AddLegalizedOperand(Op.getValue(1), LegalizeOp(TF));
5903 case ISD::BIT_CONVERT: {
5904 // We know the result is a vector. The input may be either a vector or a
5906 SDOperand InOp = Node->getOperand(0);
5907 if (!MVT::isVector(InOp.getValueType()) ||
5908 MVT::getVectorNumElements(InOp.getValueType()) == 1) {
5909 // The input is a scalar or single-element vector.
5910 // Lower to a store/load so that it can be split.
5911 // FIXME: this could be improved probably.
5912 SDOperand Ptr = CreateStackTemporary(InOp.getValueType());
5914 SDOperand St = DAG.getStore(DAG.getEntryNode(),
5915 InOp, Ptr, NULL, 0);
5916 InOp = DAG.getLoad(Op.getValueType(), St, Ptr, NULL, 0);
5918 // Split the vector and convert each of the pieces now.
5919 SplitVectorOp(InOp, Lo, Hi);
5920 Lo = DAG.getNode(ISD::BIT_CONVERT, NewVT, Lo);
5921 Hi = DAG.getNode(ISD::BIT_CONVERT, NewVT, Hi);
5926 // Remember in a map if the values will be reused later.
5928 SplitNodes.insert(std::make_pair(Op, std::make_pair(Lo, Hi))).second;
5929 assert(isNew && "Value already split?!?");
5933 /// ScalarizeVectorOp - Given an operand of single-element vector type
5934 /// (e.g. v1f32), convert it into the equivalent operation that returns a
5935 /// scalar (e.g. f32) value.
5936 SDOperand SelectionDAGLegalize::ScalarizeVectorOp(SDOperand Op) {
5937 assert(MVT::isVector(Op.getValueType()) &&
5938 "Bad ScalarizeVectorOp invocation!");
5939 SDNode *Node = Op.Val;
5940 MVT::ValueType NewVT = MVT::getVectorElementType(Op.getValueType());
5941 assert(MVT::getVectorNumElements(Op.getValueType()) == 1);
5943 // See if we already scalarized it.
5944 std::map<SDOperand, SDOperand>::iterator I = ScalarizedNodes.find(Op);
5945 if (I != ScalarizedNodes.end()) return I->second;
5948 switch (Node->getOpcode()) {
5951 Node->dump(&DAG); cerr << "\n";
5953 assert(0 && "Unknown vector operation in ScalarizeVectorOp!");
5969 Result = DAG.getNode(Node->getOpcode(),
5971 ScalarizeVectorOp(Node->getOperand(0)),
5972 ScalarizeVectorOp(Node->getOperand(1)));
5979 Result = DAG.getNode(Node->getOpcode(),
5981 ScalarizeVectorOp(Node->getOperand(0)));
5984 LoadSDNode *LD = cast<LoadSDNode>(Node);
5985 SDOperand Ch = LegalizeOp(LD->getChain()); // Legalize the chain.
5986 SDOperand Ptr = LegalizeOp(LD->getBasePtr()); // Legalize the pointer.
5988 const Value *SV = LD->getSrcValue();
5989 int SVOffset = LD->getSrcValueOffset();
5990 Result = DAG.getLoad(NewVT, Ch, Ptr, SV, SVOffset,
5991 LD->isVolatile(), LD->getAlignment());
5993 // Remember that we legalized the chain.
5994 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
5997 case ISD::BUILD_VECTOR:
5998 Result = Node->getOperand(0);
6000 case ISD::INSERT_VECTOR_ELT:
6001 // Returning the inserted scalar element.
6002 Result = Node->getOperand(1);
6004 case ISD::CONCAT_VECTORS:
6005 assert(Node->getOperand(0).getValueType() == NewVT &&
6006 "Concat of non-legal vectors not yet supported!");
6007 Result = Node->getOperand(0);
6009 case ISD::VECTOR_SHUFFLE: {
6010 // Figure out if the scalar is the LHS or RHS and return it.
6011 SDOperand EltNum = Node->getOperand(2).getOperand(0);
6012 if (cast<ConstantSDNode>(EltNum)->getValue())
6013 Result = ScalarizeVectorOp(Node->getOperand(1));
6015 Result = ScalarizeVectorOp(Node->getOperand(0));
6018 case ISD::EXTRACT_SUBVECTOR:
6019 Result = Node->getOperand(0);
6020 assert(Result.getValueType() == NewVT);
6022 case ISD::BIT_CONVERT:
6023 Result = DAG.getNode(ISD::BIT_CONVERT, NewVT, Op.getOperand(0));
6026 Result = DAG.getNode(ISD::SELECT, NewVT, Op.getOperand(0),
6027 ScalarizeVectorOp(Op.getOperand(1)),
6028 ScalarizeVectorOp(Op.getOperand(2)));
6032 if (TLI.isTypeLegal(NewVT))
6033 Result = LegalizeOp(Result);
6034 bool isNew = ScalarizedNodes.insert(std::make_pair(Op, Result)).second;
6035 assert(isNew && "Value already scalarized?");
6040 // SelectionDAG::Legalize - This is the entry point for the file.
6042 void SelectionDAG::Legalize() {
6043 if (ViewLegalizeDAGs) viewGraph();
6045 /// run - This is the main entry point to this class.
6047 SelectionDAGLegalize(*this).LegalizeDAG();