1 //===-- LegalizeDAG.cpp - Implement SelectionDAG::Legalize ----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the SelectionDAG::Legalize method.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/CodeGen/SelectionDAG.h"
15 #include "llvm/CodeGen/MachineFunction.h"
16 #include "llvm/CodeGen/MachineFrameInfo.h"
17 #include "llvm/Support/MathExtras.h"
18 #include "llvm/Target/TargetLowering.h"
19 #include "llvm/Target/TargetData.h"
20 #include "llvm/Target/TargetOptions.h"
21 #include "llvm/CallingConv.h"
22 #include "llvm/Constants.h"
27 //===----------------------------------------------------------------------===//
28 /// SelectionDAGLegalize - This takes an arbitrary SelectionDAG as input and
29 /// hacks on it until the target machine can handle it. This involves
30 /// eliminating value sizes the machine cannot handle (promoting small sizes to
31 /// large sizes or splitting up large values into small values) as well as
32 /// eliminating operations the machine cannot handle.
34 /// This code also does a small amount of optimization and recognition of idioms
35 /// as part of its processing. For example, if a target does not support a
36 /// 'setcc' instruction efficiently, but does support 'brcc' instruction, this
37 /// will attempt merge setcc and brc instructions into brcc's.
40 class SelectionDAGLegalize {
44 /// LegalizeAction - This enum indicates what action we should take for each
45 /// value type the can occur in the program.
47 Legal, // The target natively supports this value type.
48 Promote, // This should be promoted to the next larger type.
49 Expand, // This integer type should be broken into smaller pieces.
52 /// ValueTypeActions - This is a bitvector that contains two bits for each
53 /// value type, where the two bits correspond to the LegalizeAction enum.
54 /// This can be queried with "getTypeAction(VT)".
55 unsigned ValueTypeActions;
57 /// NeedsAnotherIteration - This is set when we expand a large integer
58 /// operation into smaller integer operations, but the smaller operations are
59 /// not set. This occurs only rarely in practice, for targets that don't have
60 /// 32-bit or larger integer registers.
61 bool NeedsAnotherIteration;
63 /// LegalizedNodes - For nodes that are of legal width, and that have more
64 /// than one use, this map indicates what regularized operand to use. This
65 /// allows us to avoid legalizing the same thing more than once.
66 std::map<SDOperand, SDOperand> LegalizedNodes;
68 /// PromotedNodes - For nodes that are below legal width, and that have more
69 /// than one use, this map indicates what promoted value to use. This allows
70 /// us to avoid promoting the same thing more than once.
71 std::map<SDOperand, SDOperand> PromotedNodes;
73 /// ExpandedNodes - For nodes that need to be expanded, and which have more
74 /// than one use, this map indicates which which operands are the expanded
75 /// version of the input. This allows us to avoid expanding the same node
77 std::map<SDOperand, std::pair<SDOperand, SDOperand> > ExpandedNodes;
79 void AddLegalizedOperand(SDOperand From, SDOperand To) {
80 bool isNew = LegalizedNodes.insert(std::make_pair(From, To)).second;
81 assert(isNew && "Got into the map somehow?");
83 void AddPromotedOperand(SDOperand From, SDOperand To) {
84 bool isNew = PromotedNodes.insert(std::make_pair(From, To)).second;
85 assert(isNew && "Got into the map somehow?");
90 SelectionDAGLegalize(SelectionDAG &DAG);
92 /// Run - While there is still lowering to do, perform a pass over the DAG.
93 /// Most regularization can be done in a single pass, but targets that require
94 /// large values to be split into registers multiple times (e.g. i64 -> 4x
95 /// i16) require iteration for these values (the first iteration will demote
96 /// to i32, the second will demote to i16).
99 NeedsAnotherIteration = false;
101 } while (NeedsAnotherIteration);
104 /// getTypeAction - Return how we should legalize values of this type, either
105 /// it is already legal or we need to expand it into multiple registers of
106 /// smaller integer type, or we need to promote it to a larger type.
107 LegalizeAction getTypeAction(MVT::ValueType VT) const {
108 return (LegalizeAction)((ValueTypeActions >> (2*VT)) & 3);
111 /// isTypeLegal - Return true if this type is legal on this target.
113 bool isTypeLegal(MVT::ValueType VT) const {
114 return getTypeAction(VT) == Legal;
120 SDOperand LegalizeOp(SDOperand O);
121 void ExpandOp(SDOperand O, SDOperand &Lo, SDOperand &Hi);
122 SDOperand PromoteOp(SDOperand O);
124 SDOperand ExpandLibCall(const char *Name, SDNode *Node,
126 SDOperand ExpandIntToFP(bool isSigned, MVT::ValueType DestTy,
129 SDOperand ExpandLegalINT_TO_FP(bool isSigned,
131 MVT::ValueType DestVT);
132 SDOperand PromoteLegalINT_TO_FP(SDOperand LegalOp, MVT::ValueType DestVT,
134 SDOperand PromoteLegalFP_TO_INT(SDOperand LegalOp, MVT::ValueType DestVT,
137 bool ExpandShift(unsigned Opc, SDOperand Op, SDOperand Amt,
138 SDOperand &Lo, SDOperand &Hi);
139 void ExpandShiftParts(unsigned NodeOp, SDOperand Op, SDOperand Amt,
140 SDOperand &Lo, SDOperand &Hi);
141 void ExpandByParts(unsigned NodeOp, SDOperand LHS, SDOperand RHS,
142 SDOperand &Lo, SDOperand &Hi);
144 void SpliceCallInto(const SDOperand &CallResult, SDNode *OutChain);
146 SDOperand getIntPtrConstant(uint64_t Val) {
147 return DAG.getConstant(Val, TLI.getPointerTy());
153 SelectionDAGLegalize::SelectionDAGLegalize(SelectionDAG &dag)
154 : TLI(dag.getTargetLoweringInfo()), DAG(dag),
155 ValueTypeActions(TLI.getValueTypeActions()) {
156 assert(MVT::LAST_VALUETYPE <= 16 &&
157 "Too many value types for ValueTypeActions to hold!");
160 /// ExpandLegalINT_TO_FP - This function is responsible for legalizing a
161 /// INT_TO_FP operation of the specified operand when the target requests that
162 /// we expand it. At this point, we know that the result and operand types are
163 /// legal for the target.
164 SDOperand SelectionDAGLegalize::ExpandLegalINT_TO_FP(bool isSigned,
166 MVT::ValueType DestVT) {
167 if (Op0.getValueType() == MVT::i32) {
168 // simple 32-bit [signed|unsigned] integer to float/double expansion
170 // get the stack frame index of a 8 byte buffer
171 MachineFunction &MF = DAG.getMachineFunction();
172 int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8);
173 // get address of 8 byte buffer
174 SDOperand StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy());
175 // word offset constant for Hi/Lo address computation
176 SDOperand WordOff = DAG.getConstant(sizeof(int), TLI.getPointerTy());
177 // set up Hi and Lo (into buffer) address based on endian
179 if (TLI.isLittleEndian()) {
180 Hi = DAG.getNode(ISD::ADD, TLI.getPointerTy(), StackSlot, WordOff);
184 Lo = DAG.getNode(ISD::ADD, TLI.getPointerTy(), StackSlot, WordOff);
186 // if signed map to unsigned space
189 // constant used to invert sign bit (signed to unsigned mapping)
190 SDOperand SignBit = DAG.getConstant(0x80000000u, MVT::i32);
191 Op0Mapped = DAG.getNode(ISD::XOR, MVT::i32, Op0, SignBit);
195 // store the lo of the constructed double - based on integer input
196 SDOperand Store1 = DAG.getNode(ISD::STORE, MVT::Other, DAG.getEntryNode(),
197 Op0Mapped, Lo, DAG.getSrcValue(NULL));
198 // initial hi portion of constructed double
199 SDOperand InitialHi = DAG.getConstant(0x43300000u, MVT::i32);
200 // store the hi of the constructed double - biased exponent
201 SDOperand Store2 = DAG.getNode(ISD::STORE, MVT::Other, Store1,
202 InitialHi, Hi, DAG.getSrcValue(NULL));
203 // load the constructed double
204 SDOperand Load = DAG.getLoad(MVT::f64, Store2, StackSlot,
205 DAG.getSrcValue(NULL));
206 // FP constant to bias correct the final result
207 SDOperand Bias = DAG.getConstantFP(isSigned ?
208 BitsToDouble(0x4330000080000000ULL)
209 : BitsToDouble(0x4330000000000000ULL),
212 SDOperand Sub = DAG.getNode(ISD::FSUB, MVT::f64, Load, Bias);
215 // handle final rounding
216 if (DestVT == MVT::f64) {
220 // if f32 then cast to f32
221 Result = DAG.getNode(ISD::FP_ROUND, MVT::f32, Sub);
223 NeedsAnotherIteration = true;
226 assert(!isSigned && "Legalize cannot Expand SINT_TO_FP for i64 yet");
227 SDOperand Tmp1 = DAG.getNode(ISD::SINT_TO_FP, DestVT, Op0);
229 SDOperand SignSet = DAG.getSetCC(TLI.getSetCCResultTy(), Op0,
230 DAG.getConstant(0, Op0.getValueType()),
232 SDOperand Zero = getIntPtrConstant(0), Four = getIntPtrConstant(4);
233 SDOperand CstOffset = DAG.getNode(ISD::SELECT, Zero.getValueType(),
234 SignSet, Four, Zero);
236 // If the sign bit of the integer is set, the large number will be treated
237 // as a negative number. To counteract this, the dynamic code adds an
238 // offset depending on the data type.
240 switch (Op0.getValueType()) {
241 default: assert(0 && "Unsupported integer type!");
242 case MVT::i8 : FF = 0x43800000ULL; break; // 2^8 (as a float)
243 case MVT::i16: FF = 0x47800000ULL; break; // 2^16 (as a float)
244 case MVT::i32: FF = 0x4F800000ULL; break; // 2^32 (as a float)
245 case MVT::i64: FF = 0x5F800000ULL; break; // 2^64 (as a float)
247 if (TLI.isLittleEndian()) FF <<= 32;
248 static Constant *FudgeFactor = ConstantUInt::get(Type::ULongTy, FF);
250 SDOperand CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy());
251 CPIdx = DAG.getNode(ISD::ADD, TLI.getPointerTy(), CPIdx, CstOffset);
252 SDOperand FudgeInReg;
253 if (DestVT == MVT::f32)
254 FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx,
255 DAG.getSrcValue(NULL));
257 assert(DestVT == MVT::f64 && "Unexpected conversion");
258 FudgeInReg = LegalizeOp(DAG.getExtLoad(ISD::EXTLOAD, MVT::f64,
259 DAG.getEntryNode(), CPIdx,
260 DAG.getSrcValue(NULL), MVT::f32));
263 NeedsAnotherIteration = true;
264 return DAG.getNode(ISD::FADD, DestVT, Tmp1, FudgeInReg);
267 /// PromoteLegalINT_TO_FP - This function is responsible for legalizing a
268 /// *INT_TO_FP operation of the specified operand when the target requests that
269 /// we promote it. At this point, we know that the result and operand types are
270 /// legal for the target, and that there is a legal UINT_TO_FP or SINT_TO_FP
271 /// operation that takes a larger input.
272 SDOperand SelectionDAGLegalize::PromoteLegalINT_TO_FP(SDOperand LegalOp,
273 MVT::ValueType DestVT,
275 // First step, figure out the appropriate *INT_TO_FP operation to use.
276 MVT::ValueType NewInTy = LegalOp.getValueType();
278 unsigned OpToUse = 0;
280 // Scan for the appropriate larger type to use.
282 NewInTy = (MVT::ValueType)(NewInTy+1);
283 assert(MVT::isInteger(NewInTy) && "Ran out of possibilities!");
285 // If the target supports SINT_TO_FP of this type, use it.
286 switch (TLI.getOperationAction(ISD::SINT_TO_FP, NewInTy)) {
288 case TargetLowering::Legal:
289 if (!TLI.isTypeLegal(NewInTy))
290 break; // Can't use this datatype.
292 case TargetLowering::Custom:
293 OpToUse = ISD::SINT_TO_FP;
297 if (isSigned) continue;
299 // If the target supports UINT_TO_FP of this type, use it.
300 switch (TLI.getOperationAction(ISD::UINT_TO_FP, NewInTy)) {
302 case TargetLowering::Legal:
303 if (!TLI.isTypeLegal(NewInTy))
304 break; // Can't use this datatype.
306 case TargetLowering::Custom:
307 OpToUse = ISD::UINT_TO_FP;
312 // Otherwise, try a larger type.
315 // Make sure to legalize any nodes we create here in the next pass.
316 NeedsAnotherIteration = true;
318 // Okay, we found the operation and type to use. Zero extend our input to the
319 // desired type then run the operation on it.
320 return DAG.getNode(OpToUse, DestVT,
321 DAG.getNode(isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND,
325 /// PromoteLegalFP_TO_INT - This function is responsible for legalizing a
326 /// FP_TO_*INT operation of the specified operand when the target requests that
327 /// we promote it. At this point, we know that the result and operand types are
328 /// legal for the target, and that there is a legal FP_TO_UINT or FP_TO_SINT
329 /// operation that returns a larger result.
330 SDOperand SelectionDAGLegalize::PromoteLegalFP_TO_INT(SDOperand LegalOp,
331 MVT::ValueType DestVT,
333 // First step, figure out the appropriate FP_TO*INT operation to use.
334 MVT::ValueType NewOutTy = DestVT;
336 unsigned OpToUse = 0;
338 // Scan for the appropriate larger type to use.
340 NewOutTy = (MVT::ValueType)(NewOutTy+1);
341 assert(MVT::isInteger(NewOutTy) && "Ran out of possibilities!");
343 // If the target supports FP_TO_SINT returning this type, use it.
344 switch (TLI.getOperationAction(ISD::FP_TO_SINT, NewOutTy)) {
346 case TargetLowering::Legal:
347 if (!TLI.isTypeLegal(NewOutTy))
348 break; // Can't use this datatype.
350 case TargetLowering::Custom:
351 OpToUse = ISD::FP_TO_SINT;
356 // If the target supports FP_TO_UINT of this type, use it.
357 switch (TLI.getOperationAction(ISD::FP_TO_UINT, NewOutTy)) {
359 case TargetLowering::Legal:
360 if (!TLI.isTypeLegal(NewOutTy))
361 break; // Can't use this datatype.
363 case TargetLowering::Custom:
364 OpToUse = ISD::FP_TO_UINT;
369 // Otherwise, try a larger type.
372 // Make sure to legalize any nodes we create here in the next pass.
373 NeedsAnotherIteration = true;
375 // Okay, we found the operation and type to use. Truncate the result of the
376 // extended FP_TO_*INT operation to the desired size.
377 return DAG.getNode(ISD::TRUNCATE, DestVT,
378 DAG.getNode(OpToUse, NewOutTy, LegalOp));
381 /// ComputeTopDownOrdering - Add the specified node to the Order list if it has
382 /// not been visited yet and if all of its operands have already been visited.
383 static void ComputeTopDownOrdering(SDNode *N, std::vector<SDNode*> &Order,
384 std::map<SDNode*, unsigned> &Visited) {
385 if (++Visited[N] != N->getNumOperands())
386 return; // Haven't visited all operands yet
390 if (N->hasOneUse()) { // Tail recurse in common case.
391 ComputeTopDownOrdering(*N->use_begin(), Order, Visited);
395 // Now that we have N in, add anything that uses it if all of their operands
397 for (SDNode::use_iterator UI = N->use_begin(), E = N->use_end(); UI != E;++UI)
398 ComputeTopDownOrdering(*UI, Order, Visited);
402 void SelectionDAGLegalize::LegalizeDAG() {
403 // The legalize process is inherently a bottom-up recursive process (users
404 // legalize their uses before themselves). Given infinite stack space, we
405 // could just start legalizing on the root and traverse the whole graph. In
406 // practice however, this causes us to run out of stack space on large basic
407 // blocks. To avoid this problem, compute an ordering of the nodes where each
408 // node is only legalized after all of its operands are legalized.
409 std::map<SDNode*, unsigned> Visited;
410 std::vector<SDNode*> Order;
412 // Compute ordering from all of the leaves in the graphs, those (like the
413 // entry node) that have no operands.
414 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(),
415 E = DAG.allnodes_end(); I != E; ++I) {
416 if (I->getNumOperands() == 0) {
418 ComputeTopDownOrdering(I, Order, Visited);
422 assert(Order.size() == Visited.size() &&
424 (unsigned)std::distance(DAG.allnodes_begin(), DAG.allnodes_end()) &&
425 "Error: DAG is cyclic!");
428 for (unsigned i = 0, e = Order.size(); i != e; ++i) {
429 SDNode *N = Order[i];
430 switch (getTypeAction(N->getValueType(0))) {
431 default: assert(0 && "Bad type action!");
433 LegalizeOp(SDOperand(N, 0));
436 PromoteOp(SDOperand(N, 0));
440 ExpandOp(SDOperand(N, 0), X, Y);
446 // Finally, it's possible the root changed. Get the new root.
447 SDOperand OldRoot = DAG.getRoot();
448 assert(LegalizedNodes.count(OldRoot) && "Root didn't get legalized?");
449 DAG.setRoot(LegalizedNodes[OldRoot]);
451 ExpandedNodes.clear();
452 LegalizedNodes.clear();
453 PromotedNodes.clear();
455 // Remove dead nodes now.
456 DAG.RemoveDeadNodes(OldRoot.Val);
459 SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
460 assert(isTypeLegal(Op.getValueType()) &&
461 "Caller should expand or promote operands that are not legal!");
462 SDNode *Node = Op.Val;
464 // If this operation defines any values that cannot be represented in a
465 // register on this target, make sure to expand or promote them.
466 if (Node->getNumValues() > 1) {
467 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
468 switch (getTypeAction(Node->getValueType(i))) {
469 case Legal: break; // Nothing to do.
472 ExpandOp(Op.getValue(i), T1, T2);
473 assert(LegalizedNodes.count(Op) &&
474 "Expansion didn't add legal operands!");
475 return LegalizedNodes[Op];
478 PromoteOp(Op.getValue(i));
479 assert(LegalizedNodes.count(Op) &&
480 "Expansion didn't add legal operands!");
481 return LegalizedNodes[Op];
485 // Note that LegalizeOp may be reentered even from single-use nodes, which
486 // means that we always must cache transformed nodes.
487 std::map<SDOperand, SDOperand>::iterator I = LegalizedNodes.find(Op);
488 if (I != LegalizedNodes.end()) return I->second;
490 SDOperand Tmp1, Tmp2, Tmp3, Tmp4;
492 SDOperand Result = Op;
494 switch (Node->getOpcode()) {
496 if (Node->getOpcode() >= ISD::BUILTIN_OP_END) {
497 // If this is a target node, legalize it by legalizing the operands then
498 // passing it through.
499 std::vector<SDOperand> Ops;
500 bool Changed = false;
501 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
502 Ops.push_back(LegalizeOp(Node->getOperand(i)));
503 Changed = Changed || Node->getOperand(i) != Ops.back();
506 if (Node->getNumValues() == 1)
507 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Ops);
509 std::vector<MVT::ValueType> VTs(Node->value_begin(),
511 Result = DAG.getNode(Node->getOpcode(), VTs, Ops);
514 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
515 AddLegalizedOperand(Op.getValue(i), Result.getValue(i));
516 return Result.getValue(Op.ResNo);
518 // Otherwise this is an unhandled builtin node. splat.
519 std::cerr << "NODE: "; Node->dump(); std::cerr << "\n";
520 assert(0 && "Do not know how to legalize this operator!");
522 case ISD::EntryToken:
523 case ISD::FrameIndex:
524 case ISD::TargetFrameIndex:
526 case ISD::TargetConstant:
527 case ISD::GlobalAddress:
528 case ISD::ExternalSymbol:
529 case ISD::ConstantPool: // Nothing to do.
530 case ISD::BasicBlock:
534 assert(isTypeLegal(Node->getValueType(0)) && "This must be legal!");
536 case ISD::AssertSext:
537 case ISD::AssertZext:
538 Tmp1 = LegalizeOp(Node->getOperand(0));
539 if (Tmp1 != Node->getOperand(0))
540 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1,
541 Node->getOperand(1));
543 case ISD::CopyFromReg:
544 Tmp1 = LegalizeOp(Node->getOperand(0));
545 if (Tmp1 != Node->getOperand(0))
546 Result = DAG.getCopyFromReg(Tmp1,
547 cast<RegisterSDNode>(Node->getOperand(1))->getReg(),
548 Node->getValueType(0));
550 Result = Op.getValue(0);
552 // Since CopyFromReg produces two values, make sure to remember that we
553 // legalized both of them.
554 AddLegalizedOperand(Op.getValue(0), Result);
555 AddLegalizedOperand(Op.getValue(1), Result.getValue(1));
556 return Result.getValue(Op.ResNo);
557 case ISD::ImplicitDef:
558 Tmp1 = LegalizeOp(Node->getOperand(0));
559 if (Tmp1 != Node->getOperand(0))
560 Result = DAG.getNode(ISD::ImplicitDef, MVT::Other,
561 Tmp1, Node->getOperand(1));
564 MVT::ValueType VT = Op.getValueType();
565 switch (TLI.getOperationAction(ISD::UNDEF, VT)) {
566 default: assert(0 && "This action is not supported yet!");
567 case TargetLowering::Expand:
568 case TargetLowering::Promote:
569 if (MVT::isInteger(VT))
570 Result = DAG.getConstant(0, VT);
571 else if (MVT::isFloatingPoint(VT))
572 Result = DAG.getConstantFP(0, VT);
574 assert(0 && "Unknown value type!");
576 case TargetLowering::Legal:
582 // We know we don't need to expand constants here, constants only have one
583 // value and we check that it is fine above.
585 // FIXME: Maybe we should handle things like targets that don't support full
586 // 32-bit immediates?
588 case ISD::ConstantFP: {
589 // Spill FP immediates to the constant pool if the target cannot directly
590 // codegen them. Targets often have some immediate values that can be
591 // efficiently generated into an FP register without a load. We explicitly
592 // leave these constants as ConstantFP nodes for the target to deal with.
594 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node);
596 // Check to see if this FP immediate is already legal.
597 bool isLegal = false;
598 for (TargetLowering::legal_fpimm_iterator I = TLI.legal_fpimm_begin(),
599 E = TLI.legal_fpimm_end(); I != E; ++I)
600 if (CFP->isExactlyValue(*I)) {
606 // Otherwise we need to spill the constant to memory.
609 // If a FP immediate is precise when represented as a float, we put it
610 // into the constant pool as a float, even if it's is statically typed
612 MVT::ValueType VT = CFP->getValueType(0);
613 bool isDouble = VT == MVT::f64;
614 ConstantFP *LLVMC = ConstantFP::get(isDouble ? Type::DoubleTy :
615 Type::FloatTy, CFP->getValue());
616 if (isDouble && CFP->isExactlyValue((float)CFP->getValue()) &&
617 // Only do this if the target has a native EXTLOAD instruction from
619 TLI.isOperationLegal(ISD::EXTLOAD, MVT::f32)) {
620 LLVMC = cast<ConstantFP>(ConstantExpr::getCast(LLVMC, Type::FloatTy));
625 SDOperand CPIdx = DAG.getConstantPool(LLVMC, TLI.getPointerTy());
627 Result = DAG.getExtLoad(ISD::EXTLOAD, MVT::f64, DAG.getEntryNode(),
628 CPIdx, DAG.getSrcValue(NULL), MVT::f32);
630 Result = DAG.getLoad(VT, DAG.getEntryNode(), CPIdx,
631 DAG.getSrcValue(NULL));
636 case ISD::TokenFactor:
637 if (Node->getNumOperands() == 2) {
638 bool Changed = false;
639 SDOperand Op0 = LegalizeOp(Node->getOperand(0));
640 SDOperand Op1 = LegalizeOp(Node->getOperand(1));
641 if (Op0 != Node->getOperand(0) || Op1 != Node->getOperand(1))
642 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, Op0, Op1);
644 std::vector<SDOperand> Ops;
645 bool Changed = false;
646 // Legalize the operands.
647 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
648 SDOperand Op = Node->getOperand(i);
649 Ops.push_back(LegalizeOp(Op));
650 Changed |= Ops[i] != Op;
653 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, Ops);
657 case ISD::CALLSEQ_START:
658 case ISD::CALLSEQ_END:
659 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
660 // Do not try to legalize the target-specific arguments (#1+)
661 Tmp2 = Node->getOperand(0);
663 Node->setAdjCallChain(Tmp1);
665 // Note that we do not create new CALLSEQ_DOWN/UP nodes here. These
666 // nodes are treated specially and are mutated in place. This makes the dag
667 // legalization process more efficient and also makes libcall insertion
670 case ISD::DYNAMIC_STACKALLOC:
671 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
672 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the size.
673 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the alignment.
674 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1) ||
675 Tmp3 != Node->getOperand(2)) {
676 std::vector<MVT::ValueType> VTs(Node->value_begin(), Node->value_end());
677 std::vector<SDOperand> Ops;
678 Ops.push_back(Tmp1); Ops.push_back(Tmp2); Ops.push_back(Tmp3);
679 Result = DAG.getNode(ISD::DYNAMIC_STACKALLOC, VTs, Ops);
681 Result = Op.getValue(0);
683 // Since this op produces two values, make sure to remember that we
684 // legalized both of them.
685 AddLegalizedOperand(SDOperand(Node, 0), Result);
686 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
687 return Result.getValue(Op.ResNo);
691 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
692 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the callee.
694 bool Changed = false;
695 std::vector<SDOperand> Ops;
696 for (unsigned i = 2, e = Node->getNumOperands(); i != e; ++i) {
697 Ops.push_back(LegalizeOp(Node->getOperand(i)));
698 Changed |= Ops.back() != Node->getOperand(i);
701 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1) || Changed) {
702 std::vector<MVT::ValueType> RetTyVTs;
703 RetTyVTs.reserve(Node->getNumValues());
704 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
705 RetTyVTs.push_back(Node->getValueType(i));
706 Result = SDOperand(DAG.getCall(RetTyVTs, Tmp1, Tmp2, Ops,
707 Node->getOpcode() == ISD::TAILCALL), 0);
709 Result = Result.getValue(0);
711 // Since calls produce multiple values, make sure to remember that we
712 // legalized all of them.
713 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
714 AddLegalizedOperand(SDOperand(Node, i), Result.getValue(i));
715 return Result.getValue(Op.ResNo);
718 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
719 if (Tmp1 != Node->getOperand(0))
720 Result = DAG.getNode(ISD::BR, MVT::Other, Tmp1, Node->getOperand(1));
724 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
726 switch (getTypeAction(Node->getOperand(1).getValueType())) {
727 case Expand: assert(0 && "It's impossible to expand bools");
729 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the condition.
732 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the condition.
736 switch (TLI.getOperationAction(ISD::BRCOND, MVT::Other)) {
737 default: assert(0 && "This action is not supported yet!");
738 case TargetLowering::Expand:
739 // Expand brcond's setcc into its constituent parts and create a BR_CC
741 if (Tmp2.getOpcode() == ISD::SETCC) {
742 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1, Tmp2.getOperand(2),
743 Tmp2.getOperand(0), Tmp2.getOperand(1),
744 Node->getOperand(2));
746 // Make sure the condition is either zero or one. It may have been
747 // promoted from something else.
748 Tmp2 = DAG.getZeroExtendInReg(Tmp2, MVT::i1);
750 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1,
751 DAG.getCondCode(ISD::SETNE), Tmp2,
752 DAG.getConstant(0, Tmp2.getValueType()),
753 Node->getOperand(2));
756 case TargetLowering::Legal:
757 // Basic block destination (Op#2) is always legal.
758 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1))
759 Result = DAG.getNode(ISD::BRCOND, MVT::Other, Tmp1, Tmp2,
760 Node->getOperand(2));
765 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
767 if (isTypeLegal(Node->getOperand(2).getValueType())) {
768 Tmp2 = LegalizeOp(Node->getOperand(2)); // LHS
769 Tmp3 = LegalizeOp(Node->getOperand(3)); // RHS
770 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(2) ||
771 Tmp3 != Node->getOperand(3)) {
772 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1, Node->getOperand(1),
773 Tmp2, Tmp3, Node->getOperand(4));
777 Tmp2 = LegalizeOp(DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(),
778 Node->getOperand(2), // LHS
779 Node->getOperand(3), // RHS
780 Node->getOperand(1)));
781 // If we get a SETCC back from legalizing the SETCC node we just
782 // created, then use its LHS, RHS, and CC directly in creating a new
783 // node. Otherwise, select between the true and false value based on
784 // comparing the result of the legalized with zero.
785 if (Tmp2.getOpcode() == ISD::SETCC) {
786 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1, Tmp2.getOperand(2),
787 Tmp2.getOperand(0), Tmp2.getOperand(1),
788 Node->getOperand(4));
790 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1,
791 DAG.getCondCode(ISD::SETNE),
792 Tmp2, DAG.getConstant(0, Tmp2.getValueType()),
793 Node->getOperand(4));
797 case ISD::BRCONDTWOWAY:
798 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
799 switch (getTypeAction(Node->getOperand(1).getValueType())) {
800 case Expand: assert(0 && "It's impossible to expand bools");
802 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the condition.
805 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the condition.
808 // If this target does not support BRCONDTWOWAY, lower it to a BRCOND/BR
810 switch (TLI.getOperationAction(ISD::BRCONDTWOWAY, MVT::Other)) {
811 case TargetLowering::Promote:
812 default: assert(0 && "This action is not supported yet!");
813 case TargetLowering::Legal:
814 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1)) {
815 std::vector<SDOperand> Ops;
818 Ops.push_back(Node->getOperand(2));
819 Ops.push_back(Node->getOperand(3));
820 Result = DAG.getNode(ISD::BRCONDTWOWAY, MVT::Other, Ops);
823 case TargetLowering::Expand:
824 // If BRTWOWAY_CC is legal for this target, then simply expand this node
825 // to that. Otherwise, skip BRTWOWAY_CC and expand directly to a
827 if (TLI.isOperationLegal(ISD::BRTWOWAY_CC, MVT::Other)) {
828 if (Tmp2.getOpcode() == ISD::SETCC) {
829 Result = DAG.getBR2Way_CC(Tmp1, Tmp2.getOperand(2),
830 Tmp2.getOperand(0), Tmp2.getOperand(1),
831 Node->getOperand(2), Node->getOperand(3));
833 Result = DAG.getBR2Way_CC(Tmp1, DAG.getCondCode(ISD::SETNE), Tmp2,
834 DAG.getConstant(0, Tmp2.getValueType()),
835 Node->getOperand(2), Node->getOperand(3));
838 Result = DAG.getNode(ISD::BRCOND, MVT::Other, Tmp1, Tmp2,
839 Node->getOperand(2));
840 Result = DAG.getNode(ISD::BR, MVT::Other, Result, Node->getOperand(3));
845 case ISD::BRTWOWAY_CC:
846 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
847 if (isTypeLegal(Node->getOperand(2).getValueType())) {
848 Tmp2 = LegalizeOp(Node->getOperand(2)); // LHS
849 Tmp3 = LegalizeOp(Node->getOperand(3)); // RHS
850 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(2) ||
851 Tmp3 != Node->getOperand(3)) {
852 Result = DAG.getBR2Way_CC(Tmp1, Node->getOperand(1), Tmp2, Tmp3,
853 Node->getOperand(4), Node->getOperand(5));
857 Tmp2 = LegalizeOp(DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(),
858 Node->getOperand(2), // LHS
859 Node->getOperand(3), // RHS
860 Node->getOperand(1)));
861 // If this target does not support BRTWOWAY_CC, lower it to a BRCOND/BR
863 switch (TLI.getOperationAction(ISD::BRTWOWAY_CC, MVT::Other)) {
864 default: assert(0 && "This action is not supported yet!");
865 case TargetLowering::Legal:
866 // If we get a SETCC back from legalizing the SETCC node we just
867 // created, then use its LHS, RHS, and CC directly in creating a new
868 // node. Otherwise, select between the true and false value based on
869 // comparing the result of the legalized with zero.
870 if (Tmp2.getOpcode() == ISD::SETCC) {
871 Result = DAG.getBR2Way_CC(Tmp1, Tmp2.getOperand(2),
872 Tmp2.getOperand(0), Tmp2.getOperand(1),
873 Node->getOperand(4), Node->getOperand(5));
875 Result = DAG.getBR2Way_CC(Tmp1, DAG.getCondCode(ISD::SETNE), Tmp2,
876 DAG.getConstant(0, Tmp2.getValueType()),
877 Node->getOperand(4), Node->getOperand(5));
880 case TargetLowering::Expand:
881 Result = DAG.getNode(ISD::BRCOND, MVT::Other, Tmp1, Tmp2,
882 Node->getOperand(4));
883 Result = DAG.getNode(ISD::BR, MVT::Other, Result, Node->getOperand(5));
889 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
890 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
892 if (Tmp1 != Node->getOperand(0) ||
893 Tmp2 != Node->getOperand(1))
894 Result = DAG.getLoad(Node->getValueType(0), Tmp1, Tmp2,
895 Node->getOperand(2));
897 Result = SDOperand(Node, 0);
899 // Since loads produce two values, make sure to remember that we legalized
901 AddLegalizedOperand(SDOperand(Node, 0), Result);
902 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
903 return Result.getValue(Op.ResNo);
907 case ISD::ZEXTLOAD: {
908 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
909 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
911 MVT::ValueType SrcVT = cast<VTSDNode>(Node->getOperand(3))->getVT();
912 switch (TLI.getOperationAction(Node->getOpcode(), SrcVT)) {
913 default: assert(0 && "This action is not supported yet!");
914 case TargetLowering::Promote:
915 assert(SrcVT == MVT::i1 && "Can only promote EXTLOAD from i1 -> i8!");
916 Result = DAG.getExtLoad(Node->getOpcode(), Node->getValueType(0),
917 Tmp1, Tmp2, Node->getOperand(2), MVT::i8);
918 // Since loads produce two values, make sure to remember that we legalized
920 AddLegalizedOperand(SDOperand(Node, 0), Result);
921 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
922 return Result.getValue(Op.ResNo);
924 case TargetLowering::Legal:
925 if (Tmp1 != Node->getOperand(0) ||
926 Tmp2 != Node->getOperand(1))
927 Result = DAG.getExtLoad(Node->getOpcode(), Node->getValueType(0),
928 Tmp1, Tmp2, Node->getOperand(2), SrcVT);
930 Result = SDOperand(Node, 0);
932 // Since loads produce two values, make sure to remember that we legalized
934 AddLegalizedOperand(SDOperand(Node, 0), Result);
935 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
936 return Result.getValue(Op.ResNo);
937 case TargetLowering::Expand:
938 //f64 = EXTLOAD f32 should expand to LOAD, FP_EXTEND
939 if (SrcVT == MVT::f32 && Node->getValueType(0) == MVT::f64) {
940 SDOperand Load = DAG.getLoad(SrcVT, Tmp1, Tmp2, Node->getOperand(2));
941 Result = DAG.getNode(ISD::FP_EXTEND, Node->getValueType(0), Load);
943 return Load.getValue(1);
946 assert(Node->getOpcode() != ISD::EXTLOAD &&
947 "EXTLOAD should always be supported!");
948 // Turn the unsupported load into an EXTLOAD followed by an explicit
949 // zero/sign extend inreg.
950 Result = DAG.getExtLoad(ISD::EXTLOAD, Node->getValueType(0),
951 Tmp1, Tmp2, Node->getOperand(2), SrcVT);
953 if (Node->getOpcode() == ISD::SEXTLOAD)
954 ValRes = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(),
955 Result, DAG.getValueType(SrcVT));
957 ValRes = DAG.getZeroExtendInReg(Result, SrcVT);
958 AddLegalizedOperand(SDOperand(Node, 0), ValRes);
959 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
961 return Result.getValue(1);
964 assert(0 && "Unreachable");
966 case ISD::EXTRACT_ELEMENT: {
967 MVT::ValueType OpTy = Node->getOperand(0).getValueType();
968 switch (getTypeAction(OpTy)) {
970 assert(0 && "EXTRACT_ELEMENT action for type unimplemented!");
973 if (cast<ConstantSDNode>(Node->getOperand(1))->getValue()) {
975 Result = DAG.getNode(ISD::SRL, OpTy, Node->getOperand(0),
976 DAG.getConstant(MVT::getSizeInBits(OpTy)/2,
977 TLI.getShiftAmountTy()));
978 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), Result);
981 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0),
982 Node->getOperand(0));
984 Result = LegalizeOp(Result);
987 // Get both the low and high parts.
988 ExpandOp(Node->getOperand(0), Tmp1, Tmp2);
989 if (cast<ConstantSDNode>(Node->getOperand(1))->getValue())
990 Result = Tmp2; // 1 -> Hi
992 Result = Tmp1; // 0 -> Lo
999 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1001 assert(isTypeLegal(Node->getOperand(2).getValueType()) &&
1002 "Register type must be legal!");
1003 // Legalize the incoming value (must be legal).
1004 Tmp2 = LegalizeOp(Node->getOperand(2));
1005 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(2))
1006 Result = DAG.getNode(ISD::CopyToReg, MVT::Other, Tmp1,
1007 Node->getOperand(1), Tmp2);
1011 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1012 switch (Node->getNumOperands()) {
1014 switch (getTypeAction(Node->getOperand(1).getValueType())) {
1016 Tmp2 = LegalizeOp(Node->getOperand(1));
1017 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1))
1018 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Tmp2);
1022 ExpandOp(Node->getOperand(1), Lo, Hi);
1023 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Hi);
1027 Tmp2 = PromoteOp(Node->getOperand(1));
1028 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Tmp2);
1033 if (Tmp1 != Node->getOperand(0))
1034 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1);
1036 default: { // ret <values>
1037 std::vector<SDOperand> NewValues;
1038 NewValues.push_back(Tmp1);
1039 for (unsigned i = 1, e = Node->getNumOperands(); i != e; ++i)
1040 switch (getTypeAction(Node->getOperand(i).getValueType())) {
1042 NewValues.push_back(LegalizeOp(Node->getOperand(i)));
1046 ExpandOp(Node->getOperand(i), Lo, Hi);
1047 NewValues.push_back(Lo);
1048 NewValues.push_back(Hi);
1052 assert(0 && "Can't promote multiple return value yet!");
1054 Result = DAG.getNode(ISD::RET, MVT::Other, NewValues);
1060 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1061 Tmp2 = LegalizeOp(Node->getOperand(2)); // Legalize the pointer.
1063 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr'
1064 if (ConstantFPSDNode *CFP =dyn_cast<ConstantFPSDNode>(Node->getOperand(1))){
1065 if (CFP->getValueType(0) == MVT::f32) {
1066 Result = DAG.getNode(ISD::STORE, MVT::Other, Tmp1,
1067 DAG.getConstant(FloatToBits(CFP->getValue()),
1070 Node->getOperand(3));
1072 assert(CFP->getValueType(0) == MVT::f64 && "Unknown FP type!");
1073 Result = DAG.getNode(ISD::STORE, MVT::Other, Tmp1,
1074 DAG.getConstant(DoubleToBits(CFP->getValue()),
1077 Node->getOperand(3));
1082 switch (getTypeAction(Node->getOperand(1).getValueType())) {
1084 SDOperand Val = LegalizeOp(Node->getOperand(1));
1085 if (Val != Node->getOperand(1) || Tmp1 != Node->getOperand(0) ||
1086 Tmp2 != Node->getOperand(2))
1087 Result = DAG.getNode(ISD::STORE, MVT::Other, Tmp1, Val, Tmp2,
1088 Node->getOperand(3));
1092 // Truncate the value and store the result.
1093 Tmp3 = PromoteOp(Node->getOperand(1));
1094 Result = DAG.getNode(ISD::TRUNCSTORE, MVT::Other, Tmp1, Tmp3, Tmp2,
1095 Node->getOperand(3),
1096 DAG.getValueType(Node->getOperand(1).getValueType()));
1101 ExpandOp(Node->getOperand(1), Lo, Hi);
1103 if (!TLI.isLittleEndian())
1106 Lo = DAG.getNode(ISD::STORE, MVT::Other, Tmp1, Lo, Tmp2,
1107 Node->getOperand(3));
1108 unsigned IncrementSize = MVT::getSizeInBits(Hi.getValueType())/8;
1109 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2,
1110 getIntPtrConstant(IncrementSize));
1111 assert(isTypeLegal(Tmp2.getValueType()) &&
1112 "Pointers must be legal!");
1113 //Again, claiming both parts of the store came form the same Instr
1114 Hi = DAG.getNode(ISD::STORE, MVT::Other, Tmp1, Hi, Tmp2,
1115 Node->getOperand(3));
1116 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi);
1121 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1122 if (Tmp1 != Node->getOperand(0))
1123 Result = DAG.getNode(ISD::PCMARKER, MVT::Other, Tmp1,Node->getOperand(1));
1125 case ISD::READCYCLECOUNTER:
1126 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain
1127 if (Tmp1 != Node->getOperand(0))
1128 Result = DAG.getNode(ISD::READCYCLECOUNTER, MVT::i64, Tmp1);
1130 case ISD::TRUNCSTORE:
1131 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1132 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the pointer.
1134 switch (getTypeAction(Node->getOperand(1).getValueType())) {
1136 Tmp2 = LegalizeOp(Node->getOperand(1));
1138 // The only promote case we handle is TRUNCSTORE:i1 X into
1139 // -> TRUNCSTORE:i8 (and X, 1)
1140 if (cast<VTSDNode>(Node->getOperand(4))->getVT() == MVT::i1 &&
1141 TLI.getOperationAction(ISD::TRUNCSTORE, MVT::i1) ==
1142 TargetLowering::Promote) {
1143 // Promote the bool to a mask then store.
1144 Tmp2 = DAG.getNode(ISD::AND, Tmp2.getValueType(), Tmp2,
1145 DAG.getConstant(1, Tmp2.getValueType()));
1146 Result = DAG.getNode(ISD::TRUNCSTORE, MVT::Other, Tmp1, Tmp2, Tmp3,
1147 Node->getOperand(3), DAG.getValueType(MVT::i8));
1149 } else if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1) ||
1150 Tmp3 != Node->getOperand(2)) {
1151 Result = DAG.getNode(ISD::TRUNCSTORE, MVT::Other, Tmp1, Tmp2, Tmp3,
1152 Node->getOperand(3), Node->getOperand(4));
1157 assert(0 && "Cannot handle illegal TRUNCSTORE yet!");
1161 switch (getTypeAction(Node->getOperand(0).getValueType())) {
1162 case Expand: assert(0 && "It's impossible to expand bools");
1164 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the condition.
1167 Tmp1 = PromoteOp(Node->getOperand(0)); // Promote the condition.
1170 Tmp2 = LegalizeOp(Node->getOperand(1)); // TrueVal
1171 Tmp3 = LegalizeOp(Node->getOperand(2)); // FalseVal
1173 switch (TLI.getOperationAction(ISD::SELECT, Tmp2.getValueType())) {
1174 default: assert(0 && "This action is not supported yet!");
1175 case TargetLowering::Expand:
1176 if (Tmp1.getOpcode() == ISD::SETCC) {
1177 Result = DAG.getSelectCC(Tmp1.getOperand(0), Tmp1.getOperand(1),
1179 cast<CondCodeSDNode>(Tmp1.getOperand(2))->get());
1181 // Make sure the condition is either zero or one. It may have been
1182 // promoted from something else.
1183 Tmp1 = DAG.getZeroExtendInReg(Tmp1, MVT::i1);
1184 Result = DAG.getSelectCC(Tmp1,
1185 DAG.getConstant(0, Tmp1.getValueType()),
1186 Tmp2, Tmp3, ISD::SETNE);
1189 case TargetLowering::Legal:
1190 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1) ||
1191 Tmp3 != Node->getOperand(2))
1192 Result = DAG.getNode(ISD::SELECT, Node->getValueType(0),
1195 case TargetLowering::Promote: {
1196 MVT::ValueType NVT =
1197 TLI.getTypeToPromoteTo(ISD::SELECT, Tmp2.getValueType());
1198 unsigned ExtOp, TruncOp;
1199 if (MVT::isInteger(Tmp2.getValueType())) {
1200 ExtOp = ISD::ANY_EXTEND;
1201 TruncOp = ISD::TRUNCATE;
1203 ExtOp = ISD::FP_EXTEND;
1204 TruncOp = ISD::FP_ROUND;
1206 // Promote each of the values to the new type.
1207 Tmp2 = DAG.getNode(ExtOp, NVT, Tmp2);
1208 Tmp3 = DAG.getNode(ExtOp, NVT, Tmp3);
1209 // Perform the larger operation, then round down.
1210 Result = DAG.getNode(ISD::SELECT, NVT, Tmp1, Tmp2,Tmp3);
1211 Result = DAG.getNode(TruncOp, Node->getValueType(0), Result);
1216 case ISD::SELECT_CC:
1217 Tmp3 = LegalizeOp(Node->getOperand(2)); // True
1218 Tmp4 = LegalizeOp(Node->getOperand(3)); // False
1220 if (isTypeLegal(Node->getOperand(0).getValueType())) {
1221 // Everything is legal, see if we should expand this op or something.
1222 switch (TLI.getOperationAction(ISD::SELECT_CC,
1223 Node->getOperand(0).getValueType())) {
1224 default: assert(0 && "This action is not supported yet!");
1225 case TargetLowering::Custom: {
1227 TLI.LowerOperation(DAG.getNode(ISD::SELECT_CC, Node->getValueType(0),
1228 Node->getOperand(0),
1229 Node->getOperand(1), Tmp3, Tmp4,
1230 Node->getOperand(4)), DAG);
1232 Result = LegalizeOp(Tmp);
1235 } // FALLTHROUGH if the target can't lower this operation after all.
1236 case TargetLowering::Legal:
1237 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
1238 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS
1239 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1) ||
1240 Tmp3 != Node->getOperand(2) || Tmp4 != Node->getOperand(3)) {
1241 Result = DAG.getNode(ISD::SELECT_CC, Node->getValueType(0), Tmp1, Tmp2,
1242 Tmp3, Tmp4, Node->getOperand(4));
1248 Tmp1 = LegalizeOp(DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(),
1249 Node->getOperand(0), // LHS
1250 Node->getOperand(1), // RHS
1251 Node->getOperand(4)));
1252 // If we get a SETCC back from legalizing the SETCC node we just
1253 // created, then use its LHS, RHS, and CC directly in creating a new
1254 // node. Otherwise, select between the true and false value based on
1255 // comparing the result of the legalized with zero.
1256 if (Tmp1.getOpcode() == ISD::SETCC) {
1257 Result = DAG.getNode(ISD::SELECT_CC, Tmp3.getValueType(),
1258 Tmp1.getOperand(0), Tmp1.getOperand(1),
1259 Tmp3, Tmp4, Tmp1.getOperand(2));
1261 Result = DAG.getSelectCC(Tmp1,
1262 DAG.getConstant(0, Tmp1.getValueType()),
1263 Tmp3, Tmp4, ISD::SETNE);
1268 switch (getTypeAction(Node->getOperand(0).getValueType())) {
1270 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
1271 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS
1274 Tmp1 = PromoteOp(Node->getOperand(0)); // LHS
1275 Tmp2 = PromoteOp(Node->getOperand(1)); // RHS
1277 // If this is an FP compare, the operands have already been extended.
1278 if (MVT::isInteger(Node->getOperand(0).getValueType())) {
1279 MVT::ValueType VT = Node->getOperand(0).getValueType();
1280 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT);
1282 // Otherwise, we have to insert explicit sign or zero extends. Note
1283 // that we could insert sign extends for ALL conditions, but zero extend
1284 // is cheaper on many machines (an AND instead of two shifts), so prefer
1286 switch (cast<CondCodeSDNode>(Node->getOperand(2))->get()) {
1287 default: assert(0 && "Unknown integer comparison!");
1294 // ALL of these operations will work if we either sign or zero extend
1295 // the operands (including the unsigned comparisons!). Zero extend is
1296 // usually a simpler/cheaper operation, so prefer it.
1297 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT);
1298 Tmp2 = DAG.getZeroExtendInReg(Tmp2, VT);
1304 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1,
1305 DAG.getValueType(VT));
1306 Tmp2 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp2,
1307 DAG.getValueType(VT));
1313 SDOperand LHSLo, LHSHi, RHSLo, RHSHi;
1314 ExpandOp(Node->getOperand(0), LHSLo, LHSHi);
1315 ExpandOp(Node->getOperand(1), RHSLo, RHSHi);
1316 switch (cast<CondCodeSDNode>(Node->getOperand(2))->get()) {
1320 if (ConstantSDNode *RHSCST = dyn_cast<ConstantSDNode>(RHSLo))
1321 if (RHSCST->isAllOnesValue()) {
1322 // Comparison to -1.
1323 Tmp1 = DAG.getNode(ISD::AND, LHSLo.getValueType(), LHSLo, LHSHi);
1328 Tmp1 = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSLo, RHSLo);
1329 Tmp2 = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSHi, RHSHi);
1330 Tmp1 = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp2);
1331 Tmp2 = DAG.getConstant(0, Tmp1.getValueType());
1334 // If this is a comparison of the sign bit, just look at the top part.
1336 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Node->getOperand(1)))
1337 if ((cast<CondCodeSDNode>(Node->getOperand(2))->get() == ISD::SETLT &&
1338 CST->getValue() == 0) || // X < 0
1339 (cast<CondCodeSDNode>(Node->getOperand(2))->get() == ISD::SETGT &&
1340 (CST->isAllOnesValue()))) { // X > -1
1346 // FIXME: This generated code sucks.
1347 ISD::CondCode LowCC;
1348 switch (cast<CondCodeSDNode>(Node->getOperand(2))->get()) {
1349 default: assert(0 && "Unknown integer setcc!");
1351 case ISD::SETULT: LowCC = ISD::SETULT; break;
1353 case ISD::SETUGT: LowCC = ISD::SETUGT; break;
1355 case ISD::SETULE: LowCC = ISD::SETULE; break;
1357 case ISD::SETUGE: LowCC = ISD::SETUGE; break;
1360 // Tmp1 = lo(op1) < lo(op2) // Always unsigned comparison
1361 // Tmp2 = hi(op1) < hi(op2) // Signedness depends on operands
1362 // dest = hi(op1) == hi(op2) ? Tmp1 : Tmp2;
1364 // NOTE: on targets without efficient SELECT of bools, we can always use
1365 // this identity: (B1 ? B2 : B3) --> (B1 & B2)|(!B1&B3)
1366 Tmp1 = DAG.getSetCC(Node->getValueType(0), LHSLo, RHSLo, LowCC);
1367 Tmp2 = DAG.getNode(ISD::SETCC, Node->getValueType(0), LHSHi, RHSHi,
1368 Node->getOperand(2));
1369 Result = DAG.getSetCC(Node->getValueType(0), LHSHi, RHSHi, ISD::SETEQ);
1370 Result = LegalizeOp(DAG.getNode(ISD::SELECT, Tmp1.getValueType(),
1371 Result, Tmp1, Tmp2));
1376 switch(TLI.getOperationAction(ISD::SETCC, Node->getOperand(0).getValueType())) {
1378 assert(0 && "Cannot handle this action for SETCC yet!");
1380 case TargetLowering::Promote:
1381 Result = DAG.getNode(ISD::SETCC, Node->getValueType(0), Tmp1, Tmp2,
1382 Node->getOperand(2));
1384 case TargetLowering::Legal:
1385 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1))
1386 Result = DAG.getNode(ISD::SETCC, Node->getValueType(0), Tmp1, Tmp2,
1387 Node->getOperand(2));
1389 case TargetLowering::Expand:
1390 // Expand a setcc node into a select_cc of the same condition, lhs, and
1391 // rhs that selects between const 1 (true) and const 0 (false).
1392 MVT::ValueType VT = Node->getValueType(0);
1393 Result = DAG.getNode(ISD::SELECT_CC, VT, Tmp1, Tmp2,
1394 DAG.getConstant(1, VT), DAG.getConstant(0, VT),
1395 Node->getOperand(2));
1396 Result = LegalizeOp(Result);
1403 case ISD::MEMMOVE: {
1404 Tmp1 = LegalizeOp(Node->getOperand(0)); // Chain
1405 Tmp2 = LegalizeOp(Node->getOperand(1)); // Pointer
1407 if (Node->getOpcode() == ISD::MEMSET) { // memset = ubyte
1408 switch (getTypeAction(Node->getOperand(2).getValueType())) {
1409 case Expand: assert(0 && "Cannot expand a byte!");
1411 Tmp3 = LegalizeOp(Node->getOperand(2));
1414 Tmp3 = PromoteOp(Node->getOperand(2));
1418 Tmp3 = LegalizeOp(Node->getOperand(2)); // memcpy/move = pointer,
1422 switch (getTypeAction(Node->getOperand(3).getValueType())) {
1424 // Length is too big, just take the lo-part of the length.
1426 ExpandOp(Node->getOperand(3), HiPart, Tmp4);
1430 Tmp4 = LegalizeOp(Node->getOperand(3));
1433 Tmp4 = PromoteOp(Node->getOperand(3));
1438 switch (getTypeAction(Node->getOperand(4).getValueType())) { // uint
1439 case Expand: assert(0 && "Cannot expand this yet!");
1441 Tmp5 = LegalizeOp(Node->getOperand(4));
1444 Tmp5 = PromoteOp(Node->getOperand(4));
1448 switch (TLI.getOperationAction(Node->getOpcode(), MVT::Other)) {
1449 default: assert(0 && "This action not implemented for this operation!");
1450 case TargetLowering::Custom: {
1452 TLI.LowerOperation(DAG.getNode(Node->getOpcode(), MVT::Other, Tmp1,
1453 Tmp2, Tmp3, Tmp4, Tmp5), DAG);
1455 Result = LegalizeOp(Tmp);
1458 // FALLTHROUGH if the target thinks it is legal.
1460 case TargetLowering::Legal:
1461 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1) ||
1462 Tmp3 != Node->getOperand(2) || Tmp4 != Node->getOperand(3) ||
1463 Tmp5 != Node->getOperand(4)) {
1464 std::vector<SDOperand> Ops;
1465 Ops.push_back(Tmp1); Ops.push_back(Tmp2); Ops.push_back(Tmp3);
1466 Ops.push_back(Tmp4); Ops.push_back(Tmp5);
1467 Result = DAG.getNode(Node->getOpcode(), MVT::Other, Ops);
1470 case TargetLowering::Expand: {
1471 // Otherwise, the target does not support this operation. Lower the
1472 // operation to an explicit libcall as appropriate.
1473 MVT::ValueType IntPtr = TLI.getPointerTy();
1474 const Type *IntPtrTy = TLI.getTargetData().getIntPtrType();
1475 std::vector<std::pair<SDOperand, const Type*> > Args;
1477 const char *FnName = 0;
1478 if (Node->getOpcode() == ISD::MEMSET) {
1479 Args.push_back(std::make_pair(Tmp2, IntPtrTy));
1480 // Extend the ubyte argument to be an int value for the call.
1481 Tmp3 = DAG.getNode(ISD::ZERO_EXTEND, MVT::i32, Tmp3);
1482 Args.push_back(std::make_pair(Tmp3, Type::IntTy));
1483 Args.push_back(std::make_pair(Tmp4, IntPtrTy));
1486 } else if (Node->getOpcode() == ISD::MEMCPY ||
1487 Node->getOpcode() == ISD::MEMMOVE) {
1488 Args.push_back(std::make_pair(Tmp2, IntPtrTy));
1489 Args.push_back(std::make_pair(Tmp3, IntPtrTy));
1490 Args.push_back(std::make_pair(Tmp4, IntPtrTy));
1491 FnName = Node->getOpcode() == ISD::MEMMOVE ? "memmove" : "memcpy";
1493 assert(0 && "Unknown op!");
1496 std::pair<SDOperand,SDOperand> CallResult =
1497 TLI.LowerCallTo(Tmp1, Type::VoidTy, false, CallingConv::C, false,
1498 DAG.getExternalSymbol(FnName, IntPtr), Args, DAG);
1499 Result = CallResult.second;
1500 NeedsAnotherIteration = true;
1508 Tmp1 = LegalizeOp(Node->getOperand(0));
1509 Tmp2 = LegalizeOp(Node->getOperand(1));
1511 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1)) {
1512 std::vector<MVT::ValueType> VTs(Node->value_begin(), Node->value_end());
1513 std::vector<SDOperand> Ops;
1514 Ops.push_back(Tmp1);
1515 Ops.push_back(Tmp2);
1516 Result = DAG.getNode(ISD::READPORT, VTs, Ops);
1518 Result = SDOperand(Node, 0);
1519 // Since these produce two values, make sure to remember that we legalized
1521 AddLegalizedOperand(SDOperand(Node, 0), Result);
1522 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
1523 return Result.getValue(Op.ResNo);
1524 case ISD::WRITEPORT:
1525 Tmp1 = LegalizeOp(Node->getOperand(0));
1526 Tmp2 = LegalizeOp(Node->getOperand(1));
1527 Tmp3 = LegalizeOp(Node->getOperand(2));
1528 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1) ||
1529 Tmp3 != Node->getOperand(2))
1530 Result = DAG.getNode(Node->getOpcode(), MVT::Other, Tmp1, Tmp2, Tmp3);
1534 Tmp1 = LegalizeOp(Node->getOperand(0));
1535 Tmp2 = LegalizeOp(Node->getOperand(1));
1537 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
1538 case TargetLowering::Custom:
1539 default: assert(0 && "This action not implemented for this operation!");
1540 case TargetLowering::Legal:
1541 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1)) {
1542 std::vector<MVT::ValueType> VTs(Node->value_begin(), Node->value_end());
1543 std::vector<SDOperand> Ops;
1544 Ops.push_back(Tmp1);
1545 Ops.push_back(Tmp2);
1546 Result = DAG.getNode(ISD::READPORT, VTs, Ops);
1548 Result = SDOperand(Node, 0);
1550 case TargetLowering::Expand:
1551 // Replace this with a load from memory.
1552 Result = DAG.getLoad(Node->getValueType(0), Node->getOperand(0),
1553 Node->getOperand(1), DAG.getSrcValue(NULL));
1554 Result = LegalizeOp(Result);
1558 // Since these produce two values, make sure to remember that we legalized
1560 AddLegalizedOperand(SDOperand(Node, 0), Result);
1561 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
1562 return Result.getValue(Op.ResNo);
1565 Tmp1 = LegalizeOp(Node->getOperand(0));
1566 Tmp2 = LegalizeOp(Node->getOperand(1));
1567 Tmp3 = LegalizeOp(Node->getOperand(2));
1569 switch (TLI.getOperationAction(Node->getOpcode(),
1570 Node->getOperand(1).getValueType())) {
1571 case TargetLowering::Custom:
1572 default: assert(0 && "This action not implemented for this operation!");
1573 case TargetLowering::Legal:
1574 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1) ||
1575 Tmp3 != Node->getOperand(2))
1576 Result = DAG.getNode(Node->getOpcode(), MVT::Other, Tmp1, Tmp2, Tmp3);
1578 case TargetLowering::Expand:
1579 // Replace this with a store to memory.
1580 Result = DAG.getNode(ISD::STORE, MVT::Other, Node->getOperand(0),
1581 Node->getOperand(1), Node->getOperand(2),
1582 DAG.getSrcValue(NULL));
1583 Result = LegalizeOp(Result);
1588 case ISD::ADD_PARTS:
1589 case ISD::SUB_PARTS:
1590 case ISD::SHL_PARTS:
1591 case ISD::SRA_PARTS:
1592 case ISD::SRL_PARTS: {
1593 std::vector<SDOperand> Ops;
1594 bool Changed = false;
1595 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
1596 Ops.push_back(LegalizeOp(Node->getOperand(i)));
1597 Changed |= Ops.back() != Node->getOperand(i);
1600 std::vector<MVT::ValueType> VTs(Node->value_begin(), Node->value_end());
1601 Result = DAG.getNode(Node->getOpcode(), VTs, Ops);
1604 // Since these produce multiple values, make sure to remember that we
1605 // legalized all of them.
1606 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
1607 AddLegalizedOperand(SDOperand(Node, i), Result.getValue(i));
1608 return Result.getValue(Op.ResNo);
1629 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
1630 switch (getTypeAction(Node->getOperand(1).getValueType())) {
1631 case Expand: assert(0 && "Not possible");
1633 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the RHS.
1636 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the RHS.
1639 if (Tmp1 != Node->getOperand(0) ||
1640 Tmp2 != Node->getOperand(1))
1641 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1,Tmp2);
1644 case ISD::BUILD_PAIR: {
1645 MVT::ValueType PairTy = Node->getValueType(0);
1646 // TODO: handle the case where the Lo and Hi operands are not of legal type
1647 Tmp1 = LegalizeOp(Node->getOperand(0)); // Lo
1648 Tmp2 = LegalizeOp(Node->getOperand(1)); // Hi
1649 switch (TLI.getOperationAction(ISD::BUILD_PAIR, PairTy)) {
1650 case TargetLowering::Legal:
1651 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1))
1652 Result = DAG.getNode(ISD::BUILD_PAIR, PairTy, Tmp1, Tmp2);
1654 case TargetLowering::Promote:
1655 case TargetLowering::Custom:
1656 assert(0 && "Cannot promote/custom this yet!");
1657 case TargetLowering::Expand:
1658 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, PairTy, Tmp1);
1659 Tmp2 = DAG.getNode(ISD::ANY_EXTEND, PairTy, Tmp2);
1660 Tmp2 = DAG.getNode(ISD::SHL, PairTy, Tmp2,
1661 DAG.getConstant(MVT::getSizeInBits(PairTy)/2,
1662 TLI.getShiftAmountTy()));
1663 Result = LegalizeOp(DAG.getNode(ISD::OR, PairTy, Tmp1, Tmp2));
1672 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
1673 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS
1674 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
1675 case TargetLowering::Legal:
1676 if (Tmp1 != Node->getOperand(0) ||
1677 Tmp2 != Node->getOperand(1))
1678 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1,
1681 case TargetLowering::Promote:
1682 case TargetLowering::Custom:
1683 assert(0 && "Cannot promote/custom handle this yet!");
1684 case TargetLowering::Expand:
1685 if (MVT::isInteger(Node->getValueType(0))) {
1686 MVT::ValueType VT = Node->getValueType(0);
1687 unsigned Opc = (Node->getOpcode() == ISD::UREM) ? ISD::UDIV : ISD::SDIV;
1688 Result = DAG.getNode(Opc, VT, Tmp1, Tmp2);
1689 Result = DAG.getNode(ISD::MUL, VT, Result, Tmp2);
1690 Result = DAG.getNode(ISD::SUB, VT, Tmp1, Result);
1692 // Floating point mod -> fmod libcall.
1693 const char *FnName = Node->getValueType(0) == MVT::f32 ? "fmodf":"fmod";
1695 Result = ExpandLibCall(FnName, Node, Dummy);
1704 Tmp1 = LegalizeOp(Node->getOperand(0)); // Op
1705 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
1706 case TargetLowering::Legal:
1707 if (Tmp1 != Node->getOperand(0))
1708 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1);
1710 case TargetLowering::Promote: {
1711 MVT::ValueType OVT = Tmp1.getValueType();
1712 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
1714 // Zero extend the argument.
1715 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1);
1716 // Perform the larger operation, then subtract if needed.
1717 Tmp1 = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1);
1718 switch(Node->getOpcode())
1724 //if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT)
1725 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), Tmp1,
1726 DAG.getConstant(getSizeInBits(NVT), NVT),
1728 Result = DAG.getNode(ISD::SELECT, NVT, Tmp2,
1729 DAG.getConstant(getSizeInBits(OVT),NVT), Tmp1);
1732 //Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT))
1733 Result = DAG.getNode(ISD::SUB, NVT, Tmp1,
1734 DAG.getConstant(getSizeInBits(NVT) -
1735 getSizeInBits(OVT), NVT));
1740 case TargetLowering::Custom:
1741 assert(0 && "Cannot custom handle this yet!");
1742 case TargetLowering::Expand:
1743 switch(Node->getOpcode())
1746 static const uint64_t mask[6] = {
1747 0x5555555555555555ULL, 0x3333333333333333ULL,
1748 0x0F0F0F0F0F0F0F0FULL, 0x00FF00FF00FF00FFULL,
1749 0x0000FFFF0000FFFFULL, 0x00000000FFFFFFFFULL
1751 MVT::ValueType VT = Tmp1.getValueType();
1752 MVT::ValueType ShVT = TLI.getShiftAmountTy();
1753 unsigned len = getSizeInBits(VT);
1754 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) {
1755 //x = (x & mask[i][len/8]) + (x >> (1 << i) & mask[i][len/8])
1756 Tmp2 = DAG.getConstant(mask[i], VT);
1757 Tmp3 = DAG.getConstant(1ULL << i, ShVT);
1758 Tmp1 = DAG.getNode(ISD::ADD, VT,
1759 DAG.getNode(ISD::AND, VT, Tmp1, Tmp2),
1760 DAG.getNode(ISD::AND, VT,
1761 DAG.getNode(ISD::SRL, VT, Tmp1, Tmp3),
1768 /* for now, we do this:
1773 x = x | (x >>32); // for 64-bit input
1774 return popcount(~x);
1776 but see also: http://www.hackersdelight.org/HDcode/nlz.cc */
1777 MVT::ValueType VT = Tmp1.getValueType();
1778 MVT::ValueType ShVT = TLI.getShiftAmountTy();
1779 unsigned len = getSizeInBits(VT);
1780 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) {
1781 Tmp3 = DAG.getConstant(1ULL << i, ShVT);
1782 Tmp1 = DAG.getNode(ISD::OR, VT, Tmp1,
1783 DAG.getNode(ISD::SRL, VT, Tmp1, Tmp3));
1785 Tmp3 = DAG.getNode(ISD::XOR, VT, Tmp1, DAG.getConstant(~0ULL, VT));
1786 Result = LegalizeOp(DAG.getNode(ISD::CTPOP, VT, Tmp3));
1790 // for now, we use: { return popcount(~x & (x - 1)); }
1791 // unless the target has ctlz but not ctpop, in which case we use:
1792 // { return 32 - nlz(~x & (x-1)); }
1793 // see also http://www.hackersdelight.org/HDcode/ntz.cc
1794 MVT::ValueType VT = Tmp1.getValueType();
1795 Tmp2 = DAG.getConstant(~0ULL, VT);
1796 Tmp3 = DAG.getNode(ISD::AND, VT,
1797 DAG.getNode(ISD::XOR, VT, Tmp1, Tmp2),
1798 DAG.getNode(ISD::SUB, VT, Tmp1,
1799 DAG.getConstant(1, VT)));
1800 // If ISD::CTLZ is legal and CTPOP isn't, then do that instead
1801 if (!TLI.isOperationLegal(ISD::CTPOP, VT) &&
1802 TLI.isOperationLegal(ISD::CTLZ, VT)) {
1803 Result = LegalizeOp(DAG.getNode(ISD::SUB, VT,
1804 DAG.getConstant(getSizeInBits(VT), VT),
1805 DAG.getNode(ISD::CTLZ, VT, Tmp3)));
1807 Result = LegalizeOp(DAG.getNode(ISD::CTPOP, VT, Tmp3));
1812 assert(0 && "Cannot expand this yet!");
1825 Tmp1 = LegalizeOp(Node->getOperand(0));
1826 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
1827 case TargetLowering::Legal:
1828 if (Tmp1 != Node->getOperand(0))
1829 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1);
1831 case TargetLowering::Promote:
1832 case TargetLowering::Custom:
1833 assert(0 && "Cannot promote/custom handle this yet!");
1834 case TargetLowering::Expand:
1835 switch(Node->getOpcode()) {
1837 // Expand Y = FNEG(X) -> Y = SUB -0.0, X
1838 Tmp2 = DAG.getConstantFP(-0.0, Node->getValueType(0));
1839 Result = LegalizeOp(DAG.getNode(ISD::FSUB, Node->getValueType(0),
1844 // Expand Y = FABS(X) -> Y = (X >u 0.0) ? X : fneg(X).
1845 MVT::ValueType VT = Node->getValueType(0);
1846 Tmp2 = DAG.getConstantFP(0.0, VT);
1847 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), Tmp1, Tmp2, ISD::SETUGT);
1848 Tmp3 = DAG.getNode(ISD::FNEG, VT, Tmp1);
1849 Result = DAG.getNode(ISD::SELECT, VT, Tmp2, Tmp1, Tmp3);
1850 Result = LegalizeOp(Result);
1856 MVT::ValueType VT = Node->getValueType(0);
1857 const char *FnName = 0;
1858 switch(Node->getOpcode()) {
1859 case ISD::FSQRT: FnName = VT == MVT::f32 ? "sqrtf" : "sqrt"; break;
1860 case ISD::FSIN: FnName = VT == MVT::f32 ? "sinf" : "sin"; break;
1861 case ISD::FCOS: FnName = VT == MVT::f32 ? "cosf" : "cos"; break;
1862 default: assert(0 && "Unreachable!");
1865 Result = ExpandLibCall(FnName, Node, Dummy);
1869 assert(0 && "Unreachable!");
1875 // Conversion operators. The source and destination have different types.
1876 case ISD::SINT_TO_FP:
1877 case ISD::UINT_TO_FP: {
1878 bool isSigned = Node->getOpcode() == ISD::SINT_TO_FP;
1879 switch (getTypeAction(Node->getOperand(0).getValueType())) {
1881 switch (TLI.getOperationAction(Node->getOpcode(),
1882 Node->getOperand(0).getValueType())) {
1883 default: assert(0 && "Unknown operation action!");
1884 case TargetLowering::Expand:
1885 Result = ExpandLegalINT_TO_FP(isSigned,
1886 LegalizeOp(Node->getOperand(0)),
1887 Node->getValueType(0));
1888 AddLegalizedOperand(Op, Result);
1890 case TargetLowering::Promote:
1891 Result = PromoteLegalINT_TO_FP(LegalizeOp(Node->getOperand(0)),
1892 Node->getValueType(0),
1894 AddLegalizedOperand(Op, Result);
1896 case TargetLowering::Legal:
1900 Tmp1 = LegalizeOp(Node->getOperand(0));
1901 if (Tmp1 != Node->getOperand(0))
1902 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1);
1905 Result = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP,
1906 Node->getValueType(0), Node->getOperand(0));
1910 Result = PromoteOp(Node->getOperand(0));
1911 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(),
1912 Result, DAG.getValueType(Node->getOperand(0).getValueType()));
1913 Result = DAG.getNode(ISD::SINT_TO_FP, Op.getValueType(), Result);
1915 Result = PromoteOp(Node->getOperand(0));
1916 Result = DAG.getZeroExtendInReg(Result,
1917 Node->getOperand(0).getValueType());
1918 Result = DAG.getNode(ISD::UINT_TO_FP, Op.getValueType(), Result);
1925 switch (getTypeAction(Node->getOperand(0).getValueType())) {
1927 Tmp1 = LegalizeOp(Node->getOperand(0));
1928 if (Tmp1 != Node->getOperand(0))
1929 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1);
1932 ExpandOp(Node->getOperand(0), Tmp1, Tmp2);
1934 // Since the result is legal, we should just be able to truncate the low
1935 // part of the source.
1936 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), Tmp1);
1939 Result = PromoteOp(Node->getOperand(0));
1940 Result = DAG.getNode(ISD::TRUNCATE, Op.getValueType(), Result);
1945 case ISD::FP_TO_SINT:
1946 case ISD::FP_TO_UINT:
1947 switch (getTypeAction(Node->getOperand(0).getValueType())) {
1949 Tmp1 = LegalizeOp(Node->getOperand(0));
1951 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))){
1952 default: assert(0 && "Unknown operation action!");
1953 case TargetLowering::Expand:
1954 if (Node->getOpcode() == ISD::FP_TO_UINT) {
1955 SDOperand True, False;
1956 MVT::ValueType VT = Node->getOperand(0).getValueType();
1957 MVT::ValueType NVT = Node->getValueType(0);
1958 unsigned ShiftAmt = MVT::getSizeInBits(Node->getValueType(0))-1;
1959 Tmp2 = DAG.getConstantFP((double)(1ULL << ShiftAmt), VT);
1960 Tmp3 = DAG.getSetCC(TLI.getSetCCResultTy(),
1961 Node->getOperand(0), Tmp2, ISD::SETLT);
1962 True = DAG.getNode(ISD::FP_TO_SINT, NVT, Node->getOperand(0));
1963 False = DAG.getNode(ISD::FP_TO_SINT, NVT,
1964 DAG.getNode(ISD::FSUB, VT, Node->getOperand(0),
1966 False = DAG.getNode(ISD::XOR, NVT, False,
1967 DAG.getConstant(1ULL << ShiftAmt, NVT));
1968 Result = LegalizeOp(DAG.getNode(ISD::SELECT, NVT, Tmp3, True, False));
1971 assert(0 && "Do not know how to expand FP_TO_SINT yet!");
1974 case TargetLowering::Promote:
1975 Result = PromoteLegalFP_TO_INT(Tmp1, Node->getValueType(0),
1976 Node->getOpcode() == ISD::FP_TO_SINT);
1977 AddLegalizedOperand(Op, Result);
1979 case TargetLowering::Custom: {
1981 DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1);
1982 Tmp = TLI.LowerOperation(Tmp, DAG);
1984 AddLegalizedOperand(Op, Tmp);
1985 NeedsAnotherIteration = true;
1988 // The target thinks this is legal afterall.
1992 case TargetLowering::Legal:
1996 if (Tmp1 != Node->getOperand(0))
1997 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1);
2000 assert(0 && "Shouldn't need to expand other operators here!");
2002 Result = PromoteOp(Node->getOperand(0));
2003 Result = DAG.getNode(Node->getOpcode(), Op.getValueType(), Result);
2008 case ISD::ANY_EXTEND:
2009 case ISD::ZERO_EXTEND:
2010 case ISD::SIGN_EXTEND:
2011 case ISD::FP_EXTEND:
2013 switch (getTypeAction(Node->getOperand(0).getValueType())) {
2015 Tmp1 = LegalizeOp(Node->getOperand(0));
2016 if (Tmp1 != Node->getOperand(0))
2017 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1);
2020 assert(0 && "Shouldn't need to expand other operators here!");
2023 switch (Node->getOpcode()) {
2024 case ISD::ANY_EXTEND:
2025 Result = PromoteOp(Node->getOperand(0));
2026 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Result);
2028 case ISD::ZERO_EXTEND:
2029 Result = PromoteOp(Node->getOperand(0));
2030 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Result);
2031 Result = DAG.getZeroExtendInReg(Result,
2032 Node->getOperand(0).getValueType());
2034 case ISD::SIGN_EXTEND:
2035 Result = PromoteOp(Node->getOperand(0));
2036 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Result);
2037 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(),
2039 DAG.getValueType(Node->getOperand(0).getValueType()));
2041 case ISD::FP_EXTEND:
2042 Result = PromoteOp(Node->getOperand(0));
2043 if (Result.getValueType() != Op.getValueType())
2044 // Dynamically dead while we have only 2 FP types.
2045 Result = DAG.getNode(ISD::FP_EXTEND, Op.getValueType(), Result);
2048 Result = PromoteOp(Node->getOperand(0));
2049 Result = DAG.getNode(Node->getOpcode(), Op.getValueType(), Result);
2054 case ISD::FP_ROUND_INREG:
2055 case ISD::SIGN_EXTEND_INREG: {
2056 Tmp1 = LegalizeOp(Node->getOperand(0));
2057 MVT::ValueType ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT();
2059 // If this operation is not supported, convert it to a shl/shr or load/store
2061 switch (TLI.getOperationAction(Node->getOpcode(), ExtraVT)) {
2062 default: assert(0 && "This action not supported for this op yet!");
2063 case TargetLowering::Legal:
2064 if (Tmp1 != Node->getOperand(0))
2065 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1,
2066 DAG.getValueType(ExtraVT));
2068 case TargetLowering::Expand:
2069 // If this is an integer extend and shifts are supported, do that.
2070 if (Node->getOpcode() == ISD::SIGN_EXTEND_INREG) {
2071 // NOTE: we could fall back on load/store here too for targets without
2072 // SAR. However, it is doubtful that any exist.
2073 unsigned BitsDiff = MVT::getSizeInBits(Node->getValueType(0)) -
2074 MVT::getSizeInBits(ExtraVT);
2075 SDOperand ShiftCst = DAG.getConstant(BitsDiff, TLI.getShiftAmountTy());
2076 Result = DAG.getNode(ISD::SHL, Node->getValueType(0),
2077 Node->getOperand(0), ShiftCst);
2078 Result = DAG.getNode(ISD::SRA, Node->getValueType(0),
2080 } else if (Node->getOpcode() == ISD::FP_ROUND_INREG) {
2081 // The only way we can lower this is to turn it into a STORETRUNC,
2082 // EXTLOAD pair, targetting a temporary location (a stack slot).
2084 // NOTE: there is a choice here between constantly creating new stack
2085 // slots and always reusing the same one. We currently always create
2086 // new ones, as reuse may inhibit scheduling.
2087 const Type *Ty = MVT::getTypeForValueType(ExtraVT);
2088 unsigned TySize = (unsigned)TLI.getTargetData().getTypeSize(Ty);
2089 unsigned Align = TLI.getTargetData().getTypeAlignment(Ty);
2090 MachineFunction &MF = DAG.getMachineFunction();
2092 MF.getFrameInfo()->CreateStackObject((unsigned)TySize, Align);
2093 SDOperand StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy());
2094 Result = DAG.getNode(ISD::TRUNCSTORE, MVT::Other, DAG.getEntryNode(),
2095 Node->getOperand(0), StackSlot,
2096 DAG.getSrcValue(NULL), DAG.getValueType(ExtraVT));
2097 Result = DAG.getExtLoad(ISD::EXTLOAD, Node->getValueType(0),
2098 Result, StackSlot, DAG.getSrcValue(NULL),
2101 assert(0 && "Unknown op");
2103 Result = LegalizeOp(Result);
2110 // Note that LegalizeOp may be reentered even from single-use nodes, which
2111 // means that we always must cache transformed nodes.
2112 AddLegalizedOperand(Op, Result);
2116 /// PromoteOp - Given an operation that produces a value in an invalid type,
2117 /// promote it to compute the value into a larger type. The produced value will
2118 /// have the correct bits for the low portion of the register, but no guarantee
2119 /// is made about the top bits: it may be zero, sign-extended, or garbage.
2120 SDOperand SelectionDAGLegalize::PromoteOp(SDOperand Op) {
2121 MVT::ValueType VT = Op.getValueType();
2122 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT);
2123 assert(getTypeAction(VT) == Promote &&
2124 "Caller should expand or legalize operands that are not promotable!");
2125 assert(NVT > VT && MVT::isInteger(NVT) == MVT::isInteger(VT) &&
2126 "Cannot promote to smaller type!");
2128 SDOperand Tmp1, Tmp2, Tmp3;
2131 SDNode *Node = Op.Val;
2133 std::map<SDOperand, SDOperand>::iterator I = PromotedNodes.find(Op);
2134 if (I != PromotedNodes.end()) return I->second;
2136 // Promotion needs an optimization step to clean up after it, and is not
2137 // careful to avoid operations the target does not support. Make sure that
2138 // all generated operations are legalized in the next iteration.
2139 NeedsAnotherIteration = true;
2141 switch (Node->getOpcode()) {
2142 case ISD::CopyFromReg:
2143 assert(0 && "CopyFromReg must be legal!");
2145 std::cerr << "NODE: "; Node->dump(); std::cerr << "\n";
2146 assert(0 && "Do not know how to promote this operator!");
2149 Result = DAG.getNode(ISD::UNDEF, NVT);
2153 Result = DAG.getNode(ISD::SIGN_EXTEND, NVT, Op);
2155 Result = DAG.getNode(ISD::ZERO_EXTEND, NVT, Op);
2156 assert(isa<ConstantSDNode>(Result) && "Didn't constant fold zext?");
2158 case ISD::ConstantFP:
2159 Result = DAG.getNode(ISD::FP_EXTEND, NVT, Op);
2160 assert(isa<ConstantFPSDNode>(Result) && "Didn't constant fold fp_extend?");
2164 assert(isTypeLegal(TLI.getSetCCResultTy()) && "SetCC type is not legal??");
2165 Result = DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(),Node->getOperand(0),
2166 Node->getOperand(1), Node->getOperand(2));
2167 Result = LegalizeOp(Result);
2171 switch (getTypeAction(Node->getOperand(0).getValueType())) {
2173 Result = LegalizeOp(Node->getOperand(0));
2174 assert(Result.getValueType() >= NVT &&
2175 "This truncation doesn't make sense!");
2176 if (Result.getValueType() > NVT) // Truncate to NVT instead of VT
2177 Result = DAG.getNode(ISD::TRUNCATE, NVT, Result);
2180 // The truncation is not required, because we don't guarantee anything
2181 // about high bits anyway.
2182 Result = PromoteOp(Node->getOperand(0));
2185 ExpandOp(Node->getOperand(0), Tmp1, Tmp2);
2186 // Truncate the low part of the expanded value to the result type
2187 Result = DAG.getNode(ISD::TRUNCATE, NVT, Tmp1);
2190 case ISD::SIGN_EXTEND:
2191 case ISD::ZERO_EXTEND:
2192 case ISD::ANY_EXTEND:
2193 switch (getTypeAction(Node->getOperand(0).getValueType())) {
2194 case Expand: assert(0 && "BUG: Smaller reg should have been promoted!");
2196 // Input is legal? Just do extend all the way to the larger type.
2197 Result = LegalizeOp(Node->getOperand(0));
2198 Result = DAG.getNode(Node->getOpcode(), NVT, Result);
2201 // Promote the reg if it's smaller.
2202 Result = PromoteOp(Node->getOperand(0));
2203 // The high bits are not guaranteed to be anything. Insert an extend.
2204 if (Node->getOpcode() == ISD::SIGN_EXTEND)
2205 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Result,
2206 DAG.getValueType(Node->getOperand(0).getValueType()));
2207 else if (Node->getOpcode() == ISD::ZERO_EXTEND)
2208 Result = DAG.getZeroExtendInReg(Result,
2209 Node->getOperand(0).getValueType());
2214 case ISD::FP_EXTEND:
2215 assert(0 && "Case not implemented. Dynamically dead with 2 FP types!");
2217 switch (getTypeAction(Node->getOperand(0).getValueType())) {
2218 case Expand: assert(0 && "BUG: Cannot expand FP regs!");
2219 case Promote: assert(0 && "Unreachable with 2 FP types!");
2221 // Input is legal? Do an FP_ROUND_INREG.
2222 Result = LegalizeOp(Node->getOperand(0));
2223 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
2224 DAG.getValueType(VT));
2229 case ISD::SINT_TO_FP:
2230 case ISD::UINT_TO_FP:
2231 switch (getTypeAction(Node->getOperand(0).getValueType())) {
2233 Result = LegalizeOp(Node->getOperand(0));
2234 // No extra round required here.
2235 Result = DAG.getNode(Node->getOpcode(), NVT, Result);
2239 Result = PromoteOp(Node->getOperand(0));
2240 if (Node->getOpcode() == ISD::SINT_TO_FP)
2241 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(),
2243 DAG.getValueType(Node->getOperand(0).getValueType()));
2245 Result = DAG.getZeroExtendInReg(Result,
2246 Node->getOperand(0).getValueType());
2247 // No extra round required here.
2248 Result = DAG.getNode(Node->getOpcode(), NVT, Result);
2251 Result = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP, NVT,
2252 Node->getOperand(0));
2253 // Round if we cannot tolerate excess precision.
2254 if (NoExcessFPPrecision)
2255 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
2256 DAG.getValueType(VT));
2261 case ISD::FP_TO_SINT:
2262 case ISD::FP_TO_UINT:
2263 switch (getTypeAction(Node->getOperand(0).getValueType())) {
2265 Tmp1 = LegalizeOp(Node->getOperand(0));
2268 // The input result is prerounded, so we don't have to do anything
2270 Tmp1 = PromoteOp(Node->getOperand(0));
2273 assert(0 && "not implemented");
2275 // If we're promoting a UINT to a larger size, check to see if the new node
2276 // will be legal. If it isn't, check to see if FP_TO_SINT is legal, since
2277 // we can use that instead. This allows us to generate better code for
2278 // FP_TO_UINT for small destination sizes on targets where FP_TO_UINT is not
2279 // legal, such as PowerPC.
2280 if (Node->getOpcode() == ISD::FP_TO_UINT &&
2281 !TLI.isOperationLegal(ISD::FP_TO_UINT, NVT) &&
2282 (TLI.isOperationLegal(ISD::FP_TO_SINT, NVT) ||
2283 TLI.getOperationAction(ISD::FP_TO_SINT, NVT)==TargetLowering::Custom)){
2284 Result = DAG.getNode(ISD::FP_TO_SINT, NVT, Tmp1);
2286 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
2292 Tmp1 = PromoteOp(Node->getOperand(0));
2293 assert(Tmp1.getValueType() == NVT);
2294 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
2295 // NOTE: we do not have to do any extra rounding here for
2296 // NoExcessFPPrecision, because we know the input will have the appropriate
2297 // precision, and these operations don't modify precision at all.
2303 Tmp1 = PromoteOp(Node->getOperand(0));
2304 assert(Tmp1.getValueType() == NVT);
2305 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
2306 if(NoExcessFPPrecision)
2307 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
2308 DAG.getValueType(VT));
2317 // The input may have strange things in the top bits of the registers, but
2318 // these operations don't care. They may have weird bits going out, but
2319 // that too is okay if they are integer operations.
2320 Tmp1 = PromoteOp(Node->getOperand(0));
2321 Tmp2 = PromoteOp(Node->getOperand(1));
2322 assert(Tmp1.getValueType() == NVT && Tmp2.getValueType() == NVT);
2323 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
2328 // The input may have strange things in the top bits of the registers, but
2329 // these operations don't care.
2330 Tmp1 = PromoteOp(Node->getOperand(0));
2331 Tmp2 = PromoteOp(Node->getOperand(1));
2332 assert(Tmp1.getValueType() == NVT && Tmp2.getValueType() == NVT);
2333 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
2335 // Floating point operations will give excess precision that we may not be
2336 // able to tolerate. If we DO allow excess precision, just leave it,
2337 // otherwise excise it.
2338 // FIXME: Why would we need to round FP ops more than integer ones?
2339 // Is Round(Add(Add(A,B),C)) != Round(Add(Round(Add(A,B)), C))
2340 if (NoExcessFPPrecision)
2341 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
2342 DAG.getValueType(VT));
2347 // These operators require that their input be sign extended.
2348 Tmp1 = PromoteOp(Node->getOperand(0));
2349 Tmp2 = PromoteOp(Node->getOperand(1));
2350 if (MVT::isInteger(NVT)) {
2351 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1,
2352 DAG.getValueType(VT));
2353 Tmp2 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp2,
2354 DAG.getValueType(VT));
2356 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
2358 // Perform FP_ROUND: this is probably overly pessimistic.
2359 if (MVT::isFloatingPoint(NVT) && NoExcessFPPrecision)
2360 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
2361 DAG.getValueType(VT));
2365 // These operators require that their input be fp extended.
2366 Tmp1 = PromoteOp(Node->getOperand(0));
2367 Tmp2 = PromoteOp(Node->getOperand(1));
2368 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
2370 // Perform FP_ROUND: this is probably overly pessimistic.
2371 if (NoExcessFPPrecision)
2372 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
2373 DAG.getValueType(VT));
2378 // These operators require that their input be zero extended.
2379 Tmp1 = PromoteOp(Node->getOperand(0));
2380 Tmp2 = PromoteOp(Node->getOperand(1));
2381 assert(MVT::isInteger(NVT) && "Operators don't apply to FP!");
2382 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT);
2383 Tmp2 = DAG.getZeroExtendInReg(Tmp2, VT);
2384 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
2388 Tmp1 = PromoteOp(Node->getOperand(0));
2389 Tmp2 = LegalizeOp(Node->getOperand(1));
2390 Result = DAG.getNode(ISD::SHL, NVT, Tmp1, Tmp2);
2393 // The input value must be properly sign extended.
2394 Tmp1 = PromoteOp(Node->getOperand(0));
2395 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1,
2396 DAG.getValueType(VT));
2397 Tmp2 = LegalizeOp(Node->getOperand(1));
2398 Result = DAG.getNode(ISD::SRA, NVT, Tmp1, Tmp2);
2401 // The input value must be properly zero extended.
2402 Tmp1 = PromoteOp(Node->getOperand(0));
2403 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT);
2404 Tmp2 = LegalizeOp(Node->getOperand(1));
2405 Result = DAG.getNode(ISD::SRL, NVT, Tmp1, Tmp2);
2408 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2409 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
2410 Result = DAG.getExtLoad(ISD::EXTLOAD, NVT, Tmp1, Tmp2,
2411 Node->getOperand(2), VT);
2412 // Remember that we legalized the chain.
2413 AddLegalizedOperand(Op.getValue(1), Result.getValue(1));
2418 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2419 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
2420 Result = DAG.getExtLoad(Node->getOpcode(), NVT, Tmp1, Tmp2,
2421 Node->getOperand(2),
2422 cast<VTSDNode>(Node->getOperand(3))->getVT());
2423 // Remember that we legalized the chain.
2424 AddLegalizedOperand(Op.getValue(1), Result.getValue(1));
2427 switch (getTypeAction(Node->getOperand(0).getValueType())) {
2428 case Expand: assert(0 && "It's impossible to expand bools");
2430 Tmp1 = LegalizeOp(Node->getOperand(0));// Legalize the condition.
2433 Tmp1 = PromoteOp(Node->getOperand(0)); // Promote the condition.
2436 Tmp2 = PromoteOp(Node->getOperand(1)); // Legalize the op0
2437 Tmp3 = PromoteOp(Node->getOperand(2)); // Legalize the op1
2438 Result = DAG.getNode(ISD::SELECT, NVT, Tmp1, Tmp2, Tmp3);
2440 case ISD::SELECT_CC:
2441 Tmp2 = PromoteOp(Node->getOperand(2)); // True
2442 Tmp3 = PromoteOp(Node->getOperand(3)); // False
2443 Result = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0),
2444 Node->getOperand(1), Tmp2, Tmp3,
2445 Node->getOperand(4));
2449 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2450 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the callee.
2452 std::vector<SDOperand> Ops;
2453 for (unsigned i = 2, e = Node->getNumOperands(); i != e; ++i)
2454 Ops.push_back(LegalizeOp(Node->getOperand(i)));
2456 assert(Node->getNumValues() == 2 && Op.ResNo == 0 &&
2457 "Can only promote single result calls");
2458 std::vector<MVT::ValueType> RetTyVTs;
2459 RetTyVTs.reserve(2);
2460 RetTyVTs.push_back(NVT);
2461 RetTyVTs.push_back(MVT::Other);
2462 SDNode *NC = DAG.getCall(RetTyVTs, Tmp1, Tmp2, Ops,
2463 Node->getOpcode() == ISD::TAILCALL);
2464 Result = SDOperand(NC, 0);
2466 // Insert the new chain mapping.
2467 AddLegalizedOperand(Op.getValue(1), Result.getValue(1));
2473 Tmp1 = Node->getOperand(0);
2474 //Zero extend the argument
2475 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1);
2476 // Perform the larger operation, then subtract if needed.
2477 Tmp1 = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
2478 switch(Node->getOpcode())
2484 //if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT)
2485 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), Tmp1,
2486 DAG.getConstant(getSizeInBits(NVT), NVT), ISD::SETEQ);
2487 Result = DAG.getNode(ISD::SELECT, NVT, Tmp2,
2488 DAG.getConstant(getSizeInBits(VT),NVT), Tmp1);
2491 //Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT))
2492 Result = DAG.getNode(ISD::SUB, NVT, Tmp1,
2493 DAG.getConstant(getSizeInBits(NVT) -
2494 getSizeInBits(VT), NVT));
2500 assert(Result.Val && "Didn't set a result!");
2501 AddPromotedOperand(Op, Result);
2505 /// ExpandAddSub - Find a clever way to expand this add operation into
2507 void SelectionDAGLegalize::
2508 ExpandByParts(unsigned NodeOp, SDOperand LHS, SDOperand RHS,
2509 SDOperand &Lo, SDOperand &Hi) {
2510 // Expand the subcomponents.
2511 SDOperand LHSL, LHSH, RHSL, RHSH;
2512 ExpandOp(LHS, LHSL, LHSH);
2513 ExpandOp(RHS, RHSL, RHSH);
2515 std::vector<SDOperand> Ops;
2516 Ops.push_back(LHSL);
2517 Ops.push_back(LHSH);
2518 Ops.push_back(RHSL);
2519 Ops.push_back(RHSH);
2520 std::vector<MVT::ValueType> VTs(2, LHSL.getValueType());
2521 Lo = DAG.getNode(NodeOp, VTs, Ops);
2522 Hi = Lo.getValue(1);
2525 void SelectionDAGLegalize::ExpandShiftParts(unsigned NodeOp,
2526 SDOperand Op, SDOperand Amt,
2527 SDOperand &Lo, SDOperand &Hi) {
2528 // Expand the subcomponents.
2529 SDOperand LHSL, LHSH;
2530 ExpandOp(Op, LHSL, LHSH);
2532 std::vector<SDOperand> Ops;
2533 Ops.push_back(LHSL);
2534 Ops.push_back(LHSH);
2536 std::vector<MVT::ValueType> VTs(2, LHSL.getValueType());
2537 Lo = DAG.getNode(NodeOp, VTs, Ops);
2538 Hi = Lo.getValue(1);
2542 /// ExpandShift - Try to find a clever way to expand this shift operation out to
2543 /// smaller elements. If we can't find a way that is more efficient than a
2544 /// libcall on this target, return false. Otherwise, return true with the
2545 /// low-parts expanded into Lo and Hi.
2546 bool SelectionDAGLegalize::ExpandShift(unsigned Opc, SDOperand Op,SDOperand Amt,
2547 SDOperand &Lo, SDOperand &Hi) {
2548 assert((Opc == ISD::SHL || Opc == ISD::SRA || Opc == ISD::SRL) &&
2549 "This is not a shift!");
2551 MVT::ValueType NVT = TLI.getTypeToTransformTo(Op.getValueType());
2552 SDOperand ShAmt = LegalizeOp(Amt);
2553 MVT::ValueType ShTy = ShAmt.getValueType();
2554 unsigned VTBits = MVT::getSizeInBits(Op.getValueType());
2555 unsigned NVTBits = MVT::getSizeInBits(NVT);
2557 // Handle the case when Amt is an immediate. Other cases are currently broken
2558 // and are disabled.
2559 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Amt.Val)) {
2560 unsigned Cst = CN->getValue();
2561 // Expand the incoming operand to be shifted, so that we have its parts
2563 ExpandOp(Op, InL, InH);
2567 Lo = DAG.getConstant(0, NVT);
2568 Hi = DAG.getConstant(0, NVT);
2569 } else if (Cst > NVTBits) {
2570 Lo = DAG.getConstant(0, NVT);
2571 Hi = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Cst-NVTBits,ShTy));
2572 } else if (Cst == NVTBits) {
2573 Lo = DAG.getConstant(0, NVT);
2576 Lo = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Cst, ShTy));
2577 Hi = DAG.getNode(ISD::OR, NVT,
2578 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(Cst, ShTy)),
2579 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(NVTBits-Cst, ShTy)));
2584 Lo = DAG.getConstant(0, NVT);
2585 Hi = DAG.getConstant(0, NVT);
2586 } else if (Cst > NVTBits) {
2587 Lo = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Cst-NVTBits,ShTy));
2588 Hi = DAG.getConstant(0, NVT);
2589 } else if (Cst == NVTBits) {
2591 Hi = DAG.getConstant(0, NVT);
2593 Lo = DAG.getNode(ISD::OR, NVT,
2594 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(Cst, ShTy)),
2595 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(NVTBits-Cst, ShTy)));
2596 Hi = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Cst, ShTy));
2601 Hi = Lo = DAG.getNode(ISD::SRA, NVT, InH,
2602 DAG.getConstant(NVTBits-1, ShTy));
2603 } else if (Cst > NVTBits) {
2604 Lo = DAG.getNode(ISD::SRA, NVT, InH,
2605 DAG.getConstant(Cst-NVTBits, ShTy));
2606 Hi = DAG.getNode(ISD::SRA, NVT, InH,
2607 DAG.getConstant(NVTBits-1, ShTy));
2608 } else if (Cst == NVTBits) {
2610 Hi = DAG.getNode(ISD::SRA, NVT, InH,
2611 DAG.getConstant(NVTBits-1, ShTy));
2613 Lo = DAG.getNode(ISD::OR, NVT,
2614 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(Cst, ShTy)),
2615 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(NVTBits-Cst, ShTy)));
2616 Hi = DAG.getNode(ISD::SRA, NVT, InH, DAG.getConstant(Cst, ShTy));
2621 // FIXME: The following code for expanding shifts using ISD::SELECT is buggy,
2622 // so disable it for now. Currently targets are handling this via SHL_PARTS
2626 // If we have an efficient select operation (or if the selects will all fold
2627 // away), lower to some complex code, otherwise just emit the libcall.
2628 if (!TLI.isOperationLegal(ISD::SELECT, NVT) && !isa<ConstantSDNode>(Amt))
2632 ExpandOp(Op, InL, InH);
2633 SDOperand NAmt = DAG.getNode(ISD::SUB, ShTy, // NAmt = 32-ShAmt
2634 DAG.getConstant(NVTBits, ShTy), ShAmt);
2636 // Compare the unmasked shift amount against 32.
2637 SDOperand Cond = DAG.getSetCC(TLI.getSetCCResultTy(), ShAmt,
2638 DAG.getConstant(NVTBits, ShTy), ISD::SETGE);
2640 if (TLI.getShiftAmountFlavor() != TargetLowering::Mask) {
2641 ShAmt = DAG.getNode(ISD::AND, ShTy, ShAmt, // ShAmt &= 31
2642 DAG.getConstant(NVTBits-1, ShTy));
2643 NAmt = DAG.getNode(ISD::AND, ShTy, NAmt, // NAmt &= 31
2644 DAG.getConstant(NVTBits-1, ShTy));
2647 if (Opc == ISD::SHL) {
2648 SDOperand T1 = DAG.getNode(ISD::OR, NVT,// T1 = (Hi << Amt) | (Lo >> NAmt)
2649 DAG.getNode(ISD::SHL, NVT, InH, ShAmt),
2650 DAG.getNode(ISD::SRL, NVT, InL, NAmt));
2651 SDOperand T2 = DAG.getNode(ISD::SHL, NVT, InL, ShAmt); // T2 = Lo << Amt&31
2653 Hi = DAG.getNode(ISD::SELECT, NVT, Cond, T2, T1);
2654 Lo = DAG.getNode(ISD::SELECT, NVT, Cond, DAG.getConstant(0, NVT), T2);
2656 SDOperand HiLoPart = DAG.getNode(ISD::SELECT, NVT,
2657 DAG.getSetCC(TLI.getSetCCResultTy(), NAmt,
2658 DAG.getConstant(32, ShTy),
2660 DAG.getConstant(0, NVT),
2661 DAG.getNode(ISD::SHL, NVT, InH, NAmt));
2662 SDOperand T1 = DAG.getNode(ISD::OR, NVT,// T1 = (Hi << NAmt) | (Lo >> Amt)
2664 DAG.getNode(ISD::SRL, NVT, InL, ShAmt));
2665 SDOperand T2 = DAG.getNode(Opc, NVT, InH, ShAmt); // T2 = InH >> ShAmt&31
2668 if (Opc == ISD::SRA)
2669 HiPart = DAG.getNode(ISD::SRA, NVT, InH,
2670 DAG.getConstant(NVTBits-1, ShTy));
2672 HiPart = DAG.getConstant(0, NVT);
2673 Lo = DAG.getNode(ISD::SELECT, NVT, Cond, T2, T1);
2674 Hi = DAG.getNode(ISD::SELECT, NVT, Cond, HiPart, T2);
2679 /// FindLatestCallSeqStart - Scan up the dag to find the latest (highest
2680 /// NodeDepth) node that is an CallSeqStart operation and occurs later than
2682 static void FindLatestCallSeqStart(SDNode *Node, SDNode *&Found) {
2683 if (Node->getNodeDepth() <= Found->getNodeDepth()) return;
2685 // If we found an CALLSEQ_START, we already know this node occurs later
2686 // than the Found node. Just remember this node and return.
2687 if (Node->getOpcode() == ISD::CALLSEQ_START) {
2692 // Otherwise, scan the operands of Node to see if any of them is a call.
2693 assert(Node->getNumOperands() != 0 &&
2694 "All leaves should have depth equal to the entry node!");
2695 for (unsigned i = 0, e = Node->getNumOperands()-1; i != e; ++i)
2696 FindLatestCallSeqStart(Node->getOperand(i).Val, Found);
2698 // Tail recurse for the last iteration.
2699 FindLatestCallSeqStart(Node->getOperand(Node->getNumOperands()-1).Val,
2704 /// FindEarliestCallSeqEnd - Scan down the dag to find the earliest (lowest
2705 /// NodeDepth) node that is an CallSeqEnd operation and occurs more recent
2707 static void FindEarliestCallSeqEnd(SDNode *Node, SDNode *&Found,
2708 std::set<SDNode*> &Visited) {
2709 if ((Found && Node->getNodeDepth() >= Found->getNodeDepth()) ||
2710 !Visited.insert(Node).second) return;
2712 // If we found an CALLSEQ_END, we already know this node occurs earlier
2713 // than the Found node. Just remember this node and return.
2714 if (Node->getOpcode() == ISD::CALLSEQ_END) {
2719 // Otherwise, scan the operands of Node to see if any of them is a call.
2720 SDNode::use_iterator UI = Node->use_begin(), E = Node->use_end();
2721 if (UI == E) return;
2722 for (--E; UI != E; ++UI)
2723 FindEarliestCallSeqEnd(*UI, Found, Visited);
2725 // Tail recurse for the last iteration.
2726 FindEarliestCallSeqEnd(*UI, Found, Visited);
2729 /// FindCallSeqEnd - Given a chained node that is part of a call sequence,
2730 /// find the CALLSEQ_END node that terminates the call sequence.
2731 static SDNode *FindCallSeqEnd(SDNode *Node) {
2732 if (Node->getOpcode() == ISD::CALLSEQ_END)
2734 if (Node->use_empty())
2735 return 0; // No CallSeqEnd
2737 SDOperand TheChain(Node, Node->getNumValues()-1);
2738 if (TheChain.getValueType() != MVT::Other)
2739 TheChain = SDOperand(Node, 0);
2740 if (TheChain.getValueType() != MVT::Other)
2743 for (SDNode::use_iterator UI = Node->use_begin(),
2744 E = Node->use_end(); UI != E; ++UI) {
2746 // Make sure to only follow users of our token chain.
2748 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i)
2749 if (User->getOperand(i) == TheChain)
2750 if (SDNode *Result = FindCallSeqEnd(User))
2756 /// FindCallSeqStart - Given a chained node that is part of a call sequence,
2757 /// find the CALLSEQ_START node that initiates the call sequence.
2758 static SDNode *FindCallSeqStart(SDNode *Node) {
2759 assert(Node && "Didn't find callseq_start for a call??");
2760 if (Node->getOpcode() == ISD::CALLSEQ_START) return Node;
2762 assert(Node->getOperand(0).getValueType() == MVT::Other &&
2763 "Node doesn't have a token chain argument!");
2764 return FindCallSeqStart(Node->getOperand(0).Val);
2768 /// FindInputOutputChains - If we are replacing an operation with a call we need
2769 /// to find the call that occurs before and the call that occurs after it to
2770 /// properly serialize the calls in the block. The returned operand is the
2771 /// input chain value for the new call (e.g. the entry node or the previous
2772 /// call), and OutChain is set to be the chain node to update to point to the
2773 /// end of the call chain.
2774 static SDOperand FindInputOutputChains(SDNode *OpNode, SDNode *&OutChain,
2776 SDNode *LatestCallSeqStart = Entry.Val;
2777 SDNode *LatestCallSeqEnd = 0;
2778 FindLatestCallSeqStart(OpNode, LatestCallSeqStart);
2779 //std::cerr<<"Found node: "; LatestCallSeqStart->dump(); std::cerr <<"\n";
2781 // It is possible that no ISD::CALLSEQ_START was found because there is no
2782 // previous call in the function. LatestCallStackDown may in that case be
2783 // the entry node itself. Do not attempt to find a matching CALLSEQ_END
2784 // unless LatestCallStackDown is an CALLSEQ_START.
2785 if (LatestCallSeqStart->getOpcode() == ISD::CALLSEQ_START) {
2786 LatestCallSeqEnd = FindCallSeqEnd(LatestCallSeqStart);
2787 //std::cerr<<"Found end node: "; LatestCallSeqEnd->dump(); std::cerr <<"\n";
2789 LatestCallSeqEnd = Entry.Val;
2791 assert(LatestCallSeqEnd && "NULL return from FindCallSeqEnd");
2793 // Finally, find the first call that this must come before, first we find the
2794 // CallSeqEnd that ends the call.
2796 std::set<SDNode*> Visited;
2797 FindEarliestCallSeqEnd(OpNode, OutChain, Visited);
2799 // If we found one, translate from the adj up to the callseq_start.
2801 OutChain = FindCallSeqStart(OutChain);
2803 return SDOperand(LatestCallSeqEnd, 0);
2806 /// SpliceCallInto - Given the result chain of a libcall (CallResult), and a
2807 void SelectionDAGLegalize::SpliceCallInto(const SDOperand &CallResult,
2809 // Nothing to splice it into?
2810 if (OutChain == 0) return;
2812 assert(OutChain->getOperand(0).getValueType() == MVT::Other);
2815 // Form a token factor node merging the old inval and the new inval.
2816 SDOperand InToken = DAG.getNode(ISD::TokenFactor, MVT::Other, CallResult,
2817 OutChain->getOperand(0));
2818 // Change the node to refer to the new token.
2819 OutChain->setAdjCallChain(InToken);
2823 // ExpandLibCall - Expand a node into a call to a libcall. If the result value
2824 // does not fit into a register, return the lo part and set the hi part to the
2825 // by-reg argument. If it does fit into a single register, return the result
2826 // and leave the Hi part unset.
2827 SDOperand SelectionDAGLegalize::ExpandLibCall(const char *Name, SDNode *Node,
2830 SDOperand InChain = FindInputOutputChains(Node, OutChain,
2831 DAG.getEntryNode());
2832 if (InChain.Val == 0)
2833 InChain = DAG.getEntryNode();
2835 TargetLowering::ArgListTy Args;
2836 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
2837 MVT::ValueType ArgVT = Node->getOperand(i).getValueType();
2838 const Type *ArgTy = MVT::getTypeForValueType(ArgVT);
2839 Args.push_back(std::make_pair(Node->getOperand(i), ArgTy));
2841 SDOperand Callee = DAG.getExternalSymbol(Name, TLI.getPointerTy());
2843 // Splice the libcall in wherever FindInputOutputChains tells us to.
2844 const Type *RetTy = MVT::getTypeForValueType(Node->getValueType(0));
2845 std::pair<SDOperand,SDOperand> CallInfo =
2846 TLI.LowerCallTo(InChain, RetTy, false, CallingConv::C, false,
2850 switch (getTypeAction(CallInfo.first.getValueType())) {
2851 default: assert(0 && "Unknown thing");
2853 Result = CallInfo.first;
2856 assert(0 && "Cannot promote this yet!");
2858 ExpandOp(CallInfo.first, Result, Hi);
2859 CallInfo.second = LegalizeOp(CallInfo.second);
2863 SpliceCallInto(CallInfo.second, OutChain);
2864 NeedsAnotherIteration = true;
2869 /// ExpandIntToFP - Expand a [US]INT_TO_FP operation, assuming that the
2870 /// destination type is legal.
2871 SDOperand SelectionDAGLegalize::
2872 ExpandIntToFP(bool isSigned, MVT::ValueType DestTy, SDOperand Source) {
2873 assert(isTypeLegal(DestTy) && "Destination type is not legal!");
2874 assert(getTypeAction(Source.getValueType()) == Expand &&
2875 "This is not an expansion!");
2876 assert(Source.getValueType() == MVT::i64 && "Only handle expand from i64!");
2879 assert(Source.getValueType() == MVT::i64 &&
2880 "This only works for 64-bit -> FP");
2881 // The 64-bit value loaded will be incorrectly if the 'sign bit' of the
2882 // incoming integer is set. To handle this, we dynamically test to see if
2883 // it is set, and, if so, add a fudge factor.
2885 ExpandOp(Source, Lo, Hi);
2887 // If this is unsigned, and not supported, first perform the conversion to
2888 // signed, then adjust the result if the sign bit is set.
2889 SDOperand SignedConv = ExpandIntToFP(true, DestTy,
2890 DAG.getNode(ISD::BUILD_PAIR, Source.getValueType(), Lo, Hi));
2892 SDOperand SignSet = DAG.getSetCC(TLI.getSetCCResultTy(), Hi,
2893 DAG.getConstant(0, Hi.getValueType()),
2895 SDOperand Zero = getIntPtrConstant(0), Four = getIntPtrConstant(4);
2896 SDOperand CstOffset = DAG.getNode(ISD::SELECT, Zero.getValueType(),
2897 SignSet, Four, Zero);
2898 uint64_t FF = 0x5f800000ULL;
2899 if (TLI.isLittleEndian()) FF <<= 32;
2900 static Constant *FudgeFactor = ConstantUInt::get(Type::ULongTy, FF);
2902 SDOperand CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy());
2903 CPIdx = DAG.getNode(ISD::ADD, TLI.getPointerTy(), CPIdx, CstOffset);
2904 SDOperand FudgeInReg;
2905 if (DestTy == MVT::f32)
2906 FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx,
2907 DAG.getSrcValue(NULL));
2909 assert(DestTy == MVT::f64 && "Unexpected conversion");
2910 FudgeInReg = DAG.getExtLoad(ISD::EXTLOAD, MVT::f64, DAG.getEntryNode(),
2911 CPIdx, DAG.getSrcValue(NULL), MVT::f32);
2913 return DAG.getNode(ISD::FADD, DestTy, SignedConv, FudgeInReg);
2916 // Check to see if the target has a custom way to lower this. If so, use it.
2917 switch (TLI.getOperationAction(ISD::SINT_TO_FP, Source.getValueType())) {
2918 default: assert(0 && "This action not implemented for this operation!");
2919 case TargetLowering::Legal:
2920 case TargetLowering::Expand:
2921 break; // This case is handled below.
2922 case TargetLowering::Custom: {
2923 SDOperand NV = TLI.LowerOperation(DAG.getNode(ISD::SINT_TO_FP, DestTy,
2926 return LegalizeOp(NV);
2927 break; // The target decided this was legal after all
2931 // Expand the source, then glue it back together for the call. We must expand
2932 // the source in case it is shared (this pass of legalize must traverse it).
2933 SDOperand SrcLo, SrcHi;
2934 ExpandOp(Source, SrcLo, SrcHi);
2935 Source = DAG.getNode(ISD::BUILD_PAIR, Source.getValueType(), SrcLo, SrcHi);
2937 SDNode *OutChain = 0;
2938 SDOperand InChain = FindInputOutputChains(Source.Val, OutChain,
2939 DAG.getEntryNode());
2940 const char *FnName = 0;
2941 if (DestTy == MVT::f32)
2942 FnName = "__floatdisf";
2944 assert(DestTy == MVT::f64 && "Unknown fp value type!");
2945 FnName = "__floatdidf";
2948 SDOperand Callee = DAG.getExternalSymbol(FnName, TLI.getPointerTy());
2950 TargetLowering::ArgListTy Args;
2951 const Type *ArgTy = MVT::getTypeForValueType(Source.getValueType());
2953 Args.push_back(std::make_pair(Source, ArgTy));
2955 // We don't care about token chains for libcalls. We just use the entry
2956 // node as our input and ignore the output chain. This allows us to place
2957 // calls wherever we need them to satisfy data dependences.
2958 const Type *RetTy = MVT::getTypeForValueType(DestTy);
2960 std::pair<SDOperand,SDOperand> CallResult =
2961 TLI.LowerCallTo(InChain, RetTy, false, CallingConv::C, true,
2964 SpliceCallInto(CallResult.second, OutChain);
2965 return CallResult.first;
2970 /// ExpandOp - Expand the specified SDOperand into its two component pieces
2971 /// Lo&Hi. Note that the Op MUST be an expanded type. As a result of this, the
2972 /// LegalizeNodes map is filled in for any results that are not expanded, the
2973 /// ExpandedNodes map is filled in for any results that are expanded, and the
2974 /// Lo/Hi values are returned.
2975 void SelectionDAGLegalize::ExpandOp(SDOperand Op, SDOperand &Lo, SDOperand &Hi){
2976 MVT::ValueType VT = Op.getValueType();
2977 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT);
2978 SDNode *Node = Op.Val;
2979 assert(getTypeAction(VT) == Expand && "Not an expanded type!");
2980 assert(MVT::isInteger(VT) && "Cannot expand FP values!");
2981 assert(MVT::isInteger(NVT) && NVT < VT &&
2982 "Cannot expand to FP value or to larger int value!");
2984 // See if we already expanded it.
2985 std::map<SDOperand, std::pair<SDOperand, SDOperand> >::iterator I
2986 = ExpandedNodes.find(Op);
2987 if (I != ExpandedNodes.end()) {
2988 Lo = I->second.first;
2989 Hi = I->second.second;
2993 // Expanding to multiple registers needs to perform an optimization step, and
2994 // is not careful to avoid operations the target does not support. Make sure
2995 // that all generated operations are legalized in the next iteration.
2996 NeedsAnotherIteration = true;
2998 switch (Node->getOpcode()) {
2999 case ISD::CopyFromReg:
3000 assert(0 && "CopyFromReg must be legal!");
3002 std::cerr << "NODE: "; Node->dump(); std::cerr << "\n";
3003 assert(0 && "Do not know how to expand this operator!");
3006 Lo = DAG.getNode(ISD::UNDEF, NVT);
3007 Hi = DAG.getNode(ISD::UNDEF, NVT);
3009 case ISD::Constant: {
3010 uint64_t Cst = cast<ConstantSDNode>(Node)->getValue();
3011 Lo = DAG.getConstant(Cst, NVT);
3012 Hi = DAG.getConstant(Cst >> MVT::getSizeInBits(NVT), NVT);
3016 case ISD::BUILD_PAIR:
3017 // Legalize both operands. FIXME: in the future we should handle the case
3018 // where the two elements are not legal.
3019 assert(isTypeLegal(NVT) && "Cannot expand this multiple times yet!");
3020 Lo = LegalizeOp(Node->getOperand(0));
3021 Hi = LegalizeOp(Node->getOperand(1));
3025 ExpandOp(Node->getOperand(0), Lo, Hi);
3026 Lo = DAG.getNode(ISD::ADD, NVT, // ctpop(HL) -> ctpop(H)+ctpop(L)
3027 DAG.getNode(ISD::CTPOP, NVT, Lo),
3028 DAG.getNode(ISD::CTPOP, NVT, Hi));
3029 Hi = DAG.getConstant(0, NVT);
3033 // ctlz (HL) -> ctlz(H) != 32 ? ctlz(H) : (ctlz(L)+32)
3034 ExpandOp(Node->getOperand(0), Lo, Hi);
3035 SDOperand BitsC = DAG.getConstant(MVT::getSizeInBits(NVT), NVT);
3036 SDOperand HLZ = DAG.getNode(ISD::CTLZ, NVT, Hi);
3037 SDOperand TopNotZero = DAG.getSetCC(TLI.getSetCCResultTy(), HLZ, BitsC,
3039 SDOperand LowPart = DAG.getNode(ISD::CTLZ, NVT, Lo);
3040 LowPart = DAG.getNode(ISD::ADD, NVT, LowPart, BitsC);
3042 Lo = DAG.getNode(ISD::SELECT, NVT, TopNotZero, HLZ, LowPart);
3043 Hi = DAG.getConstant(0, NVT);
3048 // cttz (HL) -> cttz(L) != 32 ? cttz(L) : (cttz(H)+32)
3049 ExpandOp(Node->getOperand(0), Lo, Hi);
3050 SDOperand BitsC = DAG.getConstant(MVT::getSizeInBits(NVT), NVT);
3051 SDOperand LTZ = DAG.getNode(ISD::CTTZ, NVT, Lo);
3052 SDOperand BotNotZero = DAG.getSetCC(TLI.getSetCCResultTy(), LTZ, BitsC,
3054 SDOperand HiPart = DAG.getNode(ISD::CTTZ, NVT, Hi);
3055 HiPart = DAG.getNode(ISD::ADD, NVT, HiPart, BitsC);
3057 Lo = DAG.getNode(ISD::SELECT, NVT, BotNotZero, LTZ, HiPart);
3058 Hi = DAG.getConstant(0, NVT);
3063 SDOperand Ch = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
3064 SDOperand Ptr = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
3065 Lo = DAG.getLoad(NVT, Ch, Ptr, Node->getOperand(2));
3067 // Increment the pointer to the other half.
3068 unsigned IncrementSize = MVT::getSizeInBits(Lo.getValueType())/8;
3069 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
3070 getIntPtrConstant(IncrementSize));
3071 //Is this safe? declaring that the two parts of the split load
3072 //are from the same instruction?
3073 Hi = DAG.getLoad(NVT, Ch, Ptr, Node->getOperand(2));
3075 // Build a factor node to remember that this load is independent of the
3077 SDOperand TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
3080 // Remember that we legalized the chain.
3081 AddLegalizedOperand(Op.getValue(1), TF);
3082 if (!TLI.isLittleEndian())
3088 SDOperand Chain = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
3089 SDOperand Callee = LegalizeOp(Node->getOperand(1)); // Legalize the callee.
3091 bool Changed = false;
3092 std::vector<SDOperand> Ops;
3093 for (unsigned i = 2, e = Node->getNumOperands(); i != e; ++i) {
3094 Ops.push_back(LegalizeOp(Node->getOperand(i)));
3095 Changed |= Ops.back() != Node->getOperand(i);
3098 assert(Node->getNumValues() == 2 && Op.ResNo == 0 &&
3099 "Can only expand a call once so far, not i64 -> i16!");
3101 std::vector<MVT::ValueType> RetTyVTs;
3102 RetTyVTs.reserve(3);
3103 RetTyVTs.push_back(NVT);
3104 RetTyVTs.push_back(NVT);
3105 RetTyVTs.push_back(MVT::Other);
3106 SDNode *NC = DAG.getCall(RetTyVTs, Chain, Callee, Ops,
3107 Node->getOpcode() == ISD::TAILCALL);
3108 Lo = SDOperand(NC, 0);
3109 Hi = SDOperand(NC, 1);
3111 // Insert the new chain mapping.
3112 AddLegalizedOperand(Op.getValue(1), Hi.getValue(2));
3117 case ISD::XOR: { // Simple logical operators -> two trivial pieces.
3118 SDOperand LL, LH, RL, RH;
3119 ExpandOp(Node->getOperand(0), LL, LH);
3120 ExpandOp(Node->getOperand(1), RL, RH);
3121 Lo = DAG.getNode(Node->getOpcode(), NVT, LL, RL);
3122 Hi = DAG.getNode(Node->getOpcode(), NVT, LH, RH);
3126 SDOperand C, LL, LH, RL, RH;
3128 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3129 case Expand: assert(0 && "It's impossible to expand bools");
3131 C = LegalizeOp(Node->getOperand(0)); // Legalize the condition.
3134 C = PromoteOp(Node->getOperand(0)); // Promote the condition.
3137 ExpandOp(Node->getOperand(1), LL, LH);
3138 ExpandOp(Node->getOperand(2), RL, RH);
3139 Lo = DAG.getNode(ISD::SELECT, NVT, C, LL, RL);
3140 Hi = DAG.getNode(ISD::SELECT, NVT, C, LH, RH);
3143 case ISD::SELECT_CC: {
3144 SDOperand TL, TH, FL, FH;
3145 ExpandOp(Node->getOperand(2), TL, TH);
3146 ExpandOp(Node->getOperand(3), FL, FH);
3147 Lo = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0),
3148 Node->getOperand(1), TL, FL, Node->getOperand(4));
3149 Hi = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0),
3150 Node->getOperand(1), TH, FH, Node->getOperand(4));
3151 Lo = LegalizeOp(Lo);
3152 Hi = LegalizeOp(Hi);
3155 case ISD::SEXTLOAD: {
3156 SDOperand Chain = LegalizeOp(Node->getOperand(0));
3157 SDOperand Ptr = LegalizeOp(Node->getOperand(1));
3158 MVT::ValueType EVT = cast<VTSDNode>(Node->getOperand(3))->getVT();
3161 Lo = DAG.getLoad(NVT, Chain, Ptr, Node->getOperand(2));
3163 Lo = DAG.getExtLoad(ISD::SEXTLOAD, NVT, Chain, Ptr, Node->getOperand(2),
3166 // Remember that we legalized the chain.
3167 AddLegalizedOperand(SDOperand(Node, 1), Lo.getValue(1));
3169 // The high part is obtained by SRA'ing all but one of the bits of the lo
3171 unsigned LoSize = MVT::getSizeInBits(Lo.getValueType());
3172 Hi = DAG.getNode(ISD::SRA, NVT, Lo, DAG.getConstant(LoSize-1,
3173 TLI.getShiftAmountTy()));
3174 Lo = LegalizeOp(Lo);
3175 Hi = LegalizeOp(Hi);
3178 case ISD::ZEXTLOAD: {
3179 SDOperand Chain = LegalizeOp(Node->getOperand(0));
3180 SDOperand Ptr = LegalizeOp(Node->getOperand(1));
3181 MVT::ValueType EVT = cast<VTSDNode>(Node->getOperand(3))->getVT();
3184 Lo = DAG.getLoad(NVT, Chain, Ptr, Node->getOperand(2));
3186 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, NVT, Chain, Ptr, Node->getOperand(2),
3189 // Remember that we legalized the chain.
3190 AddLegalizedOperand(SDOperand(Node, 1), Lo.getValue(1));
3192 // The high part is just a zero.
3193 Hi = LegalizeOp(DAG.getConstant(0, NVT));
3194 Lo = LegalizeOp(Lo);
3197 case ISD::EXTLOAD: {
3198 SDOperand Chain = LegalizeOp(Node->getOperand(0));
3199 SDOperand Ptr = LegalizeOp(Node->getOperand(1));
3200 MVT::ValueType EVT = cast<VTSDNode>(Node->getOperand(3))->getVT();
3203 Lo = DAG.getLoad(NVT, Chain, Ptr, Node->getOperand(2));
3205 Lo = DAG.getExtLoad(ISD::EXTLOAD, NVT, Chain, Ptr, Node->getOperand(2),
3208 // Remember that we legalized the chain.
3209 AddLegalizedOperand(SDOperand(Node, 1), Lo.getValue(1));
3211 // The high part is undefined.
3212 Hi = LegalizeOp(DAG.getNode(ISD::UNDEF, NVT));
3213 Lo = LegalizeOp(Lo);
3216 case ISD::ANY_EXTEND: {
3218 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3219 case Expand: assert(0 && "expand-expand not implemented yet!");
3220 case Legal: In = LegalizeOp(Node->getOperand(0)); break;
3222 In = PromoteOp(Node->getOperand(0));
3226 // The low part is any extension of the input (which degenerates to a copy).
3227 Lo = DAG.getNode(ISD::ANY_EXTEND, NVT, In);
3228 // The high part is undefined.
3229 Hi = DAG.getNode(ISD::UNDEF, NVT);
3232 case ISD::SIGN_EXTEND: {
3234 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3235 case Expand: assert(0 && "expand-expand not implemented yet!");
3236 case Legal: In = LegalizeOp(Node->getOperand(0)); break;
3238 In = PromoteOp(Node->getOperand(0));
3239 // Emit the appropriate sign_extend_inreg to get the value we want.
3240 In = DAG.getNode(ISD::SIGN_EXTEND_INREG, In.getValueType(), In,
3241 DAG.getValueType(Node->getOperand(0).getValueType()));
3245 // The low part is just a sign extension of the input (which degenerates to
3247 Lo = DAG.getNode(ISD::SIGN_EXTEND, NVT, In);
3249 // The high part is obtained by SRA'ing all but one of the bits of the lo
3251 unsigned LoSize = MVT::getSizeInBits(Lo.getValueType());
3252 Hi = DAG.getNode(ISD::SRA, NVT, Lo, DAG.getConstant(LoSize-1,
3253 TLI.getShiftAmountTy()));
3256 case ISD::ZERO_EXTEND: {
3258 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3259 case Expand: assert(0 && "expand-expand not implemented yet!");
3260 case Legal: In = LegalizeOp(Node->getOperand(0)); break;
3262 In = PromoteOp(Node->getOperand(0));
3263 // Emit the appropriate zero_extend_inreg to get the value we want.
3264 In = DAG.getZeroExtendInReg(In, Node->getOperand(0).getValueType());
3268 // The low part is just a zero extension of the input (which degenerates to
3270 Lo = DAG.getNode(ISD::ZERO_EXTEND, NVT, In);
3272 // The high part is just a zero.
3273 Hi = DAG.getConstant(0, NVT);
3276 // These operators cannot be expanded directly, emit them as calls to
3277 // library functions.
3278 case ISD::FP_TO_SINT:
3279 if (TLI.getOperationAction(ISD::FP_TO_SINT, VT) == TargetLowering::Custom) {
3281 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3282 case Expand: assert(0 && "cannot expand FP!");
3283 case Legal: Op = LegalizeOp(Node->getOperand(0)); break;
3284 case Promote: Op = PromoteOp(Node->getOperand(0)); break;
3287 Op = TLI.LowerOperation(DAG.getNode(ISD::FP_TO_SINT, VT, Op), DAG);
3289 // Now that the custom expander is done, expand the result, which is still
3292 ExpandOp(Op, Lo, Hi);
3297 if (Node->getOperand(0).getValueType() == MVT::f32)
3298 Lo = ExpandLibCall("__fixsfdi", Node, Hi);
3300 Lo = ExpandLibCall("__fixdfdi", Node, Hi);
3303 case ISD::FP_TO_UINT:
3304 if (TLI.getOperationAction(ISD::FP_TO_UINT, VT) == TargetLowering::Custom) {
3305 SDOperand Op = DAG.getNode(ISD::FP_TO_UINT, VT,
3306 LegalizeOp(Node->getOperand(0)));
3307 // Now that the custom expander is done, expand the result, which is still
3309 Op = TLI.LowerOperation(Op, DAG);
3311 ExpandOp(Op, Lo, Hi);
3316 if (Node->getOperand(0).getValueType() == MVT::f32)
3317 Lo = ExpandLibCall("__fixunssfdi", Node, Hi);
3319 Lo = ExpandLibCall("__fixunsdfdi", Node, Hi);
3323 // If the target wants custom lowering, do so.
3324 if (TLI.getOperationAction(ISD::SHL, VT) == TargetLowering::Custom) {
3325 SDOperand Op = DAG.getNode(ISD::SHL, VT, Node->getOperand(0),
3326 LegalizeOp(Node->getOperand(1)));
3327 Op = TLI.LowerOperation(Op, DAG);
3329 // Now that the custom expander is done, expand the result, which is
3331 ExpandOp(Op, Lo, Hi);
3336 // If we can emit an efficient shift operation, do so now.
3337 if (ExpandShift(ISD::SHL, Node->getOperand(0), Node->getOperand(1), Lo, Hi))
3340 // If this target supports SHL_PARTS, use it.
3341 if (TLI.isOperationLegal(ISD::SHL_PARTS, NVT)) {
3342 ExpandShiftParts(ISD::SHL_PARTS, Node->getOperand(0), Node->getOperand(1),
3347 // Otherwise, emit a libcall.
3348 Lo = ExpandLibCall("__ashldi3", Node, Hi);
3352 // If the target wants custom lowering, do so.
3353 if (TLI.getOperationAction(ISD::SRA, VT) == TargetLowering::Custom) {
3354 SDOperand Op = DAG.getNode(ISD::SRA, VT, Node->getOperand(0),
3355 LegalizeOp(Node->getOperand(1)));
3356 Op = TLI.LowerOperation(Op, DAG);
3358 // Now that the custom expander is done, expand the result, which is
3360 ExpandOp(Op, Lo, Hi);
3365 // If we can emit an efficient shift operation, do so now.
3366 if (ExpandShift(ISD::SRA, Node->getOperand(0), Node->getOperand(1), Lo, Hi))
3369 // If this target supports SRA_PARTS, use it.
3370 if (TLI.isOperationLegal(ISD::SRA_PARTS, NVT)) {
3371 ExpandShiftParts(ISD::SRA_PARTS, Node->getOperand(0), Node->getOperand(1),
3376 // Otherwise, emit a libcall.
3377 Lo = ExpandLibCall("__ashrdi3", Node, Hi);
3380 // If the target wants custom lowering, do so.
3381 if (TLI.getOperationAction(ISD::SRL, VT) == TargetLowering::Custom) {
3382 SDOperand Op = DAG.getNode(ISD::SRL, VT, Node->getOperand(0),
3383 LegalizeOp(Node->getOperand(1)));
3384 Op = TLI.LowerOperation(Op, DAG);
3386 // Now that the custom expander is done, expand the result, which is
3388 ExpandOp(Op, Lo, Hi);
3393 // If we can emit an efficient shift operation, do so now.
3394 if (ExpandShift(ISD::SRL, Node->getOperand(0), Node->getOperand(1), Lo, Hi))
3397 // If this target supports SRL_PARTS, use it.
3398 if (TLI.isOperationLegal(ISD::SRL_PARTS, NVT)) {
3399 ExpandShiftParts(ISD::SRL_PARTS, Node->getOperand(0), Node->getOperand(1),
3404 // Otherwise, emit a libcall.
3405 Lo = ExpandLibCall("__lshrdi3", Node, Hi);
3409 ExpandByParts(ISD::ADD_PARTS, Node->getOperand(0), Node->getOperand(1),
3413 ExpandByParts(ISD::SUB_PARTS, Node->getOperand(0), Node->getOperand(1),
3417 if (TLI.isOperationLegal(ISD::MULHU, NVT)) {
3418 SDOperand LL, LH, RL, RH;
3419 ExpandOp(Node->getOperand(0), LL, LH);
3420 ExpandOp(Node->getOperand(1), RL, RH);
3421 unsigned SH = MVT::getSizeInBits(RH.getValueType())-1;
3422 // MULHS implicitly sign extends its inputs. Check to see if ExpandOp
3423 // extended the sign bit of the low half through the upper half, and if so
3424 // emit a MULHS instead of the alternate sequence that is valid for any
3425 // i64 x i64 multiply.
3426 if (TLI.isOperationLegal(ISD::MULHS, NVT) &&
3427 // is RH an extension of the sign bit of RL?
3428 RH.getOpcode() == ISD::SRA && RH.getOperand(0) == RL &&
3429 RH.getOperand(1).getOpcode() == ISD::Constant &&
3430 cast<ConstantSDNode>(RH.getOperand(1))->getValue() == SH &&
3431 // is LH an extension of the sign bit of LL?
3432 LH.getOpcode() == ISD::SRA && LH.getOperand(0) == LL &&
3433 LH.getOperand(1).getOpcode() == ISD::Constant &&
3434 cast<ConstantSDNode>(LH.getOperand(1))->getValue() == SH) {
3435 Hi = DAG.getNode(ISD::MULHS, NVT, LL, RL);
3437 Hi = DAG.getNode(ISD::MULHU, NVT, LL, RL);
3438 RH = DAG.getNode(ISD::MUL, NVT, LL, RH);
3439 LH = DAG.getNode(ISD::MUL, NVT, LH, RL);
3440 Hi = DAG.getNode(ISD::ADD, NVT, Hi, RH);
3441 Hi = DAG.getNode(ISD::ADD, NVT, Hi, LH);
3443 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL);
3445 Lo = ExpandLibCall("__muldi3" , Node, Hi); break;
3449 case ISD::SDIV: Lo = ExpandLibCall("__divdi3" , Node, Hi); break;
3450 case ISD::UDIV: Lo = ExpandLibCall("__udivdi3", Node, Hi); break;
3451 case ISD::SREM: Lo = ExpandLibCall("__moddi3" , Node, Hi); break;
3452 case ISD::UREM: Lo = ExpandLibCall("__umoddi3", Node, Hi); break;
3455 // Remember in a map if the values will be reused later.
3456 bool isNew = ExpandedNodes.insert(std::make_pair(Op,
3457 std::make_pair(Lo, Hi))).second;
3458 assert(isNew && "Value already expanded?!?");
3462 // SelectionDAG::Legalize - This is the entry point for the file.
3464 void SelectionDAG::Legalize() {
3465 /// run - This is the main entry point to this class.
3467 SelectionDAGLegalize(*this).Run();