1 //===-- FastISel.cpp - Implementation of the FastISel class ---------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the implementation of the FastISel class.
12 // "Fast" instruction selection is designed to emit very poor code quickly.
13 // Also, it is not designed to be able to do much lowering, so most illegal
14 // types (e.g. i64 on 32-bit targets) and operations are not supported. It is
15 // also not intended to be able to do much optimization, except in a few cases
16 // where doing optimizations reduces overall compile time. For example, folding
17 // constants into immediate fields is often done, because it's cheap and it
18 // reduces the number of instructions later phases have to examine.
20 // "Fast" instruction selection is able to fail gracefully and transfer
21 // control to the SelectionDAG selector for operations that it doesn't
22 // support. In many cases, this allows us to avoid duplicating a lot of
23 // the complicated lowering logic that SelectionDAG currently has.
25 // The intended use for "fast" instruction selection is "-O0" mode
26 // compilation, where the quality of the generated code is irrelevant when
27 // weighed against the speed at which the code can be generated. Also,
28 // at -O0, the LLVM optimizers are not running, and this makes the
29 // compile time of codegen a much higher portion of the overall compile
30 // time. Despite its limitations, "fast" instruction selection is able to
31 // handle enough code on its own to provide noticeable overall speedups
34 // Basic operations are supported in a target-independent way, by reading
35 // the same instruction descriptions that the SelectionDAG selector reads,
36 // and identifying simple arithmetic operations that can be directly selected
37 // from simple operators. More complicated operations currently require
38 // target-specific code.
40 //===----------------------------------------------------------------------===//
42 #include "llvm/CodeGen/Analysis.h"
43 #include "llvm/ADT/Optional.h"
44 #include "llvm/ADT/Statistic.h"
45 #include "llvm/Analysis/BranchProbabilityInfo.h"
46 #include "llvm/Analysis/Loads.h"
47 #include "llvm/Analysis/TargetLibraryInfo.h"
48 #include "llvm/CodeGen/Analysis.h"
49 #include "llvm/CodeGen/FastISel.h"
50 #include "llvm/CodeGen/FunctionLoweringInfo.h"
51 #include "llvm/CodeGen/MachineFrameInfo.h"
52 #include "llvm/CodeGen/MachineInstrBuilder.h"
53 #include "llvm/CodeGen/MachineModuleInfo.h"
54 #include "llvm/CodeGen/MachineRegisterInfo.h"
55 #include "llvm/CodeGen/StackMaps.h"
56 #include "llvm/IR/DataLayout.h"
57 #include "llvm/IR/DebugInfo.h"
58 #include "llvm/IR/Function.h"
59 #include "llvm/IR/GlobalVariable.h"
60 #include "llvm/IR/Instructions.h"
61 #include "llvm/IR/IntrinsicInst.h"
62 #include "llvm/IR/Operator.h"
63 #include "llvm/Support/Debug.h"
64 #include "llvm/Support/ErrorHandling.h"
65 #include "llvm/Target/TargetInstrInfo.h"
66 #include "llvm/Target/TargetLowering.h"
67 #include "llvm/Target/TargetMachine.h"
68 #include "llvm/Target/TargetSubtargetInfo.h"
71 #define DEBUG_TYPE "isel"
73 STATISTIC(NumFastIselSuccessIndependent, "Number of insts selected by "
74 "target-independent selector");
75 STATISTIC(NumFastIselSuccessTarget, "Number of insts selected by "
76 "target-specific selector");
77 STATISTIC(NumFastIselDead, "Number of dead insts removed on failure");
79 void FastISel::ArgListEntry::setAttributes(ImmutableCallSite *CS,
81 IsSExt = CS->paramHasAttr(AttrIdx, Attribute::SExt);
82 IsZExt = CS->paramHasAttr(AttrIdx, Attribute::ZExt);
83 IsInReg = CS->paramHasAttr(AttrIdx, Attribute::InReg);
84 IsSRet = CS->paramHasAttr(AttrIdx, Attribute::StructRet);
85 IsNest = CS->paramHasAttr(AttrIdx, Attribute::Nest);
86 IsByVal = CS->paramHasAttr(AttrIdx, Attribute::ByVal);
87 IsInAlloca = CS->paramHasAttr(AttrIdx, Attribute::InAlloca);
88 IsReturned = CS->paramHasAttr(AttrIdx, Attribute::Returned);
89 Alignment = CS->getParamAlignment(AttrIdx);
92 /// Set the current block to which generated machine instructions will be
93 /// appended, and clear the local CSE map.
94 void FastISel::startNewBlock() {
95 LocalValueMap.clear();
97 // Instructions are appended to FuncInfo.MBB. If the basic block already
98 // contains labels or copies, use the last instruction as the last local
100 EmitStartPt = nullptr;
101 if (!FuncInfo.MBB->empty())
102 EmitStartPt = &FuncInfo.MBB->back();
103 LastLocalValue = EmitStartPt;
106 bool FastISel::lowerArguments() {
107 if (!FuncInfo.CanLowerReturn)
108 // Fallback to SDISel argument lowering code to deal with sret pointer
112 if (!fastLowerArguments())
115 // Enter arguments into ValueMap for uses in non-entry BBs.
116 for (Function::const_arg_iterator I = FuncInfo.Fn->arg_begin(),
117 E = FuncInfo.Fn->arg_end();
119 DenseMap<const Value *, unsigned>::iterator VI = LocalValueMap.find(I);
120 assert(VI != LocalValueMap.end() && "Missed an argument?");
121 FuncInfo.ValueMap[I] = VI->second;
126 void FastISel::flushLocalValueMap() {
127 LocalValueMap.clear();
128 LastLocalValue = EmitStartPt;
130 SavedInsertPt = FuncInfo.InsertPt;
133 bool FastISel::hasTrivialKill(const Value *V) {
134 // Don't consider constants or arguments to have trivial kills.
135 const Instruction *I = dyn_cast<Instruction>(V);
139 // No-op casts are trivially coalesced by fast-isel.
140 if (const auto *Cast = dyn_cast<CastInst>(I))
141 if (Cast->isNoopCast(DL.getIntPtrType(Cast->getContext())) &&
142 !hasTrivialKill(Cast->getOperand(0)))
145 // Even the value might have only one use in the LLVM IR, it is possible that
146 // FastISel might fold the use into another instruction and now there is more
147 // than one use at the Machine Instruction level.
148 unsigned Reg = lookUpRegForValue(V);
149 if (Reg && !MRI.use_empty(Reg))
152 // GEPs with all zero indices are trivially coalesced by fast-isel.
153 if (const auto *GEP = dyn_cast<GetElementPtrInst>(I))
154 if (GEP->hasAllZeroIndices() && !hasTrivialKill(GEP->getOperand(0)))
157 // Only instructions with a single use in the same basic block are considered
158 // to have trivial kills.
159 return I->hasOneUse() &&
160 !(I->getOpcode() == Instruction::BitCast ||
161 I->getOpcode() == Instruction::PtrToInt ||
162 I->getOpcode() == Instruction::IntToPtr) &&
163 cast<Instruction>(*I->user_begin())->getParent() == I->getParent();
166 unsigned FastISel::getRegForValue(const Value *V) {
167 EVT RealVT = TLI.getValueType(V->getType(), /*AllowUnknown=*/true);
168 // Don't handle non-simple values in FastISel.
169 if (!RealVT.isSimple())
172 // Ignore illegal types. We must do this before looking up the value
173 // in ValueMap because Arguments are given virtual registers regardless
174 // of whether FastISel can handle them.
175 MVT VT = RealVT.getSimpleVT();
176 if (!TLI.isTypeLegal(VT)) {
177 // Handle integer promotions, though, because they're common and easy.
178 if (VT == MVT::i1 || VT == MVT::i8 || VT == MVT::i16)
179 VT = TLI.getTypeToTransformTo(V->getContext(), VT).getSimpleVT();
184 // Look up the value to see if we already have a register for it.
185 unsigned Reg = lookUpRegForValue(V);
189 // In bottom-up mode, just create the virtual register which will be used
190 // to hold the value. It will be materialized later.
191 if (isa<Instruction>(V) &&
192 (!isa<AllocaInst>(V) ||
193 !FuncInfo.StaticAllocaMap.count(cast<AllocaInst>(V))))
194 return FuncInfo.InitializeRegForValue(V);
196 SavePoint SaveInsertPt = enterLocalValueArea();
198 // Materialize the value in a register. Emit any instructions in the
200 Reg = materializeRegForValue(V, VT);
202 leaveLocalValueArea(SaveInsertPt);
207 unsigned FastISel::materializeConstant(const Value *V, MVT VT) {
209 if (const auto *CI = dyn_cast<ConstantInt>(V)) {
210 if (CI->getValue().getActiveBits() <= 64)
211 Reg = fastEmit_i(VT, VT, ISD::Constant, CI->getZExtValue());
212 } else if (isa<AllocaInst>(V))
213 Reg = fastMaterializeAlloca(cast<AllocaInst>(V));
214 else if (isa<ConstantPointerNull>(V))
215 // Translate this as an integer zero so that it can be
216 // local-CSE'd with actual integer zeros.
217 Reg = getRegForValue(
218 Constant::getNullValue(DL.getIntPtrType(V->getContext())));
219 else if (const auto *CF = dyn_cast<ConstantFP>(V)) {
220 if (CF->isNullValue())
221 Reg = fastMaterializeFloatZero(CF);
223 // Try to emit the constant directly.
224 Reg = fastEmit_f(VT, VT, ISD::ConstantFP, CF);
227 // Try to emit the constant by using an integer constant with a cast.
228 const APFloat &Flt = CF->getValueAPF();
229 EVT IntVT = TLI.getPointerTy();
232 uint32_t IntBitWidth = IntVT.getSizeInBits();
234 (void)Flt.convertToInteger(x, IntBitWidth, /*isSigned=*/true,
235 APFloat::rmTowardZero, &isExact);
237 APInt IntVal(IntBitWidth, x);
239 unsigned IntegerReg =
240 getRegForValue(ConstantInt::get(V->getContext(), IntVal));
242 Reg = fastEmit_r(IntVT.getSimpleVT(), VT, ISD::SINT_TO_FP, IntegerReg,
246 } else if (const auto *Op = dyn_cast<Operator>(V)) {
247 if (!selectOperator(Op, Op->getOpcode()))
248 if (!isa<Instruction>(Op) ||
249 !fastSelectInstruction(cast<Instruction>(Op)))
251 Reg = lookUpRegForValue(Op);
252 } else if (isa<UndefValue>(V)) {
253 Reg = createResultReg(TLI.getRegClassFor(VT));
254 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
255 TII.get(TargetOpcode::IMPLICIT_DEF), Reg);
260 /// Helper for getRegForValue. This function is called when the value isn't
261 /// already available in a register and must be materialized with new
263 unsigned FastISel::materializeRegForValue(const Value *V, MVT VT) {
265 // Give the target-specific code a try first.
266 if (isa<Constant>(V))
267 Reg = fastMaterializeConstant(cast<Constant>(V));
269 // If target-specific code couldn't or didn't want to handle the value, then
270 // give target-independent code a try.
272 Reg = materializeConstant(V, VT);
274 // Don't cache constant materializations in the general ValueMap.
275 // To do so would require tracking what uses they dominate.
277 LocalValueMap[V] = Reg;
278 LastLocalValue = MRI.getVRegDef(Reg);
283 unsigned FastISel::lookUpRegForValue(const Value *V) {
284 // Look up the value to see if we already have a register for it. We
285 // cache values defined by Instructions across blocks, and other values
286 // only locally. This is because Instructions already have the SSA
287 // def-dominates-use requirement enforced.
288 DenseMap<const Value *, unsigned>::iterator I = FuncInfo.ValueMap.find(V);
289 if (I != FuncInfo.ValueMap.end())
291 return LocalValueMap[V];
294 void FastISel::updateValueMap(const Value *I, unsigned Reg, unsigned NumRegs) {
295 if (!isa<Instruction>(I)) {
296 LocalValueMap[I] = Reg;
300 unsigned &AssignedReg = FuncInfo.ValueMap[I];
301 if (AssignedReg == 0)
302 // Use the new register.
304 else if (Reg != AssignedReg) {
305 // Arrange for uses of AssignedReg to be replaced by uses of Reg.
306 for (unsigned i = 0; i < NumRegs; i++)
307 FuncInfo.RegFixups[AssignedReg + i] = Reg + i;
313 std::pair<unsigned, bool> FastISel::getRegForGEPIndex(const Value *Idx) {
314 unsigned IdxN = getRegForValue(Idx);
316 // Unhandled operand. Halt "fast" selection and bail.
317 return std::pair<unsigned, bool>(0, false);
319 bool IdxNIsKill = hasTrivialKill(Idx);
321 // If the index is smaller or larger than intptr_t, truncate or extend it.
322 MVT PtrVT = TLI.getPointerTy();
323 EVT IdxVT = EVT::getEVT(Idx->getType(), /*HandleUnknown=*/false);
324 if (IdxVT.bitsLT(PtrVT)) {
325 IdxN = fastEmit_r(IdxVT.getSimpleVT(), PtrVT, ISD::SIGN_EXTEND, IdxN,
328 } else if (IdxVT.bitsGT(PtrVT)) {
330 fastEmit_r(IdxVT.getSimpleVT(), PtrVT, ISD::TRUNCATE, IdxN, IdxNIsKill);
333 return std::pair<unsigned, bool>(IdxN, IdxNIsKill);
336 void FastISel::recomputeInsertPt() {
337 if (getLastLocalValue()) {
338 FuncInfo.InsertPt = getLastLocalValue();
339 FuncInfo.MBB = FuncInfo.InsertPt->getParent();
342 FuncInfo.InsertPt = FuncInfo.MBB->getFirstNonPHI();
344 // Now skip past any EH_LABELs, which must remain at the beginning.
345 while (FuncInfo.InsertPt != FuncInfo.MBB->end() &&
346 FuncInfo.InsertPt->getOpcode() == TargetOpcode::EH_LABEL)
350 void FastISel::removeDeadCode(MachineBasicBlock::iterator I,
351 MachineBasicBlock::iterator E) {
352 assert(I && E && std::distance(I, E) > 0 && "Invalid iterator!");
354 MachineInstr *Dead = &*I;
356 Dead->eraseFromParent();
362 FastISel::SavePoint FastISel::enterLocalValueArea() {
363 MachineBasicBlock::iterator OldInsertPt = FuncInfo.InsertPt;
364 DebugLoc OldDL = DbgLoc;
367 SavePoint SP = {OldInsertPt, OldDL};
371 void FastISel::leaveLocalValueArea(SavePoint OldInsertPt) {
372 if (FuncInfo.InsertPt != FuncInfo.MBB->begin())
373 LastLocalValue = std::prev(FuncInfo.InsertPt);
375 // Restore the previous insert position.
376 FuncInfo.InsertPt = OldInsertPt.InsertPt;
377 DbgLoc = OldInsertPt.DL;
380 bool FastISel::selectBinaryOp(const User *I, unsigned ISDOpcode) {
381 EVT VT = EVT::getEVT(I->getType(), /*HandleUnknown=*/true);
382 if (VT == MVT::Other || !VT.isSimple())
383 // Unhandled type. Halt "fast" selection and bail.
386 // We only handle legal types. For example, on x86-32 the instruction
387 // selector contains all of the 64-bit instructions from x86-64,
388 // under the assumption that i64 won't be used if the target doesn't
390 if (!TLI.isTypeLegal(VT)) {
391 // MVT::i1 is special. Allow AND, OR, or XOR because they
392 // don't require additional zeroing, which makes them easy.
393 if (VT == MVT::i1 && (ISDOpcode == ISD::AND || ISDOpcode == ISD::OR ||
394 ISDOpcode == ISD::XOR))
395 VT = TLI.getTypeToTransformTo(I->getContext(), VT);
400 // Check if the first operand is a constant, and handle it as "ri". At -O0,
401 // we don't have anything that canonicalizes operand order.
402 if (const auto *CI = dyn_cast<ConstantInt>(I->getOperand(0)))
403 if (isa<Instruction>(I) && cast<Instruction>(I)->isCommutative()) {
404 unsigned Op1 = getRegForValue(I->getOperand(1));
407 bool Op1IsKill = hasTrivialKill(I->getOperand(1));
410 fastEmit_ri_(VT.getSimpleVT(), ISDOpcode, Op1, Op1IsKill,
411 CI->getZExtValue(), VT.getSimpleVT());
415 // We successfully emitted code for the given LLVM Instruction.
416 updateValueMap(I, ResultReg);
420 unsigned Op0 = getRegForValue(I->getOperand(0));
421 if (!Op0) // Unhandled operand. Halt "fast" selection and bail.
423 bool Op0IsKill = hasTrivialKill(I->getOperand(0));
425 // Check if the second operand is a constant and handle it appropriately.
426 if (const auto *CI = dyn_cast<ConstantInt>(I->getOperand(1))) {
427 uint64_t Imm = CI->getZExtValue();
429 // Transform "sdiv exact X, 8" -> "sra X, 3".
430 if (ISDOpcode == ISD::SDIV && isa<BinaryOperator>(I) &&
431 cast<BinaryOperator>(I)->isExact() && isPowerOf2_64(Imm)) {
433 ISDOpcode = ISD::SRA;
436 // Transform "urem x, pow2" -> "and x, pow2-1".
437 if (ISDOpcode == ISD::UREM && isa<BinaryOperator>(I) &&
438 isPowerOf2_64(Imm)) {
440 ISDOpcode = ISD::AND;
443 unsigned ResultReg = fastEmit_ri_(VT.getSimpleVT(), ISDOpcode, Op0,
444 Op0IsKill, Imm, VT.getSimpleVT());
448 // We successfully emitted code for the given LLVM Instruction.
449 updateValueMap(I, ResultReg);
453 // Check if the second operand is a constant float.
454 if (const auto *CF = dyn_cast<ConstantFP>(I->getOperand(1))) {
455 unsigned ResultReg = fastEmit_rf(VT.getSimpleVT(), VT.getSimpleVT(),
456 ISDOpcode, Op0, Op0IsKill, CF);
458 // We successfully emitted code for the given LLVM Instruction.
459 updateValueMap(I, ResultReg);
464 unsigned Op1 = getRegForValue(I->getOperand(1));
465 if (!Op1) // Unhandled operand. Halt "fast" selection and bail.
467 bool Op1IsKill = hasTrivialKill(I->getOperand(1));
469 // Now we have both operands in registers. Emit the instruction.
470 unsigned ResultReg = fastEmit_rr(VT.getSimpleVT(), VT.getSimpleVT(),
471 ISDOpcode, Op0, Op0IsKill, Op1, Op1IsKill);
473 // Target-specific code wasn't able to find a machine opcode for
474 // the given ISD opcode and type. Halt "fast" selection and bail.
477 // We successfully emitted code for the given LLVM Instruction.
478 updateValueMap(I, ResultReg);
482 bool FastISel::selectGetElementPtr(const User *I) {
483 unsigned N = getRegForValue(I->getOperand(0));
484 if (!N) // Unhandled operand. Halt "fast" selection and bail.
486 bool NIsKill = hasTrivialKill(I->getOperand(0));
488 // Keep a running tab of the total offset to coalesce multiple N = N + Offset
489 // into a single N = N + TotalOffset.
490 uint64_t TotalOffs = 0;
491 // FIXME: What's a good SWAG number for MaxOffs?
492 uint64_t MaxOffs = 2048;
493 Type *Ty = I->getOperand(0)->getType();
494 MVT VT = TLI.getPointerTy();
495 for (GetElementPtrInst::const_op_iterator OI = I->op_begin() + 1,
498 const Value *Idx = *OI;
499 if (auto *StTy = dyn_cast<StructType>(Ty)) {
500 unsigned Field = cast<ConstantInt>(Idx)->getZExtValue();
503 TotalOffs += DL.getStructLayout(StTy)->getElementOffset(Field);
504 if (TotalOffs >= MaxOffs) {
505 N = fastEmit_ri_(VT, ISD::ADD, N, NIsKill, TotalOffs, VT);
506 if (!N) // Unhandled operand. Halt "fast" selection and bail.
512 Ty = StTy->getElementType(Field);
514 Ty = cast<SequentialType>(Ty)->getElementType();
516 // If this is a constant subscript, handle it quickly.
517 if (const auto *CI = dyn_cast<ConstantInt>(Idx)) {
522 DL.getTypeAllocSize(Ty) * cast<ConstantInt>(CI)->getSExtValue();
523 if (TotalOffs >= MaxOffs) {
524 N = fastEmit_ri_(VT, ISD::ADD, N, NIsKill, TotalOffs, VT);
525 if (!N) // Unhandled operand. Halt "fast" selection and bail.
533 N = fastEmit_ri_(VT, ISD::ADD, N, NIsKill, TotalOffs, VT);
534 if (!N) // Unhandled operand. Halt "fast" selection and bail.
540 // N = N + Idx * ElementSize;
541 uint64_t ElementSize = DL.getTypeAllocSize(Ty);
542 std::pair<unsigned, bool> Pair = getRegForGEPIndex(Idx);
543 unsigned IdxN = Pair.first;
544 bool IdxNIsKill = Pair.second;
545 if (!IdxN) // Unhandled operand. Halt "fast" selection and bail.
548 if (ElementSize != 1) {
549 IdxN = fastEmit_ri_(VT, ISD::MUL, IdxN, IdxNIsKill, ElementSize, VT);
550 if (!IdxN) // Unhandled operand. Halt "fast" selection and bail.
554 N = fastEmit_rr(VT, VT, ISD::ADD, N, NIsKill, IdxN, IdxNIsKill);
555 if (!N) // Unhandled operand. Halt "fast" selection and bail.
560 N = fastEmit_ri_(VT, ISD::ADD, N, NIsKill, TotalOffs, VT);
561 if (!N) // Unhandled operand. Halt "fast" selection and bail.
565 // We successfully emitted code for the given LLVM Instruction.
566 updateValueMap(I, N);
570 bool FastISel::addStackMapLiveVars(SmallVectorImpl<MachineOperand> &Ops,
571 const CallInst *CI, unsigned StartIdx) {
572 for (unsigned i = StartIdx, e = CI->getNumArgOperands(); i != e; ++i) {
573 Value *Val = CI->getArgOperand(i);
574 // Check for constants and encode them with a StackMaps::ConstantOp prefix.
575 if (const auto *C = dyn_cast<ConstantInt>(Val)) {
576 Ops.push_back(MachineOperand::CreateImm(StackMaps::ConstantOp));
577 Ops.push_back(MachineOperand::CreateImm(C->getSExtValue()));
578 } else if (isa<ConstantPointerNull>(Val)) {
579 Ops.push_back(MachineOperand::CreateImm(StackMaps::ConstantOp));
580 Ops.push_back(MachineOperand::CreateImm(0));
581 } else if (auto *AI = dyn_cast<AllocaInst>(Val)) {
582 // Values coming from a stack location also require a sepcial encoding,
583 // but that is added later on by the target specific frame index
584 // elimination implementation.
585 auto SI = FuncInfo.StaticAllocaMap.find(AI);
586 if (SI != FuncInfo.StaticAllocaMap.end())
587 Ops.push_back(MachineOperand::CreateFI(SI->second));
591 unsigned Reg = getRegForValue(Val);
594 Ops.push_back(MachineOperand::CreateReg(Reg, /*IsDef=*/false));
600 bool FastISel::selectStackmap(const CallInst *I) {
601 // void @llvm.experimental.stackmap(i64 <id>, i32 <numShadowBytes>,
602 // [live variables...])
603 assert(I->getCalledFunction()->getReturnType()->isVoidTy() &&
604 "Stackmap cannot return a value.");
606 // The stackmap intrinsic only records the live variables (the arguments
607 // passed to it) and emits NOPS (if requested). Unlike the patchpoint
608 // intrinsic, this won't be lowered to a function call. This means we don't
609 // have to worry about calling conventions and target-specific lowering code.
610 // Instead we perform the call lowering right here.
613 // STACKMAP(id, nbytes, ...)
616 SmallVector<MachineOperand, 32> Ops;
618 // Add the <id> and <numBytes> constants.
619 assert(isa<ConstantInt>(I->getOperand(PatchPointOpers::IDPos)) &&
620 "Expected a constant integer.");
621 const auto *ID = cast<ConstantInt>(I->getOperand(PatchPointOpers::IDPos));
622 Ops.push_back(MachineOperand::CreateImm(ID->getZExtValue()));
624 assert(isa<ConstantInt>(I->getOperand(PatchPointOpers::NBytesPos)) &&
625 "Expected a constant integer.");
626 const auto *NumBytes =
627 cast<ConstantInt>(I->getOperand(PatchPointOpers::NBytesPos));
628 Ops.push_back(MachineOperand::CreateImm(NumBytes->getZExtValue()));
630 // Push live variables for the stack map (skipping the first two arguments
631 // <id> and <numBytes>).
632 if (!addStackMapLiveVars(Ops, I, 2))
635 // We are not adding any register mask info here, because the stackmap doesn't
638 // Add scratch registers as implicit def and early clobber.
639 CallingConv::ID CC = I->getCallingConv();
640 const MCPhysReg *ScratchRegs = TLI.getScratchRegisters(CC);
641 for (unsigned i = 0; ScratchRegs[i]; ++i)
642 Ops.push_back(MachineOperand::CreateReg(
643 ScratchRegs[i], /*IsDef=*/true, /*IsImp=*/true, /*IsKill=*/false,
644 /*IsDead=*/false, /*IsUndef=*/false, /*IsEarlyClobber=*/true));
646 // Issue CALLSEQ_START
647 unsigned AdjStackDown = TII.getCallFrameSetupOpcode();
648 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AdjStackDown))
652 MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
653 TII.get(TargetOpcode::STACKMAP));
654 for (auto const &MO : Ops)
658 unsigned AdjStackUp = TII.getCallFrameDestroyOpcode();
659 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AdjStackUp))
663 // Inform the Frame Information that we have a stackmap in this function.
664 FuncInfo.MF->getFrameInfo()->setHasStackMap();
669 /// \brief Lower an argument list according to the target calling convention.
671 /// This is a helper for lowering intrinsics that follow a target calling
672 /// convention or require stack pointer adjustment. Only a subset of the
673 /// intrinsic's operands need to participate in the calling convention.
674 bool FastISel::lowerCallOperands(const CallInst *CI, unsigned ArgIdx,
675 unsigned NumArgs, const Value *Callee,
676 bool ForceRetVoidTy, CallLoweringInfo &CLI) {
678 Args.reserve(NumArgs);
680 // Populate the argument list.
681 // Attributes for args start at offset 1, after the return attribute.
682 ImmutableCallSite CS(CI);
683 for (unsigned ArgI = ArgIdx, ArgE = ArgIdx + NumArgs, AttrI = ArgIdx + 1;
684 ArgI != ArgE; ++ArgI) {
685 Value *V = CI->getOperand(ArgI);
687 assert(!V->getType()->isEmptyTy() && "Empty type passed to intrinsic.");
691 Entry.Ty = V->getType();
692 Entry.setAttributes(&CS, AttrI);
693 Args.push_back(Entry);
696 Type *RetTy = ForceRetVoidTy ? Type::getVoidTy(CI->getType()->getContext())
698 CLI.setCallee(CI->getCallingConv(), RetTy, Callee, std::move(Args), NumArgs);
700 return lowerCallTo(CLI);
703 bool FastISel::selectPatchpoint(const CallInst *I) {
704 // void|i64 @llvm.experimental.patchpoint.void|i64(i64 <id>,
709 // [live variables...])
710 CallingConv::ID CC = I->getCallingConv();
711 bool IsAnyRegCC = CC == CallingConv::AnyReg;
712 bool HasDef = !I->getType()->isVoidTy();
713 Value *Callee = I->getOperand(PatchPointOpers::TargetPos);
715 // Get the real number of arguments participating in the call <numArgs>
716 assert(isa<ConstantInt>(I->getOperand(PatchPointOpers::NArgPos)) &&
717 "Expected a constant integer.");
718 const auto *NumArgsVal =
719 cast<ConstantInt>(I->getOperand(PatchPointOpers::NArgPos));
720 unsigned NumArgs = NumArgsVal->getZExtValue();
722 // Skip the four meta args: <id>, <numNopBytes>, <target>, <numArgs>
723 // This includes all meta-operands up to but not including CC.
724 unsigned NumMetaOpers = PatchPointOpers::CCPos;
725 assert(I->getNumArgOperands() >= NumMetaOpers + NumArgs &&
726 "Not enough arguments provided to the patchpoint intrinsic");
728 // For AnyRegCC the arguments are lowered later on manually.
729 unsigned NumCallArgs = IsAnyRegCC ? 0 : NumArgs;
730 CallLoweringInfo CLI;
731 CLI.setIsPatchPoint();
732 if (!lowerCallOperands(I, NumMetaOpers, NumCallArgs, Callee, IsAnyRegCC, CLI))
735 assert(CLI.Call && "No call instruction specified.");
737 SmallVector<MachineOperand, 32> Ops;
739 // Add an explicit result reg if we use the anyreg calling convention.
740 if (IsAnyRegCC && HasDef) {
741 assert(CLI.NumResultRegs == 0 && "Unexpected result register.");
742 CLI.ResultReg = createResultReg(TLI.getRegClassFor(MVT::i64));
743 CLI.NumResultRegs = 1;
744 Ops.push_back(MachineOperand::CreateReg(CLI.ResultReg, /*IsDef=*/true));
747 // Add the <id> and <numBytes> constants.
748 assert(isa<ConstantInt>(I->getOperand(PatchPointOpers::IDPos)) &&
749 "Expected a constant integer.");
750 const auto *ID = cast<ConstantInt>(I->getOperand(PatchPointOpers::IDPos));
751 Ops.push_back(MachineOperand::CreateImm(ID->getZExtValue()));
753 assert(isa<ConstantInt>(I->getOperand(PatchPointOpers::NBytesPos)) &&
754 "Expected a constant integer.");
755 const auto *NumBytes =
756 cast<ConstantInt>(I->getOperand(PatchPointOpers::NBytesPos));
757 Ops.push_back(MachineOperand::CreateImm(NumBytes->getZExtValue()));
759 // Assume that the callee is a constant address or null pointer.
760 // FIXME: handle function symbols in the future.
762 if (const auto *C = dyn_cast<IntToPtrInst>(Callee))
763 CalleeAddr = cast<ConstantInt>(C->getOperand(0))->getZExtValue();
764 else if (const auto *C = dyn_cast<ConstantExpr>(Callee)) {
765 if (C->getOpcode() == Instruction::IntToPtr)
766 CalleeAddr = cast<ConstantInt>(C->getOperand(0))->getZExtValue();
768 llvm_unreachable("Unsupported ConstantExpr.");
769 } else if (isa<ConstantPointerNull>(Callee))
772 llvm_unreachable("Unsupported callee address.");
774 Ops.push_back(MachineOperand::CreateImm(CalleeAddr));
776 // Adjust <numArgs> to account for any arguments that have been passed on
777 // the stack instead.
778 unsigned NumCallRegArgs = IsAnyRegCC ? NumArgs : CLI.OutRegs.size();
779 Ops.push_back(MachineOperand::CreateImm(NumCallRegArgs));
781 // Add the calling convention
782 Ops.push_back(MachineOperand::CreateImm((unsigned)CC));
784 // Add the arguments we omitted previously. The register allocator should
785 // place these in any free register.
787 for (unsigned i = NumMetaOpers, e = NumMetaOpers + NumArgs; i != e; ++i) {
788 unsigned Reg = getRegForValue(I->getArgOperand(i));
791 Ops.push_back(MachineOperand::CreateReg(Reg, /*IsDef=*/false));
795 // Push the arguments from the call instruction.
796 for (auto Reg : CLI.OutRegs)
797 Ops.push_back(MachineOperand::CreateReg(Reg, /*IsDef=*/false));
799 // Push live variables for the stack map.
800 if (!addStackMapLiveVars(Ops, I, NumMetaOpers + NumArgs))
803 // Push the register mask info.
804 Ops.push_back(MachineOperand::CreateRegMask(
805 TRI.getCallPreservedMask(*FuncInfo.MF, CC)));
807 // Add scratch registers as implicit def and early clobber.
808 const MCPhysReg *ScratchRegs = TLI.getScratchRegisters(CC);
809 for (unsigned i = 0; ScratchRegs[i]; ++i)
810 Ops.push_back(MachineOperand::CreateReg(
811 ScratchRegs[i], /*IsDef=*/true, /*IsImp=*/true, /*IsKill=*/false,
812 /*IsDead=*/false, /*IsUndef=*/false, /*IsEarlyClobber=*/true));
814 // Add implicit defs (return values).
815 for (auto Reg : CLI.InRegs)
816 Ops.push_back(MachineOperand::CreateReg(Reg, /*IsDef=*/true,
819 // Insert the patchpoint instruction before the call generated by the target.
820 MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, CLI.Call, DbgLoc,
821 TII.get(TargetOpcode::PATCHPOINT));
826 MIB->setPhysRegsDeadExcept(CLI.InRegs, TRI);
828 // Delete the original call instruction.
829 CLI.Call->eraseFromParent();
831 // Inform the Frame Information that we have a patchpoint in this function.
832 FuncInfo.MF->getFrameInfo()->setHasPatchPoint();
834 if (CLI.NumResultRegs)
835 updateValueMap(I, CLI.ResultReg, CLI.NumResultRegs);
839 /// Returns an AttributeSet representing the attributes applied to the return
840 /// value of the given call.
841 static AttributeSet getReturnAttrs(FastISel::CallLoweringInfo &CLI) {
842 SmallVector<Attribute::AttrKind, 2> Attrs;
844 Attrs.push_back(Attribute::SExt);
846 Attrs.push_back(Attribute::ZExt);
848 Attrs.push_back(Attribute::InReg);
850 return AttributeSet::get(CLI.RetTy->getContext(), AttributeSet::ReturnIndex,
854 bool FastISel::lowerCallTo(const CallInst *CI, const char *SymName,
856 ImmutableCallSite CS(CI);
858 PointerType *PT = cast<PointerType>(CS.getCalledValue()->getType());
859 FunctionType *FTy = cast<FunctionType>(PT->getElementType());
860 Type *RetTy = FTy->getReturnType();
863 Args.reserve(NumArgs);
865 // Populate the argument list.
866 // Attributes for args start at offset 1, after the return attribute.
867 for (unsigned ArgI = 0; ArgI != NumArgs; ++ArgI) {
868 Value *V = CI->getOperand(ArgI);
870 assert(!V->getType()->isEmptyTy() && "Empty type passed to intrinsic.");
874 Entry.Ty = V->getType();
875 Entry.setAttributes(&CS, ArgI + 1);
876 Args.push_back(Entry);
879 CallLoweringInfo CLI;
880 CLI.setCallee(RetTy, FTy, SymName, std::move(Args), CS, NumArgs);
882 return lowerCallTo(CLI);
885 bool FastISel::lowerCallTo(CallLoweringInfo &CLI) {
886 // Handle the incoming return values from the call.
888 SmallVector<EVT, 4> RetTys;
889 ComputeValueVTs(TLI, CLI.RetTy, RetTys);
891 SmallVector<ISD::OutputArg, 4> Outs;
892 GetReturnInfo(CLI.RetTy, getReturnAttrs(CLI), Outs, TLI);
894 bool CanLowerReturn = TLI.CanLowerReturn(
895 CLI.CallConv, *FuncInfo.MF, CLI.IsVarArg, Outs, CLI.RetTy->getContext());
897 // FIXME: sret demotion isn't supported yet - bail out.
901 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
903 MVT RegisterVT = TLI.getRegisterType(CLI.RetTy->getContext(), VT);
904 unsigned NumRegs = TLI.getNumRegisters(CLI.RetTy->getContext(), VT);
905 for (unsigned i = 0; i != NumRegs; ++i) {
906 ISD::InputArg MyFlags;
907 MyFlags.VT = RegisterVT;
909 MyFlags.Used = CLI.IsReturnValueUsed;
911 MyFlags.Flags.setSExt();
913 MyFlags.Flags.setZExt();
915 MyFlags.Flags.setInReg();
916 CLI.Ins.push_back(MyFlags);
920 // Handle all of the outgoing arguments.
922 for (auto &Arg : CLI.getArgs()) {
923 Type *FinalType = Arg.Ty;
925 FinalType = cast<PointerType>(Arg.Ty)->getElementType();
926 bool NeedsRegBlock = TLI.functionArgumentNeedsConsecutiveRegisters(
927 FinalType, CLI.CallConv, CLI.IsVarArg);
929 ISD::ArgFlagsTy Flags;
940 if (Arg.IsInAlloca) {
942 // Set the byval flag for CCAssignFn callbacks that don't know about
943 // inalloca. This way we can know how many bytes we should've allocated
944 // and how many bytes a callee cleanup function will pop. If we port
945 // inalloca to more targets, we'll have to add custom inalloca handling in
946 // the various CC lowering callbacks.
949 if (Arg.IsByVal || Arg.IsInAlloca) {
950 PointerType *Ty = cast<PointerType>(Arg.Ty);
951 Type *ElementTy = Ty->getElementType();
952 unsigned FrameSize = DL.getTypeAllocSize(ElementTy);
953 // For ByVal, alignment should come from FE. BE will guess if this info is
954 // not there, but there are cases it cannot get right.
955 unsigned FrameAlign = Arg.Alignment;
957 FrameAlign = TLI.getByValTypeAlignment(ElementTy);
958 Flags.setByValSize(FrameSize);
959 Flags.setByValAlign(FrameAlign);
964 Flags.setInConsecutiveRegs();
965 unsigned OriginalAlignment = DL.getABITypeAlignment(Arg.Ty);
966 Flags.setOrigAlign(OriginalAlignment);
968 CLI.OutVals.push_back(Arg.Val);
969 CLI.OutFlags.push_back(Flags);
972 if (!fastLowerCall(CLI))
975 // Set all unused physreg defs as dead.
976 assert(CLI.Call && "No call instruction specified.");
977 CLI.Call->setPhysRegsDeadExcept(CLI.InRegs, TRI);
979 if (CLI.NumResultRegs && CLI.CS)
980 updateValueMap(CLI.CS->getInstruction(), CLI.ResultReg, CLI.NumResultRegs);
985 bool FastISel::lowerCall(const CallInst *CI) {
986 ImmutableCallSite CS(CI);
988 PointerType *PT = cast<PointerType>(CS.getCalledValue()->getType());
989 FunctionType *FuncTy = cast<FunctionType>(PT->getElementType());
990 Type *RetTy = FuncTy->getReturnType();
994 Args.reserve(CS.arg_size());
996 for (ImmutableCallSite::arg_iterator i = CS.arg_begin(), e = CS.arg_end();
1001 if (V->getType()->isEmptyTy())
1005 Entry.Ty = V->getType();
1007 // Skip the first return-type Attribute to get to params.
1008 Entry.setAttributes(&CS, i - CS.arg_begin() + 1);
1009 Args.push_back(Entry);
1012 // Check if target-independent constraints permit a tail call here.
1013 // Target-dependent constraints are checked within fastLowerCall.
1014 bool IsTailCall = CI->isTailCall();
1015 if (IsTailCall && !isInTailCallPosition(CS, TM))
1018 CallLoweringInfo CLI;
1019 CLI.setCallee(RetTy, FuncTy, CI->getCalledValue(), std::move(Args), CS)
1020 .setTailCall(IsTailCall);
1022 return lowerCallTo(CLI);
1025 bool FastISel::selectCall(const User *I) {
1026 const CallInst *Call = cast<CallInst>(I);
1028 // Handle simple inline asms.
1029 if (const InlineAsm *IA = dyn_cast<InlineAsm>(Call->getCalledValue())) {
1030 // If the inline asm has side effects, then make sure that no local value
1031 // lives across by flushing the local value map.
1032 if (IA->hasSideEffects())
1033 flushLocalValueMap();
1035 // Don't attempt to handle constraints.
1036 if (!IA->getConstraintString().empty())
1039 unsigned ExtraInfo = 0;
1040 if (IA->hasSideEffects())
1041 ExtraInfo |= InlineAsm::Extra_HasSideEffects;
1042 if (IA->isAlignStack())
1043 ExtraInfo |= InlineAsm::Extra_IsAlignStack;
1045 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1046 TII.get(TargetOpcode::INLINEASM))
1047 .addExternalSymbol(IA->getAsmString().c_str())
1052 MachineModuleInfo &MMI = FuncInfo.MF->getMMI();
1053 ComputeUsesVAFloatArgument(*Call, &MMI);
1055 // Handle intrinsic function calls.
1056 if (const auto *II = dyn_cast<IntrinsicInst>(Call))
1057 return selectIntrinsicCall(II);
1059 // Usually, it does not make sense to initialize a value,
1060 // make an unrelated function call and use the value, because
1061 // it tends to be spilled on the stack. So, we move the pointer
1062 // to the last local value to the beginning of the block, so that
1063 // all the values which have already been materialized,
1064 // appear after the call. It also makes sense to skip intrinsics
1065 // since they tend to be inlined.
1066 flushLocalValueMap();
1068 return lowerCall(Call);
1071 bool FastISel::selectIntrinsicCall(const IntrinsicInst *II) {
1072 switch (II->getIntrinsicID()) {
1075 // At -O0 we don't care about the lifetime intrinsics.
1076 case Intrinsic::lifetime_start:
1077 case Intrinsic::lifetime_end:
1078 // The donothing intrinsic does, well, nothing.
1079 case Intrinsic::donothing:
1081 case Intrinsic::dbg_declare: {
1082 const DbgDeclareInst *DI = cast<DbgDeclareInst>(II);
1083 DIVariable DIVar(DI->getVariable());
1084 assert((!DIVar || DIVar.isVariable()) &&
1085 "Variable in DbgDeclareInst should be either null or a DIVariable.");
1086 if (!DIVar || !FuncInfo.MF->getMMI().hasDebugInfo()) {
1087 DEBUG(dbgs() << "Dropping debug info for " << *DI << "\n");
1091 const Value *Address = DI->getAddress();
1092 if (!Address || isa<UndefValue>(Address)) {
1093 DEBUG(dbgs() << "Dropping debug info for " << *DI << "\n");
1097 unsigned Offset = 0;
1098 Optional<MachineOperand> Op;
1099 if (const auto *Arg = dyn_cast<Argument>(Address))
1100 // Some arguments' frame index is recorded during argument lowering.
1101 Offset = FuncInfo.getArgumentFrameIndex(Arg);
1103 Op = MachineOperand::CreateFI(Offset);
1105 if (unsigned Reg = lookUpRegForValue(Address))
1106 Op = MachineOperand::CreateReg(Reg, false);
1108 // If we have a VLA that has a "use" in a metadata node that's then used
1109 // here but it has no other uses, then we have a problem. E.g.,
1111 // int foo (const int *x) {
1116 // If we assign 'a' a vreg and fast isel later on has to use the selection
1117 // DAG isel, it will want to copy the value to the vreg. However, there are
1118 // no uses, which goes counter to what selection DAG isel expects.
1119 if (!Op && !Address->use_empty() && isa<Instruction>(Address) &&
1120 (!isa<AllocaInst>(Address) ||
1121 !FuncInfo.StaticAllocaMap.count(cast<AllocaInst>(Address))))
1122 Op = MachineOperand::CreateReg(FuncInfo.InitializeRegForValue(Address),
1127 Op->setIsDebug(true);
1128 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1129 TII.get(TargetOpcode::DBG_VALUE), false, Op->getReg(), 0,
1130 DI->getVariable(), DI->getExpression());
1132 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1133 TII.get(TargetOpcode::DBG_VALUE))
1136 .addMetadata(DI->getVariable())
1137 .addMetadata(DI->getExpression());
1139 // We can't yet handle anything else here because it would require
1140 // generating code, thus altering codegen because of debug info.
1141 DEBUG(dbgs() << "Dropping debug info for " << *DI << "\n");
1145 case Intrinsic::dbg_value: {
1146 // This form of DBG_VALUE is target-independent.
1147 const DbgValueInst *DI = cast<DbgValueInst>(II);
1148 const MCInstrDesc &II = TII.get(TargetOpcode::DBG_VALUE);
1149 const Value *V = DI->getValue();
1151 // Currently the optimizer can produce this; insert an undef to
1152 // help debugging. Probably the optimizer should not do this.
1153 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II)
1155 .addImm(DI->getOffset())
1156 .addMetadata(DI->getVariable())
1157 .addMetadata(DI->getExpression());
1158 } else if (const auto *CI = dyn_cast<ConstantInt>(V)) {
1159 if (CI->getBitWidth() > 64)
1160 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II)
1162 .addImm(DI->getOffset())
1163 .addMetadata(DI->getVariable())
1164 .addMetadata(DI->getExpression());
1166 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II)
1167 .addImm(CI->getZExtValue())
1168 .addImm(DI->getOffset())
1169 .addMetadata(DI->getVariable())
1170 .addMetadata(DI->getExpression());
1171 } else if (const auto *CF = dyn_cast<ConstantFP>(V)) {
1172 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II)
1174 .addImm(DI->getOffset())
1175 .addMetadata(DI->getVariable())
1176 .addMetadata(DI->getExpression());
1177 } else if (unsigned Reg = lookUpRegForValue(V)) {
1178 // FIXME: This does not handle register-indirect values at offset 0.
1179 bool IsIndirect = DI->getOffset() != 0;
1180 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, IsIndirect, Reg,
1181 DI->getOffset(), DI->getVariable(), DI->getExpression());
1183 // We can't yet handle anything else here because it would require
1184 // generating code, thus altering codegen because of debug info.
1185 DEBUG(dbgs() << "Dropping debug info for " << *DI << "\n");
1189 case Intrinsic::objectsize: {
1190 ConstantInt *CI = cast<ConstantInt>(II->getArgOperand(1));
1191 unsigned long long Res = CI->isZero() ? -1ULL : 0;
1192 Constant *ResCI = ConstantInt::get(II->getType(), Res);
1193 unsigned ResultReg = getRegForValue(ResCI);
1196 updateValueMap(II, ResultReg);
1199 case Intrinsic::expect: {
1200 unsigned ResultReg = getRegForValue(II->getArgOperand(0));
1203 updateValueMap(II, ResultReg);
1206 case Intrinsic::experimental_stackmap:
1207 return selectStackmap(II);
1208 case Intrinsic::experimental_patchpoint_void:
1209 case Intrinsic::experimental_patchpoint_i64:
1210 return selectPatchpoint(II);
1213 return fastLowerIntrinsicCall(II);
1216 bool FastISel::selectCast(const User *I, unsigned Opcode) {
1217 EVT SrcVT = TLI.getValueType(I->getOperand(0)->getType());
1218 EVT DstVT = TLI.getValueType(I->getType());
1220 if (SrcVT == MVT::Other || !SrcVT.isSimple() || DstVT == MVT::Other ||
1222 // Unhandled type. Halt "fast" selection and bail.
1225 // Check if the destination type is legal.
1226 if (!TLI.isTypeLegal(DstVT))
1229 // Check if the source operand is legal.
1230 if (!TLI.isTypeLegal(SrcVT))
1233 unsigned InputReg = getRegForValue(I->getOperand(0));
1235 // Unhandled operand. Halt "fast" selection and bail.
1238 bool InputRegIsKill = hasTrivialKill(I->getOperand(0));
1240 unsigned ResultReg = fastEmit_r(SrcVT.getSimpleVT(), DstVT.getSimpleVT(),
1241 Opcode, InputReg, InputRegIsKill);
1245 updateValueMap(I, ResultReg);
1249 bool FastISel::selectBitCast(const User *I) {
1250 // If the bitcast doesn't change the type, just use the operand value.
1251 if (I->getType() == I->getOperand(0)->getType()) {
1252 unsigned Reg = getRegForValue(I->getOperand(0));
1255 updateValueMap(I, Reg);
1259 // Bitcasts of other values become reg-reg copies or BITCAST operators.
1260 EVT SrcEVT = TLI.getValueType(I->getOperand(0)->getType());
1261 EVT DstEVT = TLI.getValueType(I->getType());
1262 if (SrcEVT == MVT::Other || DstEVT == MVT::Other ||
1263 !TLI.isTypeLegal(SrcEVT) || !TLI.isTypeLegal(DstEVT))
1264 // Unhandled type. Halt "fast" selection and bail.
1267 MVT SrcVT = SrcEVT.getSimpleVT();
1268 MVT DstVT = DstEVT.getSimpleVT();
1269 unsigned Op0 = getRegForValue(I->getOperand(0));
1270 if (!Op0) // Unhandled operand. Halt "fast" selection and bail.
1272 bool Op0IsKill = hasTrivialKill(I->getOperand(0));
1274 // First, try to perform the bitcast by inserting a reg-reg copy.
1275 unsigned ResultReg = 0;
1276 if (SrcVT == DstVT) {
1277 const TargetRegisterClass *SrcClass = TLI.getRegClassFor(SrcVT);
1278 const TargetRegisterClass *DstClass = TLI.getRegClassFor(DstVT);
1279 // Don't attempt a cross-class copy. It will likely fail.
1280 if (SrcClass == DstClass) {
1281 ResultReg = createResultReg(DstClass);
1282 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1283 TII.get(TargetOpcode::COPY), ResultReg).addReg(Op0);
1287 // If the reg-reg copy failed, select a BITCAST opcode.
1289 ResultReg = fastEmit_r(SrcVT, DstVT, ISD::BITCAST, Op0, Op0IsKill);
1294 updateValueMap(I, ResultReg);
1298 bool FastISel::selectInstruction(const Instruction *I) {
1299 // Just before the terminator instruction, insert instructions to
1300 // feed PHI nodes in successor blocks.
1301 if (isa<TerminatorInst>(I))
1302 if (!handlePHINodesInSuccessorBlocks(I->getParent()))
1305 DbgLoc = I->getDebugLoc();
1307 SavedInsertPt = FuncInfo.InsertPt;
1309 if (const auto *Call = dyn_cast<CallInst>(I)) {
1310 const Function *F = Call->getCalledFunction();
1313 // As a special case, don't handle calls to builtin library functions that
1314 // may be translated directly to target instructions.
1315 if (F && !F->hasLocalLinkage() && F->hasName() &&
1316 LibInfo->getLibFunc(F->getName(), Func) &&
1317 LibInfo->hasOptimizedCodeGen(Func))
1320 // Don't handle Intrinsic::trap if a trap funciton is specified.
1321 if (F && F->getIntrinsicID() == Intrinsic::trap &&
1322 !TM.Options.getTrapFunctionName().empty())
1326 // First, try doing target-independent selection.
1327 if (!SkipTargetIndependentISel) {
1328 if (selectOperator(I, I->getOpcode())) {
1329 ++NumFastIselSuccessIndependent;
1330 DbgLoc = DebugLoc();
1333 // Remove dead code.
1334 recomputeInsertPt();
1335 if (SavedInsertPt != FuncInfo.InsertPt)
1336 removeDeadCode(FuncInfo.InsertPt, SavedInsertPt);
1337 SavedInsertPt = FuncInfo.InsertPt;
1339 // Next, try calling the target to attempt to handle the instruction.
1340 if (fastSelectInstruction(I)) {
1341 ++NumFastIselSuccessTarget;
1342 DbgLoc = DebugLoc();
1345 // Remove dead code.
1346 recomputeInsertPt();
1347 if (SavedInsertPt != FuncInfo.InsertPt)
1348 removeDeadCode(FuncInfo.InsertPt, SavedInsertPt);
1350 DbgLoc = DebugLoc();
1351 // Undo phi node updates, because they will be added again by SelectionDAG.
1352 if (isa<TerminatorInst>(I))
1353 FuncInfo.PHINodesToUpdate.resize(FuncInfo.OrigNumPHINodesToUpdate);
1357 /// Emit an unconditional branch to the given block, unless it is the immediate
1358 /// (fall-through) successor, and update the CFG.
1359 void FastISel::fastEmitBranch(MachineBasicBlock *MSucc, DebugLoc DbgLoc) {
1360 if (FuncInfo.MBB->getBasicBlock()->size() > 1 &&
1361 FuncInfo.MBB->isLayoutSuccessor(MSucc)) {
1362 // For more accurate line information if this is the only instruction
1363 // in the block then emit it, otherwise we have the unconditional
1364 // fall-through case, which needs no instructions.
1366 // The unconditional branch case.
1367 TII.InsertBranch(*FuncInfo.MBB, MSucc, nullptr,
1368 SmallVector<MachineOperand, 0>(), DbgLoc);
1370 uint32_t BranchWeight = 0;
1372 BranchWeight = FuncInfo.BPI->getEdgeWeight(FuncInfo.MBB->getBasicBlock(),
1373 MSucc->getBasicBlock());
1374 FuncInfo.MBB->addSuccessor(MSucc, BranchWeight);
1377 /// Emit an FNeg operation.
1378 bool FastISel::selectFNeg(const User *I) {
1379 unsigned OpReg = getRegForValue(BinaryOperator::getFNegArgument(I));
1382 bool OpRegIsKill = hasTrivialKill(I);
1384 // If the target has ISD::FNEG, use it.
1385 EVT VT = TLI.getValueType(I->getType());
1386 unsigned ResultReg = fastEmit_r(VT.getSimpleVT(), VT.getSimpleVT(), ISD::FNEG,
1387 OpReg, OpRegIsKill);
1389 updateValueMap(I, ResultReg);
1393 // Bitcast the value to integer, twiddle the sign bit with xor,
1394 // and then bitcast it back to floating-point.
1395 if (VT.getSizeInBits() > 64)
1397 EVT IntVT = EVT::getIntegerVT(I->getContext(), VT.getSizeInBits());
1398 if (!TLI.isTypeLegal(IntVT))
1401 unsigned IntReg = fastEmit_r(VT.getSimpleVT(), IntVT.getSimpleVT(),
1402 ISD::BITCAST, OpReg, OpRegIsKill);
1406 unsigned IntResultReg = fastEmit_ri_(
1407 IntVT.getSimpleVT(), ISD::XOR, IntReg, /*IsKill=*/true,
1408 UINT64_C(1) << (VT.getSizeInBits() - 1), IntVT.getSimpleVT());
1412 ResultReg = fastEmit_r(IntVT.getSimpleVT(), VT.getSimpleVT(), ISD::BITCAST,
1413 IntResultReg, /*IsKill=*/true);
1417 updateValueMap(I, ResultReg);
1421 bool FastISel::selectExtractValue(const User *U) {
1422 const ExtractValueInst *EVI = dyn_cast<ExtractValueInst>(U);
1426 // Make sure we only try to handle extracts with a legal result. But also
1427 // allow i1 because it's easy.
1428 EVT RealVT = TLI.getValueType(EVI->getType(), /*AllowUnknown=*/true);
1429 if (!RealVT.isSimple())
1431 MVT VT = RealVT.getSimpleVT();
1432 if (!TLI.isTypeLegal(VT) && VT != MVT::i1)
1435 const Value *Op0 = EVI->getOperand(0);
1436 Type *AggTy = Op0->getType();
1438 // Get the base result register.
1440 DenseMap<const Value *, unsigned>::iterator I = FuncInfo.ValueMap.find(Op0);
1441 if (I != FuncInfo.ValueMap.end())
1442 ResultReg = I->second;
1443 else if (isa<Instruction>(Op0))
1444 ResultReg = FuncInfo.InitializeRegForValue(Op0);
1446 return false; // fast-isel can't handle aggregate constants at the moment
1448 // Get the actual result register, which is an offset from the base register.
1449 unsigned VTIndex = ComputeLinearIndex(AggTy, EVI->getIndices());
1451 SmallVector<EVT, 4> AggValueVTs;
1452 ComputeValueVTs(TLI, AggTy, AggValueVTs);
1454 for (unsigned i = 0; i < VTIndex; i++)
1455 ResultReg += TLI.getNumRegisters(FuncInfo.Fn->getContext(), AggValueVTs[i]);
1457 updateValueMap(EVI, ResultReg);
1461 bool FastISel::selectOperator(const User *I, unsigned Opcode) {
1463 case Instruction::Add:
1464 return selectBinaryOp(I, ISD::ADD);
1465 case Instruction::FAdd:
1466 return selectBinaryOp(I, ISD::FADD);
1467 case Instruction::Sub:
1468 return selectBinaryOp(I, ISD::SUB);
1469 case Instruction::FSub:
1470 // FNeg is currently represented in LLVM IR as a special case of FSub.
1471 if (BinaryOperator::isFNeg(I))
1472 return selectFNeg(I);
1473 return selectBinaryOp(I, ISD::FSUB);
1474 case Instruction::Mul:
1475 return selectBinaryOp(I, ISD::MUL);
1476 case Instruction::FMul:
1477 return selectBinaryOp(I, ISD::FMUL);
1478 case Instruction::SDiv:
1479 return selectBinaryOp(I, ISD::SDIV);
1480 case Instruction::UDiv:
1481 return selectBinaryOp(I, ISD::UDIV);
1482 case Instruction::FDiv:
1483 return selectBinaryOp(I, ISD::FDIV);
1484 case Instruction::SRem:
1485 return selectBinaryOp(I, ISD::SREM);
1486 case Instruction::URem:
1487 return selectBinaryOp(I, ISD::UREM);
1488 case Instruction::FRem:
1489 return selectBinaryOp(I, ISD::FREM);
1490 case Instruction::Shl:
1491 return selectBinaryOp(I, ISD::SHL);
1492 case Instruction::LShr:
1493 return selectBinaryOp(I, ISD::SRL);
1494 case Instruction::AShr:
1495 return selectBinaryOp(I, ISD::SRA);
1496 case Instruction::And:
1497 return selectBinaryOp(I, ISD::AND);
1498 case Instruction::Or:
1499 return selectBinaryOp(I, ISD::OR);
1500 case Instruction::Xor:
1501 return selectBinaryOp(I, ISD::XOR);
1503 case Instruction::GetElementPtr:
1504 return selectGetElementPtr(I);
1506 case Instruction::Br: {
1507 const BranchInst *BI = cast<BranchInst>(I);
1509 if (BI->isUnconditional()) {
1510 const BasicBlock *LLVMSucc = BI->getSuccessor(0);
1511 MachineBasicBlock *MSucc = FuncInfo.MBBMap[LLVMSucc];
1512 fastEmitBranch(MSucc, BI->getDebugLoc());
1516 // Conditional branches are not handed yet.
1517 // Halt "fast" selection and bail.
1521 case Instruction::Unreachable:
1522 if (TM.Options.TrapUnreachable)
1523 return fastEmit_(MVT::Other, MVT::Other, ISD::TRAP) != 0;
1527 case Instruction::Alloca:
1528 // FunctionLowering has the static-sized case covered.
1529 if (FuncInfo.StaticAllocaMap.count(cast<AllocaInst>(I)))
1532 // Dynamic-sized alloca is not handled yet.
1535 case Instruction::Call:
1536 return selectCall(I);
1538 case Instruction::BitCast:
1539 return selectBitCast(I);
1541 case Instruction::FPToSI:
1542 return selectCast(I, ISD::FP_TO_SINT);
1543 case Instruction::ZExt:
1544 return selectCast(I, ISD::ZERO_EXTEND);
1545 case Instruction::SExt:
1546 return selectCast(I, ISD::SIGN_EXTEND);
1547 case Instruction::Trunc:
1548 return selectCast(I, ISD::TRUNCATE);
1549 case Instruction::SIToFP:
1550 return selectCast(I, ISD::SINT_TO_FP);
1552 case Instruction::IntToPtr: // Deliberate fall-through.
1553 case Instruction::PtrToInt: {
1554 EVT SrcVT = TLI.getValueType(I->getOperand(0)->getType());
1555 EVT DstVT = TLI.getValueType(I->getType());
1556 if (DstVT.bitsGT(SrcVT))
1557 return selectCast(I, ISD::ZERO_EXTEND);
1558 if (DstVT.bitsLT(SrcVT))
1559 return selectCast(I, ISD::TRUNCATE);
1560 unsigned Reg = getRegForValue(I->getOperand(0));
1563 updateValueMap(I, Reg);
1567 case Instruction::ExtractValue:
1568 return selectExtractValue(I);
1570 case Instruction::PHI:
1571 llvm_unreachable("FastISel shouldn't visit PHI nodes!");
1574 // Unhandled instruction. Halt "fast" selection and bail.
1579 FastISel::FastISel(FunctionLoweringInfo &FuncInfo,
1580 const TargetLibraryInfo *LibInfo,
1581 bool SkipTargetIndependentISel)
1582 : FuncInfo(FuncInfo), MF(FuncInfo.MF), MRI(FuncInfo.MF->getRegInfo()),
1583 MFI(*FuncInfo.MF->getFrameInfo()), MCP(*FuncInfo.MF->getConstantPool()),
1584 TM(FuncInfo.MF->getTarget()), DL(*TM.getDataLayout()),
1585 TII(*MF->getSubtarget().getInstrInfo()),
1586 TLI(*MF->getSubtarget().getTargetLowering()),
1587 TRI(*MF->getSubtarget().getRegisterInfo()), LibInfo(LibInfo),
1588 SkipTargetIndependentISel(SkipTargetIndependentISel) {}
1590 FastISel::~FastISel() {}
1592 bool FastISel::fastLowerArguments() { return false; }
1594 bool FastISel::fastLowerCall(CallLoweringInfo & /*CLI*/) { return false; }
1596 bool FastISel::fastLowerIntrinsicCall(const IntrinsicInst * /*II*/) {
1600 unsigned FastISel::fastEmit_(MVT, MVT, unsigned) { return 0; }
1602 unsigned FastISel::fastEmit_r(MVT, MVT, unsigned, unsigned /*Op0*/,
1603 bool /*Op0IsKill*/) {
1607 unsigned FastISel::fastEmit_rr(MVT, MVT, unsigned, unsigned /*Op0*/,
1608 bool /*Op0IsKill*/, unsigned /*Op1*/,
1609 bool /*Op1IsKill*/) {
1613 unsigned FastISel::fastEmit_i(MVT, MVT, unsigned, uint64_t /*Imm*/) {
1617 unsigned FastISel::fastEmit_f(MVT, MVT, unsigned,
1618 const ConstantFP * /*FPImm*/) {
1622 unsigned FastISel::fastEmit_ri(MVT, MVT, unsigned, unsigned /*Op0*/,
1623 bool /*Op0IsKill*/, uint64_t /*Imm*/) {
1627 unsigned FastISel::fastEmit_rf(MVT, MVT, unsigned, unsigned /*Op0*/,
1629 const ConstantFP * /*FPImm*/) {
1633 unsigned FastISel::fastEmit_rri(MVT, MVT, unsigned, unsigned /*Op0*/,
1634 bool /*Op0IsKill*/, unsigned /*Op1*/,
1635 bool /*Op1IsKill*/, uint64_t /*Imm*/) {
1639 /// This method is a wrapper of fastEmit_ri. It first tries to emit an
1640 /// instruction with an immediate operand using fastEmit_ri.
1641 /// If that fails, it materializes the immediate into a register and try
1642 /// fastEmit_rr instead.
1643 unsigned FastISel::fastEmit_ri_(MVT VT, unsigned Opcode, unsigned Op0,
1644 bool Op0IsKill, uint64_t Imm, MVT ImmType) {
1645 // If this is a multiply by a power of two, emit this as a shift left.
1646 if (Opcode == ISD::MUL && isPowerOf2_64(Imm)) {
1649 } else if (Opcode == ISD::UDIV && isPowerOf2_64(Imm)) {
1650 // div x, 8 -> srl x, 3
1655 // Horrible hack (to be removed), check to make sure shift amounts are
1657 if ((Opcode == ISD::SHL || Opcode == ISD::SRA || Opcode == ISD::SRL) &&
1658 Imm >= VT.getSizeInBits())
1661 // First check if immediate type is legal. If not, we can't use the ri form.
1662 unsigned ResultReg = fastEmit_ri(VT, VT, Opcode, Op0, Op0IsKill, Imm);
1665 unsigned MaterialReg = fastEmit_i(ImmType, ImmType, ISD::Constant, Imm);
1667 // This is a bit ugly/slow, but failing here means falling out of
1668 // fast-isel, which would be very slow.
1670 IntegerType::get(FuncInfo.Fn->getContext(), VT.getSizeInBits());
1671 MaterialReg = getRegForValue(ConstantInt::get(ITy, Imm));
1675 return fastEmit_rr(VT, VT, Opcode, Op0, Op0IsKill, MaterialReg,
1679 unsigned FastISel::createResultReg(const TargetRegisterClass *RC) {
1680 return MRI.createVirtualRegister(RC);
1683 unsigned FastISel::constrainOperandRegClass(const MCInstrDesc &II, unsigned Op,
1685 if (TargetRegisterInfo::isVirtualRegister(Op)) {
1686 const TargetRegisterClass *RegClass =
1687 TII.getRegClass(II, OpNum, &TRI, *FuncInfo.MF);
1688 if (!MRI.constrainRegClass(Op, RegClass)) {
1689 // If it's not legal to COPY between the register classes, something
1690 // has gone very wrong before we got here.
1691 unsigned NewOp = createResultReg(RegClass);
1692 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1693 TII.get(TargetOpcode::COPY), NewOp).addReg(Op);
1700 unsigned FastISel::fastEmitInst_(unsigned MachineInstOpcode,
1701 const TargetRegisterClass *RC) {
1702 unsigned ResultReg = createResultReg(RC);
1703 const MCInstrDesc &II = TII.get(MachineInstOpcode);
1705 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg);
1709 unsigned FastISel::fastEmitInst_r(unsigned MachineInstOpcode,
1710 const TargetRegisterClass *RC, unsigned Op0,
1712 const MCInstrDesc &II = TII.get(MachineInstOpcode);
1714 unsigned ResultReg = createResultReg(RC);
1715 Op0 = constrainOperandRegClass(II, Op0, II.getNumDefs());
1717 if (II.getNumDefs() >= 1)
1718 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg)
1719 .addReg(Op0, getKillRegState(Op0IsKill));
1721 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II)
1722 .addReg(Op0, getKillRegState(Op0IsKill));
1723 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1724 TII.get(TargetOpcode::COPY), ResultReg).addReg(II.ImplicitDefs[0]);
1730 unsigned FastISel::fastEmitInst_rr(unsigned MachineInstOpcode,
1731 const TargetRegisterClass *RC, unsigned Op0,
1732 bool Op0IsKill, unsigned Op1,
1734 const MCInstrDesc &II = TII.get(MachineInstOpcode);
1736 unsigned ResultReg = createResultReg(RC);
1737 Op0 = constrainOperandRegClass(II, Op0, II.getNumDefs());
1738 Op1 = constrainOperandRegClass(II, Op1, II.getNumDefs() + 1);
1740 if (II.getNumDefs() >= 1)
1741 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg)
1742 .addReg(Op0, getKillRegState(Op0IsKill))
1743 .addReg(Op1, getKillRegState(Op1IsKill));
1745 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II)
1746 .addReg(Op0, getKillRegState(Op0IsKill))
1747 .addReg(Op1, getKillRegState(Op1IsKill));
1748 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1749 TII.get(TargetOpcode::COPY), ResultReg).addReg(II.ImplicitDefs[0]);
1754 unsigned FastISel::fastEmitInst_rrr(unsigned MachineInstOpcode,
1755 const TargetRegisterClass *RC, unsigned Op0,
1756 bool Op0IsKill, unsigned Op1,
1757 bool Op1IsKill, unsigned Op2,
1759 const MCInstrDesc &II = TII.get(MachineInstOpcode);
1761 unsigned ResultReg = createResultReg(RC);
1762 Op0 = constrainOperandRegClass(II, Op0, II.getNumDefs());
1763 Op1 = constrainOperandRegClass(II, Op1, II.getNumDefs() + 1);
1764 Op2 = constrainOperandRegClass(II, Op2, II.getNumDefs() + 2);
1766 if (II.getNumDefs() >= 1)
1767 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg)
1768 .addReg(Op0, getKillRegState(Op0IsKill))
1769 .addReg(Op1, getKillRegState(Op1IsKill))
1770 .addReg(Op2, getKillRegState(Op2IsKill));
1772 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II)
1773 .addReg(Op0, getKillRegState(Op0IsKill))
1774 .addReg(Op1, getKillRegState(Op1IsKill))
1775 .addReg(Op2, getKillRegState(Op2IsKill));
1776 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1777 TII.get(TargetOpcode::COPY), ResultReg).addReg(II.ImplicitDefs[0]);
1782 unsigned FastISel::fastEmitInst_ri(unsigned MachineInstOpcode,
1783 const TargetRegisterClass *RC, unsigned Op0,
1784 bool Op0IsKill, uint64_t Imm) {
1785 const MCInstrDesc &II = TII.get(MachineInstOpcode);
1787 unsigned ResultReg = createResultReg(RC);
1788 Op0 = constrainOperandRegClass(II, Op0, II.getNumDefs());
1790 if (II.getNumDefs() >= 1)
1791 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg)
1792 .addReg(Op0, getKillRegState(Op0IsKill))
1795 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II)
1796 .addReg(Op0, getKillRegState(Op0IsKill))
1798 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1799 TII.get(TargetOpcode::COPY), ResultReg).addReg(II.ImplicitDefs[0]);
1804 unsigned FastISel::fastEmitInst_rii(unsigned MachineInstOpcode,
1805 const TargetRegisterClass *RC, unsigned Op0,
1806 bool Op0IsKill, uint64_t Imm1,
1808 const MCInstrDesc &II = TII.get(MachineInstOpcode);
1810 unsigned ResultReg = createResultReg(RC);
1811 Op0 = constrainOperandRegClass(II, Op0, II.getNumDefs());
1813 if (II.getNumDefs() >= 1)
1814 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg)
1815 .addReg(Op0, getKillRegState(Op0IsKill))
1819 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II)
1820 .addReg(Op0, getKillRegState(Op0IsKill))
1823 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1824 TII.get(TargetOpcode::COPY), ResultReg).addReg(II.ImplicitDefs[0]);
1829 unsigned FastISel::fastEmitInst_rf(unsigned MachineInstOpcode,
1830 const TargetRegisterClass *RC, unsigned Op0,
1831 bool Op0IsKill, const ConstantFP *FPImm) {
1832 const MCInstrDesc &II = TII.get(MachineInstOpcode);
1834 unsigned ResultReg = createResultReg(RC);
1835 Op0 = constrainOperandRegClass(II, Op0, II.getNumDefs());
1837 if (II.getNumDefs() >= 1)
1838 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg)
1839 .addReg(Op0, getKillRegState(Op0IsKill))
1842 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II)
1843 .addReg(Op0, getKillRegState(Op0IsKill))
1845 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1846 TII.get(TargetOpcode::COPY), ResultReg).addReg(II.ImplicitDefs[0]);
1851 unsigned FastISel::fastEmitInst_rri(unsigned MachineInstOpcode,
1852 const TargetRegisterClass *RC, unsigned Op0,
1853 bool Op0IsKill, unsigned Op1,
1854 bool Op1IsKill, uint64_t Imm) {
1855 const MCInstrDesc &II = TII.get(MachineInstOpcode);
1857 unsigned ResultReg = createResultReg(RC);
1858 Op0 = constrainOperandRegClass(II, Op0, II.getNumDefs());
1859 Op1 = constrainOperandRegClass(II, Op1, II.getNumDefs() + 1);
1861 if (II.getNumDefs() >= 1)
1862 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg)
1863 .addReg(Op0, getKillRegState(Op0IsKill))
1864 .addReg(Op1, getKillRegState(Op1IsKill))
1867 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II)
1868 .addReg(Op0, getKillRegState(Op0IsKill))
1869 .addReg(Op1, getKillRegState(Op1IsKill))
1871 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1872 TII.get(TargetOpcode::COPY), ResultReg).addReg(II.ImplicitDefs[0]);
1877 unsigned FastISel::fastEmitInst_rrii(unsigned MachineInstOpcode,
1878 const TargetRegisterClass *RC,
1879 unsigned Op0, bool Op0IsKill, unsigned Op1,
1880 bool Op1IsKill, uint64_t Imm1,
1882 const MCInstrDesc &II = TII.get(MachineInstOpcode);
1884 unsigned ResultReg = createResultReg(RC);
1885 Op0 = constrainOperandRegClass(II, Op0, II.getNumDefs());
1886 Op1 = constrainOperandRegClass(II, Op1, II.getNumDefs() + 1);
1888 if (II.getNumDefs() >= 1)
1889 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg)
1890 .addReg(Op0, getKillRegState(Op0IsKill))
1891 .addReg(Op1, getKillRegState(Op1IsKill))
1895 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II)
1896 .addReg(Op0, getKillRegState(Op0IsKill))
1897 .addReg(Op1, getKillRegState(Op1IsKill))
1900 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1901 TII.get(TargetOpcode::COPY), ResultReg).addReg(II.ImplicitDefs[0]);
1906 unsigned FastISel::fastEmitInst_i(unsigned MachineInstOpcode,
1907 const TargetRegisterClass *RC, uint64_t Imm) {
1908 unsigned ResultReg = createResultReg(RC);
1909 const MCInstrDesc &II = TII.get(MachineInstOpcode);
1911 if (II.getNumDefs() >= 1)
1912 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg)
1915 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II).addImm(Imm);
1916 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1917 TII.get(TargetOpcode::COPY), ResultReg).addReg(II.ImplicitDefs[0]);
1922 unsigned FastISel::fastEmitInst_ii(unsigned MachineInstOpcode,
1923 const TargetRegisterClass *RC, uint64_t Imm1,
1925 unsigned ResultReg = createResultReg(RC);
1926 const MCInstrDesc &II = TII.get(MachineInstOpcode);
1928 if (II.getNumDefs() >= 1)
1929 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg)
1933 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II).addImm(Imm1)
1935 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1936 TII.get(TargetOpcode::COPY), ResultReg).addReg(II.ImplicitDefs[0]);
1941 unsigned FastISel::fastEmitInst_extractsubreg(MVT RetVT, unsigned Op0,
1942 bool Op0IsKill, uint32_t Idx) {
1943 unsigned ResultReg = createResultReg(TLI.getRegClassFor(RetVT));
1944 assert(TargetRegisterInfo::isVirtualRegister(Op0) &&
1945 "Cannot yet extract from physregs");
1946 const TargetRegisterClass *RC = MRI.getRegClass(Op0);
1947 MRI.constrainRegClass(Op0, TRI.getSubClassWithSubReg(RC, Idx));
1948 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(TargetOpcode::COPY),
1949 ResultReg).addReg(Op0, getKillRegState(Op0IsKill), Idx);
1953 /// Emit MachineInstrs to compute the value of Op with all but the least
1954 /// significant bit set to zero.
1955 unsigned FastISel::fastEmitZExtFromI1(MVT VT, unsigned Op0, bool Op0IsKill) {
1956 return fastEmit_ri(VT, VT, ISD::AND, Op0, Op0IsKill, 1);
1959 /// HandlePHINodesInSuccessorBlocks - Handle PHI nodes in successor blocks.
1960 /// Emit code to ensure constants are copied into registers when needed.
1961 /// Remember the virtual registers that need to be added to the Machine PHI
1962 /// nodes as input. We cannot just directly add them, because expansion
1963 /// might result in multiple MBB's for one BB. As such, the start of the
1964 /// BB might correspond to a different MBB than the end.
1965 bool FastISel::handlePHINodesInSuccessorBlocks(const BasicBlock *LLVMBB) {
1966 const TerminatorInst *TI = LLVMBB->getTerminator();
1968 SmallPtrSet<MachineBasicBlock *, 4> SuccsHandled;
1969 FuncInfo.OrigNumPHINodesToUpdate = FuncInfo.PHINodesToUpdate.size();
1971 // Check successor nodes' PHI nodes that expect a constant to be available
1973 for (unsigned succ = 0, e = TI->getNumSuccessors(); succ != e; ++succ) {
1974 const BasicBlock *SuccBB = TI->getSuccessor(succ);
1975 if (!isa<PHINode>(SuccBB->begin()))
1977 MachineBasicBlock *SuccMBB = FuncInfo.MBBMap[SuccBB];
1979 // If this terminator has multiple identical successors (common for
1980 // switches), only handle each succ once.
1981 if (!SuccsHandled.insert(SuccMBB).second)
1984 MachineBasicBlock::iterator MBBI = SuccMBB->begin();
1986 // At this point we know that there is a 1-1 correspondence between LLVM PHI
1987 // nodes and Machine PHI nodes, but the incoming operands have not been
1989 for (BasicBlock::const_iterator I = SuccBB->begin();
1990 const auto *PN = dyn_cast<PHINode>(I); ++I) {
1992 // Ignore dead phi's.
1993 if (PN->use_empty())
1996 // Only handle legal types. Two interesting things to note here. First,
1997 // by bailing out early, we may leave behind some dead instructions,
1998 // since SelectionDAG's HandlePHINodesInSuccessorBlocks will insert its
1999 // own moves. Second, this check is necessary because FastISel doesn't
2000 // use CreateRegs to create registers, so it always creates
2001 // exactly one register for each non-void instruction.
2002 EVT VT = TLI.getValueType(PN->getType(), /*AllowUnknown=*/true);
2003 if (VT == MVT::Other || !TLI.isTypeLegal(VT)) {
2004 // Handle integer promotions, though, because they're common and easy.
2005 if (!(VT == MVT::i1 || VT == MVT::i8 || VT == MVT::i16)) {
2006 FuncInfo.PHINodesToUpdate.resize(FuncInfo.OrigNumPHINodesToUpdate);
2011 const Value *PHIOp = PN->getIncomingValueForBlock(LLVMBB);
2013 // Set the DebugLoc for the copy. Prefer the location of the operand
2014 // if there is one; use the location of the PHI otherwise.
2015 DbgLoc = PN->getDebugLoc();
2016 if (const auto *Inst = dyn_cast<Instruction>(PHIOp))
2017 DbgLoc = Inst->getDebugLoc();
2019 unsigned Reg = getRegForValue(PHIOp);
2021 FuncInfo.PHINodesToUpdate.resize(FuncInfo.OrigNumPHINodesToUpdate);
2024 FuncInfo.PHINodesToUpdate.push_back(std::make_pair(MBBI++, Reg));
2025 DbgLoc = DebugLoc();
2032 bool FastISel::tryToFoldLoad(const LoadInst *LI, const Instruction *FoldInst) {
2033 assert(LI->hasOneUse() &&
2034 "tryToFoldLoad expected a LoadInst with a single use");
2035 // We know that the load has a single use, but don't know what it is. If it
2036 // isn't one of the folded instructions, then we can't succeed here. Handle
2037 // this by scanning the single-use users of the load until we get to FoldInst.
2038 unsigned MaxUsers = 6; // Don't scan down huge single-use chains of instrs.
2040 const Instruction *TheUser = LI->user_back();
2041 while (TheUser != FoldInst && // Scan up until we find FoldInst.
2042 // Stay in the right block.
2043 TheUser->getParent() == FoldInst->getParent() &&
2044 --MaxUsers) { // Don't scan too far.
2045 // If there are multiple or no uses of this instruction, then bail out.
2046 if (!TheUser->hasOneUse())
2049 TheUser = TheUser->user_back();
2052 // If we didn't find the fold instruction, then we failed to collapse the
2054 if (TheUser != FoldInst)
2057 // Don't try to fold volatile loads. Target has to deal with alignment
2059 if (LI->isVolatile())
2062 // Figure out which vreg this is going into. If there is no assigned vreg yet
2063 // then there actually was no reference to it. Perhaps the load is referenced
2064 // by a dead instruction.
2065 unsigned LoadReg = getRegForValue(LI);
2069 // We can't fold if this vreg has no uses or more than one use. Multiple uses
2070 // may mean that the instruction got lowered to multiple MIs, or the use of
2071 // the loaded value ended up being multiple operands of the result.
2072 if (!MRI.hasOneUse(LoadReg))
2075 MachineRegisterInfo::reg_iterator RI = MRI.reg_begin(LoadReg);
2076 MachineInstr *User = RI->getParent();
2078 // Set the insertion point properly. Folding the load can cause generation of
2079 // other random instructions (like sign extends) for addressing modes; make
2080 // sure they get inserted in a logical place before the new instruction.
2081 FuncInfo.InsertPt = User;
2082 FuncInfo.MBB = User->getParent();
2084 // Ask the target to try folding the load.
2085 return tryToFoldLoadIntoMI(User, RI.getOperandNo(), LI);
2088 bool FastISel::canFoldAddIntoGEP(const User *GEP, const Value *Add) {
2090 if (!isa<AddOperator>(Add))
2092 // Type size needs to match.
2093 if (DL.getTypeSizeInBits(GEP->getType()) !=
2094 DL.getTypeSizeInBits(Add->getType()))
2096 // Must be in the same basic block.
2097 if (isa<Instruction>(Add) &&
2098 FuncInfo.MBBMap[cast<Instruction>(Add)->getParent()] != FuncInfo.MBB)
2100 // Must have a constant operand.
2101 return isa<ConstantInt>(cast<AddOperator>(Add)->getOperand(1));
2105 FastISel::createMachineMemOperandFor(const Instruction *I) const {
2112 if (const auto *LI = dyn_cast<LoadInst>(I)) {
2113 Alignment = LI->getAlignment();
2114 IsVolatile = LI->isVolatile();
2115 Flags = MachineMemOperand::MOLoad;
2116 Ptr = LI->getPointerOperand();
2117 ValTy = LI->getType();
2118 } else if (const auto *SI = dyn_cast<StoreInst>(I)) {
2119 Alignment = SI->getAlignment();
2120 IsVolatile = SI->isVolatile();
2121 Flags = MachineMemOperand::MOStore;
2122 Ptr = SI->getPointerOperand();
2123 ValTy = SI->getValueOperand()->getType();
2127 bool IsNonTemporal = I->getMetadata(LLVMContext::MD_nontemporal) != nullptr;
2128 bool IsInvariant = I->getMetadata(LLVMContext::MD_invariant_load) != nullptr;
2129 const MDNode *Ranges = I->getMetadata(LLVMContext::MD_range);
2132 I->getAAMetadata(AAInfo);
2134 if (Alignment == 0) // Ensure that codegen never sees alignment 0.
2135 Alignment = DL.getABITypeAlignment(ValTy);
2137 unsigned Size = DL.getTypeStoreSize(ValTy);
2140 Flags |= MachineMemOperand::MOVolatile;
2142 Flags |= MachineMemOperand::MONonTemporal;
2144 Flags |= MachineMemOperand::MOInvariant;
2146 return FuncInfo.MF->getMachineMemOperand(MachinePointerInfo(Ptr), Flags, Size,
2147 Alignment, AAInfo, Ranges);
2150 CmpInst::Predicate FastISel::optimizeCmpPredicate(const CmpInst *CI) const {
2151 // If both operands are the same, then try to optimize or fold the cmp.
2152 CmpInst::Predicate Predicate = CI->getPredicate();
2153 if (CI->getOperand(0) != CI->getOperand(1))
2156 switch (Predicate) {
2157 default: llvm_unreachable("Invalid predicate!");
2158 case CmpInst::FCMP_FALSE: Predicate = CmpInst::FCMP_FALSE; break;
2159 case CmpInst::FCMP_OEQ: Predicate = CmpInst::FCMP_ORD; break;
2160 case CmpInst::FCMP_OGT: Predicate = CmpInst::FCMP_FALSE; break;
2161 case CmpInst::FCMP_OGE: Predicate = CmpInst::FCMP_ORD; break;
2162 case CmpInst::FCMP_OLT: Predicate = CmpInst::FCMP_FALSE; break;
2163 case CmpInst::FCMP_OLE: Predicate = CmpInst::FCMP_ORD; break;
2164 case CmpInst::FCMP_ONE: Predicate = CmpInst::FCMP_FALSE; break;
2165 case CmpInst::FCMP_ORD: Predicate = CmpInst::FCMP_ORD; break;
2166 case CmpInst::FCMP_UNO: Predicate = CmpInst::FCMP_UNO; break;
2167 case CmpInst::FCMP_UEQ: Predicate = CmpInst::FCMP_TRUE; break;
2168 case CmpInst::FCMP_UGT: Predicate = CmpInst::FCMP_UNO; break;
2169 case CmpInst::FCMP_UGE: Predicate = CmpInst::FCMP_TRUE; break;
2170 case CmpInst::FCMP_ULT: Predicate = CmpInst::FCMP_UNO; break;
2171 case CmpInst::FCMP_ULE: Predicate = CmpInst::FCMP_TRUE; break;
2172 case CmpInst::FCMP_UNE: Predicate = CmpInst::FCMP_UNO; break;
2173 case CmpInst::FCMP_TRUE: Predicate = CmpInst::FCMP_TRUE; break;
2175 case CmpInst::ICMP_EQ: Predicate = CmpInst::FCMP_TRUE; break;
2176 case CmpInst::ICMP_NE: Predicate = CmpInst::FCMP_FALSE; break;
2177 case CmpInst::ICMP_UGT: Predicate = CmpInst::FCMP_FALSE; break;
2178 case CmpInst::ICMP_UGE: Predicate = CmpInst::FCMP_TRUE; break;
2179 case CmpInst::ICMP_ULT: Predicate = CmpInst::FCMP_FALSE; break;
2180 case CmpInst::ICMP_ULE: Predicate = CmpInst::FCMP_TRUE; break;
2181 case CmpInst::ICMP_SGT: Predicate = CmpInst::FCMP_FALSE; break;
2182 case CmpInst::ICMP_SGE: Predicate = CmpInst::FCMP_TRUE; break;
2183 case CmpInst::ICMP_SLT: Predicate = CmpInst::FCMP_FALSE; break;
2184 case CmpInst::ICMP_SLE: Predicate = CmpInst::FCMP_TRUE; break;