1 ///===-- FastISel.cpp - Implementation of the FastISel class --------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the implementation of the FastISel class.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/Instructions.h"
15 #include "llvm/CodeGen/FastISel.h"
16 #include "llvm/CodeGen/MachineInstrBuilder.h"
17 #include "llvm/CodeGen/MachineRegisterInfo.h"
18 #include "llvm/Target/TargetData.h"
19 #include "llvm/Target/TargetInstrInfo.h"
20 #include "llvm/Target/TargetLowering.h"
21 #include "llvm/Target/TargetMachine.h"
24 /// SelectBinaryOp - Select and emit code for a binary operator instruction,
25 /// which has an opcode which directly corresponds to the given ISD opcode.
27 bool FastISel::SelectBinaryOp(Instruction *I, ISD::NodeType ISDOpcode,
28 DenseMap<const Value*, unsigned> &ValueMap) {
29 unsigned Op0 = ValueMap[I->getOperand(0)];
30 unsigned Op1 = ValueMap[I->getOperand(1)];
31 if (Op0 == 0 || Op1 == 0)
32 // Unhandled operand. Halt "fast" selection and bail.
35 MVT VT = MVT::getMVT(I->getType(), /*HandleUnknown=*/true);
36 if (VT == MVT::Other || !VT.isSimple())
37 // Unhandled type. Halt "fast" selection and bail.
40 unsigned ResultReg = FastEmit_rr(VT.getSimpleVT(), ISDOpcode, Op0, Op1);
42 // Target-specific code wasn't able to find a machine opcode for
43 // the given ISD opcode and type. Halt "fast" selection and bail.
46 // We successfully emitted code for the given LLVM Instruction.
47 ValueMap[I] = ResultReg;
51 bool FastISel::SelectGetElementPtr(Instruction *I,
52 DenseMap<const Value*, unsigned> &ValueMap) {
53 unsigned N = ValueMap[I->getOperand(0)];
55 // Unhandled operand. Halt "fast" selection and bail.
58 const Type *Ty = I->getOperand(0)->getType();
59 MVT VT = MVT::getMVT(Ty, /*HandleUnknown=*/true);
60 MVT::SimpleValueType PtrVT = TLI.getPointerTy().getSimpleVT();
62 for (GetElementPtrInst::op_iterator OI = I->op_begin()+1, E = I->op_end();
65 if (const StructType *StTy = dyn_cast<StructType>(Ty)) {
66 unsigned Field = cast<ConstantInt>(Idx)->getZExtValue();
69 uint64_t Offs = TD.getStructLayout(StTy)->getElementOffset(Field);
70 // FIXME: This can be optimized by combining the add with a
72 N = FastEmit_ri(VT.getSimpleVT(), ISD::ADD, N, Offs, PtrVT);
74 // Unhandled operand. Halt "fast" selection and bail.
77 Ty = StTy->getElementType(Field);
79 Ty = cast<SequentialType>(Ty)->getElementType();
81 // If this is a constant subscript, handle it quickly.
82 if (ConstantInt *CI = dyn_cast<ConstantInt>(Idx)) {
83 if (CI->getZExtValue() == 0) continue;
85 TD.getABITypeSize(Ty)*cast<ConstantInt>(CI)->getSExtValue();
86 N = FastEmit_ri(VT.getSimpleVT(), ISD::ADD, N, Offs, PtrVT);
88 // Unhandled operand. Halt "fast" selection and bail.
93 // N = N + Idx * ElementSize;
94 uint64_t ElementSize = TD.getABITypeSize(Ty);
95 unsigned IdxN = ValueMap[Idx];
97 // Unhandled operand. Halt "fast" selection and bail.
100 // If the index is smaller or larger than intptr_t, truncate or extend
102 MVT IdxVT = MVT::getMVT(Idx->getType(), /*HandleUnknown=*/true);
103 if (IdxVT.bitsLT(VT))
104 IdxN = FastEmit_r(VT.getSimpleVT(), ISD::SIGN_EXTEND, IdxN);
105 else if (IdxVT.bitsGT(VT))
106 IdxN = FastEmit_r(VT.getSimpleVT(), ISD::TRUNCATE, IdxN);
108 // Unhandled operand. Halt "fast" selection and bail.
111 // FIXME: If multiple is power of two, turn it into a shift. The
112 // optimization should be in FastEmit_ri?
113 IdxN = FastEmit_ri(VT.getSimpleVT(), ISD::MUL, IdxN,
116 // Unhandled operand. Halt "fast" selection and bail.
118 N = FastEmit_rr(VT.getSimpleVT(), ISD::ADD, N, IdxN);
120 // Unhandled operand. Halt "fast" selection and bail.
125 // We successfully emitted code for the given LLVM Instruction.
131 FastISel::SelectInstructions(BasicBlock::iterator Begin,
132 BasicBlock::iterator End,
133 DenseMap<const Value*, unsigned> &ValueMap,
134 MachineBasicBlock *mbb) {
136 BasicBlock::iterator I = Begin;
138 for (; I != End; ++I) {
139 switch (I->getOpcode()) {
140 case Instruction::Add: {
141 ISD::NodeType Opc = I->getType()->isFPOrFPVector() ? ISD::FADD : ISD::ADD;
142 if (!SelectBinaryOp(I, Opc, ValueMap)) return I; break;
144 case Instruction::Sub: {
145 ISD::NodeType Opc = I->getType()->isFPOrFPVector() ? ISD::FSUB : ISD::SUB;
146 if (!SelectBinaryOp(I, Opc, ValueMap)) return I; break;
148 case Instruction::Mul: {
149 ISD::NodeType Opc = I->getType()->isFPOrFPVector() ? ISD::FMUL : ISD::MUL;
150 if (!SelectBinaryOp(I, Opc, ValueMap)) return I; break;
152 case Instruction::SDiv:
153 if (!SelectBinaryOp(I, ISD::SDIV, ValueMap)) return I; break;
154 case Instruction::UDiv:
155 if (!SelectBinaryOp(I, ISD::UDIV, ValueMap)) return I; break;
156 case Instruction::FDiv:
157 if (!SelectBinaryOp(I, ISD::FDIV, ValueMap)) return I; break;
158 case Instruction::SRem:
159 if (!SelectBinaryOp(I, ISD::SREM, ValueMap)) return I; break;
160 case Instruction::URem:
161 if (!SelectBinaryOp(I, ISD::UREM, ValueMap)) return I; break;
162 case Instruction::FRem:
163 if (!SelectBinaryOp(I, ISD::FREM, ValueMap)) return I; break;
164 case Instruction::Shl:
165 if (!SelectBinaryOp(I, ISD::SHL, ValueMap)) return I; break;
166 case Instruction::LShr:
167 if (!SelectBinaryOp(I, ISD::SRL, ValueMap)) return I; break;
168 case Instruction::AShr:
169 if (!SelectBinaryOp(I, ISD::SRA, ValueMap)) return I; break;
170 case Instruction::And:
171 if (!SelectBinaryOp(I, ISD::AND, ValueMap)) return I; break;
172 case Instruction::Or:
173 if (!SelectBinaryOp(I, ISD::OR, ValueMap)) return I; break;
174 case Instruction::Xor:
175 if (!SelectBinaryOp(I, ISD::XOR, ValueMap)) return I; break;
177 case Instruction::GetElementPtr:
178 if (!SelectGetElementPtr(I, ValueMap)) return I;
181 case Instruction::Br: {
182 BranchInst *BI = cast<BranchInst>(I);
184 // For now, check for and handle just the most trivial case: an
185 // unconditional fall-through branch.
186 if (BI->isUnconditional()) {
187 MachineFunction::iterator NextMBB =
188 next(MachineFunction::iterator(MBB));
189 if (NextMBB != MF.end() &&
190 NextMBB->getBasicBlock() == BI->getSuccessor(0)) {
191 MBB->addSuccessor(NextMBB);
196 // Something more complicated. Halt "fast" selection and bail.
200 // Unhandled instruction. Halt "fast" selection and bail.
208 FastISel::FastISel(MachineFunction &mf)
209 : MF(mf), MRI(mf.getRegInfo()),
210 TD(*mf.getTarget().getTargetData()),
211 TII(*mf.getTarget().getInstrInfo()),
212 TLI(*mf.getTarget().getTargetLowering()) {
215 FastISel::~FastISel() {}
217 unsigned FastISel::FastEmit_(MVT::SimpleValueType, ISD::NodeType) {
221 unsigned FastISel::FastEmit_r(MVT::SimpleValueType, ISD::NodeType,
226 unsigned FastISel::FastEmit_rr(MVT::SimpleValueType, ISD::NodeType,
227 unsigned /*Op0*/, unsigned /*Op0*/) {
231 unsigned FastISel::FastEmit_i(MVT::SimpleValueType, uint64_t) {
235 unsigned FastISel::FastEmit_ri(MVT::SimpleValueType, ISD::NodeType,
236 unsigned /*Op0*/, uint64_t Imm,
237 MVT::SimpleValueType ImmType) {
241 /// FastEmit_ri_ - This method is a wrapper of FastEmit_ri. It first tries
242 /// to emit an instruction with an immediate operand using FastEmit_ri.
243 /// If that fails, it materializes the immediate into a register and try
244 /// FastEmit_rr instead.
245 unsigned FastISel::FastEmit_ri_(MVT::SimpleValueType VT, ISD::NodeType Opcode,
246 unsigned Op0, uint64_t Imm,
247 MVT::SimpleValueType ImmType) {
248 unsigned ResultReg = 0;
249 // First check if immediate type is legal. If not, we can't use the ri form.
250 if (TLI.getOperationAction(ISD::Constant, ImmType) == TargetLowering::Legal)
251 ResultReg = FastEmit_ri(VT, Opcode, Op0, Imm, ImmType);
254 return FastEmit_rr(VT, Opcode, Op0, FastEmit_i(ImmType, Imm));
257 unsigned FastISel::FastEmitInst_(unsigned MachineInstOpcode,
258 const TargetRegisterClass* RC) {
259 unsigned ResultReg = MRI.createVirtualRegister(RC);
260 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
262 MachineInstr *MI = BuildMI(MBB, II, ResultReg);
266 unsigned FastISel::FastEmitInst_r(unsigned MachineInstOpcode,
267 const TargetRegisterClass *RC,
269 unsigned ResultReg = MRI.createVirtualRegister(RC);
270 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
272 MachineInstr *MI = BuildMI(MBB, II, ResultReg).addReg(Op0);
276 unsigned FastISel::FastEmitInst_rr(unsigned MachineInstOpcode,
277 const TargetRegisterClass *RC,
278 unsigned Op0, unsigned Op1) {
279 unsigned ResultReg = MRI.createVirtualRegister(RC);
280 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
282 MachineInstr *MI = BuildMI(MBB, II, ResultReg).addReg(Op0).addReg(Op1);