1 //===-- FastISel.cpp - Implementation of the FastISel class ---------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the implementation of the FastISel class.
12 // "Fast" instruction selection is designed to emit very poor code quickly.
13 // Also, it is not designed to be able to do much lowering, so most illegal
14 // types (e.g. i64 on 32-bit targets) and operations are not supported. It is
15 // also not intended to be able to do much optimization, except in a few cases
16 // where doing optimizations reduces overall compile time. For example, folding
17 // constants into immediate fields is often done, because it's cheap and it
18 // reduces the number of instructions later phases have to examine.
20 // "Fast" instruction selection is able to fail gracefully and transfer
21 // control to the SelectionDAG selector for operations that it doesn't
22 // support. In many cases, this allows us to avoid duplicating a lot of
23 // the complicated lowering logic that SelectionDAG currently has.
25 // The intended use for "fast" instruction selection is "-O0" mode
26 // compilation, where the quality of the generated code is irrelevant when
27 // weighed against the speed at which the code can be generated. Also,
28 // at -O0, the LLVM optimizers are not running, and this makes the
29 // compile time of codegen a much higher portion of the overall compile
30 // time. Despite its limitations, "fast" instruction selection is able to
31 // handle enough code on its own to provide noticeable overall speedups
34 // Basic operations are supported in a target-independent way, by reading
35 // the same instruction descriptions that the SelectionDAG selector reads,
36 // and identifying simple arithmetic operations that can be directly selected
37 // from simple operators. More complicated operations currently require
38 // target-specific code.
40 //===----------------------------------------------------------------------===//
42 #include "llvm/Function.h"
43 #include "llvm/GlobalVariable.h"
44 #include "llvm/Instructions.h"
45 #include "llvm/IntrinsicInst.h"
46 #include "llvm/CodeGen/FastISel.h"
47 #include "llvm/CodeGen/FunctionLoweringInfo.h"
48 #include "llvm/CodeGen/MachineInstrBuilder.h"
49 #include "llvm/CodeGen/MachineModuleInfo.h"
50 #include "llvm/CodeGen/MachineRegisterInfo.h"
51 #include "llvm/Analysis/DebugInfo.h"
52 #include "llvm/Analysis/Loads.h"
53 #include "llvm/Target/TargetData.h"
54 #include "llvm/Target/TargetInstrInfo.h"
55 #include "llvm/Target/TargetLowering.h"
56 #include "llvm/Target/TargetMachine.h"
57 #include "llvm/Support/ErrorHandling.h"
60 /// startNewBlock - Set the current block to which generated machine
61 /// instructions will be appended, and clear the local CSE map.
63 void FastISel::startNewBlock() {
64 LocalValueMap.clear();
66 // Start out as null, meaining no local-value instructions have
70 // Advance the last local value past any EH_LABEL instructions.
71 MachineBasicBlock::iterator
72 I = FuncInfo.MBB->begin(), E = FuncInfo.MBB->end();
73 while (I != E && I->getOpcode() == TargetOpcode::EH_LABEL) {
79 bool FastISel::hasTrivialKill(const Value *V) const {
80 // Don't consider constants or arguments to have trivial kills.
81 const Instruction *I = dyn_cast<Instruction>(V);
85 // No-op casts are trivially coalesced by fast-isel.
86 if (const CastInst *Cast = dyn_cast<CastInst>(I))
87 if (Cast->isNoopCast(TD.getIntPtrType(Cast->getContext())) &&
88 !hasTrivialKill(Cast->getOperand(0)))
91 // Only instructions with a single use in the same basic block are considered
92 // to have trivial kills.
93 return I->hasOneUse() &&
94 !(I->getOpcode() == Instruction::BitCast ||
95 I->getOpcode() == Instruction::PtrToInt ||
96 I->getOpcode() == Instruction::IntToPtr) &&
97 cast<Instruction>(I->use_begin())->getParent() == I->getParent();
100 unsigned FastISel::getRegForValue(const Value *V) {
101 EVT RealVT = TLI.getValueType(V->getType(), /*AllowUnknown=*/true);
102 // Don't handle non-simple values in FastISel.
103 if (!RealVT.isSimple())
106 // Ignore illegal types. We must do this before looking up the value
107 // in ValueMap because Arguments are given virtual registers regardless
108 // of whether FastISel can handle them.
109 MVT VT = RealVT.getSimpleVT();
110 if (!TLI.isTypeLegal(VT)) {
111 // Promote MVT::i1 to a legal type though, because it's common and easy.
113 VT = TLI.getTypeToTransformTo(V->getContext(), VT).getSimpleVT();
118 // Look up the value to see if we already have a register for it. We
119 // cache values defined by Instructions across blocks, and other values
120 // only locally. This is because Instructions already have the SSA
121 // def-dominates-use requirement enforced.
122 DenseMap<const Value *, unsigned>::iterator I = FuncInfo.ValueMap.find(V);
123 if (I != FuncInfo.ValueMap.end()) {
124 unsigned Reg = I->second;
127 unsigned Reg = LocalValueMap[V];
131 // In bottom-up mode, just create the virtual register which will be used
132 // to hold the value. It will be materialized later.
133 if (isa<Instruction>(V) &&
134 (!isa<AllocaInst>(V) ||
135 !FuncInfo.StaticAllocaMap.count(cast<AllocaInst>(V))))
136 return FuncInfo.InitializeRegForValue(V);
138 MachineBasicBlock::iterator SaveInsertPt = enterLocalValueArea();
140 // Materialize the value in a register. Emit any instructions in the
142 Reg = materializeRegForValue(V, VT);
144 leaveLocalValueArea(SaveInsertPt);
149 /// materializeRegForValue - Helper for getRegForVale. This function is
150 /// called when the value isn't already available in a register and must
151 /// be materialized with new instructions.
152 unsigned FastISel::materializeRegForValue(const Value *V, MVT VT) {
155 if (const ConstantInt *CI = dyn_cast<ConstantInt>(V)) {
156 if (CI->getValue().getActiveBits() <= 64)
157 Reg = FastEmit_i(VT, VT, ISD::Constant, CI->getZExtValue());
158 } else if (isa<AllocaInst>(V)) {
159 Reg = TargetMaterializeAlloca(cast<AllocaInst>(V));
160 } else if (isa<ConstantPointerNull>(V)) {
161 // Translate this as an integer zero so that it can be
162 // local-CSE'd with actual integer zeros.
164 getRegForValue(Constant::getNullValue(TD.getIntPtrType(V->getContext())));
165 } else if (const ConstantFP *CF = dyn_cast<ConstantFP>(V)) {
166 // Try to emit the constant directly.
167 Reg = FastEmit_f(VT, VT, ISD::ConstantFP, CF);
170 // Try to emit the constant by using an integer constant with a cast.
171 const APFloat &Flt = CF->getValueAPF();
172 EVT IntVT = TLI.getPointerTy();
175 uint32_t IntBitWidth = IntVT.getSizeInBits();
177 (void) Flt.convertToInteger(x, IntBitWidth, /*isSigned=*/true,
178 APFloat::rmTowardZero, &isExact);
180 APInt IntVal(IntBitWidth, 2, x);
182 unsigned IntegerReg =
183 getRegForValue(ConstantInt::get(V->getContext(), IntVal));
185 Reg = FastEmit_r(IntVT.getSimpleVT(), VT, ISD::SINT_TO_FP,
186 IntegerReg, /*Kill=*/false);
189 } else if (const Operator *Op = dyn_cast<Operator>(V)) {
190 if (!SelectOperator(Op, Op->getOpcode()))
191 if (!isa<Instruction>(Op) ||
192 !TargetSelectInstruction(cast<Instruction>(Op)))
194 Reg = lookUpRegForValue(Op);
195 } else if (isa<UndefValue>(V)) {
196 Reg = createResultReg(TLI.getRegClassFor(VT));
197 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
198 TII.get(TargetOpcode::IMPLICIT_DEF), Reg);
201 // If target-independent code couldn't handle the value, give target-specific
203 if (!Reg && isa<Constant>(V))
204 Reg = TargetMaterializeConstant(cast<Constant>(V));
206 // Don't cache constant materializations in the general ValueMap.
207 // To do so would require tracking what uses they dominate.
209 LocalValueMap[V] = Reg;
210 LastLocalValue = MRI.getVRegDef(Reg);
215 unsigned FastISel::lookUpRegForValue(const Value *V) {
216 // Look up the value to see if we already have a register for it. We
217 // cache values defined by Instructions across blocks, and other values
218 // only locally. This is because Instructions already have the SSA
219 // def-dominates-use requirement enforced.
220 DenseMap<const Value *, unsigned>::iterator I = FuncInfo.ValueMap.find(V);
221 if (I != FuncInfo.ValueMap.end())
223 return LocalValueMap[V];
226 /// UpdateValueMap - Update the value map to include the new mapping for this
227 /// instruction, or insert an extra copy to get the result in a previous
228 /// determined register.
229 /// NOTE: This is only necessary because we might select a block that uses
230 /// a value before we select the block that defines the value. It might be
231 /// possible to fix this by selecting blocks in reverse postorder.
232 unsigned FastISel::UpdateValueMap(const Value *I, unsigned Reg) {
233 if (!isa<Instruction>(I)) {
234 LocalValueMap[I] = Reg;
238 unsigned &AssignedReg = FuncInfo.ValueMap[I];
239 if (AssignedReg == 0)
240 // Use the new register.
242 else if (Reg != AssignedReg) {
243 // Arrange for uses of AssignedReg to be replaced by uses of Reg.
244 FuncInfo.RegFixups[AssignedReg] = Reg;
252 std::pair<unsigned, bool> FastISel::getRegForGEPIndex(const Value *Idx) {
253 unsigned IdxN = getRegForValue(Idx);
255 // Unhandled operand. Halt "fast" selection and bail.
256 return std::pair<unsigned, bool>(0, false);
258 bool IdxNIsKill = hasTrivialKill(Idx);
260 // If the index is smaller or larger than intptr_t, truncate or extend it.
261 MVT PtrVT = TLI.getPointerTy();
262 EVT IdxVT = EVT::getEVT(Idx->getType(), /*HandleUnknown=*/false);
263 if (IdxVT.bitsLT(PtrVT)) {
264 IdxN = FastEmit_r(IdxVT.getSimpleVT(), PtrVT, ISD::SIGN_EXTEND,
268 else if (IdxVT.bitsGT(PtrVT)) {
269 IdxN = FastEmit_r(IdxVT.getSimpleVT(), PtrVT, ISD::TRUNCATE,
273 return std::pair<unsigned, bool>(IdxN, IdxNIsKill);
276 void FastISel::recomputeInsertPt() {
277 if (getLastLocalValue()) {
278 FuncInfo.InsertPt = getLastLocalValue();
281 FuncInfo.InsertPt = FuncInfo.MBB->getFirstNonPHI();
283 // Now skip past any EH_LABELs, which must remain at the beginning.
284 while (FuncInfo.InsertPt != FuncInfo.MBB->end() &&
285 FuncInfo.InsertPt->getOpcode() == TargetOpcode::EH_LABEL)
289 MachineBasicBlock::iterator FastISel::enterLocalValueArea() {
290 MachineBasicBlock::iterator OldInsertPt = FuncInfo.InsertPt;
295 void FastISel::leaveLocalValueArea(MachineBasicBlock::iterator OldInsertPt) {
296 if (FuncInfo.InsertPt != FuncInfo.MBB->begin())
297 LastLocalValue = llvm::prior(FuncInfo.InsertPt);
299 // Restore the previous insert position.
300 FuncInfo.InsertPt = OldInsertPt;
303 /// SelectBinaryOp - Select and emit code for a binary operator instruction,
304 /// which has an opcode which directly corresponds to the given ISD opcode.
306 bool FastISel::SelectBinaryOp(const User *I, unsigned ISDOpcode) {
307 EVT VT = EVT::getEVT(I->getType(), /*HandleUnknown=*/true);
308 if (VT == MVT::Other || !VT.isSimple())
309 // Unhandled type. Halt "fast" selection and bail.
312 // We only handle legal types. For example, on x86-32 the instruction
313 // selector contains all of the 64-bit instructions from x86-64,
314 // under the assumption that i64 won't be used if the target doesn't
316 if (!TLI.isTypeLegal(VT)) {
317 // MVT::i1 is special. Allow AND, OR, or XOR because they
318 // don't require additional zeroing, which makes them easy.
320 (ISDOpcode == ISD::AND || ISDOpcode == ISD::OR ||
321 ISDOpcode == ISD::XOR))
322 VT = TLI.getTypeToTransformTo(I->getContext(), VT);
327 unsigned Op0 = getRegForValue(I->getOperand(0));
329 // Unhandled operand. Halt "fast" selection and bail.
332 bool Op0IsKill = hasTrivialKill(I->getOperand(0));
334 // Check if the second operand is a constant and handle it appropriately.
335 if (ConstantInt *CI = dyn_cast<ConstantInt>(I->getOperand(1))) {
336 unsigned ResultReg = FastEmit_ri(VT.getSimpleVT(), VT.getSimpleVT(),
337 ISDOpcode, Op0, Op0IsKill,
339 if (ResultReg != 0) {
340 // We successfully emitted code for the given LLVM Instruction.
341 UpdateValueMap(I, ResultReg);
346 // Check if the second operand is a constant float.
347 if (ConstantFP *CF = dyn_cast<ConstantFP>(I->getOperand(1))) {
348 unsigned ResultReg = FastEmit_rf(VT.getSimpleVT(), VT.getSimpleVT(),
349 ISDOpcode, Op0, Op0IsKill, CF);
350 if (ResultReg != 0) {
351 // We successfully emitted code for the given LLVM Instruction.
352 UpdateValueMap(I, ResultReg);
357 unsigned Op1 = getRegForValue(I->getOperand(1));
359 // Unhandled operand. Halt "fast" selection and bail.
362 bool Op1IsKill = hasTrivialKill(I->getOperand(1));
364 // Now we have both operands in registers. Emit the instruction.
365 unsigned ResultReg = FastEmit_rr(VT.getSimpleVT(), VT.getSimpleVT(),
370 // Target-specific code wasn't able to find a machine opcode for
371 // the given ISD opcode and type. Halt "fast" selection and bail.
374 // We successfully emitted code for the given LLVM Instruction.
375 UpdateValueMap(I, ResultReg);
379 bool FastISel::SelectGetElementPtr(const User *I) {
380 unsigned N = getRegForValue(I->getOperand(0));
382 // Unhandled operand. Halt "fast" selection and bail.
385 bool NIsKill = hasTrivialKill(I->getOperand(0));
387 const Type *Ty = I->getOperand(0)->getType();
388 MVT VT = TLI.getPointerTy();
389 for (GetElementPtrInst::const_op_iterator OI = I->op_begin()+1,
390 E = I->op_end(); OI != E; ++OI) {
391 const Value *Idx = *OI;
392 if (const StructType *StTy = dyn_cast<StructType>(Ty)) {
393 unsigned Field = cast<ConstantInt>(Idx)->getZExtValue();
396 uint64_t Offs = TD.getStructLayout(StTy)->getElementOffset(Field);
397 // FIXME: This can be optimized by combining the add with a
399 N = FastEmit_ri_(VT, ISD::ADD, N, NIsKill, Offs, VT);
401 // Unhandled operand. Halt "fast" selection and bail.
405 Ty = StTy->getElementType(Field);
407 Ty = cast<SequentialType>(Ty)->getElementType();
409 // If this is a constant subscript, handle it quickly.
410 if (const ConstantInt *CI = dyn_cast<ConstantInt>(Idx)) {
411 if (CI->isZero()) continue;
413 TD.getTypeAllocSize(Ty)*cast<ConstantInt>(CI)->getSExtValue();
414 N = FastEmit_ri_(VT, ISD::ADD, N, NIsKill, Offs, VT);
416 // Unhandled operand. Halt "fast" selection and bail.
422 // N = N + Idx * ElementSize;
423 uint64_t ElementSize = TD.getTypeAllocSize(Ty);
424 std::pair<unsigned, bool> Pair = getRegForGEPIndex(Idx);
425 unsigned IdxN = Pair.first;
426 bool IdxNIsKill = Pair.second;
428 // Unhandled operand. Halt "fast" selection and bail.
431 if (ElementSize != 1) {
432 IdxN = FastEmit_ri_(VT, ISD::MUL, IdxN, IdxNIsKill, ElementSize, VT);
434 // Unhandled operand. Halt "fast" selection and bail.
438 N = FastEmit_rr(VT, VT, ISD::ADD, N, NIsKill, IdxN, IdxNIsKill);
440 // Unhandled operand. Halt "fast" selection and bail.
445 // We successfully emitted code for the given LLVM Instruction.
446 UpdateValueMap(I, N);
450 bool FastISel::SelectCall(const User *I) {
451 const Function *F = cast<CallInst>(I)->getCalledFunction();
452 if (!F) return false;
454 // Handle selected intrinsic function calls.
455 unsigned IID = F->getIntrinsicID();
458 case Intrinsic::dbg_declare: {
459 const DbgDeclareInst *DI = cast<DbgDeclareInst>(I);
460 if (!DIVariable(DI->getVariable()).Verify() ||
461 !FuncInfo.MF->getMMI().hasDebugInfo())
464 const Value *Address = DI->getAddress();
467 if (isa<UndefValue>(Address))
469 const AllocaInst *AI = dyn_cast<AllocaInst>(Address);
470 // Don't handle byval struct arguments or VLAs, for example.
471 // Note that if we have a byval struct argument, fast ISel is turned off;
472 // those are handled in SelectionDAGBuilder.
474 DenseMap<const AllocaInst*, int>::iterator SI =
475 FuncInfo.StaticAllocaMap.find(AI);
476 if (SI == FuncInfo.StaticAllocaMap.end()) break; // VLAs.
478 if (!DI->getDebugLoc().isUnknown())
479 FuncInfo.MF->getMMI().setVariableDbgInfo(DI->getVariable(),
480 FI, DI->getDebugLoc());
482 // Building the map above is target independent. Generating DBG_VALUE
483 // inline is target dependent; do this now.
484 (void)TargetSelectInstruction(cast<Instruction>(I));
487 case Intrinsic::dbg_value: {
488 // This form of DBG_VALUE is target-independent.
489 const DbgValueInst *DI = cast<DbgValueInst>(I);
490 const TargetInstrDesc &II = TII.get(TargetOpcode::DBG_VALUE);
491 const Value *V = DI->getValue();
493 // Currently the optimizer can produce this; insert an undef to
494 // help debugging. Probably the optimizer should not do this.
495 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
496 .addReg(0U).addImm(DI->getOffset())
497 .addMetadata(DI->getVariable());
498 } else if (const ConstantInt *CI = dyn_cast<ConstantInt>(V)) {
499 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
500 .addImm(CI->getZExtValue()).addImm(DI->getOffset())
501 .addMetadata(DI->getVariable());
502 } else if (const ConstantFP *CF = dyn_cast<ConstantFP>(V)) {
503 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
504 .addFPImm(CF).addImm(DI->getOffset())
505 .addMetadata(DI->getVariable());
506 } else if (unsigned Reg = lookUpRegForValue(V)) {
507 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
508 .addReg(Reg, RegState::Debug).addImm(DI->getOffset())
509 .addMetadata(DI->getVariable());
511 // We can't yet handle anything else here because it would require
512 // generating code, thus altering codegen because of debug info.
513 // Insert an undef so we can see what we dropped.
514 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
515 .addReg(0U).addImm(DI->getOffset())
516 .addMetadata(DI->getVariable());
520 case Intrinsic::eh_exception: {
521 EVT VT = TLI.getValueType(I->getType());
522 switch (TLI.getOperationAction(ISD::EXCEPTIONADDR, VT)) {
524 case TargetLowering::Expand: {
525 assert(FuncInfo.MBB->isLandingPad() &&
526 "Call to eh.exception not in landing pad!");
527 unsigned Reg = TLI.getExceptionAddressRegister();
528 const TargetRegisterClass *RC = TLI.getRegClassFor(VT);
529 unsigned ResultReg = createResultReg(RC);
530 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY),
531 ResultReg).addReg(Reg);
532 UpdateValueMap(I, ResultReg);
538 case Intrinsic::eh_selector: {
539 EVT VT = TLI.getValueType(I->getType());
540 switch (TLI.getOperationAction(ISD::EHSELECTION, VT)) {
542 case TargetLowering::Expand: {
543 if (FuncInfo.MBB->isLandingPad())
544 AddCatchInfo(*cast<CallInst>(I), &FuncInfo.MF->getMMI(), FuncInfo.MBB);
547 FuncInfo.CatchInfoLost.insert(cast<CallInst>(I));
549 // FIXME: Mark exception selector register as live in. Hack for PR1508.
550 unsigned Reg = TLI.getExceptionSelectorRegister();
551 if (Reg) FuncInfo.MBB->addLiveIn(Reg);
554 unsigned Reg = TLI.getExceptionSelectorRegister();
555 EVT SrcVT = TLI.getPointerTy();
556 const TargetRegisterClass *RC = TLI.getRegClassFor(SrcVT);
557 unsigned ResultReg = createResultReg(RC);
558 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY),
559 ResultReg).addReg(Reg);
561 bool ResultRegIsKill = hasTrivialKill(I);
563 // Cast the register to the type of the selector.
564 if (SrcVT.bitsGT(MVT::i32))
565 ResultReg = FastEmit_r(SrcVT.getSimpleVT(), MVT::i32, ISD::TRUNCATE,
566 ResultReg, ResultRegIsKill);
567 else if (SrcVT.bitsLT(MVT::i32))
568 ResultReg = FastEmit_r(SrcVT.getSimpleVT(), MVT::i32,
569 ISD::SIGN_EXTEND, ResultReg, ResultRegIsKill);
571 // Unhandled operand. Halt "fast" selection and bail.
574 UpdateValueMap(I, ResultReg);
583 // An arbitrary call. Bail.
587 bool FastISel::SelectCast(const User *I, unsigned Opcode) {
588 EVT SrcVT = TLI.getValueType(I->getOperand(0)->getType());
589 EVT DstVT = TLI.getValueType(I->getType());
591 if (SrcVT == MVT::Other || !SrcVT.isSimple() ||
592 DstVT == MVT::Other || !DstVT.isSimple())
593 // Unhandled type. Halt "fast" selection and bail.
596 // Check if the destination type is legal. Or as a special case,
597 // it may be i1 if we're doing a truncate because that's
598 // easy and somewhat common.
599 if (!TLI.isTypeLegal(DstVT))
600 if (DstVT != MVT::i1 || Opcode != ISD::TRUNCATE)
601 // Unhandled type. Halt "fast" selection and bail.
604 // Check if the source operand is legal. Or as a special case,
605 // it may be i1 if we're doing zero-extension because that's
606 // easy and somewhat common.
607 if (!TLI.isTypeLegal(SrcVT))
608 if (SrcVT != MVT::i1 || Opcode != ISD::ZERO_EXTEND)
609 // Unhandled type. Halt "fast" selection and bail.
612 unsigned InputReg = getRegForValue(I->getOperand(0));
614 // Unhandled operand. Halt "fast" selection and bail.
617 bool InputRegIsKill = hasTrivialKill(I->getOperand(0));
619 // If the operand is i1, arrange for the high bits in the register to be zero.
620 if (SrcVT == MVT::i1) {
621 SrcVT = TLI.getTypeToTransformTo(I->getContext(), SrcVT);
622 InputReg = FastEmitZExtFromI1(SrcVT.getSimpleVT(), InputReg, InputRegIsKill);
625 InputRegIsKill = true;
627 // If the result is i1, truncate to the target's type for i1 first.
628 if (DstVT == MVT::i1)
629 DstVT = TLI.getTypeToTransformTo(I->getContext(), DstVT);
631 unsigned ResultReg = FastEmit_r(SrcVT.getSimpleVT(),
634 InputReg, InputRegIsKill);
638 UpdateValueMap(I, ResultReg);
642 bool FastISel::SelectBitCast(const User *I) {
643 // If the bitcast doesn't change the type, just use the operand value.
644 if (I->getType() == I->getOperand(0)->getType()) {
645 unsigned Reg = getRegForValue(I->getOperand(0));
648 UpdateValueMap(I, Reg);
652 // Bitcasts of other values become reg-reg copies or BIT_CONVERT operators.
653 EVT SrcVT = TLI.getValueType(I->getOperand(0)->getType());
654 EVT DstVT = TLI.getValueType(I->getType());
656 if (SrcVT == MVT::Other || !SrcVT.isSimple() ||
657 DstVT == MVT::Other || !DstVT.isSimple() ||
658 !TLI.isTypeLegal(SrcVT) || !TLI.isTypeLegal(DstVT))
659 // Unhandled type. Halt "fast" selection and bail.
662 unsigned Op0 = getRegForValue(I->getOperand(0));
664 // Unhandled operand. Halt "fast" selection and bail.
667 bool Op0IsKill = hasTrivialKill(I->getOperand(0));
669 // First, try to perform the bitcast by inserting a reg-reg copy.
670 unsigned ResultReg = 0;
671 if (SrcVT.getSimpleVT() == DstVT.getSimpleVT()) {
672 TargetRegisterClass* SrcClass = TLI.getRegClassFor(SrcVT);
673 TargetRegisterClass* DstClass = TLI.getRegClassFor(DstVT);
674 // Don't attempt a cross-class copy. It will likely fail.
675 if (SrcClass == DstClass) {
676 ResultReg = createResultReg(DstClass);
677 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY),
678 ResultReg).addReg(Op0);
682 // If the reg-reg copy failed, select a BIT_CONVERT opcode.
684 ResultReg = FastEmit_r(SrcVT.getSimpleVT(), DstVT.getSimpleVT(),
685 ISD::BIT_CONVERT, Op0, Op0IsKill);
690 UpdateValueMap(I, ResultReg);
695 FastISel::SelectInstruction(const Instruction *I) {
696 // Just before the terminator instruction, insert instructions to
697 // feed PHI nodes in successor blocks.
698 if (isa<TerminatorInst>(I))
699 if (!HandlePHINodesInSuccessorBlocks(I->getParent()))
702 DL = I->getDebugLoc();
704 // First, try doing target-independent selection.
705 if (SelectOperator(I, I->getOpcode())) {
710 // Next, try calling the target to attempt to handle the instruction.
711 if (TargetSelectInstruction(I)) {
720 /// FastEmitBranch - Emit an unconditional branch to the given block,
721 /// unless it is the immediate (fall-through) successor, and update
724 FastISel::FastEmitBranch(MachineBasicBlock *MSucc, DebugLoc DL) {
725 if (FuncInfo.MBB->isLayoutSuccessor(MSucc)) {
726 // The unconditional fall-through case, which needs no instructions.
728 // The unconditional branch case.
729 TII.InsertBranch(*FuncInfo.MBB, MSucc, NULL,
730 SmallVector<MachineOperand, 0>(), DL);
732 FuncInfo.MBB->addSuccessor(MSucc);
735 /// SelectFNeg - Emit an FNeg operation.
738 FastISel::SelectFNeg(const User *I) {
739 unsigned OpReg = getRegForValue(BinaryOperator::getFNegArgument(I));
740 if (OpReg == 0) return false;
742 bool OpRegIsKill = hasTrivialKill(I);
744 // If the target has ISD::FNEG, use it.
745 EVT VT = TLI.getValueType(I->getType());
746 unsigned ResultReg = FastEmit_r(VT.getSimpleVT(), VT.getSimpleVT(),
747 ISD::FNEG, OpReg, OpRegIsKill);
748 if (ResultReg != 0) {
749 UpdateValueMap(I, ResultReg);
753 // Bitcast the value to integer, twiddle the sign bit with xor,
754 // and then bitcast it back to floating-point.
755 if (VT.getSizeInBits() > 64) return false;
756 EVT IntVT = EVT::getIntegerVT(I->getContext(), VT.getSizeInBits());
757 if (!TLI.isTypeLegal(IntVT))
760 unsigned IntReg = FastEmit_r(VT.getSimpleVT(), IntVT.getSimpleVT(),
761 ISD::BIT_CONVERT, OpReg, OpRegIsKill);
765 unsigned IntResultReg = FastEmit_ri_(IntVT.getSimpleVT(), ISD::XOR,
766 IntReg, /*Kill=*/true,
767 UINT64_C(1) << (VT.getSizeInBits()-1),
768 IntVT.getSimpleVT());
769 if (IntResultReg == 0)
772 ResultReg = FastEmit_r(IntVT.getSimpleVT(), VT.getSimpleVT(),
773 ISD::BIT_CONVERT, IntResultReg, /*Kill=*/true);
777 UpdateValueMap(I, ResultReg);
782 FastISel::SelectLoad(const User *I) {
783 LoadInst *LI = const_cast<LoadInst *>(cast<LoadInst>(I));
785 // For a load from an alloca, make a limited effort to find the value
786 // already available in a register, avoiding redundant loads.
787 if (!LI->isVolatile() && isa<AllocaInst>(LI->getPointerOperand())) {
788 BasicBlock::iterator ScanFrom = LI;
789 if (const Value *V = FindAvailableLoadedValue(LI->getPointerOperand(),
790 LI->getParent(), ScanFrom)) {
791 if (!V->use_empty() &&
792 (!isa<Instruction>(V) ||
793 cast<Instruction>(V)->getParent() == LI->getParent() ||
794 (isa<AllocaInst>(V) &&
795 FuncInfo.StaticAllocaMap.count(cast<AllocaInst>(V)))) &&
796 (!isa<Argument>(V) ||
797 LI->getParent() == &LI->getParent()->getParent()->getEntryBlock())) {
798 unsigned ResultReg = getRegForValue(V);
799 if (ResultReg != 0) {
800 UpdateValueMap(I, ResultReg);
811 FastISel::SelectOperator(const User *I, unsigned Opcode) {
813 case Instruction::Load:
814 return SelectLoad(I);
815 case Instruction::Add:
816 return SelectBinaryOp(I, ISD::ADD);
817 case Instruction::FAdd:
818 return SelectBinaryOp(I, ISD::FADD);
819 case Instruction::Sub:
820 return SelectBinaryOp(I, ISD::SUB);
821 case Instruction::FSub:
822 // FNeg is currently represented in LLVM IR as a special case of FSub.
823 if (BinaryOperator::isFNeg(I))
824 return SelectFNeg(I);
825 return SelectBinaryOp(I, ISD::FSUB);
826 case Instruction::Mul:
827 return SelectBinaryOp(I, ISD::MUL);
828 case Instruction::FMul:
829 return SelectBinaryOp(I, ISD::FMUL);
830 case Instruction::SDiv:
831 return SelectBinaryOp(I, ISD::SDIV);
832 case Instruction::UDiv:
833 return SelectBinaryOp(I, ISD::UDIV);
834 case Instruction::FDiv:
835 return SelectBinaryOp(I, ISD::FDIV);
836 case Instruction::SRem:
837 return SelectBinaryOp(I, ISD::SREM);
838 case Instruction::URem:
839 return SelectBinaryOp(I, ISD::UREM);
840 case Instruction::FRem:
841 return SelectBinaryOp(I, ISD::FREM);
842 case Instruction::Shl:
843 return SelectBinaryOp(I, ISD::SHL);
844 case Instruction::LShr:
845 return SelectBinaryOp(I, ISD::SRL);
846 case Instruction::AShr:
847 return SelectBinaryOp(I, ISD::SRA);
848 case Instruction::And:
849 return SelectBinaryOp(I, ISD::AND);
850 case Instruction::Or:
851 return SelectBinaryOp(I, ISD::OR);
852 case Instruction::Xor:
853 return SelectBinaryOp(I, ISD::XOR);
855 case Instruction::GetElementPtr:
856 return SelectGetElementPtr(I);
858 case Instruction::Br: {
859 const BranchInst *BI = cast<BranchInst>(I);
861 if (BI->isUnconditional()) {
862 const BasicBlock *LLVMSucc = BI->getSuccessor(0);
863 MachineBasicBlock *MSucc = FuncInfo.MBBMap[LLVMSucc];
864 FastEmitBranch(MSucc, BI->getDebugLoc());
868 // Conditional branches are not handed yet.
869 // Halt "fast" selection and bail.
873 case Instruction::Unreachable:
877 case Instruction::Alloca:
878 // FunctionLowering has the static-sized case covered.
879 if (FuncInfo.StaticAllocaMap.count(cast<AllocaInst>(I)))
882 // Dynamic-sized alloca is not handled yet.
885 case Instruction::Call:
886 return SelectCall(I);
888 case Instruction::BitCast:
889 return SelectBitCast(I);
891 case Instruction::FPToSI:
892 return SelectCast(I, ISD::FP_TO_SINT);
893 case Instruction::ZExt:
894 return SelectCast(I, ISD::ZERO_EXTEND);
895 case Instruction::SExt:
896 return SelectCast(I, ISD::SIGN_EXTEND);
897 case Instruction::Trunc:
898 return SelectCast(I, ISD::TRUNCATE);
899 case Instruction::SIToFP:
900 return SelectCast(I, ISD::SINT_TO_FP);
902 case Instruction::IntToPtr: // Deliberate fall-through.
903 case Instruction::PtrToInt: {
904 EVT SrcVT = TLI.getValueType(I->getOperand(0)->getType());
905 EVT DstVT = TLI.getValueType(I->getType());
906 if (DstVT.bitsGT(SrcVT))
907 return SelectCast(I, ISD::ZERO_EXTEND);
908 if (DstVT.bitsLT(SrcVT))
909 return SelectCast(I, ISD::TRUNCATE);
910 unsigned Reg = getRegForValue(I->getOperand(0));
911 if (Reg == 0) return false;
912 UpdateValueMap(I, Reg);
916 case Instruction::PHI:
917 llvm_unreachable("FastISel shouldn't visit PHI nodes!");
920 // Unhandled instruction. Halt "fast" selection and bail.
925 FastISel::FastISel(FunctionLoweringInfo &funcInfo)
926 : FuncInfo(funcInfo),
927 MRI(FuncInfo.MF->getRegInfo()),
928 MFI(*FuncInfo.MF->getFrameInfo()),
929 MCP(*FuncInfo.MF->getConstantPool()),
930 TM(FuncInfo.MF->getTarget()),
931 TD(*TM.getTargetData()),
932 TII(*TM.getInstrInfo()),
933 TLI(*TM.getTargetLowering()),
934 TRI(*TM.getRegisterInfo()) {
937 FastISel::~FastISel() {}
939 unsigned FastISel::FastEmit_(MVT, MVT,
944 unsigned FastISel::FastEmit_r(MVT, MVT,
946 unsigned /*Op0*/, bool /*Op0IsKill*/) {
950 unsigned FastISel::FastEmit_rr(MVT, MVT,
952 unsigned /*Op0*/, bool /*Op0IsKill*/,
953 unsigned /*Op1*/, bool /*Op1IsKill*/) {
957 unsigned FastISel::FastEmit_i(MVT, MVT, unsigned, uint64_t /*Imm*/) {
961 unsigned FastISel::FastEmit_f(MVT, MVT,
962 unsigned, const ConstantFP * /*FPImm*/) {
966 unsigned FastISel::FastEmit_ri(MVT, MVT,
968 unsigned /*Op0*/, bool /*Op0IsKill*/,
973 unsigned FastISel::FastEmit_rf(MVT, MVT,
975 unsigned /*Op0*/, bool /*Op0IsKill*/,
976 const ConstantFP * /*FPImm*/) {
980 unsigned FastISel::FastEmit_rri(MVT, MVT,
982 unsigned /*Op0*/, bool /*Op0IsKill*/,
983 unsigned /*Op1*/, bool /*Op1IsKill*/,
988 /// FastEmit_ri_ - This method is a wrapper of FastEmit_ri. It first tries
989 /// to emit an instruction with an immediate operand using FastEmit_ri.
990 /// If that fails, it materializes the immediate into a register and try
991 /// FastEmit_rr instead.
992 unsigned FastISel::FastEmit_ri_(MVT VT, unsigned Opcode,
993 unsigned Op0, bool Op0IsKill,
994 uint64_t Imm, MVT ImmType) {
995 // First check if immediate type is legal. If not, we can't use the ri form.
996 unsigned ResultReg = FastEmit_ri(VT, VT, Opcode, Op0, Op0IsKill, Imm);
999 unsigned MaterialReg = FastEmit_i(ImmType, ImmType, ISD::Constant, Imm);
1000 if (MaterialReg == 0)
1002 return FastEmit_rr(VT, VT, Opcode,
1004 MaterialReg, /*Kill=*/true);
1007 /// FastEmit_rf_ - This method is a wrapper of FastEmit_ri. It first tries
1008 /// to emit an instruction with a floating-point immediate operand using
1009 /// FastEmit_rf. If that fails, it materializes the immediate into a register
1010 /// and try FastEmit_rr instead.
1011 unsigned FastISel::FastEmit_rf_(MVT VT, unsigned Opcode,
1012 unsigned Op0, bool Op0IsKill,
1013 const ConstantFP *FPImm, MVT ImmType) {
1014 // First check if immediate type is legal. If not, we can't use the rf form.
1015 unsigned ResultReg = FastEmit_rf(VT, VT, Opcode, Op0, Op0IsKill, FPImm);
1019 // Materialize the constant in a register.
1020 unsigned MaterialReg = FastEmit_f(ImmType, ImmType, ISD::ConstantFP, FPImm);
1021 if (MaterialReg == 0) {
1022 // If the target doesn't have a way to directly enter a floating-point
1023 // value into a register, use an alternate approach.
1024 // TODO: The current approach only supports floating-point constants
1025 // that can be constructed by conversion from integer values. This should
1026 // be replaced by code that creates a load from a constant-pool entry,
1027 // which will require some target-specific work.
1028 const APFloat &Flt = FPImm->getValueAPF();
1029 EVT IntVT = TLI.getPointerTy();
1032 uint32_t IntBitWidth = IntVT.getSizeInBits();
1034 (void) Flt.convertToInteger(x, IntBitWidth, /*isSigned=*/true,
1035 APFloat::rmTowardZero, &isExact);
1038 APInt IntVal(IntBitWidth, 2, x);
1040 unsigned IntegerReg = FastEmit_i(IntVT.getSimpleVT(), IntVT.getSimpleVT(),
1041 ISD::Constant, IntVal.getZExtValue());
1042 if (IntegerReg == 0)
1044 MaterialReg = FastEmit_r(IntVT.getSimpleVT(), VT,
1045 ISD::SINT_TO_FP, IntegerReg, /*Kill=*/true);
1046 if (MaterialReg == 0)
1049 return FastEmit_rr(VT, VT, Opcode,
1051 MaterialReg, /*Kill=*/true);
1054 unsigned FastISel::createResultReg(const TargetRegisterClass* RC) {
1055 return MRI.createVirtualRegister(RC);
1058 unsigned FastISel::FastEmitInst_(unsigned MachineInstOpcode,
1059 const TargetRegisterClass* RC) {
1060 unsigned ResultReg = createResultReg(RC);
1061 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
1063 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg);
1067 unsigned FastISel::FastEmitInst_r(unsigned MachineInstOpcode,
1068 const TargetRegisterClass *RC,
1069 unsigned Op0, bool Op0IsKill) {
1070 unsigned ResultReg = createResultReg(RC);
1071 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
1073 if (II.getNumDefs() >= 1)
1074 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
1075 .addReg(Op0, Op0IsKill * RegState::Kill);
1077 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
1078 .addReg(Op0, Op0IsKill * RegState::Kill);
1079 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY),
1080 ResultReg).addReg(II.ImplicitDefs[0]);
1086 unsigned FastISel::FastEmitInst_rr(unsigned MachineInstOpcode,
1087 const TargetRegisterClass *RC,
1088 unsigned Op0, bool Op0IsKill,
1089 unsigned Op1, bool Op1IsKill) {
1090 unsigned ResultReg = createResultReg(RC);
1091 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
1093 if (II.getNumDefs() >= 1)
1094 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
1095 .addReg(Op0, Op0IsKill * RegState::Kill)
1096 .addReg(Op1, Op1IsKill * RegState::Kill);
1098 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
1099 .addReg(Op0, Op0IsKill * RegState::Kill)
1100 .addReg(Op1, Op1IsKill * RegState::Kill);
1101 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY),
1102 ResultReg).addReg(II.ImplicitDefs[0]);
1107 unsigned FastISel::FastEmitInst_ri(unsigned MachineInstOpcode,
1108 const TargetRegisterClass *RC,
1109 unsigned Op0, bool Op0IsKill,
1111 unsigned ResultReg = createResultReg(RC);
1112 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
1114 if (II.getNumDefs() >= 1)
1115 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
1116 .addReg(Op0, Op0IsKill * RegState::Kill)
1119 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
1120 .addReg(Op0, Op0IsKill * RegState::Kill)
1122 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY),
1123 ResultReg).addReg(II.ImplicitDefs[0]);
1128 unsigned FastISel::FastEmitInst_rf(unsigned MachineInstOpcode,
1129 const TargetRegisterClass *RC,
1130 unsigned Op0, bool Op0IsKill,
1131 const ConstantFP *FPImm) {
1132 unsigned ResultReg = createResultReg(RC);
1133 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
1135 if (II.getNumDefs() >= 1)
1136 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
1137 .addReg(Op0, Op0IsKill * RegState::Kill)
1140 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
1141 .addReg(Op0, Op0IsKill * RegState::Kill)
1143 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY),
1144 ResultReg).addReg(II.ImplicitDefs[0]);
1149 unsigned FastISel::FastEmitInst_rri(unsigned MachineInstOpcode,
1150 const TargetRegisterClass *RC,
1151 unsigned Op0, bool Op0IsKill,
1152 unsigned Op1, bool Op1IsKill,
1154 unsigned ResultReg = createResultReg(RC);
1155 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
1157 if (II.getNumDefs() >= 1)
1158 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
1159 .addReg(Op0, Op0IsKill * RegState::Kill)
1160 .addReg(Op1, Op1IsKill * RegState::Kill)
1163 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
1164 .addReg(Op0, Op0IsKill * RegState::Kill)
1165 .addReg(Op1, Op1IsKill * RegState::Kill)
1167 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY),
1168 ResultReg).addReg(II.ImplicitDefs[0]);
1173 unsigned FastISel::FastEmitInst_i(unsigned MachineInstOpcode,
1174 const TargetRegisterClass *RC,
1176 unsigned ResultReg = createResultReg(RC);
1177 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
1179 if (II.getNumDefs() >= 1)
1180 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg).addImm(Imm);
1182 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II).addImm(Imm);
1183 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY),
1184 ResultReg).addReg(II.ImplicitDefs[0]);
1189 unsigned FastISel::FastEmitInst_extractsubreg(MVT RetVT,
1190 unsigned Op0, bool Op0IsKill,
1192 unsigned ResultReg = createResultReg(TLI.getRegClassFor(RetVT));
1193 assert(TargetRegisterInfo::isVirtualRegister(Op0) &&
1194 "Cannot yet extract from physregs");
1195 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt,
1196 DL, TII.get(TargetOpcode::COPY), ResultReg)
1197 .addReg(Op0, getKillRegState(Op0IsKill), Idx);
1201 /// FastEmitZExtFromI1 - Emit MachineInstrs to compute the value of Op
1202 /// with all but the least significant bit set to zero.
1203 unsigned FastISel::FastEmitZExtFromI1(MVT VT, unsigned Op0, bool Op0IsKill) {
1204 return FastEmit_ri(VT, VT, ISD::AND, Op0, Op0IsKill, 1);
1207 /// HandlePHINodesInSuccessorBlocks - Handle PHI nodes in successor blocks.
1208 /// Emit code to ensure constants are copied into registers when needed.
1209 /// Remember the virtual registers that need to be added to the Machine PHI
1210 /// nodes as input. We cannot just directly add them, because expansion
1211 /// might result in multiple MBB's for one BB. As such, the start of the
1212 /// BB might correspond to a different MBB than the end.
1213 bool FastISel::HandlePHINodesInSuccessorBlocks(const BasicBlock *LLVMBB) {
1214 const TerminatorInst *TI = LLVMBB->getTerminator();
1216 SmallPtrSet<MachineBasicBlock *, 4> SuccsHandled;
1217 unsigned OrigNumPHINodesToUpdate = FuncInfo.PHINodesToUpdate.size();
1219 // Check successor nodes' PHI nodes that expect a constant to be available
1221 for (unsigned succ = 0, e = TI->getNumSuccessors(); succ != e; ++succ) {
1222 const BasicBlock *SuccBB = TI->getSuccessor(succ);
1223 if (!isa<PHINode>(SuccBB->begin())) continue;
1224 MachineBasicBlock *SuccMBB = FuncInfo.MBBMap[SuccBB];
1226 // If this terminator has multiple identical successors (common for
1227 // switches), only handle each succ once.
1228 if (!SuccsHandled.insert(SuccMBB)) continue;
1230 MachineBasicBlock::iterator MBBI = SuccMBB->begin();
1232 // At this point we know that there is a 1-1 correspondence between LLVM PHI
1233 // nodes and Machine PHI nodes, but the incoming operands have not been
1235 for (BasicBlock::const_iterator I = SuccBB->begin();
1236 const PHINode *PN = dyn_cast<PHINode>(I); ++I) {
1238 // Ignore dead phi's.
1239 if (PN->use_empty()) continue;
1241 // Only handle legal types. Two interesting things to note here. First,
1242 // by bailing out early, we may leave behind some dead instructions,
1243 // since SelectionDAG's HandlePHINodesInSuccessorBlocks will insert its
1244 // own moves. Second, this check is necessary becuase FastISel doesn't
1245 // use CreateRegs to create registers, so it always creates
1246 // exactly one register for each non-void instruction.
1247 EVT VT = TLI.getValueType(PN->getType(), /*AllowUnknown=*/true);
1248 if (VT == MVT::Other || !TLI.isTypeLegal(VT)) {
1251 VT = TLI.getTypeToTransformTo(LLVMBB->getContext(), VT);
1253 FuncInfo.PHINodesToUpdate.resize(OrigNumPHINodesToUpdate);
1258 const Value *PHIOp = PN->getIncomingValueForBlock(LLVMBB);
1260 // Set the DebugLoc for the copy. Prefer the location of the operand
1261 // if there is one; use the location of the PHI otherwise.
1262 DL = PN->getDebugLoc();
1263 if (const Instruction *Inst = dyn_cast<Instruction>(PHIOp))
1264 DL = Inst->getDebugLoc();
1266 unsigned Reg = getRegForValue(PHIOp);
1268 FuncInfo.PHINodesToUpdate.resize(OrigNumPHINodesToUpdate);
1271 FuncInfo.PHINodesToUpdate.push_back(std::make_pair(MBBI++, Reg));