1 ///===-- FastISel.cpp - Implementation of the FastISel class --------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the implementation of the FastISel class.
12 // "Fast" instruction selection is designed to emit very poor code quickly.
13 // Also, it is not designed to be able to do much lowering, so most illegal
14 // types (e.g. i64 on 32-bit targets) and operations are not supported. It is
15 // also not intended to be able to do much optimization, except in a few cases
16 // where doing optimizations reduces overall compile time. For example, folding
17 // constants into immediate fields is often done, because it's cheap and it
18 // reduces the number of instructions later phases have to examine.
20 // "Fast" instruction selection is able to fail gracefully and transfer
21 // control to the SelectionDAG selector for operations that it doesn't
22 // support. In many cases, this allows us to avoid duplicating a lot of
23 // the complicated lowering logic that SelectionDAG currently has.
25 // The intended use for "fast" instruction selection is "-O0" mode
26 // compilation, where the quality of the generated code is irrelevant when
27 // weighed against the speed at which the code can be generated. Also,
28 // at -O0, the LLVM optimizers are not running, and this makes the
29 // compile time of codegen a much higher portion of the overall compile
30 // time. Despite its limitations, "fast" instruction selection is able to
31 // handle enough code on its own to provide noticeable overall speedups
34 // Basic operations are supported in a target-independent way, by reading
35 // the same instruction descriptions that the SelectionDAG selector reads,
36 // and identifying simple arithmetic operations that can be directly selected
37 // from simple operators. More complicated operations currently require
38 // target-specific code.
40 //===----------------------------------------------------------------------===//
42 #include "llvm/Function.h"
43 #include "llvm/GlobalVariable.h"
44 #include "llvm/Instructions.h"
45 #include "llvm/IntrinsicInst.h"
46 #include "llvm/CodeGen/FastISel.h"
47 #include "llvm/CodeGen/MachineInstrBuilder.h"
48 #include "llvm/CodeGen/MachineModuleInfo.h"
49 #include "llvm/CodeGen/MachineRegisterInfo.h"
50 #include "llvm/CodeGen/DwarfWriter.h"
51 #include "llvm/Analysis/DebugInfo.h"
52 #include "llvm/Target/TargetData.h"
53 #include "llvm/Target/TargetInstrInfo.h"
54 #include "llvm/Target/TargetLowering.h"
55 #include "llvm/Target/TargetMachine.h"
56 #include "SelectionDAGBuilder.h"
57 #include "FunctionLoweringInfo.h"
60 unsigned FastISel::getRegForValue(Value *V) {
61 EVT RealVT = TLI.getValueType(V->getType(), /*AllowUnknown=*/true);
62 // Don't handle non-simple values in FastISel.
63 if (!RealVT.isSimple())
66 // Ignore illegal types. We must do this before looking up the value
67 // in ValueMap because Arguments are given virtual registers regardless
68 // of whether FastISel can handle them.
69 MVT VT = RealVT.getSimpleVT();
70 if (!TLI.isTypeLegal(VT)) {
71 // Promote MVT::i1 to a legal type though, because it's common and easy.
73 VT = TLI.getTypeToTransformTo(V->getContext(), VT).getSimpleVT();
78 // Look up the value to see if we already have a register for it. We
79 // cache values defined by Instructions across blocks, and other values
80 // only locally. This is because Instructions already have the SSA
81 // def-dominates-use requirement enforced.
82 if (ValueMap.count(V))
84 unsigned Reg = LocalValueMap[V];
88 if (ConstantInt *CI = dyn_cast<ConstantInt>(V)) {
89 if (CI->getValue().getActiveBits() <= 64)
90 Reg = FastEmit_i(VT, VT, ISD::Constant, CI->getZExtValue());
91 } else if (isa<AllocaInst>(V)) {
92 Reg = TargetMaterializeAlloca(cast<AllocaInst>(V));
93 } else if (isa<ConstantPointerNull>(V)) {
94 // Translate this as an integer zero so that it can be
95 // local-CSE'd with actual integer zeros.
97 getRegForValue(Constant::getNullValue(TD.getIntPtrType(V->getContext())));
98 } else if (ConstantFP *CF = dyn_cast<ConstantFP>(V)) {
99 Reg = FastEmit_f(VT, VT, ISD::ConstantFP, CF);
102 const APFloat &Flt = CF->getValueAPF();
103 EVT IntVT = TLI.getPointerTy();
106 uint32_t IntBitWidth = IntVT.getSizeInBits();
108 (void) Flt.convertToInteger(x, IntBitWidth, /*isSigned=*/true,
109 APFloat::rmTowardZero, &isExact);
111 APInt IntVal(IntBitWidth, 2, x);
113 unsigned IntegerReg =
114 getRegForValue(ConstantInt::get(V->getContext(), IntVal));
116 Reg = FastEmit_r(IntVT.getSimpleVT(), VT, ISD::SINT_TO_FP, IntegerReg);
119 } else if (ConstantExpr *CE = dyn_cast<ConstantExpr>(V)) {
120 if (!SelectOperator(CE, CE->getOpcode())) return 0;
121 Reg = LocalValueMap[CE];
122 } else if (isa<UndefValue>(V)) {
123 Reg = createResultReg(TLI.getRegClassFor(VT));
124 BuildMI(MBB, DL, TII.get(TargetInstrInfo::IMPLICIT_DEF), Reg);
127 // If target-independent code couldn't handle the value, give target-specific
129 if (!Reg && isa<Constant>(V))
130 Reg = TargetMaterializeConstant(cast<Constant>(V));
132 // Don't cache constant materializations in the general ValueMap.
133 // To do so would require tracking what uses they dominate.
135 LocalValueMap[V] = Reg;
139 unsigned FastISel::lookUpRegForValue(Value *V) {
140 // Look up the value to see if we already have a register for it. We
141 // cache values defined by Instructions across blocks, and other values
142 // only locally. This is because Instructions already have the SSA
143 // def-dominatess-use requirement enforced.
144 if (ValueMap.count(V))
146 return LocalValueMap[V];
149 /// UpdateValueMap - Update the value map to include the new mapping for this
150 /// instruction, or insert an extra copy to get the result in a previous
151 /// determined register.
152 /// NOTE: This is only necessary because we might select a block that uses
153 /// a value before we select the block that defines the value. It might be
154 /// possible to fix this by selecting blocks in reverse postorder.
155 unsigned FastISel::UpdateValueMap(Value* I, unsigned Reg) {
156 if (!isa<Instruction>(I)) {
157 LocalValueMap[I] = Reg;
161 unsigned &AssignedReg = ValueMap[I];
162 if (AssignedReg == 0)
164 else if (Reg != AssignedReg) {
165 const TargetRegisterClass *RegClass = MRI.getRegClass(Reg);
166 TII.copyRegToReg(*MBB, MBB->end(), AssignedReg,
167 Reg, RegClass, RegClass);
172 unsigned FastISel::getRegForGEPIndex(Value *Idx) {
173 unsigned IdxN = getRegForValue(Idx);
175 // Unhandled operand. Halt "fast" selection and bail.
178 // If the index is smaller or larger than intptr_t, truncate or extend it.
179 MVT PtrVT = TLI.getPointerTy();
180 EVT IdxVT = EVT::getEVT(Idx->getType(), /*HandleUnknown=*/false);
181 if (IdxVT.bitsLT(PtrVT))
182 IdxN = FastEmit_r(IdxVT.getSimpleVT(), PtrVT, ISD::SIGN_EXTEND, IdxN);
183 else if (IdxVT.bitsGT(PtrVT))
184 IdxN = FastEmit_r(IdxVT.getSimpleVT(), PtrVT, ISD::TRUNCATE, IdxN);
188 /// SelectBinaryOp - Select and emit code for a binary operator instruction,
189 /// which has an opcode which directly corresponds to the given ISD opcode.
191 bool FastISel::SelectBinaryOp(User *I, unsigned ISDOpcode) {
192 EVT VT = EVT::getEVT(I->getType(), /*HandleUnknown=*/true);
193 if (VT == MVT::Other || !VT.isSimple())
194 // Unhandled type. Halt "fast" selection and bail.
197 // We only handle legal types. For example, on x86-32 the instruction
198 // selector contains all of the 64-bit instructions from x86-64,
199 // under the assumption that i64 won't be used if the target doesn't
201 if (!TLI.isTypeLegal(VT)) {
202 // MVT::i1 is special. Allow AND, OR, or XOR because they
203 // don't require additional zeroing, which makes them easy.
205 (ISDOpcode == ISD::AND || ISDOpcode == ISD::OR ||
206 ISDOpcode == ISD::XOR))
207 VT = TLI.getTypeToTransformTo(I->getContext(), VT);
212 unsigned Op0 = getRegForValue(I->getOperand(0));
214 // Unhandled operand. Halt "fast" selection and bail.
217 // Check if the second operand is a constant and handle it appropriately.
218 if (ConstantInt *CI = dyn_cast<ConstantInt>(I->getOperand(1))) {
219 unsigned ResultReg = FastEmit_ri(VT.getSimpleVT(), VT.getSimpleVT(),
220 ISDOpcode, Op0, CI->getZExtValue());
221 if (ResultReg != 0) {
222 // We successfully emitted code for the given LLVM Instruction.
223 UpdateValueMap(I, ResultReg);
228 // Check if the second operand is a constant float.
229 if (ConstantFP *CF = dyn_cast<ConstantFP>(I->getOperand(1))) {
230 unsigned ResultReg = FastEmit_rf(VT.getSimpleVT(), VT.getSimpleVT(),
232 if (ResultReg != 0) {
233 // We successfully emitted code for the given LLVM Instruction.
234 UpdateValueMap(I, ResultReg);
239 unsigned Op1 = getRegForValue(I->getOperand(1));
241 // Unhandled operand. Halt "fast" selection and bail.
244 // Now we have both operands in registers. Emit the instruction.
245 unsigned ResultReg = FastEmit_rr(VT.getSimpleVT(), VT.getSimpleVT(),
246 ISDOpcode, Op0, Op1);
248 // Target-specific code wasn't able to find a machine opcode for
249 // the given ISD opcode and type. Halt "fast" selection and bail.
252 // We successfully emitted code for the given LLVM Instruction.
253 UpdateValueMap(I, ResultReg);
257 bool FastISel::SelectGetElementPtr(User *I) {
258 unsigned N = getRegForValue(I->getOperand(0));
260 // Unhandled operand. Halt "fast" selection and bail.
263 const Type *Ty = I->getOperand(0)->getType();
264 MVT VT = TLI.getPointerTy();
265 for (GetElementPtrInst::op_iterator OI = I->op_begin()+1, E = I->op_end();
268 if (const StructType *StTy = dyn_cast<StructType>(Ty)) {
269 unsigned Field = cast<ConstantInt>(Idx)->getZExtValue();
272 uint64_t Offs = TD.getStructLayout(StTy)->getElementOffset(Field);
273 // FIXME: This can be optimized by combining the add with a
275 N = FastEmit_ri_(VT, ISD::ADD, N, Offs, VT);
277 // Unhandled operand. Halt "fast" selection and bail.
280 Ty = StTy->getElementType(Field);
282 Ty = cast<SequentialType>(Ty)->getElementType();
284 // If this is a constant subscript, handle it quickly.
285 if (ConstantInt *CI = dyn_cast<ConstantInt>(Idx)) {
286 if (CI->getZExtValue() == 0) continue;
288 TD.getTypeAllocSize(Ty)*cast<ConstantInt>(CI)->getSExtValue();
289 N = FastEmit_ri_(VT, ISD::ADD, N, Offs, VT);
291 // Unhandled operand. Halt "fast" selection and bail.
296 // N = N + Idx * ElementSize;
297 uint64_t ElementSize = TD.getTypeAllocSize(Ty);
298 unsigned IdxN = getRegForGEPIndex(Idx);
300 // Unhandled operand. Halt "fast" selection and bail.
303 if (ElementSize != 1) {
304 IdxN = FastEmit_ri_(VT, ISD::MUL, IdxN, ElementSize, VT);
306 // Unhandled operand. Halt "fast" selection and bail.
309 N = FastEmit_rr(VT, VT, ISD::ADD, N, IdxN);
311 // Unhandled operand. Halt "fast" selection and bail.
316 // We successfully emitted code for the given LLVM Instruction.
317 UpdateValueMap(I, N);
321 bool FastISel::SelectCall(User *I) {
322 Function *F = cast<CallInst>(I)->getCalledFunction();
323 if (!F) return false;
325 unsigned IID = F->getIntrinsicID();
328 case Intrinsic::dbg_declare: {
329 DbgDeclareInst *DI = cast<DbgDeclareInst>(I);
330 if (!DIDescriptor::ValidDebugInfo(DI->getVariable(), CodeGenOpt::None)||!DW
331 || !DW->ShouldEmitDwarfDebug())
334 Value *Address = DI->getAddress();
335 AllocaInst *AI = dyn_cast<AllocaInst>(Address);
336 // Don't handle byval struct arguments or VLAs, for example.
338 DenseMap<const AllocaInst*, int>::iterator SI =
339 StaticAllocaMap.find(AI);
340 if (SI == StaticAllocaMap.end()) break; // VLAs.
343 if (MDNode *Dbg = DI->getMetadata("dbg"))
344 MMI->setVariableDbgInfo(DI->getVariable(), FI, Dbg);
348 case Intrinsic::eh_exception: {
349 EVT VT = TLI.getValueType(I->getType());
350 switch (TLI.getOperationAction(ISD::EXCEPTIONADDR, VT)) {
352 case TargetLowering::Expand: {
353 assert(MBB->isLandingPad() && "Call to eh.exception not in landing pad!");
354 unsigned Reg = TLI.getExceptionAddressRegister();
355 const TargetRegisterClass *RC = TLI.getRegClassFor(VT);
356 unsigned ResultReg = createResultReg(RC);
357 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
359 assert(InsertedCopy && "Can't copy address registers!");
360 InsertedCopy = InsertedCopy;
361 UpdateValueMap(I, ResultReg);
367 case Intrinsic::eh_selector: {
368 EVT VT = TLI.getValueType(I->getType());
369 switch (TLI.getOperationAction(ISD::EHSELECTION, VT)) {
371 case TargetLowering::Expand: {
373 if (MBB->isLandingPad())
374 AddCatchInfo(*cast<CallInst>(I), MMI, MBB);
377 CatchInfoLost.insert(cast<CallInst>(I));
379 // FIXME: Mark exception selector register as live in. Hack for PR1508.
380 unsigned Reg = TLI.getExceptionSelectorRegister();
381 if (Reg) MBB->addLiveIn(Reg);
384 unsigned Reg = TLI.getExceptionSelectorRegister();
385 EVT SrcVT = TLI.getPointerTy();
386 const TargetRegisterClass *RC = TLI.getRegClassFor(SrcVT);
387 unsigned ResultReg = createResultReg(RC);
388 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg, Reg,
390 assert(InsertedCopy && "Can't copy address registers!");
391 InsertedCopy = InsertedCopy;
393 // Cast the register to the type of the selector.
394 if (SrcVT.bitsGT(MVT::i32))
395 ResultReg = FastEmit_r(SrcVT.getSimpleVT(), MVT::i32, ISD::TRUNCATE,
397 else if (SrcVT.bitsLT(MVT::i32))
398 ResultReg = FastEmit_r(SrcVT.getSimpleVT(), MVT::i32,
399 ISD::SIGN_EXTEND, ResultReg);
401 // Unhandled operand. Halt "fast" selection and bail.
404 UpdateValueMap(I, ResultReg);
407 getRegForValue(Constant::getNullValue(I->getType()));
408 UpdateValueMap(I, ResultReg);
419 bool FastISel::SelectCast(User *I, unsigned Opcode) {
420 EVT SrcVT = TLI.getValueType(I->getOperand(0)->getType());
421 EVT DstVT = TLI.getValueType(I->getType());
423 if (SrcVT == MVT::Other || !SrcVT.isSimple() ||
424 DstVT == MVT::Other || !DstVT.isSimple())
425 // Unhandled type. Halt "fast" selection and bail.
428 // Check if the destination type is legal. Or as a special case,
429 // it may be i1 if we're doing a truncate because that's
430 // easy and somewhat common.
431 if (!TLI.isTypeLegal(DstVT))
432 if (DstVT != MVT::i1 || Opcode != ISD::TRUNCATE)
433 // Unhandled type. Halt "fast" selection and bail.
436 // Check if the source operand is legal. Or as a special case,
437 // it may be i1 if we're doing zero-extension because that's
438 // easy and somewhat common.
439 if (!TLI.isTypeLegal(SrcVT))
440 if (SrcVT != MVT::i1 || Opcode != ISD::ZERO_EXTEND)
441 // Unhandled type. Halt "fast" selection and bail.
444 unsigned InputReg = getRegForValue(I->getOperand(0));
446 // Unhandled operand. Halt "fast" selection and bail.
449 // If the operand is i1, arrange for the high bits in the register to be zero.
450 if (SrcVT == MVT::i1) {
451 SrcVT = TLI.getTypeToTransformTo(I->getContext(), SrcVT);
452 InputReg = FastEmitZExtFromI1(SrcVT.getSimpleVT(), InputReg);
456 // If the result is i1, truncate to the target's type for i1 first.
457 if (DstVT == MVT::i1)
458 DstVT = TLI.getTypeToTransformTo(I->getContext(), DstVT);
460 unsigned ResultReg = FastEmit_r(SrcVT.getSimpleVT(),
467 UpdateValueMap(I, ResultReg);
471 bool FastISel::SelectBitCast(User *I) {
472 // If the bitcast doesn't change the type, just use the operand value.
473 if (I->getType() == I->getOperand(0)->getType()) {
474 unsigned Reg = getRegForValue(I->getOperand(0));
477 UpdateValueMap(I, Reg);
481 // Bitcasts of other values become reg-reg copies or BIT_CONVERT operators.
482 EVT SrcVT = TLI.getValueType(I->getOperand(0)->getType());
483 EVT DstVT = TLI.getValueType(I->getType());
485 if (SrcVT == MVT::Other || !SrcVT.isSimple() ||
486 DstVT == MVT::Other || !DstVT.isSimple() ||
487 !TLI.isTypeLegal(SrcVT) || !TLI.isTypeLegal(DstVT))
488 // Unhandled type. Halt "fast" selection and bail.
491 unsigned Op0 = getRegForValue(I->getOperand(0));
493 // Unhandled operand. Halt "fast" selection and bail.
496 // First, try to perform the bitcast by inserting a reg-reg copy.
497 unsigned ResultReg = 0;
498 if (SrcVT.getSimpleVT() == DstVT.getSimpleVT()) {
499 TargetRegisterClass* SrcClass = TLI.getRegClassFor(SrcVT);
500 TargetRegisterClass* DstClass = TLI.getRegClassFor(DstVT);
501 ResultReg = createResultReg(DstClass);
503 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
504 Op0, DstClass, SrcClass);
509 // If the reg-reg copy failed, select a BIT_CONVERT opcode.
511 ResultReg = FastEmit_r(SrcVT.getSimpleVT(), DstVT.getSimpleVT(),
512 ISD::BIT_CONVERT, Op0);
517 UpdateValueMap(I, ResultReg);
522 FastISel::SelectInstruction(Instruction *I) {
523 // First, try doing target-independent selection.
524 if (SelectOperator(I, I->getOpcode()))
527 // Next, try calling the target to attempt to handle the instruction.
528 if (TargetSelectInstruction(I))
534 /// FastEmitBranch - Emit an unconditional branch to the given block,
535 /// unless it is the immediate (fall-through) successor, and update
538 FastISel::FastEmitBranch(MachineBasicBlock *MSucc) {
539 if (MBB->isLayoutSuccessor(MSucc)) {
540 // The unconditional fall-through case, which needs no instructions.
542 // The unconditional branch case.
543 TII.InsertBranch(*MBB, MSucc, NULL, SmallVector<MachineOperand, 0>());
545 MBB->addSuccessor(MSucc);
548 /// SelectFNeg - Emit an FNeg operation.
551 FastISel::SelectFNeg(User *I) {
552 unsigned OpReg = getRegForValue(BinaryOperator::getFNegArgument(I));
553 if (OpReg == 0) return false;
555 // If the target has ISD::FNEG, use it.
556 EVT VT = TLI.getValueType(I->getType());
557 unsigned ResultReg = FastEmit_r(VT.getSimpleVT(), VT.getSimpleVT(),
559 if (ResultReg != 0) {
560 UpdateValueMap(I, ResultReg);
564 // Bitcast the value to integer, twiddle the sign bit with xor,
565 // and then bitcast it back to floating-point.
566 if (VT.getSizeInBits() > 64) return false;
567 EVT IntVT = EVT::getIntegerVT(I->getContext(), VT.getSizeInBits());
568 if (!TLI.isTypeLegal(IntVT))
571 unsigned IntReg = FastEmit_r(VT.getSimpleVT(), IntVT.getSimpleVT(),
572 ISD::BIT_CONVERT, OpReg);
576 unsigned IntResultReg = FastEmit_ri_(IntVT.getSimpleVT(), ISD::XOR, IntReg,
577 UINT64_C(1) << (VT.getSizeInBits()-1),
578 IntVT.getSimpleVT());
579 if (IntResultReg == 0)
582 ResultReg = FastEmit_r(IntVT.getSimpleVT(), VT.getSimpleVT(),
583 ISD::BIT_CONVERT, IntResultReg);
587 UpdateValueMap(I, ResultReg);
592 FastISel::SelectOperator(User *I, unsigned Opcode) {
594 case Instruction::Add:
595 return SelectBinaryOp(I, ISD::ADD);
596 case Instruction::FAdd:
597 return SelectBinaryOp(I, ISD::FADD);
598 case Instruction::Sub:
599 return SelectBinaryOp(I, ISD::SUB);
600 case Instruction::FSub:
601 // FNeg is currently represented in LLVM IR as a special case of FSub.
602 if (BinaryOperator::isFNeg(I))
603 return SelectFNeg(I);
604 return SelectBinaryOp(I, ISD::FSUB);
605 case Instruction::Mul:
606 return SelectBinaryOp(I, ISD::MUL);
607 case Instruction::FMul:
608 return SelectBinaryOp(I, ISD::FMUL);
609 case Instruction::SDiv:
610 return SelectBinaryOp(I, ISD::SDIV);
611 case Instruction::UDiv:
612 return SelectBinaryOp(I, ISD::UDIV);
613 case Instruction::FDiv:
614 return SelectBinaryOp(I, ISD::FDIV);
615 case Instruction::SRem:
616 return SelectBinaryOp(I, ISD::SREM);
617 case Instruction::URem:
618 return SelectBinaryOp(I, ISD::UREM);
619 case Instruction::FRem:
620 return SelectBinaryOp(I, ISD::FREM);
621 case Instruction::Shl:
622 return SelectBinaryOp(I, ISD::SHL);
623 case Instruction::LShr:
624 return SelectBinaryOp(I, ISD::SRL);
625 case Instruction::AShr:
626 return SelectBinaryOp(I, ISD::SRA);
627 case Instruction::And:
628 return SelectBinaryOp(I, ISD::AND);
629 case Instruction::Or:
630 return SelectBinaryOp(I, ISD::OR);
631 case Instruction::Xor:
632 return SelectBinaryOp(I, ISD::XOR);
634 case Instruction::GetElementPtr:
635 return SelectGetElementPtr(I);
637 case Instruction::Br: {
638 BranchInst *BI = cast<BranchInst>(I);
640 if (BI->isUnconditional()) {
641 BasicBlock *LLVMSucc = BI->getSuccessor(0);
642 MachineBasicBlock *MSucc = MBBMap[LLVMSucc];
643 FastEmitBranch(MSucc);
647 // Conditional branches are not handed yet.
648 // Halt "fast" selection and bail.
652 case Instruction::Unreachable:
656 case Instruction::PHI:
657 // PHI nodes are already emitted.
660 case Instruction::Alloca:
661 // FunctionLowering has the static-sized case covered.
662 if (StaticAllocaMap.count(cast<AllocaInst>(I)))
665 // Dynamic-sized alloca is not handled yet.
668 case Instruction::Call:
669 return SelectCall(I);
671 case Instruction::BitCast:
672 return SelectBitCast(I);
674 case Instruction::FPToSI:
675 return SelectCast(I, ISD::FP_TO_SINT);
676 case Instruction::ZExt:
677 return SelectCast(I, ISD::ZERO_EXTEND);
678 case Instruction::SExt:
679 return SelectCast(I, ISD::SIGN_EXTEND);
680 case Instruction::Trunc:
681 return SelectCast(I, ISD::TRUNCATE);
682 case Instruction::SIToFP:
683 return SelectCast(I, ISD::SINT_TO_FP);
685 case Instruction::IntToPtr: // Deliberate fall-through.
686 case Instruction::PtrToInt: {
687 EVT SrcVT = TLI.getValueType(I->getOperand(0)->getType());
688 EVT DstVT = TLI.getValueType(I->getType());
689 if (DstVT.bitsGT(SrcVT))
690 return SelectCast(I, ISD::ZERO_EXTEND);
691 if (DstVT.bitsLT(SrcVT))
692 return SelectCast(I, ISD::TRUNCATE);
693 unsigned Reg = getRegForValue(I->getOperand(0));
694 if (Reg == 0) return false;
695 UpdateValueMap(I, Reg);
700 // Unhandled instruction. Halt "fast" selection and bail.
705 FastISel::FastISel(MachineFunction &mf,
706 MachineModuleInfo *mmi,
708 DenseMap<const Value *, unsigned> &vm,
709 DenseMap<const BasicBlock *, MachineBasicBlock *> &bm,
710 DenseMap<const AllocaInst *, int> &am
712 , SmallSet<Instruction*, 8> &cil
725 MRI(MF.getRegInfo()),
726 MFI(*MF.getFrameInfo()),
727 MCP(*MF.getConstantPool()),
729 TD(*TM.getTargetData()),
730 TII(*TM.getInstrInfo()),
731 TLI(*TM.getTargetLowering()) {
734 FastISel::~FastISel() {}
736 unsigned FastISel::FastEmit_(MVT, MVT,
741 unsigned FastISel::FastEmit_r(MVT, MVT,
742 unsigned, unsigned /*Op0*/) {
746 unsigned FastISel::FastEmit_rr(MVT, MVT,
747 unsigned, unsigned /*Op0*/,
752 unsigned FastISel::FastEmit_i(MVT, MVT, unsigned, uint64_t /*Imm*/) {
756 unsigned FastISel::FastEmit_f(MVT, MVT,
757 unsigned, ConstantFP * /*FPImm*/) {
761 unsigned FastISel::FastEmit_ri(MVT, MVT,
762 unsigned, unsigned /*Op0*/,
767 unsigned FastISel::FastEmit_rf(MVT, MVT,
768 unsigned, unsigned /*Op0*/,
769 ConstantFP * /*FPImm*/) {
773 unsigned FastISel::FastEmit_rri(MVT, MVT,
775 unsigned /*Op0*/, unsigned /*Op1*/,
780 /// FastEmit_ri_ - This method is a wrapper of FastEmit_ri. It first tries
781 /// to emit an instruction with an immediate operand using FastEmit_ri.
782 /// If that fails, it materializes the immediate into a register and try
783 /// FastEmit_rr instead.
784 unsigned FastISel::FastEmit_ri_(MVT VT, unsigned Opcode,
785 unsigned Op0, uint64_t Imm,
787 // First check if immediate type is legal. If not, we can't use the ri form.
788 unsigned ResultReg = FastEmit_ri(VT, VT, Opcode, Op0, Imm);
791 unsigned MaterialReg = FastEmit_i(ImmType, ImmType, ISD::Constant, Imm);
792 if (MaterialReg == 0)
794 return FastEmit_rr(VT, VT, Opcode, Op0, MaterialReg);
797 /// FastEmit_rf_ - This method is a wrapper of FastEmit_ri. It first tries
798 /// to emit an instruction with a floating-point immediate operand using
799 /// FastEmit_rf. If that fails, it materializes the immediate into a register
800 /// and try FastEmit_rr instead.
801 unsigned FastISel::FastEmit_rf_(MVT VT, unsigned Opcode,
802 unsigned Op0, ConstantFP *FPImm,
804 // First check if immediate type is legal. If not, we can't use the rf form.
805 unsigned ResultReg = FastEmit_rf(VT, VT, Opcode, Op0, FPImm);
809 // Materialize the constant in a register.
810 unsigned MaterialReg = FastEmit_f(ImmType, ImmType, ISD::ConstantFP, FPImm);
811 if (MaterialReg == 0) {
812 // If the target doesn't have a way to directly enter a floating-point
813 // value into a register, use an alternate approach.
814 // TODO: The current approach only supports floating-point constants
815 // that can be constructed by conversion from integer values. This should
816 // be replaced by code that creates a load from a constant-pool entry,
817 // which will require some target-specific work.
818 const APFloat &Flt = FPImm->getValueAPF();
819 EVT IntVT = TLI.getPointerTy();
822 uint32_t IntBitWidth = IntVT.getSizeInBits();
824 (void) Flt.convertToInteger(x, IntBitWidth, /*isSigned=*/true,
825 APFloat::rmTowardZero, &isExact);
828 APInt IntVal(IntBitWidth, 2, x);
830 unsigned IntegerReg = FastEmit_i(IntVT.getSimpleVT(), IntVT.getSimpleVT(),
831 ISD::Constant, IntVal.getZExtValue());
834 MaterialReg = FastEmit_r(IntVT.getSimpleVT(), VT,
835 ISD::SINT_TO_FP, IntegerReg);
836 if (MaterialReg == 0)
839 return FastEmit_rr(VT, VT, Opcode, Op0, MaterialReg);
842 unsigned FastISel::createResultReg(const TargetRegisterClass* RC) {
843 return MRI.createVirtualRegister(RC);
846 unsigned FastISel::FastEmitInst_(unsigned MachineInstOpcode,
847 const TargetRegisterClass* RC) {
848 unsigned ResultReg = createResultReg(RC);
849 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
851 BuildMI(MBB, DL, II, ResultReg);
855 unsigned FastISel::FastEmitInst_r(unsigned MachineInstOpcode,
856 const TargetRegisterClass *RC,
858 unsigned ResultReg = createResultReg(RC);
859 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
861 if (II.getNumDefs() >= 1)
862 BuildMI(MBB, DL, II, ResultReg).addReg(Op0);
864 BuildMI(MBB, DL, II).addReg(Op0);
865 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
866 II.ImplicitDefs[0], RC, RC);
874 unsigned FastISel::FastEmitInst_rr(unsigned MachineInstOpcode,
875 const TargetRegisterClass *RC,
876 unsigned Op0, unsigned Op1) {
877 unsigned ResultReg = createResultReg(RC);
878 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
880 if (II.getNumDefs() >= 1)
881 BuildMI(MBB, DL, II, ResultReg).addReg(Op0).addReg(Op1);
883 BuildMI(MBB, DL, II).addReg(Op0).addReg(Op1);
884 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
885 II.ImplicitDefs[0], RC, RC);
892 unsigned FastISel::FastEmitInst_ri(unsigned MachineInstOpcode,
893 const TargetRegisterClass *RC,
894 unsigned Op0, uint64_t Imm) {
895 unsigned ResultReg = createResultReg(RC);
896 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
898 if (II.getNumDefs() >= 1)
899 BuildMI(MBB, DL, II, ResultReg).addReg(Op0).addImm(Imm);
901 BuildMI(MBB, DL, II).addReg(Op0).addImm(Imm);
902 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
903 II.ImplicitDefs[0], RC, RC);
910 unsigned FastISel::FastEmitInst_rf(unsigned MachineInstOpcode,
911 const TargetRegisterClass *RC,
912 unsigned Op0, ConstantFP *FPImm) {
913 unsigned ResultReg = createResultReg(RC);
914 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
916 if (II.getNumDefs() >= 1)
917 BuildMI(MBB, DL, II, ResultReg).addReg(Op0).addFPImm(FPImm);
919 BuildMI(MBB, DL, II).addReg(Op0).addFPImm(FPImm);
920 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
921 II.ImplicitDefs[0], RC, RC);
928 unsigned FastISel::FastEmitInst_rri(unsigned MachineInstOpcode,
929 const TargetRegisterClass *RC,
930 unsigned Op0, unsigned Op1, uint64_t Imm) {
931 unsigned ResultReg = createResultReg(RC);
932 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
934 if (II.getNumDefs() >= 1)
935 BuildMI(MBB, DL, II, ResultReg).addReg(Op0).addReg(Op1).addImm(Imm);
937 BuildMI(MBB, DL, II).addReg(Op0).addReg(Op1).addImm(Imm);
938 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
939 II.ImplicitDefs[0], RC, RC);
946 unsigned FastISel::FastEmitInst_i(unsigned MachineInstOpcode,
947 const TargetRegisterClass *RC,
949 unsigned ResultReg = createResultReg(RC);
950 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
952 if (II.getNumDefs() >= 1)
953 BuildMI(MBB, DL, II, ResultReg).addImm(Imm);
955 BuildMI(MBB, DL, II).addImm(Imm);
956 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
957 II.ImplicitDefs[0], RC, RC);
964 unsigned FastISel::FastEmitInst_extractsubreg(MVT RetVT,
965 unsigned Op0, uint32_t Idx) {
966 const TargetRegisterClass* RC = MRI.getRegClass(Op0);
968 unsigned ResultReg = createResultReg(TLI.getRegClassFor(RetVT));
969 const TargetInstrDesc &II = TII.get(TargetInstrInfo::EXTRACT_SUBREG);
971 if (II.getNumDefs() >= 1)
972 BuildMI(MBB, DL, II, ResultReg).addReg(Op0).addImm(Idx);
974 BuildMI(MBB, DL, II).addReg(Op0).addImm(Idx);
975 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
976 II.ImplicitDefs[0], RC, RC);
983 /// FastEmitZExtFromI1 - Emit MachineInstrs to compute the value of Op
984 /// with all but the least significant bit set to zero.
985 unsigned FastISel::FastEmitZExtFromI1(MVT VT, unsigned Op) {
986 return FastEmit_ri(VT, VT, ISD::AND, Op, 1);